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[thirdparty/gcc.git] / gcc / config / rl78 / rl78.h
1 /* GCC backend definitions for the Renesas RL78 processor.
2 Copyright (C) 2011-2015 Free Software Foundation, Inc.
3 Contributed by Red Hat.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20 \f
21
22 #define RL78_MUL_NONE (rl78_mul_type == MUL_NONE)
23 #define RL78_MUL_RL78 (rl78_mul_type == MUL_RL78)
24 #define RL78_MUL_G13 (rl78_mul_type == MUL_G13)
25
26 #define TARGET_CPU_CPP_BUILTINS() \
27 do \
28 { \
29 builtin_define ("__RL78__"); \
30 builtin_assert ("cpu=RL78"); \
31 if (RL78_MUL_RL78) \
32 builtin_define ("__RL78_MUL_RL78__"); \
33 if (RL78_MUL_G13) \
34 builtin_define ("__RL78_MUL_G13__"); \
35 if (TARGET_G10) \
36 builtin_define ("__RL78_G10__"); \
37 } \
38 while (0)
39
40 #undef STARTFILE_SPEC
41 #define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:crt0.o%s} crtbegin.o%s"
42
43 #undef ENDFILE_SPEC
44 #define ENDFILE_SPEC "crtend.o%s crtn.o%s"
45
46 #undef ASM_SPEC
47 #define ASM_SPEC "\
48 %{mrelax:-relax} \
49 %{mg10} \
50 "
51
52 #undef LINK_SPEC
53 #define LINK_SPEC "\
54 %{mrelax:-relax} \
55 %{!r:--gc-sections} \
56 "
57
58 #undef LIB_SPEC
59 #define LIB_SPEC " \
60 --start-group \
61 -lc \
62 -lsim \
63 %{fprofile-arcs|fprofile-generate|coverage:-lgcov} \
64 --end-group \
65 %{!T*: %{msim:%Trl78-sim.ld}%{!msim:%Trl78.ld}} \
66 "
67 \f
68
69 #define BITS_BIG_ENDIAN 0
70 #define BYTES_BIG_ENDIAN 0
71 #define WORDS_BIG_ENDIAN 0
72
73 #ifdef IN_LIBGCC2
74 /* This is to get correct SI and DI modes in libgcc2.c (32 and 64 bits). */
75 #define UNITS_PER_WORD 4
76 /* We have a problem with libgcc2. It only defines two versions of
77 each function, one for "int" and one for "long long". Ie it assumes
78 that "sizeof (int) == sizeof (long)". For the RL78 this is not true
79 and we need a third set of functions. We explicitly define
80 LIBGCC2_UNITS_PER_WORD here so that it is clear that we are expecting
81 to get the SI and DI versions from the libgcc2.c sources, and we
82 provide our own set of HI functions, which is why this
83 definition is surrounded by #ifndef..#endif. */
84 #ifndef LIBGCC2_UNITS_PER_WORD
85 #define LIBGCC2_UNITS_PER_WORD 4
86 #endif
87 #else
88 /* Actual width of a word, in units (bytes). */
89 #define UNITS_PER_WORD 1
90 #endif
91
92 #define SHORT_TYPE_SIZE 16
93 #define INT_TYPE_SIZE 16
94 #define LONG_TYPE_SIZE 32
95 #define LONG_LONG_TYPE_SIZE 64
96
97 #define FLOAT_TYPE_SIZE 32
98 #define DOUBLE_TYPE_SIZE 32 /*64*/
99 #define LONG_DOUBLE_TYPE_SIZE 64 /*DOUBLE_TYPE_SIZE*/
100
101 #define DEFAULT_SIGNED_CHAR 0
102
103 #define STRICT_ALIGNMENT 1
104 #define FUNCTION_BOUNDARY 8
105 #define BIGGEST_ALIGNMENT 16
106 #define STACK_BOUNDARY 16
107 #define PARM_BOUNDARY 16
108
109 #define STACK_GROWS_DOWNWARD 1
110 #define FRAME_GROWS_DOWNWARD 1
111 #define FIRST_PARM_OFFSET(FNDECL) 0
112
113 #define MAX_REGS_PER_ADDRESS 1
114
115 #define Pmode HImode
116 #define POINTER_SIZE 16
117 #undef SIZE_TYPE
118 #define SIZE_TYPE "unsigned int"
119 #undef PTRDIFF_TYPE
120 #define PTRDIFF_TYPE "int"
121 #undef WCHAR_TYPE
122 #define WCHAR_TYPE "long int"
123 #undef WCHAR_TYPE_SIZE
124 #define WCHAR_TYPE_SIZE BITS_PER_WORD
125 #define POINTERS_EXTEND_UNSIGNED 1
126 #define FUNCTION_MODE HImode
127 #define CASE_VECTOR_MODE Pmode
128 #define WORD_REGISTER_OPERATIONS 0
129 #define HAS_LONG_COND_BRANCH 0
130 #define HAS_LONG_UNCOND_BRANCH 0
131
132 #define MOVE_MAX 2
133 #define STARTING_FRAME_OFFSET 0
134
135 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
136
137 #define ADDR_SPACE_FAR 1
138
139 #define HAVE_PRE_DECCREMENT 0
140 #define HAVE_POST_INCREMENT 0
141
142 #define MOVE_RATIO(SPEED) ((SPEED) ? 24 : 16)
143 #define SLOW_BYTE_ACCESS 0
144
145 #define STORE_FLAG_VALUE 1
146 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
147 \f
148
149 /* The RL78 has four register banks. Normal operation uses RB0 as
150 real registers, RB1 and RB2 as "virtual" registers (because we know
151 they'll be there, and not used as variables), and RB3 is reserved
152 for interrupt handlers. The virtual registers are accessed as
153 SADDRs:
154
155 FFEE0-FFEE7 RB0
156 FFEE8-FFEEF RB1
157 FFEF0-FFEF7 RB2
158 FFEF8-FFEFF RB3
159 */
160 #define REGISTER_NAMES \
161 { \
162 "x", "a", "c", "b", "e", "d", "l", "h", \
163 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
164 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
165 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
166 "sp", "ap", "psw", "es", "cs" \
167 }
168
169 #define ADDITIONAL_REGISTER_NAMES \
170 { \
171 { "ax", 0 }, \
172 { "bc", 2 }, \
173 { "de", 4 }, \
174 { "hl", 6 }, \
175 { "rp0", 0 }, \
176 { "rp1", 2 }, \
177 { "rp2", 4 }, \
178 { "rp3", 6 }, \
179 { "r0", 0 }, \
180 { "r1", 1 }, \
181 { "r2", 2 }, \
182 { "r3", 3 }, \
183 { "r4", 4 }, \
184 { "r5", 5 }, \
185 { "r6", 6 }, \
186 { "r7", 7 }, \
187 }
188
189 enum reg_class
190 {
191 NO_REGS, /* No registers in set. */
192 XREG,
193 AREG,
194 AXREG,
195 CREG,
196 BREG,
197 BCREG,
198 EREG,
199 DREG,
200 DEREG,
201 LREG,
202 HREG,
203 HLREG,
204 IDX_REGS,
205 QI_REGS,
206 SPREG,
207 R8W_REGS,
208 R10W_REGS,
209 INT_REGS,
210 V_REGS, /* Virtual registers. */
211 GR_REGS, /* Integer registers. */
212 PSWREG,
213 ALL_REGS, /* All registers. */
214 LIM_REG_CLASSES /* Max value + 1. */
215 };
216
217 #define REG_CLASS_NAMES \
218 { \
219 "NO_REGS", \
220 "XREG", \
221 "AREG", \
222 "AXREG", \
223 "CREG", \
224 "BREG", \
225 "BCREG", \
226 "EREG", \
227 "DREG", \
228 "DEREG", \
229 "LREG", \
230 "HREG", \
231 "HLREG", \
232 "IDX_REGS", \
233 "QI_REGS", \
234 "SPREG", \
235 "R8W_REGS", \
236 "R10W_REGS", \
237 "INT_REGS", \
238 "V_REGS", \
239 "GR_REGS", \
240 "PSWREG", \
241 "ALL_REGS" \
242 }
243
244 #define REG_CLASS_CONTENTS \
245 { \
246 { 0x00000000, 0x00000000 }, /* No registers, */ \
247 { 0x00000001, 0x00000000 }, \
248 { 0x00000002, 0x00000000 }, \
249 { 0x00000003, 0x00000000 }, \
250 { 0x00000004, 0x00000000 }, \
251 { 0x00000008, 0x00000000 }, \
252 { 0x0000000c, 0x00000000 }, \
253 { 0x00000010, 0x00000000 }, \
254 { 0x00000020, 0x00000000 }, \
255 { 0x00000030, 0x00000000 }, \
256 { 0x00000040, 0x00000000 }, \
257 { 0x00000080, 0x00000000 }, \
258 { 0x000000c0, 0x00000000 }, \
259 { 0x0000000c, 0x00000000 }, /* B and C - index regs. */ \
260 { 0x000000ff, 0x00000000 }, /* all real registers. */ \
261 { 0x00000000, 0x00000001 }, /* SP */ \
262 { 0x00000300, 0x00000000 }, /* R8 - HImode */ \
263 { 0x00000c00, 0x00000000 }, /* R10 - HImode */ \
264 { 0xff000000, 0x00000000 }, /* INT - HImode */ \
265 { 0xff7fff00, 0x00000000 }, /* Virtual registers. */ \
266 { 0xff7fffff, 0x00000002 }, /* General registers. */ \
267 { 0x04000000, 0x00000004 }, /* PSW. */ \
268 { 0xff7fffff, 0x0000001f } /* All registers. */ \
269 }
270
271 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
272 #define N_REG_CLASSES (int) LIM_REG_CLASSES
273 #define CLASS_MAX_NREGS(CLASS, MODE) ((GET_MODE_SIZE (MODE) \
274 + UNITS_PER_WORD - 1) \
275 / UNITS_PER_WORD)
276
277 #define GENERAL_REGS GR_REGS
278 #define BASE_REG_CLASS V_REGS
279 #define INDEX_REG_CLASS V_REGS
280
281 #define FIRST_PSEUDO_REGISTER 37
282
283 #define REGNO_REG_CLASS(REGNO) ((REGNO) < FIRST_PSEUDO_REGISTER \
284 ? GR_REGS : NO_REGS)
285
286 #define FRAME_POINTER_REGNUM 22
287 #define STACK_POINTER_REGNUM 32
288 #define ARG_POINTER_REGNUM 33
289 #define CC_REGNUM 34
290 #define FUNC_RETURN_REGNUM 8
291 #define STATIC_CHAIN_REGNUM 14
292
293 /* Trampolines are implemented with a separate data stack. The memory
294 on stack only holds the function pointer for the chosen stub.
295 */
296
297 #define TRAMPOLINE_SIZE 4
298 #define TRAMPOLINE_ALIGNMENT 16
299
300 #define ELIMINABLE_REGS \
301 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
302 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
303 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
304
305 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
306 (OFFSET) = rl78_initial_elimination_offset ((FROM), (TO))
307
308
309 #define FUNCTION_ARG_REGNO_P(N) 0
310 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8)
311 #define DEFAULT_PCC_STRUCT_RETURN 0
312
313 #define FIXED_REGISTERS \
314 { \
315 1,1,1,1, 1,1,1,1, \
316 0,0,0,0, 0,0,0,0, \
317 0,0,0,0, 0,0,1,1, \
318 1,1,1,1, 1,1,1,1, \
319 0, 1, 0, 1, 1 \
320 }
321
322 #define CALL_USED_REGISTERS \
323 { \
324 1,1,1,1, 1,1,1,1, \
325 1,1,1,1, 1,1,1,1, \
326 0,0,0,0, 0,0,1,1, \
327 1,1,1,1, 1,1,1,1, \
328 0, 1, 1, 1, 1 \
329 }
330
331 #define LIBCALL_VALUE(MODE) \
332 gen_rtx_REG ((MODE), \
333 FUNC_RETURN_REGNUM)
334
335 /* Order of allocation of registers. */
336
337 #define REG_ALLOC_ORDER \
338 { 8, 9, 10, 11, 12, 13, 14, 15, \
339 16, 17, 18, 19, 20, 21, 22, 23, \
340 0, 1, 6, 7, 2, 3, 4, 5, \
341 24, 25, 26, 27, 28, 29, 30, 31, \
342 32, 33, 34 \
343 }
344
345 #define REGNO_IN_RANGE(REGNO, MIN, MAX) \
346 (IN_RANGE ((REGNO), (MIN), (MAX)) \
347 || (reg_renumber != NULL \
348 && reg_renumber[(REGNO)] >= (MIN) \
349 && reg_renumber[(REGNO)] <= (MAX)))
350
351 #ifdef REG_OK_STRICT
352 #define REGNO_OK_FOR_BASE_P(regno) REGNO_IN_RANGE (regno, 16, 31)
353 #else
354 #define REGNO_OK_FOR_BASE_P(regno) 1
355 #endif
356
357 #define REGNO_OK_FOR_INDEX_P(regno) REGNO_OK_FOR_BASE_P (regno)
358
359 #define REGNO_MODE_CODE_OK_FOR_BASE_P(regno, mode, address_space, outer_code, index_code) \
360 rl78_regno_mode_code_ok_for_base_p (regno, mode, address_space, outer_code, index_code)
361
362 #define MODE_CODE_BASE_REG_CLASS(mode, address_space, outer_code, index_code) \
363 rl78_mode_code_base_reg_class (mode, address_space, outer_code, index_code)
364
365 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \
366 ((COUNT) == 0 \
367 ? gen_rtx_MEM (Pmode, gen_rtx_PLUS (HImode, arg_pointer_rtx, GEN_INT (-4))) \
368 : NULL_RTX)
369
370 #define INCOMING_RETURN_ADDR_RTX gen_rtx_MEM (Pmode, stack_pointer_rtx)
371
372 #define ACCUMULATE_OUTGOING_ARGS 1
373
374 typedef unsigned int CUMULATIVE_ARGS;
375
376 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
377 (CUM) = 0
378
379 \f
380 /* FIXME */
381 #define NO_PROFILE_COUNTERS 1
382 #define PROFILE_BEFORE_PROLOGUE 1
383
384 #define FUNCTION_PROFILER(FILE, LABELNO) \
385 fprintf (FILE, "\tbsr\t__mcount\n");
386 \f
387
388 #define HARD_REGNO_NREGS(REGNO, MODE) \
389 rl78_hard_regno_nregs (REGNO, MODE)
390
391 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
392 rl78_hard_regno_mode_ok (REGNO, MODE)
393
394 #define MODES_TIEABLE_P(MODE1, MODE2) \
395 ( ( GET_MODE_CLASS (MODE1) == MODE_FLOAT \
396 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
397 == ( GET_MODE_CLASS (MODE2) == MODE_FLOAT \
398 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
399 \f
400
401 #define TEXT_SECTION_ASM_OP ".text"
402 #define DATA_SECTION_ASM_OP ".data"
403 #define BSS_SECTION_ASM_OP ".bss"
404 #define CTORS_SECTION_ASM_OP ".section \".ctors\",\"a\""
405 #define DTORS_SECTION_ASM_OP ".section \".dtors\",\"a\""
406
407 #define ASM_COMMENT_START " ;"
408 #define ASM_APP_ON ""
409 #define ASM_APP_OFF ""
410 #define LOCAL_LABEL_PREFIX ".L"
411 #undef USER_LABEL_PREFIX
412 #define USER_LABEL_PREFIX "_"
413
414 #define GLOBAL_ASM_OP "\t.global\t"
415
416 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
417 fprintf (FILE, "\t.long .L%d\n", VALUE)
418
419 /* This is how to output an element of a case-vector that is relative.
420 Note: The local label referenced by the "3b" below is emitted by
421 the tablejump insn. */
422
423 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
424 fprintf (FILE, "\t.long .L%d - 1b\n", VALUE)
425
426
427 #define ASM_OUTPUT_ALIGN(STREAM, LOG) \
428 do \
429 { \
430 if ((LOG) == 0) \
431 break; \
432 fprintf (STREAM, "\t.balign %d\n", 1 << (LOG)); \
433 } \
434 while (0)
435
436 /* For PIC put jump tables into the text section so that the offsets that
437 they contain are always computed between two same-section symbols. */
438 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
439 \f
440 /* This is a version of REG_P that also returns TRUE for SUBREGs. */
441 #define RL78_REG_P(rtl) (REG_P (rtl) || GET_CODE (rtl) == SUBREG)
442
443 /* Like REG_P except that this macro is true for SET expressions. */
444 #define SET_P(rtl) (GET_CODE (rtl) == SET)
445 \f
446 #undef PREFERRED_DEBUGGING_TYPE
447 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
448
449 #undef DWARF2_ADDR_SIZE
450 #define DWARF2_ADDR_SIZE 4
451
452 #define DWARF2_ASM_LINE_DEBUG_INFO 1
453
454 #define EXIT_IGNORE_STACK 0
455 #define INCOMING_FRAME_SP_OFFSET 4
456 \f
457
458 #define BRANCH_COST(SPEED,PREDICT) 1
459 #define REGISTER_MOVE_COST(MODE,FROM,TO) 2
460
461 #define EH_RETURN_DATA_REGNO(N) (N < 2 ? (8+(N)*2) : INVALID_REGNUM)
462 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (HImode, 20)
463
464 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) DW_EH_PE_udata4
465
466 /* NOTE: defined but zero means dwarf2 debugging, but sjlj EH. */
467 #define DWARF2_UNWIND_INFO 0
468
469 #define REGISTER_TARGET_PRAGMAS() rl78_register_pragmas()
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