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Turn TRULY_NOOP_TRUNCATION into a hook
[thirdparty/gcc.git] / gcc / config / rl78 / rl78.h
1 /* GCC backend definitions for the Renesas RL78 processor.
2 Copyright (C) 2011-2017 Free Software Foundation, Inc.
3 Contributed by Red Hat.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20 \f
21
22 #define RL78_MUL_NONE (rl78_mul_type == MUL_NONE)
23 #define RL78_MUL_G13 (rl78_mul_type == MUL_G13)
24 #define RL78_MUL_G14 (rl78_mul_type == MUL_G14)
25
26 #define TARGET_G10 (rl78_cpu_type == CPU_G10)
27 #define TARGET_G13 (rl78_cpu_type == CPU_G13)
28 #define TARGET_G14 (rl78_cpu_type == CPU_G14)
29
30 #define TARGET_CPU_CPP_BUILTINS() \
31 do \
32 { \
33 builtin_define ("__RL78__"); \
34 builtin_assert ("cpu=RL78"); \
35 \
36 if (RL78_MUL_NONE) \
37 builtin_define ("__RL78_MUL_NONE__"); \
38 else if (RL78_MUL_G13) \
39 builtin_define ("__RL78_MUL_G13__"); \
40 else if (RL78_MUL_G14) \
41 builtin_define ("__RL78_MUL_G14__"); \
42 \
43 if (TARGET_G10) \
44 builtin_define ("__RL78_G10__"); \
45 else if (TARGET_G13) \
46 builtin_define ("__RL78_G13__"); \
47 else if (TARGET_G14) \
48 builtin_define ("__RL78_G14__"); \
49 } \
50 while (0)
51
52 #undef STARTFILE_SPEC
53 #define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:crt0.o%s} crtbegin.o%s"
54
55 #undef ENDFILE_SPEC
56 #define ENDFILE_SPEC "crtend.o%s crtn.o%s"
57
58 #undef ASM_SPEC
59 #define ASM_SPEC "\
60 %{mrelax:-relax} \
61 %{mg10:--mg10} \
62 %{mg13:--mg13} \
63 %{mg14:--mg14} \
64 %{mrl78:--mg14} \
65 %{mcpu=g10:--mg10} \
66 %{mcpu=g13:--mg13} \
67 %{mcpu=g14:--mg14} \
68 %{mcpu=rl78:--mg14} \
69 "
70
71 #undef LINK_SPEC
72 #define LINK_SPEC "\
73 %{mrelax:-relax} \
74 %{!r:--gc-sections} \
75 "
76
77 #undef LIB_SPEC
78 #define LIB_SPEC " \
79 --start-group \
80 -lc \
81 -lsim \
82 %{fprofile-arcs|fprofile-generate|coverage:-lgcov} \
83 --end-group \
84 %{!T*: %{msim:%Trl78-sim.ld}%{!msim:%Trl78.ld}} \
85 "
86 \f
87
88 #define BITS_BIG_ENDIAN 0
89 #define BYTES_BIG_ENDIAN 0
90 #define WORDS_BIG_ENDIAN 0
91
92 #ifdef IN_LIBGCC2
93 /* This is to get correct SI and DI modes in libgcc2.c (32 and 64 bits). */
94 #define UNITS_PER_WORD 4
95 /* We have a problem with libgcc2. It only defines two versions of
96 each function, one for "int" and one for "long long". Ie it assumes
97 that "sizeof (int) == sizeof (long)". For the RL78 this is not true
98 and we need a third set of functions. We explicitly define
99 LIBGCC2_UNITS_PER_WORD here so that it is clear that we are expecting
100 to get the SI and DI versions from the libgcc2.c sources, and we
101 provide our own set of HI functions, which is why this
102 definition is surrounded by #ifndef..#endif. */
103 #ifndef LIBGCC2_UNITS_PER_WORD
104 #define LIBGCC2_UNITS_PER_WORD 4
105 #endif
106 #else
107 /* Actual width of a word, in units (bytes). */
108 #define UNITS_PER_WORD 1
109 #endif
110
111 #define SHORT_TYPE_SIZE 16
112 #define INT_TYPE_SIZE 16
113 #define LONG_TYPE_SIZE 32
114 #define LONG_LONG_TYPE_SIZE 64
115
116 #define FLOAT_TYPE_SIZE 32
117 #define DOUBLE_TYPE_SIZE 32 /*64*/
118 #define LONG_DOUBLE_TYPE_SIZE 64 /*DOUBLE_TYPE_SIZE*/
119
120 #define DEFAULT_SIGNED_CHAR 0
121
122 #define STRICT_ALIGNMENT 1
123 #define FUNCTION_BOUNDARY 8
124 #define BIGGEST_ALIGNMENT 16
125 #define STACK_BOUNDARY 16
126 #define PARM_BOUNDARY 16
127
128 #define STACK_GROWS_DOWNWARD 1
129 #define FRAME_GROWS_DOWNWARD 1
130 #define FIRST_PARM_OFFSET(FNDECL) 0
131
132 #define MAX_REGS_PER_ADDRESS 1
133
134 #define Pmode HImode
135 #define POINTER_SIZE 16
136 #undef SIZE_TYPE
137 #define SIZE_TYPE "unsigned int"
138 #undef PTRDIFF_TYPE
139 #define PTRDIFF_TYPE "int"
140 #undef WCHAR_TYPE
141 #define WCHAR_TYPE "long int"
142 #undef WCHAR_TYPE_SIZE
143 #define WCHAR_TYPE_SIZE BITS_PER_WORD
144 #define POINTERS_EXTEND_UNSIGNED 1
145 #define FUNCTION_MODE HImode
146 #define CASE_VECTOR_MODE Pmode
147 #define WORD_REGISTER_OPERATIONS 1
148 #define HAS_LONG_COND_BRANCH 0
149 #define HAS_LONG_UNCOND_BRANCH 0
150
151 #define MOVE_MAX 2
152 #define STARTING_FRAME_OFFSET 0
153
154 #define ADDR_SPACE_NEAR 1
155 #define ADDR_SPACE_FAR 2
156
157 #define HAVE_PRE_DECCREMENT 0
158 #define HAVE_POST_INCREMENT 0
159
160 #define MOVE_RATIO(SPEED) ((SPEED) ? 24 : 16)
161 #define SLOW_BYTE_ACCESS 0
162
163 #define STORE_FLAG_VALUE 1
164 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
165 \f
166
167 /* The RL78 has four register banks. Normal operation uses RB0 as
168 real registers, RB1 and RB2 as "virtual" registers (because we know
169 they'll be there, and not used as variables), and RB3 is reserved
170 for interrupt handlers. The virtual registers are accessed as
171 SADDRs:
172
173 FFEE0-FFEE7 RB0
174 FFEE8-FFEEF RB1
175 FFEF0-FFEF7 RB2
176 FFEF8-FFEFF RB3
177 */
178 #define REGISTER_NAMES \
179 { \
180 "x", "a", "c", "b", "e", "d", "l", "h", \
181 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
182 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
183 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
184 "sp", "ap", "psw", "es", "cs" \
185 }
186
187 #define ADDITIONAL_REGISTER_NAMES \
188 { \
189 { "ax", 0 }, \
190 { "bc", 2 }, \
191 { "de", 4 }, \
192 { "hl", 6 }, \
193 { "rp0", 0 }, \
194 { "rp1", 2 }, \
195 { "rp2", 4 }, \
196 { "rp3", 6 }, \
197 { "r0", 0 }, \
198 { "r1", 1 }, \
199 { "r2", 2 }, \
200 { "r3", 3 }, \
201 { "r4", 4 }, \
202 { "r5", 5 }, \
203 { "r6", 6 }, \
204 { "r7", 7 }, \
205 }
206
207 enum reg_class
208 {
209 NO_REGS, /* No registers in set. */
210 XREG,
211 AREG,
212 AXREG,
213 CREG,
214 BREG,
215 BCREG,
216 EREG,
217 DREG,
218 DEREG,
219 LREG,
220 HREG,
221 HLREG,
222 IDX_REGS,
223 QI_REGS,
224 SPREG,
225 R8W_REGS,
226 R10W_REGS,
227 INT_REGS,
228 V_REGS, /* Virtual registers. */
229 GR_REGS, /* Integer registers. */
230 PSWREG,
231 ALL_REGS, /* All registers. */
232 LIM_REG_CLASSES /* Max value + 1. */
233 };
234
235 #define REG_CLASS_NAMES \
236 { \
237 "NO_REGS", \
238 "XREG", \
239 "AREG", \
240 "AXREG", \
241 "CREG", \
242 "BREG", \
243 "BCREG", \
244 "EREG", \
245 "DREG", \
246 "DEREG", \
247 "LREG", \
248 "HREG", \
249 "HLREG", \
250 "IDX_REGS", \
251 "QI_REGS", \
252 "SPREG", \
253 "R8W_REGS", \
254 "R10W_REGS", \
255 "INT_REGS", \
256 "V_REGS", \
257 "GR_REGS", \
258 "PSWREG", \
259 "ALL_REGS" \
260 }
261
262 /* Note that no class may include the second register in $fp, because
263 we treat $fp as a single HImode register. */
264 #define REG_CLASS_CONTENTS \
265 { \
266 { 0x00000000, 0x00000000 }, /* No registers, */ \
267 { 0x00000001, 0x00000000 }, \
268 { 0x00000002, 0x00000000 }, \
269 { 0x00000003, 0x00000000 }, \
270 { 0x00000004, 0x00000000 }, \
271 { 0x00000008, 0x00000000 }, \
272 { 0x0000000c, 0x00000000 }, \
273 { 0x00000010, 0x00000000 }, \
274 { 0x00000020, 0x00000000 }, \
275 { 0x00000030, 0x00000000 }, \
276 { 0x00000040, 0x00000000 }, \
277 { 0x00000080, 0x00000000 }, \
278 { 0x000000c0, 0x00000000 }, \
279 { 0x0000000c, 0x00000000 }, /* B and C - index regs. */ \
280 { 0x000000ff, 0x00000000 }, /* all real registers. */ \
281 { 0x00000000, 0x00000001 }, /* SP */ \
282 { 0x00000300, 0x00000000 }, /* R8 - HImode */ \
283 { 0x00000c00, 0x00000000 }, /* R10 - HImode */ \
284 { 0xff000000, 0x00000000 }, /* INT - HImode */ \
285 { 0xff7fff00, 0x00000000 }, /* Virtual registers. */ \
286 { 0xff7fff00, 0x00000002 }, /* General registers. */ \
287 { 0x04000000, 0x00000004 }, /* PSW. */ \
288 { 0xff7fffff, 0x0000001f } /* All registers. */ \
289 }
290
291 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
292 #define N_REG_CLASSES (int) LIM_REG_CLASSES
293 #define CLASS_MAX_NREGS(CLASS, MODE) ((GET_MODE_SIZE (MODE) \
294 + UNITS_PER_WORD - 1) \
295 / UNITS_PER_WORD)
296
297 #define GENERAL_REGS GR_REGS
298 #define BASE_REG_CLASS V_REGS
299 #define INDEX_REG_CLASS V_REGS
300
301 #define FIRST_PSEUDO_REGISTER 37
302
303 #define REGNO_REG_CLASS(REGNO) ((REGNO) < FIRST_PSEUDO_REGISTER \
304 ? GR_REGS : NO_REGS)
305
306 #define FRAME_POINTER_REGNUM 22
307 #define STACK_POINTER_REGNUM 32
308 #define ARG_POINTER_REGNUM 33
309 #define CC_REGNUM 34
310 #define FUNC_RETURN_REGNUM 8
311 #define STATIC_CHAIN_REGNUM 14
312
313 /* Trampolines are implemented with a separate data stack. The memory
314 on stack only holds the function pointer for the chosen stub.
315 */
316
317 #define TRAMPOLINE_SIZE 4
318 #define TRAMPOLINE_ALIGNMENT 16
319
320 #define ELIMINABLE_REGS \
321 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
322 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
323 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
324
325 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
326 (OFFSET) = rl78_initial_elimination_offset ((FROM), (TO))
327
328
329 #define FUNCTION_ARG_REGNO_P(N) 0
330 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8)
331 #define DEFAULT_PCC_STRUCT_RETURN 0
332
333 #define FIXED_REGISTERS \
334 { \
335 1,1,1,1, 1,1,1,1, \
336 0,0,0,0, 0,0,0,0, \
337 0,0,0,0, 0,0,1,1, \
338 1,1,1,1, 1,1,1,1, \
339 0, 1, 0, 1, 1 \
340 }
341
342 #define CALL_USED_REGISTERS \
343 { \
344 1,1,1,1, 1,1,1,1, \
345 1,1,1,1, 1,1,1,1, \
346 0,0,0,0, 0,0,1,1, \
347 1,1,1,1, 1,1,1,1, \
348 0, 1, 1, 1, 1 \
349 }
350
351 #define LIBCALL_VALUE(MODE) \
352 gen_rtx_REG ((MODE), \
353 FUNC_RETURN_REGNUM)
354
355 /* Order of allocation of registers. */
356
357 #define REG_ALLOC_ORDER \
358 { 8, 9, 10, 11, 12, 13, 14, 15, \
359 16, 17, 18, 19, 20, 21, 22, 23, \
360 0, 1, 6, 7, 2, 3, 4, 5, \
361 24, 25, 26, 27, 28, 29, 30, 31, \
362 32, 33, 34 \
363 }
364
365 #define REGNO_IN_RANGE(REGNO, MIN, MAX) \
366 (IN_RANGE ((REGNO), (MIN), (MAX)) \
367 || (reg_renumber != NULL \
368 && reg_renumber[(REGNO)] >= (MIN) \
369 && reg_renumber[(REGNO)] <= (MAX)))
370
371 #ifdef REG_OK_STRICT
372 #define REGNO_OK_FOR_BASE_P(regno) REGNO_IN_RANGE (regno, 16, 31)
373 #else
374 #define REGNO_OK_FOR_BASE_P(regno) 1
375 #endif
376
377 #define REGNO_OK_FOR_INDEX_P(regno) REGNO_OK_FOR_BASE_P (regno)
378
379 #define REGNO_MODE_CODE_OK_FOR_BASE_P(regno, mode, address_space, outer_code, index_code) \
380 rl78_regno_mode_code_ok_for_base_p (regno, mode, address_space, outer_code, index_code)
381
382 #define MODE_CODE_BASE_REG_CLASS(mode, address_space, outer_code, index_code) \
383 rl78_mode_code_base_reg_class (mode, address_space, outer_code, index_code)
384
385 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \
386 ((COUNT) == 0 \
387 ? gen_rtx_MEM (Pmode, gen_rtx_PLUS (HImode, arg_pointer_rtx, GEN_INT (-4))) \
388 : NULL_RTX)
389
390 #define INCOMING_RETURN_ADDR_RTX gen_rtx_MEM (Pmode, stack_pointer_rtx)
391
392 #define ACCUMULATE_OUTGOING_ARGS 1
393
394 typedef unsigned int CUMULATIVE_ARGS;
395
396 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
397 (CUM) = 0
398
399 \f
400 /* FIXME */
401 #define NO_PROFILE_COUNTERS 1
402 #define PROFILE_BEFORE_PROLOGUE 1
403
404 #define FUNCTION_PROFILER(FILE, LABELNO) \
405 fprintf (FILE, "\tbsr\t__mcount\n");
406 \f
407
408 #define TEXT_SECTION_ASM_OP ".text"
409 #define DATA_SECTION_ASM_OP ".data"
410 #define BSS_SECTION_ASM_OP ".bss"
411 #define CTORS_SECTION_ASM_OP ".section \".ctors\",\"a\""
412 #define DTORS_SECTION_ASM_OP ".section \".dtors\",\"a\""
413
414 #define ASM_COMMENT_START " ;"
415 #define ASM_APP_ON ""
416 #define ASM_APP_OFF ""
417 #define LOCAL_LABEL_PREFIX ".L"
418 #undef USER_LABEL_PREFIX
419 #define USER_LABEL_PREFIX "_"
420
421 #define GLOBAL_ASM_OP "\t.global\t"
422
423 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
424 fprintf (FILE, "\t.long .L%d\n", VALUE)
425
426 /* This is how to output an element of a case-vector that is relative.
427 Note: The local label referenced by the "3b" below is emitted by
428 the tablejump insn. */
429
430 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
431 fprintf (FILE, "\t.long .L%d - 1b\n", VALUE)
432
433
434 #define ASM_OUTPUT_SYMBOL_REF(FILE, SYM) rl78_output_symbol_ref ((FILE), (SYM))
435
436 #define ASM_OUTPUT_LABELREF(FILE, SYM) rl78_output_labelref ((FILE), (SYM))
437
438 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
439 rl78_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 1)
440
441 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
442 rl78_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0)
443
444 #define ASM_OUTPUT_ALIGN(STREAM, LOG) \
445 do \
446 { \
447 if ((LOG) == 0) \
448 break; \
449 fprintf (STREAM, "\t.balign %d\n", 1 << (LOG)); \
450 } \
451 while (0)
452
453 /* For PIC put jump tables into the text section so that the offsets that
454 they contain are always computed between two same-section symbols. */
455 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
456 \f
457 /* This is a version of REG_P that also returns TRUE for SUBREGs. */
458 #define RL78_REG_P(rtl) (REG_P (rtl) || GET_CODE (rtl) == SUBREG)
459
460 /* Like REG_P except that this macro is true for SET expressions. */
461 #define SET_P(rtl) (GET_CODE (rtl) == SET)
462 \f
463 #undef PREFERRED_DEBUGGING_TYPE
464 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
465
466 #undef DWARF2_ADDR_SIZE
467 #define DWARF2_ADDR_SIZE 4
468
469 #define DWARF2_ASM_LINE_DEBUG_INFO 1
470
471 #define EXIT_IGNORE_STACK 0
472 #define INCOMING_FRAME_SP_OFFSET 4
473 \f
474
475 #define BRANCH_COST(SPEED,PREDICT) 1
476 #define REGISTER_MOVE_COST(MODE,FROM,TO) 2
477
478 #define EH_RETURN_DATA_REGNO(N) (N < 2 ? (8+(N)*2) : INVALID_REGNUM)
479 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (HImode, 20)
480
481 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) DW_EH_PE_udata4
482
483 /* NOTE: defined but zero means dwarf2 debugging, but sjlj EH. */
484 #define DWARF2_UNWIND_INFO 0
485
486 #define REGISTER_TARGET_PRAGMAS() rl78_register_pragmas()
Mirror of https://gcc.gnu.org/git/gcc.git