gcc/config/rs6000/40x.md

   1 ;; Scheduling description for IBM PowerPC 403 and PowerPC 405  processors.
   2 ;;   Copyright (C) 2003 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5
   6 ;; GCC is free software; you can redistribute it and/or modify it
   7 ;; under the terms of the GNU General Public License as published
   8 ;; by the Free Software Foundation; either version 2, or (at your
   9 ;; option) any later version.
  10
  11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14 ;; License for more details.
  15
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING.  If not, write to the
  18 ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
  19 ;; MA 02111-1307, USA.
  20
  21 (define_automaton "ppc40x")
  22 (define_cpu_unit "iu_40x,bpu_40x" "ppc40x")
  23
  24 ;; PPC401 / PPC403 / PPC405 32-bit integer only  IU BPU
  25 ;; Embedded PowerPC controller
  26 ;; In-order execution
  27 ;; Max issue two insns/cycle (includes one branch)
  28 (define_insn_reservation "ppc403-load" 2
  29   (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
  30        (eq_attr "cpu" "ppc403,ppc405"))
  31   "iu_40x")
  32
  33 (define_insn_reservation "ppc403-store" 1
  34   (and (eq_attr "type" "store,store_ux,store_u")
  35        (eq_attr "cpu" "ppc403,ppc405"))
  36   "iu_40x")
  37
  38 (define_insn_reservation "ppc403-integer" 1
  39   (and (eq_attr "type" "integer")
  40        (eq_attr "cpu" "ppc403,ppc405"))
  41   "iu_40x")
  42
  43 (define_insn_reservation "ppc403-compare" 3
  44   (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare")
  45        (eq_attr "cpu" "ppc403,ppc405"))
  46   "iu_40x,nothing,bpu_40x")
  47
  48 (define_insn_reservation "ppc403-imul" 4
  49   (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
  50        (eq_attr "cpu" "ppc403"))
  51   "iu_40x*4")
  52
  53 (define_insn_reservation "ppc405-imul" 5
  54   (and (eq_attr "type" "imul,imul_compare")
  55        (eq_attr "cpu" "ppc405"))
  56   "iu_40x*4")
  57
  58 (define_insn_reservation "ppc405-imul2" 3
  59   (and (eq_attr "type" "imul2")
  60        (eq_attr "cpu" "ppc405"))
  61   "iu_40x*2")
  62
  63 (define_insn_reservation "ppc405-imul3" 2
  64   (and (eq_attr "type" "imul3")
  65        (eq_attr "cpu" "ppc405"))
  66   "iu_40x")
  67
  68 (define_insn_reservation "ppc403-idiv" 33
  69   (and (eq_attr "type" "idiv")
  70        (eq_attr "cpu" "ppc403,ppc405"))
  71   "iu_40x*33")
  72
  73 (define_insn_reservation "ppc403-mfcr" 2
  74   (and (eq_attr "type" "mfcr,mtcr")
  75        (eq_attr "cpu" "ppc403,ppc405"))
  76   "iu_40x")
  77
  78 (define_insn_reservation "ppc403-mtjmpr" 4
  79   (and (eq_attr "type" "mtjmpr")
  80        (eq_attr "cpu" "ppc403,ppc405"))
  81   "bpu_40x")
  82
  83 (define_insn_reservation "ppc403-jmpreg" 1
  84   (and (eq_attr "type" "jmpreg,branch,cr_logical,delayed_cr")
  85        (eq_attr "cpu" "ppc403,ppc405"))
  86   "bpu_40x")
  87