gcc/config/rs6000/6xx.md

   1 ;; Scheduling description for PowerPC 604, PowerPC 604e, PowerPC 620,
   2 ;; and PowerPC 630 processors.
   3 ;;   Copyright (C) 2003-2014 Free Software Foundation, Inc.
   4 ;;
   5 ;; This file is part of GCC.
   6
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published
   9 ;; by the Free Software Foundation; either version 3, or (at your
  10 ;; option) any later version.
  11
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 (define_automaton "ppc6xx,ppc6xxfp,ppc6xxfp2")
  22 (define_cpu_unit "iu1_6xx,iu2_6xx,mciu_6xx" "ppc6xx")
  23 (define_cpu_unit "fpu_6xx" "ppc6xxfp")
  24 (define_cpu_unit "fpu1_6xx,fpu2_6xx" "ppc6xxfp2")
  25 (define_cpu_unit "lsu_6xx,bpu_6xx,cru_6xx" "ppc6xx")
  26
  27 ;; PPC604  32-bit 2xSCIU, MCIU, LSU, FPU, BPU
  28 ;; PPC604e  32-bit 2xSCIU, MCIU, LSU, FPU, BPU, CRU
  29 ;; MCIU used for imul/idiv and moves from/to spr
  30 ;; LSU 2 stage pipelined
  31 ;; FPU 3 stage pipelined
  32 ;; Max issue 4 insns/clock cycle
  33
  34 ;; PPC604e is PPC604 with larger caches and a CRU.  In the 604
  35 ;; the CR logical operations are handled in the BPU.
  36 ;; In the 604e, the CRU shares bus with BPU so only one condition
  37 ;; register or branch insn can be issued per clock.  Not modelled.
  38
  39 ;; PPC620  64-bit 2xSCIU, MCIU, LSU, FPU, BPU, CRU
  40 ;; PPC630 64-bit 2xSCIU, MCIU, LSU, 2xFPU, BPU, CRU
  41 ;; Max issue 4 insns/clock cycle
  42 ;; Out-of-order execution, in-order completion
  43
  44 ;; No following instruction can dispatch in the same cycle as a branch
  45 ;; instruction.  Not modelled.  This is no problem if RCSP is not
  46 ;; enabled since the scheduler stops a schedule when it gets to a branch.
  47
  48 ;; Four insns can be dispatched per cycle.
  49
  50 (define_insn_reservation "ppc604-load" 2
  51   (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
  52        (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
  53   "lsu_6xx")
  54
  55 (define_insn_reservation "ppc604-fpload" 3
  56   (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
  57        (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
  58   "lsu_6xx")
  59
  60 (define_insn_reservation "ppc604-store" 3
  61   (and (eq_attr "type" "store,fpstore,store_ux,store_u,fpstore_ux,fpstore_u")
  62        (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
  63   "lsu_6xx")
  64
  65 (define_insn_reservation "ppc604-llsc" 3
  66   (and (eq_attr "type" "load_l,store_c")
  67        (eq_attr "cpu" "ppc604,ppc604e"))
  68   "lsu_6xx")
  69
  70 (define_insn_reservation "ppc630-llsc" 4
  71   (and (eq_attr "type" "load_l,store_c")
  72        (eq_attr "cpu" "ppc620,ppc630"))
  73   "lsu_6xx")
  74
  75 (define_insn_reservation "ppc604-integer" 1
  76   (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
  77                         var_shift_rotate,cntlz,exts,isel")
  78        (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
  79   "iu1_6xx|iu2_6xx")
  80
  81 (define_insn_reservation "ppc604-two" 1
  82   (and (eq_attr "type" "two")
  83        (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
  84   "iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx")
  85
  86 (define_insn_reservation "ppc604-three" 1
  87   (and (eq_attr "type" "three")
  88        (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
  89   "iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx")
  90
  91 (define_insn_reservation "ppc604-imul" 4
  92   (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
  93        (eq_attr "cpu" "ppc604"))
  94   "mciu_6xx*2")
  95
  96 (define_insn_reservation "ppc604e-imul" 2
  97   (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
  98        (eq_attr "cpu" "ppc604e"))
  99   "mciu_6xx")
 100
 101 (define_insn_reservation "ppc620-imul" 5
 102   (and (eq_attr "type" "imul,imul_compare")
 103        (eq_attr "cpu" "ppc620,ppc630"))
 104   "mciu_6xx*3")
 105
 106 (define_insn_reservation "ppc620-imul2" 4
 107   (and (eq_attr "type" "imul2")
 108        (eq_attr "cpu" "ppc620,ppc630"))
 109   "mciu_6xx*3")
 110
 111 (define_insn_reservation "ppc620-imul3" 3
 112   (and (eq_attr "type" "imul3")
 113        (eq_attr "cpu" "ppc620,ppc630"))
 114   "mciu_6xx*3")
 115
 116 (define_insn_reservation "ppc620-lmul" 7
 117   (and (eq_attr "type" "lmul,lmul_compare")
 118        (eq_attr "cpu" "ppc620,ppc630"))
 119   "mciu_6xx*5")
 120
 121 (define_insn_reservation "ppc604-idiv" 20
 122   (and (eq_attr "type" "idiv")
 123        (eq_attr "cpu" "ppc604,ppc604e"))
 124   "mciu_6xx*19")
 125
 126 (define_insn_reservation "ppc620-idiv" 37
 127   (and (eq_attr "type" "idiv")
 128        (eq_attr "cpu" "ppc620"))
 129   "mciu_6xx*36")
 130
 131 (define_insn_reservation "ppc630-idiv" 21
 132   (and (eq_attr "type" "idiv")
 133        (eq_attr "cpu" "ppc630"))
 134   "mciu_6xx*20")
 135
 136 (define_insn_reservation "ppc620-ldiv" 37
 137   (and (eq_attr "type" "ldiv")
 138        (eq_attr "cpu" "ppc620,ppc630"))
 139   "mciu_6xx*36")
 140
 141 (define_insn_reservation "ppc604-compare" 3
 142   (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
 143                         var_delayed_compare")
 144        (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
 145   "(iu1_6xx|iu2_6xx)")
 146
 147 ; FPU PPC604{,e},PPC620
 148 (define_insn_reservation "ppc604-fpcompare" 5
 149   (and (eq_attr "type" "fpcompare")
 150        (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
 151   "fpu_6xx")
 152
 153 (define_insn_reservation "ppc604-fp" 3
 154   (and (eq_attr "type" "fp")
 155        (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
 156   "fpu_6xx")
 157
 158 (define_insn_reservation "ppc604-dmul" 3
 159   (and (eq_attr "type" "dmul")
 160        (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
 161   "fpu_6xx")
 162
 163 ; Divides are not pipelined
 164 (define_insn_reservation "ppc604-sdiv" 18
 165   (and (eq_attr "type" "sdiv")
 166        (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
 167   "fpu_6xx*18")
 168
 169 (define_insn_reservation "ppc604-ddiv" 32
 170   (and (eq_attr "type" "ddiv")
 171        (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
 172   "fpu_6xx*32")
 173
 174 (define_insn_reservation "ppc620-ssqrt" 31
 175   (and (eq_attr "type" "ssqrt")
 176        (eq_attr "cpu" "ppc620"))
 177   "fpu_6xx*31")
 178
 179 (define_insn_reservation "ppc620-dsqrt" 31
 180   (and (eq_attr "type" "dsqrt")
 181        (eq_attr "cpu" "ppc620"))
 182   "fpu_6xx*31")
 183
 184
 185 ; 2xFPU PPC630
 186 (define_insn_reservation "ppc630-fpcompare" 5
 187   (and (eq_attr "type" "fpcompare")
 188        (eq_attr "cpu" "ppc630"))
 189   "fpu1_6xx|fpu2_6xx")
 190
 191 (define_insn_reservation "ppc630-fp" 3
 192   (and (eq_attr "type" "fp,dmul")
 193        (eq_attr "cpu" "ppc630"))
 194   "fpu1_6xx|fpu2_6xx")
 195
 196 (define_insn_reservation "ppc630-sdiv" 17
 197   (and (eq_attr "type" "sdiv")
 198        (eq_attr "cpu" "ppc630"))
 199   "fpu1_6xx*17|fpu2_6xx*17")
 200
 201 (define_insn_reservation "ppc630-ddiv" 21
 202   (and (eq_attr "type" "ddiv")
 203        (eq_attr "cpu" "ppc630"))
 204   "fpu1_6xx*21|fpu2_6xx*21")
 205
 206 (define_insn_reservation "ppc630-ssqrt" 18
 207   (and (eq_attr "type" "ssqrt")
 208        (eq_attr "cpu" "ppc630"))
 209   "fpu1_6xx*18|fpu2_6xx*18")
 210
 211 (define_insn_reservation "ppc630-dsqrt" 25
 212   (and (eq_attr "type" "dsqrt")
 213        (eq_attr "cpu" "ppc630"))
 214   "fpu1_6xx*25|fpu2_6xx*25")
 215
 216 (define_insn_reservation "ppc604-mfcr" 3
 217   (and (eq_attr "type" "mfcr")
 218        (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
 219   "mciu_6xx")
 220
 221 (define_insn_reservation "ppc604-mtcr" 2
 222   (and (eq_attr "type" "mtcr")
 223        (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
 224   "iu1_6xx|iu2_6xx")
 225
 226 (define_insn_reservation "ppc604-crlogical" 2
 227   (and (eq_attr "type" "cr_logical,delayed_cr")
 228        (eq_attr "cpu" "ppc604"))
 229   "bpu_6xx")
 230
 231 (define_insn_reservation "ppc604e-crlogical" 2
 232   (and (eq_attr "type" "cr_logical,delayed_cr")
 233        (eq_attr "cpu" "ppc604e,ppc620,ppc630"))
 234   "cru_6xx")
 235
 236 (define_insn_reservation "ppc604-mtjmpr" 2
 237   (and (eq_attr "type" "mtjmpr")
 238        (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
 239   "mciu_6xx")
 240
 241 (define_insn_reservation "ppc604-mfjmpr" 3
 242   (and (eq_attr "type" "mfjmpr")
 243        (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
 244   "mciu_6xx")
 245
 246 (define_insn_reservation "ppc630-mfjmpr" 2
 247   (and (eq_attr "type" "mfjmpr")
 248        (eq_attr "cpu" "ppc630"))
 249   "mciu_6xx")
 250
 251 (define_insn_reservation "ppc604-jmpreg" 1
 252   (and (eq_attr "type" "jmpreg,branch")
 253        (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
 254   "bpu_6xx")
 255
 256 (define_insn_reservation "ppc604-isync" 0
 257   (and (eq_attr "type" "isync")
 258        (eq_attr "cpu" "ppc604,ppc604e"))
 259   "bpu_6xx")
 260
 261 (define_insn_reservation "ppc630-isync" 6
 262   (and (eq_attr "type" "isync")
 263        (eq_attr "cpu" "ppc620,ppc630"))
 264   "bpu_6xx")
 265
 266 (define_insn_reservation "ppc604-sync" 35
 267   (and (eq_attr "type" "sync")
 268        (eq_attr "cpu" "ppc604,ppc604e"))
 269   "lsu_6xx")
 270
 271 (define_insn_reservation "ppc630-sync" 26
 272   (and (eq_attr "type" "sync")
 273        (eq_attr "cpu" "ppc620,ppc630"))
 274   "lsu_6xx")
 275