1 ;; Scheduling description for PowerPC 604, PowerPC 604e, PowerPC 620,
2 ;; and PowerPC 630 processors.
3 ;; Copyright (C) 2003 Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 2, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to the
19 ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
20 ;; MA 02111-1307, USA.
22 (define_automaton "ppc6xx,ppc6xxfp,ppc6xxfp2")
23 (define_cpu_unit "iu1_6xx,iu2_6xx,mciu_6xx" "ppc6xx")
24 (define_cpu_unit "fpu_6xx" "ppc6xxfp")
25 (define_cpu_unit "fpu1_6xx,fpu2_6xx" "ppc6xxfp2")
26 (define_cpu_unit "lsu_6xx,bpu_6xx,cru_6xx" "ppc6xx")
28 ;; PPC604 32-bit 2xSCIU, MCIU, LSU, FPU, BPU
29 ;; PPC604e 32-bit 2xSCIU, MCIU, LSU, FPU, BPU, CRU
30 ;; MCIU used for imul/idiv and moves from/to spr
31 ;; LSU 2 stage pipelined
32 ;; FPU 3 stage pipelined
33 ;; Max issue 4 insns/clock cycle
35 ;; PPC604e is PPC604 with larger caches and a CRU. In the 604
36 ;; the CR logical operations are handled in the BPU.
37 ;; In the 604e, the CRU shares bus with BPU so only one condition
38 ;; register or branch insn can be issued per clock. Not modelled.
40 ;; PPC620 64-bit 2xSCIU, MCIU, LSU, FPU, BPU, CRU
41 ;; PPC630 64-bit 2xSCIU, MCIU, LSU, 2xFPU, BPU, CRU
42 ;; Max issue 4 insns/clock cycle
43 ;; Out-of-order execution, in-order completion
45 ;; No following instruction can dispatch in the same cycle as a branch
46 ;; instruction. Not modelled. This is no problem if RCSP is not
47 ;; enabled since the scheduler stops a schedule when it gets to a branch.
49 ;; Four insns can be dispatched per cycle.
51 (define_insn_reservation "ppc604-load" 2
52 (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
53 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
56 (define_insn_reservation "ppc604-fpload" 3
57 (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
58 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
61 (define_insn_reservation "ppc604-store" 1
62 (and (eq_attr "type" "store,fpstore,store_ux,store_u,fpstore_ux,fpstore_u")
63 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
66 (define_insn_reservation "ppc604-integer" 1
67 (and (eq_attr "type" "integer")
68 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
71 (define_insn_reservation "ppc604-imul" 4
72 (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
73 (eq_attr "cpu" "ppc604"))
76 (define_insn_reservation "ppc604e-imul" 2
77 (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
78 (eq_attr "cpu" "ppc604e"))
81 (define_insn_reservation "ppc620-imul" 5
82 (and (eq_attr "type" "imul,imul_compare")
83 (eq_attr "cpu" "ppc620,ppc630"))
86 (define_insn_reservation "ppc620-imul2" 4
87 (and (eq_attr "type" "imul2")
88 (eq_attr "cpu" "ppc620,ppc630"))
91 (define_insn_reservation "ppc620-imul3" 3
92 (and (eq_attr "type" "imul3")
93 (eq_attr "cpu" "ppc620,ppc630"))
96 (define_insn_reservation "ppc620-lmul" 7
97 (and (eq_attr "type" "lmul,lmul_compare")
98 (eq_attr "cpu" "ppc620,ppc630"))
101 (define_insn_reservation "ppc604-idiv" 20
102 (and (eq_attr "type" "idiv")
103 (eq_attr "cpu" "ppc604,ppc604e"))
106 (define_insn_reservation "ppc620-idiv" 37
107 (and (eq_attr "type" "idiv")
108 (eq_attr "cpu" "ppc620"))
111 (define_insn_reservation "ppc630-idiv" 21
112 (and (eq_attr "type" "idiv")
113 (eq_attr "cpu" "ppc630"))
116 (define_insn_reservation "ppc620-ldiv" 37
117 (and (eq_attr "type" "ldiv")
118 (eq_attr "cpu" "ppc620,ppc630"))
121 (define_insn_reservation "ppc604-compare" 3
122 (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare")
123 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
126 ; FPU PPC604{,e},PPC620
127 (define_insn_reservation "ppc604-fpcompare" 5
128 (and (eq_attr "type" "fpcompare")
129 (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
132 (define_insn_reservation "ppc604-fp" 3
133 (and (eq_attr "type" "fp")
134 (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
137 (define_insn_reservation "ppc604-dmul" 3
138 (and (eq_attr "type" "dmul")
139 (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
142 ; Divides are not pipelined
143 (define_insn_reservation "ppc604-sdiv" 18
144 (and (eq_attr "type" "sdiv")
145 (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
148 (define_insn_reservation "ppc604-ddiv" 32
149 (and (eq_attr "type" "ddiv")
150 (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
153 (define_insn_reservation "ppc620-ssqrt" 31
154 (and (eq_attr "type" "ssqrt")
155 (eq_attr "cpu" "ppc620"))
158 (define_insn_reservation "ppc620-dsqrt" 31
159 (and (eq_attr "type" "dsqrt")
160 (eq_attr "cpu" "ppc620"))
165 (define_insn_reservation "ppc630-fpcompare" 5
166 (and (eq_attr "type" "fpcompare")
167 (eq_attr "cpu" "ppc630"))
170 (define_insn_reservation "ppc630-fp" 3
171 (and (eq_attr "type" "fp,dmul")
172 (eq_attr "cpu" "ppc630"))
175 (define_insn_reservation "ppc630-sdiv" 17
176 (and (eq_attr "type" "sdiv")
177 (eq_attr "cpu" "ppc630"))
178 "fpu1_6xx*17|fpu2_6xx*17")
180 (define_insn_reservation "ppc630-ddiv" 21
181 (and (eq_attr "type" "ddiv")
182 (eq_attr "cpu" "ppc630"))
183 "fpu1_6xx*21|fpu2_6xx*21")
185 (define_insn_reservation "ppc630-ssqrt" 18
186 (and (eq_attr "type" "ssqrt")
187 (eq_attr "cpu" "ppc630"))
188 "fpu1_6xx*18|fpu2_6xx*18")
190 (define_insn_reservation "ppc630-dsqrt" 25
191 (and (eq_attr "type" "dsqrt")
192 (eq_attr "cpu" "ppc630"))
193 "fpu1_6xx*25|fpu2_6xx*25")
195 (define_insn_reservation "ppc604-mfcr" 3
196 (and (eq_attr "type" "mfcr")
197 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
200 (define_insn_reservation "ppc604-mtcr" 2
201 (and (eq_attr "type" "mtcr")
202 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
205 (define_insn_reservation "ppc604-crlogical" 2
206 (and (eq_attr "type" "cr_logical,delayed_cr")
207 (eq_attr "cpu" "ppc604"))
210 (define_insn_reservation "ppc604e-crlogical" 2
211 (and (eq_attr "type" "cr_logical,delayed_cr")
212 (eq_attr "cpu" "ppc604e,ppc620,ppc630"))
215 (define_insn_reservation "ppc604-mtjmpr" 2
216 (and (eq_attr "type" "mtjmpr")
217 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
220 (define_insn_reservation "ppc604-mfjmpr" 3
221 (and (eq_attr "type" "mfjmpr")
222 (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
225 (define_insn_reservation "ppc630-mfjmpr" 2
226 (and (eq_attr "type" "mfjmpr")
227 (eq_attr "cpu" "ppc630"))
230 (define_insn_reservation "ppc604-jmpreg" 1
231 (and (eq_attr "type" "jmpreg,branch")
232 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))