gcc/config/rs6000/7450.md

   1 ;; Scheduling description for Motorola PowerPC 7450 processor.
   2 ;;   Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5
   6 ;; GCC is free software; you can redistribute it and/or modify it
   7 ;; under the terms of the GNU General Public License as published
   8 ;; by the Free Software Foundation; either version 3, or (at your
   9 ;; option) any later version.
  10
  11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14 ;; License for more details.
  15
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19
  20 (define_automaton "ppc7450,ppc7450mciu,ppc7450fp,ppc7450vec")
  21 (define_cpu_unit "iu1_7450,iu2_7450,iu3_7450" "ppc7450")
  22 (define_cpu_unit "mciu_7450" "ppc7450mciu")
  23 (define_cpu_unit "fpu_7450" "ppc7450fp")
  24 (define_cpu_unit "lsu_7450,bpu_7450" "ppc7450")
  25 (define_cpu_unit "du1_7450,du2_7450,du3_7450" "ppc7450")
  26 (define_cpu_unit "vecsmpl_7450,veccmplx_7450,vecflt_7450,vecperm_7450" "ppc7450vec")
  27 (define_cpu_unit "vdu1_7450,vdu2_7450" "ppc7450vec")
  28
  29
  30 ;; PPC7450  32-bit 3xIU, MCIU, LSU, SRU, FPU, BPU, 4xVEC
  31 ;; IU1,IU2,IU3 can perform all integer operations
  32 ;; MCIU performs imul and idiv, cr logical, SPR moves
  33 ;; LSU 2 stage pipelined
  34 ;; FPU 3 stage pipelined
  35 ;; It also has 4 vector units, one for each type of vector instruction.
  36 ;; However, we can only dispatch 2 instructions per cycle.
  37 ;; Max issue 3 insns/clock cycle (includes 1 branch)
  38 ;; In-order execution
  39
  40 ;; Branches go straight to the BPU.  All other insns are handled
  41 ;; by a dispatch unit which can issue a max of 3 insns per cycle.
  42 (define_reservation "ppc7450_du" "du1_7450|du2_7450|du3_7450")
  43 (define_reservation "ppc7450_vec_du" "vdu1_7450|vdu2_7450")
  44
  45 (define_insn_reservation "ppc7450-load" 3
  46   (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,\
  47                         load_ux,load_u,vecload")
  48        (eq_attr "cpu" "ppc7450"))
  49   "ppc7450_du,lsu_7450")
  50
  51 (define_insn_reservation "ppc7450-store" 3
  52   (and (eq_attr "type" "store,store_ux,store_u,vecstore")
  53        (eq_attr "cpu" "ppc7450"))
  54   "ppc7450_du,lsu_7450")
  55
  56 (define_insn_reservation "ppc7450-fpload" 4
  57   (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
  58        (eq_attr "cpu" "ppc7450"))
  59   "ppc7450_du,lsu_7450")
  60
  61 (define_insn_reservation "ppc7450-fpstore" 3
  62   (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
  63        (eq_attr "cpu" "ppc7450"))
  64   "ppc7450_du,lsu_7450*3")
  65
  66 (define_insn_reservation "ppc7450-llsc" 3
  67   (and (eq_attr "type" "load_l,store_c")
  68        (eq_attr "cpu" "ppc7450"))
  69   "ppc7450_du,lsu_7450")
  70
  71 (define_insn_reservation "ppc7450-sync" 35
  72   (and (eq_attr "type" "sync")
  73        (eq_attr "cpu" "ppc7450"))
  74   "ppc7450_du,lsu_7450")
  75
  76 (define_insn_reservation "ppc7450-integer" 1
  77   (and (eq_attr "type" "integer,insert_word,insert_dword,shift,\
  78                         trap,var_shift_rotate,cntlz,exts,isel")
  79        (eq_attr "cpu" "ppc7450"))
  80   "ppc7450_du,iu1_7450|iu2_7450|iu3_7450")
  81
  82 (define_insn_reservation "ppc7450-two" 1
  83   (and (eq_attr "type" "two")
  84        (eq_attr "cpu" "ppc7450"))
  85   "ppc7450_du,iu1_7450|iu2_7450|iu3_7450,iu1_7450|iu2_7450|iu3_7450")
  86
  87 (define_insn_reservation "ppc7450-three" 1
  88   (and (eq_attr "type" "three")
  89        (eq_attr "cpu" "ppc7450"))
  90   "ppc7450_du,iu1_7450|iu2_7450|iu3_7450,\
  91    iu1_7450|iu2_7450|iu3_7450,iu1_7450|iu2_7450|iu3_7450")
  92
  93 (define_insn_reservation "ppc7450-imul" 4
  94   (and (eq_attr "type" "imul,imul_compare")
  95        (eq_attr "cpu" "ppc7450"))
  96   "ppc7450_du,mciu_7450*2")
  97
  98 (define_insn_reservation "ppc7450-imul2" 3
  99   (and (eq_attr "type" "imul2,imul3")
 100        (eq_attr "cpu" "ppc7450"))
 101   "ppc7450_du,mciu_7450")
 102
 103 (define_insn_reservation "ppc7450-idiv" 23
 104   (and (eq_attr "type" "idiv")
 105        (eq_attr "cpu" "ppc7450"))
 106   "ppc7450_du,mciu_7450*23")
 107
 108 (define_insn_reservation "ppc7450-compare" 2
 109   (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
 110                         var_delayed_compare")
 111        (eq_attr "cpu" "ppc7450"))
 112   "ppc7450_du,(iu1_7450|iu2_7450|iu3_7450)")
 113
 114 (define_insn_reservation "ppc7450-fpcompare" 5
 115   (and (eq_attr "type" "fpcompare")
 116        (eq_attr "cpu" "ppc7450"))
 117   "ppc7450_du,fpu_7450")
 118
 119 (define_insn_reservation "ppc7450-fp" 5
 120   (and (eq_attr "type" "fp,dmul")
 121        (eq_attr "cpu" "ppc7450"))
 122   "ppc7450_du,fpu_7450")
 123
 124 ; Divides are not pipelined
 125 (define_insn_reservation "ppc7450-sdiv" 21
 126   (and (eq_attr "type" "sdiv")
 127        (eq_attr "cpu" "ppc7450"))
 128   "ppc7450_du,fpu_7450*21")
 129
 130 (define_insn_reservation "ppc7450-ddiv" 35
 131   (and (eq_attr "type" "ddiv")
 132        (eq_attr "cpu" "ppc7450"))
 133   "ppc7450_du,fpu_7450*35")
 134
 135 (define_insn_reservation "ppc7450-mfcr" 2
 136   (and (eq_attr "type" "mfcr,mtcr")
 137        (eq_attr "cpu" "ppc7450"))
 138   "ppc7450_du,mciu_7450")
 139
 140 (define_insn_reservation "ppc7450-crlogical" 1
 141   (and (eq_attr "type" "cr_logical,delayed_cr")
 142        (eq_attr "cpu" "ppc7450"))
 143   "ppc7450_du,mciu_7450")
 144
 145 (define_insn_reservation "ppc7450-mtjmpr" 2
 146   (and (eq_attr "type" "mtjmpr")
 147        (eq_attr "cpu" "ppc7450"))
 148   "nothing,mciu_7450*2")
 149
 150 (define_insn_reservation "ppc7450-mfjmpr" 3
 151   (and (eq_attr "type" "mfjmpr")
 152        (eq_attr "cpu" "ppc7450"))
 153   "nothing,mciu_7450*2")
 154
 155 (define_insn_reservation "ppc7450-jmpreg" 1
 156   (and (eq_attr "type" "jmpreg,branch,isync")
 157        (eq_attr "cpu" "ppc7450"))
 158   "nothing,bpu_7450")
 159
 160 ;; Altivec
 161 (define_insn_reservation "ppc7450-vecsimple" 1
 162   (and (eq_attr "type" "vecsimple")
 163        (eq_attr "cpu" "ppc7450"))
 164   "ppc7450_du,ppc7450_vec_du,vecsmpl_7450")
 165
 166 (define_insn_reservation "ppc7450-veccomplex" 4
 167   (and (eq_attr "type" "veccomplex")
 168        (eq_attr "cpu" "ppc7450"))
 169   "ppc7450_du,ppc7450_vec_du,veccmplx_7450")
 170
 171 (define_insn_reservation "ppc7450-veccmp" 2
 172   (and (eq_attr "type" "veccmp")
 173        (eq_attr "cpu" "ppc7450"))
 174   "ppc7450_du,ppc7450_vec_du,veccmplx_7450")
 175
 176 (define_insn_reservation "ppc7450-vecfloat" 4
 177   (and (eq_attr "type" "vecfloat")
 178        (eq_attr "cpu" "ppc7450"))
 179   "ppc7450_du,ppc7450_vec_du,vecflt_7450")
 180
 181 (define_insn_reservation "ppc7450-vecperm" 2
 182   (and (eq_attr "type" "vecperm")
 183        (eq_attr "cpu" "ppc7450"))
 184   "ppc7450_du,ppc7450_vec_du,vecperm_7450")
 185