gcc/config/rs6000/constraints.md

   1 ;; Constraint definitions for RS6000
   2 ;; Copyright (C) 2006-2023 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5 ;;
   6 ;; GCC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 3, or (at your option)
   9 ;; any later version.
  10 ;;
  11 ;; GCC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19
  20 ;; Available constraint letters: k q t u A B C D S T
  21
  22 ;; Register constraints
  23
  24 ; Actually defined in common.md:
  25 ; (define_register_constraint "r" "GENERAL_REGS"
  26 ;   "A general purpose register (GPR), @code{r0}@dots{}@code{r31}.")
  27
  28 (define_register_constraint "b" "BASE_REGS"
  29   "A base register.  Like @code{r}, but @code{r0} is not allowed, so
  30    @code{r1}@dots{}@code{r31}.")
  31
  32 (define_register_constraint "f" "rs6000_constraints[RS6000_CONSTRAINT_d]"
  33   "A floating point register (FPR), @code{f0}@dots{}@code{f31}.")
  34
  35 (define_register_constraint "d" "rs6000_constraints[RS6000_CONSTRAINT_d]"
  36   "A floating point register.  This is the same as @code{f} nowadays;
  37    historically @code{f} was for single-precision and @code{d} was for
  38    double-precision floating point.")
  39
  40 (define_register_constraint "v" "rs6000_constraints[RS6000_CONSTRAINT_v]"
  41   "An Altivec vector register (VR), @code{v0}@dots{}@code{v31}.")
  42
  43 (define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]"
  44   "A VSX register (VSR), @code{vs0}@dots{}@code{vs63}.  This is either an
  45   FPR (@code{vs0}@dots{}@code{vs31} are @code{f0}@dots{}@code{f31}) or a VR
  46   (@code{vs32}@dots{}@code{vs63} are @code{v0}@dots{}@code{v31}).")
  47
  48 (define_register_constraint "wd" "rs6000_constraints[RS6000_CONSTRAINT_wa]"
  49   "@internal A compatibility alias for @code{wa}.")
  50 (define_register_constraint "wf" "rs6000_constraints[RS6000_CONSTRAINT_wa]"
  51   "@internal A compatibility alias for @code{wa}.")
  52 (define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wa]"
  53   "@internal A compatibility alias for @code{wa}.")
  54 (define_register_constraint "ws" "rs6000_constraints[RS6000_CONSTRAINT_wa]"
  55   "@internal A compatibility alias for @code{wa}.")
  56 (define_register_constraint "ww" "rs6000_constraints[RS6000_CONSTRAINT_wa]"
  57   "@internal A compatibility alias for @code{wa}.")
  58
  59 (define_register_constraint "h" "SPECIAL_REGS"
  60   "@internal A special register (@code{vrsave}, @code{ctr}, or @code{lr}).")
  61
  62 (define_register_constraint "c" "CTR_REGS"
  63   "The count register, @code{ctr}.")
  64
  65 (define_register_constraint "l" "LINK_REGS"
  66   "The link register, @code{lr}.")
  67
  68 (define_register_constraint "x" "CR0_REGS"
  69   "Condition register field 0, @code{cr0}.")
  70
  71 (define_register_constraint "y" "CR_REGS"
  72   "Any condition register field, @code{cr0}@dots{}@code{cr7}.")
  73
  74 (define_register_constraint "z" "CA_REGS"
  75   "@internal The carry bit, @code{XER[CA]}.")
  76
  77 ;; NOTE: For compatibility, "wc" is reserved to represent individual CR bits.
  78 ;; It is currently used for that purpose in LLVM.
  79
  80 (define_register_constraint "we" "rs6000_constraints[RS6000_CONSTRAINT_we]"
  81   "@internal Like @code{wa}, if @option{-mpower9-vector} and @option{-m64} are
  82    used; otherwise, @code{NO_REGS}.")
  83
  84 ;; NO_REGs register constraint, used to merge mov{sd,sf}, since movsd can use
  85 ;; direct move directly, and movsf can't to move between the register sets.
  86 ;; There is a mode_attr that resolves to wa for SDmode and wn for SFmode
  87 (define_register_constraint "wn" "NO_REGS"
  88   "@internal No register (@code{NO_REGS}).")
  89
  90 (define_register_constraint "wr" "rs6000_constraints[RS6000_CONSTRAINT_wr]"
  91   "@internal Like @code{r}, if @option{-mpowerpc64} is used; otherwise,
  92    @code{NO_REGS}.")
  93
  94 (define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]"
  95   "@internal Like @code{d}, if @option{-mpowerpc-gfxopt} is used; otherwise,
  96    @code{NO_REGS}.")
  97
  98 (define_register_constraint "wA" "rs6000_constraints[RS6000_CONSTRAINT_wA]"
  99   "@internal Like @code{b}, if @option{-mpowerpc64} is used; otherwise,
 100    @code{NO_REGS}.")
 101
 102 ;; wB needs ISA 2.07 VUPKHSW
 103 (define_constraint "wB"
 104   "@internal Signed 5-bit constant integer that can be loaded into an
 105    Altivec register."
 106   (and (match_code "const_int")
 107        (match_test "TARGET_P8_VECTOR")
 108        (match_operand 0 "s5bit_cint_operand")))
 109
 110 (define_constraint "wE"
 111   "@internal Vector constant that can be loaded with the XXSPLTIB instruction."
 112   (match_test "xxspltib_constant_nosplit (op, mode)"))
 113
 114 ;; Extended fusion store
 115 (define_memory_constraint "wF"
 116   "@internal Memory operand suitable for power8 GPR load fusion."
 117   (match_operand 0 "fusion_addis_mem_combo_load"))
 118
 119 (define_constraint "wL"
 120   "@internal Int constant that is the element number mfvsrld accesses in
 121    a vector."
 122   (and (match_code "const_int")
 123        (match_test "TARGET_DIRECT_MOVE_128")
 124        (match_test "(ival == VECTOR_ELEMENT_MFVSRLD_64BIT)")))
 125
 126 ;; Generate the XXORC instruction to set a register to all 1's
 127 (define_constraint "wM"
 128   "@internal Match vector constant with all 1's if the XXLORC instruction
 129    is available."
 130   (and (match_test "TARGET_P8_VECTOR")
 131        (match_operand 0 "all_ones_constant")))
 132
 133 ;; ISA 3.0 vector d-form addresses
 134 (define_memory_constraint "wO"
 135   "@internal Memory operand suitable for the ISA 3.0 vector d-form instructions."
 136   (match_operand 0 "vsx_quad_dform_memory_operand"))
 137
 138 ;; Lq/stq validates the address for load/store quad
 139 (define_memory_constraint "wQ"
 140   "@internal Memory operand suitable for the load/store quad instructions."
 141   (match_operand 0 "quad_memory_operand"))
 142
 143 (define_constraint "wS"
 144   "@internal Vector constant that can be loaded with XXSPLTIB & sign extension."
 145   (match_test "xxspltib_constant_split (op, mode)"))
 146
 147 ;; ISA 3.0 DS-form instruction that has the bottom 2 bits 0 and no update form.
 148 ;; Used by LXSD/STXSD/LXSSP/STXSSP.  In contrast to "Y", the multiple-of-four
 149 ;; offset is enforced for 32-bit too.
 150 (define_memory_constraint "wY"
 151   "@internal A memory operand for a DS-form instruction."
 152   (and (match_code "mem")
 153        (not (match_test "update_address_mem (op, mode)"))
 154        (match_test "mem_operand_ds_form (op, mode)")))
 155
 156 ;; Altivec style load/store that ignores the bottom bits of the address
 157 (define_memory_constraint "wZ"
 158   "@internal An indexed or indirect memory operand, ignoring the bottom 4 bits."
 159   (match_operand 0 "altivec_indexed_or_indirect_operand"))
 160
 161 ;; Integer constraints
 162
 163 (define_constraint "I"
 164   "A signed 16-bit constant."
 165   (and (match_code "const_int")
 166        (match_test "((unsigned HOST_WIDE_INT) ival + 0x8000) < 0x10000")))
 167
 168 (define_constraint "J"
 169   "An unsigned 16-bit constant shifted left 16 bits (use @code{L} instead
 170    for @code{SImode} constants)."
 171   (and (match_code "const_int")
 172        (match_test "(ival & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0")))
 173
 174 (define_constraint "K"
 175   "An unsigned 16-bit constant."
 176   (and (match_code "const_int")
 177        (match_test "(ival & (~ (HOST_WIDE_INT) 0xffff)) == 0")))
 178
 179 (define_constraint "L"
 180   "A signed 16-bit constant shifted left 16 bits."
 181   (and (match_code "const_int")
 182        (match_test "((ival & 0xffff) == 0
 183                       && (ival >> 31 == -1 || ival >> 31 == 0))")))
 184
 185 (define_constraint "M"
 186   "@internal A constant greater than 31."
 187   (and (match_code "const_int")
 188        (match_test "ival > 31")))
 189
 190 (define_constraint "N"
 191   "@internal An exact power of two."
 192   (and (match_code "const_int")
 193        (match_test "ival > 0 && exact_log2 (ival) >= 0")))
 194
 195 (define_constraint "O"
 196   "@internal The integer constant zero."
 197   (and (match_code "const_int")
 198        (match_test "ival == 0")))
 199
 200 (define_constraint "P"
 201   "@internal A constant whose negation is a signed 16-bit constant."
 202   (and (match_code "const_int")
 203        (match_test "((- (unsigned HOST_WIDE_INT) ival) + 0x8000) < 0x10000")))
 204
 205 ;; 34-bit signed integer constant
 206 (define_constraint "eI"
 207   "A signed 34-bit integer constant if prefixed instructions are supported."
 208   (match_operand 0 "cint34_operand"))
 209
 210 ;; A SF/DF scalar constant or a vector constant that can be loaded into vector
 211 ;; registers with one prefixed instruction such as XXSPLTIDP or XXSPLTIW.
 212 (define_constraint "eP"
 213   "A constant that can be loaded into a VSX register with one prefixed insn."
 214   (match_operand 0 "vsx_prefixed_constant"))
 215
 216 ;; A TF/KF scalar constant or a vector constant that can load certain IEEE
 217 ;; 128-bit constants into vector registers using LXVKQ.
 218 (define_constraint "eQ"
 219   "An IEEE 128-bit constant that can be loaded into VSX registers."
 220   (match_operand 0 "easy_vector_constant_ieee128"))
 221
 222 ;; Floating-point constraints.  These two are defined so that insn
 223 ;; length attributes can be calculated exactly.
 224
 225 (define_constraint "G"
 226   "@internal A floating point constant that can be loaded into a register
 227    with one instruction per word."
 228   (and (match_code "const_double")
 229        (match_test "num_insns_constant (op, mode)
 230                     == (mode == SFmode || mode == SDmode ? 1 : 2)")))
 231
 232 (define_constraint "H"
 233   "@internal A floating point constant that can be loaded into a register
 234    using three instructions."
 235   (and (match_code "const_double")
 236        (match_test "num_insns_constant (op, mode) == 3")))
 237
 238 ;; Memory constraints
 239
 240 ; Actually defined in common.md:
 241 ; (define_memory_constraint "m"
 242 ;   "A memory operand."
 243
 244 (define_memory_constraint "es"
 245   "@internal
 246    A ``stable'' memory operand; that is, one which does not include any
 247    automodification of the base register.  This used to be useful when
 248    @code{m} allowed automodification of the base register, but as those
 249    are now only allowed when @code{<} or @code{>} is used, @code{es} is
 250    basically the same as @code{m} without @code{<} and @code{>}."
 251   (and (match_code "mem")
 252        (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != RTX_AUTOINC")))
 253
 254 (define_memory_constraint "Q"
 255   "A memory operand addressed by just a base register."
 256   (and (match_code "mem")
 257        (match_test "REG_P (XEXP (op, 0))")))
 258
 259 (define_memory_constraint "Y"
 260   "@internal A memory operand for a DS-form instruction."
 261   (and (match_code "mem")
 262        (match_test "mem_operand_gpr (op, mode)")))
 263
 264 (define_memory_constraint "Z"
 265   "A memory operand accessed with indexed or indirect addressing."
 266   (match_operand 0 "indexed_or_indirect_operand"))
 267
 268 ;; Address constraints
 269
 270 (define_constraint "R"
 271   "@internal An AIX TOC entry."
 272   (match_test "legitimate_constant_pool_address_p (op, QImode, false)"))
 273
 274 (define_address_constraint "a"
 275   "An indexed or indirect address."
 276   (match_operand 0 "indexed_or_indirect_address"))
 277
 278 ;; General constraints
 279
 280 (define_constraint "U"
 281   "@internal A V.4 small data reference."
 282   (and (match_test "DEFAULT_ABI == ABI_V4")
 283        (match_test "small_data_operand (op, mode)")))
 284
 285 (define_constraint "W"
 286   "@internal A vector constant that does not require memory."
 287   (match_operand 0 "easy_vector_constant"))
 288
 289 (define_constraint "j"
 290   "@internal The zero vector constant."
 291   (match_test "op == const0_rtx || op == CONST0_RTX (mode)"))