gcc/config/rs6000/constraints.md

   1 ;; Constraint definitions for RS6000
   2 ;; Copyright (C) 2006-2016 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5 ;;
   6 ;; GCC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 3, or (at your option)
   9 ;; any later version.
  10 ;;
  11 ;; GCC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19
  20 ;; Available constraint letters: e k q t u A B C D S T
  21
  22 ;; Register constraints
  23
  24 (define_register_constraint "f" "rs6000_constraints[RS6000_CONSTRAINT_f]"
  25   "@internal")
  26
  27 (define_register_constraint "d" "rs6000_constraints[RS6000_CONSTRAINT_d]"
  28   "@internal")
  29
  30 (define_register_constraint "b" "BASE_REGS"
  31   "@internal")
  32
  33 (define_register_constraint "h" "SPECIAL_REGS"
  34   "@internal")
  35
  36 (define_register_constraint "c" "CTR_REGS"
  37   "@internal")
  38
  39 (define_register_constraint "l" "LINK_REGS"
  40   "@internal")
  41
  42 (define_register_constraint "v" "ALTIVEC_REGS"
  43   "@internal")
  44
  45 (define_register_constraint "x" "CR0_REGS"
  46   "@internal")
  47
  48 (define_register_constraint "y" "CR_REGS"
  49   "@internal")
  50
  51 (define_register_constraint "z" "CA_REGS"
  52   "@internal")
  53
  54 ;; Use w as a prefix to add VSX modes
  55 ;; any VSX register
  56 (define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]"
  57   "Any VSX register if the -mvsx option was used or NO_REGS.")
  58
  59 (define_register_constraint "wb" "rs6000_constraints[RS6000_CONSTRAINT_wb]"
  60   "Altivec register if the -mpower9-dform option was used or NO_REGS.")
  61
  62 ;; NOTE: For compatibility, "wc" is reserved to represent individual CR bits.
  63 ;; It is currently used for that purpose in LLVM.
  64
  65 (define_register_constraint "wd" "rs6000_constraints[RS6000_CONSTRAINT_wd]"
  66   "VSX vector register to hold vector double data or NO_REGS.")
  67
  68 (define_register_constraint "we" "rs6000_constraints[RS6000_CONSTRAINT_we]"
  69   "VSX register if the -mpower9-vector -m64 options were used or NO_REGS.")
  70
  71 (define_register_constraint "wf" "rs6000_constraints[RS6000_CONSTRAINT_wf]"
  72   "VSX vector register to hold vector float data or NO_REGS.")
  73
  74 (define_register_constraint "wg" "rs6000_constraints[RS6000_CONSTRAINT_wg]"
  75   "If -mmfpgpr was used, a floating point register or NO_REGS.")
  76
  77 (define_register_constraint "wh" "rs6000_constraints[RS6000_CONSTRAINT_wh]"
  78   "Floating point register if direct moves are available, or NO_REGS.")
  79
  80 ;; At present, DImode is not allowed in the Altivec registers.  If in the
  81 ;; future it is allowed, wi/wj can be set to VSX_REGS instead of FLOAT_REGS.
  82 (define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wi]"
  83   "FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.")
  84
  85 (define_register_constraint "wj" "rs6000_constraints[RS6000_CONSTRAINT_wj]"
  86   "FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.")
  87
  88 (define_register_constraint "wk" "rs6000_constraints[RS6000_CONSTRAINT_wk]"
  89   "FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.")
  90
  91 (define_register_constraint "wl" "rs6000_constraints[RS6000_CONSTRAINT_wl]"
  92   "Floating point register if the LFIWAX instruction is enabled or NO_REGS.")
  93
  94 (define_register_constraint "wm" "rs6000_constraints[RS6000_CONSTRAINT_wm]"
  95   "VSX register if direct move instructions are enabled, or NO_REGS.")
  96
  97 ;; NO_REGs register constraint, used to merge mov{sd,sf}, since movsd can use
  98 ;; direct move directly, and movsf can't to move between the register sets.
  99 ;; There is a mode_attr that resolves to wm for SDmode and wn for SFmode
 100 (define_register_constraint "wn" "NO_REGS" "No register (NO_REGS).")
 101
 102 (define_register_constraint "wo" "rs6000_constraints[RS6000_CONSTRAINT_wo]"
 103   "VSX register if the -mpower9-vector option was used or NO_REGS.")
 104
 105 (define_register_constraint "wp" "rs6000_constraints[RS6000_CONSTRAINT_wp]"
 106   "VSX register to use for IEEE 128-bit fp TFmode, or NO_REGS.")
 107
 108 (define_register_constraint "wq" "rs6000_constraints[RS6000_CONSTRAINT_wq]"
 109   "VSX register to use for IEEE 128-bit fp KFmode, or NO_REGS.")
 110
 111 (define_register_constraint "wr" "rs6000_constraints[RS6000_CONSTRAINT_wr]"
 112   "General purpose register if 64-bit instructions are enabled or NO_REGS.")
 113
 114 (define_register_constraint "ws" "rs6000_constraints[RS6000_CONSTRAINT_ws]"
 115   "VSX vector register to hold scalar double values or NO_REGS.")
 116
 117 (define_register_constraint "wt" "rs6000_constraints[RS6000_CONSTRAINT_wt]"
 118   "VSX vector register to hold 128 bit integer or NO_REGS.")
 119
 120 (define_register_constraint "wu" "rs6000_constraints[RS6000_CONSTRAINT_wu]"
 121   "Altivec register to use for float/32-bit int loads/stores  or NO_REGS.")
 122
 123 (define_register_constraint "wv" "rs6000_constraints[RS6000_CONSTRAINT_wv]"
 124   "Altivec register to use for double loads/stores  or NO_REGS.")
 125
 126 (define_register_constraint "ww" "rs6000_constraints[RS6000_CONSTRAINT_ww]"
 127   "FP or VSX register to perform float operations under -mvsx or NO_REGS.")
 128
 129 (define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]"
 130   "Floating point register if the STFIWX instruction is enabled or NO_REGS.")
 131
 132 (define_register_constraint "wy" "rs6000_constraints[RS6000_CONSTRAINT_wy]"
 133   "FP or VSX register to perform ISA 2.07 float ops or NO_REGS.")
 134
 135 (define_register_constraint "wz" "rs6000_constraints[RS6000_CONSTRAINT_wz]"
 136   "Floating point register if the LFIWZX instruction is enabled or NO_REGS.")
 137
 138 (define_constraint "wD"
 139   "Int constant that is the element number of the 64-bit scalar in a vector."
 140   (and (match_code "const_int")
 141        (match_test "TARGET_VSX && (ival == VECTOR_ELEMENT_SCALAR_64BIT)")))
 142
 143 ;; Extended fusion store
 144 (define_memory_constraint "wF"
 145   "Memory operand suitable for power9 fusion load/stores"
 146   (match_operand 0 "fusion_addis_mem_combo_load"))
 147
 148 ;; Fusion gpr load.
 149 (define_memory_constraint "wG"
 150   "Memory operand suitable for TOC fusion memory references"
 151   (match_operand 0 "toc_fusion_mem_wrapped"))
 152
 153 (define_constraint "wL"
 154   "Int constant that is the element number mfvsrld accesses in a vector."
 155   (and (match_code "const_int")
 156        (and (match_test "TARGET_DIRECT_MOVE_128")
 157             (match_test "(ival == VECTOR_ELEMENT_MFVSRLD_64BIT)"))))
 158
 159 ;; Lq/stq validates the address for load/store quad
 160 (define_memory_constraint "wQ"
 161   "Memory operand suitable for the load/store quad instructions"
 162   (match_operand 0 "quad_memory_operand"))
 163
 164 ;; Altivec style load/store that ignores the bottom bits of the address
 165 (define_memory_constraint "wZ"
 166   "Indexed or indirect memory operand, ignoring the bottom 4 bits"
 167   (match_operand 0 "altivec_indexed_or_indirect_operand"))
 168
 169 ;; Integer constraints
 170
 171 (define_constraint "I"
 172   "A signed 16-bit constant"
 173   (and (match_code "const_int")
 174        (match_test "((unsigned HOST_WIDE_INT) ival + 0x8000) < 0x10000")))
 175
 176 (define_constraint "J"
 177   "high-order 16 bits nonzero"
 178   (and (match_code "const_int")
 179        (match_test "(ival & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0")))
 180
 181 (define_constraint "K"
 182   "low-order 16 bits nonzero"
 183   (and (match_code "const_int")
 184        (match_test "(ival & (~ (HOST_WIDE_INT) 0xffff)) == 0")))
 185
 186 (define_constraint "L"
 187   "signed 16-bit constant shifted left 16 bits"
 188   (and (match_code "const_int")
 189        (match_test "((ival & 0xffff) == 0
 190                       && (ival >> 31 == -1 || ival >> 31 == 0))")))
 191
 192 (define_constraint "M"
 193   "constant greater than 31"
 194   (and (match_code "const_int")
 195        (match_test "ival > 31")))
 196
 197 (define_constraint "N"
 198   "positive constant that is an exact power of two"
 199   (and (match_code "const_int")
 200        (match_test "ival > 0 && exact_log2 (ival) >= 0")))
 201
 202 (define_constraint "O"
 203   "constant zero"
 204   (and (match_code "const_int")
 205        (match_test "ival == 0")))
 206
 207 (define_constraint "P"
 208   "constant whose negation is signed 16-bit constant"
 209   (and (match_code "const_int")
 210        (match_test "((- (unsigned HOST_WIDE_INT) ival) + 0x8000) < 0x10000")))
 211
 212 ;; Floating-point constraints
 213
 214 (define_constraint "G"
 215   "Constant that can be copied into GPR with two insns for DF/DI
 216    and one for SF."
 217   (and (match_code "const_double")
 218        (match_test "num_insns_constant (op, mode)
 219                     == (mode == SFmode ? 1 : 2)")))
 220
 221 (define_constraint "H"
 222   "DF/DI constant that takes three insns."
 223   (and (match_code "const_double")
 224        (match_test "num_insns_constant (op, mode) == 3")))
 225
 226 ;; Memory constraints
 227
 228 (define_memory_constraint "es"
 229   "A ``stable'' memory operand; that is, one which does not include any
 230 automodification of the base register.  Unlike @samp{m}, this constraint
 231 can be used in @code{asm} statements that might access the operand
 232 several times, or that might not access it at all."
 233   (and (match_code "mem")
 234        (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != RTX_AUTOINC")))
 235
 236 (define_memory_constraint "Q"
 237   "Memory operand that is an offset from a register (it is usually better
 238 to use @samp{m} or @samp{es} in @code{asm} statements)"
 239   (and (match_code "mem")
 240        (match_test "GET_CODE (XEXP (op, 0)) == REG")))
 241
 242 (define_memory_constraint "Y"
 243   "memory operand for 8 byte and 16 byte gpr load/store"
 244   (and (match_code "mem")
 245        (match_test "mem_operand_gpr (op, mode)")))
 246
 247 (define_memory_constraint "Z"
 248   "Memory operand that is an indexed or indirect from a register (it is
 249 usually better to use @samp{m} or @samp{es} in @code{asm} statements)"
 250   (match_operand 0 "indexed_or_indirect_operand"))
 251
 252 ;; Address constraints
 253
 254 (define_address_constraint "a"
 255   "Indexed or indirect address operand"
 256   (match_operand 0 "indexed_or_indirect_address"))
 257
 258 (define_constraint "R"
 259   "AIX TOC entry"
 260   (match_test "legitimate_constant_pool_address_p (op, QImode, false)"))
 261
 262 ;; General constraints
 263
 264 (define_constraint "U"
 265   "V.4 small data reference"
 266   (and (match_test "DEFAULT_ABI == ABI_V4")
 267        (match_test "small_data_operand (op, mode)")))
 268
 269 (define_constraint "W"
 270   "vector constant that does not require memory"
 271   (match_operand 0 "easy_vector_constant"))
 272
 273 (define_constraint "j"
 274   "Zero vector constant"
 275   (match_test "op == const0_rtx || op == CONST0_RTX (mode)"))