gcc/config/rs6000/constraints.md

   1 ;; Constraint definitions for RS6000
   2 ;; Copyright (C) 2006-2013 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5 ;;
   6 ;; GCC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 3, or (at your option)
   9 ;; any later version.
  10 ;;
  11 ;; GCC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19
  20 ;; Available constraint letters: "e", "k", "q", "u", "A", "B", "C", "D"
  21
  22 ;; Register constraints
  23
  24 (define_register_constraint "f" "rs6000_constraints[RS6000_CONSTRAINT_f]"
  25   "@internal")
  26
  27 (define_register_constraint "d" "rs6000_constraints[RS6000_CONSTRAINT_d]"
  28   "@internal")
  29
  30 (define_register_constraint "b" "BASE_REGS"
  31   "@internal")
  32
  33 (define_register_constraint "h" "SPECIAL_REGS"
  34   "@internal")
  35
  36 (define_register_constraint "c" "CTR_REGS"
  37   "@internal")
  38
  39 (define_register_constraint "l" "LINK_REGS"
  40   "@internal")
  41
  42 (define_register_constraint "v" "ALTIVEC_REGS"
  43   "@internal")
  44
  45 (define_register_constraint "x" "CR0_REGS"
  46   "@internal")
  47
  48 (define_register_constraint "y" "CR_REGS"
  49   "@internal")
  50
  51 (define_register_constraint "z" "CA_REGS"
  52   "@internal")
  53
  54 ;; Use w as a prefix to add VSX modes
  55 ;; any VSX register
  56 (define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]"
  57   "Any VSX register if the -mvsx option was used or NO_REGS.")
  58
  59 (define_register_constraint "wd" "rs6000_constraints[RS6000_CONSTRAINT_wd]"
  60   "VSX vector register to hold vector double data or NO_REGS.")
  61
  62 (define_register_constraint "wf" "rs6000_constraints[RS6000_CONSTRAINT_wf]"
  63   "VSX vector register to hold vector float data or NO_REGS.")
  64
  65 (define_register_constraint "wg" "rs6000_constraints[RS6000_CONSTRAINT_wg]"
  66   "If -mmfpgpr was used, a floating point register or NO_REGS.")
  67
  68 (define_register_constraint "wl" "rs6000_constraints[RS6000_CONSTRAINT_wl]"
  69   "Floating point register if the LFIWAX instruction is enabled or NO_REGS.")
  70
  71 (define_register_constraint "wm" "rs6000_constraints[RS6000_CONSTRAINT_wm]"
  72   "VSX register if direct move instructions are enabled, or NO_REGS.")
  73
  74 ;; NO_REGs register constraint, used to merge mov{sd,sf}, since movsd can use
  75 ;; direct move directly, and movsf can't to move between the register sets.
  76 ;; There is a mode_attr that resolves to wm for SDmode and wn for SFmode
  77 (define_register_constraint "wn" "NO_REGS" "No register (NO_REGS).")
  78
  79 (define_register_constraint "wr" "rs6000_constraints[RS6000_CONSTRAINT_wr]"
  80   "General purpose register if 64-bit instructions are enabled or NO_REGS.")
  81
  82 (define_register_constraint "ws" "rs6000_constraints[RS6000_CONSTRAINT_ws]"
  83   "VSX vector register to hold scalar double values or NO_REGS.")
  84
  85 (define_register_constraint "wt" "rs6000_constraints[RS6000_CONSTRAINT_wt]"
  86   "VSX vector register to hold 128 bit integer or NO_REGS.")
  87
  88 (define_register_constraint "wu" "rs6000_constraints[RS6000_CONSTRAINT_wu]"
  89   "Altivec register to use for float/32-bit int loads/stores  or NO_REGS.")
  90
  91 (define_register_constraint "wv" "rs6000_constraints[RS6000_CONSTRAINT_wv]"
  92   "Altivec register to use for double loads/stores  or NO_REGS.")
  93
  94 (define_register_constraint "ww" "rs6000_constraints[RS6000_CONSTRAINT_ww]"
  95   "FP or VSX register to perform float operations under -mvsx or NO_REGS.")
  96
  97 (define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]"
  98   "Floating point register if the STFIWX instruction is enabled or NO_REGS.")
  99
 100 (define_register_constraint "wy" "rs6000_constraints[RS6000_CONSTRAINT_wy]"
 101   "VSX vector register to hold scalar float values or NO_REGS.")
 102
 103 (define_register_constraint "wz" "rs6000_constraints[RS6000_CONSTRAINT_wz]"
 104   "Floating point register if the LFIWZX instruction is enabled or NO_REGS.")
 105
 106 ;; Lq/stq validates the address for load/store quad
 107 (define_memory_constraint "wQ"
 108   "Memory operand suitable for the load/store quad instructions"
 109   (match_operand 0 "quad_memory_operand"))
 110
 111 ;; Altivec style load/store that ignores the bottom bits of the address
 112 (define_memory_constraint "wZ"
 113   "Indexed or indirect memory operand, ignoring the bottom 4 bits"
 114   (match_operand 0 "altivec_indexed_or_indirect_operand"))
 115
 116 ;; Integer constraints
 117
 118 (define_constraint "I"
 119   "A signed 16-bit constant"
 120   (and (match_code "const_int")
 121        (match_test "(unsigned HOST_WIDE_INT) (ival + 0x8000) < 0x10000")))
 122
 123 (define_constraint "J"
 124   "high-order 16 bits nonzero"
 125   (and (match_code "const_int")
 126        (match_test "(ival & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0")))
 127
 128 (define_constraint "K"
 129   "low-order 16 bits nonzero"
 130   (and (match_code "const_int")
 131        (match_test "(ival & (~ (HOST_WIDE_INT) 0xffff)) == 0")))
 132
 133 (define_constraint "L"
 134   "signed 16-bit constant shifted left 16 bits"
 135   (and (match_code "const_int")
 136        (match_test "((ival & 0xffff) == 0
 137                       && (ival >> 31 == -1 || ival >> 31 == 0))")))
 138
 139 (define_constraint "M"
 140   "constant greater than 31"
 141   (and (match_code "const_int")
 142        (match_test "ival > 31")))
 143
 144 (define_constraint "N"
 145   "positive constant that is an exact power of two"
 146   (and (match_code "const_int")
 147        (match_test "ival > 0 && exact_log2 (ival) >= 0")))
 148
 149 (define_constraint "O"
 150   "constant zero"
 151   (and (match_code "const_int")
 152        (match_test "ival == 0")))
 153
 154 (define_constraint "P"
 155   "constant whose negation is signed 16-bit constant"
 156   (and (match_code "const_int")
 157        (match_test "(unsigned HOST_WIDE_INT) ((- ival) + 0x8000) < 0x10000")))
 158
 159 ;; Floating-point constraints
 160
 161 (define_constraint "G"
 162   "Constant that can be copied into GPR with two insns for DF/DI
 163    and one for SF."
 164   (and (match_code "const_double")
 165        (match_test "num_insns_constant (op, mode)
 166                     == (mode == SFmode ? 1 : 2)")))
 167
 168 (define_constraint "H"
 169   "DF/DI constant that takes three insns."
 170   (and (match_code "const_double")
 171        (match_test "num_insns_constant (op, mode) == 3")))
 172
 173 ;; Memory constraints
 174
 175 (define_memory_constraint "es"
 176   "A ``stable'' memory operand; that is, one which does not include any
 177 automodification of the base register.  Unlike @samp{m}, this constraint
 178 can be used in @code{asm} statements that might access the operand
 179 several times, or that might not access it at all."
 180   (and (match_code "mem")
 181        (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != RTX_AUTOINC")))
 182
 183 (define_memory_constraint "Q"
 184   "Memory operand that is an offset from a register (it is usually better
 185 to use @samp{m} or @samp{es} in @code{asm} statements)"
 186   (and (match_code "mem")
 187        (match_test "GET_CODE (XEXP (op, 0)) == REG")))
 188
 189 (define_memory_constraint "Y"
 190   "memory operand for 8 byte and 16 byte gpr load/store"
 191   (and (match_code "mem")
 192        (match_operand 0 "mem_operand_gpr")))
 193
 194 (define_memory_constraint "Z"
 195   "Memory operand that is an indexed or indirect from a register (it is
 196 usually better to use @samp{m} or @samp{es} in @code{asm} statements)"
 197   (match_operand 0 "indexed_or_indirect_operand"))
 198
 199 ;; Address constraints
 200
 201 (define_address_constraint "a"
 202   "Indexed or indirect address operand"
 203   (match_operand 0 "indexed_or_indirect_address"))
 204
 205 (define_constraint "R"
 206   "AIX TOC entry"
 207   (match_test "legitimate_constant_pool_address_p (op, QImode, false)"))
 208
 209 ;; General constraints
 210
 211 (define_constraint "S"
 212   "Constant that can be placed into a 64-bit mask operand"
 213   (match_operand 0 "mask64_operand"))
 214
 215 (define_constraint "T"
 216   "Constant that can be placed into a 32-bit mask operand"
 217   (match_operand 0 "mask_operand"))
 218
 219 (define_constraint "U"
 220   "V.4 small data reference"
 221   (and (match_test "DEFAULT_ABI == ABI_V4")
 222        (match_operand 0 "small_data_operand")))
 223
 224 (define_constraint "t"
 225   "AND masks that can be performed by two rldic{l,r} insns
 226    (but excluding those that could match other constraints of anddi3)"
 227   (and (and (and (match_operand 0 "mask64_2_operand")
 228                  (match_test "(fixed_regs[CR0_REGNO]
 229                               || !logical_operand (op, DImode))"))
 230             (not (match_operand 0 "mask_operand")))
 231        (not (match_operand 0 "mask64_operand"))))
 232
 233 (define_constraint "W"
 234   "vector constant that does not require memory"
 235   (match_operand 0 "easy_vector_constant"))
 236
 237 (define_constraint "j"
 238   "Zero vector constant"
 239   (match_test "op == const0_rtx || op == CONST0_RTX (GET_MODE (op))"))