gcc/config/rs6000/darwin.md

   1 /* Machine description patterns for PowerPC running Darwin (Mac OS X).
   2    Copyright (C) 2004 Free Software Foundation, Inc.
   3    Contributed by Apple Computer Inc.
   4
   5 This file is part of GNU CC.
   6
   7 GNU CC is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 GNU CC is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with GNU CC; see the file COPYING.  If not, write to
  19 the Free Software Foundation, 59 Temple Place - Suite 330,
  20 Boston, MA 02111-1307, USA.  */
  21
  22 (define_insn "adddi3_high"
  23   [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
  24         (plus:DI (match_operand:DI 1 "gpc_reg_operand" "b")
  25                  (high:DI (match_operand 2 "" ""))))]
  26   "TARGET_MACHO && TARGET_64BIT"
  27   "{cau|addis} %0,%1,ha16(%2)"
  28   [(set_attr "length" "4")])
  29
  30 (define_insn "movdf_low_di"
  31   [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
  32         (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
  33                            (match_operand 2 "" ""))))]
  34   "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
  35   "*
  36 {
  37   switch (which_alternative)
  38     {
  39       case 0:
  40         return \"lfd %0,lo16(%2)(%1)\";
  41       case 1:
  42         {
  43           rtx operands2[4];
  44           operands2[0] = operands[0];
  45           operands2[1] = operands[1];
  46           operands2[2] = operands[2];
  47           if (TARGET_POWERPC64 && TARGET_32BIT)
  48             /* Note, old assemblers didn't support relocation here. */
  49             return \"ld %0,lo16(%2)(%1)\";
  50           else
  51           {
  52             operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM);
  53             output_asm_insn (\"{l|ld} %0,lo16(%2)(%1)\", operands);
  54 #if TARGET_MACHO
  55             if (MACHO_DYNAMIC_NO_PIC_P)
  56               output_asm_insn (\"{liu|lis} %L0,ha16(%2+4)\", operands);
  57             else
  58             /* We cannot rely on ha16(low half)==ha16(high half), alas,
  59                although in practice it almost always is.  */
  60             output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2);
  61 #endif
  62             return (\"{l|lwz} %L0,lo16(%2+4)(%L0)\");
  63           }
  64         }
  65       default:
  66         abort();
  67     }
  68 }"
  69   [(set_attr "type" "load")
  70    (set_attr "length" "4,12")])
  71
  72 (define_insn "movdf_low_st_di"
  73   [(set (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
  74                            (match_operand 2 "" "")))
  75         (match_operand:DF 0 "gpc_reg_operand" "f"))]
  76   "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
  77   "stfd %0,lo16(%2)(%1)"
  78   [(set_attr "type" "store")
  79    (set_attr "length" "4")])
  80
  81 (define_insn "movsf_low_di"
  82   [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
  83         (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
  84                            (match_operand 2 "" ""))))]
  85   "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
  86   "@
  87    lfs %0,lo16(%2)(%1)
  88    {l|ld} %0,lo16(%2)(%1)"
  89   [(set_attr "type" "load")
  90    (set_attr "length" "4")])
  91
  92 (define_insn "movsf_low_st_di"
  93   [(set (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
  94                            (match_operand 2 "" "")))
  95         (match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
  96   "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
  97   "@
  98    stfs %0,lo16(%2)(%1)
  99    {st|stw} %0,lo16(%2)(%1)"
 100   [(set_attr "type" "store")
 101    (set_attr "length" "4")])
 102
 103 ;; 64-bit MachO load/store support
 104 (define_insn "movdi_low"
 105   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
 106         (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
 107                            (match_operand 2 "" ""))))]
 108   "TARGET_MACHO && TARGET_64BIT"
 109   "{l|ld} %0,lo16(%2)(%1)"
 110   [(set_attr "type" "load")
 111    (set_attr "length" "4")])
 112
 113 (define_insn "movdi_low_st"
 114   [(set (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
 115                            (match_operand 2 "" "")))
 116         (match_operand:DI 0 "gpc_reg_operand" "r"))]
 117   "TARGET_MACHO && TARGET_64BIT"
 118   "{st|std} %0,lo16(%2)(%1)"
 119   [(set_attr "type" "store")
 120    (set_attr "length" "4")])
 121
 122 (define_insn "macho_high_di"
 123   [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
 124         (high:DI (match_operand 1 "" "")))]
 125   "TARGET_MACHO && TARGET_64BIT"
 126   "{liu|lis} %0,ha16(%1)")
 127
 128 (define_insn "macho_low_di"
 129   [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
 130         (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
 131                    (match_operand 2 "" "")))]
 132    "TARGET_MACHO && TARGET_64BIT"
 133    "@
 134     {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
 135     {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
 136
 137 (define_split
 138   [(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand" "")
 139                          (match_operand:DI 1 "short_cint_operand" "")))
 140         (match_operand:V4SI 2 "register_operand" ""))
 141    (clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
 142   "TARGET_MACHO && TARGET_64BIT"
 143   [(set (match_dup 3) (plus:DI (match_dup 0) (match_dup 1)))
 144    (set (mem:V4SI (match_dup 3))
 145         (match_dup 2))]
 146   "")
 147
 148 (define_insn ""
 149   [(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand" "b,r")
 150                          (match_operand:DI 1 "gpc_reg_operand" "r,b")))
 151         (match_operand:V4SI 2 "register_operand" "v,v"))]
 152   "TARGET_MACHO && TARGET_64BIT"
 153   "@
 154    stvx %2,%0,%1
 155    stvx %2,%1,%0"
 156   [(set_attr "type" "vecstore")])
 157
 158 (define_insn ""
 159   [(set (mem:V4SI (match_operand:DI 0 "gpc_reg_operand" "r"))
 160         (match_operand:V4SI 1 "register_operand" "v"))]
 161   "TARGET_MACHO && TARGET_64BIT"
 162   "stvx %1,0,%0"
 163   [(set_attr "type" "vecstore")])
 164
 165 (define_split
 166   [(set (match_operand:V4SI 0 "register_operand" "")
 167         (mem:V4SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
 168                          (match_operand:DI 2 "short_cint_operand" ""))))
 169    (clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
 170   "TARGET_MACHO && TARGET_64BIT"
 171   [(set (match_dup 3) (plus:DI (match_dup 1) (match_dup 2)))
 172    (set (match_dup 0)
 173         (mem:V4SI (match_dup 3)))]
 174   "")
 175
 176 (define_insn ""
 177   [(set (match_operand:V4SI 0 "register_operand" "=v,v")
 178         (mem:V4SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "b,r")
 179                          (match_operand:DI 2 "gpc_reg_operand" "r,b"))))]
 180   "TARGET_MACHO && TARGET_64BIT"
 181   "@
 182    lvx %0,%1,%2
 183    lvx %0,%2,%1"
 184   [(set_attr "type" "vecload")])
 185
 186 (define_insn ""
 187   [(set (match_operand:V4SI 0 "register_operand" "=v")
 188         (mem:V4SI (match_operand:DI 1 "gpc_reg_operand" "r")))]
 189   "TARGET_MACHO && TARGET_64BIT"
 190   "lvx %0,0,%1"
 191   [(set_attr "type" "vecload")])
 192
 193 (define_insn "load_macho_picbase_di"
 194   [(set (match_operand:DI 0 "register_operand" "=l")
 195         (unspec:DI [(match_operand:DI 1 "immediate_operand" "s")] 15))]
 196   "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
 197   "bcl 20,31,%1\\n%1:"
 198   [(set_attr "type" "branch")
 199    (set_attr "length" "4")])
 200
 201 (define_insn "macho_correct_pic_di"
 202   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
 203         (plus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
 204                  (unspec:DI [(match_operand:DI 2 "immediate_operand" "s")
 205                              (match_operand:DI 3 "immediate_operand" "s")]
 206                             16)))]
 207   "DEFAULT_ABI == ABI_DARWIN"
 208   "addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
 209   [(set_attr "length" "8")])
 210
 211 (define_insn "*call_indirect_nonlocal_darwin64"
 212   [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l,c,*l"))
 213          (match_operand 1 "" "g,g,g,g"))
 214    (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
 215    (clobber (match_scratch:SI 3 "=l,l,l,l"))]
 216   "DEFAULT_ABI == ABI_DARWIN"
 217 {
 218   return "b%T0l";
 219 }
 220   [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
 221    (set_attr "length" "4,4,8,8")])
 222
 223 (define_insn "*call_nonlocal_darwin64"
 224   [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s,s"))
 225          (match_operand 1 "" "g,g"))
 226    (use (match_operand:SI 2 "immediate_operand" "O,n"))
 227    (clobber (match_scratch:SI 3 "=l,l"))]
 228   "(DEFAULT_ABI == ABI_DARWIN)
 229    && (INTVAL (operands[2]) & CALL_LONG) == 0"
 230 {
 231 #if TARGET_MACHO
 232   return output_call(insn, operands, 0, 2);
 233 #endif
 234 }
 235   [(set_attr "type" "branch,branch")
 236    (set_attr "length" "4,8")])
 237
 238 (define_insn "*call_value_indirect_nonlocal_darwin64"
 239   [(set (match_operand 0 "" "")
 240         (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l,c,*l"))
 241               (match_operand 2 "" "g,g,g,g")))
 242    (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
 243    (clobber (match_scratch:SI 4 "=l,l,l,l"))]
 244   "DEFAULT_ABI == ABI_DARWIN"
 245 {
 246   return "b%T1l";
 247 }
 248   [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
 249    (set_attr "length" "4,4,8,8")])
 250
 251 (define_insn "*call_value_nonlocal_darwin64"
 252   [(set (match_operand 0 "" "")
 253         (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s,s"))
 254               (match_operand 2 "" "g,g")))
 255    (use (match_operand:SI 3 "immediate_operand" "O,n"))
 256    (clobber (match_scratch:SI 4 "=l,l"))]
 257   "(DEFAULT_ABI == ABI_DARWIN)
 258    && (INTVAL (operands[3]) & CALL_LONG) == 0"
 259 {
 260 #if TARGET_MACHO
 261   return output_call(insn, operands, 1, 3);
 262 #endif
 263 }
 264   [(set_attr "type" "branch,branch")
 265    (set_attr "length" "4,8")])
 266
 267 (define_insn "*sibcall_nonlocal_darwin64"
 268   [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s,s"))
 269          (match_operand 1 "" ""))
 270    (use (match_operand 2 "immediate_operand" "O,n"))
 271    (use (match_operand:SI 3 "register_operand" "l,l"))
 272    (return)]
 273   "(DEFAULT_ABI == ABI_DARWIN)
 274    && (INTVAL (operands[2]) & CALL_LONG) == 0"
 275 {
 276   return "b %z0";
 277 }
 278   [(set_attr "type" "branch,branch")
 279    (set_attr "length" "4,8")])
 280
 281 (define_insn "*sibcall_value_nonlocal_darwin64"
 282   [(set (match_operand 0 "" "")
 283         (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s,s"))
 284               (match_operand 2 "" "")))
 285    (use (match_operand:SI 3 "immediate_operand" "O,n"))
 286    (use (match_operand:SI 4 "register_operand" "l,l"))
 287    (return)]
 288   "(DEFAULT_ABI == ABI_DARWIN)
 289    && (INTVAL (operands[3]) & CALL_LONG) == 0"
 290   "*
 291 {
 292   return \"b %z1\";
 293 }"
 294   [(set_attr "type" "branch,branch")
 295    (set_attr "length" "4,8")])
 296
 297
 298 (define_insn "*sibcall_symbolic_64"
 299   [(call (mem:SI (match_operand:DI 0 "call_operand" "s,c")) ; 64
 300          (match_operand 1 "" ""))
 301    (use (match_operand 2 "" ""))
 302    (use (match_operand:SI 3 "register_operand" "l,l"))
 303    (return)]
 304   "TARGET_64BIT && DEFAULT_ABI == ABI_DARWIN"
 305   "*
 306 {
 307   switch (which_alternative)
 308     {
 309       case 0:  return \"b %z0\";
 310       case 1:  return \"b%T0\";
 311       default:  abort();
 312     }
 313 }"
 314   [(set_attr "type" "branch")
 315    (set_attr "length" "4")])
 316
 317 (define_insn "*sibcall_value_symbolic_64"
 318   [(set (match_operand 0 "" "")
 319         (call (mem:SI (match_operand:DI 1 "call_operand" "s,c"))
 320               (match_operand 2 "" "")))
 321    (use (match_operand:SI 3 "" ""))
 322    (use (match_operand:SI 4 "register_operand" "l,l"))
 323    (return)]
 324   "TARGET_64BIT && DEFAULT_ABI == ABI_DARWIN"
 325   "*
 326 {
 327   switch (which_alternative)
 328     {
 329       case 0:  return \"b %z1\";
 330       case 1:  return \"b%T1\";
 331       default:  abort();
 332     }
 333 }"
 334   [(set_attr "type" "branch")
 335    (set_attr "length" "4")])
 336
 337 (define_insn "*save_fpregs_with_label_di"
 338  [(match_parallel 0 "any_operand"
 339                   [(clobber (match_operand:DI 1 "register_operand" "=l"))
 340                    (use (match_operand:DI 2 "call_operand" "s"))
 341                    (use (match_operand:DI 3 "" ""))
 342                    (set (match_operand:DF 4 "memory_operand" "=m")
 343                         (match_operand:DF 5 "gpc_reg_operand" "f"))])]
 344  "TARGET_64BIT"
 345  "*
 346 #if TARGET_MACHO
 347   const char *picbase = machopic_function_base_name ();
 348   operands[3] = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (picbase, -1));
 349 #endif
 350   return \"bl %z2\\n%3:\";
 351 "
 352   [(set_attr "type" "branch")
 353    (set_attr "length" "4")])
 354
 355 (define_insn "*save_vregs_di"
 356  [(match_parallel 0 "any_operand"
 357                   [(clobber (match_operand:DI 1 "register_operand" "=l"))
 358                    (use (match_operand:DI 2 "call_operand" "s"))
 359                    (set (match_operand:V4SI 3 "any_operand" "=m")
 360                         (match_operand:V4SI 4 "register_operand" "v"))])]
 361  "TARGET_64BIT"
 362  "bl %z2"
 363   [(set_attr "type" "branch")
 364    (set_attr "length" "4")])
 365
 366 (define_insn "*restore_vregs_di"
 367  [(match_parallel 0 "any_operand"
 368                   [(clobber (match_operand:DI 1 "register_operand" "=l"))
 369                    (use (match_operand:DI 2 "call_operand" "s"))
 370                    (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
 371                    (set (match_operand:V4SI 4 "register_operand" "=v")
 372                         (match_operand:V4SI 5 "any_operand" "m"))])]
 373  "TARGET_64BIT"
 374  "bl %z2")
 375
 376 (define_insn "*save_vregs_with_label_di"
 377  [(match_parallel 0 "any_operand"
 378                   [(clobber (match_operand:DI 1 "register_operand" "=l"))
 379                    (use (match_operand:DI 2 "call_operand" "s"))
 380                    (use (match_operand:DI 3 "" ""))
 381                    (set (match_operand:V4SI 4 "any_operand" "=m")
 382                         (match_operand:V4SI 5 "register_operand" "v"))])]
 383  "TARGET_64BIT"
 384  "*
 385 #if TARGET_MACHO
 386   const char *picbase = machopic_function_base_name ();
 387   operands[3] = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (picbase, -1));
 388 #endif
 389   return \"bl %z2\\n%3:\";
 390 "
 391   [(set_attr "type" "branch")
 392    (set_attr "length" "4")])