gcc/config/rs6000/darwin.md

   1 /* Machine description patterns for PowerPC running Darwin (Mac OS X).
   2    Copyright (C) 2004, 2005, 2007 Free Software Foundation, Inc.
   3    Contributed by Apple Computer Inc.
   4
   5 This file is part of GCC.
   6
   7 GNU CC is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 3, or (at your option)
  10 any later version.
  11
  12 GNU CC is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.  */
  20
  21 (define_insn "adddi3_high"
  22   [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
  23         (plus:DI (match_operand:DI 1 "gpc_reg_operand" "b")
  24                  (high:DI (match_operand 2 "" ""))))]
  25   "TARGET_MACHO && TARGET_64BIT"
  26   "{cau|addis} %0,%1,ha16(%2)"
  27   [(set_attr "length" "4")])
  28
  29 (define_insn "movdf_low_si"
  30   [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
  31         (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
  32                            (match_operand 2 "" ""))))]
  33   "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_64BIT"
  34   "*
  35 {
  36   switch (which_alternative)
  37     {
  38       case 0:
  39         return \"lfd %0,lo16(%2)(%1)\";
  40       case 1:
  41         {
  42           if (TARGET_POWERPC64 && TARGET_32BIT)
  43             /* Note, old assemblers didn't support relocation here.  */
  44             return \"ld %0,lo16(%2)(%1)\";
  45           else
  46             {
  47               output_asm_insn (\"{cal|la} %0,lo16(%2)(%1)\", operands);
  48               output_asm_insn (\"{l|lwz} %L0,4(%0)\", operands);
  49               return (\"{l|lwz} %0,0(%0)\");
  50             }
  51         }
  52       default:
  53         gcc_unreachable ();
  54     }
  55 }"
  56   [(set_attr "type" "load")
  57    (set_attr "length" "4,12")])
  58
  59
  60 (define_insn "movdf_low_di"
  61   [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
  62         (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
  63                            (match_operand 2 "" ""))))]
  64   "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
  65   "*
  66 {
  67   switch (which_alternative)
  68     {
  69       case 0:
  70         return \"lfd %0,lo16(%2)(%1)\";
  71       case 1:
  72         return \"ld %0,lo16(%2)(%1)\";
  73       default:
  74         gcc_unreachable ();
  75     }
  76 }"
  77   [(set_attr "type" "load")
  78    (set_attr "length" "4,4")])
  79
  80 (define_insn "movdf_low_st_si"
  81   [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
  82                            (match_operand 2 "" "")))
  83         (match_operand:DF 0 "gpc_reg_operand" "f"))]
  84   "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
  85   "stfd %0,lo16(%2)(%1)"
  86   [(set_attr "type" "store")
  87    (set_attr "length" "4")])
  88
  89 (define_insn "movdf_low_st_di"
  90   [(set (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
  91                            (match_operand 2 "" "")))
  92         (match_operand:DF 0 "gpc_reg_operand" "f"))]
  93   "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
  94   "stfd %0,lo16(%2)(%1)"
  95   [(set_attr "type" "store")
  96    (set_attr "length" "4")])
  97
  98 (define_insn "movsf_low_si"
  99   [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
 100         (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
 101                            (match_operand 2 "" ""))))]
 102   "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
 103   "@
 104    lfs %0,lo16(%2)(%1)
 105    {l|lwz} %0,lo16(%2)(%1)"
 106   [(set_attr "type" "load")
 107    (set_attr "length" "4")])
 108
 109 (define_insn "movsf_low_di"
 110   [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
 111         (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
 112                            (match_operand 2 "" ""))))]
 113   "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
 114   "@
 115    lfs %0,lo16(%2)(%1)
 116    {l|lwz} %0,lo16(%2)(%1)"
 117   [(set_attr "type" "load")
 118    (set_attr "length" "4")])
 119
 120 (define_insn "movsf_low_st_si"
 121   [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
 122                            (match_operand 2 "" "")))
 123         (match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
 124   "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
 125   "@
 126    stfs %0,lo16(%2)(%1)
 127    {st|stw} %0,lo16(%2)(%1)"
 128   [(set_attr "type" "store")
 129    (set_attr "length" "4")])
 130
 131 (define_insn "movsf_low_st_di"
 132   [(set (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
 133                            (match_operand 2 "" "")))
 134         (match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
 135   "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
 136   "@
 137    stfs %0,lo16(%2)(%1)
 138    {st|stw} %0,lo16(%2)(%1)"
 139   [(set_attr "type" "store")
 140    (set_attr "length" "4")])
 141
 142 ;; 64-bit MachO load/store support
 143 (define_insn "movdi_low"
 144   [(set (match_operand:DI 0 "gpc_reg_operand" "=r,*!d")
 145         (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
 146                            (match_operand 2 "" ""))))]
 147   "TARGET_MACHO && TARGET_64BIT"
 148   "@
 149    {l|ld} %0,lo16(%2)(%1)
 150    lfd %0,lo16(%2)(%1)"
 151   [(set_attr "type" "load")
 152    (set_attr "length" "4")])
 153
 154 (define_insn "movsi_low_st"
 155   [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
 156                            (match_operand 2 "" "")))
 157         (match_operand:SI 0 "gpc_reg_operand" "r"))]
 158   "TARGET_MACHO && ! TARGET_64BIT"
 159   "{st|stw} %0,lo16(%2)(%1)"
 160   [(set_attr "type" "store")
 161    (set_attr "length" "4")])
 162
 163 (define_insn "movdi_low_st"
 164   [(set (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
 165                            (match_operand 2 "" "")))
 166         (match_operand:DI 0 "gpc_reg_operand" "r,*!d"))]
 167   "TARGET_MACHO && TARGET_64BIT"
 168   "@
 169    {st|std} %0,lo16(%2)(%1)
 170    stfd %0,lo16(%2)(%1)"
 171   [(set_attr "type" "store")
 172    (set_attr "length" "4")])
 173
 174 ;; Mach-O PIC trickery.
 175 (define_expand "macho_high"
 176   [(set (match_operand 0 "" "")
 177         (high (match_operand 1 "" "")))]
 178   "TARGET_MACHO"
 179 {
 180   if (TARGET_64BIT)
 181     emit_insn (gen_macho_high_di (operands[0], operands[1]));
 182   else
 183     emit_insn (gen_macho_high_si (operands[0], operands[1]));
 184
 185   DONE;
 186 })
 187
 188 (define_insn "macho_high_si"
 189   [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
 190         (high:SI (match_operand 1 "" "")))]
 191   "TARGET_MACHO && ! TARGET_64BIT"
 192   "{liu|lis} %0,ha16(%1)")
 193
 194
 195 (define_insn "macho_high_di"
 196   [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
 197         (high:DI (match_operand 1 "" "")))]
 198   "TARGET_MACHO && TARGET_64BIT"
 199   "{liu|lis} %0,ha16(%1)")
 200
 201 (define_expand "macho_low"
 202   [(set (match_operand 0 "" "")
 203         (lo_sum (match_operand 1 "" "")
 204                    (match_operand 2 "" "")))]
 205    "TARGET_MACHO"
 206 {
 207   if (TARGET_64BIT)
 208     emit_insn (gen_macho_low_di (operands[0], operands[1], operands[2]));
 209   else
 210     emit_insn (gen_macho_low_si (operands[0], operands[1], operands[2]));
 211
 212   DONE;
 213 })
 214
 215 (define_insn "macho_low_si"
 216   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 217         (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
 218                    (match_operand 2 "" "")))]
 219    "TARGET_MACHO && ! TARGET_64BIT"
 220    "@
 221     {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
 222     {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
 223
 224 (define_insn "macho_low_di"
 225   [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
 226         (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
 227                    (match_operand 2 "" "")))]
 228    "TARGET_MACHO && TARGET_64BIT"
 229    "@
 230     {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
 231     {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
 232
 233 (define_split
 234   [(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand" "")
 235                          (match_operand:DI 1 "short_cint_operand" "")))
 236         (match_operand:V4SI 2 "register_operand" ""))
 237    (clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
 238   "TARGET_MACHO && TARGET_64BIT"
 239   [(set (match_dup 3) (plus:DI (match_dup 0) (match_dup 1)))
 240    (set (mem:V4SI (match_dup 3))
 241         (match_dup 2))]
 242   "")
 243
 244 (define_expand "load_macho_picbase"
 245   [(set (reg:SI 65)
 246         (unspec [(match_operand 0 "" "")]
 247                    UNSPEC_LD_MPIC))]
 248   "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
 249 {
 250   if (TARGET_32BIT)
 251     emit_insn (gen_load_macho_picbase_si (operands[0]));
 252   else
 253     emit_insn (gen_load_macho_picbase_di (operands[0]));
 254
 255   DONE;
 256 })
 257
 258 (define_insn "load_macho_picbase_si"
 259   [(set (reg:SI 65)
 260         (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
 261                     (pc)] UNSPEC_LD_MPIC))]
 262   "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
 263   "bcl 20,31,%0\\n%0:"
 264   [(set_attr "type" "branch")
 265    (set_attr "length" "4")])
 266
 267 (define_insn "load_macho_picbase_di"
 268   [(set (reg:DI 65)
 269         (unspec:DI [(match_operand:DI 0 "immediate_operand" "s")
 270                     (pc)] UNSPEC_LD_MPIC))]
 271   "(DEFAULT_ABI == ABI_DARWIN) && flag_pic && TARGET_64BIT"
 272   "bcl 20,31,%0\\n%0:"
 273   [(set_attr "type" "branch")
 274    (set_attr "length" "4")])
 275
 276 (define_expand "macho_correct_pic"
 277   [(set (match_operand 0 "" "")
 278         (plus (match_operand 1 "" "")
 279                  (unspec [(match_operand 2 "" "")
 280                              (match_operand 3 "" "")]
 281                             UNSPEC_MPIC_CORRECT)))]
 282   "DEFAULT_ABI == ABI_DARWIN"
 283 {
 284   if (TARGET_32BIT)
 285     emit_insn (gen_macho_correct_pic_si (operands[0], operands[1], operands[2],
 286                operands[3]));
 287   else
 288     emit_insn (gen_macho_correct_pic_di (operands[0], operands[1], operands[2],
 289                operands[3]));
 290
 291   DONE;
 292 })
 293
 294 (define_insn "macho_correct_pic_si"
 295   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 296         (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 297                  (unspec:SI [(match_operand:SI 2 "immediate_operand" "s")
 298                              (match_operand:SI 3 "immediate_operand" "s")]
 299                             UNSPEC_MPIC_CORRECT)))]
 300   "DEFAULT_ABI == ABI_DARWIN"
 301   "addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
 302   [(set_attr "length" "8")])
 303
 304 (define_insn "macho_correct_pic_di"
 305   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
 306         (plus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
 307                  (unspec:DI [(match_operand:DI 2 "immediate_operand" "s")
 308                              (match_operand:DI 3 "immediate_operand" "s")]
 309                             16)))]
 310   "DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT"
 311   "addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
 312   [(set_attr "length" "8")])
 313
 314 (define_insn "*call_indirect_nonlocal_darwin64"
 315   [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l,c,*l"))
 316          (match_operand 1 "" "g,g,g,g"))
 317    (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
 318    (clobber (reg:SI 65))]
 319   "DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT"
 320 {
 321   return "b%T0l";
 322 }
 323   [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
 324    (set_attr "length" "4,4,8,8")])
 325
 326 (define_insn "*call_nonlocal_darwin64"
 327   [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s,s"))
 328          (match_operand 1 "" "g,g"))
 329    (use (match_operand:SI 2 "immediate_operand" "O,n"))
 330    (clobber (reg:SI 65))]
 331   "(DEFAULT_ABI == ABI_DARWIN)
 332    && (INTVAL (operands[2]) & CALL_LONG) == 0"
 333 {
 334 #if TARGET_MACHO
 335   return output_call(insn, operands, 0, 2);
 336 #else
 337   gcc_unreachable ();
 338 #endif
 339 }
 340   [(set_attr "type" "branch,branch")
 341    (set_attr "length" "4,8")])
 342
 343 (define_insn "*call_value_indirect_nonlocal_darwin64"
 344   [(set (match_operand 0 "" "")
 345         (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l,c,*l"))
 346               (match_operand 2 "" "g,g,g,g")))
 347    (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
 348    (clobber (reg:SI 65))]
 349   "DEFAULT_ABI == ABI_DARWIN"
 350 {
 351   return "b%T1l";
 352 }
 353   [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
 354    (set_attr "length" "4,4,8,8")])
 355
 356 (define_insn "*call_value_nonlocal_darwin64"
 357   [(set (match_operand 0 "" "")
 358         (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s,s"))
 359               (match_operand 2 "" "g,g")))
 360    (use (match_operand:SI 3 "immediate_operand" "O,n"))
 361    (clobber (reg:SI 65))]
 362   "(DEFAULT_ABI == ABI_DARWIN)
 363    && (INTVAL (operands[3]) & CALL_LONG) == 0"
 364 {
 365 #if TARGET_MACHO
 366   return output_call(insn, operands, 1, 3);
 367 #else
 368   gcc_unreachable ();
 369 #endif
 370 }
 371   [(set_attr "type" "branch,branch")
 372    (set_attr "length" "4,8")])
 373
 374 (define_insn "*sibcall_nonlocal_darwin64"
 375   [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s,s"))
 376          (match_operand 1 "" ""))
 377    (use (match_operand 2 "immediate_operand" "O,n"))
 378    (use (reg:SI 65))
 379    (return)]
 380   "(DEFAULT_ABI == ABI_DARWIN)
 381    && (INTVAL (operands[2]) & CALL_LONG) == 0"
 382 {
 383   return "b %z0";
 384 }
 385   [(set_attr "type" "branch,branch")
 386    (set_attr "length" "4,8")])
 387
 388 (define_insn "*sibcall_value_nonlocal_darwin64"
 389   [(set (match_operand 0 "" "")
 390         (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s,s"))
 391               (match_operand 2 "" "")))
 392    (use (match_operand:SI 3 "immediate_operand" "O,n"))
 393    (use (reg:SI 65))
 394    (return)]
 395   "(DEFAULT_ABI == ABI_DARWIN)
 396    && (INTVAL (operands[3]) & CALL_LONG) == 0"
 397   "*
 398 {
 399   return \"b %z1\";
 400 }"
 401   [(set_attr "type" "branch,branch")
 402    (set_attr "length" "4,8")])
 403
 404
 405 (define_insn "*sibcall_symbolic_64"
 406   [(call (mem:SI (match_operand:DI 0 "call_operand" "s,c")) ; 64
 407          (match_operand 1 "" ""))
 408    (use (match_operand 2 "" ""))
 409    (use (reg:SI 65))
 410    (return)]
 411   "TARGET_64BIT && DEFAULT_ABI == ABI_DARWIN"
 412   "*
 413 {
 414   switch (which_alternative)
 415     {
 416       case 0:  return \"b %z0\";
 417       case 1:  return \"b%T0\";
 418       default:  gcc_unreachable ();
 419     }
 420 }"
 421   [(set_attr "type" "branch")
 422    (set_attr "length" "4")])
 423
 424 (define_insn "*sibcall_value_symbolic_64"
 425   [(set (match_operand 0 "" "")
 426         (call (mem:SI (match_operand:DI 1 "call_operand" "s,c"))
 427               (match_operand 2 "" "")))
 428    (use (match_operand:SI 3 "" ""))
 429    (use (reg:SI 65))
 430    (return)]
 431   "TARGET_64BIT && DEFAULT_ABI == ABI_DARWIN"
 432   "*
 433 {
 434   switch (which_alternative)
 435     {
 436       case 0:  return \"b %z1\";
 437       case 1:  return \"b%T1\";
 438       default:  gcc_unreachable ();
 439     }
 440 }"
 441   [(set_attr "type" "branch")
 442    (set_attr "length" "4")])