gcc/config/rs6000/mpc.md

   1 ;; Scheduling description for Motorola PowerPC processor cores.
   2 ;;   Copyright (C) 2003, 2004 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5 ;;
   6 ;; GCC is free software; you can redistribute it and/or modify it
   7 ;; under the terms of the GNU General Public License as published
   8 ;; by the Free Software Foundation; either version 2, or (at your
   9 ;; option) any later version.
  10 ;;
  11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14 ;; License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING.  If not, write to the
  18 ;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  19 ;; MA 02110-1301, USA.
  20
  21 (define_automaton "mpc,mpcfp")
  22 (define_cpu_unit "iu_mpc,mciu_mpc" "mpc")
  23 (define_cpu_unit "fpu_mpc" "mpcfp")
  24 (define_cpu_unit "lsu_mpc,bpu_mpc" "mpc")
  25
  26 ;; MPCCORE 32-bit SCIU, MCIU, LSU, FPU, BPU
  27 ;; 505/801/821/823
  28
  29 (define_insn_reservation "mpccore-load" 2
  30   (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
  31        (eq_attr "cpu" "mpccore"))
  32   "lsu_mpc")
  33
  34 (define_insn_reservation "mpccore-store" 1
  35   (and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
  36        (eq_attr "cpu" "mpccore"))
  37   "lsu_mpc")
  38
  39 (define_insn_reservation "mpccore-fpload" 2
  40   (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
  41        (eq_attr "cpu" "mpccore"))
  42   "lsu_mpc")
  43
  44 (define_insn_reservation "mpccore-integer" 1
  45   (and (eq_attr "type" "integer,insert_word")
  46        (eq_attr "cpu" "mpccore"))
  47   "iu_mpc")
  48
  49 (define_insn_reservation "mpccore-two" 1
  50   (and (eq_attr "type" "two")
  51        (eq_attr "cpu" "mpccore"))
  52   "iu_mpc,iu_mpc")
  53
  54 (define_insn_reservation "mpccore-three" 1
  55   (and (eq_attr "type" "three")
  56        (eq_attr "cpu" "mpccore"))
  57   "iu_mpc,iu_mpc,iu_mpc")
  58
  59 (define_insn_reservation "mpccore-imul" 2
  60   (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
  61        (eq_attr "cpu" "mpccore"))
  62   "mciu_mpc")
  63
  64 ; Divide latency varies greatly from 2-11, use 6 as average
  65 (define_insn_reservation "mpccore-idiv" 6
  66   (and (eq_attr "type" "idiv")
  67        (eq_attr "cpu" "mpccore"))
  68   "mciu_mpc*6")
  69
  70 (define_insn_reservation "mpccore-compare" 3
  71   (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare")
  72        (eq_attr "cpu" "mpccore"))
  73   "iu_mpc,nothing,bpu_mpc")
  74
  75 (define_insn_reservation "mpccore-fpcompare" 2
  76   (and (eq_attr "type" "fpcompare")
  77        (eq_attr "cpu" "mpccore"))
  78   "fpu_mpc,bpu_mpc")
  79
  80 (define_insn_reservation "mpccore-fp" 4
  81   (and (eq_attr "type" "fp")
  82        (eq_attr "cpu" "mpccore"))
  83   "fpu_mpc*2")
  84
  85 (define_insn_reservation "mpccore-dmul" 5
  86   (and (eq_attr "type" "dmul")
  87        (eq_attr "cpu" "mpccore"))
  88   "fpu_mpc*5")
  89
  90 (define_insn_reservation "mpccore-sdiv" 10
  91   (and (eq_attr "type" "sdiv")
  92        (eq_attr "cpu" "mpccore"))
  93   "fpu_mpc*10")
  94
  95 (define_insn_reservation "mpccore-ddiv" 17
  96   (and (eq_attr "type" "ddiv")
  97        (eq_attr "cpu" "mpccore"))
  98   "fpu_mpc*17")
  99
 100 (define_insn_reservation "mpccore-mtjmpr" 4
 101   (and (eq_attr "type" "mtjmpr,mfjmpr")
 102        (eq_attr "cpu" "mpccore"))
 103   "bpu_mpc")
 104
 105 (define_insn_reservation "mpccore-jmpreg" 1
 106   (and (eq_attr "type" "jmpreg,branch,cr_logical,delayed_cr,mfcr,mtcr")
 107        (eq_attr "cpu" "mpccore"))
 108   "bpu_mpc")
 109