gcc/config/rs6000/mpc.md

   1 ;; Scheduling description for Motorola PowerPC processor cores.
   2 ;;   Copyright (C) 2003-2014 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5 ;;
   6 ;; GCC is free software; you can redistribute it and/or modify it
   7 ;; under the terms of the GNU General Public License as published
   8 ;; by the Free Software Foundation; either version 3, or (at your
   9 ;; option) any later version.
  10 ;;
  11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14 ;; License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19
  20 (define_automaton "mpc,mpcfp")
  21 (define_cpu_unit "iu_mpc,mciu_mpc" "mpc")
  22 (define_cpu_unit "fpu_mpc" "mpcfp")
  23 (define_cpu_unit "lsu_mpc,bpu_mpc" "mpc")
  24
  25 ;; MPCCORE 32-bit SCIU, MCIU, LSU, FPU, BPU
  26 ;; 505/801/821/823
  27
  28 (define_insn_reservation "mpccore-load" 2
  29   (and (eq_attr "type" "load,load_l,store_c,sync")
  30        (eq_attr "cpu" "mpccore"))
  31   "lsu_mpc")
  32
  33 (define_insn_reservation "mpccore-store" 2
  34   (and (eq_attr "type" "store,fpstore")
  35        (eq_attr "cpu" "mpccore"))
  36   "lsu_mpc")
  37
  38 (define_insn_reservation "mpccore-fpload" 2
  39   (and (eq_attr "type" "fpload")
  40        (eq_attr "cpu" "mpccore"))
  41   "lsu_mpc")
  42
  43 (define_insn_reservation "mpccore-integer" 1
  44   (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
  45                         var_shift_rotate,cntlz,exts,isel")
  46        (eq_attr "cpu" "mpccore"))
  47   "iu_mpc")
  48
  49 (define_insn_reservation "mpccore-two" 1
  50   (and (eq_attr "type" "two")
  51        (eq_attr "cpu" "mpccore"))
  52   "iu_mpc,iu_mpc")
  53
  54 (define_insn_reservation "mpccore-three" 1
  55   (and (eq_attr "type" "three")
  56        (eq_attr "cpu" "mpccore"))
  57   "iu_mpc,iu_mpc,iu_mpc")
  58
  59 (define_insn_reservation "mpccore-imul" 2
  60   (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
  61        (eq_attr "cpu" "mpccore"))
  62   "mciu_mpc")
  63
  64 ; Divide latency varies greatly from 2-11, use 6 as average
  65 (define_insn_reservation "mpccore-idiv" 6
  66   (and (eq_attr "type" "idiv")
  67        (eq_attr "cpu" "mpccore"))
  68   "mciu_mpc*6")
  69
  70 (define_insn_reservation "mpccore-compare" 3
  71   (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
  72                         var_delayed_compare")
  73        (eq_attr "cpu" "mpccore"))
  74   "iu_mpc,nothing,bpu_mpc")
  75
  76 (define_insn_reservation "mpccore-fpcompare" 2
  77   (and (eq_attr "type" "fpcompare")
  78        (eq_attr "cpu" "mpccore"))
  79   "fpu_mpc,bpu_mpc")
  80
  81 (define_insn_reservation "mpccore-fp" 4
  82   (and (eq_attr "type" "fp")
  83        (eq_attr "cpu" "mpccore"))
  84   "fpu_mpc*2")
  85
  86 (define_insn_reservation "mpccore-dmul" 5
  87   (and (eq_attr "type" "dmul")
  88        (eq_attr "cpu" "mpccore"))
  89   "fpu_mpc*5")
  90
  91 (define_insn_reservation "mpccore-sdiv" 10
  92   (and (eq_attr "type" "sdiv")
  93        (eq_attr "cpu" "mpccore"))
  94   "fpu_mpc*10")
  95
  96 (define_insn_reservation "mpccore-ddiv" 17
  97   (and (eq_attr "type" "ddiv")
  98        (eq_attr "cpu" "mpccore"))
  99   "fpu_mpc*17")
 100
 101 (define_insn_reservation "mpccore-mtjmpr" 4
 102   (and (eq_attr "type" "mtjmpr,mfjmpr")
 103        (eq_attr "cpu" "mpccore"))
 104   "bpu_mpc")
 105
 106 (define_insn_reservation "mpccore-jmpreg" 1
 107   (and (eq_attr "type" "jmpreg,branch,cr_logical,delayed_cr,mfcr,mtcr,isync")
 108        (eq_attr "cpu" "mpccore"))
 109   "bpu_mpc")
 110