gcc/config/rs6000/power4.md

   1 ;; Scheduling description for IBM Power4 and PowerPC 970 processors.
   2 ;;   Copyright (C) 2003-2014 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5 ;;
   6 ;; GCC is free software; you can redistribute it and/or modify it
   7 ;; under the terms of the GNU General Public License as published
   8 ;; by the Free Software Foundation; either version 3, or (at your
   9 ;; option) any later version.
  10 ;;
  11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14 ;; License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19
  20 ;; Sources: IBM Red Book and White Paper on POWER4
  21
  22 ;; The POWER4 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip).
  23 ;; Instructions that update more than one register get broken into two
  24 ;; (split) or more internal ops.  The chip can issue up to 5
  25 ;; internal ops per cycle.
  26
  27 (define_automaton "power4iu,power4fpu,power4vec,power4misc")
  28
  29 (define_cpu_unit "iu1_power4,iu2_power4" "power4iu")
  30 (define_cpu_unit "lsu1_power4,lsu2_power4" "power4misc")
  31 (define_cpu_unit "fpu1_power4,fpu2_power4" "power4fpu")
  32 (define_cpu_unit "bpu_power4,cru_power4" "power4misc")
  33 (define_cpu_unit "vec_power4,vecperm_power4" "power4vec")
  34 (define_cpu_unit "du1_power4,du2_power4,du3_power4,du4_power4,du5_power4"
  35                  "power4misc")
  36
  37 (define_reservation "lsq_power4"
  38                     "(du1_power4,lsu1_power4)\
  39                     |(du2_power4,lsu2_power4)\
  40                     |(du3_power4,lsu2_power4)\
  41                     |(du4_power4,lsu1_power4)")
  42
  43 (define_reservation "lsuq_power4"
  44                     "((du1_power4+du2_power4,lsu1_power4)\
  45                       |(du2_power4+du3_power4,lsu2_power4)\
  46                       |(du3_power4+du4_power4,lsu2_power4))\
  47                      +(nothing,iu2_power4|nothing,iu1_power4)")
  48
  49 (define_reservation "iq_power4"
  50                     "(du1_power4|du2_power4|du3_power4|du4_power4),\
  51                      (iu1_power4|iu2_power4)")
  52
  53 (define_reservation "fpq_power4"
  54                     "(du1_power4|du2_power4|du3_power4|du4_power4),\
  55                      (fpu1_power4|fpu2_power4)")
  56
  57 (define_reservation "vq_power4"
  58                     "(du1_power4,vec_power4)\
  59                     |(du2_power4,vec_power4)\
  60                     |(du3_power4,vec_power4)\
  61                     |(du4_power4,vec_power4)")
  62
  63 (define_reservation "vpq_power4"
  64                     "(du1_power4,vecperm_power4)\
  65                     |(du2_power4,vecperm_power4)\
  66                     |(du3_power4,vecperm_power4)\
  67                     |(du4_power4,vecperm_power4)")
  68
  69
  70 ; Dispatch slots are allocated in order conforming to program order.
  71 (absence_set "du1_power4" "du2_power4,du3_power4,du4_power4,du5_power4")
  72 (absence_set "du2_power4" "du3_power4,du4_power4,du5_power4")
  73 (absence_set "du3_power4" "du4_power4,du5_power4")
  74 (absence_set "du4_power4" "du5_power4")
  75
  76
  77 ; Load/store
  78 (define_insn_reservation "power4-load" 4 ; 3
  79   (and (eq_attr "type" "load")
  80        (eq_attr "sign_extend" "no")
  81        (eq_attr "update" "no")
  82        (eq_attr "cpu" "power4"))
  83   "lsq_power4")
  84
  85 (define_insn_reservation "power4-load-ext" 5
  86   (and (eq_attr "type" "load")
  87        (eq_attr "sign_extend" "yes")
  88        (eq_attr "update" "no")
  89        (eq_attr "cpu" "power4"))
  90   "(du1_power4+du2_power4,lsu1_power4\
  91     |du2_power4+du3_power4,lsu2_power4\
  92     |du3_power4+du4_power4,lsu2_power4),\
  93    nothing,nothing,\
  94    (iu2_power4|iu1_power4)")
  95
  96 (define_insn_reservation "power4-load-ext-update" 5
  97   (and (eq_attr "type" "load")
  98        (eq_attr "sign_extend" "yes")
  99        (eq_attr "update" "yes")
 100        (eq_attr "indexed" "no")
 101        (eq_attr "cpu" "power4"))
 102   "du1_power4+du2_power4+du3_power4+du4_power4,\
 103    lsu1_power4+iu2_power4,nothing,nothing,iu2_power4")
 104
 105 (define_insn_reservation "power4-load-ext-update-indexed" 5
 106   (and (eq_attr "type" "load")
 107        (eq_attr "sign_extend" "yes")
 108        (eq_attr "update" "yes")
 109        (eq_attr "indexed" "yes")
 110        (eq_attr "cpu" "power4"))
 111   "du1_power4+du2_power4+du3_power4+du4_power4,\
 112    iu1_power4,lsu2_power4+iu1_power4,nothing,nothing,iu2_power4")
 113
 114 (define_insn_reservation "power4-load-update-indexed" 3
 115   (and (eq_attr "type" "load")
 116        (eq_attr "sign_extend" "no")
 117        (eq_attr "update" "yes")
 118        (eq_attr "indexed" "yes")
 119        (eq_attr "cpu" "power4"))
 120   "du1_power4+du2_power4+du3_power4+du4_power4,\
 121    iu1_power4,lsu2_power4+iu2_power4")
 122
 123 (define_insn_reservation "power4-load-update" 4 ; 3
 124   (and (eq_attr "type" "load")
 125        (eq_attr "sign_extend" "no")
 126        (eq_attr "update" "yes")
 127        (eq_attr "indexed" "no")
 128        (eq_attr "cpu" "power4"))
 129   "lsuq_power4")
 130
 131 (define_insn_reservation "power4-fpload" 6 ; 5
 132   (and (eq_attr "type" "fpload")
 133        (eq_attr "update" "no")
 134        (eq_attr "cpu" "power4"))
 135   "lsq_power4")
 136
 137 (define_insn_reservation "power4-fpload-update" 6 ; 5
 138   (and (eq_attr "type" "fpload")
 139        (eq_attr "update" "yes")
 140        (eq_attr "cpu" "power4"))
 141   "lsuq_power4")
 142
 143 (define_insn_reservation "power4-vecload" 6 ; 5
 144   (and (eq_attr "type" "vecload")
 145        (eq_attr "cpu" "power4"))
 146   "lsq_power4")
 147
 148 (define_insn_reservation "power4-store" 12
 149   (and (eq_attr "type" "store")
 150        (eq_attr "update" "no")
 151        (eq_attr "cpu" "power4"))
 152   "((du1_power4,lsu1_power4)\
 153     |(du2_power4,lsu2_power4)\
 154     |(du3_power4,lsu2_power4)\
 155     |(du4_power4,lsu1_power4)),\
 156    (iu1_power4|iu2_power4)")
 157
 158 (define_insn_reservation "power4-store-update" 12
 159   (and (eq_attr "type" "store")
 160        (eq_attr "update" "yes")
 161        (eq_attr "indexed" "no")
 162        (eq_attr "cpu" "power4"))
 163   "((du1_power4+du2_power4,lsu1_power4)\
 164     |(du2_power4+du3_power4,lsu2_power4)\
 165     |(du3_power4+du4_power4,lsu2_power4))+\
 166    ((nothing,iu1_power4,iu2_power4)\
 167     |(nothing,iu2_power4,iu2_power4)\
 168     |(nothing,iu2_power4,iu1_power4))")
 169
 170 (define_insn_reservation "power4-store-update-indexed" 12
 171   (and (eq_attr "type" "store")
 172        (eq_attr "update" "yes")
 173        (eq_attr "indexed" "yes")
 174        (eq_attr "cpu" "power4"))
 175    "du1_power4+du2_power4+du3_power4+du4_power4,\
 176     iu1_power4,lsu2_power4+iu2_power4,iu2_power4")
 177
 178 (define_insn_reservation "power4-fpstore" 12
 179   (and (eq_attr "type" "fpstore")
 180        (eq_attr "update" "no")
 181        (eq_attr "cpu" "power4"))
 182   "((du1_power4,lsu1_power4)\
 183     |(du2_power4,lsu2_power4)\
 184     |(du3_power4,lsu2_power4)\
 185     |(du4_power4,lsu1_power4)),\
 186    (fpu1_power4|fpu2_power4)")
 187
 188 (define_insn_reservation "power4-fpstore-update" 12
 189   (and (eq_attr "type" "fpstore")
 190        (eq_attr "update" "yes")
 191        (eq_attr "cpu" "power4"))
 192   "((du1_power4+du2_power4,lsu1_power4)\
 193     |(du2_power4+du3_power4,lsu2_power4)\
 194     |(du3_power4+du4_power4,lsu2_power4))\
 195    +(nothing,(iu1_power4|iu2_power4),(fpu1_power4|fpu2_power4))")
 196
 197 (define_insn_reservation "power4-vecstore" 12
 198   (and (eq_attr "type" "vecstore")
 199        (eq_attr "cpu" "power4"))
 200   "(du1_power4,lsu1_power4,vec_power4)\
 201   |(du2_power4,lsu2_power4,vec_power4)\
 202   |(du3_power4,lsu2_power4,vec_power4)\
 203   |(du4_power4,lsu1_power4,vec_power4)")
 204
 205 (define_insn_reservation "power4-llsc" 11
 206   (and (eq_attr "type" "load_l,store_c,sync")
 207        (eq_attr "cpu" "power4"))
 208   "du1_power4+du2_power4+du3_power4+du4_power4,lsu1_power4")
 209
 210
 211 ; Integer latency is 2 cycles
 212 (define_insn_reservation "power4-integer" 2
 213   (and (ior (eq_attr "type" "integer,trap,cntlz,exts,isel")
 214             (and (eq_attr "type" "add,shift")
 215                  (eq_attr "dot" "no"))
 216             (and (eq_attr "type" "insert")
 217                  (eq_attr "size" "64")))
 218        (eq_attr "cpu" "power4"))
 219   "iq_power4")
 220
 221 (define_insn_reservation "power4-two" 2
 222   (and (eq_attr "type" "two")
 223        (eq_attr "cpu" "power4"))
 224   "((du1_power4+du2_power4)\
 225     |(du2_power4+du3_power4)\
 226     |(du3_power4+du4_power4)\
 227     |(du4_power4+du1_power4)),\
 228     ((iu1_power4,nothing,iu2_power4)\
 229      |(iu2_power4,nothing,iu2_power4)\
 230      |(iu2_power4,nothing,iu1_power4)\
 231      |(iu1_power4,nothing,iu1_power4))")
 232
 233 (define_insn_reservation "power4-three" 2
 234   (and (eq_attr "type" "three")
 235        (eq_attr "cpu" "power4"))
 236   "(du1_power4+du2_power4+du3_power4|du2_power4+du3_power4+du4_power4\
 237     |du3_power4+du4_power4+du1_power4|du4_power4+du1_power4+du2_power4),\
 238    ((iu1_power4,nothing,iu2_power4,nothing,iu2_power4)\
 239     |(iu2_power4,nothing,iu2_power4,nothing,iu1_power4)\
 240     |(iu2_power4,nothing,iu1_power4,nothing,iu1_power4)\
 241     |(iu1_power4,nothing,iu1_power4,nothing,iu2_power4))")
 242
 243 (define_insn_reservation "power4-insert" 4
 244   (and (eq_attr "type" "insert")
 245        (eq_attr "size" "32")
 246        (eq_attr "cpu" "power4"))
 247   "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
 248    ((iu1_power4,nothing,iu2_power4)\
 249     |(iu2_power4,nothing,iu2_power4)\
 250     |(iu2_power4,nothing,iu1_power4))")
 251
 252 (define_insn_reservation "power4-cmp" 3
 253   (and (ior (eq_attr "type" "cmp,fast_compare")
 254             (and (eq_attr "type" "add")
 255                  (eq_attr "dot" "yes")))
 256        (eq_attr "cpu" "power4"))
 257   "iq_power4")
 258
 259 (define_insn_reservation "power4-compare" 2
 260   (and (ior (eq_attr "type" "compare")
 261             (and (eq_attr "type" "shift")
 262                  (eq_attr "dot" "yes")))
 263        (eq_attr "cpu" "power4"))
 264   "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
 265    ((iu1_power4,iu2_power4)\
 266     |(iu2_power4,iu2_power4)\
 267     |(iu2_power4,iu1_power4))")
 268
 269 (define_bypass 4 "power4-compare" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
 270
 271 (define_insn_reservation "power4-lmul-cmp" 7
 272   (and (eq_attr "type" "mul")
 273        (eq_attr "dot" "yes")
 274        (eq_attr "size" "64")
 275        (eq_attr "cpu" "power4"))
 276   "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
 277    ((iu1_power4*6,iu2_power4)\
 278     |(iu2_power4*6,iu2_power4)\
 279     |(iu2_power4*6,iu1_power4))")
 280
 281 (define_bypass 10 "power4-lmul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
 282
 283 (define_insn_reservation "power4-imul-cmp" 5
 284   (and (eq_attr "type" "mul")
 285        (eq_attr "dot" "yes")
 286        (eq_attr "size" "32")
 287        (eq_attr "cpu" "power4"))
 288   "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
 289    ((iu1_power4*4,iu2_power4)\
 290     |(iu2_power4*4,iu2_power4)\
 291     |(iu2_power4*4,iu1_power4))")
 292
 293 (define_bypass 8 "power4-imul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
 294
 295 (define_insn_reservation "power4-lmul" 7
 296   (and (eq_attr "type" "mul")
 297        (eq_attr "dot" "no")
 298        (eq_attr "size" "64")
 299        (eq_attr "cpu" "power4"))
 300   "(du1_power4|du2_power4|du3_power4|du4_power4),\
 301    (iu1_power4*6|iu2_power4*6)")
 302
 303 (define_insn_reservation "power4-imul" 5
 304   (and (eq_attr "type" "mul")
 305        (eq_attr "dot" "no")
 306        (eq_attr "size" "32")
 307        (eq_attr "cpu" "power4"))
 308   "(du1_power4|du2_power4|du3_power4|du4_power4),\
 309    (iu1_power4*4|iu2_power4*4)")
 310
 311 (define_insn_reservation "power4-imul3" 4
 312   (and (eq_attr "type" "mul")
 313        (eq_attr "size" "8,16")
 314        (eq_attr "cpu" "power4"))
 315   "(du1_power4|du2_power4|du3_power4|du4_power4),\
 316    (iu1_power4*3|iu2_power4*3)")
 317
 318
 319 ; SPR move only executes in first IU.
 320 ; Integer division only executes in second IU.
 321 (define_insn_reservation "power4-idiv" 36
 322   (and (eq_attr "type" "div")
 323        (eq_attr "size" "32")
 324        (eq_attr "cpu" "power4"))
 325   "du1_power4+du2_power4,iu2_power4*35")
 326
 327 (define_insn_reservation "power4-ldiv" 68
 328   (and (eq_attr "type" "div")
 329        (eq_attr "size" "64")
 330        (eq_attr "cpu" "power4"))
 331   "du1_power4+du2_power4,iu2_power4*67")
 332
 333
 334 (define_insn_reservation "power4-mtjmpr" 3
 335   (and (eq_attr "type" "mtjmpr,mfjmpr")
 336        (eq_attr "cpu" "power4"))
 337   "du1_power4,bpu_power4")
 338
 339
 340 ; Branches take dispatch Slot 4.  The presence_sets prevent other insn from
 341 ; grabbing previous dispatch slots once this is assigned.
 342 (define_insn_reservation "power4-branch" 2
 343   (and (eq_attr "type" "jmpreg,branch")
 344        (eq_attr "cpu" "power4"))
 345   "(du5_power4\
 346    |du4_power4+du5_power4\
 347    |du3_power4+du4_power4+du5_power4\
 348    |du2_power4+du3_power4+du4_power4+du5_power4\
 349    |du1_power4+du2_power4+du3_power4+du4_power4+du5_power4),bpu_power4")
 350
 351
 352 ; Condition Register logical ops are split if non-destructive (RT != RB)
 353 (define_insn_reservation "power4-crlogical" 2
 354   (and (eq_attr "type" "cr_logical")
 355        (eq_attr "cpu" "power4"))
 356   "du1_power4,cru_power4")
 357
 358 (define_insn_reservation "power4-delayedcr" 4
 359   (and (eq_attr "type" "delayed_cr")
 360        (eq_attr "cpu" "power4"))
 361   "du1_power4+du2_power4,cru_power4,cru_power4")
 362
 363 ; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu
 364 (define_insn_reservation "power4-mfcr" 6
 365   (and (eq_attr "type" "mfcr")
 366        (eq_attr "cpu" "power4"))
 367   "du1_power4+du2_power4+du3_power4+du4_power4,\
 368    du1_power4+du2_power4+du3_power4+du4_power4+cru_power4,\
 369    cru_power4,cru_power4,cru_power4")
 370
 371 ; mfcrf (1 field)
 372 (define_insn_reservation "power4-mfcrf" 3
 373   (and (eq_attr "type" "mfcrf")
 374        (eq_attr "cpu" "power4"))
 375   "du1_power4,cru_power4")
 376
 377 ; mtcrf (1 field)
 378 (define_insn_reservation "power4-mtcr" 4
 379   (and (eq_attr "type" "mtcr")
 380        (eq_attr "cpu" "power4"))
 381   "du1_power4,iu1_power4")
 382
 383 ; Basic FP latency is 6 cycles
 384 (define_insn_reservation "power4-fp" 6
 385   (and (eq_attr "type" "fp,dmul")
 386        (eq_attr "cpu" "power4"))
 387   "fpq_power4")
 388
 389 (define_insn_reservation "power4-fpcompare" 5
 390   (and (eq_attr "type" "fpcompare")
 391        (eq_attr "cpu" "power4"))
 392   "fpq_power4")
 393
 394 (define_insn_reservation "power4-sdiv" 33
 395   (and (eq_attr "type" "sdiv,ddiv")
 396        (eq_attr "cpu" "power4"))
 397   "(du1_power4|du2_power4|du3_power4|du4_power4),\
 398    (fpu1_power4*28|fpu2_power4*28)")
 399
 400 (define_insn_reservation "power4-sqrt" 40
 401   (and (eq_attr "type" "ssqrt,dsqrt")
 402        (eq_attr "cpu" "power4"))
 403   "(du1_power4|du2_power4|du3_power4|du4_power4),\
 404    (fpu1_power4*35|fpu2_power4*35)")
 405
 406 (define_insn_reservation "power4-isync" 2
 407   (and (eq_attr "type" "isync")
 408        (eq_attr "cpu" "power4"))
 409   "du1_power4+du2_power4+du3_power4+du4_power4,lsu1_power4")
 410
 411
 412 ; VMX
 413 (define_insn_reservation "power4-vecsimple" 2
 414   (and (eq_attr "type" "vecsimple")
 415        (eq_attr "cpu" "power4"))
 416   "vq_power4")
 417
 418 (define_insn_reservation "power4-veccomplex" 5
 419   (and (eq_attr "type" "veccomplex")
 420        (eq_attr "cpu" "power4"))
 421   "vq_power4")
 422
 423 ; vecfp compare
 424 (define_insn_reservation "power4-veccmp" 8
 425   (and (eq_attr "type" "veccmp")
 426        (eq_attr "cpu" "power4"))
 427   "vq_power4")
 428
 429 (define_insn_reservation "power4-vecfloat" 8
 430   (and (eq_attr "type" "vecfloat")
 431        (eq_attr "cpu" "power4"))
 432   "vq_power4")
 433
 434 (define_insn_reservation "power4-vecperm" 2
 435   (and (eq_attr "type" "vecperm")
 436        (eq_attr "cpu" "power4"))
 437   "vpq_power4")
 438
 439 (define_bypass 4 "power4-vecload" "power4-vecperm")
 440
 441 (define_bypass 3 "power4-vecsimple" "power4-vecperm")
 442 (define_bypass 6 "power4-veccomplex" "power4-vecperm")
 443 (define_bypass 3 "power4-vecperm"
 444                  "power4-vecsimple,power4-veccomplex,power4-vecfloat")
 445 (define_bypass 9 "power4-vecfloat" "power4-vecperm")
 446
 447 (define_bypass 5 "power4-vecsimple,power4-veccomplex"
 448                  "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
 449
 450 (define_bypass 4 "power4-vecsimple,power4-vecperm" "power4-vecstore")
 451 (define_bypass 7 "power4-veccomplex" "power4-vecstore")
 452 (define_bypass 10 "power4-vecfloat" "power4-vecstore")