gcc/config/rs6000/power4.md

   1 ;; Scheduling description for IBM Power4 and PowerPC 970 processors.
   2 ;;   Copyright (C) 2003 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GNU CC.
   5 ;;
   6 ;; GNU CC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 2, or (at your option)
   9 ;; any later version.
  10 ;;
  11 ;; GNU CC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GNU CC; see the file COPYING.  If not, write to
  18 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
  19 ;; Boston, MA 02111-1307, USA.
  20
  21 ;; Sources: IBM Red Book and White Paper on POWER4
  22
  23 ;; The POWER4 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip).
  24 ;; Instructions that update more than one register get broken into two
  25 ;; (split) or more internal ops.  The chip can issue up to 5
  26 ;; internal ops per cycle.
  27
  28 (define_automaton "power4iu,power4lsu,power4fpu,power4misc,power4vec,power4disp")
  29
  30 (define_cpu_unit "iu1_power4,iu2_power4" "power4iu")
  31 (define_cpu_unit "lsu1_power4,lsu2_power4" "power4lsu")
  32 (define_cpu_unit "fpu1_power4,fpu2_power4" "power4fpu")
  33 (define_cpu_unit "bpu_power4,cru_power4" "power4misc")
  34 (define_cpu_unit "vec_power4,vecperm_power4" "power4vec")
  35 (define_cpu_unit "du1_power4,du2_power4,du3_power4,du4_power4,du5_power4"
  36                  "power4disp")
  37
  38 (define_reservation "q1_power4" "du1_power4|du4_power4")
  39 (define_reservation "q2_power4" "du2_power4|du3_power4")
  40 (define_reservation "q4_power4" "du1_power4|du2_power4|du3_power4|du4_power4")
  41
  42 (define_reservation "lsq_power4" "(q1_power4,lsu1_power4)\
  43                                  |(q2_power4,lsu2_power4)\
  44                                  |(du3_power4,nothing,lsu2_power4)\
  45                                  |(du4_power4,nothing,lsu1_power4)")
  46
  47 (define_reservation "lsuq_power4"
  48                     "((du1_power4+du2_power4),lsu1_power4+iu2_power4)\
  49                     |((du2_power4+du3_power4),lsu2_power4+iu2_power4)\
  50                     |((du3_power4+du4_power4),lsu2_power4+iu1_power4)")
  51 ;;;                 |((du2_power4+du3_power4),lsu2_power4,iu2_power4)
  52
  53 (define_reservation "lsuxq_power4"
  54                     "(du1_power4+du2_power4+du3_power4+du4_power4),\
  55                      iu1_power4,(lsu2_power4+iu2_power4)")
  56
  57 (define_reservation "iq_power4" "(q1_power4,iu1_power4)\
  58                                 |(q2_power4,iu2_power4)\
  59                                 |(du3_power4,nothing,iu2_power4)\
  60                                 |(du4_power4,nothing,iu1_power4)")
  61
  62 (define_reservation "fpq_power4" "(q1_power4,fpu1_power4)\
  63                                  |(q2_power4,fpu2_power4)\
  64                                  |(du3_power4,nothing,fpu2_power4)\
  65                                  |(du4_power4,nothing,fpu1_power4)")
  66
  67 (define_reservation "vq_power4"
  68                     "(q4_power4,vec_power4)|(q4_power4,nothing,vec_power4)")
  69 (define_reservation "vpq_power4"
  70                     "(q4_power4,vecperm_power4)\
  71                     |(q4_power4,nothing,vecperm_power4)")
  72
  73
  74 ; Dispatch slots are allocated in order conforming to program order.
  75 (absence_set "du1_power4" "du2_power4,du3_power4,du4_power4,du5_power4")
  76 (absence_set "du2_power4" "du3_power4,du4_power4,du5_power4")
  77 (absence_set "du3_power4" "du4_power4,du5_power4")
  78 (absence_set "du4_power4" "du5_power4")
  79
  80
  81 ; Load/store
  82 (define_insn_reservation "power4-load" 3
  83   (and (eq_attr "type" "load")
  84        (eq_attr "cpu" "power4"))
  85   "lsq_power4")
  86
  87 (define_insn_reservation "power4-load-ext" 5
  88   (and (eq_attr "type" "load_ext")
  89        (eq_attr "cpu" "power4"))
  90   "((du1_power4+du2_power4),lsu1_power4,nothing,nothing,iu2_power4)\
  91   |((du2_power4+du3_power4),lsu2_power4,nothing,nothing,iu2_power4)\
  92   |((du3_power4+du4_power4),lsu2_power4,nothing,nothing,iu1_power4)")
  93
  94 (define_insn_reservation "power4-load-ext-update" 5
  95   (and (eq_attr "type" "load_ext_u")
  96        (eq_attr "cpu" "power4"))
  97   "(du1_power4+du2_power4+du3_power4+du4_power4),\
  98    (lsu1_power4+iu2_power4),nothing,nothing,iu2_power4")
  99
 100 (define_insn_reservation "power4-load-ext-update-indexed" 5
 101   (and (eq_attr "type" "load_ext_ux")
 102        (eq_attr "cpu" "power4"))
 103   "(du1_power4+du2_power4+du3_power4+du4_power4),\
 104    iu1_power4,(lsu2_power4+iu1_power4),nothing,nothing,iu2_power4")
 105
 106 (define_insn_reservation "power4-load-update-indexed" 3
 107   (and (eq_attr "type" "load_ux")
 108        (eq_attr "cpu" "power4"))
 109   "lsuxq_power4")
 110
 111 (define_insn_reservation "power4-load-update" 3
 112   (and (eq_attr "type" "load_u")
 113        (eq_attr "cpu" "power4"))
 114   "lsuq_power4")
 115
 116 (define_insn_reservation "power4-fpload" 5
 117   (and (eq_attr "type" "fpload")
 118        (eq_attr "cpu" "power4"))
 119   "lsq_power4")
 120
 121 (define_insn_reservation "power4-fpload-update" 5
 122   (and (eq_attr "type" "fpload_u")
 123        (eq_attr "cpu" "power4"))
 124   "lsuq_power4")
 125
 126 (define_insn_reservation "power4-fpload-update-indexed" 5
 127   (and (eq_attr "type" "fpload_ux")
 128        (eq_attr "cpu" "power4"))
 129   "lsuxq_power4")
 130
 131 (define_insn_reservation "power4-vecload" 5
 132   (and (eq_attr "type" "vecload")
 133        (eq_attr "cpu" "power4"))
 134   "lsq_power4")
 135
 136 (define_insn_reservation "power4-store" 1
 137   (and (eq_attr "type" "store")
 138        (eq_attr "cpu" "power4"))
 139   "(q1_power4,lsu1_power4,iu1_power4)\
 140   |(q2_power4,lsu2_power4,iu2_power4)")
 141
 142 (define_insn_reservation "power4-store-update" 1
 143   (and (eq_attr "type" "store_u")
 144        (eq_attr "cpu" "power4"))
 145   "lsuq_power4")
 146
 147 (define_insn_reservation "power4-store-update-indexed" 1
 148   (and (eq_attr "type" "store_ux")
 149        (eq_attr "cpu" "power4"))
 150   "lsuxq_power4")
 151
 152 (define_insn_reservation "power4-fpstore" 1
 153   (and (eq_attr "type" "fpstore")
 154        (eq_attr "cpu" "power4"))
 155   "(q1_power4,lsu1_power4,fpu1_power4)\
 156   |(q2_power4,lsu2_power4,fpu2_power4)")
 157
 158 (define_insn_reservation "power4-fpstore-update" 1
 159   (and (eq_attr "type" "fpstore_u")
 160        (eq_attr "cpu" "power4"))
 161   "((du1_power4+du2_power4),(fpu1_power4+iu2_power4),lsu1_power4)\
 162   |((du2_power4+du3_power4),(fpu2_power4+iu2_power4),lsu2_power4)\
 163   |((du3_power4+du4_power4),(fpu2_power4+iu1_power4),lsu2_power4)")
 164 ;;;((du2_power4+du3_power4),fpu2_power4,(iu2_power4+lsu2_power4))
 165
 166 (define_insn_reservation "power4-fpstore-update-indexed" 1
 167   (and (eq_attr "type" "fpstore_ux")
 168        (eq_attr "cpu" "power4"))
 169   "(du1_power4+du2_power4+du3_power4+du4_power4),
 170    iu1_power4,fpu2_power4,(iu2_power4+lsu2_power4)")
 171
 172 (define_insn_reservation "power4-vecstore" 1
 173   (and (eq_attr "type" "vecstore")
 174        (eq_attr "cpu" "power4"))
 175   "(q1_power4,lsu1_power4,vec_power4)\
 176   |(q2_power4,lsu2_power4,vec_power4)")
 177
 178
 179 ; Integer latency is 2 cycles
 180 (define_insn_reservation "power4-integer" 2
 181   (and (eq_attr "type" "integer")
 182        (eq_attr "cpu" "power4"))
 183   "iq_power4")
 184
 185 (define_insn_reservation "power4-cmp" 3
 186   (and (eq_attr "type" "cmp,fast_compare")
 187        (eq_attr "cpu" "power4"))
 188   "iq_power4")
 189
 190 (define_insn_reservation "power4-compare" 4
 191   (and (eq_attr "type" "compare,delayed_compare")
 192        (eq_attr "cpu" "power4"))
 193   "((du1_power4+du2_power4),iu1_power4,iu2_power4)\
 194   |((du2_power4+du3_power4),iu2_power4,iu2_power4)\
 195   |((du3_power4+du4_power4),iu2_power4,iu1_power4)")
 196
 197 (define_bypass 2 "power4-compare" "power4-integer")
 198
 199 (define_insn_reservation "power4-imul" 7
 200   (and (eq_attr "type" "imul,lmul")
 201        (eq_attr "cpu" "power4"))
 202   "(q1_power4,iu1_power4*6)|(q2_power4,iu2_power4*6)")
 203
 204 (define_insn_reservation "power4-imul2" 5
 205   (and (eq_attr "type" "imul2")
 206        (eq_attr "cpu" "power4"))
 207   "(q1_power4,iu1_power4*4)|(q2_power4,iu2_power4*4)")
 208
 209 (define_insn_reservation "power4-imul3" 4
 210   (and (eq_attr "type" "imul3")
 211        (eq_attr "cpu" "power4"))
 212   "(q1_power4,iu1_power4*3)|(q2_power4,iu2_power4*3)")
 213
 214 ; SPR move only executes in first IU.
 215 ; Integer division only executes in second IU.
 216 (define_insn_reservation "power4-idiv" 36
 217   (and (eq_attr "type" "idiv")
 218        (eq_attr "cpu" "power4"))
 219   "(du1_power4+du2_power4),iu2_power4*35")
 220
 221 (define_insn_reservation "power4-ldiv" 68
 222   (and (eq_attr "type" "ldiv")
 223        (eq_attr "cpu" "power4"))
 224   "(du1_power4+du2_power4),iu2_power4*67")
 225
 226
 227 (define_insn_reservation "power4-mtjmpr" 3
 228   (and (eq_attr "type" "mtjmpr")
 229        (eq_attr "cpu" "power4"))
 230   "du1_power4,bpu_power4")
 231
 232
 233 ; Branches take dispatch Slot 4.  The presence_sets prevent other insn from
 234 ; grabbing previous dispatch slots once this is assigned.
 235 (define_insn_reservation "power4-branch" 2
 236   (and (eq_attr "type" "jmpreg,branch")
 237        (eq_attr "cpu" "power4"))
 238   "(du5_power4\
 239    |du4_power4+du5_power4\
 240    |du3_power4+du4_power4+du5_power4\
 241    |du2_power4+du3_power4+du4_power4+du5_power4\
 242    |du1_power4+du2_power4+du3_power4+du4_power4+du5_power4),bpu_power4")
 243
 244
 245 ; Condition Register logical ops are split if non-destructive (RT != RB)
 246 (define_insn_reservation "power4-crlogical" 2
 247   (and (eq_attr "type" "cr_logical")
 248        (eq_attr "cpu" "power4"))
 249   "du1_power4,cru_power4")
 250
 251 (define_insn_reservation "power4-delayedcr" 4
 252   (and (eq_attr "type" "delayed_cr")
 253        (eq_attr "cpu" "power4"))
 254   "(du1_power4+du2_power4),cru_power4,cru_power4")
 255
 256 ; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu
 257 (define_insn_reservation "power4-mfcr" 6
 258   (and (eq_attr "type" "mfcr")
 259        (eq_attr "cpu" "power4"))
 260   "(du1_power4+du2_power4+du3_power4+du4_power4),\
 261    (du1_power4+du2_power4+du3_power4+du4_power4+cru_power4),\
 262     cru_power4,cru_power4,cru_power4")
 263
 264 ; mtcrf (1 field)
 265 (define_insn_reservation "power4-mtcr" 4
 266   (and (eq_attr "type" "mtcr")
 267        (eq_attr "cpu" "power4"))
 268   "du1_power4,iu1_power4")
 269
 270 ; Basic FP latency is 6 cycles
 271 (define_insn_reservation "power4-fp" 6
 272   (and (eq_attr "type" "fp,dmul")
 273        (eq_attr "cpu" "power4"))
 274   "fpq_power4")
 275
 276 (define_insn_reservation "power4-fpcompare" 5
 277   (and (eq_attr "type" "fpcompare")
 278        (eq_attr "cpu" "power4"))
 279   "fpq_power4")
 280
 281 (define_insn_reservation "power4-sdiv" 33
 282   (and (eq_attr "type" "sdiv,ddiv")
 283        (eq_attr "cpu" "power4"))
 284   "(q1_power4,fpu1_power4*28)|(q2_power4,fpu2_power4*28)")
 285
 286 (define_insn_reservation "power4-sqrt" 40
 287   (and (eq_attr "type" "ssqrt,dsqrt")
 288        (eq_attr "cpu" "power4"))
 289   "(q1_power4,fpu1_power4*35)|(q2_power4,fpu2_power4*35)")
 290
 291
 292 ; VMX
 293 (define_insn_reservation "power4-vecsimple" 2
 294   (and (eq_attr "type" "vecsimple")
 295        (eq_attr "cpu" "power4"))
 296   "vq_power4")
 297
 298 (define_insn_reservation "power4-veccomplex" 2
 299   (and (eq_attr "type" "veccomplex")
 300        (eq_attr "cpu" "power4"))
 301   "vq_power4")
 302
 303 ; vecfp compare
 304 (define_insn_reservation "power4-veccmp" 8
 305   (and (eq_attr "type" "veccmp")
 306        (eq_attr "cpu" "power4"))
 307   "vq_power4")
 308
 309 (define_insn_reservation "power4-vecfloat" 8
 310   (and (eq_attr "type" "vecfloat")
 311        (eq_attr "cpu" "power4"))
 312   "vq_power4")
 313
 314 (define_insn_reservation "power4-vecperm" 2
 315   (and (eq_attr "type" "vecperm")
 316        (eq_attr "cpu" "power4"))
 317   "vpq_power4")
 318
 319 (define_bypass 4 "power4-vecload" "power4-vecperm")
 320
 321 (define_bypass 3 "power4-vecsimple,power4-veccomplex" "power4-vecperm")
 322 (define_bypass 3 "power4-vecperm"
 323                  "power4-vecsimple,power4-veccomplex,power4-vecfloat")
 324 (define_bypass 9 "power4-vecfloat" "power4-vecperm")
 325
 326 (define_bypass 5 "power4-vecsimple,power4-veccomplex"
 327                  "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr")
 328
 329 (define_bypass 4 "power4-vecsimple,power4-vecperm" "power4-vecstore")
 330 (define_bypass 7 "power4-veccomplex" "power4-vecstore")
 331 (define_bypass 10 "power4-vecfloat" "power4-vecstore")