gcc/config/rs6000/power4.md

   1 ;; Scheduling description for IBM Power4 and PowerPC 970 processors.
   2 ;;   Copyright (C) 2003 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GNU CC.
   5 ;;
   6 ;; GNU CC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 2, or (at your option)
   9 ;; any later version.
  10 ;;
  11 ;; GNU CC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GNU CC; see the file COPYING.  If not, write to
  18 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
  19 ;; Boston, MA 02111-1307, USA.
  20
  21 ;; Sources: IBM Red Book and White Paper on POWER4
  22
  23 ;; The POWER4 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip).
  24 ;; Instructions that update more than one register get broken into two
  25 ;; (split) or more internal ops.  The chip can issue up to 5
  26 ;; internal ops per cycle.
  27
  28 (define_automaton "power4iu,power4lsu,power4fpu,power4misc,power4vec,power4disp")
  29
  30 (define_cpu_unit "iu1_power4,iu2_power4" "power4iu")
  31 (define_cpu_unit "lsu1_power4,lsu2_power4" "power4lsu")
  32 (define_cpu_unit "fpu1_power4,fpu2_power4" "power4fpu")
  33 (define_cpu_unit "bpu_power4,cru_power4" "power4misc")
  34 (define_cpu_unit "vec_power4,vecperm_power4" "power4vec")
  35 (define_cpu_unit "du1_power4,du2_power4,du3_power4,du4_power4,du5_power4"
  36                  "power4disp")
  37
  38 (define_reservation "q1_power4" "du1_power4|du4_power4")
  39 (define_reservation "q2_power4" "du2_power4|du3_power4")
  40
  41 (define_reservation "lsq_power4" "((du1_power4|du4_power4),lsu1_power4)\
  42                                  |((du2_power4|du3_power4),lsu2_power4)")
  43
  44 (define_reservation "lsuq_power4"
  45                     "((du1_power4+du2_power4),lsu1_power4+iu2_power4)\
  46                     |((du2_power4+du3_power4),lsu2_power4+iu2_power4)\
  47                     |((du3_power4+du4_power4),lsu2_power4+iu1_power4)")
  48 ;;;                 |((du2_power4+du3_power4),lsu2_power4,iu2_power4)
  49
  50 (define_reservation "lsuxq_power4"
  51                     "(du1_power4+du2_power4+du3_power4+du4_power4),\
  52                      iu1_power4,(lsu2_power4+iu2_power4)")
  53
  54 (define_reservation "iq_power4" "((du1_power4|du4_power4),iu1_power4)\
  55                                 |((du2_power4|du3_power4),iu2_power4)")
  56
  57 (define_reservation "fpq_power4" "((du1_power4|du4_power4),fpu1_power4)\
  58                                  |((du2_power4|du3_power4),fpu2_power4)")
  59
  60 (define_reservation "vq_power4"
  61                     "(du1_power4|du2_power4|du3_power4|du4_power4),vec_power4")
  62 (define_reservation "vpq_power4"
  63                     "(du1_power4|du2_power4|du3_power4|du4_power4),\
  64                      vecperm_power4")
  65
  66
  67 ; Dispatch slots are allocated in order conforming to program order.
  68 (absence_set "du1_power4" "du2_power4,du3_power4,du4_power4,du5_power4")
  69 (absence_set "du2_power4" "du3_power4,du4_power4,du5_power4")
  70 (absence_set "du3_power4" "du4_power4,du5_power4")
  71 (absence_set "du4_power4" "du5_power4")
  72
  73
  74 ; Load/store
  75 (define_insn_reservation "power4-load" 3
  76   (and (eq_attr "type" "load")
  77        (eq_attr "cpu" "power4"))
  78   "lsq_power4")
  79
  80 (define_insn_reservation "power4-load-ext" 5
  81   (and (eq_attr "type" "load_ext")
  82        (eq_attr "cpu" "power4"))
  83   "((du1_power4+du2_power4),lsu1_power4,nothing,nothing,iu2_power4)\
  84   |((du2_power4+du3_power4),lsu2_power4,nothing,nothing,iu2_power4)\
  85   |((du3_power4+du4_power4),lsu2_power4,nothing,nothing,iu1_power4)")
  86
  87 (define_insn_reservation "power4-load-ext-update" 5
  88   (and (eq_attr "type" "load_ext_u")
  89        (eq_attr "cpu" "power4"))
  90   "(du1_power4+du2_power4+du3_power4+du4_power4),\
  91    (lsu1_power4+iu2_power4),nothing,nothing,iu2_power4")
  92
  93 (define_insn_reservation "power4-load-ext-update-indexed" 5
  94   (and (eq_attr "type" "load_ext_ux")
  95        (eq_attr "cpu" "power4"))
  96   "(du1_power4+du2_power4+du3_power4+du4_power4),\
  97    iu1_power4,(lsu2_power4+iu1_power4),nothing,nothing,iu2_power4")
  98
  99 (define_insn_reservation "power4-load-update-indexed" 3
 100   (and (eq_attr "type" "load_ux")
 101        (eq_attr "cpu" "power4"))
 102   "lsuxq_power4")
 103
 104 (define_insn_reservation "power4-load-update" 3
 105   (and (eq_attr "type" "load_u")
 106        (eq_attr "cpu" "power4"))
 107   "lsuq_power4")
 108
 109 (define_insn_reservation "power4-fpload" 5
 110   (and (eq_attr "type" "fpload")
 111        (eq_attr "cpu" "power4"))
 112   "lsq_power4")
 113
 114 (define_insn_reservation "power4-fpload-update" 5
 115   (and (eq_attr "type" "fpload_u")
 116        (eq_attr "cpu" "power4"))
 117   "lsuq_power4")
 118
 119 (define_insn_reservation "power4-fpload-update-indexed" 5
 120   (and (eq_attr "type" "fpload_ux")
 121        (eq_attr "cpu" "power4"))
 122   "lsuxq_power4")
 123
 124 (define_insn_reservation "power4-vecload" 5
 125   (and (eq_attr "type" "vecload")
 126        (eq_attr "cpu" "power4"))
 127   "lsq_power4")
 128
 129 (define_insn_reservation "power4-store" 1
 130   (and (eq_attr "type" "store")
 131        (eq_attr "cpu" "power4"))
 132   "((du1_power4|du4_power4),lsu1_power4,iu2_power4)\
 133   |((du2_power4|du3_power4),lsu2_power4,iu1_power4)")
 134
 135 (define_insn_reservation "power4-store-update" 1
 136   (and (eq_attr "type" "store_u")
 137        (eq_attr "cpu" "power4"))
 138   "lsuq_power4")
 139
 140 (define_insn_reservation "power4-store-update-indexed" 1
 141   (and (eq_attr "type" "store_ux")
 142        (eq_attr "cpu" "power4"))
 143   "lsuxq_power4")
 144
 145 (define_insn_reservation "power4-fpstore" 1
 146   (and (eq_attr "type" "fpstore")
 147        (eq_attr "cpu" "power4"))
 148   "((du1_power4|du4_power4),lsu1_power4,fpu1_power4)\
 149   |((du2_power4|du3_power4),lsu2_power4,fpu2_power4)")
 150
 151 (define_insn_reservation "power4-fpstore-update" 1
 152   (and (eq_attr "type" "fpstore_u")
 153        (eq_attr "cpu" "power4"))
 154   "((du1_power4+du2_power4),(fpu1_power4+iu2_power4),lsu1_power4)\
 155   |((du2_power4+du3_power4),(fpu2_power4+iu2_power4),lsu2_power4)\
 156   |((du3_power4+du4_power4),(fpu2_power4+iu1_power4),lsu2_power4)")
 157 ;;;((du2_power4+du3_power4),fpu2_power4,(iu2_power4+lsu2_power4))
 158
 159 (define_insn_reservation "power4-fpstore-update-indexed" 1
 160   (and (eq_attr "type" "fpstore_ux")
 161        (eq_attr "cpu" "power4"))
 162   "(du1_power4+du2_power4+du3_power4+du4_power4),
 163    iu1_power4,fpu2_power4,(iu2_power4+lsu2_power4)")
 164
 165 (define_insn_reservation "power4-vecstore" 1
 166   (and (eq_attr "type" "vecstore")
 167        (eq_attr "cpu" "power4"))
 168   "((du1_power4|du4_power4),lsu1_power4,vec_power4)\
 169   |((du2_power4|du3_power4),lsu2_power4,vec_power4)")
 170
 171
 172 ; Integer latency is 2 cycles
 173 (define_insn_reservation "power4-integer" 2
 174   (and (eq_attr "type" "integer")
 175        (eq_attr "cpu" "power4"))
 176   "iq_power4")
 177
 178 (define_insn_reservation "power4-cmp" 3
 179   (and (eq_attr "type" "cmp")
 180        (eq_attr "cpu" "power4"))
 181   "iq_power4")
 182
 183 (define_insn_reservation "power4-compare" 3
 184   (and (eq_attr "type" "compare,delayed_compare")
 185        (eq_attr "cpu" "power4"))
 186   "((du1_power4+du2_power4),iu1_power4,iu2_power4)\
 187   |((du2_power4+du3_power4),iu2_power4,iu2_power4)\
 188   |((du3_power4+du4_power4),iu2_power4,iu1_power4)")
 189
 190 (define_insn_reservation "power4-imul" 7
 191   (and (eq_attr "type" "imul,lmul")
 192        (eq_attr "cpu" "power4"))
 193   "(q1_power4,iu1_power4*6)|(q2_power4,iu2_power4*6)")
 194
 195 (define_insn_reservation "power4-imul2" 5
 196   (and (eq_attr "type" "imul2")
 197        (eq_attr "cpu" "power4"))
 198   "(q1_power4,iu1_power4*4)|(q2_power4,iu2_power4*4)")
 199
 200 (define_insn_reservation "power4-imul3" 4
 201   (and (eq_attr "type" "imul3")
 202        (eq_attr "cpu" "power4"))
 203   "(q1_power4,iu1_power4*3)|(q2_power4,iu2_power4*3)")
 204
 205 ; SPR move only executes in first IU.
 206 ; Integer division only executes in second IU.
 207 (define_insn_reservation "power4-idiv" 36
 208   (and (eq_attr "type" "idiv")
 209        (eq_attr "cpu" "power4"))
 210   "(du1_power4+du2_power4),iu2_power4*35")
 211
 212 (define_insn_reservation "power4-ldiv" 68
 213   (and (eq_attr "type" "ldiv")
 214        (eq_attr "cpu" "power4"))
 215   "(du1_power4+du2_power4),iu2_power4*67")
 216
 217
 218 (define_insn_reservation "power4-mtjmpr" 3
 219   (and (eq_attr "type" "mtjmpr")
 220        (eq_attr "cpu" "power4"))
 221   "du1_power4,bpu_power4")
 222
 223
 224 ; Branches take dispatch Slot 4.  The presence_sets prevent other insn from
 225 ; grabbing previous dispatch slots once this is assigned.
 226 (define_insn_reservation "power4-branch" 2
 227   (and (eq_attr "type" "jmpreg,branch")
 228        (eq_attr "cpu" "power4"))
 229   "du5_power4,bpu_power4")
 230
 231
 232 ; Condition Register logical ops are split if non-destructive (RT != RB)
 233 (define_insn_reservation "power4-crlogical" 2
 234   (and (eq_attr "type" "cr_logical")
 235        (eq_attr "cpu" "power4"))
 236   "du1_power4,cru_power4")
 237
 238 (define_insn_reservation "power4-delayedcr" 4
 239   (and (eq_attr "type" "delayed_cr")
 240        (eq_attr "cpu" "power4"))
 241   "(du1_power4+du2_power4),cru_power4,cru_power4")
 242
 243 ; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu
 244 (define_insn_reservation "power4-mfcr" 6
 245   (and (eq_attr "type" "mfcr")
 246        (eq_attr "cpu" "power4"))
 247   "(du1_power4+du2_power4+du3_power4+du4_power4),\
 248    (du1_power4+du2_power4+du3_power4+du4_power4+cru_power4),\
 249     cru_power4,cru_power4,cru_power4")
 250
 251 ; mtcrf (1 field)
 252 (define_insn_reservation "power4-mtcr" 4
 253   (and (eq_attr "type" "mtcr")
 254        (eq_attr "cpu" "power4"))
 255   "du1_power4,iu1_power4")
 256
 257 ; Basic FP latency is 6 cycles
 258 (define_insn_reservation "power4-fp" 6
 259   (and (eq_attr "type" "fp,dmul")
 260        (eq_attr "cpu" "power4"))
 261   "fpq_power4")
 262
 263 (define_insn_reservation "power4-fpcompare" 5
 264   (and (eq_attr "type" "fpcompare")
 265        (eq_attr "cpu" "power4"))
 266   "fpq_power4")
 267
 268 (define_insn_reservation "power4-sdiv" 33
 269   (and (eq_attr "type" "sdiv,ddiv")
 270        (eq_attr "cpu" "power4"))
 271   "(q1_power4,fpu1_power4*28)|(q2_power4,fpu2_power4*28)")
 272
 273 (define_insn_reservation "power4-sqrt" 40
 274   (and (eq_attr "type" "ssqrt,dsqrt")
 275        (eq_attr "cpu" "power4"))
 276   "(q1_power4,fpu1_power4*35)|(q2_power4,fpu2_power4*35)")
 277
 278
 279 ; VMX
 280 (define_insn_reservation "power4-vec" 2
 281   (and (eq_attr "type" "vecsimple,veccomplex")
 282        (eq_attr "cpu" "power4"))
 283   "vq_power4")
 284
 285 ; vecfp compare
 286 (define_insn_reservation "power4-veccmp" 8
 287   (and (eq_attr "type" "veccmp")
 288        (eq_attr "cpu" "power4"))
 289   "vq_power4")
 290
 291 (define_insn_reservation "power4-vecfloat" 8
 292   (and (eq_attr "type" "vecfloat")
 293        (eq_attr "cpu" "power4"))
 294   "vq_power4")
 295
 296 (define_insn_reservation "power4-vecperm" 2
 297   (and (eq_attr "type" "vecperm")
 298        (eq_attr "cpu" "power4"))
 299   "vpq_power4")
 300
 301 (define_bypass 4 "power4-vecload" "power4-vecperm")
 302 (define_bypass 5 "power4-vec"
 303                  "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr")
 304 (define_bypass 3 "power4-vec,power4-vecfloat" "power4-vecperm")
 305 (define_bypass 3 "power4-vecperm" "power4-vec,power4-vecfloat")