1 ;; Scheduling description for IBM POWER9 processor.
2 ;; Copyright (C) 2016-2019 Free Software Foundation, Inc.
4 ;; Contributed by Pat Haugen (pthaugen@us.ibm.com).
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 3, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 (define_automaton "power9dsp,power9lsu,power9vsu,power9fpdiv,power9misc")
24 (define_cpu_unit "lsu0_power9,lsu1_power9,lsu2_power9,lsu3_power9" "power9lsu")
25 (define_cpu_unit "vsu0_power9,vsu1_power9,vsu2_power9,vsu3_power9" "power9vsu")
26 ; Two vector permute units, part of vsu
27 (define_cpu_unit "prm0_power9,prm1_power9" "power9vsu")
28 ; Two fixed point divide units, not pipelined
29 (define_cpu_unit "fx_div0_power9,fx_div1_power9" "power9misc")
30 (define_cpu_unit "bru_power9,cryptu_power9,dfu_power9" "power9misc")
31 ; Create a false unit for use by non-pipelined FP div/sqrt
32 (define_cpu_unit "fp_div0_power9,fp_div1_power9,fp_div2_power9,fp_div3_power9"
36 (define_cpu_unit "x0_power9,x1_power9,xa0_power9,xa1_power9,
37 x2_power9,x3_power9,xb0_power9,xb1_power9,
38 br0_power9,br1_power9" "power9dsp")
41 ; Dispatch port reservations
43 ; Power9 can dispatch a maximum of 6 iops per cycle with the following
44 ; general restrictions (other restrictions also apply):
45 ; 1) At most 2 iops per execution slice
46 ; 2) At most 2 iops to the branch unit
47 ; Note that insn position in a dispatch group of 6 insns does not infer which
48 ; execution slice the insn is routed to. The units are used to infer the
49 ; conflicts that exist (i.e. an 'even' requirement will preclude dispatch
50 ; with 2 insns with 'superslice' requirement).
52 ; The xa0/xa1 units really represent the 3rd dispatch port for a superslice but
53 ; are listed as separate units to allow those insns that preclude its use to
54 ; still be scheduled two to a superslice while reserving the 3rd slot. The
55 ; same applies for xb0/xb1.
56 (define_reservation "DU_xa_power9" "xa0_power9+xa1_power9")
57 (define_reservation "DU_xb_power9" "xb0_power9+xb1_power9")
59 ; Any execution slice dispatch
60 (define_reservation "DU_any_power9"
61 "x0_power9|x1_power9|DU_xa_power9|x2_power9|x3_power9|
64 ; Even slice, actually takes even/odd slots
65 (define_reservation "DU_even_power9" "x0_power9+x1_power9|x2_power9+x3_power9")
68 (define_reservation "DU_slice_3_power9"
69 "x0_power9+xa0_power9|x1_power9+xa1_power9|
70 x2_power9+xb0_power9|x3_power9+xb1_power9")
73 (define_reservation "DU_super_power9"
74 "x0_power9+x1_power9|x2_power9+x3_power9")
77 (define_reservation "DU_C2_power9" "x0_power9+x1_power9|
78 x1_power9+DU_xa_power9|
80 DU_xa_power9+x2_power9|
82 x3_power9+DU_xb_power9")
84 ; 2-way cracked plus 3rd slot
85 (define_reservation "DU_C2_3_power9" "x0_power9+x1_power9+xa0_power9|
86 x1_power9+x2_power9+xa1_power9|
87 x2_power9+x3_power9+xb0_power9")
89 ; 3-way cracked (consumes whole decode/dispatch cycle)
90 (define_reservation "DU_C3_power9"
91 "x0_power9+x1_power9+xa0_power9+xa1_power9+x2_power9+
92 x3_power9+xb0_power9+xb1_power9+br0_power9+br1_power9")
95 (define_reservation "DU_branch_power9" "br0_power9|br1_power9")
98 ; Execution unit reservations
99 (define_reservation "LSU_power9"
100 "lsu0_power9|lsu1_power9|lsu2_power9|lsu3_power9")
102 (define_reservation "LSU_pair_power9"
103 "lsu0_power9+lsu1_power9|lsu1_power9+lsu2_power9|
104 lsu2_power9+lsu3_power9|lsu3_power9+lsu0_power9")
106 (define_reservation "VSU_power9"
107 "vsu0_power9|vsu1_power9|vsu2_power9|vsu3_power9")
109 (define_reservation "VSU_super_power9"
110 "vsu0_power9+vsu1_power9|vsu2_power9+vsu3_power9")
112 (define_reservation "VSU_PRM_power9" "prm0_power9|prm1_power9")
114 ; Define the reservation to be used by FP div/sqrt which allows other insns
115 ; to be issued to the VSU, but blocks other div/sqrt for a number of cycles.
116 ; Note that the number of cycles blocked varies depending on insn, but we
117 ; just use the same number for all in order to keep the number of DFA states
119 (define_reservation "FP_DIV_power9"
120 "fp_div0_power9*8|fp_div1_power9*8|fp_div2_power9*8|
122 (define_reservation "VEC_DIV_power9"
123 "fp_div0_power9*8+fp_div1_power9*8|
124 fp_div2_power9*8+fp_div3_power9*8")
128 (define_insn_reservation "power9-load" 4
129 (and (eq_attr "type" "load")
130 (eq_attr "sign_extend" "no")
131 (eq_attr "update" "no")
132 (eq_attr "cpu" "power9"))
133 "DU_any_power9,LSU_power9")
135 (define_insn_reservation "power9-load-update" 4
136 (and (eq_attr "type" "load")
137 (eq_attr "sign_extend" "no")
138 (eq_attr "update" "yes")
139 (eq_attr "cpu" "power9"))
140 "DU_C2_power9,LSU_power9+VSU_power9")
142 (define_insn_reservation "power9-load-ext" 6
143 (and (eq_attr "type" "load")
144 (eq_attr "sign_extend" "yes")
145 (eq_attr "update" "no")
146 (eq_attr "cpu" "power9"))
147 "DU_C2_power9,LSU_power9")
149 (define_insn_reservation "power9-load-ext-update" 6
150 (and (eq_attr "type" "load")
151 (eq_attr "sign_extend" "yes")
152 (eq_attr "update" "yes")
153 (eq_attr "cpu" "power9"))
154 "DU_C3_power9,LSU_power9+VSU_power9")
156 (define_insn_reservation "power9-fpload-double" 4
157 (and (eq_attr "type" "fpload")
158 (eq_attr "update" "no")
159 (eq_attr "size" "64")
160 (eq_attr "cpu" "power9"))
161 "DU_slice_3_power9,LSU_power9")
163 (define_insn_reservation "power9-fpload-update-double" 4
164 (and (eq_attr "type" "fpload")
165 (eq_attr "update" "yes")
166 (eq_attr "size" "64")
167 (eq_attr "cpu" "power9"))
168 "DU_C2_3_power9,LSU_power9+VSU_power9")
170 ; SFmode loads are cracked and have additional 2 cycles over DFmode
171 (define_insn_reservation "power9-fpload-single" 6
172 (and (eq_attr "type" "fpload")
173 (eq_attr "update" "no")
174 (eq_attr "size" "32")
175 (eq_attr "cpu" "power9"))
176 "DU_C2_3_power9,LSU_power9")
178 (define_insn_reservation "power9-fpload-update-single" 6
179 (and (eq_attr "type" "fpload")
180 (eq_attr "update" "yes")
181 (eq_attr "size" "32")
182 (eq_attr "cpu" "power9"))
183 "DU_C3_power9,LSU_power9+VSU_power9")
185 (define_insn_reservation "power9-vecload" 5
186 (and (eq_attr "type" "vecload")
187 (eq_attr "cpu" "power9"))
188 "DU_any_power9,LSU_pair_power9")
190 ; Store data can issue 2 cycles after AGEN issue, 3 cycles for vector store
191 (define_insn_reservation "power9-store" 0
192 (and (eq_attr "type" "store")
193 (eq_attr "update" "no")
194 (eq_attr "indexed" "no")
195 (eq_attr "cpu" "power9"))
196 "DU_slice_3_power9,LSU_power9")
198 (define_insn_reservation "power9-store-indexed" 0
199 (and (eq_attr "type" "store")
200 (eq_attr "update" "no")
201 (eq_attr "indexed" "yes")
202 (eq_attr "cpu" "power9"))
203 "DU_slice_3_power9,LSU_power9")
205 ; Update forms have 2 cycle latency for updated addr reg
206 (define_insn_reservation "power9-store-update" 2
207 (and (eq_attr "type" "store")
208 (eq_attr "update" "yes")
209 (eq_attr "indexed" "no")
210 (eq_attr "cpu" "power9"))
211 "DU_C2_3_power9,LSU_power9+VSU_power9")
213 ; Update forms have 2 cycle latency for updated addr reg
214 (define_insn_reservation "power9-store-update-indexed" 2
215 (and (eq_attr "type" "store")
216 (eq_attr "update" "yes")
217 (eq_attr "indexed" "yes")
218 (eq_attr "cpu" "power9"))
219 "DU_C2_3_power9,LSU_power9+VSU_power9")
221 (define_insn_reservation "power9-fpstore" 0
222 (and (eq_attr "type" "fpstore")
223 (eq_attr "update" "no")
224 (eq_attr "cpu" "power9"))
225 "DU_slice_3_power9,LSU_power9")
227 ; Update forms have 2 cycle latency for updated addr reg
228 (define_insn_reservation "power9-fpstore-update" 2
229 (and (eq_attr "type" "fpstore")
230 (eq_attr "update" "yes")
231 (eq_attr "cpu" "power9"))
232 "DU_C2_3_power9,LSU_power9+VSU_power9")
234 (define_insn_reservation "power9-vecstore" 0
235 (and (eq_attr "type" "vecstore")
236 (eq_attr "cpu" "power9"))
237 "DU_super_power9,LSU_pair_power9")
239 (define_insn_reservation "power9-larx" 4
240 (and (eq_attr "type" "load_l")
241 (eq_attr "cpu" "power9"))
242 "DU_any_power9,LSU_power9")
244 (define_insn_reservation "power9-stcx" 2
245 (and (eq_attr "type" "store_c")
246 (eq_attr "cpu" "power9"))
247 "DU_C2_3_power9,LSU_power9+VSU_power9")
249 (define_insn_reservation "power9-sync" 4
250 (and (eq_attr "type" "sync,isync")
251 (eq_attr "cpu" "power9"))
252 "DU_any_power9,LSU_power9")
259 ; Most ALU insns are simple 2 cycle, including record form
260 (define_insn_reservation "power9-alu" 2
261 (and (eq_attr "type" "add,exts,integer,logical,isel")
262 (eq_attr "cpu" "power9"))
263 "DU_any_power9,VSU_power9")
265 (define_bypass 5 "power9-alu"
266 "power9-crlogical,power9-mfcr,power9-mfcrf")
268 ; Rotate/shift prevent use of third slot
269 (define_insn_reservation "power9-rot" 2
270 (and (eq_attr "type" "insert,shift")
272 (eq_attr "cpu" "power9"))
273 "DU_slice_3_power9,VSU_power9")
275 ; Record form rotate/shift are cracked
276 (define_insn_reservation "power9-cracked-alu" 2
277 (and (eq_attr "type" "insert,shift")
278 (eq_attr "dot" "yes")
279 (eq_attr "cpu" "power9"))
280 "DU_C2_3_power9,VSU_power9")
282 (define_bypass 7 "power9-cracked-alu"
283 "power9-crlogical,power9-mfcr,power9-mfcrf")
285 (define_insn_reservation "power9-alu2" 3
286 (and (eq_attr "type" "cntlz,popcnt,trap")
287 (eq_attr "cpu" "power9"))
288 "DU_any_power9,VSU_power9")
290 (define_bypass 6 "power9-alu2"
291 "power9-crlogical,power9-mfcr,power9-mfcrf")
293 (define_insn_reservation "power9-cmp" 2
294 (and (eq_attr "type" "cmp")
295 (eq_attr "cpu" "power9"))
296 "DU_any_power9,VSU_power9")
299 ; Treat 'two' and 'three' types as 2 or 3 way cracked
300 (define_insn_reservation "power9-two" 4
301 (and (eq_attr "type" "two")
302 (eq_attr "cpu" "power9"))
303 "DU_C2_power9,VSU_power9")
305 (define_insn_reservation "power9-three" 6
306 (and (eq_attr "type" "three")
307 (eq_attr "cpu" "power9"))
308 "DU_C3_power9,VSU_power9")
310 (define_insn_reservation "power9-mul" 5
311 (and (eq_attr "type" "mul")
313 (eq_attr "cpu" "power9"))
314 "DU_slice_3_power9,VSU_power9")
316 (define_insn_reservation "power9-mul-compare" 5
317 (and (eq_attr "type" "mul")
318 (eq_attr "dot" "yes")
319 (eq_attr "cpu" "power9"))
320 "DU_C2_3_power9,VSU_power9")
321 ; 10 cycle CR latency
322 (define_bypass 10 "power9-mul-compare"
323 "power9-crlogical,power9-mfcr,power9-mfcrf")
325 ; Fixed point divides reserve the divide units for a minimum of 8 cycles
326 (define_insn_reservation "power9-idiv" 16
327 (and (eq_attr "type" "div")
328 (eq_attr "size" "32")
329 (eq_attr "cpu" "power9"))
330 "DU_even_power9,fx_div0_power9*8|fx_div1_power9*8")
332 (define_insn_reservation "power9-ldiv" 24
333 (and (eq_attr "type" "div")
334 (eq_attr "size" "64")
335 (eq_attr "cpu" "power9"))
336 "DU_even_power9,fx_div0_power9*8|fx_div1_power9*8")
338 (define_insn_reservation "power9-crlogical" 2
339 (and (eq_attr "type" "cr_logical")
340 (eq_attr "cpu" "power9"))
341 "DU_any_power9,VSU_power9")
343 (define_insn_reservation "power9-mfcrf" 2
344 (and (eq_attr "type" "mfcrf")
345 (eq_attr "cpu" "power9"))
346 "DU_any_power9,VSU_power9")
348 (define_insn_reservation "power9-mfcr" 6
349 (and (eq_attr "type" "mfcr")
350 (eq_attr "cpu" "power9"))
351 "DU_C3_power9,VSU_power9")
353 ; Should differentiate between 1 cr field and > 1 since target of > 1 cr
355 (define_insn_reservation "power9-mtcr" 2
356 (and (eq_attr "type" "mtcr")
357 (eq_attr "cpu" "power9"))
358 "DU_any_power9,VSU_power9")
360 ; Move to LR/CTR are executed in VSU
361 (define_insn_reservation "power9-mtjmpr" 5
362 (and (eq_attr "type" "mtjmpr")
363 (eq_attr "cpu" "power9"))
364 "DU_any_power9,VSU_power9")
366 ; Floating point/Vector ops
367 (define_insn_reservation "power9-fpsimple" 2
368 (and (eq_attr "type" "fpsimple")
369 (eq_attr "cpu" "power9"))
370 "DU_slice_3_power9,VSU_power9")
372 (define_insn_reservation "power9-fp" 5
373 (and (eq_attr "type" "fp,dmul")
374 (eq_attr "cpu" "power9"))
375 "DU_slice_3_power9,VSU_power9")
377 (define_insn_reservation "power9-fpcompare" 3
378 (and (eq_attr "type" "fpcompare")
379 (eq_attr "cpu" "power9"))
380 "DU_slice_3_power9,VSU_power9")
382 ; FP div/sqrt are executed in the VSU slices. They are not pipelined wrt other
383 ; div/sqrt insns, but for the most part do not block pipelined ops.
384 (define_insn_reservation "power9-sdiv" 22
385 (and (eq_attr "type" "sdiv")
386 (eq_attr "cpu" "power9"))
387 "DU_slice_3_power9,VSU_power9,FP_DIV_power9")
389 (define_insn_reservation "power9-ddiv" 27
390 (and (eq_attr "type" "ddiv")
391 (eq_attr "cpu" "power9"))
392 "DU_slice_3_power9,VSU_power9,FP_DIV_power9")
394 (define_insn_reservation "power9-sqrt" 26
395 (and (eq_attr "type" "ssqrt")
396 (eq_attr "cpu" "power9"))
397 "DU_slice_3_power9,VSU_power9,FP_DIV_power9")
399 (define_insn_reservation "power9-dsqrt" 36
400 (and (eq_attr "type" "dsqrt")
401 (eq_attr "cpu" "power9"))
402 "DU_slice_3_power9,VSU_power9,FP_DIV_power9")
404 (define_insn_reservation "power9-vec-2cyc" 2
405 (and (eq_attr "type" "vecmove,veclogical,vecexts,veccmpfx")
406 (eq_attr "cpu" "power9"))
407 "DU_super_power9,VSU_super_power9")
409 (define_insn_reservation "power9-veccmp" 3
410 (and (eq_attr "type" "veccmp")
411 (eq_attr "cpu" "power9"))
412 "DU_super_power9,VSU_super_power9")
414 (define_insn_reservation "power9-vecsimple" 3
415 (and (eq_attr "type" "vecsimple")
416 (eq_attr "cpu" "power9"))
417 "DU_super_power9,VSU_super_power9")
419 (define_insn_reservation "power9-vecnormal" 7
420 (and (eq_attr "type" "vecfloat,vecdouble")
421 (eq_attr "size" "!128")
422 (eq_attr "cpu" "power9"))
423 "DU_super_power9,VSU_super_power9")
425 ; Quad-precision FP ops, execute in DFU
426 (define_insn_reservation "power9-qp" 12
427 (and (eq_attr "type" "vecfloat,vecdouble")
428 (eq_attr "size" "128")
429 (eq_attr "cpu" "power9"))
430 "DU_super_power9,dfu_power9")
432 (define_insn_reservation "power9-vecperm" 3
433 (and (eq_attr "type" "vecperm")
434 (eq_attr "cpu" "power9"))
435 "DU_super_power9,VSU_PRM_power9")
437 (define_insn_reservation "power9-veccomplex" 7
438 (and (eq_attr "type" "veccomplex")
439 (eq_attr "cpu" "power9"))
440 "DU_super_power9,VSU_super_power9")
442 (define_insn_reservation "power9-vecfdiv" 24
443 (and (eq_attr "type" "vecfdiv")
444 (eq_attr "cpu" "power9"))
445 "DU_super_power9,VSU_super_power9,VEC_DIV_power9")
447 (define_insn_reservation "power9-vecdiv" 27
448 (and (eq_attr "type" "vecdiv")
449 (eq_attr "size" "!128")
450 (eq_attr "cpu" "power9"))
451 "DU_super_power9,VSU_super_power9,VEC_DIV_power9")
453 ; Use 8 for DFU reservation on QP div/mul to limit DFA state size
454 (define_insn_reservation "power9-qpdiv" 56
455 (and (eq_attr "type" "vecdiv")
456 (eq_attr "size" "128")
457 (eq_attr "cpu" "power9"))
458 "DU_super_power9,dfu_power9*8")
460 (define_insn_reservation "power9-qpmul" 24
461 (and (eq_attr "type" "qmul")
462 (eq_attr "size" "128")
463 (eq_attr "cpu" "power9"))
464 "DU_super_power9,dfu_power9*8")
466 (define_insn_reservation "power9-mffgpr" 2
467 (and (eq_attr "type" "mffgpr")
468 (eq_attr "cpu" "power9"))
469 "DU_slice_3_power9,VSU_power9")
471 (define_insn_reservation "power9-mftgpr" 2
472 (and (eq_attr "type" "mftgpr")
473 (eq_attr "cpu" "power9"))
474 "DU_slice_3_power9,VSU_power9")
478 ; Move from LR/CTR are executed in BRU but consume a writeback port from an
480 (define_insn_reservation "power9-mfjmpr" 6
481 (and (eq_attr "type" "mfjmpr")
482 (eq_attr "cpu" "power9"))
483 "DU_branch_power9,bru_power9+VSU_power9")
486 (define_insn_reservation "power9-branch" 2
487 (and (eq_attr "type" "jmpreg,branch")
488 (eq_attr "cpu" "power9"))
489 "DU_branch_power9,bru_power9")
493 (define_insn_reservation "power9-crypto" 6
494 (and (eq_attr "type" "crypto")
495 (eq_attr "cpu" "power9"))
496 "DU_super_power9,cryptu_power9")
500 (define_insn_reservation "power9-htm" 4
501 (and (eq_attr "type" "htm")
502 (eq_attr "cpu" "power9"))
503 "DU_C2_power9,LSU_power9")
505 (define_insn_reservation "power9-htm-simple" 2
506 (and (eq_attr "type" "htmsimple")
507 (eq_attr "cpu" "power9"))
508 "DU_any_power9,VSU_power9")
512 (define_insn_reservation "power9-dfp" 12
513 (and (eq_attr "type" "dfp")
514 (eq_attr "cpu" "power9"))
515 "DU_even_power9,dfu_power9")