1 ;; Predicate definitions for POWER and PowerPC.
2 ;; Copyright (C) 2005 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
19 ;; Boston, MA 02111-1307, USA.
21 ;; Return 1 for anything except PARALLEL.
22 (define_predicate "any_operand"
23 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem"))
25 ;; Return 1 for any PARALLEL.
26 (define_predicate "any_parallel_operand"
27 (match_code "parallel"))
29 ;; Return 1 if op is COUNT register.
30 (define_predicate "count_register_operand"
31 (and (match_code "reg")
32 (match_test "REGNO (op) == COUNT_REGISTER_REGNUM
33 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
35 ;; Return 1 if op is an Altivec register.
36 (define_predicate "altivec_register_operand"
37 (and (match_operand 0 "register_operand")
38 (match_test "GET_CODE (op) != REG
39 || ALTIVEC_REGNO_P (REGNO (op))
40 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
42 ;; Return 1 if op is XER register.
43 (define_predicate "xer_operand"
44 (and (match_code "reg")
45 (match_test "XER_REGNO_P (REGNO (op))")))
47 ;; Return 1 if op is a signed 8-bit constant integer.
48 ;; Integer multiplcation complete more quickly
49 (define_predicate "s8bit_cint_operand"
50 (and (match_code "const_int")
51 (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127")))
53 ;; Return 1 if op is a constant integer that can fit in a D field.
54 (define_predicate "short_cint_operand"
55 (and (match_code "const_int")
56 (match_test "CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')")))
58 ;; Return 1 if op is a constant integer that can fit in an unsigned D field.
59 (define_predicate "u_short_cint_operand"
60 (and (match_code "const_int")
61 (match_test "CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')")))
63 ;; Return 1 if op is a constant integer that cannot fit in a signed D field.
64 (define_predicate "non_short_cint_operand"
65 (and (match_code "const_int")
66 (match_test "(unsigned HOST_WIDE_INT)
67 (INTVAL (op) + 0x8000) >= 0x10000")))
69 ;; Return 1 if op is a positive constant integer that is an exact power of 2.
70 (define_predicate "exact_log2_cint_operand"
71 (and (match_code "const_int")
72 (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0")))
74 ;; Return 1 if op is a register that is not special.
75 (define_predicate "gpc_reg_operand"
76 (and (match_operand 0 "register_operand")
77 (match_test "GET_CODE (op) != REG
78 || (REGNO (op) >= ARG_POINTER_REGNUM
79 && !XER_REGNO_P (REGNO (op)))
80 || REGNO (op) < MQ_REGNO")))
82 ;; Return 1 if op is a register that is a condition register field.
83 (define_predicate "cc_reg_operand"
84 (and (match_operand 0 "register_operand")
85 (match_test "GET_CODE (op) != REG
86 || REGNO (op) > LAST_VIRTUAL_REGISTER
87 || CR_REGNO_P (REGNO (op))")))
89 ;; Return 1 if op is a register that is a condition register field not cr0.
90 (define_predicate "cc_reg_not_cr0_operand"
91 (and (match_operand 0 "register_operand")
92 (match_test "GET_CODE (op) != REG
93 || REGNO (op) > LAST_VIRTUAL_REGISTER
94 || CR_REGNO_NOT_CR0_P (REGNO (op))")))
96 ;; Return 1 if op is a constant integer valid for D field
97 ;; or non-special register register.
98 (define_predicate "reg_or_short_operand"
99 (if_then_else (match_code "const_int")
100 (match_operand 0 "short_cint_operand")
101 (match_operand 0 "gpc_reg_operand")))
103 ;; Return 1 if op is a constant integer valid whose negation is valid for
104 ;; D field or non-special register register.
105 ;; Do not allow a constant zero because all patterns that call this
106 ;; predicate use "addic r1,r2,-const" to set carry when r2 is greater than
107 ;; or equal to const, which does not work for zero.
108 (define_predicate "reg_or_neg_short_operand"
109 (if_then_else (match_code "const_int")
110 (match_test "CONST_OK_FOR_LETTER_P (INTVAL (op), 'P')
111 && INTVAL (op) != 0")
112 (match_operand 0 "gpc_reg_operand")))
114 ;; Return 1 if op is a constant integer valid for DS field
115 ;; or non-special register.
116 (define_predicate "reg_or_aligned_short_operand"
117 (if_then_else (match_code "const_int")
118 (and (match_operand 0 "short_cint_operand")
119 (match_test "!(INTVAL (op) & 3)"))
120 (match_operand 0 "gpc_reg_operand")))
122 ;; Return 1 if op is a constant integer whose high-order 16 bits are zero
123 ;; or non-special register.
124 (define_predicate "reg_or_u_short_operand"
125 (if_then_else (match_code "const_int")
126 (match_operand 0 "u_short_cint_operand")
127 (match_operand 0 "gpc_reg_operand")))
129 ;; Return 1 if op is any constant integer
130 ;; or non-special register.
131 (define_predicate "reg_or_cint_operand"
132 (ior (match_code "const_int")
133 (match_operand 0 "gpc_reg_operand")))
135 ;; Return 1 if op is a 32-bit signed constant integer valid for arithmetic
136 ;; or non-special register.
137 (define_predicate "reg_or_arith_cint_operand"
138 (if_then_else (match_code "const_int")
139 (match_test "HOST_BITS_PER_WIDE_INT == 32
140 || ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000)
141 < (unsigned HOST_WIDE_INT) 0x100000000ll)")
142 (match_operand 0 "gpc_reg_operand")))
144 ;; Return 1 if op is a 32-bit signed constant integer valid for 64-bit addition
145 ;; or non-special register.
146 (define_predicate "reg_or_add_cint64_operand"
147 (if_then_else (match_code "const_int")
148 (match_test "(HOST_BITS_PER_WIDE_INT == 32 && INTVAL (op) < 0x7fff8000)
149 || ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
150 < (unsigned HOST_WIDE_INT) 0x100000000ll)")
151 (match_operand 0 "gpc_reg_operand")))
153 ;; Return 1 if op is a 32-bit constant integer valid for 64-bit subtraction
154 ;; or non-special register.
155 (define_predicate "reg_or_sub_cint64_operand"
156 (if_then_else (match_code "const_int")
157 (match_test "(HOST_BITS_PER_WIDE_INT == 32 && INTVAL (op) < 0x7fff8000)
158 || ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000)
159 < (unsigned HOST_WIDE_INT) 0x100000000ll)")
160 (match_operand 0 "gpc_reg_operand")))
162 ;; Return 1 if op is any 32-bit unsigned constant integer
163 ;; or non-special register.
164 (define_predicate "reg_or_logical_cint_operand"
165 (if_then_else (match_code "const_int")
166 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
168 || ((INTVAL (op) & GET_MODE_MASK (mode)
169 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)")
170 (if_then_else (match_code "const_double")
171 (match_test "GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
173 && CONST_DOUBLE_HIGH (op) == 0")
174 (match_operand 0 "gpc_reg_operand"))))
176 ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register
177 ;; with no more than one instruction per word.
178 (define_predicate "easy_fp_constant"
179 (match_code "const_double")
184 if (GET_MODE (op) != mode
185 || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode))
188 /* Consider all constants with -msoft-float to be easy. */
189 if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
193 /* If we are using V.4 style PIC, consider all constants to be hard. */
194 if (flag_pic && DEFAULT_ABI == ABI_V4)
197 #ifdef TARGET_RELOCATABLE
198 /* Similarly if we are using -mrelocatable, consider all constants
200 if (TARGET_RELOCATABLE)
207 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
208 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
210 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
211 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1
212 && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1
213 && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1);
216 /* Force constants to memory before reload to utilize
217 compress_float_constant.
218 Avoid this when flag_unsafe_math_optimizations is enabled
219 because RDIV division to reciprocal optimization is not able
220 to regenerate the division. */
221 if (TARGET_E500_DOUBLE
222 || (!reload_in_progress && !reload_completed
223 && !flag_unsafe_math_optimizations))
226 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
227 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
229 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
230 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
233 /* Force constants to memory before reload to utilize
234 compress_float_constant.
235 Avoid this when flag_unsafe_math_optimizations is enabled
236 because RDIV division to reciprocal optimization is not able
237 to regenerate the division. */
238 if (!reload_in_progress && !reload_completed
239 && !flag_unsafe_math_optimizations)
242 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
243 REAL_VALUE_TO_TARGET_SINGLE (rv, k[0]);
245 return num_insns_constant_wide (k[0]) == 1;
248 return ((TARGET_POWERPC64
249 && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0)
250 || (num_insns_constant (op, DImode) <= 2));
260 ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
261 ;; vector register without using memory.
262 (define_predicate "easy_vector_constant"
263 (match_code "const_vector")
267 if (!TARGET_ALTIVEC && !TARGET_SPE)
270 if (zero_constant (op, mode)
271 && ((TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
272 || (TARGET_SPE && SPE_VECTOR_MODE (mode))))
275 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
278 if (TARGET_SPE && mode == V1DImode)
281 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
282 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
284 /* Limit SPE vectors to 15 bits signed. These we can generate with:
289 I don't know how efficient it would be to allow bigger constants,
290 considering we'll have an extra 'ori' for every 'li'. I doubt 5
291 instructions is better than a 64-bit memory load, but I don't
292 have the e500 timing specs. */
293 if (TARGET_SPE && mode == V2SImode
294 && cst >= -0x7fff && cst <= 0x7fff
295 && cst2 >= -0x7fff && cst2 <= 0x7fff)
299 && easy_vector_same (op, mode))
301 cst = easy_vector_splat_const (cst, mode);
302 if (EASY_VECTOR_15_ADD_SELF (cst)
303 || EASY_VECTOR_15 (cst))
309 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.
310 (define_predicate "easy_vector_constant_add_self"
311 (and (match_code "const_vector")
312 (and (match_test "TARGET_ALTIVEC")
313 (and (match_test "easy_vector_same (op, mode)")
314 (match_test "EASY_VECTOR_15_ADD_SELF
315 (easy_vector_splat_const
316 (INTVAL (CONST_VECTOR_ELT (op, 0)),
319 ;; Return 1 if operand is constant zero (scalars and vectors).
320 (define_predicate "zero_constant"
321 (and (match_code "const_int,const_double,const_vector")
322 (match_test "op == CONST0_RTX (mode)")))
324 ;; Return 1 if operand is 0.0.
325 ;; or non-special register register field no cr0
326 (define_predicate "zero_fp_constant"
327 (and (match_code "const_double")
328 (match_test "GET_MODE_CLASS (mode) == MODE_FLOAT
329 && op == CONST0_RTX (mode)")))
331 ;; Return 1 if the operand is in volatile memory. Note that during the
332 ;; RTL generation phase, memory_operand does not return TRUE for volatile
333 ;; memory references. So this function allows us to recognize volatile
334 ;; references where it's safe.
335 (define_predicate "volatile_mem_operand"
336 (and (and (match_code "mem")
337 (match_test "MEM_VOLATILE_P (op)"))
338 (if_then_else (match_test "reload_completed")
339 (match_operand 0 "memory_operand")
340 (if_then_else (match_test "reload_in_progress")
341 (match_test "strict_memory_address_p (mode, XEXP (op, 0))")
342 (match_test "memory_address_p (mode, XEXP (op, 0))")))))
344 ;; Return 1 if the operand is an offsettable memory operand.
345 (define_predicate "offsettable_mem_operand"
346 (and (match_code "mem")
347 (match_test "offsettable_address_p (reload_completed
348 || reload_in_progress,
349 mode, XEXP (op, 0))")))
351 ;; Return 1 if the operand is an indexed or indirect memory operand.
352 (define_predicate "indexed_or_indirect_operand"
353 (and (match_operand 0 "memory_operand")
354 (match_test "REG_P (XEXP (op, 0))
355 || (GET_CODE (XEXP (op, 0)) == PLUS
356 && REG_P (XEXP (XEXP (op, 0), 0))
357 && REG_P (XEXP (XEXP (op, 0), 1)))")))
359 ;; Return 1 if the operand is a memory operand with an address divisible by 4
360 (define_predicate "word_offset_memref_operand"
361 (and (match_operand 0 "memory_operand")
362 (match_test "GET_CODE (XEXP (op, 0)) != PLUS
363 || ! REG_P (XEXP (XEXP (op, 0), 0))
364 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT
365 || INTVAL (XEXP (XEXP (op, 0), 1)) % 4 == 0")))
367 ;; Return 1 if the operand is either a non-special register or can be used
368 ;; as the operand of a `mode' add insn.
369 (define_predicate "add_operand"
370 (if_then_else (match_code "const_int")
371 (match_test "CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
372 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')")
373 (match_operand 0 "gpc_reg_operand")))
375 ;; Return 1 if OP is a constant but not a valid add_operand.
376 (define_predicate "non_add_cint_operand"
377 (and (match_code "const_int")
378 (match_test "!CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
379 && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')")))
381 ;; Return 1 if the operand is a non-special register or a constant that
382 ;; can be used as the operand of an OR or XOR.
383 (define_predicate "logical_operand"
384 (match_code "reg,subreg,const_int,const_double")
386 HOST_WIDE_INT opl, oph;
388 if (gpc_reg_operand (op, mode))
391 if (GET_CODE (op) == CONST_INT)
393 opl = INTVAL (op) & GET_MODE_MASK (mode);
395 if (HOST_BITS_PER_WIDE_INT <= 32
396 && GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0)
399 else if (GET_CODE (op) == CONST_DOUBLE)
401 gcc_assert (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT);
403 opl = CONST_DOUBLE_LOW (op);
404 oph = CONST_DOUBLE_HIGH (op);
411 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
412 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
415 ;; Return 1 if op is a constant that is not a logical operand, but could
416 ;; be split into one.
417 (define_predicate "non_logical_cint_operand"
418 (and (match_code "const_int,const_double")
419 (and (not (match_operand 0 "logical_operand"))
420 (match_operand 0 "reg_or_logical_cint_operand"))))
422 ;; Return 1 if op is a constant that can be encoded in a 32-bit mask (no
423 ;; more than two 1->0 or 0->1 transitions). Reject all ones and all
424 ;; zeros, since these should have been optimized away and confuse the
425 ;; making of MB and ME.
426 (define_predicate "mask_operand"
427 (match_code "const_int")
429 HOST_WIDE_INT c, lsb;
433 /* Fail in 64-bit mode if the mask wraps around because the upper
434 32-bits of the mask will all be 1s, contrary to GCC's internal view. */
435 if (TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001)
438 /* We don't change the number of transitions by inverting,
439 so make sure we start with the LS bit zero. */
443 /* Reject all zeros or all ones. */
447 /* Find the first transition. */
450 /* Invert to look for a second transition. */
453 /* Erase first transition. */
456 /* Find the second transition (if any). */
459 /* Match if all the bits above are 1's (or c is zero). */
463 ;; Return 1 for the PowerPC64 rlwinm corner case.
464 (define_predicate "mask_operand_wrap"
465 (match_code "const_int")
467 HOST_WIDE_INT c, lsb;
471 if ((c & 0x80000001) != 0x80000001)
485 ;; Return 1 if the operand is a constant that is a PowerPC64 mask (no more
486 ;; than one 1->0 or 0->1 transitions). Reject all zeros, since zero
487 ;; should have been optimized away and confuses the making of MB and ME.
488 (define_predicate "mask64_operand"
489 (match_code "const_int")
491 HOST_WIDE_INT c, lsb;
495 /* Reject all zeros. */
499 /* We don't change the number of transitions by inverting,
500 so make sure we start with the LS bit zero. */
504 /* Find the transition, and check that all bits above are 1's. */
507 /* Match if all the bits above are 1's (or c is zero). */
511 ;; Like mask64_operand, but allow up to three transitions. This
512 ;; predicate is used by insn patterns that generate two rldicl or
513 ;; rldicr machine insns.
514 (define_predicate "mask64_2_operand"
515 (match_code "const_int")
517 return mask64_1or2_operand (op, mode, false);
520 ;; Return 1 if the operand is either a non-special register or a constant
521 ;; that can be used as the operand of a PowerPC64 logical AND insn.
522 (define_predicate "and64_operand"
523 (ior (match_operand 0 "mask64_operand")
524 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
525 (match_operand 0 "gpc_reg_operand")
526 (match_operand 0 "logical_operand"))))
528 ;; Like and64_operand, but also match constants that can be implemented
529 ;; with two rldicl or rldicr insns.
530 (define_predicate "and64_2_operand"
531 (ior (and (match_code "const_int")
532 (match_test "mask64_1or2_operand (op, mode, true)"))
533 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
534 (match_operand 0 "gpc_reg_operand")
535 (match_operand 0 "logical_operand"))))
537 ;; Return 1 if the operand is either a non-special register or a
538 ;; constant that can be used as the operand of a logical AND.
539 (define_predicate "and_operand"
540 (ior (match_operand 0 "mask_operand")
541 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
542 (match_operand 0 "gpc_reg_operand")
543 (match_operand 0 "logical_operand"))))
545 ;; Return 1 if the operand is a general non-special register or memory operand.
546 (define_predicate "reg_or_mem_operand"
547 (if_then_else (match_code "mem")
548 (ior (match_operand 0 "memory_operand")
549 (ior (match_test "macho_lo_sum_memory_operand (op, mode)")
550 (match_operand 0 "volatile_mem_operand")))
551 (match_operand 0 "gpc_reg_operand")))
553 ;; Return 1 if the operand is either an easy FP constant or memory or reg.
554 (define_predicate "reg_or_none500mem_operand"
555 (if_then_else (match_code "mem")
556 (and (match_test "!TARGET_E500_DOUBLE")
557 (ior (match_operand 0 "memory_operand")
558 (ior (match_test "macho_lo_sum_memory_operand (op, mode)")
559 (match_operand 0 "volatile_mem_operand"))))
560 (match_operand 0 "gpc_reg_operand")))
562 ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand.
563 (define_predicate "zero_reg_mem_operand"
564 (ior (match_operand 0 "zero_fp_constant")
565 (match_operand 0 "reg_or_mem_operand")))
567 ;; Return 1 if the operand is a general register or memory operand without
568 ;; pre_inc or pre_dec, which produces invalid form of PowerPC lwa
570 (define_predicate "lwa_operand"
571 (match_code "reg,subreg,mem")
575 if (reload_completed && GET_CODE (inner) == SUBREG)
576 inner = SUBREG_REG (inner);
578 return gpc_reg_operand (inner, mode)
579 || (memory_operand (inner, mode)
580 && GET_CODE (XEXP (inner, 0)) != PRE_INC
581 && GET_CODE (XEXP (inner, 0)) != PRE_DEC
582 && (GET_CODE (XEXP (inner, 0)) != PLUS
583 || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT
584 || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0));
587 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.
588 (define_predicate "symbol_ref_operand"
589 (and (match_code "symbol_ref")
590 (match_test "(mode == VOIDmode || GET_MODE (op) == mode)
591 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))")))
593 ;; Return 1 if op is an operand that can be loaded via the GOT.
594 ;; or non-special register register field no cr0
595 (define_predicate "got_operand"
596 (match_code "symbol_ref,const,label_ref"))
598 ;; Return 1 if op is a simple reference that can be loaded via the GOT,
599 ;; excluding labels involving addition.
600 (define_predicate "got_no_const_operand"
601 (match_code "symbol_ref,label_ref"))
603 ;; Return 1 if op is a SYMBOL_REF for a TLS symbol.
604 (define_predicate "rs6000_tls_symbol_ref"
605 (and (match_code "symbol_ref")
606 (match_test "RS6000_SYMBOL_REF_TLS_P (op)")))
608 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
609 ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR.
610 (define_predicate "call_operand"
611 (if_then_else (match_code "reg")
612 (match_test "REGNO (op) == LINK_REGISTER_REGNUM
613 || REGNO (op) == COUNT_REGISTER_REGNUM
614 || REGNO (op) >= FIRST_PSEUDO_REGISTER")
615 (match_code "symbol_ref")))
617 ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in
619 (define_predicate "current_file_function_operand"
620 (and (match_code "symbol_ref")
621 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
622 && (SYMBOL_REF_LOCAL_P (op)
623 || (op == XEXP (DECL_RTL (current_function_decl),
626 ;; Return 1 if this operand is a valid input for a move insn.
627 (define_predicate "input_operand"
628 (match_code "label_ref,symbol_ref,const,high,reg,subreg,mem,
629 const_double,const_vector,const_int,plus")
631 /* Memory is always valid. */
632 if (memory_operand (op, mode))
635 /* For floating-point, easy constants are valid. */
636 if (GET_MODE_CLASS (mode) == MODE_FLOAT
638 && easy_fp_constant (op, mode))
641 /* Allow any integer constant. */
642 if (GET_MODE_CLASS (mode) == MODE_INT
643 && (GET_CODE (op) == CONST_INT
644 || GET_CODE (op) == CONST_DOUBLE))
647 /* Allow easy vector constants. */
648 if (GET_CODE (op) == CONST_VECTOR
649 && easy_vector_constant (op, mode))
652 /* For floating-point or multi-word mode, the only remaining valid type
654 if (GET_MODE_CLASS (mode) == MODE_FLOAT
655 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
656 return register_operand (op, mode);
658 /* The only cases left are integral modes one word or smaller (we
659 do not get called for MODE_CC values). These can be in any
661 if (register_operand (op, mode))
664 /* A SYMBOL_REF referring to the TOC is valid. */
665 if (legitimate_constant_pool_address_p (op))
668 /* A constant pool expression (relative to the TOC) is valid */
669 if (toc_relative_expr_p (op))
672 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
674 if (DEFAULT_ABI == ABI_V4
675 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
676 && small_data_operand (op, Pmode))
682 ;; Return true if OP is an invalid SUBREG operation on the e500.
683 (define_predicate "rs6000_nonimmediate_operand"
684 (match_code "reg,subreg,mem")
686 if (TARGET_E500_DOUBLE
687 && GET_CODE (op) == SUBREG
688 && invalid_e500_subreg (op, mode))
691 return nonimmediate_operand (op, mode);
694 ;; Return true if operand is boolean operator.
695 (define_predicate "boolean_operator"
696 (match_code "and,ior,xor"))
698 ;; Return true if operand is OR-form of boolean operator.
699 (define_predicate "boolean_or_operator"
700 (match_code "ior,xor"))
702 ;; Return true if operand is MIN or MAX operator.
703 (define_predicate "min_max_operator"
704 (match_code "smin,smax,umin,umax"))
706 ;; Return 1 if OP is a comparison operation that is valid for a branch
707 ;; instruction. We check the opcode against the mode of the CC value.
708 ;; validate_condition_mode is an assertion.
709 (define_predicate "branch_comparison_operator"
710 (and (match_operand 0 "comparison_operator")
711 (and (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC")
712 (match_test "validate_condition_mode (GET_CODE (op),
713 GET_MODE (XEXP (op, 0))),
716 ;; Return 1 if OP is a comparison operation that is valid for an SCC insn --
717 ;; it must be a positive comparison.
718 (define_predicate "scc_comparison_operator"
719 (and (match_operand 0 "branch_comparison_operator")
720 (match_code "eq,lt,gt,ltu,gtu,unordered")))
722 ;; Return 1 if OP is a comparison operation that is valid for a branch
723 ;; insn, which is true if the corresponding bit in the CC register is set.
724 (define_predicate "branch_positive_comparison_operator"
725 (and (match_operand 0 "branch_comparison_operator")
726 (match_code "eq,lt,gt,ltu,gtu,unordered")))
728 ;; Return 1 is OP is a comparison operation that is valid for a trap insn.
729 (define_predicate "trap_comparison_operator"
730 (and (match_operand 0 "comparison_operator")
731 (match_code "eq,ne,le,lt,ge,gt,leu,ltu,geu,gtu")))
733 ;; Return 1 if OP is a load multiple operation, known to be a PARALLEL.
734 (define_predicate "load_multiple_operation"
735 (match_code "parallel")
737 int count = XVECLEN (op, 0);
738 unsigned int dest_regno;
742 /* Perform a quick check so we don't blow up below. */
744 || GET_CODE (XVECEXP (op, 0, 0)) != SET
745 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
746 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
749 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
750 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
752 for (i = 1; i < count; i++)
754 rtx elt = XVECEXP (op, 0, i);
756 if (GET_CODE (elt) != SET
757 || GET_CODE (SET_DEST (elt)) != REG
758 || GET_MODE (SET_DEST (elt)) != SImode
759 || REGNO (SET_DEST (elt)) != dest_regno + i
760 || GET_CODE (SET_SRC (elt)) != MEM
761 || GET_MODE (SET_SRC (elt)) != SImode
762 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
763 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
764 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
765 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
772 ;; Return 1 if OP is a store multiple operation, known to be a PARALLEL.
773 ;; The second vector element is a CLOBBER.
774 (define_predicate "store_multiple_operation"
775 (match_code "parallel")
777 int count = XVECLEN (op, 0) - 1;
778 unsigned int src_regno;
782 /* Perform a quick check so we don't blow up below. */
784 || GET_CODE (XVECEXP (op, 0, 0)) != SET
785 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
786 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
789 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
790 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
792 for (i = 1; i < count; i++)
794 rtx elt = XVECEXP (op, 0, i + 1);
796 if (GET_CODE (elt) != SET
797 || GET_CODE (SET_SRC (elt)) != REG
798 || GET_MODE (SET_SRC (elt)) != SImode
799 || REGNO (SET_SRC (elt)) != src_regno + i
800 || GET_CODE (SET_DEST (elt)) != MEM
801 || GET_MODE (SET_DEST (elt)) != SImode
802 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
803 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
804 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
805 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
812 ;; Return 1 if OP is valid for a save_world call in prologue, known to be
814 (define_predicate "save_world_operation"
815 (match_code "parallel")
820 int count = XVECLEN (op, 0);
826 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
827 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
830 for (i=1; i <= 18; i++)
832 elt = XVECEXP (op, 0, index++);
833 if (GET_CODE (elt) != SET
834 || GET_CODE (SET_DEST (elt)) != MEM
835 || ! memory_operand (SET_DEST (elt), DFmode)
836 || GET_CODE (SET_SRC (elt)) != REG
837 || GET_MODE (SET_SRC (elt)) != DFmode)
841 for (i=1; i <= 12; i++)
843 elt = XVECEXP (op, 0, index++);
844 if (GET_CODE (elt) != SET
845 || GET_CODE (SET_DEST (elt)) != MEM
846 || GET_CODE (SET_SRC (elt)) != REG
847 || GET_MODE (SET_SRC (elt)) != V4SImode)
851 for (i=1; i <= 19; i++)
853 elt = XVECEXP (op, 0, index++);
854 if (GET_CODE (elt) != SET
855 || GET_CODE (SET_DEST (elt)) != MEM
856 || ! memory_operand (SET_DEST (elt), Pmode)
857 || GET_CODE (SET_SRC (elt)) != REG
858 || GET_MODE (SET_SRC (elt)) != Pmode)
862 elt = XVECEXP (op, 0, index++);
863 if (GET_CODE (elt) != SET
864 || GET_CODE (SET_DEST (elt)) != MEM
865 || ! memory_operand (SET_DEST (elt), Pmode)
866 || GET_CODE (SET_SRC (elt)) != REG
867 || REGNO (SET_SRC (elt)) != CR2_REGNO
868 || GET_MODE (SET_SRC (elt)) != Pmode)
871 if (GET_CODE (XVECEXP (op, 0, index++)) != USE
872 || GET_CODE (XVECEXP (op, 0, index++)) != USE
873 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
878 ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be
880 (define_predicate "restore_world_operation"
881 (match_code "parallel")
886 int count = XVECLEN (op, 0);
892 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
893 || GET_CODE (XVECEXP (op, 0, index++)) != USE
894 || GET_CODE (XVECEXP (op, 0, index++)) != USE
895 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
898 elt = XVECEXP (op, 0, index++);
899 if (GET_CODE (elt) != SET
900 || GET_CODE (SET_SRC (elt)) != MEM
901 || ! memory_operand (SET_SRC (elt), Pmode)
902 || GET_CODE (SET_DEST (elt)) != REG
903 || REGNO (SET_DEST (elt)) != CR2_REGNO
904 || GET_MODE (SET_DEST (elt)) != Pmode)
907 for (i=1; i <= 19; i++)
909 elt = XVECEXP (op, 0, index++);
910 if (GET_CODE (elt) != SET
911 || GET_CODE (SET_SRC (elt)) != MEM
912 || ! memory_operand (SET_SRC (elt), Pmode)
913 || GET_CODE (SET_DEST (elt)) != REG
914 || GET_MODE (SET_DEST (elt)) != Pmode)
918 for (i=1; i <= 12; i++)
920 elt = XVECEXP (op, 0, index++);
921 if (GET_CODE (elt) != SET
922 || GET_CODE (SET_SRC (elt)) != MEM
923 || GET_CODE (SET_DEST (elt)) != REG
924 || GET_MODE (SET_DEST (elt)) != V4SImode)
928 for (i=1; i <= 18; i++)
930 elt = XVECEXP (op, 0, index++);
931 if (GET_CODE (elt) != SET
932 || GET_CODE (SET_SRC (elt)) != MEM
933 || ! memory_operand (SET_SRC (elt), DFmode)
934 || GET_CODE (SET_DEST (elt)) != REG
935 || GET_MODE (SET_DEST (elt)) != DFmode)
939 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
940 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
941 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
942 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
943 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
948 ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL.
949 (define_predicate "vrsave_operation"
950 (match_code "parallel")
952 int count = XVECLEN (op, 0);
953 unsigned int dest_regno, src_regno;
957 || GET_CODE (XVECEXP (op, 0, 0)) != SET
958 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
959 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE)
962 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
963 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
965 if (dest_regno != VRSAVE_REGNO
966 && src_regno != VRSAVE_REGNO)
969 for (i = 1; i < count; i++)
971 rtx elt = XVECEXP (op, 0, i);
973 if (GET_CODE (elt) != CLOBBER
974 && GET_CODE (elt) != SET)
981 ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL.
982 (define_predicate "mfcr_operation"
983 (match_code "parallel")
985 int count = XVECLEN (op, 0);
988 /* Perform a quick check so we don't blow up below. */
990 || GET_CODE (XVECEXP (op, 0, 0)) != SET
991 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
992 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
995 for (i = 0; i < count; i++)
997 rtx exp = XVECEXP (op, 0, i);
1002 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
1004 if (GET_CODE (src_reg) != REG
1005 || GET_MODE (src_reg) != CCmode
1006 || ! CR_REGNO_P (REGNO (src_reg)))
1009 if (GET_CODE (exp) != SET
1010 || GET_CODE (SET_DEST (exp)) != REG
1011 || GET_MODE (SET_DEST (exp)) != SImode
1012 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
1014 unspec = SET_SRC (exp);
1015 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
1017 if (GET_CODE (unspec) != UNSPEC
1018 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
1019 || XVECLEN (unspec, 0) != 2
1020 || XVECEXP (unspec, 0, 0) != src_reg
1021 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1022 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1028 ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL.
1029 (define_predicate "mtcrf_operation"
1030 (match_code "parallel")
1032 int count = XVECLEN (op, 0);
1036 /* Perform a quick check so we don't blow up below. */
1038 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1039 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1040 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1042 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
1044 if (GET_CODE (src_reg) != REG
1045 || GET_MODE (src_reg) != SImode
1046 || ! INT_REGNO_P (REGNO (src_reg)))
1049 for (i = 0; i < count; i++)
1051 rtx exp = XVECEXP (op, 0, i);
1055 if (GET_CODE (exp) != SET
1056 || GET_CODE (SET_DEST (exp)) != REG
1057 || GET_MODE (SET_DEST (exp)) != CCmode
1058 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
1060 unspec = SET_SRC (exp);
1061 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
1063 if (GET_CODE (unspec) != UNSPEC
1064 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
1065 || XVECLEN (unspec, 0) != 2
1066 || XVECEXP (unspec, 0, 0) != src_reg
1067 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1068 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1074 ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.
1075 (define_predicate "lmw_operation"
1076 (match_code "parallel")
1078 int count = XVECLEN (op, 0);
1079 unsigned int dest_regno;
1081 unsigned int base_regno;
1082 HOST_WIDE_INT offset;
1085 /* Perform a quick check so we don't blow up below. */
1087 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1088 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1089 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1092 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1093 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1096 || count != 32 - (int) dest_regno)
1099 if (legitimate_indirect_address_p (src_addr, 0))
1102 base_regno = REGNO (src_addr);
1103 if (base_regno == 0)
1106 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, 0))
1108 offset = INTVAL (XEXP (src_addr, 1));
1109 base_regno = REGNO (XEXP (src_addr, 0));
1114 for (i = 0; i < count; i++)
1116 rtx elt = XVECEXP (op, 0, i);
1119 HOST_WIDE_INT newoffset;
1121 if (GET_CODE (elt) != SET
1122 || GET_CODE (SET_DEST (elt)) != REG
1123 || GET_MODE (SET_DEST (elt)) != SImode
1124 || REGNO (SET_DEST (elt)) != dest_regno + i
1125 || GET_CODE (SET_SRC (elt)) != MEM
1126 || GET_MODE (SET_SRC (elt)) != SImode)
1128 newaddr = XEXP (SET_SRC (elt), 0);
1129 if (legitimate_indirect_address_p (newaddr, 0))
1134 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
1136 addr_reg = XEXP (newaddr, 0);
1137 newoffset = INTVAL (XEXP (newaddr, 1));
1141 if (REGNO (addr_reg) != base_regno
1142 || newoffset != offset + 4 * i)
1149 ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL.
1150 (define_predicate "stmw_operation"
1151 (match_code "parallel")
1153 int count = XVECLEN (op, 0);
1154 unsigned int src_regno;
1156 unsigned int base_regno;
1157 HOST_WIDE_INT offset;
1160 /* Perform a quick check so we don't blow up below. */
1162 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1163 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1164 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1167 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1168 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1171 || count != 32 - (int) src_regno)
1174 if (legitimate_indirect_address_p (dest_addr, 0))
1177 base_regno = REGNO (dest_addr);
1178 if (base_regno == 0)
1181 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, 0))
1183 offset = INTVAL (XEXP (dest_addr, 1));
1184 base_regno = REGNO (XEXP (dest_addr, 0));
1189 for (i = 0; i < count; i++)
1191 rtx elt = XVECEXP (op, 0, i);
1194 HOST_WIDE_INT newoffset;
1196 if (GET_CODE (elt) != SET
1197 || GET_CODE (SET_SRC (elt)) != REG
1198 || GET_MODE (SET_SRC (elt)) != SImode
1199 || REGNO (SET_SRC (elt)) != src_regno + i
1200 || GET_CODE (SET_DEST (elt)) != MEM
1201 || GET_MODE (SET_DEST (elt)) != SImode)
1203 newaddr = XEXP (SET_DEST (elt), 0);
1204 if (legitimate_indirect_address_p (newaddr, 0))
1209 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
1211 addr_reg = XEXP (newaddr, 0);
1212 newoffset = INTVAL (XEXP (newaddr, 1));
1216 if (REGNO (addr_reg) != base_regno
1217 || newoffset != offset + 4 * i)