gcc/config/rs6000/rs6000-cpus.def

   1 /* IBM RS/6000 CPU names..
   2    Copyright (C) 1991-2016 Free Software Foundation, Inc.
   3    Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 3, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21 /* ISA masks.  */
  22 #ifndef ISA_2_1_MASKS
  23 #define ISA_2_1_MASKS           OPTION_MASK_MFCRF
  24 #define ISA_2_2_MASKS           (ISA_2_1_MASKS | OPTION_MASK_POPCNTB)
  25 #define ISA_2_4_MASKS           (ISA_2_2_MASKS | OPTION_MASK_FPRND)
  26
  27   /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add
  28      ALTIVEC, since in general it isn't a win on power6.  In ISA 2.04, fsel,
  29      fre, fsqrt, etc. were no longer documented as optional.  Group masks by
  30      server and embedded. */
  31 #define ISA_2_5_MASKS_EMBEDDED  (ISA_2_4_MASKS                          \
  32                                  | OPTION_MASK_CMPB                     \
  33                                  | OPTION_MASK_RECIP_PRECISION          \
  34                                  | OPTION_MASK_PPC_GFXOPT               \
  35                                  | OPTION_MASK_PPC_GPOPT)
  36
  37 #define ISA_2_5_MASKS_SERVER    (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_DFP)
  38
  39   /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
  40      altivec is a win so enable it.  */
  41   /* OPTION_MASK_VSX_TIMODE should be set, but disable it for now until
  42      PR 58587 is fixed.  */
  43 #define ISA_2_6_MASKS_EMBEDDED  (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD)
  44 #define ISA_2_6_MASKS_SERVER    (ISA_2_5_MASKS_SERVER                   \
  45                                  | OPTION_MASK_POPCNTD                  \
  46                                  | OPTION_MASK_ALTIVEC                  \
  47                                  | OPTION_MASK_FLOAT128                 \
  48                                  | OPTION_MASK_VSX                      \
  49                                  | OPTION_MASK_UPPER_REGS_DF)
  50
  51 /* For now, don't provide an embedded version of ISA 2.07.  */
  52 #define ISA_2_7_MASKS_SERVER    (ISA_2_6_MASKS_SERVER                   \
  53                                  | OPTION_MASK_P8_FUSION                \
  54                                  | OPTION_MASK_P8_VECTOR                \
  55                                  | OPTION_MASK_CRYPTO                   \
  56                                  | OPTION_MASK_DIRECT_MOVE              \
  57                                  | OPTION_MASK_EFFICIENT_UNALIGNED_VSX  \
  58                                  | OPTION_MASK_HTM                      \
  59                                  | OPTION_MASK_QUAD_MEMORY              \
  60                                  | OPTION_MASK_QUAD_MEMORY_ATOMIC       \
  61                                  | OPTION_MASK_UPPER_REGS_SF)
  62
  63 /* Add ISEL back into ISA 3.0, since it is supposed to be a win.  Do not add
  64    P9_DFORM or P9_MINMAX until they are fully debugged.  */
  65 #define ISA_3_0_MASKS_SERVER    (ISA_2_7_MASKS_SERVER                   \
  66                                  | OPTION_MASK_FLOAT128_HW              \
  67                                  | OPTION_MASK_ISEL                     \
  68                                  | OPTION_MASK_MODULO                   \
  69                                  | OPTION_MASK_P9_FUSION                \
  70                                  | OPTION_MASK_P9_DFORM                 \
  71                                  | OPTION_MASK_P9_VECTOR)
  72
  73 #define POWERPC_7400_MASK       (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC)
  74
  75 /* Deal with ports that do not have -mstrict-align.  */
  76 #ifdef OPTION_MASK_STRICT_ALIGN
  77 #define OPTION_MASK_STRICT_ALIGN_OPTIONAL OPTION_MASK_STRICT_ALIGN
  78 #else
  79 #define OPTION_MASK_STRICT_ALIGN 0
  80 #define OPTION_MASK_STRICT_ALIGN_OPTIONAL 0
  81 #ifndef MASK_STRICT_ALIGN
  82 #define MASK_STRICT_ALIGN 0
  83 #endif
  84 #endif
  85
  86 /* Mask of all options to set the default isa flags based on -mcpu=<xxx>.  */
  87 #define POWERPC_MASKS           (OPTION_MASK_ALTIVEC                    \
  88                                  | OPTION_MASK_CMPB                     \
  89                                  | OPTION_MASK_CRYPTO                   \
  90                                  | OPTION_MASK_DFP                      \
  91                                  | OPTION_MASK_DIRECT_MOVE              \
  92                                  | OPTION_MASK_DLMZB                    \
  93                                  | OPTION_MASK_EFFICIENT_UNALIGNED_VSX  \
  94                                  | OPTION_MASK_FLOAT128                 \
  95                                  | OPTION_MASK_FPRND                    \
  96                                  | OPTION_MASK_HTM                      \
  97                                  | OPTION_MASK_ISEL                     \
  98                                  | OPTION_MASK_MFCRF                    \
  99                                  | OPTION_MASK_MFPGPR                   \
 100                                  | OPTION_MASK_MODULO                   \
 101                                  | OPTION_MASK_MULHW                    \
 102                                  | OPTION_MASK_NO_UPDATE                \
 103                                  | OPTION_MASK_P8_FUSION                \
 104                                  | OPTION_MASK_P8_VECTOR                \
 105                                  | OPTION_MASK_P9_DFORM                 \
 106                                  | OPTION_MASK_P9_FUSION                \
 107                                  | OPTION_MASK_P9_MINMAX                \
 108                                  | OPTION_MASK_P9_VECTOR                \
 109                                  | OPTION_MASK_POPCNTB                  \
 110                                  | OPTION_MASK_POPCNTD                  \
 111                                  | OPTION_MASK_POWERPC64                \
 112                                  | OPTION_MASK_PPC_GFXOPT               \
 113                                  | OPTION_MASK_PPC_GPOPT                \
 114                                  | OPTION_MASK_QUAD_MEMORY              \
 115                                  | OPTION_MASK_QUAD_MEMORY_ATOMIC       \
 116                                  | OPTION_MASK_RECIP_PRECISION          \
 117                                  | OPTION_MASK_SOFT_FLOAT               \
 118                                  | OPTION_MASK_STRICT_ALIGN_OPTIONAL    \
 119                                  | OPTION_MASK_TOC_FUSION               \
 120                                  | OPTION_MASK_UPPER_REGS_DF            \
 121                                  | OPTION_MASK_UPPER_REGS_SF            \
 122                                  | OPTION_MASK_VSX                      \
 123                                  | OPTION_MASK_VSX_TIMODE)
 124
 125 #endif
 126
 127 /* This table occasionally claims that a processor does not support a
 128    particular feature even though it does, but the feature is slower than the
 129    alternative.  Thus, it shouldn't be relied on as a complete description of
 130    the processor's support.
 131
 132    Please keep this list in order, and don't forget to update the documentation
 133    in invoke.texi when adding a new processor or flag.
 134
 135    Before including this file, define a macro:
 136
 137    RS6000_CPU (NAME, CPU, FLAGS)
 138
 139    where the arguments are the fields of struct rs6000_ptt.  */
 140
 141 RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT)
 142 RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT | MASK_STRICT_ALIGN)
 143 RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
 144 RS6000_CPU ("405fp", PROCESSOR_PPC405, MASK_MULHW | MASK_DLMZB)
 145 RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
 146 RS6000_CPU ("440fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
 147 RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
 148 RS6000_CPU ("464fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
 149 RS6000_CPU ("476", PROCESSOR_PPC476,
 150             MASK_SOFT_FLOAT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB
 151             | MASK_FPRND | MASK_CMPB | MASK_MULHW | MASK_DLMZB)
 152 RS6000_CPU ("476fp", PROCESSOR_PPC476,
 153             MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
 154             | MASK_CMPB | MASK_MULHW | MASK_DLMZB)
 155 RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
 156 RS6000_CPU ("601", PROCESSOR_PPC601, MASK_MULTIPLE | MASK_STRING)
 157 RS6000_CPU ("602", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
 158 RS6000_CPU ("603", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
 159 RS6000_CPU ("603e", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
 160 RS6000_CPU ("604", PROCESSOR_PPC604, MASK_PPC_GFXOPT)
 161 RS6000_CPU ("604e", PROCESSOR_PPC604e, MASK_PPC_GFXOPT)
 162 RS6000_CPU ("620", PROCESSOR_PPC620, MASK_PPC_GFXOPT | MASK_POWERPC64)
 163 RS6000_CPU ("630", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
 164 RS6000_CPU ("740", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
 165 RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK)
 166 RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK)
 167 RS6000_CPU ("750", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
 168 RS6000_CPU ("801", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
 169 RS6000_CPU ("821", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
 170 RS6000_CPU ("823", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
 171 RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | MASK_ISEL)
 172 RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | MASK_ISEL)
 173 RS6000_CPU ("a2", PROCESSOR_PPCA2,
 174             MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB | MASK_CMPB
 175             | MASK_NO_UPDATE)
 176 RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, MASK_SOFT_FLOAT)
 177 RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0)
 178 RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT | MASK_ISEL)
 179 RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64,
 180             MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
 181 RS6000_CPU ("e5500", PROCESSOR_PPCE5500,
 182             MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
 183 RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64
 184             | MASK_MFCRF | MASK_ISEL)
 185 RS6000_CPU ("860", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
 186 RS6000_CPU ("970", PROCESSOR_POWER4,
 187             POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
 188 RS6000_CPU ("cell", PROCESSOR_CELL,
 189             POWERPC_7400_MASK  | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
 190 RS6000_CPU ("ec603e", PROCESSOR_PPC603, MASK_SOFT_FLOAT)
 191 RS6000_CPU ("G3", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
 192 RS6000_CPU ("G4",  PROCESSOR_PPC7450, POWERPC_7400_MASK)
 193 RS6000_CPU ("G5", PROCESSOR_POWER4,
 194             POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
 195 RS6000_CPU ("titan", PROCESSOR_TITAN, MASK_MULHW | MASK_DLMZB)
 196 RS6000_CPU ("power3", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
 197 RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | MASK_PPC_GPOPT
 198             | MASK_PPC_GFXOPT | MASK_MFCRF)
 199 RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
 200             | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB)
 201 RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
 202             | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND)
 203 RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
 204             | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
 205             | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION)
 206 RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
 207             | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
 208             | MASK_CMPB | MASK_DFP | MASK_MFPGPR | MASK_RECIP_PRECISION)
 209 RS6000_CPU ("power7", PROCESSOR_POWER7,   /* Don't add MASK_ISEL by default */
 210             POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF
 211             | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD
 212             | MASK_VSX | MASK_RECIP_PRECISION | OPTION_MASK_UPPER_REGS_DF)
 213 RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER)
 214 RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER)
 215 RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
 216 RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64)
 217 RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER)
 218 RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64)