1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2013 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
27 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-attr.h"
41 #include "basic-block.h"
42 #include "diagnostic-core.h"
48 #include "target-def.h"
49 #include "common/common-target.h"
50 #include "langhooks.h"
53 #include "sched-int.h"
57 #include "tm-constrs.h"
60 #include "tree-vectorizer.h"
64 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
67 #include "gstab.h" /* for N_SLINE */
70 #ifndef TARGET_NO_PROTOTYPE
71 #define TARGET_NO_PROTOTYPE 0
74 #define min(A,B) ((A) < (B) ? (A) : (B))
75 #define max(A,B) ((A) > (B) ? (A) : (B))
77 /* Structure used to define the rs6000 stack */
78 typedef struct rs6000_stack
{
79 int reload_completed
; /* stack info won't change from here on */
80 int first_gp_reg_save
; /* first callee saved GP register used */
81 int first_fp_reg_save
; /* first callee saved FP register used */
82 int first_altivec_reg_save
; /* first callee saved AltiVec register used */
83 int lr_save_p
; /* true if the link reg needs to be saved */
84 int cr_save_p
; /* true if the CR reg needs to be saved */
85 unsigned int vrsave_mask
; /* mask of vec registers to save */
86 int push_p
; /* true if we need to allocate stack space */
87 int calls_p
; /* true if the function makes any calls */
88 int world_save_p
; /* true if we're saving *everything*:
89 r13-r31, cr, f14-f31, vrsave, v20-v31 */
90 enum rs6000_abi abi
; /* which ABI to use */
91 int gp_save_offset
; /* offset to save GP regs from initial SP */
92 int fp_save_offset
; /* offset to save FP regs from initial SP */
93 int altivec_save_offset
; /* offset to save AltiVec regs from initial SP */
94 int lr_save_offset
; /* offset to save LR from initial SP */
95 int cr_save_offset
; /* offset to save CR from initial SP */
96 int vrsave_save_offset
; /* offset to save VRSAVE from initial SP */
97 int spe_gp_save_offset
; /* offset to save spe 64-bit gprs */
98 int varargs_save_offset
; /* offset to save the varargs registers */
99 int ehrd_offset
; /* offset to EH return data */
100 int reg_size
; /* register size (4 or 8) */
101 HOST_WIDE_INT vars_size
; /* variable save area size */
102 int parm_size
; /* outgoing parameter size */
103 int save_size
; /* save area size */
104 int fixed_size
; /* fixed size of stack frame */
105 int gp_size
; /* size of saved GP registers */
106 int fp_size
; /* size of saved FP registers */
107 int altivec_size
; /* size of saved AltiVec registers */
108 int cr_size
; /* size to hold CR if not in save_size */
109 int vrsave_size
; /* size to hold VRSAVE if not in save_size */
110 int altivec_padding_size
; /* size of altivec alignment padding if
112 int spe_gp_size
; /* size of 64-bit GPR save size for SPE */
113 int spe_padding_size
;
114 HOST_WIDE_INT total_size
; /* total bytes allocated for stack */
115 int spe_64bit_regs_used
;
119 /* A C structure for machine-specific, per-function data.
120 This is added to the cfun structure. */
121 typedef struct GTY(()) machine_function
123 /* Some local-dynamic symbol. */
124 const char *some_ld_name
;
125 /* Whether the instruction chain has been scanned already. */
126 int insn_chain_scanned_p
;
127 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
128 int ra_needs_full_frame
;
129 /* Flags if __builtin_return_address (0) was used. */
131 /* Cache lr_save_p after expansion of builtin_eh_return. */
133 /* Whether we need to save the TOC to the reserved stack location in the
134 function prologue. */
135 bool save_toc_in_prologue
;
136 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
137 varargs save area. */
138 HOST_WIDE_INT varargs_save_offset
;
139 /* Temporary stack slot to use for SDmode copies. This slot is
140 64-bits wide and is allocated early enough so that the offset
141 does not overflow the 16-bit load/store offset field. */
142 rtx sdmode_stack_slot
;
145 /* Support targetm.vectorize.builtin_mask_for_load. */
146 static GTY(()) tree altivec_builtin_mask_for_load
;
148 /* Set to nonzero once AIX common-mode calls have been defined. */
149 static GTY(()) int common_mode_defined
;
151 /* Label number of label created for -mrelocatable, to call to so we can
152 get the address of the GOT section */
153 static int rs6000_pic_labelno
;
156 /* Counter for labels which are to be placed in .fixup. */
157 int fixuplabelno
= 0;
160 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
163 /* Specify the machine mode that pointers have. After generation of rtl, the
164 compiler makes no further distinction between pointers and any other objects
165 of this machine mode. The type is unsigned since not all things that
166 include rs6000.h also include machmode.h. */
167 unsigned rs6000_pmode
;
169 /* Width in bits of a pointer. */
170 unsigned rs6000_pointer_size
;
172 #ifdef HAVE_AS_GNU_ATTRIBUTE
173 /* Flag whether floating point values have been passed/returned. */
174 static bool rs6000_passes_float
;
175 /* Flag whether vector values have been passed/returned. */
176 static bool rs6000_passes_vector
;
177 /* Flag whether small (<= 8 byte) structures have been returned. */
178 static bool rs6000_returns_struct
;
181 /* Value is TRUE if register/mode pair is acceptable. */
182 bool rs6000_hard_regno_mode_ok_p
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
184 /* Maximum number of registers needed for a given register class and mode. */
185 unsigned char rs6000_class_max_nregs
[NUM_MACHINE_MODES
][LIM_REG_CLASSES
];
187 /* How many registers are needed for a given register and mode. */
188 unsigned char rs6000_hard_regno_nregs
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
190 /* Map register number to register class. */
191 enum reg_class rs6000_regno_regclass
[FIRST_PSEUDO_REGISTER
];
193 static int dbg_cost_ctrl
;
195 /* Built in types. */
196 tree rs6000_builtin_types
[RS6000_BTI_MAX
];
197 tree rs6000_builtin_decls
[RS6000_BUILTIN_COUNT
];
199 /* Flag to say the TOC is initialized */
201 char toc_label_name
[10];
203 /* Cached value of rs6000_variable_issue. This is cached in
204 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
205 static short cached_can_issue_more
;
207 static GTY(()) section
*read_only_data_section
;
208 static GTY(()) section
*private_data_section
;
209 static GTY(()) section
*tls_data_section
;
210 static GTY(()) section
*tls_private_data_section
;
211 static GTY(()) section
*read_only_private_data_section
;
212 static GTY(()) section
*sdata2_section
;
213 static GTY(()) section
*toc_section
;
215 struct builtin_description
217 const HOST_WIDE_INT mask
;
218 const enum insn_code icode
;
219 const char *const name
;
220 const enum rs6000_builtins code
;
223 /* Describe the vector unit used for modes. */
224 enum rs6000_vector rs6000_vector_unit
[NUM_MACHINE_MODES
];
225 enum rs6000_vector rs6000_vector_mem
[NUM_MACHINE_MODES
];
227 /* Register classes for various constraints that are based on the target
229 enum reg_class rs6000_constraints
[RS6000_CONSTRAINT_MAX
];
231 /* Describe the alignment of a vector. */
232 int rs6000_vector_align
[NUM_MACHINE_MODES
];
234 /* Map selected modes to types for builtins. */
235 static GTY(()) tree builtin_mode_to_type
[MAX_MACHINE_MODE
][2];
237 /* What modes to automatically generate reciprocal divide estimate (fre) and
238 reciprocal sqrt (frsqrte) for. */
239 unsigned char rs6000_recip_bits
[MAX_MACHINE_MODE
];
241 /* Masks to determine which reciprocal esitmate instructions to generate
243 enum rs6000_recip_mask
{
244 RECIP_SF_DIV
= 0x001, /* Use divide estimate */
245 RECIP_DF_DIV
= 0x002,
246 RECIP_V4SF_DIV
= 0x004,
247 RECIP_V2DF_DIV
= 0x008,
249 RECIP_SF_RSQRT
= 0x010, /* Use reciprocal sqrt estimate. */
250 RECIP_DF_RSQRT
= 0x020,
251 RECIP_V4SF_RSQRT
= 0x040,
252 RECIP_V2DF_RSQRT
= 0x080,
254 /* Various combination of flags for -mrecip=xxx. */
256 RECIP_ALL
= (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
257 | RECIP_V2DF_DIV
| RECIP_SF_RSQRT
| RECIP_DF_RSQRT
258 | RECIP_V4SF_RSQRT
| RECIP_V2DF_RSQRT
),
260 RECIP_HIGH_PRECISION
= RECIP_ALL
,
262 /* On low precision machines like the power5, don't enable double precision
263 reciprocal square root estimate, since it isn't accurate enough. */
264 RECIP_LOW_PRECISION
= (RECIP_ALL
& ~(RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
))
267 /* -mrecip options. */
270 const char *string
; /* option name */
271 unsigned int mask
; /* mask bits to set */
272 } recip_options
[] = {
273 { "all", RECIP_ALL
},
274 { "none", RECIP_NONE
},
275 { "div", (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
277 { "divf", (RECIP_SF_DIV
| RECIP_V4SF_DIV
) },
278 { "divd", (RECIP_DF_DIV
| RECIP_V2DF_DIV
) },
279 { "rsqrt", (RECIP_SF_RSQRT
| RECIP_DF_RSQRT
| RECIP_V4SF_RSQRT
280 | RECIP_V2DF_RSQRT
) },
281 { "rsqrtf", (RECIP_SF_RSQRT
| RECIP_V4SF_RSQRT
) },
282 { "rsqrtd", (RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
) },
285 /* Pointer to function (in rs6000-c.c) that can define or undefine target
286 macros that have changed. Languages that don't support the preprocessor
287 don't link in rs6000-c.c, so we can't call it directly. */
288 void (*rs6000_target_modify_macros_ptr
) (bool, HOST_WIDE_INT
, HOST_WIDE_INT
);
290 /* Simplfy register classes into simpler classifications. We assume
291 GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
292 check for standard register classes (gpr/floating/altivec/vsx) and
293 floating/vector classes (float/altivec/vsx). */
295 enum rs6000_reg_type
{
308 /* Map register class to register type. */
309 static enum rs6000_reg_type reg_class_to_reg_type
[N_REG_CLASSES
];
311 /* First/last register type for the 'normal' register types (i.e. general
312 purpose, floating point, altivec, and VSX registers). */
313 #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
315 #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
318 /* Register classes we care about in secondary reload or go if legitimate
319 address. We only need to worry about GPR, FPR, and Altivec registers here,
320 along an ANY field that is the OR of the 3 register classes. */
322 enum rs6000_reload_reg_type
{
323 RELOAD_REG_GPR
, /* General purpose registers. */
324 RELOAD_REG_FPR
, /* Traditional floating point regs. */
325 RELOAD_REG_VMX
, /* Altivec (VMX) registers. */
326 RELOAD_REG_ANY
, /* OR of GPR, FPR, Altivec masks. */
330 /* For setting up register classes, loop through the 3 register classes mapping
331 into real registers, and skip the ANY class, which is just an OR of the
333 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
334 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
336 /* Map reload register type to a register in the register class. */
337 struct reload_reg_map_type
{
338 const char *name
; /* Register class name. */
339 int reg
; /* Register in the register class. */
342 static const struct reload_reg_map_type reload_reg_map
[N_RELOAD_REG
] = {
343 { "Gpr", FIRST_GPR_REGNO
}, /* RELOAD_REG_GPR. */
344 { "Fpr", FIRST_FPR_REGNO
}, /* RELOAD_REG_FPR. */
345 { "VMX", FIRST_ALTIVEC_REGNO
}, /* RELOAD_REG_VMX. */
346 { "Any", -1 }, /* RELOAD_REG_ANY. */
349 /* Mask bits for each register class, indexed per mode. Historically the
350 compiler has been more restrictive which types can do PRE_MODIFY instead of
351 PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */
352 typedef unsigned char addr_mask_type
;
354 #define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */
355 #define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */
356 #define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */
357 #define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
358 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */
359 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */
361 /* Register type masks based on the type, of valid addressing modes. */
362 struct rs6000_reg_addr
{
363 enum insn_code reload_load
; /* INSN to reload for loading. */
364 enum insn_code reload_store
; /* INSN to reload for storing. */
365 enum insn_code reload_fpr_gpr
; /* INSN to move from FPR to GPR. */
366 enum insn_code reload_gpr_vsx
; /* INSN to move from GPR to VSX. */
367 enum insn_code reload_vsx_gpr
; /* INSN to move from VSX to GPR. */
368 addr_mask_type addr_mask
[(int)N_RELOAD_REG
]; /* Valid address masks. */
371 static struct rs6000_reg_addr reg_addr
[NUM_MACHINE_MODES
];
373 /* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */
375 mode_supports_pre_incdec_p (enum machine_mode mode
)
377 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_PRE_INCDEC
)
381 /* Helper function to say whether a mode supports PRE_MODIFY. */
383 mode_supports_pre_modify_p (enum machine_mode mode
)
385 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_PRE_MODIFY
)
390 /* Target cpu costs. */
392 struct processor_costs
{
393 const int mulsi
; /* cost of SImode multiplication. */
394 const int mulsi_const
; /* cost of SImode multiplication by constant. */
395 const int mulsi_const9
; /* cost of SImode mult by short constant. */
396 const int muldi
; /* cost of DImode multiplication. */
397 const int divsi
; /* cost of SImode division. */
398 const int divdi
; /* cost of DImode division. */
399 const int fp
; /* cost of simple SFmode and DFmode insns. */
400 const int dmul
; /* cost of DFmode multiplication (and fmadd). */
401 const int sdiv
; /* cost of SFmode division (fdivs). */
402 const int ddiv
; /* cost of DFmode division (fdiv). */
403 const int cache_line_size
; /* cache line size in bytes. */
404 const int l1_cache_size
; /* size of l1 cache, in kilobytes. */
405 const int l2_cache_size
; /* size of l2 cache, in kilobytes. */
406 const int simultaneous_prefetches
; /* number of parallel prefetch
410 const struct processor_costs
*rs6000_cost
;
412 /* Processor costs (relative to an add) */
414 /* Instruction size costs on 32bit processors. */
416 struct processor_costs size32_cost
= {
417 COSTS_N_INSNS (1), /* mulsi */
418 COSTS_N_INSNS (1), /* mulsi_const */
419 COSTS_N_INSNS (1), /* mulsi_const9 */
420 COSTS_N_INSNS (1), /* muldi */
421 COSTS_N_INSNS (1), /* divsi */
422 COSTS_N_INSNS (1), /* divdi */
423 COSTS_N_INSNS (1), /* fp */
424 COSTS_N_INSNS (1), /* dmul */
425 COSTS_N_INSNS (1), /* sdiv */
426 COSTS_N_INSNS (1), /* ddiv */
433 /* Instruction size costs on 64bit processors. */
435 struct processor_costs size64_cost
= {
436 COSTS_N_INSNS (1), /* mulsi */
437 COSTS_N_INSNS (1), /* mulsi_const */
438 COSTS_N_INSNS (1), /* mulsi_const9 */
439 COSTS_N_INSNS (1), /* muldi */
440 COSTS_N_INSNS (1), /* divsi */
441 COSTS_N_INSNS (1), /* divdi */
442 COSTS_N_INSNS (1), /* fp */
443 COSTS_N_INSNS (1), /* dmul */
444 COSTS_N_INSNS (1), /* sdiv */
445 COSTS_N_INSNS (1), /* ddiv */
452 /* Instruction costs on RS64A processors. */
454 struct processor_costs rs64a_cost
= {
455 COSTS_N_INSNS (20), /* mulsi */
456 COSTS_N_INSNS (12), /* mulsi_const */
457 COSTS_N_INSNS (8), /* mulsi_const9 */
458 COSTS_N_INSNS (34), /* muldi */
459 COSTS_N_INSNS (65), /* divsi */
460 COSTS_N_INSNS (67), /* divdi */
461 COSTS_N_INSNS (4), /* fp */
462 COSTS_N_INSNS (4), /* dmul */
463 COSTS_N_INSNS (31), /* sdiv */
464 COSTS_N_INSNS (31), /* ddiv */
465 128, /* cache line size */
471 /* Instruction costs on MPCCORE processors. */
473 struct processor_costs mpccore_cost
= {
474 COSTS_N_INSNS (2), /* mulsi */
475 COSTS_N_INSNS (2), /* mulsi_const */
476 COSTS_N_INSNS (2), /* mulsi_const9 */
477 COSTS_N_INSNS (2), /* muldi */
478 COSTS_N_INSNS (6), /* divsi */
479 COSTS_N_INSNS (6), /* divdi */
480 COSTS_N_INSNS (4), /* fp */
481 COSTS_N_INSNS (5), /* dmul */
482 COSTS_N_INSNS (10), /* sdiv */
483 COSTS_N_INSNS (17), /* ddiv */
484 32, /* cache line size */
490 /* Instruction costs on PPC403 processors. */
492 struct processor_costs ppc403_cost
= {
493 COSTS_N_INSNS (4), /* mulsi */
494 COSTS_N_INSNS (4), /* mulsi_const */
495 COSTS_N_INSNS (4), /* mulsi_const9 */
496 COSTS_N_INSNS (4), /* muldi */
497 COSTS_N_INSNS (33), /* divsi */
498 COSTS_N_INSNS (33), /* divdi */
499 COSTS_N_INSNS (11), /* fp */
500 COSTS_N_INSNS (11), /* dmul */
501 COSTS_N_INSNS (11), /* sdiv */
502 COSTS_N_INSNS (11), /* ddiv */
503 32, /* cache line size */
509 /* Instruction costs on PPC405 processors. */
511 struct processor_costs ppc405_cost
= {
512 COSTS_N_INSNS (5), /* mulsi */
513 COSTS_N_INSNS (4), /* mulsi_const */
514 COSTS_N_INSNS (3), /* mulsi_const9 */
515 COSTS_N_INSNS (5), /* muldi */
516 COSTS_N_INSNS (35), /* divsi */
517 COSTS_N_INSNS (35), /* divdi */
518 COSTS_N_INSNS (11), /* fp */
519 COSTS_N_INSNS (11), /* dmul */
520 COSTS_N_INSNS (11), /* sdiv */
521 COSTS_N_INSNS (11), /* ddiv */
522 32, /* cache line size */
528 /* Instruction costs on PPC440 processors. */
530 struct processor_costs ppc440_cost
= {
531 COSTS_N_INSNS (3), /* mulsi */
532 COSTS_N_INSNS (2), /* mulsi_const */
533 COSTS_N_INSNS (2), /* mulsi_const9 */
534 COSTS_N_INSNS (3), /* muldi */
535 COSTS_N_INSNS (34), /* divsi */
536 COSTS_N_INSNS (34), /* divdi */
537 COSTS_N_INSNS (5), /* fp */
538 COSTS_N_INSNS (5), /* dmul */
539 COSTS_N_INSNS (19), /* sdiv */
540 COSTS_N_INSNS (33), /* ddiv */
541 32, /* cache line size */
547 /* Instruction costs on PPC476 processors. */
549 struct processor_costs ppc476_cost
= {
550 COSTS_N_INSNS (4), /* mulsi */
551 COSTS_N_INSNS (4), /* mulsi_const */
552 COSTS_N_INSNS (4), /* mulsi_const9 */
553 COSTS_N_INSNS (4), /* muldi */
554 COSTS_N_INSNS (11), /* divsi */
555 COSTS_N_INSNS (11), /* divdi */
556 COSTS_N_INSNS (6), /* fp */
557 COSTS_N_INSNS (6), /* dmul */
558 COSTS_N_INSNS (19), /* sdiv */
559 COSTS_N_INSNS (33), /* ddiv */
560 32, /* l1 cache line size */
566 /* Instruction costs on PPC601 processors. */
568 struct processor_costs ppc601_cost
= {
569 COSTS_N_INSNS (5), /* mulsi */
570 COSTS_N_INSNS (5), /* mulsi_const */
571 COSTS_N_INSNS (5), /* mulsi_const9 */
572 COSTS_N_INSNS (5), /* muldi */
573 COSTS_N_INSNS (36), /* divsi */
574 COSTS_N_INSNS (36), /* divdi */
575 COSTS_N_INSNS (4), /* fp */
576 COSTS_N_INSNS (5), /* dmul */
577 COSTS_N_INSNS (17), /* sdiv */
578 COSTS_N_INSNS (31), /* ddiv */
579 32, /* cache line size */
585 /* Instruction costs on PPC603 processors. */
587 struct processor_costs ppc603_cost
= {
588 COSTS_N_INSNS (5), /* mulsi */
589 COSTS_N_INSNS (3), /* mulsi_const */
590 COSTS_N_INSNS (2), /* mulsi_const9 */
591 COSTS_N_INSNS (5), /* muldi */
592 COSTS_N_INSNS (37), /* divsi */
593 COSTS_N_INSNS (37), /* divdi */
594 COSTS_N_INSNS (3), /* fp */
595 COSTS_N_INSNS (4), /* dmul */
596 COSTS_N_INSNS (18), /* sdiv */
597 COSTS_N_INSNS (33), /* ddiv */
598 32, /* cache line size */
604 /* Instruction costs on PPC604 processors. */
606 struct processor_costs ppc604_cost
= {
607 COSTS_N_INSNS (4), /* mulsi */
608 COSTS_N_INSNS (4), /* mulsi_const */
609 COSTS_N_INSNS (4), /* mulsi_const9 */
610 COSTS_N_INSNS (4), /* muldi */
611 COSTS_N_INSNS (20), /* divsi */
612 COSTS_N_INSNS (20), /* divdi */
613 COSTS_N_INSNS (3), /* fp */
614 COSTS_N_INSNS (3), /* dmul */
615 COSTS_N_INSNS (18), /* sdiv */
616 COSTS_N_INSNS (32), /* ddiv */
617 32, /* cache line size */
623 /* Instruction costs on PPC604e processors. */
625 struct processor_costs ppc604e_cost
= {
626 COSTS_N_INSNS (2), /* mulsi */
627 COSTS_N_INSNS (2), /* mulsi_const */
628 COSTS_N_INSNS (2), /* mulsi_const9 */
629 COSTS_N_INSNS (2), /* muldi */
630 COSTS_N_INSNS (20), /* divsi */
631 COSTS_N_INSNS (20), /* divdi */
632 COSTS_N_INSNS (3), /* fp */
633 COSTS_N_INSNS (3), /* dmul */
634 COSTS_N_INSNS (18), /* sdiv */
635 COSTS_N_INSNS (32), /* ddiv */
636 32, /* cache line size */
642 /* Instruction costs on PPC620 processors. */
644 struct processor_costs ppc620_cost
= {
645 COSTS_N_INSNS (5), /* mulsi */
646 COSTS_N_INSNS (4), /* mulsi_const */
647 COSTS_N_INSNS (3), /* mulsi_const9 */
648 COSTS_N_INSNS (7), /* muldi */
649 COSTS_N_INSNS (21), /* divsi */
650 COSTS_N_INSNS (37), /* divdi */
651 COSTS_N_INSNS (3), /* fp */
652 COSTS_N_INSNS (3), /* dmul */
653 COSTS_N_INSNS (18), /* sdiv */
654 COSTS_N_INSNS (32), /* ddiv */
655 128, /* cache line size */
661 /* Instruction costs on PPC630 processors. */
663 struct processor_costs ppc630_cost
= {
664 COSTS_N_INSNS (5), /* mulsi */
665 COSTS_N_INSNS (4), /* mulsi_const */
666 COSTS_N_INSNS (3), /* mulsi_const9 */
667 COSTS_N_INSNS (7), /* muldi */
668 COSTS_N_INSNS (21), /* divsi */
669 COSTS_N_INSNS (37), /* divdi */
670 COSTS_N_INSNS (3), /* fp */
671 COSTS_N_INSNS (3), /* dmul */
672 COSTS_N_INSNS (17), /* sdiv */
673 COSTS_N_INSNS (21), /* ddiv */
674 128, /* cache line size */
680 /* Instruction costs on Cell processor. */
681 /* COSTS_N_INSNS (1) ~ one add. */
683 struct processor_costs ppccell_cost
= {
684 COSTS_N_INSNS (9/2)+2, /* mulsi */
685 COSTS_N_INSNS (6/2), /* mulsi_const */
686 COSTS_N_INSNS (6/2), /* mulsi_const9 */
687 COSTS_N_INSNS (15/2)+2, /* muldi */
688 COSTS_N_INSNS (38/2), /* divsi */
689 COSTS_N_INSNS (70/2), /* divdi */
690 COSTS_N_INSNS (10/2), /* fp */
691 COSTS_N_INSNS (10/2), /* dmul */
692 COSTS_N_INSNS (74/2), /* sdiv */
693 COSTS_N_INSNS (74/2), /* ddiv */
694 128, /* cache line size */
700 /* Instruction costs on PPC750 and PPC7400 processors. */
702 struct processor_costs ppc750_cost
= {
703 COSTS_N_INSNS (5), /* mulsi */
704 COSTS_N_INSNS (3), /* mulsi_const */
705 COSTS_N_INSNS (2), /* mulsi_const9 */
706 COSTS_N_INSNS (5), /* muldi */
707 COSTS_N_INSNS (17), /* divsi */
708 COSTS_N_INSNS (17), /* divdi */
709 COSTS_N_INSNS (3), /* fp */
710 COSTS_N_INSNS (3), /* dmul */
711 COSTS_N_INSNS (17), /* sdiv */
712 COSTS_N_INSNS (31), /* ddiv */
713 32, /* cache line size */
719 /* Instruction costs on PPC7450 processors. */
721 struct processor_costs ppc7450_cost
= {
722 COSTS_N_INSNS (4), /* mulsi */
723 COSTS_N_INSNS (3), /* mulsi_const */
724 COSTS_N_INSNS (3), /* mulsi_const9 */
725 COSTS_N_INSNS (4), /* muldi */
726 COSTS_N_INSNS (23), /* divsi */
727 COSTS_N_INSNS (23), /* divdi */
728 COSTS_N_INSNS (5), /* fp */
729 COSTS_N_INSNS (5), /* dmul */
730 COSTS_N_INSNS (21), /* sdiv */
731 COSTS_N_INSNS (35), /* ddiv */
732 32, /* cache line size */
738 /* Instruction costs on PPC8540 processors. */
740 struct processor_costs ppc8540_cost
= {
741 COSTS_N_INSNS (4), /* mulsi */
742 COSTS_N_INSNS (4), /* mulsi_const */
743 COSTS_N_INSNS (4), /* mulsi_const9 */
744 COSTS_N_INSNS (4), /* muldi */
745 COSTS_N_INSNS (19), /* divsi */
746 COSTS_N_INSNS (19), /* divdi */
747 COSTS_N_INSNS (4), /* fp */
748 COSTS_N_INSNS (4), /* dmul */
749 COSTS_N_INSNS (29), /* sdiv */
750 COSTS_N_INSNS (29), /* ddiv */
751 32, /* cache line size */
754 1, /* prefetch streams /*/
757 /* Instruction costs on E300C2 and E300C3 cores. */
759 struct processor_costs ppce300c2c3_cost
= {
760 COSTS_N_INSNS (4), /* mulsi */
761 COSTS_N_INSNS (4), /* mulsi_const */
762 COSTS_N_INSNS (4), /* mulsi_const9 */
763 COSTS_N_INSNS (4), /* muldi */
764 COSTS_N_INSNS (19), /* divsi */
765 COSTS_N_INSNS (19), /* divdi */
766 COSTS_N_INSNS (3), /* fp */
767 COSTS_N_INSNS (4), /* dmul */
768 COSTS_N_INSNS (18), /* sdiv */
769 COSTS_N_INSNS (33), /* ddiv */
773 1, /* prefetch streams /*/
776 /* Instruction costs on PPCE500MC processors. */
778 struct processor_costs ppce500mc_cost
= {
779 COSTS_N_INSNS (4), /* mulsi */
780 COSTS_N_INSNS (4), /* mulsi_const */
781 COSTS_N_INSNS (4), /* mulsi_const9 */
782 COSTS_N_INSNS (4), /* muldi */
783 COSTS_N_INSNS (14), /* divsi */
784 COSTS_N_INSNS (14), /* divdi */
785 COSTS_N_INSNS (8), /* fp */
786 COSTS_N_INSNS (10), /* dmul */
787 COSTS_N_INSNS (36), /* sdiv */
788 COSTS_N_INSNS (66), /* ddiv */
789 64, /* cache line size */
792 1, /* prefetch streams /*/
795 /* Instruction costs on PPCE500MC64 processors. */
797 struct processor_costs ppce500mc64_cost
= {
798 COSTS_N_INSNS (4), /* mulsi */
799 COSTS_N_INSNS (4), /* mulsi_const */
800 COSTS_N_INSNS (4), /* mulsi_const9 */
801 COSTS_N_INSNS (4), /* muldi */
802 COSTS_N_INSNS (14), /* divsi */
803 COSTS_N_INSNS (14), /* divdi */
804 COSTS_N_INSNS (4), /* fp */
805 COSTS_N_INSNS (10), /* dmul */
806 COSTS_N_INSNS (36), /* sdiv */
807 COSTS_N_INSNS (66), /* ddiv */
808 64, /* cache line size */
811 1, /* prefetch streams /*/
814 /* Instruction costs on PPCE5500 processors. */
816 struct processor_costs ppce5500_cost
= {
817 COSTS_N_INSNS (5), /* mulsi */
818 COSTS_N_INSNS (5), /* mulsi_const */
819 COSTS_N_INSNS (4), /* mulsi_const9 */
820 COSTS_N_INSNS (5), /* muldi */
821 COSTS_N_INSNS (14), /* divsi */
822 COSTS_N_INSNS (14), /* divdi */
823 COSTS_N_INSNS (7), /* fp */
824 COSTS_N_INSNS (10), /* dmul */
825 COSTS_N_INSNS (36), /* sdiv */
826 COSTS_N_INSNS (66), /* ddiv */
827 64, /* cache line size */
830 1, /* prefetch streams /*/
833 /* Instruction costs on PPCE6500 processors. */
835 struct processor_costs ppce6500_cost
= {
836 COSTS_N_INSNS (5), /* mulsi */
837 COSTS_N_INSNS (5), /* mulsi_const */
838 COSTS_N_INSNS (4), /* mulsi_const9 */
839 COSTS_N_INSNS (5), /* muldi */
840 COSTS_N_INSNS (14), /* divsi */
841 COSTS_N_INSNS (14), /* divdi */
842 COSTS_N_INSNS (7), /* fp */
843 COSTS_N_INSNS (10), /* dmul */
844 COSTS_N_INSNS (36), /* sdiv */
845 COSTS_N_INSNS (66), /* ddiv */
846 64, /* cache line size */
849 1, /* prefetch streams /*/
852 /* Instruction costs on AppliedMicro Titan processors. */
854 struct processor_costs titan_cost
= {
855 COSTS_N_INSNS (5), /* mulsi */
856 COSTS_N_INSNS (5), /* mulsi_const */
857 COSTS_N_INSNS (5), /* mulsi_const9 */
858 COSTS_N_INSNS (5), /* muldi */
859 COSTS_N_INSNS (18), /* divsi */
860 COSTS_N_INSNS (18), /* divdi */
861 COSTS_N_INSNS (10), /* fp */
862 COSTS_N_INSNS (10), /* dmul */
863 COSTS_N_INSNS (46), /* sdiv */
864 COSTS_N_INSNS (72), /* ddiv */
865 32, /* cache line size */
868 1, /* prefetch streams /*/
871 /* Instruction costs on POWER4 and POWER5 processors. */
873 struct processor_costs power4_cost
= {
874 COSTS_N_INSNS (3), /* mulsi */
875 COSTS_N_INSNS (2), /* mulsi_const */
876 COSTS_N_INSNS (2), /* mulsi_const9 */
877 COSTS_N_INSNS (4), /* muldi */
878 COSTS_N_INSNS (18), /* divsi */
879 COSTS_N_INSNS (34), /* divdi */
880 COSTS_N_INSNS (3), /* fp */
881 COSTS_N_INSNS (3), /* dmul */
882 COSTS_N_INSNS (17), /* sdiv */
883 COSTS_N_INSNS (17), /* ddiv */
884 128, /* cache line size */
887 8, /* prefetch streams /*/
890 /* Instruction costs on POWER6 processors. */
892 struct processor_costs power6_cost
= {
893 COSTS_N_INSNS (8), /* mulsi */
894 COSTS_N_INSNS (8), /* mulsi_const */
895 COSTS_N_INSNS (8), /* mulsi_const9 */
896 COSTS_N_INSNS (8), /* muldi */
897 COSTS_N_INSNS (22), /* divsi */
898 COSTS_N_INSNS (28), /* divdi */
899 COSTS_N_INSNS (3), /* fp */
900 COSTS_N_INSNS (3), /* dmul */
901 COSTS_N_INSNS (13), /* sdiv */
902 COSTS_N_INSNS (16), /* ddiv */
903 128, /* cache line size */
906 16, /* prefetch streams */
909 /* Instruction costs on POWER7 processors. */
911 struct processor_costs power7_cost
= {
912 COSTS_N_INSNS (2), /* mulsi */
913 COSTS_N_INSNS (2), /* mulsi_const */
914 COSTS_N_INSNS (2), /* mulsi_const9 */
915 COSTS_N_INSNS (2), /* muldi */
916 COSTS_N_INSNS (18), /* divsi */
917 COSTS_N_INSNS (34), /* divdi */
918 COSTS_N_INSNS (3), /* fp */
919 COSTS_N_INSNS (3), /* dmul */
920 COSTS_N_INSNS (13), /* sdiv */
921 COSTS_N_INSNS (16), /* ddiv */
922 128, /* cache line size */
925 12, /* prefetch streams */
928 /* Instruction costs on POWER8 processors. */
930 struct processor_costs power8_cost
= {
931 COSTS_N_INSNS (3), /* mulsi */
932 COSTS_N_INSNS (3), /* mulsi_const */
933 COSTS_N_INSNS (3), /* mulsi_const9 */
934 COSTS_N_INSNS (3), /* muldi */
935 COSTS_N_INSNS (19), /* divsi */
936 COSTS_N_INSNS (35), /* divdi */
937 COSTS_N_INSNS (3), /* fp */
938 COSTS_N_INSNS (3), /* dmul */
939 COSTS_N_INSNS (14), /* sdiv */
940 COSTS_N_INSNS (17), /* ddiv */
941 128, /* cache line size */
944 12, /* prefetch streams */
947 /* Instruction costs on POWER A2 processors. */
949 struct processor_costs ppca2_cost
= {
950 COSTS_N_INSNS (16), /* mulsi */
951 COSTS_N_INSNS (16), /* mulsi_const */
952 COSTS_N_INSNS (16), /* mulsi_const9 */
953 COSTS_N_INSNS (16), /* muldi */
954 COSTS_N_INSNS (22), /* divsi */
955 COSTS_N_INSNS (28), /* divdi */
956 COSTS_N_INSNS (3), /* fp */
957 COSTS_N_INSNS (3), /* dmul */
958 COSTS_N_INSNS (59), /* sdiv */
959 COSTS_N_INSNS (72), /* ddiv */
963 16, /* prefetch streams */
967 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
968 #undef RS6000_BUILTIN_1
969 #undef RS6000_BUILTIN_2
970 #undef RS6000_BUILTIN_3
971 #undef RS6000_BUILTIN_A
972 #undef RS6000_BUILTIN_D
973 #undef RS6000_BUILTIN_E
974 #undef RS6000_BUILTIN_H
975 #undef RS6000_BUILTIN_P
976 #undef RS6000_BUILTIN_Q
977 #undef RS6000_BUILTIN_S
978 #undef RS6000_BUILTIN_X
980 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
981 { NAME, ICODE, MASK, ATTR },
983 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
984 { NAME, ICODE, MASK, ATTR },
986 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
987 { NAME, ICODE, MASK, ATTR },
989 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
990 { NAME, ICODE, MASK, ATTR },
992 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
993 { NAME, ICODE, MASK, ATTR },
995 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
996 { NAME, ICODE, MASK, ATTR },
998 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
999 { NAME, ICODE, MASK, ATTR },
1001 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
1002 { NAME, ICODE, MASK, ATTR },
1004 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
1005 { NAME, ICODE, MASK, ATTR },
1007 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
1008 { NAME, ICODE, MASK, ATTR },
1010 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
1011 { NAME, ICODE, MASK, ATTR },
1013 struct rs6000_builtin_info_type
{
1015 const enum insn_code icode
;
1016 const HOST_WIDE_INT mask
;
1017 const unsigned attr
;
1020 static const struct rs6000_builtin_info_type rs6000_builtin_info
[] =
1022 #include "rs6000-builtin.def"
1025 #undef RS6000_BUILTIN_1
1026 #undef RS6000_BUILTIN_2
1027 #undef RS6000_BUILTIN_3
1028 #undef RS6000_BUILTIN_A
1029 #undef RS6000_BUILTIN_D
1030 #undef RS6000_BUILTIN_E
1031 #undef RS6000_BUILTIN_H
1032 #undef RS6000_BUILTIN_P
1033 #undef RS6000_BUILTIN_Q
1034 #undef RS6000_BUILTIN_S
1035 #undef RS6000_BUILTIN_X
1037 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
1038 static tree (*rs6000_veclib_handler
) (tree
, tree
, tree
);
1041 static bool rs6000_debug_legitimate_address_p (enum machine_mode
, rtx
, bool);
1042 static bool spe_func_has_64bit_regs_p (void);
1043 static struct machine_function
* rs6000_init_machine_status (void);
1044 static int rs6000_ra_ever_killed (void);
1045 static tree
rs6000_handle_longcall_attribute (tree
*, tree
, tree
, int, bool *);
1046 static tree
rs6000_handle_altivec_attribute (tree
*, tree
, tree
, int, bool *);
1047 static tree
rs6000_handle_struct_attribute (tree
*, tree
, tree
, int, bool *);
1048 static tree
rs6000_builtin_vectorized_libmass (tree
, tree
, tree
);
1049 static rtx
rs6000_emit_set_long_const (rtx
, HOST_WIDE_INT
, HOST_WIDE_INT
);
1050 static int rs6000_memory_move_cost (enum machine_mode
, reg_class_t
, bool);
1051 static bool rs6000_debug_rtx_costs (rtx
, int, int, int, int *, bool);
1052 static int rs6000_debug_address_cost (rtx
, enum machine_mode
, addr_space_t
,
1054 static int rs6000_debug_adjust_cost (rtx
, rtx
, rtx
, int);
1055 static bool is_microcoded_insn (rtx
);
1056 static bool is_nonpipeline_insn (rtx
);
1057 static bool is_cracked_insn (rtx
);
1058 static bool is_load_insn (rtx
, rtx
*);
1059 static bool is_store_insn (rtx
, rtx
*);
1060 static bool set_to_load_agen (rtx
,rtx
);
1061 static bool insn_terminates_group_p (rtx
, enum group_termination
);
1062 static bool insn_must_be_first_in_group (rtx
);
1063 static bool insn_must_be_last_in_group (rtx
);
1064 static void altivec_init_builtins (void);
1065 static tree
builtin_function_type (enum machine_mode
, enum machine_mode
,
1066 enum machine_mode
, enum machine_mode
,
1067 enum rs6000_builtins
, const char *name
);
1068 static void rs6000_common_init_builtins (void);
1069 static void paired_init_builtins (void);
1070 static rtx
paired_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
1071 static void spe_init_builtins (void);
1072 static void htm_init_builtins (void);
1073 static rtx
spe_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
1074 static rtx
spe_expand_evsel_builtin (enum insn_code
, tree
, rtx
);
1075 static int rs6000_emit_int_cmove (rtx
, rtx
, rtx
, rtx
);
1076 static rs6000_stack_t
*rs6000_stack_info (void);
1077 static void is_altivec_return_reg (rtx
, void *);
1078 int easy_vector_constant (rtx
, enum machine_mode
);
1079 static rtx
rs6000_debug_legitimize_address (rtx
, rtx
, enum machine_mode
);
1080 static rtx
rs6000_legitimize_tls_address (rtx
, enum tls_model
);
1081 static int rs6000_tls_symbol_ref_1 (rtx
*, void *);
1082 static int rs6000_get_some_local_dynamic_name_1 (rtx
*, void *);
1083 static rtx
rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*, const_tree
,
1086 static void macho_branch_islands (void);
1088 static rtx
rs6000_legitimize_reload_address (rtx
, enum machine_mode
, int, int,
1090 static rtx
rs6000_debug_legitimize_reload_address (rtx
, enum machine_mode
, int,
1092 static bool rs6000_mode_dependent_address (const_rtx
);
1093 static bool rs6000_debug_mode_dependent_address (const_rtx
);
1094 static enum reg_class
rs6000_secondary_reload_class (enum reg_class
,
1095 enum machine_mode
, rtx
);
1096 static enum reg_class
rs6000_debug_secondary_reload_class (enum reg_class
,
1099 static enum reg_class
rs6000_preferred_reload_class (rtx
, enum reg_class
);
1100 static enum reg_class
rs6000_debug_preferred_reload_class (rtx
,
1102 static bool rs6000_secondary_memory_needed (enum reg_class
, enum reg_class
,
1104 static bool rs6000_debug_secondary_memory_needed (enum reg_class
,
1107 static bool rs6000_cannot_change_mode_class (enum machine_mode
,
1110 static bool rs6000_debug_cannot_change_mode_class (enum machine_mode
,
1113 static bool rs6000_save_toc_in_prologue_p (void);
1115 rtx (*rs6000_legitimize_reload_address_ptr
) (rtx
, enum machine_mode
, int, int,
1117 = rs6000_legitimize_reload_address
;
1119 static bool (*rs6000_mode_dependent_address_ptr
) (const_rtx
)
1120 = rs6000_mode_dependent_address
;
1122 enum reg_class (*rs6000_secondary_reload_class_ptr
) (enum reg_class
,
1123 enum machine_mode
, rtx
)
1124 = rs6000_secondary_reload_class
;
1126 enum reg_class (*rs6000_preferred_reload_class_ptr
) (rtx
, enum reg_class
)
1127 = rs6000_preferred_reload_class
;
1129 bool (*rs6000_secondary_memory_needed_ptr
) (enum reg_class
, enum reg_class
,
1131 = rs6000_secondary_memory_needed
;
1133 bool (*rs6000_cannot_change_mode_class_ptr
) (enum machine_mode
,
1136 = rs6000_cannot_change_mode_class
;
1138 const int INSN_NOT_AVAILABLE
= -1;
1140 static void rs6000_print_isa_options (FILE *, int, const char *,
1142 static void rs6000_print_builtin_options (FILE *, int, const char *,
1145 static enum rs6000_reg_type
register_to_reg_type (rtx
, bool *);
1146 static bool rs6000_secondary_reload_move (enum rs6000_reg_type
,
1147 enum rs6000_reg_type
,
1149 secondary_reload_info
*,
1152 /* Hash table stuff for keeping track of TOC entries. */
1154 struct GTY(()) toc_hash_struct
1156 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1157 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1159 enum machine_mode key_mode
;
1163 static GTY ((param_is (struct toc_hash_struct
))) htab_t toc_hash_table
;
1165 /* Hash table to keep track of the argument types for builtin functions. */
1167 struct GTY(()) builtin_hash_struct
1170 enum machine_mode mode
[4]; /* return value + 3 arguments. */
1171 unsigned char uns_p
[4]; /* and whether the types are unsigned. */
1174 static GTY ((param_is (struct builtin_hash_struct
))) htab_t builtin_hash_table
;
1177 /* Default register names. */
1178 char rs6000_reg_names
[][8] =
1180 "0", "1", "2", "3", "4", "5", "6", "7",
1181 "8", "9", "10", "11", "12", "13", "14", "15",
1182 "16", "17", "18", "19", "20", "21", "22", "23",
1183 "24", "25", "26", "27", "28", "29", "30", "31",
1184 "0", "1", "2", "3", "4", "5", "6", "7",
1185 "8", "9", "10", "11", "12", "13", "14", "15",
1186 "16", "17", "18", "19", "20", "21", "22", "23",
1187 "24", "25", "26", "27", "28", "29", "30", "31",
1188 "mq", "lr", "ctr","ap",
1189 "0", "1", "2", "3", "4", "5", "6", "7",
1191 /* AltiVec registers. */
1192 "0", "1", "2", "3", "4", "5", "6", "7",
1193 "8", "9", "10", "11", "12", "13", "14", "15",
1194 "16", "17", "18", "19", "20", "21", "22", "23",
1195 "24", "25", "26", "27", "28", "29", "30", "31",
1197 /* SPE registers. */
1198 "spe_acc", "spefscr",
1199 /* Soft frame pointer. */
1201 /* HTM SPR registers. */
1202 "tfhar", "tfiar", "texasr"
1205 #ifdef TARGET_REGNAMES
1206 static const char alt_reg_names
[][8] =
1208 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1209 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1210 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1211 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1212 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1213 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1214 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1215 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1216 "mq", "lr", "ctr", "ap",
1217 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1219 /* AltiVec registers. */
1220 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1221 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1222 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1223 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1225 /* SPE registers. */
1226 "spe_acc", "spefscr",
1227 /* Soft frame pointer. */
1229 /* HTM SPR registers. */
1230 "tfhar", "tfiar", "texasr"
1234 /* Table of valid machine attributes. */
1236 static const struct attribute_spec rs6000_attribute_table
[] =
1238 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
1239 affects_type_identity } */
1240 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute
,
1242 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1244 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1246 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1248 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1250 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1251 SUBTARGET_ATTRIBUTE_TABLE
,
1253 { NULL
, 0, 0, false, false, false, NULL
, false }
1256 #ifndef TARGET_PROFILE_KERNEL
1257 #define TARGET_PROFILE_KERNEL 0
1260 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1261 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1263 /* Initialize the GCC target structure. */
1264 #undef TARGET_ATTRIBUTE_TABLE
1265 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1266 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1267 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1268 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1269 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1271 #undef TARGET_ASM_ALIGNED_DI_OP
1272 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1274 /* Default unaligned ops are only provided for ELF. Find the ops needed
1275 for non-ELF systems. */
1276 #ifndef OBJECT_FORMAT_ELF
1278 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1280 #undef TARGET_ASM_UNALIGNED_HI_OP
1281 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1282 #undef TARGET_ASM_UNALIGNED_SI_OP
1283 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1284 #undef TARGET_ASM_UNALIGNED_DI_OP
1285 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1288 #undef TARGET_ASM_UNALIGNED_HI_OP
1289 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1290 #undef TARGET_ASM_UNALIGNED_SI_OP
1291 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1292 #undef TARGET_ASM_UNALIGNED_DI_OP
1293 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1294 #undef TARGET_ASM_ALIGNED_DI_OP
1295 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1299 /* This hook deals with fixups for relocatable code and DI-mode objects
1301 #undef TARGET_ASM_INTEGER
1302 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1304 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1305 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1306 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1309 #undef TARGET_SET_UP_BY_PROLOGUE
1310 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1312 #undef TARGET_HAVE_TLS
1313 #define TARGET_HAVE_TLS HAVE_AS_TLS
1315 #undef TARGET_CANNOT_FORCE_CONST_MEM
1316 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1318 #undef TARGET_DELEGITIMIZE_ADDRESS
1319 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1321 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1322 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1324 #undef TARGET_ASM_FUNCTION_PROLOGUE
1325 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1326 #undef TARGET_ASM_FUNCTION_EPILOGUE
1327 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1329 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1330 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1332 #undef TARGET_LEGITIMIZE_ADDRESS
1333 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1335 #undef TARGET_SCHED_VARIABLE_ISSUE
1336 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1338 #undef TARGET_SCHED_ISSUE_RATE
1339 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1340 #undef TARGET_SCHED_ADJUST_COST
1341 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1342 #undef TARGET_SCHED_ADJUST_PRIORITY
1343 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1344 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1345 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1346 #undef TARGET_SCHED_INIT
1347 #define TARGET_SCHED_INIT rs6000_sched_init
1348 #undef TARGET_SCHED_FINISH
1349 #define TARGET_SCHED_FINISH rs6000_sched_finish
1350 #undef TARGET_SCHED_REORDER
1351 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1352 #undef TARGET_SCHED_REORDER2
1353 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1355 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1356 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1358 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1359 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1361 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1362 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1363 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1364 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1365 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1366 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1367 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1368 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1370 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1371 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1372 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1373 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1374 rs6000_builtin_support_vector_misalignment
1375 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1376 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1377 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1378 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1379 rs6000_builtin_vectorization_cost
1380 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1381 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1382 rs6000_preferred_simd_mode
1383 #undef TARGET_VECTORIZE_INIT_COST
1384 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1385 #undef TARGET_VECTORIZE_ADD_STMT_COST
1386 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1387 #undef TARGET_VECTORIZE_FINISH_COST
1388 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1389 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1390 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1392 #undef TARGET_INIT_BUILTINS
1393 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1394 #undef TARGET_BUILTIN_DECL
1395 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1397 #undef TARGET_EXPAND_BUILTIN
1398 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1400 #undef TARGET_MANGLE_TYPE
1401 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1403 #undef TARGET_INIT_LIBFUNCS
1404 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1407 #undef TARGET_BINDS_LOCAL_P
1408 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1411 #undef TARGET_MS_BITFIELD_LAYOUT_P
1412 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1414 #undef TARGET_ASM_OUTPUT_MI_THUNK
1415 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1417 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1418 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1420 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1421 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1423 #undef TARGET_REGISTER_MOVE_COST
1424 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1425 #undef TARGET_MEMORY_MOVE_COST
1426 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1427 #undef TARGET_RTX_COSTS
1428 #define TARGET_RTX_COSTS rs6000_rtx_costs
1429 #undef TARGET_ADDRESS_COST
1430 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1432 #undef TARGET_DWARF_REGISTER_SPAN
1433 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1435 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1436 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1438 #undef TARGET_MEMBER_TYPE_FORCES_BLK
1439 #define TARGET_MEMBER_TYPE_FORCES_BLK rs6000_member_type_forces_blk
1441 /* On rs6000, function arguments are promoted, as are function return
1443 #undef TARGET_PROMOTE_FUNCTION_MODE
1444 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
1446 #undef TARGET_RETURN_IN_MEMORY
1447 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1449 #undef TARGET_SETUP_INCOMING_VARARGS
1450 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1452 /* Always strict argument naming on rs6000. */
1453 #undef TARGET_STRICT_ARGUMENT_NAMING
1454 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1455 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1456 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1457 #undef TARGET_SPLIT_COMPLEX_ARG
1458 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1459 #undef TARGET_MUST_PASS_IN_STACK
1460 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1461 #undef TARGET_PASS_BY_REFERENCE
1462 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1463 #undef TARGET_ARG_PARTIAL_BYTES
1464 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1465 #undef TARGET_FUNCTION_ARG_ADVANCE
1466 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1467 #undef TARGET_FUNCTION_ARG
1468 #define TARGET_FUNCTION_ARG rs6000_function_arg
1469 #undef TARGET_FUNCTION_ARG_BOUNDARY
1470 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1472 #undef TARGET_BUILD_BUILTIN_VA_LIST
1473 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1475 #undef TARGET_EXPAND_BUILTIN_VA_START
1476 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1478 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1479 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1481 #undef TARGET_EH_RETURN_FILTER_MODE
1482 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1484 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1485 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1487 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1488 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1490 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1491 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1493 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1494 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1496 #undef TARGET_OPTION_OVERRIDE
1497 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1499 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1500 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1501 rs6000_builtin_vectorized_function
1504 #undef TARGET_STACK_PROTECT_FAIL
1505 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1508 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1509 The PowerPC architecture requires only weak consistency among
1510 processors--that is, memory accesses between processors need not be
1511 sequentially consistent and memory accesses among processors can occur
1512 in any order. The ability to order memory accesses weakly provides
1513 opportunities for more efficient use of the system bus. Unless a
1514 dependency exists, the 604e allows read operations to precede store
1516 #undef TARGET_RELAXED_ORDERING
1517 #define TARGET_RELAXED_ORDERING true
1520 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1521 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1524 /* Use a 32-bit anchor range. This leads to sequences like:
1526 addis tmp,anchor,high
1529 where tmp itself acts as an anchor, and can be shared between
1530 accesses to the same 64k page. */
1531 #undef TARGET_MIN_ANCHOR_OFFSET
1532 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1533 #undef TARGET_MAX_ANCHOR_OFFSET
1534 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1535 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1536 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1537 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1538 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1540 #undef TARGET_BUILTIN_RECIPROCAL
1541 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1543 #undef TARGET_EXPAND_TO_RTL_HOOK
1544 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1546 #undef TARGET_INSTANTIATE_DECLS
1547 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1549 #undef TARGET_SECONDARY_RELOAD
1550 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1552 #undef TARGET_LEGITIMATE_ADDRESS_P
1553 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1555 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1556 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1559 #define TARGET_LRA_P rs6000_lra_p
1561 #undef TARGET_CAN_ELIMINATE
1562 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1564 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1565 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1567 #undef TARGET_TRAMPOLINE_INIT
1568 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1570 #undef TARGET_FUNCTION_VALUE
1571 #define TARGET_FUNCTION_VALUE rs6000_function_value
1573 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1574 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1576 #undef TARGET_OPTION_SAVE
1577 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1579 #undef TARGET_OPTION_RESTORE
1580 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1582 #undef TARGET_OPTION_PRINT
1583 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1585 #undef TARGET_CAN_INLINE_P
1586 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1588 #undef TARGET_SET_CURRENT_FUNCTION
1589 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1591 #undef TARGET_LEGITIMATE_CONSTANT_P
1592 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1594 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
1595 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok
1597 #undef TARGET_CAN_USE_DOLOOP_P
1598 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
1601 /* Processor table. */
1604 const char *const name
; /* Canonical processor name. */
1605 const enum processor_type processor
; /* Processor type enum value. */
1606 const HOST_WIDE_INT target_enable
; /* Target flags to enable. */
1609 static struct rs6000_ptt
const processor_target_table
[] =
1611 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1612 #include "rs6000-cpus.def"
1616 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
1620 rs6000_cpu_name_lookup (const char *name
)
1626 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
1627 if (! strcmp (name
, processor_target_table
[i
].name
))
1635 /* Return number of consecutive hard regs needed starting at reg REGNO
1636 to hold something of mode MODE.
1637 This is ordinarily the length in words of a value of mode MODE
1638 but can be less for certain modes in special long registers.
1640 For the SPE, GPRs are 64 bits but only 32 bits are visible in
1641 scalar instructions. The upper 32 bits are only available to the
1644 POWER and PowerPC GPRs hold 32 bits worth;
1645 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
1648 rs6000_hard_regno_nregs_internal (int regno
, enum machine_mode mode
)
1650 unsigned HOST_WIDE_INT reg_size
;
1652 /* TF/TD modes are special in that they always take 2 registers. */
1653 if (FP_REGNO_P (regno
))
1654 reg_size
= ((VECTOR_MEM_VSX_P (mode
) && mode
!= TDmode
&& mode
!= TFmode
)
1655 ? UNITS_PER_VSX_WORD
1656 : UNITS_PER_FP_WORD
);
1658 else if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1659 reg_size
= UNITS_PER_SPE_WORD
;
1661 else if (ALTIVEC_REGNO_P (regno
))
1662 reg_size
= UNITS_PER_ALTIVEC_WORD
;
1664 /* The value returned for SCmode in the E500 double case is 2 for
1665 ABI compatibility; storing an SCmode value in a single register
1666 would require function_arg and rs6000_spe_function_arg to handle
1667 SCmode so as to pass the value correctly in a pair of
1669 else if (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
) && mode
!= SCmode
1670 && !DECIMAL_FLOAT_MODE_P (mode
))
1671 reg_size
= UNITS_PER_FP_WORD
;
1674 reg_size
= UNITS_PER_WORD
;
1676 return (GET_MODE_SIZE (mode
) + reg_size
- 1) / reg_size
;
1679 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1682 rs6000_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
1684 int last_regno
= regno
+ rs6000_hard_regno_nregs
[mode
][regno
] - 1;
1686 /* PTImode can only go in GPRs. Quad word memory operations require even/odd
1687 register combinations, and use PTImode where we need to deal with quad
1688 word memory operations. Don't allow quad words in the argument or frame
1689 pointer registers, just registers 0..31. */
1690 if (mode
== PTImode
)
1691 return (IN_RANGE (regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
1692 && IN_RANGE (last_regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
1693 && ((regno
& 1) == 0));
1695 /* VSX registers that overlap the FPR registers are larger than for non-VSX
1696 implementations. Don't allow an item to be split between a FP register
1697 and an Altivec register. Allow TImode in all VSX registers if the user
1699 if (TARGET_VSX
&& VSX_REGNO_P (regno
)
1700 && (VECTOR_MEM_VSX_P (mode
)
1701 || (TARGET_VSX_SCALAR_FLOAT
&& mode
== SFmode
)
1702 || (TARGET_VSX_SCALAR_DOUBLE
&& (mode
== DFmode
|| mode
== DImode
))
1703 || (TARGET_VSX_TIMODE
&& mode
== TImode
)))
1705 if (FP_REGNO_P (regno
))
1706 return FP_REGNO_P (last_regno
);
1708 if (ALTIVEC_REGNO_P (regno
))
1710 if (mode
== SFmode
&& !TARGET_UPPER_REGS_SF
)
1713 if ((mode
== DFmode
|| mode
== DImode
) && !TARGET_UPPER_REGS_DF
)
1716 return ALTIVEC_REGNO_P (last_regno
);
1720 /* The GPRs can hold any mode, but values bigger than one register
1721 cannot go past R31. */
1722 if (INT_REGNO_P (regno
))
1723 return INT_REGNO_P (last_regno
);
1725 /* The float registers (except for VSX vector modes) can only hold floating
1726 modes and DImode. */
1727 if (FP_REGNO_P (regno
))
1729 if (SCALAR_FLOAT_MODE_P (mode
)
1730 && (mode
!= TDmode
|| (regno
% 2) == 0)
1731 && FP_REGNO_P (last_regno
))
1734 if (GET_MODE_CLASS (mode
) == MODE_INT
1735 && GET_MODE_SIZE (mode
) == UNITS_PER_FP_WORD
)
1738 if (PAIRED_SIMD_REGNO_P (regno
) && TARGET_PAIRED_FLOAT
1739 && PAIRED_VECTOR_MODE (mode
))
1745 /* The CR register can only hold CC modes. */
1746 if (CR_REGNO_P (regno
))
1747 return GET_MODE_CLASS (mode
) == MODE_CC
;
1749 if (CA_REGNO_P (regno
))
1750 return mode
== BImode
;
1752 /* AltiVec only in AldyVec registers. */
1753 if (ALTIVEC_REGNO_P (regno
))
1754 return VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
);
1756 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1757 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1760 /* We cannot put non-VSX TImode or PTImode anywhere except general register
1761 and it must be able to fit within the register set. */
1763 return GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
;
1766 /* Print interesting facts about registers. */
1768 rs6000_debug_reg_print (int first_regno
, int last_regno
, const char *reg_name
)
1772 for (r
= first_regno
; r
<= last_regno
; ++r
)
1774 const char *comma
= "";
1777 if (first_regno
== last_regno
)
1778 fprintf (stderr
, "%s:\t", reg_name
);
1780 fprintf (stderr
, "%s%d:\t", reg_name
, r
- first_regno
);
1783 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1784 if (rs6000_hard_regno_mode_ok_p
[m
][r
] && rs6000_hard_regno_nregs
[m
][r
])
1788 fprintf (stderr
, ",\n\t");
1793 if (rs6000_hard_regno_nregs
[m
][r
] > 1)
1794 len
+= fprintf (stderr
, "%s%s/%d", comma
, GET_MODE_NAME (m
),
1795 rs6000_hard_regno_nregs
[m
][r
]);
1797 len
+= fprintf (stderr
, "%s%s", comma
, GET_MODE_NAME (m
));
1802 if (call_used_regs
[r
])
1806 fprintf (stderr
, ",\n\t");
1811 len
+= fprintf (stderr
, "%s%s", comma
, "call-used");
1819 fprintf (stderr
, ",\n\t");
1824 len
+= fprintf (stderr
, "%s%s", comma
, "fixed");
1830 fprintf (stderr
, ",\n\t");
1834 len
+= fprintf (stderr
, "%sreg-class = %s", comma
,
1835 reg_class_names
[(int)rs6000_regno_regclass
[r
]]);
1840 fprintf (stderr
, ",\n\t");
1844 fprintf (stderr
, "%sregno = %d\n", comma
, r
);
1849 rs6000_debug_vector_unit (enum rs6000_vector v
)
1855 case VECTOR_NONE
: ret
= "none"; break;
1856 case VECTOR_ALTIVEC
: ret
= "altivec"; break;
1857 case VECTOR_VSX
: ret
= "vsx"; break;
1858 case VECTOR_P8_VECTOR
: ret
= "p8_vector"; break;
1859 case VECTOR_PAIRED
: ret
= "paired"; break;
1860 case VECTOR_SPE
: ret
= "spe"; break;
1861 case VECTOR_OTHER
: ret
= "other"; break;
1862 default: ret
= "unknown"; break;
1868 /* Print the address masks in a human readble fashion. */
1870 rs6000_debug_print_mode (ssize_t m
)
1874 fprintf (stderr
, "Mode: %-5s", GET_MODE_NAME (m
));
1875 for (rc
= 0; rc
< N_RELOAD_REG
; rc
++)
1877 addr_mask_type mask
= reg_addr
[m
].addr_mask
[rc
];
1879 " %s: %c%c%c%c%c%c",
1880 reload_reg_map
[rc
].name
,
1881 (mask
& RELOAD_REG_VALID
) != 0 ? 'v' : ' ',
1882 (mask
& RELOAD_REG_MULTIPLE
) != 0 ? 'm' : ' ',
1883 (mask
& RELOAD_REG_INDEXED
) != 0 ? 'i' : ' ',
1884 (mask
& RELOAD_REG_OFFSET
) != 0 ? 'o' : ' ',
1885 (mask
& RELOAD_REG_PRE_INCDEC
) != 0 ? '+' : ' ',
1886 (mask
& RELOAD_REG_PRE_MODIFY
) != 0 ? '+' : ' ');
1889 if (rs6000_vector_unit
[m
] != VECTOR_NONE
1890 || rs6000_vector_mem
[m
] != VECTOR_NONE
1891 || (reg_addr
[m
].reload_store
!= CODE_FOR_nothing
)
1892 || (reg_addr
[m
].reload_load
!= CODE_FOR_nothing
))
1895 " Vector-arith=%-10s Vector-mem=%-10s Reload=%c%c",
1896 rs6000_debug_vector_unit (rs6000_vector_unit
[m
]),
1897 rs6000_debug_vector_unit (rs6000_vector_mem
[m
]),
1898 (reg_addr
[m
].reload_store
!= CODE_FOR_nothing
) ? 's' : '*',
1899 (reg_addr
[m
].reload_load
!= CODE_FOR_nothing
) ? 'l' : '*');
1902 fputs ("\n", stderr
);
1905 #define DEBUG_FMT_ID "%-32s= "
1906 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
1907 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
1908 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
1910 /* Print various interesting information with -mdebug=reg. */
1912 rs6000_debug_reg_global (void)
1914 static const char *const tf
[2] = { "false", "true" };
1915 const char *nl
= (const char *)0;
1918 char costly_num
[20];
1920 char flags_buffer
[40];
1921 const char *costly_str
;
1922 const char *nop_str
;
1923 const char *trace_str
;
1924 const char *abi_str
;
1925 const char *cmodel_str
;
1926 struct cl_target_option cl_opts
;
1928 /* Modes we want tieable information on. */
1929 static const enum machine_mode print_tieable_modes
[] = {
1963 /* Virtual regs we are interested in. */
1964 const static struct {
1965 int regno
; /* register number. */
1966 const char *name
; /* register name. */
1967 } virtual_regs
[] = {
1968 { STACK_POINTER_REGNUM
, "stack pointer:" },
1969 { TOC_REGNUM
, "toc: " },
1970 { STATIC_CHAIN_REGNUM
, "static chain: " },
1971 { RS6000_PIC_OFFSET_TABLE_REGNUM
, "pic offset: " },
1972 { HARD_FRAME_POINTER_REGNUM
, "hard frame: " },
1973 { ARG_POINTER_REGNUM
, "arg pointer: " },
1974 { FRAME_POINTER_REGNUM
, "frame pointer:" },
1975 { FIRST_PSEUDO_REGISTER
, "first pseudo: " },
1976 { FIRST_VIRTUAL_REGISTER
, "first virtual:" },
1977 { VIRTUAL_INCOMING_ARGS_REGNUM
, "incoming_args:" },
1978 { VIRTUAL_STACK_VARS_REGNUM
, "stack_vars: " },
1979 { VIRTUAL_STACK_DYNAMIC_REGNUM
, "stack_dynamic:" },
1980 { VIRTUAL_OUTGOING_ARGS_REGNUM
, "outgoing_args:" },
1981 { VIRTUAL_CFA_REGNUM
, "cfa (frame): " },
1982 { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM
, "stack boundry:" },
1983 { LAST_VIRTUAL_REGISTER
, "last virtual: " },
1986 fputs ("\nHard register information:\n", stderr
);
1987 rs6000_debug_reg_print (FIRST_GPR_REGNO
, LAST_GPR_REGNO
, "gr");
1988 rs6000_debug_reg_print (FIRST_FPR_REGNO
, LAST_FPR_REGNO
, "fp");
1989 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO
,
1992 rs6000_debug_reg_print (LR_REGNO
, LR_REGNO
, "lr");
1993 rs6000_debug_reg_print (CTR_REGNO
, CTR_REGNO
, "ctr");
1994 rs6000_debug_reg_print (CR0_REGNO
, CR7_REGNO
, "cr");
1995 rs6000_debug_reg_print (CA_REGNO
, CA_REGNO
, "ca");
1996 rs6000_debug_reg_print (VRSAVE_REGNO
, VRSAVE_REGNO
, "vrsave");
1997 rs6000_debug_reg_print (VSCR_REGNO
, VSCR_REGNO
, "vscr");
1998 rs6000_debug_reg_print (SPE_ACC_REGNO
, SPE_ACC_REGNO
, "spe_a");
1999 rs6000_debug_reg_print (SPEFSCR_REGNO
, SPEFSCR_REGNO
, "spe_f");
2001 fputs ("\nVirtual/stack/frame registers:\n", stderr
);
2002 for (v
= 0; v
< ARRAY_SIZE (virtual_regs
); v
++)
2003 fprintf (stderr
, "%s regno = %3d\n", virtual_regs
[v
].name
, virtual_regs
[v
].regno
);
2007 "d reg_class = %s\n"
2008 "f reg_class = %s\n"
2009 "v reg_class = %s\n"
2010 "wa reg_class = %s\n"
2011 "wd reg_class = %s\n"
2012 "wf reg_class = %s\n"
2013 "wg reg_class = %s\n"
2014 "wl reg_class = %s\n"
2015 "wm reg_class = %s\n"
2016 "wr reg_class = %s\n"
2017 "ws reg_class = %s\n"
2018 "wt reg_class = %s\n"
2019 "wu reg_class = %s\n"
2020 "wv reg_class = %s\n"
2021 "ww reg_class = %s\n"
2022 "wx reg_class = %s\n"
2023 "wy reg_class = %s\n"
2024 "wz reg_class = %s\n"
2026 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_d
]],
2027 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_f
]],
2028 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_v
]],
2029 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wa
]],
2030 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wd
]],
2031 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wf
]],
2032 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wg
]],
2033 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wl
]],
2034 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wm
]],
2035 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wr
]],
2036 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ws
]],
2037 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wt
]],
2038 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wu
]],
2039 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wv
]],
2040 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ww
]],
2041 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wx
]],
2042 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wy
]],
2043 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wz
]]);
2046 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2047 rs6000_debug_print_mode (m
);
2049 fputs ("\n", stderr
);
2051 for (m1
= 0; m1
< ARRAY_SIZE (print_tieable_modes
); m1
++)
2053 enum machine_mode mode1
= print_tieable_modes
[m1
];
2054 bool first_time
= true;
2056 nl
= (const char *)0;
2057 for (m2
= 0; m2
< ARRAY_SIZE (print_tieable_modes
); m2
++)
2059 enum machine_mode mode2
= print_tieable_modes
[m2
];
2060 if (mode1
!= mode2
&& MODES_TIEABLE_P (mode1
, mode2
))
2064 fprintf (stderr
, "Tieable modes %s:", GET_MODE_NAME (mode1
));
2069 fprintf (stderr
, " %s", GET_MODE_NAME (mode2
));
2074 fputs ("\n", stderr
);
2080 if (rs6000_recip_control
)
2082 fprintf (stderr
, "\nReciprocal mask = 0x%x\n", rs6000_recip_control
);
2084 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2085 if (rs6000_recip_bits
[m
])
2088 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2090 (RS6000_RECIP_AUTO_RE_P (m
)
2092 : (RS6000_RECIP_HAVE_RE_P (m
) ? "have" : "none")),
2093 (RS6000_RECIP_AUTO_RSQRTE_P (m
)
2095 : (RS6000_RECIP_HAVE_RSQRTE_P (m
) ? "have" : "none")));
2098 fputs ("\n", stderr
);
2101 if (rs6000_cpu_index
>= 0)
2103 const char *name
= processor_target_table
[rs6000_cpu_index
].name
;
2105 = processor_target_table
[rs6000_cpu_index
].target_enable
;
2107 sprintf (flags_buffer
, "-mcpu=%s flags", name
);
2108 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2111 fprintf (stderr
, DEBUG_FMT_S
, "cpu", "<none>");
2113 if (rs6000_tune_index
>= 0)
2115 const char *name
= processor_target_table
[rs6000_tune_index
].name
;
2117 = processor_target_table
[rs6000_tune_index
].target_enable
;
2119 sprintf (flags_buffer
, "-mtune=%s flags", name
);
2120 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2123 fprintf (stderr
, DEBUG_FMT_S
, "tune", "<none>");
2125 cl_target_option_save (&cl_opts
, &global_options
);
2126 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags",
2129 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags_explicit",
2130 rs6000_isa_flags_explicit
);
2132 rs6000_print_builtin_options (stderr
, 0, "rs6000_builtin_mask",
2133 rs6000_builtin_mask
);
2135 rs6000_print_isa_options (stderr
, 0, "TARGET_DEFAULT", TARGET_DEFAULT
);
2137 fprintf (stderr
, DEBUG_FMT_S
, "--with-cpu default",
2138 OPTION_TARGET_CPU_DEFAULT
? OPTION_TARGET_CPU_DEFAULT
: "<none>");
2140 switch (rs6000_sched_costly_dep
)
2142 case max_dep_latency
:
2143 costly_str
= "max_dep_latency";
2147 costly_str
= "no_dep_costly";
2150 case all_deps_costly
:
2151 costly_str
= "all_deps_costly";
2154 case true_store_to_load_dep_costly
:
2155 costly_str
= "true_store_to_load_dep_costly";
2158 case store_to_load_dep_costly
:
2159 costly_str
= "store_to_load_dep_costly";
2163 costly_str
= costly_num
;
2164 sprintf (costly_num
, "%d", (int)rs6000_sched_costly_dep
);
2168 fprintf (stderr
, DEBUG_FMT_S
, "sched_costly_dep", costly_str
);
2170 switch (rs6000_sched_insert_nops
)
2172 case sched_finish_regroup_exact
:
2173 nop_str
= "sched_finish_regroup_exact";
2176 case sched_finish_pad_groups
:
2177 nop_str
= "sched_finish_pad_groups";
2180 case sched_finish_none
:
2181 nop_str
= "sched_finish_none";
2186 sprintf (nop_num
, "%d", (int)rs6000_sched_insert_nops
);
2190 fprintf (stderr
, DEBUG_FMT_S
, "sched_insert_nops", nop_str
);
2192 switch (rs6000_sdata
)
2199 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "data");
2203 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "sysv");
2207 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "eabi");
2212 switch (rs6000_traceback
)
2214 case traceback_default
: trace_str
= "default"; break;
2215 case traceback_none
: trace_str
= "none"; break;
2216 case traceback_part
: trace_str
= "part"; break;
2217 case traceback_full
: trace_str
= "full"; break;
2218 default: trace_str
= "unknown"; break;
2221 fprintf (stderr
, DEBUG_FMT_S
, "traceback", trace_str
);
2223 switch (rs6000_current_cmodel
)
2225 case CMODEL_SMALL
: cmodel_str
= "small"; break;
2226 case CMODEL_MEDIUM
: cmodel_str
= "medium"; break;
2227 case CMODEL_LARGE
: cmodel_str
= "large"; break;
2228 default: cmodel_str
= "unknown"; break;
2231 fprintf (stderr
, DEBUG_FMT_S
, "cmodel", cmodel_str
);
2233 switch (rs6000_current_abi
)
2235 case ABI_NONE
: abi_str
= "none"; break;
2236 case ABI_AIX
: abi_str
= "aix"; break;
2237 case ABI_V4
: abi_str
= "V4"; break;
2238 case ABI_DARWIN
: abi_str
= "darwin"; break;
2239 default: abi_str
= "unknown"; break;
2242 fprintf (stderr
, DEBUG_FMT_S
, "abi", abi_str
);
2244 if (rs6000_altivec_abi
)
2245 fprintf (stderr
, DEBUG_FMT_S
, "altivec_abi", "true");
2248 fprintf (stderr
, DEBUG_FMT_S
, "spe_abi", "true");
2250 if (rs6000_darwin64_abi
)
2251 fprintf (stderr
, DEBUG_FMT_S
, "darwin64_abi", "true");
2253 if (rs6000_float_gprs
)
2254 fprintf (stderr
, DEBUG_FMT_S
, "float_gprs", "true");
2256 if (TARGET_LINK_STACK
)
2257 fprintf (stderr
, DEBUG_FMT_S
, "link_stack", "true");
2259 if (targetm
.lra_p ())
2260 fprintf (stderr
, DEBUG_FMT_S
, "lra", "true");
2262 if (TARGET_P8_FUSION
)
2263 fprintf (stderr
, DEBUG_FMT_S
, "p8 fusion",
2264 (TARGET_P8_FUSION_SIGN
) ? "zero+sign" : "zero");
2266 fprintf (stderr
, DEBUG_FMT_S
, "plt-format",
2267 TARGET_SECURE_PLT
? "secure" : "bss");
2268 fprintf (stderr
, DEBUG_FMT_S
, "struct-return",
2269 aix_struct_return
? "aix" : "sysv");
2270 fprintf (stderr
, DEBUG_FMT_S
, "always_hint", tf
[!!rs6000_always_hint
]);
2271 fprintf (stderr
, DEBUG_FMT_S
, "sched_groups", tf
[!!rs6000_sched_groups
]);
2272 fprintf (stderr
, DEBUG_FMT_S
, "align_branch",
2273 tf
[!!rs6000_align_branch_targets
]);
2274 fprintf (stderr
, DEBUG_FMT_D
, "tls_size", rs6000_tls_size
);
2275 fprintf (stderr
, DEBUG_FMT_D
, "long_double_size",
2276 rs6000_long_double_type_size
);
2277 fprintf (stderr
, DEBUG_FMT_D
, "sched_restricted_insns_priority",
2278 (int)rs6000_sched_restricted_insns_priority
);
2279 fprintf (stderr
, DEBUG_FMT_D
, "Number of standard builtins",
2281 fprintf (stderr
, DEBUG_FMT_D
, "Number of rs6000 builtins",
2282 (int)RS6000_BUILTIN_COUNT
);
2286 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2287 legitimate address support to figure out the appropriate addressing to
2291 rs6000_setup_reg_addr_masks (void)
2293 ssize_t rc
, reg
, m
, nregs
;
2294 addr_mask_type any_addr_mask
, addr_mask
;
2296 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2298 /* SDmode is special in that we want to access it only via REG+REG
2299 addressing on power7 and above, since we want to use the LFIWZX and
2300 STFIWZX instructions to load it. */
2301 bool indexed_only_p
= (m
== SDmode
&& TARGET_NO_SDMODE_STACK
);
2304 for (rc
= FIRST_RELOAD_REG_CLASS
; rc
<= LAST_RELOAD_REG_CLASS
; rc
++)
2307 reg
= reload_reg_map
[rc
].reg
;
2309 /* Can mode values go in the GPR/FPR/Altivec registers? */
2310 if (reg
>= 0 && rs6000_hard_regno_mode_ok_p
[m
][reg
])
2312 nregs
= rs6000_hard_regno_nregs
[m
][reg
];
2313 addr_mask
|= RELOAD_REG_VALID
;
2315 /* Indicate if the mode takes more than 1 physical register. If
2316 it takes a single register, indicate it can do REG+REG
2318 if (nregs
> 1 || m
== BLKmode
)
2319 addr_mask
|= RELOAD_REG_MULTIPLE
;
2321 addr_mask
|= RELOAD_REG_INDEXED
;
2323 /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
2324 addressing. Restrict addressing on SPE for 64-bit types
2325 because of the SUBREG hackery used to address 64-bit floats in
2326 '32-bit' GPRs. To simplify secondary reload, don't allow
2327 update forms on scalar floating point types that can go in the
2331 && (rc
== RELOAD_REG_GPR
|| rc
== RELOAD_REG_FPR
)
2332 && GET_MODE_SIZE (m
) <= 8
2333 && !VECTOR_MODE_P (m
)
2334 && !COMPLEX_MODE_P (m
)
2336 && !(TARGET_E500_DOUBLE
&& GET_MODE_SIZE (m
) == 8)
2337 && !(m
== DFmode
&& TARGET_UPPER_REGS_DF
)
2338 && !(m
== SFmode
&& TARGET_UPPER_REGS_SF
))
2340 addr_mask
|= RELOAD_REG_PRE_INCDEC
;
2342 /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that
2343 we don't allow PRE_MODIFY for some multi-register
2348 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2352 if (TARGET_POWERPC64
)
2353 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2359 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2365 /* GPR and FPR registers can do REG+OFFSET addressing, except
2366 possibly for SDmode. */
2367 if ((addr_mask
!= 0) && !indexed_only_p
2368 && (rc
== RELOAD_REG_GPR
|| rc
== RELOAD_REG_FPR
))
2369 addr_mask
|= RELOAD_REG_OFFSET
;
2371 reg_addr
[m
].addr_mask
[rc
] = addr_mask
;
2372 any_addr_mask
|= addr_mask
;
2375 reg_addr
[m
].addr_mask
[RELOAD_REG_ANY
] = any_addr_mask
;
2380 /* Initialize the various global tables that are based on register size. */
2382 rs6000_init_hard_regno_mode_ok (bool global_init_p
)
2388 /* Precalculate REGNO_REG_CLASS. */
2389 rs6000_regno_regclass
[0] = GENERAL_REGS
;
2390 for (r
= 1; r
< 32; ++r
)
2391 rs6000_regno_regclass
[r
] = BASE_REGS
;
2393 for (r
= 32; r
< 64; ++r
)
2394 rs6000_regno_regclass
[r
] = FLOAT_REGS
;
2396 for (r
= 64; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2397 rs6000_regno_regclass
[r
] = NO_REGS
;
2399 for (r
= FIRST_ALTIVEC_REGNO
; r
<= LAST_ALTIVEC_REGNO
; ++r
)
2400 rs6000_regno_regclass
[r
] = ALTIVEC_REGS
;
2402 rs6000_regno_regclass
[CR0_REGNO
] = CR0_REGS
;
2403 for (r
= CR1_REGNO
; r
<= CR7_REGNO
; ++r
)
2404 rs6000_regno_regclass
[r
] = CR_REGS
;
2406 rs6000_regno_regclass
[LR_REGNO
] = LINK_REGS
;
2407 rs6000_regno_regclass
[CTR_REGNO
] = CTR_REGS
;
2408 rs6000_regno_regclass
[CA_REGNO
] = CA_REGS
;
2409 rs6000_regno_regclass
[VRSAVE_REGNO
] = VRSAVE_REGS
;
2410 rs6000_regno_regclass
[VSCR_REGNO
] = VRSAVE_REGS
;
2411 rs6000_regno_regclass
[SPE_ACC_REGNO
] = SPE_ACC_REGS
;
2412 rs6000_regno_regclass
[SPEFSCR_REGNO
] = SPEFSCR_REGS
;
2413 rs6000_regno_regclass
[TFHAR_REGNO
] = SPR_REGS
;
2414 rs6000_regno_regclass
[TFIAR_REGNO
] = SPR_REGS
;
2415 rs6000_regno_regclass
[TEXASR_REGNO
] = SPR_REGS
;
2416 rs6000_regno_regclass
[ARG_POINTER_REGNUM
] = BASE_REGS
;
2417 rs6000_regno_regclass
[FRAME_POINTER_REGNUM
] = BASE_REGS
;
2419 /* Precalculate register class to simpler reload register class. We don't
2420 need all of the register classes that are combinations of different
2421 classes, just the simple ones that have constraint letters. */
2422 for (c
= 0; c
< N_REG_CLASSES
; c
++)
2423 reg_class_to_reg_type
[c
] = NO_REG_TYPE
;
2425 reg_class_to_reg_type
[(int)GENERAL_REGS
] = GPR_REG_TYPE
;
2426 reg_class_to_reg_type
[(int)BASE_REGS
] = GPR_REG_TYPE
;
2427 reg_class_to_reg_type
[(int)VSX_REGS
] = VSX_REG_TYPE
;
2428 reg_class_to_reg_type
[(int)VRSAVE_REGS
] = SPR_REG_TYPE
;
2429 reg_class_to_reg_type
[(int)VSCR_REGS
] = SPR_REG_TYPE
;
2430 reg_class_to_reg_type
[(int)LINK_REGS
] = SPR_REG_TYPE
;
2431 reg_class_to_reg_type
[(int)CTR_REGS
] = SPR_REG_TYPE
;
2432 reg_class_to_reg_type
[(int)LINK_OR_CTR_REGS
] = SPR_REG_TYPE
;
2433 reg_class_to_reg_type
[(int)CR_REGS
] = CR_REG_TYPE
;
2434 reg_class_to_reg_type
[(int)CR0_REGS
] = CR_REG_TYPE
;
2435 reg_class_to_reg_type
[(int)SPE_ACC_REGS
] = SPE_ACC_TYPE
;
2436 reg_class_to_reg_type
[(int)SPEFSCR_REGS
] = SPEFSCR_REG_TYPE
;
2440 reg_class_to_reg_type
[(int)FLOAT_REGS
] = VSX_REG_TYPE
;
2441 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = VSX_REG_TYPE
;
2445 reg_class_to_reg_type
[(int)FLOAT_REGS
] = FPR_REG_TYPE
;
2446 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = ALTIVEC_REG_TYPE
;
2449 /* Precalculate the valid memory formats as well as the vector information,
2450 this must be set up before the rs6000_hard_regno_nregs_internal calls
2452 gcc_assert ((int)VECTOR_NONE
== 0);
2453 memset ((void *) &rs6000_vector_unit
[0], '\0', sizeof (rs6000_vector_unit
));
2454 memset ((void *) &rs6000_vector_mem
[0], '\0', sizeof (rs6000_vector_unit
));
2456 gcc_assert ((int)CODE_FOR_nothing
== 0);
2457 memset ((void *) ®_addr
[0], '\0', sizeof (reg_addr
));
2459 gcc_assert ((int)NO_REGS
== 0);
2460 memset ((void *) &rs6000_constraints
[0], '\0', sizeof (rs6000_constraints
));
2462 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
2463 believes it can use native alignment or still uses 128-bit alignment. */
2464 if (TARGET_VSX
&& !TARGET_VSX_ALIGN_128
)
2475 /* V2DF mode, VSX only. */
2478 rs6000_vector_unit
[V2DFmode
] = VECTOR_VSX
;
2479 rs6000_vector_mem
[V2DFmode
] = VECTOR_VSX
;
2480 rs6000_vector_align
[V2DFmode
] = align64
;
2483 /* V4SF mode, either VSX or Altivec. */
2486 rs6000_vector_unit
[V4SFmode
] = VECTOR_VSX
;
2487 rs6000_vector_mem
[V4SFmode
] = VECTOR_VSX
;
2488 rs6000_vector_align
[V4SFmode
] = align32
;
2490 else if (TARGET_ALTIVEC
)
2492 rs6000_vector_unit
[V4SFmode
] = VECTOR_ALTIVEC
;
2493 rs6000_vector_mem
[V4SFmode
] = VECTOR_ALTIVEC
;
2494 rs6000_vector_align
[V4SFmode
] = align32
;
2497 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
2501 rs6000_vector_unit
[V4SImode
] = VECTOR_ALTIVEC
;
2502 rs6000_vector_unit
[V8HImode
] = VECTOR_ALTIVEC
;
2503 rs6000_vector_unit
[V16QImode
] = VECTOR_ALTIVEC
;
2504 rs6000_vector_align
[V4SImode
] = align32
;
2505 rs6000_vector_align
[V8HImode
] = align32
;
2506 rs6000_vector_align
[V16QImode
] = align32
;
2510 rs6000_vector_mem
[V4SImode
] = VECTOR_VSX
;
2511 rs6000_vector_mem
[V8HImode
] = VECTOR_VSX
;
2512 rs6000_vector_mem
[V16QImode
] = VECTOR_VSX
;
2516 rs6000_vector_mem
[V4SImode
] = VECTOR_ALTIVEC
;
2517 rs6000_vector_mem
[V8HImode
] = VECTOR_ALTIVEC
;
2518 rs6000_vector_mem
[V16QImode
] = VECTOR_ALTIVEC
;
2522 /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
2523 do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
2526 rs6000_vector_mem
[V2DImode
] = VECTOR_VSX
;
2527 rs6000_vector_unit
[V2DImode
]
2528 = (TARGET_P8_VECTOR
) ? VECTOR_P8_VECTOR
: VECTOR_NONE
;
2529 rs6000_vector_align
[V2DImode
] = align64
;
2532 /* DFmode, see if we want to use the VSX unit. */
2533 if (TARGET_VSX
&& TARGET_VSX_SCALAR_DOUBLE
)
2535 rs6000_vector_unit
[DFmode
] = VECTOR_VSX
;
2536 rs6000_vector_mem
[DFmode
]
2537 = (TARGET_UPPER_REGS_DF
? VECTOR_VSX
: VECTOR_NONE
);
2538 rs6000_vector_align
[DFmode
] = align64
;
2541 /* Allow TImode in VSX register and set the VSX memory macros. */
2542 if (TARGET_VSX
&& TARGET_VSX_TIMODE
)
2544 rs6000_vector_mem
[TImode
] = VECTOR_VSX
;
2545 rs6000_vector_align
[TImode
] = align64
;
2548 /* TODO add SPE and paired floating point vector support. */
2550 /* Register class constraints for the constraints that depend on compile
2551 switches. When the VSX code was added, different constraints were added
2552 based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all
2553 of the VSX registers are used. The register classes for scalar floating
2554 point types is set, based on whether we allow that type into the upper
2555 (Altivec) registers. GCC has register classes to target the Altivec
2556 registers for load/store operations, to select using a VSX memory
2557 operation instead of the traditional floating point operation. The
2560 d - Register class to use with traditional DFmode instructions.
2561 f - Register class to use with traditional SFmode instructions.
2562 v - Altivec register.
2563 wa - Any VSX register.
2564 wd - Preferred register class for V2DFmode.
2565 wf - Preferred register class for V4SFmode.
2566 wg - Float register for power6x move insns.
2567 wl - Float register if we can do 32-bit signed int loads.
2568 wm - VSX register for ISA 2.07 direct move operations.
2569 wr - GPR if 64-bit mode is permitted.
2570 ws - Register class to do ISA 2.06 DF operations.
2571 wu - Altivec register for ISA 2.07 VSX SF/SI load/stores.
2572 wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
2573 wt - VSX register for TImode in VSX registers.
2574 ww - Register class to do SF conversions in with VSX operations.
2575 wx - Float register if we can do 32-bit int stores.
2576 wy - Register class to do ISA 2.07 SF operations.
2577 wz - Float register if we can do 32-bit unsigned int loads. */
2579 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
2580 rs6000_constraints
[RS6000_CONSTRAINT_f
] = FLOAT_REGS
;
2582 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
2583 rs6000_constraints
[RS6000_CONSTRAINT_d
] = FLOAT_REGS
;
2587 rs6000_constraints
[RS6000_CONSTRAINT_wa
] = VSX_REGS
;
2588 rs6000_constraints
[RS6000_CONSTRAINT_wd
] = VSX_REGS
;
2589 rs6000_constraints
[RS6000_CONSTRAINT_wf
] = VSX_REGS
;
2591 if (TARGET_VSX_TIMODE
)
2592 rs6000_constraints
[RS6000_CONSTRAINT_wt
] = VSX_REGS
;
2594 if (TARGET_UPPER_REGS_DF
)
2596 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = VSX_REGS
;
2597 rs6000_constraints
[RS6000_CONSTRAINT_wv
] = ALTIVEC_REGS
;
2600 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = FLOAT_REGS
;
2603 /* Add conditional constraints based on various options, to allow us to
2604 collapse multiple insn patterns. */
2606 rs6000_constraints
[RS6000_CONSTRAINT_v
] = ALTIVEC_REGS
;
2609 rs6000_constraints
[RS6000_CONSTRAINT_wg
] = FLOAT_REGS
;
2612 rs6000_constraints
[RS6000_CONSTRAINT_wl
] = FLOAT_REGS
;
2614 if (TARGET_DIRECT_MOVE
)
2615 rs6000_constraints
[RS6000_CONSTRAINT_wm
] = VSX_REGS
;
2617 if (TARGET_POWERPC64
)
2618 rs6000_constraints
[RS6000_CONSTRAINT_wr
] = GENERAL_REGS
;
2620 if (TARGET_P8_VECTOR
&& TARGET_UPPER_REGS_SF
)
2622 rs6000_constraints
[RS6000_CONSTRAINT_wu
] = ALTIVEC_REGS
;
2623 rs6000_constraints
[RS6000_CONSTRAINT_wy
] = VSX_REGS
;
2624 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = VSX_REGS
;
2626 else if (TARGET_P8_VECTOR
)
2628 rs6000_constraints
[RS6000_CONSTRAINT_wy
] = FLOAT_REGS
;
2629 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = FLOAT_REGS
;
2631 else if (TARGET_VSX
)
2632 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = FLOAT_REGS
;
2635 rs6000_constraints
[RS6000_CONSTRAINT_wx
] = FLOAT_REGS
;
2638 rs6000_constraints
[RS6000_CONSTRAINT_wz
] = FLOAT_REGS
;
2640 /* Set up the reload helper and direct move functions. */
2641 if (TARGET_VSX
|| TARGET_ALTIVEC
)
2645 reg_addr
[V16QImode
].reload_store
= CODE_FOR_reload_v16qi_di_store
;
2646 reg_addr
[V16QImode
].reload_load
= CODE_FOR_reload_v16qi_di_load
;
2647 reg_addr
[V8HImode
].reload_store
= CODE_FOR_reload_v8hi_di_store
;
2648 reg_addr
[V8HImode
].reload_load
= CODE_FOR_reload_v8hi_di_load
;
2649 reg_addr
[V4SImode
].reload_store
= CODE_FOR_reload_v4si_di_store
;
2650 reg_addr
[V4SImode
].reload_load
= CODE_FOR_reload_v4si_di_load
;
2651 reg_addr
[V2DImode
].reload_store
= CODE_FOR_reload_v2di_di_store
;
2652 reg_addr
[V2DImode
].reload_load
= CODE_FOR_reload_v2di_di_load
;
2653 reg_addr
[V4SFmode
].reload_store
= CODE_FOR_reload_v4sf_di_store
;
2654 reg_addr
[V4SFmode
].reload_load
= CODE_FOR_reload_v4sf_di_load
;
2655 reg_addr
[V2DFmode
].reload_store
= CODE_FOR_reload_v2df_di_store
;
2656 reg_addr
[V2DFmode
].reload_load
= CODE_FOR_reload_v2df_di_load
;
2657 if (TARGET_VSX
&& TARGET_UPPER_REGS_DF
)
2659 reg_addr
[DFmode
].reload_store
= CODE_FOR_reload_df_di_store
;
2660 reg_addr
[DFmode
].reload_load
= CODE_FOR_reload_df_di_load
;
2661 reg_addr
[DDmode
].reload_store
= CODE_FOR_reload_dd_di_store
;
2662 reg_addr
[DDmode
].reload_load
= CODE_FOR_reload_dd_di_load
;
2664 if (TARGET_P8_VECTOR
)
2666 reg_addr
[SFmode
].reload_store
= CODE_FOR_reload_sf_di_store
;
2667 reg_addr
[SFmode
].reload_load
= CODE_FOR_reload_sf_di_load
;
2668 reg_addr
[SDmode
].reload_store
= CODE_FOR_reload_sd_di_store
;
2669 reg_addr
[SDmode
].reload_load
= CODE_FOR_reload_sd_di_load
;
2671 if (TARGET_VSX_TIMODE
)
2673 reg_addr
[TImode
].reload_store
= CODE_FOR_reload_ti_di_store
;
2674 reg_addr
[TImode
].reload_load
= CODE_FOR_reload_ti_di_load
;
2676 if (TARGET_DIRECT_MOVE
)
2678 if (TARGET_POWERPC64
)
2680 reg_addr
[TImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxti
;
2681 reg_addr
[V2DFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv2df
;
2682 reg_addr
[V2DImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv2di
;
2683 reg_addr
[V4SFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv4sf
;
2684 reg_addr
[V4SImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv4si
;
2685 reg_addr
[V8HImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv8hi
;
2686 reg_addr
[V16QImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv16qi
;
2687 reg_addr
[SFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxsf
;
2689 reg_addr
[TImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprti
;
2690 reg_addr
[V2DFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv2df
;
2691 reg_addr
[V2DImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv2di
;
2692 reg_addr
[V4SFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv4sf
;
2693 reg_addr
[V4SImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv4si
;
2694 reg_addr
[V8HImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv8hi
;
2695 reg_addr
[V16QImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv16qi
;
2696 reg_addr
[SFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprsf
;
2700 reg_addr
[DImode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdi
;
2701 reg_addr
[DDmode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdd
;
2702 reg_addr
[DFmode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdf
;
2708 reg_addr
[V16QImode
].reload_store
= CODE_FOR_reload_v16qi_si_store
;
2709 reg_addr
[V16QImode
].reload_load
= CODE_FOR_reload_v16qi_si_load
;
2710 reg_addr
[V8HImode
].reload_store
= CODE_FOR_reload_v8hi_si_store
;
2711 reg_addr
[V8HImode
].reload_load
= CODE_FOR_reload_v8hi_si_load
;
2712 reg_addr
[V4SImode
].reload_store
= CODE_FOR_reload_v4si_si_store
;
2713 reg_addr
[V4SImode
].reload_load
= CODE_FOR_reload_v4si_si_load
;
2714 reg_addr
[V2DImode
].reload_store
= CODE_FOR_reload_v2di_si_store
;
2715 reg_addr
[V2DImode
].reload_load
= CODE_FOR_reload_v2di_si_load
;
2716 reg_addr
[V4SFmode
].reload_store
= CODE_FOR_reload_v4sf_si_store
;
2717 reg_addr
[V4SFmode
].reload_load
= CODE_FOR_reload_v4sf_si_load
;
2718 reg_addr
[V2DFmode
].reload_store
= CODE_FOR_reload_v2df_si_store
;
2719 reg_addr
[V2DFmode
].reload_load
= CODE_FOR_reload_v2df_si_load
;
2720 if (TARGET_VSX
&& TARGET_UPPER_REGS_DF
)
2722 reg_addr
[DFmode
].reload_store
= CODE_FOR_reload_df_si_store
;
2723 reg_addr
[DFmode
].reload_load
= CODE_FOR_reload_df_si_load
;
2724 reg_addr
[DDmode
].reload_store
= CODE_FOR_reload_dd_si_store
;
2725 reg_addr
[DDmode
].reload_load
= CODE_FOR_reload_dd_si_load
;
2727 if (TARGET_P8_VECTOR
)
2729 reg_addr
[SFmode
].reload_store
= CODE_FOR_reload_sf_si_store
;
2730 reg_addr
[SFmode
].reload_load
= CODE_FOR_reload_sf_si_load
;
2731 reg_addr
[SDmode
].reload_store
= CODE_FOR_reload_sd_si_store
;
2732 reg_addr
[SDmode
].reload_load
= CODE_FOR_reload_sd_si_load
;
2734 if (TARGET_VSX_TIMODE
)
2736 reg_addr
[TImode
].reload_store
= CODE_FOR_reload_ti_si_store
;
2737 reg_addr
[TImode
].reload_load
= CODE_FOR_reload_ti_si_load
;
2742 /* Precalculate HARD_REGNO_NREGS. */
2743 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2744 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2745 rs6000_hard_regno_nregs
[m
][r
]
2746 = rs6000_hard_regno_nregs_internal (r
, (enum machine_mode
)m
);
2748 /* Precalculate HARD_REGNO_MODE_OK. */
2749 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2750 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2751 if (rs6000_hard_regno_mode_ok (r
, (enum machine_mode
)m
))
2752 rs6000_hard_regno_mode_ok_p
[m
][r
] = true;
2754 /* Precalculate CLASS_MAX_NREGS sizes. */
2755 for (c
= 0; c
< LIM_REG_CLASSES
; ++c
)
2759 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
))
2760 reg_size
= UNITS_PER_VSX_WORD
;
2762 else if (c
== ALTIVEC_REGS
)
2763 reg_size
= UNITS_PER_ALTIVEC_WORD
;
2765 else if (c
== FLOAT_REGS
)
2766 reg_size
= UNITS_PER_FP_WORD
;
2769 reg_size
= UNITS_PER_WORD
;
2771 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2773 int reg_size2
= reg_size
;
2775 /* TFmode/TDmode always takes 2 registers, even in VSX. */
2776 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
)
2777 && (m
== TDmode
|| m
== TFmode
))
2778 reg_size2
= UNITS_PER_FP_WORD
;
2780 rs6000_class_max_nregs
[m
][c
]
2781 = (GET_MODE_SIZE (m
) + reg_size2
- 1) / reg_size2
;
2785 if (TARGET_E500_DOUBLE
)
2786 rs6000_class_max_nregs
[DFmode
][GENERAL_REGS
] = 1;
2788 /* Calculate which modes to automatically generate code to use a the
2789 reciprocal divide and square root instructions. In the future, possibly
2790 automatically generate the instructions even if the user did not specify
2791 -mrecip. The older machines double precision reciprocal sqrt estimate is
2792 not accurate enough. */
2793 memset (rs6000_recip_bits
, 0, sizeof (rs6000_recip_bits
));
2795 rs6000_recip_bits
[SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2797 rs6000_recip_bits
[DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2798 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
2799 rs6000_recip_bits
[V4SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2800 if (VECTOR_UNIT_VSX_P (V2DFmode
))
2801 rs6000_recip_bits
[V2DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2803 if (TARGET_FRSQRTES
)
2804 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2806 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2807 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
2808 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2809 if (VECTOR_UNIT_VSX_P (V2DFmode
))
2810 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2812 if (rs6000_recip_control
)
2814 if (!flag_finite_math_only
)
2815 warning (0, "-mrecip requires -ffinite-math or -ffast-math");
2816 if (flag_trapping_math
)
2817 warning (0, "-mrecip requires -fno-trapping-math or -ffast-math");
2818 if (!flag_reciprocal_math
)
2819 warning (0, "-mrecip requires -freciprocal-math or -ffast-math");
2820 if (flag_finite_math_only
&& !flag_trapping_math
&& flag_reciprocal_math
)
2822 if (RS6000_RECIP_HAVE_RE_P (SFmode
)
2823 && (rs6000_recip_control
& RECIP_SF_DIV
) != 0)
2824 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2826 if (RS6000_RECIP_HAVE_RE_P (DFmode
)
2827 && (rs6000_recip_control
& RECIP_DF_DIV
) != 0)
2828 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2830 if (RS6000_RECIP_HAVE_RE_P (V4SFmode
)
2831 && (rs6000_recip_control
& RECIP_V4SF_DIV
) != 0)
2832 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2834 if (RS6000_RECIP_HAVE_RE_P (V2DFmode
)
2835 && (rs6000_recip_control
& RECIP_V2DF_DIV
) != 0)
2836 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2838 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode
)
2839 && (rs6000_recip_control
& RECIP_SF_RSQRT
) != 0)
2840 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2842 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode
)
2843 && (rs6000_recip_control
& RECIP_DF_RSQRT
) != 0)
2844 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2846 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode
)
2847 && (rs6000_recip_control
& RECIP_V4SF_RSQRT
) != 0)
2848 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2850 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode
)
2851 && (rs6000_recip_control
& RECIP_V2DF_RSQRT
) != 0)
2852 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2856 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2857 legitimate address support to figure out the appropriate addressing to
2859 rs6000_setup_reg_addr_masks ();
2861 if (global_init_p
|| TARGET_DEBUG_TARGET
)
2863 if (TARGET_DEBUG_REG
)
2864 rs6000_debug_reg_global ();
2866 if (TARGET_DEBUG_COST
|| TARGET_DEBUG_REG
)
2868 "SImode variable mult cost = %d\n"
2869 "SImode constant mult cost = %d\n"
2870 "SImode short constant mult cost = %d\n"
2871 "DImode multipliciation cost = %d\n"
2872 "SImode division cost = %d\n"
2873 "DImode division cost = %d\n"
2874 "Simple fp operation cost = %d\n"
2875 "DFmode multiplication cost = %d\n"
2876 "SFmode division cost = %d\n"
2877 "DFmode division cost = %d\n"
2878 "cache line size = %d\n"
2879 "l1 cache size = %d\n"
2880 "l2 cache size = %d\n"
2881 "simultaneous prefetches = %d\n"
2884 rs6000_cost
->mulsi_const
,
2885 rs6000_cost
->mulsi_const9
,
2893 rs6000_cost
->cache_line_size
,
2894 rs6000_cost
->l1_cache_size
,
2895 rs6000_cost
->l2_cache_size
,
2896 rs6000_cost
->simultaneous_prefetches
);
2901 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
2904 darwin_rs6000_override_options (void)
2906 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
2908 rs6000_altivec_abi
= 1;
2909 TARGET_ALTIVEC_VRSAVE
= 1;
2910 rs6000_current_abi
= ABI_DARWIN
;
2912 if (DEFAULT_ABI
== ABI_DARWIN
2914 darwin_one_byte_bool
= 1;
2916 if (TARGET_64BIT
&& ! TARGET_POWERPC64
)
2918 rs6000_isa_flags
|= OPTION_MASK_POWERPC64
;
2919 warning (0, "-m64 requires PowerPC64 architecture, enabling");
2923 rs6000_default_long_calls
= 1;
2924 rs6000_isa_flags
|= OPTION_MASK_SOFT_FLOAT
;
2927 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
2929 if (!flag_mkernel
&& !flag_apple_kext
2931 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
))
2932 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
2934 /* Unless the user (not the configurer) has explicitly overridden
2935 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
2936 G4 unless targeting the kernel. */
2939 && strverscmp (darwin_macosx_version_min
, "10.5") >= 0
2940 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
)
2941 && ! global_options_set
.x_rs6000_cpu_index
)
2943 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
2948 /* If not otherwise specified by a target, make 'long double' equivalent to
2951 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
2952 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
2955 /* Return the builtin mask of the various options used that could affect which
2956 builtins were used. In the past we used target_flags, but we've run out of
2957 bits, and some options like SPE and PAIRED are no longer in
2961 rs6000_builtin_mask_calculate (void)
2963 return (((TARGET_ALTIVEC
) ? RS6000_BTM_ALTIVEC
: 0)
2964 | ((TARGET_VSX
) ? RS6000_BTM_VSX
: 0)
2965 | ((TARGET_SPE
) ? RS6000_BTM_SPE
: 0)
2966 | ((TARGET_PAIRED_FLOAT
) ? RS6000_BTM_PAIRED
: 0)
2967 | ((TARGET_FRE
) ? RS6000_BTM_FRE
: 0)
2968 | ((TARGET_FRES
) ? RS6000_BTM_FRES
: 0)
2969 | ((TARGET_FRSQRTE
) ? RS6000_BTM_FRSQRTE
: 0)
2970 | ((TARGET_FRSQRTES
) ? RS6000_BTM_FRSQRTES
: 0)
2971 | ((TARGET_POPCNTD
) ? RS6000_BTM_POPCNTD
: 0)
2972 | ((rs6000_cpu
== PROCESSOR_CELL
) ? RS6000_BTM_CELL
: 0)
2973 | ((TARGET_P8_VECTOR
) ? RS6000_BTM_P8_VECTOR
: 0)
2974 | ((TARGET_CRYPTO
) ? RS6000_BTM_CRYPTO
: 0)
2975 | ((TARGET_HTM
) ? RS6000_BTM_HTM
: 0));
2978 /* Override command line options. Mostly we process the processor type and
2979 sometimes adjust other TARGET_ options. */
2982 rs6000_option_override_internal (bool global_init_p
)
2985 bool have_cpu
= false;
2987 /* The default cpu requested at configure time, if any. */
2988 const char *implicit_cpu
= OPTION_TARGET_CPU_DEFAULT
;
2990 HOST_WIDE_INT set_masks
;
2993 struct cl_target_option
*main_target_opt
2994 = ((global_init_p
|| target_option_default_node
== NULL
)
2995 ? NULL
: TREE_TARGET_OPTION (target_option_default_node
));
2997 /* Remember the explicit arguments. */
2999 rs6000_isa_flags_explicit
= global_options_set
.x_rs6000_isa_flags
;
3001 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
3002 library functions, so warn about it. The flag may be useful for
3003 performance studies from time to time though, so don't disable it
3005 if (global_options_set
.x_rs6000_alignment_flags
3006 && rs6000_alignment_flags
== MASK_ALIGN_POWER
3007 && DEFAULT_ABI
== ABI_DARWIN
3009 warning (0, "-malign-power is not supported for 64-bit Darwin;"
3010 " it is incompatible with the installed C and C++ libraries");
3012 /* Numerous experiment shows that IRA based loop pressure
3013 calculation works better for RTL loop invariant motion on targets
3014 with enough (>= 32) registers. It is an expensive optimization.
3015 So it is on only for peak performance. */
3016 if (optimize
>= 3 && global_init_p
)
3017 flag_ira_loop_pressure
= 1;
3019 /* Set the pointer size. */
3022 rs6000_pmode
= (int)DImode
;
3023 rs6000_pointer_size
= 64;
3027 rs6000_pmode
= (int)SImode
;
3028 rs6000_pointer_size
= 32;
3031 /* Some OSs don't support saving the high part of 64-bit registers on context
3032 switch. Other OSs don't support saving Altivec registers. On those OSs,
3033 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
3034 if the user wants either, the user must explicitly specify them and we
3035 won't interfere with the user's specification. */
3037 set_masks
= POWERPC_MASKS
;
3038 #ifdef OS_MISSING_POWERPC64
3039 if (OS_MISSING_POWERPC64
)
3040 set_masks
&= ~OPTION_MASK_POWERPC64
;
3042 #ifdef OS_MISSING_ALTIVEC
3043 if (OS_MISSING_ALTIVEC
)
3044 set_masks
&= ~(OPTION_MASK_ALTIVEC
| OPTION_MASK_VSX
);
3047 /* Don't override by the processor default if given explicitly. */
3048 set_masks
&= ~rs6000_isa_flags_explicit
;
3050 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
3051 the cpu in a target attribute or pragma, but did not specify a tuning
3052 option, use the cpu for the tuning option rather than the option specified
3053 with -mtune on the command line. Process a '--with-cpu' configuration
3054 request as an implicit --cpu. */
3055 if (rs6000_cpu_index
>= 0)
3057 cpu_index
= rs6000_cpu_index
;
3060 else if (main_target_opt
!= NULL
&& main_target_opt
->x_rs6000_cpu_index
>= 0)
3062 rs6000_cpu_index
= cpu_index
= main_target_opt
->x_rs6000_cpu_index
;
3065 else if (implicit_cpu
)
3067 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (implicit_cpu
);
3072 const char *default_cpu
= (TARGET_POWERPC64
? "powerpc64" : "powerpc");
3073 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (default_cpu
);
3077 gcc_assert (cpu_index
>= 0);
3079 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
3080 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
3081 with those from the cpu, except for options that were explicitly set. If
3082 we don't have a cpu, do not override the target bits set in
3086 rs6000_isa_flags
&= ~set_masks
;
3087 rs6000_isa_flags
|= (processor_target_table
[cpu_index
].target_enable
3091 rs6000_isa_flags
|= (processor_target_table
[cpu_index
].target_enable
3092 & ~rs6000_isa_flags_explicit
);
3094 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
3095 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
3096 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
3097 to using rs6000_isa_flags, we need to do the initialization here. */
3099 rs6000_isa_flags
|= (TARGET_DEFAULT
& ~rs6000_isa_flags_explicit
);
3101 if (rs6000_tune_index
>= 0)
3102 tune_index
= rs6000_tune_index
;
3104 rs6000_tune_index
= tune_index
= cpu_index
;
3108 enum processor_type tune_proc
3109 = (TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
);
3112 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
3113 if (processor_target_table
[i
].processor
== tune_proc
)
3115 rs6000_tune_index
= tune_index
= i
;
3120 gcc_assert (tune_index
>= 0);
3121 rs6000_cpu
= processor_target_table
[tune_index
].processor
;
3123 /* Pick defaults for SPE related control flags. Do this early to make sure
3124 that the TARGET_ macros are representative ASAP. */
3126 int spe_capable_cpu
=
3127 (rs6000_cpu
== PROCESSOR_PPC8540
3128 || rs6000_cpu
== PROCESSOR_PPC8548
);
3130 if (!global_options_set
.x_rs6000_spe_abi
)
3131 rs6000_spe_abi
= spe_capable_cpu
;
3133 if (!global_options_set
.x_rs6000_spe
)
3134 rs6000_spe
= spe_capable_cpu
;
3136 if (!global_options_set
.x_rs6000_float_gprs
)
3138 (rs6000_cpu
== PROCESSOR_PPC8540
? 1
3139 : rs6000_cpu
== PROCESSOR_PPC8548
? 2
3143 if (global_options_set
.x_rs6000_spe_abi
3146 error ("not configured for SPE ABI");
3148 if (global_options_set
.x_rs6000_spe
3151 error ("not configured for SPE instruction set");
3153 if (main_target_opt
!= NULL
3154 && ((main_target_opt
->x_rs6000_spe_abi
!= rs6000_spe_abi
)
3155 || (main_target_opt
->x_rs6000_spe
!= rs6000_spe
)
3156 || (main_target_opt
->x_rs6000_float_gprs
!= rs6000_float_gprs
)))
3157 error ("target attribute or pragma changes SPE ABI");
3159 if (rs6000_cpu
== PROCESSOR_PPCE300C2
|| rs6000_cpu
== PROCESSOR_PPCE300C3
3160 || rs6000_cpu
== PROCESSOR_PPCE500MC
|| rs6000_cpu
== PROCESSOR_PPCE500MC64
3161 || rs6000_cpu
== PROCESSOR_PPCE5500
)
3164 error ("AltiVec not supported in this target");
3166 error ("SPE not supported in this target");
3168 if (rs6000_cpu
== PROCESSOR_PPCE6500
)
3171 error ("SPE not supported in this target");
3174 /* Disable Cell microcode if we are optimizing for the Cell
3175 and not optimizing for size. */
3176 if (rs6000_gen_cell_microcode
== -1)
3177 rs6000_gen_cell_microcode
= !(rs6000_cpu
== PROCESSOR_CELL
3180 /* If we are optimizing big endian systems for space and it's OK to
3181 use instructions that would be microcoded on the Cell, use the
3182 load/store multiple and string instructions. */
3183 if (BYTES_BIG_ENDIAN
&& optimize_size
&& rs6000_gen_cell_microcode
)
3184 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& (OPTION_MASK_MULTIPLE
3185 | OPTION_MASK_STRING
);
3187 /* Don't allow -mmultiple or -mstring on little endian systems
3188 unless the cpu is a 750, because the hardware doesn't support the
3189 instructions used in little endian mode, and causes an alignment
3190 trap. The 750 does not cause an alignment trap (except when the
3191 target is unaligned). */
3193 if (!BYTES_BIG_ENDIAN
&& rs6000_cpu
!= PROCESSOR_PPC750
)
3195 if (TARGET_MULTIPLE
)
3197 rs6000_isa_flags
&= ~OPTION_MASK_MULTIPLE
;
3198 if ((rs6000_isa_flags_explicit
& OPTION_MASK_MULTIPLE
) != 0)
3199 warning (0, "-mmultiple is not supported on little endian systems");
3204 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
3205 if ((rs6000_isa_flags_explicit
& OPTION_MASK_STRING
) != 0)
3206 warning (0, "-mstring is not supported on little endian systems");
3210 /* Add some warnings for VSX. */
3213 const char *msg
= NULL
;
3214 if (!TARGET_HARD_FLOAT
|| !TARGET_FPRS
3215 || !TARGET_SINGLE_FLOAT
|| !TARGET_DOUBLE_FLOAT
)
3217 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
3218 msg
= N_("-mvsx requires hardware floating point");
3221 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
3222 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
3225 else if (TARGET_PAIRED_FLOAT
)
3226 msg
= N_("-mvsx and -mpaired are incompatible");
3227 else if (TARGET_AVOID_XFORM
> 0)
3228 msg
= N_("-mvsx needs indexed addressing");
3229 else if (!TARGET_ALTIVEC
&& (rs6000_isa_flags_explicit
3230 & OPTION_MASK_ALTIVEC
))
3232 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
3233 msg
= N_("-mvsx and -mno-altivec are incompatible");
3235 msg
= N_("-mno-altivec disables vsx");
3241 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
3242 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
3246 /* If hard-float/altivec/vsx were explicitly turned off then don't allow
3247 the -mcpu setting to enable options that conflict. */
3248 if ((!TARGET_HARD_FLOAT
|| !TARGET_ALTIVEC
|| !TARGET_VSX
)
3249 && (rs6000_isa_flags_explicit
& (OPTION_MASK_SOFT_FLOAT
3250 | OPTION_MASK_ALTIVEC
3251 | OPTION_MASK_VSX
)) != 0)
3252 rs6000_isa_flags
&= ~((OPTION_MASK_P8_VECTOR
| OPTION_MASK_CRYPTO
3253 | OPTION_MASK_DIRECT_MOVE
)
3254 & ~rs6000_isa_flags_explicit
);
3256 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3257 rs6000_print_isa_options (stderr
, 0, "before defaults", rs6000_isa_flags
);
3259 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
3260 unless the user explicitly used the -mno-<option> to disable the code. */
3261 if (TARGET_P8_VECTOR
|| TARGET_DIRECT_MOVE
|| TARGET_CRYPTO
)
3262 rs6000_isa_flags
|= (ISA_2_7_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3263 else if (TARGET_VSX
)
3264 rs6000_isa_flags
|= (ISA_2_6_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3265 else if (TARGET_POPCNTD
)
3266 rs6000_isa_flags
|= (ISA_2_6_MASKS_EMBEDDED
& ~rs6000_isa_flags_explicit
);
3267 else if (TARGET_DFP
)
3268 rs6000_isa_flags
|= (ISA_2_5_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3269 else if (TARGET_CMPB
)
3270 rs6000_isa_flags
|= (ISA_2_5_MASKS_EMBEDDED
& ~rs6000_isa_flags_explicit
);
3271 else if (TARGET_FPRND
)
3272 rs6000_isa_flags
|= (ISA_2_4_MASKS
& ~rs6000_isa_flags_explicit
);
3273 else if (TARGET_POPCNTB
)
3274 rs6000_isa_flags
|= (ISA_2_2_MASKS
& ~rs6000_isa_flags_explicit
);
3275 else if (TARGET_ALTIVEC
)
3276 rs6000_isa_flags
|= (OPTION_MASK_PPC_GFXOPT
& ~rs6000_isa_flags_explicit
);
3278 if (TARGET_CRYPTO
&& !TARGET_ALTIVEC
)
3280 if (rs6000_isa_flags_explicit
& OPTION_MASK_CRYPTO
)
3281 error ("-mcrypto requires -maltivec");
3282 rs6000_isa_flags
&= ~OPTION_MASK_CRYPTO
;
3285 if (TARGET_DIRECT_MOVE
&& !TARGET_VSX
)
3287 if (rs6000_isa_flags_explicit
& OPTION_MASK_DIRECT_MOVE
)
3288 error ("-mdirect-move requires -mvsx");
3289 rs6000_isa_flags
&= ~OPTION_MASK_DIRECT_MOVE
;
3292 if (TARGET_P8_VECTOR
&& !TARGET_ALTIVEC
)
3294 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
3295 error ("-mpower8-vector requires -maltivec");
3296 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
3299 if (TARGET_P8_VECTOR
&& !TARGET_VSX
)
3301 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
3302 error ("-mpower8-vector requires -mvsx");
3303 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
3306 if (TARGET_VSX_TIMODE
&& !TARGET_VSX
)
3308 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX_TIMODE
)
3309 error ("-mvsx-timode requires -mvsx");
3310 rs6000_isa_flags
&= ~OPTION_MASK_VSX_TIMODE
;
3313 /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
3314 silently turn off quad memory mode. */
3315 if (TARGET_QUAD_MEMORY
&& !TARGET_POWERPC64
)
3317 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY
) != 0)
3318 warning (0, N_("-mquad-memory requires 64-bit mode"));
3320 rs6000_isa_flags
&= ~OPTION_MASK_QUAD_MEMORY
;
3323 /* Enable power8 fusion if we are tuning for power8, even if we aren't
3324 generating power8 instructions. */
3325 if (!(rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION
))
3326 rs6000_isa_flags
|= (processor_target_table
[tune_index
].target_enable
3327 & OPTION_MASK_P8_FUSION
);
3329 /* Power8 does not fuse sign extended loads with the addis. If we are
3330 optimizing at high levels for speed, convert a sign extended load into a
3331 zero extending load, and an explicit sign extension. */
3332 if (TARGET_P8_FUSION
3333 && !(rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION_SIGN
)
3334 && optimize_function_for_speed_p (cfun
)
3336 rs6000_isa_flags
|= OPTION_MASK_P8_FUSION_SIGN
;
3338 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3339 rs6000_print_isa_options (stderr
, 0, "after defaults", rs6000_isa_flags
);
3341 /* E500mc does "better" if we inline more aggressively. Respect the
3342 user's opinion, though. */
3343 if (rs6000_block_move_inline_limit
== 0
3344 && (rs6000_cpu
== PROCESSOR_PPCE500MC
3345 || rs6000_cpu
== PROCESSOR_PPCE500MC64
3346 || rs6000_cpu
== PROCESSOR_PPCE5500
3347 || rs6000_cpu
== PROCESSOR_PPCE6500
))
3348 rs6000_block_move_inline_limit
= 128;
3350 /* store_one_arg depends on expand_block_move to handle at least the
3351 size of reg_parm_stack_space. */
3352 if (rs6000_block_move_inline_limit
< (TARGET_POWERPC64
? 64 : 32))
3353 rs6000_block_move_inline_limit
= (TARGET_POWERPC64
? 64 : 32);
3357 /* If the appropriate debug option is enabled, replace the target hooks
3358 with debug versions that call the real version and then prints
3359 debugging information. */
3360 if (TARGET_DEBUG_COST
)
3362 targetm
.rtx_costs
= rs6000_debug_rtx_costs
;
3363 targetm
.address_cost
= rs6000_debug_address_cost
;
3364 targetm
.sched
.adjust_cost
= rs6000_debug_adjust_cost
;
3367 if (TARGET_DEBUG_ADDR
)
3369 targetm
.legitimate_address_p
= rs6000_debug_legitimate_address_p
;
3370 targetm
.legitimize_address
= rs6000_debug_legitimize_address
;
3371 rs6000_secondary_reload_class_ptr
3372 = rs6000_debug_secondary_reload_class
;
3373 rs6000_secondary_memory_needed_ptr
3374 = rs6000_debug_secondary_memory_needed
;
3375 rs6000_cannot_change_mode_class_ptr
3376 = rs6000_debug_cannot_change_mode_class
;
3377 rs6000_preferred_reload_class_ptr
3378 = rs6000_debug_preferred_reload_class
;
3379 rs6000_legitimize_reload_address_ptr
3380 = rs6000_debug_legitimize_reload_address
;
3381 rs6000_mode_dependent_address_ptr
3382 = rs6000_debug_mode_dependent_address
;
3385 if (rs6000_veclibabi_name
)
3387 if (strcmp (rs6000_veclibabi_name
, "mass") == 0)
3388 rs6000_veclib_handler
= rs6000_builtin_vectorized_libmass
;
3391 error ("unknown vectorization library ABI type (%s) for "
3392 "-mveclibabi= switch", rs6000_veclibabi_name
);
3398 if (!global_options_set
.x_rs6000_long_double_type_size
)
3400 if (main_target_opt
!= NULL
3401 && (main_target_opt
->x_rs6000_long_double_type_size
3402 != RS6000_DEFAULT_LONG_DOUBLE_SIZE
))
3403 error ("target attribute or pragma changes long double size");
3405 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
3408 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
3409 if (!global_options_set
.x_rs6000_ieeequad
)
3410 rs6000_ieeequad
= 1;
3413 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
3414 target attribute or pragma which automatically enables both options,
3415 unless the altivec ABI was set. This is set by default for 64-bit, but
3417 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
3418 rs6000_isa_flags
&= ~((OPTION_MASK_VSX
| OPTION_MASK_ALTIVEC
)
3419 & ~rs6000_isa_flags_explicit
);
3421 /* Enable Altivec ABI for AIX -maltivec. */
3422 if (TARGET_XCOFF
&& (TARGET_ALTIVEC
|| TARGET_VSX
))
3424 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
3425 error ("target attribute or pragma changes AltiVec ABI");
3427 rs6000_altivec_abi
= 1;
3430 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
3431 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
3432 be explicitly overridden in either case. */
3435 if (!global_options_set
.x_rs6000_altivec_abi
3436 && (TARGET_64BIT
|| TARGET_ALTIVEC
|| TARGET_VSX
))
3438 if (main_target_opt
!= NULL
&&
3439 !main_target_opt
->x_rs6000_altivec_abi
)
3440 error ("target attribute or pragma changes AltiVec ABI");
3442 rs6000_altivec_abi
= 1;
3446 /* Set the Darwin64 ABI as default for 64-bit Darwin.
3447 So far, the only darwin64 targets are also MACH-O. */
3449 && DEFAULT_ABI
== ABI_DARWIN
3452 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_darwin64_abi
)
3453 error ("target attribute or pragma changes darwin64 ABI");
3456 rs6000_darwin64_abi
= 1;
3457 /* Default to natural alignment, for better performance. */
3458 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
3462 /* Place FP constants in the constant pool instead of TOC
3463 if section anchors enabled. */
3464 if (flag_section_anchors
3465 && !global_options_set
.x_TARGET_NO_FP_IN_TOC
)
3466 TARGET_NO_FP_IN_TOC
= 1;
3468 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3469 rs6000_print_isa_options (stderr
, 0, "before subtarget", rs6000_isa_flags
);
3471 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3472 SUBTARGET_OVERRIDE_OPTIONS
;
3474 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3475 SUBSUBTARGET_OVERRIDE_OPTIONS
;
3477 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
3478 SUB3TARGET_OVERRIDE_OPTIONS
;
3481 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3482 rs6000_print_isa_options (stderr
, 0, "after subtarget", rs6000_isa_flags
);
3484 /* For the E500 family of cores, reset the single/double FP flags to let us
3485 check that they remain constant across attributes or pragmas. Also,
3486 clear a possible request for string instructions, not supported and which
3487 we might have silently queried above for -Os.
3489 For other families, clear ISEL in case it was set implicitly.
3494 case PROCESSOR_PPC8540
:
3495 case PROCESSOR_PPC8548
:
3496 case PROCESSOR_PPCE500MC
:
3497 case PROCESSOR_PPCE500MC64
:
3498 case PROCESSOR_PPCE5500
:
3499 case PROCESSOR_PPCE6500
:
3501 rs6000_single_float
= TARGET_E500_SINGLE
|| TARGET_E500_DOUBLE
;
3502 rs6000_double_float
= TARGET_E500_DOUBLE
;
3504 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
3510 if (have_cpu
&& !(rs6000_isa_flags_explicit
& OPTION_MASK_ISEL
))
3511 rs6000_isa_flags
&= ~OPTION_MASK_ISEL
;
3516 if (main_target_opt
)
3518 if (main_target_opt
->x_rs6000_single_float
!= rs6000_single_float
)
3519 error ("target attribute or pragma changes single precision floating "
3521 if (main_target_opt
->x_rs6000_double_float
!= rs6000_double_float
)
3522 error ("target attribute or pragma changes double precision floating "
3526 /* Detect invalid option combinations with E500. */
3529 rs6000_always_hint
= (rs6000_cpu
!= PROCESSOR_POWER4
3530 && rs6000_cpu
!= PROCESSOR_POWER5
3531 && rs6000_cpu
!= PROCESSOR_POWER6
3532 && rs6000_cpu
!= PROCESSOR_POWER7
3533 && rs6000_cpu
!= PROCESSOR_POWER8
3534 && rs6000_cpu
!= PROCESSOR_PPCA2
3535 && rs6000_cpu
!= PROCESSOR_CELL
3536 && rs6000_cpu
!= PROCESSOR_PPC476
);
3537 rs6000_sched_groups
= (rs6000_cpu
== PROCESSOR_POWER4
3538 || rs6000_cpu
== PROCESSOR_POWER5
3539 || rs6000_cpu
== PROCESSOR_POWER7
3540 || rs6000_cpu
== PROCESSOR_POWER8
);
3541 rs6000_align_branch_targets
= (rs6000_cpu
== PROCESSOR_POWER4
3542 || rs6000_cpu
== PROCESSOR_POWER5
3543 || rs6000_cpu
== PROCESSOR_POWER6
3544 || rs6000_cpu
== PROCESSOR_POWER7
3545 || rs6000_cpu
== PROCESSOR_POWER8
3546 || rs6000_cpu
== PROCESSOR_PPCE500MC
3547 || rs6000_cpu
== PROCESSOR_PPCE500MC64
3548 || rs6000_cpu
== PROCESSOR_PPCE5500
3549 || rs6000_cpu
== PROCESSOR_PPCE6500
);
3551 /* Allow debug switches to override the above settings. These are set to -1
3552 in rs6000.opt to indicate the user hasn't directly set the switch. */
3553 if (TARGET_ALWAYS_HINT
>= 0)
3554 rs6000_always_hint
= TARGET_ALWAYS_HINT
;
3556 if (TARGET_SCHED_GROUPS
>= 0)
3557 rs6000_sched_groups
= TARGET_SCHED_GROUPS
;
3559 if (TARGET_ALIGN_BRANCH_TARGETS
>= 0)
3560 rs6000_align_branch_targets
= TARGET_ALIGN_BRANCH_TARGETS
;
3562 rs6000_sched_restricted_insns_priority
3563 = (rs6000_sched_groups
? 1 : 0);
3565 /* Handle -msched-costly-dep option. */
3566 rs6000_sched_costly_dep
3567 = (rs6000_sched_groups
? true_store_to_load_dep_costly
: no_dep_costly
);
3569 if (rs6000_sched_costly_dep_str
)
3571 if (! strcmp (rs6000_sched_costly_dep_str
, "no"))
3572 rs6000_sched_costly_dep
= no_dep_costly
;
3573 else if (! strcmp (rs6000_sched_costly_dep_str
, "all"))
3574 rs6000_sched_costly_dep
= all_deps_costly
;
3575 else if (! strcmp (rs6000_sched_costly_dep_str
, "true_store_to_load"))
3576 rs6000_sched_costly_dep
= true_store_to_load_dep_costly
;
3577 else if (! strcmp (rs6000_sched_costly_dep_str
, "store_to_load"))
3578 rs6000_sched_costly_dep
= store_to_load_dep_costly
;
3580 rs6000_sched_costly_dep
= ((enum rs6000_dependence_cost
)
3581 atoi (rs6000_sched_costly_dep_str
));
3584 /* Handle -minsert-sched-nops option. */
3585 rs6000_sched_insert_nops
3586 = (rs6000_sched_groups
? sched_finish_regroup_exact
: sched_finish_none
);
3588 if (rs6000_sched_insert_nops_str
)
3590 if (! strcmp (rs6000_sched_insert_nops_str
, "no"))
3591 rs6000_sched_insert_nops
= sched_finish_none
;
3592 else if (! strcmp (rs6000_sched_insert_nops_str
, "pad"))
3593 rs6000_sched_insert_nops
= sched_finish_pad_groups
;
3594 else if (! strcmp (rs6000_sched_insert_nops_str
, "regroup_exact"))
3595 rs6000_sched_insert_nops
= sched_finish_regroup_exact
;
3597 rs6000_sched_insert_nops
= ((enum rs6000_nop_insertion
)
3598 atoi (rs6000_sched_insert_nops_str
));
3603 #ifdef TARGET_REGNAMES
3604 /* If the user desires alternate register names, copy in the
3605 alternate names now. */
3606 if (TARGET_REGNAMES
)
3607 memcpy (rs6000_reg_names
, alt_reg_names
, sizeof (rs6000_reg_names
));
3610 /* Set aix_struct_return last, after the ABI is determined.
3611 If -maix-struct-return or -msvr4-struct-return was explicitly
3612 used, don't override with the ABI default. */
3613 if (!global_options_set
.x_aix_struct_return
)
3614 aix_struct_return
= (DEFAULT_ABI
!= ABI_V4
|| DRAFT_V4_STRUCT_RET
);
3617 /* IBM XL compiler defaults to unsigned bitfields. */
3618 if (TARGET_XL_COMPAT
)
3619 flag_signed_bitfields
= 0;
3622 if (TARGET_LONG_DOUBLE_128
&& !TARGET_IEEEQUAD
)
3623 REAL_MODE_FORMAT (TFmode
) = &ibm_extended_format
;
3626 ASM_GENERATE_INTERNAL_LABEL (toc_label_name
, "LCTOC", 1);
3628 /* We can only guarantee the availability of DI pseudo-ops when
3629 assembling for 64-bit targets. */
3632 targetm
.asm_out
.aligned_op
.di
= NULL
;
3633 targetm
.asm_out
.unaligned_op
.di
= NULL
;
3637 /* Set branch target alignment, if not optimizing for size. */
3640 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
3641 aligned 8byte to avoid misprediction by the branch predictor. */
3642 if (rs6000_cpu
== PROCESSOR_TITAN
3643 || rs6000_cpu
== PROCESSOR_CELL
)
3645 if (align_functions
<= 0)
3646 align_functions
= 8;
3647 if (align_jumps
<= 0)
3649 if (align_loops
<= 0)
3652 if (rs6000_align_branch_targets
)
3654 if (align_functions
<= 0)
3655 align_functions
= 16;
3656 if (align_jumps
<= 0)
3658 if (align_loops
<= 0)
3660 can_override_loop_align
= 1;
3664 if (align_jumps_max_skip
<= 0)
3665 align_jumps_max_skip
= 15;
3666 if (align_loops_max_skip
<= 0)
3667 align_loops_max_skip
= 15;
3670 /* Arrange to save and restore machine status around nested functions. */
3671 init_machine_status
= rs6000_init_machine_status
;
3673 /* We should always be splitting complex arguments, but we can't break
3674 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
3675 if (DEFAULT_ABI
!= ABI_AIX
)
3676 targetm
.calls
.split_complex_arg
= NULL
;
3679 /* Initialize rs6000_cost with the appropriate target costs. */
3681 rs6000_cost
= TARGET_POWERPC64
? &size64_cost
: &size32_cost
;
3685 case PROCESSOR_RS64A
:
3686 rs6000_cost
= &rs64a_cost
;
3689 case PROCESSOR_MPCCORE
:
3690 rs6000_cost
= &mpccore_cost
;
3693 case PROCESSOR_PPC403
:
3694 rs6000_cost
= &ppc403_cost
;
3697 case PROCESSOR_PPC405
:
3698 rs6000_cost
= &ppc405_cost
;
3701 case PROCESSOR_PPC440
:
3702 rs6000_cost
= &ppc440_cost
;
3705 case PROCESSOR_PPC476
:
3706 rs6000_cost
= &ppc476_cost
;
3709 case PROCESSOR_PPC601
:
3710 rs6000_cost
= &ppc601_cost
;
3713 case PROCESSOR_PPC603
:
3714 rs6000_cost
= &ppc603_cost
;
3717 case PROCESSOR_PPC604
:
3718 rs6000_cost
= &ppc604_cost
;
3721 case PROCESSOR_PPC604e
:
3722 rs6000_cost
= &ppc604e_cost
;
3725 case PROCESSOR_PPC620
:
3726 rs6000_cost
= &ppc620_cost
;
3729 case PROCESSOR_PPC630
:
3730 rs6000_cost
= &ppc630_cost
;
3733 case PROCESSOR_CELL
:
3734 rs6000_cost
= &ppccell_cost
;
3737 case PROCESSOR_PPC750
:
3738 case PROCESSOR_PPC7400
:
3739 rs6000_cost
= &ppc750_cost
;
3742 case PROCESSOR_PPC7450
:
3743 rs6000_cost
= &ppc7450_cost
;
3746 case PROCESSOR_PPC8540
:
3747 case PROCESSOR_PPC8548
:
3748 rs6000_cost
= &ppc8540_cost
;
3751 case PROCESSOR_PPCE300C2
:
3752 case PROCESSOR_PPCE300C3
:
3753 rs6000_cost
= &ppce300c2c3_cost
;
3756 case PROCESSOR_PPCE500MC
:
3757 rs6000_cost
= &ppce500mc_cost
;
3760 case PROCESSOR_PPCE500MC64
:
3761 rs6000_cost
= &ppce500mc64_cost
;
3764 case PROCESSOR_PPCE5500
:
3765 rs6000_cost
= &ppce5500_cost
;
3768 case PROCESSOR_PPCE6500
:
3769 rs6000_cost
= &ppce6500_cost
;
3772 case PROCESSOR_TITAN
:
3773 rs6000_cost
= &titan_cost
;
3776 case PROCESSOR_POWER4
:
3777 case PROCESSOR_POWER5
:
3778 rs6000_cost
= &power4_cost
;
3781 case PROCESSOR_POWER6
:
3782 rs6000_cost
= &power6_cost
;
3785 case PROCESSOR_POWER7
:
3786 rs6000_cost
= &power7_cost
;
3789 case PROCESSOR_POWER8
:
3790 rs6000_cost
= &power8_cost
;
3793 case PROCESSOR_PPCA2
:
3794 rs6000_cost
= &ppca2_cost
;
3803 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
3804 rs6000_cost
->simultaneous_prefetches
,
3805 global_options
.x_param_values
,
3806 global_options_set
.x_param_values
);
3807 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, rs6000_cost
->l1_cache_size
,
3808 global_options
.x_param_values
,
3809 global_options_set
.x_param_values
);
3810 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
3811 rs6000_cost
->cache_line_size
,
3812 global_options
.x_param_values
,
3813 global_options_set
.x_param_values
);
3814 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, rs6000_cost
->l2_cache_size
,
3815 global_options
.x_param_values
,
3816 global_options_set
.x_param_values
);
3818 /* Increase loop peeling limits based on performance analysis. */
3819 maybe_set_param_value (PARAM_MAX_PEELED_INSNS
, 400,
3820 global_options
.x_param_values
,
3821 global_options_set
.x_param_values
);
3822 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 400,
3823 global_options
.x_param_values
,
3824 global_options_set
.x_param_values
);
3826 /* If using typedef char *va_list, signal that
3827 __builtin_va_start (&ap, 0) can be optimized to
3828 ap = __builtin_next_arg (0). */
3829 if (DEFAULT_ABI
!= ABI_V4
)
3830 targetm
.expand_builtin_va_start
= NULL
;
3833 /* Set up single/double float flags.
3834 If TARGET_HARD_FLOAT is set, but neither single or double is set,
3835 then set both flags. */
3836 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
3837 && rs6000_single_float
== 0 && rs6000_double_float
== 0)
3838 rs6000_single_float
= rs6000_double_float
= 1;
3840 /* If not explicitly specified via option, decide whether to generate indexed
3841 load/store instructions. */
3842 if (TARGET_AVOID_XFORM
== -1)
3843 /* Avoid indexed addressing when targeting Power6 in order to avoid the
3844 DERAT mispredict penalty. However the LVE and STVE altivec instructions
3845 need indexed accesses and the type used is the scalar type of the element
3846 being loaded or stored. */
3847 TARGET_AVOID_XFORM
= (rs6000_cpu
== PROCESSOR_POWER6
&& TARGET_CMPB
3848 && !TARGET_ALTIVEC
);
3850 /* Set the -mrecip options. */
3851 if (rs6000_recip_name
)
3853 char *p
= ASTRDUP (rs6000_recip_name
);
3855 unsigned int mask
, i
;
3858 while ((q
= strtok (p
, ",")) != NULL
)
3869 if (!strcmp (q
, "default"))
3870 mask
= ((TARGET_RECIP_PRECISION
)
3871 ? RECIP_HIGH_PRECISION
: RECIP_LOW_PRECISION
);
3874 for (i
= 0; i
< ARRAY_SIZE (recip_options
); i
++)
3875 if (!strcmp (q
, recip_options
[i
].string
))
3877 mask
= recip_options
[i
].mask
;
3881 if (i
== ARRAY_SIZE (recip_options
))
3883 error ("unknown option for -mrecip=%s", q
);
3891 rs6000_recip_control
&= ~mask
;
3893 rs6000_recip_control
|= mask
;
3897 /* Set the builtin mask of the various options used that could affect which
3898 builtins were used. In the past we used target_flags, but we've run out
3899 of bits, and some options like SPE and PAIRED are no longer in
3901 rs6000_builtin_mask
= rs6000_builtin_mask_calculate ();
3902 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
3905 "new builtin mask = " HOST_WIDE_INT_PRINT_HEX
", ",
3906 rs6000_builtin_mask
);
3907 rs6000_print_builtin_options (stderr
, 0, NULL
, rs6000_builtin_mask
);
3910 /* Initialize all of the registers. */
3911 rs6000_init_hard_regno_mode_ok (global_init_p
);
3913 /* Save the initial options in case the user does function specific options */
3915 target_option_default_node
= target_option_current_node
3916 = build_target_option_node (&global_options
);
3918 /* If not explicitly specified via option, decide whether to generate the
3919 extra blr's required to preserve the link stack on some cpus (eg, 476). */
3920 if (TARGET_LINK_STACK
== -1)
3921 SET_TARGET_LINK_STACK (rs6000_cpu
== PROCESSOR_PPC476
&& flag_pic
);
3926 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
3927 define the target cpu type. */
3930 rs6000_option_override (void)
3932 (void) rs6000_option_override_internal (true);
3936 /* Implement targetm.vectorize.builtin_mask_for_load. */
3938 rs6000_builtin_mask_for_load (void)
3940 if (TARGET_ALTIVEC
|| TARGET_VSX
)
3941 return altivec_builtin_mask_for_load
;
3946 /* Implement LOOP_ALIGN. */
3948 rs6000_loop_align (rtx label
)
3953 /* Don't override loop alignment if -falign-loops was specified. */
3954 if (!can_override_loop_align
)
3955 return align_loops_log
;
3957 bb
= BLOCK_FOR_INSN (label
);
3958 ninsns
= num_loop_insns(bb
->loop_father
);
3960 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
3961 if (ninsns
> 4 && ninsns
<= 8
3962 && (rs6000_cpu
== PROCESSOR_POWER4
3963 || rs6000_cpu
== PROCESSOR_POWER5
3964 || rs6000_cpu
== PROCESSOR_POWER6
3965 || rs6000_cpu
== PROCESSOR_POWER7
3966 || rs6000_cpu
== PROCESSOR_POWER8
))
3969 return align_loops_log
;
3972 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
3974 rs6000_loop_align_max_skip (rtx label
)
3976 return (1 << rs6000_loop_align (label
)) - 1;
3979 /* Return true iff, data reference of TYPE can reach vector alignment (16)
3980 after applying N number of iterations. This routine does not determine
3981 how may iterations are required to reach desired alignment. */
3984 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED
, bool is_packed
)
3991 if (rs6000_alignment_flags
== MASK_ALIGN_NATURAL
)
3994 if (rs6000_alignment_flags
== MASK_ALIGN_POWER
)
4004 /* Assuming that all other types are naturally aligned. CHECKME! */
4009 /* Return true if the vector misalignment factor is supported by the
4012 rs6000_builtin_support_vector_misalignment (enum machine_mode mode
,
4019 /* Return if movmisalign pattern is not supported for this mode. */
4020 if (optab_handler (movmisalign_optab
, mode
) == CODE_FOR_nothing
)
4023 if (misalignment
== -1)
4025 /* Misalignment factor is unknown at compile time but we know
4026 it's word aligned. */
4027 if (rs6000_vector_alignment_reachable (type
, is_packed
))
4029 int element_size
= tree_to_hwi (TYPE_SIZE (type
));
4031 if (element_size
== 64 || element_size
== 32)
4038 /* VSX supports word-aligned vector. */
4039 if (misalignment
% 4 == 0)
4045 /* Implement targetm.vectorize.builtin_vectorization_cost. */
4047 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost
,
4048 tree vectype
, int misalign
)
4053 switch (type_of_cost
)
4063 case cond_branch_not_taken
:
4072 case vec_promote_demote
:
4078 case cond_branch_taken
:
4081 case unaligned_load
:
4082 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
4084 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
4086 /* Double word aligned. */
4094 /* Double word aligned. */
4098 /* Unknown misalignment. */
4111 /* Misaligned loads are not supported. */
4116 case unaligned_store
:
4117 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
4119 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
4121 /* Double word aligned. */
4129 /* Double word aligned. */
4133 /* Unknown misalignment. */
4146 /* Misaligned stores are not supported. */
4152 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
4153 elem_type
= TREE_TYPE (vectype
);
4154 /* 32-bit vectors loaded into registers are stored as double
4155 precision, so we need n/2 converts in addition to the usual
4156 n/2 merges to construct a vector of short floats from them. */
4157 if (SCALAR_FLOAT_TYPE_P (elem_type
)
4158 && TYPE_PRECISION (elem_type
) == 32)
4159 return elements
+ 1;
4161 return elements
/ 2 + 1;
4168 /* Implement targetm.vectorize.preferred_simd_mode. */
4170 static enum machine_mode
4171 rs6000_preferred_simd_mode (enum machine_mode mode
)
4180 if (TARGET_ALTIVEC
|| TARGET_VSX
)
4204 if (TARGET_PAIRED_FLOAT
4210 typedef struct _rs6000_cost_data
4212 struct loop
*loop_info
;
4216 /* Test for likely overcommitment of vector hardware resources. If a
4217 loop iteration is relatively large, and too large a percentage of
4218 instructions in the loop are vectorized, the cost model may not
4219 adequately reflect delays from unavailable vector resources.
4220 Penalize the loop body cost for this case. */
4223 rs6000_density_test (rs6000_cost_data
*data
)
4225 const int DENSITY_PCT_THRESHOLD
= 85;
4226 const int DENSITY_SIZE_THRESHOLD
= 70;
4227 const int DENSITY_PENALTY
= 10;
4228 struct loop
*loop
= data
->loop_info
;
4229 basic_block
*bbs
= get_loop_body (loop
);
4230 int nbbs
= loop
->num_nodes
;
4231 int vec_cost
= data
->cost
[vect_body
], not_vec_cost
= 0;
4234 for (i
= 0; i
< nbbs
; i
++)
4236 basic_block bb
= bbs
[i
];
4237 gimple_stmt_iterator gsi
;
4239 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
4241 gimple stmt
= gsi_stmt (gsi
);
4242 stmt_vec_info stmt_info
= vinfo_for_stmt (stmt
);
4244 if (!STMT_VINFO_RELEVANT_P (stmt_info
)
4245 && !STMT_VINFO_IN_PATTERN_P (stmt_info
))
4251 density_pct
= (vec_cost
* 100) / (vec_cost
+ not_vec_cost
);
4253 if (density_pct
> DENSITY_PCT_THRESHOLD
4254 && vec_cost
+ not_vec_cost
> DENSITY_SIZE_THRESHOLD
)
4256 data
->cost
[vect_body
] = vec_cost
* (100 + DENSITY_PENALTY
) / 100;
4257 if (dump_enabled_p ())
4258 dump_printf_loc (MSG_NOTE
, vect_location
,
4259 "density %d%%, cost %d exceeds threshold, penalizing "
4260 "loop body cost by %d%%", density_pct
,
4261 vec_cost
+ not_vec_cost
, DENSITY_PENALTY
);
4265 /* Implement targetm.vectorize.init_cost. */
4268 rs6000_init_cost (struct loop
*loop_info
)
4270 rs6000_cost_data
*data
= XNEW (struct _rs6000_cost_data
);
4271 data
->loop_info
= loop_info
;
4272 data
->cost
[vect_prologue
] = 0;
4273 data
->cost
[vect_body
] = 0;
4274 data
->cost
[vect_epilogue
] = 0;
4278 /* Implement targetm.vectorize.add_stmt_cost. */
4281 rs6000_add_stmt_cost (void *data
, int count
, enum vect_cost_for_stmt kind
,
4282 struct _stmt_vec_info
*stmt_info
, int misalign
,
4283 enum vect_cost_model_location where
)
4285 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
4286 unsigned retval
= 0;
4288 if (flag_vect_cost_model
)
4290 tree vectype
= stmt_info
? stmt_vectype (stmt_info
) : NULL_TREE
;
4291 int stmt_cost
= rs6000_builtin_vectorization_cost (kind
, vectype
,
4293 /* Statements in an inner loop relative to the loop being
4294 vectorized are weighted more heavily. The value here is
4295 arbitrary and could potentially be improved with analysis. */
4296 if (where
== vect_body
&& stmt_info
&& stmt_in_inner_loop_p (stmt_info
))
4297 count
*= 50; /* FIXME. */
4299 retval
= (unsigned) (count
* stmt_cost
);
4300 cost_data
->cost
[where
] += retval
;
4306 /* Implement targetm.vectorize.finish_cost. */
4309 rs6000_finish_cost (void *data
, unsigned *prologue_cost
,
4310 unsigned *body_cost
, unsigned *epilogue_cost
)
4312 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
4314 if (cost_data
->loop_info
)
4315 rs6000_density_test (cost_data
);
4317 *prologue_cost
= cost_data
->cost
[vect_prologue
];
4318 *body_cost
= cost_data
->cost
[vect_body
];
4319 *epilogue_cost
= cost_data
->cost
[vect_epilogue
];
4322 /* Implement targetm.vectorize.destroy_cost_data. */
4325 rs6000_destroy_cost_data (void *data
)
4330 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
4331 library with vectorized intrinsics. */
4334 rs6000_builtin_vectorized_libmass (tree fndecl
, tree type_out
, tree type_in
)
4337 const char *suffix
= NULL
;
4338 tree fntype
, new_fndecl
, bdecl
= NULL_TREE
;
4341 enum machine_mode el_mode
, in_mode
;
4344 /* Libmass is suitable for unsafe math only as it does not correctly support
4345 parts of IEEE with the required precision such as denormals. Only support
4346 it if we have VSX to use the simd d2 or f4 functions.
4347 XXX: Add variable length support. */
4348 if (!flag_unsafe_math_optimizations
|| !TARGET_VSX
)
4351 el_mode
= TYPE_MODE (TREE_TYPE (type_out
));
4352 n
= TYPE_VECTOR_SUBPARTS (type_out
);
4353 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
4354 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
4355 if (el_mode
!= in_mode
4359 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_NORMAL
)
4361 enum built_in_function fn
= DECL_FUNCTION_CODE (fndecl
);
4364 case BUILT_IN_ATAN2
:
4365 case BUILT_IN_HYPOT
:
4371 case BUILT_IN_ACOSH
:
4373 case BUILT_IN_ASINH
:
4375 case BUILT_IN_ATANH
:
4383 case BUILT_IN_EXPM1
:
4384 case BUILT_IN_LGAMMA
:
4385 case BUILT_IN_LOG10
:
4386 case BUILT_IN_LOG1P
:
4394 bdecl
= builtin_decl_implicit (fn
);
4395 suffix
= "d2"; /* pow -> powd2 */
4396 if (el_mode
!= DFmode
4402 case BUILT_IN_ATAN2F
:
4403 case BUILT_IN_HYPOTF
:
4408 case BUILT_IN_ACOSF
:
4409 case BUILT_IN_ACOSHF
:
4410 case BUILT_IN_ASINF
:
4411 case BUILT_IN_ASINHF
:
4412 case BUILT_IN_ATANF
:
4413 case BUILT_IN_ATANHF
:
4414 case BUILT_IN_CBRTF
:
4416 case BUILT_IN_COSHF
:
4418 case BUILT_IN_ERFCF
:
4419 case BUILT_IN_EXP2F
:
4421 case BUILT_IN_EXPM1F
:
4422 case BUILT_IN_LGAMMAF
:
4423 case BUILT_IN_LOG10F
:
4424 case BUILT_IN_LOG1PF
:
4425 case BUILT_IN_LOG2F
:
4428 case BUILT_IN_SINHF
:
4429 case BUILT_IN_SQRTF
:
4431 case BUILT_IN_TANHF
:
4432 bdecl
= builtin_decl_implicit (fn
);
4433 suffix
= "4"; /* powf -> powf4 */
4434 if (el_mode
!= SFmode
4447 gcc_assert (suffix
!= NULL
);
4448 bname
= IDENTIFIER_POINTER (DECL_NAME (bdecl
));
4452 strcpy (name
, bname
+ sizeof ("__builtin_") - 1);
4453 strcat (name
, suffix
);
4456 fntype
= build_function_type_list (type_out
, type_in
, NULL
);
4457 else if (n_args
== 2)
4458 fntype
= build_function_type_list (type_out
, type_in
, type_in
, NULL
);
4462 /* Build a function declaration for the vectorized function. */
4463 new_fndecl
= build_decl (BUILTINS_LOCATION
,
4464 FUNCTION_DECL
, get_identifier (name
), fntype
);
4465 TREE_PUBLIC (new_fndecl
) = 1;
4466 DECL_EXTERNAL (new_fndecl
) = 1;
4467 DECL_IS_NOVOPS (new_fndecl
) = 1;
4468 TREE_READONLY (new_fndecl
) = 1;
4473 /* Returns a function decl for a vectorized version of the builtin function
4474 with builtin function code FN and the result vector type TYPE, or NULL_TREE
4475 if it is not available. */
4478 rs6000_builtin_vectorized_function (tree fndecl
, tree type_out
,
4481 enum machine_mode in_mode
, out_mode
;
4484 if (TARGET_DEBUG_BUILTIN
)
4485 fprintf (stderr
, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
4486 IDENTIFIER_POINTER (DECL_NAME (fndecl
)),
4487 GET_MODE_NAME (TYPE_MODE (type_out
)),
4488 GET_MODE_NAME (TYPE_MODE (type_in
)));
4490 if (TREE_CODE (type_out
) != VECTOR_TYPE
4491 || TREE_CODE (type_in
) != VECTOR_TYPE
4492 || !TARGET_VECTORIZE_BUILTINS
)
4495 out_mode
= TYPE_MODE (TREE_TYPE (type_out
));
4496 out_n
= TYPE_VECTOR_SUBPARTS (type_out
);
4497 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
4498 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
4500 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_NORMAL
)
4502 enum built_in_function fn
= DECL_FUNCTION_CODE (fndecl
);
4505 case BUILT_IN_CLZIMAX
:
4506 case BUILT_IN_CLZLL
:
4509 if (TARGET_P8_VECTOR
&& in_mode
== out_mode
&& out_n
== in_n
)
4511 if (out_mode
== QImode
&& out_n
== 16)
4512 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZB
];
4513 else if (out_mode
== HImode
&& out_n
== 8)
4514 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZH
];
4515 else if (out_mode
== SImode
&& out_n
== 4)
4516 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZW
];
4517 else if (out_mode
== DImode
&& out_n
== 2)
4518 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZD
];
4521 case BUILT_IN_COPYSIGN
:
4522 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4523 && out_mode
== DFmode
&& out_n
== 2
4524 && in_mode
== DFmode
&& in_n
== 2)
4525 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNDP
];
4527 case BUILT_IN_COPYSIGNF
:
4528 if (out_mode
!= SFmode
|| out_n
!= 4
4529 || in_mode
!= SFmode
|| in_n
!= 4)
4531 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4532 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNSP
];
4533 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4534 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_COPYSIGN_V4SF
];
4536 case BUILT_IN_POPCOUNTIMAX
:
4537 case BUILT_IN_POPCOUNTLL
:
4538 case BUILT_IN_POPCOUNTL
:
4539 case BUILT_IN_POPCOUNT
:
4540 if (TARGET_P8_VECTOR
&& in_mode
== out_mode
&& out_n
== in_n
)
4542 if (out_mode
== QImode
&& out_n
== 16)
4543 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTB
];
4544 else if (out_mode
== HImode
&& out_n
== 8)
4545 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTH
];
4546 else if (out_mode
== SImode
&& out_n
== 4)
4547 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTW
];
4548 else if (out_mode
== DImode
&& out_n
== 2)
4549 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTD
];
4553 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4554 && out_mode
== DFmode
&& out_n
== 2
4555 && in_mode
== DFmode
&& in_n
== 2)
4556 return rs6000_builtin_decls
[VSX_BUILTIN_XVSQRTDP
];
4558 case BUILT_IN_SQRTF
:
4559 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4560 && out_mode
== SFmode
&& out_n
== 4
4561 && in_mode
== SFmode
&& in_n
== 4)
4562 return rs6000_builtin_decls
[VSX_BUILTIN_XVSQRTSP
];
4565 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4566 && out_mode
== DFmode
&& out_n
== 2
4567 && in_mode
== DFmode
&& in_n
== 2)
4568 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIP
];
4570 case BUILT_IN_CEILF
:
4571 if (out_mode
!= SFmode
|| out_n
!= 4
4572 || in_mode
!= SFmode
|| in_n
!= 4)
4574 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4575 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIP
];
4576 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4577 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIP
];
4579 case BUILT_IN_FLOOR
:
4580 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4581 && out_mode
== DFmode
&& out_n
== 2
4582 && in_mode
== DFmode
&& in_n
== 2)
4583 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIM
];
4585 case BUILT_IN_FLOORF
:
4586 if (out_mode
!= SFmode
|| out_n
!= 4
4587 || in_mode
!= SFmode
|| in_n
!= 4)
4589 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4590 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIM
];
4591 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4592 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIM
];
4595 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4596 && out_mode
== DFmode
&& out_n
== 2
4597 && in_mode
== DFmode
&& in_n
== 2)
4598 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDDP
];
4601 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4602 && out_mode
== SFmode
&& out_n
== 4
4603 && in_mode
== SFmode
&& in_n
== 4)
4604 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDSP
];
4605 else if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
4606 && out_mode
== SFmode
&& out_n
== 4
4607 && in_mode
== SFmode
&& in_n
== 4)
4608 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMADDFP
];
4610 case BUILT_IN_TRUNC
:
4611 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4612 && out_mode
== DFmode
&& out_n
== 2
4613 && in_mode
== DFmode
&& in_n
== 2)
4614 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIZ
];
4616 case BUILT_IN_TRUNCF
:
4617 if (out_mode
!= SFmode
|| out_n
!= 4
4618 || in_mode
!= SFmode
|| in_n
!= 4)
4620 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4621 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIZ
];
4622 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4623 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIZ
];
4625 case BUILT_IN_NEARBYINT
:
4626 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4627 && flag_unsafe_math_optimizations
4628 && out_mode
== DFmode
&& out_n
== 2
4629 && in_mode
== DFmode
&& in_n
== 2)
4630 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPI
];
4632 case BUILT_IN_NEARBYINTF
:
4633 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4634 && flag_unsafe_math_optimizations
4635 && out_mode
== SFmode
&& out_n
== 4
4636 && in_mode
== SFmode
&& in_n
== 4)
4637 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPI
];
4640 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4641 && !flag_trapping_math
4642 && out_mode
== DFmode
&& out_n
== 2
4643 && in_mode
== DFmode
&& in_n
== 2)
4644 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIC
];
4646 case BUILT_IN_RINTF
:
4647 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4648 && !flag_trapping_math
4649 && out_mode
== SFmode
&& out_n
== 4
4650 && in_mode
== SFmode
&& in_n
== 4)
4651 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIC
];
4658 else if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_MD
)
4660 enum rs6000_builtins fn
4661 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
4664 case RS6000_BUILTIN_RSQRTF
:
4665 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
4666 && out_mode
== SFmode
&& out_n
== 4
4667 && in_mode
== SFmode
&& in_n
== 4)
4668 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRSQRTFP
];
4670 case RS6000_BUILTIN_RSQRT
:
4671 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4672 && out_mode
== DFmode
&& out_n
== 2
4673 && in_mode
== DFmode
&& in_n
== 2)
4674 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
4676 case RS6000_BUILTIN_RECIPF
:
4677 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
4678 && out_mode
== SFmode
&& out_n
== 4
4679 && in_mode
== SFmode
&& in_n
== 4)
4680 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRECIPFP
];
4682 case RS6000_BUILTIN_RECIP
:
4683 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4684 && out_mode
== DFmode
&& out_n
== 2
4685 && in_mode
== DFmode
&& in_n
== 2)
4686 return rs6000_builtin_decls
[VSX_BUILTIN_RECIP_V2DF
];
4693 /* Generate calls to libmass if appropriate. */
4694 if (rs6000_veclib_handler
)
4695 return rs6000_veclib_handler (fndecl
, type_out
, type_in
);
4700 /* Default CPU string for rs6000*_file_start functions. */
4701 static const char *rs6000_default_cpu
;
4703 /* Do anything needed at the start of the asm file. */
4706 rs6000_file_start (void)
4709 const char *start
= buffer
;
4710 FILE *file
= asm_out_file
;
4712 rs6000_default_cpu
= TARGET_CPU_DEFAULT
;
4714 default_file_start ();
4716 if (flag_verbose_asm
)
4718 sprintf (buffer
, "\n%s rs6000/powerpc options:", ASM_COMMENT_START
);
4720 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
4722 fprintf (file
, "%s --with-cpu=%s", start
, rs6000_default_cpu
);
4726 if (global_options_set
.x_rs6000_cpu_index
)
4728 fprintf (file
, "%s -mcpu=%s", start
,
4729 processor_target_table
[rs6000_cpu_index
].name
);
4733 if (global_options_set
.x_rs6000_tune_index
)
4735 fprintf (file
, "%s -mtune=%s", start
,
4736 processor_target_table
[rs6000_tune_index
].name
);
4740 if (PPC405_ERRATUM77
)
4742 fprintf (file
, "%s PPC405CR_ERRATUM77", start
);
4746 #ifdef USING_ELFOS_H
4747 switch (rs6000_sdata
)
4749 case SDATA_NONE
: fprintf (file
, "%s -msdata=none", start
); start
= ""; break;
4750 case SDATA_DATA
: fprintf (file
, "%s -msdata=data", start
); start
= ""; break;
4751 case SDATA_SYSV
: fprintf (file
, "%s -msdata=sysv", start
); start
= ""; break;
4752 case SDATA_EABI
: fprintf (file
, "%s -msdata=eabi", start
); start
= ""; break;
4755 if (rs6000_sdata
&& g_switch_value
)
4757 fprintf (file
, "%s -G %d", start
,
4767 if (DEFAULT_ABI
== ABI_AIX
|| (TARGET_ELF
&& flag_pic
== 2))
4769 switch_to_section (toc_section
);
4770 switch_to_section (text_section
);
4775 /* Return nonzero if this function is known to have a null epilogue. */
4778 direct_return (void)
4780 if (reload_completed
)
4782 rs6000_stack_t
*info
= rs6000_stack_info ();
4784 if (info
->first_gp_reg_save
== 32
4785 && info
->first_fp_reg_save
== 64
4786 && info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
4787 && ! info
->lr_save_p
4788 && ! info
->cr_save_p
4789 && info
->vrsave_mask
== 0
4797 /* Return the number of instructions it takes to form a constant in an
4798 integer register. */
4801 num_insns_constant_wide (HOST_WIDE_INT value
)
4803 /* signed constant loadable with addi */
4804 if ((unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000)
4807 /* constant loadable with addis */
4808 else if ((value
& 0xffff) == 0
4809 && (value
>> 31 == -1 || value
>> 31 == 0))
4812 else if (TARGET_POWERPC64
)
4814 HOST_WIDE_INT low
= ((value
& 0xffffffff) ^ 0x80000000) - 0x80000000;
4815 HOST_WIDE_INT high
= value
>> 31;
4817 if (high
== 0 || high
== -1)
4823 return num_insns_constant_wide (high
) + 1;
4825 return num_insns_constant_wide (low
) + 1;
4827 return (num_insns_constant_wide (high
)
4828 + num_insns_constant_wide (low
) + 1);
4836 num_insns_constant (rtx op
, enum machine_mode mode
)
4838 HOST_WIDE_INT low
, high
;
4840 switch (GET_CODE (op
))
4843 if ((INTVAL (op
) >> 31) != 0 && (INTVAL (op
) >> 31) != -1
4844 && mask64_operand (op
, mode
))
4847 return num_insns_constant_wide (INTVAL (op
));
4849 case CONST_WIDE_INT
:
4852 int ins
= CONST_WIDE_INT_NUNITS (op
) - 1;
4853 for (i
= 0; i
< CONST_WIDE_INT_NUNITS (op
); i
++)
4854 ins
+= num_insns_constant_wide (CONST_WIDE_INT_ELT (op
, i
));
4859 if (mode
== SFmode
|| mode
== SDmode
)
4864 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
4865 if (DECIMAL_FLOAT_MODE_P (mode
))
4866 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
4868 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
4869 return num_insns_constant_wide ((HOST_WIDE_INT
) l
);
4875 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
4876 if (DECIMAL_FLOAT_MODE_P (mode
))
4877 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, l
);
4879 REAL_VALUE_TO_TARGET_DOUBLE (rv
, l
);
4880 high
= l
[WORDS_BIG_ENDIAN
== 0];
4881 low
= l
[WORDS_BIG_ENDIAN
!= 0];
4884 return (num_insns_constant_wide (low
)
4885 + num_insns_constant_wide (high
));
4888 if ((high
== 0 && low
>= 0)
4889 || (high
== -1 && low
< 0))
4890 return num_insns_constant_wide (low
);
4892 else if (mask64_operand (op
, mode
))
4896 return num_insns_constant_wide (high
) + 1;
4899 return (num_insns_constant_wide (high
)
4900 + num_insns_constant_wide (low
) + 1);
4908 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
4909 If the mode of OP is MODE_VECTOR_INT, this simply returns the
4910 corresponding element of the vector, but for V4SFmode and V2SFmode,
4911 the corresponding "float" is interpreted as an SImode integer. */
4914 const_vector_elt_as_int (rtx op
, unsigned int elt
)
4918 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
4919 gcc_assert (GET_MODE (op
) != V2DImode
4920 && GET_MODE (op
) != V2DFmode
);
4922 tmp
= CONST_VECTOR_ELT (op
, elt
);
4923 if (GET_MODE (op
) == V4SFmode
4924 || GET_MODE (op
) == V2SFmode
)
4925 tmp
= gen_lowpart (SImode
, tmp
);
4926 return INTVAL (tmp
);
4929 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
4930 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
4931 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
4932 all items are set to the same value and contain COPIES replicas of the
4933 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
4934 operand and the others are set to the value of the operand's msb. */
4937 vspltis_constant (rtx op
, unsigned step
, unsigned copies
)
4939 enum machine_mode mode
= GET_MODE (op
);
4940 enum machine_mode inner
= GET_MODE_INNER (mode
);
4948 HOST_WIDE_INT splat_val
;
4949 HOST_WIDE_INT msb_val
;
4951 if (mode
== V2DImode
|| mode
== V2DFmode
)
4954 nunits
= GET_MODE_NUNITS (mode
);
4955 bitsize
= GET_MODE_BITSIZE (inner
);
4956 mask
= GET_MODE_MASK (inner
);
4958 val
= const_vector_elt_as_int (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
4960 msb_val
= val
> 0 ? 0 : -1;
4962 /* Construct the value to be splatted, if possible. If not, return 0. */
4963 for (i
= 2; i
<= copies
; i
*= 2)
4965 HOST_WIDE_INT small_val
;
4967 small_val
= splat_val
>> bitsize
;
4969 if (splat_val
!= ((small_val
<< bitsize
) | (small_val
& mask
)))
4971 splat_val
= small_val
;
4974 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
4975 if (EASY_VECTOR_15 (splat_val
))
4978 /* Also check if we can splat, and then add the result to itself. Do so if
4979 the value is positive, of if the splat instruction is using OP's mode;
4980 for splat_val < 0, the splat and the add should use the same mode. */
4981 else if (EASY_VECTOR_15_ADD_SELF (splat_val
)
4982 && (splat_val
>= 0 || (step
== 1 && copies
== 1)))
4985 /* Also check if are loading up the most significant bit which can be done by
4986 loading up -1 and shifting the value left by -1. */
4987 else if (EASY_VECTOR_MSB (splat_val
, inner
))
4993 /* Check if VAL is present in every STEP-th element, and the
4994 other elements are filled with its most significant bit. */
4995 for (i
= 1; i
< nunits
; ++i
)
4997 HOST_WIDE_INT desired_val
;
4998 unsigned elt
= BYTES_BIG_ENDIAN
? nunits
- 1 - i
: i
;
4999 if ((i
& (step
- 1)) == 0)
5002 desired_val
= msb_val
;
5004 if (desired_val
!= const_vector_elt_as_int (op
, elt
))
5012 /* Return true if OP is of the given MODE and can be synthesized
5013 with a vspltisb, vspltish or vspltisw. */
5016 easy_altivec_constant (rtx op
, enum machine_mode mode
)
5018 unsigned step
, copies
;
5020 if (mode
== VOIDmode
)
5021 mode
= GET_MODE (op
);
5022 else if (mode
!= GET_MODE (op
))
5025 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
5027 if (mode
== V2DFmode
)
5028 return zero_constant (op
, mode
);
5030 if (mode
== V2DImode
)
5032 /* In case the compiler is built 32-bit, CONST_WIDE_INT
5033 constants are not easy. */
5034 if (GET_CODE (CONST_VECTOR_ELT (op
, 0)) != CONST_INT
5035 || GET_CODE (CONST_VECTOR_ELT (op
, 1)) != CONST_INT
)
5038 if (zero_constant (op
, mode
))
5041 if (INTVAL (CONST_VECTOR_ELT (op
, 0)) == -1
5042 && INTVAL (CONST_VECTOR_ELT (op
, 1)) == -1)
5048 /* Start with a vspltisw. */
5049 step
= GET_MODE_NUNITS (mode
) / 4;
5052 if (vspltis_constant (op
, step
, copies
))
5055 /* Then try with a vspltish. */
5061 if (vspltis_constant (op
, step
, copies
))
5064 /* And finally a vspltisb. */
5070 if (vspltis_constant (op
, step
, copies
))
5076 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
5077 result is OP. Abort if it is not possible. */
5080 gen_easy_altivec_constant (rtx op
)
5082 enum machine_mode mode
= GET_MODE (op
);
5083 int nunits
= GET_MODE_NUNITS (mode
);
5084 rtx val
= CONST_VECTOR_ELT (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
5085 unsigned step
= nunits
/ 4;
5086 unsigned copies
= 1;
5088 /* Start with a vspltisw. */
5089 if (vspltis_constant (op
, step
, copies
))
5090 return gen_rtx_VEC_DUPLICATE (V4SImode
, gen_lowpart (SImode
, val
));
5092 /* Then try with a vspltish. */
5098 if (vspltis_constant (op
, step
, copies
))
5099 return gen_rtx_VEC_DUPLICATE (V8HImode
, gen_lowpart (HImode
, val
));
5101 /* And finally a vspltisb. */
5107 if (vspltis_constant (op
, step
, copies
))
5108 return gen_rtx_VEC_DUPLICATE (V16QImode
, gen_lowpart (QImode
, val
));
5114 output_vec_const_move (rtx
*operands
)
5117 enum machine_mode mode
;
5122 mode
= GET_MODE (dest
);
5126 if (zero_constant (vec
, mode
))
5127 return "xxlxor %x0,%x0,%x0";
5129 if (mode
== V2DImode
5130 && INTVAL (CONST_VECTOR_ELT (vec
, 0)) == -1
5131 && INTVAL (CONST_VECTOR_ELT (vec
, 1)) == -1)
5132 return "vspltisw %0,-1";
5138 if (zero_constant (vec
, mode
))
5139 return "vxor %0,%0,%0";
5141 splat_vec
= gen_easy_altivec_constant (vec
);
5142 gcc_assert (GET_CODE (splat_vec
) == VEC_DUPLICATE
);
5143 operands
[1] = XEXP (splat_vec
, 0);
5144 if (!EASY_VECTOR_15 (INTVAL (operands
[1])))
5147 switch (GET_MODE (splat_vec
))
5150 return "vspltisw %0,%1";
5153 return "vspltish %0,%1";
5156 return "vspltisb %0,%1";
5163 gcc_assert (TARGET_SPE
);
5165 /* Vector constant 0 is handled as a splitter of V2SI, and in the
5166 pattern of V1DI, V4HI, and V2SF.
5168 FIXME: We should probably return # and add post reload
5169 splitters for these, but this way is so easy ;-). */
5170 cst
= INTVAL (CONST_VECTOR_ELT (vec
, 0));
5171 cst2
= INTVAL (CONST_VECTOR_ELT (vec
, 1));
5172 operands
[1] = CONST_VECTOR_ELT (vec
, 0);
5173 operands
[2] = CONST_VECTOR_ELT (vec
, 1);
5175 return "li %0,%1\n\tevmergelo %0,%0,%0";
5177 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
5180 /* Initialize TARGET of vector PAIRED to VALS. */
5183 paired_expand_vector_init (rtx target
, rtx vals
)
5185 enum machine_mode mode
= GET_MODE (target
);
5186 int n_elts
= GET_MODE_NUNITS (mode
);
5188 rtx x
, new_rtx
, tmp
, constant_op
, op1
, op2
;
5191 for (i
= 0; i
< n_elts
; ++i
)
5193 x
= XVECEXP (vals
, 0, i
);
5194 if (!CONSTANT_P (x
))
5199 /* Load from constant pool. */
5200 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
5206 /* The vector is initialized only with non-constants. */
5207 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, XVECEXP (vals
, 0, 0),
5208 XVECEXP (vals
, 0, 1));
5210 emit_move_insn (target
, new_rtx
);
5214 /* One field is non-constant and the other one is a constant. Load the
5215 constant from the constant pool and use ps_merge instruction to
5216 construct the whole vector. */
5217 op1
= XVECEXP (vals
, 0, 0);
5218 op2
= XVECEXP (vals
, 0, 1);
5220 constant_op
= (CONSTANT_P (op1
)) ? op1
: op2
;
5222 tmp
= gen_reg_rtx (GET_MODE (constant_op
));
5223 emit_move_insn (tmp
, constant_op
);
5225 if (CONSTANT_P (op1
))
5226 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, tmp
, op2
);
5228 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, op1
, tmp
);
5230 emit_move_insn (target
, new_rtx
);
5234 paired_expand_vector_move (rtx operands
[])
5236 rtx op0
= operands
[0], op1
= operands
[1];
5238 emit_move_insn (op0
, op1
);
5241 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
5242 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
5243 operands for the relation operation COND. This is a recursive
5247 paired_emit_vector_compare (enum rtx_code rcode
,
5248 rtx dest
, rtx op0
, rtx op1
,
5249 rtx cc_op0
, rtx cc_op1
)
5251 rtx tmp
= gen_reg_rtx (V2SFmode
);
5254 gcc_assert (TARGET_PAIRED_FLOAT
);
5255 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
5261 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5265 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
5266 emit_insn (gen_selv2sf4 (dest
, tmp
, op0
, op1
, CONST0_RTX (SFmode
)));
5270 paired_emit_vector_compare (GE
, dest
, op0
, op1
, cc_op1
, cc_op0
);
5273 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5276 tmp1
= gen_reg_rtx (V2SFmode
);
5277 max
= gen_reg_rtx (V2SFmode
);
5278 min
= gen_reg_rtx (V2SFmode
);
5279 gen_reg_rtx (V2SFmode
);
5281 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
5282 emit_insn (gen_selv2sf4
5283 (max
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
5284 emit_insn (gen_subv2sf3 (tmp
, cc_op1
, cc_op0
));
5285 emit_insn (gen_selv2sf4
5286 (min
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
5287 emit_insn (gen_subv2sf3 (tmp1
, min
, max
));
5288 emit_insn (gen_selv2sf4 (dest
, tmp1
, op0
, op1
, CONST0_RTX (SFmode
)));
5291 paired_emit_vector_compare (EQ
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5294 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5297 paired_emit_vector_compare (LT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5300 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5303 paired_emit_vector_compare (GT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5312 /* Emit vector conditional expression.
5313 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
5314 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
5317 paired_emit_vector_cond_expr (rtx dest
, rtx op1
, rtx op2
,
5318 rtx cond
, rtx cc_op0
, rtx cc_op1
)
5320 enum rtx_code rcode
= GET_CODE (cond
);
5322 if (!TARGET_PAIRED_FLOAT
)
5325 paired_emit_vector_compare (rcode
, dest
, op1
, op2
, cc_op0
, cc_op1
);
5330 /* Initialize vector TARGET to VALS. */
5333 rs6000_expand_vector_init (rtx target
, rtx vals
)
5335 enum machine_mode mode
= GET_MODE (target
);
5336 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
5337 int n_elts
= GET_MODE_NUNITS (mode
);
5338 int n_var
= 0, one_var
= -1;
5339 bool all_same
= true, all_const_zero
= true;
5343 for (i
= 0; i
< n_elts
; ++i
)
5345 x
= XVECEXP (vals
, 0, i
);
5346 if (!CONSTANT_P (x
))
5347 ++n_var
, one_var
= i
;
5348 else if (x
!= CONST0_RTX (inner_mode
))
5349 all_const_zero
= false;
5351 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
5357 rtx const_vec
= gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0));
5358 bool int_vector_p
= (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
);
5359 if ((int_vector_p
|| TARGET_VSX
) && all_const_zero
)
5361 /* Zero register. */
5362 emit_insn (gen_rtx_SET (VOIDmode
, target
,
5363 gen_rtx_XOR (mode
, target
, target
)));
5366 else if (int_vector_p
&& easy_vector_constant (const_vec
, mode
))
5368 /* Splat immediate. */
5369 emit_insn (gen_rtx_SET (VOIDmode
, target
, const_vec
));
5374 /* Load from constant pool. */
5375 emit_move_insn (target
, const_vec
);
5380 /* Double word values on VSX can use xxpermdi or lxvdsx. */
5381 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
5383 rtx op0
= XVECEXP (vals
, 0, 0);
5384 rtx op1
= XVECEXP (vals
, 0, 1);
5387 if (!MEM_P (op0
) && !REG_P (op0
))
5388 op0
= force_reg (inner_mode
, op0
);
5389 if (mode
== V2DFmode
)
5390 emit_insn (gen_vsx_splat_v2df (target
, op0
));
5392 emit_insn (gen_vsx_splat_v2di (target
, op0
));
5396 op0
= force_reg (inner_mode
, op0
);
5397 op1
= force_reg (inner_mode
, op1
);
5398 if (mode
== V2DFmode
)
5399 emit_insn (gen_vsx_concat_v2df (target
, op0
, op1
));
5401 emit_insn (gen_vsx_concat_v2di (target
, op0
, op1
));
5406 /* With single precision floating point on VSX, know that internally single
5407 precision is actually represented as a double, and either make 2 V2DF
5408 vectors, and convert these vectors to single precision, or do one
5409 conversion, and splat the result to the other elements. */
5410 if (mode
== V4SFmode
&& VECTOR_MEM_VSX_P (mode
))
5414 rtx freg
= gen_reg_rtx (V4SFmode
);
5415 rtx sreg
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
5416 rtx cvt
= ((TARGET_XSCVDPSPN
)
5417 ? gen_vsx_xscvdpspn_scalar (freg
, sreg
)
5418 : gen_vsx_xscvdpsp_scalar (freg
, sreg
));
5421 emit_insn (gen_vsx_xxspltw_v4sf (target
, freg
, const0_rtx
));
5425 rtx dbl_even
= gen_reg_rtx (V2DFmode
);
5426 rtx dbl_odd
= gen_reg_rtx (V2DFmode
);
5427 rtx flt_even
= gen_reg_rtx (V4SFmode
);
5428 rtx flt_odd
= gen_reg_rtx (V4SFmode
);
5429 rtx op0
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
5430 rtx op1
= force_reg (SFmode
, XVECEXP (vals
, 0, 1));
5431 rtx op2
= force_reg (SFmode
, XVECEXP (vals
, 0, 2));
5432 rtx op3
= force_reg (SFmode
, XVECEXP (vals
, 0, 3));
5434 emit_insn (gen_vsx_concat_v2sf (dbl_even
, op0
, op1
));
5435 emit_insn (gen_vsx_concat_v2sf (dbl_odd
, op2
, op3
));
5436 emit_insn (gen_vsx_xvcvdpsp (flt_even
, dbl_even
));
5437 emit_insn (gen_vsx_xvcvdpsp (flt_odd
, dbl_odd
));
5438 rs6000_expand_extract_even (target
, flt_even
, flt_odd
);
5443 /* Store value to stack temp. Load vector element. Splat. However, splat
5444 of 64-bit items is not supported on Altivec. */
5445 if (all_same
&& GET_MODE_SIZE (inner_mode
) <= 4)
5448 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
5449 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0),
5450 XVECEXP (vals
, 0, 0));
5451 x
= gen_rtx_UNSPEC (VOIDmode
,
5452 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
5453 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
5455 gen_rtx_SET (VOIDmode
,
5458 field
= (BYTES_BIG_ENDIAN
? const0_rtx
5459 : GEN_INT (GET_MODE_NUNITS (mode
) - 1));
5460 x
= gen_rtx_VEC_SELECT (inner_mode
, target
,
5461 gen_rtx_PARALLEL (VOIDmode
,
5462 gen_rtvec (1, field
)));
5463 emit_insn (gen_rtx_SET (VOIDmode
, target
,
5464 gen_rtx_VEC_DUPLICATE (mode
, x
)));
5468 /* One field is non-constant. Load constant then overwrite
5472 rtx copy
= copy_rtx (vals
);
5474 /* Load constant part of vector, substitute neighboring value for
5476 XVECEXP (copy
, 0, one_var
) = XVECEXP (vals
, 0, (one_var
+ 1) % n_elts
);
5477 rs6000_expand_vector_init (target
, copy
);
5479 /* Insert variable. */
5480 rs6000_expand_vector_set (target
, XVECEXP (vals
, 0, one_var
), one_var
);
5484 /* Construct the vector in memory one field at a time
5485 and load the whole vector. */
5486 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
5487 for (i
= 0; i
< n_elts
; i
++)
5488 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
5489 i
* GET_MODE_SIZE (inner_mode
)),
5490 XVECEXP (vals
, 0, i
));
5491 emit_move_insn (target
, mem
);
5494 /* Set field ELT of TARGET to VAL. */
5497 rs6000_expand_vector_set (rtx target
, rtx val
, int elt
)
5499 enum machine_mode mode
= GET_MODE (target
);
5500 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
5501 rtx reg
= gen_reg_rtx (mode
);
5503 int width
= GET_MODE_SIZE (inner_mode
);
5506 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
5508 rtx (*set_func
) (rtx
, rtx
, rtx
, rtx
)
5509 = ((mode
== V2DFmode
) ? gen_vsx_set_v2df
: gen_vsx_set_v2di
);
5510 emit_insn (set_func (target
, target
, val
, GEN_INT (elt
)));
5514 /* Load single variable value. */
5515 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
5516 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0), val
);
5517 x
= gen_rtx_UNSPEC (VOIDmode
,
5518 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
5519 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
5521 gen_rtx_SET (VOIDmode
,
5525 /* Linear sequence. */
5526 mask
= gen_rtx_PARALLEL (V16QImode
, rtvec_alloc (16));
5527 for (i
= 0; i
< 16; ++i
)
5528 XVECEXP (mask
, 0, i
) = GEN_INT (i
);
5530 /* Set permute mask to insert element into target. */
5531 for (i
= 0; i
< width
; ++i
)
5532 XVECEXP (mask
, 0, elt
*width
+ i
)
5533 = GEN_INT (i
+ 0x10);
5534 x
= gen_rtx_CONST_VECTOR (V16QImode
, XVEC (mask
, 0));
5536 if (BYTES_BIG_ENDIAN
)
5537 x
= gen_rtx_UNSPEC (mode
,
5538 gen_rtvec (3, target
, reg
,
5539 force_reg (V16QImode
, x
)),
5543 /* Invert selector. */
5544 rtx splat
= gen_rtx_VEC_DUPLICATE (V16QImode
,
5545 gen_rtx_CONST_INT (QImode
, -1));
5546 rtx tmp
= gen_reg_rtx (V16QImode
);
5547 emit_move_insn (tmp
, splat
);
5548 x
= gen_rtx_MINUS (V16QImode
, tmp
, force_reg (V16QImode
, x
));
5549 emit_move_insn (tmp
, x
);
5551 /* Permute with operands reversed and adjusted selector. */
5552 x
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, reg
, target
, tmp
),
5556 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
5559 /* Extract field ELT from VEC into TARGET. */
5562 rs6000_expand_vector_extract (rtx target
, rtx vec
, int elt
)
5564 enum machine_mode mode
= GET_MODE (vec
);
5565 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
5568 if (VECTOR_MEM_VSX_P (mode
))
5575 emit_insn (gen_vsx_extract_v2df (target
, vec
, GEN_INT (elt
)));
5578 emit_insn (gen_vsx_extract_v2di (target
, vec
, GEN_INT (elt
)));
5581 emit_insn (gen_vsx_extract_v4sf (target
, vec
, GEN_INT (elt
)));
5586 /* Allocate mode-sized buffer. */
5587 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
5589 emit_move_insn (mem
, vec
);
5591 /* Add offset to field within buffer matching vector element. */
5592 mem
= adjust_address_nv (mem
, inner_mode
, elt
* GET_MODE_SIZE (inner_mode
));
5594 emit_move_insn (target
, adjust_address_nv (mem
, inner_mode
, 0));
5597 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
5598 implement ANDing by the mask IN. */
5600 build_mask64_2_operands (rtx in
, rtx
*out
)
5602 unsigned HOST_WIDE_INT c
, lsb
, m1
, m2
;
5605 gcc_assert (GET_CODE (in
) == CONST_INT
);
5610 /* Assume c initially something like 0x00fff000000fffff. The idea
5611 is to rotate the word so that the middle ^^^^^^ group of zeros
5612 is at the MS end and can be cleared with an rldicl mask. We then
5613 rotate back and clear off the MS ^^ group of zeros with a
5615 c
= ~c
; /* c == 0xff000ffffff00000 */
5616 lsb
= c
& -c
; /* lsb == 0x0000000000100000 */
5617 m1
= -lsb
; /* m1 == 0xfffffffffff00000 */
5618 c
= ~c
; /* c == 0x00fff000000fffff */
5619 c
&= -lsb
; /* c == 0x00fff00000000000 */
5620 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
5621 c
= ~c
; /* c == 0xff000fffffffffff */
5622 c
&= -lsb
; /* c == 0xff00000000000000 */
5624 while ((lsb
>>= 1) != 0)
5625 shift
++; /* shift == 44 on exit from loop */
5626 m1
<<= 64 - shift
; /* m1 == 0xffffff0000000000 */
5627 m1
= ~m1
; /* m1 == 0x000000ffffffffff */
5628 m2
= ~c
; /* m2 == 0x00ffffffffffffff */
5632 /* Assume c initially something like 0xff000f0000000000. The idea
5633 is to rotate the word so that the ^^^ middle group of zeros
5634 is at the LS end and can be cleared with an rldicr mask. We then
5635 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
5637 lsb
= c
& -c
; /* lsb == 0x0000010000000000 */
5638 m2
= -lsb
; /* m2 == 0xffffff0000000000 */
5639 c
= ~c
; /* c == 0x00fff0ffffffffff */
5640 c
&= -lsb
; /* c == 0x00fff00000000000 */
5641 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
5642 c
= ~c
; /* c == 0xff000fffffffffff */
5643 c
&= -lsb
; /* c == 0xff00000000000000 */
5645 while ((lsb
>>= 1) != 0)
5646 shift
++; /* shift == 44 on exit from loop */
5647 m1
= ~c
; /* m1 == 0x00ffffffffffffff */
5648 m1
>>= shift
; /* m1 == 0x0000000000000fff */
5649 m1
= ~m1
; /* m1 == 0xfffffffffffff000 */
5652 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
5653 masks will be all 1's. We are guaranteed more than one transition. */
5654 out
[0] = GEN_INT (64 - shift
);
5655 out
[1] = GEN_INT (m1
);
5656 out
[2] = GEN_INT (shift
);
5657 out
[3] = GEN_INT (m2
);
5660 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
5663 invalid_e500_subreg (rtx op
, enum machine_mode mode
)
5665 if (TARGET_E500_DOUBLE
)
5667 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
5668 subreg:TI and reg:TF. Decimal float modes are like integer
5669 modes (only low part of each register used) for this
5671 if (GET_CODE (op
) == SUBREG
5672 && (mode
== SImode
|| mode
== DImode
|| mode
== TImode
5673 || mode
== DDmode
|| mode
== TDmode
|| mode
== PTImode
)
5674 && REG_P (SUBREG_REG (op
))
5675 && (GET_MODE (SUBREG_REG (op
)) == DFmode
5676 || GET_MODE (SUBREG_REG (op
)) == TFmode
))
5679 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
5681 if (GET_CODE (op
) == SUBREG
5682 && (mode
== DFmode
|| mode
== TFmode
)
5683 && REG_P (SUBREG_REG (op
))
5684 && (GET_MODE (SUBREG_REG (op
)) == DImode
5685 || GET_MODE (SUBREG_REG (op
)) == TImode
5686 || GET_MODE (SUBREG_REG (op
)) == PTImode
5687 || GET_MODE (SUBREG_REG (op
)) == DDmode
5688 || GET_MODE (SUBREG_REG (op
)) == TDmode
))
5693 && GET_CODE (op
) == SUBREG
5695 && REG_P (SUBREG_REG (op
))
5696 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op
))))
5702 /* Return alignment of TYPE. Existing alignment is ALIGN. HOW
5703 selects whether the alignment is abi mandated, optional, or
5704 both abi and optional alignment. */
5707 rs6000_data_alignment (tree type
, unsigned int align
, enum data_align how
)
5709 if (how
!= align_opt
)
5711 if (TREE_CODE (type
) == VECTOR_TYPE
)
5713 if ((TARGET_SPE
&& SPE_VECTOR_MODE (TYPE_MODE (type
)))
5714 || (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (TYPE_MODE (type
))))
5719 else if (align
< 128)
5722 else if (TARGET_E500_DOUBLE
5723 && TREE_CODE (type
) == REAL_TYPE
5724 && TYPE_MODE (type
) == DFmode
)
5731 if (how
!= align_abi
)
5733 if (TREE_CODE (type
) == ARRAY_TYPE
5734 && TYPE_MODE (TREE_TYPE (type
)) == QImode
)
5736 if (align
< BITS_PER_WORD
)
5737 align
= BITS_PER_WORD
;
5744 /* AIX increases natural record alignment to doubleword if the first
5745 field is an FP double while the FP fields remain word aligned. */
5748 rs6000_special_round_type_align (tree type
, unsigned int computed
,
5749 unsigned int specified
)
5751 unsigned int align
= MAX (computed
, specified
);
5752 tree field
= TYPE_FIELDS (type
);
5754 /* Skip all non field decls */
5755 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
5756 field
= DECL_CHAIN (field
);
5758 if (field
!= NULL
&& field
!= type
)
5760 type
= TREE_TYPE (field
);
5761 while (TREE_CODE (type
) == ARRAY_TYPE
)
5762 type
= TREE_TYPE (type
);
5764 if (type
!= error_mark_node
&& TYPE_MODE (type
) == DFmode
)
5765 align
= MAX (align
, 64);
5771 /* Darwin increases record alignment to the natural alignment of
5775 darwin_rs6000_special_round_type_align (tree type
, unsigned int computed
,
5776 unsigned int specified
)
5778 unsigned int align
= MAX (computed
, specified
);
5780 if (TYPE_PACKED (type
))
5783 /* Find the first field, looking down into aggregates. */
5785 tree field
= TYPE_FIELDS (type
);
5786 /* Skip all non field decls */
5787 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
5788 field
= DECL_CHAIN (field
);
5791 /* A packed field does not contribute any extra alignment. */
5792 if (DECL_PACKED (field
))
5794 type
= TREE_TYPE (field
);
5795 while (TREE_CODE (type
) == ARRAY_TYPE
)
5796 type
= TREE_TYPE (type
);
5797 } while (AGGREGATE_TYPE_P (type
));
5799 if (! AGGREGATE_TYPE_P (type
) && type
!= error_mark_node
)
5800 align
= MAX (align
, TYPE_ALIGN (type
));
5805 /* Return 1 for an operand in small memory on V.4/eabi. */
5808 small_data_operand (rtx op ATTRIBUTE_UNUSED
,
5809 enum machine_mode mode ATTRIBUTE_UNUSED
)
5814 if (rs6000_sdata
== SDATA_NONE
|| rs6000_sdata
== SDATA_DATA
)
5817 if (DEFAULT_ABI
!= ABI_V4
)
5820 /* Vector and float memory instructions have a limited offset on the
5821 SPE, so using a vector or float variable directly as an operand is
5824 && (SPE_VECTOR_MODE (mode
) || FLOAT_MODE_P (mode
)))
5827 if (GET_CODE (op
) == SYMBOL_REF
)
5830 else if (GET_CODE (op
) != CONST
5831 || GET_CODE (XEXP (op
, 0)) != PLUS
5832 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
5833 || GET_CODE (XEXP (XEXP (op
, 0), 1)) != CONST_INT
)
5838 rtx sum
= XEXP (op
, 0);
5839 HOST_WIDE_INT summand
;
5841 /* We have to be careful here, because it is the referenced address
5842 that must be 32k from _SDA_BASE_, not just the symbol. */
5843 summand
= INTVAL (XEXP (sum
, 1));
5844 if (summand
< 0 || summand
> g_switch_value
)
5847 sym_ref
= XEXP (sum
, 0);
5850 return SYMBOL_REF_SMALL_P (sym_ref
);
5856 /* Return true if either operand is a general purpose register. */
5859 gpr_or_gpr_p (rtx op0
, rtx op1
)
5861 return ((REG_P (op0
) && INT_REGNO_P (REGNO (op0
)))
5862 || (REG_P (op1
) && INT_REGNO_P (REGNO (op1
))));
5865 /* Return true if this is a move direct operation between GPR registers and
5866 floating point/VSX registers. */
5869 direct_move_p (rtx op0
, rtx op1
)
5873 if (!REG_P (op0
) || !REG_P (op1
))
5876 if (!TARGET_DIRECT_MOVE
&& !TARGET_MFPGPR
)
5879 regno0
= REGNO (op0
);
5880 regno1
= REGNO (op1
);
5881 if (regno0
>= FIRST_PSEUDO_REGISTER
|| regno1
>= FIRST_PSEUDO_REGISTER
)
5884 if (INT_REGNO_P (regno0
))
5885 return (TARGET_DIRECT_MOVE
) ? VSX_REGNO_P (regno1
) : FP_REGNO_P (regno1
);
5887 else if (INT_REGNO_P (regno1
))
5889 if (TARGET_MFPGPR
&& FP_REGNO_P (regno0
))
5892 else if (TARGET_DIRECT_MOVE
&& VSX_REGNO_P (regno0
))
5899 /* Return true if this is a load or store quad operation. */
5902 quad_load_store_p (rtx op0
, rtx op1
)
5906 if (!TARGET_QUAD_MEMORY
)
5909 else if (REG_P (op0
) && MEM_P (op1
))
5910 ret
= (quad_int_reg_operand (op0
, GET_MODE (op0
))
5911 && quad_memory_operand (op1
, GET_MODE (op1
))
5912 && !reg_overlap_mentioned_p (op0
, op1
));
5914 else if (MEM_P (op0
) && REG_P (op1
))
5915 ret
= (quad_memory_operand (op0
, GET_MODE (op0
))
5916 && quad_int_reg_operand (op1
, GET_MODE (op1
)));
5921 if (TARGET_DEBUG_ADDR
)
5923 fprintf (stderr
, "\n========== quad_load_store, return %s\n",
5924 ret
? "true" : "false");
5925 debug_rtx (gen_rtx_SET (VOIDmode
, op0
, op1
));
5931 /* Given an address, return a constant offset term if one exists. */
5934 address_offset (rtx op
)
5936 if (GET_CODE (op
) == PRE_INC
5937 || GET_CODE (op
) == PRE_DEC
)
5939 else if (GET_CODE (op
) == PRE_MODIFY
5940 || GET_CODE (op
) == LO_SUM
)
5943 if (GET_CODE (op
) == CONST
)
5946 if (GET_CODE (op
) == PLUS
)
5949 if (CONST_INT_P (op
))
5955 /* Return true if the MEM operand is a memory operand suitable for use
5956 with a (full width, possibly multiple) gpr load/store. On
5957 powerpc64 this means the offset must be divisible by 4.
5958 Implements 'Y' constraint.
5960 Accept direct, indexed, offset, lo_sum and tocref. Since this is
5961 a constraint function we know the operand has satisfied a suitable
5962 memory predicate. Also accept some odd rtl generated by reload
5963 (see rs6000_legitimize_reload_address for various forms). It is
5964 important that reload rtl be accepted by appropriate constraints
5965 but not by the operand predicate.
5967 Offsetting a lo_sum should not be allowed, except where we know by
5968 alignment that a 32k boundary is not crossed, but see the ???
5969 comment in rs6000_legitimize_reload_address. Note that by
5970 "offsetting" here we mean a further offset to access parts of the
5971 MEM. It's fine to have a lo_sum where the inner address is offset
5972 from a sym, since the same sym+offset will appear in the high part
5973 of the address calculation. */
5976 mem_operand_gpr (rtx op
, enum machine_mode mode
)
5978 unsigned HOST_WIDE_INT offset
;
5980 rtx addr
= XEXP (op
, 0);
5982 op
= address_offset (addr
);
5986 offset
= INTVAL (op
);
5987 if (TARGET_POWERPC64
&& (offset
& 3) != 0)
5990 extra
= GET_MODE_SIZE (mode
) - UNITS_PER_WORD
;
5991 gcc_assert (extra
>= 0);
5993 if (GET_CODE (addr
) == LO_SUM
)
5994 /* For lo_sum addresses, we must allow any offset except one that
5995 causes a wrap, so test only the low 16 bits. */
5996 offset
= ((offset
& 0xffff) ^ 0x8000) - 0x8000;
5998 return offset
+ 0x8000 < 0x10000u
- extra
;
6001 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
6004 reg_offset_addressing_ok_p (enum machine_mode mode
)
6015 /* AltiVec/VSX vector modes. Only reg+reg addressing is valid. While
6016 TImode is not a vector mode, if we want to use the VSX registers to
6017 move it around, we need to restrict ourselves to reg+reg
6019 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
6027 /* Paired vector modes. Only reg+reg addressing is valid. */
6028 if (TARGET_PAIRED_FLOAT
)
6033 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
6034 addressing for the LFIWZX and STFIWX instructions. */
6035 if (TARGET_NO_SDMODE_STACK
)
6047 virtual_stack_registers_memory_p (rtx op
)
6051 if (GET_CODE (op
) == REG
)
6052 regnum
= REGNO (op
);
6054 else if (GET_CODE (op
) == PLUS
6055 && GET_CODE (XEXP (op
, 0)) == REG
6056 && GET_CODE (XEXP (op
, 1)) == CONST_INT
)
6057 regnum
= REGNO (XEXP (op
, 0));
6062 return (regnum
>= FIRST_VIRTUAL_REGISTER
6063 && regnum
<= LAST_VIRTUAL_POINTER_REGISTER
);
6066 /* Return true if a MODE sized memory accesses to OP plus OFFSET
6067 is known to not straddle a 32k boundary. */
6070 offsettable_ok_by_alignment (rtx op
, HOST_WIDE_INT offset
,
6071 enum machine_mode mode
)
6074 unsigned HOST_WIDE_INT dsize
, dalign
, lsb
, mask
;
6076 if (GET_CODE (op
) != SYMBOL_REF
)
6079 dsize
= GET_MODE_SIZE (mode
);
6080 decl
= SYMBOL_REF_DECL (op
);
6086 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
6087 replacing memory addresses with an anchor plus offset. We
6088 could find the decl by rummaging around in the block->objects
6089 VEC for the given offset but that seems like too much work. */
6090 dalign
= BITS_PER_UNIT
;
6091 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op
)
6092 && SYMBOL_REF_ANCHOR_P (op
)
6093 && SYMBOL_REF_BLOCK (op
) != NULL
)
6095 struct object_block
*block
= SYMBOL_REF_BLOCK (op
);
6097 dalign
= block
->alignment
;
6098 offset
+= SYMBOL_REF_BLOCK_OFFSET (op
);
6100 else if (CONSTANT_POOL_ADDRESS_P (op
))
6102 /* It would be nice to have get_pool_align().. */
6103 enum machine_mode cmode
= get_pool_mode (op
);
6105 dalign
= GET_MODE_ALIGNMENT (cmode
);
6108 else if (DECL_P (decl
))
6110 dalign
= DECL_ALIGN (decl
);
6114 /* Allow BLKmode when the entire object is known to not
6115 cross a 32k boundary. */
6116 if (!DECL_SIZE_UNIT (decl
))
6119 if (!tree_fits_uhwi_p (DECL_SIZE_UNIT (decl
)))
6122 dsize
= tree_to_uhwi (DECL_SIZE_UNIT (decl
));
6126 return dalign
/ BITS_PER_UNIT
>= dsize
;
6131 type
= TREE_TYPE (decl
);
6133 dalign
= TYPE_ALIGN (type
);
6134 if (CONSTANT_CLASS_P (decl
))
6135 dalign
= CONSTANT_ALIGNMENT (decl
, dalign
);
6137 dalign
= DATA_ALIGNMENT (decl
, dalign
);
6141 /* BLKmode, check the entire object. */
6142 if (TREE_CODE (decl
) == STRING_CST
)
6143 dsize
= TREE_STRING_LENGTH (decl
);
6144 else if (TYPE_SIZE_UNIT (type
)
6145 && tree_fits_uhwi_p (TYPE_SIZE_UNIT (type
)))
6146 dsize
= tree_to_uhwi (TYPE_SIZE_UNIT (type
));
6152 return dalign
/ BITS_PER_UNIT
>= dsize
;
6156 /* Find how many bits of the alignment we know for this access. */
6157 mask
= dalign
/ BITS_PER_UNIT
- 1;
6158 lsb
= offset
& -offset
;
6162 return dalign
>= dsize
;
6166 constant_pool_expr_p (rtx op
)
6170 split_const (op
, &base
, &offset
);
6171 return (GET_CODE (base
) == SYMBOL_REF
6172 && CONSTANT_POOL_ADDRESS_P (base
)
6173 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base
), Pmode
));
6176 static const_rtx tocrel_base
, tocrel_offset
;
6178 /* Return true if OP is a toc pointer relative address (the output
6179 of create_TOC_reference). If STRICT, do not match high part or
6180 non-split -mcmodel=large/medium toc pointer relative addresses. */
6183 toc_relative_expr_p (const_rtx op
, bool strict
)
6188 if (TARGET_CMODEL
!= CMODEL_SMALL
)
6190 /* Only match the low part. */
6191 if (GET_CODE (op
) == LO_SUM
6192 && REG_P (XEXP (op
, 0))
6193 && INT_REG_OK_FOR_BASE_P (XEXP (op
, 0), strict
))
6200 tocrel_offset
= const0_rtx
;
6201 if (GET_CODE (op
) == PLUS
&& add_cint_operand (XEXP (op
, 1), GET_MODE (op
)))
6203 tocrel_base
= XEXP (op
, 0);
6204 tocrel_offset
= XEXP (op
, 1);
6207 return (GET_CODE (tocrel_base
) == UNSPEC
6208 && XINT (tocrel_base
, 1) == UNSPEC_TOCREL
);
6211 /* Return true if X is a constant pool address, and also for cmodel=medium
6212 if X is a toc-relative address known to be offsettable within MODE. */
6215 legitimate_constant_pool_address_p (const_rtx x
, enum machine_mode mode
,
6218 return (toc_relative_expr_p (x
, strict
)
6219 && (TARGET_CMODEL
!= CMODEL_MEDIUM
6220 || constant_pool_expr_p (XVECEXP (tocrel_base
, 0, 0))
6222 || offsettable_ok_by_alignment (XVECEXP (tocrel_base
, 0, 0),
6223 INTVAL (tocrel_offset
), mode
)));
6227 legitimate_small_data_p (enum machine_mode mode
, rtx x
)
6229 return (DEFAULT_ABI
== ABI_V4
6230 && !flag_pic
&& !TARGET_TOC
6231 && (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
)
6232 && small_data_operand (x
, mode
));
6235 /* SPE offset addressing is limited to 5-bits worth of double words. */
6236 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
6239 rs6000_legitimate_offset_address_p (enum machine_mode mode
, rtx x
,
6240 bool strict
, bool worst_case
)
6242 unsigned HOST_WIDE_INT offset
;
6245 if (GET_CODE (x
) != PLUS
)
6247 if (!REG_P (XEXP (x
, 0)))
6249 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
6251 if (!reg_offset_addressing_ok_p (mode
))
6252 return virtual_stack_registers_memory_p (x
);
6253 if (legitimate_constant_pool_address_p (x
, mode
, strict
|| lra_in_progress
))
6255 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6258 offset
= INTVAL (XEXP (x
, 1));
6266 /* SPE vector modes. */
6267 return SPE_CONST_OFFSET_OK (offset
);
6272 /* On e500v2, we may have:
6274 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
6276 Which gets addressed with evldd instructions. */
6277 if (TARGET_E500_DOUBLE
)
6278 return SPE_CONST_OFFSET_OK (offset
);
6280 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
6282 if (VECTOR_MEM_VSX_P (mode
))
6287 if (!TARGET_POWERPC64
)
6289 else if (offset
& 3)
6297 if (TARGET_E500_DOUBLE
)
6298 return (SPE_CONST_OFFSET_OK (offset
)
6299 && SPE_CONST_OFFSET_OK (offset
+ 8));
6304 if (!TARGET_POWERPC64
)
6306 else if (offset
& 3)
6315 return offset
< 0x10000 - extra
;
6319 legitimate_indexed_address_p (rtx x
, int strict
)
6323 if (GET_CODE (x
) != PLUS
)
6329 /* Recognize the rtl generated by reload which we know will later be
6330 replaced with proper base and index regs. */
6332 && reload_in_progress
6333 && (REG_P (op0
) || GET_CODE (op0
) == PLUS
)
6337 return (REG_P (op0
) && REG_P (op1
)
6338 && ((INT_REG_OK_FOR_BASE_P (op0
, strict
)
6339 && INT_REG_OK_FOR_INDEX_P (op1
, strict
))
6340 || (INT_REG_OK_FOR_BASE_P (op1
, strict
)
6341 && INT_REG_OK_FOR_INDEX_P (op0
, strict
))));
6345 avoiding_indexed_address_p (enum machine_mode mode
)
6347 /* Avoid indexed addressing for modes that have non-indexed
6348 load/store instruction forms. */
6349 return (TARGET_AVOID_XFORM
&& VECTOR_MEM_NONE_P (mode
));
6353 legitimate_indirect_address_p (rtx x
, int strict
)
6355 return GET_CODE (x
) == REG
&& INT_REG_OK_FOR_BASE_P (x
, strict
);
6359 macho_lo_sum_memory_operand (rtx x
, enum machine_mode mode
)
6361 if (!TARGET_MACHO
|| !flag_pic
6362 || mode
!= SImode
|| GET_CODE (x
) != MEM
)
6366 if (GET_CODE (x
) != LO_SUM
)
6368 if (GET_CODE (XEXP (x
, 0)) != REG
)
6370 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 0))
6374 return CONSTANT_P (x
);
6378 legitimate_lo_sum_address_p (enum machine_mode mode
, rtx x
, int strict
)
6380 if (GET_CODE (x
) != LO_SUM
)
6382 if (GET_CODE (XEXP (x
, 0)) != REG
)
6384 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
6386 /* Restrict addressing for DI because of our SUBREG hackery. */
6387 if (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
6391 if (TARGET_ELF
|| TARGET_MACHO
)
6395 if (DEFAULT_ABI
!= ABI_AIX
&& DEFAULT_ABI
!= ABI_DARWIN
&& flag_pic
)
6397 /* LRA don't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls
6398 push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
6399 recognizes some LO_SUM addresses as valid although this
6400 function says opposite. In most cases, LRA through different
6401 transformations can generate correct code for address reloads.
6402 It can not manage only some LO_SUM cases. So we need to add
6403 code analogous to one in rs6000_legitimize_reload_address for
6404 LOW_SUM here saying that some addresses are still valid. */
6405 large_toc_ok
= (lra_in_progress
&& TARGET_CMODEL
!= CMODEL_SMALL
6406 && small_toc_ref (x
, VOIDmode
));
6407 if (TARGET_TOC
&& ! large_toc_ok
)
6409 if (GET_MODE_NUNITS (mode
) != 1)
6411 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
6412 && !(/* ??? Assume floating point reg based on mode? */
6413 TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
6414 && (mode
== DFmode
|| mode
== DDmode
)))
6417 return CONSTANT_P (x
) || large_toc_ok
;
6424 /* Try machine-dependent ways of modifying an illegitimate address
6425 to be legitimate. If we find one, return the new, valid address.
6426 This is used from only one place: `memory_address' in explow.c.
6428 OLDX is the address as it was before break_out_memory_refs was
6429 called. In some cases it is useful to look at this to decide what
6432 It is always safe for this function to do nothing. It exists to
6433 recognize opportunities to optimize the output.
6435 On RS/6000, first check for the sum of a register with a constant
6436 integer that is out of range. If so, generate code to add the
6437 constant with the low-order 16 bits masked to the register and force
6438 this result into another register (this can be done with `cau').
6439 Then generate an address of REG+(CONST&0xffff), allowing for the
6440 possibility of bit 16 being a one.
6442 Then check for the sum of a register and something not constant, try to
6443 load the other things into a register and return the sum. */
6446 rs6000_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
6447 enum machine_mode mode
)
6451 if (!reg_offset_addressing_ok_p (mode
))
6453 if (virtual_stack_registers_memory_p (x
))
6456 /* In theory we should not be seeing addresses of the form reg+0,
6457 but just in case it is generated, optimize it away. */
6458 if (GET_CODE (x
) == PLUS
&& XEXP (x
, 1) == const0_rtx
)
6459 return force_reg (Pmode
, XEXP (x
, 0));
6461 /* For TImode with load/store quad, restrict addresses to just a single
6462 pointer, so it works with both GPRs and VSX registers. */
6463 /* Make sure both operands are registers. */
6464 else if (GET_CODE (x
) == PLUS
6465 && (mode
!= TImode
|| !TARGET_QUAD_MEMORY
))
6466 return gen_rtx_PLUS (Pmode
,
6467 force_reg (Pmode
, XEXP (x
, 0)),
6468 force_reg (Pmode
, XEXP (x
, 1)));
6470 return force_reg (Pmode
, x
);
6472 if (GET_CODE (x
) == SYMBOL_REF
)
6474 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
6476 return rs6000_legitimize_tls_address (x
, model
);
6486 /* As in legitimate_offset_address_p we do not assume
6487 worst-case. The mode here is just a hint as to the registers
6488 used. A TImode is usually in gprs, but may actually be in
6489 fprs. Leave worst-case scenario for reload to handle via
6490 insn constraints. PTImode is only GPRs. */
6497 if (GET_CODE (x
) == PLUS
6498 && GET_CODE (XEXP (x
, 0)) == REG
6499 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6500 && ((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 1)) + 0x8000)
6502 && !(SPE_VECTOR_MODE (mode
)
6503 || (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)))
6505 HOST_WIDE_INT high_int
, low_int
;
6507 low_int
= ((INTVAL (XEXP (x
, 1)) & 0xffff) ^ 0x8000) - 0x8000;
6508 if (low_int
>= 0x8000 - extra
)
6510 high_int
= INTVAL (XEXP (x
, 1)) - low_int
;
6511 sum
= force_operand (gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
6512 GEN_INT (high_int
)), 0);
6513 return plus_constant (Pmode
, sum
, low_int
);
6515 else if (GET_CODE (x
) == PLUS
6516 && GET_CODE (XEXP (x
, 0)) == REG
6517 && GET_CODE (XEXP (x
, 1)) != CONST_INT
6518 && GET_MODE_NUNITS (mode
) == 1
6519 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
6520 || (/* ??? Assume floating point reg based on mode? */
6521 (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
6522 && (mode
== DFmode
|| mode
== DDmode
)))
6523 && !avoiding_indexed_address_p (mode
))
6525 return gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
6526 force_reg (Pmode
, force_operand (XEXP (x
, 1), 0)));
6528 else if (SPE_VECTOR_MODE (mode
)
6529 || (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
))
6533 /* We accept [reg + reg] and [reg + OFFSET]. */
6535 if (GET_CODE (x
) == PLUS
)
6537 rtx op1
= XEXP (x
, 0);
6538 rtx op2
= XEXP (x
, 1);
6541 op1
= force_reg (Pmode
, op1
);
6543 if (GET_CODE (op2
) != REG
6544 && (GET_CODE (op2
) != CONST_INT
6545 || !SPE_CONST_OFFSET_OK (INTVAL (op2
))
6546 || (GET_MODE_SIZE (mode
) > 8
6547 && !SPE_CONST_OFFSET_OK (INTVAL (op2
) + 8))))
6548 op2
= force_reg (Pmode
, op2
);
6550 /* We can't always do [reg + reg] for these, because [reg +
6551 reg + offset] is not a legitimate addressing mode. */
6552 y
= gen_rtx_PLUS (Pmode
, op1
, op2
);
6554 if ((GET_MODE_SIZE (mode
) > 8 || mode
== DDmode
) && REG_P (op2
))
6555 return force_reg (Pmode
, y
);
6560 return force_reg (Pmode
, x
);
6562 else if ((TARGET_ELF
6564 || !MACHO_DYNAMIC_NO_PIC_P
6570 && GET_CODE (x
) != CONST_INT
6571 && GET_CODE (x
) != CONST_WIDE_INT
6572 && GET_CODE (x
) != CONST_DOUBLE
6574 && GET_MODE_NUNITS (mode
) == 1
6575 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
6576 || (/* ??? Assume floating point reg based on mode? */
6577 (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
6578 && (mode
== DFmode
|| mode
== DDmode
))))
6580 rtx reg
= gen_reg_rtx (Pmode
);
6582 emit_insn (gen_elf_high (reg
, x
));
6584 emit_insn (gen_macho_high (reg
, x
));
6585 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
6588 && GET_CODE (x
) == SYMBOL_REF
6589 && constant_pool_expr_p (x
)
6590 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), Pmode
))
6591 return create_TOC_reference (x
, NULL_RTX
);
6596 /* Debug version of rs6000_legitimize_address. */
6598 rs6000_debug_legitimize_address (rtx x
, rtx oldx
, enum machine_mode mode
)
6604 ret
= rs6000_legitimize_address (x
, oldx
, mode
);
6605 insns
= get_insns ();
6611 "\nrs6000_legitimize_address: mode %s, old code %s, "
6612 "new code %s, modified\n",
6613 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)),
6614 GET_RTX_NAME (GET_CODE (ret
)));
6616 fprintf (stderr
, "Original address:\n");
6619 fprintf (stderr
, "oldx:\n");
6622 fprintf (stderr
, "New address:\n");
6627 fprintf (stderr
, "Insns added:\n");
6628 debug_rtx_list (insns
, 20);
6634 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
6635 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)));
6646 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
6647 We need to emit DTP-relative relocations. */
6649 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
6651 rs6000_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
6656 fputs ("\t.long\t", file
);
6659 fputs (DOUBLE_INT_ASM_OP
, file
);
6664 output_addr_const (file
, x
);
6665 fputs ("@dtprel+0x8000", file
);
6668 /* In the name of slightly smaller debug output, and to cater to
6669 general assembler lossage, recognize various UNSPEC sequences
6670 and turn them back into a direct symbol reference. */
6673 rs6000_delegitimize_address (rtx orig_x
)
6677 orig_x
= delegitimize_mem_from_attrs (orig_x
);
6683 if (TARGET_CMODEL
!= CMODEL_SMALL
6684 && GET_CODE (y
) == LO_SUM
)
6688 if (GET_CODE (y
) == PLUS
6689 && GET_MODE (y
) == Pmode
6690 && CONST_INT_P (XEXP (y
, 1)))
6692 offset
= XEXP (y
, 1);
6696 if (GET_CODE (y
) == UNSPEC
6697 && XINT (y
, 1) == UNSPEC_TOCREL
)
6699 #ifdef ENABLE_CHECKING
6700 if (REG_P (XVECEXP (y
, 0, 1))
6701 && REGNO (XVECEXP (y
, 0, 1)) == TOC_REGISTER
)
6705 else if (GET_CODE (XVECEXP (y
, 0, 1)) == DEBUG_EXPR
)
6707 /* Weirdness alert. df_note_compute can replace r2 with a
6708 debug_expr when this unspec is in a debug_insn.
6709 Seen in gcc.dg/pr51957-1.c */
6717 y
= XVECEXP (y
, 0, 0);
6720 /* Do not associate thread-local symbols with the original
6721 constant pool symbol. */
6723 && GET_CODE (y
) == SYMBOL_REF
6724 && CONSTANT_POOL_ADDRESS_P (y
)
6725 && SYMBOL_REF_TLS_MODEL (get_pool_constant (y
)) >= TLS_MODEL_REAL
)
6729 if (offset
!= NULL_RTX
)
6730 y
= gen_rtx_PLUS (Pmode
, y
, offset
);
6731 if (!MEM_P (orig_x
))
6734 return replace_equiv_address_nv (orig_x
, y
);
6738 && GET_CODE (orig_x
) == LO_SUM
6739 && GET_CODE (XEXP (orig_x
, 1)) == CONST
)
6741 y
= XEXP (XEXP (orig_x
, 1), 0);
6742 if (GET_CODE (y
) == UNSPEC
6743 && XINT (y
, 1) == UNSPEC_MACHOPIC_OFFSET
)
6744 return XVECEXP (y
, 0, 0);
6750 /* Return true if X shouldn't be emitted into the debug info.
6751 The linker doesn't like .toc section references from
6752 .debug_* sections, so reject .toc section symbols. */
6755 rs6000_const_not_ok_for_debug_p (rtx x
)
6757 if (GET_CODE (x
) == SYMBOL_REF
6758 && CONSTANT_POOL_ADDRESS_P (x
))
6760 rtx c
= get_pool_constant (x
);
6761 enum machine_mode cmode
= get_pool_mode (x
);
6762 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c
, cmode
))
6769 /* Construct the SYMBOL_REF for the tls_get_addr function. */
6771 static GTY(()) rtx rs6000_tls_symbol
;
6773 rs6000_tls_get_addr (void)
6775 if (!rs6000_tls_symbol
)
6776 rs6000_tls_symbol
= init_one_libfunc ("__tls_get_addr");
6778 return rs6000_tls_symbol
;
6781 /* Construct the SYMBOL_REF for TLS GOT references. */
6783 static GTY(()) rtx rs6000_got_symbol
;
6785 rs6000_got_sym (void)
6787 if (!rs6000_got_symbol
)
6789 rs6000_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
6790 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_LOCAL
;
6791 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_EXTERNAL
;
6794 return rs6000_got_symbol
;
6797 /* AIX Thread-Local Address support. */
6800 rs6000_legitimize_tls_address_aix (rtx addr
, enum tls_model model
)
6802 rtx sym
, mem
, tocref
, tlsreg
, tmpreg
, dest
, tlsaddr
;
6806 name
= XSTR (addr
, 0);
6807 /* Append TLS CSECT qualifier, unless the symbol already is qualified
6808 or the symbol will be in TLS private data section. */
6809 if (name
[strlen (name
) - 1] != ']'
6810 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr
))
6811 || bss_initializer_p (SYMBOL_REF_DECL (addr
))))
6813 tlsname
= XALLOCAVEC (char, strlen (name
) + 4);
6814 strcpy (tlsname
, name
);
6816 bss_initializer_p (SYMBOL_REF_DECL (addr
)) ? "[UL]" : "[TL]");
6817 tlsaddr
= copy_rtx (addr
);
6818 XSTR (tlsaddr
, 0) = ggc_strdup (tlsname
);
6823 /* Place addr into TOC constant pool. */
6824 sym
= force_const_mem (GET_MODE (tlsaddr
), tlsaddr
);
6826 /* Output the TOC entry and create the MEM referencing the value. */
6827 if (constant_pool_expr_p (XEXP (sym
, 0))
6828 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym
, 0)), Pmode
))
6830 tocref
= create_TOC_reference (XEXP (sym
, 0), NULL_RTX
);
6831 mem
= gen_const_mem (Pmode
, tocref
);
6832 set_mem_alias_set (mem
, get_TOC_alias_set ());
6837 /* Use global-dynamic for local-dynamic. */
6838 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
6839 || model
== TLS_MODEL_LOCAL_DYNAMIC
)
6841 /* Create new TOC reference for @m symbol. */
6842 name
= XSTR (XVECEXP (XEXP (mem
, 0), 0, 0), 0);
6843 tlsname
= XALLOCAVEC (char, strlen (name
) + 1);
6844 strcpy (tlsname
, "*LCM");
6845 strcat (tlsname
, name
+ 3);
6846 rtx modaddr
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (tlsname
));
6847 SYMBOL_REF_FLAGS (modaddr
) |= SYMBOL_FLAG_LOCAL
;
6848 tocref
= create_TOC_reference (modaddr
, NULL_RTX
);
6849 rtx modmem
= gen_const_mem (Pmode
, tocref
);
6850 set_mem_alias_set (modmem
, get_TOC_alias_set ());
6852 rtx modreg
= gen_reg_rtx (Pmode
);
6853 emit_insn (gen_rtx_SET (VOIDmode
, modreg
, modmem
));
6855 tmpreg
= gen_reg_rtx (Pmode
);
6856 emit_insn (gen_rtx_SET (VOIDmode
, tmpreg
, mem
));
6858 dest
= gen_reg_rtx (Pmode
);
6860 emit_insn (gen_tls_get_addrsi (dest
, modreg
, tmpreg
));
6862 emit_insn (gen_tls_get_addrdi (dest
, modreg
, tmpreg
));
6865 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
6866 else if (TARGET_32BIT
)
6868 tlsreg
= gen_reg_rtx (SImode
);
6869 emit_insn (gen_tls_get_tpointer (tlsreg
));
6872 tlsreg
= gen_rtx_REG (DImode
, 13);
6874 /* Load the TOC value into temporary register. */
6875 tmpreg
= gen_reg_rtx (Pmode
);
6876 emit_insn (gen_rtx_SET (VOIDmode
, tmpreg
, mem
));
6877 set_unique_reg_note (get_last_insn (), REG_EQUAL
,
6878 gen_rtx_MINUS (Pmode
, addr
, tlsreg
));
6880 /* Add TOC symbol value to TLS pointer. */
6881 dest
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, tmpreg
, tlsreg
));
6886 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
6887 this (thread-local) address. */
6890 rs6000_legitimize_tls_address (rtx addr
, enum tls_model model
)
6895 return rs6000_legitimize_tls_address_aix (addr
, model
);
6897 dest
= gen_reg_rtx (Pmode
);
6898 if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 16)
6904 tlsreg
= gen_rtx_REG (Pmode
, 13);
6905 insn
= gen_tls_tprel_64 (dest
, tlsreg
, addr
);
6909 tlsreg
= gen_rtx_REG (Pmode
, 2);
6910 insn
= gen_tls_tprel_32 (dest
, tlsreg
, addr
);
6914 else if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 32)
6918 tmp
= gen_reg_rtx (Pmode
);
6921 tlsreg
= gen_rtx_REG (Pmode
, 13);
6922 insn
= gen_tls_tprel_ha_64 (tmp
, tlsreg
, addr
);
6926 tlsreg
= gen_rtx_REG (Pmode
, 2);
6927 insn
= gen_tls_tprel_ha_32 (tmp
, tlsreg
, addr
);
6931 insn
= gen_tls_tprel_lo_64 (dest
, tmp
, addr
);
6933 insn
= gen_tls_tprel_lo_32 (dest
, tmp
, addr
);
6938 rtx r3
, got
, tga
, tmp1
, tmp2
, call_insn
;
6940 /* We currently use relocations like @got@tlsgd for tls, which
6941 means the linker will handle allocation of tls entries, placing
6942 them in the .got section. So use a pointer to the .got section,
6943 not one to secondary TOC sections used by 64-bit -mminimal-toc,
6944 or to secondary GOT sections used by 32-bit -fPIC. */
6946 got
= gen_rtx_REG (Pmode
, 2);
6950 got
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
6953 rtx gsym
= rs6000_got_sym ();
6954 got
= gen_reg_rtx (Pmode
);
6956 rs6000_emit_move (got
, gsym
, Pmode
);
6961 tmp1
= gen_reg_rtx (Pmode
);
6962 tmp2
= gen_reg_rtx (Pmode
);
6963 mem
= gen_const_mem (Pmode
, tmp1
);
6964 lab
= gen_label_rtx ();
6965 emit_insn (gen_load_toc_v4_PIC_1b (gsym
, lab
));
6966 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
6967 if (TARGET_LINK_STACK
)
6968 emit_insn (gen_addsi3 (tmp1
, tmp1
, GEN_INT (4)));
6969 emit_move_insn (tmp2
, mem
);
6970 last
= emit_insn (gen_addsi3 (got
, tmp1
, tmp2
));
6971 set_unique_reg_note (last
, REG_EQUAL
, gsym
);
6976 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
)
6978 tga
= rs6000_tls_get_addr ();
6979 emit_library_call_value (tga
, dest
, LCT_CONST
, Pmode
,
6980 1, const0_rtx
, Pmode
);
6982 r3
= gen_rtx_REG (Pmode
, 3);
6983 if (DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
6984 insn
= gen_tls_gd_aix64 (r3
, got
, addr
, tga
, const0_rtx
);
6985 else if (DEFAULT_ABI
== ABI_AIX
&& !TARGET_64BIT
)
6986 insn
= gen_tls_gd_aix32 (r3
, got
, addr
, tga
, const0_rtx
);
6987 else if (DEFAULT_ABI
== ABI_V4
)
6988 insn
= gen_tls_gd_sysvsi (r3
, got
, addr
, tga
, const0_rtx
);
6991 call_insn
= last_call_insn ();
6992 PATTERN (call_insn
) = insn
;
6993 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
6994 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
6995 pic_offset_table_rtx
);
6997 else if (model
== TLS_MODEL_LOCAL_DYNAMIC
)
6999 tga
= rs6000_tls_get_addr ();
7000 tmp1
= gen_reg_rtx (Pmode
);
7001 emit_library_call_value (tga
, tmp1
, LCT_CONST
, Pmode
,
7002 1, const0_rtx
, Pmode
);
7004 r3
= gen_rtx_REG (Pmode
, 3);
7005 if (DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
7006 insn
= gen_tls_ld_aix64 (r3
, got
, tga
, const0_rtx
);
7007 else if (DEFAULT_ABI
== ABI_AIX
&& !TARGET_64BIT
)
7008 insn
= gen_tls_ld_aix32 (r3
, got
, tga
, const0_rtx
);
7009 else if (DEFAULT_ABI
== ABI_V4
)
7010 insn
= gen_tls_ld_sysvsi (r3
, got
, tga
, const0_rtx
);
7013 call_insn
= last_call_insn ();
7014 PATTERN (call_insn
) = insn
;
7015 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
7016 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
7017 pic_offset_table_rtx
);
7019 if (rs6000_tls_size
== 16)
7022 insn
= gen_tls_dtprel_64 (dest
, tmp1
, addr
);
7024 insn
= gen_tls_dtprel_32 (dest
, tmp1
, addr
);
7026 else if (rs6000_tls_size
== 32)
7028 tmp2
= gen_reg_rtx (Pmode
);
7030 insn
= gen_tls_dtprel_ha_64 (tmp2
, tmp1
, addr
);
7032 insn
= gen_tls_dtprel_ha_32 (tmp2
, tmp1
, addr
);
7035 insn
= gen_tls_dtprel_lo_64 (dest
, tmp2
, addr
);
7037 insn
= gen_tls_dtprel_lo_32 (dest
, tmp2
, addr
);
7041 tmp2
= gen_reg_rtx (Pmode
);
7043 insn
= gen_tls_got_dtprel_64 (tmp2
, got
, addr
);
7045 insn
= gen_tls_got_dtprel_32 (tmp2
, got
, addr
);
7047 insn
= gen_rtx_SET (Pmode
, dest
,
7048 gen_rtx_PLUS (Pmode
, tmp2
, tmp1
));
7054 /* IE, or 64-bit offset LE. */
7055 tmp2
= gen_reg_rtx (Pmode
);
7057 insn
= gen_tls_got_tprel_64 (tmp2
, got
, addr
);
7059 insn
= gen_tls_got_tprel_32 (tmp2
, got
, addr
);
7062 insn
= gen_tls_tls_64 (dest
, tmp2
, addr
);
7064 insn
= gen_tls_tls_32 (dest
, tmp2
, addr
);
7072 /* Return 1 if X contains a thread-local symbol. */
7075 rs6000_tls_referenced_p (rtx x
)
7077 if (! TARGET_HAVE_TLS
)
7080 return for_each_rtx (&x
, &rs6000_tls_symbol_ref_1
, 0);
7083 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
7086 rs6000_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
7088 if (GET_CODE (x
) == HIGH
7089 && GET_CODE (XEXP (x
, 0)) == UNSPEC
)
7092 /* A TLS symbol in the TOC cannot contain a sum. */
7093 if (GET_CODE (x
) == CONST
7094 && GET_CODE (XEXP (x
, 0)) == PLUS
7095 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
7096 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x
, 0), 0)) != 0)
7099 /* Do not place an ELF TLS symbol in the constant pool. */
7100 return TARGET_ELF
&& rs6000_tls_referenced_p (x
);
7103 /* Return 1 if *X is a thread-local symbol. This is the same as
7104 rs6000_tls_symbol_ref except for the type of the unused argument. */
7107 rs6000_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
7109 return RS6000_SYMBOL_REF_TLS_P (*x
);
7112 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
7113 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
7114 can be addressed relative to the toc pointer. */
7117 use_toc_relative_ref (rtx sym
)
7119 return ((constant_pool_expr_p (sym
)
7120 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym
),
7121 get_pool_mode (sym
)))
7122 || (TARGET_CMODEL
== CMODEL_MEDIUM
7123 && SYMBOL_REF_LOCAL_P (sym
)));
7126 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
7127 replace the input X, or the original X if no replacement is called for.
7128 The output parameter *WIN is 1 if the calling macro should goto WIN,
7131 For RS/6000, we wish to handle large displacements off a base
7132 register by splitting the addend across an addiu/addis and the mem insn.
7133 This cuts number of extra insns needed from 3 to 1.
7135 On Darwin, we use this to generate code for floating point constants.
7136 A movsf_low is generated so we wind up with 2 instructions rather than 3.
7137 The Darwin code is inside #if TARGET_MACHO because only then are the
7138 machopic_* functions defined. */
7140 rs6000_legitimize_reload_address (rtx x
, enum machine_mode mode
,
7141 int opnum
, int type
,
7142 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
7144 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
7146 /* Nasty hack for vsx_splat_V2DF/V2DI load from mem, which takes a
7147 DFmode/DImode MEM. */
7150 && ((mode
== DFmode
&& recog_data
.operand_mode
[0] == V2DFmode
)
7151 || (mode
== DImode
&& recog_data
.operand_mode
[0] == V2DImode
)))
7152 reg_offset_p
= false;
7154 /* We must recognize output that we have already generated ourselves. */
7155 if (GET_CODE (x
) == PLUS
7156 && GET_CODE (XEXP (x
, 0)) == PLUS
7157 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
7158 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7159 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7161 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7162 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
7163 opnum
, (enum reload_type
) type
);
7168 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
7169 if (GET_CODE (x
) == LO_SUM
7170 && GET_CODE (XEXP (x
, 0)) == HIGH
)
7172 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7173 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7174 opnum
, (enum reload_type
) type
);
7180 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
7181 && GET_CODE (x
) == LO_SUM
7182 && GET_CODE (XEXP (x
, 0)) == PLUS
7183 && XEXP (XEXP (x
, 0), 0) == pic_offset_table_rtx
7184 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == HIGH
7185 && XEXP (XEXP (XEXP (x
, 0), 1), 0) == XEXP (x
, 1)
7186 && machopic_operand_p (XEXP (x
, 1)))
7188 /* Result of previous invocation of this function on Darwin
7189 floating point constant. */
7190 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7191 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7192 opnum
, (enum reload_type
) type
);
7198 if (TARGET_CMODEL
!= CMODEL_SMALL
7200 && small_toc_ref (x
, VOIDmode
))
7202 rtx hi
= gen_rtx_HIGH (Pmode
, copy_rtx (x
));
7203 x
= gen_rtx_LO_SUM (Pmode
, hi
, x
);
7204 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7205 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7206 opnum
, (enum reload_type
) type
);
7211 if (GET_CODE (x
) == PLUS
7212 && GET_CODE (XEXP (x
, 0)) == REG
7213 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
7214 && INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 1)
7215 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7217 && !SPE_VECTOR_MODE (mode
)
7218 && !(TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
7219 && (!VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
)))
7221 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
7222 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
7224 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7226 /* Check for 32-bit overflow. */
7227 if (high
+ low
!= val
)
7233 /* Reload the high part into a base reg; leave the low part
7234 in the mem directly. */
7236 x
= gen_rtx_PLUS (GET_MODE (x
),
7237 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
7241 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7242 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
7243 opnum
, (enum reload_type
) type
);
7248 if (GET_CODE (x
) == SYMBOL_REF
7250 && (!VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
))
7251 && !SPE_VECTOR_MODE (mode
)
7253 && DEFAULT_ABI
== ABI_DARWIN
7254 && (flag_pic
|| MACHO_DYNAMIC_NO_PIC_P
)
7255 && machopic_symbol_defined_p (x
)
7257 && DEFAULT_ABI
== ABI_V4
7260 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
7261 The same goes for DImode without 64-bit gprs and DFmode and DDmode
7263 ??? Assume floating point reg based on mode? This assumption is
7264 violated by eg. powerpc-linux -m32 compile of gcc.dg/pr28796-2.c
7265 where reload ends up doing a DFmode load of a constant from
7266 mem using two gprs. Unfortunately, at this point reload
7267 hasn't yet selected regs so poking around in reload data
7268 won't help and even if we could figure out the regs reliably,
7269 we'd still want to allow this transformation when the mem is
7270 naturally aligned. Since we say the address is good here, we
7271 can't disable offsets from LO_SUMs in mem_operand_gpr.
7272 FIXME: Allow offset from lo_sum for other modes too, when
7273 mem is sufficiently aligned. */
7276 && (mode
!= TImode
|| !TARGET_VSX_TIMODE
)
7278 && (mode
!= DImode
|| TARGET_POWERPC64
)
7279 && ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_POWERPC64
7280 || (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)))
7285 rtx offset
= machopic_gen_offset (x
);
7286 x
= gen_rtx_LO_SUM (GET_MODE (x
),
7287 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
7288 gen_rtx_HIGH (Pmode
, offset
)), offset
);
7292 x
= gen_rtx_LO_SUM (GET_MODE (x
),
7293 gen_rtx_HIGH (Pmode
, x
), x
);
7295 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7296 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7297 opnum
, (enum reload_type
) type
);
7302 /* Reload an offset address wrapped by an AND that represents the
7303 masking of the lower bits. Strip the outer AND and let reload
7304 convert the offset address into an indirect address. For VSX,
7305 force reload to create the address with an AND in a separate
7306 register, because we can't guarantee an altivec register will
7308 if (VECTOR_MEM_ALTIVEC_P (mode
)
7309 && GET_CODE (x
) == AND
7310 && GET_CODE (XEXP (x
, 0)) == PLUS
7311 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
7312 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7313 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7314 && INTVAL (XEXP (x
, 1)) == -16)
7323 && GET_CODE (x
) == SYMBOL_REF
7324 && use_toc_relative_ref (x
))
7326 x
= create_TOC_reference (x
, NULL_RTX
);
7327 if (TARGET_CMODEL
!= CMODEL_SMALL
)
7328 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7329 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7330 opnum
, (enum reload_type
) type
);
7338 /* Debug version of rs6000_legitimize_reload_address. */
7340 rs6000_debug_legitimize_reload_address (rtx x
, enum machine_mode mode
,
7341 int opnum
, int type
,
7342 int ind_levels
, int *win
)
7344 rtx ret
= rs6000_legitimize_reload_address (x
, mode
, opnum
, type
,
7347 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
7348 "type = %d, ind_levels = %d, win = %d, original addr:\n",
7349 GET_MODE_NAME (mode
), opnum
, type
, ind_levels
, *win
);
7353 fprintf (stderr
, "Same address returned\n");
7355 fprintf (stderr
, "NULL returned\n");
7358 fprintf (stderr
, "New address:\n");
7365 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
7366 that is a valid memory address for an instruction.
7367 The MODE argument is the machine mode for the MEM expression
7368 that wants to use this address.
7370 On the RS/6000, there are four valid address: a SYMBOL_REF that
7371 refers to a constant pool entry of an address (or the sum of it
7372 plus a constant), a short (16-bit signed) constant plus a register,
7373 the sum of two registers, or a register indirect, possibly with an
7374 auto-increment. For DFmode, DDmode and DImode with a constant plus
7375 register, we must ensure that both words are addressable or PowerPC64
7376 with offset word aligned.
7378 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
7379 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
7380 because adjacent memory cells are accessed by adding word-sized offsets
7381 during assembly output. */
7383 rs6000_legitimate_address_p (enum machine_mode mode
, rtx x
, bool reg_ok_strict
)
7385 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
7387 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
7388 if (VECTOR_MEM_ALTIVEC_P (mode
)
7389 && GET_CODE (x
) == AND
7390 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7391 && INTVAL (XEXP (x
, 1)) == -16)
7394 if (TARGET_ELF
&& RS6000_SYMBOL_REF_TLS_P (x
))
7396 if (legitimate_indirect_address_p (x
, reg_ok_strict
))
7399 && (GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
7400 && mode_supports_pre_incdec_p (mode
)
7401 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
))
7403 if (virtual_stack_registers_memory_p (x
))
7405 if (reg_offset_p
&& legitimate_small_data_p (mode
, x
))
7408 && legitimate_constant_pool_address_p (x
, mode
,
7409 reg_ok_strict
|| lra_in_progress
))
7411 /* For TImode, if we have load/store quad and TImode in VSX registers, only
7412 allow register indirect addresses. This will allow the values to go in
7413 either GPRs or VSX registers without reloading. The vector types would
7414 tend to go into VSX registers, so we allow REG+REG, while TImode seems
7415 somewhat split, in that some uses are GPR based, and some VSX based. */
7416 if (mode
== TImode
&& TARGET_QUAD_MEMORY
&& TARGET_VSX_TIMODE
)
7418 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
7421 && GET_CODE (x
) == PLUS
7422 && GET_CODE (XEXP (x
, 0)) == REG
7423 && (XEXP (x
, 0) == virtual_stack_vars_rtx
7424 || XEXP (x
, 0) == arg_pointer_rtx
)
7425 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7427 if (rs6000_legitimate_offset_address_p (mode
, x
, reg_ok_strict
, false))
7431 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
7433 || (mode
!= DFmode
&& mode
!= DDmode
)
7434 || (TARGET_E500_DOUBLE
&& mode
!= DDmode
))
7435 && (TARGET_POWERPC64
|| mode
!= DImode
)
7436 && (mode
!= TImode
|| VECTOR_MEM_VSX_P (TImode
))
7438 && !avoiding_indexed_address_p (mode
)
7439 && legitimate_indexed_address_p (x
, reg_ok_strict
))
7441 if (TARGET_UPDATE
&& GET_CODE (x
) == PRE_MODIFY
7442 && mode_supports_pre_modify_p (mode
)
7443 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
)
7444 && (rs6000_legitimate_offset_address_p (mode
, XEXP (x
, 1),
7445 reg_ok_strict
, false)
7446 || (!avoiding_indexed_address_p (mode
)
7447 && legitimate_indexed_address_p (XEXP (x
, 1), reg_ok_strict
)))
7448 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
7450 if (reg_offset_p
&& legitimate_lo_sum_address_p (mode
, x
, reg_ok_strict
))
7455 /* Debug version of rs6000_legitimate_address_p. */
7457 rs6000_debug_legitimate_address_p (enum machine_mode mode
, rtx x
,
7460 bool ret
= rs6000_legitimate_address_p (mode
, x
, reg_ok_strict
);
7462 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
7463 "strict = %d, reload = %s, code = %s\n",
7464 ret
? "true" : "false",
7465 GET_MODE_NAME (mode
),
7469 : (reload_in_progress
? "progress" : "before")),
7470 GET_RTX_NAME (GET_CODE (x
)));
7476 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
7479 rs6000_mode_dependent_address_p (const_rtx addr
,
7480 addr_space_t as ATTRIBUTE_UNUSED
)
7482 return rs6000_mode_dependent_address_ptr (addr
);
7485 /* Go to LABEL if ADDR (a legitimate address expression)
7486 has an effect that depends on the machine mode it is used for.
7488 On the RS/6000 this is true of all integral offsets (since AltiVec
7489 and VSX modes don't allow them) or is a pre-increment or decrement.
7491 ??? Except that due to conceptual problems in offsettable_address_p
7492 we can't really report the problems of integral offsets. So leave
7493 this assuming that the adjustable offset must be valid for the
7494 sub-words of a TFmode operand, which is what we had before. */
7497 rs6000_mode_dependent_address (const_rtx addr
)
7499 switch (GET_CODE (addr
))
7502 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
7503 is considered a legitimate address before reload, so there
7504 are no offset restrictions in that case. Note that this
7505 condition is safe in strict mode because any address involving
7506 virtual_stack_vars_rtx or arg_pointer_rtx would already have
7507 been rejected as illegitimate. */
7508 if (XEXP (addr
, 0) != virtual_stack_vars_rtx
7509 && XEXP (addr
, 0) != arg_pointer_rtx
7510 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
7512 unsigned HOST_WIDE_INT val
= INTVAL (XEXP (addr
, 1));
7513 return val
+ 0x8000 >= 0x10000 - (TARGET_POWERPC64
? 8 : 12);
7518 /* Anything in the constant pool is sufficiently aligned that
7519 all bytes have the same high part address. */
7520 return !legitimate_constant_pool_address_p (addr
, QImode
, false);
7522 /* Auto-increment cases are now treated generically in recog.c. */
7524 return TARGET_UPDATE
;
7526 /* AND is only allowed in Altivec loads. */
7537 /* Debug version of rs6000_mode_dependent_address. */
7539 rs6000_debug_mode_dependent_address (const_rtx addr
)
7541 bool ret
= rs6000_mode_dependent_address (addr
);
7543 fprintf (stderr
, "\nrs6000_mode_dependent_address: ret = %s\n",
7544 ret
? "true" : "false");
7550 /* Implement FIND_BASE_TERM. */
7553 rs6000_find_base_term (rtx op
)
7558 if (GET_CODE (base
) == CONST
)
7559 base
= XEXP (base
, 0);
7560 if (GET_CODE (base
) == PLUS
)
7561 base
= XEXP (base
, 0);
7562 if (GET_CODE (base
) == UNSPEC
)
7563 switch (XINT (base
, 1))
7566 case UNSPEC_MACHOPIC_OFFSET
:
7567 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
7568 for aliasing purposes. */
7569 return XVECEXP (base
, 0, 0);
7575 /* More elaborate version of recog's offsettable_memref_p predicate
7576 that works around the ??? note of rs6000_mode_dependent_address.
7577 In particular it accepts
7579 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
7581 in 32-bit mode, that the recog predicate rejects. */
7584 rs6000_offsettable_memref_p (rtx op
, enum machine_mode reg_mode
)
7591 /* First mimic offsettable_memref_p. */
7592 if (offsettable_address_p (true, GET_MODE (op
), XEXP (op
, 0)))
7595 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
7596 the latter predicate knows nothing about the mode of the memory
7597 reference and, therefore, assumes that it is the largest supported
7598 mode (TFmode). As a consequence, legitimate offsettable memory
7599 references are rejected. rs6000_legitimate_offset_address_p contains
7600 the correct logic for the PLUS case of rs6000_mode_dependent_address,
7601 at least with a little bit of help here given that we know the
7602 actual registers used. */
7603 worst_case
= ((TARGET_POWERPC64
&& GET_MODE_CLASS (reg_mode
) == MODE_INT
)
7604 || GET_MODE_SIZE (reg_mode
) == 4);
7605 return rs6000_legitimate_offset_address_p (GET_MODE (op
), XEXP (op
, 0),
7609 /* Change register usage conditional on target flags. */
7611 rs6000_conditional_register_usage (void)
7615 if (TARGET_DEBUG_TARGET
)
7616 fprintf (stderr
, "rs6000_conditional_register_usage called\n");
7618 /* Set MQ register fixed (already call_used) so that it will not be
7622 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
7624 fixed_regs
[13] = call_used_regs
[13]
7625 = call_really_used_regs
[13] = 1;
7627 /* Conditionally disable FPRs. */
7628 if (TARGET_SOFT_FLOAT
|| !TARGET_FPRS
)
7629 for (i
= 32; i
< 64; i
++)
7630 fixed_regs
[i
] = call_used_regs
[i
]
7631 = call_really_used_regs
[i
] = 1;
7633 /* The TOC register is not killed across calls in a way that is
7634 visible to the compiler. */
7635 if (DEFAULT_ABI
== ABI_AIX
)
7636 call_really_used_regs
[2] = 0;
7638 if (DEFAULT_ABI
== ABI_V4
7639 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
7641 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7643 if (DEFAULT_ABI
== ABI_V4
7644 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
7646 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7647 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7648 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7650 if (DEFAULT_ABI
== ABI_DARWIN
7651 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
7652 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7653 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7654 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7656 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
)
7657 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7658 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7662 global_regs
[SPEFSCR_REGNO
] = 1;
7663 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
7664 registers in prologues and epilogues. We no longer use r14
7665 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
7666 pool for link-compatibility with older versions of GCC. Once
7667 "old" code has died out, we can return r14 to the allocation
7670 = call_used_regs
[14]
7671 = call_really_used_regs
[14] = 1;
7674 if (!TARGET_ALTIVEC
&& !TARGET_VSX
)
7676 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
7677 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
7678 call_really_used_regs
[VRSAVE_REGNO
] = 1;
7681 if (TARGET_ALTIVEC
|| TARGET_VSX
)
7682 global_regs
[VSCR_REGNO
] = 1;
7684 if (TARGET_ALTIVEC_ABI
)
7686 for (i
= FIRST_ALTIVEC_REGNO
; i
< FIRST_ALTIVEC_REGNO
+ 20; ++i
)
7687 call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
7689 /* AIX reserves VR20:31 in non-extended ABI mode. */
7691 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
< FIRST_ALTIVEC_REGNO
+ 32; ++i
)
7692 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
7697 /* Try to output insns to set TARGET equal to the constant C if it can
7698 be done in less than N insns. Do all computations in MODE.
7699 Returns the place where the output has been placed if it can be
7700 done and the insns have been emitted. If it would take more than N
7701 insns, zero is returned and no insns and emitted. */
7704 rs6000_emit_set_const (rtx dest
, enum machine_mode mode
,
7705 rtx source
, int n ATTRIBUTE_UNUSED
)
7707 rtx result
, insn
, set
;
7708 HOST_WIDE_INT c0
, c1
;
7715 dest
= gen_reg_rtx (mode
);
7716 emit_insn (gen_rtx_SET (VOIDmode
, dest
, source
));
7720 result
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (SImode
);
7722 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (result
),
7723 GEN_INT (INTVAL (source
)
7724 & (~ (HOST_WIDE_INT
) 0xffff))));
7725 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
7726 gen_rtx_IOR (SImode
, copy_rtx (result
),
7727 GEN_INT (INTVAL (source
) & 0xffff))));
7732 switch (GET_CODE (source
))
7735 c0
= INTVAL (source
);
7743 result
= rs6000_emit_set_long_const (dest
, c0
, c1
);
7750 insn
= get_last_insn ();
7751 set
= single_set (insn
);
7752 if (! CONSTANT_P (SET_SRC (set
)))
7753 set_unique_reg_note (insn
, REG_EQUAL
, source
);
7758 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
7759 fall back to a straight forward decomposition. We do this to avoid
7760 exponential run times encountered when looking for longer sequences
7761 with rs6000_emit_set_const. */
7763 rs6000_emit_set_long_const (rtx dest
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
7765 if (!TARGET_POWERPC64
)
7767 rtx operand1
, operand2
;
7769 operand1
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
== 0,
7771 operand2
= operand_subword_force (copy_rtx (dest
), WORDS_BIG_ENDIAN
!= 0,
7773 emit_move_insn (operand1
, GEN_INT (c1
));
7774 emit_move_insn (operand2
, GEN_INT (c2
));
7778 HOST_WIDE_INT ud1
, ud2
, ud3
, ud4
;
7781 ud2
= (c1
& 0xffff0000) >> 16;
7784 ud4
= (c2
& 0xffff0000) >> 16;
7786 if ((ud4
== 0xffff && ud3
== 0xffff && ud2
== 0xffff && (ud1
& 0x8000))
7787 || (ud4
== 0 && ud3
== 0 && ud2
== 0 && ! (ud1
& 0x8000)))
7788 emit_move_insn (dest
, GEN_INT ((ud1
^ 0x8000) - 0x8000));
7790 else if ((ud4
== 0xffff && ud3
== 0xffff && (ud2
& 0x8000))
7791 || (ud4
== 0 && ud3
== 0 && ! (ud2
& 0x8000)))
7793 emit_move_insn (dest
, GEN_INT (((ud2
<< 16) ^ 0x80000000)
7796 emit_move_insn (copy_rtx (dest
),
7797 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7800 else if (ud3
== 0 && ud4
== 0)
7802 gcc_assert (ud2
& 0x8000);
7803 emit_move_insn (dest
, GEN_INT (((ud2
<< 16) ^ 0x80000000)
7806 emit_move_insn (copy_rtx (dest
),
7807 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7809 emit_move_insn (copy_rtx (dest
),
7810 gen_rtx_ZERO_EXTEND (DImode
,
7811 gen_lowpart (SImode
,
7814 else if ((ud4
== 0xffff && (ud3
& 0x8000))
7815 || (ud4
== 0 && ! (ud3
& 0x8000)))
7817 emit_move_insn (dest
, GEN_INT (((ud3
<< 16) ^ 0x80000000)
7820 emit_move_insn (copy_rtx (dest
),
7821 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7823 emit_move_insn (copy_rtx (dest
),
7824 gen_rtx_ASHIFT (DImode
, copy_rtx (dest
),
7827 emit_move_insn (copy_rtx (dest
),
7828 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7833 emit_move_insn (dest
, GEN_INT (((ud4
<< 16) ^ 0x80000000)
7836 emit_move_insn (copy_rtx (dest
),
7837 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7840 emit_move_insn (copy_rtx (dest
),
7841 gen_rtx_ASHIFT (DImode
, copy_rtx (dest
),
7844 emit_move_insn (copy_rtx (dest
),
7845 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7846 GEN_INT (ud2
<< 16)));
7848 emit_move_insn (copy_rtx (dest
),
7849 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7856 /* Helper for the following. Get rid of [r+r] memory refs
7857 in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
7860 rs6000_eliminate_indexed_memrefs (rtx operands
[2])
7862 if (reload_in_progress
)
7865 if (GET_CODE (operands
[0]) == MEM
7866 && GET_CODE (XEXP (operands
[0], 0)) != REG
7867 && ! legitimate_constant_pool_address_p (XEXP (operands
[0], 0),
7868 GET_MODE (operands
[0]), false))
7870 = replace_equiv_address (operands
[0],
7871 copy_addr_to_reg (XEXP (operands
[0], 0)));
7873 if (GET_CODE (operands
[1]) == MEM
7874 && GET_CODE (XEXP (operands
[1], 0)) != REG
7875 && ! legitimate_constant_pool_address_p (XEXP (operands
[1], 0),
7876 GET_MODE (operands
[1]), false))
7878 = replace_equiv_address (operands
[1],
7879 copy_addr_to_reg (XEXP (operands
[1], 0)));
7882 /* Generate a vector of constants to permute MODE for a little-endian
7883 storage operation by swapping the two halves of a vector. */
7885 rs6000_const_vec (enum machine_mode mode
)
7910 v
= rtvec_alloc (subparts
);
7912 for (i
= 0; i
< subparts
/ 2; ++i
)
7913 RTVEC_ELT (v
, i
) = gen_rtx_CONST_INT (DImode
, i
+ subparts
/ 2);
7914 for (i
= subparts
/ 2; i
< subparts
; ++i
)
7915 RTVEC_ELT (v
, i
) = gen_rtx_CONST_INT (DImode
, i
- subparts
/ 2);
7920 /* Generate a permute rtx that represents an lxvd2x, stxvd2x, or xxpermdi
7921 for a VSX load or store operation. */
7923 rs6000_gen_le_vsx_permute (rtx source
, enum machine_mode mode
)
7925 rtx par
= gen_rtx_PARALLEL (VOIDmode
, rs6000_const_vec (mode
));
7926 return gen_rtx_VEC_SELECT (mode
, source
, par
);
7929 /* Emit a little-endian load from vector memory location SOURCE to VSX
7930 register DEST in mode MODE. The load is done with two permuting
7931 insn's that represent an lxvd2x and xxpermdi. */
7933 rs6000_emit_le_vsx_load (rtx dest
, rtx source
, enum machine_mode mode
)
7935 rtx tmp
= can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest
) : dest
;
7936 rtx permute_mem
= rs6000_gen_le_vsx_permute (source
, mode
);
7937 rtx permute_reg
= rs6000_gen_le_vsx_permute (tmp
, mode
);
7938 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, permute_mem
));
7939 emit_insn (gen_rtx_SET (VOIDmode
, dest
, permute_reg
));
7942 /* Emit a little-endian store to vector memory location DEST from VSX
7943 register SOURCE in mode MODE. The store is done with two permuting
7944 insn's that represent an xxpermdi and an stxvd2x. */
7946 rs6000_emit_le_vsx_store (rtx dest
, rtx source
, enum machine_mode mode
)
7948 rtx tmp
= can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source
) : source
;
7949 rtx permute_src
= rs6000_gen_le_vsx_permute (source
, mode
);
7950 rtx permute_tmp
= rs6000_gen_le_vsx_permute (tmp
, mode
);
7951 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, permute_src
));
7952 emit_insn (gen_rtx_SET (VOIDmode
, dest
, permute_tmp
));
7955 /* Emit a sequence representing a little-endian VSX load or store,
7956 moving data from SOURCE to DEST in mode MODE. This is done
7957 separately from rs6000_emit_move to ensure it is called only
7958 during expand. LE VSX loads and stores introduced later are
7959 handled with a split. The expand-time RTL generation allows
7960 us to optimize away redundant pairs of register-permutes. */
7962 rs6000_emit_le_vsx_move (rtx dest
, rtx source
, enum machine_mode mode
)
7964 gcc_assert (!BYTES_BIG_ENDIAN
7965 && VECTOR_MEM_VSX_P (mode
)
7967 && (MEM_P (source
) ^ MEM_P (dest
)));
7971 gcc_assert (REG_P (dest
));
7972 rs6000_emit_le_vsx_load (dest
, source
, mode
);
7976 if (!REG_P (source
))
7977 source
= force_reg (mode
, source
);
7978 rs6000_emit_le_vsx_store (dest
, source
, mode
);
7982 /* Emit a move from SOURCE to DEST in mode MODE. */
7984 rs6000_emit_move (rtx dest
, rtx source
, enum machine_mode mode
)
7988 operands
[1] = source
;
7990 if (TARGET_DEBUG_ADDR
)
7993 "\nrs6000_emit_move: mode = %s, reload_in_progress = %d, "
7994 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
7995 GET_MODE_NAME (mode
),
7998 can_create_pseudo_p ());
8000 fprintf (stderr
, "source:\n");
8004 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
8005 if (CONST_WIDE_INT_P (operands
[1])
8006 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
8008 /* This should be fixed with the introduction of CONST_WIDE_INT. */
8012 /* Check if GCC is setting up a block move that will end up using FP
8013 registers as temporaries. We must make sure this is acceptable. */
8014 if (GET_CODE (operands
[0]) == MEM
8015 && GET_CODE (operands
[1]) == MEM
8017 && (SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[0]))
8018 || SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[1])))
8019 && ! (SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[0]) > 32
8020 ? 32 : MEM_ALIGN (operands
[0])))
8021 || SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[1]) > 32
8023 : MEM_ALIGN (operands
[1]))))
8024 && ! MEM_VOLATILE_P (operands
[0])
8025 && ! MEM_VOLATILE_P (operands
[1]))
8027 emit_move_insn (adjust_address (operands
[0], SImode
, 0),
8028 adjust_address (operands
[1], SImode
, 0));
8029 emit_move_insn (adjust_address (copy_rtx (operands
[0]), SImode
, 4),
8030 adjust_address (copy_rtx (operands
[1]), SImode
, 4));
8034 if (can_create_pseudo_p () && GET_CODE (operands
[0]) == MEM
8035 && !gpc_reg_operand (operands
[1], mode
))
8036 operands
[1] = force_reg (mode
, operands
[1]);
8038 /* Recognize the case where operand[1] is a reference to thread-local
8039 data and load its address to a register. */
8040 if (rs6000_tls_referenced_p (operands
[1]))
8042 enum tls_model model
;
8043 rtx tmp
= operands
[1];
8046 if (GET_CODE (tmp
) == CONST
&& GET_CODE (XEXP (tmp
, 0)) == PLUS
)
8048 addend
= XEXP (XEXP (tmp
, 0), 1);
8049 tmp
= XEXP (XEXP (tmp
, 0), 0);
8052 gcc_assert (GET_CODE (tmp
) == SYMBOL_REF
);
8053 model
= SYMBOL_REF_TLS_MODEL (tmp
);
8054 gcc_assert (model
!= 0);
8056 tmp
= rs6000_legitimize_tls_address (tmp
, model
);
8059 tmp
= gen_rtx_PLUS (mode
, tmp
, addend
);
8060 tmp
= force_operand (tmp
, operands
[0]);
8065 /* Handle the case where reload calls us with an invalid address. */
8066 if (reload_in_progress
&& mode
== Pmode
8067 && (! general_operand (operands
[1], mode
)
8068 || ! nonimmediate_operand (operands
[0], mode
)))
8071 /* 128-bit constant floating-point values on Darwin should really be
8072 loaded as two parts. */
8073 if (!TARGET_IEEEQUAD
&& TARGET_LONG_DOUBLE_128
8074 && mode
== TFmode
&& GET_CODE (operands
[1]) == CONST_DOUBLE
)
8076 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
, 0),
8077 simplify_gen_subreg (DFmode
, operands
[1], mode
, 0),
8079 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
,
8080 GET_MODE_SIZE (DFmode
)),
8081 simplify_gen_subreg (DFmode
, operands
[1], mode
,
8082 GET_MODE_SIZE (DFmode
)),
8087 if (reload_in_progress
&& cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
8088 cfun
->machine
->sdmode_stack_slot
=
8089 eliminate_regs (cfun
->machine
->sdmode_stack_slot
, VOIDmode
, NULL_RTX
);
8094 && REG_P (operands
[0]) && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
8095 && reg_preferred_class (REGNO (operands
[0])) == NO_REGS
8096 && (REG_P (operands
[1])
8097 || (GET_CODE (operands
[1]) == SUBREG
8098 && REG_P (SUBREG_REG (operands
[1])))))
8100 int regno
= REGNO (GET_CODE (operands
[1]) == SUBREG
8101 ? SUBREG_REG (operands
[1]) : operands
[1]);
8104 if (regno
>= FIRST_PSEUDO_REGISTER
)
8106 cl
= reg_preferred_class (regno
);
8107 gcc_assert (cl
!= NO_REGS
);
8108 regno
= ira_class_hard_regs
[cl
][0];
8110 if (FP_REGNO_P (regno
))
8112 if (GET_MODE (operands
[0]) != DDmode
)
8113 operands
[0] = gen_rtx_SUBREG (DDmode
, operands
[0], 0);
8114 emit_insn (gen_movsd_store (operands
[0], operands
[1]));
8116 else if (INT_REGNO_P (regno
))
8117 emit_insn (gen_movsd_hardfloat (operands
[0], operands
[1]));
8124 && (REG_P (operands
[0])
8125 || (GET_CODE (operands
[0]) == SUBREG
8126 && REG_P (SUBREG_REG (operands
[0]))))
8127 && REG_P (operands
[1]) && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
8128 && reg_preferred_class (REGNO (operands
[1])) == NO_REGS
)
8130 int regno
= REGNO (GET_CODE (operands
[0]) == SUBREG
8131 ? SUBREG_REG (operands
[0]) : operands
[0]);
8134 if (regno
>= FIRST_PSEUDO_REGISTER
)
8136 cl
= reg_preferred_class (regno
);
8137 gcc_assert (cl
!= NO_REGS
);
8138 regno
= ira_class_hard_regs
[cl
][0];
8140 if (FP_REGNO_P (regno
))
8142 if (GET_MODE (operands
[1]) != DDmode
)
8143 operands
[1] = gen_rtx_SUBREG (DDmode
, operands
[1], 0);
8144 emit_insn (gen_movsd_load (operands
[0], operands
[1]));
8146 else if (INT_REGNO_P (regno
))
8147 emit_insn (gen_movsd_hardfloat (operands
[0], operands
[1]));
8153 if (reload_in_progress
8155 && cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
8156 && MEM_P (operands
[0])
8157 && rtx_equal_p (operands
[0], cfun
->machine
->sdmode_stack_slot
)
8158 && REG_P (operands
[1]))
8160 if (FP_REGNO_P (REGNO (operands
[1])))
8162 rtx mem
= adjust_address_nv (operands
[0], DDmode
, 0);
8163 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8164 emit_insn (gen_movsd_store (mem
, operands
[1]));
8166 else if (INT_REGNO_P (REGNO (operands
[1])))
8168 rtx mem
= adjust_address_nv (operands
[0], mode
, 4);
8169 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8170 emit_insn (gen_movsd_hardfloat (mem
, operands
[1]));
8176 if (reload_in_progress
8178 && REG_P (operands
[0])
8179 && MEM_P (operands
[1])
8180 && cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
8181 && rtx_equal_p (operands
[1], cfun
->machine
->sdmode_stack_slot
))
8183 if (FP_REGNO_P (REGNO (operands
[0])))
8185 rtx mem
= adjust_address_nv (operands
[1], DDmode
, 0);
8186 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8187 emit_insn (gen_movsd_load (operands
[0], mem
));
8189 else if (INT_REGNO_P (REGNO (operands
[0])))
8191 rtx mem
= adjust_address_nv (operands
[1], mode
, 4);
8192 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8193 emit_insn (gen_movsd_hardfloat (operands
[0], mem
));
8200 /* FIXME: In the long term, this switch statement should go away
8201 and be replaced by a sequence of tests based on things like
8207 if (CONSTANT_P (operands
[1])
8208 && GET_CODE (operands
[1]) != CONST_INT
)
8209 operands
[1] = force_const_mem (mode
, operands
[1]);
8214 rs6000_eliminate_indexed_memrefs (operands
);
8221 if (CONSTANT_P (operands
[1])
8222 && ! easy_fp_constant (operands
[1], mode
))
8223 operands
[1] = force_const_mem (mode
, operands
[1]);
8236 if (CONSTANT_P (operands
[1])
8237 && !easy_vector_constant (operands
[1], mode
))
8238 operands
[1] = force_const_mem (mode
, operands
[1]);
8243 /* Use default pattern for address of ELF small data */
8246 && DEFAULT_ABI
== ABI_V4
8247 && (GET_CODE (operands
[1]) == SYMBOL_REF
8248 || GET_CODE (operands
[1]) == CONST
)
8249 && small_data_operand (operands
[1], mode
))
8251 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
8255 if (DEFAULT_ABI
== ABI_V4
8256 && mode
== Pmode
&& mode
== SImode
8257 && flag_pic
== 1 && got_operand (operands
[1], mode
))
8259 emit_insn (gen_movsi_got (operands
[0], operands
[1]));
8263 if ((TARGET_ELF
|| DEFAULT_ABI
== ABI_DARWIN
)
8267 && CONSTANT_P (operands
[1])
8268 && GET_CODE (operands
[1]) != HIGH
8269 && GET_CODE (operands
[1]) != CONST_INT
)
8271 rtx target
= (!can_create_pseudo_p ()
8273 : gen_reg_rtx (mode
));
8275 /* If this is a function address on -mcall-aixdesc,
8276 convert it to the address of the descriptor. */
8277 if (DEFAULT_ABI
== ABI_AIX
8278 && GET_CODE (operands
[1]) == SYMBOL_REF
8279 && XSTR (operands
[1], 0)[0] == '.')
8281 const char *name
= XSTR (operands
[1], 0);
8283 while (*name
== '.')
8285 new_ref
= gen_rtx_SYMBOL_REF (Pmode
, name
);
8286 CONSTANT_POOL_ADDRESS_P (new_ref
)
8287 = CONSTANT_POOL_ADDRESS_P (operands
[1]);
8288 SYMBOL_REF_FLAGS (new_ref
) = SYMBOL_REF_FLAGS (operands
[1]);
8289 SYMBOL_REF_USED (new_ref
) = SYMBOL_REF_USED (operands
[1]);
8290 SYMBOL_REF_DATA (new_ref
) = SYMBOL_REF_DATA (operands
[1]);
8291 operands
[1] = new_ref
;
8294 if (DEFAULT_ABI
== ABI_DARWIN
)
8297 if (MACHO_DYNAMIC_NO_PIC_P
)
8299 /* Take care of any required data indirection. */
8300 operands
[1] = rs6000_machopic_legitimize_pic_address (
8301 operands
[1], mode
, operands
[0]);
8302 if (operands
[0] != operands
[1])
8303 emit_insn (gen_rtx_SET (VOIDmode
,
8304 operands
[0], operands
[1]));
8308 emit_insn (gen_macho_high (target
, operands
[1]));
8309 emit_insn (gen_macho_low (operands
[0], target
, operands
[1]));
8313 emit_insn (gen_elf_high (target
, operands
[1]));
8314 emit_insn (gen_elf_low (operands
[0], target
, operands
[1]));
8318 /* If this is a SYMBOL_REF that refers to a constant pool entry,
8319 and we have put it in the TOC, we just need to make a TOC-relative
8322 && GET_CODE (operands
[1]) == SYMBOL_REF
8323 && use_toc_relative_ref (operands
[1]))
8324 operands
[1] = create_TOC_reference (operands
[1], operands
[0]);
8325 else if (mode
== Pmode
8326 && CONSTANT_P (operands
[1])
8327 && GET_CODE (operands
[1]) != HIGH
8328 && ((GET_CODE (operands
[1]) != CONST_INT
8329 && ! easy_fp_constant (operands
[1], mode
))
8330 || (GET_CODE (operands
[1]) == CONST_INT
8331 && (num_insns_constant (operands
[1], mode
)
8332 > (TARGET_CMODEL
!= CMODEL_SMALL
? 3 : 2)))
8333 || (GET_CODE (operands
[0]) == REG
8334 && FP_REGNO_P (REGNO (operands
[0]))))
8335 && !toc_relative_expr_p (operands
[1], false)
8336 && (TARGET_CMODEL
== CMODEL_SMALL
8337 || can_create_pseudo_p ()
8338 || (REG_P (operands
[0])
8339 && INT_REG_OK_FOR_BASE_P (operands
[0], true))))
8343 /* Darwin uses a special PIC legitimizer. */
8344 if (DEFAULT_ABI
== ABI_DARWIN
&& MACHOPIC_INDIRECT
)
8347 rs6000_machopic_legitimize_pic_address (operands
[1], mode
,
8349 if (operands
[0] != operands
[1])
8350 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
8355 /* If we are to limit the number of things we put in the TOC and
8356 this is a symbol plus a constant we can add in one insn,
8357 just put the symbol in the TOC and add the constant. Don't do
8358 this if reload is in progress. */
8359 if (GET_CODE (operands
[1]) == CONST
8360 && TARGET_NO_SUM_IN_TOC
&& ! reload_in_progress
8361 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
8362 && add_operand (XEXP (XEXP (operands
[1], 0), 1), mode
)
8363 && (GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
8364 || GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == SYMBOL_REF
)
8365 && ! side_effects_p (operands
[0]))
8368 force_const_mem (mode
, XEXP (XEXP (operands
[1], 0), 0));
8369 rtx other
= XEXP (XEXP (operands
[1], 0), 1);
8371 sym
= force_reg (mode
, sym
);
8372 emit_insn (gen_add3_insn (operands
[0], sym
, other
));
8376 operands
[1] = force_const_mem (mode
, operands
[1]);
8379 && GET_CODE (XEXP (operands
[1], 0)) == SYMBOL_REF
8380 && constant_pool_expr_p (XEXP (operands
[1], 0))
8381 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
8382 get_pool_constant (XEXP (operands
[1], 0)),
8383 get_pool_mode (XEXP (operands
[1], 0))))
8385 rtx tocref
= create_TOC_reference (XEXP (operands
[1], 0),
8387 operands
[1] = gen_const_mem (mode
, tocref
);
8388 set_mem_alias_set (operands
[1], get_TOC_alias_set ());
8394 if (!VECTOR_MEM_VSX_P (TImode
))
8395 rs6000_eliminate_indexed_memrefs (operands
);
8399 rs6000_eliminate_indexed_memrefs (operands
);
8403 fatal_insn ("bad move", gen_rtx_SET (VOIDmode
, dest
, source
));
8406 /* Above, we may have called force_const_mem which may have returned
8407 an invalid address. If we can, fix this up; otherwise, reload will
8408 have to deal with it. */
8409 if (GET_CODE (operands
[1]) == MEM
&& ! reload_in_progress
)
8410 operands
[1] = validize_mem (operands
[1]);
8413 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
8416 /* Return true if a structure, union or array containing FIELD should be
8417 accessed using `BLKMODE'.
8419 For the SPE, simd types are V2SI, and gcc can be tempted to put the
8420 entire thing in a DI and use subregs to access the internals.
8421 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
8422 back-end. Because a single GPR can hold a V2SI, but not a DI, the
8423 best thing to do is set structs to BLKmode and avoid Severe Tire
8426 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
8427 fit into 1, whereas DI still needs two. */
8430 rs6000_member_type_forces_blk (const_tree field
, enum machine_mode mode
)
8432 return ((TARGET_SPE
&& TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
8433 || (TARGET_E500_DOUBLE
&& mode
== DFmode
));
8436 /* Nonzero if we can use a floating-point register to pass this arg. */
8437 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
8438 (SCALAR_FLOAT_MODE_P (MODE) \
8439 && (CUM)->fregno <= FP_ARG_MAX_REG \
8440 && TARGET_HARD_FLOAT && TARGET_FPRS)
8442 /* Nonzero if we can use an AltiVec register to pass this arg. */
8443 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
8444 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
8445 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
8446 && TARGET_ALTIVEC_ABI \
8449 /* Return a nonzero value to say to return the function value in
8450 memory, just as large structures are always returned. TYPE will be
8451 the data type of the value, and FNTYPE will be the type of the
8452 function doing the returning, or @code{NULL} for libcalls.
8454 The AIX ABI for the RS/6000 specifies that all structures are
8455 returned in memory. The Darwin ABI does the same.
8457 For the Darwin 64 Bit ABI, a function result can be returned in
8458 registers or in memory, depending on the size of the return data
8459 type. If it is returned in registers, the value occupies the same
8460 registers as it would if it were the first and only function
8461 argument. Otherwise, the function places its result in memory at
8462 the location pointed to by GPR3.
8464 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
8465 but a draft put them in memory, and GCC used to implement the draft
8466 instead of the final standard. Therefore, aix_struct_return
8467 controls this instead of DEFAULT_ABI; V.4 targets needing backward
8468 compatibility can change DRAFT_V4_STRUCT_RET to override the
8469 default, and -m switches get the final word. See
8470 rs6000_option_override_internal for more details.
8472 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
8473 long double support is enabled. These values are returned in memory.
8475 int_size_in_bytes returns -1 for variable size objects, which go in
8476 memory always. The cast to unsigned makes -1 > 8. */
8479 rs6000_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
8481 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
8483 && rs6000_darwin64_abi
8484 && TREE_CODE (type
) == RECORD_TYPE
8485 && int_size_in_bytes (type
) > 0)
8487 CUMULATIVE_ARGS valcum
;
8491 valcum
.fregno
= FP_ARG_MIN_REG
;
8492 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
8493 /* Do a trial code generation as if this were going to be passed
8494 as an argument; if any part goes in memory, we return NULL. */
8495 valret
= rs6000_darwin64_record_arg (&valcum
, type
, true, true);
8498 /* Otherwise fall through to more conventional ABI rules. */
8501 if (AGGREGATE_TYPE_P (type
)
8502 && (aix_struct_return
8503 || (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8))
8506 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
8507 modes only exist for GCC vector types if -maltivec. */
8508 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
8509 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
8512 /* Return synthetic vectors in memory. */
8513 if (TREE_CODE (type
) == VECTOR_TYPE
8514 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
8516 static bool warned_for_return_big_vectors
= false;
8517 if (!warned_for_return_big_vectors
)
8519 warning (0, "GCC vector returned by reference: "
8520 "non-standard ABI extension with no compatibility guarantee");
8521 warned_for_return_big_vectors
= true;
8526 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& TYPE_MODE (type
) == TFmode
)
8532 #ifdef HAVE_AS_GNU_ATTRIBUTE
8533 /* Return TRUE if a call to function FNDECL may be one that
8534 potentially affects the function calling ABI of the object file. */
8537 call_ABI_of_interest (tree fndecl
)
8539 if (cgraph_state
== CGRAPH_STATE_EXPANSION
)
8541 struct cgraph_node
*c_node
;
8543 /* Libcalls are always interesting. */
8544 if (fndecl
== NULL_TREE
)
8547 /* Any call to an external function is interesting. */
8548 if (DECL_EXTERNAL (fndecl
))
8551 /* Interesting functions that we are emitting in this object file. */
8552 c_node
= cgraph_get_node (fndecl
);
8553 c_node
= cgraph_function_or_thunk_node (c_node
, NULL
);
8554 return !cgraph_only_called_directly_p (c_node
);
8560 /* Initialize a variable CUM of type CUMULATIVE_ARGS
8561 for a call to a function whose data type is FNTYPE.
8562 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
8564 For incoming args we set the number of arguments in the prototype large
8565 so we never return a PARALLEL. */
8568 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
8569 rtx libname ATTRIBUTE_UNUSED
, int incoming
,
8570 int libcall
, int n_named_args
,
8571 tree fndecl ATTRIBUTE_UNUSED
,
8572 enum machine_mode return_mode ATTRIBUTE_UNUSED
)
8574 static CUMULATIVE_ARGS zero_cumulative
;
8576 *cum
= zero_cumulative
;
8578 cum
->fregno
= FP_ARG_MIN_REG
;
8579 cum
->vregno
= ALTIVEC_ARG_MIN_REG
;
8580 cum
->prototype
= (fntype
&& prototype_p (fntype
));
8581 cum
->call_cookie
= ((DEFAULT_ABI
== ABI_V4
&& libcall
)
8582 ? CALL_LIBCALL
: CALL_NORMAL
);
8583 cum
->sysv_gregno
= GP_ARG_MIN_REG
;
8584 cum
->stdarg
= stdarg_p (fntype
);
8586 cum
->nargs_prototype
= 0;
8587 if (incoming
|| cum
->prototype
)
8588 cum
->nargs_prototype
= n_named_args
;
8590 /* Check for a longcall attribute. */
8591 if ((!fntype
&& rs6000_default_long_calls
)
8593 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
))
8594 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
))))
8595 cum
->call_cookie
|= CALL_LONG
;
8597 if (TARGET_DEBUG_ARG
)
8599 fprintf (stderr
, "\ninit_cumulative_args:");
8602 tree ret_type
= TREE_TYPE (fntype
);
8603 fprintf (stderr
, " ret code = %s,",
8604 get_tree_code_name (TREE_CODE (ret_type
)));
8607 if (cum
->call_cookie
& CALL_LONG
)
8608 fprintf (stderr
, " longcall,");
8610 fprintf (stderr
, " proto = %d, nargs = %d\n",
8611 cum
->prototype
, cum
->nargs_prototype
);
8614 #ifdef HAVE_AS_GNU_ATTRIBUTE
8615 if (DEFAULT_ABI
== ABI_V4
)
8617 cum
->escapes
= call_ABI_of_interest (fndecl
);
8624 return_type
= TREE_TYPE (fntype
);
8625 return_mode
= TYPE_MODE (return_type
);
8628 return_type
= lang_hooks
.types
.type_for_mode (return_mode
, 0);
8630 if (return_type
!= NULL
)
8632 if (TREE_CODE (return_type
) == RECORD_TYPE
8633 && TYPE_TRANSPARENT_AGGR (return_type
))
8635 return_type
= TREE_TYPE (first_field (return_type
));
8636 return_mode
= TYPE_MODE (return_type
);
8638 if (AGGREGATE_TYPE_P (return_type
)
8639 && ((unsigned HOST_WIDE_INT
) int_size_in_bytes (return_type
)
8641 rs6000_returns_struct
= true;
8643 if (SCALAR_FLOAT_MODE_P (return_mode
))
8644 rs6000_passes_float
= true;
8645 else if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode
)
8646 || SPE_VECTOR_MODE (return_mode
))
8647 rs6000_passes_vector
= true;
8654 && TARGET_ALTIVEC_ABI
8655 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype
))))
8657 error ("cannot return value in vector register because"
8658 " altivec instructions are disabled, use -maltivec"
8663 /* Return true if TYPE must be passed on the stack and not in registers. */
8666 rs6000_must_pass_in_stack (enum machine_mode mode
, const_tree type
)
8668 if (DEFAULT_ABI
== ABI_AIX
|| TARGET_64BIT
)
8669 return must_pass_in_stack_var_size (mode
, type
);
8671 return must_pass_in_stack_var_size_or_pad (mode
, type
);
8674 /* If defined, a C expression which determines whether, and in which
8675 direction, to pad out an argument with extra space. The value
8676 should be of type `enum direction': either `upward' to pad above
8677 the argument, `downward' to pad below, or `none' to inhibit
8680 For the AIX ABI structs are always stored left shifted in their
8684 function_arg_padding (enum machine_mode mode
, const_tree type
)
8686 #ifndef AGGREGATE_PADDING_FIXED
8687 #define AGGREGATE_PADDING_FIXED 0
8689 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
8690 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
8693 if (!AGGREGATE_PADDING_FIXED
)
8695 /* GCC used to pass structures of the same size as integer types as
8696 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
8697 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
8698 passed padded downward, except that -mstrict-align further
8699 muddied the water in that multi-component structures of 2 and 4
8700 bytes in size were passed padded upward.
8702 The following arranges for best compatibility with previous
8703 versions of gcc, but removes the -mstrict-align dependency. */
8704 if (BYTES_BIG_ENDIAN
)
8706 HOST_WIDE_INT size
= 0;
8708 if (mode
== BLKmode
)
8710 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
8711 size
= int_size_in_bytes (type
);
8714 size
= GET_MODE_SIZE (mode
);
8716 if (size
== 1 || size
== 2 || size
== 4)
8722 if (AGGREGATES_PAD_UPWARD_ALWAYS
)
8724 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
8728 /* Fall back to the default. */
8729 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
8732 /* If defined, a C expression that gives the alignment boundary, in bits,
8733 of an argument with the specified mode and type. If it is not defined,
8734 PARM_BOUNDARY is used for all arguments.
8736 V.4 wants long longs and doubles to be double word aligned. Just
8737 testing the mode size is a boneheaded way to do this as it means
8738 that other types such as complex int are also double word aligned.
8739 However, we're stuck with this because changing the ABI might break
8740 existing library interfaces.
8742 Doubleword align SPE vectors.
8743 Quadword align Altivec/VSX vectors.
8744 Quadword align large synthetic vector types. */
8747 rs6000_function_arg_boundary (enum machine_mode mode
, const_tree type
)
8749 if (DEFAULT_ABI
== ABI_V4
8750 && (GET_MODE_SIZE (mode
) == 8
8751 || (TARGET_HARD_FLOAT
8753 && (mode
== TFmode
|| mode
== TDmode
))))
8755 else if (SPE_VECTOR_MODE (mode
)
8756 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
8757 && int_size_in_bytes (type
) >= 8
8758 && int_size_in_bytes (type
) < 16))
8760 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
8761 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
8762 && int_size_in_bytes (type
) >= 16))
8764 else if (((TARGET_MACHO
&& rs6000_darwin64_abi
)
8765 || (DEFAULT_ABI
== ABI_AIX
&& !rs6000_compat_align_parm
))
8767 && type
&& TYPE_ALIGN (type
) > 64)
8770 return PARM_BOUNDARY
;
8773 /* For a function parm of MODE and TYPE, return the starting word in
8774 the parameter area. NWORDS of the parameter area are already used. */
8777 rs6000_parm_start (enum machine_mode mode
, const_tree type
,
8778 unsigned int nwords
)
8781 unsigned int parm_offset
;
8783 align
= rs6000_function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
8784 parm_offset
= DEFAULT_ABI
== ABI_V4
? 2 : 6;
8785 return nwords
+ (-(parm_offset
+ nwords
) & align
);
8788 /* Compute the size (in words) of a function argument. */
8790 static unsigned long
8791 rs6000_arg_size (enum machine_mode mode
, const_tree type
)
8795 if (mode
!= BLKmode
)
8796 size
= GET_MODE_SIZE (mode
);
8798 size
= int_size_in_bytes (type
);
8801 return (size
+ 3) >> 2;
8803 return (size
+ 7) >> 3;
8806 /* Use this to flush pending int fields. */
8809 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*cum
,
8810 HOST_WIDE_INT bitpos
, int final
)
8812 unsigned int startbit
, endbit
;
8813 int intregs
, intoffset
;
8814 enum machine_mode mode
;
8816 /* Handle the situations where a float is taking up the first half
8817 of the GPR, and the other half is empty (typically due to
8818 alignment restrictions). We can detect this by a 8-byte-aligned
8819 int field, or by seeing that this is the final flush for this
8820 argument. Count the word and continue on. */
8821 if (cum
->floats_in_gpr
== 1
8822 && (cum
->intoffset
% 64 == 0
8823 || (cum
->intoffset
== -1 && final
)))
8826 cum
->floats_in_gpr
= 0;
8829 if (cum
->intoffset
== -1)
8832 intoffset
= cum
->intoffset
;
8833 cum
->intoffset
= -1;
8834 cum
->floats_in_gpr
= 0;
8836 if (intoffset
% BITS_PER_WORD
!= 0)
8838 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
8840 if (mode
== BLKmode
)
8842 /* We couldn't find an appropriate mode, which happens,
8843 e.g., in packed structs when there are 3 bytes to load.
8844 Back intoffset back to the beginning of the word in this
8846 intoffset
= intoffset
& -BITS_PER_WORD
;
8850 startbit
= intoffset
& -BITS_PER_WORD
;
8851 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
8852 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
8853 cum
->words
+= intregs
;
8854 /* words should be unsigned. */
8855 if ((unsigned)cum
->words
< (endbit
/BITS_PER_WORD
))
8857 int pad
= (endbit
/BITS_PER_WORD
) - cum
->words
;
8862 /* The darwin64 ABI calls for us to recurse down through structs,
8863 looking for elements passed in registers. Unfortunately, we have
8864 to track int register count here also because of misalignments
8865 in powerpc alignment mode. */
8868 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*cum
,
8870 HOST_WIDE_INT startbitpos
)
8874 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
8875 if (TREE_CODE (f
) == FIELD_DECL
)
8877 HOST_WIDE_INT bitpos
= startbitpos
;
8878 tree ftype
= TREE_TYPE (f
);
8879 enum machine_mode mode
;
8880 if (ftype
== error_mark_node
)
8882 mode
= TYPE_MODE (ftype
);
8884 if (DECL_SIZE (f
) != 0
8885 && tree_fits_uhwi_p (bit_position (f
)))
8886 bitpos
+= int_bit_position (f
);
8888 /* ??? FIXME: else assume zero offset. */
8890 if (TREE_CODE (ftype
) == RECORD_TYPE
)
8891 rs6000_darwin64_record_arg_advance_recurse (cum
, ftype
, bitpos
);
8892 else if (USE_FP_FOR_ARG_P (cum
, mode
, ftype
))
8894 unsigned n_fpregs
= (GET_MODE_SIZE (mode
) + 7) >> 3;
8895 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
8896 cum
->fregno
+= n_fpregs
;
8897 /* Single-precision floats present a special problem for
8898 us, because they are smaller than an 8-byte GPR, and so
8899 the structure-packing rules combined with the standard
8900 varargs behavior mean that we want to pack float/float
8901 and float/int combinations into a single register's
8902 space. This is complicated by the arg advance flushing,
8903 which works on arbitrarily large groups of int-type
8907 if (cum
->floats_in_gpr
== 1)
8909 /* Two floats in a word; count the word and reset
8912 cum
->floats_in_gpr
= 0;
8914 else if (bitpos
% 64 == 0)
8916 /* A float at the beginning of an 8-byte word;
8917 count it and put off adjusting cum->words until
8918 we see if a arg advance flush is going to do it
8920 cum
->floats_in_gpr
++;
8924 /* The float is at the end of a word, preceded
8925 by integer fields, so the arg advance flush
8926 just above has already set cum->words and
8927 everything is taken care of. */
8931 cum
->words
+= n_fpregs
;
8933 else if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, 1))
8935 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
8939 else if (cum
->intoffset
== -1)
8940 cum
->intoffset
= bitpos
;
8944 /* Check for an item that needs to be considered specially under the darwin 64
8945 bit ABI. These are record types where the mode is BLK or the structure is
8948 rs6000_darwin64_struct_check_p (enum machine_mode mode
, const_tree type
)
8950 return rs6000_darwin64_abi
8951 && ((mode
== BLKmode
8952 && TREE_CODE (type
) == RECORD_TYPE
8953 && int_size_in_bytes (type
) > 0)
8954 || (type
&& TREE_CODE (type
) == RECORD_TYPE
8955 && int_size_in_bytes (type
) == 8)) ? 1 : 0;
8958 /* Update the data in CUM to advance over an argument
8959 of mode MODE and data type TYPE.
8960 (TYPE is null for libcalls where that information may not be available.)
8962 Note that for args passed by reference, function_arg will be called
8963 with MODE and TYPE set to that of the pointer to the arg, not the arg
8967 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
8968 const_tree type
, bool named
, int depth
)
8970 /* Only tick off an argument if we're not recursing. */
8972 cum
->nargs_prototype
--;
8974 #ifdef HAVE_AS_GNU_ATTRIBUTE
8975 if (DEFAULT_ABI
== ABI_V4
8978 if (SCALAR_FLOAT_MODE_P (mode
))
8979 rs6000_passes_float
= true;
8980 else if (named
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
8981 rs6000_passes_vector
= true;
8982 else if (SPE_VECTOR_MODE (mode
)
8984 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
8985 rs6000_passes_vector
= true;
8989 if (TARGET_ALTIVEC_ABI
8990 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
8991 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
8992 && int_size_in_bytes (type
) == 16)))
8996 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
))
8999 if (!TARGET_ALTIVEC
)
9000 error ("cannot pass argument in vector register because"
9001 " altivec instructions are disabled, use -maltivec"
9004 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
9005 even if it is going to be passed in a vector register.
9006 Darwin does the same for variable-argument functions. */
9007 if ((DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
9008 || (cum
->stdarg
&& DEFAULT_ABI
!= ABI_V4
))
9018 /* Vector parameters must be 16-byte aligned. This places
9019 them at 2 mod 4 in terms of words in 32-bit mode, since
9020 the parameter save area starts at offset 24 from the
9021 stack. In 64-bit mode, they just have to start on an
9022 even word, since the parameter save area is 16-byte
9023 aligned. Space for GPRs is reserved even if the argument
9024 will be passed in memory. */
9026 align
= (2 - cum
->words
) & 3;
9028 align
= cum
->words
& 1;
9029 cum
->words
+= align
+ rs6000_arg_size (mode
, type
);
9031 if (TARGET_DEBUG_ARG
)
9033 fprintf (stderr
, "function_adv: words = %2d, align=%d, ",
9035 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s\n",
9036 cum
->nargs_prototype
, cum
->prototype
,
9037 GET_MODE_NAME (mode
));
9041 else if (TARGET_SPE_ABI
&& TARGET_SPE
&& SPE_VECTOR_MODE (mode
)
9043 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
9046 else if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
9048 int size
= int_size_in_bytes (type
);
9049 /* Variable sized types have size == -1 and are
9050 treated as if consisting entirely of ints.
9051 Pad to 16 byte boundary if needed. */
9052 if (TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
9053 && (cum
->words
% 2) != 0)
9055 /* For varargs, we can just go up by the size of the struct. */
9057 cum
->words
+= (size
+ 7) / 8;
9060 /* It is tempting to say int register count just goes up by
9061 sizeof(type)/8, but this is wrong in a case such as
9062 { int; double; int; } [powerpc alignment]. We have to
9063 grovel through the fields for these too. */
9065 cum
->floats_in_gpr
= 0;
9066 rs6000_darwin64_record_arg_advance_recurse (cum
, type
, 0);
9067 rs6000_darwin64_record_arg_advance_flush (cum
,
9068 size
* BITS_PER_UNIT
, 1);
9070 if (TARGET_DEBUG_ARG
)
9072 fprintf (stderr
, "function_adv: words = %2d, align=%d, size=%d",
9073 cum
->words
, TYPE_ALIGN (type
), size
);
9075 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
9076 cum
->nargs_prototype
, cum
->prototype
,
9077 GET_MODE_NAME (mode
));
9080 else if (DEFAULT_ABI
== ABI_V4
)
9082 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
9083 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
9084 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
9085 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
9086 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
9088 /* _Decimal128 must use an even/odd register pair. This assumes
9089 that the register number is odd when fregno is odd. */
9090 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
9093 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
9094 <= FP_ARG_V4_MAX_REG
)
9095 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
9098 cum
->fregno
= FP_ARG_V4_MAX_REG
+ 1;
9099 if (mode
== DFmode
|| mode
== TFmode
9100 || mode
== DDmode
|| mode
== TDmode
)
9101 cum
->words
+= cum
->words
& 1;
9102 cum
->words
+= rs6000_arg_size (mode
, type
);
9107 int n_words
= rs6000_arg_size (mode
, type
);
9108 int gregno
= cum
->sysv_gregno
;
9110 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
9111 (r7,r8) or (r9,r10). As does any other 2 word item such
9112 as complex int due to a historical mistake. */
9114 gregno
+= (1 - gregno
) & 1;
9116 /* Multi-reg args are not split between registers and stack. */
9117 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
9119 /* Long long and SPE vectors are aligned on the stack.
9120 So are other 2 word items such as complex int due to
9121 a historical mistake. */
9123 cum
->words
+= cum
->words
& 1;
9124 cum
->words
+= n_words
;
9127 /* Note: continuing to accumulate gregno past when we've started
9128 spilling to the stack indicates the fact that we've started
9129 spilling to the stack to expand_builtin_saveregs. */
9130 cum
->sysv_gregno
= gregno
+ n_words
;
9133 if (TARGET_DEBUG_ARG
)
9135 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
9136 cum
->words
, cum
->fregno
);
9137 fprintf (stderr
, "gregno = %2d, nargs = %4d, proto = %d, ",
9138 cum
->sysv_gregno
, cum
->nargs_prototype
, cum
->prototype
);
9139 fprintf (stderr
, "mode = %4s, named = %d\n",
9140 GET_MODE_NAME (mode
), named
);
9145 int n_words
= rs6000_arg_size (mode
, type
);
9146 int start_words
= cum
->words
;
9147 int align_words
= rs6000_parm_start (mode
, type
, start_words
);
9149 cum
->words
= align_words
+ n_words
;
9151 if (SCALAR_FLOAT_MODE_P (mode
)
9152 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
9154 /* _Decimal128 must be passed in an even/odd float register pair.
9155 This assumes that the register number is odd when fregno is
9157 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
9159 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
9162 if (TARGET_DEBUG_ARG
)
9164 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
9165 cum
->words
, cum
->fregno
);
9166 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s, ",
9167 cum
->nargs_prototype
, cum
->prototype
, GET_MODE_NAME (mode
));
9168 fprintf (stderr
, "named = %d, align = %d, depth = %d\n",
9169 named
, align_words
- start_words
, depth
);
9175 rs6000_function_arg_advance (cumulative_args_t cum
, enum machine_mode mode
,
9176 const_tree type
, bool named
)
9178 rs6000_function_arg_advance_1 (get_cumulative_args (cum
), mode
, type
, named
,
9183 spe_build_register_parallel (enum machine_mode mode
, int gregno
)
9190 r1
= gen_rtx_REG (DImode
, gregno
);
9191 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
9192 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, r1
));
9196 r1
= gen_rtx_REG (DImode
, gregno
);
9197 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
9198 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
9199 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
9200 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r3
));
9203 r1
= gen_rtx_REG (DImode
, gregno
);
9204 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
9205 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
9206 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
9207 r5
= gen_rtx_REG (DImode
, gregno
+ 4);
9208 r5
= gen_rtx_EXPR_LIST (VOIDmode
, r5
, GEN_INT (16));
9209 r7
= gen_rtx_REG (DImode
, gregno
+ 6);
9210 r7
= gen_rtx_EXPR_LIST (VOIDmode
, r7
, GEN_INT (24));
9211 return gen_rtx_PARALLEL (mode
, gen_rtvec (4, r1
, r3
, r5
, r7
));
9218 /* Determine where to put a SIMD argument on the SPE. */
9220 rs6000_spe_function_arg (const CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
9223 int gregno
= cum
->sysv_gregno
;
9225 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
9226 are passed and returned in a pair of GPRs for ABI compatibility. */
9227 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
9228 || mode
== DCmode
|| mode
== TCmode
))
9230 int n_words
= rs6000_arg_size (mode
, type
);
9232 /* Doubles go in an odd/even register pair (r5/r6, etc). */
9234 gregno
+= (1 - gregno
) & 1;
9236 /* Multi-reg args are not split between registers and stack. */
9237 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
9240 return spe_build_register_parallel (mode
, gregno
);
9244 int n_words
= rs6000_arg_size (mode
, type
);
9246 /* SPE vectors are put in odd registers. */
9247 if (n_words
== 2 && (gregno
& 1) == 0)
9250 if (gregno
+ n_words
- 1 <= GP_ARG_MAX_REG
)
9253 enum machine_mode m
= SImode
;
9255 r1
= gen_rtx_REG (m
, gregno
);
9256 r1
= gen_rtx_EXPR_LIST (m
, r1
, const0_rtx
);
9257 r2
= gen_rtx_REG (m
, gregno
+ 1);
9258 r2
= gen_rtx_EXPR_LIST (m
, r2
, GEN_INT (4));
9259 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
9266 if (gregno
<= GP_ARG_MAX_REG
)
9267 return gen_rtx_REG (mode
, gregno
);
9273 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
9274 structure between cum->intoffset and bitpos to integer registers. */
9277 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*cum
,
9278 HOST_WIDE_INT bitpos
, rtx rvec
[], int *k
)
9280 enum machine_mode mode
;
9282 unsigned int startbit
, endbit
;
9283 int this_regno
, intregs
, intoffset
;
9286 if (cum
->intoffset
== -1)
9289 intoffset
= cum
->intoffset
;
9290 cum
->intoffset
= -1;
9292 /* If this is the trailing part of a word, try to only load that
9293 much into the register. Otherwise load the whole register. Note
9294 that in the latter case we may pick up unwanted bits. It's not a
9295 problem at the moment but may wish to revisit. */
9297 if (intoffset
% BITS_PER_WORD
!= 0)
9299 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
9301 if (mode
== BLKmode
)
9303 /* We couldn't find an appropriate mode, which happens,
9304 e.g., in packed structs when there are 3 bytes to load.
9305 Back intoffset back to the beginning of the word in this
9307 intoffset
= intoffset
& -BITS_PER_WORD
;
9314 startbit
= intoffset
& -BITS_PER_WORD
;
9315 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
9316 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
9317 this_regno
= cum
->words
+ intoffset
/ BITS_PER_WORD
;
9319 if (intregs
> 0 && intregs
> GP_ARG_NUM_REG
- this_regno
)
9322 intregs
= MIN (intregs
, GP_ARG_NUM_REG
- this_regno
);
9326 intoffset
/= BITS_PER_UNIT
;
9329 regno
= GP_ARG_MIN_REG
+ this_regno
;
9330 reg
= gen_rtx_REG (mode
, regno
);
9332 gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
9335 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
9339 while (intregs
> 0);
9342 /* Recursive workhorse for the following. */
9345 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*cum
, const_tree type
,
9346 HOST_WIDE_INT startbitpos
, rtx rvec
[],
9351 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
9352 if (TREE_CODE (f
) == FIELD_DECL
)
9354 HOST_WIDE_INT bitpos
= startbitpos
;
9355 tree ftype
= TREE_TYPE (f
);
9356 enum machine_mode mode
;
9357 if (ftype
== error_mark_node
)
9359 mode
= TYPE_MODE (ftype
);
9361 if (DECL_SIZE (f
) != 0
9362 && tree_fits_uhwi_p (bit_position (f
)))
9363 bitpos
+= int_bit_position (f
);
9365 /* ??? FIXME: else assume zero offset. */
9367 if (TREE_CODE (ftype
) == RECORD_TYPE
)
9368 rs6000_darwin64_record_arg_recurse (cum
, ftype
, bitpos
, rvec
, k
);
9369 else if (cum
->named
&& USE_FP_FOR_ARG_P (cum
, mode
, ftype
))
9371 unsigned n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
9375 case SCmode
: mode
= SFmode
; break;
9376 case DCmode
: mode
= DFmode
; break;
9377 case TCmode
: mode
= TFmode
; break;
9381 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
9382 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
9384 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
9385 && (mode
== TFmode
|| mode
== TDmode
));
9386 /* Long double or _Decimal128 split over regs and memory. */
9387 mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
: DFmode
;
9391 = gen_rtx_EXPR_LIST (VOIDmode
,
9392 gen_rtx_REG (mode
, cum
->fregno
++),
9393 GEN_INT (bitpos
/ BITS_PER_UNIT
));
9394 if (mode
== TFmode
|| mode
== TDmode
)
9397 else if (cum
->named
&& USE_ALTIVEC_FOR_ARG_P (cum
, mode
, ftype
, 1))
9399 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
9401 = gen_rtx_EXPR_LIST (VOIDmode
,
9402 gen_rtx_REG (mode
, cum
->vregno
++),
9403 GEN_INT (bitpos
/ BITS_PER_UNIT
));
9405 else if (cum
->intoffset
== -1)
9406 cum
->intoffset
= bitpos
;
9410 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
9411 the register(s) to be used for each field and subfield of a struct
9412 being passed by value, along with the offset of where the
9413 register's value may be found in the block. FP fields go in FP
9414 register, vector fields go in vector registers, and everything
9415 else goes in int registers, packed as in memory.
9417 This code is also used for function return values. RETVAL indicates
9418 whether this is the case.
9420 Much of this is taken from the SPARC V9 port, which has a similar
9421 calling convention. */
9424 rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*orig_cum
, const_tree type
,
9425 bool named
, bool retval
)
9427 rtx rvec
[FIRST_PSEUDO_REGISTER
];
9428 int k
= 1, kbase
= 1;
9429 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
9430 /* This is a copy; modifications are not visible to our caller. */
9431 CUMULATIVE_ARGS copy_cum
= *orig_cum
;
9432 CUMULATIVE_ARGS
*cum
= ©_cum
;
9434 /* Pad to 16 byte boundary if needed. */
9435 if (!retval
&& TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
9436 && (cum
->words
% 2) != 0)
9443 /* Put entries into rvec[] for individual FP and vector fields, and
9444 for the chunks of memory that go in int regs. Note we start at
9445 element 1; 0 is reserved for an indication of using memory, and
9446 may or may not be filled in below. */
9447 rs6000_darwin64_record_arg_recurse (cum
, type
, /* startbit pos= */ 0, rvec
, &k
);
9448 rs6000_darwin64_record_arg_flush (cum
, typesize
* BITS_PER_UNIT
, rvec
, &k
);
9450 /* If any part of the struct went on the stack put all of it there.
9451 This hack is because the generic code for
9452 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
9453 parts of the struct are not at the beginning. */
9457 return NULL_RTX
; /* doesn't go in registers at all */
9459 rvec
[0] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
9461 if (k
> 1 || cum
->use_stack
)
9462 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (k
- kbase
, &rvec
[kbase
]));
9467 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
9470 rs6000_mixed_function_arg (enum machine_mode mode
, const_tree type
,
9475 rtx rvec
[GP_ARG_NUM_REG
+ 1];
9477 if (align_words
>= GP_ARG_NUM_REG
)
9480 n_units
= rs6000_arg_size (mode
, type
);
9482 /* Optimize the simple case where the arg fits in one gpr, except in
9483 the case of BLKmode due to assign_parms assuming that registers are
9484 BITS_PER_WORD wide. */
9486 || (n_units
== 1 && mode
!= BLKmode
))
9487 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
9490 if (align_words
+ n_units
> GP_ARG_NUM_REG
)
9491 /* Not all of the arg fits in gprs. Say that it goes in memory too,
9492 using a magic NULL_RTX component.
9493 This is not strictly correct. Only some of the arg belongs in
9494 memory, not all of it. However, the normal scheme using
9495 function_arg_partial_nregs can result in unusual subregs, eg.
9496 (subreg:SI (reg:DF) 4), which are not handled well. The code to
9497 store the whole arg to memory is often more efficient than code
9498 to store pieces, and we know that space is available in the right
9499 place for the whole arg. */
9500 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
9505 rtx r
= gen_rtx_REG (SImode
, GP_ARG_MIN_REG
+ align_words
);
9506 rtx off
= GEN_INT (i
++ * 4);
9507 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
9509 while (++align_words
< GP_ARG_NUM_REG
&& --n_units
!= 0);
9511 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
9514 /* Determine where to put an argument to a function.
9515 Value is zero to push the argument on the stack,
9516 or a hard register in which to store the argument.
9518 MODE is the argument's machine mode.
9519 TYPE is the data type of the argument (as a tree).
9520 This is null for libcalls where that information may
9522 CUM is a variable of type CUMULATIVE_ARGS which gives info about
9523 the preceding args and about the function being called. It is
9524 not modified in this routine.
9525 NAMED is nonzero if this argument is a named parameter
9526 (otherwise it is an extra parameter matching an ellipsis).
9528 On RS/6000 the first eight words of non-FP are normally in registers
9529 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
9530 Under V.4, the first 8 FP args are in registers.
9532 If this is floating-point and no prototype is specified, we use
9533 both an FP and integer register (or possibly FP reg and stack). Library
9534 functions (when CALL_LIBCALL is set) always have the proper types for args,
9535 so we can pass the FP value just in one register. emit_library_function
9536 doesn't support PARALLEL anyway.
9538 Note that for args passed by reference, function_arg will be called
9539 with MODE and TYPE set to that of the pointer to the arg, not the arg
9543 rs6000_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
9544 const_tree type
, bool named
)
9546 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
9547 enum rs6000_abi abi
= DEFAULT_ABI
;
9549 /* Return a marker to indicate whether CR1 needs to set or clear the
9550 bit that V.4 uses to say fp args were passed in registers.
9551 Assume that we don't need the marker for software floating point,
9552 or compiler generated library calls. */
9553 if (mode
== VOIDmode
)
9556 && (cum
->call_cookie
& CALL_LIBCALL
) == 0
9558 || (cum
->nargs_prototype
< 0
9559 && (cum
->prototype
|| TARGET_NO_PROTOTYPE
))))
9561 /* For the SPE, we need to crxor CR6 always. */
9563 return GEN_INT (cum
->call_cookie
| CALL_V4_SET_FP_ARGS
);
9564 else if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
9565 return GEN_INT (cum
->call_cookie
9566 | ((cum
->fregno
== FP_ARG_MIN_REG
)
9567 ? CALL_V4_SET_FP_ARGS
9568 : CALL_V4_CLEAR_FP_ARGS
));
9571 return GEN_INT (cum
->call_cookie
& ~CALL_LIBCALL
);
9574 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
9576 rtx rslt
= rs6000_darwin64_record_arg (cum
, type
, named
, /*retval= */false);
9577 if (rslt
!= NULL_RTX
)
9579 /* Else fall through to usual handling. */
9582 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
))
9583 if (TARGET_64BIT
&& ! cum
->prototype
)
9585 /* Vector parameters get passed in vector register
9586 and also in GPRs or memory, in absence of prototype. */
9589 align_words
= (cum
->words
+ 1) & ~1;
9591 if (align_words
>= GP_ARG_NUM_REG
)
9597 slot
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
9599 return gen_rtx_PARALLEL (mode
,
9601 gen_rtx_EXPR_LIST (VOIDmode
,
9603 gen_rtx_EXPR_LIST (VOIDmode
,
9604 gen_rtx_REG (mode
, cum
->vregno
),
9608 return gen_rtx_REG (mode
, cum
->vregno
);
9609 else if (TARGET_ALTIVEC_ABI
9610 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
9611 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9612 && int_size_in_bytes (type
) == 16)))
9614 if (named
|| abi
== ABI_V4
)
9618 /* Vector parameters to varargs functions under AIX or Darwin
9619 get passed in memory and possibly also in GPRs. */
9620 int align
, align_words
, n_words
;
9621 enum machine_mode part_mode
;
9623 /* Vector parameters must be 16-byte aligned. This places them at
9624 2 mod 4 in terms of words in 32-bit mode, since the parameter
9625 save area starts at offset 24 from the stack. In 64-bit mode,
9626 they just have to start on an even word, since the parameter
9627 save area is 16-byte aligned. */
9629 align
= (2 - cum
->words
) & 3;
9631 align
= cum
->words
& 1;
9632 align_words
= cum
->words
+ align
;
9634 /* Out of registers? Memory, then. */
9635 if (align_words
>= GP_ARG_NUM_REG
)
9638 if (TARGET_32BIT
&& TARGET_POWERPC64
)
9639 return rs6000_mixed_function_arg (mode
, type
, align_words
);
9641 /* The vector value goes in GPRs. Only the part of the
9642 value in GPRs is reported here. */
9644 n_words
= rs6000_arg_size (mode
, type
);
9645 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
9646 /* Fortunately, there are only two possibilities, the value
9647 is either wholly in GPRs or half in GPRs and half not. */
9650 return gen_rtx_REG (part_mode
, GP_ARG_MIN_REG
+ align_words
);
9653 else if (TARGET_SPE_ABI
&& TARGET_SPE
9654 && (SPE_VECTOR_MODE (mode
)
9655 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
9658 || mode
== TCmode
))))
9659 return rs6000_spe_function_arg (cum
, mode
, type
);
9661 else if (abi
== ABI_V4
)
9663 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
9664 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
9665 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
9666 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
9667 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
9669 /* _Decimal128 must use an even/odd register pair. This assumes
9670 that the register number is odd when fregno is odd. */
9671 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
9674 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
9675 <= FP_ARG_V4_MAX_REG
)
9676 return gen_rtx_REG (mode
, cum
->fregno
);
9682 int n_words
= rs6000_arg_size (mode
, type
);
9683 int gregno
= cum
->sysv_gregno
;
9685 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
9686 (r7,r8) or (r9,r10). As does any other 2 word item such
9687 as complex int due to a historical mistake. */
9689 gregno
+= (1 - gregno
) & 1;
9691 /* Multi-reg args are not split between registers and stack. */
9692 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
9695 if (TARGET_32BIT
&& TARGET_POWERPC64
)
9696 return rs6000_mixed_function_arg (mode
, type
,
9697 gregno
- GP_ARG_MIN_REG
);
9698 return gen_rtx_REG (mode
, gregno
);
9703 int align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
9705 /* _Decimal128 must be passed in an even/odd float register pair.
9706 This assumes that the register number is odd when fregno is odd. */
9707 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
9710 if (USE_FP_FOR_ARG_P (cum
, mode
, type
))
9712 rtx rvec
[GP_ARG_NUM_REG
+ 1];
9716 enum machine_mode fmode
= mode
;
9717 unsigned long n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
9719 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
9721 /* Currently, we only ever need one reg here because complex
9722 doubles are split. */
9723 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
9724 && (fmode
== TFmode
|| fmode
== TDmode
));
9726 /* Long double or _Decimal128 split over regs and memory. */
9727 fmode
= DECIMAL_FLOAT_MODE_P (fmode
) ? DDmode
: DFmode
;
9730 /* Do we also need to pass this arg in the parameter save
9733 && (cum
->nargs_prototype
<= 0
9734 || (DEFAULT_ABI
== ABI_AIX
9736 && align_words
>= GP_ARG_NUM_REG
)));
9738 if (!needs_psave
&& mode
== fmode
)
9739 return gen_rtx_REG (fmode
, cum
->fregno
);
9744 /* Describe the part that goes in gprs or the stack.
9745 This piece must come first, before the fprs. */
9746 if (align_words
< GP_ARG_NUM_REG
)
9748 unsigned long n_words
= rs6000_arg_size (mode
, type
);
9750 if (align_words
+ n_words
> GP_ARG_NUM_REG
9751 || (TARGET_32BIT
&& TARGET_POWERPC64
))
9753 /* If this is partially on the stack, then we only
9754 include the portion actually in registers here. */
9755 enum machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
9758 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
9759 /* Not all of the arg fits in gprs. Say that it
9760 goes in memory too, using a magic NULL_RTX
9761 component. Also see comment in
9762 rs6000_mixed_function_arg for why the normal
9763 function_arg_partial_nregs scheme doesn't work
9765 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
,
9769 r
= gen_rtx_REG (rmode
,
9770 GP_ARG_MIN_REG
+ align_words
);
9771 off
= GEN_INT (i
++ * GET_MODE_SIZE (rmode
));
9772 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
9774 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
9778 /* The whole arg fits in gprs. */
9779 r
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
9780 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
9784 /* It's entirely in memory. */
9785 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
9788 /* Describe where this piece goes in the fprs. */
9789 r
= gen_rtx_REG (fmode
, cum
->fregno
);
9790 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
9792 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
9794 else if (align_words
< GP_ARG_NUM_REG
)
9796 if (TARGET_32BIT
&& TARGET_POWERPC64
)
9797 return rs6000_mixed_function_arg (mode
, type
, align_words
);
9799 if (mode
== BLKmode
)
9802 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
9809 /* For an arg passed partly in registers and partly in memory, this is
9810 the number of bytes passed in registers. For args passed entirely in
9811 registers or entirely in memory, zero. When an arg is described by a
9812 PARALLEL, perhaps using more than one register type, this function
9813 returns the number of bytes used by the first element of the PARALLEL. */
9816 rs6000_arg_partial_bytes (cumulative_args_t cum_v
, enum machine_mode mode
,
9817 tree type
, bool named
)
9819 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
9823 if (DEFAULT_ABI
== ABI_V4
)
9826 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
)
9827 && cum
->nargs_prototype
>= 0)
9830 /* In this complicated case we just disable the partial_nregs code. */
9831 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
9834 align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
9836 if (USE_FP_FOR_ARG_P (cum
, mode
, type
))
9838 /* If we are passing this arg in the fixed parameter save area
9839 (gprs or memory) as well as fprs, then this function should
9840 return the number of partial bytes passed in the parameter
9841 save area rather than partial bytes passed in fprs. */
9843 && (cum
->nargs_prototype
<= 0
9844 || (DEFAULT_ABI
== ABI_AIX
9846 && align_words
>= GP_ARG_NUM_REG
)))
9848 else if (cum
->fregno
+ ((GET_MODE_SIZE (mode
) + 7) >> 3)
9849 > FP_ARG_MAX_REG
+ 1)
9850 ret
= (FP_ARG_MAX_REG
+ 1 - cum
->fregno
) * 8;
9851 else if (cum
->nargs_prototype
>= 0)
9855 if (align_words
< GP_ARG_NUM_REG
9856 && GP_ARG_NUM_REG
< align_words
+ rs6000_arg_size (mode
, type
))
9857 ret
= (GP_ARG_NUM_REG
- align_words
) * (TARGET_32BIT
? 4 : 8);
9859 if (ret
!= 0 && TARGET_DEBUG_ARG
)
9860 fprintf (stderr
, "rs6000_arg_partial_bytes: %d\n", ret
);
9865 /* A C expression that indicates when an argument must be passed by
9866 reference. If nonzero for an argument, a copy of that argument is
9867 made in memory and a pointer to the argument is passed instead of
9868 the argument itself. The pointer is passed in whatever way is
9869 appropriate for passing a pointer to that type.
9871 Under V.4, aggregates and long double are passed by reference.
9873 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
9874 reference unless the AltiVec vector extension ABI is in force.
9876 As an extension to all ABIs, variable sized types are passed by
9880 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
9881 enum machine_mode mode
, const_tree type
,
9882 bool named ATTRIBUTE_UNUSED
)
9884 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& mode
== TFmode
)
9886 if (TARGET_DEBUG_ARG
)
9887 fprintf (stderr
, "function_arg_pass_by_reference: V4 long double\n");
9894 if (DEFAULT_ABI
== ABI_V4
&& AGGREGATE_TYPE_P (type
))
9896 if (TARGET_DEBUG_ARG
)
9897 fprintf (stderr
, "function_arg_pass_by_reference: V4 aggregate\n");
9901 if (int_size_in_bytes (type
) < 0)
9903 if (TARGET_DEBUG_ARG
)
9904 fprintf (stderr
, "function_arg_pass_by_reference: variable size\n");
9908 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
9909 modes only exist for GCC vector types if -maltivec. */
9910 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
9912 if (TARGET_DEBUG_ARG
)
9913 fprintf (stderr
, "function_arg_pass_by_reference: AltiVec\n");
9917 /* Pass synthetic vectors in memory. */
9918 if (TREE_CODE (type
) == VECTOR_TYPE
9919 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
9921 static bool warned_for_pass_big_vectors
= false;
9922 if (TARGET_DEBUG_ARG
)
9923 fprintf (stderr
, "function_arg_pass_by_reference: synthetic vector\n");
9924 if (!warned_for_pass_big_vectors
)
9926 warning (0, "GCC vector passed by reference: "
9927 "non-standard ABI extension with no compatibility guarantee");
9928 warned_for_pass_big_vectors
= true;
9937 rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
)
9940 enum machine_mode reg_mode
= TARGET_32BIT
? SImode
: DImode
;
9945 for (i
= 0; i
< nregs
; i
++)
9947 rtx tem
= adjust_address_nv (x
, reg_mode
, i
* GET_MODE_SIZE (reg_mode
));
9948 if (reload_completed
)
9950 if (! strict_memory_address_p (reg_mode
, XEXP (tem
, 0)))
9953 tem
= simplify_gen_subreg (reg_mode
, x
, BLKmode
,
9954 i
* GET_MODE_SIZE (reg_mode
));
9957 tem
= replace_equiv_address (tem
, XEXP (tem
, 0));
9961 emit_move_insn (tem
, gen_rtx_REG (reg_mode
, regno
+ i
));
9965 /* Perform any needed actions needed for a function that is receiving a
9966 variable number of arguments.
9970 MODE and TYPE are the mode and type of the current parameter.
9972 PRETEND_SIZE is a variable that should be set to the amount of stack
9973 that must be pushed by the prolog to pretend that our caller pushed
9976 Normally, this macro will push all remaining incoming registers on the
9977 stack and set PRETEND_SIZE to the length of the registers pushed. */
9980 setup_incoming_varargs (cumulative_args_t cum
, enum machine_mode mode
,
9981 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
9984 CUMULATIVE_ARGS next_cum
;
9985 int reg_size
= TARGET_32BIT
? 4 : 8;
9986 rtx save_area
= NULL_RTX
, mem
;
9987 int first_reg_offset
;
9990 /* Skip the last named argument. */
9991 next_cum
= *get_cumulative_args (cum
);
9992 rs6000_function_arg_advance_1 (&next_cum
, mode
, type
, true, 0);
9994 if (DEFAULT_ABI
== ABI_V4
)
9996 first_reg_offset
= next_cum
.sysv_gregno
- GP_ARG_MIN_REG
;
10000 int gpr_reg_num
= 0, gpr_size
= 0, fpr_size
= 0;
10001 HOST_WIDE_INT offset
= 0;
10003 /* Try to optimize the size of the varargs save area.
10004 The ABI requires that ap.reg_save_area is doubleword
10005 aligned, but we don't need to allocate space for all
10006 the bytes, only those to which we actually will save
10008 if (cfun
->va_list_gpr_size
&& first_reg_offset
< GP_ARG_NUM_REG
)
10009 gpr_reg_num
= GP_ARG_NUM_REG
- first_reg_offset
;
10010 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
10011 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
10012 && cfun
->va_list_fpr_size
)
10015 fpr_size
= (next_cum
.fregno
- FP_ARG_MIN_REG
)
10016 * UNITS_PER_FP_WORD
;
10017 if (cfun
->va_list_fpr_size
10018 < FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
10019 fpr_size
+= cfun
->va_list_fpr_size
* UNITS_PER_FP_WORD
;
10021 fpr_size
+= (FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
10022 * UNITS_PER_FP_WORD
;
10026 offset
= -((first_reg_offset
* reg_size
) & ~7);
10027 if (!fpr_size
&& gpr_reg_num
> cfun
->va_list_gpr_size
)
10029 gpr_reg_num
= cfun
->va_list_gpr_size
;
10030 if (reg_size
== 4 && (first_reg_offset
& 1))
10033 gpr_size
= (gpr_reg_num
* reg_size
+ 7) & ~7;
10036 offset
= - (int) (next_cum
.fregno
- FP_ARG_MIN_REG
)
10037 * UNITS_PER_FP_WORD
10038 - (int) (GP_ARG_NUM_REG
* reg_size
);
10040 if (gpr_size
+ fpr_size
)
10043 = assign_stack_local (BLKmode
, gpr_size
+ fpr_size
, 64);
10044 gcc_assert (GET_CODE (reg_save_area
) == MEM
);
10045 reg_save_area
= XEXP (reg_save_area
, 0);
10046 if (GET_CODE (reg_save_area
) == PLUS
)
10048 gcc_assert (XEXP (reg_save_area
, 0)
10049 == virtual_stack_vars_rtx
);
10050 gcc_assert (GET_CODE (XEXP (reg_save_area
, 1)) == CONST_INT
);
10051 offset
+= INTVAL (XEXP (reg_save_area
, 1));
10054 gcc_assert (reg_save_area
== virtual_stack_vars_rtx
);
10057 cfun
->machine
->varargs_save_offset
= offset
;
10058 save_area
= plus_constant (Pmode
, virtual_stack_vars_rtx
, offset
);
10063 first_reg_offset
= next_cum
.words
;
10064 save_area
= virtual_incoming_args_rtx
;
10066 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
10067 first_reg_offset
+= rs6000_arg_size (TYPE_MODE (type
), type
);
10070 set
= get_varargs_alias_set ();
10071 if (! no_rtl
&& first_reg_offset
< GP_ARG_NUM_REG
10072 && cfun
->va_list_gpr_size
)
10074 int n_gpr
, nregs
= GP_ARG_NUM_REG
- first_reg_offset
;
10076 if (va_list_gpr_counter_field
)
10077 /* V4 va_list_gpr_size counts number of registers needed. */
10078 n_gpr
= cfun
->va_list_gpr_size
;
10080 /* char * va_list instead counts number of bytes needed. */
10081 n_gpr
= (cfun
->va_list_gpr_size
+ reg_size
- 1) / reg_size
;
10086 mem
= gen_rtx_MEM (BLKmode
,
10087 plus_constant (Pmode
, save_area
,
10088 first_reg_offset
* reg_size
));
10089 MEM_NOTRAP_P (mem
) = 1;
10090 set_mem_alias_set (mem
, set
);
10091 set_mem_align (mem
, BITS_PER_WORD
);
10093 rs6000_move_block_from_reg (GP_ARG_MIN_REG
+ first_reg_offset
, mem
,
10097 /* Save FP registers if needed. */
10098 if (DEFAULT_ABI
== ABI_V4
10099 && TARGET_HARD_FLOAT
&& TARGET_FPRS
10101 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
10102 && cfun
->va_list_fpr_size
)
10104 int fregno
= next_cum
.fregno
, nregs
;
10105 rtx cr1
= gen_rtx_REG (CCmode
, CR1_REGNO
);
10106 rtx lab
= gen_label_rtx ();
10107 int off
= (GP_ARG_NUM_REG
* reg_size
) + ((fregno
- FP_ARG_MIN_REG
)
10108 * UNITS_PER_FP_WORD
);
10111 (gen_rtx_SET (VOIDmode
,
10113 gen_rtx_IF_THEN_ELSE (VOIDmode
,
10114 gen_rtx_NE (VOIDmode
, cr1
,
10116 gen_rtx_LABEL_REF (VOIDmode
, lab
),
10120 fregno
<= FP_ARG_V4_MAX_REG
&& nregs
< cfun
->va_list_fpr_size
;
10121 fregno
++, off
+= UNITS_PER_FP_WORD
, nregs
++)
10123 mem
= gen_rtx_MEM ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
10125 plus_constant (Pmode
, save_area
, off
));
10126 MEM_NOTRAP_P (mem
) = 1;
10127 set_mem_alias_set (mem
, set
);
10128 set_mem_align (mem
, GET_MODE_ALIGNMENT (
10129 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
10130 ? DFmode
: SFmode
));
10131 emit_move_insn (mem
, gen_rtx_REG (
10132 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
10133 ? DFmode
: SFmode
, fregno
));
10140 /* Create the va_list data type. */
10143 rs6000_build_builtin_va_list (void)
10145 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
, record
, type_decl
;
10147 /* For AIX, prefer 'char *' because that's what the system
10148 header files like. */
10149 if (DEFAULT_ABI
!= ABI_V4
)
10150 return build_pointer_type (char_type_node
);
10152 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
10153 type_decl
= build_decl (BUILTINS_LOCATION
, TYPE_DECL
,
10154 get_identifier ("__va_list_tag"), record
);
10156 f_gpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("gpr"),
10157 unsigned_char_type_node
);
10158 f_fpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("fpr"),
10159 unsigned_char_type_node
);
10160 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
10161 every user file. */
10162 f_res
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
10163 get_identifier ("reserved"), short_unsigned_type_node
);
10164 f_ovf
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
10165 get_identifier ("overflow_arg_area"),
10167 f_sav
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
10168 get_identifier ("reg_save_area"),
10171 va_list_gpr_counter_field
= f_gpr
;
10172 va_list_fpr_counter_field
= f_fpr
;
10174 DECL_FIELD_CONTEXT (f_gpr
) = record
;
10175 DECL_FIELD_CONTEXT (f_fpr
) = record
;
10176 DECL_FIELD_CONTEXT (f_res
) = record
;
10177 DECL_FIELD_CONTEXT (f_ovf
) = record
;
10178 DECL_FIELD_CONTEXT (f_sav
) = record
;
10180 TYPE_STUB_DECL (record
) = type_decl
;
10181 TYPE_NAME (record
) = type_decl
;
10182 TYPE_FIELDS (record
) = f_gpr
;
10183 DECL_CHAIN (f_gpr
) = f_fpr
;
10184 DECL_CHAIN (f_fpr
) = f_res
;
10185 DECL_CHAIN (f_res
) = f_ovf
;
10186 DECL_CHAIN (f_ovf
) = f_sav
;
10188 layout_type (record
);
10190 /* The correct type is an array type of one element. */
10191 return build_array_type (record
, build_index_type (size_zero_node
));
10194 /* Implement va_start. */
10197 rs6000_va_start (tree valist
, rtx nextarg
)
10199 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
10200 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
10201 tree gpr
, fpr
, ovf
, sav
, t
;
10203 /* Only SVR4 needs something special. */
10204 if (DEFAULT_ABI
!= ABI_V4
)
10206 std_expand_builtin_va_start (valist
, nextarg
);
10210 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
10211 f_fpr
= DECL_CHAIN (f_gpr
);
10212 f_res
= DECL_CHAIN (f_fpr
);
10213 f_ovf
= DECL_CHAIN (f_res
);
10214 f_sav
= DECL_CHAIN (f_ovf
);
10216 valist
= build_simple_mem_ref (valist
);
10217 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
10218 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
10220 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
10222 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
10225 /* Count number of gp and fp argument registers used. */
10226 words
= crtl
->args
.info
.words
;
10227 n_gpr
= MIN (crtl
->args
.info
.sysv_gregno
- GP_ARG_MIN_REG
,
10229 n_fpr
= MIN (crtl
->args
.info
.fregno
- FP_ARG_MIN_REG
,
10232 if (TARGET_DEBUG_ARG
)
10233 fprintf (stderr
, "va_start: words = "HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
10234 HOST_WIDE_INT_PRINT_DEC
", n_fpr = "HOST_WIDE_INT_PRINT_DEC
"\n",
10235 words
, n_gpr
, n_fpr
);
10237 if (cfun
->va_list_gpr_size
)
10239 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
10240 build_int_cst (NULL_TREE
, n_gpr
));
10241 TREE_SIDE_EFFECTS (t
) = 1;
10242 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
10245 if (cfun
->va_list_fpr_size
)
10247 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
10248 build_int_cst (NULL_TREE
, n_fpr
));
10249 TREE_SIDE_EFFECTS (t
) = 1;
10250 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
10252 #ifdef HAVE_AS_GNU_ATTRIBUTE
10253 if (call_ABI_of_interest (cfun
->decl
))
10254 rs6000_passes_float
= true;
10258 /* Find the overflow area. */
10259 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
10261 t
= fold_build_pointer_plus_hwi (t
, words
* UNITS_PER_WORD
);
10262 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
10263 TREE_SIDE_EFFECTS (t
) = 1;
10264 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
10266 /* If there were no va_arg invocations, don't set up the register
10268 if (!cfun
->va_list_gpr_size
10269 && !cfun
->va_list_fpr_size
10270 && n_gpr
< GP_ARG_NUM_REG
10271 && n_fpr
< FP_ARG_V4_MAX_REG
)
10274 /* Find the register save area. */
10275 t
= make_tree (TREE_TYPE (sav
), virtual_stack_vars_rtx
);
10276 if (cfun
->machine
->varargs_save_offset
)
10277 t
= fold_build_pointer_plus_hwi (t
, cfun
->machine
->varargs_save_offset
);
10278 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
10279 TREE_SIDE_EFFECTS (t
) = 1;
10280 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
10283 /* Implement va_arg. */
10286 rs6000_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
10287 gimple_seq
*post_p
)
10289 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
10290 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
10291 int size
, rsize
, n_reg
, sav_ofs
, sav_scale
;
10292 tree lab_false
, lab_over
, addr
;
10294 tree ptrtype
= build_pointer_type_for_mode (type
, ptr_mode
, true);
10298 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
10300 t
= rs6000_gimplify_va_arg (valist
, ptrtype
, pre_p
, post_p
);
10301 return build_va_arg_indirect_ref (t
);
10304 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
10305 earlier version of gcc, with the property that it always applied alignment
10306 adjustments to the va-args (even for zero-sized types). The cheapest way
10307 to deal with this is to replicate the effect of the part of
10308 std_gimplify_va_arg_expr that carries out the align adjust, for the case
10310 We don't need to check for pass-by-reference because of the test above.
10311 We can return a simplifed answer, since we know there's no offset to add. */
10314 && rs6000_darwin64_abi
)
10315 || (DEFAULT_ABI
== ABI_AIX
&& !rs6000_compat_align_parm
))
10316 && integer_zerop (TYPE_SIZE (type
)))
10318 unsigned HOST_WIDE_INT align
, boundary
;
10319 tree valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
10320 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
10321 boundary
= rs6000_function_arg_boundary (TYPE_MODE (type
), type
);
10322 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
10323 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
10324 boundary
/= BITS_PER_UNIT
;
10325 if (boundary
> align
)
10328 /* This updates arg ptr by the amount that would be necessary
10329 to align the zero-sized (but not zero-alignment) item. */
10330 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
10331 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
10332 gimplify_and_add (t
, pre_p
);
10334 t
= fold_convert (sizetype
, valist_tmp
);
10335 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
10336 fold_convert (TREE_TYPE (valist
),
10337 fold_build2 (BIT_AND_EXPR
, sizetype
, t
,
10338 size_int (-boundary
))));
10339 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
10340 gimplify_and_add (t
, pre_p
);
10342 /* Since it is zero-sized there's no increment for the item itself. */
10343 valist_tmp
= fold_convert (build_pointer_type (type
), valist_tmp
);
10344 return build_va_arg_indirect_ref (valist_tmp
);
10347 if (DEFAULT_ABI
!= ABI_V4
)
10349 if (targetm
.calls
.split_complex_arg
&& TREE_CODE (type
) == COMPLEX_TYPE
)
10351 tree elem_type
= TREE_TYPE (type
);
10352 enum machine_mode elem_mode
= TYPE_MODE (elem_type
);
10353 int elem_size
= GET_MODE_SIZE (elem_mode
);
10355 if (elem_size
< UNITS_PER_WORD
)
10357 tree real_part
, imag_part
;
10358 gimple_seq post
= NULL
;
10360 real_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
10362 /* Copy the value into a temporary, lest the formal temporary
10363 be reused out from under us. */
10364 real_part
= get_initialized_tmp_var (real_part
, pre_p
, &post
);
10365 gimple_seq_add_seq (pre_p
, post
);
10367 imag_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
10370 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
10374 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
10377 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
10378 f_fpr
= DECL_CHAIN (f_gpr
);
10379 f_res
= DECL_CHAIN (f_fpr
);
10380 f_ovf
= DECL_CHAIN (f_res
);
10381 f_sav
= DECL_CHAIN (f_ovf
);
10383 valist
= build_va_arg_indirect_ref (valist
);
10384 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
10385 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
10387 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
10389 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
10392 size
= int_size_in_bytes (type
);
10393 rsize
= (size
+ 3) / 4;
10396 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
10397 && ((TARGET_SINGLE_FLOAT
&& TYPE_MODE (type
) == SFmode
)
10398 || (TARGET_DOUBLE_FLOAT
10399 && (TYPE_MODE (type
) == DFmode
10400 || TYPE_MODE (type
) == TFmode
10401 || TYPE_MODE (type
) == SDmode
10402 || TYPE_MODE (type
) == DDmode
10403 || TYPE_MODE (type
) == TDmode
))))
10405 /* FP args go in FP registers, if present. */
10407 n_reg
= (size
+ 7) / 8;
10408 sav_ofs
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4) * 4;
10409 sav_scale
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4);
10410 if (TYPE_MODE (type
) != SFmode
&& TYPE_MODE (type
) != SDmode
)
10415 /* Otherwise into GP registers. */
10424 /* Pull the value out of the saved registers.... */
10427 addr
= create_tmp_var (ptr_type_node
, "addr");
10429 /* AltiVec vectors never go in registers when -mabi=altivec. */
10430 if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
10434 lab_false
= create_artificial_label (input_location
);
10435 lab_over
= create_artificial_label (input_location
);
10437 /* Long long and SPE vectors are aligned in the registers.
10438 As are any other 2 gpr item such as complex int due to a
10439 historical mistake. */
10441 if (n_reg
== 2 && reg
== gpr
)
10444 u
= build2 (BIT_AND_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
10445 build_int_cst (TREE_TYPE (reg
), n_reg
- 1));
10446 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
),
10447 unshare_expr (reg
), u
);
10449 /* _Decimal128 is passed in even/odd fpr pairs; the stored
10450 reg number is 0 for f1, so we want to make it odd. */
10451 else if (reg
== fpr
&& TYPE_MODE (type
) == TDmode
)
10453 t
= build2 (BIT_IOR_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
10454 build_int_cst (TREE_TYPE (reg
), 1));
10455 u
= build2 (MODIFY_EXPR
, void_type_node
, unshare_expr (reg
), t
);
10458 t
= fold_convert (TREE_TYPE (reg
), size_int (8 - n_reg
+ 1));
10459 t
= build2 (GE_EXPR
, boolean_type_node
, u
, t
);
10460 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
10461 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
10462 gimplify_and_add (t
, pre_p
);
10466 t
= fold_build_pointer_plus_hwi (sav
, sav_ofs
);
10468 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
10469 build_int_cst (TREE_TYPE (reg
), n_reg
));
10470 u
= fold_convert (sizetype
, u
);
10471 u
= build2 (MULT_EXPR
, sizetype
, u
, size_int (sav_scale
));
10472 t
= fold_build_pointer_plus (t
, u
);
10474 /* _Decimal32 varargs are located in the second word of the 64-bit
10475 FP register for 32-bit binaries. */
10476 if (!TARGET_POWERPC64
10477 && TARGET_HARD_FLOAT
&& TARGET_FPRS
10478 && TYPE_MODE (type
) == SDmode
)
10479 t
= fold_build_pointer_plus_hwi (t
, size
);
10481 gimplify_assign (addr
, t
, pre_p
);
10483 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
10485 stmt
= gimple_build_label (lab_false
);
10486 gimple_seq_add_stmt (pre_p
, stmt
);
10488 if ((n_reg
== 2 && !regalign
) || n_reg
> 2)
10490 /* Ensure that we don't find any more args in regs.
10491 Alignment has taken care of for special cases. */
10492 gimplify_assign (reg
, build_int_cst (TREE_TYPE (reg
), 8), pre_p
);
10496 /* ... otherwise out of the overflow area. */
10498 /* Care for on-stack alignment if needed. */
10502 t
= fold_build_pointer_plus_hwi (t
, align
- 1);
10503 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
10504 build_int_cst (TREE_TYPE (t
), -align
));
10506 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
10508 gimplify_assign (unshare_expr (addr
), t
, pre_p
);
10510 t
= fold_build_pointer_plus_hwi (t
, size
);
10511 gimplify_assign (unshare_expr (ovf
), t
, pre_p
);
10515 stmt
= gimple_build_label (lab_over
);
10516 gimple_seq_add_stmt (pre_p
, stmt
);
10519 if (STRICT_ALIGNMENT
10520 && (TYPE_ALIGN (type
)
10521 > (unsigned) BITS_PER_UNIT
* (align
< 4 ? 4 : align
)))
10523 /* The value (of type complex double, for example) may not be
10524 aligned in memory in the saved registers, so copy via a
10525 temporary. (This is the same code as used for SPARC.) */
10526 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
10527 tree dest_addr
= build_fold_addr_expr (tmp
);
10529 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
10530 3, dest_addr
, addr
, size_int (rsize
* 4));
10532 gimplify_and_add (copy
, pre_p
);
10536 addr
= fold_convert (ptrtype
, addr
);
10537 return build_va_arg_indirect_ref (addr
);
10543 def_builtin (const char *name
, tree type
, enum rs6000_builtins code
)
10546 unsigned classify
= rs6000_builtin_info
[(int)code
].attr
;
10547 const char *attr_string
= "";
10549 gcc_assert (name
!= NULL
);
10550 gcc_assert (IN_RANGE ((int)code
, 0, (int)RS6000_BUILTIN_COUNT
));
10552 if (rs6000_builtin_decls
[(int)code
])
10553 fatal_error ("internal error: builtin function %s already processed", name
);
10555 rs6000_builtin_decls
[(int)code
] = t
=
10556 add_builtin_function (name
, type
, (int)code
, BUILT_IN_MD
, NULL
, NULL_TREE
);
10558 /* Set any special attributes. */
10559 if ((classify
& RS6000_BTC_CONST
) != 0)
10561 /* const function, function only depends on the inputs. */
10562 TREE_READONLY (t
) = 1;
10563 TREE_NOTHROW (t
) = 1;
10564 attr_string
= ", pure";
10566 else if ((classify
& RS6000_BTC_PURE
) != 0)
10568 /* pure function, function can read global memory, but does not set any
10570 DECL_PURE_P (t
) = 1;
10571 TREE_NOTHROW (t
) = 1;
10572 attr_string
= ", const";
10574 else if ((classify
& RS6000_BTC_FP
) != 0)
10576 /* Function is a math function. If rounding mode is on, then treat the
10577 function as not reading global memory, but it can have arbitrary side
10578 effects. If it is off, then assume the function is a const function.
10579 This mimics the ATTR_MATHFN_FPROUNDING attribute in
10580 builtin-attribute.def that is used for the math functions. */
10581 TREE_NOTHROW (t
) = 1;
10582 if (flag_rounding_math
)
10584 DECL_PURE_P (t
) = 1;
10585 DECL_IS_NOVOPS (t
) = 1;
10586 attr_string
= ", fp, pure";
10590 TREE_READONLY (t
) = 1;
10591 attr_string
= ", fp, const";
10594 else if ((classify
& RS6000_BTC_ATTR_MASK
) != 0)
10595 gcc_unreachable ();
10597 if (TARGET_DEBUG_BUILTIN
)
10598 fprintf (stderr
, "rs6000_builtin, code = %4d, %s%s\n",
10599 (int)code
, name
, attr_string
);
10602 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
10604 #undef RS6000_BUILTIN_1
10605 #undef RS6000_BUILTIN_2
10606 #undef RS6000_BUILTIN_3
10607 #undef RS6000_BUILTIN_A
10608 #undef RS6000_BUILTIN_D
10609 #undef RS6000_BUILTIN_E
10610 #undef RS6000_BUILTIN_H
10611 #undef RS6000_BUILTIN_P
10612 #undef RS6000_BUILTIN_Q
10613 #undef RS6000_BUILTIN_S
10614 #undef RS6000_BUILTIN_X
10616 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
10617 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
10618 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
10619 { MASK, ICODE, NAME, ENUM },
10621 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
10622 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
10623 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
10624 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
10625 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
10626 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
10627 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
10628 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
10630 static const struct builtin_description bdesc_3arg
[] =
10632 #include "rs6000-builtin.def"
10635 /* DST operations: void foo (void *, const int, const char). */
10637 #undef RS6000_BUILTIN_1
10638 #undef RS6000_BUILTIN_2
10639 #undef RS6000_BUILTIN_3
10640 #undef RS6000_BUILTIN_A
10641 #undef RS6000_BUILTIN_D
10642 #undef RS6000_BUILTIN_E
10643 #undef RS6000_BUILTIN_H
10644 #undef RS6000_BUILTIN_P
10645 #undef RS6000_BUILTIN_Q
10646 #undef RS6000_BUILTIN_S
10647 #undef RS6000_BUILTIN_X
10649 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
10650 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
10651 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
10652 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
10653 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
10654 { MASK, ICODE, NAME, ENUM },
10656 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
10657 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
10658 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
10659 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
10660 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
10661 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
10663 static const struct builtin_description bdesc_dst
[] =
10665 #include "rs6000-builtin.def"
10668 /* Simple binary operations: VECc = foo (VECa, VECb). */
10670 #undef RS6000_BUILTIN_1
10671 #undef RS6000_BUILTIN_2
10672 #undef RS6000_BUILTIN_3
10673 #undef RS6000_BUILTIN_A
10674 #undef RS6000_BUILTIN_D
10675 #undef RS6000_BUILTIN_E
10676 #undef RS6000_BUILTIN_H
10677 #undef RS6000_BUILTIN_P
10678 #undef RS6000_BUILTIN_Q
10679 #undef RS6000_BUILTIN_S
10680 #undef RS6000_BUILTIN_X
10682 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
10683 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
10684 { MASK, ICODE, NAME, ENUM },
10686 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
10687 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
10688 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
10689 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
10690 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
10691 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
10692 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
10693 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
10694 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
10696 static const struct builtin_description bdesc_2arg
[] =
10698 #include "rs6000-builtin.def"
10701 #undef RS6000_BUILTIN_1
10702 #undef RS6000_BUILTIN_2
10703 #undef RS6000_BUILTIN_3
10704 #undef RS6000_BUILTIN_A
10705 #undef RS6000_BUILTIN_D
10706 #undef RS6000_BUILTIN_E
10707 #undef RS6000_BUILTIN_H
10708 #undef RS6000_BUILTIN_P
10709 #undef RS6000_BUILTIN_Q
10710 #undef RS6000_BUILTIN_S
10711 #undef RS6000_BUILTIN_X
10713 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
10714 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
10715 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
10716 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
10717 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
10718 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
10719 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
10720 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
10721 { MASK, ICODE, NAME, ENUM },
10723 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
10724 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
10725 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
10727 /* AltiVec predicates. */
10729 static const struct builtin_description bdesc_altivec_preds
[] =
10731 #include "rs6000-builtin.def"
10734 /* SPE predicates. */
10735 #undef RS6000_BUILTIN_1
10736 #undef RS6000_BUILTIN_2
10737 #undef RS6000_BUILTIN_3
10738 #undef RS6000_BUILTIN_A
10739 #undef RS6000_BUILTIN_D
10740 #undef RS6000_BUILTIN_E
10741 #undef RS6000_BUILTIN_H
10742 #undef RS6000_BUILTIN_P
10743 #undef RS6000_BUILTIN_Q
10744 #undef RS6000_BUILTIN_S
10745 #undef RS6000_BUILTIN_X
10747 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
10748 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
10749 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
10750 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
10751 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
10752 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
10753 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
10754 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
10755 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
10756 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
10757 { MASK, ICODE, NAME, ENUM },
10759 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
10761 static const struct builtin_description bdesc_spe_predicates
[] =
10763 #include "rs6000-builtin.def"
10766 /* SPE evsel predicates. */
10767 #undef RS6000_BUILTIN_1
10768 #undef RS6000_BUILTIN_2
10769 #undef RS6000_BUILTIN_3
10770 #undef RS6000_BUILTIN_A
10771 #undef RS6000_BUILTIN_D
10772 #undef RS6000_BUILTIN_E
10773 #undef RS6000_BUILTIN_H
10774 #undef RS6000_BUILTIN_P
10775 #undef RS6000_BUILTIN_Q
10776 #undef RS6000_BUILTIN_S
10777 #undef RS6000_BUILTIN_X
10779 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
10780 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
10781 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
10782 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
10783 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
10784 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
10785 { MASK, ICODE, NAME, ENUM },
10787 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
10788 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
10789 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
10790 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
10791 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
10793 static const struct builtin_description bdesc_spe_evsel
[] =
10795 #include "rs6000-builtin.def"
10798 /* PAIRED predicates. */
10799 #undef RS6000_BUILTIN_1
10800 #undef RS6000_BUILTIN_2
10801 #undef RS6000_BUILTIN_3
10802 #undef RS6000_BUILTIN_A
10803 #undef RS6000_BUILTIN_D
10804 #undef RS6000_BUILTIN_E
10805 #undef RS6000_BUILTIN_H
10806 #undef RS6000_BUILTIN_P
10807 #undef RS6000_BUILTIN_Q
10808 #undef RS6000_BUILTIN_S
10809 #undef RS6000_BUILTIN_X
10811 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
10812 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
10813 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
10814 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
10815 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
10816 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
10817 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
10818 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
10819 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
10820 { MASK, ICODE, NAME, ENUM },
10822 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
10823 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
10825 static const struct builtin_description bdesc_paired_preds
[] =
10827 #include "rs6000-builtin.def"
10830 /* ABS* operations. */
10832 #undef RS6000_BUILTIN_1
10833 #undef RS6000_BUILTIN_2
10834 #undef RS6000_BUILTIN_3
10835 #undef RS6000_BUILTIN_A
10836 #undef RS6000_BUILTIN_D
10837 #undef RS6000_BUILTIN_E
10838 #undef RS6000_BUILTIN_H
10839 #undef RS6000_BUILTIN_P
10840 #undef RS6000_BUILTIN_Q
10841 #undef RS6000_BUILTIN_S
10842 #undef RS6000_BUILTIN_X
10844 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
10845 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
10846 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
10847 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
10848 { MASK, ICODE, NAME, ENUM },
10850 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
10851 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
10852 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
10853 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
10854 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
10855 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
10856 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
10858 static const struct builtin_description bdesc_abs
[] =
10860 #include "rs6000-builtin.def"
10863 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
10866 #undef RS6000_BUILTIN_1
10867 #undef RS6000_BUILTIN_2
10868 #undef RS6000_BUILTIN_3
10869 #undef RS6000_BUILTIN_A
10870 #undef RS6000_BUILTIN_D
10871 #undef RS6000_BUILTIN_E
10872 #undef RS6000_BUILTIN_H
10873 #undef RS6000_BUILTIN_P
10874 #undef RS6000_BUILTIN_Q
10875 #undef RS6000_BUILTIN_S
10876 #undef RS6000_BUILTIN_X
10878 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
10879 { MASK, ICODE, NAME, ENUM },
10881 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
10882 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
10883 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
10884 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
10885 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
10886 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
10887 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
10888 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
10889 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
10890 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
10892 static const struct builtin_description bdesc_1arg
[] =
10894 #include "rs6000-builtin.def"
10897 /* HTM builtins. */
10898 #undef RS6000_BUILTIN_1
10899 #undef RS6000_BUILTIN_2
10900 #undef RS6000_BUILTIN_3
10901 #undef RS6000_BUILTIN_A
10902 #undef RS6000_BUILTIN_D
10903 #undef RS6000_BUILTIN_E
10904 #undef RS6000_BUILTIN_H
10905 #undef RS6000_BUILTIN_P
10906 #undef RS6000_BUILTIN_Q
10907 #undef RS6000_BUILTIN_S
10908 #undef RS6000_BUILTIN_X
10910 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
10911 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
10912 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
10913 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
10914 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
10915 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
10916 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
10917 { MASK, ICODE, NAME, ENUM },
10919 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
10920 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
10921 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
10922 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
10924 static const struct builtin_description bdesc_htm
[] =
10926 #include "rs6000-builtin.def"
10929 #undef RS6000_BUILTIN_1
10930 #undef RS6000_BUILTIN_2
10931 #undef RS6000_BUILTIN_3
10932 #undef RS6000_BUILTIN_A
10933 #undef RS6000_BUILTIN_D
10934 #undef RS6000_BUILTIN_E
10935 #undef RS6000_BUILTIN_H
10936 #undef RS6000_BUILTIN_P
10937 #undef RS6000_BUILTIN_Q
10938 #undef RS6000_BUILTIN_S
10940 /* Return true if a builtin function is overloaded. */
10942 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode
)
10944 return (rs6000_builtin_info
[(int)fncode
].attr
& RS6000_BTC_OVERLOADED
) != 0;
10947 /* Expand an expression EXP that calls a builtin without arguments. */
10949 rs6000_expand_zeroop_builtin (enum insn_code icode
, rtx target
)
10952 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10954 if (icode
== CODE_FOR_nothing
)
10955 /* Builtin not supported on this processor. */
10959 || GET_MODE (target
) != tmode
10960 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10961 target
= gen_reg_rtx (tmode
);
10963 pat
= GEN_FCN (icode
) (target
);
10973 rs6000_expand_unop_builtin (enum insn_code icode
, tree exp
, rtx target
)
10976 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10977 rtx op0
= expand_normal (arg0
);
10978 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10979 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
10981 if (icode
== CODE_FOR_nothing
)
10982 /* Builtin not supported on this processor. */
10985 /* If we got invalid arguments bail out before generating bad rtl. */
10986 if (arg0
== error_mark_node
)
10989 if (icode
== CODE_FOR_altivec_vspltisb
10990 || icode
== CODE_FOR_altivec_vspltish
10991 || icode
== CODE_FOR_altivec_vspltisw
10992 || icode
== CODE_FOR_spe_evsplatfi
10993 || icode
== CODE_FOR_spe_evsplati
)
10995 /* Only allow 5-bit *signed* literals. */
10996 if (GET_CODE (op0
) != CONST_INT
10997 || INTVAL (op0
) > 15
10998 || INTVAL (op0
) < -16)
11000 error ("argument 1 must be a 5-bit signed literal");
11006 || GET_MODE (target
) != tmode
11007 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11008 target
= gen_reg_rtx (tmode
);
11010 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11011 op0
= copy_to_mode_reg (mode0
, op0
);
11013 pat
= GEN_FCN (icode
) (target
, op0
);
11022 altivec_expand_abs_builtin (enum insn_code icode
, tree exp
, rtx target
)
11024 rtx pat
, scratch1
, scratch2
;
11025 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11026 rtx op0
= expand_normal (arg0
);
11027 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11028 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11030 /* If we have invalid arguments, bail out before generating bad rtl. */
11031 if (arg0
== error_mark_node
)
11035 || GET_MODE (target
) != tmode
11036 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11037 target
= gen_reg_rtx (tmode
);
11039 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11040 op0
= copy_to_mode_reg (mode0
, op0
);
11042 scratch1
= gen_reg_rtx (mode0
);
11043 scratch2
= gen_reg_rtx (mode0
);
11045 pat
= GEN_FCN (icode
) (target
, op0
, scratch1
, scratch2
);
11054 rs6000_expand_binop_builtin (enum insn_code icode
, tree exp
, rtx target
)
11057 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11058 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11059 rtx op0
= expand_normal (arg0
);
11060 rtx op1
= expand_normal (arg1
);
11061 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11062 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11063 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
11065 if (icode
== CODE_FOR_nothing
)
11066 /* Builtin not supported on this processor. */
11069 /* If we got invalid arguments bail out before generating bad rtl. */
11070 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11073 if (icode
== CODE_FOR_altivec_vcfux
11074 || icode
== CODE_FOR_altivec_vcfsx
11075 || icode
== CODE_FOR_altivec_vctsxs
11076 || icode
== CODE_FOR_altivec_vctuxs
11077 || icode
== CODE_FOR_altivec_vspltb
11078 || icode
== CODE_FOR_altivec_vsplth
11079 || icode
== CODE_FOR_altivec_vspltw
11080 || icode
== CODE_FOR_spe_evaddiw
11081 || icode
== CODE_FOR_spe_evldd
11082 || icode
== CODE_FOR_spe_evldh
11083 || icode
== CODE_FOR_spe_evldw
11084 || icode
== CODE_FOR_spe_evlhhesplat
11085 || icode
== CODE_FOR_spe_evlhhossplat
11086 || icode
== CODE_FOR_spe_evlhhousplat
11087 || icode
== CODE_FOR_spe_evlwhe
11088 || icode
== CODE_FOR_spe_evlwhos
11089 || icode
== CODE_FOR_spe_evlwhou
11090 || icode
== CODE_FOR_spe_evlwhsplat
11091 || icode
== CODE_FOR_spe_evlwwsplat
11092 || icode
== CODE_FOR_spe_evrlwi
11093 || icode
== CODE_FOR_spe_evslwi
11094 || icode
== CODE_FOR_spe_evsrwis
11095 || icode
== CODE_FOR_spe_evsubifw
11096 || icode
== CODE_FOR_spe_evsrwiu
)
11098 /* Only allow 5-bit unsigned literals. */
11100 if (TREE_CODE (arg1
) != INTEGER_CST
11101 || tree_to_hwi (arg1
) & ~0x1f)
11103 error ("argument 2 must be a 5-bit unsigned literal");
11109 || GET_MODE (target
) != tmode
11110 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11111 target
= gen_reg_rtx (tmode
);
11113 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11114 op0
= copy_to_mode_reg (mode0
, op0
);
11115 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11116 op1
= copy_to_mode_reg (mode1
, op1
);
11118 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
11127 altivec_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
11130 tree cr6_form
= CALL_EXPR_ARG (exp
, 0);
11131 tree arg0
= CALL_EXPR_ARG (exp
, 1);
11132 tree arg1
= CALL_EXPR_ARG (exp
, 2);
11133 rtx op0
= expand_normal (arg0
);
11134 rtx op1
= expand_normal (arg1
);
11135 enum machine_mode tmode
= SImode
;
11136 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11137 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
11140 if (TREE_CODE (cr6_form
) != INTEGER_CST
)
11142 error ("argument 1 of __builtin_altivec_predicate must be a constant");
11146 cr6_form_int
= tree_to_hwi (cr6_form
);
11148 gcc_assert (mode0
== mode1
);
11150 /* If we have invalid arguments, bail out before generating bad rtl. */
11151 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11155 || GET_MODE (target
) != tmode
11156 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11157 target
= gen_reg_rtx (tmode
);
11159 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11160 op0
= copy_to_mode_reg (mode0
, op0
);
11161 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11162 op1
= copy_to_mode_reg (mode1
, op1
);
11164 scratch
= gen_reg_rtx (mode0
);
11166 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
11171 /* The vec_any* and vec_all* predicates use the same opcodes for two
11172 different operations, but the bits in CR6 will be different
11173 depending on what information we want. So we have to play tricks
11174 with CR6 to get the right bits out.
11176 If you think this is disgusting, look at the specs for the
11177 AltiVec predicates. */
11179 switch (cr6_form_int
)
11182 emit_insn (gen_cr6_test_for_zero (target
));
11185 emit_insn (gen_cr6_test_for_zero_reverse (target
));
11188 emit_insn (gen_cr6_test_for_lt (target
));
11191 emit_insn (gen_cr6_test_for_lt_reverse (target
));
11194 error ("argument 1 of __builtin_altivec_predicate is out of range");
11202 paired_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
)
11205 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11206 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11207 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11208 enum machine_mode mode0
= Pmode
;
11209 enum machine_mode mode1
= Pmode
;
11210 rtx op0
= expand_normal (arg0
);
11211 rtx op1
= expand_normal (arg1
);
11213 if (icode
== CODE_FOR_nothing
)
11214 /* Builtin not supported on this processor. */
11217 /* If we got invalid arguments bail out before generating bad rtl. */
11218 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11222 || GET_MODE (target
) != tmode
11223 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11224 target
= gen_reg_rtx (tmode
);
11226 op1
= copy_to_mode_reg (mode1
, op1
);
11228 if (op0
== const0_rtx
)
11230 addr
= gen_rtx_MEM (tmode
, op1
);
11234 op0
= copy_to_mode_reg (mode0
, op0
);
11235 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
11238 pat
= GEN_FCN (icode
) (target
, addr
);
11248 altivec_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
, bool blk
)
11251 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11252 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11253 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11254 enum machine_mode mode0
= Pmode
;
11255 enum machine_mode mode1
= Pmode
;
11256 rtx op0
= expand_normal (arg0
);
11257 rtx op1
= expand_normal (arg1
);
11259 if (icode
== CODE_FOR_nothing
)
11260 /* Builtin not supported on this processor. */
11263 /* If we got invalid arguments bail out before generating bad rtl. */
11264 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11268 || GET_MODE (target
) != tmode
11269 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11270 target
= gen_reg_rtx (tmode
);
11272 op1
= copy_to_mode_reg (mode1
, op1
);
11274 if (op0
== const0_rtx
)
11276 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, op1
);
11280 op0
= copy_to_mode_reg (mode0
, op0
);
11281 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
11284 pat
= GEN_FCN (icode
) (target
, addr
);
11294 spe_expand_stv_builtin (enum insn_code icode
, tree exp
)
11296 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11297 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11298 tree arg2
= CALL_EXPR_ARG (exp
, 2);
11299 rtx op0
= expand_normal (arg0
);
11300 rtx op1
= expand_normal (arg1
);
11301 rtx op2
= expand_normal (arg2
);
11303 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
11304 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
11305 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
11307 /* Invalid arguments. Bail before doing anything stoopid! */
11308 if (arg0
== error_mark_node
11309 || arg1
== error_mark_node
11310 || arg2
== error_mark_node
)
11313 if (! (*insn_data
[icode
].operand
[2].predicate
) (op0
, mode2
))
11314 op0
= copy_to_mode_reg (mode2
, op0
);
11315 if (! (*insn_data
[icode
].operand
[0].predicate
) (op1
, mode0
))
11316 op1
= copy_to_mode_reg (mode0
, op1
);
11317 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
11318 op2
= copy_to_mode_reg (mode1
, op2
);
11320 pat
= GEN_FCN (icode
) (op1
, op2
, op0
);
11327 paired_expand_stv_builtin (enum insn_code icode
, tree exp
)
11329 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11330 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11331 tree arg2
= CALL_EXPR_ARG (exp
, 2);
11332 rtx op0
= expand_normal (arg0
);
11333 rtx op1
= expand_normal (arg1
);
11334 rtx op2
= expand_normal (arg2
);
11336 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11337 enum machine_mode mode1
= Pmode
;
11338 enum machine_mode mode2
= Pmode
;
11340 /* Invalid arguments. Bail before doing anything stoopid! */
11341 if (arg0
== error_mark_node
11342 || arg1
== error_mark_node
11343 || arg2
== error_mark_node
)
11346 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
11347 op0
= copy_to_mode_reg (tmode
, op0
);
11349 op2
= copy_to_mode_reg (mode2
, op2
);
11351 if (op1
== const0_rtx
)
11353 addr
= gen_rtx_MEM (tmode
, op2
);
11357 op1
= copy_to_mode_reg (mode1
, op1
);
11358 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
11361 pat
= GEN_FCN (icode
) (addr
, op0
);
11368 altivec_expand_stv_builtin (enum insn_code icode
, tree exp
)
11370 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11371 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11372 tree arg2
= CALL_EXPR_ARG (exp
, 2);
11373 rtx op0
= expand_normal (arg0
);
11374 rtx op1
= expand_normal (arg1
);
11375 rtx op2
= expand_normal (arg2
);
11377 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11378 enum machine_mode smode
= insn_data
[icode
].operand
[1].mode
;
11379 enum machine_mode mode1
= Pmode
;
11380 enum machine_mode mode2
= Pmode
;
11382 /* Invalid arguments. Bail before doing anything stoopid! */
11383 if (arg0
== error_mark_node
11384 || arg1
== error_mark_node
11385 || arg2
== error_mark_node
)
11388 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, smode
))
11389 op0
= copy_to_mode_reg (smode
, op0
);
11391 op2
= copy_to_mode_reg (mode2
, op2
);
11393 if (op1
== const0_rtx
)
11395 addr
= gen_rtx_MEM (tmode
, op2
);
11399 op1
= copy_to_mode_reg (mode1
, op1
);
11400 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
11403 pat
= GEN_FCN (icode
) (addr
, op0
);
11409 /* Return the appropriate SPR number associated with the given builtin. */
11410 static inline HOST_WIDE_INT
11411 htm_spr_num (enum rs6000_builtins code
)
11413 if (code
== HTM_BUILTIN_GET_TFHAR
11414 || code
== HTM_BUILTIN_SET_TFHAR
)
11416 else if (code
== HTM_BUILTIN_GET_TFIAR
11417 || code
== HTM_BUILTIN_SET_TFIAR
)
11419 else if (code
== HTM_BUILTIN_GET_TEXASR
11420 || code
== HTM_BUILTIN_SET_TEXASR
)
11422 gcc_assert (code
== HTM_BUILTIN_GET_TEXASRU
11423 || code
== HTM_BUILTIN_SET_TEXASRU
);
11424 return TEXASRU_SPR
;
11427 /* Return the appropriate SPR regno associated with the given builtin. */
11428 static inline HOST_WIDE_INT
11429 htm_spr_regno (enum rs6000_builtins code
)
11431 if (code
== HTM_BUILTIN_GET_TFHAR
11432 || code
== HTM_BUILTIN_SET_TFHAR
)
11433 return TFHAR_REGNO
;
11434 else if (code
== HTM_BUILTIN_GET_TFIAR
11435 || code
== HTM_BUILTIN_SET_TFIAR
)
11436 return TFIAR_REGNO
;
11437 gcc_assert (code
== HTM_BUILTIN_GET_TEXASR
11438 || code
== HTM_BUILTIN_SET_TEXASR
11439 || code
== HTM_BUILTIN_GET_TEXASRU
11440 || code
== HTM_BUILTIN_SET_TEXASRU
);
11441 return TEXASR_REGNO
;
11444 /* Return the correct ICODE value depending on whether we are
11445 setting or reading the HTM SPRs. */
11446 static inline enum insn_code
11447 rs6000_htm_spr_icode (bool nonvoid
)
11450 return (TARGET_64BIT
) ? CODE_FOR_htm_mfspr_di
: CODE_FOR_htm_mfspr_si
;
11452 return (TARGET_64BIT
) ? CODE_FOR_htm_mtspr_di
: CODE_FOR_htm_mtspr_si
;
11455 /* Expand the HTM builtin in EXP and store the result in TARGET.
11456 Store true in *EXPANDEDP if we found a builtin to expand. */
11458 htm_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
11460 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11461 bool nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
11462 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
11463 const struct builtin_description
*d
;
11466 *expandedp
= false;
11468 /* Expand the HTM builtins. */
11470 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
11471 if (d
->code
== fcode
)
11473 rtx op
[MAX_HTM_OPERANDS
], pat
;
11476 call_expr_arg_iterator iter
;
11477 unsigned attr
= rs6000_builtin_info
[fcode
].attr
;
11478 enum insn_code icode
= d
->icode
;
11480 if (attr
& RS6000_BTC_SPR
)
11481 icode
= rs6000_htm_spr_icode (nonvoid
);
11485 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11487 || GET_MODE (target
) != tmode
11488 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11489 target
= gen_reg_rtx (tmode
);
11490 op
[nopnds
++] = target
;
11493 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
11495 const struct insn_operand_data
*insn_op
;
11497 if (arg
== error_mark_node
|| nopnds
>= MAX_HTM_OPERANDS
)
11500 insn_op
= &insn_data
[icode
].operand
[nopnds
];
11502 op
[nopnds
] = expand_normal (arg
);
11504 if (!(*insn_op
->predicate
) (op
[nopnds
], insn_op
->mode
))
11506 if (!strcmp (insn_op
->constraint
, "n"))
11508 int arg_num
= (nonvoid
) ? nopnds
: nopnds
+ 1;
11509 if (!CONST_INT_P (op
[nopnds
]))
11510 error ("argument %d must be an unsigned literal", arg_num
);
11512 error ("argument %d is an unsigned literal that is "
11513 "out of range", arg_num
);
11516 op
[nopnds
] = copy_to_mode_reg (insn_op
->mode
, op
[nopnds
]);
11522 /* Handle the builtins for extended mnemonics. These accept
11523 no arguments, but map to builtins that take arguments. */
11526 case HTM_BUILTIN_TENDALL
: /* Alias for: tend. 1 */
11527 case HTM_BUILTIN_TRESUME
: /* Alias for: tsr. 1 */
11528 op
[nopnds
++] = GEN_INT (1);
11529 #ifdef ENABLE_CHECKING
11530 attr
|= RS6000_BTC_UNARY
;
11533 case HTM_BUILTIN_TSUSPEND
: /* Alias for: tsr. 0 */
11534 op
[nopnds
++] = GEN_INT (0);
11535 #ifdef ENABLE_CHECKING
11536 attr
|= RS6000_BTC_UNARY
;
11543 /* If this builtin accesses SPRs, then pass in the appropriate
11544 SPR number and SPR regno as the last two operands. */
11545 if (attr
& RS6000_BTC_SPR
)
11547 op
[nopnds
++] = gen_rtx_CONST_INT (Pmode
, htm_spr_num (fcode
));
11548 op
[nopnds
++] = gen_rtx_REG (Pmode
, htm_spr_regno (fcode
));
11551 #ifdef ENABLE_CHECKING
11552 int expected_nopnds
= 0;
11553 if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_UNARY
)
11554 expected_nopnds
= 1;
11555 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_BINARY
)
11556 expected_nopnds
= 2;
11557 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_TERNARY
)
11558 expected_nopnds
= 3;
11559 if (!(attr
& RS6000_BTC_VOID
))
11560 expected_nopnds
+= 1;
11561 if (attr
& RS6000_BTC_SPR
)
11562 expected_nopnds
+= 2;
11564 gcc_assert (nopnds
== expected_nopnds
&& nopnds
<= MAX_HTM_OPERANDS
);
11570 pat
= GEN_FCN (icode
) (op
[0]);
11573 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
11576 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
11579 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
11582 gcc_unreachable ();
11598 rs6000_expand_ternop_builtin (enum insn_code icode
, tree exp
, rtx target
)
11601 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11602 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11603 tree arg2
= CALL_EXPR_ARG (exp
, 2);
11604 rtx op0
= expand_normal (arg0
);
11605 rtx op1
= expand_normal (arg1
);
11606 rtx op2
= expand_normal (arg2
);
11607 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11608 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11609 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
11610 enum machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
11612 if (icode
== CODE_FOR_nothing
)
11613 /* Builtin not supported on this processor. */
11616 /* If we got invalid arguments bail out before generating bad rtl. */
11617 if (arg0
== error_mark_node
11618 || arg1
== error_mark_node
11619 || arg2
== error_mark_node
)
11622 /* Check and prepare argument depending on the instruction code.
11624 Note that a switch statement instead of the sequence of tests
11625 would be incorrect as many of the CODE_FOR values could be
11626 CODE_FOR_nothing and that would yield multiple alternatives
11627 with identical values. We'd never reach here at runtime in
11629 if (icode
== CODE_FOR_altivec_vsldoi_v4sf
11630 || icode
== CODE_FOR_altivec_vsldoi_v4si
11631 || icode
== CODE_FOR_altivec_vsldoi_v8hi
11632 || icode
== CODE_FOR_altivec_vsldoi_v16qi
)
11634 /* Only allow 4-bit unsigned literals. */
11636 if (TREE_CODE (arg2
) != INTEGER_CST
11637 || tree_to_hwi (arg2
) & ~0xf)
11639 error ("argument 3 must be a 4-bit unsigned literal");
11643 else if (icode
== CODE_FOR_vsx_xxpermdi_v2df
11644 || icode
== CODE_FOR_vsx_xxpermdi_v2di
11645 || icode
== CODE_FOR_vsx_xxsldwi_v16qi
11646 || icode
== CODE_FOR_vsx_xxsldwi_v8hi
11647 || icode
== CODE_FOR_vsx_xxsldwi_v4si
11648 || icode
== CODE_FOR_vsx_xxsldwi_v4sf
11649 || icode
== CODE_FOR_vsx_xxsldwi_v2di
11650 || icode
== CODE_FOR_vsx_xxsldwi_v2df
)
11652 /* Only allow 2-bit unsigned literals. */
11654 if (TREE_CODE (arg2
) != INTEGER_CST
11655 || tree_to_hwi (arg2
) & ~0x3)
11657 error ("argument 3 must be a 2-bit unsigned literal");
11661 else if (icode
== CODE_FOR_vsx_set_v2df
11662 || icode
== CODE_FOR_vsx_set_v2di
)
11664 /* Only allow 1-bit unsigned literals. */
11666 if (TREE_CODE (arg2
) != INTEGER_CST
11667 || tree_to_hwi (arg2
) & ~0x1)
11669 error ("argument 3 must be a 1-bit unsigned literal");
11673 else if (icode
== CODE_FOR_crypto_vshasigmaw
11674 || icode
== CODE_FOR_crypto_vshasigmad
)
11676 /* Check whether the 2nd and 3rd arguments are integer constants and in
11677 range and prepare arguments. */
11679 if (TREE_CODE (arg1
) != INTEGER_CST
11680 || !IN_RANGE (TREE_INT_CST_ELT (arg1
, 0), 0, 1))
11682 error ("argument 2 must be 0 or 1");
11687 if (TREE_CODE (arg2
) != INTEGER_CST
11688 || !IN_RANGE (TREE_INT_CST_ELT (arg2
, 0), 0, 15))
11690 error ("argument 3 must be in the range 0..15");
11696 || GET_MODE (target
) != tmode
11697 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11698 target
= gen_reg_rtx (tmode
);
11700 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11701 op0
= copy_to_mode_reg (mode0
, op0
);
11702 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11703 op1
= copy_to_mode_reg (mode1
, op1
);
11704 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
11705 op2
= copy_to_mode_reg (mode2
, op2
);
11707 if (TARGET_PAIRED_FLOAT
&& icode
== CODE_FOR_selv2sf4
)
11708 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
, CONST0_RTX (SFmode
));
11710 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
11718 /* Expand the lvx builtins. */
11720 altivec_expand_ld_builtin (tree exp
, rtx target
, bool *expandedp
)
11722 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11723 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
11725 enum machine_mode tmode
, mode0
;
11727 enum insn_code icode
;
11731 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi
:
11732 icode
= CODE_FOR_vector_altivec_load_v16qi
;
11734 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi
:
11735 icode
= CODE_FOR_vector_altivec_load_v8hi
;
11737 case ALTIVEC_BUILTIN_LD_INTERNAL_4si
:
11738 icode
= CODE_FOR_vector_altivec_load_v4si
;
11740 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf
:
11741 icode
= CODE_FOR_vector_altivec_load_v4sf
;
11743 case ALTIVEC_BUILTIN_LD_INTERNAL_2df
:
11744 icode
= CODE_FOR_vector_altivec_load_v2df
;
11746 case ALTIVEC_BUILTIN_LD_INTERNAL_2di
:
11747 icode
= CODE_FOR_vector_altivec_load_v2di
;
11750 *expandedp
= false;
11756 arg0
= CALL_EXPR_ARG (exp
, 0);
11757 op0
= expand_normal (arg0
);
11758 tmode
= insn_data
[icode
].operand
[0].mode
;
11759 mode0
= insn_data
[icode
].operand
[1].mode
;
11762 || GET_MODE (target
) != tmode
11763 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11764 target
= gen_reg_rtx (tmode
);
11766 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11767 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
11769 pat
= GEN_FCN (icode
) (target
, op0
);
11776 /* Expand the stvx builtins. */
11778 altivec_expand_st_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
11781 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11782 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
11784 enum machine_mode mode0
, mode1
;
11786 enum insn_code icode
;
11790 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi
:
11791 icode
= CODE_FOR_vector_altivec_store_v16qi
;
11793 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi
:
11794 icode
= CODE_FOR_vector_altivec_store_v8hi
;
11796 case ALTIVEC_BUILTIN_ST_INTERNAL_4si
:
11797 icode
= CODE_FOR_vector_altivec_store_v4si
;
11799 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf
:
11800 icode
= CODE_FOR_vector_altivec_store_v4sf
;
11802 case ALTIVEC_BUILTIN_ST_INTERNAL_2df
:
11803 icode
= CODE_FOR_vector_altivec_store_v2df
;
11805 case ALTIVEC_BUILTIN_ST_INTERNAL_2di
:
11806 icode
= CODE_FOR_vector_altivec_store_v2di
;
11809 *expandedp
= false;
11813 arg0
= CALL_EXPR_ARG (exp
, 0);
11814 arg1
= CALL_EXPR_ARG (exp
, 1);
11815 op0
= expand_normal (arg0
);
11816 op1
= expand_normal (arg1
);
11817 mode0
= insn_data
[icode
].operand
[0].mode
;
11818 mode1
= insn_data
[icode
].operand
[1].mode
;
11820 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
11821 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
11822 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
11823 op1
= copy_to_mode_reg (mode1
, op1
);
11825 pat
= GEN_FCN (icode
) (op0
, op1
);
11833 /* Expand the dst builtins. */
11835 altivec_expand_dst_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
11838 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11839 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
11840 tree arg0
, arg1
, arg2
;
11841 enum machine_mode mode0
, mode1
;
11842 rtx pat
, op0
, op1
, op2
;
11843 const struct builtin_description
*d
;
11846 *expandedp
= false;
11848 /* Handle DST variants. */
11850 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
11851 if (d
->code
== fcode
)
11853 arg0
= CALL_EXPR_ARG (exp
, 0);
11854 arg1
= CALL_EXPR_ARG (exp
, 1);
11855 arg2
= CALL_EXPR_ARG (exp
, 2);
11856 op0
= expand_normal (arg0
);
11857 op1
= expand_normal (arg1
);
11858 op2
= expand_normal (arg2
);
11859 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
11860 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
11862 /* Invalid arguments, bail out before generating bad rtl. */
11863 if (arg0
== error_mark_node
11864 || arg1
== error_mark_node
11865 || arg2
== error_mark_node
)
11870 if (TREE_CODE (arg2
) != INTEGER_CST
11871 || tree_to_hwi (arg2
) & ~0x3)
11873 error ("argument to %qs must be a 2-bit unsigned literal", d
->name
);
11877 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
11878 op0
= copy_to_mode_reg (Pmode
, op0
);
11879 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
11880 op1
= copy_to_mode_reg (mode1
, op1
);
11882 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
11892 /* Expand vec_init builtin. */
11894 altivec_expand_vec_init_builtin (tree type
, tree exp
, rtx target
)
11896 enum machine_mode tmode
= TYPE_MODE (type
);
11897 enum machine_mode inner_mode
= GET_MODE_INNER (tmode
);
11898 int i
, n_elt
= GET_MODE_NUNITS (tmode
);
11899 rtvec v
= rtvec_alloc (n_elt
);
11901 gcc_assert (VECTOR_MODE_P (tmode
));
11902 gcc_assert (n_elt
== call_expr_nargs (exp
));
11904 for (i
= 0; i
< n_elt
; ++i
)
11906 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, i
));
11907 RTVEC_ELT (v
, i
) = gen_lowpart (inner_mode
, x
);
11910 if (!target
|| !register_operand (target
, tmode
))
11911 target
= gen_reg_rtx (tmode
);
11913 rs6000_expand_vector_init (target
, gen_rtx_PARALLEL (tmode
, v
));
11917 /* Return the integer constant in ARG. Constrain it to be in the range
11918 of the subparts of VEC_TYPE; issue an error if not. */
11921 get_element_number (tree vec_type
, tree arg
)
11923 unsigned HOST_WIDE_INT elt
, max
= TYPE_VECTOR_SUBPARTS (vec_type
) - 1;
11925 if (!tree_fits_uhwi_p (arg
)
11926 || (elt
= tree_to_uhwi (arg
), elt
> max
))
11928 error ("selector must be an integer constant in the range 0..%wi", max
);
11935 /* Expand vec_set builtin. */
11937 altivec_expand_vec_set_builtin (tree exp
)
11939 enum machine_mode tmode
, mode1
;
11940 tree arg0
, arg1
, arg2
;
11944 arg0
= CALL_EXPR_ARG (exp
, 0);
11945 arg1
= CALL_EXPR_ARG (exp
, 1);
11946 arg2
= CALL_EXPR_ARG (exp
, 2);
11948 tmode
= TYPE_MODE (TREE_TYPE (arg0
));
11949 mode1
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
11950 gcc_assert (VECTOR_MODE_P (tmode
));
11952 op0
= expand_expr (arg0
, NULL_RTX
, tmode
, EXPAND_NORMAL
);
11953 op1
= expand_expr (arg1
, NULL_RTX
, mode1
, EXPAND_NORMAL
);
11954 elt
= get_element_number (TREE_TYPE (arg0
), arg2
);
11956 if (GET_MODE (op1
) != mode1
&& GET_MODE (op1
) != VOIDmode
)
11957 op1
= convert_modes (mode1
, GET_MODE (op1
), op1
, true);
11959 op0
= force_reg (tmode
, op0
);
11960 op1
= force_reg (mode1
, op1
);
11962 rs6000_expand_vector_set (op0
, op1
, elt
);
11967 /* Expand vec_ext builtin. */
11969 altivec_expand_vec_ext_builtin (tree exp
, rtx target
)
11971 enum machine_mode tmode
, mode0
;
11976 arg0
= CALL_EXPR_ARG (exp
, 0);
11977 arg1
= CALL_EXPR_ARG (exp
, 1);
11979 op0
= expand_normal (arg0
);
11980 elt
= get_element_number (TREE_TYPE (arg0
), arg1
);
11982 tmode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
11983 mode0
= TYPE_MODE (TREE_TYPE (arg0
));
11984 gcc_assert (VECTOR_MODE_P (mode0
));
11986 op0
= force_reg (mode0
, op0
);
11988 if (optimize
|| !target
|| !register_operand (target
, tmode
))
11989 target
= gen_reg_rtx (tmode
);
11991 rs6000_expand_vector_extract (target
, op0
, elt
);
11996 /* Expand the builtin in EXP and store the result in TARGET. Store
11997 true in *EXPANDEDP if we found a builtin to expand. */
11999 altivec_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
12001 const struct builtin_description
*d
;
12003 enum insn_code icode
;
12004 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12007 enum machine_mode tmode
, mode0
;
12008 enum rs6000_builtins fcode
12009 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
12011 if (rs6000_overloaded_builtin_p (fcode
))
12014 error ("unresolved overload for Altivec builtin %qF", fndecl
);
12016 /* Given it is invalid, just generate a normal call. */
12017 return expand_call (exp
, target
, false);
12020 target
= altivec_expand_ld_builtin (exp
, target
, expandedp
);
12024 target
= altivec_expand_st_builtin (exp
, target
, expandedp
);
12028 target
= altivec_expand_dst_builtin (exp
, target
, expandedp
);
12036 case ALTIVEC_BUILTIN_STVX
:
12037 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si
, exp
);
12038 case ALTIVEC_BUILTIN_STVEBX
:
12039 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx
, exp
);
12040 case ALTIVEC_BUILTIN_STVEHX
:
12041 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx
, exp
);
12042 case ALTIVEC_BUILTIN_STVEWX
:
12043 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx
, exp
);
12044 case ALTIVEC_BUILTIN_STVXL
:
12045 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl
, exp
);
12047 case ALTIVEC_BUILTIN_STVLX
:
12048 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx
, exp
);
12049 case ALTIVEC_BUILTIN_STVLXL
:
12050 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl
, exp
);
12051 case ALTIVEC_BUILTIN_STVRX
:
12052 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx
, exp
);
12053 case ALTIVEC_BUILTIN_STVRXL
:
12054 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl
, exp
);
12056 case VSX_BUILTIN_STXVD2X_V2DF
:
12057 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df
, exp
);
12058 case VSX_BUILTIN_STXVD2X_V2DI
:
12059 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di
, exp
);
12060 case VSX_BUILTIN_STXVW4X_V4SF
:
12061 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf
, exp
);
12062 case VSX_BUILTIN_STXVW4X_V4SI
:
12063 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si
, exp
);
12064 case VSX_BUILTIN_STXVW4X_V8HI
:
12065 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi
, exp
);
12066 case VSX_BUILTIN_STXVW4X_V16QI
:
12067 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi
, exp
);
12069 case ALTIVEC_BUILTIN_MFVSCR
:
12070 icode
= CODE_FOR_altivec_mfvscr
;
12071 tmode
= insn_data
[icode
].operand
[0].mode
;
12074 || GET_MODE (target
) != tmode
12075 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12076 target
= gen_reg_rtx (tmode
);
12078 pat
= GEN_FCN (icode
) (target
);
12084 case ALTIVEC_BUILTIN_MTVSCR
:
12085 icode
= CODE_FOR_altivec_mtvscr
;
12086 arg0
= CALL_EXPR_ARG (exp
, 0);
12087 op0
= expand_normal (arg0
);
12088 mode0
= insn_data
[icode
].operand
[0].mode
;
12090 /* If we got invalid arguments bail out before generating bad rtl. */
12091 if (arg0
== error_mark_node
)
12094 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
12095 op0
= copy_to_mode_reg (mode0
, op0
);
12097 pat
= GEN_FCN (icode
) (op0
);
12102 case ALTIVEC_BUILTIN_DSSALL
:
12103 emit_insn (gen_altivec_dssall ());
12106 case ALTIVEC_BUILTIN_DSS
:
12107 icode
= CODE_FOR_altivec_dss
;
12108 arg0
= CALL_EXPR_ARG (exp
, 0);
12110 op0
= expand_normal (arg0
);
12111 mode0
= insn_data
[icode
].operand
[0].mode
;
12113 /* If we got invalid arguments bail out before generating bad rtl. */
12114 if (arg0
== error_mark_node
)
12117 if (TREE_CODE (arg0
) != INTEGER_CST
12118 || tree_to_hwi (arg0
) & ~0x3)
12120 error ("argument to dss must be a 2-bit unsigned literal");
12124 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
12125 op0
= copy_to_mode_reg (mode0
, op0
);
12127 emit_insn (gen_altivec_dss (op0
));
12130 case ALTIVEC_BUILTIN_VEC_INIT_V4SI
:
12131 case ALTIVEC_BUILTIN_VEC_INIT_V8HI
:
12132 case ALTIVEC_BUILTIN_VEC_INIT_V16QI
:
12133 case ALTIVEC_BUILTIN_VEC_INIT_V4SF
:
12134 case VSX_BUILTIN_VEC_INIT_V2DF
:
12135 case VSX_BUILTIN_VEC_INIT_V2DI
:
12136 return altivec_expand_vec_init_builtin (TREE_TYPE (exp
), exp
, target
);
12138 case ALTIVEC_BUILTIN_VEC_SET_V4SI
:
12139 case ALTIVEC_BUILTIN_VEC_SET_V8HI
:
12140 case ALTIVEC_BUILTIN_VEC_SET_V16QI
:
12141 case ALTIVEC_BUILTIN_VEC_SET_V4SF
:
12142 case VSX_BUILTIN_VEC_SET_V2DF
:
12143 case VSX_BUILTIN_VEC_SET_V2DI
:
12144 return altivec_expand_vec_set_builtin (exp
);
12146 case ALTIVEC_BUILTIN_VEC_EXT_V4SI
:
12147 case ALTIVEC_BUILTIN_VEC_EXT_V8HI
:
12148 case ALTIVEC_BUILTIN_VEC_EXT_V16QI
:
12149 case ALTIVEC_BUILTIN_VEC_EXT_V4SF
:
12150 case VSX_BUILTIN_VEC_EXT_V2DF
:
12151 case VSX_BUILTIN_VEC_EXT_V2DI
:
12152 return altivec_expand_vec_ext_builtin (exp
, target
);
12156 /* Fall through. */
12159 /* Expand abs* operations. */
12161 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
12162 if (d
->code
== fcode
)
12163 return altivec_expand_abs_builtin (d
->icode
, exp
, target
);
12165 /* Expand the AltiVec predicates. */
12166 d
= bdesc_altivec_preds
;
12167 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
12168 if (d
->code
== fcode
)
12169 return altivec_expand_predicate_builtin (d
->icode
, exp
, target
);
12171 /* LV* are funky. We initialized them differently. */
12174 case ALTIVEC_BUILTIN_LVSL
:
12175 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl
,
12176 exp
, target
, false);
12177 case ALTIVEC_BUILTIN_LVSR
:
12178 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr
,
12179 exp
, target
, false);
12180 case ALTIVEC_BUILTIN_LVEBX
:
12181 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx
,
12182 exp
, target
, false);
12183 case ALTIVEC_BUILTIN_LVEHX
:
12184 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx
,
12185 exp
, target
, false);
12186 case ALTIVEC_BUILTIN_LVEWX
:
12187 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx
,
12188 exp
, target
, false);
12189 case ALTIVEC_BUILTIN_LVXL
:
12190 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl
,
12191 exp
, target
, false);
12192 case ALTIVEC_BUILTIN_LVX
:
12193 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si
,
12194 exp
, target
, false);
12195 case ALTIVEC_BUILTIN_LVLX
:
12196 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx
,
12197 exp
, target
, true);
12198 case ALTIVEC_BUILTIN_LVLXL
:
12199 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl
,
12200 exp
, target
, true);
12201 case ALTIVEC_BUILTIN_LVRX
:
12202 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx
,
12203 exp
, target
, true);
12204 case ALTIVEC_BUILTIN_LVRXL
:
12205 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl
,
12206 exp
, target
, true);
12207 case VSX_BUILTIN_LXVD2X_V2DF
:
12208 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df
,
12209 exp
, target
, false);
12210 case VSX_BUILTIN_LXVD2X_V2DI
:
12211 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di
,
12212 exp
, target
, false);
12213 case VSX_BUILTIN_LXVW4X_V4SF
:
12214 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf
,
12215 exp
, target
, false);
12216 case VSX_BUILTIN_LXVW4X_V4SI
:
12217 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si
,
12218 exp
, target
, false);
12219 case VSX_BUILTIN_LXVW4X_V8HI
:
12220 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi
,
12221 exp
, target
, false);
12222 case VSX_BUILTIN_LXVW4X_V16QI
:
12223 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi
,
12224 exp
, target
, false);
12228 /* Fall through. */
12231 *expandedp
= false;
12235 /* Expand the builtin in EXP and store the result in TARGET. Store
12236 true in *EXPANDEDP if we found a builtin to expand. */
12238 paired_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
12240 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12241 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
12242 const struct builtin_description
*d
;
12249 case PAIRED_BUILTIN_STX
:
12250 return paired_expand_stv_builtin (CODE_FOR_paired_stx
, exp
);
12251 case PAIRED_BUILTIN_LX
:
12252 return paired_expand_lv_builtin (CODE_FOR_paired_lx
, exp
, target
);
12255 /* Fall through. */
12258 /* Expand the paired predicates. */
12259 d
= bdesc_paired_preds
;
12260 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); i
++, d
++)
12261 if (d
->code
== fcode
)
12262 return paired_expand_predicate_builtin (d
->icode
, exp
, target
);
12264 *expandedp
= false;
12268 /* Binops that need to be initialized manually, but can be expanded
12269 automagically by rs6000_expand_binop_builtin. */
12270 static const struct builtin_description bdesc_2arg_spe
[] =
12272 { RS6000_BTM_SPE
, CODE_FOR_spe_evlddx
, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX
},
12273 { RS6000_BTM_SPE
, CODE_FOR_spe_evldwx
, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX
},
12274 { RS6000_BTM_SPE
, CODE_FOR_spe_evldhx
, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX
},
12275 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhex
, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX
},
12276 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhoux
, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX
},
12277 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhosx
, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX
},
12278 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplatx
, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX
},
12279 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplatx
, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX
},
12280 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplatx
, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX
},
12281 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplatx
, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX
},
12282 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplatx
, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX
},
12283 { RS6000_BTM_SPE
, CODE_FOR_spe_evldd
, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD
},
12284 { RS6000_BTM_SPE
, CODE_FOR_spe_evldw
, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW
},
12285 { RS6000_BTM_SPE
, CODE_FOR_spe_evldh
, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH
},
12286 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhe
, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE
},
12287 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhou
, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU
},
12288 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhos
, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS
},
12289 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplat
, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT
},
12290 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplat
, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT
},
12291 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplat
, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT
},
12292 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplat
, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT
},
12293 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplat
, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT
}
12296 /* Expand the builtin in EXP and store the result in TARGET. Store
12297 true in *EXPANDEDP if we found a builtin to expand.
12299 This expands the SPE builtins that are not simple unary and binary
12302 spe_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
12304 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12306 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
12307 enum insn_code icode
;
12308 enum machine_mode tmode
, mode0
;
12310 const struct builtin_description
*d
;
12315 /* Syntax check for a 5-bit unsigned immediate. */
12318 case SPE_BUILTIN_EVSTDD
:
12319 case SPE_BUILTIN_EVSTDH
:
12320 case SPE_BUILTIN_EVSTDW
:
12321 case SPE_BUILTIN_EVSTWHE
:
12322 case SPE_BUILTIN_EVSTWHO
:
12323 case SPE_BUILTIN_EVSTWWE
:
12324 case SPE_BUILTIN_EVSTWWO
:
12325 arg1
= CALL_EXPR_ARG (exp
, 2);
12326 if (TREE_CODE (arg1
) != INTEGER_CST
12327 || tree_to_hwi (arg1
) & ~0x1f)
12329 error ("argument 2 must be a 5-bit unsigned literal");
12337 /* The evsplat*i instructions are not quite generic. */
12340 case SPE_BUILTIN_EVSPLATFI
:
12341 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi
,
12343 case SPE_BUILTIN_EVSPLATI
:
12344 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati
,
12350 d
= bdesc_2arg_spe
;
12351 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg_spe
); ++i
, ++d
)
12352 if (d
->code
== fcode
)
12353 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
12355 d
= bdesc_spe_predicates
;
12356 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, ++d
)
12357 if (d
->code
== fcode
)
12358 return spe_expand_predicate_builtin (d
->icode
, exp
, target
);
12360 d
= bdesc_spe_evsel
;
12361 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, ++d
)
12362 if (d
->code
== fcode
)
12363 return spe_expand_evsel_builtin (d
->icode
, exp
, target
);
12367 case SPE_BUILTIN_EVSTDDX
:
12368 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx
, exp
);
12369 case SPE_BUILTIN_EVSTDHX
:
12370 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx
, exp
);
12371 case SPE_BUILTIN_EVSTDWX
:
12372 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx
, exp
);
12373 case SPE_BUILTIN_EVSTWHEX
:
12374 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex
, exp
);
12375 case SPE_BUILTIN_EVSTWHOX
:
12376 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox
, exp
);
12377 case SPE_BUILTIN_EVSTWWEX
:
12378 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex
, exp
);
12379 case SPE_BUILTIN_EVSTWWOX
:
12380 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox
, exp
);
12381 case SPE_BUILTIN_EVSTDD
:
12382 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd
, exp
);
12383 case SPE_BUILTIN_EVSTDH
:
12384 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh
, exp
);
12385 case SPE_BUILTIN_EVSTDW
:
12386 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw
, exp
);
12387 case SPE_BUILTIN_EVSTWHE
:
12388 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe
, exp
);
12389 case SPE_BUILTIN_EVSTWHO
:
12390 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho
, exp
);
12391 case SPE_BUILTIN_EVSTWWE
:
12392 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe
, exp
);
12393 case SPE_BUILTIN_EVSTWWO
:
12394 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo
, exp
);
12395 case SPE_BUILTIN_MFSPEFSCR
:
12396 icode
= CODE_FOR_spe_mfspefscr
;
12397 tmode
= insn_data
[icode
].operand
[0].mode
;
12400 || GET_MODE (target
) != tmode
12401 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12402 target
= gen_reg_rtx (tmode
);
12404 pat
= GEN_FCN (icode
) (target
);
12409 case SPE_BUILTIN_MTSPEFSCR
:
12410 icode
= CODE_FOR_spe_mtspefscr
;
12411 arg0
= CALL_EXPR_ARG (exp
, 0);
12412 op0
= expand_normal (arg0
);
12413 mode0
= insn_data
[icode
].operand
[0].mode
;
12415 if (arg0
== error_mark_node
)
12418 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
12419 op0
= copy_to_mode_reg (mode0
, op0
);
12421 pat
= GEN_FCN (icode
) (op0
);
12429 *expandedp
= false;
12434 paired_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
12436 rtx pat
, scratch
, tmp
;
12437 tree form
= CALL_EXPR_ARG (exp
, 0);
12438 tree arg0
= CALL_EXPR_ARG (exp
, 1);
12439 tree arg1
= CALL_EXPR_ARG (exp
, 2);
12440 rtx op0
= expand_normal (arg0
);
12441 rtx op1
= expand_normal (arg1
);
12442 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12443 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12445 enum rtx_code code
;
12447 if (TREE_CODE (form
) != INTEGER_CST
)
12449 error ("argument 1 of __builtin_paired_predicate must be a constant");
12453 form_int
= tree_to_hwi (form
);
12455 gcc_assert (mode0
== mode1
);
12457 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
12461 || GET_MODE (target
) != SImode
12462 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
12463 target
= gen_reg_rtx (SImode
);
12464 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12465 op0
= copy_to_mode_reg (mode0
, op0
);
12466 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12467 op1
= copy_to_mode_reg (mode1
, op1
);
12469 scratch
= gen_reg_rtx (CCFPmode
);
12471 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
12493 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
12496 error ("argument 1 of __builtin_paired_predicate is out of range");
12500 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
12501 emit_move_insn (target
, tmp
);
12506 spe_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
12508 rtx pat
, scratch
, tmp
;
12509 tree form
= CALL_EXPR_ARG (exp
, 0);
12510 tree arg0
= CALL_EXPR_ARG (exp
, 1);
12511 tree arg1
= CALL_EXPR_ARG (exp
, 2);
12512 rtx op0
= expand_normal (arg0
);
12513 rtx op1
= expand_normal (arg1
);
12514 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12515 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12517 enum rtx_code code
;
12519 if (TREE_CODE (form
) != INTEGER_CST
)
12521 error ("argument 1 of __builtin_spe_predicate must be a constant");
12525 form_int
= tree_to_hwi (form
);
12527 gcc_assert (mode0
== mode1
);
12529 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
12533 || GET_MODE (target
) != SImode
12534 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
12535 target
= gen_reg_rtx (SImode
);
12537 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12538 op0
= copy_to_mode_reg (mode0
, op0
);
12539 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12540 op1
= copy_to_mode_reg (mode1
, op1
);
12542 scratch
= gen_reg_rtx (CCmode
);
12544 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
12549 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
12550 _lower_. We use one compare, but look in different bits of the
12551 CR for each variant.
12553 There are 2 elements in each SPE simd type (upper/lower). The CR
12554 bits are set as follows:
12556 BIT0 | BIT 1 | BIT 2 | BIT 3
12557 U | L | (U | L) | (U & L)
12559 So, for an "all" relationship, BIT 3 would be set.
12560 For an "any" relationship, BIT 2 would be set. Etc.
12562 Following traditional nomenclature, these bits map to:
12564 BIT0 | BIT 1 | BIT 2 | BIT 3
12567 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
12572 /* All variant. OV bit. */
12574 /* We need to get to the OV bit, which is the ORDERED bit. We
12575 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
12576 that's ugly and will make validate_condition_mode die.
12577 So let's just use another pattern. */
12578 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
12580 /* Any variant. EQ bit. */
12584 /* Upper variant. LT bit. */
12588 /* Lower variant. GT bit. */
12593 error ("argument 1 of __builtin_spe_predicate is out of range");
12597 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
12598 emit_move_insn (target
, tmp
);
12603 /* The evsel builtins look like this:
12605 e = __builtin_spe_evsel_OP (a, b, c, d);
12607 and work like this:
12609 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
12610 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
12614 spe_expand_evsel_builtin (enum insn_code icode
, tree exp
, rtx target
)
12617 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12618 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12619 tree arg2
= CALL_EXPR_ARG (exp
, 2);
12620 tree arg3
= CALL_EXPR_ARG (exp
, 3);
12621 rtx op0
= expand_normal (arg0
);
12622 rtx op1
= expand_normal (arg1
);
12623 rtx op2
= expand_normal (arg2
);
12624 rtx op3
= expand_normal (arg3
);
12625 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12626 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12628 gcc_assert (mode0
== mode1
);
12630 if (arg0
== error_mark_node
|| arg1
== error_mark_node
12631 || arg2
== error_mark_node
|| arg3
== error_mark_node
)
12635 || GET_MODE (target
) != mode0
12636 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode0
))
12637 target
= gen_reg_rtx (mode0
);
12639 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12640 op0
= copy_to_mode_reg (mode0
, op0
);
12641 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
12642 op1
= copy_to_mode_reg (mode0
, op1
);
12643 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
12644 op2
= copy_to_mode_reg (mode0
, op2
);
12645 if (! (*insn_data
[icode
].operand
[1].predicate
) (op3
, mode1
))
12646 op3
= copy_to_mode_reg (mode0
, op3
);
12648 /* Generate the compare. */
12649 scratch
= gen_reg_rtx (CCmode
);
12650 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
12655 if (mode0
== V2SImode
)
12656 emit_insn (gen_spe_evsel (target
, op2
, op3
, scratch
));
12658 emit_insn (gen_spe_evsel_fs (target
, op2
, op3
, scratch
));
12663 /* Raise an error message for a builtin function that is called without the
12664 appropriate target options being set. */
12667 rs6000_invalid_builtin (enum rs6000_builtins fncode
)
12669 size_t uns_fncode
= (size_t)fncode
;
12670 const char *name
= rs6000_builtin_info
[uns_fncode
].name
;
12671 HOST_WIDE_INT fnmask
= rs6000_builtin_info
[uns_fncode
].mask
;
12673 gcc_assert (name
!= NULL
);
12674 if ((fnmask
& RS6000_BTM_CELL
) != 0)
12675 error ("Builtin function %s is only valid for the cell processor", name
);
12676 else if ((fnmask
& RS6000_BTM_VSX
) != 0)
12677 error ("Builtin function %s requires the -mvsx option", name
);
12678 else if ((fnmask
& RS6000_BTM_HTM
) != 0)
12679 error ("Builtin function %s requires the -mhtm option", name
);
12680 else if ((fnmask
& RS6000_BTM_ALTIVEC
) != 0)
12681 error ("Builtin function %s requires the -maltivec option", name
);
12682 else if ((fnmask
& RS6000_BTM_PAIRED
) != 0)
12683 error ("Builtin function %s requires the -mpaired option", name
);
12684 else if ((fnmask
& RS6000_BTM_SPE
) != 0)
12685 error ("Builtin function %s requires the -mspe option", name
);
12687 error ("Builtin function %s is not supported with the current options",
12691 /* Expand an expression EXP that calls a built-in function,
12692 with result going to TARGET if that's convenient
12693 (and in mode MODE if that's convenient).
12694 SUBTARGET may be used as the target for computing one of EXP's operands.
12695 IGNORE is nonzero if the value is to be ignored. */
12698 rs6000_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
12699 enum machine_mode mode ATTRIBUTE_UNUSED
,
12700 int ignore ATTRIBUTE_UNUSED
)
12702 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12703 enum rs6000_builtins fcode
12704 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
12705 size_t uns_fcode
= (size_t)fcode
;
12706 const struct builtin_description
*d
;
12710 HOST_WIDE_INT mask
= rs6000_builtin_info
[uns_fcode
].mask
;
12711 bool func_valid_p
= ((rs6000_builtin_mask
& mask
) == mask
);
12713 if (TARGET_DEBUG_BUILTIN
)
12715 enum insn_code icode
= rs6000_builtin_info
[uns_fcode
].icode
;
12716 const char *name1
= rs6000_builtin_info
[uns_fcode
].name
;
12717 const char *name2
= ((icode
!= CODE_FOR_nothing
)
12718 ? get_insn_name ((int)icode
)
12722 switch (rs6000_builtin_info
[uns_fcode
].attr
& RS6000_BTC_TYPE_MASK
)
12724 default: name3
= "unknown"; break;
12725 case RS6000_BTC_SPECIAL
: name3
= "special"; break;
12726 case RS6000_BTC_UNARY
: name3
= "unary"; break;
12727 case RS6000_BTC_BINARY
: name3
= "binary"; break;
12728 case RS6000_BTC_TERNARY
: name3
= "ternary"; break;
12729 case RS6000_BTC_PREDICATE
: name3
= "predicate"; break;
12730 case RS6000_BTC_ABS
: name3
= "abs"; break;
12731 case RS6000_BTC_EVSEL
: name3
= "evsel"; break;
12732 case RS6000_BTC_DST
: name3
= "dst"; break;
12737 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
12738 (name1
) ? name1
: "---", fcode
,
12739 (name2
) ? name2
: "---", (int)icode
,
12741 func_valid_p
? "" : ", not valid");
12746 rs6000_invalid_builtin (fcode
);
12748 /* Given it is invalid, just generate a normal call. */
12749 return expand_call (exp
, target
, ignore
);
12754 case RS6000_BUILTIN_RECIP
:
12755 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3
, exp
, target
);
12757 case RS6000_BUILTIN_RECIPF
:
12758 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3
, exp
, target
);
12760 case RS6000_BUILTIN_RSQRTF
:
12761 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2
, exp
, target
);
12763 case RS6000_BUILTIN_RSQRT
:
12764 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2
, exp
, target
);
12766 case POWER7_BUILTIN_BPERMD
:
12767 return rs6000_expand_binop_builtin (((TARGET_64BIT
)
12768 ? CODE_FOR_bpermd_di
12769 : CODE_FOR_bpermd_si
), exp
, target
);
12771 case RS6000_BUILTIN_GET_TB
:
12772 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase
,
12775 case RS6000_BUILTIN_MFTB
:
12776 return rs6000_expand_zeroop_builtin (((TARGET_64BIT
)
12777 ? CODE_FOR_rs6000_mftb_di
12778 : CODE_FOR_rs6000_mftb_si
),
12781 case ALTIVEC_BUILTIN_MASK_FOR_LOAD
:
12782 case ALTIVEC_BUILTIN_MASK_FOR_STORE
:
12784 int icode
= (BYTES_BIG_ENDIAN
? (int) CODE_FOR_altivec_lvsr
12785 : (int) CODE_FOR_altivec_lvsl
);
12786 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12787 enum machine_mode mode
= insn_data
[icode
].operand
[1].mode
;
12791 gcc_assert (TARGET_ALTIVEC
);
12793 arg
= CALL_EXPR_ARG (exp
, 0);
12794 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg
)));
12795 op
= expand_expr (arg
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
12796 addr
= memory_address (mode
, op
);
12797 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
12801 /* For the load case need to negate the address. */
12802 op
= gen_reg_rtx (GET_MODE (addr
));
12803 emit_insn (gen_rtx_SET (VOIDmode
, op
,
12804 gen_rtx_NEG (GET_MODE (addr
), addr
)));
12806 op
= gen_rtx_MEM (mode
, op
);
12809 || GET_MODE (target
) != tmode
12810 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12811 target
= gen_reg_rtx (tmode
);
12813 /*pat = gen_altivec_lvsr (target, op);*/
12814 pat
= GEN_FCN (icode
) (target
, op
);
12822 case ALTIVEC_BUILTIN_VCFUX
:
12823 case ALTIVEC_BUILTIN_VCFSX
:
12824 case ALTIVEC_BUILTIN_VCTUXS
:
12825 case ALTIVEC_BUILTIN_VCTSXS
:
12826 /* FIXME: There's got to be a nicer way to handle this case than
12827 constructing a new CALL_EXPR. */
12828 if (call_expr_nargs (exp
) == 1)
12830 exp
= build_call_nary (TREE_TYPE (exp
), CALL_EXPR_FN (exp
),
12831 2, CALL_EXPR_ARG (exp
, 0), integer_zero_node
);
12839 if (TARGET_ALTIVEC
)
12841 ret
= altivec_expand_builtin (exp
, target
, &success
);
12848 ret
= spe_expand_builtin (exp
, target
, &success
);
12853 if (TARGET_PAIRED_FLOAT
)
12855 ret
= paired_expand_builtin (exp
, target
, &success
);
12862 ret
= htm_expand_builtin (exp
, target
, &success
);
12868 gcc_assert (TARGET_ALTIVEC
|| TARGET_VSX
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
);
12870 /* Handle simple unary operations. */
12872 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
12873 if (d
->code
== fcode
)
12874 return rs6000_expand_unop_builtin (d
->icode
, exp
, target
);
12876 /* Handle simple binary operations. */
12878 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12879 if (d
->code
== fcode
)
12880 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
12882 /* Handle simple ternary operations. */
12884 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
12885 if (d
->code
== fcode
)
12886 return rs6000_expand_ternop_builtin (d
->icode
, exp
, target
);
12888 gcc_unreachable ();
12892 rs6000_init_builtins (void)
12896 enum machine_mode mode
;
12898 if (TARGET_DEBUG_BUILTIN
)
12899 fprintf (stderr
, "rs6000_init_builtins%s%s%s%s\n",
12900 (TARGET_PAIRED_FLOAT
) ? ", paired" : "",
12901 (TARGET_SPE
) ? ", spe" : "",
12902 (TARGET_ALTIVEC
) ? ", altivec" : "",
12903 (TARGET_VSX
) ? ", vsx" : "");
12905 V2SI_type_node
= build_vector_type (intSI_type_node
, 2);
12906 V2SF_type_node
= build_vector_type (float_type_node
, 2);
12907 V2DI_type_node
= build_vector_type (intDI_type_node
, 2);
12908 V2DF_type_node
= build_vector_type (double_type_node
, 2);
12909 V4HI_type_node
= build_vector_type (intHI_type_node
, 4);
12910 V4SI_type_node
= build_vector_type (intSI_type_node
, 4);
12911 V4SF_type_node
= build_vector_type (float_type_node
, 4);
12912 V8HI_type_node
= build_vector_type (intHI_type_node
, 8);
12913 V16QI_type_node
= build_vector_type (intQI_type_node
, 16);
12915 unsigned_V16QI_type_node
= build_vector_type (unsigned_intQI_type_node
, 16);
12916 unsigned_V8HI_type_node
= build_vector_type (unsigned_intHI_type_node
, 8);
12917 unsigned_V4SI_type_node
= build_vector_type (unsigned_intSI_type_node
, 4);
12918 unsigned_V2DI_type_node
= build_vector_type (unsigned_intDI_type_node
, 2);
12920 opaque_V2SF_type_node
= build_opaque_vector_type (float_type_node
, 2);
12921 opaque_V2SI_type_node
= build_opaque_vector_type (intSI_type_node
, 2);
12922 opaque_p_V2SI_type_node
= build_pointer_type (opaque_V2SI_type_node
);
12923 opaque_V4SI_type_node
= build_opaque_vector_type (intSI_type_node
, 4);
12925 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
12926 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
12927 'vector unsigned short'. */
12929 bool_char_type_node
= build_distinct_type_copy (unsigned_intQI_type_node
);
12930 bool_short_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
12931 bool_int_type_node
= build_distinct_type_copy (unsigned_intSI_type_node
);
12932 bool_long_type_node
= build_distinct_type_copy (unsigned_intDI_type_node
);
12933 pixel_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
12935 long_integer_type_internal_node
= long_integer_type_node
;
12936 long_unsigned_type_internal_node
= long_unsigned_type_node
;
12937 long_long_integer_type_internal_node
= long_long_integer_type_node
;
12938 long_long_unsigned_type_internal_node
= long_long_unsigned_type_node
;
12939 intQI_type_internal_node
= intQI_type_node
;
12940 uintQI_type_internal_node
= unsigned_intQI_type_node
;
12941 intHI_type_internal_node
= intHI_type_node
;
12942 uintHI_type_internal_node
= unsigned_intHI_type_node
;
12943 intSI_type_internal_node
= intSI_type_node
;
12944 uintSI_type_internal_node
= unsigned_intSI_type_node
;
12945 intDI_type_internal_node
= intDI_type_node
;
12946 uintDI_type_internal_node
= unsigned_intDI_type_node
;
12947 float_type_internal_node
= float_type_node
;
12948 double_type_internal_node
= double_type_node
;
12949 void_type_internal_node
= void_type_node
;
12951 /* Initialize the modes for builtin_function_type, mapping a machine mode to
12953 builtin_mode_to_type
[QImode
][0] = integer_type_node
;
12954 builtin_mode_to_type
[HImode
][0] = integer_type_node
;
12955 builtin_mode_to_type
[SImode
][0] = intSI_type_node
;
12956 builtin_mode_to_type
[SImode
][1] = unsigned_intSI_type_node
;
12957 builtin_mode_to_type
[DImode
][0] = intDI_type_node
;
12958 builtin_mode_to_type
[DImode
][1] = unsigned_intDI_type_node
;
12959 builtin_mode_to_type
[SFmode
][0] = float_type_node
;
12960 builtin_mode_to_type
[DFmode
][0] = double_type_node
;
12961 builtin_mode_to_type
[V2SImode
][0] = V2SI_type_node
;
12962 builtin_mode_to_type
[V2SFmode
][0] = V2SF_type_node
;
12963 builtin_mode_to_type
[V2DImode
][0] = V2DI_type_node
;
12964 builtin_mode_to_type
[V2DImode
][1] = unsigned_V2DI_type_node
;
12965 builtin_mode_to_type
[V2DFmode
][0] = V2DF_type_node
;
12966 builtin_mode_to_type
[V4HImode
][0] = V4HI_type_node
;
12967 builtin_mode_to_type
[V4SImode
][0] = V4SI_type_node
;
12968 builtin_mode_to_type
[V4SImode
][1] = unsigned_V4SI_type_node
;
12969 builtin_mode_to_type
[V4SFmode
][0] = V4SF_type_node
;
12970 builtin_mode_to_type
[V8HImode
][0] = V8HI_type_node
;
12971 builtin_mode_to_type
[V8HImode
][1] = unsigned_V8HI_type_node
;
12972 builtin_mode_to_type
[V16QImode
][0] = V16QI_type_node
;
12973 builtin_mode_to_type
[V16QImode
][1] = unsigned_V16QI_type_node
;
12975 tdecl
= add_builtin_type ("__bool char", bool_char_type_node
);
12976 TYPE_NAME (bool_char_type_node
) = tdecl
;
12978 tdecl
= add_builtin_type ("__bool short", bool_short_type_node
);
12979 TYPE_NAME (bool_short_type_node
) = tdecl
;
12981 tdecl
= add_builtin_type ("__bool int", bool_int_type_node
);
12982 TYPE_NAME (bool_int_type_node
) = tdecl
;
12984 tdecl
= add_builtin_type ("__pixel", pixel_type_node
);
12985 TYPE_NAME (pixel_type_node
) = tdecl
;
12987 bool_V16QI_type_node
= build_vector_type (bool_char_type_node
, 16);
12988 bool_V8HI_type_node
= build_vector_type (bool_short_type_node
, 8);
12989 bool_V4SI_type_node
= build_vector_type (bool_int_type_node
, 4);
12990 bool_V2DI_type_node
= build_vector_type (bool_long_type_node
, 2);
12991 pixel_V8HI_type_node
= build_vector_type (pixel_type_node
, 8);
12993 tdecl
= add_builtin_type ("__vector unsigned char", unsigned_V16QI_type_node
);
12994 TYPE_NAME (unsigned_V16QI_type_node
) = tdecl
;
12996 tdecl
= add_builtin_type ("__vector signed char", V16QI_type_node
);
12997 TYPE_NAME (V16QI_type_node
) = tdecl
;
12999 tdecl
= add_builtin_type ("__vector __bool char", bool_V16QI_type_node
);
13000 TYPE_NAME ( bool_V16QI_type_node
) = tdecl
;
13002 tdecl
= add_builtin_type ("__vector unsigned short", unsigned_V8HI_type_node
);
13003 TYPE_NAME (unsigned_V8HI_type_node
) = tdecl
;
13005 tdecl
= add_builtin_type ("__vector signed short", V8HI_type_node
);
13006 TYPE_NAME (V8HI_type_node
) = tdecl
;
13008 tdecl
= add_builtin_type ("__vector __bool short", bool_V8HI_type_node
);
13009 TYPE_NAME (bool_V8HI_type_node
) = tdecl
;
13011 tdecl
= add_builtin_type ("__vector unsigned int", unsigned_V4SI_type_node
);
13012 TYPE_NAME (unsigned_V4SI_type_node
) = tdecl
;
13014 tdecl
= add_builtin_type ("__vector signed int", V4SI_type_node
);
13015 TYPE_NAME (V4SI_type_node
) = tdecl
;
13017 tdecl
= add_builtin_type ("__vector __bool int", bool_V4SI_type_node
);
13018 TYPE_NAME (bool_V4SI_type_node
) = tdecl
;
13020 tdecl
= add_builtin_type ("__vector float", V4SF_type_node
);
13021 TYPE_NAME (V4SF_type_node
) = tdecl
;
13023 tdecl
= add_builtin_type ("__vector __pixel", pixel_V8HI_type_node
);
13024 TYPE_NAME (pixel_V8HI_type_node
) = tdecl
;
13026 tdecl
= add_builtin_type ("__vector double", V2DF_type_node
);
13027 TYPE_NAME (V2DF_type_node
) = tdecl
;
13029 tdecl
= add_builtin_type ("__vector long", V2DI_type_node
);
13030 TYPE_NAME (V2DI_type_node
) = tdecl
;
13032 tdecl
= add_builtin_type ("__vector unsigned long", unsigned_V2DI_type_node
);
13033 TYPE_NAME (unsigned_V2DI_type_node
) = tdecl
;
13035 tdecl
= add_builtin_type ("__vector __bool long", bool_V2DI_type_node
);
13036 TYPE_NAME (bool_V2DI_type_node
) = tdecl
;
13038 /* Paired and SPE builtins are only available if you build a compiler with
13039 the appropriate options, so only create those builtins with the
13040 appropriate compiler option. Create Altivec and VSX builtins on machines
13041 with at least the general purpose extensions (970 and newer) to allow the
13042 use of the target attribute. */
13043 if (TARGET_PAIRED_FLOAT
)
13044 paired_init_builtins ();
13046 spe_init_builtins ();
13047 if (TARGET_EXTRA_BUILTINS
)
13048 altivec_init_builtins ();
13050 htm_init_builtins ();
13052 if (TARGET_EXTRA_BUILTINS
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
)
13053 rs6000_common_init_builtins ();
13055 ftype
= builtin_function_type (DFmode
, DFmode
, DFmode
, VOIDmode
,
13056 RS6000_BUILTIN_RECIP
, "__builtin_recipdiv");
13057 def_builtin ("__builtin_recipdiv", ftype
, RS6000_BUILTIN_RECIP
);
13059 ftype
= builtin_function_type (SFmode
, SFmode
, SFmode
, VOIDmode
,
13060 RS6000_BUILTIN_RECIPF
, "__builtin_recipdivf");
13061 def_builtin ("__builtin_recipdivf", ftype
, RS6000_BUILTIN_RECIPF
);
13063 ftype
= builtin_function_type (DFmode
, DFmode
, VOIDmode
, VOIDmode
,
13064 RS6000_BUILTIN_RSQRT
, "__builtin_rsqrt");
13065 def_builtin ("__builtin_rsqrt", ftype
, RS6000_BUILTIN_RSQRT
);
13067 ftype
= builtin_function_type (SFmode
, SFmode
, VOIDmode
, VOIDmode
,
13068 RS6000_BUILTIN_RSQRTF
, "__builtin_rsqrtf");
13069 def_builtin ("__builtin_rsqrtf", ftype
, RS6000_BUILTIN_RSQRTF
);
13071 mode
= (TARGET_64BIT
) ? DImode
: SImode
;
13072 ftype
= builtin_function_type (mode
, mode
, mode
, VOIDmode
,
13073 POWER7_BUILTIN_BPERMD
, "__builtin_bpermd");
13074 def_builtin ("__builtin_bpermd", ftype
, POWER7_BUILTIN_BPERMD
);
13076 ftype
= build_function_type_list (unsigned_intDI_type_node
,
13078 def_builtin ("__builtin_ppc_get_timebase", ftype
, RS6000_BUILTIN_GET_TB
);
13081 ftype
= build_function_type_list (unsigned_intDI_type_node
,
13084 ftype
= build_function_type_list (unsigned_intSI_type_node
,
13086 def_builtin ("__builtin_ppc_mftb", ftype
, RS6000_BUILTIN_MFTB
);
13089 /* AIX libm provides clog as __clog. */
13090 if ((tdecl
= builtin_decl_explicit (BUILT_IN_CLOG
)) != NULL_TREE
)
13091 set_user_assembler_name (tdecl
, "__clog");
13094 #ifdef SUBTARGET_INIT_BUILTINS
13095 SUBTARGET_INIT_BUILTINS
;
13099 /* Returns the rs6000 builtin decl for CODE. */
13102 rs6000_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
13104 HOST_WIDE_INT fnmask
;
13106 if (code
>= RS6000_BUILTIN_COUNT
)
13107 return error_mark_node
;
13109 fnmask
= rs6000_builtin_info
[code
].mask
;
13110 if ((fnmask
& rs6000_builtin_mask
) != fnmask
)
13112 rs6000_invalid_builtin ((enum rs6000_builtins
)code
);
13113 return error_mark_node
;
13116 return rs6000_builtin_decls
[code
];
13120 spe_init_builtins (void)
13122 tree puint_type_node
= build_pointer_type (unsigned_type_node
);
13123 tree pushort_type_node
= build_pointer_type (short_unsigned_type_node
);
13124 const struct builtin_description
*d
;
13127 tree v2si_ftype_4_v2si
13128 = build_function_type_list (opaque_V2SI_type_node
,
13129 opaque_V2SI_type_node
,
13130 opaque_V2SI_type_node
,
13131 opaque_V2SI_type_node
,
13132 opaque_V2SI_type_node
,
13135 tree v2sf_ftype_4_v2sf
13136 = build_function_type_list (opaque_V2SF_type_node
,
13137 opaque_V2SF_type_node
,
13138 opaque_V2SF_type_node
,
13139 opaque_V2SF_type_node
,
13140 opaque_V2SF_type_node
,
13143 tree int_ftype_int_v2si_v2si
13144 = build_function_type_list (integer_type_node
,
13146 opaque_V2SI_type_node
,
13147 opaque_V2SI_type_node
,
13150 tree int_ftype_int_v2sf_v2sf
13151 = build_function_type_list (integer_type_node
,
13153 opaque_V2SF_type_node
,
13154 opaque_V2SF_type_node
,
13157 tree void_ftype_v2si_puint_int
13158 = build_function_type_list (void_type_node
,
13159 opaque_V2SI_type_node
,
13164 tree void_ftype_v2si_puint_char
13165 = build_function_type_list (void_type_node
,
13166 opaque_V2SI_type_node
,
13171 tree void_ftype_v2si_pv2si_int
13172 = build_function_type_list (void_type_node
,
13173 opaque_V2SI_type_node
,
13174 opaque_p_V2SI_type_node
,
13178 tree void_ftype_v2si_pv2si_char
13179 = build_function_type_list (void_type_node
,
13180 opaque_V2SI_type_node
,
13181 opaque_p_V2SI_type_node
,
13185 tree void_ftype_int
13186 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
13188 tree int_ftype_void
13189 = build_function_type_list (integer_type_node
, NULL_TREE
);
13191 tree v2si_ftype_pv2si_int
13192 = build_function_type_list (opaque_V2SI_type_node
,
13193 opaque_p_V2SI_type_node
,
13197 tree v2si_ftype_puint_int
13198 = build_function_type_list (opaque_V2SI_type_node
,
13203 tree v2si_ftype_pushort_int
13204 = build_function_type_list (opaque_V2SI_type_node
,
13209 tree v2si_ftype_signed_char
13210 = build_function_type_list (opaque_V2SI_type_node
,
13211 signed_char_type_node
,
13214 add_builtin_type ("__ev64_opaque__", opaque_V2SI_type_node
);
13216 /* Initialize irregular SPE builtins. */
13218 def_builtin ("__builtin_spe_mtspefscr", void_ftype_int
, SPE_BUILTIN_MTSPEFSCR
);
13219 def_builtin ("__builtin_spe_mfspefscr", int_ftype_void
, SPE_BUILTIN_MFSPEFSCR
);
13220 def_builtin ("__builtin_spe_evstddx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDDX
);
13221 def_builtin ("__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDHX
);
13222 def_builtin ("__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDWX
);
13223 def_builtin ("__builtin_spe_evstwhex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHEX
);
13224 def_builtin ("__builtin_spe_evstwhox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHOX
);
13225 def_builtin ("__builtin_spe_evstwwex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWEX
);
13226 def_builtin ("__builtin_spe_evstwwox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWOX
);
13227 def_builtin ("__builtin_spe_evstdd", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDD
);
13228 def_builtin ("__builtin_spe_evstdh", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDH
);
13229 def_builtin ("__builtin_spe_evstdw", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDW
);
13230 def_builtin ("__builtin_spe_evstwhe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHE
);
13231 def_builtin ("__builtin_spe_evstwho", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHO
);
13232 def_builtin ("__builtin_spe_evstwwe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWE
);
13233 def_builtin ("__builtin_spe_evstwwo", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWO
);
13234 def_builtin ("__builtin_spe_evsplatfi", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATFI
);
13235 def_builtin ("__builtin_spe_evsplati", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATI
);
13238 def_builtin ("__builtin_spe_evlddx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDDX
);
13239 def_builtin ("__builtin_spe_evldwx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDWX
);
13240 def_builtin ("__builtin_spe_evldhx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDHX
);
13241 def_builtin ("__builtin_spe_evlwhex", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHEX
);
13242 def_builtin ("__builtin_spe_evlwhoux", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOUX
);
13243 def_builtin ("__builtin_spe_evlwhosx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOSX
);
13244 def_builtin ("__builtin_spe_evlwwsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLATX
);
13245 def_builtin ("__builtin_spe_evlwhsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLATX
);
13246 def_builtin ("__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLATX
);
13247 def_builtin ("__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLATX
);
13248 def_builtin ("__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLATX
);
13249 def_builtin ("__builtin_spe_evldd", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDD
);
13250 def_builtin ("__builtin_spe_evldw", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDW
);
13251 def_builtin ("__builtin_spe_evldh", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDH
);
13252 def_builtin ("__builtin_spe_evlhhesplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLAT
);
13253 def_builtin ("__builtin_spe_evlhhossplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLAT
);
13254 def_builtin ("__builtin_spe_evlhhousplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLAT
);
13255 def_builtin ("__builtin_spe_evlwhe", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHE
);
13256 def_builtin ("__builtin_spe_evlwhos", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOS
);
13257 def_builtin ("__builtin_spe_evlwhou", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOU
);
13258 def_builtin ("__builtin_spe_evlwhsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLAT
);
13259 def_builtin ("__builtin_spe_evlwwsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLAT
);
13262 d
= bdesc_spe_predicates
;
13263 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, d
++)
13267 switch (insn_data
[d
->icode
].operand
[1].mode
)
13270 type
= int_ftype_int_v2si_v2si
;
13273 type
= int_ftype_int_v2sf_v2sf
;
13276 gcc_unreachable ();
13279 def_builtin (d
->name
, type
, d
->code
);
13282 /* Evsel predicates. */
13283 d
= bdesc_spe_evsel
;
13284 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, d
++)
13288 switch (insn_data
[d
->icode
].operand
[1].mode
)
13291 type
= v2si_ftype_4_v2si
;
13294 type
= v2sf_ftype_4_v2sf
;
13297 gcc_unreachable ();
13300 def_builtin (d
->name
, type
, d
->code
);
13305 paired_init_builtins (void)
13307 const struct builtin_description
*d
;
13310 tree int_ftype_int_v2sf_v2sf
13311 = build_function_type_list (integer_type_node
,
13316 tree pcfloat_type_node
=
13317 build_pointer_type (build_qualified_type
13318 (float_type_node
, TYPE_QUAL_CONST
));
13320 tree v2sf_ftype_long_pcfloat
= build_function_type_list (V2SF_type_node
,
13321 long_integer_type_node
,
13324 tree void_ftype_v2sf_long_pcfloat
=
13325 build_function_type_list (void_type_node
,
13327 long_integer_type_node
,
13332 def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat
,
13333 PAIRED_BUILTIN_LX
);
13336 def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat
,
13337 PAIRED_BUILTIN_STX
);
13340 d
= bdesc_paired_preds
;
13341 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); ++i
, d
++)
13345 if (TARGET_DEBUG_BUILTIN
)
13346 fprintf (stderr
, "paired pred #%d, insn = %s [%d], mode = %s\n",
13347 (int)i
, get_insn_name (d
->icode
), (int)d
->icode
,
13348 GET_MODE_NAME (insn_data
[d
->icode
].operand
[1].mode
));
13350 switch (insn_data
[d
->icode
].operand
[1].mode
)
13353 type
= int_ftype_int_v2sf_v2sf
;
13356 gcc_unreachable ();
13359 def_builtin (d
->name
, type
, d
->code
);
13364 altivec_init_builtins (void)
13366 const struct builtin_description
*d
;
13371 tree pvoid_type_node
= build_pointer_type (void_type_node
);
13373 tree pcvoid_type_node
13374 = build_pointer_type (build_qualified_type (void_type_node
,
13377 tree int_ftype_opaque
13378 = build_function_type_list (integer_type_node
,
13379 opaque_V4SI_type_node
, NULL_TREE
);
13380 tree opaque_ftype_opaque
13381 = build_function_type_list (integer_type_node
, NULL_TREE
);
13382 tree opaque_ftype_opaque_int
13383 = build_function_type_list (opaque_V4SI_type_node
,
13384 opaque_V4SI_type_node
, integer_type_node
, NULL_TREE
);
13385 tree opaque_ftype_opaque_opaque_int
13386 = build_function_type_list (opaque_V4SI_type_node
,
13387 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
13388 integer_type_node
, NULL_TREE
);
13389 tree int_ftype_int_opaque_opaque
13390 = build_function_type_list (integer_type_node
,
13391 integer_type_node
, opaque_V4SI_type_node
,
13392 opaque_V4SI_type_node
, NULL_TREE
);
13393 tree int_ftype_int_v4si_v4si
13394 = build_function_type_list (integer_type_node
,
13395 integer_type_node
, V4SI_type_node
,
13396 V4SI_type_node
, NULL_TREE
);
13397 tree int_ftype_int_v2di_v2di
13398 = build_function_type_list (integer_type_node
,
13399 integer_type_node
, V2DI_type_node
,
13400 V2DI_type_node
, NULL_TREE
);
13401 tree void_ftype_v4si
13402 = build_function_type_list (void_type_node
, V4SI_type_node
, NULL_TREE
);
13403 tree v8hi_ftype_void
13404 = build_function_type_list (V8HI_type_node
, NULL_TREE
);
13405 tree void_ftype_void
13406 = build_function_type_list (void_type_node
, NULL_TREE
);
13407 tree void_ftype_int
13408 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
13410 tree opaque_ftype_long_pcvoid
13411 = build_function_type_list (opaque_V4SI_type_node
,
13412 long_integer_type_node
, pcvoid_type_node
,
13414 tree v16qi_ftype_long_pcvoid
13415 = build_function_type_list (V16QI_type_node
,
13416 long_integer_type_node
, pcvoid_type_node
,
13418 tree v8hi_ftype_long_pcvoid
13419 = build_function_type_list (V8HI_type_node
,
13420 long_integer_type_node
, pcvoid_type_node
,
13422 tree v4si_ftype_long_pcvoid
13423 = build_function_type_list (V4SI_type_node
,
13424 long_integer_type_node
, pcvoid_type_node
,
13426 tree v4sf_ftype_long_pcvoid
13427 = build_function_type_list (V4SF_type_node
,
13428 long_integer_type_node
, pcvoid_type_node
,
13430 tree v2df_ftype_long_pcvoid
13431 = build_function_type_list (V2DF_type_node
,
13432 long_integer_type_node
, pcvoid_type_node
,
13434 tree v2di_ftype_long_pcvoid
13435 = build_function_type_list (V2DI_type_node
,
13436 long_integer_type_node
, pcvoid_type_node
,
13439 tree void_ftype_opaque_long_pvoid
13440 = build_function_type_list (void_type_node
,
13441 opaque_V4SI_type_node
, long_integer_type_node
,
13442 pvoid_type_node
, NULL_TREE
);
13443 tree void_ftype_v4si_long_pvoid
13444 = build_function_type_list (void_type_node
,
13445 V4SI_type_node
, long_integer_type_node
,
13446 pvoid_type_node
, NULL_TREE
);
13447 tree void_ftype_v16qi_long_pvoid
13448 = build_function_type_list (void_type_node
,
13449 V16QI_type_node
, long_integer_type_node
,
13450 pvoid_type_node
, NULL_TREE
);
13451 tree void_ftype_v8hi_long_pvoid
13452 = build_function_type_list (void_type_node
,
13453 V8HI_type_node
, long_integer_type_node
,
13454 pvoid_type_node
, NULL_TREE
);
13455 tree void_ftype_v4sf_long_pvoid
13456 = build_function_type_list (void_type_node
,
13457 V4SF_type_node
, long_integer_type_node
,
13458 pvoid_type_node
, NULL_TREE
);
13459 tree void_ftype_v2df_long_pvoid
13460 = build_function_type_list (void_type_node
,
13461 V2DF_type_node
, long_integer_type_node
,
13462 pvoid_type_node
, NULL_TREE
);
13463 tree void_ftype_v2di_long_pvoid
13464 = build_function_type_list (void_type_node
,
13465 V2DI_type_node
, long_integer_type_node
,
13466 pvoid_type_node
, NULL_TREE
);
13467 tree int_ftype_int_v8hi_v8hi
13468 = build_function_type_list (integer_type_node
,
13469 integer_type_node
, V8HI_type_node
,
13470 V8HI_type_node
, NULL_TREE
);
13471 tree int_ftype_int_v16qi_v16qi
13472 = build_function_type_list (integer_type_node
,
13473 integer_type_node
, V16QI_type_node
,
13474 V16QI_type_node
, NULL_TREE
);
13475 tree int_ftype_int_v4sf_v4sf
13476 = build_function_type_list (integer_type_node
,
13477 integer_type_node
, V4SF_type_node
,
13478 V4SF_type_node
, NULL_TREE
);
13479 tree int_ftype_int_v2df_v2df
13480 = build_function_type_list (integer_type_node
,
13481 integer_type_node
, V2DF_type_node
,
13482 V2DF_type_node
, NULL_TREE
);
13483 tree v2di_ftype_v2di
13484 = build_function_type_list (V2DI_type_node
, V2DI_type_node
, NULL_TREE
);
13485 tree v4si_ftype_v4si
13486 = build_function_type_list (V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
13487 tree v8hi_ftype_v8hi
13488 = build_function_type_list (V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
13489 tree v16qi_ftype_v16qi
13490 = build_function_type_list (V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
13491 tree v4sf_ftype_v4sf
13492 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
13493 tree v2df_ftype_v2df
13494 = build_function_type_list (V2DF_type_node
, V2DF_type_node
, NULL_TREE
);
13495 tree void_ftype_pcvoid_int_int
13496 = build_function_type_list (void_type_node
,
13497 pcvoid_type_node
, integer_type_node
,
13498 integer_type_node
, NULL_TREE
);
13500 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si
, ALTIVEC_BUILTIN_MTVSCR
);
13501 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void
, ALTIVEC_BUILTIN_MFVSCR
);
13502 def_builtin ("__builtin_altivec_dssall", void_ftype_void
, ALTIVEC_BUILTIN_DSSALL
);
13503 def_builtin ("__builtin_altivec_dss", void_ftype_int
, ALTIVEC_BUILTIN_DSS
);
13504 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSL
);
13505 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSR
);
13506 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEBX
);
13507 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEHX
);
13508 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEWX
);
13509 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVXL
);
13510 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVX
);
13511 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVX
);
13512 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVEWX
);
13513 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVXL
);
13514 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVEBX
);
13515 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid
, ALTIVEC_BUILTIN_STVEHX
);
13516 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LD
);
13517 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDE
);
13518 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDL
);
13519 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSL
);
13520 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSR
);
13521 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEBX
);
13522 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEHX
);
13523 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEWX
);
13524 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_ST
);
13525 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STE
);
13526 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STL
);
13527 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEWX
);
13528 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEBX
);
13529 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEHX
);
13531 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid
,
13532 VSX_BUILTIN_LXVD2X_V2DF
);
13533 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid
,
13534 VSX_BUILTIN_LXVD2X_V2DI
);
13535 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid
,
13536 VSX_BUILTIN_LXVW4X_V4SF
);
13537 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid
,
13538 VSX_BUILTIN_LXVW4X_V4SI
);
13539 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid
,
13540 VSX_BUILTIN_LXVW4X_V8HI
);
13541 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid
,
13542 VSX_BUILTIN_LXVW4X_V16QI
);
13543 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid
,
13544 VSX_BUILTIN_STXVD2X_V2DF
);
13545 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid
,
13546 VSX_BUILTIN_STXVD2X_V2DI
);
13547 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid
,
13548 VSX_BUILTIN_STXVW4X_V4SF
);
13549 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid
,
13550 VSX_BUILTIN_STXVW4X_V4SI
);
13551 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid
,
13552 VSX_BUILTIN_STXVW4X_V8HI
);
13553 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid
,
13554 VSX_BUILTIN_STXVW4X_V16QI
);
13555 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid
,
13556 VSX_BUILTIN_VEC_LD
);
13557 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid
,
13558 VSX_BUILTIN_VEC_ST
);
13560 def_builtin ("__builtin_vec_step", int_ftype_opaque
, ALTIVEC_BUILTIN_VEC_STEP
);
13561 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_SPLATS
);
13562 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_PROMOTE
);
13564 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_SLD
);
13565 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_SPLAT
);
13566 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_EXTRACT
);
13567 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_INSERT
);
13568 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTW
);
13569 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTH
);
13570 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTB
);
13571 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTF
);
13572 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFSX
);
13573 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFUX
);
13574 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTS
);
13575 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTU
);
13577 /* Cell builtins. */
13578 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLX
);
13579 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLXL
);
13580 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRX
);
13581 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRXL
);
13583 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLX
);
13584 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLXL
);
13585 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRX
);
13586 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRXL
);
13588 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLX
);
13589 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLXL
);
13590 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRX
);
13591 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRXL
);
13593 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLX
);
13594 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLXL
);
13595 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRX
);
13596 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRXL
);
13598 /* Add the DST variants. */
13600 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
13601 def_builtin (d
->name
, void_ftype_pcvoid_int_int
, d
->code
);
13603 /* Initialize the predicates. */
13604 d
= bdesc_altivec_preds
;
13605 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
13607 enum machine_mode mode1
;
13610 if (rs6000_overloaded_builtin_p (d
->code
))
13613 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
13618 type
= int_ftype_int_opaque_opaque
;
13621 type
= int_ftype_int_v2di_v2di
;
13624 type
= int_ftype_int_v4si_v4si
;
13627 type
= int_ftype_int_v8hi_v8hi
;
13630 type
= int_ftype_int_v16qi_v16qi
;
13633 type
= int_ftype_int_v4sf_v4sf
;
13636 type
= int_ftype_int_v2df_v2df
;
13639 gcc_unreachable ();
13642 def_builtin (d
->name
, type
, d
->code
);
13645 /* Initialize the abs* operators. */
13647 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
13649 enum machine_mode mode0
;
13652 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
13657 type
= v2di_ftype_v2di
;
13660 type
= v4si_ftype_v4si
;
13663 type
= v8hi_ftype_v8hi
;
13666 type
= v16qi_ftype_v16qi
;
13669 type
= v4sf_ftype_v4sf
;
13672 type
= v2df_ftype_v2df
;
13675 gcc_unreachable ();
13678 def_builtin (d
->name
, type
, d
->code
);
13681 /* Initialize target builtin that implements
13682 targetm.vectorize.builtin_mask_for_load. */
13684 decl
= add_builtin_function ("__builtin_altivec_mask_for_load",
13685 v16qi_ftype_long_pcvoid
,
13686 ALTIVEC_BUILTIN_MASK_FOR_LOAD
,
13687 BUILT_IN_MD
, NULL
, NULL_TREE
);
13688 TREE_READONLY (decl
) = 1;
13689 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
13690 altivec_builtin_mask_for_load
= decl
;
13692 /* Access to the vec_init patterns. */
13693 ftype
= build_function_type_list (V4SI_type_node
, integer_type_node
,
13694 integer_type_node
, integer_type_node
,
13695 integer_type_node
, NULL_TREE
);
13696 def_builtin ("__builtin_vec_init_v4si", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SI
);
13698 ftype
= build_function_type_list (V8HI_type_node
, short_integer_type_node
,
13699 short_integer_type_node
,
13700 short_integer_type_node
,
13701 short_integer_type_node
,
13702 short_integer_type_node
,
13703 short_integer_type_node
,
13704 short_integer_type_node
,
13705 short_integer_type_node
, NULL_TREE
);
13706 def_builtin ("__builtin_vec_init_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V8HI
);
13708 ftype
= build_function_type_list (V16QI_type_node
, char_type_node
,
13709 char_type_node
, char_type_node
,
13710 char_type_node
, char_type_node
,
13711 char_type_node
, char_type_node
,
13712 char_type_node
, char_type_node
,
13713 char_type_node
, char_type_node
,
13714 char_type_node
, char_type_node
,
13715 char_type_node
, char_type_node
,
13716 char_type_node
, NULL_TREE
);
13717 def_builtin ("__builtin_vec_init_v16qi", ftype
,
13718 ALTIVEC_BUILTIN_VEC_INIT_V16QI
);
13720 ftype
= build_function_type_list (V4SF_type_node
, float_type_node
,
13721 float_type_node
, float_type_node
,
13722 float_type_node
, NULL_TREE
);
13723 def_builtin ("__builtin_vec_init_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SF
);
13725 /* VSX builtins. */
13726 ftype
= build_function_type_list (V2DF_type_node
, double_type_node
,
13727 double_type_node
, NULL_TREE
);
13728 def_builtin ("__builtin_vec_init_v2df", ftype
, VSX_BUILTIN_VEC_INIT_V2DF
);
13730 ftype
= build_function_type_list (V2DI_type_node
, intDI_type_node
,
13731 intDI_type_node
, NULL_TREE
);
13732 def_builtin ("__builtin_vec_init_v2di", ftype
, VSX_BUILTIN_VEC_INIT_V2DI
);
13734 /* Access to the vec_set patterns. */
13735 ftype
= build_function_type_list (V4SI_type_node
, V4SI_type_node
,
13737 integer_type_node
, NULL_TREE
);
13738 def_builtin ("__builtin_vec_set_v4si", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SI
);
13740 ftype
= build_function_type_list (V8HI_type_node
, V8HI_type_node
,
13742 integer_type_node
, NULL_TREE
);
13743 def_builtin ("__builtin_vec_set_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V8HI
);
13745 ftype
= build_function_type_list (V16QI_type_node
, V16QI_type_node
,
13747 integer_type_node
, NULL_TREE
);
13748 def_builtin ("__builtin_vec_set_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V16QI
);
13750 ftype
= build_function_type_list (V4SF_type_node
, V4SF_type_node
,
13752 integer_type_node
, NULL_TREE
);
13753 def_builtin ("__builtin_vec_set_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SF
);
13755 ftype
= build_function_type_list (V2DF_type_node
, V2DF_type_node
,
13757 integer_type_node
, NULL_TREE
);
13758 def_builtin ("__builtin_vec_set_v2df", ftype
, VSX_BUILTIN_VEC_SET_V2DF
);
13760 ftype
= build_function_type_list (V2DI_type_node
, V2DI_type_node
,
13762 integer_type_node
, NULL_TREE
);
13763 def_builtin ("__builtin_vec_set_v2di", ftype
, VSX_BUILTIN_VEC_SET_V2DI
);
13765 /* Access to the vec_extract patterns. */
13766 ftype
= build_function_type_list (intSI_type_node
, V4SI_type_node
,
13767 integer_type_node
, NULL_TREE
);
13768 def_builtin ("__builtin_vec_ext_v4si", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SI
);
13770 ftype
= build_function_type_list (intHI_type_node
, V8HI_type_node
,
13771 integer_type_node
, NULL_TREE
);
13772 def_builtin ("__builtin_vec_ext_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V8HI
);
13774 ftype
= build_function_type_list (intQI_type_node
, V16QI_type_node
,
13775 integer_type_node
, NULL_TREE
);
13776 def_builtin ("__builtin_vec_ext_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V16QI
);
13778 ftype
= build_function_type_list (float_type_node
, V4SF_type_node
,
13779 integer_type_node
, NULL_TREE
);
13780 def_builtin ("__builtin_vec_ext_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SF
);
13782 ftype
= build_function_type_list (double_type_node
, V2DF_type_node
,
13783 integer_type_node
, NULL_TREE
);
13784 def_builtin ("__builtin_vec_ext_v2df", ftype
, VSX_BUILTIN_VEC_EXT_V2DF
);
13786 ftype
= build_function_type_list (intDI_type_node
, V2DI_type_node
,
13787 integer_type_node
, NULL_TREE
);
13788 def_builtin ("__builtin_vec_ext_v2di", ftype
, VSX_BUILTIN_VEC_EXT_V2DI
);
13792 htm_init_builtins (void)
13794 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
13795 const struct builtin_description
*d
;
13799 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
13801 tree op
[MAX_HTM_OPERANDS
], type
;
13802 HOST_WIDE_INT mask
= d
->mask
;
13803 unsigned attr
= rs6000_builtin_info
[d
->code
].attr
;
13804 bool void_func
= (attr
& RS6000_BTC_VOID
);
13805 int attr_args
= (attr
& RS6000_BTC_TYPE_MASK
);
13807 tree argtype
= (attr
& RS6000_BTC_SPR
) ? long_unsigned_type_node
13808 : unsigned_type_node
;
13810 if ((mask
& builtin_mask
) != mask
)
13812 if (TARGET_DEBUG_BUILTIN
)
13813 fprintf (stderr
, "htm_builtin, skip binary %s\n", d
->name
);
13819 if (TARGET_DEBUG_BUILTIN
)
13820 fprintf (stderr
, "htm_builtin, bdesc_htm[%ld] no name\n",
13821 (long unsigned) i
);
13825 op
[nopnds
++] = (void_func
) ? void_type_node
: argtype
;
13827 if (attr_args
== RS6000_BTC_UNARY
)
13828 op
[nopnds
++] = argtype
;
13829 else if (attr_args
== RS6000_BTC_BINARY
)
13831 op
[nopnds
++] = argtype
;
13832 op
[nopnds
++] = argtype
;
13834 else if (attr_args
== RS6000_BTC_TERNARY
)
13836 op
[nopnds
++] = argtype
;
13837 op
[nopnds
++] = argtype
;
13838 op
[nopnds
++] = argtype
;
13844 type
= build_function_type_list (op
[0], NULL_TREE
);
13847 type
= build_function_type_list (op
[0], op
[1], NULL_TREE
);
13850 type
= build_function_type_list (op
[0], op
[1], op
[2], NULL_TREE
);
13853 type
= build_function_type_list (op
[0], op
[1], op
[2], op
[3],
13857 gcc_unreachable ();
13860 def_builtin (d
->name
, type
, d
->code
);
13864 /* Hash function for builtin functions with up to 3 arguments and a return
13867 builtin_hash_function (const void *hash_entry
)
13871 const struct builtin_hash_struct
*bh
=
13872 (const struct builtin_hash_struct
*) hash_entry
;
13874 for (i
= 0; i
< 4; i
++)
13876 ret
= (ret
* (unsigned)MAX_MACHINE_MODE
) + ((unsigned)bh
->mode
[i
]);
13877 ret
= (ret
* 2) + bh
->uns_p
[i
];
13883 /* Compare builtin hash entries H1 and H2 for equivalence. */
13885 builtin_hash_eq (const void *h1
, const void *h2
)
13887 const struct builtin_hash_struct
*p1
= (const struct builtin_hash_struct
*) h1
;
13888 const struct builtin_hash_struct
*p2
= (const struct builtin_hash_struct
*) h2
;
13890 return ((p1
->mode
[0] == p2
->mode
[0])
13891 && (p1
->mode
[1] == p2
->mode
[1])
13892 && (p1
->mode
[2] == p2
->mode
[2])
13893 && (p1
->mode
[3] == p2
->mode
[3])
13894 && (p1
->uns_p
[0] == p2
->uns_p
[0])
13895 && (p1
->uns_p
[1] == p2
->uns_p
[1])
13896 && (p1
->uns_p
[2] == p2
->uns_p
[2])
13897 && (p1
->uns_p
[3] == p2
->uns_p
[3]));
13900 /* Map types for builtin functions with an explicit return type and up to 3
13901 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
13902 of the argument. */
13904 builtin_function_type (enum machine_mode mode_ret
, enum machine_mode mode_arg0
,
13905 enum machine_mode mode_arg1
, enum machine_mode mode_arg2
,
13906 enum rs6000_builtins builtin
, const char *name
)
13908 struct builtin_hash_struct h
;
13909 struct builtin_hash_struct
*h2
;
13913 tree ret_type
= NULL_TREE
;
13914 tree arg_type
[3] = { NULL_TREE
, NULL_TREE
, NULL_TREE
};
13916 /* Create builtin_hash_table. */
13917 if (builtin_hash_table
== NULL
)
13918 builtin_hash_table
= htab_create_ggc (1500, builtin_hash_function
,
13919 builtin_hash_eq
, NULL
);
13921 h
.type
= NULL_TREE
;
13922 h
.mode
[0] = mode_ret
;
13923 h
.mode
[1] = mode_arg0
;
13924 h
.mode
[2] = mode_arg1
;
13925 h
.mode
[3] = mode_arg2
;
13931 /* If the builtin is a type that produces unsigned results or takes unsigned
13932 arguments, and it is returned as a decl for the vectorizer (such as
13933 widening multiplies, permute), make sure the arguments and return value
13934 are type correct. */
13937 /* unsigned 1 argument functions. */
13938 case CRYPTO_BUILTIN_VSBOX
:
13939 case P8V_BUILTIN_VGBBD
:
13944 /* unsigned 2 argument functions. */
13945 case ALTIVEC_BUILTIN_VMULEUB_UNS
:
13946 case ALTIVEC_BUILTIN_VMULEUH_UNS
:
13947 case ALTIVEC_BUILTIN_VMULOUB_UNS
:
13948 case ALTIVEC_BUILTIN_VMULOUH_UNS
:
13949 case CRYPTO_BUILTIN_VCIPHER
:
13950 case CRYPTO_BUILTIN_VCIPHERLAST
:
13951 case CRYPTO_BUILTIN_VNCIPHER
:
13952 case CRYPTO_BUILTIN_VNCIPHERLAST
:
13953 case CRYPTO_BUILTIN_VPMSUMB
:
13954 case CRYPTO_BUILTIN_VPMSUMH
:
13955 case CRYPTO_BUILTIN_VPMSUMW
:
13956 case CRYPTO_BUILTIN_VPMSUMD
:
13957 case CRYPTO_BUILTIN_VPMSUM
:
13963 /* unsigned 3 argument functions. */
13964 case ALTIVEC_BUILTIN_VPERM_16QI_UNS
:
13965 case ALTIVEC_BUILTIN_VPERM_8HI_UNS
:
13966 case ALTIVEC_BUILTIN_VPERM_4SI_UNS
:
13967 case ALTIVEC_BUILTIN_VPERM_2DI_UNS
:
13968 case ALTIVEC_BUILTIN_VSEL_16QI_UNS
:
13969 case ALTIVEC_BUILTIN_VSEL_8HI_UNS
:
13970 case ALTIVEC_BUILTIN_VSEL_4SI_UNS
:
13971 case ALTIVEC_BUILTIN_VSEL_2DI_UNS
:
13972 case VSX_BUILTIN_VPERM_16QI_UNS
:
13973 case VSX_BUILTIN_VPERM_8HI_UNS
:
13974 case VSX_BUILTIN_VPERM_4SI_UNS
:
13975 case VSX_BUILTIN_VPERM_2DI_UNS
:
13976 case VSX_BUILTIN_XXSEL_16QI_UNS
:
13977 case VSX_BUILTIN_XXSEL_8HI_UNS
:
13978 case VSX_BUILTIN_XXSEL_4SI_UNS
:
13979 case VSX_BUILTIN_XXSEL_2DI_UNS
:
13980 case CRYPTO_BUILTIN_VPERMXOR
:
13981 case CRYPTO_BUILTIN_VPERMXOR_V2DI
:
13982 case CRYPTO_BUILTIN_VPERMXOR_V4SI
:
13983 case CRYPTO_BUILTIN_VPERMXOR_V8HI
:
13984 case CRYPTO_BUILTIN_VPERMXOR_V16QI
:
13985 case CRYPTO_BUILTIN_VSHASIGMAW
:
13986 case CRYPTO_BUILTIN_VSHASIGMAD
:
13987 case CRYPTO_BUILTIN_VSHASIGMA
:
13994 /* signed permute functions with unsigned char mask. */
13995 case ALTIVEC_BUILTIN_VPERM_16QI
:
13996 case ALTIVEC_BUILTIN_VPERM_8HI
:
13997 case ALTIVEC_BUILTIN_VPERM_4SI
:
13998 case ALTIVEC_BUILTIN_VPERM_4SF
:
13999 case ALTIVEC_BUILTIN_VPERM_2DI
:
14000 case ALTIVEC_BUILTIN_VPERM_2DF
:
14001 case VSX_BUILTIN_VPERM_16QI
:
14002 case VSX_BUILTIN_VPERM_8HI
:
14003 case VSX_BUILTIN_VPERM_4SI
:
14004 case VSX_BUILTIN_VPERM_4SF
:
14005 case VSX_BUILTIN_VPERM_2DI
:
14006 case VSX_BUILTIN_VPERM_2DF
:
14010 /* unsigned args, signed return. */
14011 case VSX_BUILTIN_XVCVUXDDP_UNS
:
14012 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF
:
14016 /* signed args, unsigned return. */
14017 case VSX_BUILTIN_XVCVDPUXDS_UNS
:
14018 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI
:
14026 /* Figure out how many args are present. */
14027 while (num_args
> 0 && h
.mode
[num_args
] == VOIDmode
)
14031 fatal_error ("internal error: builtin function %s had no type", name
);
14033 ret_type
= builtin_mode_to_type
[h
.mode
[0]][h
.uns_p
[0]];
14034 if (!ret_type
&& h
.uns_p
[0])
14035 ret_type
= builtin_mode_to_type
[h
.mode
[0]][0];
14038 fatal_error ("internal error: builtin function %s had an unexpected "
14039 "return type %s", name
, GET_MODE_NAME (h
.mode
[0]));
14041 for (i
= 0; i
< (int) ARRAY_SIZE (arg_type
); i
++)
14042 arg_type
[i
] = NULL_TREE
;
14044 for (i
= 0; i
< num_args
; i
++)
14046 int m
= (int) h
.mode
[i
+1];
14047 int uns_p
= h
.uns_p
[i
+1];
14049 arg_type
[i
] = builtin_mode_to_type
[m
][uns_p
];
14050 if (!arg_type
[i
] && uns_p
)
14051 arg_type
[i
] = builtin_mode_to_type
[m
][0];
14054 fatal_error ("internal error: builtin function %s, argument %d "
14055 "had unexpected argument type %s", name
, i
,
14056 GET_MODE_NAME (m
));
14059 found
= htab_find_slot (builtin_hash_table
, &h
, INSERT
);
14060 if (*found
== NULL
)
14062 h2
= ggc_alloc_builtin_hash_struct ();
14064 *found
= (void *)h2
;
14066 h2
->type
= build_function_type_list (ret_type
, arg_type
[0], arg_type
[1],
14067 arg_type
[2], NULL_TREE
);
14070 return ((struct builtin_hash_struct
*)(*found
))->type
;
14074 rs6000_common_init_builtins (void)
14076 const struct builtin_description
*d
;
14079 tree opaque_ftype_opaque
= NULL_TREE
;
14080 tree opaque_ftype_opaque_opaque
= NULL_TREE
;
14081 tree opaque_ftype_opaque_opaque_opaque
= NULL_TREE
;
14082 tree v2si_ftype_qi
= NULL_TREE
;
14083 tree v2si_ftype_v2si_qi
= NULL_TREE
;
14084 tree v2si_ftype_int_qi
= NULL_TREE
;
14085 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
14087 if (!TARGET_PAIRED_FLOAT
)
14089 builtin_mode_to_type
[V2SImode
][0] = opaque_V2SI_type_node
;
14090 builtin_mode_to_type
[V2SFmode
][0] = opaque_V2SF_type_node
;
14093 /* Paired and SPE builtins are only available if you build a compiler with
14094 the appropriate options, so only create those builtins with the
14095 appropriate compiler option. Create Altivec and VSX builtins on machines
14096 with at least the general purpose extensions (970 and newer) to allow the
14097 use of the target attribute.. */
14099 if (TARGET_EXTRA_BUILTINS
)
14100 builtin_mask
|= RS6000_BTM_COMMON
;
14102 /* Add the ternary operators. */
14104 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
14107 HOST_WIDE_INT mask
= d
->mask
;
14109 if ((mask
& builtin_mask
) != mask
)
14111 if (TARGET_DEBUG_BUILTIN
)
14112 fprintf (stderr
, "rs6000_builtin, skip ternary %s\n", d
->name
);
14116 if (rs6000_overloaded_builtin_p (d
->code
))
14118 if (! (type
= opaque_ftype_opaque_opaque_opaque
))
14119 type
= opaque_ftype_opaque_opaque_opaque
14120 = build_function_type_list (opaque_V4SI_type_node
,
14121 opaque_V4SI_type_node
,
14122 opaque_V4SI_type_node
,
14123 opaque_V4SI_type_node
,
14128 enum insn_code icode
= d
->icode
;
14131 if (TARGET_DEBUG_BUILTIN
)
14132 fprintf (stderr
, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
14138 if (icode
== CODE_FOR_nothing
)
14140 if (TARGET_DEBUG_BUILTIN
)
14141 fprintf (stderr
, "rs6000_builtin, skip ternary %s (no code)\n",
14147 type
= builtin_function_type (insn_data
[icode
].operand
[0].mode
,
14148 insn_data
[icode
].operand
[1].mode
,
14149 insn_data
[icode
].operand
[2].mode
,
14150 insn_data
[icode
].operand
[3].mode
,
14154 def_builtin (d
->name
, type
, d
->code
);
14157 /* Add the binary operators. */
14159 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
14161 enum machine_mode mode0
, mode1
, mode2
;
14163 HOST_WIDE_INT mask
= d
->mask
;
14165 if ((mask
& builtin_mask
) != mask
)
14167 if (TARGET_DEBUG_BUILTIN
)
14168 fprintf (stderr
, "rs6000_builtin, skip binary %s\n", d
->name
);
14172 if (rs6000_overloaded_builtin_p (d
->code
))
14174 if (! (type
= opaque_ftype_opaque_opaque
))
14175 type
= opaque_ftype_opaque_opaque
14176 = build_function_type_list (opaque_V4SI_type_node
,
14177 opaque_V4SI_type_node
,
14178 opaque_V4SI_type_node
,
14183 enum insn_code icode
= d
->icode
;
14186 if (TARGET_DEBUG_BUILTIN
)
14187 fprintf (stderr
, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
14193 if (icode
== CODE_FOR_nothing
)
14195 if (TARGET_DEBUG_BUILTIN
)
14196 fprintf (stderr
, "rs6000_builtin, skip binary %s (no code)\n",
14202 mode0
= insn_data
[icode
].operand
[0].mode
;
14203 mode1
= insn_data
[icode
].operand
[1].mode
;
14204 mode2
= insn_data
[icode
].operand
[2].mode
;
14206 if (mode0
== V2SImode
&& mode1
== V2SImode
&& mode2
== QImode
)
14208 if (! (type
= v2si_ftype_v2si_qi
))
14209 type
= v2si_ftype_v2si_qi
14210 = build_function_type_list (opaque_V2SI_type_node
,
14211 opaque_V2SI_type_node
,
14216 else if (mode0
== V2SImode
&& GET_MODE_CLASS (mode1
) == MODE_INT
14217 && mode2
== QImode
)
14219 if (! (type
= v2si_ftype_int_qi
))
14220 type
= v2si_ftype_int_qi
14221 = build_function_type_list (opaque_V2SI_type_node
,
14228 type
= builtin_function_type (mode0
, mode1
, mode2
, VOIDmode
,
14232 def_builtin (d
->name
, type
, d
->code
);
14235 /* Add the simple unary operators. */
14237 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
14239 enum machine_mode mode0
, mode1
;
14241 HOST_WIDE_INT mask
= d
->mask
;
14243 if ((mask
& builtin_mask
) != mask
)
14245 if (TARGET_DEBUG_BUILTIN
)
14246 fprintf (stderr
, "rs6000_builtin, skip unary %s\n", d
->name
);
14250 if (rs6000_overloaded_builtin_p (d
->code
))
14252 if (! (type
= opaque_ftype_opaque
))
14253 type
= opaque_ftype_opaque
14254 = build_function_type_list (opaque_V4SI_type_node
,
14255 opaque_V4SI_type_node
,
14260 enum insn_code icode
= d
->icode
;
14263 if (TARGET_DEBUG_BUILTIN
)
14264 fprintf (stderr
, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
14270 if (icode
== CODE_FOR_nothing
)
14272 if (TARGET_DEBUG_BUILTIN
)
14273 fprintf (stderr
, "rs6000_builtin, skip unary %s (no code)\n",
14279 mode0
= insn_data
[icode
].operand
[0].mode
;
14280 mode1
= insn_data
[icode
].operand
[1].mode
;
14282 if (mode0
== V2SImode
&& mode1
== QImode
)
14284 if (! (type
= v2si_ftype_qi
))
14285 type
= v2si_ftype_qi
14286 = build_function_type_list (opaque_V2SI_type_node
,
14292 type
= builtin_function_type (mode0
, mode1
, VOIDmode
, VOIDmode
,
14296 def_builtin (d
->name
, type
, d
->code
);
14301 rs6000_init_libfuncs (void)
14303 if (!TARGET_IEEEQUAD
)
14304 /* AIX/Darwin/64-bit Linux quad floating point routines. */
14305 if (!TARGET_XL_COMPAT
)
14307 set_optab_libfunc (add_optab
, TFmode
, "__gcc_qadd");
14308 set_optab_libfunc (sub_optab
, TFmode
, "__gcc_qsub");
14309 set_optab_libfunc (smul_optab
, TFmode
, "__gcc_qmul");
14310 set_optab_libfunc (sdiv_optab
, TFmode
, "__gcc_qdiv");
14312 if (!(TARGET_HARD_FLOAT
&& (TARGET_FPRS
|| TARGET_E500_DOUBLE
)))
14314 set_optab_libfunc (neg_optab
, TFmode
, "__gcc_qneg");
14315 set_optab_libfunc (eq_optab
, TFmode
, "__gcc_qeq");
14316 set_optab_libfunc (ne_optab
, TFmode
, "__gcc_qne");
14317 set_optab_libfunc (gt_optab
, TFmode
, "__gcc_qgt");
14318 set_optab_libfunc (ge_optab
, TFmode
, "__gcc_qge");
14319 set_optab_libfunc (lt_optab
, TFmode
, "__gcc_qlt");
14320 set_optab_libfunc (le_optab
, TFmode
, "__gcc_qle");
14322 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "__gcc_stoq");
14323 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "__gcc_dtoq");
14324 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "__gcc_qtos");
14325 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "__gcc_qtod");
14326 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "__gcc_qtoi");
14327 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "__gcc_qtou");
14328 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "__gcc_itoq");
14329 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "__gcc_utoq");
14332 if (!(TARGET_HARD_FLOAT
&& TARGET_FPRS
))
14333 set_optab_libfunc (unord_optab
, TFmode
, "__gcc_qunord");
14337 set_optab_libfunc (add_optab
, TFmode
, "_xlqadd");
14338 set_optab_libfunc (sub_optab
, TFmode
, "_xlqsub");
14339 set_optab_libfunc (smul_optab
, TFmode
, "_xlqmul");
14340 set_optab_libfunc (sdiv_optab
, TFmode
, "_xlqdiv");
14344 /* 32-bit SVR4 quad floating point routines. */
14346 set_optab_libfunc (add_optab
, TFmode
, "_q_add");
14347 set_optab_libfunc (sub_optab
, TFmode
, "_q_sub");
14348 set_optab_libfunc (neg_optab
, TFmode
, "_q_neg");
14349 set_optab_libfunc (smul_optab
, TFmode
, "_q_mul");
14350 set_optab_libfunc (sdiv_optab
, TFmode
, "_q_div");
14351 if (TARGET_PPC_GPOPT
)
14352 set_optab_libfunc (sqrt_optab
, TFmode
, "_q_sqrt");
14354 set_optab_libfunc (eq_optab
, TFmode
, "_q_feq");
14355 set_optab_libfunc (ne_optab
, TFmode
, "_q_fne");
14356 set_optab_libfunc (gt_optab
, TFmode
, "_q_fgt");
14357 set_optab_libfunc (ge_optab
, TFmode
, "_q_fge");
14358 set_optab_libfunc (lt_optab
, TFmode
, "_q_flt");
14359 set_optab_libfunc (le_optab
, TFmode
, "_q_fle");
14361 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_q_stoq");
14362 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_q_dtoq");
14363 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_q_qtos");
14364 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_q_qtod");
14365 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_q_qtoi");
14366 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_q_qtou");
14367 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_q_itoq");
14368 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_q_utoq");
14373 /* Expand a block clear operation, and return 1 if successful. Return 0
14374 if we should let the compiler generate normal code.
14376 operands[0] is the destination
14377 operands[1] is the length
14378 operands[3] is the alignment */
14381 expand_block_clear (rtx operands
[])
14383 rtx orig_dest
= operands
[0];
14384 rtx bytes_rtx
= operands
[1];
14385 rtx align_rtx
= operands
[3];
14386 bool constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
14387 HOST_WIDE_INT align
;
14388 HOST_WIDE_INT bytes
;
14393 /* If this is not a fixed size move, just call memcpy */
14397 /* This must be a fixed size alignment */
14398 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
14399 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
14401 /* Anything to clear? */
14402 bytes
= INTVAL (bytes_rtx
);
14406 /* Use the builtin memset after a point, to avoid huge code bloat.
14407 When optimize_size, avoid any significant code bloat; calling
14408 memset is about 4 instructions, so allow for one instruction to
14409 load zero and three to do clearing. */
14410 if (TARGET_ALTIVEC
&& align
>= 128)
14412 else if (TARGET_POWERPC64
&& align
>= 32)
14414 else if (TARGET_SPE
&& align
>= 64)
14419 if (optimize_size
&& bytes
> 3 * clear_step
)
14421 if (! optimize_size
&& bytes
> 8 * clear_step
)
14424 for (offset
= 0; bytes
> 0; offset
+= clear_bytes
, bytes
-= clear_bytes
)
14426 enum machine_mode mode
= BLKmode
;
14429 if (bytes
>= 16 && TARGET_ALTIVEC
&& align
>= 128)
14434 else if (bytes
>= 8 && TARGET_SPE
&& align
>= 64)
14439 else if (bytes
>= 8 && TARGET_POWERPC64
14440 /* 64-bit loads and stores require word-aligned
14442 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
14447 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
14448 { /* move 4 bytes */
14452 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
14453 { /* move 2 bytes */
14457 else /* move 1 byte at a time */
14463 dest
= adjust_address (orig_dest
, mode
, offset
);
14465 emit_move_insn (dest
, CONST0_RTX (mode
));
14472 /* Expand a block move operation, and return 1 if successful. Return 0
14473 if we should let the compiler generate normal code.
14475 operands[0] is the destination
14476 operands[1] is the source
14477 operands[2] is the length
14478 operands[3] is the alignment */
14480 #define MAX_MOVE_REG 4
14483 expand_block_move (rtx operands
[])
14485 rtx orig_dest
= operands
[0];
14486 rtx orig_src
= operands
[1];
14487 rtx bytes_rtx
= operands
[2];
14488 rtx align_rtx
= operands
[3];
14489 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
14494 rtx stores
[MAX_MOVE_REG
];
14497 /* If this is not a fixed size move, just call memcpy */
14501 /* This must be a fixed size alignment */
14502 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
14503 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
14505 /* Anything to move? */
14506 bytes
= INTVAL (bytes_rtx
);
14510 if (bytes
> rs6000_block_move_inline_limit
)
14513 for (offset
= 0; bytes
> 0; offset
+= move_bytes
, bytes
-= move_bytes
)
14516 rtx (*movmemsi
) (rtx
, rtx
, rtx
, rtx
);
14517 rtx (*mov
) (rtx
, rtx
);
14519 enum machine_mode mode
= BLKmode
;
14522 /* Altivec first, since it will be faster than a string move
14523 when it applies, and usually not significantly larger. */
14524 if (TARGET_ALTIVEC
&& bytes
>= 16 && align
>= 128)
14528 gen_func
.mov
= gen_movv4si
;
14530 else if (TARGET_SPE
&& bytes
>= 8 && align
>= 64)
14534 gen_func
.mov
= gen_movv2si
;
14536 else if (TARGET_STRING
14537 && bytes
> 24 /* move up to 32 bytes at a time */
14543 && ! fixed_regs
[10]
14544 && ! fixed_regs
[11]
14545 && ! fixed_regs
[12])
14547 move_bytes
= (bytes
> 32) ? 32 : bytes
;
14548 gen_func
.movmemsi
= gen_movmemsi_8reg
;
14550 else if (TARGET_STRING
14551 && bytes
> 16 /* move up to 24 bytes at a time */
14557 && ! fixed_regs
[10])
14559 move_bytes
= (bytes
> 24) ? 24 : bytes
;
14560 gen_func
.movmemsi
= gen_movmemsi_6reg
;
14562 else if (TARGET_STRING
14563 && bytes
> 8 /* move up to 16 bytes at a time */
14567 && ! fixed_regs
[8])
14569 move_bytes
= (bytes
> 16) ? 16 : bytes
;
14570 gen_func
.movmemsi
= gen_movmemsi_4reg
;
14572 else if (bytes
>= 8 && TARGET_POWERPC64
14573 /* 64-bit loads and stores require word-aligned
14575 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
14579 gen_func
.mov
= gen_movdi
;
14581 else if (TARGET_STRING
&& bytes
> 4 && !TARGET_POWERPC64
)
14582 { /* move up to 8 bytes at a time */
14583 move_bytes
= (bytes
> 8) ? 8 : bytes
;
14584 gen_func
.movmemsi
= gen_movmemsi_2reg
;
14586 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
14587 { /* move 4 bytes */
14590 gen_func
.mov
= gen_movsi
;
14592 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
14593 { /* move 2 bytes */
14596 gen_func
.mov
= gen_movhi
;
14598 else if (TARGET_STRING
&& bytes
> 1)
14599 { /* move up to 4 bytes at a time */
14600 move_bytes
= (bytes
> 4) ? 4 : bytes
;
14601 gen_func
.movmemsi
= gen_movmemsi_1reg
;
14603 else /* move 1 byte at a time */
14607 gen_func
.mov
= gen_movqi
;
14610 src
= adjust_address (orig_src
, mode
, offset
);
14611 dest
= adjust_address (orig_dest
, mode
, offset
);
14613 if (mode
!= BLKmode
)
14615 rtx tmp_reg
= gen_reg_rtx (mode
);
14617 emit_insn ((*gen_func
.mov
) (tmp_reg
, src
));
14618 stores
[num_reg
++] = (*gen_func
.mov
) (dest
, tmp_reg
);
14621 if (mode
== BLKmode
|| num_reg
>= MAX_MOVE_REG
|| bytes
== move_bytes
)
14624 for (i
= 0; i
< num_reg
; i
++)
14625 emit_insn (stores
[i
]);
14629 if (mode
== BLKmode
)
14631 /* Move the address into scratch registers. The movmemsi
14632 patterns require zero offset. */
14633 if (!REG_P (XEXP (src
, 0)))
14635 rtx src_reg
= copy_addr_to_reg (XEXP (src
, 0));
14636 src
= replace_equiv_address (src
, src_reg
);
14638 set_mem_size (src
, move_bytes
);
14640 if (!REG_P (XEXP (dest
, 0)))
14642 rtx dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
14643 dest
= replace_equiv_address (dest
, dest_reg
);
14645 set_mem_size (dest
, move_bytes
);
14647 emit_insn ((*gen_func
.movmemsi
) (dest
, src
,
14648 GEN_INT (move_bytes
& 31),
14657 /* Return a string to perform a load_multiple operation.
14658 operands[0] is the vector.
14659 operands[1] is the source address.
14660 operands[2] is the first destination register. */
14663 rs6000_output_load_multiple (rtx operands
[3])
14665 /* We have to handle the case where the pseudo used to contain the address
14666 is assigned to one of the output registers. */
14668 int words
= XVECLEN (operands
[0], 0);
14671 if (XVECLEN (operands
[0], 0) == 1)
14672 return "lwz %2,0(%1)";
14674 for (i
= 0; i
< words
; i
++)
14675 if (refers_to_regno_p (REGNO (operands
[2]) + i
,
14676 REGNO (operands
[2]) + i
+ 1, operands
[1], 0))
14680 xop
[0] = GEN_INT (4 * (words
-1));
14681 xop
[1] = operands
[1];
14682 xop
[2] = operands
[2];
14683 output_asm_insn ("lswi %2,%1,%0\n\tlwz %1,%0(%1)", xop
);
14688 xop
[0] = GEN_INT (4 * (words
-1));
14689 xop
[1] = operands
[1];
14690 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
14691 output_asm_insn ("addi %1,%1,4\n\tlswi %2,%1,%0\n\tlwz %1,-4(%1)", xop
);
14696 for (j
= 0; j
< words
; j
++)
14699 xop
[0] = GEN_INT (j
* 4);
14700 xop
[1] = operands
[1];
14701 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + j
);
14702 output_asm_insn ("lwz %2,%0(%1)", xop
);
14704 xop
[0] = GEN_INT (i
* 4);
14705 xop
[1] = operands
[1];
14706 output_asm_insn ("lwz %1,%0(%1)", xop
);
14711 return "lswi %2,%1,%N0";
14715 /* A validation routine: say whether CODE, a condition code, and MODE
14716 match. The other alternatives either don't make sense or should
14717 never be generated. */
14720 validate_condition_mode (enum rtx_code code
, enum machine_mode mode
)
14722 gcc_assert ((GET_RTX_CLASS (code
) == RTX_COMPARE
14723 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
14724 && GET_MODE_CLASS (mode
) == MODE_CC
);
14726 /* These don't make sense. */
14727 gcc_assert ((code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
)
14728 || mode
!= CCUNSmode
);
14730 gcc_assert ((code
!= GTU
&& code
!= LTU
&& code
!= GEU
&& code
!= LEU
)
14731 || mode
== CCUNSmode
);
14733 gcc_assert (mode
== CCFPmode
14734 || (code
!= ORDERED
&& code
!= UNORDERED
14735 && code
!= UNEQ
&& code
!= LTGT
14736 && code
!= UNGT
&& code
!= UNLT
14737 && code
!= UNGE
&& code
!= UNLE
));
14739 /* These should never be generated except for
14740 flag_finite_math_only. */
14741 gcc_assert (mode
!= CCFPmode
14742 || flag_finite_math_only
14743 || (code
!= LE
&& code
!= GE
14744 && code
!= UNEQ
&& code
!= LTGT
14745 && code
!= UNGT
&& code
!= UNLT
));
14747 /* These are invalid; the information is not there. */
14748 gcc_assert (mode
!= CCEQmode
|| code
== EQ
|| code
== NE
);
14752 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
14753 mask required to convert the result of a rotate insn into a shift
14754 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
14757 includes_lshift_p (rtx shiftop
, rtx andop
)
14759 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
14761 shift_mask
<<= INTVAL (shiftop
);
14763 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
14766 /* Similar, but for right shift. */
14769 includes_rshift_p (rtx shiftop
, rtx andop
)
14771 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
14773 shift_mask
>>= INTVAL (shiftop
);
14775 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
14778 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
14779 to perform a left shift. It must have exactly SHIFTOP least
14780 significant 0's, then one or more 1's, then zero or more 0's. */
14783 includes_rldic_lshift_p (rtx shiftop
, rtx andop
)
14785 if (GET_CODE (andop
) == CONST_INT
)
14787 HOST_WIDE_INT c
, lsb
, shift_mask
;
14789 c
= INTVAL (andop
);
14790 if (c
== 0 || c
== ~0)
14794 shift_mask
<<= INTVAL (shiftop
);
14796 /* Find the least significant one bit. */
14799 /* It must coincide with the LSB of the shift mask. */
14800 if (-lsb
!= shift_mask
)
14803 /* Invert to look for the next transition (if any). */
14806 /* Remove the low group of ones (originally low group of zeros). */
14809 /* Again find the lsb, and check we have all 1's above. */
14817 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
14818 to perform a left shift. It must have SHIFTOP or more least
14819 significant 0's, with the remainder of the word 1's. */
14822 includes_rldicr_lshift_p (rtx shiftop
, rtx andop
)
14824 if (GET_CODE (andop
) == CONST_INT
)
14826 HOST_WIDE_INT c
, lsb
, shift_mask
;
14829 shift_mask
<<= INTVAL (shiftop
);
14830 c
= INTVAL (andop
);
14832 /* Find the least significant one bit. */
14835 /* It must be covered by the shift mask.
14836 This test also rejects c == 0. */
14837 if ((lsb
& shift_mask
) == 0)
14840 /* Check we have all 1's above the transition, and reject all 1's. */
14841 return c
== -lsb
&& lsb
!= 1;
14847 /* Return 1 if operands will generate a valid arguments to rlwimi
14848 instruction for insert with right shift in 64-bit mode. The mask may
14849 not start on the first bit or stop on the last bit because wrap-around
14850 effects of instruction do not correspond to semantics of RTL insn. */
14853 insvdi_rshift_rlwimi_p (rtx sizeop
, rtx startop
, rtx shiftop
)
14855 if (INTVAL (startop
) > 32
14856 && INTVAL (startop
) < 64
14857 && INTVAL (sizeop
) > 1
14858 && INTVAL (sizeop
) + INTVAL (startop
) < 64
14859 && INTVAL (shiftop
) > 0
14860 && INTVAL (sizeop
) + INTVAL (shiftop
) < 32
14861 && (64 - (INTVAL (shiftop
) & 63)) >= INTVAL (sizeop
))
14867 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
14868 for lfq and stfq insns iff the registers are hard registers. */
14871 registers_ok_for_quad_peep (rtx reg1
, rtx reg2
)
14873 /* We might have been passed a SUBREG. */
14874 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
14877 /* We might have been passed non floating point registers. */
14878 if (!FP_REGNO_P (REGNO (reg1
))
14879 || !FP_REGNO_P (REGNO (reg2
)))
14882 return (REGNO (reg1
) == REGNO (reg2
) - 1);
14885 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
14886 addr1 and addr2 must be in consecutive memory locations
14887 (addr2 == addr1 + 8). */
14890 mems_ok_for_quad_peep (rtx mem1
, rtx mem2
)
14893 unsigned int reg1
, reg2
;
14894 int offset1
, offset2
;
14896 /* The mems cannot be volatile. */
14897 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
14900 addr1
= XEXP (mem1
, 0);
14901 addr2
= XEXP (mem2
, 0);
14903 /* Extract an offset (if used) from the first addr. */
14904 if (GET_CODE (addr1
) == PLUS
)
14906 /* If not a REG, return zero. */
14907 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
14911 reg1
= REGNO (XEXP (addr1
, 0));
14912 /* The offset must be constant! */
14913 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
14915 offset1
= INTVAL (XEXP (addr1
, 1));
14918 else if (GET_CODE (addr1
) != REG
)
14922 reg1
= REGNO (addr1
);
14923 /* This was a simple (mem (reg)) expression. Offset is 0. */
14927 /* And now for the second addr. */
14928 if (GET_CODE (addr2
) == PLUS
)
14930 /* If not a REG, return zero. */
14931 if (GET_CODE (XEXP (addr2
, 0)) != REG
)
14935 reg2
= REGNO (XEXP (addr2
, 0));
14936 /* The offset must be constant. */
14937 if (GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
14939 offset2
= INTVAL (XEXP (addr2
, 1));
14942 else if (GET_CODE (addr2
) != REG
)
14946 reg2
= REGNO (addr2
);
14947 /* This was a simple (mem (reg)) expression. Offset is 0. */
14951 /* Both of these must have the same base register. */
14955 /* The offset for the second addr must be 8 more than the first addr. */
14956 if (offset2
!= offset1
+ 8)
14959 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
14966 rs6000_secondary_memory_needed_rtx (enum machine_mode mode
)
14968 static bool eliminated
= false;
14971 if (mode
!= SDmode
|| TARGET_NO_SDMODE_STACK
)
14972 ret
= assign_stack_local (mode
, GET_MODE_SIZE (mode
), 0);
14975 rtx mem
= cfun
->machine
->sdmode_stack_slot
;
14976 gcc_assert (mem
!= NULL_RTX
);
14980 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
14981 cfun
->machine
->sdmode_stack_slot
= mem
;
14987 if (TARGET_DEBUG_ADDR
)
14989 fprintf (stderr
, "\nrs6000_secondary_memory_needed_rtx, mode %s, rtx:\n",
14990 GET_MODE_NAME (mode
));
14992 fprintf (stderr
, "\tNULL_RTX\n");
15000 /* Return the mode to be used for memory when a secondary memory
15001 location is needed. For SDmode values we need to use DDmode, in
15002 all other cases we can use the same mode. */
15004 rs6000_secondary_memory_needed_mode (enum machine_mode mode
)
15006 if (mode
== SDmode
)
15012 rs6000_check_sdmode (tree
*tp
, int *walk_subtrees
, void *data ATTRIBUTE_UNUSED
)
15014 /* Don't walk into types. */
15015 if (*tp
== NULL_TREE
|| *tp
== error_mark_node
|| TYPE_P (*tp
))
15017 *walk_subtrees
= 0;
15021 switch (TREE_CODE (*tp
))
15030 case VIEW_CONVERT_EXPR
:
15031 if (TYPE_MODE (TREE_TYPE (*tp
)) == SDmode
)
15041 /* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
15042 on traditional floating point registers, and the VMRGOW/VMRGEW instructions
15043 only work on the traditional altivec registers, note if an altivec register
15046 static enum rs6000_reg_type
15047 register_to_reg_type (rtx reg
, bool *is_altivec
)
15049 HOST_WIDE_INT regno
;
15050 enum reg_class rclass
;
15052 if (GET_CODE (reg
) == SUBREG
)
15053 reg
= SUBREG_REG (reg
);
15056 return NO_REG_TYPE
;
15058 regno
= REGNO (reg
);
15059 if (regno
>= FIRST_PSEUDO_REGISTER
)
15061 if (!lra_in_progress
&& !reload_in_progress
&& !reload_completed
)
15062 return PSEUDO_REG_TYPE
;
15064 regno
= true_regnum (reg
);
15065 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
15066 return PSEUDO_REG_TYPE
;
15069 gcc_assert (regno
>= 0);
15071 if (is_altivec
&& ALTIVEC_REGNO_P (regno
))
15072 *is_altivec
= true;
15074 rclass
= rs6000_regno_regclass
[regno
];
15075 return reg_class_to_reg_type
[(int)rclass
];
15078 /* Helper function for rs6000_secondary_reload to return true if a move to a
15079 different register classe is really a simple move. */
15082 rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type
,
15083 enum rs6000_reg_type from_type
,
15084 enum machine_mode mode
)
15088 /* Add support for various direct moves available. In this function, we only
15089 look at cases where we don't need any extra registers, and one or more
15090 simple move insns are issued. At present, 32-bit integers are not allowed
15091 in FPR/VSX registers. Single precision binary floating is not a simple
15092 move because we need to convert to the single precision memory layout.
15093 The 4-byte SDmode can be moved. */
15094 size
= GET_MODE_SIZE (mode
);
15095 if (TARGET_DIRECT_MOVE
15096 && ((mode
== SDmode
) || (TARGET_POWERPC64
&& size
== 8))
15097 && ((to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
15098 || (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
15101 else if (TARGET_MFPGPR
&& TARGET_POWERPC64
&& size
== 8
15102 && ((to_type
== GPR_REG_TYPE
&& from_type
== FPR_REG_TYPE
)
15103 || (to_type
== FPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
15106 else if ((size
== 4 || (TARGET_POWERPC64
&& size
== 8))
15107 && ((to_type
== GPR_REG_TYPE
&& from_type
== SPR_REG_TYPE
)
15108 || (to_type
== SPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
15114 /* Power8 helper function for rs6000_secondary_reload, handle all of the
15115 special direct moves that involve allocating an extra register, return the
15116 insn code of the helper function if there is such a function or
15117 CODE_FOR_nothing if not. */
15120 rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type
,
15121 enum rs6000_reg_type from_type
,
15122 enum machine_mode mode
,
15123 secondary_reload_info
*sri
,
15127 enum insn_code icode
= CODE_FOR_nothing
;
15129 int size
= GET_MODE_SIZE (mode
);
15131 if (TARGET_POWERPC64
)
15135 /* Handle moving 128-bit values from GPRs to VSX point registers on
15136 power8 when running in 64-bit mode using XXPERMDI to glue the two
15137 64-bit values back together. */
15138 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
15140 cost
= 3; /* 2 mtvsrd's, 1 xxpermdi. */
15141 icode
= reg_addr
[mode
].reload_vsx_gpr
;
15144 /* Handle moving 128-bit values from VSX point registers to GPRs on
15145 power8 when running in 64-bit mode using XXPERMDI to get access to the
15146 bottom 64-bit value. */
15147 else if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
15149 cost
= 3; /* 2 mfvsrd's, 1 xxpermdi. */
15150 icode
= reg_addr
[mode
].reload_gpr_vsx
;
15154 else if (mode
== SFmode
)
15156 if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
15158 cost
= 3; /* xscvdpspn, mfvsrd, and. */
15159 icode
= reg_addr
[mode
].reload_gpr_vsx
;
15162 else if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
15164 cost
= 2; /* mtvsrz, xscvspdpn. */
15165 icode
= reg_addr
[mode
].reload_vsx_gpr
;
15170 if (TARGET_POWERPC64
&& size
== 16)
15172 /* Handle moving 128-bit values from GPRs to VSX point registers on
15173 power8 when running in 64-bit mode using XXPERMDI to glue the two
15174 64-bit values back together. */
15175 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
15177 cost
= 3; /* 2 mtvsrd's, 1 xxpermdi. */
15178 icode
= reg_addr
[mode
].reload_vsx_gpr
;
15181 /* Handle moving 128-bit values from VSX point registers to GPRs on
15182 power8 when running in 64-bit mode using XXPERMDI to get access to the
15183 bottom 64-bit value. */
15184 else if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
15186 cost
= 3; /* 2 mfvsrd's, 1 xxpermdi. */
15187 icode
= reg_addr
[mode
].reload_gpr_vsx
;
15191 else if (!TARGET_POWERPC64
&& size
== 8)
15193 /* Handle moving 64-bit values from GPRs to floating point registers on
15194 power8 when running in 32-bit mode using FMRGOW to glue the two 32-bit
15195 values back together. Altivec register classes must be handled
15196 specially since a different instruction is used, and the secondary
15197 reload support requires a single instruction class in the scratch
15198 register constraint. However, right now TFmode is not allowed in
15199 Altivec registers, so the pattern will never match. */
15200 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
&& !altivec_p
)
15202 cost
= 3; /* 2 mtvsrwz's, 1 fmrgow. */
15203 icode
= reg_addr
[mode
].reload_fpr_gpr
;
15207 if (icode
!= CODE_FOR_nothing
)
15212 sri
->icode
= icode
;
15213 sri
->extra_cost
= cost
;
15220 /* Return whether a move between two register classes can be done either
15221 directly (simple move) or via a pattern that uses a single extra temporary
15222 (using power8's direct move in this case. */
15225 rs6000_secondary_reload_move (enum rs6000_reg_type to_type
,
15226 enum rs6000_reg_type from_type
,
15227 enum machine_mode mode
,
15228 secondary_reload_info
*sri
,
15231 /* Fall back to load/store reloads if either type is not a register. */
15232 if (to_type
== NO_REG_TYPE
|| from_type
== NO_REG_TYPE
)
15235 /* If we haven't allocated registers yet, assume the move can be done for the
15236 standard register types. */
15237 if ((to_type
== PSEUDO_REG_TYPE
&& from_type
== PSEUDO_REG_TYPE
)
15238 || (to_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (from_type
))
15239 || (from_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (to_type
)))
15242 /* Moves to the same set of registers is a simple move for non-specialized
15244 if (to_type
== from_type
&& IS_STD_REG_TYPE (to_type
))
15247 /* Check whether a simple move can be done directly. */
15248 if (rs6000_secondary_reload_simple_move (to_type
, from_type
, mode
))
15252 sri
->icode
= CODE_FOR_nothing
;
15253 sri
->extra_cost
= 0;
15258 /* Now check if we can do it in a few steps. */
15259 return rs6000_secondary_reload_direct_move (to_type
, from_type
, mode
, sri
,
15263 /* Inform reload about cases where moving X with a mode MODE to a register in
15264 RCLASS requires an extra scratch or immediate register. Return the class
15265 needed for the immediate register.
15267 For VSX and Altivec, we may need a register to convert sp+offset into
15270 For misaligned 64-bit gpr loads and stores we need a register to
15271 convert an offset address to indirect. */
15274 rs6000_secondary_reload (bool in_p
,
15276 reg_class_t rclass_i
,
15277 enum machine_mode mode
,
15278 secondary_reload_info
*sri
)
15280 enum reg_class rclass
= (enum reg_class
) rclass_i
;
15281 reg_class_t ret
= ALL_REGS
;
15282 enum insn_code icode
;
15283 bool default_p
= false;
15285 sri
->icode
= CODE_FOR_nothing
;
15287 ? reg_addr
[mode
].reload_load
15288 : reg_addr
[mode
].reload_store
);
15290 if (REG_P (x
) || register_operand (x
, mode
))
15292 enum rs6000_reg_type to_type
= reg_class_to_reg_type
[(int)rclass
];
15293 bool altivec_p
= (rclass
== ALTIVEC_REGS
);
15294 enum rs6000_reg_type from_type
= register_to_reg_type (x
, &altivec_p
);
15298 enum rs6000_reg_type exchange
= to_type
;
15299 to_type
= from_type
;
15300 from_type
= exchange
;
15303 /* Can we do a direct move of some sort? */
15304 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
, sri
,
15307 icode
= (enum insn_code
)sri
->icode
;
15313 /* Handle vector moves with reload helper functions. */
15314 if (ret
== ALL_REGS
&& icode
!= CODE_FOR_nothing
)
15317 sri
->icode
= CODE_FOR_nothing
;
15318 sri
->extra_cost
= 0;
15320 if (GET_CODE (x
) == MEM
)
15322 rtx addr
= XEXP (x
, 0);
15324 /* Loads to and stores from gprs can do reg+offset, and wouldn't need
15325 an extra register in that case, but it would need an extra
15326 register if the addressing is reg+reg or (reg+reg)&(-16). Special
15327 case load/store quad. */
15328 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
)
15330 if (TARGET_POWERPC64
&& TARGET_QUAD_MEMORY
15331 && GET_MODE_SIZE (mode
) == 16
15332 && quad_memory_operand (x
, mode
))
15334 sri
->icode
= icode
;
15335 sri
->extra_cost
= 2;
15338 else if (!legitimate_indirect_address_p (addr
, false)
15339 && !rs6000_legitimate_offset_address_p (PTImode
, addr
,
15342 sri
->icode
= icode
;
15343 /* account for splitting the loads, and converting the
15344 address from reg+reg to reg. */
15345 sri
->extra_cost
= (((TARGET_64BIT
) ? 3 : 5)
15346 + ((GET_CODE (addr
) == AND
) ? 1 : 0));
15349 /* Allow scalar loads to/from the traditional floating point
15350 registers, even if VSX memory is set. */
15351 else if ((rclass
== FLOAT_REGS
|| rclass
== NO_REGS
)
15352 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8)
15353 && (legitimate_indirect_address_p (addr
, false)
15354 || legitimate_indirect_address_p (addr
, false)
15355 || rs6000_legitimate_offset_address_p (mode
, addr
,
15359 /* Loads to and stores from vector registers can only do reg+reg
15360 addressing. Altivec registers can also do (reg+reg)&(-16). Allow
15361 scalar modes loading up the traditional floating point registers
15362 to use offset addresses. */
15363 else if (rclass
== VSX_REGS
|| rclass
== ALTIVEC_REGS
15364 || rclass
== FLOAT_REGS
|| rclass
== NO_REGS
)
15366 if (!VECTOR_MEM_ALTIVEC_P (mode
)
15367 && GET_CODE (addr
) == AND
15368 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
15369 && INTVAL (XEXP (addr
, 1)) == -16
15370 && (legitimate_indirect_address_p (XEXP (addr
, 0), false)
15371 || legitimate_indexed_address_p (XEXP (addr
, 0), false)))
15373 sri
->icode
= icode
;
15374 sri
->extra_cost
= ((GET_CODE (XEXP (addr
, 0)) == PLUS
)
15377 else if (!legitimate_indirect_address_p (addr
, false)
15378 && (rclass
== NO_REGS
15379 || !legitimate_indexed_address_p (addr
, false)))
15381 sri
->icode
= icode
;
15382 sri
->extra_cost
= 1;
15385 icode
= CODE_FOR_nothing
;
15387 /* Any other loads, including to pseudo registers which haven't been
15388 assigned to a register yet, default to require a scratch
15392 sri
->icode
= icode
;
15393 sri
->extra_cost
= 2;
15396 else if (REG_P (x
))
15398 int regno
= true_regnum (x
);
15400 icode
= CODE_FOR_nothing
;
15401 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
15405 enum reg_class xclass
= REGNO_REG_CLASS (regno
);
15406 enum rs6000_reg_type rtype1
= reg_class_to_reg_type
[(int)rclass
];
15407 enum rs6000_reg_type rtype2
= reg_class_to_reg_type
[(int)xclass
];
15409 /* If memory is needed, use default_secondary_reload to create the
15411 if (rtype1
!= rtype2
|| !IS_STD_REG_TYPE (rtype1
))
15420 else if (TARGET_POWERPC64
15421 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
15423 && GET_MODE_SIZE (GET_MODE (x
)) >= UNITS_PER_WORD
)
15425 rtx addr
= XEXP (x
, 0);
15426 rtx off
= address_offset (addr
);
15428 if (off
!= NULL_RTX
)
15430 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
15431 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
15433 /* We need a secondary reload when our legitimate_address_p
15434 says the address is good (as otherwise the entire address
15435 will be reloaded), and the offset is not a multiple of
15436 four or we have an address wrap. Address wrap will only
15437 occur for LO_SUMs since legitimate_offset_address_p
15438 rejects addresses for 16-byte mems that will wrap. */
15439 if (GET_CODE (addr
) == LO_SUM
15440 ? (1 /* legitimate_address_p allows any offset for lo_sum */
15441 && ((offset
& 3) != 0
15442 || ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
))
15443 : (offset
+ 0x8000 < 0x10000 - extra
/* legitimate_address_p */
15444 && (offset
& 3) != 0))
15447 sri
->icode
= CODE_FOR_reload_di_load
;
15449 sri
->icode
= CODE_FOR_reload_di_store
;
15450 sri
->extra_cost
= 2;
15459 else if (!TARGET_POWERPC64
15460 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
15462 && GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
15464 rtx addr
= XEXP (x
, 0);
15465 rtx off
= address_offset (addr
);
15467 if (off
!= NULL_RTX
)
15469 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
15470 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
15472 /* We need a secondary reload when our legitimate_address_p
15473 says the address is good (as otherwise the entire address
15474 will be reloaded), and we have a wrap.
15476 legitimate_lo_sum_address_p allows LO_SUM addresses to
15477 have any offset so test for wrap in the low 16 bits.
15479 legitimate_offset_address_p checks for the range
15480 [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
15481 for mode size of 16. We wrap at [0x7ffc,0x7fff] and
15482 [0x7ff4,0x7fff] respectively, so test for the
15483 intersection of these ranges, [0x7ffc,0x7fff] and
15484 [0x7ff4,0x7ff7] respectively.
15486 Note that the address we see here may have been
15487 manipulated by legitimize_reload_address. */
15488 if (GET_CODE (addr
) == LO_SUM
15489 ? ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
15490 : offset
- (0x8000 - extra
) < UNITS_PER_WORD
)
15493 sri
->icode
= CODE_FOR_reload_si_load
;
15495 sri
->icode
= CODE_FOR_reload_si_store
;
15496 sri
->extra_cost
= 2;
15509 ret
= default_secondary_reload (in_p
, x
, rclass
, mode
, sri
);
15511 gcc_assert (ret
!= ALL_REGS
);
15513 if (TARGET_DEBUG_ADDR
)
15516 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
15518 reg_class_names
[ret
],
15519 in_p
? "true" : "false",
15520 reg_class_names
[rclass
],
15521 GET_MODE_NAME (mode
));
15524 fprintf (stderr
, ", default secondary reload");
15526 if (sri
->icode
!= CODE_FOR_nothing
)
15527 fprintf (stderr
, ", reload func = %s, extra cost = %d\n",
15528 insn_data
[sri
->icode
].name
, sri
->extra_cost
);
15530 fprintf (stderr
, "\n");
15538 /* Better tracing for rs6000_secondary_reload_inner. */
15541 rs6000_secondary_reload_trace (int line
, rtx reg
, rtx mem
, rtx scratch
,
15546 gcc_assert (reg
!= NULL_RTX
&& mem
!= NULL_RTX
&& scratch
!= NULL_RTX
);
15548 fprintf (stderr
, "rs6000_secondary_reload_inner:%d, type = %s\n", line
,
15549 store_p
? "store" : "load");
15552 set
= gen_rtx_SET (VOIDmode
, mem
, reg
);
15554 set
= gen_rtx_SET (VOIDmode
, reg
, mem
);
15556 clobber
= gen_rtx_CLOBBER (VOIDmode
, scratch
);
15557 debug_rtx (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
15561 rs6000_secondary_reload_fail (int line
, rtx reg
, rtx mem
, rtx scratch
,
15564 rs6000_secondary_reload_trace (line
, reg
, mem
, scratch
, store_p
);
15565 gcc_unreachable ();
15568 /* Fixup reload addresses for Altivec or VSX loads/stores to change SP+offset
15569 to SP+reg addressing. */
15572 rs6000_secondary_reload_inner (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
15574 int regno
= true_regnum (reg
);
15575 enum machine_mode mode
= GET_MODE (reg
);
15576 enum reg_class rclass
;
15578 rtx and_op2
= NULL_RTX
;
15581 rtx scratch_or_premodify
= scratch
;
15585 if (TARGET_DEBUG_ADDR
)
15586 rs6000_secondary_reload_trace (__LINE__
, reg
, mem
, scratch
, store_p
);
15588 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
15589 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
15591 if (GET_CODE (mem
) != MEM
)
15592 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
15594 rclass
= REGNO_REG_CLASS (regno
);
15595 addr
= XEXP (mem
, 0);
15599 /* GPRs can handle reg + small constant, all other addresses need to use
15600 the scratch register. */
15603 if (GET_CODE (addr
) == AND
)
15605 and_op2
= XEXP (addr
, 1);
15606 addr
= XEXP (addr
, 0);
15609 if (GET_CODE (addr
) == PRE_MODIFY
)
15611 scratch_or_premodify
= XEXP (addr
, 0);
15612 if (!REG_P (scratch_or_premodify
))
15613 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
15615 if (GET_CODE (XEXP (addr
, 1)) != PLUS
)
15616 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
15618 addr
= XEXP (addr
, 1);
15621 if (GET_CODE (addr
) == PLUS
15622 && (and_op2
!= NULL_RTX
15623 || !rs6000_legitimate_offset_address_p (PTImode
, addr
,
15626 addr_op1
= XEXP (addr
, 0);
15627 addr_op2
= XEXP (addr
, 1);
15628 if (!legitimate_indirect_address_p (addr_op1
, false))
15629 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
15631 if (!REG_P (addr_op2
)
15632 && (GET_CODE (addr_op2
) != CONST_INT
15633 || !satisfies_constraint_I (addr_op2
)))
15635 if (TARGET_DEBUG_ADDR
)
15638 "\nMove plus addr to register %s, mode = %s: ",
15639 rs6000_reg_names
[REGNO (scratch
)],
15640 GET_MODE_NAME (mode
));
15641 debug_rtx (addr_op2
);
15643 rs6000_emit_move (scratch
, addr_op2
, Pmode
);
15644 addr_op2
= scratch
;
15647 emit_insn (gen_rtx_SET (VOIDmode
,
15648 scratch_or_premodify
,
15649 gen_rtx_PLUS (Pmode
,
15653 addr
= scratch_or_premodify
;
15654 scratch_or_premodify
= scratch
;
15656 else if (!legitimate_indirect_address_p (addr
, false)
15657 && !rs6000_legitimate_offset_address_p (PTImode
, addr
,
15660 if (TARGET_DEBUG_ADDR
)
15662 fprintf (stderr
, "\nMove addr to register %s, mode = %s: ",
15663 rs6000_reg_names
[REGNO (scratch_or_premodify
)],
15664 GET_MODE_NAME (mode
));
15667 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
15668 addr
= scratch_or_premodify
;
15669 scratch_or_premodify
= scratch
;
15673 /* Float registers can do offset+reg addressing for scalar types. */
15675 if (legitimate_indirect_address_p (addr
, false) /* reg */
15676 || legitimate_indexed_address_p (addr
, false) /* reg+reg */
15677 || ((GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8)
15678 && and_op2
== NULL_RTX
15679 && scratch_or_premodify
== scratch
15680 && rs6000_legitimate_offset_address_p (mode
, addr
, false, false)))
15683 /* If this isn't a legacy floating point load/store, fall through to the
15686 /* VSX/Altivec registers can only handle reg+reg addressing. Move other
15687 addresses into a scratch register. */
15691 /* With float regs, we need to handle the AND ourselves, since we can't
15692 use the Altivec instruction with an implicit AND -16. Allow scalar
15693 loads to float registers to use reg+offset even if VSX. */
15694 if (GET_CODE (addr
) == AND
15695 && (rclass
!= ALTIVEC_REGS
|| GET_MODE_SIZE (mode
) != 16
15696 || GET_CODE (XEXP (addr
, 1)) != CONST_INT
15697 || INTVAL (XEXP (addr
, 1)) != -16
15698 || !VECTOR_MEM_ALTIVEC_P (mode
)))
15700 and_op2
= XEXP (addr
, 1);
15701 addr
= XEXP (addr
, 0);
15704 /* If we aren't using a VSX load, save the PRE_MODIFY register and use it
15705 as the address later. */
15706 if (GET_CODE (addr
) == PRE_MODIFY
15707 && ((ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
15708 && (rclass
!= FLOAT_REGS
15709 || (GET_MODE_SIZE (mode
) != 4 && GET_MODE_SIZE (mode
) != 8)))
15710 || and_op2
!= NULL_RTX
15711 || !legitimate_indexed_address_p (XEXP (addr
, 1), false)))
15713 scratch_or_premodify
= XEXP (addr
, 0);
15714 if (!legitimate_indirect_address_p (scratch_or_premodify
, false))
15715 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
15717 if (GET_CODE (XEXP (addr
, 1)) != PLUS
)
15718 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
15720 addr
= XEXP (addr
, 1);
15723 if (legitimate_indirect_address_p (addr
, false) /* reg */
15724 || legitimate_indexed_address_p (addr
, false) /* reg+reg */
15725 || (GET_CODE (addr
) == AND
/* Altivec memory */
15726 && rclass
== ALTIVEC_REGS
15727 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
15728 && INTVAL (XEXP (addr
, 1)) == -16
15729 && (legitimate_indirect_address_p (XEXP (addr
, 0), false)
15730 || legitimate_indexed_address_p (XEXP (addr
, 0), false))))
15733 else if (GET_CODE (addr
) == PLUS
)
15735 addr_op1
= XEXP (addr
, 0);
15736 addr_op2
= XEXP (addr
, 1);
15737 if (!REG_P (addr_op1
))
15738 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
15740 if (TARGET_DEBUG_ADDR
)
15742 fprintf (stderr
, "\nMove plus addr to register %s, mode = %s: ",
15743 rs6000_reg_names
[REGNO (scratch
)], GET_MODE_NAME (mode
));
15744 debug_rtx (addr_op2
);
15746 rs6000_emit_move (scratch
, addr_op2
, Pmode
);
15747 emit_insn (gen_rtx_SET (VOIDmode
,
15748 scratch_or_premodify
,
15749 gen_rtx_PLUS (Pmode
,
15752 addr
= scratch_or_premodify
;
15753 scratch_or_premodify
= scratch
;
15756 else if (GET_CODE (addr
) == SYMBOL_REF
|| GET_CODE (addr
) == CONST
15757 || GET_CODE (addr
) == CONST_INT
|| GET_CODE (addr
) == LO_SUM
15760 if (TARGET_DEBUG_ADDR
)
15762 fprintf (stderr
, "\nMove addr to register %s, mode = %s: ",
15763 rs6000_reg_names
[REGNO (scratch_or_premodify
)],
15764 GET_MODE_NAME (mode
));
15768 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
15769 addr
= scratch_or_premodify
;
15770 scratch_or_premodify
= scratch
;
15774 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
15779 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
15782 /* If the original address involved a pre-modify that we couldn't use the VSX
15783 memory instruction with update, and we haven't taken care of already,
15784 store the address in the pre-modify register and use that as the
15786 if (scratch_or_premodify
!= scratch
&& scratch_or_premodify
!= addr
)
15788 emit_insn (gen_rtx_SET (VOIDmode
, scratch_or_premodify
, addr
));
15789 addr
= scratch_or_premodify
;
15792 /* If the original address involved an AND -16 and we couldn't use an ALTIVEC
15793 memory instruction, recreate the AND now, including the clobber which is
15794 generated by the general ANDSI3/ANDDI3 patterns for the
15795 andi. instruction. */
15796 if (and_op2
!= NULL_RTX
)
15798 if (! legitimate_indirect_address_p (addr
, false))
15800 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, addr
));
15804 if (TARGET_DEBUG_ADDR
)
15806 fprintf (stderr
, "\nAnd addr to register %s, mode = %s: ",
15807 rs6000_reg_names
[REGNO (scratch
)], GET_MODE_NAME (mode
));
15808 debug_rtx (and_op2
);
15811 and_rtx
= gen_rtx_SET (VOIDmode
,
15813 gen_rtx_AND (Pmode
,
15817 cc_clobber
= gen_rtx_CLOBBER (CCmode
, gen_rtx_SCRATCH (CCmode
));
15818 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
15819 gen_rtvec (2, and_rtx
, cc_clobber
)));
15823 /* Adjust the address if it changed. */
15824 if (addr
!= XEXP (mem
, 0))
15826 mem
= replace_equiv_address_nv (mem
, addr
);
15827 if (TARGET_DEBUG_ADDR
)
15828 fprintf (stderr
, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
15831 /* Now create the move. */
15833 emit_insn (gen_rtx_SET (VOIDmode
, mem
, reg
));
15835 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
15840 /* Convert reloads involving 64-bit gprs and misaligned offset
15841 addressing, or multiple 32-bit gprs and offsets that are too large,
15842 to use indirect addressing. */
15845 rs6000_secondary_reload_gpr (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
15847 int regno
= true_regnum (reg
);
15848 enum reg_class rclass
;
15850 rtx scratch_or_premodify
= scratch
;
15852 if (TARGET_DEBUG_ADDR
)
15854 fprintf (stderr
, "\nrs6000_secondary_reload_gpr, type = %s\n",
15855 store_p
? "store" : "load");
15856 fprintf (stderr
, "reg:\n");
15858 fprintf (stderr
, "mem:\n");
15860 fprintf (stderr
, "scratch:\n");
15861 debug_rtx (scratch
);
15864 gcc_assert (regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
);
15865 gcc_assert (GET_CODE (mem
) == MEM
);
15866 rclass
= REGNO_REG_CLASS (regno
);
15867 gcc_assert (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
);
15868 addr
= XEXP (mem
, 0);
15870 if (GET_CODE (addr
) == PRE_MODIFY
)
15872 scratch_or_premodify
= XEXP (addr
, 0);
15873 gcc_assert (REG_P (scratch_or_premodify
));
15874 addr
= XEXP (addr
, 1);
15876 gcc_assert (GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
);
15878 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
15880 mem
= replace_equiv_address_nv (mem
, scratch_or_premodify
);
15882 /* Now create the move. */
15884 emit_insn (gen_rtx_SET (VOIDmode
, mem
, reg
));
15886 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
15891 /* Allocate a 64-bit stack slot to be used for copying SDmode values through if
15892 this function has any SDmode references. If we are on a power7 or later, we
15893 don't need the 64-bit stack slot since the LFIWZX and STIFWX instructions
15894 can load/store the value. */
15897 rs6000_alloc_sdmode_stack_slot (void)
15901 gimple_stmt_iterator gsi
;
15903 gcc_assert (cfun
->machine
->sdmode_stack_slot
== NULL_RTX
);
15904 /* We use a different approach for dealing with the secondary
15909 if (TARGET_NO_SDMODE_STACK
)
15913 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
15915 tree ret
= walk_gimple_op (gsi_stmt (gsi
), rs6000_check_sdmode
, NULL
);
15918 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
15919 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
15925 /* Check for any SDmode parameters of the function. */
15926 for (t
= DECL_ARGUMENTS (cfun
->decl
); t
; t
= DECL_CHAIN (t
))
15928 if (TREE_TYPE (t
) == error_mark_node
)
15931 if (TYPE_MODE (TREE_TYPE (t
)) == SDmode
15932 || TYPE_MODE (DECL_ARG_TYPE (t
)) == SDmode
)
15934 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
15935 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
15943 rs6000_instantiate_decls (void)
15945 if (cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
15946 instantiate_decl_rtl (cfun
->machine
->sdmode_stack_slot
);
15949 /* Given an rtx X being reloaded into a reg required to be
15950 in class CLASS, return the class of reg to actually use.
15951 In general this is just CLASS; but on some machines
15952 in some cases it is preferable to use a more restrictive class.
15954 On the RS/6000, we have to return NO_REGS when we want to reload a
15955 floating-point CONST_DOUBLE to force it to be copied to memory.
15957 We also don't want to reload integer values into floating-point
15958 registers if we can at all help it. In fact, this can
15959 cause reload to die, if it tries to generate a reload of CTR
15960 into a FP register and discovers it doesn't have the memory location
15963 ??? Would it be a good idea to have reload do the converse, that is
15964 try to reload floating modes into FP registers if possible?
15967 static enum reg_class
15968 rs6000_preferred_reload_class (rtx x
, enum reg_class rclass
)
15970 enum machine_mode mode
= GET_MODE (x
);
15972 if (TARGET_VSX
&& x
== CONST0_RTX (mode
) && VSX_REG_CLASS_P (rclass
))
15975 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
15976 && (rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
15977 && easy_vector_constant (x
, mode
))
15978 return ALTIVEC_REGS
;
15980 if (CONSTANT_P (x
) && reg_classes_intersect_p (rclass
, FLOAT_REGS
))
15983 if (GET_MODE_CLASS (mode
) == MODE_INT
&& rclass
== NON_SPECIAL_REGS
)
15984 return GENERAL_REGS
;
15986 /* For VSX, prefer the traditional registers for 64-bit values because we can
15987 use the non-VSX loads. Prefer the Altivec registers if Altivec is
15988 handling the vector operations (i.e. V16QI, V8HI, and V4SI), or if we
15989 prefer Altivec loads.. */
15990 if (rclass
== VSX_REGS
)
15992 if (GET_MODE_SIZE (mode
) <= 8)
15995 if (VECTOR_UNIT_ALTIVEC_P (mode
) || VECTOR_MEM_ALTIVEC_P (mode
))
15996 return ALTIVEC_REGS
;
16004 /* Debug version of rs6000_preferred_reload_class. */
16005 static enum reg_class
16006 rs6000_debug_preferred_reload_class (rtx x
, enum reg_class rclass
)
16008 enum reg_class ret
= rs6000_preferred_reload_class (x
, rclass
);
16011 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
16013 reg_class_names
[ret
], reg_class_names
[rclass
],
16014 GET_MODE_NAME (GET_MODE (x
)));
16020 /* If we are copying between FP or AltiVec registers and anything else, we need
16021 a memory location. The exception is when we are targeting ppc64 and the
16022 move to/from fpr to gpr instructions are available. Also, under VSX, you
16023 can copy vector registers from the FP register set to the Altivec register
16024 set and vice versa. */
16027 rs6000_secondary_memory_needed (enum reg_class from_class
,
16028 enum reg_class to_class
,
16029 enum machine_mode mode
)
16031 enum rs6000_reg_type from_type
, to_type
;
16032 bool altivec_p
= ((from_class
== ALTIVEC_REGS
)
16033 || (to_class
== ALTIVEC_REGS
));
16035 /* If a simple/direct move is available, we don't need secondary memory */
16036 from_type
= reg_class_to_reg_type
[(int)from_class
];
16037 to_type
= reg_class_to_reg_type
[(int)to_class
];
16039 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
,
16040 (secondary_reload_info
*)0, altivec_p
))
16043 /* If we have a floating point or vector register class, we need to use
16044 memory to transfer the data. */
16045 if (IS_FP_VECT_REG_TYPE (from_type
) || IS_FP_VECT_REG_TYPE (to_type
))
16051 /* Debug version of rs6000_secondary_memory_needed. */
16053 rs6000_debug_secondary_memory_needed (enum reg_class from_class
,
16054 enum reg_class to_class
,
16055 enum machine_mode mode
)
16057 bool ret
= rs6000_secondary_memory_needed (from_class
, to_class
, mode
);
16060 "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
16061 "to_class = %s, mode = %s\n",
16062 ret
? "true" : "false",
16063 reg_class_names
[from_class
],
16064 reg_class_names
[to_class
],
16065 GET_MODE_NAME (mode
));
16070 /* Return the register class of a scratch register needed to copy IN into
16071 or out of a register in RCLASS in MODE. If it can be done directly,
16072 NO_REGS is returned. */
16074 static enum reg_class
16075 rs6000_secondary_reload_class (enum reg_class rclass
, enum machine_mode mode
,
16080 if (TARGET_ELF
|| (DEFAULT_ABI
== ABI_DARWIN
16082 && MACHOPIC_INDIRECT
16086 /* We cannot copy a symbolic operand directly into anything
16087 other than BASE_REGS for TARGET_ELF. So indicate that a
16088 register from BASE_REGS is needed as an intermediate
16091 On Darwin, pic addresses require a load from memory, which
16092 needs a base register. */
16093 if (rclass
!= BASE_REGS
16094 && (GET_CODE (in
) == SYMBOL_REF
16095 || GET_CODE (in
) == HIGH
16096 || GET_CODE (in
) == LABEL_REF
16097 || GET_CODE (in
) == CONST
))
16101 if (GET_CODE (in
) == REG
)
16103 regno
= REGNO (in
);
16104 if (regno
>= FIRST_PSEUDO_REGISTER
)
16106 regno
= true_regnum (in
);
16107 if (regno
>= FIRST_PSEUDO_REGISTER
)
16111 else if (GET_CODE (in
) == SUBREG
)
16113 regno
= true_regnum (in
);
16114 if (regno
>= FIRST_PSEUDO_REGISTER
)
16120 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
16122 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
16123 || (regno
>= 0 && INT_REGNO_P (regno
)))
16126 /* Constants, memory, and FP registers can go into FP registers. */
16127 if ((regno
== -1 || FP_REGNO_P (regno
))
16128 && (rclass
== FLOAT_REGS
|| rclass
== NON_SPECIAL_REGS
))
16129 return (mode
!= SDmode
|| lra_in_progress
) ? NO_REGS
: GENERAL_REGS
;
16131 /* Memory, and FP/altivec registers can go into fp/altivec registers under
16132 VSX. However, for scalar variables, use the traditional floating point
16133 registers so that we can use offset+register addressing. */
16135 && (regno
== -1 || VSX_REGNO_P (regno
))
16136 && VSX_REG_CLASS_P (rclass
))
16138 if (GET_MODE_SIZE (mode
) < 16)
16144 /* Memory, and AltiVec registers can go into AltiVec registers. */
16145 if ((regno
== -1 || ALTIVEC_REGNO_P (regno
))
16146 && rclass
== ALTIVEC_REGS
)
16149 /* We can copy among the CR registers. */
16150 if ((rclass
== CR_REGS
|| rclass
== CR0_REGS
)
16151 && regno
>= 0 && CR_REGNO_P (regno
))
16154 /* Otherwise, we need GENERAL_REGS. */
16155 return GENERAL_REGS
;
16158 /* Debug version of rs6000_secondary_reload_class. */
16159 static enum reg_class
16160 rs6000_debug_secondary_reload_class (enum reg_class rclass
,
16161 enum machine_mode mode
, rtx in
)
16163 enum reg_class ret
= rs6000_secondary_reload_class (rclass
, mode
, in
);
16165 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
16166 "mode = %s, input rtx:\n",
16167 reg_class_names
[ret
], reg_class_names
[rclass
],
16168 GET_MODE_NAME (mode
));
16174 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
16177 rs6000_cannot_change_mode_class (enum machine_mode from
,
16178 enum machine_mode to
,
16179 enum reg_class rclass
)
16181 unsigned from_size
= GET_MODE_SIZE (from
);
16182 unsigned to_size
= GET_MODE_SIZE (to
);
16184 if (from_size
!= to_size
)
16186 enum reg_class xclass
= (TARGET_VSX
) ? VSX_REGS
: FLOAT_REGS
;
16188 if (reg_classes_intersect_p (xclass
, rclass
))
16190 unsigned to_nregs
= hard_regno_nregs
[FIRST_FPR_REGNO
][to
];
16191 unsigned from_nregs
= hard_regno_nregs
[FIRST_FPR_REGNO
][from
];
16193 /* Don't allow 64-bit types to overlap with 128-bit types that take a
16194 single register under VSX because the scalar part of the register
16195 is in the upper 64-bits, and not the lower 64-bits. Types like
16196 TFmode/TDmode that take 2 scalar register can overlap. 128-bit
16197 IEEE floating point can't overlap, and neither can small
16200 if (TARGET_IEEEQUAD
&& (to
== TFmode
|| from
== TFmode
))
16203 if (from_size
< 8 || to_size
< 8)
16206 if (from_size
== 8 && (8 * to_nregs
) != to_size
)
16209 if (to_size
== 8 && (8 * from_nregs
) != from_size
)
16218 if (TARGET_E500_DOUBLE
16219 && ((((to
) == DFmode
) + ((from
) == DFmode
)) == 1
16220 || (((to
) == TFmode
) + ((from
) == TFmode
)) == 1
16221 || (((to
) == DDmode
) + ((from
) == DDmode
)) == 1
16222 || (((to
) == TDmode
) + ((from
) == TDmode
)) == 1
16223 || (((to
) == DImode
) + ((from
) == DImode
)) == 1))
16226 /* Since the VSX register set includes traditional floating point registers
16227 and altivec registers, just check for the size being different instead of
16228 trying to check whether the modes are vector modes. Otherwise it won't
16229 allow say DF and DI to change classes. For types like TFmode and TDmode
16230 that take 2 64-bit registers, rather than a single 128-bit register, don't
16231 allow subregs of those types to other 128 bit types. */
16232 if (TARGET_VSX
&& VSX_REG_CLASS_P (rclass
))
16234 unsigned num_regs
= (from_size
+ 15) / 16;
16235 if (hard_regno_nregs
[FIRST_FPR_REGNO
][to
] > num_regs
16236 || hard_regno_nregs
[FIRST_FPR_REGNO
][from
] > num_regs
)
16239 return (from_size
!= 8 && from_size
!= 16);
16242 if (TARGET_ALTIVEC
&& rclass
== ALTIVEC_REGS
16243 && (ALTIVEC_VECTOR_MODE (from
) + ALTIVEC_VECTOR_MODE (to
)) == 1)
16246 if (TARGET_SPE
&& (SPE_VECTOR_MODE (from
) + SPE_VECTOR_MODE (to
)) == 1
16247 && reg_classes_intersect_p (GENERAL_REGS
, rclass
))
16253 /* Debug version of rs6000_cannot_change_mode_class. */
16255 rs6000_debug_cannot_change_mode_class (enum machine_mode from
,
16256 enum machine_mode to
,
16257 enum reg_class rclass
)
16259 bool ret
= rs6000_cannot_change_mode_class (from
, to
, rclass
);
16262 "rs6000_cannot_change_mode_class, return %s, from = %s, "
16263 "to = %s, rclass = %s\n",
16264 ret
? "true" : "false",
16265 GET_MODE_NAME (from
), GET_MODE_NAME (to
),
16266 reg_class_names
[rclass
]);
16271 /* Return a string to do a move operation of 128 bits of data. */
16274 rs6000_output_move_128bit (rtx operands
[])
16276 rtx dest
= operands
[0];
16277 rtx src
= operands
[1];
16278 enum machine_mode mode
= GET_MODE (dest
);
16281 bool dest_gpr_p
, dest_fp_p
, dest_vmx_p
, dest_vsx_p
;
16282 bool src_gpr_p
, src_fp_p
, src_vmx_p
, src_vsx_p
;
16286 dest_regno
= REGNO (dest
);
16287 dest_gpr_p
= INT_REGNO_P (dest_regno
);
16288 dest_fp_p
= FP_REGNO_P (dest_regno
);
16289 dest_vmx_p
= ALTIVEC_REGNO_P (dest_regno
);
16290 dest_vsx_p
= dest_fp_p
| dest_vmx_p
;
16295 dest_gpr_p
= dest_fp_p
= dest_vmx_p
= dest_vsx_p
= false;
16300 src_regno
= REGNO (src
);
16301 src_gpr_p
= INT_REGNO_P (src_regno
);
16302 src_fp_p
= FP_REGNO_P (src_regno
);
16303 src_vmx_p
= ALTIVEC_REGNO_P (src_regno
);
16304 src_vsx_p
= src_fp_p
| src_vmx_p
;
16309 src_gpr_p
= src_fp_p
= src_vmx_p
= src_vsx_p
= false;
16312 /* Register moves. */
16313 if (dest_regno
>= 0 && src_regno
>= 0)
16320 else if (TARGET_VSX
&& TARGET_DIRECT_MOVE
&& src_vsx_p
)
16324 else if (TARGET_VSX
&& dest_vsx_p
)
16327 return "xxlor %x0,%x1,%x1";
16329 else if (TARGET_DIRECT_MOVE
&& src_gpr_p
)
16333 else if (TARGET_ALTIVEC
&& dest_vmx_p
&& src_vmx_p
)
16334 return "vor %0,%1,%1";
16336 else if (dest_fp_p
&& src_fp_p
)
16341 else if (dest_regno
>= 0 && MEM_P (src
))
16345 if (TARGET_QUAD_MEMORY
&& quad_load_store_p (dest
, src
))
16351 else if (TARGET_ALTIVEC
&& dest_vmx_p
16352 && altivec_indexed_or_indirect_operand (src
, mode
))
16353 return "lvx %0,%y1";
16355 else if (TARGET_VSX
&& dest_vsx_p
)
16357 if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
16358 return "lxvw4x %x0,%y1";
16360 return "lxvd2x %x0,%y1";
16363 else if (TARGET_ALTIVEC
&& dest_vmx_p
)
16364 return "lvx %0,%y1";
16366 else if (dest_fp_p
)
16371 else if (src_regno
>= 0 && MEM_P (dest
))
16375 if (TARGET_QUAD_MEMORY
&& quad_load_store_p (dest
, src
))
16376 return "stq %1,%0";
16381 else if (TARGET_ALTIVEC
&& src_vmx_p
16382 && altivec_indexed_or_indirect_operand (src
, mode
))
16383 return "stvx %1,%y0";
16385 else if (TARGET_VSX
&& src_vsx_p
)
16387 if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
16388 return "stxvw4x %x1,%y0";
16390 return "stxvd2x %x1,%y0";
16393 else if (TARGET_ALTIVEC
&& src_vmx_p
)
16394 return "stvx %1,%y0";
16401 else if (dest_regno
>= 0
16402 && (GET_CODE (src
) == CONST_INT
16403 || GET_CODE (src
) == CONST_WIDE_INT
16404 || GET_CODE (src
) == CONST_DOUBLE
16405 || GET_CODE (src
) == CONST_VECTOR
))
16410 else if (TARGET_VSX
&& dest_vsx_p
&& zero_constant (src
, mode
))
16411 return "xxlxor %x0,%x0,%x0";
16413 else if (TARGET_ALTIVEC
&& dest_vmx_p
)
16414 return output_vec_const_move (operands
);
16417 if (TARGET_DEBUG_ADDR
)
16419 fprintf (stderr
, "\n===== Bad 128 bit move:\n");
16420 debug_rtx (gen_rtx_SET (VOIDmode
, dest
, src
));
16423 gcc_unreachable ();
16427 /* Given a comparison operation, return the bit number in CCR to test. We
16428 know this is a valid comparison.
16430 SCC_P is 1 if this is for an scc. That means that %D will have been
16431 used instead of %C, so the bits will be in different places.
16433 Return -1 if OP isn't a valid comparison for some reason. */
16436 ccr_bit (rtx op
, int scc_p
)
16438 enum rtx_code code
= GET_CODE (op
);
16439 enum machine_mode cc_mode
;
16444 if (!COMPARISON_P (op
))
16447 reg
= XEXP (op
, 0);
16449 gcc_assert (GET_CODE (reg
) == REG
&& CR_REGNO_P (REGNO (reg
)));
16451 cc_mode
= GET_MODE (reg
);
16452 cc_regnum
= REGNO (reg
);
16453 base_bit
= 4 * (cc_regnum
- CR0_REGNO
);
16455 validate_condition_mode (code
, cc_mode
);
16457 /* When generating a sCOND operation, only positive conditions are
16460 || code
== EQ
|| code
== GT
|| code
== LT
|| code
== UNORDERED
16461 || code
== GTU
|| code
== LTU
);
16466 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
16468 return base_bit
+ 2;
16469 case GT
: case GTU
: case UNLE
:
16470 return base_bit
+ 1;
16471 case LT
: case LTU
: case UNGE
:
16473 case ORDERED
: case UNORDERED
:
16474 return base_bit
+ 3;
16477 /* If scc, we will have done a cror to put the bit in the
16478 unordered position. So test that bit. For integer, this is ! LT
16479 unless this is an scc insn. */
16480 return scc_p
? base_bit
+ 3 : base_bit
;
16483 return scc_p
? base_bit
+ 3 : base_bit
+ 1;
16486 gcc_unreachable ();
16490 /* Return the GOT register. */
16493 rs6000_got_register (rtx value ATTRIBUTE_UNUSED
)
16495 /* The second flow pass currently (June 1999) can't update
16496 regs_ever_live without disturbing other parts of the compiler, so
16497 update it here to make the prolog/epilogue code happy. */
16498 if (!can_create_pseudo_p ()
16499 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
16500 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM
, true);
16502 crtl
->uses_pic_offset_table
= 1;
16504 return pic_offset_table_rtx
;
16507 static rs6000_stack_t stack_info
;
16509 /* Function to init struct machine_function.
16510 This will be called, via a pointer variable,
16511 from push_function_context. */
16513 static struct machine_function
*
16514 rs6000_init_machine_status (void)
16516 stack_info
.reload_completed
= 0;
16517 return ggc_alloc_cleared_machine_function ();
16520 #define INT_P(X) (GET_CODE (X) == CONST_INT && GET_MODE (X) == VOIDmode)
16523 extract_MB (rtx op
)
16526 unsigned long val
= INTVAL (op
);
16528 /* If the high bit is zero, the value is the first 1 bit we find
16530 if ((val
& 0x80000000) == 0)
16532 gcc_assert (val
& 0xffffffff);
16535 while (((val
<<= 1) & 0x80000000) == 0)
16540 /* If the high bit is set and the low bit is not, or the mask is all
16541 1's, the value is zero. */
16542 if ((val
& 1) == 0 || (val
& 0xffffffff) == 0xffffffff)
16545 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
16548 while (((val
>>= 1) & 1) != 0)
16555 extract_ME (rtx op
)
16558 unsigned long val
= INTVAL (op
);
16560 /* If the low bit is zero, the value is the first 1 bit we find from
16562 if ((val
& 1) == 0)
16564 gcc_assert (val
& 0xffffffff);
16567 while (((val
>>= 1) & 1) == 0)
16573 /* If the low bit is set and the high bit is not, or the mask is all
16574 1's, the value is 31. */
16575 if ((val
& 0x80000000) == 0 || (val
& 0xffffffff) == 0xffffffff)
16578 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
16581 while (((val
<<= 1) & 0x80000000) != 0)
16587 /* Locate some local-dynamic symbol still in use by this function
16588 so that we can print its name in some tls_ld pattern. */
16590 static const char *
16591 rs6000_get_some_local_dynamic_name (void)
16595 if (cfun
->machine
->some_ld_name
)
16596 return cfun
->machine
->some_ld_name
;
16598 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
16600 && for_each_rtx (&PATTERN (insn
),
16601 rs6000_get_some_local_dynamic_name_1
, 0))
16602 return cfun
->machine
->some_ld_name
;
16604 gcc_unreachable ();
16607 /* Helper function for rs6000_get_some_local_dynamic_name. */
16610 rs6000_get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
16614 if (GET_CODE (x
) == SYMBOL_REF
)
16616 const char *str
= XSTR (x
, 0);
16617 if (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
16619 cfun
->machine
->some_ld_name
= str
;
16627 /* Write out a function code label. */
16630 rs6000_output_function_entry (FILE *file
, const char *fname
)
16632 if (fname
[0] != '.')
16634 switch (DEFAULT_ABI
)
16637 gcc_unreachable ();
16643 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "L.");
16652 RS6000_OUTPUT_BASENAME (file
, fname
);
16655 /* Print an operand. Recognize special options, documented below. */
16658 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
16659 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
16661 #define SMALL_DATA_RELOC "sda21"
16662 #define SMALL_DATA_REG 0
16666 print_operand (FILE *file
, rtx x
, int code
)
16669 unsigned HOST_WIDE_INT uval
;
16673 /* %a is output_address. */
16676 /* If constant, low-order 16 bits of constant, unsigned.
16677 Otherwise, write normally. */
16679 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffff);
16681 print_operand (file
, x
, 0);
16685 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
16686 for 64-bit mask direction. */
16687 putc (((INTVAL (x
) & 1) == 0 ? 'r' : 'l'), file
);
16690 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
16694 /* Like 'J' but get to the GT bit only. */
16695 gcc_assert (REG_P (x
));
16697 /* Bit 1 is GT bit. */
16698 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 1;
16700 /* Add one for shift count in rlinm for scc. */
16701 fprintf (file
, "%d", i
+ 1);
16705 /* X is a CR register. Print the number of the EQ bit of the CR */
16706 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
16707 output_operand_lossage ("invalid %%E value");
16709 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 2);
16713 /* X is a CR register. Print the shift count needed to move it
16714 to the high-order four bits. */
16715 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
16716 output_operand_lossage ("invalid %%f value");
16718 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
));
16722 /* Similar, but print the count for the rotate in the opposite
16724 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
16725 output_operand_lossage ("invalid %%F value");
16727 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - CR0_REGNO
));
16731 /* X is a constant integer. If it is negative, print "m",
16732 otherwise print "z". This is to make an aze or ame insn. */
16733 if (GET_CODE (x
) != CONST_INT
)
16734 output_operand_lossage ("invalid %%G value");
16735 else if (INTVAL (x
) >= 0)
16742 /* If constant, output low-order five bits. Otherwise, write
16745 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 31);
16747 print_operand (file
, x
, 0);
16751 /* If constant, output low-order six bits. Otherwise, write
16754 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 63);
16756 print_operand (file
, x
, 0);
16760 /* Print `i' if this is a constant, else nothing. */
16766 /* Write the bit number in CCR for jump. */
16767 i
= ccr_bit (x
, 0);
16769 output_operand_lossage ("invalid %%j code");
16771 fprintf (file
, "%d", i
);
16775 /* Similar, but add one for shift count in rlinm for scc and pass
16776 scc flag to `ccr_bit'. */
16777 i
= ccr_bit (x
, 1);
16779 output_operand_lossage ("invalid %%J code");
16781 /* If we want bit 31, write a shift count of zero, not 32. */
16782 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
16786 /* X must be a constant. Write the 1's complement of the
16789 output_operand_lossage ("invalid %%k value");
16791 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
16795 /* X must be a symbolic constant on ELF. Write an
16796 expression suitable for an 'addi' that adds in the low 16
16797 bits of the MEM. */
16798 if (GET_CODE (x
) == CONST
)
16800 if (GET_CODE (XEXP (x
, 0)) != PLUS
16801 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
16802 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
16803 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
16804 output_operand_lossage ("invalid %%K value");
16806 print_operand_address (file
, x
);
16807 fputs ("@l", file
);
16810 /* %l is output_asm_label. */
16813 /* Write second word of DImode or DFmode reference. Works on register
16814 or non-indexed memory only. */
16816 fputs (reg_names
[REGNO (x
) + 1], file
);
16817 else if (MEM_P (x
))
16819 /* Handle possible auto-increment. Since it is pre-increment and
16820 we have already done it, we can just use an offset of word. */
16821 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
16822 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
16823 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
16825 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
16826 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
16829 output_address (XEXP (adjust_address_nv (x
, SImode
,
16833 if (small_data_operand (x
, GET_MODE (x
)))
16834 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
16835 reg_names
[SMALL_DATA_REG
]);
16840 /* MB value for a mask operand. */
16841 if (! mask_operand (x
, SImode
))
16842 output_operand_lossage ("invalid %%m value");
16844 fprintf (file
, "%d", extract_MB (x
));
16848 /* ME value for a mask operand. */
16849 if (! mask_operand (x
, SImode
))
16850 output_operand_lossage ("invalid %%M value");
16852 fprintf (file
, "%d", extract_ME (x
));
16855 /* %n outputs the negative of its operand. */
16858 /* Write the number of elements in the vector times 4. */
16859 if (GET_CODE (x
) != PARALLEL
)
16860 output_operand_lossage ("invalid %%N value");
16862 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
16866 /* Similar, but subtract 1 first. */
16867 if (GET_CODE (x
) != PARALLEL
)
16868 output_operand_lossage ("invalid %%O value");
16870 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
16874 /* X is a CONST_INT that is a power of two. Output the logarithm. */
16877 || (i
= exact_log2 (INTVAL (x
))) < 0)
16878 output_operand_lossage ("invalid %%p value");
16880 fprintf (file
, "%d", i
);
16884 /* The operand must be an indirect memory reference. The result
16885 is the register name. */
16886 if (GET_CODE (x
) != MEM
|| GET_CODE (XEXP (x
, 0)) != REG
16887 || REGNO (XEXP (x
, 0)) >= 32)
16888 output_operand_lossage ("invalid %%P value");
16890 fputs (reg_names
[REGNO (XEXP (x
, 0))], file
);
16894 /* This outputs the logical code corresponding to a boolean
16895 expression. The expression may have one or both operands
16896 negated (if one, only the first one). For condition register
16897 logical operations, it will also treat the negated
16898 CR codes as NOTs, but not handle NOTs of them. */
16900 const char *const *t
= 0;
16902 enum rtx_code code
= GET_CODE (x
);
16903 static const char * const tbl
[3][3] = {
16904 { "and", "andc", "nor" },
16905 { "or", "orc", "nand" },
16906 { "xor", "eqv", "xor" } };
16910 else if (code
== IOR
)
16912 else if (code
== XOR
)
16915 output_operand_lossage ("invalid %%q value");
16917 if (GET_CODE (XEXP (x
, 0)) != NOT
)
16921 if (GET_CODE (XEXP (x
, 1)) == NOT
)
16932 if (! TARGET_MFCRF
)
16938 /* X is a CR register. Print the mask for `mtcrf'. */
16939 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
16940 output_operand_lossage ("invalid %%R value");
16942 fprintf (file
, "%d", 128 >> (REGNO (x
) - CR0_REGNO
));
16946 /* Low 5 bits of 32 - value */
16948 output_operand_lossage ("invalid %%s value");
16950 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (32 - INTVAL (x
)) & 31);
16954 /* PowerPC64 mask position. All 0's is excluded.
16955 CONST_INT 32-bit mask is considered sign-extended so any
16956 transition must occur within the CONST_INT, not on the boundary. */
16957 if (! mask64_operand (x
, DImode
))
16958 output_operand_lossage ("invalid %%S value");
16962 if (uval
& 1) /* Clear Left */
16964 #if HOST_BITS_PER_WIDE_INT > 64
16965 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
16969 else /* Clear Right */
16972 #if HOST_BITS_PER_WIDE_INT > 64
16973 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
16979 gcc_assert (i
>= 0);
16980 fprintf (file
, "%d", i
);
16984 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
16985 gcc_assert (REG_P (x
) && GET_MODE (x
) == CCmode
);
16987 /* Bit 3 is OV bit. */
16988 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 3;
16990 /* If we want bit 31, write a shift count of zero, not 32. */
16991 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
16995 /* Print the symbolic name of a branch target register. */
16996 if (GET_CODE (x
) != REG
|| (REGNO (x
) != LR_REGNO
16997 && REGNO (x
) != CTR_REGNO
))
16998 output_operand_lossage ("invalid %%T value");
16999 else if (REGNO (x
) == LR_REGNO
)
17000 fputs ("lr", file
);
17002 fputs ("ctr", file
);
17006 /* High-order 16 bits of constant for use in unsigned operand. */
17008 output_operand_lossage ("invalid %%u value");
17010 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
17011 (INTVAL (x
) >> 16) & 0xffff);
17015 /* High-order 16 bits of constant for use in signed operand. */
17017 output_operand_lossage ("invalid %%v value");
17019 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
17020 (INTVAL (x
) >> 16) & 0xffff);
17024 /* Print `u' if this has an auto-increment or auto-decrement. */
17026 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
17027 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
17028 || GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
))
17033 /* Print the trap code for this operand. */
17034 switch (GET_CODE (x
))
17037 fputs ("eq", file
); /* 4 */
17040 fputs ("ne", file
); /* 24 */
17043 fputs ("lt", file
); /* 16 */
17046 fputs ("le", file
); /* 20 */
17049 fputs ("gt", file
); /* 8 */
17052 fputs ("ge", file
); /* 12 */
17055 fputs ("llt", file
); /* 2 */
17058 fputs ("lle", file
); /* 6 */
17061 fputs ("lgt", file
); /* 1 */
17064 fputs ("lge", file
); /* 5 */
17067 gcc_unreachable ();
17072 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
17075 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
17076 ((INTVAL (x
) & 0xffff) ^ 0x8000) - 0x8000);
17078 print_operand (file
, x
, 0);
17082 /* MB value for a PowerPC64 rldic operand. */
17083 i
= clz_hwi (INTVAL (x
));
17085 fprintf (file
, "%d", i
);
17089 /* X is a FPR or Altivec register used in a VSX context. */
17090 if (GET_CODE (x
) != REG
|| !VSX_REGNO_P (REGNO (x
)))
17091 output_operand_lossage ("invalid %%x value");
17094 int reg
= REGNO (x
);
17095 int vsx_reg
= (FP_REGNO_P (reg
)
17097 : reg
- FIRST_ALTIVEC_REGNO
+ 32);
17099 #ifdef TARGET_REGNAMES
17100 if (TARGET_REGNAMES
)
17101 fprintf (file
, "%%vs%d", vsx_reg
);
17104 fprintf (file
, "%d", vsx_reg
);
17110 && (legitimate_indexed_address_p (XEXP (x
, 0), 0)
17111 || (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
17112 && legitimate_indexed_address_p (XEXP (XEXP (x
, 0), 1), 0))))
17117 /* Like 'L', for third word of TImode/PTImode */
17119 fputs (reg_names
[REGNO (x
) + 2], file
);
17120 else if (MEM_P (x
))
17122 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
17123 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
17124 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 8));
17125 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
17126 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 8));
17128 output_address (XEXP (adjust_address_nv (x
, SImode
, 8), 0));
17129 if (small_data_operand (x
, GET_MODE (x
)))
17130 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
17131 reg_names
[SMALL_DATA_REG
]);
17136 /* X is a SYMBOL_REF. Write out the name preceded by a
17137 period and without any trailing data in brackets. Used for function
17138 names. If we are configured for System V (or the embedded ABI) on
17139 the PowerPC, do not emit the period, since those systems do not use
17140 TOCs and the like. */
17141 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
17143 /* For macho, check to see if we need a stub. */
17146 const char *name
= XSTR (x
, 0);
17148 if (darwin_emit_branch_islands
17149 && MACHOPIC_INDIRECT
17150 && machopic_classify_symbol (x
) == MACHOPIC_UNDEFINED_FUNCTION
)
17151 name
= machopic_indirection_name (x
, /*stub_p=*/true);
17153 assemble_name (file
, name
);
17155 else if (!DOT_SYMBOLS
)
17156 assemble_name (file
, XSTR (x
, 0));
17158 rs6000_output_function_entry (file
, XSTR (x
, 0));
17162 /* Like 'L', for last word of TImode/PTImode. */
17164 fputs (reg_names
[REGNO (x
) + 3], file
);
17165 else if (MEM_P (x
))
17167 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
17168 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
17169 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 12));
17170 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
17171 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 12));
17173 output_address (XEXP (adjust_address_nv (x
, SImode
, 12), 0));
17174 if (small_data_operand (x
, GET_MODE (x
)))
17175 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
17176 reg_names
[SMALL_DATA_REG
]);
17180 /* Print AltiVec or SPE memory operand. */
17185 gcc_assert (MEM_P (x
));
17189 /* Ugly hack because %y is overloaded. */
17190 if ((TARGET_SPE
|| TARGET_E500_DOUBLE
)
17191 && (GET_MODE_SIZE (GET_MODE (x
)) == 8
17192 || GET_MODE (x
) == TFmode
17193 || GET_MODE (x
) == TImode
17194 || GET_MODE (x
) == PTImode
))
17196 /* Handle [reg]. */
17199 fprintf (file
, "0(%s)", reg_names
[REGNO (tmp
)]);
17202 /* Handle [reg+UIMM]. */
17203 else if (GET_CODE (tmp
) == PLUS
&&
17204 GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
17208 gcc_assert (REG_P (XEXP (tmp
, 0)));
17210 x
= INTVAL (XEXP (tmp
, 1));
17211 fprintf (file
, "%d(%s)", x
, reg_names
[REGNO (XEXP (tmp
, 0))]);
17215 /* Fall through. Must be [reg+reg]. */
17217 if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x
))
17218 && GET_CODE (tmp
) == AND
17219 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
17220 && INTVAL (XEXP (tmp
, 1)) == -16)
17221 tmp
= XEXP (tmp
, 0);
17222 else if (VECTOR_MEM_VSX_P (GET_MODE (x
))
17223 && GET_CODE (tmp
) == PRE_MODIFY
)
17224 tmp
= XEXP (tmp
, 1);
17226 fprintf (file
, "0,%s", reg_names
[REGNO (tmp
)]);
17229 if (!GET_CODE (tmp
) == PLUS
17230 || !REG_P (XEXP (tmp
, 0))
17231 || !REG_P (XEXP (tmp
, 1)))
17233 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
17237 if (REGNO (XEXP (tmp
, 0)) == 0)
17238 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 1)) ],
17239 reg_names
[ REGNO (XEXP (tmp
, 0)) ]);
17241 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 0)) ],
17242 reg_names
[ REGNO (XEXP (tmp
, 1)) ]);
17249 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
17250 else if (MEM_P (x
))
17252 /* We need to handle PRE_INC and PRE_DEC here, since we need to
17253 know the width from the mode. */
17254 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
17255 fprintf (file
, "%d(%s)", GET_MODE_SIZE (GET_MODE (x
)),
17256 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
17257 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
17258 fprintf (file
, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x
)),
17259 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
17260 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
17261 output_address (XEXP (XEXP (x
, 0), 1));
17263 output_address (XEXP (x
, 0));
17267 if (toc_relative_expr_p (x
, false))
17268 /* This hack along with a corresponding hack in
17269 rs6000_output_addr_const_extra arranges to output addends
17270 where the assembler expects to find them. eg.
17271 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
17272 without this hack would be output as "x@toc+4". We
17274 output_addr_const (file
, CONST_CAST_RTX (tocrel_base
));
17276 output_addr_const (file
, x
);
17281 assemble_name (file
, rs6000_get_some_local_dynamic_name ());
17285 output_operand_lossage ("invalid %%xn code");
17289 /* Print the address of an operand. */
17292 print_operand_address (FILE *file
, rtx x
)
17295 fprintf (file
, "0(%s)", reg_names
[ REGNO (x
) ]);
17296 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
17297 || GET_CODE (x
) == LABEL_REF
)
17299 output_addr_const (file
, x
);
17300 if (small_data_operand (x
, GET_MODE (x
)))
17301 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
17302 reg_names
[SMALL_DATA_REG
]);
17304 gcc_assert (!TARGET_TOC
);
17306 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
17307 && REG_P (XEXP (x
, 1)))
17309 if (REGNO (XEXP (x
, 0)) == 0)
17310 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 1)) ],
17311 reg_names
[ REGNO (XEXP (x
, 0)) ]);
17313 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 0)) ],
17314 reg_names
[ REGNO (XEXP (x
, 1)) ]);
17316 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
17317 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
17318 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"(%s)",
17319 INTVAL (XEXP (x
, 1)), reg_names
[ REGNO (XEXP (x
, 0)) ]);
17321 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
17322 && CONSTANT_P (XEXP (x
, 1)))
17324 fprintf (file
, "lo16(");
17325 output_addr_const (file
, XEXP (x
, 1));
17326 fprintf (file
, ")(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
17330 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
17331 && CONSTANT_P (XEXP (x
, 1)))
17333 output_addr_const (file
, XEXP (x
, 1));
17334 fprintf (file
, "@l(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
17337 else if (toc_relative_expr_p (x
, false))
17339 /* This hack along with a corresponding hack in
17340 rs6000_output_addr_const_extra arranges to output addends
17341 where the assembler expects to find them. eg.
17343 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
17344 without this hack would be output as "x@toc+8@l(9)". We
17345 want "x+8@toc@l(9)". */
17346 output_addr_const (file
, CONST_CAST_RTX (tocrel_base
));
17347 if (GET_CODE (x
) == LO_SUM
)
17348 fprintf (file
, "@l(%s)", reg_names
[REGNO (XEXP (x
, 0))]);
17350 fprintf (file
, "(%s)", reg_names
[REGNO (XVECEXP (tocrel_base
, 0, 1))]);
17353 gcc_unreachable ();
17356 /* Implement TARGET_OUTPUT_ADDR_CONST_EXTRA. */
17359 rs6000_output_addr_const_extra (FILE *file
, rtx x
)
17361 if (GET_CODE (x
) == UNSPEC
)
17362 switch (XINT (x
, 1))
17364 case UNSPEC_TOCREL
:
17365 gcc_checking_assert (GET_CODE (XVECEXP (x
, 0, 0)) == SYMBOL_REF
17366 && REG_P (XVECEXP (x
, 0, 1))
17367 && REGNO (XVECEXP (x
, 0, 1)) == TOC_REGISTER
);
17368 output_addr_const (file
, XVECEXP (x
, 0, 0));
17369 if (x
== tocrel_base
&& tocrel_offset
!= const0_rtx
)
17371 if (INTVAL (tocrel_offset
) >= 0)
17372 fprintf (file
, "+");
17373 output_addr_const (file
, CONST_CAST_RTX (tocrel_offset
));
17375 if (!TARGET_AIX
|| (TARGET_ELF
&& TARGET_MINIMAL_TOC
))
17378 assemble_name (file
, toc_label_name
);
17380 else if (TARGET_ELF
)
17381 fputs ("@toc", file
);
17385 case UNSPEC_MACHOPIC_OFFSET
:
17386 output_addr_const (file
, XVECEXP (x
, 0, 0));
17388 machopic_output_function_base_name (file
);
17395 /* Target hook for assembling integer objects. The PowerPC version has
17396 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
17397 is defined. It also needs to handle DI-mode objects on 64-bit
17401 rs6000_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
17403 #ifdef RELOCATABLE_NEEDS_FIXUP
17404 /* Special handling for SI values. */
17405 if (RELOCATABLE_NEEDS_FIXUP
&& size
== 4 && aligned_p
)
17407 static int recurse
= 0;
17409 /* For -mrelocatable, we mark all addresses that need to be fixed up in
17410 the .fixup section. Since the TOC section is already relocated, we
17411 don't need to mark it here. We used to skip the text section, but it
17412 should never be valid for relocated addresses to be placed in the text
17414 if (TARGET_RELOCATABLE
17415 && in_section
!= toc_section
17417 && !CONST_SCALAR_INT_P (x
)
17423 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", fixuplabelno
);
17425 ASM_OUTPUT_LABEL (asm_out_file
, buf
);
17426 fprintf (asm_out_file
, "\t.long\t(");
17427 output_addr_const (asm_out_file
, x
);
17428 fprintf (asm_out_file
, ")@fixup\n");
17429 fprintf (asm_out_file
, "\t.section\t\".fixup\",\"aw\"\n");
17430 ASM_OUTPUT_ALIGN (asm_out_file
, 2);
17431 fprintf (asm_out_file
, "\t.long\t");
17432 assemble_name (asm_out_file
, buf
);
17433 fprintf (asm_out_file
, "\n\t.previous\n");
17437 /* Remove initial .'s to turn a -mcall-aixdesc function
17438 address into the address of the descriptor, not the function
17440 else if (GET_CODE (x
) == SYMBOL_REF
17441 && XSTR (x
, 0)[0] == '.'
17442 && DEFAULT_ABI
== ABI_AIX
)
17444 const char *name
= XSTR (x
, 0);
17445 while (*name
== '.')
17448 fprintf (asm_out_file
, "\t.long\t%s\n", name
);
17452 #endif /* RELOCATABLE_NEEDS_FIXUP */
17453 return default_assemble_integer (x
, size
, aligned_p
);
17456 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
17457 /* Emit an assembler directive to set symbol visibility for DECL to
17458 VISIBILITY_TYPE. */
17461 rs6000_assemble_visibility (tree decl
, int vis
)
17466 /* Functions need to have their entry point symbol visibility set as
17467 well as their descriptor symbol visibility. */
17468 if (DEFAULT_ABI
== ABI_AIX
17470 && TREE_CODE (decl
) == FUNCTION_DECL
)
17472 static const char * const visibility_types
[] = {
17473 NULL
, "internal", "hidden", "protected"
17476 const char *name
, *type
;
17478 name
= ((* targetm
.strip_name_encoding
)
17479 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
))));
17480 type
= visibility_types
[vis
];
17482 fprintf (asm_out_file
, "\t.%s\t%s\n", type
, name
);
17483 fprintf (asm_out_file
, "\t.%s\t.%s\n", type
, name
);
17486 default_assemble_visibility (decl
, vis
);
17491 rs6000_reverse_condition (enum machine_mode mode
, enum rtx_code code
)
17493 /* Reversal of FP compares takes care -- an ordered compare
17494 becomes an unordered compare and vice versa. */
17495 if (mode
== CCFPmode
17496 && (!flag_finite_math_only
17497 || code
== UNLT
|| code
== UNLE
|| code
== UNGT
|| code
== UNGE
17498 || code
== UNEQ
|| code
== LTGT
))
17499 return reverse_condition_maybe_unordered (code
);
17501 return reverse_condition (code
);
17504 /* Generate a compare for CODE. Return a brand-new rtx that
17505 represents the result of the compare. */
17508 rs6000_generate_compare (rtx cmp
, enum machine_mode mode
)
17510 enum machine_mode comp_mode
;
17511 rtx compare_result
;
17512 enum rtx_code code
= GET_CODE (cmp
);
17513 rtx op0
= XEXP (cmp
, 0);
17514 rtx op1
= XEXP (cmp
, 1);
17516 if (FLOAT_MODE_P (mode
))
17517 comp_mode
= CCFPmode
;
17518 else if (code
== GTU
|| code
== LTU
17519 || code
== GEU
|| code
== LEU
)
17520 comp_mode
= CCUNSmode
;
17521 else if ((code
== EQ
|| code
== NE
)
17522 && unsigned_reg_p (op0
)
17523 && (unsigned_reg_p (op1
)
17524 || (CONST_INT_P (op1
) && INTVAL (op1
) != 0)))
17525 /* These are unsigned values, perhaps there will be a later
17526 ordering compare that can be shared with this one. */
17527 comp_mode
= CCUNSmode
;
17529 comp_mode
= CCmode
;
17531 /* If we have an unsigned compare, make sure we don't have a signed value as
17533 if (comp_mode
== CCUNSmode
&& GET_CODE (op1
) == CONST_INT
17534 && INTVAL (op1
) < 0)
17536 op0
= copy_rtx_if_shared (op0
);
17537 op1
= force_reg (GET_MODE (op0
), op1
);
17538 cmp
= gen_rtx_fmt_ee (code
, GET_MODE (cmp
), op0
, op1
);
17541 /* First, the compare. */
17542 compare_result
= gen_reg_rtx (comp_mode
);
17544 /* E500 FP compare instructions on the GPRs. Yuck! */
17545 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
)
17546 && FLOAT_MODE_P (mode
))
17548 rtx cmp
, or_result
, compare_result2
;
17549 enum machine_mode op_mode
= GET_MODE (op0
);
17552 if (op_mode
== VOIDmode
)
17553 op_mode
= GET_MODE (op1
);
17555 /* First reverse the condition codes that aren't directly supported. */
17563 code
= reverse_condition_maybe_unordered (code
);
17576 gcc_unreachable ();
17579 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
17580 This explains the following mess. */
17588 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
17589 ? gen_tstsfeq_gpr (compare_result
, op0
, op1
)
17590 : gen_cmpsfeq_gpr (compare_result
, op0
, op1
);
17594 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
17595 ? gen_tstdfeq_gpr (compare_result
, op0
, op1
)
17596 : gen_cmpdfeq_gpr (compare_result
, op0
, op1
);
17600 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
17601 ? gen_tsttfeq_gpr (compare_result
, op0
, op1
)
17602 : gen_cmptfeq_gpr (compare_result
, op0
, op1
);
17606 gcc_unreachable ();
17615 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
17616 ? gen_tstsfgt_gpr (compare_result
, op0
, op1
)
17617 : gen_cmpsfgt_gpr (compare_result
, op0
, op1
);
17621 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
17622 ? gen_tstdfgt_gpr (compare_result
, op0
, op1
)
17623 : gen_cmpdfgt_gpr (compare_result
, op0
, op1
);
17627 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
17628 ? gen_tsttfgt_gpr (compare_result
, op0
, op1
)
17629 : gen_cmptfgt_gpr (compare_result
, op0
, op1
);
17633 gcc_unreachable ();
17642 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
17643 ? gen_tstsflt_gpr (compare_result
, op0
, op1
)
17644 : gen_cmpsflt_gpr (compare_result
, op0
, op1
);
17648 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
17649 ? gen_tstdflt_gpr (compare_result
, op0
, op1
)
17650 : gen_cmpdflt_gpr (compare_result
, op0
, op1
);
17654 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
17655 ? gen_tsttflt_gpr (compare_result
, op0
, op1
)
17656 : gen_cmptflt_gpr (compare_result
, op0
, op1
);
17660 gcc_unreachable ();
17665 gcc_unreachable ();
17668 /* Synthesize LE and GE from LT/GT || EQ. */
17669 if (code
== LE
|| code
== GE
)
17673 compare_result2
= gen_reg_rtx (CCFPmode
);
17679 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
17680 ? gen_tstsfeq_gpr (compare_result2
, op0
, op1
)
17681 : gen_cmpsfeq_gpr (compare_result2
, op0
, op1
);
17685 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
17686 ? gen_tstdfeq_gpr (compare_result2
, op0
, op1
)
17687 : gen_cmpdfeq_gpr (compare_result2
, op0
, op1
);
17691 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
17692 ? gen_tsttfeq_gpr (compare_result2
, op0
, op1
)
17693 : gen_cmptfeq_gpr (compare_result2
, op0
, op1
);
17697 gcc_unreachable ();
17702 /* OR them together. */
17703 or_result
= gen_reg_rtx (CCFPmode
);
17704 cmp
= gen_e500_cr_ior_compare (or_result
, compare_result
,
17706 compare_result
= or_result
;
17709 code
= reverse_p
? NE
: EQ
;
17715 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
17716 CLOBBERs to match cmptf_internal2 pattern. */
17717 if (comp_mode
== CCFPmode
&& TARGET_XL_COMPAT
17718 && GET_MODE (op0
) == TFmode
17719 && !TARGET_IEEEQUAD
17720 && TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_LONG_DOUBLE_128
)
17721 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
17723 gen_rtx_SET (VOIDmode
,
17725 gen_rtx_COMPARE (comp_mode
, op0
, op1
)),
17726 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
17727 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
17728 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
17729 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
17730 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
17731 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
17732 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
17733 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
17734 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (Pmode
)))));
17735 else if (GET_CODE (op1
) == UNSPEC
17736 && XINT (op1
, 1) == UNSPEC_SP_TEST
)
17738 rtx op1b
= XVECEXP (op1
, 0, 0);
17739 comp_mode
= CCEQmode
;
17740 compare_result
= gen_reg_rtx (CCEQmode
);
17742 emit_insn (gen_stack_protect_testdi (compare_result
, op0
, op1b
));
17744 emit_insn (gen_stack_protect_testsi (compare_result
, op0
, op1b
));
17747 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
17748 gen_rtx_COMPARE (comp_mode
, op0
, op1
)));
17751 /* Some kinds of FP comparisons need an OR operation;
17752 under flag_finite_math_only we don't bother. */
17753 if (FLOAT_MODE_P (mode
)
17754 && !flag_finite_math_only
17755 && !(TARGET_HARD_FLOAT
&& !TARGET_FPRS
)
17756 && (code
== LE
|| code
== GE
17757 || code
== UNEQ
|| code
== LTGT
17758 || code
== UNGT
|| code
== UNLT
))
17760 enum rtx_code or1
, or2
;
17761 rtx or1_rtx
, or2_rtx
, compare2_rtx
;
17762 rtx or_result
= gen_reg_rtx (CCEQmode
);
17766 case LE
: or1
= LT
; or2
= EQ
; break;
17767 case GE
: or1
= GT
; or2
= EQ
; break;
17768 case UNEQ
: or1
= UNORDERED
; or2
= EQ
; break;
17769 case LTGT
: or1
= LT
; or2
= GT
; break;
17770 case UNGT
: or1
= UNORDERED
; or2
= GT
; break;
17771 case UNLT
: or1
= UNORDERED
; or2
= LT
; break;
17772 default: gcc_unreachable ();
17774 validate_condition_mode (or1
, comp_mode
);
17775 validate_condition_mode (or2
, comp_mode
);
17776 or1_rtx
= gen_rtx_fmt_ee (or1
, SImode
, compare_result
, const0_rtx
);
17777 or2_rtx
= gen_rtx_fmt_ee (or2
, SImode
, compare_result
, const0_rtx
);
17778 compare2_rtx
= gen_rtx_COMPARE (CCEQmode
,
17779 gen_rtx_IOR (SImode
, or1_rtx
, or2_rtx
),
17781 emit_insn (gen_rtx_SET (VOIDmode
, or_result
, compare2_rtx
));
17783 compare_result
= or_result
;
17787 validate_condition_mode (code
, GET_MODE (compare_result
));
17789 return gen_rtx_fmt_ee (code
, VOIDmode
, compare_result
, const0_rtx
);
17793 /* Emit the RTL for an sISEL pattern. */
17796 rs6000_emit_sISEL (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx operands
[])
17798 rs6000_emit_int_cmove (operands
[0], operands
[1], const1_rtx
, const0_rtx
);
17802 rs6000_emit_sCOND (enum machine_mode mode
, rtx operands
[])
17805 enum machine_mode op_mode
;
17806 enum rtx_code cond_code
;
17807 rtx result
= operands
[0];
17809 if (TARGET_ISEL
&& (mode
== SImode
|| mode
== DImode
))
17811 rs6000_emit_sISEL (mode
, operands
);
17815 condition_rtx
= rs6000_generate_compare (operands
[1], mode
);
17816 cond_code
= GET_CODE (condition_rtx
);
17818 if (FLOAT_MODE_P (mode
)
17819 && !TARGET_FPRS
&& TARGET_HARD_FLOAT
)
17823 PUT_MODE (condition_rtx
, SImode
);
17824 t
= XEXP (condition_rtx
, 0);
17826 gcc_assert (cond_code
== NE
|| cond_code
== EQ
);
17828 if (cond_code
== NE
)
17829 emit_insn (gen_e500_flip_gt_bit (t
, t
));
17831 emit_insn (gen_move_from_CR_gt_bit (result
, t
));
17835 if (cond_code
== NE
17836 || cond_code
== GE
|| cond_code
== LE
17837 || cond_code
== GEU
|| cond_code
== LEU
17838 || cond_code
== ORDERED
|| cond_code
== UNGE
|| cond_code
== UNLE
)
17840 rtx not_result
= gen_reg_rtx (CCEQmode
);
17841 rtx not_op
, rev_cond_rtx
;
17842 enum machine_mode cc_mode
;
17844 cc_mode
= GET_MODE (XEXP (condition_rtx
, 0));
17846 rev_cond_rtx
= gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode
, cond_code
),
17847 SImode
, XEXP (condition_rtx
, 0), const0_rtx
);
17848 not_op
= gen_rtx_COMPARE (CCEQmode
, rev_cond_rtx
, const0_rtx
);
17849 emit_insn (gen_rtx_SET (VOIDmode
, not_result
, not_op
));
17850 condition_rtx
= gen_rtx_EQ (VOIDmode
, not_result
, const0_rtx
);
17853 op_mode
= GET_MODE (XEXP (operands
[1], 0));
17854 if (op_mode
== VOIDmode
)
17855 op_mode
= GET_MODE (XEXP (operands
[1], 1));
17857 if (TARGET_POWERPC64
&& (op_mode
== DImode
|| FLOAT_MODE_P (mode
)))
17859 PUT_MODE (condition_rtx
, DImode
);
17860 convert_move (result
, condition_rtx
, 0);
17864 PUT_MODE (condition_rtx
, SImode
);
17865 emit_insn (gen_rtx_SET (VOIDmode
, result
, condition_rtx
));
17869 /* Emit a branch of kind CODE to location LOC. */
17872 rs6000_emit_cbranch (enum machine_mode mode
, rtx operands
[])
17874 rtx condition_rtx
, loc_ref
;
17876 condition_rtx
= rs6000_generate_compare (operands
[0], mode
);
17877 loc_ref
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
17878 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
17879 gen_rtx_IF_THEN_ELSE (VOIDmode
, condition_rtx
,
17880 loc_ref
, pc_rtx
)));
17883 /* Return the string to output a conditional branch to LABEL, which is
17884 the operand template of the label, or NULL if the branch is really a
17885 conditional return.
17887 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
17888 condition code register and its mode specifies what kind of
17889 comparison we made.
17891 REVERSED is nonzero if we should reverse the sense of the comparison.
17893 INSN is the insn. */
17896 output_cbranch (rtx op
, const char *label
, int reversed
, rtx insn
)
17898 static char string
[64];
17899 enum rtx_code code
= GET_CODE (op
);
17900 rtx cc_reg
= XEXP (op
, 0);
17901 enum machine_mode mode
= GET_MODE (cc_reg
);
17902 int cc_regno
= REGNO (cc_reg
) - CR0_REGNO
;
17903 int need_longbranch
= label
!= NULL
&& get_attr_length (insn
) == 8;
17904 int really_reversed
= reversed
^ need_longbranch
;
17910 validate_condition_mode (code
, mode
);
17912 /* Work out which way this really branches. We could use
17913 reverse_condition_maybe_unordered here always but this
17914 makes the resulting assembler clearer. */
17915 if (really_reversed
)
17917 /* Reversal of FP compares takes care -- an ordered compare
17918 becomes an unordered compare and vice versa. */
17919 if (mode
== CCFPmode
)
17920 code
= reverse_condition_maybe_unordered (code
);
17922 code
= reverse_condition (code
);
17925 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
) && mode
== CCFPmode
)
17927 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
17932 /* Opposite of GT. */
17941 gcc_unreachable ();
17947 /* Not all of these are actually distinct opcodes, but
17948 we distinguish them for clarity of the resulting assembler. */
17949 case NE
: case LTGT
:
17950 ccode
= "ne"; break;
17951 case EQ
: case UNEQ
:
17952 ccode
= "eq"; break;
17954 ccode
= "ge"; break;
17955 case GT
: case GTU
: case UNGT
:
17956 ccode
= "gt"; break;
17958 ccode
= "le"; break;
17959 case LT
: case LTU
: case UNLT
:
17960 ccode
= "lt"; break;
17961 case UNORDERED
: ccode
= "un"; break;
17962 case ORDERED
: ccode
= "nu"; break;
17963 case UNGE
: ccode
= "nl"; break;
17964 case UNLE
: ccode
= "ng"; break;
17966 gcc_unreachable ();
17969 /* Maybe we have a guess as to how likely the branch is. */
17971 note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
);
17972 if (note
!= NULL_RTX
)
17974 /* PROB is the difference from 50%. */
17975 int prob
= XINT (note
, 0) - REG_BR_PROB_BASE
/ 2;
17977 /* Only hint for highly probable/improbable branches on newer
17978 cpus as static prediction overrides processor dynamic
17979 prediction. For older cpus we may as well always hint, but
17980 assume not taken for branches that are very close to 50% as a
17981 mispredicted taken branch is more expensive than a
17982 mispredicted not-taken branch. */
17983 if (rs6000_always_hint
17984 || (abs (prob
) > REG_BR_PROB_BASE
/ 100 * 48
17985 && br_prob_note_reliable_p (note
)))
17987 if (abs (prob
) > REG_BR_PROB_BASE
/ 20
17988 && ((prob
> 0) ^ need_longbranch
))
17996 s
+= sprintf (s
, "b%slr%s ", ccode
, pred
);
17998 s
+= sprintf (s
, "b%s%s ", ccode
, pred
);
18000 /* We need to escape any '%' characters in the reg_names string.
18001 Assume they'd only be the first character.... */
18002 if (reg_names
[cc_regno
+ CR0_REGNO
][0] == '%')
18004 s
+= sprintf (s
, "%s", reg_names
[cc_regno
+ CR0_REGNO
]);
18008 /* If the branch distance was too far, we may have to use an
18009 unconditional branch to go the distance. */
18010 if (need_longbranch
)
18011 s
+= sprintf (s
, ",$+8\n\tb %s", label
);
18013 s
+= sprintf (s
, ",%s", label
);
18019 /* Return the string to flip the GT bit on a CR. */
18021 output_e500_flip_gt_bit (rtx dst
, rtx src
)
18023 static char string
[64];
18026 gcc_assert (GET_CODE (dst
) == REG
&& CR_REGNO_P (REGNO (dst
))
18027 && GET_CODE (src
) == REG
&& CR_REGNO_P (REGNO (src
)));
18030 a
= 4 * (REGNO (dst
) - CR0_REGNO
) + 1;
18031 b
= 4 * (REGNO (src
) - CR0_REGNO
) + 1;
18033 sprintf (string
, "crnot %d,%d", a
, b
);
18037 /* Return insn for VSX or Altivec comparisons. */
18040 rs6000_emit_vector_compare_inner (enum rtx_code code
, rtx op0
, rtx op1
)
18043 enum machine_mode mode
= GET_MODE (op0
);
18051 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
18061 mask
= gen_reg_rtx (mode
);
18062 emit_insn (gen_rtx_SET (VOIDmode
,
18064 gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
18071 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
18072 DMODE is expected destination mode. This is a recursive function. */
18075 rs6000_emit_vector_compare (enum rtx_code rcode
,
18077 enum machine_mode dmode
)
18080 bool swap_operands
= false;
18081 bool try_again
= false;
18083 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode
));
18084 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
18086 /* See if the comparison works as is. */
18087 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
18095 swap_operands
= true;
18100 swap_operands
= true;
18108 /* Invert condition and try again.
18109 e.g., A != B becomes ~(A==B). */
18111 enum rtx_code rev_code
;
18112 enum insn_code nor_code
;
18115 rev_code
= reverse_condition_maybe_unordered (rcode
);
18116 if (rev_code
== UNKNOWN
)
18119 nor_code
= optab_handler (one_cmpl_optab
, dmode
);
18120 if (nor_code
== CODE_FOR_nothing
)
18123 mask2
= rs6000_emit_vector_compare (rev_code
, op0
, op1
, dmode
);
18127 mask
= gen_reg_rtx (dmode
);
18128 emit_insn (GEN_FCN (nor_code
) (mask
, mask2
));
18136 /* Try GT/GTU/LT/LTU OR EQ */
18139 enum insn_code ior_code
;
18140 enum rtx_code new_code
;
18161 gcc_unreachable ();
18164 ior_code
= optab_handler (ior_optab
, dmode
);
18165 if (ior_code
== CODE_FOR_nothing
)
18168 c_rtx
= rs6000_emit_vector_compare (new_code
, op0
, op1
, dmode
);
18172 eq_rtx
= rs6000_emit_vector_compare (EQ
, op0
, op1
, dmode
);
18176 mask
= gen_reg_rtx (dmode
);
18177 emit_insn (GEN_FCN (ior_code
) (mask
, c_rtx
, eq_rtx
));
18195 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
18200 /* You only get two chances. */
18204 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
18205 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
18206 operands for the relation operation COND. */
18209 rs6000_emit_vector_cond_expr (rtx dest
, rtx op_true
, rtx op_false
,
18210 rtx cond
, rtx cc_op0
, rtx cc_op1
)
18212 enum machine_mode dest_mode
= GET_MODE (dest
);
18213 enum machine_mode mask_mode
= GET_MODE (cc_op0
);
18214 enum rtx_code rcode
= GET_CODE (cond
);
18215 enum machine_mode cc_mode
= CCmode
;
18219 bool invert_move
= false;
18221 if (VECTOR_UNIT_NONE_P (dest_mode
))
18224 gcc_assert (GET_MODE_SIZE (dest_mode
) == GET_MODE_SIZE (mask_mode
)
18225 && GET_MODE_NUNITS (dest_mode
) == GET_MODE_NUNITS (mask_mode
));
18229 /* Swap operands if we can, and fall back to doing the operation as
18230 specified, and doing a NOR to invert the test. */
18236 /* Invert condition and try again.
18237 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
18238 invert_move
= true;
18239 rcode
= reverse_condition_maybe_unordered (rcode
);
18240 if (rcode
== UNKNOWN
)
18244 /* Mark unsigned tests with CCUNSmode. */
18249 cc_mode
= CCUNSmode
;
18256 /* Get the vector mask for the given relational operations. */
18257 mask
= rs6000_emit_vector_compare (rcode
, cc_op0
, cc_op1
, mask_mode
);
18265 op_true
= op_false
;
18269 cond2
= gen_rtx_fmt_ee (NE
, cc_mode
, gen_lowpart (dest_mode
, mask
),
18270 CONST0_RTX (dest_mode
));
18271 emit_insn (gen_rtx_SET (VOIDmode
,
18273 gen_rtx_IF_THEN_ELSE (dest_mode
,
18280 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
18281 operands of the last comparison is nonzero/true, FALSE_COND if it
18282 is zero/false. Return 0 if the hardware has no such operation. */
18285 rs6000_emit_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
18287 enum rtx_code code
= GET_CODE (op
);
18288 rtx op0
= XEXP (op
, 0);
18289 rtx op1
= XEXP (op
, 1);
18290 REAL_VALUE_TYPE c1
;
18291 enum machine_mode compare_mode
= GET_MODE (op0
);
18292 enum machine_mode result_mode
= GET_MODE (dest
);
18294 bool is_against_zero
;
18296 /* These modes should always match. */
18297 if (GET_MODE (op1
) != compare_mode
18298 /* In the isel case however, we can use a compare immediate, so
18299 op1 may be a small constant. */
18300 && (!TARGET_ISEL
|| !short_cint_operand (op1
, VOIDmode
)))
18302 if (GET_MODE (true_cond
) != result_mode
)
18304 if (GET_MODE (false_cond
) != result_mode
)
18307 /* Don't allow using floating point comparisons for integer results for
18309 if (FLOAT_MODE_P (compare_mode
) && !FLOAT_MODE_P (result_mode
))
18312 /* First, work out if the hardware can do this at all, or
18313 if it's too slow.... */
18314 if (!FLOAT_MODE_P (compare_mode
))
18317 return rs6000_emit_int_cmove (dest
, op
, true_cond
, false_cond
);
18320 else if (TARGET_HARD_FLOAT
&& !TARGET_FPRS
18321 && SCALAR_FLOAT_MODE_P (compare_mode
))
18324 is_against_zero
= op1
== CONST0_RTX (compare_mode
);
18326 /* A floating-point subtract might overflow, underflow, or produce
18327 an inexact result, thus changing the floating-point flags, so it
18328 can't be generated if we care about that. It's safe if one side
18329 of the construct is zero, since then no subtract will be
18331 if (SCALAR_FLOAT_MODE_P (compare_mode
)
18332 && flag_trapping_math
&& ! is_against_zero
)
18335 /* Eliminate half of the comparisons by switching operands, this
18336 makes the remaining code simpler. */
18337 if (code
== UNLT
|| code
== UNGT
|| code
== UNORDERED
|| code
== NE
18338 || code
== LTGT
|| code
== LT
|| code
== UNLE
)
18340 code
= reverse_condition_maybe_unordered (code
);
18342 true_cond
= false_cond
;
18346 /* UNEQ and LTGT take four instructions for a comparison with zero,
18347 it'll probably be faster to use a branch here too. */
18348 if (code
== UNEQ
&& HONOR_NANS (compare_mode
))
18351 if (GET_CODE (op1
) == CONST_DOUBLE
)
18352 REAL_VALUE_FROM_CONST_DOUBLE (c1
, op1
);
18354 /* We're going to try to implement comparisons by performing
18355 a subtract, then comparing against zero. Unfortunately,
18356 Inf - Inf is NaN which is not zero, and so if we don't
18357 know that the operand is finite and the comparison
18358 would treat EQ different to UNORDERED, we can't do it. */
18359 if (HONOR_INFINITIES (compare_mode
)
18360 && code
!= GT
&& code
!= UNGE
18361 && (GET_CODE (op1
) != CONST_DOUBLE
|| real_isinf (&c1
))
18362 /* Constructs of the form (a OP b ? a : b) are safe. */
18363 && ((! rtx_equal_p (op0
, false_cond
) && ! rtx_equal_p (op1
, false_cond
))
18364 || (! rtx_equal_p (op0
, true_cond
)
18365 && ! rtx_equal_p (op1
, true_cond
))))
18368 /* At this point we know we can use fsel. */
18370 /* Reduce the comparison to a comparison against zero. */
18371 if (! is_against_zero
)
18373 temp
= gen_reg_rtx (compare_mode
);
18374 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
18375 gen_rtx_MINUS (compare_mode
, op0
, op1
)));
18377 op1
= CONST0_RTX (compare_mode
);
18380 /* If we don't care about NaNs we can reduce some of the comparisons
18381 down to faster ones. */
18382 if (! HONOR_NANS (compare_mode
))
18388 true_cond
= false_cond
;
18401 /* Now, reduce everything down to a GE. */
18408 temp
= gen_reg_rtx (compare_mode
);
18409 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
18414 temp
= gen_reg_rtx (compare_mode
);
18415 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_ABS (compare_mode
, op0
)));
18420 temp
= gen_reg_rtx (compare_mode
);
18421 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
18422 gen_rtx_NEG (compare_mode
,
18423 gen_rtx_ABS (compare_mode
, op0
))));
18428 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
18429 temp
= gen_reg_rtx (result_mode
);
18430 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
18431 gen_rtx_IF_THEN_ELSE (result_mode
,
18432 gen_rtx_GE (VOIDmode
,
18434 true_cond
, false_cond
)));
18435 false_cond
= true_cond
;
18438 temp
= gen_reg_rtx (compare_mode
);
18439 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
18444 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
18445 temp
= gen_reg_rtx (result_mode
);
18446 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
18447 gen_rtx_IF_THEN_ELSE (result_mode
,
18448 gen_rtx_GE (VOIDmode
,
18450 true_cond
, false_cond
)));
18451 true_cond
= false_cond
;
18454 temp
= gen_reg_rtx (compare_mode
);
18455 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
18460 gcc_unreachable ();
18463 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
18464 gen_rtx_IF_THEN_ELSE (result_mode
,
18465 gen_rtx_GE (VOIDmode
,
18467 true_cond
, false_cond
)));
18471 /* Same as above, but for ints (isel). */
18474 rs6000_emit_int_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
18476 rtx condition_rtx
, cr
;
18477 enum machine_mode mode
= GET_MODE (dest
);
18478 enum rtx_code cond_code
;
18479 rtx (*isel_func
) (rtx
, rtx
, rtx
, rtx
, rtx
);
18482 if (mode
!= SImode
&& (!TARGET_POWERPC64
|| mode
!= DImode
))
18485 /* We still have to do the compare, because isel doesn't do a
18486 compare, it just looks at the CRx bits set by a previous compare
18488 condition_rtx
= rs6000_generate_compare (op
, mode
);
18489 cond_code
= GET_CODE (condition_rtx
);
18490 cr
= XEXP (condition_rtx
, 0);
18491 signedp
= GET_MODE (cr
) == CCmode
;
18493 isel_func
= (mode
== SImode
18494 ? (signedp
? gen_isel_signed_si
: gen_isel_unsigned_si
)
18495 : (signedp
? gen_isel_signed_di
: gen_isel_unsigned_di
));
18499 case LT
: case GT
: case LTU
: case GTU
: case EQ
:
18500 /* isel handles these directly. */
18504 /* We need to swap the sense of the comparison. */
18507 true_cond
= false_cond
;
18509 PUT_CODE (condition_rtx
, reverse_condition (cond_code
));
18514 false_cond
= force_reg (mode
, false_cond
);
18515 if (true_cond
!= const0_rtx
)
18516 true_cond
= force_reg (mode
, true_cond
);
18518 emit_insn (isel_func (dest
, condition_rtx
, true_cond
, false_cond
, cr
));
18524 output_isel (rtx
*operands
)
18526 enum rtx_code code
;
18528 code
= GET_CODE (operands
[1]);
18530 if (code
== GE
|| code
== GEU
|| code
== LE
|| code
== LEU
|| code
== NE
)
18532 gcc_assert (GET_CODE (operands
[2]) == REG
18533 && GET_CODE (operands
[3]) == REG
);
18534 PUT_CODE (operands
[1], reverse_condition (code
));
18535 return "isel %0,%3,%2,%j1";
18538 return "isel %0,%2,%3,%j1";
18542 rs6000_emit_minmax (rtx dest
, enum rtx_code code
, rtx op0
, rtx op1
)
18544 enum machine_mode mode
= GET_MODE (op0
);
18548 /* VSX/altivec have direct min/max insns. */
18549 if ((code
== SMAX
|| code
== SMIN
)
18550 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
18551 || (mode
== SFmode
&& VECTOR_UNIT_VSX_P (DFmode
))))
18553 emit_insn (gen_rtx_SET (VOIDmode
,
18555 gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
18559 if (code
== SMAX
|| code
== SMIN
)
18564 if (code
== SMAX
|| code
== UMAX
)
18565 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
18566 op0
, op1
, mode
, 0);
18568 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
18569 op1
, op0
, mode
, 0);
18570 gcc_assert (target
);
18571 if (target
!= dest
)
18572 emit_move_insn (dest
, target
);
18575 /* A subroutine of the atomic operation splitters. Jump to LABEL if
18576 COND is true. Mark the jump as unlikely to be taken. */
18579 emit_unlikely_jump (rtx cond
, rtx label
)
18581 int very_unlikely
= REG_BR_PROB_BASE
/ 100 - 1;
18584 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, label
, pc_rtx
);
18585 x
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, x
));
18586 add_int_reg_note (x
, REG_BR_PROB
, very_unlikely
);
18589 /* A subroutine of the atomic operation splitters. Emit a load-locked
18590 instruction in MODE. For QI/HImode, possibly use a pattern than includes
18591 the zero_extend operation. */
18594 emit_load_locked (enum machine_mode mode
, rtx reg
, rtx mem
)
18596 rtx (*fn
) (rtx
, rtx
) = NULL
;
18601 fn
= gen_load_lockedqi
;
18604 fn
= gen_load_lockedhi
;
18607 if (GET_MODE (mem
) == QImode
)
18608 fn
= gen_load_lockedqi_si
;
18609 else if (GET_MODE (mem
) == HImode
)
18610 fn
= gen_load_lockedhi_si
;
18612 fn
= gen_load_lockedsi
;
18615 fn
= gen_load_lockeddi
;
18618 fn
= gen_load_lockedti
;
18621 gcc_unreachable ();
18623 emit_insn (fn (reg
, mem
));
18626 /* A subroutine of the atomic operation splitters. Emit a store-conditional
18627 instruction in MODE. */
18630 emit_store_conditional (enum machine_mode mode
, rtx res
, rtx mem
, rtx val
)
18632 rtx (*fn
) (rtx
, rtx
, rtx
) = NULL
;
18637 fn
= gen_store_conditionalqi
;
18640 fn
= gen_store_conditionalhi
;
18643 fn
= gen_store_conditionalsi
;
18646 fn
= gen_store_conditionaldi
;
18649 fn
= gen_store_conditionalti
;
18652 gcc_unreachable ();
18655 /* Emit sync before stwcx. to address PPC405 Erratum. */
18656 if (PPC405_ERRATUM77
)
18657 emit_insn (gen_hwsync ());
18659 emit_insn (fn (res
, mem
, val
));
18662 /* Expand barriers before and after a load_locked/store_cond sequence. */
18665 rs6000_pre_atomic_barrier (rtx mem
, enum memmodel model
)
18667 rtx addr
= XEXP (mem
, 0);
18668 int strict_p
= (reload_in_progress
|| reload_completed
);
18670 if (!legitimate_indirect_address_p (addr
, strict_p
)
18671 && !legitimate_indexed_address_p (addr
, strict_p
))
18673 addr
= force_reg (Pmode
, addr
);
18674 mem
= replace_equiv_address_nv (mem
, addr
);
18679 case MEMMODEL_RELAXED
:
18680 case MEMMODEL_CONSUME
:
18681 case MEMMODEL_ACQUIRE
:
18683 case MEMMODEL_RELEASE
:
18684 case MEMMODEL_ACQ_REL
:
18685 emit_insn (gen_lwsync ());
18687 case MEMMODEL_SEQ_CST
:
18688 emit_insn (gen_hwsync ());
18691 gcc_unreachable ();
18697 rs6000_post_atomic_barrier (enum memmodel model
)
18701 case MEMMODEL_RELAXED
:
18702 case MEMMODEL_CONSUME
:
18703 case MEMMODEL_RELEASE
:
18705 case MEMMODEL_ACQUIRE
:
18706 case MEMMODEL_ACQ_REL
:
18707 case MEMMODEL_SEQ_CST
:
18708 emit_insn (gen_isync ());
18711 gcc_unreachable ();
18715 /* A subroutine of the various atomic expanders. For sub-word operations,
18716 we must adjust things to operate on SImode. Given the original MEM,
18717 return a new aligned memory. Also build and return the quantities by
18718 which to shift and mask. */
18721 rs6000_adjust_atomic_subword (rtx orig_mem
, rtx
*pshift
, rtx
*pmask
)
18723 rtx addr
, align
, shift
, mask
, mem
;
18724 HOST_WIDE_INT shift_mask
;
18725 enum machine_mode mode
= GET_MODE (orig_mem
);
18727 /* For smaller modes, we have to implement this via SImode. */
18728 shift_mask
= (mode
== QImode
? 0x18 : 0x10);
18730 addr
= XEXP (orig_mem
, 0);
18731 addr
= force_reg (GET_MODE (addr
), addr
);
18733 /* Aligned memory containing subword. Generate a new memory. We
18734 do not want any of the existing MEM_ATTR data, as we're now
18735 accessing memory outside the original object. */
18736 align
= expand_simple_binop (Pmode
, AND
, addr
, GEN_INT (-4),
18737 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
18738 mem
= gen_rtx_MEM (SImode
, align
);
18739 MEM_VOLATILE_P (mem
) = MEM_VOLATILE_P (orig_mem
);
18740 if (MEM_ALIAS_SET (orig_mem
) == ALIAS_SET_MEMORY_BARRIER
)
18741 set_mem_alias_set (mem
, ALIAS_SET_MEMORY_BARRIER
);
18743 /* Shift amount for subword relative to aligned word. */
18744 shift
= gen_reg_rtx (SImode
);
18745 addr
= gen_lowpart (SImode
, addr
);
18746 emit_insn (gen_rlwinm (shift
, addr
, GEN_INT (3), GEN_INT (shift_mask
)));
18747 if (WORDS_BIG_ENDIAN
)
18748 shift
= expand_simple_binop (SImode
, XOR
, shift
, GEN_INT (shift_mask
),
18749 shift
, 1, OPTAB_LIB_WIDEN
);
18752 /* Mask for insertion. */
18753 mask
= expand_simple_binop (SImode
, ASHIFT
, GEN_INT (GET_MODE_MASK (mode
)),
18754 shift
, NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
18760 /* A subroutine of the various atomic expanders. For sub-word operands,
18761 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
18764 rs6000_mask_atomic_subword (rtx oldval
, rtx newval
, rtx mask
)
18768 x
= gen_reg_rtx (SImode
);
18769 emit_insn (gen_rtx_SET (VOIDmode
, x
,
18770 gen_rtx_AND (SImode
,
18771 gen_rtx_NOT (SImode
, mask
),
18774 x
= expand_simple_binop (SImode
, IOR
, newval
, x
, x
, 1, OPTAB_LIB_WIDEN
);
18779 /* A subroutine of the various atomic expanders. For sub-word operands,
18780 extract WIDE to NARROW via SHIFT. */
18783 rs6000_finish_atomic_subword (rtx narrow
, rtx wide
, rtx shift
)
18785 wide
= expand_simple_binop (SImode
, LSHIFTRT
, wide
, shift
,
18786 wide
, 1, OPTAB_LIB_WIDEN
);
18787 emit_move_insn (narrow
, gen_lowpart (GET_MODE (narrow
), wide
));
18790 /* Expand an atomic compare and swap operation. */
18793 rs6000_expand_atomic_compare_and_swap (rtx operands
[])
18795 rtx boolval
, retval
, mem
, oldval
, newval
, cond
;
18796 rtx label1
, label2
, x
, mask
, shift
;
18797 enum machine_mode mode
, orig_mode
;
18798 enum memmodel mod_s
, mod_f
;
18801 boolval
= operands
[0];
18802 retval
= operands
[1];
18804 oldval
= operands
[3];
18805 newval
= operands
[4];
18806 is_weak
= (INTVAL (operands
[5]) != 0);
18807 mod_s
= (enum memmodel
) INTVAL (operands
[6]);
18808 mod_f
= (enum memmodel
) INTVAL (operands
[7]);
18809 orig_mode
= mode
= GET_MODE (mem
);
18811 mask
= shift
= NULL_RTX
;
18812 if (mode
== QImode
|| mode
== HImode
)
18814 /* Before power8, we didn't have access to lbarx/lharx, so generate a
18815 lwarx and shift/mask operations. With power8, we need to do the
18816 comparison in SImode, but the store is still done in QI/HImode. */
18817 oldval
= convert_modes (SImode
, mode
, oldval
, 1);
18819 if (!TARGET_SYNC_HI_QI
)
18821 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
18823 /* Shift and mask OLDVAL into position with the word. */
18824 oldval
= expand_simple_binop (SImode
, ASHIFT
, oldval
, shift
,
18825 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
18827 /* Shift and mask NEWVAL into position within the word. */
18828 newval
= convert_modes (SImode
, mode
, newval
, 1);
18829 newval
= expand_simple_binop (SImode
, ASHIFT
, newval
, shift
,
18830 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
18833 /* Prepare to adjust the return value. */
18834 retval
= gen_reg_rtx (SImode
);
18837 else if (reg_overlap_mentioned_p (retval
, oldval
))
18838 oldval
= copy_to_reg (oldval
);
18840 mem
= rs6000_pre_atomic_barrier (mem
, mod_s
);
18845 label1
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
18846 emit_label (XEXP (label1
, 0));
18848 label2
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
18850 emit_load_locked (mode
, retval
, mem
);
18855 x
= expand_simple_binop (SImode
, AND
, retval
, mask
,
18856 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
18859 cond
= gen_reg_rtx (CCmode
);
18860 /* If we have TImode, synthesize a comparison. */
18861 if (mode
!= TImode
)
18862 x
= gen_rtx_COMPARE (CCmode
, x
, oldval
);
18865 rtx xor1_result
= gen_reg_rtx (DImode
);
18866 rtx xor2_result
= gen_reg_rtx (DImode
);
18867 rtx or_result
= gen_reg_rtx (DImode
);
18868 rtx new_word0
= simplify_gen_subreg (DImode
, x
, TImode
, 0);
18869 rtx new_word1
= simplify_gen_subreg (DImode
, x
, TImode
, 8);
18870 rtx old_word0
= simplify_gen_subreg (DImode
, oldval
, TImode
, 0);
18871 rtx old_word1
= simplify_gen_subreg (DImode
, oldval
, TImode
, 8);
18873 emit_insn (gen_xordi3 (xor1_result
, new_word0
, old_word0
));
18874 emit_insn (gen_xordi3 (xor2_result
, new_word1
, old_word1
));
18875 emit_insn (gen_iordi3 (or_result
, xor1_result
, xor2_result
));
18876 x
= gen_rtx_COMPARE (CCmode
, or_result
, const0_rtx
);
18879 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
18881 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
18882 emit_unlikely_jump (x
, label2
);
18886 x
= rs6000_mask_atomic_subword (retval
, newval
, mask
);
18888 emit_store_conditional (orig_mode
, cond
, mem
, x
);
18892 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
18893 emit_unlikely_jump (x
, label1
);
18896 if (mod_f
!= MEMMODEL_RELAXED
)
18897 emit_label (XEXP (label2
, 0));
18899 rs6000_post_atomic_barrier (mod_s
);
18901 if (mod_f
== MEMMODEL_RELAXED
)
18902 emit_label (XEXP (label2
, 0));
18905 rs6000_finish_atomic_subword (operands
[1], retval
, shift
);
18906 else if (mode
!= GET_MODE (operands
[1]))
18907 convert_move (operands
[1], retval
, 1);
18909 /* In all cases, CR0 contains EQ on success, and NE on failure. */
18910 x
= gen_rtx_EQ (SImode
, cond
, const0_rtx
);
18911 emit_insn (gen_rtx_SET (VOIDmode
, boolval
, x
));
18914 /* Expand an atomic exchange operation. */
18917 rs6000_expand_atomic_exchange (rtx operands
[])
18919 rtx retval
, mem
, val
, cond
;
18920 enum machine_mode mode
;
18921 enum memmodel model
;
18922 rtx label
, x
, mask
, shift
;
18924 retval
= operands
[0];
18927 model
= (enum memmodel
) INTVAL (operands
[3]);
18928 mode
= GET_MODE (mem
);
18930 mask
= shift
= NULL_RTX
;
18931 if (!TARGET_SYNC_HI_QI
&& (mode
== QImode
|| mode
== HImode
))
18933 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
18935 /* Shift and mask VAL into position with the word. */
18936 val
= convert_modes (SImode
, mode
, val
, 1);
18937 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
18938 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
18940 /* Prepare to adjust the return value. */
18941 retval
= gen_reg_rtx (SImode
);
18945 mem
= rs6000_pre_atomic_barrier (mem
, model
);
18947 label
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
18948 emit_label (XEXP (label
, 0));
18950 emit_load_locked (mode
, retval
, mem
);
18954 x
= rs6000_mask_atomic_subword (retval
, val
, mask
);
18956 cond
= gen_reg_rtx (CCmode
);
18957 emit_store_conditional (mode
, cond
, mem
, x
);
18959 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
18960 emit_unlikely_jump (x
, label
);
18962 rs6000_post_atomic_barrier (model
);
18965 rs6000_finish_atomic_subword (operands
[0], retval
, shift
);
18968 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
18969 to perform. MEM is the memory on which to operate. VAL is the second
18970 operand of the binary operator. BEFORE and AFTER are optional locations to
18971 return the value of MEM either before of after the operation. MODEL_RTX
18972 is a CONST_INT containing the memory model to use. */
18975 rs6000_expand_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
18976 rtx orig_before
, rtx orig_after
, rtx model_rtx
)
18978 enum memmodel model
= (enum memmodel
) INTVAL (model_rtx
);
18979 enum machine_mode mode
= GET_MODE (mem
);
18980 enum machine_mode store_mode
= mode
;
18981 rtx label
, x
, cond
, mask
, shift
;
18982 rtx before
= orig_before
, after
= orig_after
;
18984 mask
= shift
= NULL_RTX
;
18985 /* On power8, we want to use SImode for the operation. On previous systems,
18986 use the operation in a subword and shift/mask to get the proper byte or
18988 if (mode
== QImode
|| mode
== HImode
)
18990 if (TARGET_SYNC_HI_QI
)
18992 val
= convert_modes (SImode
, mode
, val
, 1);
18994 /* Prepare to adjust the return value. */
18995 before
= gen_reg_rtx (SImode
);
18997 after
= gen_reg_rtx (SImode
);
19002 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
19004 /* Shift and mask VAL into position with the word. */
19005 val
= convert_modes (SImode
, mode
, val
, 1);
19006 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
19007 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19013 /* We've already zero-extended VAL. That is sufficient to
19014 make certain that it does not affect other bits. */
19019 /* If we make certain that all of the other bits in VAL are
19020 set, that will be sufficient to not affect other bits. */
19021 x
= gen_rtx_NOT (SImode
, mask
);
19022 x
= gen_rtx_IOR (SImode
, x
, val
);
19023 emit_insn (gen_rtx_SET (VOIDmode
, val
, x
));
19030 /* These will all affect bits outside the field and need
19031 adjustment via MASK within the loop. */
19035 gcc_unreachable ();
19038 /* Prepare to adjust the return value. */
19039 before
= gen_reg_rtx (SImode
);
19041 after
= gen_reg_rtx (SImode
);
19042 store_mode
= mode
= SImode
;
19046 mem
= rs6000_pre_atomic_barrier (mem
, model
);
19048 label
= gen_label_rtx ();
19049 emit_label (label
);
19050 label
= gen_rtx_LABEL_REF (VOIDmode
, label
);
19052 if (before
== NULL_RTX
)
19053 before
= gen_reg_rtx (mode
);
19055 emit_load_locked (mode
, before
, mem
);
19059 x
= expand_simple_binop (mode
, AND
, before
, val
,
19060 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19061 after
= expand_simple_unop (mode
, NOT
, x
, after
, 1);
19065 after
= expand_simple_binop (mode
, code
, before
, val
,
19066 after
, 1, OPTAB_LIB_WIDEN
);
19072 x
= expand_simple_binop (SImode
, AND
, after
, mask
,
19073 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19074 x
= rs6000_mask_atomic_subword (before
, x
, mask
);
19076 else if (store_mode
!= mode
)
19077 x
= convert_modes (store_mode
, mode
, x
, 1);
19079 cond
= gen_reg_rtx (CCmode
);
19080 emit_store_conditional (store_mode
, cond
, mem
, x
);
19082 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
19083 emit_unlikely_jump (x
, label
);
19085 rs6000_post_atomic_barrier (model
);
19089 /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and
19090 then do the calcuations in a SImode register. */
19092 rs6000_finish_atomic_subword (orig_before
, before
, shift
);
19094 rs6000_finish_atomic_subword (orig_after
, after
, shift
);
19096 else if (store_mode
!= mode
)
19098 /* QImode/HImode on machines with lbarx/lharx where we do the native
19099 operation and then do the calcuations in a SImode register. */
19101 convert_move (orig_before
, before
, 1);
19103 convert_move (orig_after
, after
, 1);
19105 else if (orig_after
&& after
!= orig_after
)
19106 emit_move_insn (orig_after
, after
);
19109 /* Emit instructions to move SRC to DST. Called by splitters for
19110 multi-register moves. It will emit at most one instruction for
19111 each register that is accessed; that is, it won't emit li/lis pairs
19112 (or equivalent for 64-bit code). One of SRC or DST must be a hard
19116 rs6000_split_multireg_move (rtx dst
, rtx src
)
19118 /* The register number of the first register being moved. */
19120 /* The mode that is to be moved. */
19121 enum machine_mode mode
;
19122 /* The mode that the move is being done in, and its size. */
19123 enum machine_mode reg_mode
;
19125 /* The number of registers that will be moved. */
19128 reg
= REG_P (dst
) ? REGNO (dst
) : REGNO (src
);
19129 mode
= GET_MODE (dst
);
19130 nregs
= hard_regno_nregs
[reg
][mode
];
19131 if (FP_REGNO_P (reg
))
19132 reg_mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
:
19133 ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? DFmode
: SFmode
);
19134 else if (ALTIVEC_REGNO_P (reg
))
19135 reg_mode
= V16QImode
;
19136 else if (TARGET_E500_DOUBLE
&& mode
== TFmode
)
19139 reg_mode
= word_mode
;
19140 reg_mode_size
= GET_MODE_SIZE (reg_mode
);
19142 gcc_assert (reg_mode_size
* nregs
== GET_MODE_SIZE (mode
));
19144 if (REG_P (src
) && REG_P (dst
) && (REGNO (src
) < REGNO (dst
)))
19146 /* Move register range backwards, if we might have destructive
19149 for (i
= nregs
- 1; i
>= 0; i
--)
19150 emit_insn (gen_rtx_SET (VOIDmode
,
19151 simplify_gen_subreg (reg_mode
, dst
, mode
,
19152 i
* reg_mode_size
),
19153 simplify_gen_subreg (reg_mode
, src
, mode
,
19154 i
* reg_mode_size
)));
19160 bool used_update
= false;
19161 rtx restore_basereg
= NULL_RTX
;
19163 if (MEM_P (src
) && INT_REGNO_P (reg
))
19167 if (GET_CODE (XEXP (src
, 0)) == PRE_INC
19168 || GET_CODE (XEXP (src
, 0)) == PRE_DEC
)
19171 breg
= XEXP (XEXP (src
, 0), 0);
19172 delta_rtx
= (GET_CODE (XEXP (src
, 0)) == PRE_INC
19173 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src
)))
19174 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src
))));
19175 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
19176 src
= replace_equiv_address (src
, breg
);
19178 else if (! rs6000_offsettable_memref_p (src
, reg_mode
))
19180 if (GET_CODE (XEXP (src
, 0)) == PRE_MODIFY
)
19182 rtx basereg
= XEXP (XEXP (src
, 0), 0);
19185 rtx ndst
= simplify_gen_subreg (reg_mode
, dst
, mode
, 0);
19186 emit_insn (gen_rtx_SET (VOIDmode
, ndst
,
19187 gen_rtx_MEM (reg_mode
, XEXP (src
, 0))));
19188 used_update
= true;
19191 emit_insn (gen_rtx_SET (VOIDmode
, basereg
,
19192 XEXP (XEXP (src
, 0), 1)));
19193 src
= replace_equiv_address (src
, basereg
);
19197 rtx basereg
= gen_rtx_REG (Pmode
, reg
);
19198 emit_insn (gen_rtx_SET (VOIDmode
, basereg
, XEXP (src
, 0)));
19199 src
= replace_equiv_address (src
, basereg
);
19203 breg
= XEXP (src
, 0);
19204 if (GET_CODE (breg
) == PLUS
|| GET_CODE (breg
) == LO_SUM
)
19205 breg
= XEXP (breg
, 0);
19207 /* If the base register we are using to address memory is
19208 also a destination reg, then change that register last. */
19210 && REGNO (breg
) >= REGNO (dst
)
19211 && REGNO (breg
) < REGNO (dst
) + nregs
)
19212 j
= REGNO (breg
) - REGNO (dst
);
19214 else if (MEM_P (dst
) && INT_REGNO_P (reg
))
19218 if (GET_CODE (XEXP (dst
, 0)) == PRE_INC
19219 || GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
19222 breg
= XEXP (XEXP (dst
, 0), 0);
19223 delta_rtx
= (GET_CODE (XEXP (dst
, 0)) == PRE_INC
19224 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst
)))
19225 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst
))));
19227 /* We have to update the breg before doing the store.
19228 Use store with update, if available. */
19232 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
19233 emit_insn (TARGET_32BIT
19234 ? (TARGET_POWERPC64
19235 ? gen_movdi_si_update (breg
, breg
, delta_rtx
, nsrc
)
19236 : gen_movsi_update (breg
, breg
, delta_rtx
, nsrc
))
19237 : gen_movdi_di_update (breg
, breg
, delta_rtx
, nsrc
));
19238 used_update
= true;
19241 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
19242 dst
= replace_equiv_address (dst
, breg
);
19244 else if (!rs6000_offsettable_memref_p (dst
, reg_mode
)
19245 && GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
19247 if (GET_CODE (XEXP (dst
, 0)) == PRE_MODIFY
)
19249 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
19252 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
19253 emit_insn (gen_rtx_SET (VOIDmode
,
19254 gen_rtx_MEM (reg_mode
, XEXP (dst
, 0)), nsrc
));
19255 used_update
= true;
19258 emit_insn (gen_rtx_SET (VOIDmode
, basereg
,
19259 XEXP (XEXP (dst
, 0), 1)));
19260 dst
= replace_equiv_address (dst
, basereg
);
19264 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
19265 rtx offsetreg
= XEXP (XEXP (dst
, 0), 1);
19266 gcc_assert (GET_CODE (XEXP (dst
, 0)) == PLUS
19268 && REG_P (offsetreg
)
19269 && REGNO (basereg
) != REGNO (offsetreg
));
19270 if (REGNO (basereg
) == 0)
19272 rtx tmp
= offsetreg
;
19273 offsetreg
= basereg
;
19276 emit_insn (gen_add3_insn (basereg
, basereg
, offsetreg
));
19277 restore_basereg
= gen_sub3_insn (basereg
, basereg
, offsetreg
);
19278 dst
= replace_equiv_address (dst
, basereg
);
19281 else if (GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
19282 gcc_assert (rs6000_offsettable_memref_p (dst
, reg_mode
));
19285 for (i
= 0; i
< nregs
; i
++)
19287 /* Calculate index to next subword. */
19292 /* If compiler already emitted move of first word by
19293 store with update, no need to do anything. */
19294 if (j
== 0 && used_update
)
19297 emit_insn (gen_rtx_SET (VOIDmode
,
19298 simplify_gen_subreg (reg_mode
, dst
, mode
,
19299 j
* reg_mode_size
),
19300 simplify_gen_subreg (reg_mode
, src
, mode
,
19301 j
* reg_mode_size
)));
19303 if (restore_basereg
!= NULL_RTX
)
19304 emit_insn (restore_basereg
);
19309 /* This page contains routines that are used to determine what the
19310 function prologue and epilogue code will do and write them out. */
19315 return !call_used_regs
[r
] && df_regs_ever_live_p (r
);
19318 /* Return the first fixed-point register that is required to be
19319 saved. 32 if none. */
19322 first_reg_to_save (void)
19326 /* Find lowest numbered live register. */
19327 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
19328 if (save_reg_p (first_reg
))
19331 if (first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
19332 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
19333 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
19334 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
))
19335 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
19336 first_reg
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
19340 && crtl
->uses_pic_offset_table
19341 && first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
19342 return RS6000_PIC_OFFSET_TABLE_REGNUM
;
19348 /* Similar, for FP regs. */
19351 first_fp_reg_to_save (void)
19355 /* Find lowest numbered live register. */
19356 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
19357 if (save_reg_p (first_reg
))
19363 /* Similar, for AltiVec regs. */
19366 first_altivec_reg_to_save (void)
19370 /* Stack frame remains as is unless we are in AltiVec ABI. */
19371 if (! TARGET_ALTIVEC_ABI
)
19372 return LAST_ALTIVEC_REGNO
+ 1;
19374 /* On Darwin, the unwind routines are compiled without
19375 TARGET_ALTIVEC, and use save_world to save/restore the
19376 altivec registers when necessary. */
19377 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
19378 && ! TARGET_ALTIVEC
)
19379 return FIRST_ALTIVEC_REGNO
+ 20;
19381 /* Find lowest numbered live register. */
19382 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
<= LAST_ALTIVEC_REGNO
; ++i
)
19383 if (save_reg_p (i
))
19389 /* Return a 32-bit mask of the AltiVec registers we need to set in
19390 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
19391 the 32-bit word is 0. */
19393 static unsigned int
19394 compute_vrsave_mask (void)
19396 unsigned int i
, mask
= 0;
19398 /* On Darwin, the unwind routines are compiled without
19399 TARGET_ALTIVEC, and use save_world to save/restore the
19400 call-saved altivec registers when necessary. */
19401 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
19402 && ! TARGET_ALTIVEC
)
19405 /* First, find out if we use _any_ altivec registers. */
19406 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
19407 if (df_regs_ever_live_p (i
))
19408 mask
|= ALTIVEC_REG_BIT (i
);
19413 /* Next, remove the argument registers from the set. These must
19414 be in the VRSAVE mask set by the caller, so we don't need to add
19415 them in again. More importantly, the mask we compute here is
19416 used to generate CLOBBERs in the set_vrsave insn, and we do not
19417 wish the argument registers to die. */
19418 for (i
= crtl
->args
.info
.vregno
- 1; i
>= ALTIVEC_ARG_MIN_REG
; --i
)
19419 mask
&= ~ALTIVEC_REG_BIT (i
);
19421 /* Similarly, remove the return value from the set. */
19424 diddle_return_value (is_altivec_return_reg
, &yes
);
19426 mask
&= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN
);
19432 /* For a very restricted set of circumstances, we can cut down the
19433 size of prologues/epilogues by calling our own save/restore-the-world
19437 compute_save_world_info (rs6000_stack_t
*info_ptr
)
19439 info_ptr
->world_save_p
= 1;
19440 info_ptr
->world_save_p
19441 = (WORLD_SAVE_P (info_ptr
)
19442 && DEFAULT_ABI
== ABI_DARWIN
19443 && !cfun
->has_nonlocal_label
19444 && info_ptr
->first_fp_reg_save
== FIRST_SAVED_FP_REGNO
19445 && info_ptr
->first_gp_reg_save
== FIRST_SAVED_GP_REGNO
19446 && info_ptr
->first_altivec_reg_save
== FIRST_SAVED_ALTIVEC_REGNO
19447 && info_ptr
->cr_save_p
);
19449 /* This will not work in conjunction with sibcalls. Make sure there
19450 are none. (This check is expensive, but seldom executed.) */
19451 if (WORLD_SAVE_P (info_ptr
))
19454 for (insn
= get_last_insn_anywhere (); insn
; insn
= PREV_INSN (insn
))
19455 if (CALL_P (insn
) && SIBLING_CALL_P (insn
))
19457 info_ptr
->world_save_p
= 0;
19462 if (WORLD_SAVE_P (info_ptr
))
19464 /* Even if we're not touching VRsave, make sure there's room on the
19465 stack for it, if it looks like we're calling SAVE_WORLD, which
19466 will attempt to save it. */
19467 info_ptr
->vrsave_size
= 4;
19469 /* If we are going to save the world, we need to save the link register too. */
19470 info_ptr
->lr_save_p
= 1;
19472 /* "Save" the VRsave register too if we're saving the world. */
19473 if (info_ptr
->vrsave_mask
== 0)
19474 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
19476 /* Because the Darwin register save/restore routines only handle
19477 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
19479 gcc_assert (info_ptr
->first_fp_reg_save
>= FIRST_SAVED_FP_REGNO
19480 && (info_ptr
->first_altivec_reg_save
19481 >= FIRST_SAVED_ALTIVEC_REGNO
));
19488 is_altivec_return_reg (rtx reg
, void *xyes
)
19490 bool *yes
= (bool *) xyes
;
19491 if (REGNO (reg
) == ALTIVEC_ARG_RETURN
)
19496 /* Look for user-defined global regs in the range FIRST to LAST-1.
19497 We should not restore these, and so cannot use lmw or out-of-line
19498 restore functions if there are any. We also can't save them
19499 (well, emit frame notes for them), because frame unwinding during
19500 exception handling will restore saved registers. */
19503 global_regs_p (unsigned first
, unsigned last
)
19505 while (first
< last
)
19506 if (global_regs
[first
++])
19511 /* Determine the strategy for savings/restoring registers. */
19514 SAVRES_MULTIPLE
= 0x1,
19515 SAVE_INLINE_FPRS
= 0x2,
19516 SAVE_INLINE_GPRS
= 0x4,
19517 REST_INLINE_FPRS
= 0x8,
19518 REST_INLINE_GPRS
= 0x10,
19519 SAVE_NOINLINE_GPRS_SAVES_LR
= 0x20,
19520 SAVE_NOINLINE_FPRS_SAVES_LR
= 0x40,
19521 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
= 0x80,
19522 SAVE_INLINE_VRS
= 0x100,
19523 REST_INLINE_VRS
= 0x200
19527 rs6000_savres_strategy (rs6000_stack_t
*info
,
19528 bool using_static_chain_p
)
19533 if (TARGET_MULTIPLE
19534 && !TARGET_POWERPC64
19535 && !(TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
)
19536 && info
->first_gp_reg_save
< 31
19537 && !global_regs_p (info
->first_gp_reg_save
, 32))
19538 strategy
|= SAVRES_MULTIPLE
;
19540 if (crtl
->calls_eh_return
19541 || cfun
->machine
->ra_need_lr
)
19542 strategy
|= (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
19543 | SAVE_INLINE_GPRS
| REST_INLINE_GPRS
19544 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
19546 if (info
->first_fp_reg_save
== 64
19547 /* The out-of-line FP routines use double-precision stores;
19548 we can't use those routines if we don't have such stores. */
19549 || (TARGET_HARD_FLOAT
&& !TARGET_DOUBLE_FLOAT
)
19550 || global_regs_p (info
->first_fp_reg_save
, 64))
19551 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
19553 if (info
->first_gp_reg_save
== 32
19554 || (!(strategy
& SAVRES_MULTIPLE
)
19555 && global_regs_p (info
->first_gp_reg_save
, 32)))
19556 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
19558 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
19559 || global_regs_p (info
->first_altivec_reg_save
, LAST_ALTIVEC_REGNO
+ 1))
19560 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
19562 /* Define cutoff for using out-of-line functions to save registers. */
19563 if (DEFAULT_ABI
== ABI_V4
|| TARGET_ELF
)
19565 if (!optimize_size
)
19567 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
19568 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
19569 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
19573 /* Prefer out-of-line restore if it will exit. */
19574 if (info
->first_fp_reg_save
> 61)
19575 strategy
|= SAVE_INLINE_FPRS
;
19576 if (info
->first_gp_reg_save
> 29)
19578 if (info
->first_fp_reg_save
== 64)
19579 strategy
|= SAVE_INLINE_GPRS
;
19581 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
19583 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
)
19584 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
19587 else if (DEFAULT_ABI
== ABI_DARWIN
)
19589 if (info
->first_fp_reg_save
> 60)
19590 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
19591 if (info
->first_gp_reg_save
> 29)
19592 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
19593 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
19597 gcc_checking_assert (DEFAULT_ABI
== ABI_AIX
);
19598 if (info
->first_fp_reg_save
> 61)
19599 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
19600 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
19601 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
19604 /* Don't bother to try to save things out-of-line if r11 is occupied
19605 by the static chain. It would require too much fiddling and the
19606 static chain is rarely used anyway. FPRs are saved w.r.t the stack
19607 pointer on Darwin, and AIX uses r1 or r12. */
19608 if (using_static_chain_p
&& DEFAULT_ABI
!= ABI_AIX
)
19609 strategy
|= ((DEFAULT_ABI
== ABI_DARWIN
? 0 : SAVE_INLINE_FPRS
)
19611 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
19613 /* We can only use the out-of-line routines to restore if we've
19614 saved all the registers from first_fp_reg_save in the prologue.
19615 Otherwise, we risk loading garbage. */
19616 if ((strategy
& (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
)) == SAVE_INLINE_FPRS
)
19620 for (i
= info
->first_fp_reg_save
; i
< 64; i
++)
19621 if (!save_reg_p (i
))
19623 strategy
|= REST_INLINE_FPRS
;
19628 /* If we are going to use store multiple, then don't even bother
19629 with the out-of-line routines, since the store-multiple
19630 instruction will always be smaller. */
19631 if ((strategy
& SAVRES_MULTIPLE
))
19632 strategy
|= SAVE_INLINE_GPRS
;
19634 /* info->lr_save_p isn't yet set if the only reason lr needs to be
19635 saved is an out-of-line save or restore. Set up the value for
19636 the next test (excluding out-of-line gpr restore). */
19637 lr_save_p
= (info
->lr_save_p
19638 || !(strategy
& SAVE_INLINE_GPRS
)
19639 || !(strategy
& SAVE_INLINE_FPRS
)
19640 || !(strategy
& SAVE_INLINE_VRS
)
19641 || !(strategy
& REST_INLINE_FPRS
)
19642 || !(strategy
& REST_INLINE_VRS
));
19644 /* The situation is more complicated with load multiple. We'd
19645 prefer to use the out-of-line routines for restores, since the
19646 "exit" out-of-line routines can handle the restore of LR and the
19647 frame teardown. However if doesn't make sense to use the
19648 out-of-line routine if that is the only reason we'd need to save
19649 LR, and we can't use the "exit" out-of-line gpr restore if we
19650 have saved some fprs; In those cases it is advantageous to use
19651 load multiple when available. */
19652 if ((strategy
& SAVRES_MULTIPLE
)
19654 || info
->first_fp_reg_save
!= 64))
19655 strategy
|= REST_INLINE_GPRS
;
19657 /* Saving CR interferes with the exit routines used on the SPE, so
19660 && info
->spe_64bit_regs_used
19661 && info
->cr_save_p
)
19662 strategy
|= REST_INLINE_GPRS
;
19664 /* We can only use load multiple or the out-of-line routines to
19665 restore if we've used store multiple or out-of-line routines
19666 in the prologue, i.e. if we've saved all the registers from
19667 first_gp_reg_save. Otherwise, we risk loading garbage. */
19668 if ((strategy
& (SAVE_INLINE_GPRS
| REST_INLINE_GPRS
| SAVRES_MULTIPLE
))
19669 == SAVE_INLINE_GPRS
)
19673 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
19674 if (!save_reg_p (i
))
19676 strategy
|= REST_INLINE_GPRS
;
19681 if (TARGET_ELF
&& TARGET_64BIT
)
19683 if (!(strategy
& SAVE_INLINE_FPRS
))
19684 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
19685 else if (!(strategy
& SAVE_INLINE_GPRS
)
19686 && info
->first_fp_reg_save
== 64)
19687 strategy
|= SAVE_NOINLINE_GPRS_SAVES_LR
;
19689 else if (TARGET_AIX
&& !(strategy
& REST_INLINE_FPRS
))
19690 strategy
|= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
;
19692 if (TARGET_MACHO
&& !(strategy
& SAVE_INLINE_FPRS
))
19693 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
19698 /* Calculate the stack information for the current function. This is
19699 complicated by having two separate calling sequences, the AIX calling
19700 sequence and the V.4 calling sequence.
19702 AIX (and Darwin/Mac OS X) stack frames look like:
19704 SP----> +---------------------------------------+
19705 | back chain to caller | 0 0
19706 +---------------------------------------+
19707 | saved CR | 4 8 (8-11)
19708 +---------------------------------------+
19710 +---------------------------------------+
19711 | reserved for compilers | 12 24
19712 +---------------------------------------+
19713 | reserved for binders | 16 32
19714 +---------------------------------------+
19715 | saved TOC pointer | 20 40
19716 +---------------------------------------+
19717 | Parameter save area (P) | 24 48
19718 +---------------------------------------+
19719 | Alloca space (A) | 24+P etc.
19720 +---------------------------------------+
19721 | Local variable space (L) | 24+P+A
19722 +---------------------------------------+
19723 | Float/int conversion temporary (X) | 24+P+A+L
19724 +---------------------------------------+
19725 | Save area for AltiVec registers (W) | 24+P+A+L+X
19726 +---------------------------------------+
19727 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
19728 +---------------------------------------+
19729 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
19730 +---------------------------------------+
19731 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
19732 +---------------------------------------+
19733 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
19734 +---------------------------------------+
19735 old SP->| back chain to caller's caller |
19736 +---------------------------------------+
19738 The required alignment for AIX configurations is two words (i.e., 8
19742 V.4 stack frames look like:
19744 SP----> +---------------------------------------+
19745 | back chain to caller | 0
19746 +---------------------------------------+
19747 | caller's saved LR | 4
19748 +---------------------------------------+
19749 | Parameter save area (P) | 8
19750 +---------------------------------------+
19751 | Alloca space (A) | 8+P
19752 +---------------------------------------+
19753 | Varargs save area (V) | 8+P+A
19754 +---------------------------------------+
19755 | Local variable space (L) | 8+P+A+V
19756 +---------------------------------------+
19757 | Float/int conversion temporary (X) | 8+P+A+V+L
19758 +---------------------------------------+
19759 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
19760 +---------------------------------------+
19761 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
19762 +---------------------------------------+
19763 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
19764 +---------------------------------------+
19765 | SPE: area for 64-bit GP registers |
19766 +---------------------------------------+
19767 | SPE alignment padding |
19768 +---------------------------------------+
19769 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
19770 +---------------------------------------+
19771 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
19772 +---------------------------------------+
19773 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
19774 +---------------------------------------+
19775 old SP->| back chain to caller's caller |
19776 +---------------------------------------+
19778 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
19779 given. (But note below and in sysv4.h that we require only 8 and
19780 may round up the size of our stack frame anyways. The historical
19781 reason is early versions of powerpc-linux which didn't properly
19782 align the stack at program startup. A happy side-effect is that
19783 -mno-eabi libraries can be used with -meabi programs.)
19785 The EABI configuration defaults to the V.4 layout. However,
19786 the stack alignment requirements may differ. If -mno-eabi is not
19787 given, the required stack alignment is 8 bytes; if -mno-eabi is
19788 given, the required alignment is 16 bytes. (But see V.4 comment
19791 #ifndef ABI_STACK_BOUNDARY
19792 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
19795 static rs6000_stack_t
*
19796 rs6000_stack_info (void)
19798 rs6000_stack_t
*info_ptr
= &stack_info
;
19799 int reg_size
= TARGET_32BIT
? 4 : 8;
19803 HOST_WIDE_INT non_fixed_size
;
19804 bool using_static_chain_p
;
19806 if (reload_completed
&& info_ptr
->reload_completed
)
19809 memset (info_ptr
, 0, sizeof (*info_ptr
));
19810 info_ptr
->reload_completed
= reload_completed
;
19814 /* Cache value so we don't rescan instruction chain over and over. */
19815 if (cfun
->machine
->insn_chain_scanned_p
== 0)
19816 cfun
->machine
->insn_chain_scanned_p
19817 = spe_func_has_64bit_regs_p () + 1;
19818 info_ptr
->spe_64bit_regs_used
= cfun
->machine
->insn_chain_scanned_p
- 1;
19821 /* Select which calling sequence. */
19822 info_ptr
->abi
= DEFAULT_ABI
;
19824 /* Calculate which registers need to be saved & save area size. */
19825 info_ptr
->first_gp_reg_save
= first_reg_to_save ();
19826 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
19827 even if it currently looks like we won't. Reload may need it to
19828 get at a constant; if so, it will have already created a constant
19829 pool entry for it. */
19830 if (((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
19831 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
19832 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
19833 && crtl
->uses_const_pool
19834 && info_ptr
->first_gp_reg_save
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
19835 first_gp
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
19837 first_gp
= info_ptr
->first_gp_reg_save
;
19839 info_ptr
->gp_size
= reg_size
* (32 - first_gp
);
19841 /* For the SPE, we have an additional upper 32-bits on each GPR.
19842 Ideally we should save the entire 64-bits only when the upper
19843 half is used in SIMD instructions. Since we only record
19844 registers live (not the size they are used in), this proves
19845 difficult because we'd have to traverse the instruction chain at
19846 the right time, taking reload into account. This is a real pain,
19847 so we opt to save the GPRs in 64-bits always if but one register
19848 gets used in 64-bits. Otherwise, all the registers in the frame
19849 get saved in 32-bits.
19851 So... since when we save all GPRs (except the SP) in 64-bits, the
19852 traditional GP save area will be empty. */
19853 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
19854 info_ptr
->gp_size
= 0;
19856 info_ptr
->first_fp_reg_save
= first_fp_reg_to_save ();
19857 info_ptr
->fp_size
= 8 * (64 - info_ptr
->first_fp_reg_save
);
19859 info_ptr
->first_altivec_reg_save
= first_altivec_reg_to_save ();
19860 info_ptr
->altivec_size
= 16 * (LAST_ALTIVEC_REGNO
+ 1
19861 - info_ptr
->first_altivec_reg_save
);
19863 /* Does this function call anything? */
19864 info_ptr
->calls_p
= (! crtl
->is_leaf
19865 || cfun
->machine
->ra_needs_full_frame
);
19867 /* Determine if we need to save the condition code registers. */
19868 if (df_regs_ever_live_p (CR2_REGNO
)
19869 || df_regs_ever_live_p (CR3_REGNO
)
19870 || df_regs_ever_live_p (CR4_REGNO
))
19872 info_ptr
->cr_save_p
= 1;
19873 if (DEFAULT_ABI
== ABI_V4
)
19874 info_ptr
->cr_size
= reg_size
;
19877 /* If the current function calls __builtin_eh_return, then we need
19878 to allocate stack space for registers that will hold data for
19879 the exception handler. */
19880 if (crtl
->calls_eh_return
)
19883 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
19886 /* SPE saves EH registers in 64-bits. */
19887 ehrd_size
= i
* (TARGET_SPE_ABI
19888 && info_ptr
->spe_64bit_regs_used
!= 0
19889 ? UNITS_PER_SPE_WORD
: UNITS_PER_WORD
);
19894 /* Determine various sizes. */
19895 info_ptr
->reg_size
= reg_size
;
19896 info_ptr
->fixed_size
= RS6000_SAVE_AREA
;
19897 info_ptr
->vars_size
= RS6000_ALIGN (get_frame_size (), 8);
19898 info_ptr
->parm_size
= RS6000_ALIGN (crtl
->outgoing_args_size
,
19899 TARGET_ALTIVEC
? 16 : 8);
19900 if (FRAME_GROWS_DOWNWARD
)
19901 info_ptr
->vars_size
19902 += RS6000_ALIGN (info_ptr
->fixed_size
+ info_ptr
->vars_size
19903 + info_ptr
->parm_size
,
19904 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
)
19905 - (info_ptr
->fixed_size
+ info_ptr
->vars_size
19906 + info_ptr
->parm_size
);
19908 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
19909 info_ptr
->spe_gp_size
= 8 * (32 - first_gp
);
19911 info_ptr
->spe_gp_size
= 0;
19913 if (TARGET_ALTIVEC_ABI
)
19914 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
19916 info_ptr
->vrsave_mask
= 0;
19918 if (TARGET_ALTIVEC_VRSAVE
&& info_ptr
->vrsave_mask
)
19919 info_ptr
->vrsave_size
= 4;
19921 info_ptr
->vrsave_size
= 0;
19923 compute_save_world_info (info_ptr
);
19925 /* Calculate the offsets. */
19926 switch (DEFAULT_ABI
)
19930 gcc_unreachable ();
19934 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
19935 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
19937 if (TARGET_ALTIVEC_ABI
)
19939 info_ptr
->vrsave_save_offset
19940 = info_ptr
->gp_save_offset
- info_ptr
->vrsave_size
;
19942 /* Align stack so vector save area is on a quadword boundary.
19943 The padding goes above the vectors. */
19944 if (info_ptr
->altivec_size
!= 0)
19945 info_ptr
->altivec_padding_size
19946 = info_ptr
->vrsave_save_offset
& 0xF;
19948 info_ptr
->altivec_padding_size
= 0;
19950 info_ptr
->altivec_save_offset
19951 = info_ptr
->vrsave_save_offset
19952 - info_ptr
->altivec_padding_size
19953 - info_ptr
->altivec_size
;
19954 gcc_assert (info_ptr
->altivec_size
== 0
19955 || info_ptr
->altivec_save_offset
% 16 == 0);
19957 /* Adjust for AltiVec case. */
19958 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
- ehrd_size
;
19961 info_ptr
->ehrd_offset
= info_ptr
->gp_save_offset
- ehrd_size
;
19962 info_ptr
->cr_save_offset
= reg_size
; /* first word when 64-bit. */
19963 info_ptr
->lr_save_offset
= 2*reg_size
;
19967 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
19968 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
19969 info_ptr
->cr_save_offset
= info_ptr
->gp_save_offset
- info_ptr
->cr_size
;
19971 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
19973 /* Align stack so SPE GPR save area is aligned on a
19974 double-word boundary. */
19975 if (info_ptr
->spe_gp_size
!= 0 && info_ptr
->cr_save_offset
!= 0)
19976 info_ptr
->spe_padding_size
19977 = 8 - (-info_ptr
->cr_save_offset
% 8);
19979 info_ptr
->spe_padding_size
= 0;
19981 info_ptr
->spe_gp_save_offset
19982 = info_ptr
->cr_save_offset
19983 - info_ptr
->spe_padding_size
19984 - info_ptr
->spe_gp_size
;
19986 /* Adjust for SPE case. */
19987 info_ptr
->ehrd_offset
= info_ptr
->spe_gp_save_offset
;
19989 else if (TARGET_ALTIVEC_ABI
)
19991 info_ptr
->vrsave_save_offset
19992 = info_ptr
->cr_save_offset
- info_ptr
->vrsave_size
;
19994 /* Align stack so vector save area is on a quadword boundary. */
19995 if (info_ptr
->altivec_size
!= 0)
19996 info_ptr
->altivec_padding_size
19997 = 16 - (-info_ptr
->vrsave_save_offset
% 16);
19999 info_ptr
->altivec_padding_size
= 0;
20001 info_ptr
->altivec_save_offset
20002 = info_ptr
->vrsave_save_offset
20003 - info_ptr
->altivec_padding_size
20004 - info_ptr
->altivec_size
;
20006 /* Adjust for AltiVec case. */
20007 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
;
20010 info_ptr
->ehrd_offset
= info_ptr
->cr_save_offset
;
20011 info_ptr
->ehrd_offset
-= ehrd_size
;
20012 info_ptr
->lr_save_offset
= reg_size
;
20016 save_align
= (TARGET_ALTIVEC_ABI
|| DEFAULT_ABI
== ABI_DARWIN
) ? 16 : 8;
20017 info_ptr
->save_size
= RS6000_ALIGN (info_ptr
->fp_size
20018 + info_ptr
->gp_size
20019 + info_ptr
->altivec_size
20020 + info_ptr
->altivec_padding_size
20021 + info_ptr
->spe_gp_size
20022 + info_ptr
->spe_padding_size
20024 + info_ptr
->cr_size
20025 + info_ptr
->vrsave_size
,
20028 non_fixed_size
= (info_ptr
->vars_size
20029 + info_ptr
->parm_size
20030 + info_ptr
->save_size
);
20032 info_ptr
->total_size
= RS6000_ALIGN (non_fixed_size
+ info_ptr
->fixed_size
,
20033 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
);
20035 /* Determine if we need to save the link register. */
20036 if (info_ptr
->calls_p
20037 || (DEFAULT_ABI
== ABI_AIX
20039 && !TARGET_PROFILE_KERNEL
)
20040 || (DEFAULT_ABI
== ABI_V4
&& cfun
->calls_alloca
)
20041 #ifdef TARGET_RELOCATABLE
20042 || (TARGET_RELOCATABLE
&& (get_pool_size () != 0))
20044 || rs6000_ra_ever_killed ())
20045 info_ptr
->lr_save_p
= 1;
20047 using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
20048 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
20049 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
20050 info_ptr
->savres_strategy
= rs6000_savres_strategy (info_ptr
,
20051 using_static_chain_p
);
20053 if (!(info_ptr
->savres_strategy
& SAVE_INLINE_GPRS
)
20054 || !(info_ptr
->savres_strategy
& SAVE_INLINE_FPRS
)
20055 || !(info_ptr
->savres_strategy
& SAVE_INLINE_VRS
)
20056 || !(info_ptr
->savres_strategy
& REST_INLINE_GPRS
)
20057 || !(info_ptr
->savres_strategy
& REST_INLINE_FPRS
)
20058 || !(info_ptr
->savres_strategy
& REST_INLINE_VRS
))
20059 info_ptr
->lr_save_p
= 1;
20061 if (info_ptr
->lr_save_p
)
20062 df_set_regs_ever_live (LR_REGNO
, true);
20064 /* Determine if we need to allocate any stack frame:
20066 For AIX we need to push the stack if a frame pointer is needed
20067 (because the stack might be dynamically adjusted), if we are
20068 debugging, if we make calls, or if the sum of fp_save, gp_save,
20069 and local variables are more than the space needed to save all
20070 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
20071 + 18*8 = 288 (GPR13 reserved).
20073 For V.4 we don't have the stack cushion that AIX uses, but assume
20074 that the debugger can handle stackless frames. */
20076 if (info_ptr
->calls_p
)
20077 info_ptr
->push_p
= 1;
20079 else if (DEFAULT_ABI
== ABI_V4
)
20080 info_ptr
->push_p
= non_fixed_size
!= 0;
20082 else if (frame_pointer_needed
)
20083 info_ptr
->push_p
= 1;
20085 else if (TARGET_XCOFF
&& write_symbols
!= NO_DEBUG
)
20086 info_ptr
->push_p
= 1;
20089 info_ptr
->push_p
= non_fixed_size
> (TARGET_32BIT
? 220 : 288);
20091 /* Zero offsets if we're not saving those registers. */
20092 if (info_ptr
->fp_size
== 0)
20093 info_ptr
->fp_save_offset
= 0;
20095 if (info_ptr
->gp_size
== 0)
20096 info_ptr
->gp_save_offset
= 0;
20098 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->altivec_size
== 0)
20099 info_ptr
->altivec_save_offset
= 0;
20101 /* Zero VRSAVE offset if not saved and restored. */
20102 if (! TARGET_ALTIVEC_VRSAVE
|| info_ptr
->vrsave_mask
== 0)
20103 info_ptr
->vrsave_save_offset
= 0;
20105 if (! TARGET_SPE_ABI
20106 || info_ptr
->spe_64bit_regs_used
== 0
20107 || info_ptr
->spe_gp_size
== 0)
20108 info_ptr
->spe_gp_save_offset
= 0;
20110 if (! info_ptr
->lr_save_p
)
20111 info_ptr
->lr_save_offset
= 0;
20113 if (! info_ptr
->cr_save_p
)
20114 info_ptr
->cr_save_offset
= 0;
20119 /* Return true if the current function uses any GPRs in 64-bit SIMD
20123 spe_func_has_64bit_regs_p (void)
20127 /* Functions that save and restore all the call-saved registers will
20128 need to save/restore the registers in 64-bits. */
20129 if (crtl
->calls_eh_return
20130 || cfun
->calls_setjmp
20131 || crtl
->has_nonlocal_goto
)
20134 insns
= get_insns ();
20136 for (insn
= NEXT_INSN (insns
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
20142 /* FIXME: This should be implemented with attributes...
20144 (set_attr "spe64" "true")....then,
20145 if (get_spe64(insn)) return true;
20147 It's the only reliable way to do the stuff below. */
20149 i
= PATTERN (insn
);
20150 if (GET_CODE (i
) == SET
)
20152 enum machine_mode mode
= GET_MODE (SET_SRC (i
));
20154 if (SPE_VECTOR_MODE (mode
))
20156 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
))
20166 debug_stack_info (rs6000_stack_t
*info
)
20168 const char *abi_string
;
20171 info
= rs6000_stack_info ();
20173 fprintf (stderr
, "\nStack information for function %s:\n",
20174 ((current_function_decl
&& DECL_NAME (current_function_decl
))
20175 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
20180 default: abi_string
= "Unknown"; break;
20181 case ABI_NONE
: abi_string
= "NONE"; break;
20182 case ABI_AIX
: abi_string
= "AIX"; break;
20183 case ABI_DARWIN
: abi_string
= "Darwin"; break;
20184 case ABI_V4
: abi_string
= "V.4"; break;
20187 fprintf (stderr
, "\tABI = %5s\n", abi_string
);
20189 if (TARGET_ALTIVEC_ABI
)
20190 fprintf (stderr
, "\tALTIVEC ABI extensions enabled.\n");
20192 if (TARGET_SPE_ABI
)
20193 fprintf (stderr
, "\tSPE ABI extensions enabled.\n");
20195 if (info
->first_gp_reg_save
!= 32)
20196 fprintf (stderr
, "\tfirst_gp_reg_save = %5d\n", info
->first_gp_reg_save
);
20198 if (info
->first_fp_reg_save
!= 64)
20199 fprintf (stderr
, "\tfirst_fp_reg_save = %5d\n", info
->first_fp_reg_save
);
20201 if (info
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
)
20202 fprintf (stderr
, "\tfirst_altivec_reg_save = %5d\n",
20203 info
->first_altivec_reg_save
);
20205 if (info
->lr_save_p
)
20206 fprintf (stderr
, "\tlr_save_p = %5d\n", info
->lr_save_p
);
20208 if (info
->cr_save_p
)
20209 fprintf (stderr
, "\tcr_save_p = %5d\n", info
->cr_save_p
);
20211 if (info
->vrsave_mask
)
20212 fprintf (stderr
, "\tvrsave_mask = 0x%x\n", info
->vrsave_mask
);
20215 fprintf (stderr
, "\tpush_p = %5d\n", info
->push_p
);
20218 fprintf (stderr
, "\tcalls_p = %5d\n", info
->calls_p
);
20220 if (info
->gp_save_offset
)
20221 fprintf (stderr
, "\tgp_save_offset = %5d\n", info
->gp_save_offset
);
20223 if (info
->fp_save_offset
)
20224 fprintf (stderr
, "\tfp_save_offset = %5d\n", info
->fp_save_offset
);
20226 if (info
->altivec_save_offset
)
20227 fprintf (stderr
, "\taltivec_save_offset = %5d\n",
20228 info
->altivec_save_offset
);
20230 if (info
->spe_gp_save_offset
)
20231 fprintf (stderr
, "\tspe_gp_save_offset = %5d\n",
20232 info
->spe_gp_save_offset
);
20234 if (info
->vrsave_save_offset
)
20235 fprintf (stderr
, "\tvrsave_save_offset = %5d\n",
20236 info
->vrsave_save_offset
);
20238 if (info
->lr_save_offset
)
20239 fprintf (stderr
, "\tlr_save_offset = %5d\n", info
->lr_save_offset
);
20241 if (info
->cr_save_offset
)
20242 fprintf (stderr
, "\tcr_save_offset = %5d\n", info
->cr_save_offset
);
20244 if (info
->varargs_save_offset
)
20245 fprintf (stderr
, "\tvarargs_save_offset = %5d\n", info
->varargs_save_offset
);
20247 if (info
->total_size
)
20248 fprintf (stderr
, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
20251 if (info
->vars_size
)
20252 fprintf (stderr
, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
20255 if (info
->parm_size
)
20256 fprintf (stderr
, "\tparm_size = %5d\n", info
->parm_size
);
20258 if (info
->fixed_size
)
20259 fprintf (stderr
, "\tfixed_size = %5d\n", info
->fixed_size
);
20262 fprintf (stderr
, "\tgp_size = %5d\n", info
->gp_size
);
20264 if (info
->spe_gp_size
)
20265 fprintf (stderr
, "\tspe_gp_size = %5d\n", info
->spe_gp_size
);
20268 fprintf (stderr
, "\tfp_size = %5d\n", info
->fp_size
);
20270 if (info
->altivec_size
)
20271 fprintf (stderr
, "\taltivec_size = %5d\n", info
->altivec_size
);
20273 if (info
->vrsave_size
)
20274 fprintf (stderr
, "\tvrsave_size = %5d\n", info
->vrsave_size
);
20276 if (info
->altivec_padding_size
)
20277 fprintf (stderr
, "\taltivec_padding_size= %5d\n",
20278 info
->altivec_padding_size
);
20280 if (info
->spe_padding_size
)
20281 fprintf (stderr
, "\tspe_padding_size = %5d\n",
20282 info
->spe_padding_size
);
20285 fprintf (stderr
, "\tcr_size = %5d\n", info
->cr_size
);
20287 if (info
->save_size
)
20288 fprintf (stderr
, "\tsave_size = %5d\n", info
->save_size
);
20290 if (info
->reg_size
!= 4)
20291 fprintf (stderr
, "\treg_size = %5d\n", info
->reg_size
);
20293 fprintf (stderr
, "\tsave-strategy = %04x\n", info
->savres_strategy
);
20295 fprintf (stderr
, "\n");
20299 rs6000_return_addr (int count
, rtx frame
)
20301 /* Currently we don't optimize very well between prolog and body
20302 code and for PIC code the code can be actually quite bad, so
20303 don't try to be too clever here. */
20304 if (count
!= 0 || (DEFAULT_ABI
!= ABI_AIX
&& flag_pic
))
20306 cfun
->machine
->ra_needs_full_frame
= 1;
20313 plus_constant (Pmode
,
20315 (gen_rtx_MEM (Pmode
,
20316 memory_address (Pmode
, frame
))),
20317 RETURN_ADDRESS_OFFSET
)));
20320 cfun
->machine
->ra_need_lr
= 1;
20321 return get_hard_reg_initial_val (Pmode
, LR_REGNO
);
20324 /* Say whether a function is a candidate for sibcall handling or not. */
20327 rs6000_function_ok_for_sibcall (tree decl
, tree exp
)
20332 fntype
= TREE_TYPE (decl
);
20334 fntype
= TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp
)));
20336 /* We can't do it if the called function has more vector parameters
20337 than the current function; there's nowhere to put the VRsave code. */
20338 if (TARGET_ALTIVEC_ABI
20339 && TARGET_ALTIVEC_VRSAVE
20340 && !(decl
&& decl
== current_function_decl
))
20342 function_args_iterator args_iter
;
20346 /* Functions with vector parameters are required to have a
20347 prototype, so the argument type info must be available
20349 FOREACH_FUNCTION_ARGS(fntype
, type
, args_iter
)
20350 if (TREE_CODE (type
) == VECTOR_TYPE
20351 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
20354 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl
), type
, args_iter
)
20355 if (TREE_CODE (type
) == VECTOR_TYPE
20356 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
20363 /* Under the AIX ABI we can't allow calls to non-local functions,
20364 because the callee may have a different TOC pointer to the
20365 caller and there's no way to ensure we restore the TOC when we
20366 return. With the secure-plt SYSV ABI we can't make non-local
20367 calls when -fpic/PIC because the plt call stubs use r30. */
20368 if (DEFAULT_ABI
== ABI_DARWIN
20369 || (DEFAULT_ABI
== ABI_AIX
20371 && !DECL_EXTERNAL (decl
)
20372 && (*targetm
.binds_local_p
) (decl
))
20373 || (DEFAULT_ABI
== ABI_V4
20374 && (!TARGET_SECURE_PLT
20377 && (*targetm
.binds_local_p
) (decl
)))))
20379 tree attr_list
= TYPE_ATTRIBUTES (fntype
);
20381 if (!lookup_attribute ("longcall", attr_list
)
20382 || lookup_attribute ("shortcall", attr_list
))
20390 rs6000_ra_ever_killed (void)
20396 if (cfun
->is_thunk
)
20399 if (cfun
->machine
->lr_save_state
)
20400 return cfun
->machine
->lr_save_state
- 1;
20402 /* regs_ever_live has LR marked as used if any sibcalls are present,
20403 but this should not force saving and restoring in the
20404 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
20405 clobbers LR, so that is inappropriate. */
20407 /* Also, the prologue can generate a store into LR that
20408 doesn't really count, like this:
20411 bcl to set PIC register
20415 When we're called from the epilogue, we need to avoid counting
20416 this as a store. */
20418 push_topmost_sequence ();
20419 top
= get_insns ();
20420 pop_topmost_sequence ();
20421 reg
= gen_rtx_REG (Pmode
, LR_REGNO
);
20423 for (insn
= NEXT_INSN (top
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
20429 if (!SIBLING_CALL_P (insn
))
20432 else if (find_regno_note (insn
, REG_INC
, LR_REGNO
))
20434 else if (set_of (reg
, insn
) != NULL_RTX
20435 && !prologue_epilogue_contains (insn
))
20442 /* Emit instructions needed to load the TOC register.
20443 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
20444 a constant pool; or for SVR4 -fpic. */
20447 rs6000_emit_load_toc_table (int fromprolog
)
20450 dest
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
20452 if (TARGET_ELF
&& TARGET_SECURE_PLT
&& DEFAULT_ABI
!= ABI_AIX
&& flag_pic
)
20455 rtx lab
, tmp1
, tmp2
, got
;
20457 lab
= gen_label_rtx ();
20458 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (lab
));
20459 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
20461 got
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
20463 got
= rs6000_got_sym ();
20464 tmp1
= tmp2
= dest
;
20467 tmp1
= gen_reg_rtx (Pmode
);
20468 tmp2
= gen_reg_rtx (Pmode
);
20470 emit_insn (gen_load_toc_v4_PIC_1 (lab
));
20471 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
20472 emit_insn (gen_load_toc_v4_PIC_3b (tmp2
, tmp1
, got
, lab
));
20473 emit_insn (gen_load_toc_v4_PIC_3c (dest
, tmp2
, got
, lab
));
20475 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
20477 emit_insn (gen_load_toc_v4_pic_si ());
20478 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
20480 else if (TARGET_ELF
&& DEFAULT_ABI
!= ABI_AIX
&& flag_pic
== 2)
20483 rtx temp0
= (fromprolog
20484 ? gen_rtx_REG (Pmode
, 0)
20485 : gen_reg_rtx (Pmode
));
20491 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
20492 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
20494 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
20495 symL
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
20497 emit_insn (gen_load_toc_v4_PIC_1 (symF
));
20498 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
20499 emit_insn (gen_load_toc_v4_PIC_2 (temp0
, dest
, symL
, symF
));
20505 tocsym
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
20506 lab
= gen_label_rtx ();
20507 emit_insn (gen_load_toc_v4_PIC_1b (tocsym
, lab
));
20508 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
20509 if (TARGET_LINK_STACK
)
20510 emit_insn (gen_addsi3 (dest
, dest
, GEN_INT (4)));
20511 emit_move_insn (temp0
, gen_rtx_MEM (Pmode
, dest
));
20513 emit_insn (gen_addsi3 (dest
, temp0
, dest
));
20515 else if (TARGET_ELF
&& !TARGET_AIX
&& flag_pic
== 0 && TARGET_MINIMAL_TOC
)
20517 /* This is for AIX code running in non-PIC ELF32. */
20520 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
20521 realsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
20523 emit_insn (gen_elf_high (dest
, realsym
));
20524 emit_insn (gen_elf_low (dest
, dest
, realsym
));
20528 gcc_assert (DEFAULT_ABI
== ABI_AIX
);
20531 emit_insn (gen_load_toc_aix_si (dest
));
20533 emit_insn (gen_load_toc_aix_di (dest
));
20537 /* Emit instructions to restore the link register after determining where
20538 its value has been stored. */
20541 rs6000_emit_eh_reg_restore (rtx source
, rtx scratch
)
20543 rs6000_stack_t
*info
= rs6000_stack_info ();
20546 operands
[0] = source
;
20547 operands
[1] = scratch
;
20549 if (info
->lr_save_p
)
20551 rtx frame_rtx
= stack_pointer_rtx
;
20552 HOST_WIDE_INT sp_offset
= 0;
20555 if (frame_pointer_needed
20556 || cfun
->calls_alloca
20557 || info
->total_size
> 32767)
20559 tmp
= gen_frame_mem (Pmode
, frame_rtx
);
20560 emit_move_insn (operands
[1], tmp
);
20561 frame_rtx
= operands
[1];
20563 else if (info
->push_p
)
20564 sp_offset
= info
->total_size
;
20566 tmp
= plus_constant (Pmode
, frame_rtx
,
20567 info
->lr_save_offset
+ sp_offset
);
20568 tmp
= gen_frame_mem (Pmode
, tmp
);
20569 emit_move_insn (tmp
, operands
[0]);
20572 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
), operands
[0]);
20574 /* Freeze lr_save_p. We've just emitted rtl that depends on the
20575 state of lr_save_p so any change from here on would be a bug. In
20576 particular, stop rs6000_ra_ever_killed from considering the SET
20577 of lr we may have added just above. */
20578 cfun
->machine
->lr_save_state
= info
->lr_save_p
+ 1;
20581 static GTY(()) alias_set_type set
= -1;
20584 get_TOC_alias_set (void)
20587 set
= new_alias_set ();
20591 /* This returns nonzero if the current function uses the TOC. This is
20592 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
20593 is generated by the ABI_V4 load_toc_* patterns. */
20600 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
20603 rtx pat
= PATTERN (insn
);
20606 if (GET_CODE (pat
) == PARALLEL
)
20607 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
20609 rtx sub
= XVECEXP (pat
, 0, i
);
20610 if (GET_CODE (sub
) == USE
)
20612 sub
= XEXP (sub
, 0);
20613 if (GET_CODE (sub
) == UNSPEC
20614 && XINT (sub
, 1) == UNSPEC_TOC
)
20624 create_TOC_reference (rtx symbol
, rtx largetoc_reg
)
20626 rtx tocrel
, tocreg
, hi
;
20628 if (TARGET_DEBUG_ADDR
)
20630 if (GET_CODE (symbol
) == SYMBOL_REF
)
20631 fprintf (stderr
, "\ncreate_TOC_reference, (symbol_ref %s)\n",
20635 fprintf (stderr
, "\ncreate_TOC_reference, code %s:\n",
20636 GET_RTX_NAME (GET_CODE (symbol
)));
20637 debug_rtx (symbol
);
20641 if (!can_create_pseudo_p ())
20642 df_set_regs_ever_live (TOC_REGISTER
, true);
20644 tocreg
= gen_rtx_REG (Pmode
, TOC_REGISTER
);
20645 tocrel
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, symbol
, tocreg
), UNSPEC_TOCREL
);
20646 if (TARGET_CMODEL
== CMODEL_SMALL
|| can_create_pseudo_p ())
20649 hi
= gen_rtx_HIGH (Pmode
, copy_rtx (tocrel
));
20650 if (largetoc_reg
!= NULL
)
20652 emit_move_insn (largetoc_reg
, hi
);
20655 return gen_rtx_LO_SUM (Pmode
, hi
, tocrel
);
20658 /* Issue assembly directives that create a reference to the given DWARF
20659 FRAME_TABLE_LABEL from the current function section. */
20661 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label
)
20663 fprintf (asm_out_file
, "\t.ref %s\n",
20664 (* targetm
.strip_name_encoding
) (frame_table_label
));
20667 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
20668 and the change to the stack pointer. */
20671 rs6000_emit_stack_tie (rtx fp
, bool hard_frame_needed
)
20678 regs
[i
++] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
20679 if (hard_frame_needed
)
20680 regs
[i
++] = gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
);
20681 if (!(REGNO (fp
) == STACK_POINTER_REGNUM
20682 || (hard_frame_needed
20683 && REGNO (fp
) == HARD_FRAME_POINTER_REGNUM
)))
20686 p
= rtvec_alloc (i
);
20689 rtx mem
= gen_frame_mem (BLKmode
, regs
[i
]);
20690 RTVEC_ELT (p
, i
) = gen_rtx_SET (VOIDmode
, mem
, const0_rtx
);
20693 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode
, p
)));
20696 /* Emit the correct code for allocating stack space, as insns.
20697 If COPY_REG, make sure a copy of the old frame is left there.
20698 The generated code may use hard register 0 as a temporary. */
20701 rs6000_emit_allocate_stack (HOST_WIDE_INT size
, rtx copy_reg
, int copy_off
)
20704 rtx stack_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
20705 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
20706 rtx todec
= gen_int_mode (-size
, Pmode
);
20709 if (INTVAL (todec
) != -size
)
20711 warning (0, "stack frame too large");
20712 emit_insn (gen_trap ());
20716 if (crtl
->limit_stack
)
20718 if (REG_P (stack_limit_rtx
)
20719 && REGNO (stack_limit_rtx
) > 1
20720 && REGNO (stack_limit_rtx
) <= 31)
20722 emit_insn (gen_add3_insn (tmp_reg
, stack_limit_rtx
, GEN_INT (size
)));
20723 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
20726 else if (GET_CODE (stack_limit_rtx
) == SYMBOL_REF
20728 && DEFAULT_ABI
== ABI_V4
)
20730 rtx toload
= gen_rtx_CONST (VOIDmode
,
20731 gen_rtx_PLUS (Pmode
,
20735 emit_insn (gen_elf_high (tmp_reg
, toload
));
20736 emit_insn (gen_elf_low (tmp_reg
, tmp_reg
, toload
));
20737 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
20741 warning (0, "stack limit expression is not supported");
20747 emit_insn (gen_add3_insn (copy_reg
, stack_reg
, GEN_INT (copy_off
)));
20749 emit_move_insn (copy_reg
, stack_reg
);
20754 /* Need a note here so that try_split doesn't get confused. */
20755 if (get_last_insn () == NULL_RTX
)
20756 emit_note (NOTE_INSN_DELETED
);
20757 insn
= emit_move_insn (tmp_reg
, todec
);
20758 try_split (PATTERN (insn
), insn
, 0);
20762 insn
= emit_insn (TARGET_32BIT
20763 ? gen_movsi_update_stack (stack_reg
, stack_reg
,
20765 : gen_movdi_di_update_stack (stack_reg
, stack_reg
,
20766 todec
, stack_reg
));
20767 /* Since we didn't use gen_frame_mem to generate the MEM, grab
20768 it now and set the alias set/attributes. The above gen_*_update
20769 calls will generate a PARALLEL with the MEM set being the first
20771 par
= PATTERN (insn
);
20772 gcc_assert (GET_CODE (par
) == PARALLEL
);
20773 set
= XVECEXP (par
, 0, 0);
20774 gcc_assert (GET_CODE (set
) == SET
);
20775 mem
= SET_DEST (set
);
20776 gcc_assert (MEM_P (mem
));
20777 MEM_NOTRAP_P (mem
) = 1;
20778 set_mem_alias_set (mem
, get_frame_alias_set ());
20780 RTX_FRAME_RELATED_P (insn
) = 1;
20781 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
20782 gen_rtx_SET (VOIDmode
, stack_reg
,
20783 gen_rtx_PLUS (Pmode
, stack_reg
,
20784 GEN_INT (-size
))));
20787 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
20789 #if PROBE_INTERVAL > 32768
20790 #error Cannot use indexed addressing mode for stack probing
20793 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
20794 inclusive. These are offsets from the current stack pointer. */
20797 rs6000_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
20799 /* See if we have a constant small number of probes to generate. If so,
20800 that's the easy case. */
20801 if (first
+ size
<= 32768)
20805 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
20806 it exceeds SIZE. If only one probe is needed, this will not
20807 generate any code. Then probe at FIRST + SIZE. */
20808 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
20809 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
20812 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
20816 /* Otherwise, do the same as above, but in a loop. Note that we must be
20817 extra careful with variables wrapping around because we might be at
20818 the very top (or the very bottom) of the address space and we have
20819 to be able to handle this case properly; in particular, we use an
20820 equality test for the loop condition. */
20823 HOST_WIDE_INT rounded_size
;
20824 rtx r12
= gen_rtx_REG (Pmode
, 12);
20825 rtx r0
= gen_rtx_REG (Pmode
, 0);
20827 /* Sanity check for the addressing mode we're going to use. */
20828 gcc_assert (first
<= 32768);
20830 /* Step 1: round SIZE to the previous multiple of the interval. */
20832 rounded_size
= size
& -PROBE_INTERVAL
;
20835 /* Step 2: compute initial and final value of the loop counter. */
20837 /* TEST_ADDR = SP + FIRST. */
20838 emit_insn (gen_rtx_SET (VOIDmode
, r12
,
20839 plus_constant (Pmode
, stack_pointer_rtx
,
20842 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
20843 if (rounded_size
> 32768)
20845 emit_move_insn (r0
, GEN_INT (-rounded_size
));
20846 emit_insn (gen_rtx_SET (VOIDmode
, r0
,
20847 gen_rtx_PLUS (Pmode
, r12
, r0
)));
20850 emit_insn (gen_rtx_SET (VOIDmode
, r0
,
20851 plus_constant (Pmode
, r12
, -rounded_size
)));
20854 /* Step 3: the loop
20856 while (TEST_ADDR != LAST_ADDR)
20858 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
20862 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
20863 until it is equal to ROUNDED_SIZE. */
20866 emit_insn (gen_probe_stack_rangedi (r12
, r12
, r0
));
20868 emit_insn (gen_probe_stack_rangesi (r12
, r12
, r0
));
20871 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
20872 that SIZE is equal to ROUNDED_SIZE. */
20874 if (size
!= rounded_size
)
20875 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
20879 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
20880 absolute addresses. */
20883 output_probe_stack_range (rtx reg1
, rtx reg2
)
20885 static int labelno
= 0;
20886 char loop_lab
[32], end_lab
[32];
20889 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
20890 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
20892 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
20894 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
20898 output_asm_insn ("cmpd 0,%0,%1", xops
);
20900 output_asm_insn ("cmpw 0,%0,%1", xops
);
20902 fputs ("\tbeq 0,", asm_out_file
);
20903 assemble_name_raw (asm_out_file
, end_lab
);
20904 fputc ('\n', asm_out_file
);
20906 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
20907 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
20908 output_asm_insn ("addi %0,%0,%1", xops
);
20910 /* Probe at TEST_ADDR and branch. */
20911 xops
[1] = gen_rtx_REG (Pmode
, 0);
20912 output_asm_insn ("stw %1,0(%0)", xops
);
20913 fprintf (asm_out_file
, "\tb ");
20914 assemble_name_raw (asm_out_file
, loop_lab
);
20915 fputc ('\n', asm_out_file
);
20917 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
20922 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
20923 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
20924 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
20925 deduce these equivalences by itself so it wasn't necessary to hold
20926 its hand so much. Don't be tempted to always supply d2_f_d_e with
20927 the actual cfa register, ie. r31 when we are using a hard frame
20928 pointer. That fails when saving regs off r1, and sched moves the
20929 r31 setup past the reg saves. */
20932 rs6000_frame_related (rtx insn
, rtx reg
, HOST_WIDE_INT val
,
20933 rtx reg2
, rtx rreg
)
20937 if (REGNO (reg
) == STACK_POINTER_REGNUM
&& reg2
== NULL_RTX
)
20939 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
20942 gcc_checking_assert (val
== 0);
20943 real
= PATTERN (insn
);
20944 if (GET_CODE (real
) == PARALLEL
)
20945 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
20946 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
20948 rtx set
= XVECEXP (real
, 0, i
);
20950 RTX_FRAME_RELATED_P (set
) = 1;
20952 RTX_FRAME_RELATED_P (insn
) = 1;
20956 /* copy_rtx will not make unique copies of registers, so we need to
20957 ensure we don't have unwanted sharing here. */
20959 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
20962 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
20964 real
= copy_rtx (PATTERN (insn
));
20966 if (reg2
!= NULL_RTX
)
20967 real
= replace_rtx (real
, reg2
, rreg
);
20969 if (REGNO (reg
) == STACK_POINTER_REGNUM
)
20970 gcc_checking_assert (val
== 0);
20972 real
= replace_rtx (real
, reg
,
20973 gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
,
20974 STACK_POINTER_REGNUM
),
20977 /* We expect that 'real' is either a SET or a PARALLEL containing
20978 SETs (and possibly other stuff). In a PARALLEL, all the SETs
20979 are important so they all have to be marked RTX_FRAME_RELATED_P. */
20981 if (GET_CODE (real
) == SET
)
20985 temp
= simplify_rtx (SET_SRC (set
));
20987 SET_SRC (set
) = temp
;
20988 temp
= simplify_rtx (SET_DEST (set
));
20990 SET_DEST (set
) = temp
;
20991 if (GET_CODE (SET_DEST (set
)) == MEM
)
20993 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
20995 XEXP (SET_DEST (set
), 0) = temp
;
21002 gcc_assert (GET_CODE (real
) == PARALLEL
);
21003 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
21004 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
21006 rtx set
= XVECEXP (real
, 0, i
);
21008 temp
= simplify_rtx (SET_SRC (set
));
21010 SET_SRC (set
) = temp
;
21011 temp
= simplify_rtx (SET_DEST (set
));
21013 SET_DEST (set
) = temp
;
21014 if (GET_CODE (SET_DEST (set
)) == MEM
)
21016 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
21018 XEXP (SET_DEST (set
), 0) = temp
;
21020 RTX_FRAME_RELATED_P (set
) = 1;
21024 RTX_FRAME_RELATED_P (insn
) = 1;
21025 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, real
);
21030 /* Returns an insn that has a vrsave set operation with the
21031 appropriate CLOBBERs. */
21034 generate_set_vrsave (rtx reg
, rs6000_stack_t
*info
, int epiloguep
)
21037 rtx insn
, clobs
[TOTAL_ALTIVEC_REGS
+ 1];
21038 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
21041 = gen_rtx_SET (VOIDmode
,
21043 gen_rtx_UNSPEC_VOLATILE (SImode
,
21044 gen_rtvec (2, reg
, vrsave
),
21045 UNSPECV_SET_VRSAVE
));
21049 /* We need to clobber the registers in the mask so the scheduler
21050 does not move sets to VRSAVE before sets of AltiVec registers.
21052 However, if the function receives nonlocal gotos, reload will set
21053 all call saved registers live. We will end up with:
21055 (set (reg 999) (mem))
21056 (parallel [ (set (reg vrsave) (unspec blah))
21057 (clobber (reg 999))])
21059 The clobber will cause the store into reg 999 to be dead, and
21060 flow will attempt to delete an epilogue insn. In this case, we
21061 need an unspec use/set of the register. */
21063 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
21064 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
21066 if (!epiloguep
|| call_used_regs
[i
])
21067 clobs
[nclobs
++] = gen_rtx_CLOBBER (VOIDmode
,
21068 gen_rtx_REG (V4SImode
, i
));
21071 rtx reg
= gen_rtx_REG (V4SImode
, i
);
21074 = gen_rtx_SET (VOIDmode
,
21076 gen_rtx_UNSPEC (V4SImode
,
21077 gen_rtvec (1, reg
), 27));
21081 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nclobs
));
21083 for (i
= 0; i
< nclobs
; ++i
)
21084 XVECEXP (insn
, 0, i
) = clobs
[i
];
21090 gen_frame_set (rtx reg
, rtx frame_reg
, int offset
, bool store
)
21094 addr
= gen_rtx_PLUS (Pmode
, frame_reg
, GEN_INT (offset
));
21095 mem
= gen_frame_mem (GET_MODE (reg
), addr
);
21096 return gen_rtx_SET (VOIDmode
, store
? mem
: reg
, store
? reg
: mem
);
21100 gen_frame_load (rtx reg
, rtx frame_reg
, int offset
)
21102 return gen_frame_set (reg
, frame_reg
, offset
, false);
21106 gen_frame_store (rtx reg
, rtx frame_reg
, int offset
)
21108 return gen_frame_set (reg
, frame_reg
, offset
, true);
21111 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
21112 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
21115 emit_frame_save (rtx frame_reg
, enum machine_mode mode
,
21116 unsigned int regno
, int offset
, HOST_WIDE_INT frame_reg_to_sp
)
21120 /* Some cases that need register indexed addressing. */
21121 gcc_checking_assert (!((TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
21122 || (TARGET_VSX
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
21123 || (TARGET_E500_DOUBLE
&& mode
== DFmode
)
21125 && SPE_VECTOR_MODE (mode
)
21126 && !SPE_CONST_OFFSET_OK (offset
))));
21128 reg
= gen_rtx_REG (mode
, regno
);
21129 insn
= emit_insn (gen_frame_store (reg
, frame_reg
, offset
));
21130 return rs6000_frame_related (insn
, frame_reg
, frame_reg_to_sp
,
21131 NULL_RTX
, NULL_RTX
);
21134 /* Emit an offset memory reference suitable for a frame store, while
21135 converting to a valid addressing mode. */
21138 gen_frame_mem_offset (enum machine_mode mode
, rtx reg
, int offset
)
21140 rtx int_rtx
, offset_rtx
;
21142 int_rtx
= GEN_INT (offset
);
21144 if ((TARGET_SPE_ABI
&& SPE_VECTOR_MODE (mode
) && !SPE_CONST_OFFSET_OK (offset
))
21145 || (TARGET_E500_DOUBLE
&& mode
== DFmode
))
21147 offset_rtx
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
21148 emit_move_insn (offset_rtx
, int_rtx
);
21151 offset_rtx
= int_rtx
;
21153 return gen_frame_mem (mode
, gen_rtx_PLUS (Pmode
, reg
, offset_rtx
));
21156 #ifndef TARGET_FIX_AND_CONTINUE
21157 #define TARGET_FIX_AND_CONTINUE 0
21160 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
21161 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
21162 #define LAST_SAVRES_REGISTER 31
21163 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
21174 static GTY(()) rtx savres_routine_syms
[N_SAVRES_REGISTERS
][12];
21176 /* Temporary holding space for an out-of-line register save/restore
21178 static char savres_routine_name
[30];
21180 /* Return the name for an out-of-line register save/restore routine.
21181 We are saving/restoring GPRs if GPR is true. */
21184 rs6000_savres_routine_name (rs6000_stack_t
*info
, int regno
, int sel
)
21186 const char *prefix
= "";
21187 const char *suffix
= "";
21189 /* Different targets are supposed to define
21190 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
21191 routine name could be defined with:
21193 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
21195 This is a nice idea in practice, but in reality, things are
21196 complicated in several ways:
21198 - ELF targets have save/restore routines for GPRs.
21200 - SPE targets use different prefixes for 32/64-bit registers, and
21201 neither of them fit neatly in the FOO_{PREFIX,SUFFIX} regimen.
21203 - PPC64 ELF targets have routines for save/restore of GPRs that
21204 differ in what they do with the link register, so having a set
21205 prefix doesn't work. (We only use one of the save routines at
21206 the moment, though.)
21208 - PPC32 elf targets have "exit" versions of the restore routines
21209 that restore the link register and can save some extra space.
21210 These require an extra suffix. (There are also "tail" versions
21211 of the restore routines and "GOT" versions of the save routines,
21212 but we don't generate those at present. Same problems apply,
21215 We deal with all this by synthesizing our own prefix/suffix and
21216 using that for the simple sprintf call shown above. */
21219 /* No floating point saves on the SPE. */
21220 gcc_assert ((sel
& SAVRES_REG
) == SAVRES_GPR
);
21222 if ((sel
& SAVRES_SAVE
))
21223 prefix
= info
->spe_64bit_regs_used
? "_save64gpr_" : "_save32gpr_";
21225 prefix
= info
->spe_64bit_regs_used
? "_rest64gpr_" : "_rest32gpr_";
21227 if ((sel
& SAVRES_LR
))
21230 else if (DEFAULT_ABI
== ABI_V4
)
21235 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
21236 prefix
= (sel
& SAVRES_SAVE
) ? "_savegpr_" : "_restgpr_";
21237 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
21238 prefix
= (sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_";
21239 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
21240 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
21244 if ((sel
& SAVRES_LR
))
21247 else if (DEFAULT_ABI
== ABI_AIX
)
21249 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
21250 /* No out-of-line save/restore routines for GPRs on AIX. */
21251 gcc_assert (!TARGET_AIX
|| (sel
& SAVRES_REG
) != SAVRES_GPR
);
21255 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
21256 prefix
= ((sel
& SAVRES_SAVE
)
21257 ? ((sel
& SAVRES_LR
) ? "_savegpr0_" : "_savegpr1_")
21258 : ((sel
& SAVRES_LR
) ? "_restgpr0_" : "_restgpr1_"));
21259 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
21261 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
21262 if ((sel
& SAVRES_LR
))
21263 prefix
= ((sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_");
21267 prefix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_PREFIX
: RESTORE_FP_PREFIX
;
21268 suffix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_SUFFIX
: RESTORE_FP_SUFFIX
;
21271 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
21272 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
21277 if (DEFAULT_ABI
== ABI_DARWIN
)
21279 /* The Darwin approach is (slightly) different, in order to be
21280 compatible with code generated by the system toolchain. There is a
21281 single symbol for the start of save sequence, and the code here
21282 embeds an offset into that code on the basis of the first register
21284 prefix
= (sel
& SAVRES_SAVE
) ? "save" : "rest" ;
21285 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
21286 sprintf (savres_routine_name
, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix
,
21287 ((sel
& SAVRES_LR
) ? "x" : ""), (regno
== 13 ? "" : "+"),
21288 (regno
- 13) * 4, prefix
, regno
);
21289 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
21290 sprintf (savres_routine_name
, "*%sFP%s%.0d ; %s f%d-f31", prefix
,
21291 (regno
== 14 ? "" : "+"), (regno
- 14) * 4, prefix
, regno
);
21292 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
21293 sprintf (savres_routine_name
, "*%sVEC%s%.0d ; %s v%d-v31", prefix
,
21294 (regno
== 20 ? "" : "+"), (regno
- 20) * 8, prefix
, regno
);
21299 sprintf (savres_routine_name
, "%s%d%s", prefix
, regno
, suffix
);
21301 return savres_routine_name
;
21304 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
21305 We are saving/restoring GPRs if GPR is true. */
21308 rs6000_savres_routine_sym (rs6000_stack_t
*info
, int sel
)
21310 int regno
= ((sel
& SAVRES_REG
) == SAVRES_GPR
21311 ? info
->first_gp_reg_save
21312 : (sel
& SAVRES_REG
) == SAVRES_FPR
21313 ? info
->first_fp_reg_save
- 32
21314 : (sel
& SAVRES_REG
) == SAVRES_VR
21315 ? info
->first_altivec_reg_save
- FIRST_ALTIVEC_REGNO
21320 /* On the SPE, we never have any FPRs, but we do have 32/64-bit
21321 versions of the gpr routines. */
21322 if (TARGET_SPE_ABI
&& (sel
& SAVRES_REG
) == SAVRES_GPR
21323 && info
->spe_64bit_regs_used
)
21324 select
^= SAVRES_FPR
^ SAVRES_GPR
;
21326 /* Don't generate bogus routine names. */
21327 gcc_assert (FIRST_SAVRES_REGISTER
<= regno
21328 && regno
<= LAST_SAVRES_REGISTER
21329 && select
>= 0 && select
<= 12);
21331 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
];
21337 name
= rs6000_savres_routine_name (info
, regno
, sel
);
21339 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
]
21340 = gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
21341 SYMBOL_REF_FLAGS (sym
) |= SYMBOL_FLAG_FUNCTION
;
21347 /* Emit a sequence of insns, including a stack tie if needed, for
21348 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
21349 reset the stack pointer, but move the base of the frame into
21350 reg UPDT_REGNO for use by out-of-line register restore routines. */
21353 rs6000_emit_stack_reset (rs6000_stack_t
*info
,
21354 rtx frame_reg_rtx
, HOST_WIDE_INT frame_off
,
21355 unsigned updt_regno
)
21359 /* This blockage is needed so that sched doesn't decide to move
21360 the sp change before the register restores. */
21361 if (DEFAULT_ABI
== ABI_V4
21363 && info
->spe_64bit_regs_used
!= 0
21364 && info
->first_gp_reg_save
!= 32))
21365 rs6000_emit_stack_tie (frame_reg_rtx
, frame_pointer_needed
);
21367 /* If we are restoring registers out-of-line, we will be using the
21368 "exit" variants of the restore routines, which will reset the
21369 stack for us. But we do need to point updt_reg into the
21370 right place for those routines. */
21371 updt_reg_rtx
= gen_rtx_REG (Pmode
, updt_regno
);
21373 if (frame_off
!= 0)
21374 return emit_insn (gen_add3_insn (updt_reg_rtx
,
21375 frame_reg_rtx
, GEN_INT (frame_off
)));
21376 else if (REGNO (frame_reg_rtx
) != updt_regno
)
21377 return emit_move_insn (updt_reg_rtx
, frame_reg_rtx
);
21382 /* Return the register number used as a pointer by out-of-line
21383 save/restore functions. */
21385 static inline unsigned
21386 ptr_regno_for_savres (int sel
)
21388 if (DEFAULT_ABI
== ABI_AIX
)
21389 return (sel
& SAVRES_REG
) == SAVRES_FPR
|| (sel
& SAVRES_LR
) ? 1 : 12;
21390 return DEFAULT_ABI
== ABI_DARWIN
&& (sel
& SAVRES_REG
) == SAVRES_FPR
? 1 : 11;
21393 /* Construct a parallel rtx describing the effect of a call to an
21394 out-of-line register save/restore routine, and emit the insn
21395 or jump_insn as appropriate. */
21398 rs6000_emit_savres_rtx (rs6000_stack_t
*info
,
21399 rtx frame_reg_rtx
, int save_area_offset
, int lr_offset
,
21400 enum machine_mode reg_mode
, int sel
)
21403 int offset
, start_reg
, end_reg
, n_regs
, use_reg
;
21404 int reg_size
= GET_MODE_SIZE (reg_mode
);
21410 start_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
21411 ? info
->first_gp_reg_save
21412 : (sel
& SAVRES_REG
) == SAVRES_FPR
21413 ? info
->first_fp_reg_save
21414 : (sel
& SAVRES_REG
) == SAVRES_VR
21415 ? info
->first_altivec_reg_save
21417 end_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
21419 : (sel
& SAVRES_REG
) == SAVRES_FPR
21421 : (sel
& SAVRES_REG
) == SAVRES_VR
21422 ? LAST_ALTIVEC_REGNO
+ 1
21424 n_regs
= end_reg
- start_reg
;
21425 p
= rtvec_alloc (3 + ((sel
& SAVRES_LR
) ? 1 : 0)
21426 + ((sel
& SAVRES_REG
) == SAVRES_VR
? 1 : 0)
21429 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
21430 RTVEC_ELT (p
, offset
++) = ret_rtx
;
21432 RTVEC_ELT (p
, offset
++)
21433 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
21435 sym
= rs6000_savres_routine_sym (info
, sel
);
21436 RTVEC_ELT (p
, offset
++) = gen_rtx_USE (VOIDmode
, sym
);
21438 use_reg
= ptr_regno_for_savres (sel
);
21439 if ((sel
& SAVRES_REG
) == SAVRES_VR
)
21441 /* Vector regs are saved/restored using [reg+reg] addressing. */
21442 RTVEC_ELT (p
, offset
++)
21443 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
21444 RTVEC_ELT (p
, offset
++)
21445 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 0));
21448 RTVEC_ELT (p
, offset
++)
21449 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
21451 for (i
= 0; i
< end_reg
- start_reg
; i
++)
21452 RTVEC_ELT (p
, i
+ offset
)
21453 = gen_frame_set (gen_rtx_REG (reg_mode
, start_reg
+ i
),
21454 frame_reg_rtx
, save_area_offset
+ reg_size
* i
,
21455 (sel
& SAVRES_SAVE
) != 0);
21457 if ((sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
21458 RTVEC_ELT (p
, i
+ offset
)
21459 = gen_frame_store (gen_rtx_REG (Pmode
, 0), frame_reg_rtx
, lr_offset
);
21461 par
= gen_rtx_PARALLEL (VOIDmode
, p
);
21463 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
21465 insn
= emit_jump_insn (par
);
21466 JUMP_LABEL (insn
) = ret_rtx
;
21469 insn
= emit_insn (par
);
21473 /* Determine whether the gp REG is really used. */
21476 rs6000_reg_live_or_pic_offset_p (int reg
)
21478 /* If the function calls eh_return, claim used all the registers that would
21479 be checked for liveness otherwise. This is required for the PIC offset
21480 register with -mminimal-toc on AIX, as it is advertised as "fixed" for
21481 register allocation purposes in this case. */
21483 return (((crtl
->calls_eh_return
|| df_regs_ever_live_p (reg
))
21484 && (!call_used_regs
[reg
]
21485 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
21486 && !TARGET_SINGLE_PIC_BASE
21487 && TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
21488 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
21489 && !TARGET_SINGLE_PIC_BASE
21490 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
21491 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
))));
21494 /* Emit function prologue as insns. */
21497 rs6000_emit_prologue (void)
21499 rs6000_stack_t
*info
= rs6000_stack_info ();
21500 enum machine_mode reg_mode
= Pmode
;
21501 int reg_size
= TARGET_32BIT
? 4 : 8;
21502 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
21503 rtx frame_reg_rtx
= sp_reg_rtx
;
21504 unsigned int cr_save_regno
;
21505 rtx cr_save_rtx
= NULL_RTX
;
21508 int using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
21509 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
21510 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
21511 /* Offset to top of frame for frame_reg and sp respectively. */
21512 HOST_WIDE_INT frame_off
= 0;
21513 HOST_WIDE_INT sp_off
= 0;
21515 #ifdef ENABLE_CHECKING
21516 /* Track and check usage of r0, r11, r12. */
21517 int reg_inuse
= using_static_chain_p
? 1 << 11 : 0;
21518 #define START_USE(R) do \
21520 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
21521 reg_inuse |= 1 << (R); \
21523 #define END_USE(R) do \
21525 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
21526 reg_inuse &= ~(1 << (R)); \
21528 #define NOT_INUSE(R) do \
21530 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
21533 #define START_USE(R) do {} while (0)
21534 #define END_USE(R) do {} while (0)
21535 #define NOT_INUSE(R) do {} while (0)
21538 if (flag_stack_usage_info
)
21539 current_function_static_stack_size
= info
->total_size
;
21541 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
21543 HOST_WIDE_INT size
= info
->total_size
;
21545 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
21547 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
21548 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT
,
21549 size
- STACK_CHECK_PROTECT
);
21552 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
21555 if (TARGET_FIX_AND_CONTINUE
)
21557 /* gdb on darwin arranges to forward a function from the old
21558 address by modifying the first 5 instructions of the function
21559 to branch to the overriding function. This is necessary to
21560 permit function pointers that point to the old function to
21561 actually forward to the new function. */
21562 emit_insn (gen_nop ());
21563 emit_insn (gen_nop ());
21564 emit_insn (gen_nop ());
21565 emit_insn (gen_nop ());
21566 emit_insn (gen_nop ());
21569 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
21571 reg_mode
= V2SImode
;
21575 /* Handle world saves specially here. */
21576 if (WORLD_SAVE_P (info
))
21583 /* save_world expects lr in r0. */
21584 reg0
= gen_rtx_REG (Pmode
, 0);
21585 if (info
->lr_save_p
)
21587 insn
= emit_move_insn (reg0
,
21588 gen_rtx_REG (Pmode
, LR_REGNO
));
21589 RTX_FRAME_RELATED_P (insn
) = 1;
21592 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
21593 assumptions about the offsets of various bits of the stack
21595 gcc_assert (info
->gp_save_offset
== -220
21596 && info
->fp_save_offset
== -144
21597 && info
->lr_save_offset
== 8
21598 && info
->cr_save_offset
== 4
21601 && (!crtl
->calls_eh_return
21602 || info
->ehrd_offset
== -432)
21603 && info
->vrsave_save_offset
== -224
21604 && info
->altivec_save_offset
== -416);
21606 treg
= gen_rtx_REG (SImode
, 11);
21607 emit_move_insn (treg
, GEN_INT (-info
->total_size
));
21609 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
21610 in R11. It also clobbers R12, so beware! */
21612 /* Preserve CR2 for save_world prologues */
21614 sz
+= 32 - info
->first_gp_reg_save
;
21615 sz
+= 64 - info
->first_fp_reg_save
;
21616 sz
+= LAST_ALTIVEC_REGNO
- info
->first_altivec_reg_save
+ 1;
21617 p
= rtvec_alloc (sz
);
21619 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
,
21620 gen_rtx_REG (SImode
,
21622 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
21623 gen_rtx_SYMBOL_REF (Pmode
,
21625 /* We do floats first so that the instruction pattern matches
21627 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
21629 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
21631 info
->first_fp_reg_save
+ i
),
21633 info
->fp_save_offset
+ frame_off
+ 8 * i
);
21634 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
21636 = gen_frame_store (gen_rtx_REG (V4SImode
,
21637 info
->first_altivec_reg_save
+ i
),
21639 info
->altivec_save_offset
+ frame_off
+ 16 * i
);
21640 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
21642 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
21644 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
21646 /* CR register traditionally saved as CR2. */
21648 = gen_frame_store (gen_rtx_REG (SImode
, CR2_REGNO
),
21649 frame_reg_rtx
, info
->cr_save_offset
+ frame_off
);
21650 /* Explain about use of R0. */
21651 if (info
->lr_save_p
)
21653 = gen_frame_store (reg0
,
21654 frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
21655 /* Explain what happens to the stack pointer. */
21657 rtx newval
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
, treg
);
21658 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, sp_reg_rtx
, newval
);
21661 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
21662 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
21663 treg
, GEN_INT (-info
->total_size
));
21664 sp_off
= frame_off
= info
->total_size
;
21667 strategy
= info
->savres_strategy
;
21669 /* For V.4, update stack before we do any saving and set back pointer. */
21670 if (! WORLD_SAVE_P (info
)
21672 && (DEFAULT_ABI
== ABI_V4
21673 || crtl
->calls_eh_return
))
21675 bool need_r11
= (TARGET_SPE
21676 ? (!(strategy
& SAVE_INLINE_GPRS
)
21677 && info
->spe_64bit_regs_used
== 0)
21678 : (!(strategy
& SAVE_INLINE_FPRS
)
21679 || !(strategy
& SAVE_INLINE_GPRS
)
21680 || !(strategy
& SAVE_INLINE_VRS
)));
21681 int ptr_regno
= -1;
21682 rtx ptr_reg
= NULL_RTX
;
21685 if (info
->total_size
< 32767)
21686 frame_off
= info
->total_size
;
21689 else if (info
->cr_save_p
21691 || info
->first_fp_reg_save
< 64
21692 || info
->first_gp_reg_save
< 32
21693 || info
->altivec_size
!= 0
21694 || info
->vrsave_mask
!= 0
21695 || crtl
->calls_eh_return
)
21699 /* The prologue won't be saving any regs so there is no need
21700 to set up a frame register to access any frame save area.
21701 We also won't be using frame_off anywhere below, but set
21702 the correct value anyway to protect against future
21703 changes to this function. */
21704 frame_off
= info
->total_size
;
21706 if (ptr_regno
!= -1)
21708 /* Set up the frame offset to that needed by the first
21709 out-of-line save function. */
21710 START_USE (ptr_regno
);
21711 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
21712 frame_reg_rtx
= ptr_reg
;
21713 if (!(strategy
& SAVE_INLINE_FPRS
) && info
->fp_size
!= 0)
21714 gcc_checking_assert (info
->fp_save_offset
+ info
->fp_size
== 0);
21715 else if (!(strategy
& SAVE_INLINE_GPRS
) && info
->first_gp_reg_save
< 32)
21716 ptr_off
= info
->gp_save_offset
+ info
->gp_size
;
21717 else if (!(strategy
& SAVE_INLINE_VRS
) && info
->altivec_size
!= 0)
21718 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
21719 frame_off
= -ptr_off
;
21721 rs6000_emit_allocate_stack (info
->total_size
, ptr_reg
, ptr_off
);
21722 sp_off
= info
->total_size
;
21723 if (frame_reg_rtx
!= sp_reg_rtx
)
21724 rs6000_emit_stack_tie (frame_reg_rtx
, false);
21727 /* If we use the link register, get it into r0. */
21728 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
)
21730 rtx addr
, reg
, mem
;
21732 reg
= gen_rtx_REG (Pmode
, 0);
21734 insn
= emit_move_insn (reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
21735 RTX_FRAME_RELATED_P (insn
) = 1;
21737 if (!(strategy
& (SAVE_NOINLINE_GPRS_SAVES_LR
21738 | SAVE_NOINLINE_FPRS_SAVES_LR
)))
21740 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
21741 GEN_INT (info
->lr_save_offset
+ frame_off
));
21742 mem
= gen_rtx_MEM (Pmode
, addr
);
21743 /* This should not be of rs6000_sr_alias_set, because of
21744 __builtin_return_address. */
21746 insn
= emit_move_insn (mem
, reg
);
21747 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
21748 NULL_RTX
, NULL_RTX
);
21753 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
21754 r12 will be needed by out-of-line gpr restore. */
21755 cr_save_regno
= (DEFAULT_ABI
== ABI_AIX
21756 && !(strategy
& (SAVE_INLINE_GPRS
21757 | SAVE_NOINLINE_GPRS_SAVES_LR
))
21759 if (!WORLD_SAVE_P (info
)
21761 && REGNO (frame_reg_rtx
) != cr_save_regno
21762 && !(using_static_chain_p
&& cr_save_regno
== 11))
21766 cr_save_rtx
= gen_rtx_REG (SImode
, cr_save_regno
);
21767 START_USE (cr_save_regno
);
21768 insn
= emit_insn (gen_movesi_from_cr (cr_save_rtx
));
21769 RTX_FRAME_RELATED_P (insn
) = 1;
21770 /* Now, there's no way that dwarf2out_frame_debug_expr is going
21771 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
21772 But that's OK. All we have to do is specify that _one_ condition
21773 code register is saved in this stack slot. The thrower's epilogue
21774 will then restore all the call-saved registers.
21775 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
21776 set
= gen_rtx_SET (VOIDmode
, cr_save_rtx
,
21777 gen_rtx_REG (SImode
, CR2_REGNO
));
21778 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
21781 /* Do any required saving of fpr's. If only one or two to save, do
21782 it ourselves. Otherwise, call function. */
21783 if (!WORLD_SAVE_P (info
) && (strategy
& SAVE_INLINE_FPRS
))
21786 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
21787 if (save_reg_p (info
->first_fp_reg_save
+ i
))
21788 emit_frame_save (frame_reg_rtx
,
21789 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
21790 ? DFmode
: SFmode
),
21791 info
->first_fp_reg_save
+ i
,
21792 info
->fp_save_offset
+ frame_off
+ 8 * i
,
21793 sp_off
- frame_off
);
21795 else if (!WORLD_SAVE_P (info
) && info
->first_fp_reg_save
!= 64)
21797 bool lr
= (strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
21798 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
21799 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
21800 rtx ptr_reg
= frame_reg_rtx
;
21802 if (REGNO (frame_reg_rtx
) == ptr_regno
)
21803 gcc_checking_assert (frame_off
== 0);
21806 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
21807 NOT_INUSE (ptr_regno
);
21808 emit_insn (gen_add3_insn (ptr_reg
,
21809 frame_reg_rtx
, GEN_INT (frame_off
)));
21811 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
21812 info
->fp_save_offset
,
21813 info
->lr_save_offset
,
21815 rs6000_frame_related (insn
, ptr_reg
, sp_off
,
21816 NULL_RTX
, NULL_RTX
);
21821 /* Save GPRs. This is done as a PARALLEL if we are using
21822 the store-multiple instructions. */
21823 if (!WORLD_SAVE_P (info
)
21825 && info
->spe_64bit_regs_used
!= 0
21826 && info
->first_gp_reg_save
!= 32)
21829 rtx spe_save_area_ptr
;
21830 HOST_WIDE_INT save_off
;
21831 int ool_adjust
= 0;
21833 /* Determine whether we can address all of the registers that need
21834 to be saved with an offset from frame_reg_rtx that fits in
21835 the small const field for SPE memory instructions. */
21836 int spe_regs_addressable
21837 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ frame_off
21838 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
21839 && (strategy
& SAVE_INLINE_GPRS
));
21841 if (spe_regs_addressable
)
21843 spe_save_area_ptr
= frame_reg_rtx
;
21844 save_off
= frame_off
;
21848 /* Make r11 point to the start of the SPE save area. We need
21849 to be careful here if r11 is holding the static chain. If
21850 it is, then temporarily save it in r0. */
21851 HOST_WIDE_INT offset
;
21853 if (!(strategy
& SAVE_INLINE_GPRS
))
21854 ool_adjust
= 8 * (info
->first_gp_reg_save
- FIRST_SAVED_GP_REGNO
);
21855 offset
= info
->spe_gp_save_offset
+ frame_off
- ool_adjust
;
21856 spe_save_area_ptr
= gen_rtx_REG (Pmode
, 11);
21857 save_off
= frame_off
- offset
;
21859 if (using_static_chain_p
)
21861 rtx r0
= gen_rtx_REG (Pmode
, 0);
21864 gcc_assert (info
->first_gp_reg_save
> 11);
21866 emit_move_insn (r0
, spe_save_area_ptr
);
21868 else if (REGNO (frame_reg_rtx
) != 11)
21871 emit_insn (gen_addsi3 (spe_save_area_ptr
,
21872 frame_reg_rtx
, GEN_INT (offset
)));
21873 if (!using_static_chain_p
&& REGNO (frame_reg_rtx
) == 11)
21874 frame_off
= -info
->spe_gp_save_offset
+ ool_adjust
;
21877 if ((strategy
& SAVE_INLINE_GPRS
))
21879 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
21880 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
21881 emit_frame_save (spe_save_area_ptr
, reg_mode
,
21882 info
->first_gp_reg_save
+ i
,
21883 (info
->spe_gp_save_offset
+ save_off
21885 sp_off
- save_off
);
21889 insn
= rs6000_emit_savres_rtx (info
, spe_save_area_ptr
,
21890 info
->spe_gp_save_offset
+ save_off
,
21892 SAVRES_SAVE
| SAVRES_GPR
);
21894 rs6000_frame_related (insn
, spe_save_area_ptr
, sp_off
- save_off
,
21895 NULL_RTX
, NULL_RTX
);
21898 /* Move the static chain pointer back. */
21899 if (!spe_regs_addressable
)
21901 if (using_static_chain_p
)
21903 emit_move_insn (spe_save_area_ptr
, gen_rtx_REG (Pmode
, 0));
21906 else if (REGNO (frame_reg_rtx
) != 11)
21910 else if (!WORLD_SAVE_P (info
) && !(strategy
& SAVE_INLINE_GPRS
))
21912 bool lr
= (strategy
& SAVE_NOINLINE_GPRS_SAVES_LR
) != 0;
21913 int sel
= SAVRES_SAVE
| SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
21914 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
21915 rtx ptr_reg
= frame_reg_rtx
;
21916 bool ptr_set_up
= REGNO (ptr_reg
) == ptr_regno
;
21917 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
21921 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
21923 /* Need to adjust r11 (r12) if we saved any FPRs. */
21924 if (end_save
+ frame_off
!= 0)
21926 rtx offset
= GEN_INT (end_save
+ frame_off
);
21929 frame_off
= -end_save
;
21931 NOT_INUSE (ptr_regno
);
21932 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
21934 else if (!ptr_set_up
)
21936 NOT_INUSE (ptr_regno
);
21937 emit_move_insn (ptr_reg
, frame_reg_rtx
);
21939 ptr_off
= -end_save
;
21940 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
21941 info
->gp_save_offset
+ ptr_off
,
21942 info
->lr_save_offset
+ ptr_off
,
21944 rs6000_frame_related (insn
, ptr_reg
, sp_off
- ptr_off
,
21945 NULL_RTX
, NULL_RTX
);
21949 else if (!WORLD_SAVE_P (info
) && (strategy
& SAVRES_MULTIPLE
))
21953 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
21954 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
21956 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
21958 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
21959 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
21960 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
21961 NULL_RTX
, NULL_RTX
);
21963 else if (!WORLD_SAVE_P (info
))
21966 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
21967 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
21968 emit_frame_save (frame_reg_rtx
, reg_mode
,
21969 info
->first_gp_reg_save
+ i
,
21970 info
->gp_save_offset
+ frame_off
+ reg_size
* i
,
21971 sp_off
- frame_off
);
21974 if (crtl
->calls_eh_return
)
21981 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
21982 if (regno
== INVALID_REGNUM
)
21986 p
= rtvec_alloc (i
);
21990 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
21991 if (regno
== INVALID_REGNUM
)
21995 = gen_frame_store (gen_rtx_REG (reg_mode
, regno
),
21997 info
->ehrd_offset
+ sp_off
+ reg_size
* (int) i
);
21998 RTVEC_ELT (p
, i
) = insn
;
21999 RTX_FRAME_RELATED_P (insn
) = 1;
22002 insn
= emit_insn (gen_blockage ());
22003 RTX_FRAME_RELATED_P (insn
) = 1;
22004 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, gen_rtx_PARALLEL (VOIDmode
, p
));
22007 /* In AIX ABI we need to make sure r2 is really saved. */
22008 if (TARGET_AIX
&& crtl
->calls_eh_return
)
22010 rtx tmp_reg
, tmp_reg_si
, hi
, lo
, compare_result
, toc_save_done
, jump
;
22011 rtx save_insn
, join_insn
, note
;
22012 long toc_restore_insn
;
22014 tmp_reg
= gen_rtx_REG (Pmode
, 11);
22015 tmp_reg_si
= gen_rtx_REG (SImode
, 11);
22016 if (using_static_chain_p
)
22019 emit_move_insn (gen_rtx_REG (Pmode
, 0), tmp_reg
);
22023 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
22024 /* Peek at instruction to which this function returns. If it's
22025 restoring r2, then we know we've already saved r2. We can't
22026 unconditionally save r2 because the value we have will already
22027 be updated if we arrived at this function via a plt call or
22028 toc adjusting stub. */
22029 emit_move_insn (tmp_reg_si
, gen_rtx_MEM (SImode
, tmp_reg
));
22030 toc_restore_insn
= TARGET_32BIT
? 0x80410014 : 0xE8410028;
22031 hi
= gen_int_mode (toc_restore_insn
& ~0xffff, SImode
);
22032 emit_insn (gen_xorsi3 (tmp_reg_si
, tmp_reg_si
, hi
));
22033 compare_result
= gen_rtx_REG (CCUNSmode
, CR0_REGNO
);
22034 validate_condition_mode (EQ
, CCUNSmode
);
22035 lo
= gen_int_mode (toc_restore_insn
& 0xffff, SImode
);
22036 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
22037 gen_rtx_COMPARE (CCUNSmode
, tmp_reg_si
, lo
)));
22038 toc_save_done
= gen_label_rtx ();
22039 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
22040 gen_rtx_EQ (VOIDmode
, compare_result
,
22042 gen_rtx_LABEL_REF (VOIDmode
, toc_save_done
),
22044 jump
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, jump
));
22045 JUMP_LABEL (jump
) = toc_save_done
;
22046 LABEL_NUSES (toc_save_done
) += 1;
22048 save_insn
= emit_frame_save (frame_reg_rtx
, reg_mode
,
22049 TOC_REGNUM
, frame_off
+ 5 * reg_size
,
22050 sp_off
- frame_off
);
22052 emit_label (toc_save_done
);
22054 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
22055 have a CFG that has different saves along different paths.
22056 Move the note to a dummy blockage insn, which describes that
22057 R2 is unconditionally saved after the label. */
22058 /* ??? An alternate representation might be a special insn pattern
22059 containing both the branch and the store. That might let the
22060 code that minimizes the number of DW_CFA_advance opcodes better
22061 freedom in placing the annotations. */
22062 note
= find_reg_note (save_insn
, REG_FRAME_RELATED_EXPR
, NULL
);
22064 remove_note (save_insn
, note
);
22066 note
= alloc_reg_note (REG_FRAME_RELATED_EXPR
,
22067 copy_rtx (PATTERN (save_insn
)), NULL_RTX
);
22068 RTX_FRAME_RELATED_P (save_insn
) = 0;
22070 join_insn
= emit_insn (gen_blockage ());
22071 REG_NOTES (join_insn
) = note
;
22072 RTX_FRAME_RELATED_P (join_insn
) = 1;
22074 if (using_static_chain_p
)
22076 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, 0));
22083 /* Save CR if we use any that must be preserved. */
22084 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
)
22086 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
22087 GEN_INT (info
->cr_save_offset
+ frame_off
));
22088 rtx mem
= gen_frame_mem (SImode
, addr
);
22089 /* See the large comment above about why CR2_REGNO is used. */
22090 rtx magic_eh_cr_reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
22092 /* If we didn't copy cr before, do so now using r0. */
22093 if (cr_save_rtx
== NULL_RTX
)
22098 cr_save_rtx
= gen_rtx_REG (SImode
, 0);
22099 insn
= emit_insn (gen_movesi_from_cr (cr_save_rtx
));
22100 RTX_FRAME_RELATED_P (insn
) = 1;
22101 set
= gen_rtx_SET (VOIDmode
, cr_save_rtx
, magic_eh_cr_reg
);
22102 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
22104 insn
= emit_move_insn (mem
, cr_save_rtx
);
22105 END_USE (REGNO (cr_save_rtx
));
22107 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
22108 NULL_RTX
, NULL_RTX
);
22111 /* Update stack and set back pointer unless this is V.4,
22112 for which it was done previously. */
22113 if (!WORLD_SAVE_P (info
) && info
->push_p
22114 && !(DEFAULT_ABI
== ABI_V4
|| crtl
->calls_eh_return
))
22116 rtx ptr_reg
= NULL
;
22119 /* If saving altivec regs we need to be able to address all save
22120 locations using a 16-bit offset. */
22121 if ((strategy
& SAVE_INLINE_VRS
) == 0
22122 || (info
->altivec_size
!= 0
22123 && (info
->altivec_save_offset
+ info
->altivec_size
- 16
22124 + info
->total_size
- frame_off
) > 32767)
22125 || (info
->vrsave_size
!= 0
22126 && (info
->vrsave_save_offset
22127 + info
->total_size
- frame_off
) > 32767))
22129 int sel
= SAVRES_SAVE
| SAVRES_VR
;
22130 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
22132 if (using_static_chain_p
22133 && ptr_regno
== STATIC_CHAIN_REGNUM
)
22135 if (REGNO (frame_reg_rtx
) != ptr_regno
)
22136 START_USE (ptr_regno
);
22137 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
22138 frame_reg_rtx
= ptr_reg
;
22139 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
22140 frame_off
= -ptr_off
;
22142 else if (REGNO (frame_reg_rtx
) == 1)
22143 frame_off
= info
->total_size
;
22144 rs6000_emit_allocate_stack (info
->total_size
, ptr_reg
, ptr_off
);
22145 sp_off
= info
->total_size
;
22146 if (frame_reg_rtx
!= sp_reg_rtx
)
22147 rs6000_emit_stack_tie (frame_reg_rtx
, false);
22150 /* Set frame pointer, if needed. */
22151 if (frame_pointer_needed
)
22153 insn
= emit_move_insn (gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
22155 RTX_FRAME_RELATED_P (insn
) = 1;
22158 /* Save AltiVec registers if needed. Save here because the red zone does
22159 not always include AltiVec registers. */
22160 if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
22161 && info
->altivec_size
!= 0 && (strategy
& SAVE_INLINE_VRS
) == 0)
22163 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
22165 /* Oddly, the vector save/restore functions point r0 at the end
22166 of the save area, then use r11 or r12 to load offsets for
22167 [reg+reg] addressing. */
22168 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
22169 int scratch_regno
= ptr_regno_for_savres (SAVRES_SAVE
| SAVRES_VR
);
22170 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
22172 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
22174 if (end_save
+ frame_off
!= 0)
22176 rtx offset
= GEN_INT (end_save
+ frame_off
);
22178 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
22181 emit_move_insn (ptr_reg
, frame_reg_rtx
);
22183 ptr_off
= -end_save
;
22184 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
22185 info
->altivec_save_offset
+ ptr_off
,
22186 0, V4SImode
, SAVRES_SAVE
| SAVRES_VR
);
22187 rs6000_frame_related (insn
, scratch_reg
, sp_off
- ptr_off
,
22188 NULL_RTX
, NULL_RTX
);
22189 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
22191 /* The oddity mentioned above clobbered our frame reg. */
22192 emit_move_insn (frame_reg_rtx
, ptr_reg
);
22193 frame_off
= ptr_off
;
22196 else if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
22197 && info
->altivec_size
!= 0)
22201 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
22202 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
22204 rtx areg
, savereg
, mem
;
22207 offset
= (info
->altivec_save_offset
+ frame_off
22208 + 16 * (i
- info
->first_altivec_reg_save
));
22210 savereg
= gen_rtx_REG (V4SImode
, i
);
22213 areg
= gen_rtx_REG (Pmode
, 0);
22214 emit_move_insn (areg
, GEN_INT (offset
));
22216 /* AltiVec addressing mode is [reg+reg]. */
22217 mem
= gen_frame_mem (V4SImode
,
22218 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
));
22220 insn
= emit_move_insn (mem
, savereg
);
22222 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
22223 areg
, GEN_INT (offset
));
22227 /* VRSAVE is a bit vector representing which AltiVec registers
22228 are used. The OS uses this to determine which vector
22229 registers to save on a context switch. We need to save
22230 VRSAVE on the stack frame, add whatever AltiVec registers we
22231 used in this function, and do the corresponding magic in the
22234 if (!WORLD_SAVE_P (info
)
22236 && TARGET_ALTIVEC_VRSAVE
22237 && info
->vrsave_mask
!= 0)
22243 /* Get VRSAVE onto a GPR. Note that ABI_V4 and ABI_DARWIN might
22244 be using r12 as frame_reg_rtx and r11 as the static chain
22245 pointer for nested functions. */
22247 if (DEFAULT_ABI
== ABI_AIX
&& !using_static_chain_p
)
22249 else if (REGNO (frame_reg_rtx
) == 12)
22252 if (using_static_chain_p
)
22256 NOT_INUSE (save_regno
);
22257 reg
= gen_rtx_REG (SImode
, save_regno
);
22258 vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
22260 emit_insn (gen_get_vrsave_internal (reg
));
22262 emit_insn (gen_rtx_SET (VOIDmode
, reg
, vrsave
));
22265 offset
= info
->vrsave_save_offset
+ frame_off
;
22266 insn
= emit_insn (gen_frame_store (reg
, frame_reg_rtx
, offset
));
22268 /* Include the registers in the mask. */
22269 emit_insn (gen_iorsi3 (reg
, reg
, GEN_INT ((int) info
->vrsave_mask
)));
22271 insn
= emit_insn (generate_set_vrsave (reg
, info
, 0));
22274 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
22275 if (!TARGET_SINGLE_PIC_BASE
22276 && ((TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
22277 || (DEFAULT_ABI
== ABI_V4
22278 && (flag_pic
== 1 || (flag_pic
&& TARGET_SECURE_PLT
))
22279 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))))
22281 /* If emit_load_toc_table will use the link register, we need to save
22282 it. We use R12 for this purpose because emit_load_toc_table
22283 can use register 0. This allows us to use a plain 'blr' to return
22284 from the procedure more often. */
22285 int save_LR_around_toc_setup
= (TARGET_ELF
22286 && DEFAULT_ABI
!= ABI_AIX
22288 && ! info
->lr_save_p
22289 && EDGE_COUNT (EXIT_BLOCK_PTR
->preds
) > 0);
22290 if (save_LR_around_toc_setup
)
22292 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
22293 rtx tmp
= gen_rtx_REG (Pmode
, 12);
22295 insn
= emit_move_insn (tmp
, lr
);
22296 RTX_FRAME_RELATED_P (insn
) = 1;
22298 rs6000_emit_load_toc_table (TRUE
);
22300 insn
= emit_move_insn (lr
, tmp
);
22301 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
22302 RTX_FRAME_RELATED_P (insn
) = 1;
22305 rs6000_emit_load_toc_table (TRUE
);
22309 if (!TARGET_SINGLE_PIC_BASE
22310 && DEFAULT_ABI
== ABI_DARWIN
22311 && flag_pic
&& crtl
->uses_pic_offset_table
)
22313 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
22314 rtx src
= gen_rtx_SYMBOL_REF (Pmode
, MACHOPIC_FUNCTION_BASE_NAME
);
22316 /* Save and restore LR locally around this call (in R0). */
22317 if (!info
->lr_save_p
)
22318 emit_move_insn (gen_rtx_REG (Pmode
, 0), lr
);
22320 emit_insn (gen_load_macho_picbase (src
));
22322 emit_move_insn (gen_rtx_REG (Pmode
,
22323 RS6000_PIC_OFFSET_TABLE_REGNUM
),
22326 if (!info
->lr_save_p
)
22327 emit_move_insn (lr
, gen_rtx_REG (Pmode
, 0));
22331 /* If we need to, save the TOC register after doing the stack setup.
22332 Do not emit eh frame info for this save. The unwinder wants info,
22333 conceptually attached to instructions in this function, about
22334 register values in the caller of this function. This R2 may have
22335 already been changed from the value in the caller.
22336 We don't attempt to write accurate DWARF EH frame info for R2
22337 because code emitted by gcc for a (non-pointer) function call
22338 doesn't save and restore R2. Instead, R2 is managed out-of-line
22339 by a linker generated plt call stub when the function resides in
22340 a shared library. This behaviour is costly to describe in DWARF,
22341 both in terms of the size of DWARF info and the time taken in the
22342 unwinder to interpret it. R2 changes, apart from the
22343 calls_eh_return case earlier in this function, are handled by
22344 linux-unwind.h frob_update_context. */
22345 if (rs6000_save_toc_in_prologue_p ())
22347 rtx reg
= gen_rtx_REG (reg_mode
, TOC_REGNUM
);
22348 emit_insn (gen_frame_store (reg
, sp_reg_rtx
, 5 * reg_size
));
22352 /* Write function prologue. */
22355 rs6000_output_function_prologue (FILE *file
,
22356 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
22358 rs6000_stack_t
*info
= rs6000_stack_info ();
22360 if (TARGET_DEBUG_STACK
)
22361 debug_stack_info (info
);
22363 /* Write .extern for any function we will call to save and restore
22365 if (info
->first_fp_reg_save
< 64
22370 int regno
= info
->first_fp_reg_save
- 32;
22372 if ((info
->savres_strategy
& SAVE_INLINE_FPRS
) == 0)
22374 bool lr
= (info
->savres_strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
22375 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
22376 name
= rs6000_savres_routine_name (info
, regno
, sel
);
22377 fprintf (file
, "\t.extern %s\n", name
);
22379 if ((info
->savres_strategy
& REST_INLINE_FPRS
) == 0)
22381 bool lr
= (info
->savres_strategy
22382 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
22383 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
22384 name
= rs6000_savres_routine_name (info
, regno
, sel
);
22385 fprintf (file
, "\t.extern %s\n", name
);
22389 rs6000_pic_labelno
++;
22392 /* Non-zero if vmx regs are restored before the frame pop, zero if
22393 we restore after the pop when possible. */
22394 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
22396 /* Restoring cr is a two step process: loading a reg from the frame
22397 save, then moving the reg to cr. For ABI_V4 we must let the
22398 unwinder know that the stack location is no longer valid at or
22399 before the stack deallocation, but we can't emit a cfa_restore for
22400 cr at the stack deallocation like we do for other registers.
22401 The trouble is that it is possible for the move to cr to be
22402 scheduled after the stack deallocation. So say exactly where cr
22403 is located on each of the two insns. */
22406 load_cr_save (int regno
, rtx frame_reg_rtx
, int offset
, bool exit_func
)
22408 rtx mem
= gen_frame_mem_offset (SImode
, frame_reg_rtx
, offset
);
22409 rtx reg
= gen_rtx_REG (SImode
, regno
);
22410 rtx insn
= emit_move_insn (reg
, mem
);
22412 if (!exit_func
&& DEFAULT_ABI
== ABI_V4
)
22414 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
22415 rtx set
= gen_rtx_SET (VOIDmode
, reg
, cr
);
22417 add_reg_note (insn
, REG_CFA_REGISTER
, set
);
22418 RTX_FRAME_RELATED_P (insn
) = 1;
22423 /* Reload CR from REG. */
22426 restore_saved_cr (rtx reg
, int using_mfcr_multiple
, bool exit_func
)
22431 if (using_mfcr_multiple
)
22433 for (i
= 0; i
< 8; i
++)
22434 if (save_reg_p (CR0_REGNO
+ i
))
22436 gcc_assert (count
);
22439 if (using_mfcr_multiple
&& count
> 1)
22444 p
= rtvec_alloc (count
);
22447 for (i
= 0; i
< 8; i
++)
22448 if (save_reg_p (CR0_REGNO
+ i
))
22450 rtvec r
= rtvec_alloc (2);
22451 RTVEC_ELT (r
, 0) = reg
;
22452 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7-i
));
22453 RTVEC_ELT (p
, ndx
) =
22454 gen_rtx_SET (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
),
22455 gen_rtx_UNSPEC (CCmode
, r
, UNSPEC_MOVESI_TO_CR
));
22458 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
22459 gcc_assert (ndx
== count
);
22462 for (i
= 0; i
< 8; i
++)
22463 if (save_reg_p (CR0_REGNO
+ i
))
22464 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
),
22467 if (!exit_func
&& (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
22469 rtx insn
= get_last_insn ();
22470 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
22472 add_reg_note (insn
, REG_CFA_RESTORE
, cr
);
22473 RTX_FRAME_RELATED_P (insn
) = 1;
22477 /* Like cr, the move to lr instruction can be scheduled after the
22478 stack deallocation, but unlike cr, its stack frame save is still
22479 valid. So we only need to emit the cfa_restore on the correct
22483 load_lr_save (int regno
, rtx frame_reg_rtx
, int offset
)
22485 rtx mem
= gen_frame_mem_offset (Pmode
, frame_reg_rtx
, offset
);
22486 rtx reg
= gen_rtx_REG (Pmode
, regno
);
22488 emit_move_insn (reg
, mem
);
22492 restore_saved_lr (int regno
, bool exit_func
)
22494 rtx reg
= gen_rtx_REG (Pmode
, regno
);
22495 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
22496 rtx insn
= emit_move_insn (lr
, reg
);
22498 if (!exit_func
&& flag_shrink_wrap
)
22500 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
22501 RTX_FRAME_RELATED_P (insn
) = 1;
22506 add_crlr_cfa_restore (const rs6000_stack_t
*info
, rtx cfa_restores
)
22508 if (info
->cr_save_p
)
22509 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
22510 gen_rtx_REG (SImode
, CR2_REGNO
),
22512 if (info
->lr_save_p
)
22513 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
22514 gen_rtx_REG (Pmode
, LR_REGNO
),
22516 return cfa_restores
;
22519 /* Return true if OFFSET from stack pointer can be clobbered by signals.
22520 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
22521 below stack pointer not cloberred by signals. */
22524 offset_below_red_zone_p (HOST_WIDE_INT offset
)
22526 return offset
< (DEFAULT_ABI
== ABI_V4
22528 : TARGET_32BIT
? -220 : -288);
22531 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
22534 emit_cfa_restores (rtx cfa_restores
)
22536 rtx insn
= get_last_insn ();
22537 rtx
*loc
= ®_NOTES (insn
);
22540 loc
= &XEXP (*loc
, 1);
22541 *loc
= cfa_restores
;
22542 RTX_FRAME_RELATED_P (insn
) = 1;
22545 /* Emit function epilogue as insns. */
22548 rs6000_emit_epilogue (int sibcall
)
22550 rs6000_stack_t
*info
;
22551 int restoring_GPRs_inline
;
22552 int restoring_FPRs_inline
;
22553 int using_load_multiple
;
22554 int using_mtcr_multiple
;
22555 int use_backchain_to_restore_sp
;
22558 HOST_WIDE_INT frame_off
= 0;
22559 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, 1);
22560 rtx frame_reg_rtx
= sp_reg_rtx
;
22561 rtx cfa_restores
= NULL_RTX
;
22563 rtx cr_save_reg
= NULL_RTX
;
22564 enum machine_mode reg_mode
= Pmode
;
22565 int reg_size
= TARGET_32BIT
? 4 : 8;
22568 unsigned ptr_regno
;
22570 info
= rs6000_stack_info ();
22572 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
22574 reg_mode
= V2SImode
;
22578 strategy
= info
->savres_strategy
;
22579 using_load_multiple
= strategy
& SAVRES_MULTIPLE
;
22580 restoring_FPRs_inline
= sibcall
|| (strategy
& REST_INLINE_FPRS
);
22581 restoring_GPRs_inline
= sibcall
|| (strategy
& REST_INLINE_GPRS
);
22582 using_mtcr_multiple
= (rs6000_cpu
== PROCESSOR_PPC601
22583 || rs6000_cpu
== PROCESSOR_PPC603
22584 || rs6000_cpu
== PROCESSOR_PPC750
22586 /* Restore via the backchain when we have a large frame, since this
22587 is more efficient than an addis, addi pair. The second condition
22588 here will not trigger at the moment; We don't actually need a
22589 frame pointer for alloca, but the generic parts of the compiler
22590 give us one anyway. */
22591 use_backchain_to_restore_sp
= (info
->total_size
> 32767 - info
->lr_save_offset
22592 || (cfun
->calls_alloca
22593 && !frame_pointer_needed
));
22594 restore_lr
= (info
->lr_save_p
22595 && (restoring_FPRs_inline
22596 || (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
))
22597 && (restoring_GPRs_inline
22598 || info
->first_fp_reg_save
< 64));
22600 if (WORLD_SAVE_P (info
))
22604 const char *alloc_rname
;
22607 /* eh_rest_world_r10 will return to the location saved in the LR
22608 stack slot (which is not likely to be our caller.)
22609 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
22610 rest_world is similar, except any R10 parameter is ignored.
22611 The exception-handling stuff that was here in 2.95 is no
22612 longer necessary. */
22616 + 32 - info
->first_gp_reg_save
22617 + LAST_ALTIVEC_REGNO
+ 1 - info
->first_altivec_reg_save
22618 + 63 + 1 - info
->first_fp_reg_save
);
22620 strcpy (rname
, ((crtl
->calls_eh_return
) ?
22621 "*eh_rest_world_r10" : "*rest_world"));
22622 alloc_rname
= ggc_strdup (rname
);
22625 RTVEC_ELT (p
, j
++) = ret_rtx
;
22626 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
22627 gen_rtx_REG (Pmode
,
22630 = gen_rtx_USE (VOIDmode
, gen_rtx_SYMBOL_REF (Pmode
, alloc_rname
));
22631 /* The instruction pattern requires a clobber here;
22632 it is shared with the restVEC helper. */
22634 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 11));
22637 /* CR register traditionally saved as CR2. */
22638 rtx reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
22640 = gen_frame_load (reg
, frame_reg_rtx
, info
->cr_save_offset
);
22641 if (flag_shrink_wrap
)
22643 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
22644 gen_rtx_REG (Pmode
, LR_REGNO
),
22646 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
22650 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
22652 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
22654 = gen_frame_load (reg
,
22655 frame_reg_rtx
, info
->gp_save_offset
+ reg_size
* i
);
22656 if (flag_shrink_wrap
)
22657 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
22659 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
22661 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
22663 = gen_frame_load (reg
,
22664 frame_reg_rtx
, info
->altivec_save_offset
+ 16 * i
);
22665 if (flag_shrink_wrap
)
22666 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
22668 for (i
= 0; info
->first_fp_reg_save
+ i
<= 63; i
++)
22670 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
22671 ? DFmode
: SFmode
),
22672 info
->first_fp_reg_save
+ i
);
22674 = gen_frame_load (reg
, frame_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
22675 if (flag_shrink_wrap
)
22676 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
22679 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 0));
22681 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 12));
22683 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 7));
22685 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 8));
22687 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, 10));
22688 insn
= emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
22690 if (flag_shrink_wrap
)
22692 REG_NOTES (insn
) = cfa_restores
;
22693 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
22694 RTX_FRAME_RELATED_P (insn
) = 1;
22699 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
22701 frame_off
= info
->total_size
;
22703 /* Restore AltiVec registers if we must do so before adjusting the
22705 if (TARGET_ALTIVEC_ABI
22706 && info
->altivec_size
!= 0
22707 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
22708 || (DEFAULT_ABI
!= ABI_V4
22709 && offset_below_red_zone_p (info
->altivec_save_offset
))))
22712 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
22714 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
22715 if (use_backchain_to_restore_sp
)
22717 int frame_regno
= 11;
22719 if ((strategy
& REST_INLINE_VRS
) == 0)
22721 /* Of r11 and r12, select the one not clobbered by an
22722 out-of-line restore function for the frame register. */
22723 frame_regno
= 11 + 12 - scratch_regno
;
22725 frame_reg_rtx
= gen_rtx_REG (Pmode
, frame_regno
);
22726 emit_move_insn (frame_reg_rtx
,
22727 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
22730 else if (frame_pointer_needed
)
22731 frame_reg_rtx
= hard_frame_pointer_rtx
;
22733 if ((strategy
& REST_INLINE_VRS
) == 0)
22735 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
22737 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
22738 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
22740 if (end_save
+ frame_off
!= 0)
22742 rtx offset
= GEN_INT (end_save
+ frame_off
);
22744 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
22747 emit_move_insn (ptr_reg
, frame_reg_rtx
);
22749 ptr_off
= -end_save
;
22750 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
22751 info
->altivec_save_offset
+ ptr_off
,
22752 0, V4SImode
, SAVRES_VR
);
22756 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
22757 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
22759 rtx addr
, areg
, mem
, reg
;
22761 areg
= gen_rtx_REG (Pmode
, 0);
22763 (areg
, GEN_INT (info
->altivec_save_offset
22765 + 16 * (i
- info
->first_altivec_reg_save
)));
22767 /* AltiVec addressing mode is [reg+reg]. */
22768 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
22769 mem
= gen_frame_mem (V4SImode
, addr
);
22771 reg
= gen_rtx_REG (V4SImode
, i
);
22772 emit_move_insn (reg
, mem
);
22776 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
22777 if (((strategy
& REST_INLINE_VRS
) == 0
22778 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
22779 && (flag_shrink_wrap
22780 || (offset_below_red_zone_p
22781 (info
->altivec_save_offset
22782 + 16 * (i
- info
->first_altivec_reg_save
)))))
22784 rtx reg
= gen_rtx_REG (V4SImode
, i
);
22785 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
22789 /* Restore VRSAVE if we must do so before adjusting the stack. */
22791 && TARGET_ALTIVEC_VRSAVE
22792 && info
->vrsave_mask
!= 0
22793 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
22794 || (DEFAULT_ABI
!= ABI_V4
22795 && offset_below_red_zone_p (info
->vrsave_save_offset
))))
22799 if (frame_reg_rtx
== sp_reg_rtx
)
22801 if (use_backchain_to_restore_sp
)
22803 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
22804 emit_move_insn (frame_reg_rtx
,
22805 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
22808 else if (frame_pointer_needed
)
22809 frame_reg_rtx
= hard_frame_pointer_rtx
;
22812 reg
= gen_rtx_REG (SImode
, 12);
22813 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
22814 info
->vrsave_save_offset
+ frame_off
));
22816 emit_insn (generate_set_vrsave (reg
, info
, 1));
22820 /* If we have a large stack frame, restore the old stack pointer
22821 using the backchain. */
22822 if (use_backchain_to_restore_sp
)
22824 if (frame_reg_rtx
== sp_reg_rtx
)
22826 /* Under V.4, don't reset the stack pointer until after we're done
22827 loading the saved registers. */
22828 if (DEFAULT_ABI
== ABI_V4
)
22829 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
22831 insn
= emit_move_insn (frame_reg_rtx
,
22832 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
22835 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
22836 && DEFAULT_ABI
== ABI_V4
)
22837 /* frame_reg_rtx has been set up by the altivec restore. */
22841 insn
= emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
22842 frame_reg_rtx
= sp_reg_rtx
;
22845 /* If we have a frame pointer, we can restore the old stack pointer
22847 else if (frame_pointer_needed
)
22849 frame_reg_rtx
= sp_reg_rtx
;
22850 if (DEFAULT_ABI
== ABI_V4
)
22851 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
22852 /* Prevent reordering memory accesses against stack pointer restore. */
22853 else if (cfun
->calls_alloca
22854 || offset_below_red_zone_p (-info
->total_size
))
22855 rs6000_emit_stack_tie (frame_reg_rtx
, true);
22857 insn
= emit_insn (gen_add3_insn (frame_reg_rtx
, hard_frame_pointer_rtx
,
22858 GEN_INT (info
->total_size
)));
22861 else if (info
->push_p
22862 && DEFAULT_ABI
!= ABI_V4
22863 && !crtl
->calls_eh_return
)
22865 /* Prevent reordering memory accesses against stack pointer restore. */
22866 if (cfun
->calls_alloca
22867 || offset_below_red_zone_p (-info
->total_size
))
22868 rs6000_emit_stack_tie (frame_reg_rtx
, false);
22869 insn
= emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
,
22870 GEN_INT (info
->total_size
)));
22873 if (insn
&& frame_reg_rtx
== sp_reg_rtx
)
22877 REG_NOTES (insn
) = cfa_restores
;
22878 cfa_restores
= NULL_RTX
;
22880 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
22881 RTX_FRAME_RELATED_P (insn
) = 1;
22884 /* Restore AltiVec registers if we have not done so already. */
22885 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
22886 && TARGET_ALTIVEC_ABI
22887 && info
->altivec_size
!= 0
22888 && (DEFAULT_ABI
== ABI_V4
22889 || !offset_below_red_zone_p (info
->altivec_save_offset
)))
22893 if ((strategy
& REST_INLINE_VRS
) == 0)
22895 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
22897 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
22898 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
22899 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
22901 if (end_save
+ frame_off
!= 0)
22903 rtx offset
= GEN_INT (end_save
+ frame_off
);
22905 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
22908 emit_move_insn (ptr_reg
, frame_reg_rtx
);
22910 ptr_off
= -end_save
;
22911 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
22912 info
->altivec_save_offset
+ ptr_off
,
22913 0, V4SImode
, SAVRES_VR
);
22914 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
22916 /* Frame reg was clobbered by out-of-line save. Restore it
22917 from ptr_reg, and if we are calling out-of-line gpr or
22918 fpr restore set up the correct pointer and offset. */
22919 unsigned newptr_regno
= 1;
22920 if (!restoring_GPRs_inline
)
22922 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
22923 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
22924 newptr_regno
= ptr_regno_for_savres (sel
);
22925 end_save
= info
->gp_save_offset
+ info
->gp_size
;
22927 else if (!restoring_FPRs_inline
)
22929 bool lr
= !(strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
);
22930 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
22931 newptr_regno
= ptr_regno_for_savres (sel
);
22932 end_save
= info
->gp_save_offset
+ info
->gp_size
;
22935 if (newptr_regno
!= 1 && REGNO (frame_reg_rtx
) != newptr_regno
)
22936 frame_reg_rtx
= gen_rtx_REG (Pmode
, newptr_regno
);
22938 if (end_save
+ ptr_off
!= 0)
22940 rtx offset
= GEN_INT (end_save
+ ptr_off
);
22942 frame_off
= -end_save
;
22943 emit_insn (gen_add3_insn (frame_reg_rtx
, ptr_reg
, offset
));
22947 frame_off
= ptr_off
;
22948 emit_move_insn (frame_reg_rtx
, ptr_reg
);
22954 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
22955 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
22957 rtx addr
, areg
, mem
, reg
;
22959 areg
= gen_rtx_REG (Pmode
, 0);
22961 (areg
, GEN_INT (info
->altivec_save_offset
22963 + 16 * (i
- info
->first_altivec_reg_save
)));
22965 /* AltiVec addressing mode is [reg+reg]. */
22966 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
22967 mem
= gen_frame_mem (V4SImode
, addr
);
22969 reg
= gen_rtx_REG (V4SImode
, i
);
22970 emit_move_insn (reg
, mem
);
22974 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
22975 if (((strategy
& REST_INLINE_VRS
) == 0
22976 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
22977 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
22979 rtx reg
= gen_rtx_REG (V4SImode
, i
);
22980 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
22984 /* Restore VRSAVE if we have not done so already. */
22985 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
22987 && TARGET_ALTIVEC_VRSAVE
22988 && info
->vrsave_mask
!= 0
22989 && (DEFAULT_ABI
== ABI_V4
22990 || !offset_below_red_zone_p (info
->vrsave_save_offset
)))
22994 reg
= gen_rtx_REG (SImode
, 12);
22995 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
22996 info
->vrsave_save_offset
+ frame_off
));
22998 emit_insn (generate_set_vrsave (reg
, info
, 1));
23001 /* If we exit by an out-of-line restore function on ABI_V4 then that
23002 function will deallocate the stack, so we don't need to worry
23003 about the unwinder restoring cr from an invalid stack frame
23005 exit_func
= (!restoring_FPRs_inline
23006 || (!restoring_GPRs_inline
23007 && info
->first_fp_reg_save
== 64));
23009 /* Get the old lr if we saved it. If we are restoring registers
23010 out-of-line, then the out-of-line routines can do this for us. */
23011 if (restore_lr
&& restoring_GPRs_inline
)
23012 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
23014 /* Get the old cr if we saved it. */
23015 if (info
->cr_save_p
)
23017 unsigned cr_save_regno
= 12;
23019 if (!restoring_GPRs_inline
)
23021 /* Ensure we don't use the register used by the out-of-line
23022 gpr register restore below. */
23023 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
23024 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
23025 int gpr_ptr_regno
= ptr_regno_for_savres (sel
);
23027 if (gpr_ptr_regno
== 12)
23028 cr_save_regno
= 11;
23029 gcc_checking_assert (REGNO (frame_reg_rtx
) != cr_save_regno
);
23031 else if (REGNO (frame_reg_rtx
) == 12)
23032 cr_save_regno
= 11;
23034 cr_save_reg
= load_cr_save (cr_save_regno
, frame_reg_rtx
,
23035 info
->cr_save_offset
+ frame_off
,
23039 /* Set LR here to try to overlap restores below. */
23040 if (restore_lr
&& restoring_GPRs_inline
)
23041 restore_saved_lr (0, exit_func
);
23043 /* Load exception handler data registers, if needed. */
23044 if (crtl
->calls_eh_return
)
23046 unsigned int i
, regno
;
23050 rtx reg
= gen_rtx_REG (reg_mode
, 2);
23051 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
23052 frame_off
+ 5 * reg_size
));
23059 regno
= EH_RETURN_DATA_REGNO (i
);
23060 if (regno
== INVALID_REGNUM
)
23063 /* Note: possible use of r0 here to address SPE regs. */
23064 mem
= gen_frame_mem_offset (reg_mode
, frame_reg_rtx
,
23065 info
->ehrd_offset
+ frame_off
23066 + reg_size
* (int) i
);
23068 emit_move_insn (gen_rtx_REG (reg_mode
, regno
), mem
);
23072 /* Restore GPRs. This is done as a PARALLEL if we are using
23073 the load-multiple instructions. */
23075 && info
->spe_64bit_regs_used
23076 && info
->first_gp_reg_save
!= 32)
23078 /* Determine whether we can address all of the registers that need
23079 to be saved with an offset from frame_reg_rtx that fits in
23080 the small const field for SPE memory instructions. */
23081 int spe_regs_addressable
23082 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ frame_off
23083 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
23084 && restoring_GPRs_inline
);
23086 if (!spe_regs_addressable
)
23088 int ool_adjust
= 0;
23089 rtx old_frame_reg_rtx
= frame_reg_rtx
;
23090 /* Make r11 point to the start of the SPE save area. We worried about
23091 not clobbering it when we were saving registers in the prologue.
23092 There's no need to worry here because the static chain is passed
23093 anew to every function. */
23095 if (!restoring_GPRs_inline
)
23096 ool_adjust
= 8 * (info
->first_gp_reg_save
- FIRST_SAVED_GP_REGNO
);
23097 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
23098 emit_insn (gen_addsi3 (frame_reg_rtx
, old_frame_reg_rtx
,
23099 GEN_INT (info
->spe_gp_save_offset
23102 /* Keep the invariant that frame_reg_rtx + frame_off points
23103 at the top of the stack frame. */
23104 frame_off
= -info
->spe_gp_save_offset
+ ool_adjust
;
23107 if (restoring_GPRs_inline
)
23109 HOST_WIDE_INT spe_offset
= info
->spe_gp_save_offset
+ frame_off
;
23111 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
23112 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
23114 rtx offset
, addr
, mem
, reg
;
23116 /* We're doing all this to ensure that the immediate offset
23117 fits into the immediate field of 'evldd'. */
23118 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset
+ reg_size
* i
));
23120 offset
= GEN_INT (spe_offset
+ reg_size
* i
);
23121 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, offset
);
23122 mem
= gen_rtx_MEM (V2SImode
, addr
);
23123 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
23125 emit_move_insn (reg
, mem
);
23129 rs6000_emit_savres_rtx (info
, frame_reg_rtx
,
23130 info
->spe_gp_save_offset
+ frame_off
,
23131 info
->lr_save_offset
+ frame_off
,
23133 SAVRES_GPR
| SAVRES_LR
);
23135 else if (!restoring_GPRs_inline
)
23137 /* We are jumping to an out-of-line function. */
23139 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
23140 bool can_use_exit
= end_save
== 0;
23141 int sel
= SAVRES_GPR
| (can_use_exit
? SAVRES_LR
: 0);
23144 /* Emit stack reset code if we need it. */
23145 ptr_regno
= ptr_regno_for_savres (sel
);
23146 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
23148 rs6000_emit_stack_reset (info
, frame_reg_rtx
, frame_off
, ptr_regno
);
23149 else if (end_save
+ frame_off
!= 0)
23150 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
,
23151 GEN_INT (end_save
+ frame_off
)));
23152 else if (REGNO (frame_reg_rtx
) != ptr_regno
)
23153 emit_move_insn (ptr_reg
, frame_reg_rtx
);
23154 if (REGNO (frame_reg_rtx
) == ptr_regno
)
23155 frame_off
= -end_save
;
23157 if (can_use_exit
&& info
->cr_save_p
)
23158 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, true);
23160 ptr_off
= -end_save
;
23161 rs6000_emit_savres_rtx (info
, ptr_reg
,
23162 info
->gp_save_offset
+ ptr_off
,
23163 info
->lr_save_offset
+ ptr_off
,
23166 else if (using_load_multiple
)
23169 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
23170 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
23172 = gen_frame_load (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
23174 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
23175 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
23179 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
23180 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
23181 emit_insn (gen_frame_load
23182 (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
23184 info
->gp_save_offset
+ frame_off
+ reg_size
* i
));
23187 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
23189 /* If the frame pointer was used then we can't delay emitting
23190 a REG_CFA_DEF_CFA note. This must happen on the insn that
23191 restores the frame pointer, r31. We may have already emitted
23192 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
23193 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
23194 be harmless if emitted. */
23195 if (frame_pointer_needed
)
23197 insn
= get_last_insn ();
23198 add_reg_note (insn
, REG_CFA_DEF_CFA
,
23199 plus_constant (Pmode
, frame_reg_rtx
, frame_off
));
23200 RTX_FRAME_RELATED_P (insn
) = 1;
23203 /* Set up cfa_restores. We always need these when
23204 shrink-wrapping. If not shrink-wrapping then we only need
23205 the cfa_restore when the stack location is no longer valid.
23206 The cfa_restores must be emitted on or before the insn that
23207 invalidates the stack, and of course must not be emitted
23208 before the insn that actually does the restore. The latter
23209 is why it is a bad idea to emit the cfa_restores as a group
23210 on the last instruction here that actually does a restore:
23211 That insn may be reordered with respect to others doing
23213 if (flag_shrink_wrap
23214 && !restoring_GPRs_inline
23215 && info
->first_fp_reg_save
== 64)
23216 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
23218 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
23219 if (!restoring_GPRs_inline
23220 || using_load_multiple
23221 || rs6000_reg_live_or_pic_offset_p (i
))
23223 rtx reg
= gen_rtx_REG (reg_mode
, i
);
23225 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
23229 if (!restoring_GPRs_inline
23230 && info
->first_fp_reg_save
== 64)
23232 /* We are jumping to an out-of-line function. */
23234 emit_cfa_restores (cfa_restores
);
23238 if (restore_lr
&& !restoring_GPRs_inline
)
23240 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
23241 restore_saved_lr (0, exit_func
);
23244 /* Restore fpr's if we need to do it without calling a function. */
23245 if (restoring_FPRs_inline
)
23246 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
23247 if (save_reg_p (info
->first_fp_reg_save
+ i
))
23249 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
23250 ? DFmode
: SFmode
),
23251 info
->first_fp_reg_save
+ i
);
23252 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
23253 info
->fp_save_offset
+ frame_off
+ 8 * i
));
23254 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
23255 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
23258 /* If we saved cr, restore it here. Just those that were used. */
23259 if (info
->cr_save_p
)
23260 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, exit_func
);
23262 /* If this is V.4, unwind the stack pointer after all of the loads
23263 have been done, or set up r11 if we are restoring fp out of line. */
23265 if (!restoring_FPRs_inline
)
23267 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
23268 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
23269 ptr_regno
= ptr_regno_for_savres (sel
);
23272 insn
= rs6000_emit_stack_reset (info
, frame_reg_rtx
, frame_off
, ptr_regno
);
23273 if (REGNO (frame_reg_rtx
) == ptr_regno
)
23276 if (insn
&& restoring_FPRs_inline
)
23280 REG_NOTES (insn
) = cfa_restores
;
23281 cfa_restores
= NULL_RTX
;
23283 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
23284 RTX_FRAME_RELATED_P (insn
) = 1;
23287 if (crtl
->calls_eh_return
)
23289 rtx sa
= EH_RETURN_STACKADJ_RTX
;
23290 emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
, sa
));
23296 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
23297 if (! restoring_FPRs_inline
)
23299 p
= rtvec_alloc (4 + 64 - info
->first_fp_reg_save
);
23300 RTVEC_ELT (p
, 0) = ret_rtx
;
23306 /* We can't hang the cfa_restores off a simple return,
23307 since the shrink-wrap code sometimes uses an existing
23308 return. This means there might be a path from
23309 pre-prologue code to this return, and dwarf2cfi code
23310 wants the eh_frame unwinder state to be the same on
23311 all paths to any point. So we need to emit the
23312 cfa_restores before the return. For -m64 we really
23313 don't need epilogue cfa_restores at all, except for
23314 this irritating dwarf2cfi with shrink-wrap
23315 requirement; The stack red-zone means eh_frame info
23316 from the prologue telling the unwinder to restore
23317 from the stack is perfectly good right to the end of
23319 emit_insn (gen_blockage ());
23320 emit_cfa_restores (cfa_restores
);
23321 cfa_restores
= NULL_RTX
;
23323 p
= rtvec_alloc (2);
23324 RTVEC_ELT (p
, 0) = simple_return_rtx
;
23327 RTVEC_ELT (p
, 1) = ((restoring_FPRs_inline
|| !lr
)
23328 ? gen_rtx_USE (VOIDmode
,
23329 gen_rtx_REG (Pmode
, LR_REGNO
))
23330 : gen_rtx_CLOBBER (VOIDmode
,
23331 gen_rtx_REG (Pmode
, LR_REGNO
)));
23333 /* If we have to restore more than two FP registers, branch to the
23334 restore function. It will return to our caller. */
23335 if (! restoring_FPRs_inline
)
23340 if (flag_shrink_wrap
)
23341 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
23343 sym
= rs6000_savres_routine_sym (info
,
23344 SAVRES_FPR
| (lr
? SAVRES_LR
: 0));
23345 RTVEC_ELT (p
, 2) = gen_rtx_USE (VOIDmode
, sym
);
23346 RTVEC_ELT (p
, 3) = gen_rtx_USE (VOIDmode
,
23347 gen_rtx_REG (Pmode
,
23348 DEFAULT_ABI
== ABI_AIX
23350 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
23352 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
23354 RTVEC_ELT (p
, i
+ 4)
23355 = gen_frame_load (reg
, sp_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
23356 if (flag_shrink_wrap
)
23357 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
23362 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
23368 /* Ensure the cfa_restores are hung off an insn that won't
23369 be reordered above other restores. */
23370 emit_insn (gen_blockage ());
23372 emit_cfa_restores (cfa_restores
);
23376 /* Write function epilogue. */
23379 rs6000_output_function_epilogue (FILE *file
,
23380 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
23383 macho_branch_islands ();
23384 /* Mach-O doesn't support labels at the end of objects, so if
23385 it looks like we might want one, insert a NOP. */
23387 rtx insn
= get_last_insn ();
23388 rtx deleted_debug_label
= NULL_RTX
;
23391 && NOTE_KIND (insn
) != NOTE_INSN_DELETED_LABEL
)
23393 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
23394 notes only, instead set their CODE_LABEL_NUMBER to -1,
23395 otherwise there would be code generation differences
23396 in between -g and -g0. */
23397 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
23398 deleted_debug_label
= insn
;
23399 insn
= PREV_INSN (insn
);
23404 && NOTE_KIND (insn
) == NOTE_INSN_DELETED_LABEL
)))
23405 fputs ("\tnop\n", file
);
23406 else if (deleted_debug_label
)
23407 for (insn
= deleted_debug_label
; insn
; insn
= NEXT_INSN (insn
))
23408 if (NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
23409 CODE_LABEL_NUMBER (insn
) = -1;
23413 /* Output a traceback table here. See /usr/include/sys/debug.h for info
23416 We don't output a traceback table if -finhibit-size-directive was
23417 used. The documentation for -finhibit-size-directive reads
23418 ``don't output a @code{.size} assembler directive, or anything
23419 else that would cause trouble if the function is split in the
23420 middle, and the two halves are placed at locations far apart in
23421 memory.'' The traceback table has this property, since it
23422 includes the offset from the start of the function to the
23423 traceback table itself.
23425 System V.4 Powerpc's (and the embedded ABI derived from it) use a
23426 different traceback table. */
23427 if (DEFAULT_ABI
== ABI_AIX
&& ! flag_inhibit_size_directive
23428 && rs6000_traceback
!= traceback_none
&& !cfun
->is_thunk
)
23430 const char *fname
= NULL
;
23431 const char *language_string
= lang_hooks
.name
;
23432 int fixed_parms
= 0, float_parms
= 0, parm_info
= 0;
23434 int optional_tbtab
;
23435 rs6000_stack_t
*info
= rs6000_stack_info ();
23437 if (rs6000_traceback
== traceback_full
)
23438 optional_tbtab
= 1;
23439 else if (rs6000_traceback
== traceback_part
)
23440 optional_tbtab
= 0;
23442 optional_tbtab
= !optimize_size
&& !TARGET_ELF
;
23444 if (optional_tbtab
)
23446 fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
23447 while (*fname
== '.') /* V.4 encodes . in the name */
23450 /* Need label immediately before tbtab, so we can compute
23451 its offset from the function start. */
23452 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
23453 ASM_OUTPUT_LABEL (file
, fname
);
23456 /* The .tbtab pseudo-op can only be used for the first eight
23457 expressions, since it can't handle the possibly variable
23458 length fields that follow. However, if you omit the optional
23459 fields, the assembler outputs zeros for all optional fields
23460 anyways, giving each variable length field is minimum length
23461 (as defined in sys/debug.h). Thus we can not use the .tbtab
23462 pseudo-op at all. */
23464 /* An all-zero word flags the start of the tbtab, for debuggers
23465 that have to find it by searching forward from the entry
23466 point or from the current pc. */
23467 fputs ("\t.long 0\n", file
);
23469 /* Tbtab format type. Use format type 0. */
23470 fputs ("\t.byte 0,", file
);
23472 /* Language type. Unfortunately, there does not seem to be any
23473 official way to discover the language being compiled, so we
23474 use language_string.
23475 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
23476 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
23477 a number, so for now use 9. LTO and Go aren't assigned numbers
23478 either, so for now use 0. */
23479 if (! strcmp (language_string
, "GNU C")
23480 || ! strcmp (language_string
, "GNU GIMPLE")
23481 || ! strcmp (language_string
, "GNU Go"))
23483 else if (! strcmp (language_string
, "GNU F77")
23484 || ! strcmp (language_string
, "GNU Fortran"))
23486 else if (! strcmp (language_string
, "GNU Pascal"))
23488 else if (! strcmp (language_string
, "GNU Ada"))
23490 else if (! strcmp (language_string
, "GNU C++")
23491 || ! strcmp (language_string
, "GNU Objective-C++"))
23493 else if (! strcmp (language_string
, "GNU Java"))
23495 else if (! strcmp (language_string
, "GNU Objective-C"))
23498 gcc_unreachable ();
23499 fprintf (file
, "%d,", i
);
23501 /* 8 single bit fields: global linkage (not set for C extern linkage,
23502 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
23503 from start of procedure stored in tbtab, internal function, function
23504 has controlled storage, function has no toc, function uses fp,
23505 function logs/aborts fp operations. */
23506 /* Assume that fp operations are used if any fp reg must be saved. */
23507 fprintf (file
, "%d,",
23508 (optional_tbtab
<< 5) | ((info
->first_fp_reg_save
!= 64) << 1));
23510 /* 6 bitfields: function is interrupt handler, name present in
23511 proc table, function calls alloca, on condition directives
23512 (controls stack walks, 3 bits), saves condition reg, saves
23514 /* The `function calls alloca' bit seems to be set whenever reg 31 is
23515 set up as a frame pointer, even when there is no alloca call. */
23516 fprintf (file
, "%d,",
23517 ((optional_tbtab
<< 6)
23518 | ((optional_tbtab
& frame_pointer_needed
) << 5)
23519 | (info
->cr_save_p
<< 1)
23520 | (info
->lr_save_p
)));
23522 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
23524 fprintf (file
, "%d,",
23525 (info
->push_p
<< 7) | (64 - info
->first_fp_reg_save
));
23527 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
23528 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
23530 if (optional_tbtab
)
23532 /* Compute the parameter info from the function decl argument
23535 int next_parm_info_bit
= 31;
23537 for (decl
= DECL_ARGUMENTS (current_function_decl
);
23538 decl
; decl
= DECL_CHAIN (decl
))
23540 rtx parameter
= DECL_INCOMING_RTL (decl
);
23541 enum machine_mode mode
= GET_MODE (parameter
);
23543 if (GET_CODE (parameter
) == REG
)
23545 if (SCALAR_FLOAT_MODE_P (mode
))
23566 gcc_unreachable ();
23569 /* If only one bit will fit, don't or in this entry. */
23570 if (next_parm_info_bit
> 0)
23571 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
23572 next_parm_info_bit
-= 2;
23576 fixed_parms
+= ((GET_MODE_SIZE (mode
)
23577 + (UNITS_PER_WORD
- 1))
23579 next_parm_info_bit
-= 1;
23585 /* Number of fixed point parameters. */
23586 /* This is actually the number of words of fixed point parameters; thus
23587 an 8 byte struct counts as 2; and thus the maximum value is 8. */
23588 fprintf (file
, "%d,", fixed_parms
);
23590 /* 2 bitfields: number of floating point parameters (7 bits), parameters
23592 /* This is actually the number of fp registers that hold parameters;
23593 and thus the maximum value is 13. */
23594 /* Set parameters on stack bit if parameters are not in their original
23595 registers, regardless of whether they are on the stack? Xlc
23596 seems to set the bit when not optimizing. */
23597 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
23599 if (! optional_tbtab
)
23602 /* Optional fields follow. Some are variable length. */
23604 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
23605 11 double float. */
23606 /* There is an entry for each parameter in a register, in the order that
23607 they occur in the parameter list. Any intervening arguments on the
23608 stack are ignored. If the list overflows a long (max possible length
23609 34 bits) then completely leave off all elements that don't fit. */
23610 /* Only emit this long if there was at least one parameter. */
23611 if (fixed_parms
|| float_parms
)
23612 fprintf (file
, "\t.long %d\n", parm_info
);
23614 /* Offset from start of code to tb table. */
23615 fputs ("\t.long ", file
);
23616 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
23617 RS6000_OUTPUT_BASENAME (file
, fname
);
23619 rs6000_output_function_entry (file
, fname
);
23622 /* Interrupt handler mask. */
23623 /* Omit this long, since we never set the interrupt handler bit
23626 /* Number of CTL (controlled storage) anchors. */
23627 /* Omit this long, since the has_ctl bit is never set above. */
23629 /* Displacement into stack of each CTL anchor. */
23630 /* Omit this list of longs, because there are no CTL anchors. */
23632 /* Length of function name. */
23635 fprintf (file
, "\t.short %d\n", (int) strlen (fname
));
23637 /* Function name. */
23638 assemble_string (fname
, strlen (fname
));
23640 /* Register for alloca automatic storage; this is always reg 31.
23641 Only emit this if the alloca bit was set above. */
23642 if (frame_pointer_needed
)
23643 fputs ("\t.byte 31\n", file
);
23645 fputs ("\t.align 2\n", file
);
23649 /* A C compound statement that outputs the assembler code for a thunk
23650 function, used to implement C++ virtual function calls with
23651 multiple inheritance. The thunk acts as a wrapper around a virtual
23652 function, adjusting the implicit object parameter before handing
23653 control off to the real function.
23655 First, emit code to add the integer DELTA to the location that
23656 contains the incoming first argument. Assume that this argument
23657 contains a pointer, and is the one used to pass the `this' pointer
23658 in C++. This is the incoming argument *before* the function
23659 prologue, e.g. `%o0' on a sparc. The addition must preserve the
23660 values of all other incoming arguments.
23662 After the addition, emit code to jump to FUNCTION, which is a
23663 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
23664 not touch the return address. Hence returning from FUNCTION will
23665 return to whoever called the current `thunk'.
23667 The effect must be as if FUNCTION had been called directly with the
23668 adjusted first argument. This macro is responsible for emitting
23669 all of the code for a thunk function; output_function_prologue()
23670 and output_function_epilogue() are not invoked.
23672 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
23673 been extracted from it.) It might possibly be useful on some
23674 targets, but probably not.
23676 If you do not define this macro, the target-independent code in the
23677 C++ frontend will generate a less efficient heavyweight thunk that
23678 calls FUNCTION instead of jumping to it. The generic approach does
23679 not support varargs. */
23682 rs6000_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
23683 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
23686 rtx this_rtx
, insn
, funexp
;
23688 reload_completed
= 1;
23689 epilogue_completed
= 1;
23691 /* Mark the end of the (empty) prologue. */
23692 emit_note (NOTE_INSN_PROLOGUE_END
);
23694 /* Find the "this" pointer. If the function returns a structure,
23695 the structure return pointer is in r3. */
23696 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
23697 this_rtx
= gen_rtx_REG (Pmode
, 4);
23699 this_rtx
= gen_rtx_REG (Pmode
, 3);
23701 /* Apply the constant offset, if required. */
23703 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, GEN_INT (delta
)));
23705 /* Apply the offset from the vtable, if required. */
23708 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
23709 rtx tmp
= gen_rtx_REG (Pmode
, 12);
23711 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this_rtx
));
23712 if (((unsigned HOST_WIDE_INT
) vcall_offset
) + 0x8000 >= 0x10000)
23714 emit_insn (gen_add3_insn (tmp
, tmp
, vcall_offset_rtx
));
23715 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
23719 rtx loc
= gen_rtx_PLUS (Pmode
, tmp
, vcall_offset_rtx
);
23721 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, loc
));
23723 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, tmp
));
23726 /* Generate a tail call to the target function. */
23727 if (!TREE_USED (function
))
23729 assemble_external (function
);
23730 TREE_USED (function
) = 1;
23732 funexp
= XEXP (DECL_RTL (function
), 0);
23733 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
23736 if (MACHOPIC_INDIRECT
)
23737 funexp
= machopic_indirect_call_target (funexp
);
23740 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
23741 generate sibcall RTL explicitly. */
23742 insn
= emit_call_insn (
23743 gen_rtx_PARALLEL (VOIDmode
,
23745 gen_rtx_CALL (VOIDmode
,
23746 funexp
, const0_rtx
),
23747 gen_rtx_USE (VOIDmode
, const0_rtx
),
23748 gen_rtx_USE (VOIDmode
,
23749 gen_rtx_REG (SImode
,
23751 simple_return_rtx
)));
23752 SIBLING_CALL_P (insn
) = 1;
23755 /* Run just enough of rest_of_compilation to get the insns emitted.
23756 There's not really enough bulk here to make other passes such as
23757 instruction scheduling worth while. Note that use_thunk calls
23758 assemble_start_function and assemble_end_function. */
23759 insn
= get_insns ();
23760 shorten_branches (insn
);
23761 final_start_function (insn
, file
, 1);
23762 final (insn
, file
, 1);
23763 final_end_function ();
23765 reload_completed
= 0;
23766 epilogue_completed
= 0;
23769 /* A quick summary of the various types of 'constant-pool tables'
23772 Target Flags Name One table per
23773 AIX (none) AIX TOC object file
23774 AIX -mfull-toc AIX TOC object file
23775 AIX -mminimal-toc AIX minimal TOC translation unit
23776 SVR4/EABI (none) SVR4 SDATA object file
23777 SVR4/EABI -fpic SVR4 pic object file
23778 SVR4/EABI -fPIC SVR4 PIC translation unit
23779 SVR4/EABI -mrelocatable EABI TOC function
23780 SVR4/EABI -maix AIX TOC object file
23781 SVR4/EABI -maix -mminimal-toc
23782 AIX minimal TOC translation unit
23784 Name Reg. Set by entries contains:
23785 made by addrs? fp? sum?
23787 AIX TOC 2 crt0 as Y option option
23788 AIX minimal TOC 30 prolog gcc Y Y option
23789 SVR4 SDATA 13 crt0 gcc N Y N
23790 SVR4 pic 30 prolog ld Y not yet N
23791 SVR4 PIC 30 prolog gcc Y option option
23792 EABI TOC 30 prolog gcc Y option option
23796 /* Hash functions for the hash table. */
23799 rs6000_hash_constant (rtx k
)
23801 enum rtx_code code
= GET_CODE (k
);
23802 enum machine_mode mode
= GET_MODE (k
);
23803 unsigned result
= (code
<< 3) ^ mode
;
23804 const char *format
;
23807 format
= GET_RTX_FORMAT (code
);
23808 flen
= strlen (format
);
23814 return result
* 1231 + (unsigned) INSN_UID (XEXP (k
, 0));
23816 case CONST_WIDE_INT
:
23819 flen
= CONST_WIDE_INT_NUNITS (k
);
23820 for (i
= 0; i
< flen
; i
++)
23821 result
= result
* 613 + CONST_WIDE_INT_ELT (k
, i
);
23826 if (mode
!= VOIDmode
)
23827 return real_hash (CONST_DOUBLE_REAL_VALUE (k
)) * result
;
23839 for (; fidx
< flen
; fidx
++)
23840 switch (format
[fidx
])
23845 const char *str
= XSTR (k
, fidx
);
23846 len
= strlen (str
);
23847 result
= result
* 613 + len
;
23848 for (i
= 0; i
< len
; i
++)
23849 result
= result
* 613 + (unsigned) str
[i
];
23854 result
= result
* 1231 + rs6000_hash_constant (XEXP (k
, fidx
));
23858 result
= result
* 613 + (unsigned) XINT (k
, fidx
);
23861 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT
))
23862 result
= result
* 613 + (unsigned) XWINT (k
, fidx
);
23866 for (i
= 0; i
< sizeof (HOST_WIDE_INT
) / sizeof (unsigned); i
++)
23867 result
= result
* 613 + (unsigned) (XWINT (k
, fidx
)
23874 gcc_unreachable ();
23881 toc_hash_function (const void *hash_entry
)
23883 const struct toc_hash_struct
*thc
=
23884 (const struct toc_hash_struct
*) hash_entry
;
23885 return rs6000_hash_constant (thc
->key
) ^ thc
->key_mode
;
23888 /* Compare H1 and H2 for equivalence. */
23891 toc_hash_eq (const void *h1
, const void *h2
)
23893 rtx r1
= ((const struct toc_hash_struct
*) h1
)->key
;
23894 rtx r2
= ((const struct toc_hash_struct
*) h2
)->key
;
23896 if (((const struct toc_hash_struct
*) h1
)->key_mode
23897 != ((const struct toc_hash_struct
*) h2
)->key_mode
)
23900 return rtx_equal_p (r1
, r2
);
23903 /* These are the names given by the C++ front-end to vtables, and
23904 vtable-like objects. Ideally, this logic should not be here;
23905 instead, there should be some programmatic way of inquiring as
23906 to whether or not an object is a vtable. */
23908 #define VTABLE_NAME_P(NAME) \
23909 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
23910 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
23911 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
23912 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
23913 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
23915 #ifdef NO_DOLLAR_IN_LABEL
23916 /* Return a GGC-allocated character string translating dollar signs in
23917 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
23920 rs6000_xcoff_strip_dollar (const char *name
)
23926 q
= (const char *) strchr (name
, '$');
23928 if (q
== 0 || q
== name
)
23931 len
= strlen (name
);
23932 strip
= XALLOCAVEC (char, len
+ 1);
23933 strcpy (strip
, name
);
23934 p
= strip
+ (q
- name
);
23938 p
= strchr (p
+ 1, '$');
23941 return ggc_alloc_string (strip
, len
);
23946 rs6000_output_symbol_ref (FILE *file
, rtx x
)
23948 /* Currently C++ toc references to vtables can be emitted before it
23949 is decided whether the vtable is public or private. If this is
23950 the case, then the linker will eventually complain that there is
23951 a reference to an unknown section. Thus, for vtables only,
23952 we emit the TOC reference to reference the symbol and not the
23954 const char *name
= XSTR (x
, 0);
23956 if (VTABLE_NAME_P (name
))
23958 RS6000_OUTPUT_BASENAME (file
, name
);
23961 assemble_name (file
, name
);
23964 /* Output a TOC entry. We derive the entry name from what is being
23968 output_toc (FILE *file
, rtx x
, int labelno
, enum machine_mode mode
)
23971 const char *name
= buf
;
23973 HOST_WIDE_INT offset
= 0;
23975 gcc_assert (!TARGET_NO_TOC
);
23977 /* When the linker won't eliminate them, don't output duplicate
23978 TOC entries (this happens on AIX if there is any kind of TOC,
23979 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
23981 if (TARGET_TOC
&& GET_CODE (x
) != LABEL_REF
)
23983 struct toc_hash_struct
*h
;
23986 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
23987 time because GGC is not initialized at that point. */
23988 if (toc_hash_table
== NULL
)
23989 toc_hash_table
= htab_create_ggc (1021, toc_hash_function
,
23990 toc_hash_eq
, NULL
);
23992 h
= ggc_alloc_toc_hash_struct ();
23994 h
->key_mode
= mode
;
23995 h
->labelno
= labelno
;
23997 found
= htab_find_slot (toc_hash_table
, h
, INSERT
);
23998 if (*found
== NULL
)
24000 else /* This is indeed a duplicate.
24001 Set this label equal to that label. */
24003 fputs ("\t.set ", file
);
24004 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
24005 fprintf (file
, "%d,", labelno
);
24006 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
24007 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
24011 if (TARGET_XCOFF
&& GET_CODE (x
) == SYMBOL_REF
24012 && (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_GLOBAL_DYNAMIC
24013 || SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
))
24015 fputs ("\t.set ", file
);
24016 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
24017 fprintf (file
, "%d,", labelno
);
24018 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
24019 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
24027 /* If we're going to put a double constant in the TOC, make sure it's
24028 aligned properly when strict alignment is on. */
24029 if ((CONST_DOUBLE_P (x
) || CONST_WIDE_INT_P (x
))
24030 && STRICT_ALIGNMENT
24031 && GET_MODE_BITSIZE (mode
) >= 64
24032 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
)) {
24033 ASM_OUTPUT_ALIGN (file
, 3);
24036 (*targetm
.asm_out
.internal_label
) (file
, "LC", labelno
);
24038 /* Handle FP constants specially. Note that if we have a minimal
24039 TOC, things we put here aren't actually in the TOC, so we can allow
24041 if (GET_CODE (x
) == CONST_DOUBLE
&&
24042 (GET_MODE (x
) == TFmode
|| GET_MODE (x
) == TDmode
))
24044 REAL_VALUE_TYPE rv
;
24047 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
24048 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
24049 REAL_VALUE_TO_TARGET_DECIMAL128 (rv
, k
);
24051 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv
, k
);
24055 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24056 fputs (DOUBLE_INT_ASM_OP
, file
);
24058 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
24059 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
24060 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
24061 fprintf (file
, "0x%lx%08lx,0x%lx%08lx\n",
24062 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
24063 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff,
24064 k
[WORDS_BIG_ENDIAN
? 2 : 3] & 0xffffffff,
24065 k
[WORDS_BIG_ENDIAN
? 3 : 2] & 0xffffffff);
24070 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24071 fputs ("\t.long ", file
);
24073 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
24074 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
24075 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
24076 fprintf (file
, "0x%lx,0x%lx,0x%lx,0x%lx\n",
24077 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
24078 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
24082 else if (GET_CODE (x
) == CONST_DOUBLE
&&
24083 (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DDmode
))
24085 REAL_VALUE_TYPE rv
;
24088 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
24090 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
24091 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, k
);
24093 REAL_VALUE_TO_TARGET_DOUBLE (rv
, k
);
24097 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24098 fputs (DOUBLE_INT_ASM_OP
, file
);
24100 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
24101 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
24102 fprintf (file
, "0x%lx%08lx\n",
24103 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
24104 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff);
24109 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24110 fputs ("\t.long ", file
);
24112 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
24113 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
24114 fprintf (file
, "0x%lx,0x%lx\n",
24115 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
24119 else if (GET_CODE (x
) == CONST_DOUBLE
&&
24120 (GET_MODE (x
) == SFmode
|| GET_MODE (x
) == SDmode
))
24122 REAL_VALUE_TYPE rv
;
24125 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
24126 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
24127 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
24129 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
24133 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24134 fputs (DOUBLE_INT_ASM_OP
, file
);
24136 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
24137 if (WORDS_BIG_ENDIAN
)
24138 fprintf (file
, "0x%lx00000000\n", l
& 0xffffffff);
24140 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
24145 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24146 fputs ("\t.long ", file
);
24148 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
24149 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
24153 else if (GET_MODE (x
) == VOIDmode
&& GET_CODE (x
) == CONST_INT
)
24155 unsigned HOST_WIDE_INT low
;
24156 HOST_WIDE_INT high
;
24158 low
= INTVAL (x
) & 0xffffffff;
24159 high
= (HOST_WIDE_INT
) INTVAL (x
) >> 32;
24161 /* TOC entries are always Pmode-sized, so when big-endian
24162 smaller integer constants in the TOC need to be padded.
24163 (This is still a win over putting the constants in
24164 a separate constant pool, because then we'd have
24165 to have both a TOC entry _and_ the actual constant.)
24167 For a 32-bit target, CONST_INT values are loaded and shifted
24168 entirely within `low' and can be stored in one TOC entry. */
24170 /* It would be easy to make this work, but it doesn't now. */
24171 gcc_assert (!TARGET_64BIT
|| POINTER_SIZE
>= GET_MODE_BITSIZE (mode
));
24173 if (WORDS_BIG_ENDIAN
&& POINTER_SIZE
> GET_MODE_BITSIZE (mode
))
24176 low
<<= POINTER_SIZE
- GET_MODE_BITSIZE (mode
);
24177 high
= (HOST_WIDE_INT
) low
>> 32;
24183 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24184 fputs (DOUBLE_INT_ASM_OP
, file
);
24186 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
24187 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
24188 fprintf (file
, "0x%lx%08lx\n",
24189 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
24194 if (POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
24196 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24197 fputs ("\t.long ", file
);
24199 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
24200 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
24201 fprintf (file
, "0x%lx,0x%lx\n",
24202 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
24206 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24207 fputs ("\t.long ", file
);
24209 fprintf (file
, "\t.tc IS_%lx[TC],", (long) low
& 0xffffffff);
24210 fprintf (file
, "0x%lx\n", (long) low
& 0xffffffff);
24216 if (GET_CODE (x
) == CONST
)
24218 gcc_assert (GET_CODE (XEXP (x
, 0)) == PLUS
24219 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
);
24221 base
= XEXP (XEXP (x
, 0), 0);
24222 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
24225 switch (GET_CODE (base
))
24228 name
= XSTR (base
, 0);
24232 ASM_GENERATE_INTERNAL_LABEL (buf
, "L",
24233 CODE_LABEL_NUMBER (XEXP (base
, 0)));
24237 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
24241 gcc_unreachable ();
24244 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24245 fputs (TARGET_32BIT
? "\t.long " : DOUBLE_INT_ASM_OP
, file
);
24248 fputs ("\t.tc ", file
);
24249 RS6000_OUTPUT_BASENAME (file
, name
);
24252 fprintf (file
, ".N" HOST_WIDE_INT_PRINT_UNSIGNED
, - offset
);
24254 fprintf (file
, ".P" HOST_WIDE_INT_PRINT_UNSIGNED
, offset
);
24256 /* Mark large TOC symbols on AIX with [TE] so they are mapped
24257 after other TOC symbols, reducing overflow of small TOC access
24258 to [TC] symbols. */
24259 fputs (TARGET_XCOFF
&& TARGET_CMODEL
!= CMODEL_SMALL
24260 ? "[TE]," : "[TC],", file
);
24263 /* Currently C++ toc references to vtables can be emitted before it
24264 is decided whether the vtable is public or private. If this is
24265 the case, then the linker will eventually complain that there is
24266 a TOC reference to an unknown section. Thus, for vtables only,
24267 we emit the TOC reference to reference the symbol and not the
24269 if (VTABLE_NAME_P (name
))
24271 RS6000_OUTPUT_BASENAME (file
, name
);
24273 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
24274 else if (offset
> 0)
24275 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
24278 output_addr_const (file
, x
);
24281 if (TARGET_XCOFF
&& GET_CODE (base
) == SYMBOL_REF
24282 && SYMBOL_REF_TLS_MODEL (base
) != 0)
24284 if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_LOCAL_EXEC
)
24285 fputs ("@le", file
);
24286 else if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_INITIAL_EXEC
)
24287 fputs ("@ie", file
);
24288 /* Use global-dynamic for local-dynamic. */
24289 else if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_GLOBAL_DYNAMIC
24290 || SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_LOCAL_DYNAMIC
)
24293 (*targetm
.asm_out
.internal_label
) (file
, "LCM", labelno
);
24294 fputs ("\t.tc .", file
);
24295 RS6000_OUTPUT_BASENAME (file
, name
);
24296 fputs ("[TC],", file
);
24297 output_addr_const (file
, x
);
24298 fputs ("@m", file
);
24306 /* Output an assembler pseudo-op to write an ASCII string of N characters
24307 starting at P to FILE.
24309 On the RS/6000, we have to do this using the .byte operation and
24310 write out special characters outside the quoted string.
24311 Also, the assembler is broken; very long strings are truncated,
24312 so we must artificially break them up early. */
24315 output_ascii (FILE *file
, const char *p
, int n
)
24318 int i
, count_string
;
24319 const char *for_string
= "\t.byte \"";
24320 const char *for_decimal
= "\t.byte ";
24321 const char *to_close
= NULL
;
24324 for (i
= 0; i
< n
; i
++)
24327 if (c
>= ' ' && c
< 0177)
24330 fputs (for_string
, file
);
24333 /* Write two quotes to get one. */
24341 for_decimal
= "\"\n\t.byte ";
24345 if (count_string
>= 512)
24347 fputs (to_close
, file
);
24349 for_string
= "\t.byte \"";
24350 for_decimal
= "\t.byte ";
24358 fputs (for_decimal
, file
);
24359 fprintf (file
, "%d", c
);
24361 for_string
= "\n\t.byte \"";
24362 for_decimal
= ", ";
24368 /* Now close the string if we have written one. Then end the line. */
24370 fputs (to_close
, file
);
24373 /* Generate a unique section name for FILENAME for a section type
24374 represented by SECTION_DESC. Output goes into BUF.
24376 SECTION_DESC can be any string, as long as it is different for each
24377 possible section type.
24379 We name the section in the same manner as xlc. The name begins with an
24380 underscore followed by the filename (after stripping any leading directory
24381 names) with the last period replaced by the string SECTION_DESC. If
24382 FILENAME does not contain a period, SECTION_DESC is appended to the end of
24386 rs6000_gen_section_name (char **buf
, const char *filename
,
24387 const char *section_desc
)
24389 const char *q
, *after_last_slash
, *last_period
= 0;
24393 after_last_slash
= filename
;
24394 for (q
= filename
; *q
; q
++)
24397 after_last_slash
= q
+ 1;
24398 else if (*q
== '.')
24402 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
24403 *buf
= (char *) xmalloc (len
);
24408 for (q
= after_last_slash
; *q
; q
++)
24410 if (q
== last_period
)
24412 strcpy (p
, section_desc
);
24413 p
+= strlen (section_desc
);
24417 else if (ISALNUM (*q
))
24421 if (last_period
== 0)
24422 strcpy (p
, section_desc
);
24427 /* Emit profile function. */
24430 output_profile_hook (int labelno ATTRIBUTE_UNUSED
)
24432 /* Non-standard profiling for kernels, which just saves LR then calls
24433 _mcount without worrying about arg saves. The idea is to change
24434 the function prologue as little as possible as it isn't easy to
24435 account for arg save/restore code added just for _mcount. */
24436 if (TARGET_PROFILE_KERNEL
)
24439 if (DEFAULT_ABI
== ABI_AIX
)
24441 #ifndef NO_PROFILE_COUNTERS
24442 # define NO_PROFILE_COUNTERS 0
24444 if (NO_PROFILE_COUNTERS
)
24445 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
24446 LCT_NORMAL
, VOIDmode
, 0);
24450 const char *label_name
;
24453 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
24454 label_name
= ggc_strdup ((*targetm
.strip_name_encoding
) (buf
));
24455 fun
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
24457 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
24458 LCT_NORMAL
, VOIDmode
, 1, fun
, Pmode
);
24461 else if (DEFAULT_ABI
== ABI_DARWIN
)
24463 const char *mcount_name
= RS6000_MCOUNT
;
24464 int caller_addr_regno
= LR_REGNO
;
24466 /* Be conservative and always set this, at least for now. */
24467 crtl
->uses_pic_offset_table
= 1;
24470 /* For PIC code, set up a stub and collect the caller's address
24471 from r0, which is where the prologue puts it. */
24472 if (MACHOPIC_INDIRECT
24473 && crtl
->uses_pic_offset_table
)
24474 caller_addr_regno
= 0;
24476 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, mcount_name
),
24477 LCT_NORMAL
, VOIDmode
, 1,
24478 gen_rtx_REG (Pmode
, caller_addr_regno
), Pmode
);
24482 /* Write function profiler code. */
24485 output_function_profiler (FILE *file
, int labelno
)
24489 switch (DEFAULT_ABI
)
24492 gcc_unreachable ();
24497 warning (0, "no profiling of 64-bit code for this ABI");
24500 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
24501 fprintf (file
, "\tmflr %s\n", reg_names
[0]);
24502 if (NO_PROFILE_COUNTERS
)
24504 asm_fprintf (file
, "\tstw %s,4(%s)\n",
24505 reg_names
[0], reg_names
[1]);
24507 else if (TARGET_SECURE_PLT
&& flag_pic
)
24509 if (TARGET_LINK_STACK
)
24512 get_ppc476_thunk_name (name
);
24513 asm_fprintf (file
, "\tbl %s\n", name
);
24516 asm_fprintf (file
, "\tbcl 20,31,1f\n1:\n");
24517 asm_fprintf (file
, "\tstw %s,4(%s)\n",
24518 reg_names
[0], reg_names
[1]);
24519 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
24520 asm_fprintf (file
, "\taddis %s,%s,",
24521 reg_names
[12], reg_names
[12]);
24522 assemble_name (file
, buf
);
24523 asm_fprintf (file
, "-1b@ha\n\tla %s,", reg_names
[0]);
24524 assemble_name (file
, buf
);
24525 asm_fprintf (file
, "-1b@l(%s)\n", reg_names
[12]);
24527 else if (flag_pic
== 1)
24529 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file
);
24530 asm_fprintf (file
, "\tstw %s,4(%s)\n",
24531 reg_names
[0], reg_names
[1]);
24532 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
24533 asm_fprintf (file
, "\tlwz %s,", reg_names
[0]);
24534 assemble_name (file
, buf
);
24535 asm_fprintf (file
, "@got(%s)\n", reg_names
[12]);
24537 else if (flag_pic
> 1)
24539 asm_fprintf (file
, "\tstw %s,4(%s)\n",
24540 reg_names
[0], reg_names
[1]);
24541 /* Now, we need to get the address of the label. */
24542 if (TARGET_LINK_STACK
)
24545 get_ppc476_thunk_name (name
);
24546 asm_fprintf (file
, "\tbl %s\n\tb 1f\n\t.long ", name
);
24547 assemble_name (file
, buf
);
24548 fputs ("-.\n1:", file
);
24549 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
24550 asm_fprintf (file
, "\taddi %s,%s,4\n",
24551 reg_names
[11], reg_names
[11]);
24555 fputs ("\tbcl 20,31,1f\n\t.long ", file
);
24556 assemble_name (file
, buf
);
24557 fputs ("-.\n1:", file
);
24558 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
24560 asm_fprintf (file
, "\tlwz %s,0(%s)\n",
24561 reg_names
[0], reg_names
[11]);
24562 asm_fprintf (file
, "\tadd %s,%s,%s\n",
24563 reg_names
[0], reg_names
[0], reg_names
[11]);
24567 asm_fprintf (file
, "\tlis %s,", reg_names
[12]);
24568 assemble_name (file
, buf
);
24569 fputs ("@ha\n", file
);
24570 asm_fprintf (file
, "\tstw %s,4(%s)\n",
24571 reg_names
[0], reg_names
[1]);
24572 asm_fprintf (file
, "\tla %s,", reg_names
[0]);
24573 assemble_name (file
, buf
);
24574 asm_fprintf (file
, "@l(%s)\n", reg_names
[12]);
24577 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
24578 fprintf (file
, "\tbl %s%s\n",
24579 RS6000_MCOUNT
, flag_pic
? "@plt" : "");
24584 if (!TARGET_PROFILE_KERNEL
)
24586 /* Don't do anything, done in output_profile_hook (). */
24590 gcc_assert (!TARGET_32BIT
);
24592 asm_fprintf (file
, "\tmflr %s\n", reg_names
[0]);
24593 asm_fprintf (file
, "\tstd %s,16(%s)\n", reg_names
[0], reg_names
[1]);
24595 if (cfun
->static_chain_decl
!= NULL
)
24597 asm_fprintf (file
, "\tstd %s,24(%s)\n",
24598 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
24599 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
24600 asm_fprintf (file
, "\tld %s,24(%s)\n",
24601 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
24604 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
24612 /* The following variable value is the last issued insn. */
24614 static rtx last_scheduled_insn
;
24616 /* The following variable helps to balance issuing of load and
24617 store instructions */
24619 static int load_store_pendulum
;
24621 /* Power4 load update and store update instructions are cracked into a
24622 load or store and an integer insn which are executed in the same cycle.
24623 Branches have their own dispatch slot which does not count against the
24624 GCC issue rate, but it changes the program flow so there are no other
24625 instructions to issue in this cycle. */
24628 rs6000_variable_issue_1 (rtx insn
, int more
)
24630 last_scheduled_insn
= insn
;
24631 if (GET_CODE (PATTERN (insn
)) == USE
24632 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
24634 cached_can_issue_more
= more
;
24635 return cached_can_issue_more
;
24638 if (insn_terminates_group_p (insn
, current_group
))
24640 cached_can_issue_more
= 0;
24641 return cached_can_issue_more
;
24644 /* If no reservation, but reach here */
24645 if (recog_memoized (insn
) < 0)
24648 if (rs6000_sched_groups
)
24650 if (is_microcoded_insn (insn
))
24651 cached_can_issue_more
= 0;
24652 else if (is_cracked_insn (insn
))
24653 cached_can_issue_more
= more
> 2 ? more
- 2 : 0;
24655 cached_can_issue_more
= more
- 1;
24657 return cached_can_issue_more
;
24660 if (rs6000_cpu_attr
== CPU_CELL
&& is_nonpipeline_insn (insn
))
24663 cached_can_issue_more
= more
- 1;
24664 return cached_can_issue_more
;
24668 rs6000_variable_issue (FILE *stream
, int verbose
, rtx insn
, int more
)
24670 int r
= rs6000_variable_issue_1 (insn
, more
);
24672 fprintf (stream
, "// rs6000_variable_issue (more = %d) = %d\n", more
, r
);
24676 /* Adjust the cost of a scheduling dependency. Return the new cost of
24677 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
24680 rs6000_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
24682 enum attr_type attr_type
;
24684 if (! recog_memoized (insn
))
24687 switch (REG_NOTE_KIND (link
))
24691 /* Data dependency; DEP_INSN writes a register that INSN reads
24692 some cycles later. */
24694 /* Separate a load from a narrower, dependent store. */
24695 if (rs6000_sched_groups
24696 && GET_CODE (PATTERN (insn
)) == SET
24697 && GET_CODE (PATTERN (dep_insn
)) == SET
24698 && GET_CODE (XEXP (PATTERN (insn
), 1)) == MEM
24699 && GET_CODE (XEXP (PATTERN (dep_insn
), 0)) == MEM
24700 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn
), 1)))
24701 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn
), 0)))))
24704 attr_type
= get_attr_type (insn
);
24709 /* Tell the first scheduling pass about the latency between
24710 a mtctr and bctr (and mtlr and br/blr). The first
24711 scheduling pass will not know about this latency since
24712 the mtctr instruction, which has the latency associated
24713 to it, will be generated by reload. */
24716 /* Leave some extra cycles between a compare and its
24717 dependent branch, to inhibit expensive mispredicts. */
24718 if ((rs6000_cpu_attr
== CPU_PPC603
24719 || rs6000_cpu_attr
== CPU_PPC604
24720 || rs6000_cpu_attr
== CPU_PPC604E
24721 || rs6000_cpu_attr
== CPU_PPC620
24722 || rs6000_cpu_attr
== CPU_PPC630
24723 || rs6000_cpu_attr
== CPU_PPC750
24724 || rs6000_cpu_attr
== CPU_PPC7400
24725 || rs6000_cpu_attr
== CPU_PPC7450
24726 || rs6000_cpu_attr
== CPU_PPCE5500
24727 || rs6000_cpu_attr
== CPU_PPCE6500
24728 || rs6000_cpu_attr
== CPU_POWER4
24729 || rs6000_cpu_attr
== CPU_POWER5
24730 || rs6000_cpu_attr
== CPU_POWER7
24731 || rs6000_cpu_attr
== CPU_POWER8
24732 || rs6000_cpu_attr
== CPU_CELL
)
24733 && recog_memoized (dep_insn
)
24734 && (INSN_CODE (dep_insn
) >= 0))
24736 switch (get_attr_type (dep_insn
))
24740 case TYPE_DELAYED_COMPARE
:
24741 case TYPE_IMUL_COMPARE
:
24742 case TYPE_LMUL_COMPARE
:
24743 case TYPE_FPCOMPARE
:
24744 case TYPE_CR_LOGICAL
:
24745 case TYPE_DELAYED_CR
:
24754 case TYPE_STORE_UX
:
24756 case TYPE_FPSTORE_U
:
24757 case TYPE_FPSTORE_UX
:
24758 if ((rs6000_cpu
== PROCESSOR_POWER6
)
24759 && recog_memoized (dep_insn
)
24760 && (INSN_CODE (dep_insn
) >= 0))
24763 if (GET_CODE (PATTERN (insn
)) != SET
)
24764 /* If this happens, we have to extend this to schedule
24765 optimally. Return default for now. */
24768 /* Adjust the cost for the case where the value written
24769 by a fixed point operation is used as the address
24770 gen value on a store. */
24771 switch (get_attr_type (dep_insn
))
24778 if (! store_data_bypass_p (dep_insn
, insn
))
24782 case TYPE_LOAD_EXT
:
24783 case TYPE_LOAD_EXT_U
:
24784 case TYPE_LOAD_EXT_UX
:
24785 case TYPE_VAR_SHIFT_ROTATE
:
24786 case TYPE_VAR_DELAYED_COMPARE
:
24788 if (! store_data_bypass_p (dep_insn
, insn
))
24794 case TYPE_FAST_COMPARE
:
24797 case TYPE_INSERT_WORD
:
24798 case TYPE_INSERT_DWORD
:
24799 case TYPE_FPLOAD_U
:
24800 case TYPE_FPLOAD_UX
:
24802 case TYPE_STORE_UX
:
24803 case TYPE_FPSTORE_U
:
24804 case TYPE_FPSTORE_UX
:
24806 if (! store_data_bypass_p (dep_insn
, insn
))
24814 case TYPE_IMUL_COMPARE
:
24815 case TYPE_LMUL_COMPARE
:
24817 if (! store_data_bypass_p (dep_insn
, insn
))
24823 if (! store_data_bypass_p (dep_insn
, insn
))
24829 if (! store_data_bypass_p (dep_insn
, insn
))
24842 case TYPE_LOAD_EXT
:
24843 case TYPE_LOAD_EXT_U
:
24844 case TYPE_LOAD_EXT_UX
:
24845 if ((rs6000_cpu
== PROCESSOR_POWER6
)
24846 && recog_memoized (dep_insn
)
24847 && (INSN_CODE (dep_insn
) >= 0))
24850 /* Adjust the cost for the case where the value written
24851 by a fixed point instruction is used within the address
24852 gen portion of a subsequent load(u)(x) */
24853 switch (get_attr_type (dep_insn
))
24860 if (set_to_load_agen (dep_insn
, insn
))
24864 case TYPE_LOAD_EXT
:
24865 case TYPE_LOAD_EXT_U
:
24866 case TYPE_LOAD_EXT_UX
:
24867 case TYPE_VAR_SHIFT_ROTATE
:
24868 case TYPE_VAR_DELAYED_COMPARE
:
24870 if (set_to_load_agen (dep_insn
, insn
))
24876 case TYPE_FAST_COMPARE
:
24879 case TYPE_INSERT_WORD
:
24880 case TYPE_INSERT_DWORD
:
24881 case TYPE_FPLOAD_U
:
24882 case TYPE_FPLOAD_UX
:
24884 case TYPE_STORE_UX
:
24885 case TYPE_FPSTORE_U
:
24886 case TYPE_FPSTORE_UX
:
24888 if (set_to_load_agen (dep_insn
, insn
))
24896 case TYPE_IMUL_COMPARE
:
24897 case TYPE_LMUL_COMPARE
:
24899 if (set_to_load_agen (dep_insn
, insn
))
24905 if (set_to_load_agen (dep_insn
, insn
))
24911 if (set_to_load_agen (dep_insn
, insn
))
24922 if ((rs6000_cpu
== PROCESSOR_POWER6
)
24923 && recog_memoized (dep_insn
)
24924 && (INSN_CODE (dep_insn
) >= 0)
24925 && (get_attr_type (dep_insn
) == TYPE_MFFGPR
))
24932 /* Fall out to return default cost. */
24936 case REG_DEP_OUTPUT
:
24937 /* Output dependency; DEP_INSN writes a register that INSN writes some
24939 if ((rs6000_cpu
== PROCESSOR_POWER6
)
24940 && recog_memoized (dep_insn
)
24941 && (INSN_CODE (dep_insn
) >= 0))
24943 attr_type
= get_attr_type (insn
);
24948 if (get_attr_type (dep_insn
) == TYPE_FP
)
24952 if (get_attr_type (dep_insn
) == TYPE_MFFGPR
)
24960 /* Anti dependency; DEP_INSN reads a register that INSN writes some
24965 gcc_unreachable ();
24971 /* Debug version of rs6000_adjust_cost. */
24974 rs6000_debug_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
24976 int ret
= rs6000_adjust_cost (insn
, link
, dep_insn
, cost
);
24982 switch (REG_NOTE_KIND (link
))
24984 default: dep
= "unknown depencency"; break;
24985 case REG_DEP_TRUE
: dep
= "data dependency"; break;
24986 case REG_DEP_OUTPUT
: dep
= "output dependency"; break;
24987 case REG_DEP_ANTI
: dep
= "anti depencency"; break;
24991 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
24992 "%s, insn:\n", ret
, cost
, dep
);
25000 /* The function returns a true if INSN is microcoded.
25001 Return false otherwise. */
25004 is_microcoded_insn (rtx insn
)
25006 if (!insn
|| !NONDEBUG_INSN_P (insn
)
25007 || GET_CODE (PATTERN (insn
)) == USE
25008 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
25011 if (rs6000_cpu_attr
== CPU_CELL
)
25012 return get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
;
25014 if (rs6000_sched_groups
25015 && (rs6000_cpu
== PROCESSOR_POWER4
|| rs6000_cpu
== PROCESSOR_POWER5
))
25017 enum attr_type type
= get_attr_type (insn
);
25018 if (type
== TYPE_LOAD_EXT_U
25019 || type
== TYPE_LOAD_EXT_UX
25020 || type
== TYPE_LOAD_UX
25021 || type
== TYPE_STORE_UX
25022 || type
== TYPE_MFCR
)
25029 /* The function returns true if INSN is cracked into 2 instructions
25030 by the processor (and therefore occupies 2 issue slots). */
25033 is_cracked_insn (rtx insn
)
25035 if (!insn
|| !NONDEBUG_INSN_P (insn
)
25036 || GET_CODE (PATTERN (insn
)) == USE
25037 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
25040 if (rs6000_sched_groups
25041 && (rs6000_cpu
== PROCESSOR_POWER4
|| rs6000_cpu
== PROCESSOR_POWER5
))
25043 enum attr_type type
= get_attr_type (insn
);
25044 if (type
== TYPE_LOAD_U
|| type
== TYPE_STORE_U
25045 || type
== TYPE_FPLOAD_U
|| type
== TYPE_FPSTORE_U
25046 || type
== TYPE_FPLOAD_UX
|| type
== TYPE_FPSTORE_UX
25047 || type
== TYPE_LOAD_EXT
|| type
== TYPE_DELAYED_CR
25048 || type
== TYPE_COMPARE
|| type
== TYPE_DELAYED_COMPARE
25049 || type
== TYPE_IMUL_COMPARE
|| type
== TYPE_LMUL_COMPARE
25050 || type
== TYPE_IDIV
|| type
== TYPE_LDIV
25051 || type
== TYPE_INSERT_WORD
)
25058 /* The function returns true if INSN can be issued only from
25059 the branch slot. */
25062 is_branch_slot_insn (rtx insn
)
25064 if (!insn
|| !NONDEBUG_INSN_P (insn
)
25065 || GET_CODE (PATTERN (insn
)) == USE
25066 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
25069 if (rs6000_sched_groups
)
25071 enum attr_type type
= get_attr_type (insn
);
25072 if (type
== TYPE_BRANCH
|| type
== TYPE_JMPREG
)
25080 /* The function returns true if out_inst sets a value that is
25081 used in the address generation computation of in_insn */
25083 set_to_load_agen (rtx out_insn
, rtx in_insn
)
25085 rtx out_set
, in_set
;
25087 /* For performance reasons, only handle the simple case where
25088 both loads are a single_set. */
25089 out_set
= single_set (out_insn
);
25092 in_set
= single_set (in_insn
);
25094 return reg_mentioned_p (SET_DEST (out_set
), SET_SRC (in_set
));
25100 /* Try to determine base/offset/size parts of the given MEM.
25101 Return true if successful, false if all the values couldn't
25104 This function only looks for REG or REG+CONST address forms.
25105 REG+REG address form will return false. */
25108 get_memref_parts (rtx mem
, rtx
*base
, HOST_WIDE_INT
*offset
,
25109 HOST_WIDE_INT
*size
)
25112 if MEM_SIZE_KNOWN_P (mem
)
25113 *size
= MEM_SIZE (mem
);
25117 if (GET_CODE (XEXP (mem
, 0)) == PRE_MODIFY
)
25118 addr_rtx
= XEXP (XEXP (mem
, 0), 1);
25120 addr_rtx
= (XEXP (mem
, 0));
25122 if (GET_CODE (addr_rtx
) == REG
)
25127 else if (GET_CODE (addr_rtx
) == PLUS
25128 && CONST_INT_P (XEXP (addr_rtx
, 1)))
25130 *base
= XEXP (addr_rtx
, 0);
25131 *offset
= INTVAL (XEXP (addr_rtx
, 1));
25139 /* The function returns true if the target storage location of
25140 mem1 is adjacent to the target storage location of mem2 */
25141 /* Return 1 if memory locations are adjacent. */
25144 adjacent_mem_locations (rtx mem1
, rtx mem2
)
25147 HOST_WIDE_INT off1
, size1
, off2
, size2
;
25149 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
25150 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
25151 return ((REGNO (reg1
) == REGNO (reg2
))
25152 && ((off1
+ size1
== off2
)
25153 || (off2
+ size2
== off1
)));
25158 /* This function returns true if it can be determined that the two MEM
25159 locations overlap by at least 1 byte based on base reg/offset/size. */
25162 mem_locations_overlap (rtx mem1
, rtx mem2
)
25165 HOST_WIDE_INT off1
, size1
, off2
, size2
;
25167 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
25168 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
25169 return ((REGNO (reg1
) == REGNO (reg2
))
25170 && (((off1
<= off2
) && (off1
+ size1
> off2
))
25171 || ((off2
<= off1
) && (off2
+ size2
> off1
))));
25176 /* A C statement (sans semicolon) to update the integer scheduling
25177 priority INSN_PRIORITY (INSN). Increase the priority to execute the
25178 INSN earlier, reduce the priority to execute INSN later. Do not
25179 define this macro if you do not need to adjust the scheduling
25180 priorities of insns. */
25183 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
25185 rtx load_mem
, str_mem
;
25186 /* On machines (like the 750) which have asymmetric integer units,
25187 where one integer unit can do multiply and divides and the other
25188 can't, reduce the priority of multiply/divide so it is scheduled
25189 before other integer operations. */
25192 if (! INSN_P (insn
))
25195 if (GET_CODE (PATTERN (insn
)) == USE
)
25198 switch (rs6000_cpu_attr
) {
25200 switch (get_attr_type (insn
))
25207 fprintf (stderr
, "priority was %#x (%d) before adjustment\n",
25208 priority
, priority
);
25209 if (priority
>= 0 && priority
< 0x01000000)
25216 if (insn_must_be_first_in_group (insn
)
25217 && reload_completed
25218 && current_sched_info
->sched_max_insns_priority
25219 && rs6000_sched_restricted_insns_priority
)
25222 /* Prioritize insns that can be dispatched only in the first
25224 if (rs6000_sched_restricted_insns_priority
== 1)
25225 /* Attach highest priority to insn. This means that in
25226 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
25227 precede 'priority' (critical path) considerations. */
25228 return current_sched_info
->sched_max_insns_priority
;
25229 else if (rs6000_sched_restricted_insns_priority
== 2)
25230 /* Increase priority of insn by a minimal amount. This means that in
25231 haifa-sched.c:ready_sort(), only 'priority' (critical path)
25232 considerations precede dispatch-slot restriction considerations. */
25233 return (priority
+ 1);
25236 if (rs6000_cpu
== PROCESSOR_POWER6
25237 && ((load_store_pendulum
== -2 && is_load_insn (insn
, &load_mem
))
25238 || (load_store_pendulum
== 2 && is_store_insn (insn
, &str_mem
))))
25239 /* Attach highest priority to insn if the scheduler has just issued two
25240 stores and this instruction is a load, or two loads and this instruction
25241 is a store. Power6 wants loads and stores scheduled alternately
25243 return current_sched_info
->sched_max_insns_priority
;
25248 /* Return true if the instruction is nonpipelined on the Cell. */
25250 is_nonpipeline_insn (rtx insn
)
25252 enum attr_type type
;
25253 if (!insn
|| !NONDEBUG_INSN_P (insn
)
25254 || GET_CODE (PATTERN (insn
)) == USE
25255 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
25258 type
= get_attr_type (insn
);
25259 if (type
== TYPE_IMUL
25260 || type
== TYPE_IMUL2
25261 || type
== TYPE_IMUL3
25262 || type
== TYPE_LMUL
25263 || type
== TYPE_IDIV
25264 || type
== TYPE_LDIV
25265 || type
== TYPE_SDIV
25266 || type
== TYPE_DDIV
25267 || type
== TYPE_SSQRT
25268 || type
== TYPE_DSQRT
25269 || type
== TYPE_MFCR
25270 || type
== TYPE_MFCRF
25271 || type
== TYPE_MFJMPR
)
25279 /* Return how many instructions the machine can issue per cycle. */
25282 rs6000_issue_rate (void)
25284 /* Unless scheduling for register pressure, use issue rate of 1 for
25285 first scheduling pass to decrease degradation. */
25286 if (!reload_completed
&& !flag_sched_pressure
)
25289 switch (rs6000_cpu_attr
) {
25291 case CPU_PPC601
: /* ? */
25301 case CPU_PPCE300C2
:
25302 case CPU_PPCE300C3
:
25303 case CPU_PPCE500MC
:
25304 case CPU_PPCE500MC64
:
25327 /* Return how many instructions to look ahead for better insn
25331 rs6000_use_sched_lookahead (void)
25333 switch (rs6000_cpu_attr
)
25340 return (reload_completed
? 8 : 0);
25347 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
25349 rs6000_use_sched_lookahead_guard (rtx insn
)
25351 if (rs6000_cpu_attr
!= CPU_CELL
)
25354 if (insn
== NULL_RTX
|| !INSN_P (insn
))
25357 if (!reload_completed
25358 || is_nonpipeline_insn (insn
)
25359 || is_microcoded_insn (insn
))
25365 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
25366 and return true. */
25369 find_mem_ref (rtx pat
, rtx
*mem_ref
)
25374 /* stack_tie does not produce any real memory traffic. */
25375 if (tie_operand (pat
, VOIDmode
))
25378 if (GET_CODE (pat
) == MEM
)
25384 /* Recursively process the pattern. */
25385 fmt
= GET_RTX_FORMAT (GET_CODE (pat
));
25387 for (i
= GET_RTX_LENGTH (GET_CODE (pat
)) - 1; i
>= 0; i
--)
25391 if (find_mem_ref (XEXP (pat
, i
), mem_ref
))
25394 else if (fmt
[i
] == 'E')
25395 for (j
= XVECLEN (pat
, i
) - 1; j
>= 0; j
--)
25397 if (find_mem_ref (XVECEXP (pat
, i
, j
), mem_ref
))
25405 /* Determine if PAT is a PATTERN of a load insn. */
25408 is_load_insn1 (rtx pat
, rtx
*load_mem
)
25410 if (!pat
|| pat
== NULL_RTX
)
25413 if (GET_CODE (pat
) == SET
)
25414 return find_mem_ref (SET_SRC (pat
), load_mem
);
25416 if (GET_CODE (pat
) == PARALLEL
)
25420 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
25421 if (is_load_insn1 (XVECEXP (pat
, 0, i
), load_mem
))
25428 /* Determine if INSN loads from memory. */
25431 is_load_insn (rtx insn
, rtx
*load_mem
)
25433 if (!insn
|| !INSN_P (insn
))
25439 return is_load_insn1 (PATTERN (insn
), load_mem
);
25442 /* Determine if PAT is a PATTERN of a store insn. */
25445 is_store_insn1 (rtx pat
, rtx
*str_mem
)
25447 if (!pat
|| pat
== NULL_RTX
)
25450 if (GET_CODE (pat
) == SET
)
25451 return find_mem_ref (SET_DEST (pat
), str_mem
);
25453 if (GET_CODE (pat
) == PARALLEL
)
25457 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
25458 if (is_store_insn1 (XVECEXP (pat
, 0, i
), str_mem
))
25465 /* Determine if INSN stores to memory. */
25468 is_store_insn (rtx insn
, rtx
*str_mem
)
25470 if (!insn
|| !INSN_P (insn
))
25473 return is_store_insn1 (PATTERN (insn
), str_mem
);
25476 /* Returns whether the dependence between INSN and NEXT is considered
25477 costly by the given target. */
25480 rs6000_is_costly_dependence (dep_t dep
, int cost
, int distance
)
25484 rtx load_mem
, str_mem
;
25486 /* If the flag is not enabled - no dependence is considered costly;
25487 allow all dependent insns in the same group.
25488 This is the most aggressive option. */
25489 if (rs6000_sched_costly_dep
== no_dep_costly
)
25492 /* If the flag is set to 1 - a dependence is always considered costly;
25493 do not allow dependent instructions in the same group.
25494 This is the most conservative option. */
25495 if (rs6000_sched_costly_dep
== all_deps_costly
)
25498 insn
= DEP_PRO (dep
);
25499 next
= DEP_CON (dep
);
25501 if (rs6000_sched_costly_dep
== store_to_load_dep_costly
25502 && is_load_insn (next
, &load_mem
)
25503 && is_store_insn (insn
, &str_mem
))
25504 /* Prevent load after store in the same group. */
25507 if (rs6000_sched_costly_dep
== true_store_to_load_dep_costly
25508 && is_load_insn (next
, &load_mem
)
25509 && is_store_insn (insn
, &str_mem
)
25510 && DEP_TYPE (dep
) == REG_DEP_TRUE
25511 && mem_locations_overlap(str_mem
, load_mem
))
25512 /* Prevent load after store in the same group if it is a true
25516 /* The flag is set to X; dependences with latency >= X are considered costly,
25517 and will not be scheduled in the same group. */
25518 if (rs6000_sched_costly_dep
<= max_dep_latency
25519 && ((cost
- distance
) >= (int)rs6000_sched_costly_dep
))
25525 /* Return the next insn after INSN that is found before TAIL is reached,
25526 skipping any "non-active" insns - insns that will not actually occupy
25527 an issue slot. Return NULL_RTX if such an insn is not found. */
25530 get_next_active_insn (rtx insn
, rtx tail
)
25532 if (insn
== NULL_RTX
|| insn
== tail
)
25537 insn
= NEXT_INSN (insn
);
25538 if (insn
== NULL_RTX
|| insn
== tail
)
25542 || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
25543 || (NONJUMP_INSN_P (insn
)
25544 && GET_CODE (PATTERN (insn
)) != USE
25545 && GET_CODE (PATTERN (insn
)) != CLOBBER
25546 && INSN_CODE (insn
) != CODE_FOR_stack_tie
))
25552 /* We are about to begin issuing insns for this clock cycle. */
25555 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED
, int sched_verbose
,
25556 rtx
*ready ATTRIBUTE_UNUSED
,
25557 int *pn_ready ATTRIBUTE_UNUSED
,
25558 int clock_var ATTRIBUTE_UNUSED
)
25560 int n_ready
= *pn_ready
;
25563 fprintf (dump
, "// rs6000_sched_reorder :\n");
25565 /* Reorder the ready list, if the second to last ready insn
25566 is a nonepipeline insn. */
25567 if (rs6000_cpu_attr
== CPU_CELL
&& n_ready
> 1)
25569 if (is_nonpipeline_insn (ready
[n_ready
- 1])
25570 && (recog_memoized (ready
[n_ready
- 2]) > 0))
25571 /* Simply swap first two insns. */
25573 rtx tmp
= ready
[n_ready
- 1];
25574 ready
[n_ready
- 1] = ready
[n_ready
- 2];
25575 ready
[n_ready
- 2] = tmp
;
25579 if (rs6000_cpu
== PROCESSOR_POWER6
)
25580 load_store_pendulum
= 0;
25582 return rs6000_issue_rate ();
25585 /* Like rs6000_sched_reorder, but called after issuing each insn. */
25588 rs6000_sched_reorder2 (FILE *dump
, int sched_verbose
, rtx
*ready
,
25589 int *pn_ready
, int clock_var ATTRIBUTE_UNUSED
)
25592 fprintf (dump
, "// rs6000_sched_reorder2 :\n");
25594 /* For Power6, we need to handle some special cases to try and keep the
25595 store queue from overflowing and triggering expensive flushes.
25597 This code monitors how load and store instructions are being issued
25598 and skews the ready list one way or the other to increase the likelihood
25599 that a desired instruction is issued at the proper time.
25601 A couple of things are done. First, we maintain a "load_store_pendulum"
25602 to track the current state of load/store issue.
25604 - If the pendulum is at zero, then no loads or stores have been
25605 issued in the current cycle so we do nothing.
25607 - If the pendulum is 1, then a single load has been issued in this
25608 cycle and we attempt to locate another load in the ready list to
25611 - If the pendulum is -2, then two stores have already been
25612 issued in this cycle, so we increase the priority of the first load
25613 in the ready list to increase it's likelihood of being chosen first
25616 - If the pendulum is -1, then a single store has been issued in this
25617 cycle and we attempt to locate another store in the ready list to
25618 issue with it, preferring a store to an adjacent memory location to
25619 facilitate store pairing in the store queue.
25621 - If the pendulum is 2, then two loads have already been
25622 issued in this cycle, so we increase the priority of the first store
25623 in the ready list to increase it's likelihood of being chosen first
25626 - If the pendulum < -2 or > 2, then do nothing.
25628 Note: This code covers the most common scenarios. There exist non
25629 load/store instructions which make use of the LSU and which
25630 would need to be accounted for to strictly model the behavior
25631 of the machine. Those instructions are currently unaccounted
25632 for to help minimize compile time overhead of this code.
25634 if (rs6000_cpu
== PROCESSOR_POWER6
&& last_scheduled_insn
)
25638 rtx tmp
, load_mem
, str_mem
;
25640 if (is_store_insn (last_scheduled_insn
, &str_mem
))
25641 /* Issuing a store, swing the load_store_pendulum to the left */
25642 load_store_pendulum
--;
25643 else if (is_load_insn (last_scheduled_insn
, &load_mem
))
25644 /* Issuing a load, swing the load_store_pendulum to the right */
25645 load_store_pendulum
++;
25647 return cached_can_issue_more
;
25649 /* If the pendulum is balanced, or there is only one instruction on
25650 the ready list, then all is well, so return. */
25651 if ((load_store_pendulum
== 0) || (*pn_ready
<= 1))
25652 return cached_can_issue_more
;
25654 if (load_store_pendulum
== 1)
25656 /* A load has been issued in this cycle. Scan the ready list
25657 for another load to issue with it */
25662 if (is_load_insn (ready
[pos
], &load_mem
))
25664 /* Found a load. Move it to the head of the ready list,
25665 and adjust it's priority so that it is more likely to
25668 for (i
=pos
; i
<*pn_ready
-1; i
++)
25669 ready
[i
] = ready
[i
+ 1];
25670 ready
[*pn_ready
-1] = tmp
;
25672 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
25673 INSN_PRIORITY (tmp
)++;
25679 else if (load_store_pendulum
== -2)
25681 /* Two stores have been issued in this cycle. Increase the
25682 priority of the first load in the ready list to favor it for
25683 issuing in the next cycle. */
25688 if (is_load_insn (ready
[pos
], &load_mem
)
25690 && INSN_PRIORITY_KNOWN (ready
[pos
]))
25692 INSN_PRIORITY (ready
[pos
])++;
25694 /* Adjust the pendulum to account for the fact that a load
25695 was found and increased in priority. This is to prevent
25696 increasing the priority of multiple loads */
25697 load_store_pendulum
--;
25704 else if (load_store_pendulum
== -1)
25706 /* A store has been issued in this cycle. Scan the ready list for
25707 another store to issue with it, preferring a store to an adjacent
25709 int first_store_pos
= -1;
25715 if (is_store_insn (ready
[pos
], &str_mem
))
25718 /* Maintain the index of the first store found on the
25720 if (first_store_pos
== -1)
25721 first_store_pos
= pos
;
25723 if (is_store_insn (last_scheduled_insn
, &str_mem2
)
25724 && adjacent_mem_locations (str_mem
, str_mem2
))
25726 /* Found an adjacent store. Move it to the head of the
25727 ready list, and adjust it's priority so that it is
25728 more likely to stay there */
25730 for (i
=pos
; i
<*pn_ready
-1; i
++)
25731 ready
[i
] = ready
[i
+ 1];
25732 ready
[*pn_ready
-1] = tmp
;
25734 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
25735 INSN_PRIORITY (tmp
)++;
25737 first_store_pos
= -1;
25745 if (first_store_pos
>= 0)
25747 /* An adjacent store wasn't found, but a non-adjacent store was,
25748 so move the non-adjacent store to the front of the ready
25749 list, and adjust its priority so that it is more likely to
25751 tmp
= ready
[first_store_pos
];
25752 for (i
=first_store_pos
; i
<*pn_ready
-1; i
++)
25753 ready
[i
] = ready
[i
+ 1];
25754 ready
[*pn_ready
-1] = tmp
;
25755 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
25756 INSN_PRIORITY (tmp
)++;
25759 else if (load_store_pendulum
== 2)
25761 /* Two loads have been issued in this cycle. Increase the priority
25762 of the first store in the ready list to favor it for issuing in
25768 if (is_store_insn (ready
[pos
], &str_mem
)
25770 && INSN_PRIORITY_KNOWN (ready
[pos
]))
25772 INSN_PRIORITY (ready
[pos
])++;
25774 /* Adjust the pendulum to account for the fact that a store
25775 was found and increased in priority. This is to prevent
25776 increasing the priority of multiple stores */
25777 load_store_pendulum
++;
25786 return cached_can_issue_more
;
25789 /* Return whether the presence of INSN causes a dispatch group termination
25790 of group WHICH_GROUP.
25792 If WHICH_GROUP == current_group, this function will return true if INSN
25793 causes the termination of the current group (i.e, the dispatch group to
25794 which INSN belongs). This means that INSN will be the last insn in the
25795 group it belongs to.
25797 If WHICH_GROUP == previous_group, this function will return true if INSN
25798 causes the termination of the previous group (i.e, the dispatch group that
25799 precedes the group to which INSN belongs). This means that INSN will be
25800 the first insn in the group it belongs to). */
25803 insn_terminates_group_p (rtx insn
, enum group_termination which_group
)
25810 first
= insn_must_be_first_in_group (insn
);
25811 last
= insn_must_be_last_in_group (insn
);
25816 if (which_group
== current_group
)
25818 else if (which_group
== previous_group
)
25826 insn_must_be_first_in_group (rtx insn
)
25828 enum attr_type type
;
25832 || DEBUG_INSN_P (insn
)
25833 || GET_CODE (PATTERN (insn
)) == USE
25834 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
25837 switch (rs6000_cpu
)
25839 case PROCESSOR_POWER5
:
25840 if (is_cracked_insn (insn
))
25842 case PROCESSOR_POWER4
:
25843 if (is_microcoded_insn (insn
))
25846 if (!rs6000_sched_groups
)
25849 type
= get_attr_type (insn
);
25856 case TYPE_DELAYED_CR
:
25857 case TYPE_CR_LOGICAL
:
25871 case PROCESSOR_POWER6
:
25872 type
= get_attr_type (insn
);
25876 case TYPE_INSERT_DWORD
:
25880 case TYPE_VAR_SHIFT_ROTATE
:
25887 case TYPE_INSERT_WORD
:
25888 case TYPE_DELAYED_COMPARE
:
25889 case TYPE_IMUL_COMPARE
:
25890 case TYPE_LMUL_COMPARE
:
25891 case TYPE_FPCOMPARE
:
25902 case TYPE_LOAD_EXT_UX
:
25904 case TYPE_STORE_UX
:
25905 case TYPE_FPLOAD_U
:
25906 case TYPE_FPLOAD_UX
:
25907 case TYPE_FPSTORE_U
:
25908 case TYPE_FPSTORE_UX
:
25914 case PROCESSOR_POWER7
:
25915 type
= get_attr_type (insn
);
25919 case TYPE_CR_LOGICAL
:
25926 case TYPE_DELAYED_COMPARE
:
25927 case TYPE_VAR_DELAYED_COMPARE
:
25933 case TYPE_LOAD_EXT
:
25934 case TYPE_LOAD_EXT_U
:
25935 case TYPE_LOAD_EXT_UX
:
25937 case TYPE_STORE_UX
:
25938 case TYPE_FPLOAD_U
:
25939 case TYPE_FPLOAD_UX
:
25940 case TYPE_FPSTORE_U
:
25941 case TYPE_FPSTORE_UX
:
25949 case PROCESSOR_POWER8
:
25950 type
= get_attr_type (insn
);
25954 case TYPE_CR_LOGICAL
:
25955 case TYPE_DELAYED_CR
:
25960 case TYPE_DELAYED_COMPARE
:
25961 case TYPE_VAR_DELAYED_COMPARE
:
25962 case TYPE_IMUL_COMPARE
:
25963 case TYPE_LMUL_COMPARE
:
25970 case TYPE_LOAD_EXT
:
25971 case TYPE_LOAD_EXT_U
:
25972 case TYPE_LOAD_EXT_UX
:
25973 case TYPE_STORE_UX
:
25974 case TYPE_VECSTORE
:
25990 insn_must_be_last_in_group (rtx insn
)
25992 enum attr_type type
;
25996 || DEBUG_INSN_P (insn
)
25997 || GET_CODE (PATTERN (insn
)) == USE
25998 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
26001 switch (rs6000_cpu
) {
26002 case PROCESSOR_POWER4
:
26003 case PROCESSOR_POWER5
:
26004 if (is_microcoded_insn (insn
))
26007 if (is_branch_slot_insn (insn
))
26011 case PROCESSOR_POWER6
:
26012 type
= get_attr_type (insn
);
26019 case TYPE_VAR_SHIFT_ROTATE
:
26026 case TYPE_DELAYED_COMPARE
:
26027 case TYPE_IMUL_COMPARE
:
26028 case TYPE_LMUL_COMPARE
:
26029 case TYPE_FPCOMPARE
:
26043 case PROCESSOR_POWER7
:
26044 type
= get_attr_type (insn
);
26052 case TYPE_LOAD_EXT_U
:
26053 case TYPE_LOAD_EXT_UX
:
26054 case TYPE_STORE_UX
:
26060 case PROCESSOR_POWER8
:
26061 type
= get_attr_type (insn
);
26071 case TYPE_LOAD_EXT_U
:
26072 case TYPE_LOAD_EXT_UX
:
26073 case TYPE_STORE_UX
:
26086 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
26087 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
26090 is_costly_group (rtx
*group_insns
, rtx next_insn
)
26093 int issue_rate
= rs6000_issue_rate ();
26095 for (i
= 0; i
< issue_rate
; i
++)
26097 sd_iterator_def sd_it
;
26099 rtx insn
= group_insns
[i
];
26104 FOR_EACH_DEP (insn
, SD_LIST_RES_FORW
, sd_it
, dep
)
26106 rtx next
= DEP_CON (dep
);
26108 if (next
== next_insn
26109 && rs6000_is_costly_dependence (dep
, dep_cost (dep
), 0))
26117 /* Utility of the function redefine_groups.
26118 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
26119 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
26120 to keep it "far" (in a separate group) from GROUP_INSNS, following
26121 one of the following schemes, depending on the value of the flag
26122 -minsert_sched_nops = X:
26123 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
26124 in order to force NEXT_INSN into a separate group.
26125 (2) X < sched_finish_regroup_exact: insert exactly X nops.
26126 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
26127 insertion (has a group just ended, how many vacant issue slots remain in the
26128 last group, and how many dispatch groups were encountered so far). */
26131 force_new_group (int sched_verbose
, FILE *dump
, rtx
*group_insns
,
26132 rtx next_insn
, bool *group_end
, int can_issue_more
,
26137 int issue_rate
= rs6000_issue_rate ();
26138 bool end
= *group_end
;
26141 if (next_insn
== NULL_RTX
|| DEBUG_INSN_P (next_insn
))
26142 return can_issue_more
;
26144 if (rs6000_sched_insert_nops
> sched_finish_regroup_exact
)
26145 return can_issue_more
;
26147 force
= is_costly_group (group_insns
, next_insn
);
26149 return can_issue_more
;
26151 if (sched_verbose
> 6)
26152 fprintf (dump
,"force: group count = %d, can_issue_more = %d\n",
26153 *group_count
,can_issue_more
);
26155 if (rs6000_sched_insert_nops
== sched_finish_regroup_exact
)
26158 can_issue_more
= 0;
26160 /* Since only a branch can be issued in the last issue_slot, it is
26161 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
26162 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
26163 in this case the last nop will start a new group and the branch
26164 will be forced to the new group. */
26165 if (can_issue_more
&& !is_branch_slot_insn (next_insn
))
26168 /* Do we have a special group ending nop? */
26169 if (rs6000_cpu_attr
== CPU_POWER6
|| rs6000_cpu_attr
== CPU_POWER7
26170 || rs6000_cpu_attr
== CPU_POWER8
)
26172 nop
= gen_group_ending_nop ();
26173 emit_insn_before (nop
, next_insn
);
26174 can_issue_more
= 0;
26177 while (can_issue_more
> 0)
26180 emit_insn_before (nop
, next_insn
);
26188 if (rs6000_sched_insert_nops
< sched_finish_regroup_exact
)
26190 int n_nops
= rs6000_sched_insert_nops
;
26192 /* Nops can't be issued from the branch slot, so the effective
26193 issue_rate for nops is 'issue_rate - 1'. */
26194 if (can_issue_more
== 0)
26195 can_issue_more
= issue_rate
;
26197 if (can_issue_more
== 0)
26199 can_issue_more
= issue_rate
- 1;
26202 for (i
= 0; i
< issue_rate
; i
++)
26204 group_insns
[i
] = 0;
26211 emit_insn_before (nop
, next_insn
);
26212 if (can_issue_more
== issue_rate
- 1) /* new group begins */
26215 if (can_issue_more
== 0)
26217 can_issue_more
= issue_rate
- 1;
26220 for (i
= 0; i
< issue_rate
; i
++)
26222 group_insns
[i
] = 0;
26228 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
26231 /* Is next_insn going to start a new group? */
26234 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
26235 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
26236 || (can_issue_more
< issue_rate
&&
26237 insn_terminates_group_p (next_insn
, previous_group
)));
26238 if (*group_end
&& end
)
26241 if (sched_verbose
> 6)
26242 fprintf (dump
, "done force: group count = %d, can_issue_more = %d\n",
26243 *group_count
, can_issue_more
);
26244 return can_issue_more
;
26247 return can_issue_more
;
26250 /* This function tries to synch the dispatch groups that the compiler "sees"
26251 with the dispatch groups that the processor dispatcher is expected to
26252 form in practice. It tries to achieve this synchronization by forcing the
26253 estimated processor grouping on the compiler (as opposed to the function
26254 'pad_goups' which tries to force the scheduler's grouping on the processor).
26256 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
26257 examines the (estimated) dispatch groups that will be formed by the processor
26258 dispatcher. It marks these group boundaries to reflect the estimated
26259 processor grouping, overriding the grouping that the scheduler had marked.
26260 Depending on the value of the flag '-minsert-sched-nops' this function can
26261 force certain insns into separate groups or force a certain distance between
26262 them by inserting nops, for example, if there exists a "costly dependence"
26265 The function estimates the group boundaries that the processor will form as
26266 follows: It keeps track of how many vacant issue slots are available after
26267 each insn. A subsequent insn will start a new group if one of the following
26269 - no more vacant issue slots remain in the current dispatch group.
26270 - only the last issue slot, which is the branch slot, is vacant, but the next
26271 insn is not a branch.
26272 - only the last 2 or less issue slots, including the branch slot, are vacant,
26273 which means that a cracked insn (which occupies two issue slots) can't be
26274 issued in this group.
26275 - less than 'issue_rate' slots are vacant, and the next insn always needs to
26276 start a new group. */
26279 redefine_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
26281 rtx insn
, next_insn
;
26283 int can_issue_more
;
26286 int group_count
= 0;
26290 issue_rate
= rs6000_issue_rate ();
26291 group_insns
= XALLOCAVEC (rtx
, issue_rate
);
26292 for (i
= 0; i
< issue_rate
; i
++)
26294 group_insns
[i
] = 0;
26296 can_issue_more
= issue_rate
;
26298 insn
= get_next_active_insn (prev_head_insn
, tail
);
26301 while (insn
!= NULL_RTX
)
26303 slot
= (issue_rate
- can_issue_more
);
26304 group_insns
[slot
] = insn
;
26306 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
26307 if (insn_terminates_group_p (insn
, current_group
))
26308 can_issue_more
= 0;
26310 next_insn
= get_next_active_insn (insn
, tail
);
26311 if (next_insn
== NULL_RTX
)
26312 return group_count
+ 1;
26314 /* Is next_insn going to start a new group? */
26316 = (can_issue_more
== 0
26317 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
26318 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
26319 || (can_issue_more
< issue_rate
&&
26320 insn_terminates_group_p (next_insn
, previous_group
)));
26322 can_issue_more
= force_new_group (sched_verbose
, dump
, group_insns
,
26323 next_insn
, &group_end
, can_issue_more
,
26329 can_issue_more
= 0;
26330 for (i
= 0; i
< issue_rate
; i
++)
26332 group_insns
[i
] = 0;
26336 if (GET_MODE (next_insn
) == TImode
&& can_issue_more
)
26337 PUT_MODE (next_insn
, VOIDmode
);
26338 else if (!can_issue_more
&& GET_MODE (next_insn
) != TImode
)
26339 PUT_MODE (next_insn
, TImode
);
26342 if (can_issue_more
== 0)
26343 can_issue_more
= issue_rate
;
26346 return group_count
;
26349 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
26350 dispatch group boundaries that the scheduler had marked. Pad with nops
26351 any dispatch groups which have vacant issue slots, in order to force the
26352 scheduler's grouping on the processor dispatcher. The function
26353 returns the number of dispatch groups found. */
26356 pad_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
26358 rtx insn
, next_insn
;
26361 int can_issue_more
;
26363 int group_count
= 0;
26365 /* Initialize issue_rate. */
26366 issue_rate
= rs6000_issue_rate ();
26367 can_issue_more
= issue_rate
;
26369 insn
= get_next_active_insn (prev_head_insn
, tail
);
26370 next_insn
= get_next_active_insn (insn
, tail
);
26372 while (insn
!= NULL_RTX
)
26375 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
26377 group_end
= (next_insn
== NULL_RTX
|| GET_MODE (next_insn
) == TImode
);
26379 if (next_insn
== NULL_RTX
)
26384 /* If the scheduler had marked group termination at this location
26385 (between insn and next_insn), and neither insn nor next_insn will
26386 force group termination, pad the group with nops to force group
26389 && (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
26390 && !insn_terminates_group_p (insn
, current_group
)
26391 && !insn_terminates_group_p (next_insn
, previous_group
))
26393 if (!is_branch_slot_insn (next_insn
))
26396 while (can_issue_more
)
26399 emit_insn_before (nop
, next_insn
);
26404 can_issue_more
= issue_rate
;
26409 next_insn
= get_next_active_insn (insn
, tail
);
26412 return group_count
;
26415 /* We're beginning a new block. Initialize data structures as necessary. */
26418 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
26419 int sched_verbose ATTRIBUTE_UNUSED
,
26420 int max_ready ATTRIBUTE_UNUSED
)
26422 last_scheduled_insn
= NULL_RTX
;
26423 load_store_pendulum
= 0;
26426 /* The following function is called at the end of scheduling BB.
26427 After reload, it inserts nops at insn group bundling. */
26430 rs6000_sched_finish (FILE *dump
, int sched_verbose
)
26435 fprintf (dump
, "=== Finishing schedule.\n");
26437 if (reload_completed
&& rs6000_sched_groups
)
26439 /* Do not run sched_finish hook when selective scheduling enabled. */
26440 if (sel_sched_p ())
26443 if (rs6000_sched_insert_nops
== sched_finish_none
)
26446 if (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
26447 n_groups
= pad_groups (dump
, sched_verbose
,
26448 current_sched_info
->prev_head
,
26449 current_sched_info
->next_tail
);
26451 n_groups
= redefine_groups (dump
, sched_verbose
,
26452 current_sched_info
->prev_head
,
26453 current_sched_info
->next_tail
);
26455 if (sched_verbose
>= 6)
26457 fprintf (dump
, "ngroups = %d\n", n_groups
);
26458 print_rtl (dump
, current_sched_info
->prev_head
);
26459 fprintf (dump
, "Done finish_sched\n");
26464 struct _rs6000_sched_context
26466 short cached_can_issue_more
;
26467 rtx last_scheduled_insn
;
26468 int load_store_pendulum
;
26471 typedef struct _rs6000_sched_context rs6000_sched_context_def
;
26472 typedef rs6000_sched_context_def
*rs6000_sched_context_t
;
26474 /* Allocate store for new scheduling context. */
26476 rs6000_alloc_sched_context (void)
26478 return xmalloc (sizeof (rs6000_sched_context_def
));
26481 /* If CLEAN_P is true then initializes _SC with clean data,
26482 and from the global context otherwise. */
26484 rs6000_init_sched_context (void *_sc
, bool clean_p
)
26486 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
26490 sc
->cached_can_issue_more
= 0;
26491 sc
->last_scheduled_insn
= NULL_RTX
;
26492 sc
->load_store_pendulum
= 0;
26496 sc
->cached_can_issue_more
= cached_can_issue_more
;
26497 sc
->last_scheduled_insn
= last_scheduled_insn
;
26498 sc
->load_store_pendulum
= load_store_pendulum
;
26502 /* Sets the global scheduling context to the one pointed to by _SC. */
26504 rs6000_set_sched_context (void *_sc
)
26506 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
26508 gcc_assert (sc
!= NULL
);
26510 cached_can_issue_more
= sc
->cached_can_issue_more
;
26511 last_scheduled_insn
= sc
->last_scheduled_insn
;
26512 load_store_pendulum
= sc
->load_store_pendulum
;
26517 rs6000_free_sched_context (void *_sc
)
26519 gcc_assert (_sc
!= NULL
);
26525 /* Length in units of the trampoline for entering a nested function. */
26528 rs6000_trampoline_size (void)
26532 switch (DEFAULT_ABI
)
26535 gcc_unreachable ();
26538 ret
= (TARGET_32BIT
) ? 12 : 24;
26543 ret
= (TARGET_32BIT
) ? 40 : 48;
26550 /* Emit RTL insns to initialize the variable parts of a trampoline.
26551 FNADDR is an RTX for the address of the function's pure code.
26552 CXT is an RTX for the static chain value for the function. */
26555 rs6000_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
26557 int regsize
= (TARGET_32BIT
) ? 4 : 8;
26558 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
26559 rtx ctx_reg
= force_reg (Pmode
, cxt
);
26560 rtx addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
26562 switch (DEFAULT_ABI
)
26565 gcc_unreachable ();
26567 /* Under AIX, just build the 3 word function descriptor */
26570 rtx fnmem
, fn_reg
, toc_reg
;
26572 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
26573 error ("You cannot take the address of a nested function if you use "
26574 "the -mno-pointers-to-nested-functions option.");
26576 fnmem
= gen_const_mem (Pmode
, force_reg (Pmode
, fnaddr
));
26577 fn_reg
= gen_reg_rtx (Pmode
);
26578 toc_reg
= gen_reg_rtx (Pmode
);
26580 /* Macro to shorten the code expansions below. */
26581 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
26583 m_tramp
= replace_equiv_address (m_tramp
, addr
);
26585 emit_move_insn (fn_reg
, MEM_PLUS (fnmem
, 0));
26586 emit_move_insn (toc_reg
, MEM_PLUS (fnmem
, regsize
));
26587 emit_move_insn (MEM_PLUS (m_tramp
, 0), fn_reg
);
26588 emit_move_insn (MEM_PLUS (m_tramp
, regsize
), toc_reg
);
26589 emit_move_insn (MEM_PLUS (m_tramp
, 2*regsize
), ctx_reg
);
26595 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
26598 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__trampoline_setup"),
26599 LCT_NORMAL
, VOIDmode
, 4,
26601 GEN_INT (rs6000_trampoline_size ()), SImode
,
26609 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
26610 identifier as an argument, so the front end shouldn't look it up. */
26613 rs6000_attribute_takes_identifier_p (const_tree attr_id
)
26615 return is_attribute_p ("altivec", attr_id
);
26618 /* Handle the "altivec" attribute. The attribute may have
26619 arguments as follows:
26621 __attribute__((altivec(vector__)))
26622 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
26623 __attribute__((altivec(bool__))) (always followed by 'unsigned')
26625 and may appear more than once (e.g., 'vector bool char') in a
26626 given declaration. */
26629 rs6000_handle_altivec_attribute (tree
*node
,
26630 tree name ATTRIBUTE_UNUSED
,
26632 int flags ATTRIBUTE_UNUSED
,
26633 bool *no_add_attrs
)
26635 tree type
= *node
, result
= NULL_TREE
;
26636 enum machine_mode mode
;
26639 = ((args
&& TREE_CODE (args
) == TREE_LIST
&& TREE_VALUE (args
)
26640 && TREE_CODE (TREE_VALUE (args
)) == IDENTIFIER_NODE
)
26641 ? *IDENTIFIER_POINTER (TREE_VALUE (args
))
26644 while (POINTER_TYPE_P (type
)
26645 || TREE_CODE (type
) == FUNCTION_TYPE
26646 || TREE_CODE (type
) == METHOD_TYPE
26647 || TREE_CODE (type
) == ARRAY_TYPE
)
26648 type
= TREE_TYPE (type
);
26650 mode
= TYPE_MODE (type
);
26652 /* Check for invalid AltiVec type qualifiers. */
26653 if (type
== long_double_type_node
)
26654 error ("use of %<long double%> in AltiVec types is invalid");
26655 else if (type
== boolean_type_node
)
26656 error ("use of boolean types in AltiVec types is invalid");
26657 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
26658 error ("use of %<complex%> in AltiVec types is invalid");
26659 else if (DECIMAL_FLOAT_MODE_P (mode
))
26660 error ("use of decimal floating point types in AltiVec types is invalid");
26661 else if (!TARGET_VSX
)
26663 if (type
== long_unsigned_type_node
|| type
== long_integer_type_node
)
26666 error ("use of %<long%> in AltiVec types is invalid for "
26667 "64-bit code without -mvsx");
26668 else if (rs6000_warn_altivec_long
)
26669 warning (0, "use of %<long%> in AltiVec types is deprecated; "
26672 else if (type
== long_long_unsigned_type_node
26673 || type
== long_long_integer_type_node
)
26674 error ("use of %<long long%> in AltiVec types is invalid without "
26676 else if (type
== double_type_node
)
26677 error ("use of %<double%> in AltiVec types is invalid without -mvsx");
26680 switch (altivec_type
)
26683 unsigned_p
= TYPE_UNSIGNED (type
);
26687 result
= (unsigned_p
? unsigned_V2DI_type_node
: V2DI_type_node
);
26690 result
= (unsigned_p
? unsigned_V4SI_type_node
: V4SI_type_node
);
26693 result
= (unsigned_p
? unsigned_V8HI_type_node
: V8HI_type_node
);
26696 result
= (unsigned_p
? unsigned_V16QI_type_node
: V16QI_type_node
);
26698 case SFmode
: result
= V4SF_type_node
; break;
26699 case DFmode
: result
= V2DF_type_node
; break;
26700 /* If the user says 'vector int bool', we may be handed the 'bool'
26701 attribute _before_ the 'vector' attribute, and so select the
26702 proper type in the 'b' case below. */
26703 case V4SImode
: case V8HImode
: case V16QImode
: case V4SFmode
:
26704 case V2DImode
: case V2DFmode
:
26712 case DImode
: case V2DImode
: result
= bool_V2DI_type_node
; break;
26713 case SImode
: case V4SImode
: result
= bool_V4SI_type_node
; break;
26714 case HImode
: case V8HImode
: result
= bool_V8HI_type_node
; break;
26715 case QImode
: case V16QImode
: result
= bool_V16QI_type_node
;
26722 case V8HImode
: result
= pixel_V8HI_type_node
;
26728 /* Propagate qualifiers attached to the element type
26729 onto the vector type. */
26730 if (result
&& result
!= type
&& TYPE_QUALS (type
))
26731 result
= build_qualified_type (result
, TYPE_QUALS (type
));
26733 *no_add_attrs
= true; /* No need to hang on to the attribute. */
26736 *node
= lang_hooks
.types
.reconstruct_complex_type (*node
, result
);
26741 /* AltiVec defines four built-in scalar types that serve as vector
26742 elements; we must teach the compiler how to mangle them. */
26744 static const char *
26745 rs6000_mangle_type (const_tree type
)
26747 type
= TYPE_MAIN_VARIANT (type
);
26749 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
26750 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
26753 if (type
== bool_char_type_node
) return "U6__boolc";
26754 if (type
== bool_short_type_node
) return "U6__bools";
26755 if (type
== pixel_type_node
) return "u7__pixel";
26756 if (type
== bool_int_type_node
) return "U6__booli";
26757 if (type
== bool_long_type_node
) return "U6__booll";
26759 /* Mangle IBM extended float long double as `g' (__float128) on
26760 powerpc*-linux where long-double-64 previously was the default. */
26761 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
26763 && TARGET_LONG_DOUBLE_128
26764 && !TARGET_IEEEQUAD
)
26767 /* For all other types, use normal C++ mangling. */
26771 /* Handle a "longcall" or "shortcall" attribute; arguments as in
26772 struct attribute_spec.handler. */
26775 rs6000_handle_longcall_attribute (tree
*node
, tree name
,
26776 tree args ATTRIBUTE_UNUSED
,
26777 int flags ATTRIBUTE_UNUSED
,
26778 bool *no_add_attrs
)
26780 if (TREE_CODE (*node
) != FUNCTION_TYPE
26781 && TREE_CODE (*node
) != FIELD_DECL
26782 && TREE_CODE (*node
) != TYPE_DECL
)
26784 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
26786 *no_add_attrs
= true;
26792 /* Set longcall attributes on all functions declared when
26793 rs6000_default_long_calls is true. */
26795 rs6000_set_default_type_attributes (tree type
)
26797 if (rs6000_default_long_calls
26798 && (TREE_CODE (type
) == FUNCTION_TYPE
26799 || TREE_CODE (type
) == METHOD_TYPE
))
26800 TYPE_ATTRIBUTES (type
) = tree_cons (get_identifier ("longcall"),
26802 TYPE_ATTRIBUTES (type
));
26805 darwin_set_default_type_attributes (type
);
26809 /* Return a reference suitable for calling a function with the
26810 longcall attribute. */
26813 rs6000_longcall_ref (rtx call_ref
)
26815 const char *call_name
;
26818 if (GET_CODE (call_ref
) != SYMBOL_REF
)
26821 /* System V adds '.' to the internal name, so skip them. */
26822 call_name
= XSTR (call_ref
, 0);
26823 if (*call_name
== '.')
26825 while (*call_name
== '.')
26828 node
= get_identifier (call_name
);
26829 call_ref
= gen_rtx_SYMBOL_REF (VOIDmode
, IDENTIFIER_POINTER (node
));
26832 return force_reg (Pmode
, call_ref
);
26835 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
26836 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
26839 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
26840 struct attribute_spec.handler. */
26842 rs6000_handle_struct_attribute (tree
*node
, tree name
,
26843 tree args ATTRIBUTE_UNUSED
,
26844 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
26847 if (DECL_P (*node
))
26849 if (TREE_CODE (*node
) == TYPE_DECL
)
26850 type
= &TREE_TYPE (*node
);
26855 if (!(type
&& (TREE_CODE (*type
) == RECORD_TYPE
26856 || TREE_CODE (*type
) == UNION_TYPE
)))
26858 warning (OPT_Wattributes
, "%qE attribute ignored", name
);
26859 *no_add_attrs
= true;
26862 else if ((is_attribute_p ("ms_struct", name
)
26863 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type
)))
26864 || ((is_attribute_p ("gcc_struct", name
)
26865 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type
)))))
26867 warning (OPT_Wattributes
, "%qE incompatible attribute ignored",
26869 *no_add_attrs
= true;
26876 rs6000_ms_bitfield_layout_p (const_tree record_type
)
26878 return (TARGET_USE_MS_BITFIELD_LAYOUT
&&
26879 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type
)))
26880 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type
));
26883 #ifdef USING_ELFOS_H
26885 /* A get_unnamed_section callback, used for switching to toc_section. */
26888 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
26890 if (DEFAULT_ABI
== ABI_AIX
26891 && TARGET_MINIMAL_TOC
26892 && !TARGET_RELOCATABLE
)
26894 if (!toc_initialized
)
26896 toc_initialized
= 1;
26897 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
26898 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LCTOC", 0);
26899 fprintf (asm_out_file
, "\t.tc ");
26900 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1[TC],");
26901 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
26902 fprintf (asm_out_file
, "\n");
26904 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
26905 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
26906 fprintf (asm_out_file
, " = .+32768\n");
26909 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
26911 else if (DEFAULT_ABI
== ABI_AIX
&& !TARGET_RELOCATABLE
)
26912 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
26915 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
26916 if (!toc_initialized
)
26918 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
26919 fprintf (asm_out_file
, " = .+32768\n");
26920 toc_initialized
= 1;
26925 /* Implement TARGET_ASM_INIT_SECTIONS. */
26928 rs6000_elf_asm_init_sections (void)
26931 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op
, NULL
);
26934 = get_unnamed_section (SECTION_WRITE
, output_section_asm_op
,
26935 SDATA2_SECTION_ASM_OP
);
26938 /* Implement TARGET_SELECT_RTX_SECTION. */
26941 rs6000_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
26942 unsigned HOST_WIDE_INT align
)
26944 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
26945 return toc_section
;
26947 return default_elf_select_rtx_section (mode
, x
, align
);
26950 /* For a SYMBOL_REF, set generic flags and then perform some
26951 target-specific processing.
26953 When the AIX ABI is requested on a non-AIX system, replace the
26954 function name with the real name (with a leading .) rather than the
26955 function descriptor name. This saves a lot of overriding code to
26956 read the prefixes. */
26958 static void rs6000_elf_encode_section_info (tree
, rtx
, int) ATTRIBUTE_UNUSED
;
26960 rs6000_elf_encode_section_info (tree decl
, rtx rtl
, int first
)
26962 default_encode_section_info (decl
, rtl
, first
);
26965 && TREE_CODE (decl
) == FUNCTION_DECL
26967 && DEFAULT_ABI
== ABI_AIX
)
26969 rtx sym_ref
= XEXP (rtl
, 0);
26970 size_t len
= strlen (XSTR (sym_ref
, 0));
26971 char *str
= XALLOCAVEC (char, len
+ 2);
26973 memcpy (str
+ 1, XSTR (sym_ref
, 0), len
+ 1);
26974 XSTR (sym_ref
, 0) = ggc_alloc_string (str
, len
+ 1);
26979 compare_section_name (const char *section
, const char *templ
)
26983 len
= strlen (templ
);
26984 return (strncmp (section
, templ
, len
) == 0
26985 && (section
[len
] == 0 || section
[len
] == '.'));
26989 rs6000_elf_in_small_data_p (const_tree decl
)
26991 if (rs6000_sdata
== SDATA_NONE
)
26994 /* We want to merge strings, so we never consider them small data. */
26995 if (TREE_CODE (decl
) == STRING_CST
)
26998 /* Functions are never in the small data area. */
26999 if (TREE_CODE (decl
) == FUNCTION_DECL
)
27002 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
))
27004 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
27005 if (compare_section_name (section
, ".sdata")
27006 || compare_section_name (section
, ".sdata2")
27007 || compare_section_name (section
, ".gnu.linkonce.s")
27008 || compare_section_name (section
, ".sbss")
27009 || compare_section_name (section
, ".sbss2")
27010 || compare_section_name (section
, ".gnu.linkonce.sb")
27011 || strcmp (section
, ".PPC.EMB.sdata0") == 0
27012 || strcmp (section
, ".PPC.EMB.sbss0") == 0)
27017 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
27020 && size
<= g_switch_value
27021 /* If it's not public, and we're not going to reference it there,
27022 there's no need to put it in the small data section. */
27023 && (rs6000_sdata
!= SDATA_DATA
|| TREE_PUBLIC (decl
)))
27030 #endif /* USING_ELFOS_H */
27032 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
27035 rs6000_use_blocks_for_constant_p (enum machine_mode mode
, const_rtx x
)
27037 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
);
27040 /* Do not place thread-local symbols refs in the object blocks. */
27043 rs6000_use_blocks_for_decl_p (const_tree decl
)
27045 return !DECL_THREAD_LOCAL_P (decl
);
27048 /* Return a REG that occurs in ADDR with coefficient 1.
27049 ADDR can be effectively incremented by incrementing REG.
27051 r0 is special and we must not select it as an address
27052 register by this routine since our caller will try to
27053 increment the returned register via an "la" instruction. */
27056 find_addr_reg (rtx addr
)
27058 while (GET_CODE (addr
) == PLUS
)
27060 if (GET_CODE (XEXP (addr
, 0)) == REG
27061 && REGNO (XEXP (addr
, 0)) != 0)
27062 addr
= XEXP (addr
, 0);
27063 else if (GET_CODE (XEXP (addr
, 1)) == REG
27064 && REGNO (XEXP (addr
, 1)) != 0)
27065 addr
= XEXP (addr
, 1);
27066 else if (CONSTANT_P (XEXP (addr
, 0)))
27067 addr
= XEXP (addr
, 1);
27068 else if (CONSTANT_P (XEXP (addr
, 1)))
27069 addr
= XEXP (addr
, 0);
27071 gcc_unreachable ();
27073 gcc_assert (GET_CODE (addr
) == REG
&& REGNO (addr
) != 0);
27078 rs6000_fatal_bad_address (rtx op
)
27080 fatal_insn ("bad address", op
);
27085 typedef struct branch_island_d
{
27086 tree function_name
;
27092 static vec
<branch_island
, va_gc
> *branch_islands
;
27094 /* Remember to generate a branch island for far calls to the given
27098 add_compiler_branch_island (tree label_name
, tree function_name
,
27101 branch_island bi
= {function_name
, label_name
, line_number
};
27102 vec_safe_push (branch_islands
, bi
);
27105 /* Generate far-jump branch islands for everything recorded in
27106 branch_islands. Invoked immediately after the last instruction of
27107 the epilogue has been emitted; the branch islands must be appended
27108 to, and contiguous with, the function body. Mach-O stubs are
27109 generated in machopic_output_stub(). */
27112 macho_branch_islands (void)
27116 while (!vec_safe_is_empty (branch_islands
))
27118 branch_island
*bi
= &branch_islands
->last ();
27119 const char *label
= IDENTIFIER_POINTER (bi
->label_name
);
27120 const char *name
= IDENTIFIER_POINTER (bi
->function_name
);
27121 char name_buf
[512];
27122 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
27123 if (name
[0] == '*' || name
[0] == '&')
27124 strcpy (name_buf
, name
+1);
27128 strcpy (name_buf
+1, name
);
27130 strcpy (tmp_buf
, "\n");
27131 strcat (tmp_buf
, label
);
27132 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
27133 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
27134 dbxout_stabd (N_SLINE
, bi
->line_number
);
27135 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
27138 if (TARGET_LINK_STACK
)
27141 get_ppc476_thunk_name (name
);
27142 strcat (tmp_buf
, ":\n\tmflr r0\n\tbl ");
27143 strcat (tmp_buf
, name
);
27144 strcat (tmp_buf
, "\n");
27145 strcat (tmp_buf
, label
);
27146 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
27150 strcat (tmp_buf
, ":\n\tmflr r0\n\tbcl 20,31,");
27151 strcat (tmp_buf
, label
);
27152 strcat (tmp_buf
, "_pic\n");
27153 strcat (tmp_buf
, label
);
27154 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
27157 strcat (tmp_buf
, "\taddis r11,r11,ha16(");
27158 strcat (tmp_buf
, name_buf
);
27159 strcat (tmp_buf
, " - ");
27160 strcat (tmp_buf
, label
);
27161 strcat (tmp_buf
, "_pic)\n");
27163 strcat (tmp_buf
, "\tmtlr r0\n");
27165 strcat (tmp_buf
, "\taddi r12,r11,lo16(");
27166 strcat (tmp_buf
, name_buf
);
27167 strcat (tmp_buf
, " - ");
27168 strcat (tmp_buf
, label
);
27169 strcat (tmp_buf
, "_pic)\n");
27171 strcat (tmp_buf
, "\tmtctr r12\n\tbctr\n");
27175 strcat (tmp_buf
, ":\nlis r12,hi16(");
27176 strcat (tmp_buf
, name_buf
);
27177 strcat (tmp_buf
, ")\n\tori r12,r12,lo16(");
27178 strcat (tmp_buf
, name_buf
);
27179 strcat (tmp_buf
, ")\n\tmtctr r12\n\tbctr");
27181 output_asm_insn (tmp_buf
, 0);
27182 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
27183 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
27184 dbxout_stabd (N_SLINE
, bi
->line_number
);
27185 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
27186 branch_islands
->pop ();
27190 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
27191 already there or not. */
27194 no_previous_def (tree function_name
)
27199 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
27200 if (function_name
== bi
->function_name
)
27205 /* GET_PREV_LABEL gets the label name from the previous definition of
27209 get_prev_label (tree function_name
)
27214 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
27215 if (function_name
== bi
->function_name
)
27216 return bi
->label_name
;
27220 /* INSN is either a function call or a millicode call. It may have an
27221 unconditional jump in its delay slot.
27223 CALL_DEST is the routine we are calling. */
27226 output_call (rtx insn
, rtx
*operands
, int dest_operand_number
,
27227 int cookie_operand_number
)
27229 static char buf
[256];
27230 if (darwin_emit_branch_islands
27231 && GET_CODE (operands
[dest_operand_number
]) == SYMBOL_REF
27232 && (INTVAL (operands
[cookie_operand_number
]) & CALL_LONG
))
27235 tree funname
= get_identifier (XSTR (operands
[dest_operand_number
], 0));
27237 if (no_previous_def (funname
))
27239 rtx label_rtx
= gen_label_rtx ();
27240 char *label_buf
, temp_buf
[256];
27241 ASM_GENERATE_INTERNAL_LABEL (temp_buf
, "L",
27242 CODE_LABEL_NUMBER (label_rtx
));
27243 label_buf
= temp_buf
[0] == '*' ? temp_buf
+ 1 : temp_buf
;
27244 labelname
= get_identifier (label_buf
);
27245 add_compiler_branch_island (labelname
, funname
, insn_line (insn
));
27248 labelname
= get_prev_label (funname
);
27250 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
27251 instruction will reach 'foo', otherwise link as 'bl L42'".
27252 "L42" should be a 'branch island', that will do a far jump to
27253 'foo'. Branch islands are generated in
27254 macho_branch_islands(). */
27255 sprintf (buf
, "jbsr %%z%d,%.246s",
27256 dest_operand_number
, IDENTIFIER_POINTER (labelname
));
27259 sprintf (buf
, "bl %%z%d", dest_operand_number
);
27263 /* Generate PIC and indirect symbol stubs. */
27266 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
27268 unsigned int length
;
27269 char *symbol_name
, *lazy_ptr_name
;
27270 char *local_label_0
;
27271 static int label
= 0;
27273 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
27274 symb
= (*targetm
.strip_name_encoding
) (symb
);
27277 length
= strlen (symb
);
27278 symbol_name
= XALLOCAVEC (char, length
+ 32);
27279 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
27281 lazy_ptr_name
= XALLOCAVEC (char, length
+ 32);
27282 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name
, symb
, length
);
27285 switch_to_section (darwin_sections
[machopic_picsymbol_stub1_section
]);
27287 switch_to_section (darwin_sections
[machopic_symbol_stub1_section
]);
27291 fprintf (file
, "\t.align 5\n");
27293 fprintf (file
, "%s:\n", stub
);
27294 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
27297 local_label_0
= XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
27298 sprintf (local_label_0
, "\"L%011d$spb\"", label
);
27300 fprintf (file
, "\tmflr r0\n");
27301 if (TARGET_LINK_STACK
)
27304 get_ppc476_thunk_name (name
);
27305 fprintf (file
, "\tbl %s\n", name
);
27306 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
27310 fprintf (file
, "\tbcl 20,31,%s\n", local_label_0
);
27311 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
27313 fprintf (file
, "\taddis r11,r11,ha16(%s-%s)\n",
27314 lazy_ptr_name
, local_label_0
);
27315 fprintf (file
, "\tmtlr r0\n");
27316 fprintf (file
, "\t%s r12,lo16(%s-%s)(r11)\n",
27317 (TARGET_64BIT
? "ldu" : "lwzu"),
27318 lazy_ptr_name
, local_label_0
);
27319 fprintf (file
, "\tmtctr r12\n");
27320 fprintf (file
, "\tbctr\n");
27324 fprintf (file
, "\t.align 4\n");
27326 fprintf (file
, "%s:\n", stub
);
27327 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
27329 fprintf (file
, "\tlis r11,ha16(%s)\n", lazy_ptr_name
);
27330 fprintf (file
, "\t%s r12,lo16(%s)(r11)\n",
27331 (TARGET_64BIT
? "ldu" : "lwzu"),
27333 fprintf (file
, "\tmtctr r12\n");
27334 fprintf (file
, "\tbctr\n");
27337 switch_to_section (darwin_sections
[machopic_lazy_symbol_ptr_section
]);
27338 fprintf (file
, "%s:\n", lazy_ptr_name
);
27339 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
27340 fprintf (file
, "%sdyld_stub_binding_helper\n",
27341 (TARGET_64BIT
? DOUBLE_INT_ASM_OP
: "\t.long\t"));
27344 /* Legitimize PIC addresses. If the address is already
27345 position-independent, we return ORIG. Newly generated
27346 position-independent addresses go into a reg. This is REG if non
27347 zero, otherwise we allocate register(s) as necessary. */
27349 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
27352 rs6000_machopic_legitimize_pic_address (rtx orig
, enum machine_mode mode
,
27357 if (reg
== NULL
&& ! reload_in_progress
&& ! reload_completed
)
27358 reg
= gen_reg_rtx (Pmode
);
27360 if (GET_CODE (orig
) == CONST
)
27364 if (GET_CODE (XEXP (orig
, 0)) == PLUS
27365 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
27368 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
27370 /* Use a different reg for the intermediate value, as
27371 it will be marked UNCHANGING. */
27372 reg_temp
= !can_create_pseudo_p () ? reg
: gen_reg_rtx (Pmode
);
27373 base
= rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0),
27376 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
27379 if (GET_CODE (offset
) == CONST_INT
)
27381 if (SMALL_INT (offset
))
27382 return plus_constant (Pmode
, base
, INTVAL (offset
));
27383 else if (! reload_in_progress
&& ! reload_completed
)
27384 offset
= force_reg (Pmode
, offset
);
27387 rtx mem
= force_const_mem (Pmode
, orig
);
27388 return machopic_legitimize_pic_address (mem
, Pmode
, reg
);
27391 return gen_rtx_PLUS (Pmode
, base
, offset
);
27394 /* Fall back on generic machopic code. */
27395 return machopic_legitimize_pic_address (orig
, mode
, reg
);
27398 /* Output a .machine directive for the Darwin assembler, and call
27399 the generic start_file routine. */
27402 rs6000_darwin_file_start (void)
27404 static const struct
27408 HOST_WIDE_INT if_set
;
27410 { "ppc64", "ppc64", MASK_64BIT
},
27411 { "970", "ppc970", MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
27412 { "power4", "ppc970", 0 },
27413 { "G5", "ppc970", 0 },
27414 { "7450", "ppc7450", 0 },
27415 { "7400", "ppc7400", MASK_ALTIVEC
},
27416 { "G4", "ppc7400", 0 },
27417 { "750", "ppc750", 0 },
27418 { "740", "ppc750", 0 },
27419 { "G3", "ppc750", 0 },
27420 { "604e", "ppc604e", 0 },
27421 { "604", "ppc604", 0 },
27422 { "603e", "ppc603", 0 },
27423 { "603", "ppc603", 0 },
27424 { "601", "ppc601", 0 },
27425 { NULL
, "ppc", 0 } };
27426 const char *cpu_id
= "";
27429 rs6000_file_start ();
27430 darwin_file_start ();
27432 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
27434 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
27435 cpu_id
= rs6000_default_cpu
;
27437 if (global_options_set
.x_rs6000_cpu_index
)
27438 cpu_id
= processor_target_table
[rs6000_cpu_index
].name
;
27440 /* Look through the mapping array. Pick the first name that either
27441 matches the argument, has a bit set in IF_SET that is also set
27442 in the target flags, or has a NULL name. */
27445 while (mapping
[i
].arg
!= NULL
27446 && strcmp (mapping
[i
].arg
, cpu_id
) != 0
27447 && (mapping
[i
].if_set
& rs6000_isa_flags
) == 0)
27450 fprintf (asm_out_file
, "\t.machine %s\n", mapping
[i
].name
);
27453 #endif /* TARGET_MACHO */
27457 rs6000_elf_reloc_rw_mask (void)
27461 else if (DEFAULT_ABI
== ABI_AIX
)
27467 /* Record an element in the table of global constructors. SYMBOL is
27468 a SYMBOL_REF of the function to be called; PRIORITY is a number
27469 between 0 and MAX_INIT_PRIORITY.
27471 This differs from default_named_section_asm_out_constructor in
27472 that we have special handling for -mrelocatable. */
27474 static void rs6000_elf_asm_out_constructor (rtx
, int) ATTRIBUTE_UNUSED
;
27476 rs6000_elf_asm_out_constructor (rtx symbol
, int priority
)
27478 const char *section
= ".ctors";
27481 if (priority
!= DEFAULT_INIT_PRIORITY
)
27483 sprintf (buf
, ".ctors.%.5u",
27484 /* Invert the numbering so the linker puts us in the proper
27485 order; constructors are run from right to left, and the
27486 linker sorts in increasing order. */
27487 MAX_INIT_PRIORITY
- priority
);
27491 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
27492 assemble_align (POINTER_SIZE
);
27494 if (TARGET_RELOCATABLE
)
27496 fputs ("\t.long (", asm_out_file
);
27497 output_addr_const (asm_out_file
, symbol
);
27498 fputs (")@fixup\n", asm_out_file
);
27501 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
27504 static void rs6000_elf_asm_out_destructor (rtx
, int) ATTRIBUTE_UNUSED
;
27506 rs6000_elf_asm_out_destructor (rtx symbol
, int priority
)
27508 const char *section
= ".dtors";
27511 if (priority
!= DEFAULT_INIT_PRIORITY
)
27513 sprintf (buf
, ".dtors.%.5u",
27514 /* Invert the numbering so the linker puts us in the proper
27515 order; constructors are run from right to left, and the
27516 linker sorts in increasing order. */
27517 MAX_INIT_PRIORITY
- priority
);
27521 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
27522 assemble_align (POINTER_SIZE
);
27524 if (TARGET_RELOCATABLE
)
27526 fputs ("\t.long (", asm_out_file
);
27527 output_addr_const (asm_out_file
, symbol
);
27528 fputs (")@fixup\n", asm_out_file
);
27531 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
27535 rs6000_elf_declare_function_name (FILE *file
, const char *name
, tree decl
)
27539 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file
);
27540 ASM_OUTPUT_LABEL (file
, name
);
27541 fputs (DOUBLE_INT_ASM_OP
, file
);
27542 rs6000_output_function_entry (file
, name
);
27543 fputs (",.TOC.@tocbase,0\n\t.previous\n", file
);
27546 fputs ("\t.size\t", file
);
27547 assemble_name (file
, name
);
27548 fputs (",24\n\t.type\t.", file
);
27549 assemble_name (file
, name
);
27550 fputs (",@function\n", file
);
27551 if (TREE_PUBLIC (decl
) && ! DECL_WEAK (decl
))
27553 fputs ("\t.globl\t.", file
);
27554 assemble_name (file
, name
);
27559 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
27560 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
27561 rs6000_output_function_entry (file
, name
);
27562 fputs (":\n", file
);
27566 if (TARGET_RELOCATABLE
27567 && !TARGET_SECURE_PLT
27568 && (get_pool_size () != 0 || crtl
->profile
)
27573 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
27575 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
27576 fprintf (file
, "\t.long ");
27577 assemble_name (file
, buf
);
27579 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
27580 assemble_name (file
, buf
);
27584 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
27585 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
27587 if (DEFAULT_ABI
== ABI_AIX
)
27589 const char *desc_name
, *orig_name
;
27591 orig_name
= (*targetm
.strip_name_encoding
) (name
);
27592 desc_name
= orig_name
;
27593 while (*desc_name
== '.')
27596 if (TREE_PUBLIC (decl
))
27597 fprintf (file
, "\t.globl %s\n", desc_name
);
27599 fprintf (file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
27600 fprintf (file
, "%s:\n", desc_name
);
27601 fprintf (file
, "\t.long %s\n", orig_name
);
27602 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file
);
27603 if (DEFAULT_ABI
== ABI_AIX
)
27604 fputs ("\t.long 0\n", file
);
27605 fprintf (file
, "\t.previous\n");
27607 ASM_OUTPUT_LABEL (file
, name
);
27610 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED
;
27612 rs6000_elf_file_end (void)
27614 #ifdef HAVE_AS_GNU_ATTRIBUTE
27615 if (TARGET_32BIT
&& DEFAULT_ABI
== ABI_V4
)
27617 if (rs6000_passes_float
)
27618 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n",
27619 ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
) ? 1
27620 : (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_SINGLE_FLOAT
) ? 3
27622 if (rs6000_passes_vector
)
27623 fprintf (asm_out_file
, "\t.gnu_attribute 8, %d\n",
27624 (TARGET_ALTIVEC_ABI
? 2
27625 : TARGET_SPE_ABI
? 3
27627 if (rs6000_returns_struct
)
27628 fprintf (asm_out_file
, "\t.gnu_attribute 12, %d\n",
27629 aix_struct_return
? 2 : 1);
27632 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
27634 file_end_indicate_exec_stack ();
27641 rs6000_xcoff_asm_output_anchor (rtx symbol
)
27645 sprintf (buffer
, "$ + " HOST_WIDE_INT_PRINT_DEC
,
27646 SYMBOL_REF_BLOCK_OFFSET (symbol
));
27647 ASM_OUTPUT_DEF (asm_out_file
, XSTR (symbol
, 0), buffer
);
27651 rs6000_xcoff_asm_globalize_label (FILE *stream
, const char *name
)
27653 fputs (GLOBAL_ASM_OP
, stream
);
27654 RS6000_OUTPUT_BASENAME (stream
, name
);
27655 putc ('\n', stream
);
27658 /* A get_unnamed_decl callback, used for read-only sections. PTR
27659 points to the section string variable. */
27662 rs6000_xcoff_output_readonly_section_asm_op (const void *directive
)
27664 fprintf (asm_out_file
, "\t.csect %s[RO],%s\n",
27665 *(const char *const *) directive
,
27666 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
27669 /* Likewise for read-write sections. */
27672 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive
)
27674 fprintf (asm_out_file
, "\t.csect %s[RW],%s\n",
27675 *(const char *const *) directive
,
27676 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
27680 rs6000_xcoff_output_tls_section_asm_op (const void *directive
)
27682 fprintf (asm_out_file
, "\t.csect %s[TL],%s\n",
27683 *(const char *const *) directive
,
27684 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
27687 /* A get_unnamed_section callback, used for switching to toc_section. */
27690 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
27692 if (TARGET_MINIMAL_TOC
)
27694 /* toc_section is always selected at least once from
27695 rs6000_xcoff_file_start, so this is guaranteed to
27696 always be defined once and only once in each file. */
27697 if (!toc_initialized
)
27699 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file
);
27700 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file
);
27701 toc_initialized
= 1;
27703 fprintf (asm_out_file
, "\t.csect toc_table[RW]%s\n",
27704 (TARGET_32BIT
? "" : ",3"));
27707 fputs ("\t.toc\n", asm_out_file
);
27710 /* Implement TARGET_ASM_INIT_SECTIONS. */
27713 rs6000_xcoff_asm_init_sections (void)
27715 read_only_data_section
27716 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
27717 &xcoff_read_only_section_name
);
27719 private_data_section
27720 = get_unnamed_section (SECTION_WRITE
,
27721 rs6000_xcoff_output_readwrite_section_asm_op
,
27722 &xcoff_private_data_section_name
);
27725 = get_unnamed_section (SECTION_TLS
,
27726 rs6000_xcoff_output_tls_section_asm_op
,
27727 &xcoff_tls_data_section_name
);
27729 tls_private_data_section
27730 = get_unnamed_section (SECTION_TLS
,
27731 rs6000_xcoff_output_tls_section_asm_op
,
27732 &xcoff_private_data_section_name
);
27734 read_only_private_data_section
27735 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
27736 &xcoff_private_data_section_name
);
27739 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op
, NULL
);
27741 readonly_data_section
= read_only_data_section
;
27742 exception_section
= data_section
;
27746 rs6000_xcoff_reloc_rw_mask (void)
27752 rs6000_xcoff_asm_named_section (const char *name
, unsigned int flags
,
27753 tree decl ATTRIBUTE_UNUSED
)
27756 static const char * const suffix
[4] = { "PR", "RO", "RW", "TL" };
27758 if (flags
& SECTION_CODE
)
27760 else if (flags
& SECTION_TLS
)
27762 else if (flags
& SECTION_WRITE
)
27767 fprintf (asm_out_file
, "\t.csect %s%s[%s],%u\n",
27768 (flags
& SECTION_CODE
) ? "." : "",
27769 name
, suffix
[smclass
], flags
& SECTION_ENTSIZE
);
27773 rs6000_xcoff_select_section (tree decl
, int reloc
,
27774 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
27776 if (decl_readonly_section (decl
, reloc
))
27778 if (TREE_PUBLIC (decl
))
27779 return read_only_data_section
;
27781 return read_only_private_data_section
;
27786 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
27788 if (TREE_PUBLIC (decl
))
27789 return tls_data_section
;
27790 else if (bss_initializer_p (decl
))
27792 /* Convert to COMMON to emit in BSS. */
27793 DECL_COMMON (decl
) = 1;
27794 return tls_comm_section
;
27797 return tls_private_data_section
;
27801 if (TREE_PUBLIC (decl
))
27802 return data_section
;
27804 return private_data_section
;
27809 rs6000_xcoff_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
27813 /* Use select_section for private and uninitialized data. */
27814 if (!TREE_PUBLIC (decl
)
27815 || DECL_COMMON (decl
)
27816 || DECL_INITIAL (decl
) == NULL_TREE
27817 || DECL_INITIAL (decl
) == error_mark_node
27818 || (flag_zero_initialized_in_bss
27819 && initializer_zerop (DECL_INITIAL (decl
))))
27822 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
27823 name
= (*targetm
.strip_name_encoding
) (name
);
27824 DECL_SECTION_NAME (decl
) = build_string (strlen (name
), name
);
27827 /* Select section for constant in constant pool.
27829 On RS/6000, all constants are in the private read-only data area.
27830 However, if this is being placed in the TOC it must be output as a
27834 rs6000_xcoff_select_rtx_section (enum machine_mode mode
, rtx x
,
27835 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
27837 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
27838 return toc_section
;
27840 return read_only_private_data_section
;
27843 /* Remove any trailing [DS] or the like from the symbol name. */
27845 static const char *
27846 rs6000_xcoff_strip_name_encoding (const char *name
)
27851 len
= strlen (name
);
27852 if (name
[len
- 1] == ']')
27853 return ggc_alloc_string (name
, len
- 4);
27858 /* Section attributes. AIX is always PIC. */
27860 static unsigned int
27861 rs6000_xcoff_section_type_flags (tree decl
, const char *name
, int reloc
)
27863 unsigned int align
;
27864 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
27866 /* Align to at least UNIT size. */
27867 if ((flags
& SECTION_CODE
) != 0 || !decl
|| !DECL_P (decl
))
27868 align
= MIN_UNITS_PER_WORD
;
27870 /* Increase alignment of large objects if not already stricter. */
27871 align
= MAX ((DECL_ALIGN (decl
) / BITS_PER_UNIT
),
27872 int_size_in_bytes (TREE_TYPE (decl
)) > MIN_UNITS_PER_WORD
27873 ? UNITS_PER_FP_WORD
: MIN_UNITS_PER_WORD
);
27875 return flags
| (exact_log2 (align
) & SECTION_ENTSIZE
);
27878 /* Output at beginning of assembler file.
27880 Initialize the section names for the RS/6000 at this point.
27882 Specify filename, including full path, to assembler.
27884 We want to go into the TOC section so at least one .toc will be emitted.
27885 Also, in order to output proper .bs/.es pairs, we need at least one static
27886 [RW] section emitted.
27888 Finally, declare mcount when profiling to make the assembler happy. */
27891 rs6000_xcoff_file_start (void)
27893 rs6000_gen_section_name (&xcoff_bss_section_name
,
27894 main_input_filename
, ".bss_");
27895 rs6000_gen_section_name (&xcoff_private_data_section_name
,
27896 main_input_filename
, ".rw_");
27897 rs6000_gen_section_name (&xcoff_read_only_section_name
,
27898 main_input_filename
, ".ro_");
27899 rs6000_gen_section_name (&xcoff_tls_data_section_name
,
27900 main_input_filename
, ".tls_");
27901 rs6000_gen_section_name (&xcoff_tbss_section_name
,
27902 main_input_filename
, ".tbss_[UL]");
27904 fputs ("\t.file\t", asm_out_file
);
27905 output_quoted_string (asm_out_file
, main_input_filename
);
27906 fputc ('\n', asm_out_file
);
27907 if (write_symbols
!= NO_DEBUG
)
27908 switch_to_section (private_data_section
);
27909 switch_to_section (text_section
);
27911 fprintf (asm_out_file
, "\t.extern %s\n", RS6000_MCOUNT
);
27912 rs6000_file_start ();
27915 /* Output at end of assembler file.
27916 On the RS/6000, referencing data should automatically pull in text. */
27919 rs6000_xcoff_file_end (void)
27921 switch_to_section (text_section
);
27922 fputs ("_section_.text:\n", asm_out_file
);
27923 switch_to_section (data_section
);
27924 fputs (TARGET_32BIT
27925 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
27931 rs6000_xcoff_encode_section_info (tree decl
, rtx rtl
, int first
)
27936 default_encode_section_info (decl
, rtl
, first
);
27938 /* Careful not to prod global register variables. */
27941 symbol
= XEXP (rtl
, 0);
27942 if (GET_CODE (symbol
) != SYMBOL_REF
)
27945 flags
= SYMBOL_REF_FLAGS (symbol
);
27947 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
27948 flags
&= ~SYMBOL_FLAG_HAS_BLOCK_INFO
;
27950 SYMBOL_REF_FLAGS (symbol
) = flags
;
27952 #endif /* HAVE_AS_TLS */
27953 #endif /* TARGET_XCOFF */
27955 /* Compute a (partial) cost for rtx X. Return true if the complete
27956 cost has been computed, and false if subexpressions should be
27957 scanned. In either case, *TOTAL contains the cost result. */
27960 rs6000_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
27961 int *total
, bool speed
)
27963 enum machine_mode mode
= GET_MODE (x
);
27967 /* On the RS/6000, if it is valid in the insn, it is free. */
27969 if (((outer_code
== SET
27970 || outer_code
== PLUS
27971 || outer_code
== MINUS
)
27972 && (satisfies_constraint_I (x
)
27973 || satisfies_constraint_L (x
)))
27974 || (outer_code
== AND
27975 && (satisfies_constraint_K (x
)
27977 ? satisfies_constraint_L (x
)
27978 : satisfies_constraint_J (x
))
27979 || mask_operand (x
, mode
)
27981 && mask64_operand (x
, DImode
))))
27982 || ((outer_code
== IOR
|| outer_code
== XOR
)
27983 && (satisfies_constraint_K (x
)
27985 ? satisfies_constraint_L (x
)
27986 : satisfies_constraint_J (x
))))
27987 || outer_code
== ASHIFT
27988 || outer_code
== ASHIFTRT
27989 || outer_code
== LSHIFTRT
27990 || outer_code
== ROTATE
27991 || outer_code
== ROTATERT
27992 || outer_code
== ZERO_EXTRACT
27993 || (outer_code
== MULT
27994 && satisfies_constraint_I (x
))
27995 || ((outer_code
== DIV
|| outer_code
== UDIV
27996 || outer_code
== MOD
|| outer_code
== UMOD
)
27997 && exact_log2 (INTVAL (x
)) >= 0)
27998 || (outer_code
== COMPARE
27999 && (satisfies_constraint_I (x
)
28000 || satisfies_constraint_K (x
)))
28001 || ((outer_code
== EQ
|| outer_code
== NE
)
28002 && (satisfies_constraint_I (x
)
28003 || satisfies_constraint_K (x
)
28005 ? satisfies_constraint_L (x
)
28006 : satisfies_constraint_J (x
))))
28007 || (outer_code
== GTU
28008 && satisfies_constraint_I (x
))
28009 || (outer_code
== LTU
28010 && satisfies_constraint_P (x
)))
28015 else if ((outer_code
== PLUS
28016 && reg_or_add_cint_operand (x
, VOIDmode
))
28017 || (outer_code
== MINUS
28018 && reg_or_sub_cint_operand (x
, VOIDmode
))
28019 || ((outer_code
== SET
28020 || outer_code
== IOR
28021 || outer_code
== XOR
)
28023 & ~ (unsigned HOST_WIDE_INT
) 0xffffffff) == 0))
28025 *total
= COSTS_N_INSNS (1);
28031 case CONST_WIDE_INT
:
28036 /* When optimizing for size, MEM should be slightly more expensive
28037 than generating address, e.g., (plus (reg) (const)).
28038 L1 cache latency is about two instructions. */
28039 *total
= !speed
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
28048 if (FLOAT_MODE_P (mode
))
28049 *total
= rs6000_cost
->fp
;
28051 *total
= COSTS_N_INSNS (1);
28055 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
28056 && satisfies_constraint_I (XEXP (x
, 1)))
28058 if (INTVAL (XEXP (x
, 1)) >= -256
28059 && INTVAL (XEXP (x
, 1)) <= 255)
28060 *total
= rs6000_cost
->mulsi_const9
;
28062 *total
= rs6000_cost
->mulsi_const
;
28064 else if (mode
== SFmode
)
28065 *total
= rs6000_cost
->fp
;
28066 else if (FLOAT_MODE_P (mode
))
28067 *total
= rs6000_cost
->dmul
;
28068 else if (mode
== DImode
)
28069 *total
= rs6000_cost
->muldi
;
28071 *total
= rs6000_cost
->mulsi
;
28075 if (mode
== SFmode
)
28076 *total
= rs6000_cost
->fp
;
28078 *total
= rs6000_cost
->dmul
;
28083 if (FLOAT_MODE_P (mode
))
28085 *total
= mode
== DFmode
? rs6000_cost
->ddiv
28086 : rs6000_cost
->sdiv
;
28093 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
28094 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
28096 if (code
== DIV
|| code
== MOD
)
28098 *total
= COSTS_N_INSNS (2);
28101 *total
= COSTS_N_INSNS (1);
28105 if (GET_MODE (XEXP (x
, 1)) == DImode
)
28106 *total
= rs6000_cost
->divdi
;
28108 *total
= rs6000_cost
->divsi
;
28110 /* Add in shift and subtract for MOD. */
28111 if (code
== MOD
|| code
== UMOD
)
28112 *total
+= COSTS_N_INSNS (2);
28117 *total
= COSTS_N_INSNS (4);
28121 *total
= COSTS_N_INSNS (TARGET_POPCNTD
? 1 : 6);
28125 *total
= COSTS_N_INSNS (TARGET_CMPB
? 2 : 6);
28129 if (outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
28141 *total
= COSTS_N_INSNS (1);
28149 /* Handle mul_highpart. */
28150 if (outer_code
== TRUNCATE
28151 && GET_CODE (XEXP (x
, 0)) == MULT
)
28153 if (mode
== DImode
)
28154 *total
= rs6000_cost
->muldi
;
28156 *total
= rs6000_cost
->mulsi
;
28159 else if (outer_code
== AND
)
28162 *total
= COSTS_N_INSNS (1);
28167 if (GET_CODE (XEXP (x
, 0)) == MEM
)
28170 *total
= COSTS_N_INSNS (1);
28176 if (!FLOAT_MODE_P (mode
))
28178 *total
= COSTS_N_INSNS (1);
28184 case UNSIGNED_FLOAT
:
28187 case FLOAT_TRUNCATE
:
28188 *total
= rs6000_cost
->fp
;
28192 if (mode
== DFmode
)
28195 *total
= rs6000_cost
->fp
;
28199 switch (XINT (x
, 1))
28202 *total
= rs6000_cost
->fp
;
28214 *total
= COSTS_N_INSNS (1);
28217 else if (FLOAT_MODE_P (mode
)
28218 && TARGET_PPC_GFXOPT
&& TARGET_HARD_FLOAT
&& TARGET_FPRS
)
28220 *total
= rs6000_cost
->fp
;
28228 /* Carry bit requires mode == Pmode.
28229 NEG or PLUS already counted so only add one. */
28231 && (outer_code
== NEG
|| outer_code
== PLUS
))
28233 *total
= COSTS_N_INSNS (1);
28236 if (outer_code
== SET
)
28238 if (XEXP (x
, 1) == const0_rtx
)
28240 if (TARGET_ISEL
&& !TARGET_MFCRF
)
28241 *total
= COSTS_N_INSNS (8);
28243 *total
= COSTS_N_INSNS (2);
28246 else if (mode
== Pmode
)
28248 *total
= COSTS_N_INSNS (3);
28257 if (outer_code
== SET
&& (XEXP (x
, 1) == const0_rtx
))
28259 if (TARGET_ISEL
&& !TARGET_MFCRF
)
28260 *total
= COSTS_N_INSNS (8);
28262 *total
= COSTS_N_INSNS (2);
28266 if (outer_code
== COMPARE
)
28280 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
28283 rs6000_debug_rtx_costs (rtx x
, int code
, int outer_code
, int opno
, int *total
,
28286 bool ret
= rs6000_rtx_costs (x
, code
, outer_code
, opno
, total
, speed
);
28289 "\nrs6000_rtx_costs, return = %s, code = %s, outer_code = %s, "
28290 "opno = %d, total = %d, speed = %s, x:\n",
28291 ret
? "complete" : "scan inner",
28292 GET_RTX_NAME (code
),
28293 GET_RTX_NAME (outer_code
),
28296 speed
? "true" : "false");
28303 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
28306 rs6000_debug_address_cost (rtx x
, enum machine_mode mode
,
28307 addr_space_t as
, bool speed
)
28309 int ret
= TARGET_ADDRESS_COST (x
, mode
, as
, speed
);
28311 fprintf (stderr
, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
28312 ret
, speed
? "true" : "false");
28319 /* A C expression returning the cost of moving data from a register of class
28320 CLASS1 to one of CLASS2. */
28323 rs6000_register_move_cost (enum machine_mode mode
,
28324 reg_class_t from
, reg_class_t to
)
28328 if (TARGET_DEBUG_COST
)
28331 /* Moves from/to GENERAL_REGS. */
28332 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
28333 || reg_classes_intersect_p (from
, GENERAL_REGS
))
28335 reg_class_t rclass
= from
;
28337 if (! reg_classes_intersect_p (to
, GENERAL_REGS
))
28340 if (rclass
== FLOAT_REGS
|| rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
28341 ret
= (rs6000_memory_move_cost (mode
, rclass
, false)
28342 + rs6000_memory_move_cost (mode
, GENERAL_REGS
, false));
28344 /* It's more expensive to move CR_REGS than CR0_REGS because of the
28346 else if (rclass
== CR_REGS
)
28349 /* For those processors that have slow LR/CTR moves, make them more
28350 expensive than memory in order to bias spills to memory .*/
28351 else if ((rs6000_cpu
== PROCESSOR_POWER6
28352 || rs6000_cpu
== PROCESSOR_POWER7
28353 || rs6000_cpu
== PROCESSOR_POWER8
)
28354 && reg_classes_intersect_p (rclass
, LINK_OR_CTR_REGS
))
28355 ret
= 6 * hard_regno_nregs
[0][mode
];
28358 /* A move will cost one instruction per GPR moved. */
28359 ret
= 2 * hard_regno_nregs
[0][mode
];
28362 /* If we have VSX, we can easily move between FPR or Altivec registers. */
28363 else if (VECTOR_MEM_VSX_P (mode
)
28364 && reg_classes_intersect_p (to
, VSX_REGS
)
28365 && reg_classes_intersect_p (from
, VSX_REGS
))
28366 ret
= 2 * hard_regno_nregs
[32][mode
];
28368 /* Moving between two similar registers is just one instruction. */
28369 else if (reg_classes_intersect_p (to
, from
))
28370 ret
= (mode
== TFmode
|| mode
== TDmode
) ? 4 : 2;
28372 /* Everything else has to go through GENERAL_REGS. */
28374 ret
= (rs6000_register_move_cost (mode
, GENERAL_REGS
, to
)
28375 + rs6000_register_move_cost (mode
, from
, GENERAL_REGS
));
28377 if (TARGET_DEBUG_COST
)
28379 if (dbg_cost_ctrl
== 1)
28381 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
28382 ret
, GET_MODE_NAME (mode
), reg_class_names
[from
],
28383 reg_class_names
[to
]);
28390 /* A C expressions returning the cost of moving data of MODE from a register to
28394 rs6000_memory_move_cost (enum machine_mode mode
, reg_class_t rclass
,
28395 bool in ATTRIBUTE_UNUSED
)
28399 if (TARGET_DEBUG_COST
)
28402 if (reg_classes_intersect_p (rclass
, GENERAL_REGS
))
28403 ret
= 4 * hard_regno_nregs
[0][mode
];
28404 else if ((reg_classes_intersect_p (rclass
, FLOAT_REGS
)
28405 || reg_classes_intersect_p (rclass
, VSX_REGS
)))
28406 ret
= 4 * hard_regno_nregs
[32][mode
];
28407 else if (reg_classes_intersect_p (rclass
, ALTIVEC_REGS
))
28408 ret
= 4 * hard_regno_nregs
[FIRST_ALTIVEC_REGNO
][mode
];
28410 ret
= 4 + rs6000_register_move_cost (mode
, rclass
, GENERAL_REGS
);
28412 if (TARGET_DEBUG_COST
)
28414 if (dbg_cost_ctrl
== 1)
28416 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
28417 ret
, GET_MODE_NAME (mode
), reg_class_names
[rclass
], in
);
28424 /* Returns a code for a target-specific builtin that implements
28425 reciprocal of the function, or NULL_TREE if not available. */
28428 rs6000_builtin_reciprocal (unsigned int fn
, bool md_fn
,
28429 bool sqrt ATTRIBUTE_UNUSED
)
28431 if (optimize_insn_for_size_p ())
28437 case VSX_BUILTIN_XVSQRTDP
:
28438 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode
))
28441 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
28443 case VSX_BUILTIN_XVSQRTSP
:
28444 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode
))
28447 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_4SF
];
28456 case BUILT_IN_SQRT
:
28457 if (!RS6000_RECIP_AUTO_RSQRTE_P (DFmode
))
28460 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRT
];
28462 case BUILT_IN_SQRTF
:
28463 if (!RS6000_RECIP_AUTO_RSQRTE_P (SFmode
))
28466 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRTF
];
28473 /* Load up a constant. If the mode is a vector mode, splat the value across
28474 all of the vector elements. */
28477 rs6000_load_constant_and_splat (enum machine_mode mode
, REAL_VALUE_TYPE dconst
)
28481 if (mode
== SFmode
|| mode
== DFmode
)
28483 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, mode
);
28484 reg
= force_reg (mode
, d
);
28486 else if (mode
== V4SFmode
)
28488 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, SFmode
);
28489 rtvec v
= gen_rtvec (4, d
, d
, d
, d
);
28490 reg
= gen_reg_rtx (mode
);
28491 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
28493 else if (mode
== V2DFmode
)
28495 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, DFmode
);
28496 rtvec v
= gen_rtvec (2, d
, d
);
28497 reg
= gen_reg_rtx (mode
);
28498 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
28501 gcc_unreachable ();
28506 /* Generate an FMA instruction. */
28509 rs6000_emit_madd (rtx target
, rtx m1
, rtx m2
, rtx a
)
28511 enum machine_mode mode
= GET_MODE (target
);
28514 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
28515 gcc_assert (dst
!= NULL
);
28518 emit_move_insn (target
, dst
);
28521 /* Generate a FMSUB instruction: dst = fma(m1, m2, -a). */
28524 rs6000_emit_msub (rtx target
, rtx m1
, rtx m2
, rtx a
)
28526 enum machine_mode mode
= GET_MODE (target
);
28529 /* Altivec does not support fms directly;
28530 generate in terms of fma in that case. */
28531 if (optab_handler (fms_optab
, mode
) != CODE_FOR_nothing
)
28532 dst
= expand_ternary_op (mode
, fms_optab
, m1
, m2
, a
, target
, 0);
28535 a
= expand_unop (mode
, neg_optab
, a
, NULL_RTX
, 0);
28536 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
28538 gcc_assert (dst
!= NULL
);
28541 emit_move_insn (target
, dst
);
28544 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
28547 rs6000_emit_nmsub (rtx dst
, rtx m1
, rtx m2
, rtx a
)
28549 enum machine_mode mode
= GET_MODE (dst
);
28552 /* This is a tad more complicated, since the fnma_optab is for
28553 a different expression: fma(-m1, m2, a), which is the same
28554 thing except in the case of signed zeros.
28556 Fortunately we know that if FMA is supported that FNMSUB is
28557 also supported in the ISA. Just expand it directly. */
28559 gcc_assert (optab_handler (fma_optab
, mode
) != CODE_FOR_nothing
);
28561 r
= gen_rtx_NEG (mode
, a
);
28562 r
= gen_rtx_FMA (mode
, m1
, m2
, r
);
28563 r
= gen_rtx_NEG (mode
, r
);
28564 emit_insn (gen_rtx_SET (VOIDmode
, dst
, r
));
28567 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
28568 add a reg_note saying that this was a division. Support both scalar and
28569 vector divide. Assumes no trapping math and finite arguments. */
28572 rs6000_emit_swdiv (rtx dst
, rtx n
, rtx d
, bool note_p
)
28574 enum machine_mode mode
= GET_MODE (dst
);
28575 rtx one
, x0
, e0
, x1
, xprev
, eprev
, xnext
, enext
, u
, v
;
28578 /* Low precision estimates guarantee 5 bits of accuracy. High
28579 precision estimates guarantee 14 bits of accuracy. SFmode
28580 requires 23 bits of accuracy. DFmode requires 52 bits of
28581 accuracy. Each pass at least doubles the accuracy, leading
28582 to the following. */
28583 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
28584 if (mode
== DFmode
|| mode
== V2DFmode
)
28587 enum insn_code code
= optab_handler (smul_optab
, mode
);
28588 insn_gen_fn gen_mul
= GEN_FCN (code
);
28590 gcc_assert (code
!= CODE_FOR_nothing
);
28592 one
= rs6000_load_constant_and_splat (mode
, dconst1
);
28594 /* x0 = 1./d estimate */
28595 x0
= gen_reg_rtx (mode
);
28596 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
28597 gen_rtx_UNSPEC (mode
, gen_rtvec (1, d
),
28600 /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
28603 /* e0 = 1. - d * x0 */
28604 e0
= gen_reg_rtx (mode
);
28605 rs6000_emit_nmsub (e0
, d
, x0
, one
);
28607 /* x1 = x0 + e0 * x0 */
28608 x1
= gen_reg_rtx (mode
);
28609 rs6000_emit_madd (x1
, e0
, x0
, x0
);
28611 for (i
= 0, xprev
= x1
, eprev
= e0
; i
< passes
- 2;
28612 ++i
, xprev
= xnext
, eprev
= enext
) {
28614 /* enext = eprev * eprev */
28615 enext
= gen_reg_rtx (mode
);
28616 emit_insn (gen_mul (enext
, eprev
, eprev
));
28618 /* xnext = xprev + enext * xprev */
28619 xnext
= gen_reg_rtx (mode
);
28620 rs6000_emit_madd (xnext
, enext
, xprev
, xprev
);
28626 /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
28628 /* u = n * xprev */
28629 u
= gen_reg_rtx (mode
);
28630 emit_insn (gen_mul (u
, n
, xprev
));
28632 /* v = n - (d * u) */
28633 v
= gen_reg_rtx (mode
);
28634 rs6000_emit_nmsub (v
, d
, u
, n
);
28636 /* dst = (v * xprev) + u */
28637 rs6000_emit_madd (dst
, v
, xprev
, u
);
28640 add_reg_note (get_last_insn (), REG_EQUAL
, gen_rtx_DIV (mode
, n
, d
));
28643 /* Newton-Raphson approximation of single/double-precision floating point
28644 rsqrt. Assumes no trapping math and finite arguments. */
28647 rs6000_emit_swrsqrt (rtx dst
, rtx src
)
28649 enum machine_mode mode
= GET_MODE (src
);
28650 rtx x0
= gen_reg_rtx (mode
);
28651 rtx y
= gen_reg_rtx (mode
);
28653 /* Low precision estimates guarantee 5 bits of accuracy. High
28654 precision estimates guarantee 14 bits of accuracy. SFmode
28655 requires 23 bits of accuracy. DFmode requires 52 bits of
28656 accuracy. Each pass at least doubles the accuracy, leading
28657 to the following. */
28658 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
28659 if (mode
== DFmode
|| mode
== V2DFmode
)
28662 REAL_VALUE_TYPE dconst3_2
;
28665 enum insn_code code
= optab_handler (smul_optab
, mode
);
28666 insn_gen_fn gen_mul
= GEN_FCN (code
);
28668 gcc_assert (code
!= CODE_FOR_nothing
);
28670 /* Load up the constant 1.5 either as a scalar, or as a vector. */
28671 real_from_integer (&dconst3_2
, VOIDmode
, 3, SIGNED
);
28672 SET_REAL_EXP (&dconst3_2
, REAL_EXP (&dconst3_2
) - 1);
28674 halfthree
= rs6000_load_constant_and_splat (mode
, dconst3_2
);
28676 /* x0 = rsqrt estimate */
28677 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
28678 gen_rtx_UNSPEC (mode
, gen_rtvec (1, src
),
28681 /* y = 0.5 * src = 1.5 * src - src -> fewer constants */
28682 rs6000_emit_msub (y
, src
, halfthree
, src
);
28684 for (i
= 0; i
< passes
; i
++)
28686 rtx x1
= gen_reg_rtx (mode
);
28687 rtx u
= gen_reg_rtx (mode
);
28688 rtx v
= gen_reg_rtx (mode
);
28690 /* x1 = x0 * (1.5 - y * (x0 * x0)) */
28691 emit_insn (gen_mul (u
, x0
, x0
));
28692 rs6000_emit_nmsub (v
, y
, u
, halfthree
);
28693 emit_insn (gen_mul (x1
, x0
, v
));
28697 emit_move_insn (dst
, x0
);
28701 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
28702 (Power7) targets. DST is the target, and SRC is the argument operand. */
28705 rs6000_emit_popcount (rtx dst
, rtx src
)
28707 enum machine_mode mode
= GET_MODE (dst
);
28710 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
28711 if (TARGET_POPCNTD
)
28713 if (mode
== SImode
)
28714 emit_insn (gen_popcntdsi2 (dst
, src
));
28716 emit_insn (gen_popcntddi2 (dst
, src
));
28720 tmp1
= gen_reg_rtx (mode
);
28722 if (mode
== SImode
)
28724 emit_insn (gen_popcntbsi2 (tmp1
, src
));
28725 tmp2
= expand_mult (SImode
, tmp1
, GEN_INT (0x01010101),
28727 tmp2
= force_reg (SImode
, tmp2
);
28728 emit_insn (gen_lshrsi3 (dst
, tmp2
, GEN_INT (24)));
28732 emit_insn (gen_popcntbdi2 (tmp1
, src
));
28733 tmp2
= expand_mult (DImode
, tmp1
,
28734 GEN_INT ((HOST_WIDE_INT
)
28735 0x01010101 << 32 | 0x01010101),
28737 tmp2
= force_reg (DImode
, tmp2
);
28738 emit_insn (gen_lshrdi3 (dst
, tmp2
, GEN_INT (56)));
28743 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
28744 target, and SRC is the argument operand. */
28747 rs6000_emit_parity (rtx dst
, rtx src
)
28749 enum machine_mode mode
= GET_MODE (dst
);
28752 tmp
= gen_reg_rtx (mode
);
28754 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
28757 if (mode
== SImode
)
28759 emit_insn (gen_popcntbsi2 (tmp
, src
));
28760 emit_insn (gen_paritysi2_cmpb (dst
, tmp
));
28764 emit_insn (gen_popcntbdi2 (tmp
, src
));
28765 emit_insn (gen_paritydi2_cmpb (dst
, tmp
));
28770 if (mode
== SImode
)
28772 /* Is mult+shift >= shift+xor+shift+xor? */
28773 if (rs6000_cost
->mulsi_const
>= COSTS_N_INSNS (3))
28775 rtx tmp1
, tmp2
, tmp3
, tmp4
;
28777 tmp1
= gen_reg_rtx (SImode
);
28778 emit_insn (gen_popcntbsi2 (tmp1
, src
));
28780 tmp2
= gen_reg_rtx (SImode
);
28781 emit_insn (gen_lshrsi3 (tmp2
, tmp1
, GEN_INT (16)));
28782 tmp3
= gen_reg_rtx (SImode
);
28783 emit_insn (gen_xorsi3 (tmp3
, tmp1
, tmp2
));
28785 tmp4
= gen_reg_rtx (SImode
);
28786 emit_insn (gen_lshrsi3 (tmp4
, tmp3
, GEN_INT (8)));
28787 emit_insn (gen_xorsi3 (tmp
, tmp3
, tmp4
));
28790 rs6000_emit_popcount (tmp
, src
);
28791 emit_insn (gen_andsi3 (dst
, tmp
, const1_rtx
));
28795 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
28796 if (rs6000_cost
->muldi
>= COSTS_N_INSNS (5))
28798 rtx tmp1
, tmp2
, tmp3
, tmp4
, tmp5
, tmp6
;
28800 tmp1
= gen_reg_rtx (DImode
);
28801 emit_insn (gen_popcntbdi2 (tmp1
, src
));
28803 tmp2
= gen_reg_rtx (DImode
);
28804 emit_insn (gen_lshrdi3 (tmp2
, tmp1
, GEN_INT (32)));
28805 tmp3
= gen_reg_rtx (DImode
);
28806 emit_insn (gen_xordi3 (tmp3
, tmp1
, tmp2
));
28808 tmp4
= gen_reg_rtx (DImode
);
28809 emit_insn (gen_lshrdi3 (tmp4
, tmp3
, GEN_INT (16)));
28810 tmp5
= gen_reg_rtx (DImode
);
28811 emit_insn (gen_xordi3 (tmp5
, tmp3
, tmp4
));
28813 tmp6
= gen_reg_rtx (DImode
);
28814 emit_insn (gen_lshrdi3 (tmp6
, tmp5
, GEN_INT (8)));
28815 emit_insn (gen_xordi3 (tmp
, tmp5
, tmp6
));
28818 rs6000_emit_popcount (tmp
, src
);
28819 emit_insn (gen_anddi3 (dst
, tmp
, const1_rtx
));
28823 /* Expand an Altivec constant permutation for little endian mode.
28824 There are two issues: First, the two input operands must be
28825 swapped so that together they form a double-wide array in LE
28826 order. Second, the vperm instruction has surprising behavior
28827 in LE mode: it interprets the elements of the source vectors
28828 in BE mode ("left to right") and interprets the elements of
28829 the destination vector in LE mode ("right to left"). To
28830 correct for this, we must subtract each element of the permute
28831 control vector from 31.
28833 For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}
28834 with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.
28835 We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to
28836 serve as the permute control vector. Then, in BE mode,
28840 places the desired result in vr9. However, in LE mode the
28841 vector contents will be
28843 vr10 = 00000003 00000002 00000001 00000000
28844 vr11 = 00000007 00000006 00000005 00000004
28846 The result of the vperm using the same permute control vector is
28848 vr9 = 05000000 07000000 01000000 03000000
28850 That is, the leftmost 4 bytes of vr10 are interpreted as the
28851 source for the rightmost 4 bytes of vr9, and so on.
28853 If we change the permute control vector to
28855 vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}
28863 vr9 = 00000006 00000004 00000002 00000000. */
28866 altivec_expand_vec_perm_const_le (rtx operands
[4])
28870 rtx constv
, unspec
;
28871 rtx target
= operands
[0];
28872 rtx op0
= operands
[1];
28873 rtx op1
= operands
[2];
28874 rtx sel
= operands
[3];
28876 /* Unpack and adjust the constant selector. */
28877 for (i
= 0; i
< 16; ++i
)
28879 rtx e
= XVECEXP (sel
, 0, i
);
28880 unsigned int elt
= 31 - (INTVAL (e
) & 31);
28881 perm
[i
] = GEN_INT (elt
);
28884 /* Expand to a permute, swapping the inputs and using the
28885 adjusted selector. */
28887 op0
= force_reg (V16QImode
, op0
);
28889 op1
= force_reg (V16QImode
, op1
);
28891 constv
= gen_rtx_CONST_VECTOR (V16QImode
, gen_rtvec_v (16, perm
));
28892 constv
= force_reg (V16QImode
, constv
);
28893 unspec
= gen_rtx_UNSPEC (V16QImode
, gen_rtvec (3, op1
, op0
, constv
),
28895 if (!REG_P (target
))
28897 rtx tmp
= gen_reg_rtx (V16QImode
);
28898 emit_move_insn (tmp
, unspec
);
28902 emit_move_insn (target
, unspec
);
28905 /* Similarly to altivec_expand_vec_perm_const_le, we must adjust the
28906 permute control vector. But here it's not a constant, so we must
28907 generate a vector splat/subtract to do the adjustment. */
28910 altivec_expand_vec_perm_le (rtx operands
[4])
28913 rtx target
= operands
[0];
28914 rtx op0
= operands
[1];
28915 rtx op1
= operands
[2];
28916 rtx sel
= operands
[3];
28919 /* Get everything in regs so the pattern matches. */
28921 op0
= force_reg (V16QImode
, op0
);
28923 op1
= force_reg (V16QImode
, op1
);
28925 sel
= force_reg (V16QImode
, sel
);
28926 if (!REG_P (target
))
28927 tmp
= gen_reg_rtx (V16QImode
);
28929 /* SEL = splat(31) - SEL. */
28930 /* We want to subtract from 31, but we can't vspltisb 31 since
28931 it's out of range. -1 works as well because only the low-order
28932 five bits of the permute control vector elements are used. */
28933 splat
= gen_rtx_VEC_DUPLICATE (V16QImode
,
28934 gen_rtx_CONST_INT (QImode
, -1));
28935 emit_move_insn (tmp
, splat
);
28936 sel
= gen_rtx_MINUS (V16QImode
, tmp
, sel
);
28937 emit_move_insn (tmp
, sel
);
28939 /* Permute with operands reversed and adjusted selector. */
28940 unspec
= gen_rtx_UNSPEC (V16QImode
, gen_rtvec (3, op1
, op0
, tmp
),
28943 /* Copy into target, possibly by way of a register. */
28944 if (!REG_P (target
))
28946 emit_move_insn (tmp
, unspec
);
28950 emit_move_insn (target
, unspec
);
28953 /* Expand an Altivec constant permutation. Return true if we match
28954 an efficient implementation; false to fall back to VPERM. */
28957 altivec_expand_vec_perm_const (rtx operands
[4])
28959 struct altivec_perm_insn
{
28960 HOST_WIDE_INT mask
;
28961 enum insn_code impl
;
28962 unsigned char perm
[16];
28964 static const struct altivec_perm_insn patterns
[] = {
28965 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhum
,
28966 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
28967 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwum
,
28968 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
28969 { OPTION_MASK_ALTIVEC
,
28970 BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghb
: CODE_FOR_altivec_vmrglb
,
28971 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
28972 { OPTION_MASK_ALTIVEC
,
28973 BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghh
: CODE_FOR_altivec_vmrglh
,
28974 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
28975 { OPTION_MASK_ALTIVEC
,
28976 BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghw
: CODE_FOR_altivec_vmrglw
,
28977 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
28978 { OPTION_MASK_ALTIVEC
,
28979 BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglb
: CODE_FOR_altivec_vmrghb
,
28980 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
28981 { OPTION_MASK_ALTIVEC
,
28982 BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglh
: CODE_FOR_altivec_vmrghh
,
28983 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
28984 { OPTION_MASK_ALTIVEC
,
28985 BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglw
: CODE_FOR_altivec_vmrghw
,
28986 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
28987 { OPTION_MASK_P8_VECTOR
, CODE_FOR_p8_vmrgew
,
28988 { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
28989 { OPTION_MASK_P8_VECTOR
, CODE_FOR_p8_vmrgow
,
28990 { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
28993 unsigned int i
, j
, elt
, which
;
28994 unsigned char perm
[16];
28995 rtx target
, op0
, op1
, sel
, x
;
28998 target
= operands
[0];
29003 /* Unpack the constant selector. */
29004 for (i
= which
= 0; i
< 16; ++i
)
29006 rtx e
= XVECEXP (sel
, 0, i
);
29007 elt
= INTVAL (e
) & 31;
29008 which
|= (elt
< 16 ? 1 : 2);
29012 /* Simplify the constant selector based on operands. */
29016 gcc_unreachable ();
29020 if (!rtx_equal_p (op0
, op1
))
29025 for (i
= 0; i
< 16; ++i
)
29037 /* Look for splat patterns. */
29042 for (i
= 0; i
< 16; ++i
)
29043 if (perm
[i
] != elt
)
29047 emit_insn (gen_altivec_vspltb (target
, op0
, GEN_INT (elt
)));
29053 for (i
= 0; i
< 16; i
+= 2)
29054 if (perm
[i
] != elt
|| perm
[i
+ 1] != elt
+ 1)
29058 int field
= BYTES_BIG_ENDIAN
? elt
/ 2 : 7 - elt
/ 2;
29059 x
= gen_reg_rtx (V8HImode
);
29060 emit_insn (gen_altivec_vsplth (x
, gen_lowpart (V8HImode
, op0
),
29062 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
29069 for (i
= 0; i
< 16; i
+= 4)
29071 || perm
[i
+ 1] != elt
+ 1
29072 || perm
[i
+ 2] != elt
+ 2
29073 || perm
[i
+ 3] != elt
+ 3)
29077 int field
= BYTES_BIG_ENDIAN
? elt
/ 4 : 3 - elt
/ 4;
29078 x
= gen_reg_rtx (V4SImode
);
29079 emit_insn (gen_altivec_vspltw (x
, gen_lowpart (V4SImode
, op0
),
29081 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
29087 /* Look for merge and pack patterns. */
29088 for (j
= 0; j
< ARRAY_SIZE (patterns
); ++j
)
29092 if ((patterns
[j
].mask
& rs6000_isa_flags
) == 0)
29095 elt
= patterns
[j
].perm
[0];
29096 if (perm
[0] == elt
)
29098 else if (perm
[0] == elt
+ 16)
29102 for (i
= 1; i
< 16; ++i
)
29104 elt
= patterns
[j
].perm
[i
];
29106 elt
= (elt
>= 16 ? elt
- 16 : elt
+ 16);
29107 else if (one_vec
&& elt
>= 16)
29109 if (perm
[i
] != elt
)
29114 enum insn_code icode
= patterns
[j
].impl
;
29115 enum machine_mode omode
= insn_data
[icode
].operand
[0].mode
;
29116 enum machine_mode imode
= insn_data
[icode
].operand
[1].mode
;
29118 /* For little-endian, don't use vpkuwum and vpkuhum if the
29119 underlying vector type is not V4SI and V8HI, respectively.
29120 For example, using vpkuwum with a V8HI picks up the even
29121 halfwords (BE numbering) when the even halfwords (LE
29122 numbering) are what we need. */
29123 if (!BYTES_BIG_ENDIAN
29124 && icode
== CODE_FOR_altivec_vpkuwum
29125 && ((GET_CODE (op0
) == REG
29126 && GET_MODE (op0
) != V4SImode
)
29127 || (GET_CODE (op0
) == SUBREG
29128 && GET_MODE (XEXP (op0
, 0)) != V4SImode
)))
29130 if (!BYTES_BIG_ENDIAN
29131 && icode
== CODE_FOR_altivec_vpkuhum
29132 && ((GET_CODE (op0
) == REG
29133 && GET_MODE (op0
) != V8HImode
)
29134 || (GET_CODE (op0
) == SUBREG
29135 && GET_MODE (XEXP (op0
, 0)) != V8HImode
)))
29138 /* For little-endian, the two input operands must be swapped
29139 (or swapped back) to ensure proper right-to-left numbering
29141 if (swapped
^ !BYTES_BIG_ENDIAN
)
29142 x
= op0
, op0
= op1
, op1
= x
;
29143 if (imode
!= V16QImode
)
29145 op0
= gen_lowpart (imode
, op0
);
29146 op1
= gen_lowpart (imode
, op1
);
29148 if (omode
== V16QImode
)
29151 x
= gen_reg_rtx (omode
);
29152 emit_insn (GEN_FCN (icode
) (x
, op0
, op1
));
29153 if (omode
!= V16QImode
)
29154 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
29159 if (!BYTES_BIG_ENDIAN
)
29161 altivec_expand_vec_perm_const_le (operands
);
29168 /* Expand a Paired Single, VSX Permute Doubleword, or SPE constant permutation.
29169 Return true if we match an efficient implementation. */
29172 rs6000_expand_vec_perm_const_1 (rtx target
, rtx op0
, rtx op1
,
29173 unsigned char perm0
, unsigned char perm1
)
29177 /* If both selectors come from the same operand, fold to single op. */
29178 if ((perm0
& 2) == (perm1
& 2))
29185 /* If both operands are equal, fold to simpler permutation. */
29186 if (rtx_equal_p (op0
, op1
))
29189 perm1
= (perm1
& 1) + 2;
29191 /* If the first selector comes from the second operand, swap. */
29192 else if (perm0
& 2)
29198 x
= op0
, op0
= op1
, op1
= x
;
29200 /* If the second selector does not come from the second operand, fail. */
29201 else if ((perm1
& 2) == 0)
29205 if (target
!= NULL
)
29207 enum machine_mode vmode
, dmode
;
29210 vmode
= GET_MODE (target
);
29211 gcc_assert (GET_MODE_NUNITS (vmode
) == 2);
29212 dmode
= mode_for_vector (GET_MODE_INNER (vmode
), 4);
29214 x
= gen_rtx_VEC_CONCAT (dmode
, op0
, op1
);
29215 v
= gen_rtvec (2, GEN_INT (perm0
), GEN_INT (perm1
));
29216 x
= gen_rtx_VEC_SELECT (vmode
, x
, gen_rtx_PARALLEL (VOIDmode
, v
));
29217 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
29223 rs6000_expand_vec_perm_const (rtx operands
[4])
29225 rtx target
, op0
, op1
, sel
;
29226 unsigned char perm0
, perm1
;
29228 target
= operands
[0];
29233 /* Unpack the constant selector. */
29234 perm0
= INTVAL (XVECEXP (sel
, 0, 0)) & 3;
29235 perm1
= INTVAL (XVECEXP (sel
, 0, 1)) & 3;
29237 return rs6000_expand_vec_perm_const_1 (target
, op0
, op1
, perm0
, perm1
);
29240 /* Test whether a constant permutation is supported. */
29243 rs6000_vectorize_vec_perm_const_ok (enum machine_mode vmode
,
29244 const unsigned char *sel
)
29246 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
29247 if (TARGET_ALTIVEC
)
29250 /* Check for ps_merge* or evmerge* insns. */
29251 if ((TARGET_PAIRED_FLOAT
&& vmode
== V2SFmode
)
29252 || (TARGET_SPE
&& vmode
== V2SImode
))
29254 rtx op0
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 1);
29255 rtx op1
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 2);
29256 return rs6000_expand_vec_perm_const_1 (NULL
, op0
, op1
, sel
[0], sel
[1]);
29262 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave. */
29265 rs6000_do_expand_vec_perm (rtx target
, rtx op0
, rtx op1
,
29266 enum machine_mode vmode
, unsigned nelt
, rtx perm
[])
29268 enum machine_mode imode
;
29272 if (GET_MODE_CLASS (vmode
) != MODE_VECTOR_INT
)
29274 imode
= GET_MODE_INNER (vmode
);
29275 imode
= mode_for_size (GET_MODE_BITSIZE (imode
), MODE_INT
, 0);
29276 imode
= mode_for_vector (imode
, nelt
);
29279 x
= gen_rtx_CONST_VECTOR (imode
, gen_rtvec_v (nelt
, perm
));
29280 x
= expand_vec_perm (vmode
, op0
, op1
, x
, target
);
29282 emit_move_insn (target
, x
);
29285 /* Expand an extract even operation. */
29288 rs6000_expand_extract_even (rtx target
, rtx op0
, rtx op1
)
29290 enum machine_mode vmode
= GET_MODE (target
);
29291 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
29294 for (i
= 0; i
< nelt
; i
++)
29295 perm
[i
] = GEN_INT (i
* 2);
29297 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
29300 /* Expand a vector interleave operation. */
29303 rs6000_expand_interleave (rtx target
, rtx op0
, rtx op1
, bool highp
)
29305 enum machine_mode vmode
= GET_MODE (target
);
29306 unsigned i
, high
, nelt
= GET_MODE_NUNITS (vmode
);
29309 high
= (highp
== BYTES_BIG_ENDIAN
? 0 : nelt
/ 2);
29310 for (i
= 0; i
< nelt
/ 2; i
++)
29312 perm
[i
* 2] = GEN_INT (i
+ high
);
29313 perm
[i
* 2 + 1] = GEN_INT (i
+ nelt
+ high
);
29316 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
29319 /* Return an RTX representing where to find the function value of a
29320 function returning MODE. */
29322 rs6000_complex_function_value (enum machine_mode mode
)
29324 unsigned int regno
;
29326 enum machine_mode inner
= GET_MODE_INNER (mode
);
29327 unsigned int inner_bytes
= GET_MODE_SIZE (inner
);
29329 if (FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
29330 regno
= FP_ARG_RETURN
;
29333 regno
= GP_ARG_RETURN
;
29335 /* 32-bit is OK since it'll go in r3/r4. */
29336 if (TARGET_32BIT
&& inner_bytes
>= 4)
29337 return gen_rtx_REG (mode
, regno
);
29340 if (inner_bytes
>= 8)
29341 return gen_rtx_REG (mode
, regno
);
29343 r1
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
),
29345 r2
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
+ 1),
29346 GEN_INT (inner_bytes
));
29347 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
29350 /* Target hook for TARGET_FUNCTION_VALUE.
29352 On the SPE, both FPs and vectors are returned in r3.
29354 On RS/6000 an integer value is in r3 and a floating-point value is in
29355 fp1, unless -msoft-float. */
29358 rs6000_function_value (const_tree valtype
,
29359 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
29360 bool outgoing ATTRIBUTE_UNUSED
)
29362 enum machine_mode mode
;
29363 unsigned int regno
;
29365 /* Special handling for structs in darwin64. */
29367 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype
), valtype
))
29369 CUMULATIVE_ARGS valcum
;
29373 valcum
.fregno
= FP_ARG_MIN_REG
;
29374 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
29375 /* Do a trial code generation as if this were going to be passed as
29376 an argument; if any part goes in memory, we return NULL. */
29377 valret
= rs6000_darwin64_record_arg (&valcum
, valtype
, true, /* retval= */ true);
29380 /* Otherwise fall through to standard ABI rules. */
29383 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DImode
)
29385 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
29386 return gen_rtx_PARALLEL (DImode
,
29388 gen_rtx_EXPR_LIST (VOIDmode
,
29389 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
29391 gen_rtx_EXPR_LIST (VOIDmode
,
29392 gen_rtx_REG (SImode
,
29393 GP_ARG_RETURN
+ 1),
29396 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DCmode
)
29398 return gen_rtx_PARALLEL (DCmode
,
29400 gen_rtx_EXPR_LIST (VOIDmode
,
29401 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
29403 gen_rtx_EXPR_LIST (VOIDmode
,
29404 gen_rtx_REG (SImode
,
29405 GP_ARG_RETURN
+ 1),
29407 gen_rtx_EXPR_LIST (VOIDmode
,
29408 gen_rtx_REG (SImode
,
29409 GP_ARG_RETURN
+ 2),
29411 gen_rtx_EXPR_LIST (VOIDmode
,
29412 gen_rtx_REG (SImode
,
29413 GP_ARG_RETURN
+ 3),
29417 mode
= TYPE_MODE (valtype
);
29418 if ((INTEGRAL_TYPE_P (valtype
) && GET_MODE_BITSIZE (mode
) < BITS_PER_WORD
)
29419 || POINTER_TYPE_P (valtype
))
29420 mode
= TARGET_32BIT
? SImode
: DImode
;
29422 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
29423 /* _Decimal128 must use an even/odd register pair. */
29424 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
29425 else if (SCALAR_FLOAT_TYPE_P (valtype
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
29426 && ((TARGET_SINGLE_FLOAT
&& (mode
== SFmode
)) || TARGET_DOUBLE_FLOAT
))
29427 regno
= FP_ARG_RETURN
;
29428 else if (TREE_CODE (valtype
) == COMPLEX_TYPE
29429 && targetm
.calls
.split_complex_arg
)
29430 return rs6000_complex_function_value (mode
);
29431 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
29432 return register is used in both cases, and we won't see V2DImode/V2DFmode
29433 for pure altivec, combine the two cases. */
29434 else if (TREE_CODE (valtype
) == VECTOR_TYPE
29435 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
29436 && ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
29437 regno
= ALTIVEC_ARG_RETURN
;
29438 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
29439 && (mode
== DFmode
|| mode
== DCmode
29440 || mode
== TFmode
|| mode
== TCmode
))
29441 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
29443 regno
= GP_ARG_RETURN
;
29445 return gen_rtx_REG (mode
, regno
);
29448 /* Define how to find the value returned by a library function
29449 assuming the value has mode MODE. */
29451 rs6000_libcall_value (enum machine_mode mode
)
29453 unsigned int regno
;
29455 if (TARGET_32BIT
&& TARGET_POWERPC64
&& mode
== DImode
)
29457 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
29458 return gen_rtx_PARALLEL (DImode
,
29460 gen_rtx_EXPR_LIST (VOIDmode
,
29461 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
29463 gen_rtx_EXPR_LIST (VOIDmode
,
29464 gen_rtx_REG (SImode
,
29465 GP_ARG_RETURN
+ 1),
29469 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
29470 /* _Decimal128 must use an even/odd register pair. */
29471 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
29472 else if (SCALAR_FLOAT_MODE_P (mode
)
29473 && TARGET_HARD_FLOAT
&& TARGET_FPRS
29474 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
) || TARGET_DOUBLE_FLOAT
))
29475 regno
= FP_ARG_RETURN
;
29476 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
29477 return register is used in both cases, and we won't see V2DImode/V2DFmode
29478 for pure altivec, combine the two cases. */
29479 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
29480 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
)
29481 regno
= ALTIVEC_ARG_RETURN
;
29482 else if (COMPLEX_MODE_P (mode
) && targetm
.calls
.split_complex_arg
)
29483 return rs6000_complex_function_value (mode
);
29484 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
29485 && (mode
== DFmode
|| mode
== DCmode
29486 || mode
== TFmode
|| mode
== TCmode
))
29487 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
29489 regno
= GP_ARG_RETURN
;
29491 return gen_rtx_REG (mode
, regno
);
29495 /* Return true if we use LRA instead of reload pass. */
29497 rs6000_lra_p (void)
29499 return rs6000_lra_flag
;
29502 /* Given FROM and TO register numbers, say whether this elimination is allowed.
29503 Frame pointer elimination is automatically handled.
29505 For the RS/6000, if frame pointer elimination is being done, we would like
29506 to convert ap into fp, not sp.
29508 We need r30 if -mminimal-toc was specified, and there are constant pool
29512 rs6000_can_eliminate (const int from
, const int to
)
29514 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
29515 ? ! frame_pointer_needed
29516 : from
== RS6000_PIC_OFFSET_TABLE_REGNUM
29517 ? ! TARGET_MINIMAL_TOC
|| TARGET_NO_TOC
|| get_pool_size () == 0
29521 /* Define the offset between two registers, FROM to be eliminated and its
29522 replacement TO, at the start of a routine. */
29524 rs6000_initial_elimination_offset (int from
, int to
)
29526 rs6000_stack_t
*info
= rs6000_stack_info ();
29527 HOST_WIDE_INT offset
;
29529 if (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
29530 offset
= info
->push_p
? 0 : -info
->total_size
;
29531 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
29533 offset
= info
->push_p
? 0 : -info
->total_size
;
29534 if (FRAME_GROWS_DOWNWARD
)
29535 offset
+= info
->fixed_size
+ info
->vars_size
+ info
->parm_size
;
29537 else if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
29538 offset
= FRAME_GROWS_DOWNWARD
29539 ? info
->fixed_size
+ info
->vars_size
+ info
->parm_size
29541 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
29542 offset
= info
->total_size
;
29543 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
29544 offset
= info
->push_p
? info
->total_size
: 0;
29545 else if (from
== RS6000_PIC_OFFSET_TABLE_REGNUM
)
29548 gcc_unreachable ();
29554 rs6000_dwarf_register_span (rtx reg
)
29558 unsigned regno
= REGNO (reg
);
29559 enum machine_mode mode
= GET_MODE (reg
);
29563 && (SPE_VECTOR_MODE (GET_MODE (reg
))
29564 || (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
)
29565 && mode
!= SFmode
&& mode
!= SDmode
&& mode
!= SCmode
)))
29570 regno
= REGNO (reg
);
29572 /* The duality of the SPE register size wreaks all kinds of havoc.
29573 This is a way of distinguishing r0 in 32-bits from r0 in
29575 words
= (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
29576 gcc_assert (words
<= 4);
29577 for (i
= 0; i
< words
; i
++, regno
++)
29579 if (BYTES_BIG_ENDIAN
)
29581 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
+ 1200);
29582 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
);
29586 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
);
29587 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
+ 1200);
29591 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (words
* 2, parts
));
29594 /* Fill in sizes for SPE register high parts in table used by unwinder. */
29597 rs6000_init_dwarf_reg_sizes_extra (tree address
)
29602 enum machine_mode mode
= TYPE_MODE (char_type_node
);
29603 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
29604 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
29605 rtx value
= gen_int_mode (4, mode
);
29607 for (i
= 1201; i
< 1232; i
++)
29609 int column
= DWARF_REG_TO_UNWIND_COLUMN (i
);
29610 HOST_WIDE_INT offset
29611 = DWARF_FRAME_REGNUM (column
) * GET_MODE_SIZE (mode
);
29613 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
29617 if (TARGET_MACHO
&& ! TARGET_ALTIVEC
)
29620 enum machine_mode mode
= TYPE_MODE (char_type_node
);
29621 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
29622 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
29623 rtx value
= gen_int_mode (16, mode
);
29625 /* On Darwin, libgcc may be built to run on both G3 and G4/5.
29626 The unwinder still needs to know the size of Altivec registers. */
29628 for (i
= FIRST_ALTIVEC_REGNO
; i
< LAST_ALTIVEC_REGNO
+1; i
++)
29630 int column
= DWARF_REG_TO_UNWIND_COLUMN (i
);
29631 HOST_WIDE_INT offset
29632 = DWARF_FRAME_REGNUM (column
) * GET_MODE_SIZE (mode
);
29634 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
29639 /* Map internal gcc register numbers to DWARF2 register numbers. */
29642 rs6000_dbx_register_number (unsigned int regno
)
29644 if (regno
<= 63 || write_symbols
!= DWARF2_DEBUG
)
29646 if (regno
== LR_REGNO
)
29648 if (regno
== CTR_REGNO
)
29650 if (CR_REGNO_P (regno
))
29651 return regno
- CR0_REGNO
+ 86;
29652 if (regno
== CA_REGNO
)
29653 return 101; /* XER */
29654 if (ALTIVEC_REGNO_P (regno
))
29655 return regno
- FIRST_ALTIVEC_REGNO
+ 1124;
29656 if (regno
== VRSAVE_REGNO
)
29658 if (regno
== VSCR_REGNO
)
29660 if (regno
== SPE_ACC_REGNO
)
29662 if (regno
== SPEFSCR_REGNO
)
29664 /* SPE high reg number. We get these values of regno from
29665 rs6000_dwarf_register_span. */
29666 gcc_assert (regno
>= 1200 && regno
< 1232);
29670 /* target hook eh_return_filter_mode */
29671 static enum machine_mode
29672 rs6000_eh_return_filter_mode (void)
29674 return TARGET_32BIT
? SImode
: word_mode
;
29677 /* Target hook for scalar_mode_supported_p. */
29679 rs6000_scalar_mode_supported_p (enum machine_mode mode
)
29681 if (DECIMAL_FLOAT_MODE_P (mode
))
29682 return default_decimal_float_supported_p ();
29684 return default_scalar_mode_supported_p (mode
);
29687 /* Target hook for vector_mode_supported_p. */
29689 rs6000_vector_mode_supported_p (enum machine_mode mode
)
29692 if (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (mode
))
29695 if (TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
29698 else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
29705 /* Target hook for invalid_arg_for_unprototyped_fn. */
29706 static const char *
29707 invalid_arg_for_unprototyped_fn (const_tree typelist
, const_tree funcdecl
, const_tree val
)
29709 return (!rs6000_darwin64_abi
29711 && TREE_CODE (TREE_TYPE (val
)) == VECTOR_TYPE
29712 && (funcdecl
== NULL_TREE
29713 || (TREE_CODE (funcdecl
) == FUNCTION_DECL
29714 && DECL_BUILT_IN_CLASS (funcdecl
) != BUILT_IN_MD
)))
29715 ? N_("AltiVec argument passed to unprototyped function")
29719 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
29720 setup by using __stack_chk_fail_local hidden function instead of
29721 calling __stack_chk_fail directly. Otherwise it is better to call
29722 __stack_chk_fail directly. */
29724 static tree ATTRIBUTE_UNUSED
29725 rs6000_stack_protect_fail (void)
29727 return (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
29728 ? default_hidden_stack_protect_fail ()
29729 : default_external_stack_protect_fail ();
29733 rs6000_final_prescan_insn (rtx insn
, rtx
*operand ATTRIBUTE_UNUSED
,
29734 int num_operands ATTRIBUTE_UNUSED
)
29736 if (rs6000_warn_cell_microcode
)
29739 int insn_code_number
= recog_memoized (insn
);
29740 location_t location
= INSN_LOCATION (insn
);
29742 /* Punt on insns we cannot recognize. */
29743 if (insn_code_number
< 0)
29746 temp
= get_insn_template (insn_code_number
, insn
);
29748 if (get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
)
29749 warning_at (location
, OPT_mwarn_cell_microcode
,
29750 "emitting microcode insn %s\t[%s] #%d",
29751 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
29752 else if (get_attr_cell_micro (insn
) == CELL_MICRO_CONDITIONAL
)
29753 warning_at (location
, OPT_mwarn_cell_microcode
,
29754 "emitting conditional microcode insn %s\t[%s] #%d",
29755 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
29759 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
29762 static unsigned HOST_WIDE_INT
29763 rs6000_asan_shadow_offset (void)
29765 return (unsigned HOST_WIDE_INT
) 1 << (TARGET_64BIT
? 41 : 29);
29769 /* Mask options that we want to support inside of attribute((target)) and
29770 #pragma GCC target operations. Note, we do not include things like
29771 64/32-bit, endianess, hard/soft floating point, etc. that would have
29772 different calling sequences. */
29774 struct rs6000_opt_mask
{
29775 const char *name
; /* option name */
29776 HOST_WIDE_INT mask
; /* mask to set */
29777 bool invert
; /* invert sense of mask */
29778 bool valid_target
; /* option is a target option */
29781 static struct rs6000_opt_mask
const rs6000_opt_masks
[] =
29783 { "altivec", OPTION_MASK_ALTIVEC
, false, true },
29784 { "cmpb", OPTION_MASK_CMPB
, false, true },
29785 { "crypto", OPTION_MASK_CRYPTO
, false, true },
29786 { "direct-move", OPTION_MASK_DIRECT_MOVE
, false, true },
29787 { "dlmzb", OPTION_MASK_DLMZB
, false, true },
29788 { "fprnd", OPTION_MASK_FPRND
, false, true },
29789 { "hard-dfp", OPTION_MASK_DFP
, false, true },
29790 { "htm", OPTION_MASK_HTM
, false, true },
29791 { "isel", OPTION_MASK_ISEL
, false, true },
29792 { "mfcrf", OPTION_MASK_MFCRF
, false, true },
29793 { "mfpgpr", OPTION_MASK_MFPGPR
, false, true },
29794 { "mulhw", OPTION_MASK_MULHW
, false, true },
29795 { "multiple", OPTION_MASK_MULTIPLE
, false, true },
29796 { "popcntb", OPTION_MASK_POPCNTB
, false, true },
29797 { "popcntd", OPTION_MASK_POPCNTD
, false, true },
29798 { "power8-fusion", OPTION_MASK_P8_FUSION
, false, true },
29799 { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN
, false, true },
29800 { "power8-vector", OPTION_MASK_P8_VECTOR
, false, true },
29801 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT
, false, true },
29802 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT
, false, true },
29803 { "quad-memory", OPTION_MASK_QUAD_MEMORY
, false, true },
29804 { "recip-precision", OPTION_MASK_RECIP_PRECISION
, false, true },
29805 { "string", OPTION_MASK_STRING
, false, true },
29806 { "update", OPTION_MASK_NO_UPDATE
, true , true },
29807 { "upper-regs-df", OPTION_MASK_UPPER_REGS_DF
, false, false },
29808 { "upper-regs-sf", OPTION_MASK_UPPER_REGS_SF
, false, false },
29809 { "vsx", OPTION_MASK_VSX
, false, true },
29810 { "vsx-timode", OPTION_MASK_VSX_TIMODE
, false, true },
29811 #ifdef OPTION_MASK_64BIT
29813 { "aix64", OPTION_MASK_64BIT
, false, false },
29814 { "aix32", OPTION_MASK_64BIT
, true, false },
29816 { "64", OPTION_MASK_64BIT
, false, false },
29817 { "32", OPTION_MASK_64BIT
, true, false },
29820 #ifdef OPTION_MASK_EABI
29821 { "eabi", OPTION_MASK_EABI
, false, false },
29823 #ifdef OPTION_MASK_LITTLE_ENDIAN
29824 { "little", OPTION_MASK_LITTLE_ENDIAN
, false, false },
29825 { "big", OPTION_MASK_LITTLE_ENDIAN
, true, false },
29827 #ifdef OPTION_MASK_RELOCATABLE
29828 { "relocatable", OPTION_MASK_RELOCATABLE
, false, false },
29830 #ifdef OPTION_MASK_STRICT_ALIGN
29831 { "strict-align", OPTION_MASK_STRICT_ALIGN
, false, false },
29833 { "soft-float", OPTION_MASK_SOFT_FLOAT
, false, false },
29834 { "string", OPTION_MASK_STRING
, false, false },
29837 /* Builtin mask mapping for printing the flags. */
29838 static struct rs6000_opt_mask
const rs6000_builtin_mask_names
[] =
29840 { "altivec", RS6000_BTM_ALTIVEC
, false, false },
29841 { "vsx", RS6000_BTM_VSX
, false, false },
29842 { "spe", RS6000_BTM_SPE
, false, false },
29843 { "paired", RS6000_BTM_PAIRED
, false, false },
29844 { "fre", RS6000_BTM_FRE
, false, false },
29845 { "fres", RS6000_BTM_FRES
, false, false },
29846 { "frsqrte", RS6000_BTM_FRSQRTE
, false, false },
29847 { "frsqrtes", RS6000_BTM_FRSQRTES
, false, false },
29848 { "popcntd", RS6000_BTM_POPCNTD
, false, false },
29849 { "cell", RS6000_BTM_CELL
, false, false },
29850 { "power8-vector", RS6000_BTM_P8_VECTOR
, false, false },
29851 { "crypto", RS6000_BTM_CRYPTO
, false, false },
29852 { "htm", RS6000_BTM_HTM
, false, false },
29855 /* Option variables that we want to support inside attribute((target)) and
29856 #pragma GCC target operations. */
29858 struct rs6000_opt_var
{
29859 const char *name
; /* option name */
29860 size_t global_offset
; /* offset of the option in global_options. */
29861 size_t target_offset
; /* offset of the option in target optiosn. */
29864 static struct rs6000_opt_var
const rs6000_opt_vars
[] =
29867 offsetof (struct gcc_options
, x_TARGET_FRIZ
),
29868 offsetof (struct cl_target_option
, x_TARGET_FRIZ
), },
29869 { "avoid-indexed-addresses",
29870 offsetof (struct gcc_options
, x_TARGET_AVOID_XFORM
),
29871 offsetof (struct cl_target_option
, x_TARGET_AVOID_XFORM
) },
29873 offsetof (struct gcc_options
, x_rs6000_paired_float
),
29874 offsetof (struct cl_target_option
, x_rs6000_paired_float
), },
29876 offsetof (struct gcc_options
, x_rs6000_default_long_calls
),
29877 offsetof (struct cl_target_option
, x_rs6000_default_long_calls
), },
29880 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
29881 parsing. Return true if there were no errors. */
29884 rs6000_inner_target_options (tree args
, bool attr_p
)
29888 if (args
== NULL_TREE
)
29891 else if (TREE_CODE (args
) == STRING_CST
)
29893 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
29896 while ((q
= strtok (p
, ",")) != NULL
)
29898 bool error_p
= false;
29899 bool not_valid_p
= false;
29900 const char *cpu_opt
= NULL
;
29903 if (strncmp (q
, "cpu=", 4) == 0)
29905 int cpu_index
= rs6000_cpu_name_lookup (q
+4);
29906 if (cpu_index
>= 0)
29907 rs6000_cpu_index
= cpu_index
;
29914 else if (strncmp (q
, "tune=", 5) == 0)
29916 int tune_index
= rs6000_cpu_name_lookup (q
+5);
29917 if (tune_index
>= 0)
29918 rs6000_tune_index
= tune_index
;
29928 bool invert
= false;
29932 if (strncmp (r
, "no-", 3) == 0)
29938 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_masks
); i
++)
29939 if (strcmp (r
, rs6000_opt_masks
[i
].name
) == 0)
29941 HOST_WIDE_INT mask
= rs6000_opt_masks
[i
].mask
;
29943 if (!rs6000_opt_masks
[i
].valid_target
)
29944 not_valid_p
= true;
29948 rs6000_isa_flags_explicit
|= mask
;
29950 /* VSX needs altivec, so -mvsx automagically sets
29952 if (mask
== OPTION_MASK_VSX
&& !invert
)
29953 mask
|= OPTION_MASK_ALTIVEC
;
29955 if (rs6000_opt_masks
[i
].invert
)
29959 rs6000_isa_flags
&= ~mask
;
29961 rs6000_isa_flags
|= mask
;
29966 if (error_p
&& !not_valid_p
)
29968 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_vars
); i
++)
29969 if (strcmp (r
, rs6000_opt_vars
[i
].name
) == 0)
29971 size_t j
= rs6000_opt_vars
[i
].global_offset
;
29972 *((int *) ((char *)&global_options
+ j
)) = !invert
;
29981 const char *eprefix
, *esuffix
;
29986 eprefix
= "__attribute__((__target__(";
29991 eprefix
= "#pragma GCC target ";
29996 error ("invalid cpu \"%s\" for %s\"%s\"%s", cpu_opt
, eprefix
,
29998 else if (not_valid_p
)
29999 error ("%s\"%s\"%s is not allowed", eprefix
, q
, esuffix
);
30001 error ("%s\"%s\"%s is invalid", eprefix
, q
, esuffix
);
30006 else if (TREE_CODE (args
) == TREE_LIST
)
30010 tree value
= TREE_VALUE (args
);
30013 bool ret2
= rs6000_inner_target_options (value
, attr_p
);
30017 args
= TREE_CHAIN (args
);
30019 while (args
!= NULL_TREE
);
30023 gcc_unreachable ();
30028 /* Print out the target options as a list for -mdebug=target. */
30031 rs6000_debug_target_options (tree args
, const char *prefix
)
30033 if (args
== NULL_TREE
)
30034 fprintf (stderr
, "%s<NULL>", prefix
);
30036 else if (TREE_CODE (args
) == STRING_CST
)
30038 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
30041 while ((q
= strtok (p
, ",")) != NULL
)
30044 fprintf (stderr
, "%s\"%s\"", prefix
, q
);
30049 else if (TREE_CODE (args
) == TREE_LIST
)
30053 tree value
= TREE_VALUE (args
);
30056 rs6000_debug_target_options (value
, prefix
);
30059 args
= TREE_CHAIN (args
);
30061 while (args
!= NULL_TREE
);
30065 gcc_unreachable ();
30071 /* Hook to validate attribute((target("..."))). */
30074 rs6000_valid_attribute_p (tree fndecl
,
30075 tree
ARG_UNUSED (name
),
30079 struct cl_target_option cur_target
;
30081 tree old_optimize
= build_optimization_node (&global_options
);
30082 tree new_target
, new_optimize
;
30083 tree func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
30085 gcc_assert ((fndecl
!= NULL_TREE
) && (args
!= NULL_TREE
));
30087 if (TARGET_DEBUG_TARGET
)
30089 tree tname
= DECL_NAME (fndecl
);
30090 fprintf (stderr
, "\n==================== rs6000_valid_attribute_p:\n");
30092 fprintf (stderr
, "function: %.*s\n",
30093 (int) IDENTIFIER_LENGTH (tname
),
30094 IDENTIFIER_POINTER (tname
));
30096 fprintf (stderr
, "function: unknown\n");
30098 fprintf (stderr
, "args:");
30099 rs6000_debug_target_options (args
, " ");
30100 fprintf (stderr
, "\n");
30103 fprintf (stderr
, "flags: 0x%x\n", flags
);
30105 fprintf (stderr
, "--------------------\n");
30108 old_optimize
= build_optimization_node (&global_options
);
30109 func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
30111 /* If the function changed the optimization levels as well as setting target
30112 options, start with the optimizations specified. */
30113 if (func_optimize
&& func_optimize
!= old_optimize
)
30114 cl_optimization_restore (&global_options
,
30115 TREE_OPTIMIZATION (func_optimize
));
30117 /* The target attributes may also change some optimization flags, so update
30118 the optimization options if necessary. */
30119 cl_target_option_save (&cur_target
, &global_options
);
30120 rs6000_cpu_index
= rs6000_tune_index
= -1;
30121 ret
= rs6000_inner_target_options (args
, true);
30123 /* Set up any additional state. */
30126 ret
= rs6000_option_override_internal (false);
30127 new_target
= build_target_option_node (&global_options
);
30132 new_optimize
= build_optimization_node (&global_options
);
30139 DECL_FUNCTION_SPECIFIC_TARGET (fndecl
) = new_target
;
30141 if (old_optimize
!= new_optimize
)
30142 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
) = new_optimize
;
30145 cl_target_option_restore (&global_options
, &cur_target
);
30147 if (old_optimize
!= new_optimize
)
30148 cl_optimization_restore (&global_options
,
30149 TREE_OPTIMIZATION (old_optimize
));
30155 /* Hook to validate the current #pragma GCC target and set the state, and
30156 update the macros based on what was changed. If ARGS is NULL, then
30157 POP_TARGET is used to reset the options. */
30160 rs6000_pragma_target_parse (tree args
, tree pop_target
)
30162 tree prev_tree
= build_target_option_node (&global_options
);
30164 struct cl_target_option
*prev_opt
, *cur_opt
;
30165 HOST_WIDE_INT prev_flags
, cur_flags
, diff_flags
;
30166 HOST_WIDE_INT prev_bumask
, cur_bumask
, diff_bumask
;
30168 if (TARGET_DEBUG_TARGET
)
30170 fprintf (stderr
, "\n==================== rs6000_pragma_target_parse\n");
30171 fprintf (stderr
, "args:");
30172 rs6000_debug_target_options (args
, " ");
30173 fprintf (stderr
, "\n");
30177 fprintf (stderr
, "pop_target:\n");
30178 debug_tree (pop_target
);
30181 fprintf (stderr
, "pop_target: <NULL>\n");
30183 fprintf (stderr
, "--------------------\n");
30188 cur_tree
= ((pop_target
)
30190 : target_option_default_node
);
30191 cl_target_option_restore (&global_options
,
30192 TREE_TARGET_OPTION (cur_tree
));
30196 rs6000_cpu_index
= rs6000_tune_index
= -1;
30197 if (!rs6000_inner_target_options (args
, false)
30198 || !rs6000_option_override_internal (false)
30199 || (cur_tree
= build_target_option_node (&global_options
))
30202 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
30203 fprintf (stderr
, "invalid pragma\n");
30209 target_option_current_node
= cur_tree
;
30211 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
30212 change the macros that are defined. */
30213 if (rs6000_target_modify_macros_ptr
)
30215 prev_opt
= TREE_TARGET_OPTION (prev_tree
);
30216 prev_bumask
= prev_opt
->x_rs6000_builtin_mask
;
30217 prev_flags
= prev_opt
->x_rs6000_isa_flags
;
30219 cur_opt
= TREE_TARGET_OPTION (cur_tree
);
30220 cur_flags
= cur_opt
->x_rs6000_isa_flags
;
30221 cur_bumask
= cur_opt
->x_rs6000_builtin_mask
;
30223 diff_bumask
= (prev_bumask
^ cur_bumask
);
30224 diff_flags
= (prev_flags
^ cur_flags
);
30226 if ((diff_flags
!= 0) || (diff_bumask
!= 0))
30228 /* Delete old macros. */
30229 rs6000_target_modify_macros_ptr (false,
30230 prev_flags
& diff_flags
,
30231 prev_bumask
& diff_bumask
);
30233 /* Define new macros. */
30234 rs6000_target_modify_macros_ptr (true,
30235 cur_flags
& diff_flags
,
30236 cur_bumask
& diff_bumask
);
30244 /* Remember the last target of rs6000_set_current_function. */
30245 static GTY(()) tree rs6000_previous_fndecl
;
30247 /* Establish appropriate back-end context for processing the function
30248 FNDECL. The argument might be NULL to indicate processing at top
30249 level, outside of any function scope. */
30251 rs6000_set_current_function (tree fndecl
)
30253 tree old_tree
= (rs6000_previous_fndecl
30254 ? DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl
)
30257 tree new_tree
= (fndecl
30258 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl
)
30261 if (TARGET_DEBUG_TARGET
)
30263 bool print_final
= false;
30264 fprintf (stderr
, "\n==================== rs6000_set_current_function");
30267 fprintf (stderr
, ", fndecl %s (%p)",
30268 (DECL_NAME (fndecl
)
30269 ? IDENTIFIER_POINTER (DECL_NAME (fndecl
))
30270 : "<unknown>"), (void *)fndecl
);
30272 if (rs6000_previous_fndecl
)
30273 fprintf (stderr
, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl
);
30275 fprintf (stderr
, "\n");
30278 fprintf (stderr
, "\nnew fndecl target specific options:\n");
30279 debug_tree (new_tree
);
30280 print_final
= true;
30285 fprintf (stderr
, "\nold fndecl target specific options:\n");
30286 debug_tree (old_tree
);
30287 print_final
= true;
30291 fprintf (stderr
, "--------------------\n");
30294 /* Only change the context if the function changes. This hook is called
30295 several times in the course of compiling a function, and we don't want to
30296 slow things down too much or call target_reinit when it isn't safe. */
30297 if (fndecl
&& fndecl
!= rs6000_previous_fndecl
)
30299 rs6000_previous_fndecl
= fndecl
;
30300 if (old_tree
== new_tree
)
30305 cl_target_option_restore (&global_options
,
30306 TREE_TARGET_OPTION (new_tree
));
30312 struct cl_target_option
*def
30313 = TREE_TARGET_OPTION (target_option_current_node
);
30315 cl_target_option_restore (&global_options
, def
);
30322 /* Save the current options */
30325 rs6000_function_specific_save (struct cl_target_option
*ptr
,
30326 struct gcc_options
*opts
)
30328 ptr
->x_rs6000_isa_flags
= opts
->x_rs6000_isa_flags
;
30329 ptr
->x_rs6000_isa_flags_explicit
= opts
->x_rs6000_isa_flags_explicit
;
30332 /* Restore the current options */
30335 rs6000_function_specific_restore (struct gcc_options
*opts
,
30336 struct cl_target_option
*ptr
)
30339 opts
->x_rs6000_isa_flags
= ptr
->x_rs6000_isa_flags
;
30340 opts
->x_rs6000_isa_flags_explicit
= ptr
->x_rs6000_isa_flags_explicit
;
30341 (void) rs6000_option_override_internal (false);
30344 /* Print the current options */
30347 rs6000_function_specific_print (FILE *file
, int indent
,
30348 struct cl_target_option
*ptr
)
30350 rs6000_print_isa_options (file
, indent
, "Isa options set",
30351 ptr
->x_rs6000_isa_flags
);
30353 rs6000_print_isa_options (file
, indent
, "Isa options explicit",
30354 ptr
->x_rs6000_isa_flags_explicit
);
30357 /* Helper function to print the current isa or misc options on a line. */
30360 rs6000_print_options_internal (FILE *file
,
30362 const char *string
,
30363 HOST_WIDE_INT flags
,
30364 const char *prefix
,
30365 const struct rs6000_opt_mask
*opts
,
30366 size_t num_elements
)
30369 size_t start_column
= 0;
30371 size_t max_column
= 76;
30372 const char *comma
= "";
30375 start_column
+= fprintf (file
, "%*s", indent
, "");
30379 fprintf (stderr
, DEBUG_FMT_S
, string
, "<none>");
30383 start_column
+= fprintf (stderr
, DEBUG_FMT_WX
, string
, flags
);
30385 /* Print the various mask options. */
30386 cur_column
= start_column
;
30387 for (i
= 0; i
< num_elements
; i
++)
30389 if ((flags
& opts
[i
].mask
) != 0)
30391 const char *no_str
= rs6000_opt_masks
[i
].invert
? "no-" : "";
30392 size_t len
= (strlen (comma
)
30395 + strlen (rs6000_opt_masks
[i
].name
));
30398 if (cur_column
> max_column
)
30400 fprintf (stderr
, ", \\\n%*s", (int)start_column
, "");
30401 cur_column
= start_column
+ len
;
30405 fprintf (file
, "%s%s%s%s", comma
, prefix
, no_str
,
30406 rs6000_opt_masks
[i
].name
);
30407 flags
&= ~ opts
[i
].mask
;
30412 fputs ("\n", file
);
30415 /* Helper function to print the current isa options on a line. */
30418 rs6000_print_isa_options (FILE *file
, int indent
, const char *string
,
30419 HOST_WIDE_INT flags
)
30421 rs6000_print_options_internal (file
, indent
, string
, flags
, "-m",
30422 &rs6000_opt_masks
[0],
30423 ARRAY_SIZE (rs6000_opt_masks
));
30427 rs6000_print_builtin_options (FILE *file
, int indent
, const char *string
,
30428 HOST_WIDE_INT flags
)
30430 rs6000_print_options_internal (file
, indent
, string
, flags
, "",
30431 &rs6000_builtin_mask_names
[0],
30432 ARRAY_SIZE (rs6000_builtin_mask_names
));
30436 /* Hook to determine if one function can safely inline another. */
30439 rs6000_can_inline_p (tree caller
, tree callee
)
30442 tree caller_tree
= DECL_FUNCTION_SPECIFIC_TARGET (caller
);
30443 tree callee_tree
= DECL_FUNCTION_SPECIFIC_TARGET (callee
);
30445 /* If callee has no option attributes, then it is ok to inline. */
30449 /* If caller has no option attributes, but callee does then it is not ok to
30451 else if (!caller_tree
)
30456 struct cl_target_option
*caller_opts
= TREE_TARGET_OPTION (caller_tree
);
30457 struct cl_target_option
*callee_opts
= TREE_TARGET_OPTION (callee_tree
);
30459 /* Callee's options should a subset of the caller's, i.e. a vsx function
30460 can inline an altivec function but a non-vsx function can't inline a
30462 if ((caller_opts
->x_rs6000_isa_flags
& callee_opts
->x_rs6000_isa_flags
)
30463 == callee_opts
->x_rs6000_isa_flags
)
30467 if (TARGET_DEBUG_TARGET
)
30468 fprintf (stderr
, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
30469 (DECL_NAME (caller
)
30470 ? IDENTIFIER_POINTER (DECL_NAME (caller
))
30472 (DECL_NAME (callee
)
30473 ? IDENTIFIER_POINTER (DECL_NAME (callee
))
30475 (ret
? "can" : "cannot"));
30480 /* Allocate a stack temp and fixup the address so it meets the particular
30481 memory requirements (either offetable or REG+REG addressing). */
30484 rs6000_allocate_stack_temp (enum machine_mode mode
,
30485 bool offsettable_p
,
30488 rtx stack
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
30489 rtx addr
= XEXP (stack
, 0);
30490 int strict_p
= (reload_in_progress
|| reload_completed
);
30492 if (!legitimate_indirect_address_p (addr
, strict_p
))
30495 && !rs6000_legitimate_offset_address_p (mode
, addr
, strict_p
, true))
30496 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
30498 else if (reg_reg_p
&& !legitimate_indexed_address_p (addr
, strict_p
))
30499 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
30505 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
30506 to such a form to deal with memory reference instructions like STFIWX that
30507 only take reg+reg addressing. */
30510 rs6000_address_for_fpconvert (rtx x
)
30512 int strict_p
= (reload_in_progress
|| reload_completed
);
30515 gcc_assert (MEM_P (x
));
30516 addr
= XEXP (x
, 0);
30517 if (! legitimate_indirect_address_p (addr
, strict_p
)
30518 && ! legitimate_indexed_address_p (addr
, strict_p
))
30520 if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
30522 rtx reg
= XEXP (addr
, 0);
30523 HOST_WIDE_INT size
= GET_MODE_SIZE (GET_MODE (x
));
30524 rtx size_rtx
= GEN_INT ((GET_CODE (addr
) == PRE_DEC
) ? -size
: size
);
30525 gcc_assert (REG_P (reg
));
30526 emit_insn (gen_add3_insn (reg
, reg
, size_rtx
));
30529 else if (GET_CODE (addr
) == PRE_MODIFY
)
30531 rtx reg
= XEXP (addr
, 0);
30532 rtx expr
= XEXP (addr
, 1);
30533 gcc_assert (REG_P (reg
));
30534 gcc_assert (GET_CODE (expr
) == PLUS
);
30535 emit_insn (gen_add3_insn (reg
, XEXP (expr
, 0), XEXP (expr
, 1)));
30539 x
= replace_equiv_address (x
, copy_addr_to_reg (addr
));
30545 /* Given a memory reference, if it is not in the form for altivec memory
30546 reference instructions (i.e. reg or reg+reg addressing with AND of -16),
30547 convert to the altivec format. */
30550 rs6000_address_for_altivec (rtx x
)
30552 gcc_assert (MEM_P (x
));
30553 if (!altivec_indexed_or_indirect_operand (x
, GET_MODE (x
)))
30555 rtx addr
= XEXP (x
, 0);
30556 int strict_p
= (reload_in_progress
|| reload_completed
);
30558 if (!legitimate_indexed_address_p (addr
, strict_p
)
30559 && !legitimate_indirect_address_p (addr
, strict_p
))
30560 addr
= copy_to_mode_reg (Pmode
, addr
);
30562 addr
= gen_rtx_AND (Pmode
, addr
, GEN_INT (-16));
30563 x
= change_address (x
, GET_MODE (x
), addr
);
30569 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
30571 On the RS/6000, all integer constants are acceptable, most won't be valid
30572 for particular insns, though. Only easy FP constants are acceptable. */
30575 rs6000_legitimate_constant_p (enum machine_mode mode
, rtx x
)
30577 if (TARGET_ELF
&& rs6000_tls_referenced_p (x
))
30580 return ((GET_CODE (x
) != CONST_DOUBLE
&& GET_CODE (x
) != CONST_VECTOR
)
30581 || GET_MODE (x
) == VOIDmode
30582 || (TARGET_POWERPC64
&& mode
== DImode
)
30583 || easy_fp_constant (x
, mode
)
30584 || easy_vector_constant (x
, mode
));
30588 /* A function pointer under AIX is a pointer to a data area whose first word
30589 contains the actual address of the function, whose second word contains a
30590 pointer to its TOC, and whose third word contains a value to place in the
30591 static chain register (r11). Note that if we load the static chain, our
30592 "trampoline" need not have any executable code. */
30595 rs6000_call_indirect_aix (rtx value
, rtx func_desc
, rtx flag
)
30601 rtx stack_toc_offset
;
30603 rtx func_toc_offset
;
30605 rtx func_sc_offset
;
30608 rtx (*call_func
) (rtx
, rtx
, rtx
, rtx
);
30609 rtx (*call_value_func
) (rtx
, rtx
, rtx
, rtx
, rtx
);
30611 stack_ptr
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
30612 toc_reg
= gen_rtx_REG (Pmode
, TOC_REGNUM
);
30614 /* Load up address of the actual function. */
30615 func_desc
= force_reg (Pmode
, func_desc
);
30616 func_addr
= gen_reg_rtx (Pmode
);
30617 emit_move_insn (func_addr
, gen_rtx_MEM (Pmode
, func_desc
));
30622 stack_toc_offset
= GEN_INT (TOC_SAVE_OFFSET_32BIT
);
30623 func_toc_offset
= GEN_INT (AIX_FUNC_DESC_TOC_32BIT
);
30624 func_sc_offset
= GEN_INT (AIX_FUNC_DESC_SC_32BIT
);
30625 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
30627 call_func
= gen_call_indirect_aix32bit
;
30628 call_value_func
= gen_call_value_indirect_aix32bit
;
30632 call_func
= gen_call_indirect_aix32bit_nor11
;
30633 call_value_func
= gen_call_value_indirect_aix32bit_nor11
;
30638 stack_toc_offset
= GEN_INT (TOC_SAVE_OFFSET_64BIT
);
30639 func_toc_offset
= GEN_INT (AIX_FUNC_DESC_TOC_64BIT
);
30640 func_sc_offset
= GEN_INT (AIX_FUNC_DESC_SC_64BIT
);
30641 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
30643 call_func
= gen_call_indirect_aix64bit
;
30644 call_value_func
= gen_call_value_indirect_aix64bit
;
30648 call_func
= gen_call_indirect_aix64bit_nor11
;
30649 call_value_func
= gen_call_value_indirect_aix64bit_nor11
;
30653 /* Reserved spot to store the TOC. */
30654 stack_toc_mem
= gen_frame_mem (Pmode
,
30655 gen_rtx_PLUS (Pmode
,
30657 stack_toc_offset
));
30660 gcc_assert (cfun
->machine
);
30662 /* Can we optimize saving the TOC in the prologue or do we need to do it at
30664 if (TARGET_SAVE_TOC_INDIRECT
&& !cfun
->calls_alloca
)
30665 cfun
->machine
->save_toc_in_prologue
= true;
30669 MEM_VOLATILE_P (stack_toc_mem
) = 1;
30670 emit_move_insn (stack_toc_mem
, toc_reg
);
30673 /* Calculate the address to load the TOC of the called function. We don't
30674 actually load this until the split after reload. */
30675 func_toc_mem
= gen_rtx_MEM (Pmode
,
30676 gen_rtx_PLUS (Pmode
,
30680 /* If we have a static chain, load it up. */
30681 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
30683 func_sc_mem
= gen_rtx_MEM (Pmode
,
30684 gen_rtx_PLUS (Pmode
,
30688 sc_reg
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
30689 emit_move_insn (sc_reg
, func_sc_mem
);
30692 /* Create the call. */
30694 insn
= call_value_func (value
, func_addr
, flag
, func_toc_mem
,
30697 insn
= call_func (func_addr
, flag
, func_toc_mem
, stack_toc_mem
);
30699 emit_call_insn (insn
);
30702 /* Return whether we need to always update the saved TOC pointer when we update
30703 the stack pointer. */
30706 rs6000_save_toc_in_prologue_p (void)
30708 return (cfun
&& cfun
->machine
&& cfun
->machine
->save_toc_in_prologue
);
30711 #ifdef HAVE_GAS_HIDDEN
30712 # define USE_HIDDEN_LINKONCE 1
30714 # define USE_HIDDEN_LINKONCE 0
30717 /* Fills in the label name that should be used for a 476 link stack thunk. */
30720 get_ppc476_thunk_name (char name
[32])
30722 gcc_assert (TARGET_LINK_STACK
);
30724 if (USE_HIDDEN_LINKONCE
)
30725 sprintf (name
, "__ppc476.get_thunk");
30727 ASM_GENERATE_INTERNAL_LABEL (name
, "LPPC476_", 0);
30730 /* This function emits the simple thunk routine that is used to preserve
30731 the link stack on the 476 cpu. */
30733 static void rs6000_code_end (void) ATTRIBUTE_UNUSED
;
30735 rs6000_code_end (void)
30740 if (!TARGET_LINK_STACK
)
30743 get_ppc476_thunk_name (name
);
30745 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
, get_identifier (name
),
30746 build_function_type_list (void_type_node
, NULL_TREE
));
30747 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
30748 NULL_TREE
, void_type_node
);
30749 TREE_PUBLIC (decl
) = 1;
30750 TREE_STATIC (decl
) = 1;
30753 if (USE_HIDDEN_LINKONCE
)
30755 DECL_COMDAT_GROUP (decl
) = DECL_ASSEMBLER_NAME (decl
);
30756 targetm
.asm_out
.unique_section (decl
, 0);
30757 switch_to_section (get_named_section (decl
, NULL
, 0));
30758 DECL_WEAK (decl
) = 1;
30759 ASM_WEAKEN_DECL (asm_out_file
, decl
, name
, 0);
30760 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
30761 targetm
.asm_out
.assemble_visibility (decl
, VISIBILITY_HIDDEN
);
30762 ASM_DECLARE_FUNCTION_NAME (asm_out_file
, name
, decl
);
30767 switch_to_section (text_section
);
30768 ASM_OUTPUT_LABEL (asm_out_file
, name
);
30771 DECL_INITIAL (decl
) = make_node (BLOCK
);
30772 current_function_decl
= decl
;
30773 init_function_start (decl
);
30774 first_function_block_is_cold
= false;
30775 /* Make sure unwind info is emitted for the thunk if needed. */
30776 final_start_function (emit_barrier (), asm_out_file
, 1);
30778 fputs ("\tblr\n", asm_out_file
);
30780 final_end_function ();
30781 init_insn_lengths ();
30782 free_after_compilation (cfun
);
30784 current_function_decl
= NULL
;
30787 /* Add r30 to hard reg set if the prologue sets it up and it is not
30788 pic_offset_table_rtx. */
30791 rs6000_set_up_by_prologue (struct hard_reg_set_container
*set
)
30793 if (!TARGET_SINGLE_PIC_BASE
30795 && TARGET_MINIMAL_TOC
30796 && get_pool_size () != 0)
30797 add_to_hard_reg_set (&set
->set
, Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
30801 /* Helper function for rs6000_split_logical to emit a logical instruction after
30802 spliting the operation to single GPR registers.
30804 DEST is the destination register.
30805 OP1 and OP2 are the input source registers.
30806 CODE is the base operation (AND, IOR, XOR, NOT).
30807 MODE is the machine mode.
30808 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
30809 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
30810 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
30811 CLOBBER_REG is either NULL or a scratch register of type CC to allow
30812 formation of the AND instructions. */
30815 rs6000_split_logical_inner (rtx dest
,
30818 enum rtx_code code
,
30819 enum machine_mode mode
,
30820 bool complement_final_p
,
30821 bool complement_op1_p
,
30822 bool complement_op2_p
,
30828 /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */
30829 if (op2
&& GET_CODE (op2
) == CONST_INT
30830 && (mode
== SImode
|| (mode
== DImode
&& TARGET_POWERPC64
))
30831 && !complement_final_p
&& !complement_op1_p
&& !complement_op2_p
)
30833 HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
30834 HOST_WIDE_INT value
= INTVAL (op2
) & mask
;
30836 /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */
30841 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
30845 else if (value
== mask
)
30847 if (!rtx_equal_p (dest
, op1
))
30848 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op1
));
30853 /* Optimize IOR/XOR of 0 to be a simple move. Split large operations
30854 into separate ORI/ORIS or XORI/XORIS instrucitons. */
30855 else if (code
== IOR
|| code
== XOR
)
30859 if (!rtx_equal_p (dest
, op1
))
30860 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op1
));
30866 if (complement_op1_p
)
30867 op1
= gen_rtx_NOT (mode
, op1
);
30869 if (complement_op2_p
)
30870 op2
= gen_rtx_NOT (mode
, op2
);
30872 bool_rtx
= ((code
== NOT
)
30873 ? gen_rtx_NOT (mode
, op1
)
30874 : gen_rtx_fmt_ee (code
, mode
, op1
, op2
));
30876 if (complement_final_p
)
30877 bool_rtx
= gen_rtx_NOT (mode
, bool_rtx
);
30879 set_rtx
= gen_rtx_SET (VOIDmode
, dest
, bool_rtx
);
30881 /* Is this AND with an explicit clobber? */
30884 rtx clobber
= gen_rtx_CLOBBER (VOIDmode
, clobber_reg
);
30885 set_rtx
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set_rtx
, clobber
));
30888 emit_insn (set_rtx
);
30892 /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These
30893 operations are split immediately during RTL generation to allow for more
30894 optimizations of the AND/IOR/XOR.
30896 OPERANDS is an array containing the destination and two input operands.
30897 CODE is the base operation (AND, IOR, XOR, NOT).
30898 MODE is the machine mode.
30899 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
30900 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
30901 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
30902 CLOBBER_REG is either NULL or a scratch register of type CC to allow
30903 formation of the AND instructions. */
30906 rs6000_split_logical_di (rtx operands
[3],
30907 enum rtx_code code
,
30908 bool complement_final_p
,
30909 bool complement_op1_p
,
30910 bool complement_op2_p
,
30913 const HOST_WIDE_INT lower_32bits
= HOST_WIDE_INT_C(0xffffffff);
30914 const HOST_WIDE_INT upper_32bits
= ~ lower_32bits
;
30915 const HOST_WIDE_INT sign_bit
= HOST_WIDE_INT_C(0x80000000);
30916 enum hi_lo
{ hi
= 0, lo
= 1 };
30917 rtx op0_hi_lo
[2], op1_hi_lo
[2], op2_hi_lo
[2];
30920 op0_hi_lo
[hi
] = gen_highpart (SImode
, operands
[0]);
30921 op1_hi_lo
[hi
] = gen_highpart (SImode
, operands
[1]);
30922 op0_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[0]);
30923 op1_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[1]);
30926 op2_hi_lo
[hi
] = op2_hi_lo
[lo
] = NULL_RTX
;
30929 if (GET_CODE (operands
[2]) != CONST_INT
)
30931 op2_hi_lo
[hi
] = gen_highpart_mode (SImode
, DImode
, operands
[2]);
30932 op2_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[2]);
30936 HOST_WIDE_INT value
= INTVAL (operands
[2]);
30937 HOST_WIDE_INT value_hi_lo
[2];
30939 gcc_assert (!complement_final_p
);
30940 gcc_assert (!complement_op1_p
);
30941 gcc_assert (!complement_op2_p
);
30943 value_hi_lo
[hi
] = value
>> 32;
30944 value_hi_lo
[lo
] = value
& lower_32bits
;
30946 for (i
= 0; i
< 2; i
++)
30948 HOST_WIDE_INT sub_value
= value_hi_lo
[i
];
30950 if (sub_value
& sign_bit
)
30951 sub_value
|= upper_32bits
;
30953 op2_hi_lo
[i
] = GEN_INT (sub_value
);
30955 /* If this is an AND instruction, check to see if we need to load
30956 the value in a register. */
30957 if (code
== AND
&& sub_value
!= -1 && sub_value
!= 0
30958 && !and_operand (op2_hi_lo
[i
], SImode
))
30959 op2_hi_lo
[i
] = force_reg (SImode
, op2_hi_lo
[i
]);
30964 for (i
= 0; i
< 2; i
++)
30966 /* Split large IOR/XOR operations. */
30967 if ((code
== IOR
|| code
== XOR
)
30968 && GET_CODE (op2_hi_lo
[i
]) == CONST_INT
30969 && !complement_final_p
30970 && !complement_op1_p
30971 && !complement_op2_p
30972 && clobber_reg
== NULL_RTX
30973 && !logical_const_operand (op2_hi_lo
[i
], SImode
))
30975 HOST_WIDE_INT value
= INTVAL (op2_hi_lo
[i
]);
30976 HOST_WIDE_INT hi_16bits
= value
& HOST_WIDE_INT_C(0xffff0000);
30977 HOST_WIDE_INT lo_16bits
= value
& HOST_WIDE_INT_C(0x0000ffff);
30978 rtx tmp
= gen_reg_rtx (SImode
);
30980 /* Make sure the constant is sign extended. */
30981 if ((hi_16bits
& sign_bit
) != 0)
30982 hi_16bits
|= upper_32bits
;
30984 rs6000_split_logical_inner (tmp
, op1_hi_lo
[i
], GEN_INT (hi_16bits
),
30985 code
, SImode
, false, false, false,
30988 rs6000_split_logical_inner (op0_hi_lo
[i
], tmp
, GEN_INT (lo_16bits
),
30989 code
, SImode
, false, false, false,
30993 rs6000_split_logical_inner (op0_hi_lo
[i
], op1_hi_lo
[i
], op2_hi_lo
[i
],
30994 code
, SImode
, complement_final_p
,
30995 complement_op1_p
, complement_op2_p
,
31002 /* Split the insns that make up boolean operations operating on multiple GPR
31003 registers. The boolean MD patterns ensure that the inputs either are
31004 exactly the same as the output registers, or there is no overlap.
31006 OPERANDS is an array containing the destination and two input operands.
31007 CODE is the base operation (AND, IOR, XOR, NOT).
31008 MODE is the machine mode.
31009 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
31010 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
31011 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
31012 CLOBBER_REG is either NULL or a scratch register of type CC to allow
31013 formation of the AND instructions. */
31016 rs6000_split_logical (rtx operands
[3],
31017 enum rtx_code code
,
31018 bool complement_final_p
,
31019 bool complement_op1_p
,
31020 bool complement_op2_p
,
31023 enum machine_mode mode
= GET_MODE (operands
[0]);
31024 enum machine_mode sub_mode
;
31026 int sub_size
, regno0
, regno1
, nregs
, i
;
31028 /* If this is DImode, use the specialized version that can run before
31029 register allocation. */
31030 if (mode
== DImode
&& !TARGET_POWERPC64
)
31032 rs6000_split_logical_di (operands
, code
, complement_final_p
,
31033 complement_op1_p
, complement_op2_p
,
31040 op2
= (code
== NOT
) ? NULL_RTX
: operands
[2];
31041 sub_mode
= (TARGET_POWERPC64
) ? DImode
: SImode
;
31042 sub_size
= GET_MODE_SIZE (sub_mode
);
31043 regno0
= REGNO (op0
);
31044 regno1
= REGNO (op1
);
31046 gcc_assert (reload_completed
);
31047 gcc_assert (IN_RANGE (regno0
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
31048 gcc_assert (IN_RANGE (regno1
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
31050 nregs
= rs6000_hard_regno_nregs
[(int)mode
][regno0
];
31051 gcc_assert (nregs
> 1);
31053 if (op2
&& REG_P (op2
))
31054 gcc_assert (IN_RANGE (REGNO (op2
), FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
31056 for (i
= 0; i
< nregs
; i
++)
31058 int offset
= i
* sub_size
;
31059 rtx sub_op0
= simplify_subreg (sub_mode
, op0
, mode
, offset
);
31060 rtx sub_op1
= simplify_subreg (sub_mode
, op1
, mode
, offset
);
31061 rtx sub_op2
= ((code
== NOT
)
31063 : simplify_subreg (sub_mode
, op2
, mode
, offset
));
31065 rs6000_split_logical_inner (sub_op0
, sub_op1
, sub_op2
, code
, sub_mode
,
31066 complement_final_p
, complement_op1_p
,
31067 complement_op2_p
, clobber_reg
);
31074 /* Return true if the peephole2 can combine a load involving a combination of
31075 an addis instruction and a load with an offset that can be fused together on
31079 operands[0] register set with addis
31080 operands[1] value set via addis
31081 operands[2] target register being loaded
31082 operands[3] D-form memory reference using operands[0].
31084 In addition, we are passed a boolean that is true if this is a peephole2,
31085 and we can use see if the addis_reg is dead after the insn and can be
31086 replaced by the target register. */
31089 fusion_gpr_load_p (rtx
*operands
, bool peep2_p
)
31091 rtx addis_reg
= operands
[0];
31092 rtx addis_value
= operands
[1];
31093 rtx target
= operands
[2];
31094 rtx mem
= operands
[3];
31098 /* Validate arguments. */
31099 if (!base_reg_operand (addis_reg
, GET_MODE (addis_reg
)))
31102 if (!base_reg_operand (target
, GET_MODE (target
)))
31105 if (!fusion_gpr_addis (addis_value
, GET_MODE (addis_value
)))
31108 if (!fusion_gpr_mem_load (mem
, GET_MODE (mem
)))
31111 /* Allow sign/zero extension. */
31112 if (GET_CODE (mem
) == ZERO_EXTEND
31113 || (GET_CODE (mem
) == SIGN_EXTEND
&& TARGET_P8_FUSION_SIGN
))
31114 mem
= XEXP (mem
, 0);
31119 addr
= XEXP (mem
, 0); /* either PLUS or LO_SUM. */
31120 if (GET_CODE (addr
) != PLUS
&& GET_CODE (addr
) != LO_SUM
)
31123 /* Validate that the register used to load the high value is either the
31124 register being loaded, or we can safely replace its use in a peephole2.
31126 If this is a peephole2, we assume that there are 2 instructions in the
31127 peephole (addis and load), so we want to check if the target register was
31128 not used in the memory address and the register to hold the addis result
31129 is dead after the peephole. */
31130 if (REGNO (addis_reg
) != REGNO (target
))
31135 if (reg_mentioned_p (target
, mem
))
31138 if (!peep2_reg_dead_p (2, addis_reg
))
31142 base_reg
= XEXP (addr
, 0);
31143 return REGNO (addis_reg
) == REGNO (base_reg
);
31146 /* During the peephole2 pass, adjust and expand the insns for a load fusion
31147 sequence. We adjust the addis register to use the target register. If the
31148 load sign extends, we adjust the code to do the zero extending load, and an
31149 explicit sign extension later since the fusion only covers zero extending
31153 operands[0] register set with addis (to be replaced with target)
31154 operands[1] value set via addis
31155 operands[2] target register being loaded
31156 operands[3] D-form memory reference using operands[0]. */
31159 expand_fusion_gpr_load (rtx
*operands
)
31161 rtx addis_value
= operands
[1];
31162 rtx target
= operands
[2];
31163 rtx orig_mem
= operands
[3];
31164 rtx new_addr
, new_mem
, orig_addr
, offset
;
31165 enum rtx_code plus_or_lo_sum
;
31166 enum machine_mode target_mode
= GET_MODE (target
);
31167 enum machine_mode extend_mode
= target_mode
;
31168 enum machine_mode ptr_mode
= Pmode
;
31169 enum rtx_code extend
= UNKNOWN
;
31170 rtx addis_reg
= ((ptr_mode
== target_mode
)
31172 : simplify_subreg (ptr_mode
, target
, target_mode
, 0));
31174 if (GET_CODE (orig_mem
) == ZERO_EXTEND
31175 || (TARGET_P8_FUSION_SIGN
&& GET_CODE (orig_mem
) == SIGN_EXTEND
))
31177 extend
= GET_CODE (orig_mem
);
31178 orig_mem
= XEXP (orig_mem
, 0);
31179 target_mode
= GET_MODE (orig_mem
);
31182 gcc_assert (MEM_P (orig_mem
));
31184 orig_addr
= XEXP (orig_mem
, 0);
31185 plus_or_lo_sum
= GET_CODE (orig_addr
);
31186 gcc_assert (plus_or_lo_sum
== PLUS
|| plus_or_lo_sum
== LO_SUM
);
31188 offset
= XEXP (orig_addr
, 1);
31189 new_addr
= gen_rtx_fmt_ee (plus_or_lo_sum
, ptr_mode
, addis_reg
, offset
);
31190 new_mem
= change_address (orig_mem
, target_mode
, new_addr
);
31192 if (extend
!= UNKNOWN
)
31193 new_mem
= gen_rtx_fmt_e (ZERO_EXTEND
, extend_mode
, new_mem
);
31195 emit_insn (gen_rtx_SET (VOIDmode
, addis_reg
, addis_value
));
31196 emit_insn (gen_rtx_SET (VOIDmode
, target
, new_mem
));
31198 if (extend
== SIGN_EXTEND
)
31200 int sub_off
= ((BYTES_BIG_ENDIAN
)
31201 ? GET_MODE_SIZE (extend_mode
) - GET_MODE_SIZE (target_mode
)
31204 = simplify_subreg (target_mode
, target
, extend_mode
, sub_off
);
31206 emit_insn (gen_rtx_SET (VOIDmode
, target
,
31207 gen_rtx_SIGN_EXTEND (extend_mode
, sign_reg
)));
31213 /* Return a string to fuse an addis instruction with a gpr load to the same
31214 register that we loaded up the addis instruction. The code is complicated,
31215 so we call output_asm_insn directly, and just return "".
31218 operands[0] register set with addis (must be same reg as target).
31219 operands[1] value set via addis
31220 operands[2] target register being loaded
31221 operands[3] D-form memory reference using operands[0]. */
31224 emit_fusion_gpr_load (rtx
*operands
)
31226 rtx addis_reg
= operands
[0];
31227 rtx addis_value
= operands
[1];
31228 rtx target
= operands
[2];
31229 rtx mem
= operands
[3];
31233 const char *addis_str
= NULL
;
31234 const char *load_str
= NULL
;
31235 const char *extend_insn
= NULL
;
31236 const char *mode_name
= NULL
;
31237 char insn_template
[80];
31238 enum machine_mode mode
;
31239 const char *comment_str
= ASM_COMMENT_START
;
31240 bool sign_p
= false;
31242 gcc_assert (REG_P (addis_reg
) && REG_P (target
));
31243 gcc_assert (REGNO (addis_reg
) == REGNO (target
));
31245 if (*comment_str
== ' ')
31248 /* Allow sign/zero extension. */
31249 if (GET_CODE (mem
) == ZERO_EXTEND
)
31250 mem
= XEXP (mem
, 0);
31252 else if (GET_CODE (mem
) == SIGN_EXTEND
&& TARGET_P8_FUSION_SIGN
)
31255 mem
= XEXP (mem
, 0);
31258 gcc_assert (MEM_P (mem
));
31259 addr
= XEXP (mem
, 0);
31260 if (GET_CODE (addr
) != PLUS
&& GET_CODE (addr
) != LO_SUM
)
31261 gcc_unreachable ();
31263 load_offset
= XEXP (addr
, 1);
31265 /* Now emit the load instruction to the same register. */
31266 mode
= GET_MODE (mem
);
31270 mode_name
= "char";
31272 extend_insn
= "extsb %0,%0";
31276 mode_name
= "short";
31278 extend_insn
= "extsh %0,%0";
31284 extend_insn
= "extsw %0,%0";
31288 if (TARGET_POWERPC64
)
31290 mode_name
= "long";
31294 gcc_unreachable ();
31298 gcc_unreachable ();
31301 /* Emit the addis instruction. */
31302 fuse_ops
[0] = target
;
31303 if (satisfies_constraint_L (addis_value
))
31305 fuse_ops
[1] = addis_value
;
31306 addis_str
= "lis %0,%v1";
31309 else if (GET_CODE (addis_value
) == PLUS
)
31311 rtx op0
= XEXP (addis_value
, 0);
31312 rtx op1
= XEXP (addis_value
, 1);
31314 if (REG_P (op0
) && CONST_INT_P (op1
)
31315 && satisfies_constraint_L (op1
))
31319 addis_str
= "addis %0,%1,%v2";
31323 else if (GET_CODE (addis_value
) == HIGH
)
31325 rtx value
= XEXP (addis_value
, 0);
31326 if (GET_CODE (value
) == UNSPEC
&& XINT (value
, 1) == UNSPEC_TOCREL
)
31328 fuse_ops
[1] = XVECEXP (value
, 0, 0); /* symbol ref. */
31329 fuse_ops
[2] = XVECEXP (value
, 0, 1); /* TOC register. */
31331 addis_str
= "addis %0,%2,%1@toc@ha";
31333 else if (TARGET_XCOFF
)
31334 addis_str
= "addis %0,%1@u(%2)";
31337 gcc_unreachable ();
31340 else if (GET_CODE (value
) == PLUS
)
31342 rtx op0
= XEXP (value
, 0);
31343 rtx op1
= XEXP (value
, 1);
31345 if (GET_CODE (op0
) == UNSPEC
31346 && XINT (op0
, 1) == UNSPEC_TOCREL
31347 && CONST_INT_P (op1
))
31349 fuse_ops
[1] = XVECEXP (op0
, 0, 0); /* symbol ref. */
31350 fuse_ops
[2] = XVECEXP (op0
, 0, 1); /* TOC register. */
31353 addis_str
= "addis %0,%2,%1+%3@toc@ha";
31355 else if (TARGET_XCOFF
)
31356 addis_str
= "addis %0,%1+%3@u(%2)";
31359 gcc_unreachable ();
31363 else if (satisfies_constraint_L (value
))
31365 fuse_ops
[1] = value
;
31366 addis_str
= "lis %0,%v1";
31369 else if (TARGET_ELF
&& !TARGET_POWERPC64
&& CONSTANT_P (value
))
31371 fuse_ops
[1] = value
;
31372 addis_str
= "lis %0,%1@ha";
31377 fatal_insn ("Could not generate addis value for fusion", addis_value
);
31379 sprintf (insn_template
, "%s\t\t%s gpr load fusion, type %s", addis_str
,
31380 comment_str
, mode_name
);
31381 output_asm_insn (insn_template
, fuse_ops
);
31383 /* Emit the D-form load instruction. */
31384 if (CONST_INT_P (load_offset
) && satisfies_constraint_I (load_offset
))
31386 sprintf (insn_template
, "%s %%0,%%1(%%0)", load_str
);
31387 fuse_ops
[1] = load_offset
;
31388 output_asm_insn (insn_template
, fuse_ops
);
31391 else if (GET_CODE (load_offset
) == UNSPEC
31392 && XINT (load_offset
, 1) == UNSPEC_TOCREL
)
31395 sprintf (insn_template
, "%s %%0,%%1@toc@l(%%0)", load_str
);
31397 else if (TARGET_XCOFF
)
31398 sprintf (insn_template
, "%s %%0,%%1@l(%%0)", load_str
);
31401 gcc_unreachable ();
31403 fuse_ops
[1] = XVECEXP (load_offset
, 0, 0);
31404 output_asm_insn (insn_template
, fuse_ops
);
31407 else if (GET_CODE (load_offset
) == PLUS
31408 && GET_CODE (XEXP (load_offset
, 0)) == UNSPEC
31409 && XINT (XEXP (load_offset
, 0), 1) == UNSPEC_TOCREL
31410 && CONST_INT_P (XEXP (load_offset
, 1)))
31412 rtx tocrel_unspec
= XEXP (load_offset
, 0);
31414 sprintf (insn_template
, "%s %%0,%%1+%%2@toc@l(%%0)", load_str
);
31416 else if (TARGET_XCOFF
)
31417 sprintf (insn_template
, "%s %%0,%%1+%%2@l(%%0)", load_str
);
31420 gcc_unreachable ();
31422 fuse_ops
[1] = XVECEXP (tocrel_unspec
, 0, 0);
31423 fuse_ops
[2] = XEXP (load_offset
, 1);
31424 output_asm_insn (insn_template
, fuse_ops
);
31427 else if (TARGET_ELF
&& !TARGET_POWERPC64
&& CONSTANT_P (load_offset
))
31429 sprintf (insn_template
, "%s %%0,%%1@l(%%0)", load_str
);
31431 fuse_ops
[1] = load_offset
;
31432 output_asm_insn (insn_template
, fuse_ops
);
31436 fatal_insn ("Unable to generate load offset for fusion", load_offset
);
31438 /* Handle sign extension. The peephole2 pass generates this as a separate
31439 insn, but we handle it just in case it got reattached. */
31442 gcc_assert (extend_insn
!= NULL
);
31443 output_asm_insn (extend_insn
, fuse_ops
);
31450 struct gcc_target targetm
= TARGET_INITIALIZER
;
31452 #include "gt-rs6000.h"