1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2014 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
27 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-attr.h"
35 #include "stringpool.h"
36 #include "stor-layout.h"
38 #include "print-tree.h"
46 #include "basic-block.h"
47 #include "diagnostic-core.h"
53 #include "target-def.h"
54 #include "common/common-target.h"
55 #include "langhooks.h"
58 #include "sched-int.h"
59 #include "pointer-set.h"
60 #include "hash-table.h"
62 #include "basic-block.h"
63 #include "tree-ssa-alias.h"
64 #include "internal-fn.h"
65 #include "gimple-fold.h"
67 #include "gimple-expr.h"
71 #include "gimple-iterator.h"
72 #include "gimple-walk.h"
75 #include "tm-constrs.h"
78 #include "tree-vectorizer.h"
81 #include "target-globals.h"
83 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
86 #include "gstab.h" /* for N_SLINE */
89 #ifndef TARGET_NO_PROTOTYPE
90 #define TARGET_NO_PROTOTYPE 0
93 #define min(A,B) ((A) < (B) ? (A) : (B))
94 #define max(A,B) ((A) > (B) ? (A) : (B))
96 /* Structure used to define the rs6000 stack */
97 typedef struct rs6000_stack
{
98 int reload_completed
; /* stack info won't change from here on */
99 int first_gp_reg_save
; /* first callee saved GP register used */
100 int first_fp_reg_save
; /* first callee saved FP register used */
101 int first_altivec_reg_save
; /* first callee saved AltiVec register used */
102 int lr_save_p
; /* true if the link reg needs to be saved */
103 int cr_save_p
; /* true if the CR reg needs to be saved */
104 unsigned int vrsave_mask
; /* mask of vec registers to save */
105 int push_p
; /* true if we need to allocate stack space */
106 int calls_p
; /* true if the function makes any calls */
107 int world_save_p
; /* true if we're saving *everything*:
108 r13-r31, cr, f14-f31, vrsave, v20-v31 */
109 enum rs6000_abi abi
; /* which ABI to use */
110 int gp_save_offset
; /* offset to save GP regs from initial SP */
111 int fp_save_offset
; /* offset to save FP regs from initial SP */
112 int altivec_save_offset
; /* offset to save AltiVec regs from initial SP */
113 int lr_save_offset
; /* offset to save LR from initial SP */
114 int cr_save_offset
; /* offset to save CR from initial SP */
115 int vrsave_save_offset
; /* offset to save VRSAVE from initial SP */
116 int spe_gp_save_offset
; /* offset to save spe 64-bit gprs */
117 int varargs_save_offset
; /* offset to save the varargs registers */
118 int ehrd_offset
; /* offset to EH return data */
119 int ehcr_offset
; /* offset to EH CR field data */
120 int reg_size
; /* register size (4 or 8) */
121 HOST_WIDE_INT vars_size
; /* variable save area size */
122 int parm_size
; /* outgoing parameter size */
123 int save_size
; /* save area size */
124 int fixed_size
; /* fixed size of stack frame */
125 int gp_size
; /* size of saved GP registers */
126 int fp_size
; /* size of saved FP registers */
127 int altivec_size
; /* size of saved AltiVec registers */
128 int cr_size
; /* size to hold CR if not in save_size */
129 int vrsave_size
; /* size to hold VRSAVE if not in save_size */
130 int altivec_padding_size
; /* size of altivec alignment padding if
132 int spe_gp_size
; /* size of 64-bit GPR save size for SPE */
133 int spe_padding_size
;
134 HOST_WIDE_INT total_size
; /* total bytes allocated for stack */
135 int spe_64bit_regs_used
;
139 /* A C structure for machine-specific, per-function data.
140 This is added to the cfun structure. */
141 typedef struct GTY(()) machine_function
143 /* Some local-dynamic symbol. */
144 const char *some_ld_name
;
145 /* Whether the instruction chain has been scanned already. */
146 int insn_chain_scanned_p
;
147 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
148 int ra_needs_full_frame
;
149 /* Flags if __builtin_return_address (0) was used. */
151 /* Cache lr_save_p after expansion of builtin_eh_return. */
153 /* Whether we need to save the TOC to the reserved stack location in the
154 function prologue. */
155 bool save_toc_in_prologue
;
156 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
157 varargs save area. */
158 HOST_WIDE_INT varargs_save_offset
;
159 /* Temporary stack slot to use for SDmode copies. This slot is
160 64-bits wide and is allocated early enough so that the offset
161 does not overflow the 16-bit load/store offset field. */
162 rtx sdmode_stack_slot
;
163 /* Flag if r2 setup is needed with ELFv2 ABI. */
164 bool r2_setup_needed
;
167 /* Support targetm.vectorize.builtin_mask_for_load. */
168 static GTY(()) tree altivec_builtin_mask_for_load
;
170 /* Set to nonzero once AIX common-mode calls have been defined. */
171 static GTY(()) int common_mode_defined
;
173 /* Label number of label created for -mrelocatable, to call to so we can
174 get the address of the GOT section */
175 static int rs6000_pic_labelno
;
178 /* Counter for labels which are to be placed in .fixup. */
179 int fixuplabelno
= 0;
182 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
185 /* Specify the machine mode that pointers have. After generation of rtl, the
186 compiler makes no further distinction between pointers and any other objects
187 of this machine mode. The type is unsigned since not all things that
188 include rs6000.h also include machmode.h. */
189 unsigned rs6000_pmode
;
191 /* Width in bits of a pointer. */
192 unsigned rs6000_pointer_size
;
194 #ifdef HAVE_AS_GNU_ATTRIBUTE
195 /* Flag whether floating point values have been passed/returned. */
196 static bool rs6000_passes_float
;
197 /* Flag whether vector values have been passed/returned. */
198 static bool rs6000_passes_vector
;
199 /* Flag whether small (<= 8 byte) structures have been returned. */
200 static bool rs6000_returns_struct
;
203 /* Value is TRUE if register/mode pair is acceptable. */
204 bool rs6000_hard_regno_mode_ok_p
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
206 /* Maximum number of registers needed for a given register class and mode. */
207 unsigned char rs6000_class_max_nregs
[NUM_MACHINE_MODES
][LIM_REG_CLASSES
];
209 /* How many registers are needed for a given register and mode. */
210 unsigned char rs6000_hard_regno_nregs
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
212 /* Map register number to register class. */
213 enum reg_class rs6000_regno_regclass
[FIRST_PSEUDO_REGISTER
];
215 static int dbg_cost_ctrl
;
217 /* Built in types. */
218 tree rs6000_builtin_types
[RS6000_BTI_MAX
];
219 tree rs6000_builtin_decls
[RS6000_BUILTIN_COUNT
];
221 /* Flag to say the TOC is initialized */
223 char toc_label_name
[10];
225 /* Cached value of rs6000_variable_issue. This is cached in
226 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
227 static short cached_can_issue_more
;
229 static GTY(()) section
*read_only_data_section
;
230 static GTY(()) section
*private_data_section
;
231 static GTY(()) section
*tls_data_section
;
232 static GTY(()) section
*tls_private_data_section
;
233 static GTY(()) section
*read_only_private_data_section
;
234 static GTY(()) section
*sdata2_section
;
235 static GTY(()) section
*toc_section
;
237 struct builtin_description
239 const HOST_WIDE_INT mask
;
240 const enum insn_code icode
;
241 const char *const name
;
242 const enum rs6000_builtins code
;
245 /* Describe the vector unit used for modes. */
246 enum rs6000_vector rs6000_vector_unit
[NUM_MACHINE_MODES
];
247 enum rs6000_vector rs6000_vector_mem
[NUM_MACHINE_MODES
];
249 /* Register classes for various constraints that are based on the target
251 enum reg_class rs6000_constraints
[RS6000_CONSTRAINT_MAX
];
253 /* Describe the alignment of a vector. */
254 int rs6000_vector_align
[NUM_MACHINE_MODES
];
256 /* Map selected modes to types for builtins. */
257 static GTY(()) tree builtin_mode_to_type
[MAX_MACHINE_MODE
][2];
259 /* What modes to automatically generate reciprocal divide estimate (fre) and
260 reciprocal sqrt (frsqrte) for. */
261 unsigned char rs6000_recip_bits
[MAX_MACHINE_MODE
];
263 /* Masks to determine which reciprocal esitmate instructions to generate
265 enum rs6000_recip_mask
{
266 RECIP_SF_DIV
= 0x001, /* Use divide estimate */
267 RECIP_DF_DIV
= 0x002,
268 RECIP_V4SF_DIV
= 0x004,
269 RECIP_V2DF_DIV
= 0x008,
271 RECIP_SF_RSQRT
= 0x010, /* Use reciprocal sqrt estimate. */
272 RECIP_DF_RSQRT
= 0x020,
273 RECIP_V4SF_RSQRT
= 0x040,
274 RECIP_V2DF_RSQRT
= 0x080,
276 /* Various combination of flags for -mrecip=xxx. */
278 RECIP_ALL
= (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
279 | RECIP_V2DF_DIV
| RECIP_SF_RSQRT
| RECIP_DF_RSQRT
280 | RECIP_V4SF_RSQRT
| RECIP_V2DF_RSQRT
),
282 RECIP_HIGH_PRECISION
= RECIP_ALL
,
284 /* On low precision machines like the power5, don't enable double precision
285 reciprocal square root estimate, since it isn't accurate enough. */
286 RECIP_LOW_PRECISION
= (RECIP_ALL
& ~(RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
))
289 /* -mrecip options. */
292 const char *string
; /* option name */
293 unsigned int mask
; /* mask bits to set */
294 } recip_options
[] = {
295 { "all", RECIP_ALL
},
296 { "none", RECIP_NONE
},
297 { "div", (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
299 { "divf", (RECIP_SF_DIV
| RECIP_V4SF_DIV
) },
300 { "divd", (RECIP_DF_DIV
| RECIP_V2DF_DIV
) },
301 { "rsqrt", (RECIP_SF_RSQRT
| RECIP_DF_RSQRT
| RECIP_V4SF_RSQRT
302 | RECIP_V2DF_RSQRT
) },
303 { "rsqrtf", (RECIP_SF_RSQRT
| RECIP_V4SF_RSQRT
) },
304 { "rsqrtd", (RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
) },
307 /* Pointer to function (in rs6000-c.c) that can define or undefine target
308 macros that have changed. Languages that don't support the preprocessor
309 don't link in rs6000-c.c, so we can't call it directly. */
310 void (*rs6000_target_modify_macros_ptr
) (bool, HOST_WIDE_INT
, HOST_WIDE_INT
);
312 /* Simplfy register classes into simpler classifications. We assume
313 GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
314 check for standard register classes (gpr/floating/altivec/vsx) and
315 floating/vector classes (float/altivec/vsx). */
317 enum rs6000_reg_type
{
330 /* Map register class to register type. */
331 static enum rs6000_reg_type reg_class_to_reg_type
[N_REG_CLASSES
];
333 /* First/last register type for the 'normal' register types (i.e. general
334 purpose, floating point, altivec, and VSX registers). */
335 #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
337 #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
340 /* Register classes we care about in secondary reload or go if legitimate
341 address. We only need to worry about GPR, FPR, and Altivec registers here,
342 along an ANY field that is the OR of the 3 register classes. */
344 enum rs6000_reload_reg_type
{
345 RELOAD_REG_GPR
, /* General purpose registers. */
346 RELOAD_REG_FPR
, /* Traditional floating point regs. */
347 RELOAD_REG_VMX
, /* Altivec (VMX) registers. */
348 RELOAD_REG_ANY
, /* OR of GPR, FPR, Altivec masks. */
352 /* For setting up register classes, loop through the 3 register classes mapping
353 into real registers, and skip the ANY class, which is just an OR of the
355 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
356 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
358 /* Map reload register type to a register in the register class. */
359 struct reload_reg_map_type
{
360 const char *name
; /* Register class name. */
361 int reg
; /* Register in the register class. */
364 static const struct reload_reg_map_type reload_reg_map
[N_RELOAD_REG
] = {
365 { "Gpr", FIRST_GPR_REGNO
}, /* RELOAD_REG_GPR. */
366 { "Fpr", FIRST_FPR_REGNO
}, /* RELOAD_REG_FPR. */
367 { "VMX", FIRST_ALTIVEC_REGNO
}, /* RELOAD_REG_VMX. */
368 { "Any", -1 }, /* RELOAD_REG_ANY. */
371 /* Mask bits for each register class, indexed per mode. Historically the
372 compiler has been more restrictive which types can do PRE_MODIFY instead of
373 PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */
374 typedef unsigned char addr_mask_type
;
376 #define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */
377 #define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */
378 #define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */
379 #define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
380 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */
381 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */
383 /* Register type masks based on the type, of valid addressing modes. */
384 struct rs6000_reg_addr
{
385 enum insn_code reload_load
; /* INSN to reload for loading. */
386 enum insn_code reload_store
; /* INSN to reload for storing. */
387 enum insn_code reload_fpr_gpr
; /* INSN to move from FPR to GPR. */
388 enum insn_code reload_gpr_vsx
; /* INSN to move from GPR to VSX. */
389 enum insn_code reload_vsx_gpr
; /* INSN to move from VSX to GPR. */
390 addr_mask_type addr_mask
[(int)N_RELOAD_REG
]; /* Valid address masks. */
393 static struct rs6000_reg_addr reg_addr
[NUM_MACHINE_MODES
];
395 /* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */
397 mode_supports_pre_incdec_p (enum machine_mode mode
)
399 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_PRE_INCDEC
)
403 /* Helper function to say whether a mode supports PRE_MODIFY. */
405 mode_supports_pre_modify_p (enum machine_mode mode
)
407 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_PRE_MODIFY
)
412 /* Target cpu costs. */
414 struct processor_costs
{
415 const int mulsi
; /* cost of SImode multiplication. */
416 const int mulsi_const
; /* cost of SImode multiplication by constant. */
417 const int mulsi_const9
; /* cost of SImode mult by short constant. */
418 const int muldi
; /* cost of DImode multiplication. */
419 const int divsi
; /* cost of SImode division. */
420 const int divdi
; /* cost of DImode division. */
421 const int fp
; /* cost of simple SFmode and DFmode insns. */
422 const int dmul
; /* cost of DFmode multiplication (and fmadd). */
423 const int sdiv
; /* cost of SFmode division (fdivs). */
424 const int ddiv
; /* cost of DFmode division (fdiv). */
425 const int cache_line_size
; /* cache line size in bytes. */
426 const int l1_cache_size
; /* size of l1 cache, in kilobytes. */
427 const int l2_cache_size
; /* size of l2 cache, in kilobytes. */
428 const int simultaneous_prefetches
; /* number of parallel prefetch
432 const struct processor_costs
*rs6000_cost
;
434 /* Processor costs (relative to an add) */
436 /* Instruction size costs on 32bit processors. */
438 struct processor_costs size32_cost
= {
439 COSTS_N_INSNS (1), /* mulsi */
440 COSTS_N_INSNS (1), /* mulsi_const */
441 COSTS_N_INSNS (1), /* mulsi_const9 */
442 COSTS_N_INSNS (1), /* muldi */
443 COSTS_N_INSNS (1), /* divsi */
444 COSTS_N_INSNS (1), /* divdi */
445 COSTS_N_INSNS (1), /* fp */
446 COSTS_N_INSNS (1), /* dmul */
447 COSTS_N_INSNS (1), /* sdiv */
448 COSTS_N_INSNS (1), /* ddiv */
455 /* Instruction size costs on 64bit processors. */
457 struct processor_costs size64_cost
= {
458 COSTS_N_INSNS (1), /* mulsi */
459 COSTS_N_INSNS (1), /* mulsi_const */
460 COSTS_N_INSNS (1), /* mulsi_const9 */
461 COSTS_N_INSNS (1), /* muldi */
462 COSTS_N_INSNS (1), /* divsi */
463 COSTS_N_INSNS (1), /* divdi */
464 COSTS_N_INSNS (1), /* fp */
465 COSTS_N_INSNS (1), /* dmul */
466 COSTS_N_INSNS (1), /* sdiv */
467 COSTS_N_INSNS (1), /* ddiv */
474 /* Instruction costs on RS64A processors. */
476 struct processor_costs rs64a_cost
= {
477 COSTS_N_INSNS (20), /* mulsi */
478 COSTS_N_INSNS (12), /* mulsi_const */
479 COSTS_N_INSNS (8), /* mulsi_const9 */
480 COSTS_N_INSNS (34), /* muldi */
481 COSTS_N_INSNS (65), /* divsi */
482 COSTS_N_INSNS (67), /* divdi */
483 COSTS_N_INSNS (4), /* fp */
484 COSTS_N_INSNS (4), /* dmul */
485 COSTS_N_INSNS (31), /* sdiv */
486 COSTS_N_INSNS (31), /* ddiv */
487 128, /* cache line size */
493 /* Instruction costs on MPCCORE processors. */
495 struct processor_costs mpccore_cost
= {
496 COSTS_N_INSNS (2), /* mulsi */
497 COSTS_N_INSNS (2), /* mulsi_const */
498 COSTS_N_INSNS (2), /* mulsi_const9 */
499 COSTS_N_INSNS (2), /* muldi */
500 COSTS_N_INSNS (6), /* divsi */
501 COSTS_N_INSNS (6), /* divdi */
502 COSTS_N_INSNS (4), /* fp */
503 COSTS_N_INSNS (5), /* dmul */
504 COSTS_N_INSNS (10), /* sdiv */
505 COSTS_N_INSNS (17), /* ddiv */
506 32, /* cache line size */
512 /* Instruction costs on PPC403 processors. */
514 struct processor_costs ppc403_cost
= {
515 COSTS_N_INSNS (4), /* mulsi */
516 COSTS_N_INSNS (4), /* mulsi_const */
517 COSTS_N_INSNS (4), /* mulsi_const9 */
518 COSTS_N_INSNS (4), /* muldi */
519 COSTS_N_INSNS (33), /* divsi */
520 COSTS_N_INSNS (33), /* divdi */
521 COSTS_N_INSNS (11), /* fp */
522 COSTS_N_INSNS (11), /* dmul */
523 COSTS_N_INSNS (11), /* sdiv */
524 COSTS_N_INSNS (11), /* ddiv */
525 32, /* cache line size */
531 /* Instruction costs on PPC405 processors. */
533 struct processor_costs ppc405_cost
= {
534 COSTS_N_INSNS (5), /* mulsi */
535 COSTS_N_INSNS (4), /* mulsi_const */
536 COSTS_N_INSNS (3), /* mulsi_const9 */
537 COSTS_N_INSNS (5), /* muldi */
538 COSTS_N_INSNS (35), /* divsi */
539 COSTS_N_INSNS (35), /* divdi */
540 COSTS_N_INSNS (11), /* fp */
541 COSTS_N_INSNS (11), /* dmul */
542 COSTS_N_INSNS (11), /* sdiv */
543 COSTS_N_INSNS (11), /* ddiv */
544 32, /* cache line size */
550 /* Instruction costs on PPC440 processors. */
552 struct processor_costs ppc440_cost
= {
553 COSTS_N_INSNS (3), /* mulsi */
554 COSTS_N_INSNS (2), /* mulsi_const */
555 COSTS_N_INSNS (2), /* mulsi_const9 */
556 COSTS_N_INSNS (3), /* muldi */
557 COSTS_N_INSNS (34), /* divsi */
558 COSTS_N_INSNS (34), /* divdi */
559 COSTS_N_INSNS (5), /* fp */
560 COSTS_N_INSNS (5), /* dmul */
561 COSTS_N_INSNS (19), /* sdiv */
562 COSTS_N_INSNS (33), /* ddiv */
563 32, /* cache line size */
569 /* Instruction costs on PPC476 processors. */
571 struct processor_costs ppc476_cost
= {
572 COSTS_N_INSNS (4), /* mulsi */
573 COSTS_N_INSNS (4), /* mulsi_const */
574 COSTS_N_INSNS (4), /* mulsi_const9 */
575 COSTS_N_INSNS (4), /* muldi */
576 COSTS_N_INSNS (11), /* divsi */
577 COSTS_N_INSNS (11), /* divdi */
578 COSTS_N_INSNS (6), /* fp */
579 COSTS_N_INSNS (6), /* dmul */
580 COSTS_N_INSNS (19), /* sdiv */
581 COSTS_N_INSNS (33), /* ddiv */
582 32, /* l1 cache line size */
588 /* Instruction costs on PPC601 processors. */
590 struct processor_costs ppc601_cost
= {
591 COSTS_N_INSNS (5), /* mulsi */
592 COSTS_N_INSNS (5), /* mulsi_const */
593 COSTS_N_INSNS (5), /* mulsi_const9 */
594 COSTS_N_INSNS (5), /* muldi */
595 COSTS_N_INSNS (36), /* divsi */
596 COSTS_N_INSNS (36), /* divdi */
597 COSTS_N_INSNS (4), /* fp */
598 COSTS_N_INSNS (5), /* dmul */
599 COSTS_N_INSNS (17), /* sdiv */
600 COSTS_N_INSNS (31), /* ddiv */
601 32, /* cache line size */
607 /* Instruction costs on PPC603 processors. */
609 struct processor_costs ppc603_cost
= {
610 COSTS_N_INSNS (5), /* mulsi */
611 COSTS_N_INSNS (3), /* mulsi_const */
612 COSTS_N_INSNS (2), /* mulsi_const9 */
613 COSTS_N_INSNS (5), /* muldi */
614 COSTS_N_INSNS (37), /* divsi */
615 COSTS_N_INSNS (37), /* divdi */
616 COSTS_N_INSNS (3), /* fp */
617 COSTS_N_INSNS (4), /* dmul */
618 COSTS_N_INSNS (18), /* sdiv */
619 COSTS_N_INSNS (33), /* ddiv */
620 32, /* cache line size */
626 /* Instruction costs on PPC604 processors. */
628 struct processor_costs ppc604_cost
= {
629 COSTS_N_INSNS (4), /* mulsi */
630 COSTS_N_INSNS (4), /* mulsi_const */
631 COSTS_N_INSNS (4), /* mulsi_const9 */
632 COSTS_N_INSNS (4), /* muldi */
633 COSTS_N_INSNS (20), /* divsi */
634 COSTS_N_INSNS (20), /* divdi */
635 COSTS_N_INSNS (3), /* fp */
636 COSTS_N_INSNS (3), /* dmul */
637 COSTS_N_INSNS (18), /* sdiv */
638 COSTS_N_INSNS (32), /* ddiv */
639 32, /* cache line size */
645 /* Instruction costs on PPC604e processors. */
647 struct processor_costs ppc604e_cost
= {
648 COSTS_N_INSNS (2), /* mulsi */
649 COSTS_N_INSNS (2), /* mulsi_const */
650 COSTS_N_INSNS (2), /* mulsi_const9 */
651 COSTS_N_INSNS (2), /* muldi */
652 COSTS_N_INSNS (20), /* divsi */
653 COSTS_N_INSNS (20), /* divdi */
654 COSTS_N_INSNS (3), /* fp */
655 COSTS_N_INSNS (3), /* dmul */
656 COSTS_N_INSNS (18), /* sdiv */
657 COSTS_N_INSNS (32), /* ddiv */
658 32, /* cache line size */
664 /* Instruction costs on PPC620 processors. */
666 struct processor_costs ppc620_cost
= {
667 COSTS_N_INSNS (5), /* mulsi */
668 COSTS_N_INSNS (4), /* mulsi_const */
669 COSTS_N_INSNS (3), /* mulsi_const9 */
670 COSTS_N_INSNS (7), /* muldi */
671 COSTS_N_INSNS (21), /* divsi */
672 COSTS_N_INSNS (37), /* divdi */
673 COSTS_N_INSNS (3), /* fp */
674 COSTS_N_INSNS (3), /* dmul */
675 COSTS_N_INSNS (18), /* sdiv */
676 COSTS_N_INSNS (32), /* ddiv */
677 128, /* cache line size */
683 /* Instruction costs on PPC630 processors. */
685 struct processor_costs ppc630_cost
= {
686 COSTS_N_INSNS (5), /* mulsi */
687 COSTS_N_INSNS (4), /* mulsi_const */
688 COSTS_N_INSNS (3), /* mulsi_const9 */
689 COSTS_N_INSNS (7), /* muldi */
690 COSTS_N_INSNS (21), /* divsi */
691 COSTS_N_INSNS (37), /* divdi */
692 COSTS_N_INSNS (3), /* fp */
693 COSTS_N_INSNS (3), /* dmul */
694 COSTS_N_INSNS (17), /* sdiv */
695 COSTS_N_INSNS (21), /* ddiv */
696 128, /* cache line size */
702 /* Instruction costs on Cell processor. */
703 /* COSTS_N_INSNS (1) ~ one add. */
705 struct processor_costs ppccell_cost
= {
706 COSTS_N_INSNS (9/2)+2, /* mulsi */
707 COSTS_N_INSNS (6/2), /* mulsi_const */
708 COSTS_N_INSNS (6/2), /* mulsi_const9 */
709 COSTS_N_INSNS (15/2)+2, /* muldi */
710 COSTS_N_INSNS (38/2), /* divsi */
711 COSTS_N_INSNS (70/2), /* divdi */
712 COSTS_N_INSNS (10/2), /* fp */
713 COSTS_N_INSNS (10/2), /* dmul */
714 COSTS_N_INSNS (74/2), /* sdiv */
715 COSTS_N_INSNS (74/2), /* ddiv */
716 128, /* cache line size */
722 /* Instruction costs on PPC750 and PPC7400 processors. */
724 struct processor_costs ppc750_cost
= {
725 COSTS_N_INSNS (5), /* mulsi */
726 COSTS_N_INSNS (3), /* mulsi_const */
727 COSTS_N_INSNS (2), /* mulsi_const9 */
728 COSTS_N_INSNS (5), /* muldi */
729 COSTS_N_INSNS (17), /* divsi */
730 COSTS_N_INSNS (17), /* divdi */
731 COSTS_N_INSNS (3), /* fp */
732 COSTS_N_INSNS (3), /* dmul */
733 COSTS_N_INSNS (17), /* sdiv */
734 COSTS_N_INSNS (31), /* ddiv */
735 32, /* cache line size */
741 /* Instruction costs on PPC7450 processors. */
743 struct processor_costs ppc7450_cost
= {
744 COSTS_N_INSNS (4), /* mulsi */
745 COSTS_N_INSNS (3), /* mulsi_const */
746 COSTS_N_INSNS (3), /* mulsi_const9 */
747 COSTS_N_INSNS (4), /* muldi */
748 COSTS_N_INSNS (23), /* divsi */
749 COSTS_N_INSNS (23), /* divdi */
750 COSTS_N_INSNS (5), /* fp */
751 COSTS_N_INSNS (5), /* dmul */
752 COSTS_N_INSNS (21), /* sdiv */
753 COSTS_N_INSNS (35), /* ddiv */
754 32, /* cache line size */
760 /* Instruction costs on PPC8540 processors. */
762 struct processor_costs ppc8540_cost
= {
763 COSTS_N_INSNS (4), /* mulsi */
764 COSTS_N_INSNS (4), /* mulsi_const */
765 COSTS_N_INSNS (4), /* mulsi_const9 */
766 COSTS_N_INSNS (4), /* muldi */
767 COSTS_N_INSNS (19), /* divsi */
768 COSTS_N_INSNS (19), /* divdi */
769 COSTS_N_INSNS (4), /* fp */
770 COSTS_N_INSNS (4), /* dmul */
771 COSTS_N_INSNS (29), /* sdiv */
772 COSTS_N_INSNS (29), /* ddiv */
773 32, /* cache line size */
776 1, /* prefetch streams /*/
779 /* Instruction costs on E300C2 and E300C3 cores. */
781 struct processor_costs ppce300c2c3_cost
= {
782 COSTS_N_INSNS (4), /* mulsi */
783 COSTS_N_INSNS (4), /* mulsi_const */
784 COSTS_N_INSNS (4), /* mulsi_const9 */
785 COSTS_N_INSNS (4), /* muldi */
786 COSTS_N_INSNS (19), /* divsi */
787 COSTS_N_INSNS (19), /* divdi */
788 COSTS_N_INSNS (3), /* fp */
789 COSTS_N_INSNS (4), /* dmul */
790 COSTS_N_INSNS (18), /* sdiv */
791 COSTS_N_INSNS (33), /* ddiv */
795 1, /* prefetch streams /*/
798 /* Instruction costs on PPCE500MC processors. */
800 struct processor_costs ppce500mc_cost
= {
801 COSTS_N_INSNS (4), /* mulsi */
802 COSTS_N_INSNS (4), /* mulsi_const */
803 COSTS_N_INSNS (4), /* mulsi_const9 */
804 COSTS_N_INSNS (4), /* muldi */
805 COSTS_N_INSNS (14), /* divsi */
806 COSTS_N_INSNS (14), /* divdi */
807 COSTS_N_INSNS (8), /* fp */
808 COSTS_N_INSNS (10), /* dmul */
809 COSTS_N_INSNS (36), /* sdiv */
810 COSTS_N_INSNS (66), /* ddiv */
811 64, /* cache line size */
814 1, /* prefetch streams /*/
817 /* Instruction costs on PPCE500MC64 processors. */
819 struct processor_costs ppce500mc64_cost
= {
820 COSTS_N_INSNS (4), /* mulsi */
821 COSTS_N_INSNS (4), /* mulsi_const */
822 COSTS_N_INSNS (4), /* mulsi_const9 */
823 COSTS_N_INSNS (4), /* muldi */
824 COSTS_N_INSNS (14), /* divsi */
825 COSTS_N_INSNS (14), /* divdi */
826 COSTS_N_INSNS (4), /* fp */
827 COSTS_N_INSNS (10), /* dmul */
828 COSTS_N_INSNS (36), /* sdiv */
829 COSTS_N_INSNS (66), /* ddiv */
830 64, /* cache line size */
833 1, /* prefetch streams /*/
836 /* Instruction costs on PPCE5500 processors. */
838 struct processor_costs ppce5500_cost
= {
839 COSTS_N_INSNS (5), /* mulsi */
840 COSTS_N_INSNS (5), /* mulsi_const */
841 COSTS_N_INSNS (4), /* mulsi_const9 */
842 COSTS_N_INSNS (5), /* muldi */
843 COSTS_N_INSNS (14), /* divsi */
844 COSTS_N_INSNS (14), /* divdi */
845 COSTS_N_INSNS (7), /* fp */
846 COSTS_N_INSNS (10), /* dmul */
847 COSTS_N_INSNS (36), /* sdiv */
848 COSTS_N_INSNS (66), /* ddiv */
849 64, /* cache line size */
852 1, /* prefetch streams /*/
855 /* Instruction costs on PPCE6500 processors. */
857 struct processor_costs ppce6500_cost
= {
858 COSTS_N_INSNS (5), /* mulsi */
859 COSTS_N_INSNS (5), /* mulsi_const */
860 COSTS_N_INSNS (4), /* mulsi_const9 */
861 COSTS_N_INSNS (5), /* muldi */
862 COSTS_N_INSNS (14), /* divsi */
863 COSTS_N_INSNS (14), /* divdi */
864 COSTS_N_INSNS (7), /* fp */
865 COSTS_N_INSNS (10), /* dmul */
866 COSTS_N_INSNS (36), /* sdiv */
867 COSTS_N_INSNS (66), /* ddiv */
868 64, /* cache line size */
871 1, /* prefetch streams /*/
874 /* Instruction costs on AppliedMicro Titan processors. */
876 struct processor_costs titan_cost
= {
877 COSTS_N_INSNS (5), /* mulsi */
878 COSTS_N_INSNS (5), /* mulsi_const */
879 COSTS_N_INSNS (5), /* mulsi_const9 */
880 COSTS_N_INSNS (5), /* muldi */
881 COSTS_N_INSNS (18), /* divsi */
882 COSTS_N_INSNS (18), /* divdi */
883 COSTS_N_INSNS (10), /* fp */
884 COSTS_N_INSNS (10), /* dmul */
885 COSTS_N_INSNS (46), /* sdiv */
886 COSTS_N_INSNS (72), /* ddiv */
887 32, /* cache line size */
890 1, /* prefetch streams /*/
893 /* Instruction costs on POWER4 and POWER5 processors. */
895 struct processor_costs power4_cost
= {
896 COSTS_N_INSNS (3), /* mulsi */
897 COSTS_N_INSNS (2), /* mulsi_const */
898 COSTS_N_INSNS (2), /* mulsi_const9 */
899 COSTS_N_INSNS (4), /* muldi */
900 COSTS_N_INSNS (18), /* divsi */
901 COSTS_N_INSNS (34), /* divdi */
902 COSTS_N_INSNS (3), /* fp */
903 COSTS_N_INSNS (3), /* dmul */
904 COSTS_N_INSNS (17), /* sdiv */
905 COSTS_N_INSNS (17), /* ddiv */
906 128, /* cache line size */
909 8, /* prefetch streams /*/
912 /* Instruction costs on POWER6 processors. */
914 struct processor_costs power6_cost
= {
915 COSTS_N_INSNS (8), /* mulsi */
916 COSTS_N_INSNS (8), /* mulsi_const */
917 COSTS_N_INSNS (8), /* mulsi_const9 */
918 COSTS_N_INSNS (8), /* muldi */
919 COSTS_N_INSNS (22), /* divsi */
920 COSTS_N_INSNS (28), /* divdi */
921 COSTS_N_INSNS (3), /* fp */
922 COSTS_N_INSNS (3), /* dmul */
923 COSTS_N_INSNS (13), /* sdiv */
924 COSTS_N_INSNS (16), /* ddiv */
925 128, /* cache line size */
928 16, /* prefetch streams */
931 /* Instruction costs on POWER7 processors. */
933 struct processor_costs power7_cost
= {
934 COSTS_N_INSNS (2), /* mulsi */
935 COSTS_N_INSNS (2), /* mulsi_const */
936 COSTS_N_INSNS (2), /* mulsi_const9 */
937 COSTS_N_INSNS (2), /* muldi */
938 COSTS_N_INSNS (18), /* divsi */
939 COSTS_N_INSNS (34), /* divdi */
940 COSTS_N_INSNS (3), /* fp */
941 COSTS_N_INSNS (3), /* dmul */
942 COSTS_N_INSNS (13), /* sdiv */
943 COSTS_N_INSNS (16), /* ddiv */
944 128, /* cache line size */
947 12, /* prefetch streams */
950 /* Instruction costs on POWER8 processors. */
952 struct processor_costs power8_cost
= {
953 COSTS_N_INSNS (3), /* mulsi */
954 COSTS_N_INSNS (3), /* mulsi_const */
955 COSTS_N_INSNS (3), /* mulsi_const9 */
956 COSTS_N_INSNS (3), /* muldi */
957 COSTS_N_INSNS (19), /* divsi */
958 COSTS_N_INSNS (35), /* divdi */
959 COSTS_N_INSNS (3), /* fp */
960 COSTS_N_INSNS (3), /* dmul */
961 COSTS_N_INSNS (14), /* sdiv */
962 COSTS_N_INSNS (17), /* ddiv */
963 128, /* cache line size */
966 12, /* prefetch streams */
969 /* Instruction costs on POWER A2 processors. */
971 struct processor_costs ppca2_cost
= {
972 COSTS_N_INSNS (16), /* mulsi */
973 COSTS_N_INSNS (16), /* mulsi_const */
974 COSTS_N_INSNS (16), /* mulsi_const9 */
975 COSTS_N_INSNS (16), /* muldi */
976 COSTS_N_INSNS (22), /* divsi */
977 COSTS_N_INSNS (28), /* divdi */
978 COSTS_N_INSNS (3), /* fp */
979 COSTS_N_INSNS (3), /* dmul */
980 COSTS_N_INSNS (59), /* sdiv */
981 COSTS_N_INSNS (72), /* ddiv */
985 16, /* prefetch streams */
989 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
990 #undef RS6000_BUILTIN_1
991 #undef RS6000_BUILTIN_2
992 #undef RS6000_BUILTIN_3
993 #undef RS6000_BUILTIN_A
994 #undef RS6000_BUILTIN_D
995 #undef RS6000_BUILTIN_E
996 #undef RS6000_BUILTIN_H
997 #undef RS6000_BUILTIN_P
998 #undef RS6000_BUILTIN_Q
999 #undef RS6000_BUILTIN_S
1000 #undef RS6000_BUILTIN_X
1002 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
1003 { NAME, ICODE, MASK, ATTR },
1005 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
1006 { NAME, ICODE, MASK, ATTR },
1008 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
1009 { NAME, ICODE, MASK, ATTR },
1011 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
1012 { NAME, ICODE, MASK, ATTR },
1014 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
1015 { NAME, ICODE, MASK, ATTR },
1017 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
1018 { NAME, ICODE, MASK, ATTR },
1020 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
1021 { NAME, ICODE, MASK, ATTR },
1023 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
1024 { NAME, ICODE, MASK, ATTR },
1026 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
1027 { NAME, ICODE, MASK, ATTR },
1029 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
1030 { NAME, ICODE, MASK, ATTR },
1032 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
1033 { NAME, ICODE, MASK, ATTR },
1035 struct rs6000_builtin_info_type
{
1037 const enum insn_code icode
;
1038 const HOST_WIDE_INT mask
;
1039 const unsigned attr
;
1042 static const struct rs6000_builtin_info_type rs6000_builtin_info
[] =
1044 #include "rs6000-builtin.def"
1047 #undef RS6000_BUILTIN_1
1048 #undef RS6000_BUILTIN_2
1049 #undef RS6000_BUILTIN_3
1050 #undef RS6000_BUILTIN_A
1051 #undef RS6000_BUILTIN_D
1052 #undef RS6000_BUILTIN_E
1053 #undef RS6000_BUILTIN_H
1054 #undef RS6000_BUILTIN_P
1055 #undef RS6000_BUILTIN_Q
1056 #undef RS6000_BUILTIN_S
1057 #undef RS6000_BUILTIN_X
1059 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
1060 static tree (*rs6000_veclib_handler
) (tree
, tree
, tree
);
1063 static bool rs6000_debug_legitimate_address_p (enum machine_mode
, rtx
, bool);
1064 static bool spe_func_has_64bit_regs_p (void);
1065 static struct machine_function
* rs6000_init_machine_status (void);
1066 static int rs6000_ra_ever_killed (void);
1067 static tree
rs6000_handle_longcall_attribute (tree
*, tree
, tree
, int, bool *);
1068 static tree
rs6000_handle_altivec_attribute (tree
*, tree
, tree
, int, bool *);
1069 static tree
rs6000_handle_struct_attribute (tree
*, tree
, tree
, int, bool *);
1070 static tree
rs6000_builtin_vectorized_libmass (tree
, tree
, tree
);
1071 static rtx
rs6000_emit_set_long_const (rtx
, HOST_WIDE_INT
, HOST_WIDE_INT
);
1072 static int rs6000_memory_move_cost (enum machine_mode
, reg_class_t
, bool);
1073 static bool rs6000_debug_rtx_costs (rtx
, int, int, int, int *, bool);
1074 static int rs6000_debug_address_cost (rtx
, enum machine_mode
, addr_space_t
,
1076 static int rs6000_debug_adjust_cost (rtx
, rtx
, rtx
, int);
1077 static bool is_microcoded_insn (rtx
);
1078 static bool is_nonpipeline_insn (rtx
);
1079 static bool is_cracked_insn (rtx
);
1080 static bool is_load_insn (rtx
, rtx
*);
1081 static bool is_store_insn (rtx
, rtx
*);
1082 static bool set_to_load_agen (rtx
,rtx
);
1083 static bool insn_terminates_group_p (rtx
, enum group_termination
);
1084 static bool insn_must_be_first_in_group (rtx
);
1085 static bool insn_must_be_last_in_group (rtx
);
1086 static void altivec_init_builtins (void);
1087 static tree
builtin_function_type (enum machine_mode
, enum machine_mode
,
1088 enum machine_mode
, enum machine_mode
,
1089 enum rs6000_builtins
, const char *name
);
1090 static void rs6000_common_init_builtins (void);
1091 static void paired_init_builtins (void);
1092 static rtx
paired_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
1093 static void spe_init_builtins (void);
1094 static void htm_init_builtins (void);
1095 static rtx
spe_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
1096 static rtx
spe_expand_evsel_builtin (enum insn_code
, tree
, rtx
);
1097 static int rs6000_emit_int_cmove (rtx
, rtx
, rtx
, rtx
);
1098 static rs6000_stack_t
*rs6000_stack_info (void);
1099 static void is_altivec_return_reg (rtx
, void *);
1100 int easy_vector_constant (rtx
, enum machine_mode
);
1101 static rtx
rs6000_debug_legitimize_address (rtx
, rtx
, enum machine_mode
);
1102 static rtx
rs6000_legitimize_tls_address (rtx
, enum tls_model
);
1103 static int rs6000_tls_symbol_ref_1 (rtx
*, void *);
1104 static int rs6000_get_some_local_dynamic_name_1 (rtx
*, void *);
1105 static rtx
rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*, const_tree
,
1108 static void macho_branch_islands (void);
1110 static rtx
rs6000_legitimize_reload_address (rtx
, enum machine_mode
, int, int,
1112 static rtx
rs6000_debug_legitimize_reload_address (rtx
, enum machine_mode
, int,
1114 static bool rs6000_mode_dependent_address (const_rtx
);
1115 static bool rs6000_debug_mode_dependent_address (const_rtx
);
1116 static enum reg_class
rs6000_secondary_reload_class (enum reg_class
,
1117 enum machine_mode
, rtx
);
1118 static enum reg_class
rs6000_debug_secondary_reload_class (enum reg_class
,
1121 static enum reg_class
rs6000_preferred_reload_class (rtx
, enum reg_class
);
1122 static enum reg_class
rs6000_debug_preferred_reload_class (rtx
,
1124 static bool rs6000_secondary_memory_needed (enum reg_class
, enum reg_class
,
1126 static bool rs6000_debug_secondary_memory_needed (enum reg_class
,
1129 static bool rs6000_cannot_change_mode_class (enum machine_mode
,
1132 static bool rs6000_debug_cannot_change_mode_class (enum machine_mode
,
1135 static bool rs6000_save_toc_in_prologue_p (void);
1137 rtx (*rs6000_legitimize_reload_address_ptr
) (rtx
, enum machine_mode
, int, int,
1139 = rs6000_legitimize_reload_address
;
1141 static bool (*rs6000_mode_dependent_address_ptr
) (const_rtx
)
1142 = rs6000_mode_dependent_address
;
1144 enum reg_class (*rs6000_secondary_reload_class_ptr
) (enum reg_class
,
1145 enum machine_mode
, rtx
)
1146 = rs6000_secondary_reload_class
;
1148 enum reg_class (*rs6000_preferred_reload_class_ptr
) (rtx
, enum reg_class
)
1149 = rs6000_preferred_reload_class
;
1151 bool (*rs6000_secondary_memory_needed_ptr
) (enum reg_class
, enum reg_class
,
1153 = rs6000_secondary_memory_needed
;
1155 bool (*rs6000_cannot_change_mode_class_ptr
) (enum machine_mode
,
1158 = rs6000_cannot_change_mode_class
;
1160 const int INSN_NOT_AVAILABLE
= -1;
1162 static void rs6000_print_isa_options (FILE *, int, const char *,
1164 static void rs6000_print_builtin_options (FILE *, int, const char *,
1167 static enum rs6000_reg_type
register_to_reg_type (rtx
, bool *);
1168 static bool rs6000_secondary_reload_move (enum rs6000_reg_type
,
1169 enum rs6000_reg_type
,
1171 secondary_reload_info
*,
1174 /* Hash table stuff for keeping track of TOC entries. */
1176 struct GTY(()) toc_hash_struct
1178 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1179 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1181 enum machine_mode key_mode
;
1185 static GTY ((param_is (struct toc_hash_struct
))) htab_t toc_hash_table
;
1187 /* Hash table to keep track of the argument types for builtin functions. */
1189 struct GTY(()) builtin_hash_struct
1192 enum machine_mode mode
[4]; /* return value + 3 arguments. */
1193 unsigned char uns_p
[4]; /* and whether the types are unsigned. */
1196 static GTY ((param_is (struct builtin_hash_struct
))) htab_t builtin_hash_table
;
1199 /* Default register names. */
1200 char rs6000_reg_names
[][8] =
1202 "0", "1", "2", "3", "4", "5", "6", "7",
1203 "8", "9", "10", "11", "12", "13", "14", "15",
1204 "16", "17", "18", "19", "20", "21", "22", "23",
1205 "24", "25", "26", "27", "28", "29", "30", "31",
1206 "0", "1", "2", "3", "4", "5", "6", "7",
1207 "8", "9", "10", "11", "12", "13", "14", "15",
1208 "16", "17", "18", "19", "20", "21", "22", "23",
1209 "24", "25", "26", "27", "28", "29", "30", "31",
1210 "mq", "lr", "ctr","ap",
1211 "0", "1", "2", "3", "4", "5", "6", "7",
1213 /* AltiVec registers. */
1214 "0", "1", "2", "3", "4", "5", "6", "7",
1215 "8", "9", "10", "11", "12", "13", "14", "15",
1216 "16", "17", "18", "19", "20", "21", "22", "23",
1217 "24", "25", "26", "27", "28", "29", "30", "31",
1219 /* SPE registers. */
1220 "spe_acc", "spefscr",
1221 /* Soft frame pointer. */
1223 /* HTM SPR registers. */
1224 "tfhar", "tfiar", "texasr"
1227 #ifdef TARGET_REGNAMES
1228 static const char alt_reg_names
[][8] =
1230 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1231 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1232 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1233 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1234 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1235 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1236 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1237 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1238 "mq", "lr", "ctr", "ap",
1239 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1241 /* AltiVec registers. */
1242 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1243 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1244 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1245 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1247 /* SPE registers. */
1248 "spe_acc", "spefscr",
1249 /* Soft frame pointer. */
1251 /* HTM SPR registers. */
1252 "tfhar", "tfiar", "texasr"
1256 /* Table of valid machine attributes. */
1258 static const struct attribute_spec rs6000_attribute_table
[] =
1260 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
1261 affects_type_identity } */
1262 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute
,
1264 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1266 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1268 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1270 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1272 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1273 SUBTARGET_ATTRIBUTE_TABLE
,
1275 { NULL
, 0, 0, false, false, false, NULL
, false }
1278 #ifndef TARGET_PROFILE_KERNEL
1279 #define TARGET_PROFILE_KERNEL 0
1282 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1283 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1285 /* Initialize the GCC target structure. */
1286 #undef TARGET_ATTRIBUTE_TABLE
1287 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1288 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1289 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1290 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1291 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1293 #undef TARGET_ASM_ALIGNED_DI_OP
1294 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1296 /* Default unaligned ops are only provided for ELF. Find the ops needed
1297 for non-ELF systems. */
1298 #ifndef OBJECT_FORMAT_ELF
1300 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1302 #undef TARGET_ASM_UNALIGNED_HI_OP
1303 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1304 #undef TARGET_ASM_UNALIGNED_SI_OP
1305 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1306 #undef TARGET_ASM_UNALIGNED_DI_OP
1307 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1310 #undef TARGET_ASM_UNALIGNED_HI_OP
1311 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1312 #undef TARGET_ASM_UNALIGNED_SI_OP
1313 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1314 #undef TARGET_ASM_UNALIGNED_DI_OP
1315 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1316 #undef TARGET_ASM_ALIGNED_DI_OP
1317 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1321 /* This hook deals with fixups for relocatable code and DI-mode objects
1323 #undef TARGET_ASM_INTEGER
1324 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1326 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1327 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1328 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1331 #undef TARGET_SET_UP_BY_PROLOGUE
1332 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1334 #undef TARGET_HAVE_TLS
1335 #define TARGET_HAVE_TLS HAVE_AS_TLS
1337 #undef TARGET_CANNOT_FORCE_CONST_MEM
1338 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1340 #undef TARGET_DELEGITIMIZE_ADDRESS
1341 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1343 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1344 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1346 #undef TARGET_ASM_FUNCTION_PROLOGUE
1347 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1348 #undef TARGET_ASM_FUNCTION_EPILOGUE
1349 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1351 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1352 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1354 #undef TARGET_LEGITIMIZE_ADDRESS
1355 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1357 #undef TARGET_SCHED_VARIABLE_ISSUE
1358 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1360 #undef TARGET_SCHED_ISSUE_RATE
1361 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1362 #undef TARGET_SCHED_ADJUST_COST
1363 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1364 #undef TARGET_SCHED_ADJUST_PRIORITY
1365 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1366 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1367 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1368 #undef TARGET_SCHED_INIT
1369 #define TARGET_SCHED_INIT rs6000_sched_init
1370 #undef TARGET_SCHED_FINISH
1371 #define TARGET_SCHED_FINISH rs6000_sched_finish
1372 #undef TARGET_SCHED_REORDER
1373 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1374 #undef TARGET_SCHED_REORDER2
1375 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1377 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1378 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1380 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1381 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1383 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1384 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1385 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1386 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1387 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1388 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1389 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1390 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1392 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1393 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1394 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1395 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1396 rs6000_builtin_support_vector_misalignment
1397 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1398 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1399 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1400 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1401 rs6000_builtin_vectorization_cost
1402 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1403 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1404 rs6000_preferred_simd_mode
1405 #undef TARGET_VECTORIZE_INIT_COST
1406 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1407 #undef TARGET_VECTORIZE_ADD_STMT_COST
1408 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1409 #undef TARGET_VECTORIZE_FINISH_COST
1410 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1411 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1412 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1414 #undef TARGET_INIT_BUILTINS
1415 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1416 #undef TARGET_BUILTIN_DECL
1417 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1419 #undef TARGET_EXPAND_BUILTIN
1420 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1422 #undef TARGET_MANGLE_TYPE
1423 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1425 #undef TARGET_INIT_LIBFUNCS
1426 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1429 #undef TARGET_BINDS_LOCAL_P
1430 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1433 #undef TARGET_MS_BITFIELD_LAYOUT_P
1434 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1436 #undef TARGET_ASM_OUTPUT_MI_THUNK
1437 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1439 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1440 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1442 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1443 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1445 #undef TARGET_REGISTER_MOVE_COST
1446 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1447 #undef TARGET_MEMORY_MOVE_COST
1448 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1449 #undef TARGET_RTX_COSTS
1450 #define TARGET_RTX_COSTS rs6000_rtx_costs
1451 #undef TARGET_ADDRESS_COST
1452 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1454 #undef TARGET_DWARF_REGISTER_SPAN
1455 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1457 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1458 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1460 #undef TARGET_MEMBER_TYPE_FORCES_BLK
1461 #define TARGET_MEMBER_TYPE_FORCES_BLK rs6000_member_type_forces_blk
1463 /* On rs6000, function arguments are promoted, as are function return
1465 #undef TARGET_PROMOTE_FUNCTION_MODE
1466 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
1468 #undef TARGET_RETURN_IN_MEMORY
1469 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1471 #undef TARGET_RETURN_IN_MSB
1472 #define TARGET_RETURN_IN_MSB rs6000_return_in_msb
1474 #undef TARGET_SETUP_INCOMING_VARARGS
1475 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1477 /* Always strict argument naming on rs6000. */
1478 #undef TARGET_STRICT_ARGUMENT_NAMING
1479 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1480 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1481 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1482 #undef TARGET_SPLIT_COMPLEX_ARG
1483 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1484 #undef TARGET_MUST_PASS_IN_STACK
1485 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1486 #undef TARGET_PASS_BY_REFERENCE
1487 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1488 #undef TARGET_ARG_PARTIAL_BYTES
1489 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1490 #undef TARGET_FUNCTION_ARG_ADVANCE
1491 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1492 #undef TARGET_FUNCTION_ARG
1493 #define TARGET_FUNCTION_ARG rs6000_function_arg
1494 #undef TARGET_FUNCTION_ARG_BOUNDARY
1495 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1497 #undef TARGET_BUILD_BUILTIN_VA_LIST
1498 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1500 #undef TARGET_EXPAND_BUILTIN_VA_START
1501 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1503 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1504 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1506 #undef TARGET_EH_RETURN_FILTER_MODE
1507 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1509 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1510 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1512 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1513 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1515 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1516 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1518 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1519 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1521 #undef TARGET_OPTION_OVERRIDE
1522 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1524 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1525 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1526 rs6000_builtin_vectorized_function
1529 #undef TARGET_STACK_PROTECT_FAIL
1530 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1533 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1534 The PowerPC architecture requires only weak consistency among
1535 processors--that is, memory accesses between processors need not be
1536 sequentially consistent and memory accesses among processors can occur
1537 in any order. The ability to order memory accesses weakly provides
1538 opportunities for more efficient use of the system bus. Unless a
1539 dependency exists, the 604e allows read operations to precede store
1541 #undef TARGET_RELAXED_ORDERING
1542 #define TARGET_RELAXED_ORDERING true
1545 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1546 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1549 /* Use a 32-bit anchor range. This leads to sequences like:
1551 addis tmp,anchor,high
1554 where tmp itself acts as an anchor, and can be shared between
1555 accesses to the same 64k page. */
1556 #undef TARGET_MIN_ANCHOR_OFFSET
1557 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1558 #undef TARGET_MAX_ANCHOR_OFFSET
1559 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1560 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1561 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1562 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1563 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1565 #undef TARGET_BUILTIN_RECIPROCAL
1566 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1568 #undef TARGET_EXPAND_TO_RTL_HOOK
1569 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1571 #undef TARGET_INSTANTIATE_DECLS
1572 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1574 #undef TARGET_SECONDARY_RELOAD
1575 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1577 #undef TARGET_LEGITIMATE_ADDRESS_P
1578 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1580 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1581 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1584 #define TARGET_LRA_P rs6000_lra_p
1586 #undef TARGET_CAN_ELIMINATE
1587 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1589 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1590 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1592 #undef TARGET_TRAMPOLINE_INIT
1593 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1595 #undef TARGET_FUNCTION_VALUE
1596 #define TARGET_FUNCTION_VALUE rs6000_function_value
1598 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1599 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1601 #undef TARGET_OPTION_SAVE
1602 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1604 #undef TARGET_OPTION_RESTORE
1605 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1607 #undef TARGET_OPTION_PRINT
1608 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1610 #undef TARGET_CAN_INLINE_P
1611 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1613 #undef TARGET_SET_CURRENT_FUNCTION
1614 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1616 #undef TARGET_LEGITIMATE_CONSTANT_P
1617 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1619 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
1620 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok
1622 #undef TARGET_CAN_USE_DOLOOP_P
1623 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
1626 /* Processor table. */
1629 const char *const name
; /* Canonical processor name. */
1630 const enum processor_type processor
; /* Processor type enum value. */
1631 const HOST_WIDE_INT target_enable
; /* Target flags to enable. */
1634 static struct rs6000_ptt
const processor_target_table
[] =
1636 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1637 #include "rs6000-cpus.def"
1641 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
1645 rs6000_cpu_name_lookup (const char *name
)
1651 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
1652 if (! strcmp (name
, processor_target_table
[i
].name
))
1660 /* Return number of consecutive hard regs needed starting at reg REGNO
1661 to hold something of mode MODE.
1662 This is ordinarily the length in words of a value of mode MODE
1663 but can be less for certain modes in special long registers.
1665 For the SPE, GPRs are 64 bits but only 32 bits are visible in
1666 scalar instructions. The upper 32 bits are only available to the
1669 POWER and PowerPC GPRs hold 32 bits worth;
1670 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
1673 rs6000_hard_regno_nregs_internal (int regno
, enum machine_mode mode
)
1675 unsigned HOST_WIDE_INT reg_size
;
1677 /* TF/TD modes are special in that they always take 2 registers. */
1678 if (FP_REGNO_P (regno
))
1679 reg_size
= ((VECTOR_MEM_VSX_P (mode
) && mode
!= TDmode
&& mode
!= TFmode
)
1680 ? UNITS_PER_VSX_WORD
1681 : UNITS_PER_FP_WORD
);
1683 else if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1684 reg_size
= UNITS_PER_SPE_WORD
;
1686 else if (ALTIVEC_REGNO_P (regno
))
1687 reg_size
= UNITS_PER_ALTIVEC_WORD
;
1689 /* The value returned for SCmode in the E500 double case is 2 for
1690 ABI compatibility; storing an SCmode value in a single register
1691 would require function_arg and rs6000_spe_function_arg to handle
1692 SCmode so as to pass the value correctly in a pair of
1694 else if (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
) && mode
!= SCmode
1695 && !DECIMAL_FLOAT_MODE_P (mode
))
1696 reg_size
= UNITS_PER_FP_WORD
;
1699 reg_size
= UNITS_PER_WORD
;
1701 return (GET_MODE_SIZE (mode
) + reg_size
- 1) / reg_size
;
1704 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1707 rs6000_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
1709 int last_regno
= regno
+ rs6000_hard_regno_nregs
[mode
][regno
] - 1;
1711 /* PTImode can only go in GPRs. Quad word memory operations require even/odd
1712 register combinations, and use PTImode where we need to deal with quad
1713 word memory operations. Don't allow quad words in the argument or frame
1714 pointer registers, just registers 0..31. */
1715 if (mode
== PTImode
)
1716 return (IN_RANGE (regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
1717 && IN_RANGE (last_regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
1718 && ((regno
& 1) == 0));
1720 /* VSX registers that overlap the FPR registers are larger than for non-VSX
1721 implementations. Don't allow an item to be split between a FP register
1722 and an Altivec register. Allow TImode in all VSX registers if the user
1724 if (TARGET_VSX
&& VSX_REGNO_P (regno
)
1725 && (VECTOR_MEM_VSX_P (mode
)
1726 || (TARGET_VSX_SCALAR_FLOAT
&& mode
== SFmode
)
1727 || (TARGET_VSX_SCALAR_DOUBLE
&& (mode
== DFmode
|| mode
== DImode
))
1728 || (TARGET_VSX_TIMODE
&& mode
== TImode
)
1729 || (TARGET_VADDUQM
&& mode
== V1TImode
)))
1731 if (FP_REGNO_P (regno
))
1732 return FP_REGNO_P (last_regno
);
1734 if (ALTIVEC_REGNO_P (regno
))
1736 if (mode
== SFmode
&& !TARGET_UPPER_REGS_SF
)
1739 if ((mode
== DFmode
|| mode
== DImode
) && !TARGET_UPPER_REGS_DF
)
1742 return ALTIVEC_REGNO_P (last_regno
);
1746 /* The GPRs can hold any mode, but values bigger than one register
1747 cannot go past R31. */
1748 if (INT_REGNO_P (regno
))
1749 return INT_REGNO_P (last_regno
);
1751 /* The float registers (except for VSX vector modes) can only hold floating
1752 modes and DImode. */
1753 if (FP_REGNO_P (regno
))
1755 if (SCALAR_FLOAT_MODE_P (mode
)
1756 && (mode
!= TDmode
|| (regno
% 2) == 0)
1757 && FP_REGNO_P (last_regno
))
1760 if (GET_MODE_CLASS (mode
) == MODE_INT
1761 && GET_MODE_SIZE (mode
) == UNITS_PER_FP_WORD
)
1764 if (PAIRED_SIMD_REGNO_P (regno
) && TARGET_PAIRED_FLOAT
1765 && PAIRED_VECTOR_MODE (mode
))
1771 /* The CR register can only hold CC modes. */
1772 if (CR_REGNO_P (regno
))
1773 return GET_MODE_CLASS (mode
) == MODE_CC
;
1775 if (CA_REGNO_P (regno
))
1776 return mode
== BImode
;
1778 /* AltiVec only in AldyVec registers. */
1779 if (ALTIVEC_REGNO_P (regno
))
1780 return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
)
1781 || mode
== V1TImode
);
1783 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1784 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1787 /* We cannot put non-VSX TImode or PTImode anywhere except general register
1788 and it must be able to fit within the register set. */
1790 return GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
;
1793 /* Print interesting facts about registers. */
1795 rs6000_debug_reg_print (int first_regno
, int last_regno
, const char *reg_name
)
1799 for (r
= first_regno
; r
<= last_regno
; ++r
)
1801 const char *comma
= "";
1804 if (first_regno
== last_regno
)
1805 fprintf (stderr
, "%s:\t", reg_name
);
1807 fprintf (stderr
, "%s%d:\t", reg_name
, r
- first_regno
);
1810 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1811 if (rs6000_hard_regno_mode_ok_p
[m
][r
] && rs6000_hard_regno_nregs
[m
][r
])
1815 fprintf (stderr
, ",\n\t");
1820 if (rs6000_hard_regno_nregs
[m
][r
] > 1)
1821 len
+= fprintf (stderr
, "%s%s/%d", comma
, GET_MODE_NAME (m
),
1822 rs6000_hard_regno_nregs
[m
][r
]);
1824 len
+= fprintf (stderr
, "%s%s", comma
, GET_MODE_NAME (m
));
1829 if (call_used_regs
[r
])
1833 fprintf (stderr
, ",\n\t");
1838 len
+= fprintf (stderr
, "%s%s", comma
, "call-used");
1846 fprintf (stderr
, ",\n\t");
1851 len
+= fprintf (stderr
, "%s%s", comma
, "fixed");
1857 fprintf (stderr
, ",\n\t");
1861 len
+= fprintf (stderr
, "%sreg-class = %s", comma
,
1862 reg_class_names
[(int)rs6000_regno_regclass
[r
]]);
1867 fprintf (stderr
, ",\n\t");
1871 fprintf (stderr
, "%sregno = %d\n", comma
, r
);
1876 rs6000_debug_vector_unit (enum rs6000_vector v
)
1882 case VECTOR_NONE
: ret
= "none"; break;
1883 case VECTOR_ALTIVEC
: ret
= "altivec"; break;
1884 case VECTOR_VSX
: ret
= "vsx"; break;
1885 case VECTOR_P8_VECTOR
: ret
= "p8_vector"; break;
1886 case VECTOR_PAIRED
: ret
= "paired"; break;
1887 case VECTOR_SPE
: ret
= "spe"; break;
1888 case VECTOR_OTHER
: ret
= "other"; break;
1889 default: ret
= "unknown"; break;
1895 /* Print the address masks in a human readble fashion. */
1897 rs6000_debug_print_mode (ssize_t m
)
1901 fprintf (stderr
, "Mode: %-5s", GET_MODE_NAME (m
));
1902 for (rc
= 0; rc
< N_RELOAD_REG
; rc
++)
1904 addr_mask_type mask
= reg_addr
[m
].addr_mask
[rc
];
1906 " %s: %c%c%c%c%c%c",
1907 reload_reg_map
[rc
].name
,
1908 (mask
& RELOAD_REG_VALID
) != 0 ? 'v' : ' ',
1909 (mask
& RELOAD_REG_MULTIPLE
) != 0 ? 'm' : ' ',
1910 (mask
& RELOAD_REG_INDEXED
) != 0 ? 'i' : ' ',
1911 (mask
& RELOAD_REG_OFFSET
) != 0 ? 'o' : ' ',
1912 (mask
& RELOAD_REG_PRE_INCDEC
) != 0 ? '+' : ' ',
1913 (mask
& RELOAD_REG_PRE_MODIFY
) != 0 ? '+' : ' ');
1916 if (rs6000_vector_unit
[m
] != VECTOR_NONE
1917 || rs6000_vector_mem
[m
] != VECTOR_NONE
1918 || (reg_addr
[m
].reload_store
!= CODE_FOR_nothing
)
1919 || (reg_addr
[m
].reload_load
!= CODE_FOR_nothing
))
1922 " Vector-arith=%-10s Vector-mem=%-10s Reload=%c%c",
1923 rs6000_debug_vector_unit (rs6000_vector_unit
[m
]),
1924 rs6000_debug_vector_unit (rs6000_vector_mem
[m
]),
1925 (reg_addr
[m
].reload_store
!= CODE_FOR_nothing
) ? 's' : '*',
1926 (reg_addr
[m
].reload_load
!= CODE_FOR_nothing
) ? 'l' : '*');
1929 fputs ("\n", stderr
);
1932 #define DEBUG_FMT_ID "%-32s= "
1933 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
1934 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
1935 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
1937 /* Print various interesting information with -mdebug=reg. */
1939 rs6000_debug_reg_global (void)
1941 static const char *const tf
[2] = { "false", "true" };
1942 const char *nl
= (const char *)0;
1945 char costly_num
[20];
1947 char flags_buffer
[40];
1948 const char *costly_str
;
1949 const char *nop_str
;
1950 const char *trace_str
;
1951 const char *abi_str
;
1952 const char *cmodel_str
;
1953 struct cl_target_option cl_opts
;
1955 /* Modes we want tieable information on. */
1956 static const enum machine_mode print_tieable_modes
[] = {
1992 /* Virtual regs we are interested in. */
1993 const static struct {
1994 int regno
; /* register number. */
1995 const char *name
; /* register name. */
1996 } virtual_regs
[] = {
1997 { STACK_POINTER_REGNUM
, "stack pointer:" },
1998 { TOC_REGNUM
, "toc: " },
1999 { STATIC_CHAIN_REGNUM
, "static chain: " },
2000 { RS6000_PIC_OFFSET_TABLE_REGNUM
, "pic offset: " },
2001 { HARD_FRAME_POINTER_REGNUM
, "hard frame: " },
2002 { ARG_POINTER_REGNUM
, "arg pointer: " },
2003 { FRAME_POINTER_REGNUM
, "frame pointer:" },
2004 { FIRST_PSEUDO_REGISTER
, "first pseudo: " },
2005 { FIRST_VIRTUAL_REGISTER
, "first virtual:" },
2006 { VIRTUAL_INCOMING_ARGS_REGNUM
, "incoming_args:" },
2007 { VIRTUAL_STACK_VARS_REGNUM
, "stack_vars: " },
2008 { VIRTUAL_STACK_DYNAMIC_REGNUM
, "stack_dynamic:" },
2009 { VIRTUAL_OUTGOING_ARGS_REGNUM
, "outgoing_args:" },
2010 { VIRTUAL_CFA_REGNUM
, "cfa (frame): " },
2011 { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM
, "stack boundry:" },
2012 { LAST_VIRTUAL_REGISTER
, "last virtual: " },
2015 fputs ("\nHard register information:\n", stderr
);
2016 rs6000_debug_reg_print (FIRST_GPR_REGNO
, LAST_GPR_REGNO
, "gr");
2017 rs6000_debug_reg_print (FIRST_FPR_REGNO
, LAST_FPR_REGNO
, "fp");
2018 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO
,
2021 rs6000_debug_reg_print (LR_REGNO
, LR_REGNO
, "lr");
2022 rs6000_debug_reg_print (CTR_REGNO
, CTR_REGNO
, "ctr");
2023 rs6000_debug_reg_print (CR0_REGNO
, CR7_REGNO
, "cr");
2024 rs6000_debug_reg_print (CA_REGNO
, CA_REGNO
, "ca");
2025 rs6000_debug_reg_print (VRSAVE_REGNO
, VRSAVE_REGNO
, "vrsave");
2026 rs6000_debug_reg_print (VSCR_REGNO
, VSCR_REGNO
, "vscr");
2027 rs6000_debug_reg_print (SPE_ACC_REGNO
, SPE_ACC_REGNO
, "spe_a");
2028 rs6000_debug_reg_print (SPEFSCR_REGNO
, SPEFSCR_REGNO
, "spe_f");
2030 fputs ("\nVirtual/stack/frame registers:\n", stderr
);
2031 for (v
= 0; v
< ARRAY_SIZE (virtual_regs
); v
++)
2032 fprintf (stderr
, "%s regno = %3d\n", virtual_regs
[v
].name
, virtual_regs
[v
].regno
);
2036 "d reg_class = %s\n"
2037 "f reg_class = %s\n"
2038 "v reg_class = %s\n"
2039 "wa reg_class = %s\n"
2040 "wd reg_class = %s\n"
2041 "wf reg_class = %s\n"
2042 "wg reg_class = %s\n"
2043 "wl reg_class = %s\n"
2044 "wm reg_class = %s\n"
2045 "wr reg_class = %s\n"
2046 "ws reg_class = %s\n"
2047 "wt reg_class = %s\n"
2048 "wu reg_class = %s\n"
2049 "wv reg_class = %s\n"
2050 "ww reg_class = %s\n"
2051 "wx reg_class = %s\n"
2052 "wy reg_class = %s\n"
2053 "wz reg_class = %s\n"
2055 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_d
]],
2056 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_f
]],
2057 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_v
]],
2058 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wa
]],
2059 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wd
]],
2060 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wf
]],
2061 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wg
]],
2062 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wl
]],
2063 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wm
]],
2064 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wr
]],
2065 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ws
]],
2066 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wt
]],
2067 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wu
]],
2068 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wv
]],
2069 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ww
]],
2070 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wx
]],
2071 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wy
]],
2072 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wz
]]);
2075 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2076 rs6000_debug_print_mode (m
);
2078 fputs ("\n", stderr
);
2080 for (m1
= 0; m1
< ARRAY_SIZE (print_tieable_modes
); m1
++)
2082 enum machine_mode mode1
= print_tieable_modes
[m1
];
2083 bool first_time
= true;
2085 nl
= (const char *)0;
2086 for (m2
= 0; m2
< ARRAY_SIZE (print_tieable_modes
); m2
++)
2088 enum machine_mode mode2
= print_tieable_modes
[m2
];
2089 if (mode1
!= mode2
&& MODES_TIEABLE_P (mode1
, mode2
))
2093 fprintf (stderr
, "Tieable modes %s:", GET_MODE_NAME (mode1
));
2098 fprintf (stderr
, " %s", GET_MODE_NAME (mode2
));
2103 fputs ("\n", stderr
);
2109 if (rs6000_recip_control
)
2111 fprintf (stderr
, "\nReciprocal mask = 0x%x\n", rs6000_recip_control
);
2113 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2114 if (rs6000_recip_bits
[m
])
2117 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2119 (RS6000_RECIP_AUTO_RE_P (m
)
2121 : (RS6000_RECIP_HAVE_RE_P (m
) ? "have" : "none")),
2122 (RS6000_RECIP_AUTO_RSQRTE_P (m
)
2124 : (RS6000_RECIP_HAVE_RSQRTE_P (m
) ? "have" : "none")));
2127 fputs ("\n", stderr
);
2130 if (rs6000_cpu_index
>= 0)
2132 const char *name
= processor_target_table
[rs6000_cpu_index
].name
;
2134 = processor_target_table
[rs6000_cpu_index
].target_enable
;
2136 sprintf (flags_buffer
, "-mcpu=%s flags", name
);
2137 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2140 fprintf (stderr
, DEBUG_FMT_S
, "cpu", "<none>");
2142 if (rs6000_tune_index
>= 0)
2144 const char *name
= processor_target_table
[rs6000_tune_index
].name
;
2146 = processor_target_table
[rs6000_tune_index
].target_enable
;
2148 sprintf (flags_buffer
, "-mtune=%s flags", name
);
2149 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2152 fprintf (stderr
, DEBUG_FMT_S
, "tune", "<none>");
2154 cl_target_option_save (&cl_opts
, &global_options
);
2155 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags",
2158 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags_explicit",
2159 rs6000_isa_flags_explicit
);
2161 rs6000_print_builtin_options (stderr
, 0, "rs6000_builtin_mask",
2162 rs6000_builtin_mask
);
2164 rs6000_print_isa_options (stderr
, 0, "TARGET_DEFAULT", TARGET_DEFAULT
);
2166 fprintf (stderr
, DEBUG_FMT_S
, "--with-cpu default",
2167 OPTION_TARGET_CPU_DEFAULT
? OPTION_TARGET_CPU_DEFAULT
: "<none>");
2169 switch (rs6000_sched_costly_dep
)
2171 case max_dep_latency
:
2172 costly_str
= "max_dep_latency";
2176 costly_str
= "no_dep_costly";
2179 case all_deps_costly
:
2180 costly_str
= "all_deps_costly";
2183 case true_store_to_load_dep_costly
:
2184 costly_str
= "true_store_to_load_dep_costly";
2187 case store_to_load_dep_costly
:
2188 costly_str
= "store_to_load_dep_costly";
2192 costly_str
= costly_num
;
2193 sprintf (costly_num
, "%d", (int)rs6000_sched_costly_dep
);
2197 fprintf (stderr
, DEBUG_FMT_S
, "sched_costly_dep", costly_str
);
2199 switch (rs6000_sched_insert_nops
)
2201 case sched_finish_regroup_exact
:
2202 nop_str
= "sched_finish_regroup_exact";
2205 case sched_finish_pad_groups
:
2206 nop_str
= "sched_finish_pad_groups";
2209 case sched_finish_none
:
2210 nop_str
= "sched_finish_none";
2215 sprintf (nop_num
, "%d", (int)rs6000_sched_insert_nops
);
2219 fprintf (stderr
, DEBUG_FMT_S
, "sched_insert_nops", nop_str
);
2221 switch (rs6000_sdata
)
2228 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "data");
2232 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "sysv");
2236 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "eabi");
2241 switch (rs6000_traceback
)
2243 case traceback_default
: trace_str
= "default"; break;
2244 case traceback_none
: trace_str
= "none"; break;
2245 case traceback_part
: trace_str
= "part"; break;
2246 case traceback_full
: trace_str
= "full"; break;
2247 default: trace_str
= "unknown"; break;
2250 fprintf (stderr
, DEBUG_FMT_S
, "traceback", trace_str
);
2252 switch (rs6000_current_cmodel
)
2254 case CMODEL_SMALL
: cmodel_str
= "small"; break;
2255 case CMODEL_MEDIUM
: cmodel_str
= "medium"; break;
2256 case CMODEL_LARGE
: cmodel_str
= "large"; break;
2257 default: cmodel_str
= "unknown"; break;
2260 fprintf (stderr
, DEBUG_FMT_S
, "cmodel", cmodel_str
);
2262 switch (rs6000_current_abi
)
2264 case ABI_NONE
: abi_str
= "none"; break;
2265 case ABI_AIX
: abi_str
= "aix"; break;
2266 case ABI_ELFv2
: abi_str
= "ELFv2"; break;
2267 case ABI_V4
: abi_str
= "V4"; break;
2268 case ABI_DARWIN
: abi_str
= "darwin"; break;
2269 default: abi_str
= "unknown"; break;
2272 fprintf (stderr
, DEBUG_FMT_S
, "abi", abi_str
);
2274 if (rs6000_altivec_abi
)
2275 fprintf (stderr
, DEBUG_FMT_S
, "altivec_abi", "true");
2278 fprintf (stderr
, DEBUG_FMT_S
, "spe_abi", "true");
2280 if (rs6000_darwin64_abi
)
2281 fprintf (stderr
, DEBUG_FMT_S
, "darwin64_abi", "true");
2283 if (rs6000_float_gprs
)
2284 fprintf (stderr
, DEBUG_FMT_S
, "float_gprs", "true");
2286 fprintf (stderr
, DEBUG_FMT_S
, "fprs",
2287 (TARGET_FPRS
? "true" : "false"));
2289 fprintf (stderr
, DEBUG_FMT_S
, "single_float",
2290 (TARGET_SINGLE_FLOAT
? "true" : "false"));
2292 fprintf (stderr
, DEBUG_FMT_S
, "double_float",
2293 (TARGET_DOUBLE_FLOAT
? "true" : "false"));
2295 fprintf (stderr
, DEBUG_FMT_S
, "soft_float",
2296 (TARGET_SOFT_FLOAT
? "true" : "false"));
2298 fprintf (stderr
, DEBUG_FMT_S
, "e500_single",
2299 (TARGET_E500_SINGLE
? "true" : "false"));
2301 fprintf (stderr
, DEBUG_FMT_S
, "e500_double",
2302 (TARGET_E500_DOUBLE
? "true" : "false"));
2304 if (TARGET_LINK_STACK
)
2305 fprintf (stderr
, DEBUG_FMT_S
, "link_stack", "true");
2307 if (targetm
.lra_p ())
2308 fprintf (stderr
, DEBUG_FMT_S
, "lra", "true");
2310 if (TARGET_P8_FUSION
)
2311 fprintf (stderr
, DEBUG_FMT_S
, "p8 fusion",
2312 (TARGET_P8_FUSION_SIGN
) ? "zero+sign" : "zero");
2314 fprintf (stderr
, DEBUG_FMT_S
, "plt-format",
2315 TARGET_SECURE_PLT
? "secure" : "bss");
2316 fprintf (stderr
, DEBUG_FMT_S
, "struct-return",
2317 aix_struct_return
? "aix" : "sysv");
2318 fprintf (stderr
, DEBUG_FMT_S
, "always_hint", tf
[!!rs6000_always_hint
]);
2319 fprintf (stderr
, DEBUG_FMT_S
, "sched_groups", tf
[!!rs6000_sched_groups
]);
2320 fprintf (stderr
, DEBUG_FMT_S
, "align_branch",
2321 tf
[!!rs6000_align_branch_targets
]);
2322 fprintf (stderr
, DEBUG_FMT_D
, "tls_size", rs6000_tls_size
);
2323 fprintf (stderr
, DEBUG_FMT_D
, "long_double_size",
2324 rs6000_long_double_type_size
);
2325 fprintf (stderr
, DEBUG_FMT_D
, "sched_restricted_insns_priority",
2326 (int)rs6000_sched_restricted_insns_priority
);
2327 fprintf (stderr
, DEBUG_FMT_D
, "Number of standard builtins",
2329 fprintf (stderr
, DEBUG_FMT_D
, "Number of rs6000 builtins",
2330 (int)RS6000_BUILTIN_COUNT
);
2333 fprintf (stderr
, DEBUG_FMT_D
, "VSX easy 64-bit scalar element",
2334 (int)VECTOR_ELEMENT_SCALAR_64BIT
);
2338 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2339 legitimate address support to figure out the appropriate addressing to
2343 rs6000_setup_reg_addr_masks (void)
2345 ssize_t rc
, reg
, m
, nregs
;
2346 addr_mask_type any_addr_mask
, addr_mask
;
2348 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2350 enum machine_mode m2
= (enum machine_mode
)m
;
2352 /* SDmode is special in that we want to access it only via REG+REG
2353 addressing on power7 and above, since we want to use the LFIWZX and
2354 STFIWZX instructions to load it. */
2355 bool indexed_only_p
= (m
== SDmode
&& TARGET_NO_SDMODE_STACK
);
2358 for (rc
= FIRST_RELOAD_REG_CLASS
; rc
<= LAST_RELOAD_REG_CLASS
; rc
++)
2361 reg
= reload_reg_map
[rc
].reg
;
2363 /* Can mode values go in the GPR/FPR/Altivec registers? */
2364 if (reg
>= 0 && rs6000_hard_regno_mode_ok_p
[m
][reg
])
2366 nregs
= rs6000_hard_regno_nregs
[m
][reg
];
2367 addr_mask
|= RELOAD_REG_VALID
;
2369 /* Indicate if the mode takes more than 1 physical register. If
2370 it takes a single register, indicate it can do REG+REG
2372 if (nregs
> 1 || m
== BLKmode
)
2373 addr_mask
|= RELOAD_REG_MULTIPLE
;
2375 addr_mask
|= RELOAD_REG_INDEXED
;
2377 /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
2378 addressing. Restrict addressing on SPE for 64-bit types
2379 because of the SUBREG hackery used to address 64-bit floats in
2380 '32-bit' GPRs. To simplify secondary reload, don't allow
2381 update forms on scalar floating point types that can go in the
2385 && (rc
== RELOAD_REG_GPR
|| rc
== RELOAD_REG_FPR
)
2386 && GET_MODE_SIZE (m2
) <= 8
2387 && !VECTOR_MODE_P (m2
)
2388 && !COMPLEX_MODE_P (m2
)
2390 && !(TARGET_E500_DOUBLE
&& GET_MODE_SIZE (m2
) == 8)
2391 && !(m2
== DFmode
&& TARGET_UPPER_REGS_DF
)
2392 && !(m2
== SFmode
&& TARGET_UPPER_REGS_SF
))
2394 addr_mask
|= RELOAD_REG_PRE_INCDEC
;
2396 /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that
2397 we don't allow PRE_MODIFY for some multi-register
2402 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2406 if (TARGET_POWERPC64
)
2407 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2413 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2419 /* GPR and FPR registers can do REG+OFFSET addressing, except
2420 possibly for SDmode. */
2421 if ((addr_mask
!= 0) && !indexed_only_p
2422 && (rc
== RELOAD_REG_GPR
|| rc
== RELOAD_REG_FPR
))
2423 addr_mask
|= RELOAD_REG_OFFSET
;
2425 reg_addr
[m
].addr_mask
[rc
] = addr_mask
;
2426 any_addr_mask
|= addr_mask
;
2429 reg_addr
[m
].addr_mask
[RELOAD_REG_ANY
] = any_addr_mask
;
2434 /* Initialize the various global tables that are based on register size. */
2436 rs6000_init_hard_regno_mode_ok (bool global_init_p
)
2442 /* Precalculate REGNO_REG_CLASS. */
2443 rs6000_regno_regclass
[0] = GENERAL_REGS
;
2444 for (r
= 1; r
< 32; ++r
)
2445 rs6000_regno_regclass
[r
] = BASE_REGS
;
2447 for (r
= 32; r
< 64; ++r
)
2448 rs6000_regno_regclass
[r
] = FLOAT_REGS
;
2450 for (r
= 64; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2451 rs6000_regno_regclass
[r
] = NO_REGS
;
2453 for (r
= FIRST_ALTIVEC_REGNO
; r
<= LAST_ALTIVEC_REGNO
; ++r
)
2454 rs6000_regno_regclass
[r
] = ALTIVEC_REGS
;
2456 rs6000_regno_regclass
[CR0_REGNO
] = CR0_REGS
;
2457 for (r
= CR1_REGNO
; r
<= CR7_REGNO
; ++r
)
2458 rs6000_regno_regclass
[r
] = CR_REGS
;
2460 rs6000_regno_regclass
[LR_REGNO
] = LINK_REGS
;
2461 rs6000_regno_regclass
[CTR_REGNO
] = CTR_REGS
;
2462 rs6000_regno_regclass
[CA_REGNO
] = CA_REGS
;
2463 rs6000_regno_regclass
[VRSAVE_REGNO
] = VRSAVE_REGS
;
2464 rs6000_regno_regclass
[VSCR_REGNO
] = VRSAVE_REGS
;
2465 rs6000_regno_regclass
[SPE_ACC_REGNO
] = SPE_ACC_REGS
;
2466 rs6000_regno_regclass
[SPEFSCR_REGNO
] = SPEFSCR_REGS
;
2467 rs6000_regno_regclass
[TFHAR_REGNO
] = SPR_REGS
;
2468 rs6000_regno_regclass
[TFIAR_REGNO
] = SPR_REGS
;
2469 rs6000_regno_regclass
[TEXASR_REGNO
] = SPR_REGS
;
2470 rs6000_regno_regclass
[ARG_POINTER_REGNUM
] = BASE_REGS
;
2471 rs6000_regno_regclass
[FRAME_POINTER_REGNUM
] = BASE_REGS
;
2473 /* Precalculate register class to simpler reload register class. We don't
2474 need all of the register classes that are combinations of different
2475 classes, just the simple ones that have constraint letters. */
2476 for (c
= 0; c
< N_REG_CLASSES
; c
++)
2477 reg_class_to_reg_type
[c
] = NO_REG_TYPE
;
2479 reg_class_to_reg_type
[(int)GENERAL_REGS
] = GPR_REG_TYPE
;
2480 reg_class_to_reg_type
[(int)BASE_REGS
] = GPR_REG_TYPE
;
2481 reg_class_to_reg_type
[(int)VSX_REGS
] = VSX_REG_TYPE
;
2482 reg_class_to_reg_type
[(int)VRSAVE_REGS
] = SPR_REG_TYPE
;
2483 reg_class_to_reg_type
[(int)VSCR_REGS
] = SPR_REG_TYPE
;
2484 reg_class_to_reg_type
[(int)LINK_REGS
] = SPR_REG_TYPE
;
2485 reg_class_to_reg_type
[(int)CTR_REGS
] = SPR_REG_TYPE
;
2486 reg_class_to_reg_type
[(int)LINK_OR_CTR_REGS
] = SPR_REG_TYPE
;
2487 reg_class_to_reg_type
[(int)CR_REGS
] = CR_REG_TYPE
;
2488 reg_class_to_reg_type
[(int)CR0_REGS
] = CR_REG_TYPE
;
2489 reg_class_to_reg_type
[(int)SPE_ACC_REGS
] = SPE_ACC_TYPE
;
2490 reg_class_to_reg_type
[(int)SPEFSCR_REGS
] = SPEFSCR_REG_TYPE
;
2494 reg_class_to_reg_type
[(int)FLOAT_REGS
] = VSX_REG_TYPE
;
2495 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = VSX_REG_TYPE
;
2499 reg_class_to_reg_type
[(int)FLOAT_REGS
] = FPR_REG_TYPE
;
2500 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = ALTIVEC_REG_TYPE
;
2503 /* Precalculate the valid memory formats as well as the vector information,
2504 this must be set up before the rs6000_hard_regno_nregs_internal calls
2506 gcc_assert ((int)VECTOR_NONE
== 0);
2507 memset ((void *) &rs6000_vector_unit
[0], '\0', sizeof (rs6000_vector_unit
));
2508 memset ((void *) &rs6000_vector_mem
[0], '\0', sizeof (rs6000_vector_unit
));
2510 gcc_assert ((int)CODE_FOR_nothing
== 0);
2511 memset ((void *) ®_addr
[0], '\0', sizeof (reg_addr
));
2513 gcc_assert ((int)NO_REGS
== 0);
2514 memset ((void *) &rs6000_constraints
[0], '\0', sizeof (rs6000_constraints
));
2516 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
2517 believes it can use native alignment or still uses 128-bit alignment. */
2518 if (TARGET_VSX
&& !TARGET_VSX_ALIGN_128
)
2529 /* V2DF mode, VSX only. */
2532 rs6000_vector_unit
[V2DFmode
] = VECTOR_VSX
;
2533 rs6000_vector_mem
[V2DFmode
] = VECTOR_VSX
;
2534 rs6000_vector_align
[V2DFmode
] = align64
;
2537 /* V4SF mode, either VSX or Altivec. */
2540 rs6000_vector_unit
[V4SFmode
] = VECTOR_VSX
;
2541 rs6000_vector_mem
[V4SFmode
] = VECTOR_VSX
;
2542 rs6000_vector_align
[V4SFmode
] = align32
;
2544 else if (TARGET_ALTIVEC
)
2546 rs6000_vector_unit
[V4SFmode
] = VECTOR_ALTIVEC
;
2547 rs6000_vector_mem
[V4SFmode
] = VECTOR_ALTIVEC
;
2548 rs6000_vector_align
[V4SFmode
] = align32
;
2551 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
2555 rs6000_vector_unit
[V4SImode
] = VECTOR_ALTIVEC
;
2556 rs6000_vector_unit
[V8HImode
] = VECTOR_ALTIVEC
;
2557 rs6000_vector_unit
[V16QImode
] = VECTOR_ALTIVEC
;
2558 rs6000_vector_align
[V4SImode
] = align32
;
2559 rs6000_vector_align
[V8HImode
] = align32
;
2560 rs6000_vector_align
[V16QImode
] = align32
;
2564 rs6000_vector_mem
[V4SImode
] = VECTOR_VSX
;
2565 rs6000_vector_mem
[V8HImode
] = VECTOR_VSX
;
2566 rs6000_vector_mem
[V16QImode
] = VECTOR_VSX
;
2570 rs6000_vector_mem
[V4SImode
] = VECTOR_ALTIVEC
;
2571 rs6000_vector_mem
[V8HImode
] = VECTOR_ALTIVEC
;
2572 rs6000_vector_mem
[V16QImode
] = VECTOR_ALTIVEC
;
2576 /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
2577 do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
2580 rs6000_vector_mem
[V2DImode
] = VECTOR_VSX
;
2581 rs6000_vector_unit
[V2DImode
]
2582 = (TARGET_P8_VECTOR
) ? VECTOR_P8_VECTOR
: VECTOR_NONE
;
2583 rs6000_vector_align
[V2DImode
] = align64
;
2585 rs6000_vector_mem
[V1TImode
] = VECTOR_VSX
;
2586 rs6000_vector_unit
[V1TImode
]
2587 = (TARGET_P8_VECTOR
) ? VECTOR_P8_VECTOR
: VECTOR_NONE
;
2588 rs6000_vector_align
[V1TImode
] = 128;
2591 /* DFmode, see if we want to use the VSX unit. */
2592 if (TARGET_VSX
&& TARGET_VSX_SCALAR_DOUBLE
)
2594 rs6000_vector_unit
[DFmode
] = VECTOR_VSX
;
2595 rs6000_vector_mem
[DFmode
]
2596 = (TARGET_UPPER_REGS_DF
? VECTOR_VSX
: VECTOR_NONE
);
2597 rs6000_vector_align
[DFmode
] = align64
;
2600 /* Allow TImode in VSX register and set the VSX memory macros. */
2601 if (TARGET_VSX
&& TARGET_VSX_TIMODE
)
2603 rs6000_vector_mem
[TImode
] = VECTOR_VSX
;
2604 rs6000_vector_align
[TImode
] = align64
;
2607 /* TODO add SPE and paired floating point vector support. */
2609 /* Register class constraints for the constraints that depend on compile
2610 switches. When the VSX code was added, different constraints were added
2611 based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all
2612 of the VSX registers are used. The register classes for scalar floating
2613 point types is set, based on whether we allow that type into the upper
2614 (Altivec) registers. GCC has register classes to target the Altivec
2615 registers for load/store operations, to select using a VSX memory
2616 operation instead of the traditional floating point operation. The
2619 d - Register class to use with traditional DFmode instructions.
2620 f - Register class to use with traditional SFmode instructions.
2621 v - Altivec register.
2622 wa - Any VSX register.
2623 wd - Preferred register class for V2DFmode.
2624 wf - Preferred register class for V4SFmode.
2625 wg - Float register for power6x move insns.
2626 wl - Float register if we can do 32-bit signed int loads.
2627 wm - VSX register for ISA 2.07 direct move operations.
2628 wr - GPR if 64-bit mode is permitted.
2629 ws - Register class to do ISA 2.06 DF operations.
2630 wu - Altivec register for ISA 2.07 VSX SF/SI load/stores.
2631 wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
2632 wt - VSX register for TImode in VSX registers.
2633 ww - Register class to do SF conversions in with VSX operations.
2634 wx - Float register if we can do 32-bit int stores.
2635 wy - Register class to do ISA 2.07 SF operations.
2636 wz - Float register if we can do 32-bit unsigned int loads. */
2638 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
2639 rs6000_constraints
[RS6000_CONSTRAINT_f
] = FLOAT_REGS
;
2641 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
2642 rs6000_constraints
[RS6000_CONSTRAINT_d
] = FLOAT_REGS
;
2646 rs6000_constraints
[RS6000_CONSTRAINT_wa
] = VSX_REGS
;
2647 rs6000_constraints
[RS6000_CONSTRAINT_wd
] = VSX_REGS
;
2648 rs6000_constraints
[RS6000_CONSTRAINT_wf
] = VSX_REGS
;
2650 if (TARGET_VSX_TIMODE
)
2651 rs6000_constraints
[RS6000_CONSTRAINT_wt
] = VSX_REGS
;
2653 if (TARGET_UPPER_REGS_DF
)
2655 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = VSX_REGS
;
2656 rs6000_constraints
[RS6000_CONSTRAINT_wv
] = ALTIVEC_REGS
;
2659 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = FLOAT_REGS
;
2662 /* Add conditional constraints based on various options, to allow us to
2663 collapse multiple insn patterns. */
2665 rs6000_constraints
[RS6000_CONSTRAINT_v
] = ALTIVEC_REGS
;
2668 rs6000_constraints
[RS6000_CONSTRAINT_wg
] = FLOAT_REGS
;
2671 rs6000_constraints
[RS6000_CONSTRAINT_wl
] = FLOAT_REGS
;
2673 if (TARGET_DIRECT_MOVE
)
2674 rs6000_constraints
[RS6000_CONSTRAINT_wm
] = VSX_REGS
;
2676 if (TARGET_POWERPC64
)
2677 rs6000_constraints
[RS6000_CONSTRAINT_wr
] = GENERAL_REGS
;
2679 if (TARGET_P8_VECTOR
&& TARGET_UPPER_REGS_SF
)
2681 rs6000_constraints
[RS6000_CONSTRAINT_wu
] = ALTIVEC_REGS
;
2682 rs6000_constraints
[RS6000_CONSTRAINT_wy
] = VSX_REGS
;
2683 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = VSX_REGS
;
2685 else if (TARGET_P8_VECTOR
)
2687 rs6000_constraints
[RS6000_CONSTRAINT_wy
] = FLOAT_REGS
;
2688 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = FLOAT_REGS
;
2690 else if (TARGET_VSX
)
2691 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = FLOAT_REGS
;
2694 rs6000_constraints
[RS6000_CONSTRAINT_wx
] = FLOAT_REGS
;
2697 rs6000_constraints
[RS6000_CONSTRAINT_wz
] = FLOAT_REGS
;
2699 /* Set up the reload helper and direct move functions. */
2700 if (TARGET_VSX
|| TARGET_ALTIVEC
)
2704 reg_addr
[V16QImode
].reload_store
= CODE_FOR_reload_v16qi_di_store
;
2705 reg_addr
[V16QImode
].reload_load
= CODE_FOR_reload_v16qi_di_load
;
2706 reg_addr
[V8HImode
].reload_store
= CODE_FOR_reload_v8hi_di_store
;
2707 reg_addr
[V8HImode
].reload_load
= CODE_FOR_reload_v8hi_di_load
;
2708 reg_addr
[V4SImode
].reload_store
= CODE_FOR_reload_v4si_di_store
;
2709 reg_addr
[V4SImode
].reload_load
= CODE_FOR_reload_v4si_di_load
;
2710 reg_addr
[V2DImode
].reload_store
= CODE_FOR_reload_v2di_di_store
;
2711 reg_addr
[V2DImode
].reload_load
= CODE_FOR_reload_v2di_di_load
;
2712 reg_addr
[V1TImode
].reload_store
= CODE_FOR_reload_v1ti_di_store
;
2713 reg_addr
[V1TImode
].reload_load
= CODE_FOR_reload_v1ti_di_load
;
2714 reg_addr
[V4SFmode
].reload_store
= CODE_FOR_reload_v4sf_di_store
;
2715 reg_addr
[V4SFmode
].reload_load
= CODE_FOR_reload_v4sf_di_load
;
2716 reg_addr
[V2DFmode
].reload_store
= CODE_FOR_reload_v2df_di_store
;
2717 reg_addr
[V2DFmode
].reload_load
= CODE_FOR_reload_v2df_di_load
;
2718 if (TARGET_VSX
&& TARGET_UPPER_REGS_DF
)
2720 reg_addr
[DFmode
].reload_store
= CODE_FOR_reload_df_di_store
;
2721 reg_addr
[DFmode
].reload_load
= CODE_FOR_reload_df_di_load
;
2722 reg_addr
[DDmode
].reload_store
= CODE_FOR_reload_dd_di_store
;
2723 reg_addr
[DDmode
].reload_load
= CODE_FOR_reload_dd_di_load
;
2725 if (TARGET_P8_VECTOR
)
2727 reg_addr
[SFmode
].reload_store
= CODE_FOR_reload_sf_di_store
;
2728 reg_addr
[SFmode
].reload_load
= CODE_FOR_reload_sf_di_load
;
2729 reg_addr
[SDmode
].reload_store
= CODE_FOR_reload_sd_di_store
;
2730 reg_addr
[SDmode
].reload_load
= CODE_FOR_reload_sd_di_load
;
2732 if (TARGET_VSX_TIMODE
)
2734 reg_addr
[TImode
].reload_store
= CODE_FOR_reload_ti_di_store
;
2735 reg_addr
[TImode
].reload_load
= CODE_FOR_reload_ti_di_load
;
2737 if (TARGET_DIRECT_MOVE
)
2739 if (TARGET_POWERPC64
)
2741 reg_addr
[TImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxti
;
2742 reg_addr
[V1TImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv1ti
;
2743 reg_addr
[V2DFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv2df
;
2744 reg_addr
[V2DImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv2di
;
2745 reg_addr
[V4SFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv4sf
;
2746 reg_addr
[V4SImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv4si
;
2747 reg_addr
[V8HImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv8hi
;
2748 reg_addr
[V16QImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv16qi
;
2749 reg_addr
[SFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxsf
;
2751 reg_addr
[TImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprti
;
2752 reg_addr
[V1TImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv1ti
;
2753 reg_addr
[V2DFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv2df
;
2754 reg_addr
[V2DImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv2di
;
2755 reg_addr
[V4SFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv4sf
;
2756 reg_addr
[V4SImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv4si
;
2757 reg_addr
[V8HImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv8hi
;
2758 reg_addr
[V16QImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv16qi
;
2759 reg_addr
[SFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprsf
;
2763 reg_addr
[DImode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdi
;
2764 reg_addr
[DDmode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdd
;
2765 reg_addr
[DFmode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdf
;
2771 reg_addr
[V16QImode
].reload_store
= CODE_FOR_reload_v16qi_si_store
;
2772 reg_addr
[V16QImode
].reload_load
= CODE_FOR_reload_v16qi_si_load
;
2773 reg_addr
[V8HImode
].reload_store
= CODE_FOR_reload_v8hi_si_store
;
2774 reg_addr
[V8HImode
].reload_load
= CODE_FOR_reload_v8hi_si_load
;
2775 reg_addr
[V4SImode
].reload_store
= CODE_FOR_reload_v4si_si_store
;
2776 reg_addr
[V4SImode
].reload_load
= CODE_FOR_reload_v4si_si_load
;
2777 reg_addr
[V2DImode
].reload_store
= CODE_FOR_reload_v2di_si_store
;
2778 reg_addr
[V2DImode
].reload_load
= CODE_FOR_reload_v2di_si_load
;
2779 reg_addr
[V1TImode
].reload_store
= CODE_FOR_reload_v1ti_si_store
;
2780 reg_addr
[V1TImode
].reload_load
= CODE_FOR_reload_v1ti_si_load
;
2781 reg_addr
[V4SFmode
].reload_store
= CODE_FOR_reload_v4sf_si_store
;
2782 reg_addr
[V4SFmode
].reload_load
= CODE_FOR_reload_v4sf_si_load
;
2783 reg_addr
[V2DFmode
].reload_store
= CODE_FOR_reload_v2df_si_store
;
2784 reg_addr
[V2DFmode
].reload_load
= CODE_FOR_reload_v2df_si_load
;
2785 if (TARGET_VSX
&& TARGET_UPPER_REGS_DF
)
2787 reg_addr
[DFmode
].reload_store
= CODE_FOR_reload_df_si_store
;
2788 reg_addr
[DFmode
].reload_load
= CODE_FOR_reload_df_si_load
;
2789 reg_addr
[DDmode
].reload_store
= CODE_FOR_reload_dd_si_store
;
2790 reg_addr
[DDmode
].reload_load
= CODE_FOR_reload_dd_si_load
;
2792 if (TARGET_P8_VECTOR
)
2794 reg_addr
[SFmode
].reload_store
= CODE_FOR_reload_sf_si_store
;
2795 reg_addr
[SFmode
].reload_load
= CODE_FOR_reload_sf_si_load
;
2796 reg_addr
[SDmode
].reload_store
= CODE_FOR_reload_sd_si_store
;
2797 reg_addr
[SDmode
].reload_load
= CODE_FOR_reload_sd_si_load
;
2799 if (TARGET_VSX_TIMODE
)
2801 reg_addr
[TImode
].reload_store
= CODE_FOR_reload_ti_si_store
;
2802 reg_addr
[TImode
].reload_load
= CODE_FOR_reload_ti_si_load
;
2807 /* Precalculate HARD_REGNO_NREGS. */
2808 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2809 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2810 rs6000_hard_regno_nregs
[m
][r
]
2811 = rs6000_hard_regno_nregs_internal (r
, (enum machine_mode
)m
);
2813 /* Precalculate HARD_REGNO_MODE_OK. */
2814 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2815 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2816 if (rs6000_hard_regno_mode_ok (r
, (enum machine_mode
)m
))
2817 rs6000_hard_regno_mode_ok_p
[m
][r
] = true;
2819 /* Precalculate CLASS_MAX_NREGS sizes. */
2820 for (c
= 0; c
< LIM_REG_CLASSES
; ++c
)
2824 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
))
2825 reg_size
= UNITS_PER_VSX_WORD
;
2827 else if (c
== ALTIVEC_REGS
)
2828 reg_size
= UNITS_PER_ALTIVEC_WORD
;
2830 else if (c
== FLOAT_REGS
)
2831 reg_size
= UNITS_PER_FP_WORD
;
2834 reg_size
= UNITS_PER_WORD
;
2836 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2838 enum machine_mode m2
= (enum machine_mode
)m
;
2839 int reg_size2
= reg_size
;
2841 /* TFmode/TDmode always takes 2 registers, even in VSX. */
2842 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
)
2843 && (m
== TDmode
|| m
== TFmode
))
2844 reg_size2
= UNITS_PER_FP_WORD
;
2846 rs6000_class_max_nregs
[m
][c
]
2847 = (GET_MODE_SIZE (m2
) + reg_size2
- 1) / reg_size2
;
2851 if (TARGET_E500_DOUBLE
)
2852 rs6000_class_max_nregs
[DFmode
][GENERAL_REGS
] = 1;
2854 /* Calculate which modes to automatically generate code to use a the
2855 reciprocal divide and square root instructions. In the future, possibly
2856 automatically generate the instructions even if the user did not specify
2857 -mrecip. The older machines double precision reciprocal sqrt estimate is
2858 not accurate enough. */
2859 memset (rs6000_recip_bits
, 0, sizeof (rs6000_recip_bits
));
2861 rs6000_recip_bits
[SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2863 rs6000_recip_bits
[DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2864 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
2865 rs6000_recip_bits
[V4SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2866 if (VECTOR_UNIT_VSX_P (V2DFmode
))
2867 rs6000_recip_bits
[V2DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2869 if (TARGET_FRSQRTES
)
2870 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2872 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2873 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
2874 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2875 if (VECTOR_UNIT_VSX_P (V2DFmode
))
2876 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2878 if (rs6000_recip_control
)
2880 if (!flag_finite_math_only
)
2881 warning (0, "-mrecip requires -ffinite-math or -ffast-math");
2882 if (flag_trapping_math
)
2883 warning (0, "-mrecip requires -fno-trapping-math or -ffast-math");
2884 if (!flag_reciprocal_math
)
2885 warning (0, "-mrecip requires -freciprocal-math or -ffast-math");
2886 if (flag_finite_math_only
&& !flag_trapping_math
&& flag_reciprocal_math
)
2888 if (RS6000_RECIP_HAVE_RE_P (SFmode
)
2889 && (rs6000_recip_control
& RECIP_SF_DIV
) != 0)
2890 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2892 if (RS6000_RECIP_HAVE_RE_P (DFmode
)
2893 && (rs6000_recip_control
& RECIP_DF_DIV
) != 0)
2894 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2896 if (RS6000_RECIP_HAVE_RE_P (V4SFmode
)
2897 && (rs6000_recip_control
& RECIP_V4SF_DIV
) != 0)
2898 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2900 if (RS6000_RECIP_HAVE_RE_P (V2DFmode
)
2901 && (rs6000_recip_control
& RECIP_V2DF_DIV
) != 0)
2902 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2904 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode
)
2905 && (rs6000_recip_control
& RECIP_SF_RSQRT
) != 0)
2906 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2908 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode
)
2909 && (rs6000_recip_control
& RECIP_DF_RSQRT
) != 0)
2910 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2912 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode
)
2913 && (rs6000_recip_control
& RECIP_V4SF_RSQRT
) != 0)
2914 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2916 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode
)
2917 && (rs6000_recip_control
& RECIP_V2DF_RSQRT
) != 0)
2918 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2922 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2923 legitimate address support to figure out the appropriate addressing to
2925 rs6000_setup_reg_addr_masks ();
2927 if (global_init_p
|| TARGET_DEBUG_TARGET
)
2929 if (TARGET_DEBUG_REG
)
2930 rs6000_debug_reg_global ();
2932 if (TARGET_DEBUG_COST
|| TARGET_DEBUG_REG
)
2934 "SImode variable mult cost = %d\n"
2935 "SImode constant mult cost = %d\n"
2936 "SImode short constant mult cost = %d\n"
2937 "DImode multipliciation cost = %d\n"
2938 "SImode division cost = %d\n"
2939 "DImode division cost = %d\n"
2940 "Simple fp operation cost = %d\n"
2941 "DFmode multiplication cost = %d\n"
2942 "SFmode division cost = %d\n"
2943 "DFmode division cost = %d\n"
2944 "cache line size = %d\n"
2945 "l1 cache size = %d\n"
2946 "l2 cache size = %d\n"
2947 "simultaneous prefetches = %d\n"
2950 rs6000_cost
->mulsi_const
,
2951 rs6000_cost
->mulsi_const9
,
2959 rs6000_cost
->cache_line_size
,
2960 rs6000_cost
->l1_cache_size
,
2961 rs6000_cost
->l2_cache_size
,
2962 rs6000_cost
->simultaneous_prefetches
);
2967 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
2970 darwin_rs6000_override_options (void)
2972 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
2974 rs6000_altivec_abi
= 1;
2975 TARGET_ALTIVEC_VRSAVE
= 1;
2976 rs6000_current_abi
= ABI_DARWIN
;
2978 if (DEFAULT_ABI
== ABI_DARWIN
2980 darwin_one_byte_bool
= 1;
2982 if (TARGET_64BIT
&& ! TARGET_POWERPC64
)
2984 rs6000_isa_flags
|= OPTION_MASK_POWERPC64
;
2985 warning (0, "-m64 requires PowerPC64 architecture, enabling");
2989 rs6000_default_long_calls
= 1;
2990 rs6000_isa_flags
|= OPTION_MASK_SOFT_FLOAT
;
2993 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
2995 if (!flag_mkernel
&& !flag_apple_kext
2997 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
))
2998 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
3000 /* Unless the user (not the configurer) has explicitly overridden
3001 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
3002 G4 unless targeting the kernel. */
3005 && strverscmp (darwin_macosx_version_min
, "10.5") >= 0
3006 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
)
3007 && ! global_options_set
.x_rs6000_cpu_index
)
3009 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
3014 /* If not otherwise specified by a target, make 'long double' equivalent to
3017 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
3018 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
3021 /* Return the builtin mask of the various options used that could affect which
3022 builtins were used. In the past we used target_flags, but we've run out of
3023 bits, and some options like SPE and PAIRED are no longer in
3027 rs6000_builtin_mask_calculate (void)
3029 return (((TARGET_ALTIVEC
) ? RS6000_BTM_ALTIVEC
: 0)
3030 | ((TARGET_VSX
) ? RS6000_BTM_VSX
: 0)
3031 | ((TARGET_SPE
) ? RS6000_BTM_SPE
: 0)
3032 | ((TARGET_PAIRED_FLOAT
) ? RS6000_BTM_PAIRED
: 0)
3033 | ((TARGET_FRE
) ? RS6000_BTM_FRE
: 0)
3034 | ((TARGET_FRES
) ? RS6000_BTM_FRES
: 0)
3035 | ((TARGET_FRSQRTE
) ? RS6000_BTM_FRSQRTE
: 0)
3036 | ((TARGET_FRSQRTES
) ? RS6000_BTM_FRSQRTES
: 0)
3037 | ((TARGET_POPCNTD
) ? RS6000_BTM_POPCNTD
: 0)
3038 | ((rs6000_cpu
== PROCESSOR_CELL
) ? RS6000_BTM_CELL
: 0)
3039 | ((TARGET_P8_VECTOR
) ? RS6000_BTM_P8_VECTOR
: 0)
3040 | ((TARGET_CRYPTO
) ? RS6000_BTM_CRYPTO
: 0)
3041 | ((TARGET_HTM
) ? RS6000_BTM_HTM
: 0)
3042 | ((TARGET_DFP
) ? RS6000_BTM_DFP
: 0)
3043 | ((TARGET_HARD_FLOAT
) ? RS6000_BTM_HARD_FLOAT
: 0));
3046 /* Override command line options. Mostly we process the processor type and
3047 sometimes adjust other TARGET_ options. */
3050 rs6000_option_override_internal (bool global_init_p
)
3053 bool have_cpu
= false;
3055 /* The default cpu requested at configure time, if any. */
3056 const char *implicit_cpu
= OPTION_TARGET_CPU_DEFAULT
;
3058 HOST_WIDE_INT set_masks
;
3061 struct cl_target_option
*main_target_opt
3062 = ((global_init_p
|| target_option_default_node
== NULL
)
3063 ? NULL
: TREE_TARGET_OPTION (target_option_default_node
));
3065 /* Remember the explicit arguments. */
3067 rs6000_isa_flags_explicit
= global_options_set
.x_rs6000_isa_flags
;
3069 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
3070 library functions, so warn about it. The flag may be useful for
3071 performance studies from time to time though, so don't disable it
3073 if (global_options_set
.x_rs6000_alignment_flags
3074 && rs6000_alignment_flags
== MASK_ALIGN_POWER
3075 && DEFAULT_ABI
== ABI_DARWIN
3077 warning (0, "-malign-power is not supported for 64-bit Darwin;"
3078 " it is incompatible with the installed C and C++ libraries");
3080 /* Numerous experiment shows that IRA based loop pressure
3081 calculation works better for RTL loop invariant motion on targets
3082 with enough (>= 32) registers. It is an expensive optimization.
3083 So it is on only for peak performance. */
3084 if (optimize
>= 3 && global_init_p
3085 && !global_options_set
.x_flag_ira_loop_pressure
)
3086 flag_ira_loop_pressure
= 1;
3088 /* Set the pointer size. */
3091 rs6000_pmode
= (int)DImode
;
3092 rs6000_pointer_size
= 64;
3096 rs6000_pmode
= (int)SImode
;
3097 rs6000_pointer_size
= 32;
3100 /* Some OSs don't support saving the high part of 64-bit registers on context
3101 switch. Other OSs don't support saving Altivec registers. On those OSs,
3102 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
3103 if the user wants either, the user must explicitly specify them and we
3104 won't interfere with the user's specification. */
3106 set_masks
= POWERPC_MASKS
;
3107 #ifdef OS_MISSING_POWERPC64
3108 if (OS_MISSING_POWERPC64
)
3109 set_masks
&= ~OPTION_MASK_POWERPC64
;
3111 #ifdef OS_MISSING_ALTIVEC
3112 if (OS_MISSING_ALTIVEC
)
3113 set_masks
&= ~(OPTION_MASK_ALTIVEC
| OPTION_MASK_VSX
);
3116 /* Don't override by the processor default if given explicitly. */
3117 set_masks
&= ~rs6000_isa_flags_explicit
;
3119 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
3120 the cpu in a target attribute or pragma, but did not specify a tuning
3121 option, use the cpu for the tuning option rather than the option specified
3122 with -mtune on the command line. Process a '--with-cpu' configuration
3123 request as an implicit --cpu. */
3124 if (rs6000_cpu_index
>= 0)
3126 cpu_index
= rs6000_cpu_index
;
3129 else if (main_target_opt
!= NULL
&& main_target_opt
->x_rs6000_cpu_index
>= 0)
3131 rs6000_cpu_index
= cpu_index
= main_target_opt
->x_rs6000_cpu_index
;
3134 else if (implicit_cpu
)
3136 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (implicit_cpu
);
3141 const char *default_cpu
= (TARGET_POWERPC64
? "powerpc64" : "powerpc");
3142 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (default_cpu
);
3146 gcc_assert (cpu_index
>= 0);
3148 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
3149 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
3150 with those from the cpu, except for options that were explicitly set. If
3151 we don't have a cpu, do not override the target bits set in
3155 rs6000_isa_flags
&= ~set_masks
;
3156 rs6000_isa_flags
|= (processor_target_table
[cpu_index
].target_enable
3160 rs6000_isa_flags
|= (processor_target_table
[cpu_index
].target_enable
3161 & ~rs6000_isa_flags_explicit
);
3163 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
3164 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
3165 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
3166 to using rs6000_isa_flags, we need to do the initialization here. */
3168 rs6000_isa_flags
|= (TARGET_DEFAULT
& ~rs6000_isa_flags_explicit
);
3170 if (rs6000_tune_index
>= 0)
3171 tune_index
= rs6000_tune_index
;
3173 rs6000_tune_index
= tune_index
= cpu_index
;
3177 enum processor_type tune_proc
3178 = (TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
);
3181 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
3182 if (processor_target_table
[i
].processor
== tune_proc
)
3184 rs6000_tune_index
= tune_index
= i
;
3189 gcc_assert (tune_index
>= 0);
3190 rs6000_cpu
= processor_target_table
[tune_index
].processor
;
3192 /* Pick defaults for SPE related control flags. Do this early to make sure
3193 that the TARGET_ macros are representative ASAP. */
3195 int spe_capable_cpu
=
3196 (rs6000_cpu
== PROCESSOR_PPC8540
3197 || rs6000_cpu
== PROCESSOR_PPC8548
);
3199 if (!global_options_set
.x_rs6000_spe_abi
)
3200 rs6000_spe_abi
= spe_capable_cpu
;
3202 if (!global_options_set
.x_rs6000_spe
)
3203 rs6000_spe
= spe_capable_cpu
;
3205 if (!global_options_set
.x_rs6000_float_gprs
)
3207 (rs6000_cpu
== PROCESSOR_PPC8540
? 1
3208 : rs6000_cpu
== PROCESSOR_PPC8548
? 2
3212 if (global_options_set
.x_rs6000_spe_abi
3215 error ("not configured for SPE ABI");
3217 if (global_options_set
.x_rs6000_spe
3220 error ("not configured for SPE instruction set");
3222 if (main_target_opt
!= NULL
3223 && ((main_target_opt
->x_rs6000_spe_abi
!= rs6000_spe_abi
)
3224 || (main_target_opt
->x_rs6000_spe
!= rs6000_spe
)
3225 || (main_target_opt
->x_rs6000_float_gprs
!= rs6000_float_gprs
)))
3226 error ("target attribute or pragma changes SPE ABI");
3228 if (rs6000_cpu
== PROCESSOR_PPCE300C2
|| rs6000_cpu
== PROCESSOR_PPCE300C3
3229 || rs6000_cpu
== PROCESSOR_PPCE500MC
|| rs6000_cpu
== PROCESSOR_PPCE500MC64
3230 || rs6000_cpu
== PROCESSOR_PPCE5500
)
3233 error ("AltiVec not supported in this target");
3235 error ("SPE not supported in this target");
3237 if (rs6000_cpu
== PROCESSOR_PPCE6500
)
3240 error ("SPE not supported in this target");
3243 /* Disable Cell microcode if we are optimizing for the Cell
3244 and not optimizing for size. */
3245 if (rs6000_gen_cell_microcode
== -1)
3246 rs6000_gen_cell_microcode
= !(rs6000_cpu
== PROCESSOR_CELL
3249 /* If we are optimizing big endian systems for space and it's OK to
3250 use instructions that would be microcoded on the Cell, use the
3251 load/store multiple and string instructions. */
3252 if (BYTES_BIG_ENDIAN
&& optimize_size
&& rs6000_gen_cell_microcode
)
3253 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& (OPTION_MASK_MULTIPLE
3254 | OPTION_MASK_STRING
);
3256 /* Don't allow -mmultiple or -mstring on little endian systems
3257 unless the cpu is a 750, because the hardware doesn't support the
3258 instructions used in little endian mode, and causes an alignment
3259 trap. The 750 does not cause an alignment trap (except when the
3260 target is unaligned). */
3262 if (!BYTES_BIG_ENDIAN
&& rs6000_cpu
!= PROCESSOR_PPC750
)
3264 if (TARGET_MULTIPLE
)
3266 rs6000_isa_flags
&= ~OPTION_MASK_MULTIPLE
;
3267 if ((rs6000_isa_flags_explicit
& OPTION_MASK_MULTIPLE
) != 0)
3268 warning (0, "-mmultiple is not supported on little endian systems");
3273 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
3274 if ((rs6000_isa_flags_explicit
& OPTION_MASK_STRING
) != 0)
3275 warning (0, "-mstring is not supported on little endian systems");
3279 /* If little-endian, default to -mstrict-align on older processors.
3280 Testing for htm matches power8 and later. */
3281 if (!BYTES_BIG_ENDIAN
3282 && !(processor_target_table
[tune_index
].target_enable
& OPTION_MASK_HTM
))
3283 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& OPTION_MASK_STRICT_ALIGN
;
3285 /* -maltivec={le,be} implies -maltivec. */
3286 if (rs6000_altivec_element_order
!= 0)
3287 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
3289 /* Disallow -maltivec=le in big endian mode for now. This is not
3290 known to be useful for anyone. */
3291 if (BYTES_BIG_ENDIAN
&& rs6000_altivec_element_order
== 1)
3293 warning (0, N_("-maltivec=le not allowed for big-endian targets"));
3294 rs6000_altivec_element_order
= 0;
3297 /* Add some warnings for VSX. */
3300 const char *msg
= NULL
;
3301 if (!TARGET_HARD_FLOAT
|| !TARGET_FPRS
3302 || !TARGET_SINGLE_FLOAT
|| !TARGET_DOUBLE_FLOAT
)
3304 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
3305 msg
= N_("-mvsx requires hardware floating point");
3308 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
3309 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
3312 else if (TARGET_PAIRED_FLOAT
)
3313 msg
= N_("-mvsx and -mpaired are incompatible");
3314 else if (TARGET_AVOID_XFORM
> 0)
3315 msg
= N_("-mvsx needs indexed addressing");
3316 else if (!TARGET_ALTIVEC
&& (rs6000_isa_flags_explicit
3317 & OPTION_MASK_ALTIVEC
))
3319 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
3320 msg
= N_("-mvsx and -mno-altivec are incompatible");
3322 msg
= N_("-mno-altivec disables vsx");
3328 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
3329 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
3333 /* If hard-float/altivec/vsx were explicitly turned off then don't allow
3334 the -mcpu setting to enable options that conflict. */
3335 if ((!TARGET_HARD_FLOAT
|| !TARGET_ALTIVEC
|| !TARGET_VSX
)
3336 && (rs6000_isa_flags_explicit
& (OPTION_MASK_SOFT_FLOAT
3337 | OPTION_MASK_ALTIVEC
3338 | OPTION_MASK_VSX
)) != 0)
3339 rs6000_isa_flags
&= ~((OPTION_MASK_P8_VECTOR
| OPTION_MASK_CRYPTO
3340 | OPTION_MASK_DIRECT_MOVE
)
3341 & ~rs6000_isa_flags_explicit
);
3343 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3344 rs6000_print_isa_options (stderr
, 0, "before defaults", rs6000_isa_flags
);
3346 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
3347 unless the user explicitly used the -mno-<option> to disable the code. */
3348 if (TARGET_P8_VECTOR
|| TARGET_DIRECT_MOVE
|| TARGET_CRYPTO
)
3349 rs6000_isa_flags
|= (ISA_2_7_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3350 else if (TARGET_VSX
)
3351 rs6000_isa_flags
|= (ISA_2_6_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3352 else if (TARGET_POPCNTD
)
3353 rs6000_isa_flags
|= (ISA_2_6_MASKS_EMBEDDED
& ~rs6000_isa_flags_explicit
);
3354 else if (TARGET_DFP
)
3355 rs6000_isa_flags
|= (ISA_2_5_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3356 else if (TARGET_CMPB
)
3357 rs6000_isa_flags
|= (ISA_2_5_MASKS_EMBEDDED
& ~rs6000_isa_flags_explicit
);
3358 else if (TARGET_FPRND
)
3359 rs6000_isa_flags
|= (ISA_2_4_MASKS
& ~rs6000_isa_flags_explicit
);
3360 else if (TARGET_POPCNTB
)
3361 rs6000_isa_flags
|= (ISA_2_2_MASKS
& ~rs6000_isa_flags_explicit
);
3362 else if (TARGET_ALTIVEC
)
3363 rs6000_isa_flags
|= (OPTION_MASK_PPC_GFXOPT
& ~rs6000_isa_flags_explicit
);
3365 if (TARGET_CRYPTO
&& !TARGET_ALTIVEC
)
3367 if (rs6000_isa_flags_explicit
& OPTION_MASK_CRYPTO
)
3368 error ("-mcrypto requires -maltivec");
3369 rs6000_isa_flags
&= ~OPTION_MASK_CRYPTO
;
3372 if (TARGET_DIRECT_MOVE
&& !TARGET_VSX
)
3374 if (rs6000_isa_flags_explicit
& OPTION_MASK_DIRECT_MOVE
)
3375 error ("-mdirect-move requires -mvsx");
3376 rs6000_isa_flags
&= ~OPTION_MASK_DIRECT_MOVE
;
3379 if (TARGET_P8_VECTOR
&& !TARGET_ALTIVEC
)
3381 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
3382 error ("-mpower8-vector requires -maltivec");
3383 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
3386 if (TARGET_P8_VECTOR
&& !TARGET_VSX
)
3388 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
3389 error ("-mpower8-vector requires -mvsx");
3390 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
3393 if (TARGET_VSX_TIMODE
&& !TARGET_VSX
)
3395 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX_TIMODE
)
3396 error ("-mvsx-timode requires -mvsx");
3397 rs6000_isa_flags
&= ~OPTION_MASK_VSX_TIMODE
;
3400 if (TARGET_DFP
&& !TARGET_HARD_FLOAT
)
3402 if (rs6000_isa_flags_explicit
& OPTION_MASK_DFP
)
3403 error ("-mhard-dfp requires -mhard-float");
3404 rs6000_isa_flags
&= ~OPTION_MASK_DFP
;
3407 /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
3408 silently turn off quad memory mode. */
3409 if ((TARGET_QUAD_MEMORY
|| TARGET_QUAD_MEMORY_ATOMIC
) && !TARGET_POWERPC64
)
3411 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY
) != 0)
3412 warning (0, N_("-mquad-memory requires 64-bit mode"));
3414 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY_ATOMIC
) != 0)
3415 warning (0, N_("-mquad-memory-atomic requires 64-bit mode"));
3417 rs6000_isa_flags
&= ~(OPTION_MASK_QUAD_MEMORY
3418 | OPTION_MASK_QUAD_MEMORY_ATOMIC
);
3421 /* Non-atomic quad memory load/store are disabled for little endian, since
3422 the words are reversed, but atomic operations can still be done by
3423 swapping the words. */
3424 if (TARGET_QUAD_MEMORY
&& !WORDS_BIG_ENDIAN
)
3426 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY
) != 0)
3427 warning (0, N_("-mquad-memory is not available in little endian mode"));
3429 rs6000_isa_flags
&= ~OPTION_MASK_QUAD_MEMORY
;
3432 /* Assume if the user asked for normal quad memory instructions, they want
3433 the atomic versions as well, unless they explicity told us not to use quad
3434 word atomic instructions. */
3435 if (TARGET_QUAD_MEMORY
3436 && !TARGET_QUAD_MEMORY_ATOMIC
3437 && ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY_ATOMIC
) == 0))
3438 rs6000_isa_flags
|= OPTION_MASK_QUAD_MEMORY_ATOMIC
;
3440 /* Enable power8 fusion if we are tuning for power8, even if we aren't
3441 generating power8 instructions. */
3442 if (!(rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION
))
3443 rs6000_isa_flags
|= (processor_target_table
[tune_index
].target_enable
3444 & OPTION_MASK_P8_FUSION
);
3446 /* Power8 does not fuse sign extended loads with the addis. If we are
3447 optimizing at high levels for speed, convert a sign extended load into a
3448 zero extending load, and an explicit sign extension. */
3449 if (TARGET_P8_FUSION
3450 && !(rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION_SIGN
)
3451 && optimize_function_for_speed_p (cfun
)
3453 rs6000_isa_flags
|= OPTION_MASK_P8_FUSION_SIGN
;
3455 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3456 rs6000_print_isa_options (stderr
, 0, "after defaults", rs6000_isa_flags
);
3458 /* E500mc does "better" if we inline more aggressively. Respect the
3459 user's opinion, though. */
3460 if (rs6000_block_move_inline_limit
== 0
3461 && (rs6000_cpu
== PROCESSOR_PPCE500MC
3462 || rs6000_cpu
== PROCESSOR_PPCE500MC64
3463 || rs6000_cpu
== PROCESSOR_PPCE5500
3464 || rs6000_cpu
== PROCESSOR_PPCE6500
))
3465 rs6000_block_move_inline_limit
= 128;
3467 /* store_one_arg depends on expand_block_move to handle at least the
3468 size of reg_parm_stack_space. */
3469 if (rs6000_block_move_inline_limit
< (TARGET_POWERPC64
? 64 : 32))
3470 rs6000_block_move_inline_limit
= (TARGET_POWERPC64
? 64 : 32);
3474 /* If the appropriate debug option is enabled, replace the target hooks
3475 with debug versions that call the real version and then prints
3476 debugging information. */
3477 if (TARGET_DEBUG_COST
)
3479 targetm
.rtx_costs
= rs6000_debug_rtx_costs
;
3480 targetm
.address_cost
= rs6000_debug_address_cost
;
3481 targetm
.sched
.adjust_cost
= rs6000_debug_adjust_cost
;
3484 if (TARGET_DEBUG_ADDR
)
3486 targetm
.legitimate_address_p
= rs6000_debug_legitimate_address_p
;
3487 targetm
.legitimize_address
= rs6000_debug_legitimize_address
;
3488 rs6000_secondary_reload_class_ptr
3489 = rs6000_debug_secondary_reload_class
;
3490 rs6000_secondary_memory_needed_ptr
3491 = rs6000_debug_secondary_memory_needed
;
3492 rs6000_cannot_change_mode_class_ptr
3493 = rs6000_debug_cannot_change_mode_class
;
3494 rs6000_preferred_reload_class_ptr
3495 = rs6000_debug_preferred_reload_class
;
3496 rs6000_legitimize_reload_address_ptr
3497 = rs6000_debug_legitimize_reload_address
;
3498 rs6000_mode_dependent_address_ptr
3499 = rs6000_debug_mode_dependent_address
;
3502 if (rs6000_veclibabi_name
)
3504 if (strcmp (rs6000_veclibabi_name
, "mass") == 0)
3505 rs6000_veclib_handler
= rs6000_builtin_vectorized_libmass
;
3508 error ("unknown vectorization library ABI type (%s) for "
3509 "-mveclibabi= switch", rs6000_veclibabi_name
);
3515 if (!global_options_set
.x_rs6000_long_double_type_size
)
3517 if (main_target_opt
!= NULL
3518 && (main_target_opt
->x_rs6000_long_double_type_size
3519 != RS6000_DEFAULT_LONG_DOUBLE_SIZE
))
3520 error ("target attribute or pragma changes long double size");
3522 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
3525 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
3526 if (!global_options_set
.x_rs6000_ieeequad
)
3527 rs6000_ieeequad
= 1;
3530 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
3531 target attribute or pragma which automatically enables both options,
3532 unless the altivec ABI was set. This is set by default for 64-bit, but
3534 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
3535 rs6000_isa_flags
&= ~((OPTION_MASK_VSX
| OPTION_MASK_ALTIVEC
)
3536 & ~rs6000_isa_flags_explicit
);
3538 /* Enable Altivec ABI for AIX -maltivec. */
3539 if (TARGET_XCOFF
&& (TARGET_ALTIVEC
|| TARGET_VSX
))
3541 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
3542 error ("target attribute or pragma changes AltiVec ABI");
3544 rs6000_altivec_abi
= 1;
3547 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
3548 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
3549 be explicitly overridden in either case. */
3552 if (!global_options_set
.x_rs6000_altivec_abi
3553 && (TARGET_64BIT
|| TARGET_ALTIVEC
|| TARGET_VSX
))
3555 if (main_target_opt
!= NULL
&&
3556 !main_target_opt
->x_rs6000_altivec_abi
)
3557 error ("target attribute or pragma changes AltiVec ABI");
3559 rs6000_altivec_abi
= 1;
3563 /* Set the Darwin64 ABI as default for 64-bit Darwin.
3564 So far, the only darwin64 targets are also MACH-O. */
3566 && DEFAULT_ABI
== ABI_DARWIN
3569 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_darwin64_abi
)
3570 error ("target attribute or pragma changes darwin64 ABI");
3573 rs6000_darwin64_abi
= 1;
3574 /* Default to natural alignment, for better performance. */
3575 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
3579 /* Place FP constants in the constant pool instead of TOC
3580 if section anchors enabled. */
3581 if (flag_section_anchors
3582 && !global_options_set
.x_TARGET_NO_FP_IN_TOC
)
3583 TARGET_NO_FP_IN_TOC
= 1;
3585 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3586 rs6000_print_isa_options (stderr
, 0, "before subtarget", rs6000_isa_flags
);
3588 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3589 SUBTARGET_OVERRIDE_OPTIONS
;
3591 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3592 SUBSUBTARGET_OVERRIDE_OPTIONS
;
3594 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
3595 SUB3TARGET_OVERRIDE_OPTIONS
;
3598 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3599 rs6000_print_isa_options (stderr
, 0, "after subtarget", rs6000_isa_flags
);
3601 /* For the E500 family of cores, reset the single/double FP flags to let us
3602 check that they remain constant across attributes or pragmas. Also,
3603 clear a possible request for string instructions, not supported and which
3604 we might have silently queried above for -Os.
3606 For other families, clear ISEL in case it was set implicitly.
3611 case PROCESSOR_PPC8540
:
3612 case PROCESSOR_PPC8548
:
3613 case PROCESSOR_PPCE500MC
:
3614 case PROCESSOR_PPCE500MC64
:
3615 case PROCESSOR_PPCE5500
:
3616 case PROCESSOR_PPCE6500
:
3618 rs6000_single_float
= TARGET_E500_SINGLE
|| TARGET_E500_DOUBLE
;
3619 rs6000_double_float
= TARGET_E500_DOUBLE
;
3621 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
3627 if (have_cpu
&& !(rs6000_isa_flags_explicit
& OPTION_MASK_ISEL
))
3628 rs6000_isa_flags
&= ~OPTION_MASK_ISEL
;
3633 if (main_target_opt
)
3635 if (main_target_opt
->x_rs6000_single_float
!= rs6000_single_float
)
3636 error ("target attribute or pragma changes single precision floating "
3638 if (main_target_opt
->x_rs6000_double_float
!= rs6000_double_float
)
3639 error ("target attribute or pragma changes double precision floating "
3643 /* Detect invalid option combinations with E500. */
3646 rs6000_always_hint
= (rs6000_cpu
!= PROCESSOR_POWER4
3647 && rs6000_cpu
!= PROCESSOR_POWER5
3648 && rs6000_cpu
!= PROCESSOR_POWER6
3649 && rs6000_cpu
!= PROCESSOR_POWER7
3650 && rs6000_cpu
!= PROCESSOR_POWER8
3651 && rs6000_cpu
!= PROCESSOR_PPCA2
3652 && rs6000_cpu
!= PROCESSOR_CELL
3653 && rs6000_cpu
!= PROCESSOR_PPC476
);
3654 rs6000_sched_groups
= (rs6000_cpu
== PROCESSOR_POWER4
3655 || rs6000_cpu
== PROCESSOR_POWER5
3656 || rs6000_cpu
== PROCESSOR_POWER7
3657 || rs6000_cpu
== PROCESSOR_POWER8
);
3658 rs6000_align_branch_targets
= (rs6000_cpu
== PROCESSOR_POWER4
3659 || rs6000_cpu
== PROCESSOR_POWER5
3660 || rs6000_cpu
== PROCESSOR_POWER6
3661 || rs6000_cpu
== PROCESSOR_POWER7
3662 || rs6000_cpu
== PROCESSOR_POWER8
3663 || rs6000_cpu
== PROCESSOR_PPCE500MC
3664 || rs6000_cpu
== PROCESSOR_PPCE500MC64
3665 || rs6000_cpu
== PROCESSOR_PPCE5500
3666 || rs6000_cpu
== PROCESSOR_PPCE6500
);
3668 /* Allow debug switches to override the above settings. These are set to -1
3669 in rs6000.opt to indicate the user hasn't directly set the switch. */
3670 if (TARGET_ALWAYS_HINT
>= 0)
3671 rs6000_always_hint
= TARGET_ALWAYS_HINT
;
3673 if (TARGET_SCHED_GROUPS
>= 0)
3674 rs6000_sched_groups
= TARGET_SCHED_GROUPS
;
3676 if (TARGET_ALIGN_BRANCH_TARGETS
>= 0)
3677 rs6000_align_branch_targets
= TARGET_ALIGN_BRANCH_TARGETS
;
3679 rs6000_sched_restricted_insns_priority
3680 = (rs6000_sched_groups
? 1 : 0);
3682 /* Handle -msched-costly-dep option. */
3683 rs6000_sched_costly_dep
3684 = (rs6000_sched_groups
? true_store_to_load_dep_costly
: no_dep_costly
);
3686 if (rs6000_sched_costly_dep_str
)
3688 if (! strcmp (rs6000_sched_costly_dep_str
, "no"))
3689 rs6000_sched_costly_dep
= no_dep_costly
;
3690 else if (! strcmp (rs6000_sched_costly_dep_str
, "all"))
3691 rs6000_sched_costly_dep
= all_deps_costly
;
3692 else if (! strcmp (rs6000_sched_costly_dep_str
, "true_store_to_load"))
3693 rs6000_sched_costly_dep
= true_store_to_load_dep_costly
;
3694 else if (! strcmp (rs6000_sched_costly_dep_str
, "store_to_load"))
3695 rs6000_sched_costly_dep
= store_to_load_dep_costly
;
3697 rs6000_sched_costly_dep
= ((enum rs6000_dependence_cost
)
3698 atoi (rs6000_sched_costly_dep_str
));
3701 /* Handle -minsert-sched-nops option. */
3702 rs6000_sched_insert_nops
3703 = (rs6000_sched_groups
? sched_finish_regroup_exact
: sched_finish_none
);
3705 if (rs6000_sched_insert_nops_str
)
3707 if (! strcmp (rs6000_sched_insert_nops_str
, "no"))
3708 rs6000_sched_insert_nops
= sched_finish_none
;
3709 else if (! strcmp (rs6000_sched_insert_nops_str
, "pad"))
3710 rs6000_sched_insert_nops
= sched_finish_pad_groups
;
3711 else if (! strcmp (rs6000_sched_insert_nops_str
, "regroup_exact"))
3712 rs6000_sched_insert_nops
= sched_finish_regroup_exact
;
3714 rs6000_sched_insert_nops
= ((enum rs6000_nop_insertion
)
3715 atoi (rs6000_sched_insert_nops_str
));
3720 #ifdef TARGET_REGNAMES
3721 /* If the user desires alternate register names, copy in the
3722 alternate names now. */
3723 if (TARGET_REGNAMES
)
3724 memcpy (rs6000_reg_names
, alt_reg_names
, sizeof (rs6000_reg_names
));
3727 /* Set aix_struct_return last, after the ABI is determined.
3728 If -maix-struct-return or -msvr4-struct-return was explicitly
3729 used, don't override with the ABI default. */
3730 if (!global_options_set
.x_aix_struct_return
)
3731 aix_struct_return
= (DEFAULT_ABI
!= ABI_V4
|| DRAFT_V4_STRUCT_RET
);
3734 /* IBM XL compiler defaults to unsigned bitfields. */
3735 if (TARGET_XL_COMPAT
)
3736 flag_signed_bitfields
= 0;
3739 if (TARGET_LONG_DOUBLE_128
&& !TARGET_IEEEQUAD
)
3740 REAL_MODE_FORMAT (TFmode
) = &ibm_extended_format
;
3743 ASM_GENERATE_INTERNAL_LABEL (toc_label_name
, "LCTOC", 1);
3745 /* We can only guarantee the availability of DI pseudo-ops when
3746 assembling for 64-bit targets. */
3749 targetm
.asm_out
.aligned_op
.di
= NULL
;
3750 targetm
.asm_out
.unaligned_op
.di
= NULL
;
3754 /* Set branch target alignment, if not optimizing for size. */
3757 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
3758 aligned 8byte to avoid misprediction by the branch predictor. */
3759 if (rs6000_cpu
== PROCESSOR_TITAN
3760 || rs6000_cpu
== PROCESSOR_CELL
)
3762 if (align_functions
<= 0)
3763 align_functions
= 8;
3764 if (align_jumps
<= 0)
3766 if (align_loops
<= 0)
3769 if (rs6000_align_branch_targets
)
3771 if (align_functions
<= 0)
3772 align_functions
= 16;
3773 if (align_jumps
<= 0)
3775 if (align_loops
<= 0)
3777 can_override_loop_align
= 1;
3781 if (align_jumps_max_skip
<= 0)
3782 align_jumps_max_skip
= 15;
3783 if (align_loops_max_skip
<= 0)
3784 align_loops_max_skip
= 15;
3787 /* Arrange to save and restore machine status around nested functions. */
3788 init_machine_status
= rs6000_init_machine_status
;
3790 /* We should always be splitting complex arguments, but we can't break
3791 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
3792 if (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
)
3793 targetm
.calls
.split_complex_arg
= NULL
;
3796 /* Initialize rs6000_cost with the appropriate target costs. */
3798 rs6000_cost
= TARGET_POWERPC64
? &size64_cost
: &size32_cost
;
3802 case PROCESSOR_RS64A
:
3803 rs6000_cost
= &rs64a_cost
;
3806 case PROCESSOR_MPCCORE
:
3807 rs6000_cost
= &mpccore_cost
;
3810 case PROCESSOR_PPC403
:
3811 rs6000_cost
= &ppc403_cost
;
3814 case PROCESSOR_PPC405
:
3815 rs6000_cost
= &ppc405_cost
;
3818 case PROCESSOR_PPC440
:
3819 rs6000_cost
= &ppc440_cost
;
3822 case PROCESSOR_PPC476
:
3823 rs6000_cost
= &ppc476_cost
;
3826 case PROCESSOR_PPC601
:
3827 rs6000_cost
= &ppc601_cost
;
3830 case PROCESSOR_PPC603
:
3831 rs6000_cost
= &ppc603_cost
;
3834 case PROCESSOR_PPC604
:
3835 rs6000_cost
= &ppc604_cost
;
3838 case PROCESSOR_PPC604e
:
3839 rs6000_cost
= &ppc604e_cost
;
3842 case PROCESSOR_PPC620
:
3843 rs6000_cost
= &ppc620_cost
;
3846 case PROCESSOR_PPC630
:
3847 rs6000_cost
= &ppc630_cost
;
3850 case PROCESSOR_CELL
:
3851 rs6000_cost
= &ppccell_cost
;
3854 case PROCESSOR_PPC750
:
3855 case PROCESSOR_PPC7400
:
3856 rs6000_cost
= &ppc750_cost
;
3859 case PROCESSOR_PPC7450
:
3860 rs6000_cost
= &ppc7450_cost
;
3863 case PROCESSOR_PPC8540
:
3864 case PROCESSOR_PPC8548
:
3865 rs6000_cost
= &ppc8540_cost
;
3868 case PROCESSOR_PPCE300C2
:
3869 case PROCESSOR_PPCE300C3
:
3870 rs6000_cost
= &ppce300c2c3_cost
;
3873 case PROCESSOR_PPCE500MC
:
3874 rs6000_cost
= &ppce500mc_cost
;
3877 case PROCESSOR_PPCE500MC64
:
3878 rs6000_cost
= &ppce500mc64_cost
;
3881 case PROCESSOR_PPCE5500
:
3882 rs6000_cost
= &ppce5500_cost
;
3885 case PROCESSOR_PPCE6500
:
3886 rs6000_cost
= &ppce6500_cost
;
3889 case PROCESSOR_TITAN
:
3890 rs6000_cost
= &titan_cost
;
3893 case PROCESSOR_POWER4
:
3894 case PROCESSOR_POWER5
:
3895 rs6000_cost
= &power4_cost
;
3898 case PROCESSOR_POWER6
:
3899 rs6000_cost
= &power6_cost
;
3902 case PROCESSOR_POWER7
:
3903 rs6000_cost
= &power7_cost
;
3906 case PROCESSOR_POWER8
:
3907 rs6000_cost
= &power8_cost
;
3910 case PROCESSOR_PPCA2
:
3911 rs6000_cost
= &ppca2_cost
;
3920 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
3921 rs6000_cost
->simultaneous_prefetches
,
3922 global_options
.x_param_values
,
3923 global_options_set
.x_param_values
);
3924 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, rs6000_cost
->l1_cache_size
,
3925 global_options
.x_param_values
,
3926 global_options_set
.x_param_values
);
3927 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
3928 rs6000_cost
->cache_line_size
,
3929 global_options
.x_param_values
,
3930 global_options_set
.x_param_values
);
3931 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, rs6000_cost
->l2_cache_size
,
3932 global_options
.x_param_values
,
3933 global_options_set
.x_param_values
);
3935 /* Increase loop peeling limits based on performance analysis. */
3936 maybe_set_param_value (PARAM_MAX_PEELED_INSNS
, 400,
3937 global_options
.x_param_values
,
3938 global_options_set
.x_param_values
);
3939 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 400,
3940 global_options
.x_param_values
,
3941 global_options_set
.x_param_values
);
3943 /* If using typedef char *va_list, signal that
3944 __builtin_va_start (&ap, 0) can be optimized to
3945 ap = __builtin_next_arg (0). */
3946 if (DEFAULT_ABI
!= ABI_V4
)
3947 targetm
.expand_builtin_va_start
= NULL
;
3950 /* Set up single/double float flags.
3951 If TARGET_HARD_FLOAT is set, but neither single or double is set,
3952 then set both flags. */
3953 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
3954 && rs6000_single_float
== 0 && rs6000_double_float
== 0)
3955 rs6000_single_float
= rs6000_double_float
= 1;
3957 /* If not explicitly specified via option, decide whether to generate indexed
3958 load/store instructions. */
3959 if (TARGET_AVOID_XFORM
== -1)
3960 /* Avoid indexed addressing when targeting Power6 in order to avoid the
3961 DERAT mispredict penalty. However the LVE and STVE altivec instructions
3962 need indexed accesses and the type used is the scalar type of the element
3963 being loaded or stored. */
3964 TARGET_AVOID_XFORM
= (rs6000_cpu
== PROCESSOR_POWER6
&& TARGET_CMPB
3965 && !TARGET_ALTIVEC
);
3967 /* Set the -mrecip options. */
3968 if (rs6000_recip_name
)
3970 char *p
= ASTRDUP (rs6000_recip_name
);
3972 unsigned int mask
, i
;
3975 while ((q
= strtok (p
, ",")) != NULL
)
3986 if (!strcmp (q
, "default"))
3987 mask
= ((TARGET_RECIP_PRECISION
)
3988 ? RECIP_HIGH_PRECISION
: RECIP_LOW_PRECISION
);
3991 for (i
= 0; i
< ARRAY_SIZE (recip_options
); i
++)
3992 if (!strcmp (q
, recip_options
[i
].string
))
3994 mask
= recip_options
[i
].mask
;
3998 if (i
== ARRAY_SIZE (recip_options
))
4000 error ("unknown option for -mrecip=%s", q
);
4008 rs6000_recip_control
&= ~mask
;
4010 rs6000_recip_control
|= mask
;
4014 /* Set the builtin mask of the various options used that could affect which
4015 builtins were used. In the past we used target_flags, but we've run out
4016 of bits, and some options like SPE and PAIRED are no longer in
4018 rs6000_builtin_mask
= rs6000_builtin_mask_calculate ();
4019 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
4022 "new builtin mask = " HOST_WIDE_INT_PRINT_HEX
", ",
4023 rs6000_builtin_mask
);
4024 rs6000_print_builtin_options (stderr
, 0, NULL
, rs6000_builtin_mask
);
4027 /* Initialize all of the registers. */
4028 rs6000_init_hard_regno_mode_ok (global_init_p
);
4030 /* Save the initial options in case the user does function specific options */
4032 target_option_default_node
= target_option_current_node
4033 = build_target_option_node (&global_options
);
4035 /* If not explicitly specified via option, decide whether to generate the
4036 extra blr's required to preserve the link stack on some cpus (eg, 476). */
4037 if (TARGET_LINK_STACK
== -1)
4038 SET_TARGET_LINK_STACK (rs6000_cpu
== PROCESSOR_PPC476
&& flag_pic
);
4043 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
4044 define the target cpu type. */
4047 rs6000_option_override (void)
4049 (void) rs6000_option_override_internal (true);
4053 /* Implement targetm.vectorize.builtin_mask_for_load. */
4055 rs6000_builtin_mask_for_load (void)
4057 if (TARGET_ALTIVEC
|| TARGET_VSX
)
4058 return altivec_builtin_mask_for_load
;
4063 /* Implement LOOP_ALIGN. */
4065 rs6000_loop_align (rtx label
)
4070 /* Don't override loop alignment if -falign-loops was specified. */
4071 if (!can_override_loop_align
)
4072 return align_loops_log
;
4074 bb
= BLOCK_FOR_INSN (label
);
4075 ninsns
= num_loop_insns(bb
->loop_father
);
4077 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
4078 if (ninsns
> 4 && ninsns
<= 8
4079 && (rs6000_cpu
== PROCESSOR_POWER4
4080 || rs6000_cpu
== PROCESSOR_POWER5
4081 || rs6000_cpu
== PROCESSOR_POWER6
4082 || rs6000_cpu
== PROCESSOR_POWER7
4083 || rs6000_cpu
== PROCESSOR_POWER8
))
4086 return align_loops_log
;
4089 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
4091 rs6000_loop_align_max_skip (rtx label
)
4093 return (1 << rs6000_loop_align (label
)) - 1;
4096 /* Return true iff, data reference of TYPE can reach vector alignment (16)
4097 after applying N number of iterations. This routine does not determine
4098 how may iterations are required to reach desired alignment. */
4101 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED
, bool is_packed
)
4108 if (rs6000_alignment_flags
== MASK_ALIGN_NATURAL
)
4111 if (rs6000_alignment_flags
== MASK_ALIGN_POWER
)
4121 /* Assuming that all other types are naturally aligned. CHECKME! */
4126 /* Return true if the vector misalignment factor is supported by the
4129 rs6000_builtin_support_vector_misalignment (enum machine_mode mode
,
4136 /* Return if movmisalign pattern is not supported for this mode. */
4137 if (optab_handler (movmisalign_optab
, mode
) == CODE_FOR_nothing
)
4140 if (misalignment
== -1)
4142 /* Misalignment factor is unknown at compile time but we know
4143 it's word aligned. */
4144 if (rs6000_vector_alignment_reachable (type
, is_packed
))
4146 int element_size
= TREE_INT_CST_LOW (TYPE_SIZE (type
));
4148 if (element_size
== 64 || element_size
== 32)
4155 /* VSX supports word-aligned vector. */
4156 if (misalignment
% 4 == 0)
4162 /* Implement targetm.vectorize.builtin_vectorization_cost. */
4164 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost
,
4165 tree vectype
, int misalign
)
4170 switch (type_of_cost
)
4180 case cond_branch_not_taken
:
4189 case vec_promote_demote
:
4195 case cond_branch_taken
:
4198 case unaligned_load
:
4199 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
4201 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
4203 /* Double word aligned. */
4211 /* Double word aligned. */
4215 /* Unknown misalignment. */
4228 /* Misaligned loads are not supported. */
4233 case unaligned_store
:
4234 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
4236 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
4238 /* Double word aligned. */
4246 /* Double word aligned. */
4250 /* Unknown misalignment. */
4263 /* Misaligned stores are not supported. */
4269 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
4270 elem_type
= TREE_TYPE (vectype
);
4271 /* 32-bit vectors loaded into registers are stored as double
4272 precision, so we need n/2 converts in addition to the usual
4273 n/2 merges to construct a vector of short floats from them. */
4274 if (SCALAR_FLOAT_TYPE_P (elem_type
)
4275 && TYPE_PRECISION (elem_type
) == 32)
4276 return elements
+ 1;
4278 return elements
/ 2 + 1;
4285 /* Implement targetm.vectorize.preferred_simd_mode. */
4287 static enum machine_mode
4288 rs6000_preferred_simd_mode (enum machine_mode mode
)
4297 if (TARGET_ALTIVEC
|| TARGET_VSX
)
4323 if (TARGET_PAIRED_FLOAT
4329 typedef struct _rs6000_cost_data
4331 struct loop
*loop_info
;
4335 /* Test for likely overcommitment of vector hardware resources. If a
4336 loop iteration is relatively large, and too large a percentage of
4337 instructions in the loop are vectorized, the cost model may not
4338 adequately reflect delays from unavailable vector resources.
4339 Penalize the loop body cost for this case. */
4342 rs6000_density_test (rs6000_cost_data
*data
)
4344 const int DENSITY_PCT_THRESHOLD
= 85;
4345 const int DENSITY_SIZE_THRESHOLD
= 70;
4346 const int DENSITY_PENALTY
= 10;
4347 struct loop
*loop
= data
->loop_info
;
4348 basic_block
*bbs
= get_loop_body (loop
);
4349 int nbbs
= loop
->num_nodes
;
4350 int vec_cost
= data
->cost
[vect_body
], not_vec_cost
= 0;
4353 for (i
= 0; i
< nbbs
; i
++)
4355 basic_block bb
= bbs
[i
];
4356 gimple_stmt_iterator gsi
;
4358 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
4360 gimple stmt
= gsi_stmt (gsi
);
4361 stmt_vec_info stmt_info
= vinfo_for_stmt (stmt
);
4363 if (!STMT_VINFO_RELEVANT_P (stmt_info
)
4364 && !STMT_VINFO_IN_PATTERN_P (stmt_info
))
4370 density_pct
= (vec_cost
* 100) / (vec_cost
+ not_vec_cost
);
4372 if (density_pct
> DENSITY_PCT_THRESHOLD
4373 && vec_cost
+ not_vec_cost
> DENSITY_SIZE_THRESHOLD
)
4375 data
->cost
[vect_body
] = vec_cost
* (100 + DENSITY_PENALTY
) / 100;
4376 if (dump_enabled_p ())
4377 dump_printf_loc (MSG_NOTE
, vect_location
,
4378 "density %d%%, cost %d exceeds threshold, penalizing "
4379 "loop body cost by %d%%", density_pct
,
4380 vec_cost
+ not_vec_cost
, DENSITY_PENALTY
);
4384 /* Implement targetm.vectorize.init_cost. */
4387 rs6000_init_cost (struct loop
*loop_info
)
4389 rs6000_cost_data
*data
= XNEW (struct _rs6000_cost_data
);
4390 data
->loop_info
= loop_info
;
4391 data
->cost
[vect_prologue
] = 0;
4392 data
->cost
[vect_body
] = 0;
4393 data
->cost
[vect_epilogue
] = 0;
4397 /* Implement targetm.vectorize.add_stmt_cost. */
4400 rs6000_add_stmt_cost (void *data
, int count
, enum vect_cost_for_stmt kind
,
4401 struct _stmt_vec_info
*stmt_info
, int misalign
,
4402 enum vect_cost_model_location where
)
4404 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
4405 unsigned retval
= 0;
4407 if (flag_vect_cost_model
)
4409 tree vectype
= stmt_info
? stmt_vectype (stmt_info
) : NULL_TREE
;
4410 int stmt_cost
= rs6000_builtin_vectorization_cost (kind
, vectype
,
4412 /* Statements in an inner loop relative to the loop being
4413 vectorized are weighted more heavily. The value here is
4414 arbitrary and could potentially be improved with analysis. */
4415 if (where
== vect_body
&& stmt_info
&& stmt_in_inner_loop_p (stmt_info
))
4416 count
*= 50; /* FIXME. */
4418 retval
= (unsigned) (count
* stmt_cost
);
4419 cost_data
->cost
[where
] += retval
;
4425 /* Implement targetm.vectorize.finish_cost. */
4428 rs6000_finish_cost (void *data
, unsigned *prologue_cost
,
4429 unsigned *body_cost
, unsigned *epilogue_cost
)
4431 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
4433 if (cost_data
->loop_info
)
4434 rs6000_density_test (cost_data
);
4436 *prologue_cost
= cost_data
->cost
[vect_prologue
];
4437 *body_cost
= cost_data
->cost
[vect_body
];
4438 *epilogue_cost
= cost_data
->cost
[vect_epilogue
];
4441 /* Implement targetm.vectorize.destroy_cost_data. */
4444 rs6000_destroy_cost_data (void *data
)
4449 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
4450 library with vectorized intrinsics. */
4453 rs6000_builtin_vectorized_libmass (tree fndecl
, tree type_out
, tree type_in
)
4456 const char *suffix
= NULL
;
4457 tree fntype
, new_fndecl
, bdecl
= NULL_TREE
;
4460 enum machine_mode el_mode
, in_mode
;
4463 /* Libmass is suitable for unsafe math only as it does not correctly support
4464 parts of IEEE with the required precision such as denormals. Only support
4465 it if we have VSX to use the simd d2 or f4 functions.
4466 XXX: Add variable length support. */
4467 if (!flag_unsafe_math_optimizations
|| !TARGET_VSX
)
4470 el_mode
= TYPE_MODE (TREE_TYPE (type_out
));
4471 n
= TYPE_VECTOR_SUBPARTS (type_out
);
4472 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
4473 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
4474 if (el_mode
!= in_mode
4478 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_NORMAL
)
4480 enum built_in_function fn
= DECL_FUNCTION_CODE (fndecl
);
4483 case BUILT_IN_ATAN2
:
4484 case BUILT_IN_HYPOT
:
4490 case BUILT_IN_ACOSH
:
4492 case BUILT_IN_ASINH
:
4494 case BUILT_IN_ATANH
:
4502 case BUILT_IN_EXPM1
:
4503 case BUILT_IN_LGAMMA
:
4504 case BUILT_IN_LOG10
:
4505 case BUILT_IN_LOG1P
:
4513 bdecl
= builtin_decl_implicit (fn
);
4514 suffix
= "d2"; /* pow -> powd2 */
4515 if (el_mode
!= DFmode
4521 case BUILT_IN_ATAN2F
:
4522 case BUILT_IN_HYPOTF
:
4527 case BUILT_IN_ACOSF
:
4528 case BUILT_IN_ACOSHF
:
4529 case BUILT_IN_ASINF
:
4530 case BUILT_IN_ASINHF
:
4531 case BUILT_IN_ATANF
:
4532 case BUILT_IN_ATANHF
:
4533 case BUILT_IN_CBRTF
:
4535 case BUILT_IN_COSHF
:
4537 case BUILT_IN_ERFCF
:
4538 case BUILT_IN_EXP2F
:
4540 case BUILT_IN_EXPM1F
:
4541 case BUILT_IN_LGAMMAF
:
4542 case BUILT_IN_LOG10F
:
4543 case BUILT_IN_LOG1PF
:
4544 case BUILT_IN_LOG2F
:
4547 case BUILT_IN_SINHF
:
4548 case BUILT_IN_SQRTF
:
4550 case BUILT_IN_TANHF
:
4551 bdecl
= builtin_decl_implicit (fn
);
4552 suffix
= "4"; /* powf -> powf4 */
4553 if (el_mode
!= SFmode
4566 gcc_assert (suffix
!= NULL
);
4567 bname
= IDENTIFIER_POINTER (DECL_NAME (bdecl
));
4571 strcpy (name
, bname
+ sizeof ("__builtin_") - 1);
4572 strcat (name
, suffix
);
4575 fntype
= build_function_type_list (type_out
, type_in
, NULL
);
4576 else if (n_args
== 2)
4577 fntype
= build_function_type_list (type_out
, type_in
, type_in
, NULL
);
4581 /* Build a function declaration for the vectorized function. */
4582 new_fndecl
= build_decl (BUILTINS_LOCATION
,
4583 FUNCTION_DECL
, get_identifier (name
), fntype
);
4584 TREE_PUBLIC (new_fndecl
) = 1;
4585 DECL_EXTERNAL (new_fndecl
) = 1;
4586 DECL_IS_NOVOPS (new_fndecl
) = 1;
4587 TREE_READONLY (new_fndecl
) = 1;
4592 /* Returns a function decl for a vectorized version of the builtin function
4593 with builtin function code FN and the result vector type TYPE, or NULL_TREE
4594 if it is not available. */
4597 rs6000_builtin_vectorized_function (tree fndecl
, tree type_out
,
4600 enum machine_mode in_mode
, out_mode
;
4603 if (TARGET_DEBUG_BUILTIN
)
4604 fprintf (stderr
, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
4605 IDENTIFIER_POINTER (DECL_NAME (fndecl
)),
4606 GET_MODE_NAME (TYPE_MODE (type_out
)),
4607 GET_MODE_NAME (TYPE_MODE (type_in
)));
4609 if (TREE_CODE (type_out
) != VECTOR_TYPE
4610 || TREE_CODE (type_in
) != VECTOR_TYPE
4611 || !TARGET_VECTORIZE_BUILTINS
)
4614 out_mode
= TYPE_MODE (TREE_TYPE (type_out
));
4615 out_n
= TYPE_VECTOR_SUBPARTS (type_out
);
4616 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
4617 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
4619 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_NORMAL
)
4621 enum built_in_function fn
= DECL_FUNCTION_CODE (fndecl
);
4624 case BUILT_IN_CLZIMAX
:
4625 case BUILT_IN_CLZLL
:
4628 if (TARGET_P8_VECTOR
&& in_mode
== out_mode
&& out_n
== in_n
)
4630 if (out_mode
== QImode
&& out_n
== 16)
4631 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZB
];
4632 else if (out_mode
== HImode
&& out_n
== 8)
4633 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZH
];
4634 else if (out_mode
== SImode
&& out_n
== 4)
4635 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZW
];
4636 else if (out_mode
== DImode
&& out_n
== 2)
4637 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZD
];
4640 case BUILT_IN_COPYSIGN
:
4641 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4642 && out_mode
== DFmode
&& out_n
== 2
4643 && in_mode
== DFmode
&& in_n
== 2)
4644 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNDP
];
4646 case BUILT_IN_COPYSIGNF
:
4647 if (out_mode
!= SFmode
|| out_n
!= 4
4648 || in_mode
!= SFmode
|| in_n
!= 4)
4650 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4651 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNSP
];
4652 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4653 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_COPYSIGN_V4SF
];
4655 case BUILT_IN_POPCOUNTIMAX
:
4656 case BUILT_IN_POPCOUNTLL
:
4657 case BUILT_IN_POPCOUNTL
:
4658 case BUILT_IN_POPCOUNT
:
4659 if (TARGET_P8_VECTOR
&& in_mode
== out_mode
&& out_n
== in_n
)
4661 if (out_mode
== QImode
&& out_n
== 16)
4662 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTB
];
4663 else if (out_mode
== HImode
&& out_n
== 8)
4664 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTH
];
4665 else if (out_mode
== SImode
&& out_n
== 4)
4666 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTW
];
4667 else if (out_mode
== DImode
&& out_n
== 2)
4668 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTD
];
4672 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4673 && out_mode
== DFmode
&& out_n
== 2
4674 && in_mode
== DFmode
&& in_n
== 2)
4675 return rs6000_builtin_decls
[VSX_BUILTIN_XVSQRTDP
];
4677 case BUILT_IN_SQRTF
:
4678 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4679 && out_mode
== SFmode
&& out_n
== 4
4680 && in_mode
== SFmode
&& in_n
== 4)
4681 return rs6000_builtin_decls
[VSX_BUILTIN_XVSQRTSP
];
4684 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4685 && out_mode
== DFmode
&& out_n
== 2
4686 && in_mode
== DFmode
&& in_n
== 2)
4687 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIP
];
4689 case BUILT_IN_CEILF
:
4690 if (out_mode
!= SFmode
|| out_n
!= 4
4691 || in_mode
!= SFmode
|| in_n
!= 4)
4693 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4694 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIP
];
4695 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4696 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIP
];
4698 case BUILT_IN_FLOOR
:
4699 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4700 && out_mode
== DFmode
&& out_n
== 2
4701 && in_mode
== DFmode
&& in_n
== 2)
4702 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIM
];
4704 case BUILT_IN_FLOORF
:
4705 if (out_mode
!= SFmode
|| out_n
!= 4
4706 || in_mode
!= SFmode
|| in_n
!= 4)
4708 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4709 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIM
];
4710 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4711 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIM
];
4714 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4715 && out_mode
== DFmode
&& out_n
== 2
4716 && in_mode
== DFmode
&& in_n
== 2)
4717 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDDP
];
4720 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4721 && out_mode
== SFmode
&& out_n
== 4
4722 && in_mode
== SFmode
&& in_n
== 4)
4723 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDSP
];
4724 else if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
4725 && out_mode
== SFmode
&& out_n
== 4
4726 && in_mode
== SFmode
&& in_n
== 4)
4727 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMADDFP
];
4729 case BUILT_IN_TRUNC
:
4730 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4731 && out_mode
== DFmode
&& out_n
== 2
4732 && in_mode
== DFmode
&& in_n
== 2)
4733 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIZ
];
4735 case BUILT_IN_TRUNCF
:
4736 if (out_mode
!= SFmode
|| out_n
!= 4
4737 || in_mode
!= SFmode
|| in_n
!= 4)
4739 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4740 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIZ
];
4741 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4742 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIZ
];
4744 case BUILT_IN_NEARBYINT
:
4745 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4746 && flag_unsafe_math_optimizations
4747 && out_mode
== DFmode
&& out_n
== 2
4748 && in_mode
== DFmode
&& in_n
== 2)
4749 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPI
];
4751 case BUILT_IN_NEARBYINTF
:
4752 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4753 && flag_unsafe_math_optimizations
4754 && out_mode
== SFmode
&& out_n
== 4
4755 && in_mode
== SFmode
&& in_n
== 4)
4756 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPI
];
4759 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4760 && !flag_trapping_math
4761 && out_mode
== DFmode
&& out_n
== 2
4762 && in_mode
== DFmode
&& in_n
== 2)
4763 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIC
];
4765 case BUILT_IN_RINTF
:
4766 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4767 && !flag_trapping_math
4768 && out_mode
== SFmode
&& out_n
== 4
4769 && in_mode
== SFmode
&& in_n
== 4)
4770 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIC
];
4777 else if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_MD
)
4779 enum rs6000_builtins fn
4780 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
4783 case RS6000_BUILTIN_RSQRTF
:
4784 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
4785 && out_mode
== SFmode
&& out_n
== 4
4786 && in_mode
== SFmode
&& in_n
== 4)
4787 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRSQRTFP
];
4789 case RS6000_BUILTIN_RSQRT
:
4790 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4791 && out_mode
== DFmode
&& out_n
== 2
4792 && in_mode
== DFmode
&& in_n
== 2)
4793 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
4795 case RS6000_BUILTIN_RECIPF
:
4796 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
4797 && out_mode
== SFmode
&& out_n
== 4
4798 && in_mode
== SFmode
&& in_n
== 4)
4799 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRECIPFP
];
4801 case RS6000_BUILTIN_RECIP
:
4802 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4803 && out_mode
== DFmode
&& out_n
== 2
4804 && in_mode
== DFmode
&& in_n
== 2)
4805 return rs6000_builtin_decls
[VSX_BUILTIN_RECIP_V2DF
];
4812 /* Generate calls to libmass if appropriate. */
4813 if (rs6000_veclib_handler
)
4814 return rs6000_veclib_handler (fndecl
, type_out
, type_in
);
4819 /* Default CPU string for rs6000*_file_start functions. */
4820 static const char *rs6000_default_cpu
;
4822 /* Do anything needed at the start of the asm file. */
4825 rs6000_file_start (void)
4828 const char *start
= buffer
;
4829 FILE *file
= asm_out_file
;
4831 rs6000_default_cpu
= TARGET_CPU_DEFAULT
;
4833 default_file_start ();
4835 if (flag_verbose_asm
)
4837 sprintf (buffer
, "\n%s rs6000/powerpc options:", ASM_COMMENT_START
);
4839 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
4841 fprintf (file
, "%s --with-cpu=%s", start
, rs6000_default_cpu
);
4845 if (global_options_set
.x_rs6000_cpu_index
)
4847 fprintf (file
, "%s -mcpu=%s", start
,
4848 processor_target_table
[rs6000_cpu_index
].name
);
4852 if (global_options_set
.x_rs6000_tune_index
)
4854 fprintf (file
, "%s -mtune=%s", start
,
4855 processor_target_table
[rs6000_tune_index
].name
);
4859 if (PPC405_ERRATUM77
)
4861 fprintf (file
, "%s PPC405CR_ERRATUM77", start
);
4865 #ifdef USING_ELFOS_H
4866 switch (rs6000_sdata
)
4868 case SDATA_NONE
: fprintf (file
, "%s -msdata=none", start
); start
= ""; break;
4869 case SDATA_DATA
: fprintf (file
, "%s -msdata=data", start
); start
= ""; break;
4870 case SDATA_SYSV
: fprintf (file
, "%s -msdata=sysv", start
); start
= ""; break;
4871 case SDATA_EABI
: fprintf (file
, "%s -msdata=eabi", start
); start
= ""; break;
4874 if (rs6000_sdata
&& g_switch_value
)
4876 fprintf (file
, "%s -G %d", start
,
4886 if (DEFAULT_ABI
== ABI_ELFv2
)
4887 fprintf (file
, "\t.abiversion 2\n");
4889 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
4890 || (TARGET_ELF
&& flag_pic
== 2))
4892 switch_to_section (toc_section
);
4893 switch_to_section (text_section
);
4898 /* Return nonzero if this function is known to have a null epilogue. */
4901 direct_return (void)
4903 if (reload_completed
)
4905 rs6000_stack_t
*info
= rs6000_stack_info ();
4907 if (info
->first_gp_reg_save
== 32
4908 && info
->first_fp_reg_save
== 64
4909 && info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
4910 && ! info
->lr_save_p
4911 && ! info
->cr_save_p
4912 && info
->vrsave_mask
== 0
4920 /* Return the number of instructions it takes to form a constant in an
4921 integer register. */
4924 num_insns_constant_wide (HOST_WIDE_INT value
)
4926 /* signed constant loadable with addi */
4927 if ((unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000)
4930 /* constant loadable with addis */
4931 else if ((value
& 0xffff) == 0
4932 && (value
>> 31 == -1 || value
>> 31 == 0))
4935 else if (TARGET_POWERPC64
)
4937 HOST_WIDE_INT low
= ((value
& 0xffffffff) ^ 0x80000000) - 0x80000000;
4938 HOST_WIDE_INT high
= value
>> 31;
4940 if (high
== 0 || high
== -1)
4946 return num_insns_constant_wide (high
) + 1;
4948 return num_insns_constant_wide (low
) + 1;
4950 return (num_insns_constant_wide (high
)
4951 + num_insns_constant_wide (low
) + 1);
4959 num_insns_constant (rtx op
, enum machine_mode mode
)
4961 HOST_WIDE_INT low
, high
;
4963 switch (GET_CODE (op
))
4966 if ((INTVAL (op
) >> 31) != 0 && (INTVAL (op
) >> 31) != -1
4967 && mask64_operand (op
, mode
))
4970 return num_insns_constant_wide (INTVAL (op
));
4972 case CONST_WIDE_INT
:
4975 int ins
= CONST_WIDE_INT_NUNITS (op
) - 1;
4976 for (i
= 0; i
< CONST_WIDE_INT_NUNITS (op
); i
++)
4977 ins
+= num_insns_constant_wide (CONST_WIDE_INT_ELT (op
, i
));
4982 if (mode
== SFmode
|| mode
== SDmode
)
4987 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
4988 if (DECIMAL_FLOAT_MODE_P (mode
))
4989 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
4991 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
4992 return num_insns_constant_wide ((HOST_WIDE_INT
) l
);
4998 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
4999 if (DECIMAL_FLOAT_MODE_P (mode
))
5000 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, l
);
5002 REAL_VALUE_TO_TARGET_DOUBLE (rv
, l
);
5003 high
= l
[WORDS_BIG_ENDIAN
== 0];
5004 low
= l
[WORDS_BIG_ENDIAN
!= 0];
5007 return (num_insns_constant_wide (low
)
5008 + num_insns_constant_wide (high
));
5011 if ((high
== 0 && low
>= 0)
5012 || (high
== -1 && low
< 0))
5013 return num_insns_constant_wide (low
);
5015 else if (mask64_operand (op
, mode
))
5019 return num_insns_constant_wide (high
) + 1;
5022 return (num_insns_constant_wide (high
)
5023 + num_insns_constant_wide (low
) + 1);
5031 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
5032 If the mode of OP is MODE_VECTOR_INT, this simply returns the
5033 corresponding element of the vector, but for V4SFmode and V2SFmode,
5034 the corresponding "float" is interpreted as an SImode integer. */
5037 const_vector_elt_as_int (rtx op
, unsigned int elt
)
5041 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
5042 gcc_assert (GET_MODE (op
) != V2DImode
5043 && GET_MODE (op
) != V2DFmode
);
5045 tmp
= CONST_VECTOR_ELT (op
, elt
);
5046 if (GET_MODE (op
) == V4SFmode
5047 || GET_MODE (op
) == V2SFmode
)
5048 tmp
= gen_lowpart (SImode
, tmp
);
5049 return INTVAL (tmp
);
5052 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
5053 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
5054 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
5055 all items are set to the same value and contain COPIES replicas of the
5056 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
5057 operand and the others are set to the value of the operand's msb. */
5060 vspltis_constant (rtx op
, unsigned step
, unsigned copies
)
5062 enum machine_mode mode
= GET_MODE (op
);
5063 enum machine_mode inner
= GET_MODE_INNER (mode
);
5071 HOST_WIDE_INT splat_val
;
5072 HOST_WIDE_INT msb_val
;
5074 if (mode
== V2DImode
|| mode
== V2DFmode
|| mode
== V1TImode
)
5077 nunits
= GET_MODE_NUNITS (mode
);
5078 bitsize
= GET_MODE_BITSIZE (inner
);
5079 mask
= GET_MODE_MASK (inner
);
5081 val
= const_vector_elt_as_int (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
5083 msb_val
= val
>= 0 ? 0 : -1;
5085 /* Construct the value to be splatted, if possible. If not, return 0. */
5086 for (i
= 2; i
<= copies
; i
*= 2)
5088 HOST_WIDE_INT small_val
;
5090 small_val
= splat_val
>> bitsize
;
5092 if (splat_val
!= ((small_val
<< bitsize
) | (small_val
& mask
)))
5094 splat_val
= small_val
;
5097 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
5098 if (EASY_VECTOR_15 (splat_val
))
5101 /* Also check if we can splat, and then add the result to itself. Do so if
5102 the value is positive, of if the splat instruction is using OP's mode;
5103 for splat_val < 0, the splat and the add should use the same mode. */
5104 else if (EASY_VECTOR_15_ADD_SELF (splat_val
)
5105 && (splat_val
>= 0 || (step
== 1 && copies
== 1)))
5108 /* Also check if are loading up the most significant bit which can be done by
5109 loading up -1 and shifting the value left by -1. */
5110 else if (EASY_VECTOR_MSB (splat_val
, inner
))
5116 /* Check if VAL is present in every STEP-th element, and the
5117 other elements are filled with its most significant bit. */
5118 for (i
= 1; i
< nunits
; ++i
)
5120 HOST_WIDE_INT desired_val
;
5121 unsigned elt
= BYTES_BIG_ENDIAN
? nunits
- 1 - i
: i
;
5122 if ((i
& (step
- 1)) == 0)
5125 desired_val
= msb_val
;
5127 if (desired_val
!= const_vector_elt_as_int (op
, elt
))
5135 /* Return true if OP is of the given MODE and can be synthesized
5136 with a vspltisb, vspltish or vspltisw. */
5139 easy_altivec_constant (rtx op
, enum machine_mode mode
)
5141 unsigned step
, copies
;
5143 if (mode
== VOIDmode
)
5144 mode
= GET_MODE (op
);
5145 else if (mode
!= GET_MODE (op
))
5148 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
5150 if (mode
== V2DFmode
)
5151 return zero_constant (op
, mode
);
5153 else if (mode
== V2DImode
)
5155 if (GET_CODE (CONST_VECTOR_ELT (op
, 0)) != CONST_INT
5156 || GET_CODE (CONST_VECTOR_ELT (op
, 1)) != CONST_INT
)
5159 if (zero_constant (op
, mode
))
5162 if (INTVAL (CONST_VECTOR_ELT (op
, 0)) == -1
5163 && INTVAL (CONST_VECTOR_ELT (op
, 1)) == -1)
5169 /* V1TImode is a special container for TImode. Ignore for now. */
5170 else if (mode
== V1TImode
)
5173 /* Start with a vspltisw. */
5174 step
= GET_MODE_NUNITS (mode
) / 4;
5177 if (vspltis_constant (op
, step
, copies
))
5180 /* Then try with a vspltish. */
5186 if (vspltis_constant (op
, step
, copies
))
5189 /* And finally a vspltisb. */
5195 if (vspltis_constant (op
, step
, copies
))
5201 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
5202 result is OP. Abort if it is not possible. */
5205 gen_easy_altivec_constant (rtx op
)
5207 enum machine_mode mode
= GET_MODE (op
);
5208 int nunits
= GET_MODE_NUNITS (mode
);
5209 rtx val
= CONST_VECTOR_ELT (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
5210 unsigned step
= nunits
/ 4;
5211 unsigned copies
= 1;
5213 /* Start with a vspltisw. */
5214 if (vspltis_constant (op
, step
, copies
))
5215 return gen_rtx_VEC_DUPLICATE (V4SImode
, gen_lowpart (SImode
, val
));
5217 /* Then try with a vspltish. */
5223 if (vspltis_constant (op
, step
, copies
))
5224 return gen_rtx_VEC_DUPLICATE (V8HImode
, gen_lowpart (HImode
, val
));
5226 /* And finally a vspltisb. */
5232 if (vspltis_constant (op
, step
, copies
))
5233 return gen_rtx_VEC_DUPLICATE (V16QImode
, gen_lowpart (QImode
, val
));
5239 output_vec_const_move (rtx
*operands
)
5242 enum machine_mode mode
;
5247 mode
= GET_MODE (dest
);
5251 if (zero_constant (vec
, mode
))
5252 return "xxlxor %x0,%x0,%x0";
5254 if ((mode
== V2DImode
|| mode
== V1TImode
)
5255 && INTVAL (CONST_VECTOR_ELT (vec
, 0)) == -1
5256 && INTVAL (CONST_VECTOR_ELT (vec
, 1)) == -1)
5257 return "vspltisw %0,-1";
5263 if (zero_constant (vec
, mode
))
5264 return "vxor %0,%0,%0";
5266 splat_vec
= gen_easy_altivec_constant (vec
);
5267 gcc_assert (GET_CODE (splat_vec
) == VEC_DUPLICATE
);
5268 operands
[1] = XEXP (splat_vec
, 0);
5269 if (!EASY_VECTOR_15 (INTVAL (operands
[1])))
5272 switch (GET_MODE (splat_vec
))
5275 return "vspltisw %0,%1";
5278 return "vspltish %0,%1";
5281 return "vspltisb %0,%1";
5288 gcc_assert (TARGET_SPE
);
5290 /* Vector constant 0 is handled as a splitter of V2SI, and in the
5291 pattern of V1DI, V4HI, and V2SF.
5293 FIXME: We should probably return # and add post reload
5294 splitters for these, but this way is so easy ;-). */
5295 cst
= INTVAL (CONST_VECTOR_ELT (vec
, 0));
5296 cst2
= INTVAL (CONST_VECTOR_ELT (vec
, 1));
5297 operands
[1] = CONST_VECTOR_ELT (vec
, 0);
5298 operands
[2] = CONST_VECTOR_ELT (vec
, 1);
5300 return "li %0,%1\n\tevmergelo %0,%0,%0";
5302 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
5305 /* Initialize TARGET of vector PAIRED to VALS. */
5308 paired_expand_vector_init (rtx target
, rtx vals
)
5310 enum machine_mode mode
= GET_MODE (target
);
5311 int n_elts
= GET_MODE_NUNITS (mode
);
5313 rtx x
, new_rtx
, tmp
, constant_op
, op1
, op2
;
5316 for (i
= 0; i
< n_elts
; ++i
)
5318 x
= XVECEXP (vals
, 0, i
);
5319 if (!CONSTANT_P (x
))
5324 /* Load from constant pool. */
5325 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
5331 /* The vector is initialized only with non-constants. */
5332 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, XVECEXP (vals
, 0, 0),
5333 XVECEXP (vals
, 0, 1));
5335 emit_move_insn (target
, new_rtx
);
5339 /* One field is non-constant and the other one is a constant. Load the
5340 constant from the constant pool and use ps_merge instruction to
5341 construct the whole vector. */
5342 op1
= XVECEXP (vals
, 0, 0);
5343 op2
= XVECEXP (vals
, 0, 1);
5345 constant_op
= (CONSTANT_P (op1
)) ? op1
: op2
;
5347 tmp
= gen_reg_rtx (GET_MODE (constant_op
));
5348 emit_move_insn (tmp
, constant_op
);
5350 if (CONSTANT_P (op1
))
5351 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, tmp
, op2
);
5353 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, op1
, tmp
);
5355 emit_move_insn (target
, new_rtx
);
5359 paired_expand_vector_move (rtx operands
[])
5361 rtx op0
= operands
[0], op1
= operands
[1];
5363 emit_move_insn (op0
, op1
);
5366 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
5367 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
5368 operands for the relation operation COND. This is a recursive
5372 paired_emit_vector_compare (enum rtx_code rcode
,
5373 rtx dest
, rtx op0
, rtx op1
,
5374 rtx cc_op0
, rtx cc_op1
)
5376 rtx tmp
= gen_reg_rtx (V2SFmode
);
5379 gcc_assert (TARGET_PAIRED_FLOAT
);
5380 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
5386 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5390 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
5391 emit_insn (gen_selv2sf4 (dest
, tmp
, op0
, op1
, CONST0_RTX (SFmode
)));
5395 paired_emit_vector_compare (GE
, dest
, op0
, op1
, cc_op1
, cc_op0
);
5398 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5401 tmp1
= gen_reg_rtx (V2SFmode
);
5402 max
= gen_reg_rtx (V2SFmode
);
5403 min
= gen_reg_rtx (V2SFmode
);
5404 gen_reg_rtx (V2SFmode
);
5406 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
5407 emit_insn (gen_selv2sf4
5408 (max
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
5409 emit_insn (gen_subv2sf3 (tmp
, cc_op1
, cc_op0
));
5410 emit_insn (gen_selv2sf4
5411 (min
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
5412 emit_insn (gen_subv2sf3 (tmp1
, min
, max
));
5413 emit_insn (gen_selv2sf4 (dest
, tmp1
, op0
, op1
, CONST0_RTX (SFmode
)));
5416 paired_emit_vector_compare (EQ
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5419 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5422 paired_emit_vector_compare (LT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5425 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5428 paired_emit_vector_compare (GT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5437 /* Emit vector conditional expression.
5438 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
5439 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
5442 paired_emit_vector_cond_expr (rtx dest
, rtx op1
, rtx op2
,
5443 rtx cond
, rtx cc_op0
, rtx cc_op1
)
5445 enum rtx_code rcode
= GET_CODE (cond
);
5447 if (!TARGET_PAIRED_FLOAT
)
5450 paired_emit_vector_compare (rcode
, dest
, op1
, op2
, cc_op0
, cc_op1
);
5455 /* Initialize vector TARGET to VALS. */
5458 rs6000_expand_vector_init (rtx target
, rtx vals
)
5460 enum machine_mode mode
= GET_MODE (target
);
5461 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
5462 int n_elts
= GET_MODE_NUNITS (mode
);
5463 int n_var
= 0, one_var
= -1;
5464 bool all_same
= true, all_const_zero
= true;
5468 for (i
= 0; i
< n_elts
; ++i
)
5470 x
= XVECEXP (vals
, 0, i
);
5471 if (!CONSTANT_P (x
))
5472 ++n_var
, one_var
= i
;
5473 else if (x
!= CONST0_RTX (inner_mode
))
5474 all_const_zero
= false;
5476 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
5482 rtx const_vec
= gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0));
5483 bool int_vector_p
= (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
);
5484 if ((int_vector_p
|| TARGET_VSX
) && all_const_zero
)
5486 /* Zero register. */
5487 emit_insn (gen_rtx_SET (VOIDmode
, target
,
5488 gen_rtx_XOR (mode
, target
, target
)));
5491 else if (int_vector_p
&& easy_vector_constant (const_vec
, mode
))
5493 /* Splat immediate. */
5494 emit_insn (gen_rtx_SET (VOIDmode
, target
, const_vec
));
5499 /* Load from constant pool. */
5500 emit_move_insn (target
, const_vec
);
5505 /* Double word values on VSX can use xxpermdi or lxvdsx. */
5506 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
5508 rtx op0
= XVECEXP (vals
, 0, 0);
5509 rtx op1
= XVECEXP (vals
, 0, 1);
5512 if (!MEM_P (op0
) && !REG_P (op0
))
5513 op0
= force_reg (inner_mode
, op0
);
5514 if (mode
== V2DFmode
)
5515 emit_insn (gen_vsx_splat_v2df (target
, op0
));
5517 emit_insn (gen_vsx_splat_v2di (target
, op0
));
5521 op0
= force_reg (inner_mode
, op0
);
5522 op1
= force_reg (inner_mode
, op1
);
5523 if (mode
== V2DFmode
)
5524 emit_insn (gen_vsx_concat_v2df (target
, op0
, op1
));
5526 emit_insn (gen_vsx_concat_v2di (target
, op0
, op1
));
5531 /* With single precision floating point on VSX, know that internally single
5532 precision is actually represented as a double, and either make 2 V2DF
5533 vectors, and convert these vectors to single precision, or do one
5534 conversion, and splat the result to the other elements. */
5535 if (mode
== V4SFmode
&& VECTOR_MEM_VSX_P (mode
))
5539 rtx freg
= gen_reg_rtx (V4SFmode
);
5540 rtx sreg
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
5541 rtx cvt
= ((TARGET_XSCVDPSPN
)
5542 ? gen_vsx_xscvdpspn_scalar (freg
, sreg
)
5543 : gen_vsx_xscvdpsp_scalar (freg
, sreg
));
5546 emit_insn (gen_vsx_xxspltw_v4sf_direct (target
, freg
, const0_rtx
));
5550 rtx dbl_even
= gen_reg_rtx (V2DFmode
);
5551 rtx dbl_odd
= gen_reg_rtx (V2DFmode
);
5552 rtx flt_even
= gen_reg_rtx (V4SFmode
);
5553 rtx flt_odd
= gen_reg_rtx (V4SFmode
);
5554 rtx op0
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
5555 rtx op1
= force_reg (SFmode
, XVECEXP (vals
, 0, 1));
5556 rtx op2
= force_reg (SFmode
, XVECEXP (vals
, 0, 2));
5557 rtx op3
= force_reg (SFmode
, XVECEXP (vals
, 0, 3));
5559 emit_insn (gen_vsx_concat_v2sf (dbl_even
, op0
, op1
));
5560 emit_insn (gen_vsx_concat_v2sf (dbl_odd
, op2
, op3
));
5561 emit_insn (gen_vsx_xvcvdpsp (flt_even
, dbl_even
));
5562 emit_insn (gen_vsx_xvcvdpsp (flt_odd
, dbl_odd
));
5563 rs6000_expand_extract_even (target
, flt_even
, flt_odd
);
5568 /* Store value to stack temp. Load vector element. Splat. However, splat
5569 of 64-bit items is not supported on Altivec. */
5570 if (all_same
&& GET_MODE_SIZE (inner_mode
) <= 4)
5572 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
5573 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0),
5574 XVECEXP (vals
, 0, 0));
5575 x
= gen_rtx_UNSPEC (VOIDmode
,
5576 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
5577 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
5579 gen_rtx_SET (VOIDmode
,
5582 x
= gen_rtx_VEC_SELECT (inner_mode
, target
,
5583 gen_rtx_PARALLEL (VOIDmode
,
5584 gen_rtvec (1, const0_rtx
)));
5585 emit_insn (gen_rtx_SET (VOIDmode
, target
,
5586 gen_rtx_VEC_DUPLICATE (mode
, x
)));
5590 /* One field is non-constant. Load constant then overwrite
5594 rtx copy
= copy_rtx (vals
);
5596 /* Load constant part of vector, substitute neighboring value for
5598 XVECEXP (copy
, 0, one_var
) = XVECEXP (vals
, 0, (one_var
+ 1) % n_elts
);
5599 rs6000_expand_vector_init (target
, copy
);
5601 /* Insert variable. */
5602 rs6000_expand_vector_set (target
, XVECEXP (vals
, 0, one_var
), one_var
);
5606 /* Construct the vector in memory one field at a time
5607 and load the whole vector. */
5608 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
5609 for (i
= 0; i
< n_elts
; i
++)
5610 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
5611 i
* GET_MODE_SIZE (inner_mode
)),
5612 XVECEXP (vals
, 0, i
));
5613 emit_move_insn (target
, mem
);
5616 /* Set field ELT of TARGET to VAL. */
5619 rs6000_expand_vector_set (rtx target
, rtx val
, int elt
)
5621 enum machine_mode mode
= GET_MODE (target
);
5622 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
5623 rtx reg
= gen_reg_rtx (mode
);
5625 int width
= GET_MODE_SIZE (inner_mode
);
5628 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
5630 rtx (*set_func
) (rtx
, rtx
, rtx
, rtx
)
5631 = ((mode
== V2DFmode
) ? gen_vsx_set_v2df
: gen_vsx_set_v2di
);
5632 emit_insn (set_func (target
, target
, val
, GEN_INT (elt
)));
5636 /* Simplify setting single element vectors like V1TImode. */
5637 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE (inner_mode
) && elt
== 0)
5639 emit_move_insn (target
, gen_lowpart (mode
, val
));
5643 /* Load single variable value. */
5644 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
5645 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0), val
);
5646 x
= gen_rtx_UNSPEC (VOIDmode
,
5647 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
5648 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
5650 gen_rtx_SET (VOIDmode
,
5654 /* Linear sequence. */
5655 mask
= gen_rtx_PARALLEL (V16QImode
, rtvec_alloc (16));
5656 for (i
= 0; i
< 16; ++i
)
5657 XVECEXP (mask
, 0, i
) = GEN_INT (i
);
5659 /* Set permute mask to insert element into target. */
5660 for (i
= 0; i
< width
; ++i
)
5661 XVECEXP (mask
, 0, elt
*width
+ i
)
5662 = GEN_INT (i
+ 0x10);
5663 x
= gen_rtx_CONST_VECTOR (V16QImode
, XVEC (mask
, 0));
5665 if (BYTES_BIG_ENDIAN
)
5666 x
= gen_rtx_UNSPEC (mode
,
5667 gen_rtvec (3, target
, reg
,
5668 force_reg (V16QImode
, x
)),
5672 /* Invert selector. We prefer to generate VNAND on P8 so
5673 that future fusion opportunities can kick in, but must
5674 generate VNOR elsewhere. */
5675 rtx notx
= gen_rtx_NOT (V16QImode
, force_reg (V16QImode
, x
));
5676 rtx iorx
= (TARGET_P8_VECTOR
5677 ? gen_rtx_IOR (V16QImode
, notx
, notx
)
5678 : gen_rtx_AND (V16QImode
, notx
, notx
));
5679 rtx tmp
= gen_reg_rtx (V16QImode
);
5680 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, iorx
));
5682 /* Permute with operands reversed and adjusted selector. */
5683 x
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, reg
, target
, tmp
),
5687 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
5690 /* Extract field ELT from VEC into TARGET. */
5693 rs6000_expand_vector_extract (rtx target
, rtx vec
, int elt
)
5695 enum machine_mode mode
= GET_MODE (vec
);
5696 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
5699 if (VECTOR_MEM_VSX_P (mode
))
5706 gcc_assert (elt
== 0 && inner_mode
== TImode
);
5707 emit_move_insn (target
, gen_lowpart (TImode
, vec
));
5710 emit_insn (gen_vsx_extract_v2df (target
, vec
, GEN_INT (elt
)));
5713 emit_insn (gen_vsx_extract_v2di (target
, vec
, GEN_INT (elt
)));
5716 emit_insn (gen_vsx_extract_v4sf (target
, vec
, GEN_INT (elt
)));
5721 /* Allocate mode-sized buffer. */
5722 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
5724 emit_move_insn (mem
, vec
);
5726 /* Add offset to field within buffer matching vector element. */
5727 mem
= adjust_address_nv (mem
, inner_mode
, elt
* GET_MODE_SIZE (inner_mode
));
5729 emit_move_insn (target
, adjust_address_nv (mem
, inner_mode
, 0));
5732 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
5733 implement ANDing by the mask IN. */
5735 build_mask64_2_operands (rtx in
, rtx
*out
)
5737 unsigned HOST_WIDE_INT c
, lsb
, m1
, m2
;
5740 gcc_assert (GET_CODE (in
) == CONST_INT
);
5745 /* Assume c initially something like 0x00fff000000fffff. The idea
5746 is to rotate the word so that the middle ^^^^^^ group of zeros
5747 is at the MS end and can be cleared with an rldicl mask. We then
5748 rotate back and clear off the MS ^^ group of zeros with a
5750 c
= ~c
; /* c == 0xff000ffffff00000 */
5751 lsb
= c
& -c
; /* lsb == 0x0000000000100000 */
5752 m1
= -lsb
; /* m1 == 0xfffffffffff00000 */
5753 c
= ~c
; /* c == 0x00fff000000fffff */
5754 c
&= -lsb
; /* c == 0x00fff00000000000 */
5755 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
5756 c
= ~c
; /* c == 0xff000fffffffffff */
5757 c
&= -lsb
; /* c == 0xff00000000000000 */
5759 while ((lsb
>>= 1) != 0)
5760 shift
++; /* shift == 44 on exit from loop */
5761 m1
<<= 64 - shift
; /* m1 == 0xffffff0000000000 */
5762 m1
= ~m1
; /* m1 == 0x000000ffffffffff */
5763 m2
= ~c
; /* m2 == 0x00ffffffffffffff */
5767 /* Assume c initially something like 0xff000f0000000000. The idea
5768 is to rotate the word so that the ^^^ middle group of zeros
5769 is at the LS end and can be cleared with an rldicr mask. We then
5770 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
5772 lsb
= c
& -c
; /* lsb == 0x0000010000000000 */
5773 m2
= -lsb
; /* m2 == 0xffffff0000000000 */
5774 c
= ~c
; /* c == 0x00fff0ffffffffff */
5775 c
&= -lsb
; /* c == 0x00fff00000000000 */
5776 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
5777 c
= ~c
; /* c == 0xff000fffffffffff */
5778 c
&= -lsb
; /* c == 0xff00000000000000 */
5780 while ((lsb
>>= 1) != 0)
5781 shift
++; /* shift == 44 on exit from loop */
5782 m1
= ~c
; /* m1 == 0x00ffffffffffffff */
5783 m1
>>= shift
; /* m1 == 0x0000000000000fff */
5784 m1
= ~m1
; /* m1 == 0xfffffffffffff000 */
5787 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
5788 masks will be all 1's. We are guaranteed more than one transition. */
5789 out
[0] = GEN_INT (64 - shift
);
5790 out
[1] = GEN_INT (m1
);
5791 out
[2] = GEN_INT (shift
);
5792 out
[3] = GEN_INT (m2
);
5795 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
5798 invalid_e500_subreg (rtx op
, enum machine_mode mode
)
5800 if (TARGET_E500_DOUBLE
)
5802 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
5803 subreg:TI and reg:TF. Decimal float modes are like integer
5804 modes (only low part of each register used) for this
5806 if (GET_CODE (op
) == SUBREG
5807 && (mode
== SImode
|| mode
== DImode
|| mode
== TImode
5808 || mode
== DDmode
|| mode
== TDmode
|| mode
== PTImode
)
5809 && REG_P (SUBREG_REG (op
))
5810 && (GET_MODE (SUBREG_REG (op
)) == DFmode
5811 || GET_MODE (SUBREG_REG (op
)) == TFmode
))
5814 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
5816 if (GET_CODE (op
) == SUBREG
5817 && (mode
== DFmode
|| mode
== TFmode
)
5818 && REG_P (SUBREG_REG (op
))
5819 && (GET_MODE (SUBREG_REG (op
)) == DImode
5820 || GET_MODE (SUBREG_REG (op
)) == TImode
5821 || GET_MODE (SUBREG_REG (op
)) == PTImode
5822 || GET_MODE (SUBREG_REG (op
)) == DDmode
5823 || GET_MODE (SUBREG_REG (op
)) == TDmode
))
5828 && GET_CODE (op
) == SUBREG
5830 && REG_P (SUBREG_REG (op
))
5831 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op
))))
5837 /* Return alignment of TYPE. Existing alignment is ALIGN. HOW
5838 selects whether the alignment is abi mandated, optional, or
5839 both abi and optional alignment. */
5842 rs6000_data_alignment (tree type
, unsigned int align
, enum data_align how
)
5844 if (how
!= align_opt
)
5846 if (TREE_CODE (type
) == VECTOR_TYPE
)
5848 if ((TARGET_SPE
&& SPE_VECTOR_MODE (TYPE_MODE (type
)))
5849 || (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (TYPE_MODE (type
))))
5854 else if (align
< 128)
5857 else if (TARGET_E500_DOUBLE
5858 && TREE_CODE (type
) == REAL_TYPE
5859 && TYPE_MODE (type
) == DFmode
)
5866 if (how
!= align_abi
)
5868 if (TREE_CODE (type
) == ARRAY_TYPE
5869 && TYPE_MODE (TREE_TYPE (type
)) == QImode
)
5871 if (align
< BITS_PER_WORD
)
5872 align
= BITS_PER_WORD
;
5879 /* AIX increases natural record alignment to doubleword if the first
5880 field is an FP double while the FP fields remain word aligned. */
5883 rs6000_special_round_type_align (tree type
, unsigned int computed
,
5884 unsigned int specified
)
5886 unsigned int align
= MAX (computed
, specified
);
5887 tree field
= TYPE_FIELDS (type
);
5889 /* Skip all non field decls */
5890 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
5891 field
= DECL_CHAIN (field
);
5893 if (field
!= NULL
&& field
!= type
)
5895 type
= TREE_TYPE (field
);
5896 while (TREE_CODE (type
) == ARRAY_TYPE
)
5897 type
= TREE_TYPE (type
);
5899 if (type
!= error_mark_node
&& TYPE_MODE (type
) == DFmode
)
5900 align
= MAX (align
, 64);
5906 /* Darwin increases record alignment to the natural alignment of
5910 darwin_rs6000_special_round_type_align (tree type
, unsigned int computed
,
5911 unsigned int specified
)
5913 unsigned int align
= MAX (computed
, specified
);
5915 if (TYPE_PACKED (type
))
5918 /* Find the first field, looking down into aggregates. */
5920 tree field
= TYPE_FIELDS (type
);
5921 /* Skip all non field decls */
5922 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
5923 field
= DECL_CHAIN (field
);
5926 /* A packed field does not contribute any extra alignment. */
5927 if (DECL_PACKED (field
))
5929 type
= TREE_TYPE (field
);
5930 while (TREE_CODE (type
) == ARRAY_TYPE
)
5931 type
= TREE_TYPE (type
);
5932 } while (AGGREGATE_TYPE_P (type
));
5934 if (! AGGREGATE_TYPE_P (type
) && type
!= error_mark_node
)
5935 align
= MAX (align
, TYPE_ALIGN (type
));
5940 /* Return 1 for an operand in small memory on V.4/eabi. */
5943 small_data_operand (rtx op ATTRIBUTE_UNUSED
,
5944 enum machine_mode mode ATTRIBUTE_UNUSED
)
5949 if (rs6000_sdata
== SDATA_NONE
|| rs6000_sdata
== SDATA_DATA
)
5952 if (DEFAULT_ABI
!= ABI_V4
)
5955 /* Vector and float memory instructions have a limited offset on the
5956 SPE, so using a vector or float variable directly as an operand is
5959 && (SPE_VECTOR_MODE (mode
) || FLOAT_MODE_P (mode
)))
5962 if (GET_CODE (op
) == SYMBOL_REF
)
5965 else if (GET_CODE (op
) != CONST
5966 || GET_CODE (XEXP (op
, 0)) != PLUS
5967 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
5968 || GET_CODE (XEXP (XEXP (op
, 0), 1)) != CONST_INT
)
5973 rtx sum
= XEXP (op
, 0);
5974 HOST_WIDE_INT summand
;
5976 /* We have to be careful here, because it is the referenced address
5977 that must be 32k from _SDA_BASE_, not just the symbol. */
5978 summand
= INTVAL (XEXP (sum
, 1));
5979 if (summand
< 0 || summand
> g_switch_value
)
5982 sym_ref
= XEXP (sum
, 0);
5985 return SYMBOL_REF_SMALL_P (sym_ref
);
5991 /* Return true if either operand is a general purpose register. */
5994 gpr_or_gpr_p (rtx op0
, rtx op1
)
5996 return ((REG_P (op0
) && INT_REGNO_P (REGNO (op0
)))
5997 || (REG_P (op1
) && INT_REGNO_P (REGNO (op1
))));
6000 /* Return true if this is a move direct operation between GPR registers and
6001 floating point/VSX registers. */
6004 direct_move_p (rtx op0
, rtx op1
)
6008 if (!REG_P (op0
) || !REG_P (op1
))
6011 if (!TARGET_DIRECT_MOVE
&& !TARGET_MFPGPR
)
6014 regno0
= REGNO (op0
);
6015 regno1
= REGNO (op1
);
6016 if (regno0
>= FIRST_PSEUDO_REGISTER
|| regno1
>= FIRST_PSEUDO_REGISTER
)
6019 if (INT_REGNO_P (regno0
))
6020 return (TARGET_DIRECT_MOVE
) ? VSX_REGNO_P (regno1
) : FP_REGNO_P (regno1
);
6022 else if (INT_REGNO_P (regno1
))
6024 if (TARGET_MFPGPR
&& FP_REGNO_P (regno0
))
6027 else if (TARGET_DIRECT_MOVE
&& VSX_REGNO_P (regno0
))
6034 /* Return true if this is a load or store quad operation. This function does
6035 not handle the atomic quad memory instructions. */
6038 quad_load_store_p (rtx op0
, rtx op1
)
6042 if (!TARGET_QUAD_MEMORY
)
6045 else if (REG_P (op0
) && MEM_P (op1
))
6046 ret
= (quad_int_reg_operand (op0
, GET_MODE (op0
))
6047 && quad_memory_operand (op1
, GET_MODE (op1
))
6048 && !reg_overlap_mentioned_p (op0
, op1
));
6050 else if (MEM_P (op0
) && REG_P (op1
))
6051 ret
= (quad_memory_operand (op0
, GET_MODE (op0
))
6052 && quad_int_reg_operand (op1
, GET_MODE (op1
)));
6057 if (TARGET_DEBUG_ADDR
)
6059 fprintf (stderr
, "\n========== quad_load_store, return %s\n",
6060 ret
? "true" : "false");
6061 debug_rtx (gen_rtx_SET (VOIDmode
, op0
, op1
));
6067 /* Given an address, return a constant offset term if one exists. */
6070 address_offset (rtx op
)
6072 if (GET_CODE (op
) == PRE_INC
6073 || GET_CODE (op
) == PRE_DEC
)
6075 else if (GET_CODE (op
) == PRE_MODIFY
6076 || GET_CODE (op
) == LO_SUM
)
6079 if (GET_CODE (op
) == CONST
)
6082 if (GET_CODE (op
) == PLUS
)
6085 if (CONST_INT_P (op
))
6091 /* Return true if the MEM operand is a memory operand suitable for use
6092 with a (full width, possibly multiple) gpr load/store. On
6093 powerpc64 this means the offset must be divisible by 4.
6094 Implements 'Y' constraint.
6096 Accept direct, indexed, offset, lo_sum and tocref. Since this is
6097 a constraint function we know the operand has satisfied a suitable
6098 memory predicate. Also accept some odd rtl generated by reload
6099 (see rs6000_legitimize_reload_address for various forms). It is
6100 important that reload rtl be accepted by appropriate constraints
6101 but not by the operand predicate.
6103 Offsetting a lo_sum should not be allowed, except where we know by
6104 alignment that a 32k boundary is not crossed, but see the ???
6105 comment in rs6000_legitimize_reload_address. Note that by
6106 "offsetting" here we mean a further offset to access parts of the
6107 MEM. It's fine to have a lo_sum where the inner address is offset
6108 from a sym, since the same sym+offset will appear in the high part
6109 of the address calculation. */
6112 mem_operand_gpr (rtx op
, enum machine_mode mode
)
6114 unsigned HOST_WIDE_INT offset
;
6116 rtx addr
= XEXP (op
, 0);
6118 op
= address_offset (addr
);
6122 offset
= INTVAL (op
);
6123 if (TARGET_POWERPC64
&& (offset
& 3) != 0)
6126 extra
= GET_MODE_SIZE (mode
) - UNITS_PER_WORD
;
6127 gcc_assert (extra
>= 0);
6129 if (GET_CODE (addr
) == LO_SUM
)
6130 /* For lo_sum addresses, we must allow any offset except one that
6131 causes a wrap, so test only the low 16 bits. */
6132 offset
= ((offset
& 0xffff) ^ 0x8000) - 0x8000;
6134 return offset
+ 0x8000 < 0x10000u
- extra
;
6137 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
6140 reg_offset_addressing_ok_p (enum machine_mode mode
)
6152 /* AltiVec/VSX vector modes. Only reg+reg addressing is valid. While
6153 TImode is not a vector mode, if we want to use the VSX registers to
6154 move it around, we need to restrict ourselves to reg+reg
6156 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
6164 /* Paired vector modes. Only reg+reg addressing is valid. */
6165 if (TARGET_PAIRED_FLOAT
)
6170 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
6171 addressing for the LFIWZX and STFIWX instructions. */
6172 if (TARGET_NO_SDMODE_STACK
)
6184 virtual_stack_registers_memory_p (rtx op
)
6188 if (GET_CODE (op
) == REG
)
6189 regnum
= REGNO (op
);
6191 else if (GET_CODE (op
) == PLUS
6192 && GET_CODE (XEXP (op
, 0)) == REG
6193 && GET_CODE (XEXP (op
, 1)) == CONST_INT
)
6194 regnum
= REGNO (XEXP (op
, 0));
6199 return (regnum
>= FIRST_VIRTUAL_REGISTER
6200 && regnum
<= LAST_VIRTUAL_POINTER_REGISTER
);
6203 /* Return true if a MODE sized memory accesses to OP plus OFFSET
6204 is known to not straddle a 32k boundary. */
6207 offsettable_ok_by_alignment (rtx op
, HOST_WIDE_INT offset
,
6208 enum machine_mode mode
)
6211 unsigned HOST_WIDE_INT dsize
, dalign
, lsb
, mask
;
6213 if (GET_CODE (op
) != SYMBOL_REF
)
6216 dsize
= GET_MODE_SIZE (mode
);
6217 decl
= SYMBOL_REF_DECL (op
);
6223 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
6224 replacing memory addresses with an anchor plus offset. We
6225 could find the decl by rummaging around in the block->objects
6226 VEC for the given offset but that seems like too much work. */
6227 dalign
= BITS_PER_UNIT
;
6228 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op
)
6229 && SYMBOL_REF_ANCHOR_P (op
)
6230 && SYMBOL_REF_BLOCK (op
) != NULL
)
6232 struct object_block
*block
= SYMBOL_REF_BLOCK (op
);
6234 dalign
= block
->alignment
;
6235 offset
+= SYMBOL_REF_BLOCK_OFFSET (op
);
6237 else if (CONSTANT_POOL_ADDRESS_P (op
))
6239 /* It would be nice to have get_pool_align().. */
6240 enum machine_mode cmode
= get_pool_mode (op
);
6242 dalign
= GET_MODE_ALIGNMENT (cmode
);
6245 else if (DECL_P (decl
))
6247 dalign
= DECL_ALIGN (decl
);
6251 /* Allow BLKmode when the entire object is known to not
6252 cross a 32k boundary. */
6253 if (!DECL_SIZE_UNIT (decl
))
6256 if (!tree_fits_uhwi_p (DECL_SIZE_UNIT (decl
)))
6259 dsize
= tree_to_uhwi (DECL_SIZE_UNIT (decl
));
6263 return dalign
/ BITS_PER_UNIT
>= dsize
;
6268 type
= TREE_TYPE (decl
);
6270 dalign
= TYPE_ALIGN (type
);
6271 if (CONSTANT_CLASS_P (decl
))
6272 dalign
= CONSTANT_ALIGNMENT (decl
, dalign
);
6274 dalign
= DATA_ALIGNMENT (decl
, dalign
);
6278 /* BLKmode, check the entire object. */
6279 if (TREE_CODE (decl
) == STRING_CST
)
6280 dsize
= TREE_STRING_LENGTH (decl
);
6281 else if (TYPE_SIZE_UNIT (type
)
6282 && tree_fits_uhwi_p (TYPE_SIZE_UNIT (type
)))
6283 dsize
= tree_to_uhwi (TYPE_SIZE_UNIT (type
));
6289 return dalign
/ BITS_PER_UNIT
>= dsize
;
6293 /* Find how many bits of the alignment we know for this access. */
6294 mask
= dalign
/ BITS_PER_UNIT
- 1;
6295 lsb
= offset
& -offset
;
6299 return dalign
>= dsize
;
6303 constant_pool_expr_p (rtx op
)
6307 split_const (op
, &base
, &offset
);
6308 return (GET_CODE (base
) == SYMBOL_REF
6309 && CONSTANT_POOL_ADDRESS_P (base
)
6310 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base
), Pmode
));
6313 static const_rtx tocrel_base
, tocrel_offset
;
6315 /* Return true if OP is a toc pointer relative address (the output
6316 of create_TOC_reference). If STRICT, do not match high part or
6317 non-split -mcmodel=large/medium toc pointer relative addresses. */
6320 toc_relative_expr_p (const_rtx op
, bool strict
)
6325 if (TARGET_CMODEL
!= CMODEL_SMALL
)
6327 /* Only match the low part. */
6328 if (GET_CODE (op
) == LO_SUM
6329 && REG_P (XEXP (op
, 0))
6330 && INT_REG_OK_FOR_BASE_P (XEXP (op
, 0), strict
))
6337 tocrel_offset
= const0_rtx
;
6338 if (GET_CODE (op
) == PLUS
&& add_cint_operand (XEXP (op
, 1), GET_MODE (op
)))
6340 tocrel_base
= XEXP (op
, 0);
6341 tocrel_offset
= XEXP (op
, 1);
6344 return (GET_CODE (tocrel_base
) == UNSPEC
6345 && XINT (tocrel_base
, 1) == UNSPEC_TOCREL
);
6348 /* Return true if X is a constant pool address, and also for cmodel=medium
6349 if X is a toc-relative address known to be offsettable within MODE. */
6352 legitimate_constant_pool_address_p (const_rtx x
, enum machine_mode mode
,
6355 return (toc_relative_expr_p (x
, strict
)
6356 && (TARGET_CMODEL
!= CMODEL_MEDIUM
6357 || constant_pool_expr_p (XVECEXP (tocrel_base
, 0, 0))
6359 || offsettable_ok_by_alignment (XVECEXP (tocrel_base
, 0, 0),
6360 INTVAL (tocrel_offset
), mode
)));
6364 legitimate_small_data_p (enum machine_mode mode
, rtx x
)
6366 return (DEFAULT_ABI
== ABI_V4
6367 && !flag_pic
&& !TARGET_TOC
6368 && (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
)
6369 && small_data_operand (x
, mode
));
6372 /* SPE offset addressing is limited to 5-bits worth of double words. */
6373 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
6376 rs6000_legitimate_offset_address_p (enum machine_mode mode
, rtx x
,
6377 bool strict
, bool worst_case
)
6379 unsigned HOST_WIDE_INT offset
;
6382 if (GET_CODE (x
) != PLUS
)
6384 if (!REG_P (XEXP (x
, 0)))
6386 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
6388 if (!reg_offset_addressing_ok_p (mode
))
6389 return virtual_stack_registers_memory_p (x
);
6390 if (legitimate_constant_pool_address_p (x
, mode
, strict
|| lra_in_progress
))
6392 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6395 offset
= INTVAL (XEXP (x
, 1));
6403 /* SPE vector modes. */
6404 return SPE_CONST_OFFSET_OK (offset
);
6409 /* On e500v2, we may have:
6411 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
6413 Which gets addressed with evldd instructions. */
6414 if (TARGET_E500_DOUBLE
)
6415 return SPE_CONST_OFFSET_OK (offset
);
6417 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
6419 if (VECTOR_MEM_VSX_P (mode
))
6424 if (!TARGET_POWERPC64
)
6426 else if (offset
& 3)
6431 if (TARGET_E500_DOUBLE
)
6432 return (SPE_CONST_OFFSET_OK (offset
)
6433 && SPE_CONST_OFFSET_OK (offset
+ 8));
6442 if (!TARGET_POWERPC64
)
6444 else if (offset
& 3)
6453 return offset
< 0x10000 - extra
;
6457 legitimate_indexed_address_p (rtx x
, int strict
)
6461 if (GET_CODE (x
) != PLUS
)
6467 /* Recognize the rtl generated by reload which we know will later be
6468 replaced with proper base and index regs. */
6470 && reload_in_progress
6471 && (REG_P (op0
) || GET_CODE (op0
) == PLUS
)
6475 return (REG_P (op0
) && REG_P (op1
)
6476 && ((INT_REG_OK_FOR_BASE_P (op0
, strict
)
6477 && INT_REG_OK_FOR_INDEX_P (op1
, strict
))
6478 || (INT_REG_OK_FOR_BASE_P (op1
, strict
)
6479 && INT_REG_OK_FOR_INDEX_P (op0
, strict
))));
6483 avoiding_indexed_address_p (enum machine_mode mode
)
6485 /* Avoid indexed addressing for modes that have non-indexed
6486 load/store instruction forms. */
6487 return (TARGET_AVOID_XFORM
&& VECTOR_MEM_NONE_P (mode
));
6491 legitimate_indirect_address_p (rtx x
, int strict
)
6493 return GET_CODE (x
) == REG
&& INT_REG_OK_FOR_BASE_P (x
, strict
);
6497 macho_lo_sum_memory_operand (rtx x
, enum machine_mode mode
)
6499 if (!TARGET_MACHO
|| !flag_pic
6500 || mode
!= SImode
|| GET_CODE (x
) != MEM
)
6504 if (GET_CODE (x
) != LO_SUM
)
6506 if (GET_CODE (XEXP (x
, 0)) != REG
)
6508 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 0))
6512 return CONSTANT_P (x
);
6516 legitimate_lo_sum_address_p (enum machine_mode mode
, rtx x
, int strict
)
6518 if (GET_CODE (x
) != LO_SUM
)
6520 if (GET_CODE (XEXP (x
, 0)) != REG
)
6522 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
6524 /* Restrict addressing for DI because of our SUBREG hackery. */
6525 if (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
6529 if (TARGET_ELF
|| TARGET_MACHO
)
6533 if (DEFAULT_ABI
== ABI_V4
&& flag_pic
)
6535 /* LRA don't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls
6536 push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
6537 recognizes some LO_SUM addresses as valid although this
6538 function says opposite. In most cases, LRA through different
6539 transformations can generate correct code for address reloads.
6540 It can not manage only some LO_SUM cases. So we need to add
6541 code analogous to one in rs6000_legitimize_reload_address for
6542 LOW_SUM here saying that some addresses are still valid. */
6543 large_toc_ok
= (lra_in_progress
&& TARGET_CMODEL
!= CMODEL_SMALL
6544 && small_toc_ref (x
, VOIDmode
));
6545 if (TARGET_TOC
&& ! large_toc_ok
)
6547 if (GET_MODE_NUNITS (mode
) != 1)
6549 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
6550 && !(/* ??? Assume floating point reg based on mode? */
6551 TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
6552 && (mode
== DFmode
|| mode
== DDmode
)))
6555 return CONSTANT_P (x
) || large_toc_ok
;
6562 /* Try machine-dependent ways of modifying an illegitimate address
6563 to be legitimate. If we find one, return the new, valid address.
6564 This is used from only one place: `memory_address' in explow.c.
6566 OLDX is the address as it was before break_out_memory_refs was
6567 called. In some cases it is useful to look at this to decide what
6570 It is always safe for this function to do nothing. It exists to
6571 recognize opportunities to optimize the output.
6573 On RS/6000, first check for the sum of a register with a constant
6574 integer that is out of range. If so, generate code to add the
6575 constant with the low-order 16 bits masked to the register and force
6576 this result into another register (this can be done with `cau').
6577 Then generate an address of REG+(CONST&0xffff), allowing for the
6578 possibility of bit 16 being a one.
6580 Then check for the sum of a register and something not constant, try to
6581 load the other things into a register and return the sum. */
6584 rs6000_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
6585 enum machine_mode mode
)
6589 if (!reg_offset_addressing_ok_p (mode
))
6591 if (virtual_stack_registers_memory_p (x
))
6594 /* In theory we should not be seeing addresses of the form reg+0,
6595 but just in case it is generated, optimize it away. */
6596 if (GET_CODE (x
) == PLUS
&& XEXP (x
, 1) == const0_rtx
)
6597 return force_reg (Pmode
, XEXP (x
, 0));
6599 /* For TImode with load/store quad, restrict addresses to just a single
6600 pointer, so it works with both GPRs and VSX registers. */
6601 /* Make sure both operands are registers. */
6602 else if (GET_CODE (x
) == PLUS
6603 && (mode
!= TImode
|| !TARGET_QUAD_MEMORY
))
6604 return gen_rtx_PLUS (Pmode
,
6605 force_reg (Pmode
, XEXP (x
, 0)),
6606 force_reg (Pmode
, XEXP (x
, 1)));
6608 return force_reg (Pmode
, x
);
6610 if (GET_CODE (x
) == SYMBOL_REF
)
6612 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
6614 return rs6000_legitimize_tls_address (x
, model
);
6624 /* As in legitimate_offset_address_p we do not assume
6625 worst-case. The mode here is just a hint as to the registers
6626 used. A TImode is usually in gprs, but may actually be in
6627 fprs. Leave worst-case scenario for reload to handle via
6628 insn constraints. PTImode is only GPRs. */
6635 if (GET_CODE (x
) == PLUS
6636 && GET_CODE (XEXP (x
, 0)) == REG
6637 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6638 && ((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 1)) + 0x8000)
6640 && !(SPE_VECTOR_MODE (mode
)
6641 || (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)))
6643 HOST_WIDE_INT high_int
, low_int
;
6645 low_int
= ((INTVAL (XEXP (x
, 1)) & 0xffff) ^ 0x8000) - 0x8000;
6646 if (low_int
>= 0x8000 - extra
)
6648 high_int
= INTVAL (XEXP (x
, 1)) - low_int
;
6649 sum
= force_operand (gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
6650 GEN_INT (high_int
)), 0);
6651 return plus_constant (Pmode
, sum
, low_int
);
6653 else if (GET_CODE (x
) == PLUS
6654 && GET_CODE (XEXP (x
, 0)) == REG
6655 && GET_CODE (XEXP (x
, 1)) != CONST_INT
6656 && GET_MODE_NUNITS (mode
) == 1
6657 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
6658 || (/* ??? Assume floating point reg based on mode? */
6659 (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
6660 && (mode
== DFmode
|| mode
== DDmode
)))
6661 && !avoiding_indexed_address_p (mode
))
6663 return gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
6664 force_reg (Pmode
, force_operand (XEXP (x
, 1), 0)));
6666 else if (SPE_VECTOR_MODE (mode
)
6667 || (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
))
6671 /* We accept [reg + reg] and [reg + OFFSET]. */
6673 if (GET_CODE (x
) == PLUS
)
6675 rtx op1
= XEXP (x
, 0);
6676 rtx op2
= XEXP (x
, 1);
6679 op1
= force_reg (Pmode
, op1
);
6681 if (GET_CODE (op2
) != REG
6682 && (GET_CODE (op2
) != CONST_INT
6683 || !SPE_CONST_OFFSET_OK (INTVAL (op2
))
6684 || (GET_MODE_SIZE (mode
) > 8
6685 && !SPE_CONST_OFFSET_OK (INTVAL (op2
) + 8))))
6686 op2
= force_reg (Pmode
, op2
);
6688 /* We can't always do [reg + reg] for these, because [reg +
6689 reg + offset] is not a legitimate addressing mode. */
6690 y
= gen_rtx_PLUS (Pmode
, op1
, op2
);
6692 if ((GET_MODE_SIZE (mode
) > 8 || mode
== DDmode
) && REG_P (op2
))
6693 return force_reg (Pmode
, y
);
6698 return force_reg (Pmode
, x
);
6700 else if ((TARGET_ELF
6702 || !MACHO_DYNAMIC_NO_PIC_P
6708 && GET_CODE (x
) != CONST_INT
6709 && GET_CODE (x
) != CONST_WIDE_INT
6710 && GET_CODE (x
) != CONST_DOUBLE
6712 && GET_MODE_NUNITS (mode
) == 1
6713 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
6714 || (/* ??? Assume floating point reg based on mode? */
6715 (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
6716 && (mode
== DFmode
|| mode
== DDmode
))))
6718 rtx reg
= gen_reg_rtx (Pmode
);
6720 emit_insn (gen_elf_high (reg
, x
));
6722 emit_insn (gen_macho_high (reg
, x
));
6723 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
6726 && GET_CODE (x
) == SYMBOL_REF
6727 && constant_pool_expr_p (x
)
6728 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), Pmode
))
6729 return create_TOC_reference (x
, NULL_RTX
);
6734 /* Debug version of rs6000_legitimize_address. */
6736 rs6000_debug_legitimize_address (rtx x
, rtx oldx
, enum machine_mode mode
)
6742 ret
= rs6000_legitimize_address (x
, oldx
, mode
);
6743 insns
= get_insns ();
6749 "\nrs6000_legitimize_address: mode %s, old code %s, "
6750 "new code %s, modified\n",
6751 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)),
6752 GET_RTX_NAME (GET_CODE (ret
)));
6754 fprintf (stderr
, "Original address:\n");
6757 fprintf (stderr
, "oldx:\n");
6760 fprintf (stderr
, "New address:\n");
6765 fprintf (stderr
, "Insns added:\n");
6766 debug_rtx_list (insns
, 20);
6772 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
6773 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)));
6784 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
6785 We need to emit DTP-relative relocations. */
6787 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
6789 rs6000_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
6794 fputs ("\t.long\t", file
);
6797 fputs (DOUBLE_INT_ASM_OP
, file
);
6802 output_addr_const (file
, x
);
6803 fputs ("@dtprel+0x8000", file
);
6806 /* Return true if X is a symbol that refers to real (rather than emulated)
6810 rs6000_real_tls_symbol_ref_p (rtx x
)
6812 return (GET_CODE (x
) == SYMBOL_REF
6813 && SYMBOL_REF_TLS_MODEL (x
) >= TLS_MODEL_REAL
);
6816 /* In the name of slightly smaller debug output, and to cater to
6817 general assembler lossage, recognize various UNSPEC sequences
6818 and turn them back into a direct symbol reference. */
6821 rs6000_delegitimize_address (rtx orig_x
)
6825 orig_x
= delegitimize_mem_from_attrs (orig_x
);
6831 if (TARGET_CMODEL
!= CMODEL_SMALL
6832 && GET_CODE (y
) == LO_SUM
)
6836 if (GET_CODE (y
) == PLUS
6837 && GET_MODE (y
) == Pmode
6838 && CONST_INT_P (XEXP (y
, 1)))
6840 offset
= XEXP (y
, 1);
6844 if (GET_CODE (y
) == UNSPEC
6845 && XINT (y
, 1) == UNSPEC_TOCREL
)
6847 #ifdef ENABLE_CHECKING
6848 if (REG_P (XVECEXP (y
, 0, 1))
6849 && REGNO (XVECEXP (y
, 0, 1)) == TOC_REGISTER
)
6853 else if (GET_CODE (XVECEXP (y
, 0, 1)) == DEBUG_EXPR
)
6855 /* Weirdness alert. df_note_compute can replace r2 with a
6856 debug_expr when this unspec is in a debug_insn.
6857 Seen in gcc.dg/pr51957-1.c */
6865 y
= XVECEXP (y
, 0, 0);
6868 /* Do not associate thread-local symbols with the original
6869 constant pool symbol. */
6871 && GET_CODE (y
) == SYMBOL_REF
6872 && CONSTANT_POOL_ADDRESS_P (y
)
6873 && rs6000_real_tls_symbol_ref_p (get_pool_constant (y
)))
6877 if (offset
!= NULL_RTX
)
6878 y
= gen_rtx_PLUS (Pmode
, y
, offset
);
6879 if (!MEM_P (orig_x
))
6882 return replace_equiv_address_nv (orig_x
, y
);
6886 && GET_CODE (orig_x
) == LO_SUM
6887 && GET_CODE (XEXP (orig_x
, 1)) == CONST
)
6889 y
= XEXP (XEXP (orig_x
, 1), 0);
6890 if (GET_CODE (y
) == UNSPEC
6891 && XINT (y
, 1) == UNSPEC_MACHOPIC_OFFSET
)
6892 return XVECEXP (y
, 0, 0);
6898 /* Return true if X shouldn't be emitted into the debug info.
6899 The linker doesn't like .toc section references from
6900 .debug_* sections, so reject .toc section symbols. */
6903 rs6000_const_not_ok_for_debug_p (rtx x
)
6905 if (GET_CODE (x
) == SYMBOL_REF
6906 && CONSTANT_POOL_ADDRESS_P (x
))
6908 rtx c
= get_pool_constant (x
);
6909 enum machine_mode cmode
= get_pool_mode (x
);
6910 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c
, cmode
))
6917 /* Construct the SYMBOL_REF for the tls_get_addr function. */
6919 static GTY(()) rtx rs6000_tls_symbol
;
6921 rs6000_tls_get_addr (void)
6923 if (!rs6000_tls_symbol
)
6924 rs6000_tls_symbol
= init_one_libfunc ("__tls_get_addr");
6926 return rs6000_tls_symbol
;
6929 /* Construct the SYMBOL_REF for TLS GOT references. */
6931 static GTY(()) rtx rs6000_got_symbol
;
6933 rs6000_got_sym (void)
6935 if (!rs6000_got_symbol
)
6937 rs6000_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
6938 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_LOCAL
;
6939 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_EXTERNAL
;
6942 return rs6000_got_symbol
;
6945 /* AIX Thread-Local Address support. */
6948 rs6000_legitimize_tls_address_aix (rtx addr
, enum tls_model model
)
6950 rtx sym
, mem
, tocref
, tlsreg
, tmpreg
, dest
, tlsaddr
;
6954 name
= XSTR (addr
, 0);
6955 /* Append TLS CSECT qualifier, unless the symbol already is qualified
6956 or the symbol will be in TLS private data section. */
6957 if (name
[strlen (name
) - 1] != ']'
6958 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr
))
6959 || bss_initializer_p (SYMBOL_REF_DECL (addr
))))
6961 tlsname
= XALLOCAVEC (char, strlen (name
) + 4);
6962 strcpy (tlsname
, name
);
6964 bss_initializer_p (SYMBOL_REF_DECL (addr
)) ? "[UL]" : "[TL]");
6965 tlsaddr
= copy_rtx (addr
);
6966 XSTR (tlsaddr
, 0) = ggc_strdup (tlsname
);
6971 /* Place addr into TOC constant pool. */
6972 sym
= force_const_mem (GET_MODE (tlsaddr
), tlsaddr
);
6974 /* Output the TOC entry and create the MEM referencing the value. */
6975 if (constant_pool_expr_p (XEXP (sym
, 0))
6976 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym
, 0)), Pmode
))
6978 tocref
= create_TOC_reference (XEXP (sym
, 0), NULL_RTX
);
6979 mem
= gen_const_mem (Pmode
, tocref
);
6980 set_mem_alias_set (mem
, get_TOC_alias_set ());
6985 /* Use global-dynamic for local-dynamic. */
6986 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
6987 || model
== TLS_MODEL_LOCAL_DYNAMIC
)
6989 /* Create new TOC reference for @m symbol. */
6990 name
= XSTR (XVECEXP (XEXP (mem
, 0), 0, 0), 0);
6991 tlsname
= XALLOCAVEC (char, strlen (name
) + 1);
6992 strcpy (tlsname
, "*LCM");
6993 strcat (tlsname
, name
+ 3);
6994 rtx modaddr
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (tlsname
));
6995 SYMBOL_REF_FLAGS (modaddr
) |= SYMBOL_FLAG_LOCAL
;
6996 tocref
= create_TOC_reference (modaddr
, NULL_RTX
);
6997 rtx modmem
= gen_const_mem (Pmode
, tocref
);
6998 set_mem_alias_set (modmem
, get_TOC_alias_set ());
7000 rtx modreg
= gen_reg_rtx (Pmode
);
7001 emit_insn (gen_rtx_SET (VOIDmode
, modreg
, modmem
));
7003 tmpreg
= gen_reg_rtx (Pmode
);
7004 emit_insn (gen_rtx_SET (VOIDmode
, tmpreg
, mem
));
7006 dest
= gen_reg_rtx (Pmode
);
7008 emit_insn (gen_tls_get_addrsi (dest
, modreg
, tmpreg
));
7010 emit_insn (gen_tls_get_addrdi (dest
, modreg
, tmpreg
));
7013 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
7014 else if (TARGET_32BIT
)
7016 tlsreg
= gen_reg_rtx (SImode
);
7017 emit_insn (gen_tls_get_tpointer (tlsreg
));
7020 tlsreg
= gen_rtx_REG (DImode
, 13);
7022 /* Load the TOC value into temporary register. */
7023 tmpreg
= gen_reg_rtx (Pmode
);
7024 emit_insn (gen_rtx_SET (VOIDmode
, tmpreg
, mem
));
7025 set_unique_reg_note (get_last_insn (), REG_EQUAL
,
7026 gen_rtx_MINUS (Pmode
, addr
, tlsreg
));
7028 /* Add TOC symbol value to TLS pointer. */
7029 dest
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, tmpreg
, tlsreg
));
7034 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
7035 this (thread-local) address. */
7038 rs6000_legitimize_tls_address (rtx addr
, enum tls_model model
)
7043 return rs6000_legitimize_tls_address_aix (addr
, model
);
7045 dest
= gen_reg_rtx (Pmode
);
7046 if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 16)
7052 tlsreg
= gen_rtx_REG (Pmode
, 13);
7053 insn
= gen_tls_tprel_64 (dest
, tlsreg
, addr
);
7057 tlsreg
= gen_rtx_REG (Pmode
, 2);
7058 insn
= gen_tls_tprel_32 (dest
, tlsreg
, addr
);
7062 else if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 32)
7066 tmp
= gen_reg_rtx (Pmode
);
7069 tlsreg
= gen_rtx_REG (Pmode
, 13);
7070 insn
= gen_tls_tprel_ha_64 (tmp
, tlsreg
, addr
);
7074 tlsreg
= gen_rtx_REG (Pmode
, 2);
7075 insn
= gen_tls_tprel_ha_32 (tmp
, tlsreg
, addr
);
7079 insn
= gen_tls_tprel_lo_64 (dest
, tmp
, addr
);
7081 insn
= gen_tls_tprel_lo_32 (dest
, tmp
, addr
);
7086 rtx r3
, got
, tga
, tmp1
, tmp2
, call_insn
;
7088 /* We currently use relocations like @got@tlsgd for tls, which
7089 means the linker will handle allocation of tls entries, placing
7090 them in the .got section. So use a pointer to the .got section,
7091 not one to secondary TOC sections used by 64-bit -mminimal-toc,
7092 or to secondary GOT sections used by 32-bit -fPIC. */
7094 got
= gen_rtx_REG (Pmode
, 2);
7098 got
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
7101 rtx gsym
= rs6000_got_sym ();
7102 got
= gen_reg_rtx (Pmode
);
7104 rs6000_emit_move (got
, gsym
, Pmode
);
7109 tmp1
= gen_reg_rtx (Pmode
);
7110 tmp2
= gen_reg_rtx (Pmode
);
7111 mem
= gen_const_mem (Pmode
, tmp1
);
7112 lab
= gen_label_rtx ();
7113 emit_insn (gen_load_toc_v4_PIC_1b (gsym
, lab
));
7114 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
7115 if (TARGET_LINK_STACK
)
7116 emit_insn (gen_addsi3 (tmp1
, tmp1
, GEN_INT (4)));
7117 emit_move_insn (tmp2
, mem
);
7118 last
= emit_insn (gen_addsi3 (got
, tmp1
, tmp2
));
7119 set_unique_reg_note (last
, REG_EQUAL
, gsym
);
7124 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
)
7126 tga
= rs6000_tls_get_addr ();
7127 emit_library_call_value (tga
, dest
, LCT_CONST
, Pmode
,
7128 1, const0_rtx
, Pmode
);
7130 r3
= gen_rtx_REG (Pmode
, 3);
7131 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
7134 insn
= gen_tls_gd_aix64 (r3
, got
, addr
, tga
, const0_rtx
);
7136 insn
= gen_tls_gd_aix32 (r3
, got
, addr
, tga
, const0_rtx
);
7138 else if (DEFAULT_ABI
== ABI_V4
)
7139 insn
= gen_tls_gd_sysvsi (r3
, got
, addr
, tga
, const0_rtx
);
7142 call_insn
= last_call_insn ();
7143 PATTERN (call_insn
) = insn
;
7144 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
7145 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
7146 pic_offset_table_rtx
);
7148 else if (model
== TLS_MODEL_LOCAL_DYNAMIC
)
7150 tga
= rs6000_tls_get_addr ();
7151 tmp1
= gen_reg_rtx (Pmode
);
7152 emit_library_call_value (tga
, tmp1
, LCT_CONST
, Pmode
,
7153 1, const0_rtx
, Pmode
);
7155 r3
= gen_rtx_REG (Pmode
, 3);
7156 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
7159 insn
= gen_tls_ld_aix64 (r3
, got
, tga
, const0_rtx
);
7161 insn
= gen_tls_ld_aix32 (r3
, got
, tga
, const0_rtx
);
7163 else if (DEFAULT_ABI
== ABI_V4
)
7164 insn
= gen_tls_ld_sysvsi (r3
, got
, tga
, const0_rtx
);
7167 call_insn
= last_call_insn ();
7168 PATTERN (call_insn
) = insn
;
7169 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
7170 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
7171 pic_offset_table_rtx
);
7173 if (rs6000_tls_size
== 16)
7176 insn
= gen_tls_dtprel_64 (dest
, tmp1
, addr
);
7178 insn
= gen_tls_dtprel_32 (dest
, tmp1
, addr
);
7180 else if (rs6000_tls_size
== 32)
7182 tmp2
= gen_reg_rtx (Pmode
);
7184 insn
= gen_tls_dtprel_ha_64 (tmp2
, tmp1
, addr
);
7186 insn
= gen_tls_dtprel_ha_32 (tmp2
, tmp1
, addr
);
7189 insn
= gen_tls_dtprel_lo_64 (dest
, tmp2
, addr
);
7191 insn
= gen_tls_dtprel_lo_32 (dest
, tmp2
, addr
);
7195 tmp2
= gen_reg_rtx (Pmode
);
7197 insn
= gen_tls_got_dtprel_64 (tmp2
, got
, addr
);
7199 insn
= gen_tls_got_dtprel_32 (tmp2
, got
, addr
);
7201 insn
= gen_rtx_SET (Pmode
, dest
,
7202 gen_rtx_PLUS (Pmode
, tmp2
, tmp1
));
7208 /* IE, or 64-bit offset LE. */
7209 tmp2
= gen_reg_rtx (Pmode
);
7211 insn
= gen_tls_got_tprel_64 (tmp2
, got
, addr
);
7213 insn
= gen_tls_got_tprel_32 (tmp2
, got
, addr
);
7216 insn
= gen_tls_tls_64 (dest
, tmp2
, addr
);
7218 insn
= gen_tls_tls_32 (dest
, tmp2
, addr
);
7226 /* Return 1 if X contains a thread-local symbol. */
7229 rs6000_tls_referenced_p (rtx x
)
7231 if (! TARGET_HAVE_TLS
)
7234 return for_each_rtx (&x
, &rs6000_tls_symbol_ref_1
, 0);
7237 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
7240 rs6000_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
7242 if (GET_CODE (x
) == HIGH
7243 && GET_CODE (XEXP (x
, 0)) == UNSPEC
)
7246 /* A TLS symbol in the TOC cannot contain a sum. */
7247 if (GET_CODE (x
) == CONST
7248 && GET_CODE (XEXP (x
, 0)) == PLUS
7249 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
7250 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x
, 0), 0)) != 0)
7253 /* Do not place an ELF TLS symbol in the constant pool. */
7254 return TARGET_ELF
&& rs6000_tls_referenced_p (x
);
7257 /* Return 1 if *X is a thread-local symbol. This is the same as
7258 rs6000_tls_symbol_ref except for the type of the unused argument. */
7261 rs6000_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
7263 return RS6000_SYMBOL_REF_TLS_P (*x
);
7266 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
7267 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
7268 can be addressed relative to the toc pointer. */
7271 use_toc_relative_ref (rtx sym
)
7273 return ((constant_pool_expr_p (sym
)
7274 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym
),
7275 get_pool_mode (sym
)))
7276 || (TARGET_CMODEL
== CMODEL_MEDIUM
7277 && SYMBOL_REF_LOCAL_P (sym
)));
7280 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
7281 replace the input X, or the original X if no replacement is called for.
7282 The output parameter *WIN is 1 if the calling macro should goto WIN,
7285 For RS/6000, we wish to handle large displacements off a base
7286 register by splitting the addend across an addiu/addis and the mem insn.
7287 This cuts number of extra insns needed from 3 to 1.
7289 On Darwin, we use this to generate code for floating point constants.
7290 A movsf_low is generated so we wind up with 2 instructions rather than 3.
7291 The Darwin code is inside #if TARGET_MACHO because only then are the
7292 machopic_* functions defined. */
7294 rs6000_legitimize_reload_address (rtx x
, enum machine_mode mode
,
7295 int opnum
, int type
,
7296 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
7298 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
7300 /* Nasty hack for vsx_splat_V2DF/V2DI load from mem, which takes a
7301 DFmode/DImode MEM. */
7304 && ((mode
== DFmode
&& recog_data
.operand_mode
[0] == V2DFmode
)
7305 || (mode
== DImode
&& recog_data
.operand_mode
[0] == V2DImode
)))
7306 reg_offset_p
= false;
7308 /* We must recognize output that we have already generated ourselves. */
7309 if (GET_CODE (x
) == PLUS
7310 && GET_CODE (XEXP (x
, 0)) == PLUS
7311 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
7312 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7313 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7315 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7316 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
7317 opnum
, (enum reload_type
) type
);
7322 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
7323 if (GET_CODE (x
) == LO_SUM
7324 && GET_CODE (XEXP (x
, 0)) == HIGH
)
7326 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7327 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7328 opnum
, (enum reload_type
) type
);
7334 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
7335 && GET_CODE (x
) == LO_SUM
7336 && GET_CODE (XEXP (x
, 0)) == PLUS
7337 && XEXP (XEXP (x
, 0), 0) == pic_offset_table_rtx
7338 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == HIGH
7339 && XEXP (XEXP (XEXP (x
, 0), 1), 0) == XEXP (x
, 1)
7340 && machopic_operand_p (XEXP (x
, 1)))
7342 /* Result of previous invocation of this function on Darwin
7343 floating point constant. */
7344 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7345 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7346 opnum
, (enum reload_type
) type
);
7352 if (TARGET_CMODEL
!= CMODEL_SMALL
7354 && small_toc_ref (x
, VOIDmode
))
7356 rtx hi
= gen_rtx_HIGH (Pmode
, copy_rtx (x
));
7357 x
= gen_rtx_LO_SUM (Pmode
, hi
, x
);
7358 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7359 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7360 opnum
, (enum reload_type
) type
);
7365 if (GET_CODE (x
) == PLUS
7366 && GET_CODE (XEXP (x
, 0)) == REG
7367 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
7368 && INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 1)
7369 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7371 && !SPE_VECTOR_MODE (mode
)
7372 && !(TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
7373 && (!VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
)))
7375 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
7376 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
7378 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7380 /* Check for 32-bit overflow. */
7381 if (high
+ low
!= val
)
7387 /* Reload the high part into a base reg; leave the low part
7388 in the mem directly. */
7390 x
= gen_rtx_PLUS (GET_MODE (x
),
7391 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
7395 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7396 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
7397 opnum
, (enum reload_type
) type
);
7402 if (GET_CODE (x
) == SYMBOL_REF
7404 && (!VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
))
7405 && !SPE_VECTOR_MODE (mode
)
7407 && DEFAULT_ABI
== ABI_DARWIN
7408 && (flag_pic
|| MACHO_DYNAMIC_NO_PIC_P
)
7409 && machopic_symbol_defined_p (x
)
7411 && DEFAULT_ABI
== ABI_V4
7414 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
7415 The same goes for DImode without 64-bit gprs and DFmode and DDmode
7417 ??? Assume floating point reg based on mode? This assumption is
7418 violated by eg. powerpc-linux -m32 compile of gcc.dg/pr28796-2.c
7419 where reload ends up doing a DFmode load of a constant from
7420 mem using two gprs. Unfortunately, at this point reload
7421 hasn't yet selected regs so poking around in reload data
7422 won't help and even if we could figure out the regs reliably,
7423 we'd still want to allow this transformation when the mem is
7424 naturally aligned. Since we say the address is good here, we
7425 can't disable offsets from LO_SUMs in mem_operand_gpr.
7426 FIXME: Allow offset from lo_sum for other modes too, when
7427 mem is sufficiently aligned. */
7430 && (mode
!= TImode
|| !TARGET_VSX_TIMODE
)
7432 && (mode
!= DImode
|| TARGET_POWERPC64
)
7433 && ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_POWERPC64
7434 || (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)))
7439 rtx offset
= machopic_gen_offset (x
);
7440 x
= gen_rtx_LO_SUM (GET_MODE (x
),
7441 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
7442 gen_rtx_HIGH (Pmode
, offset
)), offset
);
7446 x
= gen_rtx_LO_SUM (GET_MODE (x
),
7447 gen_rtx_HIGH (Pmode
, x
), x
);
7449 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7450 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7451 opnum
, (enum reload_type
) type
);
7456 /* Reload an offset address wrapped by an AND that represents the
7457 masking of the lower bits. Strip the outer AND and let reload
7458 convert the offset address into an indirect address. For VSX,
7459 force reload to create the address with an AND in a separate
7460 register, because we can't guarantee an altivec register will
7462 if (VECTOR_MEM_ALTIVEC_P (mode
)
7463 && GET_CODE (x
) == AND
7464 && GET_CODE (XEXP (x
, 0)) == PLUS
7465 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
7466 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7467 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7468 && INTVAL (XEXP (x
, 1)) == -16)
7477 && GET_CODE (x
) == SYMBOL_REF
7478 && use_toc_relative_ref (x
))
7480 x
= create_TOC_reference (x
, NULL_RTX
);
7481 if (TARGET_CMODEL
!= CMODEL_SMALL
)
7482 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7483 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7484 opnum
, (enum reload_type
) type
);
7492 /* Debug version of rs6000_legitimize_reload_address. */
7494 rs6000_debug_legitimize_reload_address (rtx x
, enum machine_mode mode
,
7495 int opnum
, int type
,
7496 int ind_levels
, int *win
)
7498 rtx ret
= rs6000_legitimize_reload_address (x
, mode
, opnum
, type
,
7501 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
7502 "type = %d, ind_levels = %d, win = %d, original addr:\n",
7503 GET_MODE_NAME (mode
), opnum
, type
, ind_levels
, *win
);
7507 fprintf (stderr
, "Same address returned\n");
7509 fprintf (stderr
, "NULL returned\n");
7512 fprintf (stderr
, "New address:\n");
7519 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
7520 that is a valid memory address for an instruction.
7521 The MODE argument is the machine mode for the MEM expression
7522 that wants to use this address.
7524 On the RS/6000, there are four valid address: a SYMBOL_REF that
7525 refers to a constant pool entry of an address (or the sum of it
7526 plus a constant), a short (16-bit signed) constant plus a register,
7527 the sum of two registers, or a register indirect, possibly with an
7528 auto-increment. For DFmode, DDmode and DImode with a constant plus
7529 register, we must ensure that both words are addressable or PowerPC64
7530 with offset word aligned.
7532 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
7533 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
7534 because adjacent memory cells are accessed by adding word-sized offsets
7535 during assembly output. */
7537 rs6000_legitimate_address_p (enum machine_mode mode
, rtx x
, bool reg_ok_strict
)
7539 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
7541 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
7542 if (VECTOR_MEM_ALTIVEC_P (mode
)
7543 && GET_CODE (x
) == AND
7544 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7545 && INTVAL (XEXP (x
, 1)) == -16)
7548 if (TARGET_ELF
&& RS6000_SYMBOL_REF_TLS_P (x
))
7550 if (legitimate_indirect_address_p (x
, reg_ok_strict
))
7553 && (GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
7554 && mode_supports_pre_incdec_p (mode
)
7555 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
))
7557 if (virtual_stack_registers_memory_p (x
))
7559 if (reg_offset_p
&& legitimate_small_data_p (mode
, x
))
7562 && legitimate_constant_pool_address_p (x
, mode
,
7563 reg_ok_strict
|| lra_in_progress
))
7565 /* For TImode, if we have load/store quad and TImode in VSX registers, only
7566 allow register indirect addresses. This will allow the values to go in
7567 either GPRs or VSX registers without reloading. The vector types would
7568 tend to go into VSX registers, so we allow REG+REG, while TImode seems
7569 somewhat split, in that some uses are GPR based, and some VSX based. */
7570 if (mode
== TImode
&& TARGET_QUAD_MEMORY
&& TARGET_VSX_TIMODE
)
7572 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
7575 && GET_CODE (x
) == PLUS
7576 && GET_CODE (XEXP (x
, 0)) == REG
7577 && (XEXP (x
, 0) == virtual_stack_vars_rtx
7578 || XEXP (x
, 0) == arg_pointer_rtx
)
7579 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7581 if (rs6000_legitimate_offset_address_p (mode
, x
, reg_ok_strict
, false))
7585 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
7587 || (mode
!= DFmode
&& mode
!= DDmode
)
7588 || (TARGET_E500_DOUBLE
&& mode
!= DDmode
))
7589 && (TARGET_POWERPC64
|| mode
!= DImode
)
7590 && (mode
!= TImode
|| VECTOR_MEM_VSX_P (TImode
))
7592 && !avoiding_indexed_address_p (mode
)
7593 && legitimate_indexed_address_p (x
, reg_ok_strict
))
7595 if (TARGET_UPDATE
&& GET_CODE (x
) == PRE_MODIFY
7596 && mode_supports_pre_modify_p (mode
)
7597 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
)
7598 && (rs6000_legitimate_offset_address_p (mode
, XEXP (x
, 1),
7599 reg_ok_strict
, false)
7600 || (!avoiding_indexed_address_p (mode
)
7601 && legitimate_indexed_address_p (XEXP (x
, 1), reg_ok_strict
)))
7602 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
7604 if (reg_offset_p
&& legitimate_lo_sum_address_p (mode
, x
, reg_ok_strict
))
7609 /* Debug version of rs6000_legitimate_address_p. */
7611 rs6000_debug_legitimate_address_p (enum machine_mode mode
, rtx x
,
7614 bool ret
= rs6000_legitimate_address_p (mode
, x
, reg_ok_strict
);
7616 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
7617 "strict = %d, reload = %s, code = %s\n",
7618 ret
? "true" : "false",
7619 GET_MODE_NAME (mode
),
7623 : (reload_in_progress
? "progress" : "before")),
7624 GET_RTX_NAME (GET_CODE (x
)));
7630 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
7633 rs6000_mode_dependent_address_p (const_rtx addr
,
7634 addr_space_t as ATTRIBUTE_UNUSED
)
7636 return rs6000_mode_dependent_address_ptr (addr
);
7639 /* Go to LABEL if ADDR (a legitimate address expression)
7640 has an effect that depends on the machine mode it is used for.
7642 On the RS/6000 this is true of all integral offsets (since AltiVec
7643 and VSX modes don't allow them) or is a pre-increment or decrement.
7645 ??? Except that due to conceptual problems in offsettable_address_p
7646 we can't really report the problems of integral offsets. So leave
7647 this assuming that the adjustable offset must be valid for the
7648 sub-words of a TFmode operand, which is what we had before. */
7651 rs6000_mode_dependent_address (const_rtx addr
)
7653 switch (GET_CODE (addr
))
7656 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
7657 is considered a legitimate address before reload, so there
7658 are no offset restrictions in that case. Note that this
7659 condition is safe in strict mode because any address involving
7660 virtual_stack_vars_rtx or arg_pointer_rtx would already have
7661 been rejected as illegitimate. */
7662 if (XEXP (addr
, 0) != virtual_stack_vars_rtx
7663 && XEXP (addr
, 0) != arg_pointer_rtx
7664 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
7666 unsigned HOST_WIDE_INT val
= INTVAL (XEXP (addr
, 1));
7667 return val
+ 0x8000 >= 0x10000 - (TARGET_POWERPC64
? 8 : 12);
7672 /* Anything in the constant pool is sufficiently aligned that
7673 all bytes have the same high part address. */
7674 return !legitimate_constant_pool_address_p (addr
, QImode
, false);
7676 /* Auto-increment cases are now treated generically in recog.c. */
7678 return TARGET_UPDATE
;
7680 /* AND is only allowed in Altivec loads. */
7691 /* Debug version of rs6000_mode_dependent_address. */
7693 rs6000_debug_mode_dependent_address (const_rtx addr
)
7695 bool ret
= rs6000_mode_dependent_address (addr
);
7697 fprintf (stderr
, "\nrs6000_mode_dependent_address: ret = %s\n",
7698 ret
? "true" : "false");
7704 /* Implement FIND_BASE_TERM. */
7707 rs6000_find_base_term (rtx op
)
7712 if (GET_CODE (base
) == CONST
)
7713 base
= XEXP (base
, 0);
7714 if (GET_CODE (base
) == PLUS
)
7715 base
= XEXP (base
, 0);
7716 if (GET_CODE (base
) == UNSPEC
)
7717 switch (XINT (base
, 1))
7720 case UNSPEC_MACHOPIC_OFFSET
:
7721 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
7722 for aliasing purposes. */
7723 return XVECEXP (base
, 0, 0);
7729 /* More elaborate version of recog's offsettable_memref_p predicate
7730 that works around the ??? note of rs6000_mode_dependent_address.
7731 In particular it accepts
7733 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
7735 in 32-bit mode, that the recog predicate rejects. */
7738 rs6000_offsettable_memref_p (rtx op
, enum machine_mode reg_mode
)
7745 /* First mimic offsettable_memref_p. */
7746 if (offsettable_address_p (true, GET_MODE (op
), XEXP (op
, 0)))
7749 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
7750 the latter predicate knows nothing about the mode of the memory
7751 reference and, therefore, assumes that it is the largest supported
7752 mode (TFmode). As a consequence, legitimate offsettable memory
7753 references are rejected. rs6000_legitimate_offset_address_p contains
7754 the correct logic for the PLUS case of rs6000_mode_dependent_address,
7755 at least with a little bit of help here given that we know the
7756 actual registers used. */
7757 worst_case
= ((TARGET_POWERPC64
&& GET_MODE_CLASS (reg_mode
) == MODE_INT
)
7758 || GET_MODE_SIZE (reg_mode
) == 4);
7759 return rs6000_legitimate_offset_address_p (GET_MODE (op
), XEXP (op
, 0),
7763 /* Change register usage conditional on target flags. */
7765 rs6000_conditional_register_usage (void)
7769 if (TARGET_DEBUG_TARGET
)
7770 fprintf (stderr
, "rs6000_conditional_register_usage called\n");
7772 /* Set MQ register fixed (already call_used) so that it will not be
7776 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
7778 fixed_regs
[13] = call_used_regs
[13]
7779 = call_really_used_regs
[13] = 1;
7781 /* Conditionally disable FPRs. */
7782 if (TARGET_SOFT_FLOAT
|| !TARGET_FPRS
)
7783 for (i
= 32; i
< 64; i
++)
7784 fixed_regs
[i
] = call_used_regs
[i
]
7785 = call_really_used_regs
[i
] = 1;
7787 /* The TOC register is not killed across calls in a way that is
7788 visible to the compiler. */
7789 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
7790 call_really_used_regs
[2] = 0;
7792 if (DEFAULT_ABI
== ABI_V4
7793 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
7795 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7797 if (DEFAULT_ABI
== ABI_V4
7798 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
7800 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7801 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7802 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7804 if (DEFAULT_ABI
== ABI_DARWIN
7805 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
7806 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7807 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7808 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7810 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
)
7811 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7812 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7816 global_regs
[SPEFSCR_REGNO
] = 1;
7817 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
7818 registers in prologues and epilogues. We no longer use r14
7819 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
7820 pool for link-compatibility with older versions of GCC. Once
7821 "old" code has died out, we can return r14 to the allocation
7824 = call_used_regs
[14]
7825 = call_really_used_regs
[14] = 1;
7828 if (!TARGET_ALTIVEC
&& !TARGET_VSX
)
7830 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
7831 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
7832 call_really_used_regs
[VRSAVE_REGNO
] = 1;
7835 if (TARGET_ALTIVEC
|| TARGET_VSX
)
7836 global_regs
[VSCR_REGNO
] = 1;
7838 if (TARGET_ALTIVEC_ABI
)
7840 for (i
= FIRST_ALTIVEC_REGNO
; i
< FIRST_ALTIVEC_REGNO
+ 20; ++i
)
7841 call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
7843 /* AIX reserves VR20:31 in non-extended ABI mode. */
7845 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
< FIRST_ALTIVEC_REGNO
+ 32; ++i
)
7846 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
7851 /* Try to output insns to set TARGET equal to the constant C if it can
7852 be done in less than N insns. Do all computations in MODE.
7853 Returns the place where the output has been placed if it can be
7854 done and the insns have been emitted. If it would take more than N
7855 insns, zero is returned and no insns and emitted. */
7858 rs6000_emit_set_const (rtx dest
, enum machine_mode mode
,
7859 rtx source
, int n ATTRIBUTE_UNUSED
)
7861 rtx result
, insn
, set
;
7862 HOST_WIDE_INT c0
, c1
;
7869 dest
= gen_reg_rtx (mode
);
7870 emit_insn (gen_rtx_SET (VOIDmode
, dest
, source
));
7874 result
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (SImode
);
7876 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (result
),
7877 GEN_INT (INTVAL (source
)
7878 & (~ (HOST_WIDE_INT
) 0xffff))));
7879 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
7880 gen_rtx_IOR (SImode
, copy_rtx (result
),
7881 GEN_INT (INTVAL (source
) & 0xffff))));
7886 switch (GET_CODE (source
))
7889 c0
= INTVAL (source
);
7897 result
= rs6000_emit_set_long_const (dest
, c0
, c1
);
7904 insn
= get_last_insn ();
7905 set
= single_set (insn
);
7906 if (! CONSTANT_P (SET_SRC (set
)))
7907 set_unique_reg_note (insn
, REG_EQUAL
, source
);
7912 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
7913 fall back to a straight forward decomposition. We do this to avoid
7914 exponential run times encountered when looking for longer sequences
7915 with rs6000_emit_set_const. */
7917 rs6000_emit_set_long_const (rtx dest
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
7919 if (!TARGET_POWERPC64
)
7921 rtx operand1
, operand2
;
7923 operand1
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
== 0,
7925 operand2
= operand_subword_force (copy_rtx (dest
), WORDS_BIG_ENDIAN
!= 0,
7927 emit_move_insn (operand1
, GEN_INT (c1
));
7928 emit_move_insn (operand2
, GEN_INT (c2
));
7932 HOST_WIDE_INT ud1
, ud2
, ud3
, ud4
;
7935 ud2
= (c1
& 0xffff0000) >> 16;
7938 ud4
= (c2
& 0xffff0000) >> 16;
7940 if ((ud4
== 0xffff && ud3
== 0xffff && ud2
== 0xffff && (ud1
& 0x8000))
7941 || (ud4
== 0 && ud3
== 0 && ud2
== 0 && ! (ud1
& 0x8000)))
7942 emit_move_insn (dest
, GEN_INT ((ud1
^ 0x8000) - 0x8000));
7944 else if ((ud4
== 0xffff && ud3
== 0xffff && (ud2
& 0x8000))
7945 || (ud4
== 0 && ud3
== 0 && ! (ud2
& 0x8000)))
7947 emit_move_insn (dest
, GEN_INT (((ud2
<< 16) ^ 0x80000000)
7950 emit_move_insn (copy_rtx (dest
),
7951 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7954 else if (ud3
== 0 && ud4
== 0)
7956 gcc_assert (ud2
& 0x8000);
7957 emit_move_insn (dest
, GEN_INT (((ud2
<< 16) ^ 0x80000000)
7960 emit_move_insn (copy_rtx (dest
),
7961 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7963 emit_move_insn (copy_rtx (dest
),
7964 gen_rtx_ZERO_EXTEND (DImode
,
7965 gen_lowpart (SImode
,
7968 else if ((ud4
== 0xffff && (ud3
& 0x8000))
7969 || (ud4
== 0 && ! (ud3
& 0x8000)))
7971 emit_move_insn (dest
, GEN_INT (((ud3
<< 16) ^ 0x80000000)
7974 emit_move_insn (copy_rtx (dest
),
7975 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7977 emit_move_insn (copy_rtx (dest
),
7978 gen_rtx_ASHIFT (DImode
, copy_rtx (dest
),
7981 emit_move_insn (copy_rtx (dest
),
7982 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7987 emit_move_insn (dest
, GEN_INT (((ud4
<< 16) ^ 0x80000000)
7990 emit_move_insn (copy_rtx (dest
),
7991 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7994 emit_move_insn (copy_rtx (dest
),
7995 gen_rtx_ASHIFT (DImode
, copy_rtx (dest
),
7998 emit_move_insn (copy_rtx (dest
),
7999 gen_rtx_IOR (DImode
, copy_rtx (dest
),
8000 GEN_INT (ud2
<< 16)));
8002 emit_move_insn (copy_rtx (dest
),
8003 gen_rtx_IOR (DImode
, copy_rtx (dest
),
8010 /* Helper for the following. Get rid of [r+r] memory refs
8011 in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
8014 rs6000_eliminate_indexed_memrefs (rtx operands
[2])
8016 if (reload_in_progress
)
8019 if (GET_CODE (operands
[0]) == MEM
8020 && GET_CODE (XEXP (operands
[0], 0)) != REG
8021 && ! legitimate_constant_pool_address_p (XEXP (operands
[0], 0),
8022 GET_MODE (operands
[0]), false))
8024 = replace_equiv_address (operands
[0],
8025 copy_addr_to_reg (XEXP (operands
[0], 0)));
8027 if (GET_CODE (operands
[1]) == MEM
8028 && GET_CODE (XEXP (operands
[1], 0)) != REG
8029 && ! legitimate_constant_pool_address_p (XEXP (operands
[1], 0),
8030 GET_MODE (operands
[1]), false))
8032 = replace_equiv_address (operands
[1],
8033 copy_addr_to_reg (XEXP (operands
[1], 0)));
8036 /* Generate a vector of constants to permute MODE for a little-endian
8037 storage operation by swapping the two halves of a vector. */
8039 rs6000_const_vec (enum machine_mode mode
)
8067 v
= rtvec_alloc (subparts
);
8069 for (i
= 0; i
< subparts
/ 2; ++i
)
8070 RTVEC_ELT (v
, i
) = gen_rtx_CONST_INT (DImode
, i
+ subparts
/ 2);
8071 for (i
= subparts
/ 2; i
< subparts
; ++i
)
8072 RTVEC_ELT (v
, i
) = gen_rtx_CONST_INT (DImode
, i
- subparts
/ 2);
8077 /* Generate a permute rtx that represents an lxvd2x, stxvd2x, or xxpermdi
8078 for a VSX load or store operation. */
8080 rs6000_gen_le_vsx_permute (rtx source
, enum machine_mode mode
)
8082 rtx par
= gen_rtx_PARALLEL (VOIDmode
, rs6000_const_vec (mode
));
8083 return gen_rtx_VEC_SELECT (mode
, source
, par
);
8086 /* Emit a little-endian load from vector memory location SOURCE to VSX
8087 register DEST in mode MODE. The load is done with two permuting
8088 insn's that represent an lxvd2x and xxpermdi. */
8090 rs6000_emit_le_vsx_load (rtx dest
, rtx source
, enum machine_mode mode
)
8092 rtx tmp
, permute_mem
, permute_reg
;
8094 /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
8096 if (mode
== TImode
|| mode
== V1TImode
)
8099 dest
= gen_lowpart (V2DImode
, dest
);
8100 source
= adjust_address (source
, V2DImode
, 0);
8103 tmp
= can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest
) : dest
;
8104 permute_mem
= rs6000_gen_le_vsx_permute (source
, mode
);
8105 permute_reg
= rs6000_gen_le_vsx_permute (tmp
, mode
);
8106 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, permute_mem
));
8107 emit_insn (gen_rtx_SET (VOIDmode
, dest
, permute_reg
));
8110 /* Emit a little-endian store to vector memory location DEST from VSX
8111 register SOURCE in mode MODE. The store is done with two permuting
8112 insn's that represent an xxpermdi and an stxvd2x. */
8114 rs6000_emit_le_vsx_store (rtx dest
, rtx source
, enum machine_mode mode
)
8116 rtx tmp
, permute_src
, permute_tmp
;
8118 /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
8120 if (mode
== TImode
|| mode
== V1TImode
)
8123 dest
= adjust_address (dest
, V2DImode
, 0);
8124 source
= gen_lowpart (V2DImode
, source
);
8127 tmp
= can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source
) : source
;
8128 permute_src
= rs6000_gen_le_vsx_permute (source
, mode
);
8129 permute_tmp
= rs6000_gen_le_vsx_permute (tmp
, mode
);
8130 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, permute_src
));
8131 emit_insn (gen_rtx_SET (VOIDmode
, dest
, permute_tmp
));
8134 /* Emit a sequence representing a little-endian VSX load or store,
8135 moving data from SOURCE to DEST in mode MODE. This is done
8136 separately from rs6000_emit_move to ensure it is called only
8137 during expand. LE VSX loads and stores introduced later are
8138 handled with a split. The expand-time RTL generation allows
8139 us to optimize away redundant pairs of register-permutes. */
8141 rs6000_emit_le_vsx_move (rtx dest
, rtx source
, enum machine_mode mode
)
8143 gcc_assert (!BYTES_BIG_ENDIAN
8144 && VECTOR_MEM_VSX_P (mode
)
8145 && !gpr_or_gpr_p (dest
, source
)
8146 && (MEM_P (source
) ^ MEM_P (dest
)));
8150 gcc_assert (REG_P (dest
) || GET_CODE (dest
) == SUBREG
);
8151 rs6000_emit_le_vsx_load (dest
, source
, mode
);
8155 if (!REG_P (source
))
8156 source
= force_reg (mode
, source
);
8157 rs6000_emit_le_vsx_store (dest
, source
, mode
);
8161 /* Emit a move from SOURCE to DEST in mode MODE. */
8163 rs6000_emit_move (rtx dest
, rtx source
, enum machine_mode mode
)
8167 operands
[1] = source
;
8169 if (TARGET_DEBUG_ADDR
)
8172 "\nrs6000_emit_move: mode = %s, reload_in_progress = %d, "
8173 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
8174 GET_MODE_NAME (mode
),
8177 can_create_pseudo_p ());
8179 fprintf (stderr
, "source:\n");
8183 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
8184 if (CONST_WIDE_INT_P (operands
[1])
8185 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
8187 /* This should be fixed with the introduction of CONST_WIDE_INT. */
8191 /* Check if GCC is setting up a block move that will end up using FP
8192 registers as temporaries. We must make sure this is acceptable. */
8193 if (GET_CODE (operands
[0]) == MEM
8194 && GET_CODE (operands
[1]) == MEM
8196 && (SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[0]))
8197 || SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[1])))
8198 && ! (SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[0]) > 32
8199 ? 32 : MEM_ALIGN (operands
[0])))
8200 || SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[1]) > 32
8202 : MEM_ALIGN (operands
[1]))))
8203 && ! MEM_VOLATILE_P (operands
[0])
8204 && ! MEM_VOLATILE_P (operands
[1]))
8206 emit_move_insn (adjust_address (operands
[0], SImode
, 0),
8207 adjust_address (operands
[1], SImode
, 0));
8208 emit_move_insn (adjust_address (copy_rtx (operands
[0]), SImode
, 4),
8209 adjust_address (copy_rtx (operands
[1]), SImode
, 4));
8213 if (can_create_pseudo_p () && GET_CODE (operands
[0]) == MEM
8214 && !gpc_reg_operand (operands
[1], mode
))
8215 operands
[1] = force_reg (mode
, operands
[1]);
8217 /* Recognize the case where operand[1] is a reference to thread-local
8218 data and load its address to a register. */
8219 if (rs6000_tls_referenced_p (operands
[1]))
8221 enum tls_model model
;
8222 rtx tmp
= operands
[1];
8225 if (GET_CODE (tmp
) == CONST
&& GET_CODE (XEXP (tmp
, 0)) == PLUS
)
8227 addend
= XEXP (XEXP (tmp
, 0), 1);
8228 tmp
= XEXP (XEXP (tmp
, 0), 0);
8231 gcc_assert (GET_CODE (tmp
) == SYMBOL_REF
);
8232 model
= SYMBOL_REF_TLS_MODEL (tmp
);
8233 gcc_assert (model
!= 0);
8235 tmp
= rs6000_legitimize_tls_address (tmp
, model
);
8238 tmp
= gen_rtx_PLUS (mode
, tmp
, addend
);
8239 tmp
= force_operand (tmp
, operands
[0]);
8244 /* Handle the case where reload calls us with an invalid address. */
8245 if (reload_in_progress
&& mode
== Pmode
8246 && (! general_operand (operands
[1], mode
)
8247 || ! nonimmediate_operand (operands
[0], mode
)))
8250 /* 128-bit constant floating-point values on Darwin should really be
8251 loaded as two parts. */
8252 if (!TARGET_IEEEQUAD
&& TARGET_LONG_DOUBLE_128
8253 && mode
== TFmode
&& GET_CODE (operands
[1]) == CONST_DOUBLE
)
8255 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
, 0),
8256 simplify_gen_subreg (DFmode
, operands
[1], mode
, 0),
8258 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
,
8259 GET_MODE_SIZE (DFmode
)),
8260 simplify_gen_subreg (DFmode
, operands
[1], mode
,
8261 GET_MODE_SIZE (DFmode
)),
8266 if (reload_in_progress
&& cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
8267 cfun
->machine
->sdmode_stack_slot
=
8268 eliminate_regs (cfun
->machine
->sdmode_stack_slot
, VOIDmode
, NULL_RTX
);
8273 && REG_P (operands
[0]) && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
8274 && reg_preferred_class (REGNO (operands
[0])) == NO_REGS
8275 && (REG_P (operands
[1])
8276 || (GET_CODE (operands
[1]) == SUBREG
8277 && REG_P (SUBREG_REG (operands
[1])))))
8279 int regno
= REGNO (GET_CODE (operands
[1]) == SUBREG
8280 ? SUBREG_REG (operands
[1]) : operands
[1]);
8283 if (regno
>= FIRST_PSEUDO_REGISTER
)
8285 cl
= reg_preferred_class (regno
);
8286 gcc_assert (cl
!= NO_REGS
);
8287 regno
= ira_class_hard_regs
[cl
][0];
8289 if (FP_REGNO_P (regno
))
8291 if (GET_MODE (operands
[0]) != DDmode
)
8292 operands
[0] = gen_rtx_SUBREG (DDmode
, operands
[0], 0);
8293 emit_insn (gen_movsd_store (operands
[0], operands
[1]));
8295 else if (INT_REGNO_P (regno
))
8296 emit_insn (gen_movsd_hardfloat (operands
[0], operands
[1]));
8303 && (REG_P (operands
[0])
8304 || (GET_CODE (operands
[0]) == SUBREG
8305 && REG_P (SUBREG_REG (operands
[0]))))
8306 && REG_P (operands
[1]) && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
8307 && reg_preferred_class (REGNO (operands
[1])) == NO_REGS
)
8309 int regno
= REGNO (GET_CODE (operands
[0]) == SUBREG
8310 ? SUBREG_REG (operands
[0]) : operands
[0]);
8313 if (regno
>= FIRST_PSEUDO_REGISTER
)
8315 cl
= reg_preferred_class (regno
);
8316 gcc_assert (cl
!= NO_REGS
);
8317 regno
= ira_class_hard_regs
[cl
][0];
8319 if (FP_REGNO_P (regno
))
8321 if (GET_MODE (operands
[1]) != DDmode
)
8322 operands
[1] = gen_rtx_SUBREG (DDmode
, operands
[1], 0);
8323 emit_insn (gen_movsd_load (operands
[0], operands
[1]));
8325 else if (INT_REGNO_P (regno
))
8326 emit_insn (gen_movsd_hardfloat (operands
[0], operands
[1]));
8332 if (reload_in_progress
8334 && cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
8335 && MEM_P (operands
[0])
8336 && rtx_equal_p (operands
[0], cfun
->machine
->sdmode_stack_slot
)
8337 && REG_P (operands
[1]))
8339 if (FP_REGNO_P (REGNO (operands
[1])))
8341 rtx mem
= adjust_address_nv (operands
[0], DDmode
, 0);
8342 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8343 emit_insn (gen_movsd_store (mem
, operands
[1]));
8345 else if (INT_REGNO_P (REGNO (operands
[1])))
8347 rtx mem
= operands
[0];
8348 if (BYTES_BIG_ENDIAN
)
8349 mem
= adjust_address_nv (mem
, mode
, 4);
8350 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8351 emit_insn (gen_movsd_hardfloat (mem
, operands
[1]));
8357 if (reload_in_progress
8359 && REG_P (operands
[0])
8360 && MEM_P (operands
[1])
8361 && cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
8362 && rtx_equal_p (operands
[1], cfun
->machine
->sdmode_stack_slot
))
8364 if (FP_REGNO_P (REGNO (operands
[0])))
8366 rtx mem
= adjust_address_nv (operands
[1], DDmode
, 0);
8367 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8368 emit_insn (gen_movsd_load (operands
[0], mem
));
8370 else if (INT_REGNO_P (REGNO (operands
[0])))
8372 rtx mem
= operands
[1];
8373 if (BYTES_BIG_ENDIAN
)
8374 mem
= adjust_address_nv (mem
, mode
, 4);
8375 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8376 emit_insn (gen_movsd_hardfloat (operands
[0], mem
));
8383 /* FIXME: In the long term, this switch statement should go away
8384 and be replaced by a sequence of tests based on things like
8390 if (CONSTANT_P (operands
[1])
8391 && GET_CODE (operands
[1]) != CONST_INT
)
8392 operands
[1] = force_const_mem (mode
, operands
[1]);
8397 rs6000_eliminate_indexed_memrefs (operands
);
8404 if (CONSTANT_P (operands
[1])
8405 && ! easy_fp_constant (operands
[1], mode
))
8406 operands
[1] = force_const_mem (mode
, operands
[1]);
8420 if (CONSTANT_P (operands
[1])
8421 && !easy_vector_constant (operands
[1], mode
))
8422 operands
[1] = force_const_mem (mode
, operands
[1]);
8427 /* Use default pattern for address of ELF small data */
8430 && DEFAULT_ABI
== ABI_V4
8431 && (GET_CODE (operands
[1]) == SYMBOL_REF
8432 || GET_CODE (operands
[1]) == CONST
)
8433 && small_data_operand (operands
[1], mode
))
8435 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
8439 if (DEFAULT_ABI
== ABI_V4
8440 && mode
== Pmode
&& mode
== SImode
8441 && flag_pic
== 1 && got_operand (operands
[1], mode
))
8443 emit_insn (gen_movsi_got (operands
[0], operands
[1]));
8447 if ((TARGET_ELF
|| DEFAULT_ABI
== ABI_DARWIN
)
8451 && CONSTANT_P (operands
[1])
8452 && GET_CODE (operands
[1]) != HIGH
8453 && GET_CODE (operands
[1]) != CONST_INT
)
8455 rtx target
= (!can_create_pseudo_p ()
8457 : gen_reg_rtx (mode
));
8459 /* If this is a function address on -mcall-aixdesc,
8460 convert it to the address of the descriptor. */
8461 if (DEFAULT_ABI
== ABI_AIX
8462 && GET_CODE (operands
[1]) == SYMBOL_REF
8463 && XSTR (operands
[1], 0)[0] == '.')
8465 const char *name
= XSTR (operands
[1], 0);
8467 while (*name
== '.')
8469 new_ref
= gen_rtx_SYMBOL_REF (Pmode
, name
);
8470 CONSTANT_POOL_ADDRESS_P (new_ref
)
8471 = CONSTANT_POOL_ADDRESS_P (operands
[1]);
8472 SYMBOL_REF_FLAGS (new_ref
) = SYMBOL_REF_FLAGS (operands
[1]);
8473 SYMBOL_REF_USED (new_ref
) = SYMBOL_REF_USED (operands
[1]);
8474 SYMBOL_REF_DATA (new_ref
) = SYMBOL_REF_DATA (operands
[1]);
8475 operands
[1] = new_ref
;
8478 if (DEFAULT_ABI
== ABI_DARWIN
)
8481 if (MACHO_DYNAMIC_NO_PIC_P
)
8483 /* Take care of any required data indirection. */
8484 operands
[1] = rs6000_machopic_legitimize_pic_address (
8485 operands
[1], mode
, operands
[0]);
8486 if (operands
[0] != operands
[1])
8487 emit_insn (gen_rtx_SET (VOIDmode
,
8488 operands
[0], operands
[1]));
8492 emit_insn (gen_macho_high (target
, operands
[1]));
8493 emit_insn (gen_macho_low (operands
[0], target
, operands
[1]));
8497 emit_insn (gen_elf_high (target
, operands
[1]));
8498 emit_insn (gen_elf_low (operands
[0], target
, operands
[1]));
8502 /* If this is a SYMBOL_REF that refers to a constant pool entry,
8503 and we have put it in the TOC, we just need to make a TOC-relative
8506 && GET_CODE (operands
[1]) == SYMBOL_REF
8507 && use_toc_relative_ref (operands
[1]))
8508 operands
[1] = create_TOC_reference (operands
[1], operands
[0]);
8509 else if (mode
== Pmode
8510 && CONSTANT_P (operands
[1])
8511 && GET_CODE (operands
[1]) != HIGH
8512 && ((GET_CODE (operands
[1]) != CONST_INT
8513 && ! easy_fp_constant (operands
[1], mode
))
8514 || (GET_CODE (operands
[1]) == CONST_INT
8515 && (num_insns_constant (operands
[1], mode
)
8516 > (TARGET_CMODEL
!= CMODEL_SMALL
? 3 : 2)))
8517 || (GET_CODE (operands
[0]) == REG
8518 && FP_REGNO_P (REGNO (operands
[0]))))
8519 && !toc_relative_expr_p (operands
[1], false)
8520 && (TARGET_CMODEL
== CMODEL_SMALL
8521 || can_create_pseudo_p ()
8522 || (REG_P (operands
[0])
8523 && INT_REG_OK_FOR_BASE_P (operands
[0], true))))
8527 /* Darwin uses a special PIC legitimizer. */
8528 if (DEFAULT_ABI
== ABI_DARWIN
&& MACHOPIC_INDIRECT
)
8531 rs6000_machopic_legitimize_pic_address (operands
[1], mode
,
8533 if (operands
[0] != operands
[1])
8534 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
8539 /* If we are to limit the number of things we put in the TOC and
8540 this is a symbol plus a constant we can add in one insn,
8541 just put the symbol in the TOC and add the constant. Don't do
8542 this if reload is in progress. */
8543 if (GET_CODE (operands
[1]) == CONST
8544 && TARGET_NO_SUM_IN_TOC
&& ! reload_in_progress
8545 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
8546 && add_operand (XEXP (XEXP (operands
[1], 0), 1), mode
)
8547 && (GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
8548 || GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == SYMBOL_REF
)
8549 && ! side_effects_p (operands
[0]))
8552 force_const_mem (mode
, XEXP (XEXP (operands
[1], 0), 0));
8553 rtx other
= XEXP (XEXP (operands
[1], 0), 1);
8555 sym
= force_reg (mode
, sym
);
8556 emit_insn (gen_add3_insn (operands
[0], sym
, other
));
8560 operands
[1] = force_const_mem (mode
, operands
[1]);
8563 && GET_CODE (XEXP (operands
[1], 0)) == SYMBOL_REF
8564 && constant_pool_expr_p (XEXP (operands
[1], 0))
8565 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
8566 get_pool_constant (XEXP (operands
[1], 0)),
8567 get_pool_mode (XEXP (operands
[1], 0))))
8569 rtx tocref
= create_TOC_reference (XEXP (operands
[1], 0),
8571 operands
[1] = gen_const_mem (mode
, tocref
);
8572 set_mem_alias_set (operands
[1], get_TOC_alias_set ());
8578 if (!VECTOR_MEM_VSX_P (TImode
))
8579 rs6000_eliminate_indexed_memrefs (operands
);
8583 rs6000_eliminate_indexed_memrefs (operands
);
8587 fatal_insn ("bad move", gen_rtx_SET (VOIDmode
, dest
, source
));
8590 /* Above, we may have called force_const_mem which may have returned
8591 an invalid address. If we can, fix this up; otherwise, reload will
8592 have to deal with it. */
8593 if (GET_CODE (operands
[1]) == MEM
&& ! reload_in_progress
)
8594 operands
[1] = validize_mem (operands
[1]);
8597 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
8600 /* Return true if a structure, union or array containing FIELD should be
8601 accessed using `BLKMODE'.
8603 For the SPE, simd types are V2SI, and gcc can be tempted to put the
8604 entire thing in a DI and use subregs to access the internals.
8605 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
8606 back-end. Because a single GPR can hold a V2SI, but not a DI, the
8607 best thing to do is set structs to BLKmode and avoid Severe Tire
8610 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
8611 fit into 1, whereas DI still needs two. */
8614 rs6000_member_type_forces_blk (const_tree field
, enum machine_mode mode
)
8616 return ((TARGET_SPE
&& TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
8617 || (TARGET_E500_DOUBLE
&& mode
== DFmode
));
8620 /* Nonzero if we can use a floating-point register to pass this arg. */
8621 #define USE_FP_FOR_ARG_P(CUM,MODE) \
8622 (SCALAR_FLOAT_MODE_P (MODE) \
8623 && (CUM)->fregno <= FP_ARG_MAX_REG \
8624 && TARGET_HARD_FLOAT && TARGET_FPRS)
8626 /* Nonzero if we can use an AltiVec register to pass this arg. */
8627 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
8628 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
8629 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
8630 && TARGET_ALTIVEC_ABI \
8633 /* Walk down the type tree of TYPE counting consecutive base elements.
8634 If *MODEP is VOIDmode, then set it to the first valid floating point
8635 or vector type. If a non-floating point or vector type is found, or
8636 if a floating point or vector type that doesn't match a non-VOIDmode
8637 *MODEP is found, then return -1, otherwise return the count in the
8641 rs6000_aggregate_candidate (const_tree type
, enum machine_mode
*modep
)
8643 enum machine_mode mode
;
8646 switch (TREE_CODE (type
))
8649 mode
= TYPE_MODE (type
);
8650 if (!SCALAR_FLOAT_MODE_P (mode
))
8653 if (*modep
== VOIDmode
)
8662 mode
= TYPE_MODE (TREE_TYPE (type
));
8663 if (!SCALAR_FLOAT_MODE_P (mode
))
8666 if (*modep
== VOIDmode
)
8675 if (!TARGET_ALTIVEC_ABI
|| !TARGET_ALTIVEC
)
8678 /* Use V4SImode as representative of all 128-bit vector types. */
8679 size
= int_size_in_bytes (type
);
8689 if (*modep
== VOIDmode
)
8692 /* Vector modes are considered to be opaque: two vectors are
8693 equivalent for the purposes of being homogeneous aggregates
8694 if they are the same size. */
8703 tree index
= TYPE_DOMAIN (type
);
8705 /* Can't handle incomplete types nor sizes that are not
8707 if (!COMPLETE_TYPE_P (type
)
8708 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
8711 count
= rs6000_aggregate_candidate (TREE_TYPE (type
), modep
);
8714 || !TYPE_MAX_VALUE (index
)
8715 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index
))
8716 || !TYPE_MIN_VALUE (index
)
8717 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index
))
8721 count
*= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index
))
8722 - tree_to_uhwi (TYPE_MIN_VALUE (index
)));
8724 /* There must be no padding. */
8725 if (wi::ne_p (TYPE_SIZE (type
), count
* GET_MODE_BITSIZE (*modep
)))
8737 /* Can't handle incomplete types nor sizes that are not
8739 if (!COMPLETE_TYPE_P (type
)
8740 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
8743 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
8745 if (TREE_CODE (field
) != FIELD_DECL
)
8748 sub_count
= rs6000_aggregate_candidate (TREE_TYPE (field
), modep
);
8754 /* There must be no padding. */
8755 if (wi::ne_p (TYPE_SIZE (type
), count
* GET_MODE_BITSIZE (*modep
)))
8762 case QUAL_UNION_TYPE
:
8764 /* These aren't very interesting except in a degenerate case. */
8769 /* Can't handle incomplete types nor sizes that are not
8771 if (!COMPLETE_TYPE_P (type
)
8772 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
8774 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
8776 if (TREE_CODE (field
) != FIELD_DECL
)
8779 sub_count
= rs6000_aggregate_candidate (TREE_TYPE (field
), modep
);
8782 count
= count
> sub_count
? count
: sub_count
;
8785 /* There must be no padding. */
8786 if (wi::ne_p (TYPE_SIZE (type
), count
* GET_MODE_BITSIZE (*modep
)))
8799 /* If an argument, whose type is described by TYPE and MODE, is a homogeneous
8800 float or vector aggregate that shall be passed in FP/vector registers
8801 according to the ELFv2 ABI, return the homogeneous element mode in
8802 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
8804 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
8807 rs6000_discover_homogeneous_aggregate (enum machine_mode mode
, const_tree type
,
8808 enum machine_mode
*elt_mode
,
8811 /* Note that we do not accept complex types at the top level as
8812 homogeneous aggregates; these types are handled via the
8813 targetm.calls.split_complex_arg mechanism. Complex types
8814 can be elements of homogeneous aggregates, however. */
8815 if (DEFAULT_ABI
== ABI_ELFv2
&& type
&& AGGREGATE_TYPE_P (type
))
8817 enum machine_mode field_mode
= VOIDmode
;
8818 int field_count
= rs6000_aggregate_candidate (type
, &field_mode
);
8820 if (field_count
> 0)
8822 int n_regs
= (SCALAR_FLOAT_MODE_P (field_mode
)?
8823 (GET_MODE_SIZE (field_mode
) + 7) >> 3 : 1);
8825 /* The ELFv2 ABI allows homogeneous aggregates to occupy
8826 up to AGGR_ARG_NUM_REG registers. */
8827 if (field_count
* n_regs
<= AGGR_ARG_NUM_REG
)
8830 *elt_mode
= field_mode
;
8832 *n_elts
= field_count
;
8845 /* Return a nonzero value to say to return the function value in
8846 memory, just as large structures are always returned. TYPE will be
8847 the data type of the value, and FNTYPE will be the type of the
8848 function doing the returning, or @code{NULL} for libcalls.
8850 The AIX ABI for the RS/6000 specifies that all structures are
8851 returned in memory. The Darwin ABI does the same.
8853 For the Darwin 64 Bit ABI, a function result can be returned in
8854 registers or in memory, depending on the size of the return data
8855 type. If it is returned in registers, the value occupies the same
8856 registers as it would if it were the first and only function
8857 argument. Otherwise, the function places its result in memory at
8858 the location pointed to by GPR3.
8860 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
8861 but a draft put them in memory, and GCC used to implement the draft
8862 instead of the final standard. Therefore, aix_struct_return
8863 controls this instead of DEFAULT_ABI; V.4 targets needing backward
8864 compatibility can change DRAFT_V4_STRUCT_RET to override the
8865 default, and -m switches get the final word. See
8866 rs6000_option_override_internal for more details.
8868 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
8869 long double support is enabled. These values are returned in memory.
8871 int_size_in_bytes returns -1 for variable size objects, which go in
8872 memory always. The cast to unsigned makes -1 > 8. */
8875 rs6000_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
8877 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
8879 && rs6000_darwin64_abi
8880 && TREE_CODE (type
) == RECORD_TYPE
8881 && int_size_in_bytes (type
) > 0)
8883 CUMULATIVE_ARGS valcum
;
8887 valcum
.fregno
= FP_ARG_MIN_REG
;
8888 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
8889 /* Do a trial code generation as if this were going to be passed
8890 as an argument; if any part goes in memory, we return NULL. */
8891 valret
= rs6000_darwin64_record_arg (&valcum
, type
, true, true);
8894 /* Otherwise fall through to more conventional ABI rules. */
8897 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
8898 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type
), type
,
8902 /* The ELFv2 ABI returns aggregates up to 16B in registers */
8903 if (DEFAULT_ABI
== ABI_ELFv2
&& AGGREGATE_TYPE_P (type
)
8904 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) <= 16)
8907 if (AGGREGATE_TYPE_P (type
)
8908 && (aix_struct_return
8909 || (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8))
8912 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
8913 modes only exist for GCC vector types if -maltivec. */
8914 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
8915 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
8918 /* Return synthetic vectors in memory. */
8919 if (TREE_CODE (type
) == VECTOR_TYPE
8920 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
8922 static bool warned_for_return_big_vectors
= false;
8923 if (!warned_for_return_big_vectors
)
8925 warning (0, "GCC vector returned by reference: "
8926 "non-standard ABI extension with no compatibility guarantee");
8927 warned_for_return_big_vectors
= true;
8932 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& TYPE_MODE (type
) == TFmode
)
8938 /* Specify whether values returned in registers should be at the most
8939 significant end of a register. We want aggregates returned by
8940 value to match the way aggregates are passed to functions. */
8943 rs6000_return_in_msb (const_tree valtype
)
8945 return (DEFAULT_ABI
== ABI_ELFv2
8947 && AGGREGATE_TYPE_P (valtype
)
8948 && FUNCTION_ARG_PADDING (TYPE_MODE (valtype
), valtype
) == upward
);
8951 #ifdef HAVE_AS_GNU_ATTRIBUTE
8952 /* Return TRUE if a call to function FNDECL may be one that
8953 potentially affects the function calling ABI of the object file. */
8956 call_ABI_of_interest (tree fndecl
)
8958 if (cgraph_state
== CGRAPH_STATE_EXPANSION
)
8960 struct cgraph_node
*c_node
;
8962 /* Libcalls are always interesting. */
8963 if (fndecl
== NULL_TREE
)
8966 /* Any call to an external function is interesting. */
8967 if (DECL_EXTERNAL (fndecl
))
8970 /* Interesting functions that we are emitting in this object file. */
8971 c_node
= cgraph_get_node (fndecl
);
8972 c_node
= cgraph_function_or_thunk_node (c_node
, NULL
);
8973 return !cgraph_only_called_directly_p (c_node
);
8979 /* Initialize a variable CUM of type CUMULATIVE_ARGS
8980 for a call to a function whose data type is FNTYPE.
8981 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
8983 For incoming args we set the number of arguments in the prototype large
8984 so we never return a PARALLEL. */
8987 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
8988 rtx libname ATTRIBUTE_UNUSED
, int incoming
,
8989 int libcall
, int n_named_args
,
8990 tree fndecl ATTRIBUTE_UNUSED
,
8991 enum machine_mode return_mode ATTRIBUTE_UNUSED
)
8993 static CUMULATIVE_ARGS zero_cumulative
;
8995 *cum
= zero_cumulative
;
8997 cum
->fregno
= FP_ARG_MIN_REG
;
8998 cum
->vregno
= ALTIVEC_ARG_MIN_REG
;
8999 cum
->prototype
= (fntype
&& prototype_p (fntype
));
9000 cum
->call_cookie
= ((DEFAULT_ABI
== ABI_V4
&& libcall
)
9001 ? CALL_LIBCALL
: CALL_NORMAL
);
9002 cum
->sysv_gregno
= GP_ARG_MIN_REG
;
9003 cum
->stdarg
= stdarg_p (fntype
);
9005 cum
->nargs_prototype
= 0;
9006 if (incoming
|| cum
->prototype
)
9007 cum
->nargs_prototype
= n_named_args
;
9009 /* Check for a longcall attribute. */
9010 if ((!fntype
&& rs6000_default_long_calls
)
9012 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
))
9013 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
))))
9014 cum
->call_cookie
|= CALL_LONG
;
9016 if (TARGET_DEBUG_ARG
)
9018 fprintf (stderr
, "\ninit_cumulative_args:");
9021 tree ret_type
= TREE_TYPE (fntype
);
9022 fprintf (stderr
, " ret code = %s,",
9023 get_tree_code_name (TREE_CODE (ret_type
)));
9026 if (cum
->call_cookie
& CALL_LONG
)
9027 fprintf (stderr
, " longcall,");
9029 fprintf (stderr
, " proto = %d, nargs = %d\n",
9030 cum
->prototype
, cum
->nargs_prototype
);
9033 #ifdef HAVE_AS_GNU_ATTRIBUTE
9034 if (DEFAULT_ABI
== ABI_V4
)
9036 cum
->escapes
= call_ABI_of_interest (fndecl
);
9043 return_type
= TREE_TYPE (fntype
);
9044 return_mode
= TYPE_MODE (return_type
);
9047 return_type
= lang_hooks
.types
.type_for_mode (return_mode
, 0);
9049 if (return_type
!= NULL
)
9051 if (TREE_CODE (return_type
) == RECORD_TYPE
9052 && TYPE_TRANSPARENT_AGGR (return_type
))
9054 return_type
= TREE_TYPE (first_field (return_type
));
9055 return_mode
= TYPE_MODE (return_type
);
9057 if (AGGREGATE_TYPE_P (return_type
)
9058 && ((unsigned HOST_WIDE_INT
) int_size_in_bytes (return_type
)
9060 rs6000_returns_struct
= true;
9062 if (SCALAR_FLOAT_MODE_P (return_mode
))
9063 rs6000_passes_float
= true;
9064 else if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode
)
9065 || SPE_VECTOR_MODE (return_mode
))
9066 rs6000_passes_vector
= true;
9073 && TARGET_ALTIVEC_ABI
9074 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype
))))
9076 error ("cannot return value in vector register because"
9077 " altivec instructions are disabled, use -maltivec"
9082 /* Return true if TYPE must be passed on the stack and not in registers. */
9085 rs6000_must_pass_in_stack (enum machine_mode mode
, const_tree type
)
9087 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
|| TARGET_64BIT
)
9088 return must_pass_in_stack_var_size (mode
, type
);
9090 return must_pass_in_stack_var_size_or_pad (mode
, type
);
9093 /* If defined, a C expression which determines whether, and in which
9094 direction, to pad out an argument with extra space. The value
9095 should be of type `enum direction': either `upward' to pad above
9096 the argument, `downward' to pad below, or `none' to inhibit
9099 For the AIX ABI structs are always stored left shifted in their
9103 function_arg_padding (enum machine_mode mode
, const_tree type
)
9105 #ifndef AGGREGATE_PADDING_FIXED
9106 #define AGGREGATE_PADDING_FIXED 0
9108 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
9109 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
9112 if (!AGGREGATE_PADDING_FIXED
)
9114 /* GCC used to pass structures of the same size as integer types as
9115 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
9116 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
9117 passed padded downward, except that -mstrict-align further
9118 muddied the water in that multi-component structures of 2 and 4
9119 bytes in size were passed padded upward.
9121 The following arranges for best compatibility with previous
9122 versions of gcc, but removes the -mstrict-align dependency. */
9123 if (BYTES_BIG_ENDIAN
)
9125 HOST_WIDE_INT size
= 0;
9127 if (mode
== BLKmode
)
9129 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
9130 size
= int_size_in_bytes (type
);
9133 size
= GET_MODE_SIZE (mode
);
9135 if (size
== 1 || size
== 2 || size
== 4)
9141 if (AGGREGATES_PAD_UPWARD_ALWAYS
)
9143 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
9147 /* Fall back to the default. */
9148 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
9151 /* If defined, a C expression that gives the alignment boundary, in bits,
9152 of an argument with the specified mode and type. If it is not defined,
9153 PARM_BOUNDARY is used for all arguments.
9155 V.4 wants long longs and doubles to be double word aligned. Just
9156 testing the mode size is a boneheaded way to do this as it means
9157 that other types such as complex int are also double word aligned.
9158 However, we're stuck with this because changing the ABI might break
9159 existing library interfaces.
9161 Doubleword align SPE vectors.
9162 Quadword align Altivec/VSX vectors.
9163 Quadword align large synthetic vector types. */
9166 rs6000_function_arg_boundary (enum machine_mode mode
, const_tree type
)
9168 enum machine_mode elt_mode
;
9171 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
9173 if (DEFAULT_ABI
== ABI_V4
9174 && (GET_MODE_SIZE (mode
) == 8
9175 || (TARGET_HARD_FLOAT
9177 && (mode
== TFmode
|| mode
== TDmode
))))
9179 else if (SPE_VECTOR_MODE (mode
)
9180 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9181 && int_size_in_bytes (type
) >= 8
9182 && int_size_in_bytes (type
) < 16))
9184 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode
)
9185 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9186 && int_size_in_bytes (type
) >= 16))
9188 else if (((TARGET_MACHO
&& rs6000_darwin64_abi
)
9189 || DEFAULT_ABI
== ABI_ELFv2
9190 || (DEFAULT_ABI
== ABI_AIX
&& !rs6000_compat_align_parm
))
9192 && type
&& TYPE_ALIGN (type
) > 64)
9195 return PARM_BOUNDARY
;
9198 /* The offset in words to the start of the parameter save area. */
9201 rs6000_parm_offset (void)
9203 return (DEFAULT_ABI
== ABI_V4
? 2
9204 : DEFAULT_ABI
== ABI_ELFv2
? 4
9208 /* For a function parm of MODE and TYPE, return the starting word in
9209 the parameter area. NWORDS of the parameter area are already used. */
9212 rs6000_parm_start (enum machine_mode mode
, const_tree type
,
9213 unsigned int nwords
)
9217 align
= rs6000_function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
9218 return nwords
+ (-(rs6000_parm_offset () + nwords
) & align
);
9221 /* Compute the size (in words) of a function argument. */
9223 static unsigned long
9224 rs6000_arg_size (enum machine_mode mode
, const_tree type
)
9228 if (mode
!= BLKmode
)
9229 size
= GET_MODE_SIZE (mode
);
9231 size
= int_size_in_bytes (type
);
9234 return (size
+ 3) >> 2;
9236 return (size
+ 7) >> 3;
9239 /* Use this to flush pending int fields. */
9242 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*cum
,
9243 HOST_WIDE_INT bitpos
, int final
)
9245 unsigned int startbit
, endbit
;
9246 int intregs
, intoffset
;
9247 enum machine_mode mode
;
9249 /* Handle the situations where a float is taking up the first half
9250 of the GPR, and the other half is empty (typically due to
9251 alignment restrictions). We can detect this by a 8-byte-aligned
9252 int field, or by seeing that this is the final flush for this
9253 argument. Count the word and continue on. */
9254 if (cum
->floats_in_gpr
== 1
9255 && (cum
->intoffset
% 64 == 0
9256 || (cum
->intoffset
== -1 && final
)))
9259 cum
->floats_in_gpr
= 0;
9262 if (cum
->intoffset
== -1)
9265 intoffset
= cum
->intoffset
;
9266 cum
->intoffset
= -1;
9267 cum
->floats_in_gpr
= 0;
9269 if (intoffset
% BITS_PER_WORD
!= 0)
9271 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
9273 if (mode
== BLKmode
)
9275 /* We couldn't find an appropriate mode, which happens,
9276 e.g., in packed structs when there are 3 bytes to load.
9277 Back intoffset back to the beginning of the word in this
9279 intoffset
= intoffset
& -BITS_PER_WORD
;
9283 startbit
= intoffset
& -BITS_PER_WORD
;
9284 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
9285 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
9286 cum
->words
+= intregs
;
9287 /* words should be unsigned. */
9288 if ((unsigned)cum
->words
< (endbit
/BITS_PER_WORD
))
9290 int pad
= (endbit
/BITS_PER_WORD
) - cum
->words
;
9295 /* The darwin64 ABI calls for us to recurse down through structs,
9296 looking for elements passed in registers. Unfortunately, we have
9297 to track int register count here also because of misalignments
9298 in powerpc alignment mode. */
9301 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*cum
,
9303 HOST_WIDE_INT startbitpos
)
9307 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
9308 if (TREE_CODE (f
) == FIELD_DECL
)
9310 HOST_WIDE_INT bitpos
= startbitpos
;
9311 tree ftype
= TREE_TYPE (f
);
9312 enum machine_mode mode
;
9313 if (ftype
== error_mark_node
)
9315 mode
= TYPE_MODE (ftype
);
9317 if (DECL_SIZE (f
) != 0
9318 && tree_fits_uhwi_p (bit_position (f
)))
9319 bitpos
+= int_bit_position (f
);
9321 /* ??? FIXME: else assume zero offset. */
9323 if (TREE_CODE (ftype
) == RECORD_TYPE
)
9324 rs6000_darwin64_record_arg_advance_recurse (cum
, ftype
, bitpos
);
9325 else if (USE_FP_FOR_ARG_P (cum
, mode
))
9327 unsigned n_fpregs
= (GET_MODE_SIZE (mode
) + 7) >> 3;
9328 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
9329 cum
->fregno
+= n_fpregs
;
9330 /* Single-precision floats present a special problem for
9331 us, because they are smaller than an 8-byte GPR, and so
9332 the structure-packing rules combined with the standard
9333 varargs behavior mean that we want to pack float/float
9334 and float/int combinations into a single register's
9335 space. This is complicated by the arg advance flushing,
9336 which works on arbitrarily large groups of int-type
9340 if (cum
->floats_in_gpr
== 1)
9342 /* Two floats in a word; count the word and reset
9345 cum
->floats_in_gpr
= 0;
9347 else if (bitpos
% 64 == 0)
9349 /* A float at the beginning of an 8-byte word;
9350 count it and put off adjusting cum->words until
9351 we see if a arg advance flush is going to do it
9353 cum
->floats_in_gpr
++;
9357 /* The float is at the end of a word, preceded
9358 by integer fields, so the arg advance flush
9359 just above has already set cum->words and
9360 everything is taken care of. */
9364 cum
->words
+= n_fpregs
;
9366 else if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, 1))
9368 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
9372 else if (cum
->intoffset
== -1)
9373 cum
->intoffset
= bitpos
;
9377 /* Check for an item that needs to be considered specially under the darwin 64
9378 bit ABI. These are record types where the mode is BLK or the structure is
9381 rs6000_darwin64_struct_check_p (enum machine_mode mode
, const_tree type
)
9383 return rs6000_darwin64_abi
9384 && ((mode
== BLKmode
9385 && TREE_CODE (type
) == RECORD_TYPE
9386 && int_size_in_bytes (type
) > 0)
9387 || (type
&& TREE_CODE (type
) == RECORD_TYPE
9388 && int_size_in_bytes (type
) == 8)) ? 1 : 0;
9391 /* Update the data in CUM to advance over an argument
9392 of mode MODE and data type TYPE.
9393 (TYPE is null for libcalls where that information may not be available.)
9395 Note that for args passed by reference, function_arg will be called
9396 with MODE and TYPE set to that of the pointer to the arg, not the arg
9400 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
9401 const_tree type
, bool named
, int depth
)
9403 enum machine_mode elt_mode
;
9406 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
9408 /* Only tick off an argument if we're not recursing. */
9410 cum
->nargs_prototype
--;
9412 #ifdef HAVE_AS_GNU_ATTRIBUTE
9413 if (DEFAULT_ABI
== ABI_V4
9416 if (SCALAR_FLOAT_MODE_P (mode
))
9417 rs6000_passes_float
= true;
9418 else if (named
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
9419 rs6000_passes_vector
= true;
9420 else if (SPE_VECTOR_MODE (mode
)
9422 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
9423 rs6000_passes_vector
= true;
9427 if (TARGET_ALTIVEC_ABI
9428 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode
)
9429 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9430 && int_size_in_bytes (type
) == 16)))
9434 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
9436 cum
->vregno
+= n_elts
;
9438 if (!TARGET_ALTIVEC
)
9439 error ("cannot pass argument in vector register because"
9440 " altivec instructions are disabled, use -maltivec"
9443 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
9444 even if it is going to be passed in a vector register.
9445 Darwin does the same for variable-argument functions. */
9446 if (((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
9448 || (cum
->stdarg
&& DEFAULT_ABI
!= ABI_V4
))
9458 /* Vector parameters must be 16-byte aligned. In 32-bit
9459 mode this means we need to take into account the offset
9460 to the parameter save area. In 64-bit mode, they just
9461 have to start on an even word, since the parameter save
9462 area is 16-byte aligned. */
9464 align
= -(rs6000_parm_offset () + cum
->words
) & 3;
9466 align
= cum
->words
& 1;
9467 cum
->words
+= align
+ rs6000_arg_size (mode
, type
);
9469 if (TARGET_DEBUG_ARG
)
9471 fprintf (stderr
, "function_adv: words = %2d, align=%d, ",
9473 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s\n",
9474 cum
->nargs_prototype
, cum
->prototype
,
9475 GET_MODE_NAME (mode
));
9479 else if (TARGET_SPE_ABI
&& TARGET_SPE
&& SPE_VECTOR_MODE (mode
)
9481 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
9484 else if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
9486 int size
= int_size_in_bytes (type
);
9487 /* Variable sized types have size == -1 and are
9488 treated as if consisting entirely of ints.
9489 Pad to 16 byte boundary if needed. */
9490 if (TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
9491 && (cum
->words
% 2) != 0)
9493 /* For varargs, we can just go up by the size of the struct. */
9495 cum
->words
+= (size
+ 7) / 8;
9498 /* It is tempting to say int register count just goes up by
9499 sizeof(type)/8, but this is wrong in a case such as
9500 { int; double; int; } [powerpc alignment]. We have to
9501 grovel through the fields for these too. */
9503 cum
->floats_in_gpr
= 0;
9504 rs6000_darwin64_record_arg_advance_recurse (cum
, type
, 0);
9505 rs6000_darwin64_record_arg_advance_flush (cum
,
9506 size
* BITS_PER_UNIT
, 1);
9508 if (TARGET_DEBUG_ARG
)
9510 fprintf (stderr
, "function_adv: words = %2d, align=%d, size=%d",
9511 cum
->words
, TYPE_ALIGN (type
), size
);
9513 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
9514 cum
->nargs_prototype
, cum
->prototype
,
9515 GET_MODE_NAME (mode
));
9518 else if (DEFAULT_ABI
== ABI_V4
)
9520 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
9521 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
9522 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
9523 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
9524 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
9526 /* _Decimal128 must use an even/odd register pair. This assumes
9527 that the register number is odd when fregno is odd. */
9528 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
9531 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
9532 <= FP_ARG_V4_MAX_REG
)
9533 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
9536 cum
->fregno
= FP_ARG_V4_MAX_REG
+ 1;
9537 if (mode
== DFmode
|| mode
== TFmode
9538 || mode
== DDmode
|| mode
== TDmode
)
9539 cum
->words
+= cum
->words
& 1;
9540 cum
->words
+= rs6000_arg_size (mode
, type
);
9545 int n_words
= rs6000_arg_size (mode
, type
);
9546 int gregno
= cum
->sysv_gregno
;
9548 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
9549 (r7,r8) or (r9,r10). As does any other 2 word item such
9550 as complex int due to a historical mistake. */
9552 gregno
+= (1 - gregno
) & 1;
9554 /* Multi-reg args are not split between registers and stack. */
9555 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
9557 /* Long long and SPE vectors are aligned on the stack.
9558 So are other 2 word items such as complex int due to
9559 a historical mistake. */
9561 cum
->words
+= cum
->words
& 1;
9562 cum
->words
+= n_words
;
9565 /* Note: continuing to accumulate gregno past when we've started
9566 spilling to the stack indicates the fact that we've started
9567 spilling to the stack to expand_builtin_saveregs. */
9568 cum
->sysv_gregno
= gregno
+ n_words
;
9571 if (TARGET_DEBUG_ARG
)
9573 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
9574 cum
->words
, cum
->fregno
);
9575 fprintf (stderr
, "gregno = %2d, nargs = %4d, proto = %d, ",
9576 cum
->sysv_gregno
, cum
->nargs_prototype
, cum
->prototype
);
9577 fprintf (stderr
, "mode = %4s, named = %d\n",
9578 GET_MODE_NAME (mode
), named
);
9583 int n_words
= rs6000_arg_size (mode
, type
);
9584 int start_words
= cum
->words
;
9585 int align_words
= rs6000_parm_start (mode
, type
, start_words
);
9587 cum
->words
= align_words
+ n_words
;
9589 if (SCALAR_FLOAT_MODE_P (elt_mode
)
9590 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
9592 /* _Decimal128 must be passed in an even/odd float register pair.
9593 This assumes that the register number is odd when fregno is
9595 if (elt_mode
== TDmode
&& (cum
->fregno
% 2) == 1)
9597 cum
->fregno
+= n_elts
* ((GET_MODE_SIZE (elt_mode
) + 7) >> 3);
9600 if (TARGET_DEBUG_ARG
)
9602 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
9603 cum
->words
, cum
->fregno
);
9604 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s, ",
9605 cum
->nargs_prototype
, cum
->prototype
, GET_MODE_NAME (mode
));
9606 fprintf (stderr
, "named = %d, align = %d, depth = %d\n",
9607 named
, align_words
- start_words
, depth
);
9613 rs6000_function_arg_advance (cumulative_args_t cum
, enum machine_mode mode
,
9614 const_tree type
, bool named
)
9616 rs6000_function_arg_advance_1 (get_cumulative_args (cum
), mode
, type
, named
,
9621 spe_build_register_parallel (enum machine_mode mode
, int gregno
)
9628 r1
= gen_rtx_REG (DImode
, gregno
);
9629 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
9630 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, r1
));
9634 r1
= gen_rtx_REG (DImode
, gregno
);
9635 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
9636 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
9637 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
9638 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r3
));
9641 r1
= gen_rtx_REG (DImode
, gregno
);
9642 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
9643 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
9644 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
9645 r5
= gen_rtx_REG (DImode
, gregno
+ 4);
9646 r5
= gen_rtx_EXPR_LIST (VOIDmode
, r5
, GEN_INT (16));
9647 r7
= gen_rtx_REG (DImode
, gregno
+ 6);
9648 r7
= gen_rtx_EXPR_LIST (VOIDmode
, r7
, GEN_INT (24));
9649 return gen_rtx_PARALLEL (mode
, gen_rtvec (4, r1
, r3
, r5
, r7
));
9656 /* Determine where to put a SIMD argument on the SPE. */
9658 rs6000_spe_function_arg (const CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
9661 int gregno
= cum
->sysv_gregno
;
9663 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
9664 are passed and returned in a pair of GPRs for ABI compatibility. */
9665 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
9666 || mode
== DCmode
|| mode
== TCmode
))
9668 int n_words
= rs6000_arg_size (mode
, type
);
9670 /* Doubles go in an odd/even register pair (r5/r6, etc). */
9672 gregno
+= (1 - gregno
) & 1;
9674 /* Multi-reg args are not split between registers and stack. */
9675 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
9678 return spe_build_register_parallel (mode
, gregno
);
9682 int n_words
= rs6000_arg_size (mode
, type
);
9684 /* SPE vectors are put in odd registers. */
9685 if (n_words
== 2 && (gregno
& 1) == 0)
9688 if (gregno
+ n_words
- 1 <= GP_ARG_MAX_REG
)
9691 enum machine_mode m
= SImode
;
9693 r1
= gen_rtx_REG (m
, gregno
);
9694 r1
= gen_rtx_EXPR_LIST (m
, r1
, const0_rtx
);
9695 r2
= gen_rtx_REG (m
, gregno
+ 1);
9696 r2
= gen_rtx_EXPR_LIST (m
, r2
, GEN_INT (4));
9697 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
9704 if (gregno
<= GP_ARG_MAX_REG
)
9705 return gen_rtx_REG (mode
, gregno
);
9711 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
9712 structure between cum->intoffset and bitpos to integer registers. */
9715 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*cum
,
9716 HOST_WIDE_INT bitpos
, rtx rvec
[], int *k
)
9718 enum machine_mode mode
;
9720 unsigned int startbit
, endbit
;
9721 int this_regno
, intregs
, intoffset
;
9724 if (cum
->intoffset
== -1)
9727 intoffset
= cum
->intoffset
;
9728 cum
->intoffset
= -1;
9730 /* If this is the trailing part of a word, try to only load that
9731 much into the register. Otherwise load the whole register. Note
9732 that in the latter case we may pick up unwanted bits. It's not a
9733 problem at the moment but may wish to revisit. */
9735 if (intoffset
% BITS_PER_WORD
!= 0)
9737 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
9739 if (mode
== BLKmode
)
9741 /* We couldn't find an appropriate mode, which happens,
9742 e.g., in packed structs when there are 3 bytes to load.
9743 Back intoffset back to the beginning of the word in this
9745 intoffset
= intoffset
& -BITS_PER_WORD
;
9752 startbit
= intoffset
& -BITS_PER_WORD
;
9753 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
9754 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
9755 this_regno
= cum
->words
+ intoffset
/ BITS_PER_WORD
;
9757 if (intregs
> 0 && intregs
> GP_ARG_NUM_REG
- this_regno
)
9760 intregs
= MIN (intregs
, GP_ARG_NUM_REG
- this_regno
);
9764 intoffset
/= BITS_PER_UNIT
;
9767 regno
= GP_ARG_MIN_REG
+ this_regno
;
9768 reg
= gen_rtx_REG (mode
, regno
);
9770 gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
9773 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
9777 while (intregs
> 0);
9780 /* Recursive workhorse for the following. */
9783 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*cum
, const_tree type
,
9784 HOST_WIDE_INT startbitpos
, rtx rvec
[],
9789 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
9790 if (TREE_CODE (f
) == FIELD_DECL
)
9792 HOST_WIDE_INT bitpos
= startbitpos
;
9793 tree ftype
= TREE_TYPE (f
);
9794 enum machine_mode mode
;
9795 if (ftype
== error_mark_node
)
9797 mode
= TYPE_MODE (ftype
);
9799 if (DECL_SIZE (f
) != 0
9800 && tree_fits_uhwi_p (bit_position (f
)))
9801 bitpos
+= int_bit_position (f
);
9803 /* ??? FIXME: else assume zero offset. */
9805 if (TREE_CODE (ftype
) == RECORD_TYPE
)
9806 rs6000_darwin64_record_arg_recurse (cum
, ftype
, bitpos
, rvec
, k
);
9807 else if (cum
->named
&& USE_FP_FOR_ARG_P (cum
, mode
))
9809 unsigned n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
9813 case SCmode
: mode
= SFmode
; break;
9814 case DCmode
: mode
= DFmode
; break;
9815 case TCmode
: mode
= TFmode
; break;
9819 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
9820 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
9822 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
9823 && (mode
== TFmode
|| mode
== TDmode
));
9824 /* Long double or _Decimal128 split over regs and memory. */
9825 mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
: DFmode
;
9829 = gen_rtx_EXPR_LIST (VOIDmode
,
9830 gen_rtx_REG (mode
, cum
->fregno
++),
9831 GEN_INT (bitpos
/ BITS_PER_UNIT
));
9832 if (mode
== TFmode
|| mode
== TDmode
)
9835 else if (cum
->named
&& USE_ALTIVEC_FOR_ARG_P (cum
, mode
, 1))
9837 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
9839 = gen_rtx_EXPR_LIST (VOIDmode
,
9840 gen_rtx_REG (mode
, cum
->vregno
++),
9841 GEN_INT (bitpos
/ BITS_PER_UNIT
));
9843 else if (cum
->intoffset
== -1)
9844 cum
->intoffset
= bitpos
;
9848 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
9849 the register(s) to be used for each field and subfield of a struct
9850 being passed by value, along with the offset of where the
9851 register's value may be found in the block. FP fields go in FP
9852 register, vector fields go in vector registers, and everything
9853 else goes in int registers, packed as in memory.
9855 This code is also used for function return values. RETVAL indicates
9856 whether this is the case.
9858 Much of this is taken from the SPARC V9 port, which has a similar
9859 calling convention. */
9862 rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*orig_cum
, const_tree type
,
9863 bool named
, bool retval
)
9865 rtx rvec
[FIRST_PSEUDO_REGISTER
];
9866 int k
= 1, kbase
= 1;
9867 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
9868 /* This is a copy; modifications are not visible to our caller. */
9869 CUMULATIVE_ARGS copy_cum
= *orig_cum
;
9870 CUMULATIVE_ARGS
*cum
= ©_cum
;
9872 /* Pad to 16 byte boundary if needed. */
9873 if (!retval
&& TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
9874 && (cum
->words
% 2) != 0)
9881 /* Put entries into rvec[] for individual FP and vector fields, and
9882 for the chunks of memory that go in int regs. Note we start at
9883 element 1; 0 is reserved for an indication of using memory, and
9884 may or may not be filled in below. */
9885 rs6000_darwin64_record_arg_recurse (cum
, type
, /* startbit pos= */ 0, rvec
, &k
);
9886 rs6000_darwin64_record_arg_flush (cum
, typesize
* BITS_PER_UNIT
, rvec
, &k
);
9888 /* If any part of the struct went on the stack put all of it there.
9889 This hack is because the generic code for
9890 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
9891 parts of the struct are not at the beginning. */
9895 return NULL_RTX
; /* doesn't go in registers at all */
9897 rvec
[0] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
9899 if (k
> 1 || cum
->use_stack
)
9900 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (k
- kbase
, &rvec
[kbase
]));
9905 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
9908 rs6000_mixed_function_arg (enum machine_mode mode
, const_tree type
,
9913 rtx rvec
[GP_ARG_NUM_REG
+ 1];
9915 if (align_words
>= GP_ARG_NUM_REG
)
9918 n_units
= rs6000_arg_size (mode
, type
);
9920 /* Optimize the simple case where the arg fits in one gpr, except in
9921 the case of BLKmode due to assign_parms assuming that registers are
9922 BITS_PER_WORD wide. */
9924 || (n_units
== 1 && mode
!= BLKmode
))
9925 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
9928 if (align_words
+ n_units
> GP_ARG_NUM_REG
)
9929 /* Not all of the arg fits in gprs. Say that it goes in memory too,
9930 using a magic NULL_RTX component.
9931 This is not strictly correct. Only some of the arg belongs in
9932 memory, not all of it. However, the normal scheme using
9933 function_arg_partial_nregs can result in unusual subregs, eg.
9934 (subreg:SI (reg:DF) 4), which are not handled well. The code to
9935 store the whole arg to memory is often more efficient than code
9936 to store pieces, and we know that space is available in the right
9937 place for the whole arg. */
9938 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
9943 rtx r
= gen_rtx_REG (SImode
, GP_ARG_MIN_REG
+ align_words
);
9944 rtx off
= GEN_INT (i
++ * 4);
9945 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
9947 while (++align_words
< GP_ARG_NUM_REG
&& --n_units
!= 0);
9949 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
9952 /* We have an argument of MODE and TYPE that goes into FPRs or VRs,
9953 but must also be copied into the parameter save area starting at
9954 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
9955 to the GPRs and/or memory. Return the number of elements used. */
9958 rs6000_psave_function_arg (enum machine_mode mode
, const_tree type
,
9959 int align_words
, rtx
*rvec
)
9963 if (align_words
< GP_ARG_NUM_REG
)
9965 int n_words
= rs6000_arg_size (mode
, type
);
9967 if (align_words
+ n_words
> GP_ARG_NUM_REG
9969 || (TARGET_32BIT
&& TARGET_POWERPC64
))
9971 /* If this is partially on the stack, then we only
9972 include the portion actually in registers here. */
9973 enum machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
9976 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
9978 /* Not all of the arg fits in gprs. Say that it goes in memory
9979 too, using a magic NULL_RTX component. Also see comment in
9980 rs6000_mixed_function_arg for why the normal
9981 function_arg_partial_nregs scheme doesn't work in this case. */
9982 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
9987 rtx r
= gen_rtx_REG (rmode
, GP_ARG_MIN_REG
+ align_words
);
9988 rtx off
= GEN_INT (i
++ * GET_MODE_SIZE (rmode
));
9989 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
9991 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
9995 /* The whole arg fits in gprs. */
9996 rtx r
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
9997 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
10002 /* It's entirely in memory. */
10003 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
10009 /* RVEC is a vector of K components of an argument of mode MODE.
10010 Construct the final function_arg return value from it. */
10013 rs6000_finish_function_arg (enum machine_mode mode
, rtx
*rvec
, int k
)
10015 gcc_assert (k
>= 1);
10017 /* Avoid returning a PARALLEL in the trivial cases. */
10020 if (XEXP (rvec
[0], 0) == NULL_RTX
)
10023 if (GET_MODE (XEXP (rvec
[0], 0)) == mode
)
10024 return XEXP (rvec
[0], 0);
10027 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
10030 /* Determine where to put an argument to a function.
10031 Value is zero to push the argument on the stack,
10032 or a hard register in which to store the argument.
10034 MODE is the argument's machine mode.
10035 TYPE is the data type of the argument (as a tree).
10036 This is null for libcalls where that information may
10038 CUM is a variable of type CUMULATIVE_ARGS which gives info about
10039 the preceding args and about the function being called. It is
10040 not modified in this routine.
10041 NAMED is nonzero if this argument is a named parameter
10042 (otherwise it is an extra parameter matching an ellipsis).
10044 On RS/6000 the first eight words of non-FP are normally in registers
10045 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
10046 Under V.4, the first 8 FP args are in registers.
10048 If this is floating-point and no prototype is specified, we use
10049 both an FP and integer register (or possibly FP reg and stack). Library
10050 functions (when CALL_LIBCALL is set) always have the proper types for args,
10051 so we can pass the FP value just in one register. emit_library_function
10052 doesn't support PARALLEL anyway.
10054 Note that for args passed by reference, function_arg will be called
10055 with MODE and TYPE set to that of the pointer to the arg, not the arg
10059 rs6000_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
10060 const_tree type
, bool named
)
10062 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
10063 enum rs6000_abi abi
= DEFAULT_ABI
;
10064 enum machine_mode elt_mode
;
10067 /* Return a marker to indicate whether CR1 needs to set or clear the
10068 bit that V.4 uses to say fp args were passed in registers.
10069 Assume that we don't need the marker for software floating point,
10070 or compiler generated library calls. */
10071 if (mode
== VOIDmode
)
10074 && (cum
->call_cookie
& CALL_LIBCALL
) == 0
10076 || (cum
->nargs_prototype
< 0
10077 && (cum
->prototype
|| TARGET_NO_PROTOTYPE
))))
10079 /* For the SPE, we need to crxor CR6 always. */
10080 if (TARGET_SPE_ABI
)
10081 return GEN_INT (cum
->call_cookie
| CALL_V4_SET_FP_ARGS
);
10082 else if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
10083 return GEN_INT (cum
->call_cookie
10084 | ((cum
->fregno
== FP_ARG_MIN_REG
)
10085 ? CALL_V4_SET_FP_ARGS
10086 : CALL_V4_CLEAR_FP_ARGS
));
10089 return GEN_INT (cum
->call_cookie
& ~CALL_LIBCALL
);
10092 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
10094 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
10096 rtx rslt
= rs6000_darwin64_record_arg (cum
, type
, named
, /*retval= */false);
10097 if (rslt
!= NULL_RTX
)
10099 /* Else fall through to usual handling. */
10102 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
10104 rtx rvec
[GP_ARG_NUM_REG
+ AGGR_ARG_NUM_REG
+ 1];
10108 /* Do we also need to pass this argument in the parameter
10110 if (TARGET_64BIT
&& ! cum
->prototype
)
10112 int align_words
= (cum
->words
+ 1) & ~1;
10113 k
= rs6000_psave_function_arg (mode
, type
, align_words
, rvec
);
10116 /* Describe where this argument goes in the vector registers. */
10117 for (i
= 0; i
< n_elts
&& cum
->vregno
+ i
<= ALTIVEC_ARG_MAX_REG
; i
++)
10119 r
= gen_rtx_REG (elt_mode
, cum
->vregno
+ i
);
10120 off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
10121 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
10124 return rs6000_finish_function_arg (mode
, rvec
, k
);
10126 else if (TARGET_ALTIVEC_ABI
10127 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
10128 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
10129 && int_size_in_bytes (type
) == 16)))
10131 if (named
|| abi
== ABI_V4
)
10135 /* Vector parameters to varargs functions under AIX or Darwin
10136 get passed in memory and possibly also in GPRs. */
10137 int align
, align_words
, n_words
;
10138 enum machine_mode part_mode
;
10140 /* Vector parameters must be 16-byte aligned. In 32-bit
10141 mode this means we need to take into account the offset
10142 to the parameter save area. In 64-bit mode, they just
10143 have to start on an even word, since the parameter save
10144 area is 16-byte aligned. */
10146 align
= -(rs6000_parm_offset () + cum
->words
) & 3;
10148 align
= cum
->words
& 1;
10149 align_words
= cum
->words
+ align
;
10151 /* Out of registers? Memory, then. */
10152 if (align_words
>= GP_ARG_NUM_REG
)
10155 if (TARGET_32BIT
&& TARGET_POWERPC64
)
10156 return rs6000_mixed_function_arg (mode
, type
, align_words
);
10158 /* The vector value goes in GPRs. Only the part of the
10159 value in GPRs is reported here. */
10161 n_words
= rs6000_arg_size (mode
, type
);
10162 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
10163 /* Fortunately, there are only two possibilities, the value
10164 is either wholly in GPRs or half in GPRs and half not. */
10165 part_mode
= DImode
;
10167 return gen_rtx_REG (part_mode
, GP_ARG_MIN_REG
+ align_words
);
10170 else if (TARGET_SPE_ABI
&& TARGET_SPE
10171 && (SPE_VECTOR_MODE (mode
)
10172 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
10175 || mode
== TCmode
))))
10176 return rs6000_spe_function_arg (cum
, mode
, type
);
10178 else if (abi
== ABI_V4
)
10180 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
10181 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
10182 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
10183 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
10184 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
10186 /* _Decimal128 must use an even/odd register pair. This assumes
10187 that the register number is odd when fregno is odd. */
10188 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
10191 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
10192 <= FP_ARG_V4_MAX_REG
)
10193 return gen_rtx_REG (mode
, cum
->fregno
);
10199 int n_words
= rs6000_arg_size (mode
, type
);
10200 int gregno
= cum
->sysv_gregno
;
10202 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
10203 (r7,r8) or (r9,r10). As does any other 2 word item such
10204 as complex int due to a historical mistake. */
10206 gregno
+= (1 - gregno
) & 1;
10208 /* Multi-reg args are not split between registers and stack. */
10209 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
10212 if (TARGET_32BIT
&& TARGET_POWERPC64
)
10213 return rs6000_mixed_function_arg (mode
, type
,
10214 gregno
- GP_ARG_MIN_REG
);
10215 return gen_rtx_REG (mode
, gregno
);
10220 int align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
10222 /* _Decimal128 must be passed in an even/odd float register pair.
10223 This assumes that the register number is odd when fregno is odd. */
10224 if (elt_mode
== TDmode
&& (cum
->fregno
% 2) == 1)
10227 if (USE_FP_FOR_ARG_P (cum
, elt_mode
))
10229 rtx rvec
[GP_ARG_NUM_REG
+ AGGR_ARG_NUM_REG
+ 1];
10232 unsigned long n_fpreg
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
10234 /* Do we also need to pass this argument in the parameter
10236 if (type
&& (cum
->nargs_prototype
<= 0
10237 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
10238 && TARGET_XL_COMPAT
10239 && align_words
>= GP_ARG_NUM_REG
)))
10240 k
= rs6000_psave_function_arg (mode
, type
, align_words
, rvec
);
10242 /* Describe where this argument goes in the fprs. */
10243 for (i
= 0; i
< n_elts
10244 && cum
->fregno
+ i
* n_fpreg
<= FP_ARG_MAX_REG
; i
++)
10246 /* Check if the argument is split over registers and memory.
10247 This can only ever happen for long double or _Decimal128;
10248 complex types are handled via split_complex_arg. */
10249 enum machine_mode fmode
= elt_mode
;
10250 if (cum
->fregno
+ (i
+ 1) * n_fpreg
> FP_ARG_MAX_REG
+ 1)
10252 gcc_assert (fmode
== TFmode
|| fmode
== TDmode
);
10253 fmode
= DECIMAL_FLOAT_MODE_P (fmode
) ? DDmode
: DFmode
;
10256 r
= gen_rtx_REG (fmode
, cum
->fregno
+ i
* n_fpreg
);
10257 off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
10258 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
10261 return rs6000_finish_function_arg (mode
, rvec
, k
);
10263 else if (align_words
< GP_ARG_NUM_REG
)
10265 if (TARGET_32BIT
&& TARGET_POWERPC64
)
10266 return rs6000_mixed_function_arg (mode
, type
, align_words
);
10268 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
10275 /* For an arg passed partly in registers and partly in memory, this is
10276 the number of bytes passed in registers. For args passed entirely in
10277 registers or entirely in memory, zero. When an arg is described by a
10278 PARALLEL, perhaps using more than one register type, this function
10279 returns the number of bytes used by the first element of the PARALLEL. */
10282 rs6000_arg_partial_bytes (cumulative_args_t cum_v
, enum machine_mode mode
,
10283 tree type
, bool named
)
10285 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
10286 bool passed_in_gprs
= true;
10289 enum machine_mode elt_mode
;
10292 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
10294 if (DEFAULT_ABI
== ABI_V4
)
10297 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
10299 /* If we are passing this arg in the fixed parameter save area
10300 (gprs or memory) as well as VRs, we do not use the partial
10301 bytes mechanism; instead, rs6000_function_arg will return a
10302 PARALLEL including a memory element as necessary. */
10303 if (TARGET_64BIT
&& ! cum
->prototype
)
10306 /* Otherwise, we pass in VRs only. Check for partial copies. */
10307 passed_in_gprs
= false;
10308 if (cum
->vregno
+ n_elts
> ALTIVEC_ARG_MAX_REG
+ 1)
10309 ret
= (ALTIVEC_ARG_MAX_REG
+ 1 - cum
->vregno
) * 16;
10312 /* In this complicated case we just disable the partial_nregs code. */
10313 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
10316 align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
10318 if (USE_FP_FOR_ARG_P (cum
, elt_mode
))
10320 unsigned long n_fpreg
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
10322 /* If we are passing this arg in the fixed parameter save area
10323 (gprs or memory) as well as FPRs, we do not use the partial
10324 bytes mechanism; instead, rs6000_function_arg will return a
10325 PARALLEL including a memory element as necessary. */
10327 && (cum
->nargs_prototype
<= 0
10328 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
10329 && TARGET_XL_COMPAT
10330 && align_words
>= GP_ARG_NUM_REG
)))
10333 /* Otherwise, we pass in FPRs only. Check for partial copies. */
10334 passed_in_gprs
= false;
10335 if (cum
->fregno
+ n_elts
* n_fpreg
> FP_ARG_MAX_REG
+ 1)
10336 ret
= ((FP_ARG_MAX_REG
+ 1 - cum
->fregno
)
10337 * MIN (8, GET_MODE_SIZE (elt_mode
)));
10341 && align_words
< GP_ARG_NUM_REG
10342 && GP_ARG_NUM_REG
< align_words
+ rs6000_arg_size (mode
, type
))
10343 ret
= (GP_ARG_NUM_REG
- align_words
) * (TARGET_32BIT
? 4 : 8);
10345 if (ret
!= 0 && TARGET_DEBUG_ARG
)
10346 fprintf (stderr
, "rs6000_arg_partial_bytes: %d\n", ret
);
10351 /* A C expression that indicates when an argument must be passed by
10352 reference. If nonzero for an argument, a copy of that argument is
10353 made in memory and a pointer to the argument is passed instead of
10354 the argument itself. The pointer is passed in whatever way is
10355 appropriate for passing a pointer to that type.
10357 Under V.4, aggregates and long double are passed by reference.
10359 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
10360 reference unless the AltiVec vector extension ABI is in force.
10362 As an extension to all ABIs, variable sized types are passed by
10366 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
10367 enum machine_mode mode
, const_tree type
,
10368 bool named ATTRIBUTE_UNUSED
)
10370 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& mode
== TFmode
)
10372 if (TARGET_DEBUG_ARG
)
10373 fprintf (stderr
, "function_arg_pass_by_reference: V4 long double\n");
10380 if (DEFAULT_ABI
== ABI_V4
&& AGGREGATE_TYPE_P (type
))
10382 if (TARGET_DEBUG_ARG
)
10383 fprintf (stderr
, "function_arg_pass_by_reference: V4 aggregate\n");
10387 if (int_size_in_bytes (type
) < 0)
10389 if (TARGET_DEBUG_ARG
)
10390 fprintf (stderr
, "function_arg_pass_by_reference: variable size\n");
10394 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
10395 modes only exist for GCC vector types if -maltivec. */
10396 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
10398 if (TARGET_DEBUG_ARG
)
10399 fprintf (stderr
, "function_arg_pass_by_reference: AltiVec\n");
10403 /* Pass synthetic vectors in memory. */
10404 if (TREE_CODE (type
) == VECTOR_TYPE
10405 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
10407 static bool warned_for_pass_big_vectors
= false;
10408 if (TARGET_DEBUG_ARG
)
10409 fprintf (stderr
, "function_arg_pass_by_reference: synthetic vector\n");
10410 if (!warned_for_pass_big_vectors
)
10412 warning (0, "GCC vector passed by reference: "
10413 "non-standard ABI extension with no compatibility guarantee");
10414 warned_for_pass_big_vectors
= true;
10422 /* Process parameter of type TYPE after ARGS_SO_FAR parameters were
10423 already processes. Return true if the parameter must be passed
10424 (fully or partially) on the stack. */
10427 rs6000_parm_needs_stack (cumulative_args_t args_so_far
, tree type
)
10429 enum machine_mode mode
;
10433 /* Catch errors. */
10434 if (type
== NULL
|| type
== error_mark_node
)
10437 /* Handle types with no storage requirement. */
10438 if (TYPE_MODE (type
) == VOIDmode
)
10441 /* Handle complex types. */
10442 if (TREE_CODE (type
) == COMPLEX_TYPE
)
10443 return (rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (type
))
10444 || rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (type
)));
10446 /* Handle transparent aggregates. */
10447 if ((TREE_CODE (type
) == UNION_TYPE
|| TREE_CODE (type
) == RECORD_TYPE
)
10448 && TYPE_TRANSPARENT_AGGR (type
))
10449 type
= TREE_TYPE (first_field (type
));
10451 /* See if this arg was passed by invisible reference. */
10452 if (pass_by_reference (get_cumulative_args (args_so_far
),
10453 TYPE_MODE (type
), type
, true))
10454 type
= build_pointer_type (type
);
10456 /* Find mode as it is passed by the ABI. */
10457 unsignedp
= TYPE_UNSIGNED (type
);
10458 mode
= promote_mode (type
, TYPE_MODE (type
), &unsignedp
);
10460 /* If we must pass in stack, we need a stack. */
10461 if (rs6000_must_pass_in_stack (mode
, type
))
10464 /* If there is no incoming register, we need a stack. */
10465 entry_parm
= rs6000_function_arg (args_so_far
, mode
, type
, true);
10466 if (entry_parm
== NULL
)
10469 /* Likewise if we need to pass both in registers and on the stack. */
10470 if (GET_CODE (entry_parm
) == PARALLEL
10471 && XEXP (XVECEXP (entry_parm
, 0, 0), 0) == NULL_RTX
)
10474 /* Also true if we're partially in registers and partially not. */
10475 if (rs6000_arg_partial_bytes (args_so_far
, mode
, type
, true) != 0)
10478 /* Update info on where next arg arrives in registers. */
10479 rs6000_function_arg_advance (args_so_far
, mode
, type
, true);
10483 /* Return true if FUN has no prototype, has a variable argument
10484 list, or passes any parameter in memory. */
10487 rs6000_function_parms_need_stack (tree fun
)
10489 function_args_iterator args_iter
;
10491 CUMULATIVE_ARGS args_so_far_v
;
10492 cumulative_args_t args_so_far
;
10495 /* Must be a libcall, all of which only use reg parms. */
10498 fun
= TREE_TYPE (fun
);
10500 /* Varargs functions need the parameter save area. */
10501 if (!prototype_p (fun
) || stdarg_p (fun
))
10504 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v
, fun
, NULL_RTX
);
10505 args_so_far
= pack_cumulative_args (&args_so_far_v
);
10507 if (aggregate_value_p (TREE_TYPE (fun
), fun
))
10509 tree type
= build_pointer_type (TREE_TYPE (fun
));
10510 rs6000_parm_needs_stack (args_so_far
, type
);
10513 FOREACH_FUNCTION_ARGS (fun
, arg_type
, args_iter
)
10514 if (rs6000_parm_needs_stack (args_so_far
, arg_type
))
10520 /* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
10521 usually a constant depending on the ABI. However, in the ELFv2 ABI
10522 the register parameter area is optional when calling a function that
10523 has a prototype is scope, has no variable argument list, and passes
10524 all parameters in registers. */
10527 rs6000_reg_parm_stack_space (tree fun
)
10529 int reg_parm_stack_space
;
10531 switch (DEFAULT_ABI
)
10534 reg_parm_stack_space
= 0;
10539 reg_parm_stack_space
= TARGET_64BIT
? 64 : 32;
10543 /* ??? Recomputing this every time is a bit expensive. Is there
10544 a place to cache this information? */
10545 if (rs6000_function_parms_need_stack (fun
))
10546 reg_parm_stack_space
= TARGET_64BIT
? 64 : 32;
10548 reg_parm_stack_space
= 0;
10552 return reg_parm_stack_space
;
10556 rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
)
10559 enum machine_mode reg_mode
= TARGET_32BIT
? SImode
: DImode
;
10564 for (i
= 0; i
< nregs
; i
++)
10566 rtx tem
= adjust_address_nv (x
, reg_mode
, i
* GET_MODE_SIZE (reg_mode
));
10567 if (reload_completed
)
10569 if (! strict_memory_address_p (reg_mode
, XEXP (tem
, 0)))
10572 tem
= simplify_gen_subreg (reg_mode
, x
, BLKmode
,
10573 i
* GET_MODE_SIZE (reg_mode
));
10576 tem
= replace_equiv_address (tem
, XEXP (tem
, 0));
10580 emit_move_insn (tem
, gen_rtx_REG (reg_mode
, regno
+ i
));
10584 /* Perform any needed actions needed for a function that is receiving a
10585 variable number of arguments.
10589 MODE and TYPE are the mode and type of the current parameter.
10591 PRETEND_SIZE is a variable that should be set to the amount of stack
10592 that must be pushed by the prolog to pretend that our caller pushed
10595 Normally, this macro will push all remaining incoming registers on the
10596 stack and set PRETEND_SIZE to the length of the registers pushed. */
10599 setup_incoming_varargs (cumulative_args_t cum
, enum machine_mode mode
,
10600 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
10603 CUMULATIVE_ARGS next_cum
;
10604 int reg_size
= TARGET_32BIT
? 4 : 8;
10605 rtx save_area
= NULL_RTX
, mem
;
10606 int first_reg_offset
;
10607 alias_set_type set
;
10609 /* Skip the last named argument. */
10610 next_cum
= *get_cumulative_args (cum
);
10611 rs6000_function_arg_advance_1 (&next_cum
, mode
, type
, true, 0);
10613 if (DEFAULT_ABI
== ABI_V4
)
10615 first_reg_offset
= next_cum
.sysv_gregno
- GP_ARG_MIN_REG
;
10619 int gpr_reg_num
= 0, gpr_size
= 0, fpr_size
= 0;
10620 HOST_WIDE_INT offset
= 0;
10622 /* Try to optimize the size of the varargs save area.
10623 The ABI requires that ap.reg_save_area is doubleword
10624 aligned, but we don't need to allocate space for all
10625 the bytes, only those to which we actually will save
10627 if (cfun
->va_list_gpr_size
&& first_reg_offset
< GP_ARG_NUM_REG
)
10628 gpr_reg_num
= GP_ARG_NUM_REG
- first_reg_offset
;
10629 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
10630 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
10631 && cfun
->va_list_fpr_size
)
10634 fpr_size
= (next_cum
.fregno
- FP_ARG_MIN_REG
)
10635 * UNITS_PER_FP_WORD
;
10636 if (cfun
->va_list_fpr_size
10637 < FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
10638 fpr_size
+= cfun
->va_list_fpr_size
* UNITS_PER_FP_WORD
;
10640 fpr_size
+= (FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
10641 * UNITS_PER_FP_WORD
;
10645 offset
= -((first_reg_offset
* reg_size
) & ~7);
10646 if (!fpr_size
&& gpr_reg_num
> cfun
->va_list_gpr_size
)
10648 gpr_reg_num
= cfun
->va_list_gpr_size
;
10649 if (reg_size
== 4 && (first_reg_offset
& 1))
10652 gpr_size
= (gpr_reg_num
* reg_size
+ 7) & ~7;
10655 offset
= - (int) (next_cum
.fregno
- FP_ARG_MIN_REG
)
10656 * UNITS_PER_FP_WORD
10657 - (int) (GP_ARG_NUM_REG
* reg_size
);
10659 if (gpr_size
+ fpr_size
)
10662 = assign_stack_local (BLKmode
, gpr_size
+ fpr_size
, 64);
10663 gcc_assert (GET_CODE (reg_save_area
) == MEM
);
10664 reg_save_area
= XEXP (reg_save_area
, 0);
10665 if (GET_CODE (reg_save_area
) == PLUS
)
10667 gcc_assert (XEXP (reg_save_area
, 0)
10668 == virtual_stack_vars_rtx
);
10669 gcc_assert (GET_CODE (XEXP (reg_save_area
, 1)) == CONST_INT
);
10670 offset
+= INTVAL (XEXP (reg_save_area
, 1));
10673 gcc_assert (reg_save_area
== virtual_stack_vars_rtx
);
10676 cfun
->machine
->varargs_save_offset
= offset
;
10677 save_area
= plus_constant (Pmode
, virtual_stack_vars_rtx
, offset
);
10682 first_reg_offset
= next_cum
.words
;
10683 save_area
= virtual_incoming_args_rtx
;
10685 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
10686 first_reg_offset
+= rs6000_arg_size (TYPE_MODE (type
), type
);
10689 set
= get_varargs_alias_set ();
10690 if (! no_rtl
&& first_reg_offset
< GP_ARG_NUM_REG
10691 && cfun
->va_list_gpr_size
)
10693 int n_gpr
, nregs
= GP_ARG_NUM_REG
- first_reg_offset
;
10695 if (va_list_gpr_counter_field
)
10696 /* V4 va_list_gpr_size counts number of registers needed. */
10697 n_gpr
= cfun
->va_list_gpr_size
;
10699 /* char * va_list instead counts number of bytes needed. */
10700 n_gpr
= (cfun
->va_list_gpr_size
+ reg_size
- 1) / reg_size
;
10705 mem
= gen_rtx_MEM (BLKmode
,
10706 plus_constant (Pmode
, save_area
,
10707 first_reg_offset
* reg_size
));
10708 MEM_NOTRAP_P (mem
) = 1;
10709 set_mem_alias_set (mem
, set
);
10710 set_mem_align (mem
, BITS_PER_WORD
);
10712 rs6000_move_block_from_reg (GP_ARG_MIN_REG
+ first_reg_offset
, mem
,
10716 /* Save FP registers if needed. */
10717 if (DEFAULT_ABI
== ABI_V4
10718 && TARGET_HARD_FLOAT
&& TARGET_FPRS
10720 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
10721 && cfun
->va_list_fpr_size
)
10723 int fregno
= next_cum
.fregno
, nregs
;
10724 rtx cr1
= gen_rtx_REG (CCmode
, CR1_REGNO
);
10725 rtx lab
= gen_label_rtx ();
10726 int off
= (GP_ARG_NUM_REG
* reg_size
) + ((fregno
- FP_ARG_MIN_REG
)
10727 * UNITS_PER_FP_WORD
);
10730 (gen_rtx_SET (VOIDmode
,
10732 gen_rtx_IF_THEN_ELSE (VOIDmode
,
10733 gen_rtx_NE (VOIDmode
, cr1
,
10735 gen_rtx_LABEL_REF (VOIDmode
, lab
),
10739 fregno
<= FP_ARG_V4_MAX_REG
&& nregs
< cfun
->va_list_fpr_size
;
10740 fregno
++, off
+= UNITS_PER_FP_WORD
, nregs
++)
10742 mem
= gen_rtx_MEM ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
10744 plus_constant (Pmode
, save_area
, off
));
10745 MEM_NOTRAP_P (mem
) = 1;
10746 set_mem_alias_set (mem
, set
);
10747 set_mem_align (mem
, GET_MODE_ALIGNMENT (
10748 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
10749 ? DFmode
: SFmode
));
10750 emit_move_insn (mem
, gen_rtx_REG (
10751 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
10752 ? DFmode
: SFmode
, fregno
));
10759 /* Create the va_list data type. */
10762 rs6000_build_builtin_va_list (void)
10764 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
, record
, type_decl
;
10766 /* For AIX, prefer 'char *' because that's what the system
10767 header files like. */
10768 if (DEFAULT_ABI
!= ABI_V4
)
10769 return build_pointer_type (char_type_node
);
10771 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
10772 type_decl
= build_decl (BUILTINS_LOCATION
, TYPE_DECL
,
10773 get_identifier ("__va_list_tag"), record
);
10775 f_gpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("gpr"),
10776 unsigned_char_type_node
);
10777 f_fpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("fpr"),
10778 unsigned_char_type_node
);
10779 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
10780 every user file. */
10781 f_res
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
10782 get_identifier ("reserved"), short_unsigned_type_node
);
10783 f_ovf
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
10784 get_identifier ("overflow_arg_area"),
10786 f_sav
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
10787 get_identifier ("reg_save_area"),
10790 va_list_gpr_counter_field
= f_gpr
;
10791 va_list_fpr_counter_field
= f_fpr
;
10793 DECL_FIELD_CONTEXT (f_gpr
) = record
;
10794 DECL_FIELD_CONTEXT (f_fpr
) = record
;
10795 DECL_FIELD_CONTEXT (f_res
) = record
;
10796 DECL_FIELD_CONTEXT (f_ovf
) = record
;
10797 DECL_FIELD_CONTEXT (f_sav
) = record
;
10799 TYPE_STUB_DECL (record
) = type_decl
;
10800 TYPE_NAME (record
) = type_decl
;
10801 TYPE_FIELDS (record
) = f_gpr
;
10802 DECL_CHAIN (f_gpr
) = f_fpr
;
10803 DECL_CHAIN (f_fpr
) = f_res
;
10804 DECL_CHAIN (f_res
) = f_ovf
;
10805 DECL_CHAIN (f_ovf
) = f_sav
;
10807 layout_type (record
);
10809 /* The correct type is an array type of one element. */
10810 return build_array_type (record
, build_index_type (size_zero_node
));
10813 /* Implement va_start. */
10816 rs6000_va_start (tree valist
, rtx nextarg
)
10818 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
10819 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
10820 tree gpr
, fpr
, ovf
, sav
, t
;
10822 /* Only SVR4 needs something special. */
10823 if (DEFAULT_ABI
!= ABI_V4
)
10825 std_expand_builtin_va_start (valist
, nextarg
);
10829 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
10830 f_fpr
= DECL_CHAIN (f_gpr
);
10831 f_res
= DECL_CHAIN (f_fpr
);
10832 f_ovf
= DECL_CHAIN (f_res
);
10833 f_sav
= DECL_CHAIN (f_ovf
);
10835 valist
= build_simple_mem_ref (valist
);
10836 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
10837 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
10839 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
10841 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
10844 /* Count number of gp and fp argument registers used. */
10845 words
= crtl
->args
.info
.words
;
10846 n_gpr
= MIN (crtl
->args
.info
.sysv_gregno
- GP_ARG_MIN_REG
,
10848 n_fpr
= MIN (crtl
->args
.info
.fregno
- FP_ARG_MIN_REG
,
10851 if (TARGET_DEBUG_ARG
)
10852 fprintf (stderr
, "va_start: words = "HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
10853 HOST_WIDE_INT_PRINT_DEC
", n_fpr = "HOST_WIDE_INT_PRINT_DEC
"\n",
10854 words
, n_gpr
, n_fpr
);
10856 if (cfun
->va_list_gpr_size
)
10858 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
10859 build_int_cst (NULL_TREE
, n_gpr
));
10860 TREE_SIDE_EFFECTS (t
) = 1;
10861 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
10864 if (cfun
->va_list_fpr_size
)
10866 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
10867 build_int_cst (NULL_TREE
, n_fpr
));
10868 TREE_SIDE_EFFECTS (t
) = 1;
10869 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
10871 #ifdef HAVE_AS_GNU_ATTRIBUTE
10872 if (call_ABI_of_interest (cfun
->decl
))
10873 rs6000_passes_float
= true;
10877 /* Find the overflow area. */
10878 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
10880 t
= fold_build_pointer_plus_hwi (t
, words
* UNITS_PER_WORD
);
10881 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
10882 TREE_SIDE_EFFECTS (t
) = 1;
10883 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
10885 /* If there were no va_arg invocations, don't set up the register
10887 if (!cfun
->va_list_gpr_size
10888 && !cfun
->va_list_fpr_size
10889 && n_gpr
< GP_ARG_NUM_REG
10890 && n_fpr
< FP_ARG_V4_MAX_REG
)
10893 /* Find the register save area. */
10894 t
= make_tree (TREE_TYPE (sav
), virtual_stack_vars_rtx
);
10895 if (cfun
->machine
->varargs_save_offset
)
10896 t
= fold_build_pointer_plus_hwi (t
, cfun
->machine
->varargs_save_offset
);
10897 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
10898 TREE_SIDE_EFFECTS (t
) = 1;
10899 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
10902 /* Implement va_arg. */
10905 rs6000_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
10906 gimple_seq
*post_p
)
10908 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
10909 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
10910 int size
, rsize
, n_reg
, sav_ofs
, sav_scale
;
10911 tree lab_false
, lab_over
, addr
;
10913 tree ptrtype
= build_pointer_type_for_mode (type
, ptr_mode
, true);
10917 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
10919 t
= rs6000_gimplify_va_arg (valist
, ptrtype
, pre_p
, post_p
);
10920 return build_va_arg_indirect_ref (t
);
10923 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
10924 earlier version of gcc, with the property that it always applied alignment
10925 adjustments to the va-args (even for zero-sized types). The cheapest way
10926 to deal with this is to replicate the effect of the part of
10927 std_gimplify_va_arg_expr that carries out the align adjust, for the case
10929 We don't need to check for pass-by-reference because of the test above.
10930 We can return a simplifed answer, since we know there's no offset to add. */
10933 && rs6000_darwin64_abi
)
10934 || DEFAULT_ABI
== ABI_ELFv2
10935 || (DEFAULT_ABI
== ABI_AIX
&& !rs6000_compat_align_parm
))
10936 && integer_zerop (TYPE_SIZE (type
)))
10938 unsigned HOST_WIDE_INT align
, boundary
;
10939 tree valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
10940 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
10941 boundary
= rs6000_function_arg_boundary (TYPE_MODE (type
), type
);
10942 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
10943 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
10944 boundary
/= BITS_PER_UNIT
;
10945 if (boundary
> align
)
10948 /* This updates arg ptr by the amount that would be necessary
10949 to align the zero-sized (but not zero-alignment) item. */
10950 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
10951 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
10952 gimplify_and_add (t
, pre_p
);
10954 t
= fold_convert (sizetype
, valist_tmp
);
10955 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
10956 fold_convert (TREE_TYPE (valist
),
10957 fold_build2 (BIT_AND_EXPR
, sizetype
, t
,
10958 size_int (-boundary
))));
10959 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
10960 gimplify_and_add (t
, pre_p
);
10962 /* Since it is zero-sized there's no increment for the item itself. */
10963 valist_tmp
= fold_convert (build_pointer_type (type
), valist_tmp
);
10964 return build_va_arg_indirect_ref (valist_tmp
);
10967 if (DEFAULT_ABI
!= ABI_V4
)
10969 if (targetm
.calls
.split_complex_arg
&& TREE_CODE (type
) == COMPLEX_TYPE
)
10971 tree elem_type
= TREE_TYPE (type
);
10972 enum machine_mode elem_mode
= TYPE_MODE (elem_type
);
10973 int elem_size
= GET_MODE_SIZE (elem_mode
);
10975 if (elem_size
< UNITS_PER_WORD
)
10977 tree real_part
, imag_part
;
10978 gimple_seq post
= NULL
;
10980 real_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
10982 /* Copy the value into a temporary, lest the formal temporary
10983 be reused out from under us. */
10984 real_part
= get_initialized_tmp_var (real_part
, pre_p
, &post
);
10985 gimple_seq_add_seq (pre_p
, post
);
10987 imag_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
10990 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
10994 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
10997 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
10998 f_fpr
= DECL_CHAIN (f_gpr
);
10999 f_res
= DECL_CHAIN (f_fpr
);
11000 f_ovf
= DECL_CHAIN (f_res
);
11001 f_sav
= DECL_CHAIN (f_ovf
);
11003 valist
= build_va_arg_indirect_ref (valist
);
11004 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
11005 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
11007 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
11009 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
11012 size
= int_size_in_bytes (type
);
11013 rsize
= (size
+ 3) / 4;
11016 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
11017 && ((TARGET_SINGLE_FLOAT
&& TYPE_MODE (type
) == SFmode
)
11018 || (TARGET_DOUBLE_FLOAT
11019 && (TYPE_MODE (type
) == DFmode
11020 || TYPE_MODE (type
) == TFmode
11021 || TYPE_MODE (type
) == SDmode
11022 || TYPE_MODE (type
) == DDmode
11023 || TYPE_MODE (type
) == TDmode
))))
11025 /* FP args go in FP registers, if present. */
11027 n_reg
= (size
+ 7) / 8;
11028 sav_ofs
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4) * 4;
11029 sav_scale
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4);
11030 if (TYPE_MODE (type
) != SFmode
&& TYPE_MODE (type
) != SDmode
)
11035 /* Otherwise into GP registers. */
11044 /* Pull the value out of the saved registers.... */
11047 addr
= create_tmp_var (ptr_type_node
, "addr");
11049 /* AltiVec vectors never go in registers when -mabi=altivec. */
11050 if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
11054 lab_false
= create_artificial_label (input_location
);
11055 lab_over
= create_artificial_label (input_location
);
11057 /* Long long and SPE vectors are aligned in the registers.
11058 As are any other 2 gpr item such as complex int due to a
11059 historical mistake. */
11061 if (n_reg
== 2 && reg
== gpr
)
11064 u
= build2 (BIT_AND_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
11065 build_int_cst (TREE_TYPE (reg
), n_reg
- 1));
11066 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
),
11067 unshare_expr (reg
), u
);
11069 /* _Decimal128 is passed in even/odd fpr pairs; the stored
11070 reg number is 0 for f1, so we want to make it odd. */
11071 else if (reg
== fpr
&& TYPE_MODE (type
) == TDmode
)
11073 t
= build2 (BIT_IOR_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
11074 build_int_cst (TREE_TYPE (reg
), 1));
11075 u
= build2 (MODIFY_EXPR
, void_type_node
, unshare_expr (reg
), t
);
11078 t
= fold_convert (TREE_TYPE (reg
), size_int (8 - n_reg
+ 1));
11079 t
= build2 (GE_EXPR
, boolean_type_node
, u
, t
);
11080 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
11081 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
11082 gimplify_and_add (t
, pre_p
);
11086 t
= fold_build_pointer_plus_hwi (sav
, sav_ofs
);
11088 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
11089 build_int_cst (TREE_TYPE (reg
), n_reg
));
11090 u
= fold_convert (sizetype
, u
);
11091 u
= build2 (MULT_EXPR
, sizetype
, u
, size_int (sav_scale
));
11092 t
= fold_build_pointer_plus (t
, u
);
11094 /* _Decimal32 varargs are located in the second word of the 64-bit
11095 FP register for 32-bit binaries. */
11096 if (!TARGET_POWERPC64
11097 && TARGET_HARD_FLOAT
&& TARGET_FPRS
11098 && TYPE_MODE (type
) == SDmode
)
11099 t
= fold_build_pointer_plus_hwi (t
, size
);
11101 gimplify_assign (addr
, t
, pre_p
);
11103 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
11105 stmt
= gimple_build_label (lab_false
);
11106 gimple_seq_add_stmt (pre_p
, stmt
);
11108 if ((n_reg
== 2 && !regalign
) || n_reg
> 2)
11110 /* Ensure that we don't find any more args in regs.
11111 Alignment has taken care of for special cases. */
11112 gimplify_assign (reg
, build_int_cst (TREE_TYPE (reg
), 8), pre_p
);
11116 /* ... otherwise out of the overflow area. */
11118 /* Care for on-stack alignment if needed. */
11122 t
= fold_build_pointer_plus_hwi (t
, align
- 1);
11123 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
11124 build_int_cst (TREE_TYPE (t
), -align
));
11126 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
11128 gimplify_assign (unshare_expr (addr
), t
, pre_p
);
11130 t
= fold_build_pointer_plus_hwi (t
, size
);
11131 gimplify_assign (unshare_expr (ovf
), t
, pre_p
);
11135 stmt
= gimple_build_label (lab_over
);
11136 gimple_seq_add_stmt (pre_p
, stmt
);
11139 if (STRICT_ALIGNMENT
11140 && (TYPE_ALIGN (type
)
11141 > (unsigned) BITS_PER_UNIT
* (align
< 4 ? 4 : align
)))
11143 /* The value (of type complex double, for example) may not be
11144 aligned in memory in the saved registers, so copy via a
11145 temporary. (This is the same code as used for SPARC.) */
11146 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
11147 tree dest_addr
= build_fold_addr_expr (tmp
);
11149 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
11150 3, dest_addr
, addr
, size_int (rsize
* 4));
11152 gimplify_and_add (copy
, pre_p
);
11156 addr
= fold_convert (ptrtype
, addr
);
11157 return build_va_arg_indirect_ref (addr
);
11163 def_builtin (const char *name
, tree type
, enum rs6000_builtins code
)
11166 unsigned classify
= rs6000_builtin_info
[(int)code
].attr
;
11167 const char *attr_string
= "";
11169 gcc_assert (name
!= NULL
);
11170 gcc_assert (IN_RANGE ((int)code
, 0, (int)RS6000_BUILTIN_COUNT
));
11172 if (rs6000_builtin_decls
[(int)code
])
11173 fatal_error ("internal error: builtin function %s already processed", name
);
11175 rs6000_builtin_decls
[(int)code
] = t
=
11176 add_builtin_function (name
, type
, (int)code
, BUILT_IN_MD
, NULL
, NULL_TREE
);
11178 /* Set any special attributes. */
11179 if ((classify
& RS6000_BTC_CONST
) != 0)
11181 /* const function, function only depends on the inputs. */
11182 TREE_READONLY (t
) = 1;
11183 TREE_NOTHROW (t
) = 1;
11184 attr_string
= ", pure";
11186 else if ((classify
& RS6000_BTC_PURE
) != 0)
11188 /* pure function, function can read global memory, but does not set any
11190 DECL_PURE_P (t
) = 1;
11191 TREE_NOTHROW (t
) = 1;
11192 attr_string
= ", const";
11194 else if ((classify
& RS6000_BTC_FP
) != 0)
11196 /* Function is a math function. If rounding mode is on, then treat the
11197 function as not reading global memory, but it can have arbitrary side
11198 effects. If it is off, then assume the function is a const function.
11199 This mimics the ATTR_MATHFN_FPROUNDING attribute in
11200 builtin-attribute.def that is used for the math functions. */
11201 TREE_NOTHROW (t
) = 1;
11202 if (flag_rounding_math
)
11204 DECL_PURE_P (t
) = 1;
11205 DECL_IS_NOVOPS (t
) = 1;
11206 attr_string
= ", fp, pure";
11210 TREE_READONLY (t
) = 1;
11211 attr_string
= ", fp, const";
11214 else if ((classify
& RS6000_BTC_ATTR_MASK
) != 0)
11215 gcc_unreachable ();
11217 if (TARGET_DEBUG_BUILTIN
)
11218 fprintf (stderr
, "rs6000_builtin, code = %4d, %s%s\n",
11219 (int)code
, name
, attr_string
);
11222 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
11224 #undef RS6000_BUILTIN_1
11225 #undef RS6000_BUILTIN_2
11226 #undef RS6000_BUILTIN_3
11227 #undef RS6000_BUILTIN_A
11228 #undef RS6000_BUILTIN_D
11229 #undef RS6000_BUILTIN_E
11230 #undef RS6000_BUILTIN_H
11231 #undef RS6000_BUILTIN_P
11232 #undef RS6000_BUILTIN_Q
11233 #undef RS6000_BUILTIN_S
11234 #undef RS6000_BUILTIN_X
11236 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11237 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11238 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
11239 { MASK, ICODE, NAME, ENUM },
11241 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11242 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11243 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11244 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11245 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11246 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11247 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11248 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11250 static const struct builtin_description bdesc_3arg
[] =
11252 #include "rs6000-builtin.def"
11255 /* DST operations: void foo (void *, const int, const char). */
11257 #undef RS6000_BUILTIN_1
11258 #undef RS6000_BUILTIN_2
11259 #undef RS6000_BUILTIN_3
11260 #undef RS6000_BUILTIN_A
11261 #undef RS6000_BUILTIN_D
11262 #undef RS6000_BUILTIN_E
11263 #undef RS6000_BUILTIN_H
11264 #undef RS6000_BUILTIN_P
11265 #undef RS6000_BUILTIN_Q
11266 #undef RS6000_BUILTIN_S
11267 #undef RS6000_BUILTIN_X
11269 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11270 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11271 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11272 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11273 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
11274 { MASK, ICODE, NAME, ENUM },
11276 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11277 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11278 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11279 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11280 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11281 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11283 static const struct builtin_description bdesc_dst
[] =
11285 #include "rs6000-builtin.def"
11288 /* Simple binary operations: VECc = foo (VECa, VECb). */
11290 #undef RS6000_BUILTIN_1
11291 #undef RS6000_BUILTIN_2
11292 #undef RS6000_BUILTIN_3
11293 #undef RS6000_BUILTIN_A
11294 #undef RS6000_BUILTIN_D
11295 #undef RS6000_BUILTIN_E
11296 #undef RS6000_BUILTIN_H
11297 #undef RS6000_BUILTIN_P
11298 #undef RS6000_BUILTIN_Q
11299 #undef RS6000_BUILTIN_S
11300 #undef RS6000_BUILTIN_X
11302 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11303 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
11304 { MASK, ICODE, NAME, ENUM },
11306 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11307 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11308 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11309 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11310 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11311 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11312 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11313 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11314 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11316 static const struct builtin_description bdesc_2arg
[] =
11318 #include "rs6000-builtin.def"
11321 #undef RS6000_BUILTIN_1
11322 #undef RS6000_BUILTIN_2
11323 #undef RS6000_BUILTIN_3
11324 #undef RS6000_BUILTIN_A
11325 #undef RS6000_BUILTIN_D
11326 #undef RS6000_BUILTIN_E
11327 #undef RS6000_BUILTIN_H
11328 #undef RS6000_BUILTIN_P
11329 #undef RS6000_BUILTIN_Q
11330 #undef RS6000_BUILTIN_S
11331 #undef RS6000_BUILTIN_X
11333 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11334 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11335 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11336 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11337 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11338 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11339 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11340 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
11341 { MASK, ICODE, NAME, ENUM },
11343 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11344 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11345 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11347 /* AltiVec predicates. */
11349 static const struct builtin_description bdesc_altivec_preds
[] =
11351 #include "rs6000-builtin.def"
11354 /* SPE predicates. */
11355 #undef RS6000_BUILTIN_1
11356 #undef RS6000_BUILTIN_2
11357 #undef RS6000_BUILTIN_3
11358 #undef RS6000_BUILTIN_A
11359 #undef RS6000_BUILTIN_D
11360 #undef RS6000_BUILTIN_E
11361 #undef RS6000_BUILTIN_H
11362 #undef RS6000_BUILTIN_P
11363 #undef RS6000_BUILTIN_Q
11364 #undef RS6000_BUILTIN_S
11365 #undef RS6000_BUILTIN_X
11367 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11368 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11369 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11370 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11371 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11372 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11373 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11374 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11375 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11376 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
11377 { MASK, ICODE, NAME, ENUM },
11379 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11381 static const struct builtin_description bdesc_spe_predicates
[] =
11383 #include "rs6000-builtin.def"
11386 /* SPE evsel predicates. */
11387 #undef RS6000_BUILTIN_1
11388 #undef RS6000_BUILTIN_2
11389 #undef RS6000_BUILTIN_3
11390 #undef RS6000_BUILTIN_A
11391 #undef RS6000_BUILTIN_D
11392 #undef RS6000_BUILTIN_E
11393 #undef RS6000_BUILTIN_H
11394 #undef RS6000_BUILTIN_P
11395 #undef RS6000_BUILTIN_Q
11396 #undef RS6000_BUILTIN_S
11397 #undef RS6000_BUILTIN_X
11399 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11400 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11401 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11402 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11403 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11404 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
11405 { MASK, ICODE, NAME, ENUM },
11407 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11408 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11409 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11410 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11411 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11413 static const struct builtin_description bdesc_spe_evsel
[] =
11415 #include "rs6000-builtin.def"
11418 /* PAIRED predicates. */
11419 #undef RS6000_BUILTIN_1
11420 #undef RS6000_BUILTIN_2
11421 #undef RS6000_BUILTIN_3
11422 #undef RS6000_BUILTIN_A
11423 #undef RS6000_BUILTIN_D
11424 #undef RS6000_BUILTIN_E
11425 #undef RS6000_BUILTIN_H
11426 #undef RS6000_BUILTIN_P
11427 #undef RS6000_BUILTIN_Q
11428 #undef RS6000_BUILTIN_S
11429 #undef RS6000_BUILTIN_X
11431 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11432 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11433 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11434 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11435 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11436 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11437 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11438 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11439 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
11440 { MASK, ICODE, NAME, ENUM },
11442 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11443 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11445 static const struct builtin_description bdesc_paired_preds
[] =
11447 #include "rs6000-builtin.def"
11450 /* ABS* operations. */
11452 #undef RS6000_BUILTIN_1
11453 #undef RS6000_BUILTIN_2
11454 #undef RS6000_BUILTIN_3
11455 #undef RS6000_BUILTIN_A
11456 #undef RS6000_BUILTIN_D
11457 #undef RS6000_BUILTIN_E
11458 #undef RS6000_BUILTIN_H
11459 #undef RS6000_BUILTIN_P
11460 #undef RS6000_BUILTIN_Q
11461 #undef RS6000_BUILTIN_S
11462 #undef RS6000_BUILTIN_X
11464 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11465 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11466 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11467 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
11468 { MASK, ICODE, NAME, ENUM },
11470 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11471 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11472 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11473 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11474 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11475 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11476 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11478 static const struct builtin_description bdesc_abs
[] =
11480 #include "rs6000-builtin.def"
11483 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
11486 #undef RS6000_BUILTIN_1
11487 #undef RS6000_BUILTIN_2
11488 #undef RS6000_BUILTIN_3
11489 #undef RS6000_BUILTIN_A
11490 #undef RS6000_BUILTIN_D
11491 #undef RS6000_BUILTIN_E
11492 #undef RS6000_BUILTIN_H
11493 #undef RS6000_BUILTIN_P
11494 #undef RS6000_BUILTIN_Q
11495 #undef RS6000_BUILTIN_S
11496 #undef RS6000_BUILTIN_X
11498 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
11499 { MASK, ICODE, NAME, ENUM },
11501 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11502 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11503 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11504 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11505 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11506 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11507 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11508 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11509 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11510 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11512 static const struct builtin_description bdesc_1arg
[] =
11514 #include "rs6000-builtin.def"
11517 /* HTM builtins. */
11518 #undef RS6000_BUILTIN_1
11519 #undef RS6000_BUILTIN_2
11520 #undef RS6000_BUILTIN_3
11521 #undef RS6000_BUILTIN_A
11522 #undef RS6000_BUILTIN_D
11523 #undef RS6000_BUILTIN_E
11524 #undef RS6000_BUILTIN_H
11525 #undef RS6000_BUILTIN_P
11526 #undef RS6000_BUILTIN_Q
11527 #undef RS6000_BUILTIN_S
11528 #undef RS6000_BUILTIN_X
11530 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11531 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11532 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11533 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11534 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11535 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11536 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
11537 { MASK, ICODE, NAME, ENUM },
11539 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11540 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11541 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11542 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11544 static const struct builtin_description bdesc_htm
[] =
11546 #include "rs6000-builtin.def"
11549 #undef RS6000_BUILTIN_1
11550 #undef RS6000_BUILTIN_2
11551 #undef RS6000_BUILTIN_3
11552 #undef RS6000_BUILTIN_A
11553 #undef RS6000_BUILTIN_D
11554 #undef RS6000_BUILTIN_E
11555 #undef RS6000_BUILTIN_H
11556 #undef RS6000_BUILTIN_P
11557 #undef RS6000_BUILTIN_Q
11558 #undef RS6000_BUILTIN_S
11560 /* Return true if a builtin function is overloaded. */
11562 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode
)
11564 return (rs6000_builtin_info
[(int)fncode
].attr
& RS6000_BTC_OVERLOADED
) != 0;
11567 /* Expand an expression EXP that calls a builtin without arguments. */
11569 rs6000_expand_zeroop_builtin (enum insn_code icode
, rtx target
)
11572 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11574 if (icode
== CODE_FOR_nothing
)
11575 /* Builtin not supported on this processor. */
11579 || GET_MODE (target
) != tmode
11580 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11581 target
= gen_reg_rtx (tmode
);
11583 pat
= GEN_FCN (icode
) (target
);
11593 rs6000_expand_mtfsf_builtin (enum insn_code icode
, tree exp
)
11596 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11597 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11598 rtx op0
= expand_normal (arg0
);
11599 rtx op1
= expand_normal (arg1
);
11600 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
11601 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
11603 if (icode
== CODE_FOR_nothing
)
11604 /* Builtin not supported on this processor. */
11607 /* If we got invalid arguments bail out before generating bad rtl. */
11608 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11611 if (GET_CODE (op0
) != CONST_INT
11612 || INTVAL (op0
) > 255
11613 || INTVAL (op0
) < 0)
11615 error ("argument 1 must be an 8-bit field value");
11619 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
11620 op0
= copy_to_mode_reg (mode0
, op0
);
11622 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
11623 op1
= copy_to_mode_reg (mode1
, op1
);
11625 pat
= GEN_FCN (icode
) (op0
, op1
);
11635 rs6000_expand_unop_builtin (enum insn_code icode
, tree exp
, rtx target
)
11638 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11639 rtx op0
= expand_normal (arg0
);
11640 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11641 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11643 if (icode
== CODE_FOR_nothing
)
11644 /* Builtin not supported on this processor. */
11647 /* If we got invalid arguments bail out before generating bad rtl. */
11648 if (arg0
== error_mark_node
)
11651 if (icode
== CODE_FOR_altivec_vspltisb
11652 || icode
== CODE_FOR_altivec_vspltish
11653 || icode
== CODE_FOR_altivec_vspltisw
11654 || icode
== CODE_FOR_spe_evsplatfi
11655 || icode
== CODE_FOR_spe_evsplati
)
11657 /* Only allow 5-bit *signed* literals. */
11658 if (GET_CODE (op0
) != CONST_INT
11659 || INTVAL (op0
) > 15
11660 || INTVAL (op0
) < -16)
11662 error ("argument 1 must be a 5-bit signed literal");
11668 || GET_MODE (target
) != tmode
11669 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11670 target
= gen_reg_rtx (tmode
);
11672 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11673 op0
= copy_to_mode_reg (mode0
, op0
);
11675 pat
= GEN_FCN (icode
) (target
, op0
);
11684 altivec_expand_abs_builtin (enum insn_code icode
, tree exp
, rtx target
)
11686 rtx pat
, scratch1
, scratch2
;
11687 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11688 rtx op0
= expand_normal (arg0
);
11689 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11690 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11692 /* If we have invalid arguments, bail out before generating bad rtl. */
11693 if (arg0
== error_mark_node
)
11697 || GET_MODE (target
) != tmode
11698 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11699 target
= gen_reg_rtx (tmode
);
11701 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11702 op0
= copy_to_mode_reg (mode0
, op0
);
11704 scratch1
= gen_reg_rtx (mode0
);
11705 scratch2
= gen_reg_rtx (mode0
);
11707 pat
= GEN_FCN (icode
) (target
, op0
, scratch1
, scratch2
);
11716 rs6000_expand_binop_builtin (enum insn_code icode
, tree exp
, rtx target
)
11719 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11720 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11721 rtx op0
= expand_normal (arg0
);
11722 rtx op1
= expand_normal (arg1
);
11723 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11724 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11725 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
11727 if (icode
== CODE_FOR_nothing
)
11728 /* Builtin not supported on this processor. */
11731 /* If we got invalid arguments bail out before generating bad rtl. */
11732 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11735 if (icode
== CODE_FOR_altivec_vcfux
11736 || icode
== CODE_FOR_altivec_vcfsx
11737 || icode
== CODE_FOR_altivec_vctsxs
11738 || icode
== CODE_FOR_altivec_vctuxs
11739 || icode
== CODE_FOR_altivec_vspltb
11740 || icode
== CODE_FOR_altivec_vsplth
11741 || icode
== CODE_FOR_altivec_vspltw
11742 || icode
== CODE_FOR_spe_evaddiw
11743 || icode
== CODE_FOR_spe_evldd
11744 || icode
== CODE_FOR_spe_evldh
11745 || icode
== CODE_FOR_spe_evldw
11746 || icode
== CODE_FOR_spe_evlhhesplat
11747 || icode
== CODE_FOR_spe_evlhhossplat
11748 || icode
== CODE_FOR_spe_evlhhousplat
11749 || icode
== CODE_FOR_spe_evlwhe
11750 || icode
== CODE_FOR_spe_evlwhos
11751 || icode
== CODE_FOR_spe_evlwhou
11752 || icode
== CODE_FOR_spe_evlwhsplat
11753 || icode
== CODE_FOR_spe_evlwwsplat
11754 || icode
== CODE_FOR_spe_evrlwi
11755 || icode
== CODE_FOR_spe_evslwi
11756 || icode
== CODE_FOR_spe_evsrwis
11757 || icode
== CODE_FOR_spe_evsubifw
11758 || icode
== CODE_FOR_spe_evsrwiu
)
11760 /* Only allow 5-bit unsigned literals. */
11762 if (TREE_CODE (arg1
) != INTEGER_CST
11763 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
11765 error ("argument 2 must be a 5-bit unsigned literal");
11771 || GET_MODE (target
) != tmode
11772 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11773 target
= gen_reg_rtx (tmode
);
11775 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11776 op0
= copy_to_mode_reg (mode0
, op0
);
11777 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11778 op1
= copy_to_mode_reg (mode1
, op1
);
11780 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
11789 altivec_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
11792 tree cr6_form
= CALL_EXPR_ARG (exp
, 0);
11793 tree arg0
= CALL_EXPR_ARG (exp
, 1);
11794 tree arg1
= CALL_EXPR_ARG (exp
, 2);
11795 rtx op0
= expand_normal (arg0
);
11796 rtx op1
= expand_normal (arg1
);
11797 enum machine_mode tmode
= SImode
;
11798 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11799 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
11802 if (TREE_CODE (cr6_form
) != INTEGER_CST
)
11804 error ("argument 1 of __builtin_altivec_predicate must be a constant");
11808 cr6_form_int
= TREE_INT_CST_LOW (cr6_form
);
11810 gcc_assert (mode0
== mode1
);
11812 /* If we have invalid arguments, bail out before generating bad rtl. */
11813 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11817 || GET_MODE (target
) != tmode
11818 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11819 target
= gen_reg_rtx (tmode
);
11821 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11822 op0
= copy_to_mode_reg (mode0
, op0
);
11823 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11824 op1
= copy_to_mode_reg (mode1
, op1
);
11826 scratch
= gen_reg_rtx (mode0
);
11828 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
11833 /* The vec_any* and vec_all* predicates use the same opcodes for two
11834 different operations, but the bits in CR6 will be different
11835 depending on what information we want. So we have to play tricks
11836 with CR6 to get the right bits out.
11838 If you think this is disgusting, look at the specs for the
11839 AltiVec predicates. */
11841 switch (cr6_form_int
)
11844 emit_insn (gen_cr6_test_for_zero (target
));
11847 emit_insn (gen_cr6_test_for_zero_reverse (target
));
11850 emit_insn (gen_cr6_test_for_lt (target
));
11853 emit_insn (gen_cr6_test_for_lt_reverse (target
));
11856 error ("argument 1 of __builtin_altivec_predicate is out of range");
11864 paired_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
)
11867 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11868 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11869 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11870 enum machine_mode mode0
= Pmode
;
11871 enum machine_mode mode1
= Pmode
;
11872 rtx op0
= expand_normal (arg0
);
11873 rtx op1
= expand_normal (arg1
);
11875 if (icode
== CODE_FOR_nothing
)
11876 /* Builtin not supported on this processor. */
11879 /* If we got invalid arguments bail out before generating bad rtl. */
11880 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11884 || GET_MODE (target
) != tmode
11885 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11886 target
= gen_reg_rtx (tmode
);
11888 op1
= copy_to_mode_reg (mode1
, op1
);
11890 if (op0
== const0_rtx
)
11892 addr
= gen_rtx_MEM (tmode
, op1
);
11896 op0
= copy_to_mode_reg (mode0
, op0
);
11897 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
11900 pat
= GEN_FCN (icode
) (target
, addr
);
11909 /* Return a constant vector for use as a little-endian permute control vector
11910 to reverse the order of elements of the given vector mode. */
11912 swap_selector_for_mode (enum machine_mode mode
)
11914 /* These are little endian vectors, so their elements are reversed
11915 from what you would normally expect for a permute control vector. */
11916 unsigned int swap2
[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
11917 unsigned int swap4
[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
11918 unsigned int swap8
[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
11919 unsigned int swap16
[16] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
11920 unsigned int *swaparray
, i
;
11937 swaparray
= swap16
;
11940 gcc_unreachable ();
11943 for (i
= 0; i
< 16; ++i
)
11944 perm
[i
] = GEN_INT (swaparray
[i
]);
11946 return force_reg (V16QImode
, gen_rtx_CONST_VECTOR (V16QImode
, gen_rtvec_v (16, perm
)));
11949 /* Generate code for an "lvx", "lvxl", or "lve*x" built-in for a little endian target
11950 with -maltivec=be specified. Issue the load followed by an element-reversing
11953 altivec_expand_lvx_be (rtx op0
, rtx op1
, enum machine_mode mode
, unsigned unspec
)
11955 rtx tmp
= gen_reg_rtx (mode
);
11956 rtx load
= gen_rtx_SET (VOIDmode
, tmp
, op1
);
11957 rtx lvx
= gen_rtx_UNSPEC (mode
, gen_rtvec (1, const0_rtx
), unspec
);
11958 rtx par
= gen_rtx_PARALLEL (mode
, gen_rtvec (2, load
, lvx
));
11959 rtx sel
= swap_selector_for_mode (mode
);
11960 rtx vperm
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, tmp
, tmp
, sel
), UNSPEC_VPERM
);
11962 gcc_assert (REG_P (op0
));
11964 emit_insn (gen_rtx_SET (VOIDmode
, op0
, vperm
));
11967 /* Generate code for a "stvx" or "stvxl" built-in for a little endian target
11968 with -maltivec=be specified. Issue the store preceded by an element-reversing
11971 altivec_expand_stvx_be (rtx op0
, rtx op1
, enum machine_mode mode
, unsigned unspec
)
11973 rtx tmp
= gen_reg_rtx (mode
);
11974 rtx store
= gen_rtx_SET (VOIDmode
, op0
, tmp
);
11975 rtx stvx
= gen_rtx_UNSPEC (mode
, gen_rtvec (1, const0_rtx
), unspec
);
11976 rtx par
= gen_rtx_PARALLEL (mode
, gen_rtvec (2, store
, stvx
));
11977 rtx sel
= swap_selector_for_mode (mode
);
11980 gcc_assert (REG_P (op1
));
11981 vperm
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op1
, sel
), UNSPEC_VPERM
);
11982 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, vperm
));
11986 /* Generate code for a "stve*x" built-in for a little endian target with -maltivec=be
11987 specified. Issue the store preceded by an element-reversing permute. */
11989 altivec_expand_stvex_be (rtx op0
, rtx op1
, enum machine_mode mode
, unsigned unspec
)
11991 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
11992 rtx tmp
= gen_reg_rtx (mode
);
11993 rtx stvx
= gen_rtx_UNSPEC (inner_mode
, gen_rtvec (1, tmp
), unspec
);
11994 rtx sel
= swap_selector_for_mode (mode
);
11997 gcc_assert (REG_P (op1
));
11998 vperm
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op1
, sel
), UNSPEC_VPERM
);
11999 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, vperm
));
12000 emit_insn (gen_rtx_SET (VOIDmode
, op0
, stvx
));
12004 altivec_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
, bool blk
)
12007 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12008 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12009 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12010 enum machine_mode mode0
= Pmode
;
12011 enum machine_mode mode1
= Pmode
;
12012 rtx op0
= expand_normal (arg0
);
12013 rtx op1
= expand_normal (arg1
);
12015 if (icode
== CODE_FOR_nothing
)
12016 /* Builtin not supported on this processor. */
12019 /* If we got invalid arguments bail out before generating bad rtl. */
12020 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
12024 || GET_MODE (target
) != tmode
12025 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12026 target
= gen_reg_rtx (tmode
);
12028 op1
= copy_to_mode_reg (mode1
, op1
);
12030 if (op0
== const0_rtx
)
12032 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, op1
);
12036 op0
= copy_to_mode_reg (mode0
, op0
);
12037 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
12040 pat
= GEN_FCN (icode
) (target
, addr
);
12050 spe_expand_stv_builtin (enum insn_code icode
, tree exp
)
12052 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12053 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12054 tree arg2
= CALL_EXPR_ARG (exp
, 2);
12055 rtx op0
= expand_normal (arg0
);
12056 rtx op1
= expand_normal (arg1
);
12057 rtx op2
= expand_normal (arg2
);
12059 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
12060 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
12061 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
12063 /* Invalid arguments. Bail before doing anything stoopid! */
12064 if (arg0
== error_mark_node
12065 || arg1
== error_mark_node
12066 || arg2
== error_mark_node
)
12069 if (! (*insn_data
[icode
].operand
[2].predicate
) (op0
, mode2
))
12070 op0
= copy_to_mode_reg (mode2
, op0
);
12071 if (! (*insn_data
[icode
].operand
[0].predicate
) (op1
, mode0
))
12072 op1
= copy_to_mode_reg (mode0
, op1
);
12073 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
12074 op2
= copy_to_mode_reg (mode1
, op2
);
12076 pat
= GEN_FCN (icode
) (op1
, op2
, op0
);
12083 paired_expand_stv_builtin (enum insn_code icode
, tree exp
)
12085 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12086 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12087 tree arg2
= CALL_EXPR_ARG (exp
, 2);
12088 rtx op0
= expand_normal (arg0
);
12089 rtx op1
= expand_normal (arg1
);
12090 rtx op2
= expand_normal (arg2
);
12092 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12093 enum machine_mode mode1
= Pmode
;
12094 enum machine_mode mode2
= Pmode
;
12096 /* Invalid arguments. Bail before doing anything stoopid! */
12097 if (arg0
== error_mark_node
12098 || arg1
== error_mark_node
12099 || arg2
== error_mark_node
)
12102 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
12103 op0
= copy_to_mode_reg (tmode
, op0
);
12105 op2
= copy_to_mode_reg (mode2
, op2
);
12107 if (op1
== const0_rtx
)
12109 addr
= gen_rtx_MEM (tmode
, op2
);
12113 op1
= copy_to_mode_reg (mode1
, op1
);
12114 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
12117 pat
= GEN_FCN (icode
) (addr
, op0
);
12124 altivec_expand_stv_builtin (enum insn_code icode
, tree exp
)
12126 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12127 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12128 tree arg2
= CALL_EXPR_ARG (exp
, 2);
12129 rtx op0
= expand_normal (arg0
);
12130 rtx op1
= expand_normal (arg1
);
12131 rtx op2
= expand_normal (arg2
);
12133 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12134 enum machine_mode smode
= insn_data
[icode
].operand
[1].mode
;
12135 enum machine_mode mode1
= Pmode
;
12136 enum machine_mode mode2
= Pmode
;
12138 /* Invalid arguments. Bail before doing anything stoopid! */
12139 if (arg0
== error_mark_node
12140 || arg1
== error_mark_node
12141 || arg2
== error_mark_node
)
12144 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, smode
))
12145 op0
= copy_to_mode_reg (smode
, op0
);
12147 op2
= copy_to_mode_reg (mode2
, op2
);
12149 if (op1
== const0_rtx
)
12151 addr
= gen_rtx_MEM (tmode
, op2
);
12155 op1
= copy_to_mode_reg (mode1
, op1
);
12156 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
12159 pat
= GEN_FCN (icode
) (addr
, op0
);
12165 /* Return the appropriate SPR number associated with the given builtin. */
12166 static inline HOST_WIDE_INT
12167 htm_spr_num (enum rs6000_builtins code
)
12169 if (code
== HTM_BUILTIN_GET_TFHAR
12170 || code
== HTM_BUILTIN_SET_TFHAR
)
12172 else if (code
== HTM_BUILTIN_GET_TFIAR
12173 || code
== HTM_BUILTIN_SET_TFIAR
)
12175 else if (code
== HTM_BUILTIN_GET_TEXASR
12176 || code
== HTM_BUILTIN_SET_TEXASR
)
12178 gcc_assert (code
== HTM_BUILTIN_GET_TEXASRU
12179 || code
== HTM_BUILTIN_SET_TEXASRU
);
12180 return TEXASRU_SPR
;
12183 /* Return the appropriate SPR regno associated with the given builtin. */
12184 static inline HOST_WIDE_INT
12185 htm_spr_regno (enum rs6000_builtins code
)
12187 if (code
== HTM_BUILTIN_GET_TFHAR
12188 || code
== HTM_BUILTIN_SET_TFHAR
)
12189 return TFHAR_REGNO
;
12190 else if (code
== HTM_BUILTIN_GET_TFIAR
12191 || code
== HTM_BUILTIN_SET_TFIAR
)
12192 return TFIAR_REGNO
;
12193 gcc_assert (code
== HTM_BUILTIN_GET_TEXASR
12194 || code
== HTM_BUILTIN_SET_TEXASR
12195 || code
== HTM_BUILTIN_GET_TEXASRU
12196 || code
== HTM_BUILTIN_SET_TEXASRU
);
12197 return TEXASR_REGNO
;
12200 /* Return the correct ICODE value depending on whether we are
12201 setting or reading the HTM SPRs. */
12202 static inline enum insn_code
12203 rs6000_htm_spr_icode (bool nonvoid
)
12206 return (TARGET_64BIT
) ? CODE_FOR_htm_mfspr_di
: CODE_FOR_htm_mfspr_si
;
12208 return (TARGET_64BIT
) ? CODE_FOR_htm_mtspr_di
: CODE_FOR_htm_mtspr_si
;
12211 /* Expand the HTM builtin in EXP and store the result in TARGET.
12212 Store true in *EXPANDEDP if we found a builtin to expand. */
12214 htm_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
12216 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12217 bool nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
12218 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
12219 const struct builtin_description
*d
;
12222 *expandedp
= false;
12224 /* Expand the HTM builtins. */
12226 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
12227 if (d
->code
== fcode
)
12229 rtx op
[MAX_HTM_OPERANDS
], pat
;
12232 call_expr_arg_iterator iter
;
12233 unsigned attr
= rs6000_builtin_info
[fcode
].attr
;
12234 enum insn_code icode
= d
->icode
;
12236 if (attr
& RS6000_BTC_SPR
)
12237 icode
= rs6000_htm_spr_icode (nonvoid
);
12241 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12243 || GET_MODE (target
) != tmode
12244 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12245 target
= gen_reg_rtx (tmode
);
12246 op
[nopnds
++] = target
;
12249 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
12251 const struct insn_operand_data
*insn_op
;
12253 if (arg
== error_mark_node
|| nopnds
>= MAX_HTM_OPERANDS
)
12256 insn_op
= &insn_data
[icode
].operand
[nopnds
];
12258 op
[nopnds
] = expand_normal (arg
);
12260 if (!(*insn_op
->predicate
) (op
[nopnds
], insn_op
->mode
))
12262 if (!strcmp (insn_op
->constraint
, "n"))
12264 int arg_num
= (nonvoid
) ? nopnds
: nopnds
+ 1;
12265 if (!CONST_INT_P (op
[nopnds
]))
12266 error ("argument %d must be an unsigned literal", arg_num
);
12268 error ("argument %d is an unsigned literal that is "
12269 "out of range", arg_num
);
12272 op
[nopnds
] = copy_to_mode_reg (insn_op
->mode
, op
[nopnds
]);
12278 /* Handle the builtins for extended mnemonics. These accept
12279 no arguments, but map to builtins that take arguments. */
12282 case HTM_BUILTIN_TENDALL
: /* Alias for: tend. 1 */
12283 case HTM_BUILTIN_TRESUME
: /* Alias for: tsr. 1 */
12284 op
[nopnds
++] = GEN_INT (1);
12285 #ifdef ENABLE_CHECKING
12286 attr
|= RS6000_BTC_UNARY
;
12289 case HTM_BUILTIN_TSUSPEND
: /* Alias for: tsr. 0 */
12290 op
[nopnds
++] = GEN_INT (0);
12291 #ifdef ENABLE_CHECKING
12292 attr
|= RS6000_BTC_UNARY
;
12299 /* If this builtin accesses SPRs, then pass in the appropriate
12300 SPR number and SPR regno as the last two operands. */
12301 if (attr
& RS6000_BTC_SPR
)
12303 op
[nopnds
++] = gen_rtx_CONST_INT (Pmode
, htm_spr_num (fcode
));
12304 op
[nopnds
++] = gen_rtx_REG (Pmode
, htm_spr_regno (fcode
));
12307 #ifdef ENABLE_CHECKING
12308 int expected_nopnds
= 0;
12309 if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_UNARY
)
12310 expected_nopnds
= 1;
12311 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_BINARY
)
12312 expected_nopnds
= 2;
12313 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_TERNARY
)
12314 expected_nopnds
= 3;
12315 if (!(attr
& RS6000_BTC_VOID
))
12316 expected_nopnds
+= 1;
12317 if (attr
& RS6000_BTC_SPR
)
12318 expected_nopnds
+= 2;
12320 gcc_assert (nopnds
== expected_nopnds
&& nopnds
<= MAX_HTM_OPERANDS
);
12326 pat
= GEN_FCN (icode
) (op
[0]);
12329 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
12332 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
12335 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
12338 gcc_unreachable ();
12354 rs6000_expand_ternop_builtin (enum insn_code icode
, tree exp
, rtx target
)
12357 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12358 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12359 tree arg2
= CALL_EXPR_ARG (exp
, 2);
12360 rtx op0
= expand_normal (arg0
);
12361 rtx op1
= expand_normal (arg1
);
12362 rtx op2
= expand_normal (arg2
);
12363 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12364 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12365 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12366 enum machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
12368 if (icode
== CODE_FOR_nothing
)
12369 /* Builtin not supported on this processor. */
12372 /* If we got invalid arguments bail out before generating bad rtl. */
12373 if (arg0
== error_mark_node
12374 || arg1
== error_mark_node
12375 || arg2
== error_mark_node
)
12378 /* Check and prepare argument depending on the instruction code.
12380 Note that a switch statement instead of the sequence of tests
12381 would be incorrect as many of the CODE_FOR values could be
12382 CODE_FOR_nothing and that would yield multiple alternatives
12383 with identical values. We'd never reach here at runtime in
12385 if (icode
== CODE_FOR_altivec_vsldoi_v4sf
12386 || icode
== CODE_FOR_altivec_vsldoi_v4si
12387 || icode
== CODE_FOR_altivec_vsldoi_v8hi
12388 || icode
== CODE_FOR_altivec_vsldoi_v16qi
)
12390 /* Only allow 4-bit unsigned literals. */
12392 if (TREE_CODE (arg2
) != INTEGER_CST
12393 || TREE_INT_CST_LOW (arg2
) & ~0xf)
12395 error ("argument 3 must be a 4-bit unsigned literal");
12399 else if (icode
== CODE_FOR_vsx_xxpermdi_v2df
12400 || icode
== CODE_FOR_vsx_xxpermdi_v2di
12401 || icode
== CODE_FOR_vsx_xxsldwi_v16qi
12402 || icode
== CODE_FOR_vsx_xxsldwi_v8hi
12403 || icode
== CODE_FOR_vsx_xxsldwi_v4si
12404 || icode
== CODE_FOR_vsx_xxsldwi_v4sf
12405 || icode
== CODE_FOR_vsx_xxsldwi_v2di
12406 || icode
== CODE_FOR_vsx_xxsldwi_v2df
)
12408 /* Only allow 2-bit unsigned literals. */
12410 if (TREE_CODE (arg2
) != INTEGER_CST
12411 || TREE_INT_CST_LOW (arg2
) & ~0x3)
12413 error ("argument 3 must be a 2-bit unsigned literal");
12417 else if (icode
== CODE_FOR_vsx_set_v2df
12418 || icode
== CODE_FOR_vsx_set_v2di
12419 || icode
== CODE_FOR_bcdadd
12420 || icode
== CODE_FOR_bcdadd_lt
12421 || icode
== CODE_FOR_bcdadd_eq
12422 || icode
== CODE_FOR_bcdadd_gt
12423 || icode
== CODE_FOR_bcdsub
12424 || icode
== CODE_FOR_bcdsub_lt
12425 || icode
== CODE_FOR_bcdsub_eq
12426 || icode
== CODE_FOR_bcdsub_gt
)
12428 /* Only allow 1-bit unsigned literals. */
12430 if (TREE_CODE (arg2
) != INTEGER_CST
12431 || TREE_INT_CST_LOW (arg2
) & ~0x1)
12433 error ("argument 3 must be a 1-bit unsigned literal");
12437 else if (icode
== CODE_FOR_dfp_ddedpd_dd
12438 || icode
== CODE_FOR_dfp_ddedpd_td
)
12440 /* Only allow 2-bit unsigned literals where the value is 0 or 2. */
12442 if (TREE_CODE (arg0
) != INTEGER_CST
12443 || TREE_INT_CST_LOW (arg2
) & ~0x3)
12445 error ("argument 1 must be 0 or 2");
12449 else if (icode
== CODE_FOR_dfp_denbcd_dd
12450 || icode
== CODE_FOR_dfp_denbcd_td
)
12452 /* Only allow 1-bit unsigned literals. */
12454 if (TREE_CODE (arg0
) != INTEGER_CST
12455 || TREE_INT_CST_LOW (arg0
) & ~0x1)
12457 error ("argument 1 must be a 1-bit unsigned literal");
12461 else if (icode
== CODE_FOR_dfp_dscli_dd
12462 || icode
== CODE_FOR_dfp_dscli_td
12463 || icode
== CODE_FOR_dfp_dscri_dd
12464 || icode
== CODE_FOR_dfp_dscri_td
)
12466 /* Only allow 6-bit unsigned literals. */
12468 if (TREE_CODE (arg1
) != INTEGER_CST
12469 || TREE_INT_CST_LOW (arg1
) & ~0x3f)
12471 error ("argument 2 must be a 6-bit unsigned literal");
12475 else if (icode
== CODE_FOR_crypto_vshasigmaw
12476 || icode
== CODE_FOR_crypto_vshasigmad
)
12478 /* Check whether the 2nd and 3rd arguments are integer constants and in
12479 range and prepare arguments. */
12481 if (TREE_CODE (arg1
) != INTEGER_CST
|| wi::geu_p (arg1
, 2))
12483 error ("argument 2 must be 0 or 1");
12488 if (TREE_CODE (arg2
) != INTEGER_CST
|| wi::geu_p (arg1
, 16))
12490 error ("argument 3 must be in the range 0..15");
12496 || GET_MODE (target
) != tmode
12497 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12498 target
= gen_reg_rtx (tmode
);
12500 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12501 op0
= copy_to_mode_reg (mode0
, op0
);
12502 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12503 op1
= copy_to_mode_reg (mode1
, op1
);
12504 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12505 op2
= copy_to_mode_reg (mode2
, op2
);
12507 if (TARGET_PAIRED_FLOAT
&& icode
== CODE_FOR_selv2sf4
)
12508 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
, CONST0_RTX (SFmode
));
12510 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12518 /* Expand the lvx builtins. */
12520 altivec_expand_ld_builtin (tree exp
, rtx target
, bool *expandedp
)
12522 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12523 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
12525 enum machine_mode tmode
, mode0
;
12527 enum insn_code icode
;
12531 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi
:
12532 icode
= CODE_FOR_vector_altivec_load_v16qi
;
12534 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi
:
12535 icode
= CODE_FOR_vector_altivec_load_v8hi
;
12537 case ALTIVEC_BUILTIN_LD_INTERNAL_4si
:
12538 icode
= CODE_FOR_vector_altivec_load_v4si
;
12540 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf
:
12541 icode
= CODE_FOR_vector_altivec_load_v4sf
;
12543 case ALTIVEC_BUILTIN_LD_INTERNAL_2df
:
12544 icode
= CODE_FOR_vector_altivec_load_v2df
;
12546 case ALTIVEC_BUILTIN_LD_INTERNAL_2di
:
12547 icode
= CODE_FOR_vector_altivec_load_v2di
;
12548 case ALTIVEC_BUILTIN_LD_INTERNAL_1ti
:
12549 icode
= CODE_FOR_vector_altivec_load_v1ti
;
12552 *expandedp
= false;
12558 arg0
= CALL_EXPR_ARG (exp
, 0);
12559 op0
= expand_normal (arg0
);
12560 tmode
= insn_data
[icode
].operand
[0].mode
;
12561 mode0
= insn_data
[icode
].operand
[1].mode
;
12564 || GET_MODE (target
) != tmode
12565 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12566 target
= gen_reg_rtx (tmode
);
12568 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12569 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
12571 pat
= GEN_FCN (icode
) (target
, op0
);
12578 /* Expand the stvx builtins. */
12580 altivec_expand_st_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
12583 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12584 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
12586 enum machine_mode mode0
, mode1
;
12588 enum insn_code icode
;
12592 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi
:
12593 icode
= CODE_FOR_vector_altivec_store_v16qi
;
12595 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi
:
12596 icode
= CODE_FOR_vector_altivec_store_v8hi
;
12598 case ALTIVEC_BUILTIN_ST_INTERNAL_4si
:
12599 icode
= CODE_FOR_vector_altivec_store_v4si
;
12601 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf
:
12602 icode
= CODE_FOR_vector_altivec_store_v4sf
;
12604 case ALTIVEC_BUILTIN_ST_INTERNAL_2df
:
12605 icode
= CODE_FOR_vector_altivec_store_v2df
;
12607 case ALTIVEC_BUILTIN_ST_INTERNAL_2di
:
12608 icode
= CODE_FOR_vector_altivec_store_v2di
;
12609 case ALTIVEC_BUILTIN_ST_INTERNAL_1ti
:
12610 icode
= CODE_FOR_vector_altivec_store_v1ti
;
12613 *expandedp
= false;
12617 arg0
= CALL_EXPR_ARG (exp
, 0);
12618 arg1
= CALL_EXPR_ARG (exp
, 1);
12619 op0
= expand_normal (arg0
);
12620 op1
= expand_normal (arg1
);
12621 mode0
= insn_data
[icode
].operand
[0].mode
;
12622 mode1
= insn_data
[icode
].operand
[1].mode
;
12624 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
12625 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
12626 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
12627 op1
= copy_to_mode_reg (mode1
, op1
);
12629 pat
= GEN_FCN (icode
) (op0
, op1
);
12637 /* Expand the dst builtins. */
12639 altivec_expand_dst_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
12642 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12643 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
12644 tree arg0
, arg1
, arg2
;
12645 enum machine_mode mode0
, mode1
;
12646 rtx pat
, op0
, op1
, op2
;
12647 const struct builtin_description
*d
;
12650 *expandedp
= false;
12652 /* Handle DST variants. */
12654 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
12655 if (d
->code
== fcode
)
12657 arg0
= CALL_EXPR_ARG (exp
, 0);
12658 arg1
= CALL_EXPR_ARG (exp
, 1);
12659 arg2
= CALL_EXPR_ARG (exp
, 2);
12660 op0
= expand_normal (arg0
);
12661 op1
= expand_normal (arg1
);
12662 op2
= expand_normal (arg2
);
12663 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
12664 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
12666 /* Invalid arguments, bail out before generating bad rtl. */
12667 if (arg0
== error_mark_node
12668 || arg1
== error_mark_node
12669 || arg2
== error_mark_node
)
12674 if (TREE_CODE (arg2
) != INTEGER_CST
12675 || TREE_INT_CST_LOW (arg2
) & ~0x3)
12677 error ("argument to %qs must be a 2-bit unsigned literal", d
->name
);
12681 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
12682 op0
= copy_to_mode_reg (Pmode
, op0
);
12683 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
12684 op1
= copy_to_mode_reg (mode1
, op1
);
12686 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
12696 /* Expand vec_init builtin. */
12698 altivec_expand_vec_init_builtin (tree type
, tree exp
, rtx target
)
12700 enum machine_mode tmode
= TYPE_MODE (type
);
12701 enum machine_mode inner_mode
= GET_MODE_INNER (tmode
);
12702 int i
, n_elt
= GET_MODE_NUNITS (tmode
);
12704 gcc_assert (VECTOR_MODE_P (tmode
));
12705 gcc_assert (n_elt
== call_expr_nargs (exp
));
12707 if (!target
|| !register_operand (target
, tmode
))
12708 target
= gen_reg_rtx (tmode
);
12710 /* If we have a vector compromised of a single element, such as V1TImode, do
12711 the initialization directly. */
12712 if (n_elt
== 1 && GET_MODE_SIZE (tmode
) == GET_MODE_SIZE (inner_mode
))
12714 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, 0));
12715 emit_move_insn (target
, gen_lowpart (tmode
, x
));
12719 rtvec v
= rtvec_alloc (n_elt
);
12721 for (i
= 0; i
< n_elt
; ++i
)
12723 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, i
));
12724 RTVEC_ELT (v
, i
) = gen_lowpart (inner_mode
, x
);
12727 rs6000_expand_vector_init (target
, gen_rtx_PARALLEL (tmode
, v
));
12733 /* Return the integer constant in ARG. Constrain it to be in the range
12734 of the subparts of VEC_TYPE; issue an error if not. */
12737 get_element_number (tree vec_type
, tree arg
)
12739 unsigned HOST_WIDE_INT elt
, max
= TYPE_VECTOR_SUBPARTS (vec_type
) - 1;
12741 if (!tree_fits_uhwi_p (arg
)
12742 || (elt
= tree_to_uhwi (arg
), elt
> max
))
12744 error ("selector must be an integer constant in the range 0..%wi", max
);
12751 /* Expand vec_set builtin. */
12753 altivec_expand_vec_set_builtin (tree exp
)
12755 enum machine_mode tmode
, mode1
;
12756 tree arg0
, arg1
, arg2
;
12760 arg0
= CALL_EXPR_ARG (exp
, 0);
12761 arg1
= CALL_EXPR_ARG (exp
, 1);
12762 arg2
= CALL_EXPR_ARG (exp
, 2);
12764 tmode
= TYPE_MODE (TREE_TYPE (arg0
));
12765 mode1
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
12766 gcc_assert (VECTOR_MODE_P (tmode
));
12768 op0
= expand_expr (arg0
, NULL_RTX
, tmode
, EXPAND_NORMAL
);
12769 op1
= expand_expr (arg1
, NULL_RTX
, mode1
, EXPAND_NORMAL
);
12770 elt
= get_element_number (TREE_TYPE (arg0
), arg2
);
12772 if (GET_MODE (op1
) != mode1
&& GET_MODE (op1
) != VOIDmode
)
12773 op1
= convert_modes (mode1
, GET_MODE (op1
), op1
, true);
12775 op0
= force_reg (tmode
, op0
);
12776 op1
= force_reg (mode1
, op1
);
12778 rs6000_expand_vector_set (op0
, op1
, elt
);
12783 /* Expand vec_ext builtin. */
12785 altivec_expand_vec_ext_builtin (tree exp
, rtx target
)
12787 enum machine_mode tmode
, mode0
;
12792 arg0
= CALL_EXPR_ARG (exp
, 0);
12793 arg1
= CALL_EXPR_ARG (exp
, 1);
12795 op0
= expand_normal (arg0
);
12796 elt
= get_element_number (TREE_TYPE (arg0
), arg1
);
12798 tmode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
12799 mode0
= TYPE_MODE (TREE_TYPE (arg0
));
12800 gcc_assert (VECTOR_MODE_P (mode0
));
12802 op0
= force_reg (mode0
, op0
);
12804 if (optimize
|| !target
|| !register_operand (target
, tmode
))
12805 target
= gen_reg_rtx (tmode
);
12807 rs6000_expand_vector_extract (target
, op0
, elt
);
12812 /* Expand the builtin in EXP and store the result in TARGET. Store
12813 true in *EXPANDEDP if we found a builtin to expand. */
12815 altivec_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
12817 const struct builtin_description
*d
;
12819 enum insn_code icode
;
12820 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12823 enum machine_mode tmode
, mode0
;
12824 enum rs6000_builtins fcode
12825 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
12827 if (rs6000_overloaded_builtin_p (fcode
))
12830 error ("unresolved overload for Altivec builtin %qF", fndecl
);
12832 /* Given it is invalid, just generate a normal call. */
12833 return expand_call (exp
, target
, false);
12836 target
= altivec_expand_ld_builtin (exp
, target
, expandedp
);
12840 target
= altivec_expand_st_builtin (exp
, target
, expandedp
);
12844 target
= altivec_expand_dst_builtin (exp
, target
, expandedp
);
12852 case ALTIVEC_BUILTIN_STVX_V2DF
:
12853 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df
, exp
);
12854 case ALTIVEC_BUILTIN_STVX_V2DI
:
12855 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di
, exp
);
12856 case ALTIVEC_BUILTIN_STVX_V4SF
:
12857 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf
, exp
);
12858 case ALTIVEC_BUILTIN_STVX
:
12859 case ALTIVEC_BUILTIN_STVX_V4SI
:
12860 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si
, exp
);
12861 case ALTIVEC_BUILTIN_STVX_V8HI
:
12862 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi
, exp
);
12863 case ALTIVEC_BUILTIN_STVX_V16QI
:
12864 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi
, exp
);
12865 case ALTIVEC_BUILTIN_STVEBX
:
12866 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx
, exp
);
12867 case ALTIVEC_BUILTIN_STVEHX
:
12868 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx
, exp
);
12869 case ALTIVEC_BUILTIN_STVEWX
:
12870 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx
, exp
);
12871 case ALTIVEC_BUILTIN_STVXL_V2DF
:
12872 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df
, exp
);
12873 case ALTIVEC_BUILTIN_STVXL_V2DI
:
12874 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di
, exp
);
12875 case ALTIVEC_BUILTIN_STVXL_V4SF
:
12876 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf
, exp
);
12877 case ALTIVEC_BUILTIN_STVXL
:
12878 case ALTIVEC_BUILTIN_STVXL_V4SI
:
12879 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si
, exp
);
12880 case ALTIVEC_BUILTIN_STVXL_V8HI
:
12881 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi
, exp
);
12882 case ALTIVEC_BUILTIN_STVXL_V16QI
:
12883 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi
, exp
);
12885 case ALTIVEC_BUILTIN_STVLX
:
12886 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx
, exp
);
12887 case ALTIVEC_BUILTIN_STVLXL
:
12888 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl
, exp
);
12889 case ALTIVEC_BUILTIN_STVRX
:
12890 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx
, exp
);
12891 case ALTIVEC_BUILTIN_STVRXL
:
12892 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl
, exp
);
12894 case VSX_BUILTIN_STXVD2X_V1TI
:
12895 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti
, exp
);
12896 case VSX_BUILTIN_STXVD2X_V2DF
:
12897 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df
, exp
);
12898 case VSX_BUILTIN_STXVD2X_V2DI
:
12899 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di
, exp
);
12900 case VSX_BUILTIN_STXVW4X_V4SF
:
12901 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf
, exp
);
12902 case VSX_BUILTIN_STXVW4X_V4SI
:
12903 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si
, exp
);
12904 case VSX_BUILTIN_STXVW4X_V8HI
:
12905 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi
, exp
);
12906 case VSX_BUILTIN_STXVW4X_V16QI
:
12907 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi
, exp
);
12909 case ALTIVEC_BUILTIN_MFVSCR
:
12910 icode
= CODE_FOR_altivec_mfvscr
;
12911 tmode
= insn_data
[icode
].operand
[0].mode
;
12914 || GET_MODE (target
) != tmode
12915 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12916 target
= gen_reg_rtx (tmode
);
12918 pat
= GEN_FCN (icode
) (target
);
12924 case ALTIVEC_BUILTIN_MTVSCR
:
12925 icode
= CODE_FOR_altivec_mtvscr
;
12926 arg0
= CALL_EXPR_ARG (exp
, 0);
12927 op0
= expand_normal (arg0
);
12928 mode0
= insn_data
[icode
].operand
[0].mode
;
12930 /* If we got invalid arguments bail out before generating bad rtl. */
12931 if (arg0
== error_mark_node
)
12934 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
12935 op0
= copy_to_mode_reg (mode0
, op0
);
12937 pat
= GEN_FCN (icode
) (op0
);
12942 case ALTIVEC_BUILTIN_DSSALL
:
12943 emit_insn (gen_altivec_dssall ());
12946 case ALTIVEC_BUILTIN_DSS
:
12947 icode
= CODE_FOR_altivec_dss
;
12948 arg0
= CALL_EXPR_ARG (exp
, 0);
12950 op0
= expand_normal (arg0
);
12951 mode0
= insn_data
[icode
].operand
[0].mode
;
12953 /* If we got invalid arguments bail out before generating bad rtl. */
12954 if (arg0
== error_mark_node
)
12957 if (TREE_CODE (arg0
) != INTEGER_CST
12958 || TREE_INT_CST_LOW (arg0
) & ~0x3)
12960 error ("argument to dss must be a 2-bit unsigned literal");
12964 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
12965 op0
= copy_to_mode_reg (mode0
, op0
);
12967 emit_insn (gen_altivec_dss (op0
));
12970 case ALTIVEC_BUILTIN_VEC_INIT_V4SI
:
12971 case ALTIVEC_BUILTIN_VEC_INIT_V8HI
:
12972 case ALTIVEC_BUILTIN_VEC_INIT_V16QI
:
12973 case ALTIVEC_BUILTIN_VEC_INIT_V4SF
:
12974 case VSX_BUILTIN_VEC_INIT_V2DF
:
12975 case VSX_BUILTIN_VEC_INIT_V2DI
:
12976 case VSX_BUILTIN_VEC_INIT_V1TI
:
12977 return altivec_expand_vec_init_builtin (TREE_TYPE (exp
), exp
, target
);
12979 case ALTIVEC_BUILTIN_VEC_SET_V4SI
:
12980 case ALTIVEC_BUILTIN_VEC_SET_V8HI
:
12981 case ALTIVEC_BUILTIN_VEC_SET_V16QI
:
12982 case ALTIVEC_BUILTIN_VEC_SET_V4SF
:
12983 case VSX_BUILTIN_VEC_SET_V2DF
:
12984 case VSX_BUILTIN_VEC_SET_V2DI
:
12985 case VSX_BUILTIN_VEC_SET_V1TI
:
12986 return altivec_expand_vec_set_builtin (exp
);
12988 case ALTIVEC_BUILTIN_VEC_EXT_V4SI
:
12989 case ALTIVEC_BUILTIN_VEC_EXT_V8HI
:
12990 case ALTIVEC_BUILTIN_VEC_EXT_V16QI
:
12991 case ALTIVEC_BUILTIN_VEC_EXT_V4SF
:
12992 case VSX_BUILTIN_VEC_EXT_V2DF
:
12993 case VSX_BUILTIN_VEC_EXT_V2DI
:
12994 case VSX_BUILTIN_VEC_EXT_V1TI
:
12995 return altivec_expand_vec_ext_builtin (exp
, target
);
12999 /* Fall through. */
13002 /* Expand abs* operations. */
13004 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
13005 if (d
->code
== fcode
)
13006 return altivec_expand_abs_builtin (d
->icode
, exp
, target
);
13008 /* Expand the AltiVec predicates. */
13009 d
= bdesc_altivec_preds
;
13010 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
13011 if (d
->code
== fcode
)
13012 return altivec_expand_predicate_builtin (d
->icode
, exp
, target
);
13014 /* LV* are funky. We initialized them differently. */
13017 case ALTIVEC_BUILTIN_LVSL
:
13018 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl
,
13019 exp
, target
, false);
13020 case ALTIVEC_BUILTIN_LVSR
:
13021 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr
,
13022 exp
, target
, false);
13023 case ALTIVEC_BUILTIN_LVEBX
:
13024 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx
,
13025 exp
, target
, false);
13026 case ALTIVEC_BUILTIN_LVEHX
:
13027 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx
,
13028 exp
, target
, false);
13029 case ALTIVEC_BUILTIN_LVEWX
:
13030 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx
,
13031 exp
, target
, false);
13032 case ALTIVEC_BUILTIN_LVXL_V2DF
:
13033 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df
,
13034 exp
, target
, false);
13035 case ALTIVEC_BUILTIN_LVXL_V2DI
:
13036 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di
,
13037 exp
, target
, false);
13038 case ALTIVEC_BUILTIN_LVXL_V4SF
:
13039 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf
,
13040 exp
, target
, false);
13041 case ALTIVEC_BUILTIN_LVXL
:
13042 case ALTIVEC_BUILTIN_LVXL_V4SI
:
13043 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si
,
13044 exp
, target
, false);
13045 case ALTIVEC_BUILTIN_LVXL_V8HI
:
13046 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi
,
13047 exp
, target
, false);
13048 case ALTIVEC_BUILTIN_LVXL_V16QI
:
13049 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi
,
13050 exp
, target
, false);
13051 case ALTIVEC_BUILTIN_LVX_V2DF
:
13052 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df
,
13053 exp
, target
, false);
13054 case ALTIVEC_BUILTIN_LVX_V2DI
:
13055 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di
,
13056 exp
, target
, false);
13057 case ALTIVEC_BUILTIN_LVX_V4SF
:
13058 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf
,
13059 exp
, target
, false);
13060 case ALTIVEC_BUILTIN_LVX
:
13061 case ALTIVEC_BUILTIN_LVX_V4SI
:
13062 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si
,
13063 exp
, target
, false);
13064 case ALTIVEC_BUILTIN_LVX_V8HI
:
13065 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi
,
13066 exp
, target
, false);
13067 case ALTIVEC_BUILTIN_LVX_V16QI
:
13068 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi
,
13069 exp
, target
, false);
13070 case ALTIVEC_BUILTIN_LVLX
:
13071 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx
,
13072 exp
, target
, true);
13073 case ALTIVEC_BUILTIN_LVLXL
:
13074 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl
,
13075 exp
, target
, true);
13076 case ALTIVEC_BUILTIN_LVRX
:
13077 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx
,
13078 exp
, target
, true);
13079 case ALTIVEC_BUILTIN_LVRXL
:
13080 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl
,
13081 exp
, target
, true);
13082 case VSX_BUILTIN_LXVD2X_V1TI
:
13083 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti
,
13084 exp
, target
, false);
13085 case VSX_BUILTIN_LXVD2X_V2DF
:
13086 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df
,
13087 exp
, target
, false);
13088 case VSX_BUILTIN_LXVD2X_V2DI
:
13089 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di
,
13090 exp
, target
, false);
13091 case VSX_BUILTIN_LXVW4X_V4SF
:
13092 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf
,
13093 exp
, target
, false);
13094 case VSX_BUILTIN_LXVW4X_V4SI
:
13095 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si
,
13096 exp
, target
, false);
13097 case VSX_BUILTIN_LXVW4X_V8HI
:
13098 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi
,
13099 exp
, target
, false);
13100 case VSX_BUILTIN_LXVW4X_V16QI
:
13101 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi
,
13102 exp
, target
, false);
13106 /* Fall through. */
13109 *expandedp
= false;
13113 /* Expand the builtin in EXP and store the result in TARGET. Store
13114 true in *EXPANDEDP if we found a builtin to expand. */
13116 paired_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
13118 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13119 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
13120 const struct builtin_description
*d
;
13127 case PAIRED_BUILTIN_STX
:
13128 return paired_expand_stv_builtin (CODE_FOR_paired_stx
, exp
);
13129 case PAIRED_BUILTIN_LX
:
13130 return paired_expand_lv_builtin (CODE_FOR_paired_lx
, exp
, target
);
13133 /* Fall through. */
13136 /* Expand the paired predicates. */
13137 d
= bdesc_paired_preds
;
13138 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); i
++, d
++)
13139 if (d
->code
== fcode
)
13140 return paired_expand_predicate_builtin (d
->icode
, exp
, target
);
13142 *expandedp
= false;
13146 /* Binops that need to be initialized manually, but can be expanded
13147 automagically by rs6000_expand_binop_builtin. */
13148 static const struct builtin_description bdesc_2arg_spe
[] =
13150 { RS6000_BTM_SPE
, CODE_FOR_spe_evlddx
, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX
},
13151 { RS6000_BTM_SPE
, CODE_FOR_spe_evldwx
, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX
},
13152 { RS6000_BTM_SPE
, CODE_FOR_spe_evldhx
, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX
},
13153 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhex
, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX
},
13154 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhoux
, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX
},
13155 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhosx
, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX
},
13156 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplatx
, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX
},
13157 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplatx
, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX
},
13158 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplatx
, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX
},
13159 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplatx
, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX
},
13160 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplatx
, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX
},
13161 { RS6000_BTM_SPE
, CODE_FOR_spe_evldd
, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD
},
13162 { RS6000_BTM_SPE
, CODE_FOR_spe_evldw
, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW
},
13163 { RS6000_BTM_SPE
, CODE_FOR_spe_evldh
, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH
},
13164 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhe
, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE
},
13165 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhou
, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU
},
13166 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhos
, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS
},
13167 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplat
, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT
},
13168 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplat
, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT
},
13169 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplat
, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT
},
13170 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplat
, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT
},
13171 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplat
, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT
}
13174 /* Expand the builtin in EXP and store the result in TARGET. Store
13175 true in *EXPANDEDP if we found a builtin to expand.
13177 This expands the SPE builtins that are not simple unary and binary
13180 spe_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
13182 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13184 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
13185 enum insn_code icode
;
13186 enum machine_mode tmode
, mode0
;
13188 const struct builtin_description
*d
;
13193 /* Syntax check for a 5-bit unsigned immediate. */
13196 case SPE_BUILTIN_EVSTDD
:
13197 case SPE_BUILTIN_EVSTDH
:
13198 case SPE_BUILTIN_EVSTDW
:
13199 case SPE_BUILTIN_EVSTWHE
:
13200 case SPE_BUILTIN_EVSTWHO
:
13201 case SPE_BUILTIN_EVSTWWE
:
13202 case SPE_BUILTIN_EVSTWWO
:
13203 arg1
= CALL_EXPR_ARG (exp
, 2);
13204 if (TREE_CODE (arg1
) != INTEGER_CST
13205 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
13207 error ("argument 2 must be a 5-bit unsigned literal");
13215 /* The evsplat*i instructions are not quite generic. */
13218 case SPE_BUILTIN_EVSPLATFI
:
13219 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi
,
13221 case SPE_BUILTIN_EVSPLATI
:
13222 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati
,
13228 d
= bdesc_2arg_spe
;
13229 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg_spe
); ++i
, ++d
)
13230 if (d
->code
== fcode
)
13231 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
13233 d
= bdesc_spe_predicates
;
13234 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, ++d
)
13235 if (d
->code
== fcode
)
13236 return spe_expand_predicate_builtin (d
->icode
, exp
, target
);
13238 d
= bdesc_spe_evsel
;
13239 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, ++d
)
13240 if (d
->code
== fcode
)
13241 return spe_expand_evsel_builtin (d
->icode
, exp
, target
);
13245 case SPE_BUILTIN_EVSTDDX
:
13246 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx
, exp
);
13247 case SPE_BUILTIN_EVSTDHX
:
13248 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx
, exp
);
13249 case SPE_BUILTIN_EVSTDWX
:
13250 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx
, exp
);
13251 case SPE_BUILTIN_EVSTWHEX
:
13252 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex
, exp
);
13253 case SPE_BUILTIN_EVSTWHOX
:
13254 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox
, exp
);
13255 case SPE_BUILTIN_EVSTWWEX
:
13256 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex
, exp
);
13257 case SPE_BUILTIN_EVSTWWOX
:
13258 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox
, exp
);
13259 case SPE_BUILTIN_EVSTDD
:
13260 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd
, exp
);
13261 case SPE_BUILTIN_EVSTDH
:
13262 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh
, exp
);
13263 case SPE_BUILTIN_EVSTDW
:
13264 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw
, exp
);
13265 case SPE_BUILTIN_EVSTWHE
:
13266 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe
, exp
);
13267 case SPE_BUILTIN_EVSTWHO
:
13268 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho
, exp
);
13269 case SPE_BUILTIN_EVSTWWE
:
13270 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe
, exp
);
13271 case SPE_BUILTIN_EVSTWWO
:
13272 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo
, exp
);
13273 case SPE_BUILTIN_MFSPEFSCR
:
13274 icode
= CODE_FOR_spe_mfspefscr
;
13275 tmode
= insn_data
[icode
].operand
[0].mode
;
13278 || GET_MODE (target
) != tmode
13279 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13280 target
= gen_reg_rtx (tmode
);
13282 pat
= GEN_FCN (icode
) (target
);
13287 case SPE_BUILTIN_MTSPEFSCR
:
13288 icode
= CODE_FOR_spe_mtspefscr
;
13289 arg0
= CALL_EXPR_ARG (exp
, 0);
13290 op0
= expand_normal (arg0
);
13291 mode0
= insn_data
[icode
].operand
[0].mode
;
13293 if (arg0
== error_mark_node
)
13296 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
13297 op0
= copy_to_mode_reg (mode0
, op0
);
13299 pat
= GEN_FCN (icode
) (op0
);
13307 *expandedp
= false;
13312 paired_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
13314 rtx pat
, scratch
, tmp
;
13315 tree form
= CALL_EXPR_ARG (exp
, 0);
13316 tree arg0
= CALL_EXPR_ARG (exp
, 1);
13317 tree arg1
= CALL_EXPR_ARG (exp
, 2);
13318 rtx op0
= expand_normal (arg0
);
13319 rtx op1
= expand_normal (arg1
);
13320 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13321 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
13323 enum rtx_code code
;
13325 if (TREE_CODE (form
) != INTEGER_CST
)
13327 error ("argument 1 of __builtin_paired_predicate must be a constant");
13331 form_int
= TREE_INT_CST_LOW (form
);
13333 gcc_assert (mode0
== mode1
);
13335 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
13339 || GET_MODE (target
) != SImode
13340 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
13341 target
= gen_reg_rtx (SImode
);
13342 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13343 op0
= copy_to_mode_reg (mode0
, op0
);
13344 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13345 op1
= copy_to_mode_reg (mode1
, op1
);
13347 scratch
= gen_reg_rtx (CCFPmode
);
13349 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
13371 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
13374 error ("argument 1 of __builtin_paired_predicate is out of range");
13378 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
13379 emit_move_insn (target
, tmp
);
13384 spe_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
13386 rtx pat
, scratch
, tmp
;
13387 tree form
= CALL_EXPR_ARG (exp
, 0);
13388 tree arg0
= CALL_EXPR_ARG (exp
, 1);
13389 tree arg1
= CALL_EXPR_ARG (exp
, 2);
13390 rtx op0
= expand_normal (arg0
);
13391 rtx op1
= expand_normal (arg1
);
13392 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13393 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
13395 enum rtx_code code
;
13397 if (TREE_CODE (form
) != INTEGER_CST
)
13399 error ("argument 1 of __builtin_spe_predicate must be a constant");
13403 form_int
= TREE_INT_CST_LOW (form
);
13405 gcc_assert (mode0
== mode1
);
13407 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
13411 || GET_MODE (target
) != SImode
13412 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
13413 target
= gen_reg_rtx (SImode
);
13415 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13416 op0
= copy_to_mode_reg (mode0
, op0
);
13417 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13418 op1
= copy_to_mode_reg (mode1
, op1
);
13420 scratch
= gen_reg_rtx (CCmode
);
13422 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
13427 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
13428 _lower_. We use one compare, but look in different bits of the
13429 CR for each variant.
13431 There are 2 elements in each SPE simd type (upper/lower). The CR
13432 bits are set as follows:
13434 BIT0 | BIT 1 | BIT 2 | BIT 3
13435 U | L | (U | L) | (U & L)
13437 So, for an "all" relationship, BIT 3 would be set.
13438 For an "any" relationship, BIT 2 would be set. Etc.
13440 Following traditional nomenclature, these bits map to:
13442 BIT0 | BIT 1 | BIT 2 | BIT 3
13445 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
13450 /* All variant. OV bit. */
13452 /* We need to get to the OV bit, which is the ORDERED bit. We
13453 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
13454 that's ugly and will make validate_condition_mode die.
13455 So let's just use another pattern. */
13456 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
13458 /* Any variant. EQ bit. */
13462 /* Upper variant. LT bit. */
13466 /* Lower variant. GT bit. */
13471 error ("argument 1 of __builtin_spe_predicate is out of range");
13475 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
13476 emit_move_insn (target
, tmp
);
13481 /* The evsel builtins look like this:
13483 e = __builtin_spe_evsel_OP (a, b, c, d);
13485 and work like this:
13487 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
13488 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
13492 spe_expand_evsel_builtin (enum insn_code icode
, tree exp
, rtx target
)
13495 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13496 tree arg1
= CALL_EXPR_ARG (exp
, 1);
13497 tree arg2
= CALL_EXPR_ARG (exp
, 2);
13498 tree arg3
= CALL_EXPR_ARG (exp
, 3);
13499 rtx op0
= expand_normal (arg0
);
13500 rtx op1
= expand_normal (arg1
);
13501 rtx op2
= expand_normal (arg2
);
13502 rtx op3
= expand_normal (arg3
);
13503 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13504 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
13506 gcc_assert (mode0
== mode1
);
13508 if (arg0
== error_mark_node
|| arg1
== error_mark_node
13509 || arg2
== error_mark_node
|| arg3
== error_mark_node
)
13513 || GET_MODE (target
) != mode0
13514 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode0
))
13515 target
= gen_reg_rtx (mode0
);
13517 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13518 op0
= copy_to_mode_reg (mode0
, op0
);
13519 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
13520 op1
= copy_to_mode_reg (mode0
, op1
);
13521 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
13522 op2
= copy_to_mode_reg (mode0
, op2
);
13523 if (! (*insn_data
[icode
].operand
[1].predicate
) (op3
, mode1
))
13524 op3
= copy_to_mode_reg (mode0
, op3
);
13526 /* Generate the compare. */
13527 scratch
= gen_reg_rtx (CCmode
);
13528 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
13533 if (mode0
== V2SImode
)
13534 emit_insn (gen_spe_evsel (target
, op2
, op3
, scratch
));
13536 emit_insn (gen_spe_evsel_fs (target
, op2
, op3
, scratch
));
13541 /* Raise an error message for a builtin function that is called without the
13542 appropriate target options being set. */
13545 rs6000_invalid_builtin (enum rs6000_builtins fncode
)
13547 size_t uns_fncode
= (size_t)fncode
;
13548 const char *name
= rs6000_builtin_info
[uns_fncode
].name
;
13549 HOST_WIDE_INT fnmask
= rs6000_builtin_info
[uns_fncode
].mask
;
13551 gcc_assert (name
!= NULL
);
13552 if ((fnmask
& RS6000_BTM_CELL
) != 0)
13553 error ("Builtin function %s is only valid for the cell processor", name
);
13554 else if ((fnmask
& RS6000_BTM_VSX
) != 0)
13555 error ("Builtin function %s requires the -mvsx option", name
);
13556 else if ((fnmask
& RS6000_BTM_HTM
) != 0)
13557 error ("Builtin function %s requires the -mhtm option", name
);
13558 else if ((fnmask
& RS6000_BTM_ALTIVEC
) != 0)
13559 error ("Builtin function %s requires the -maltivec option", name
);
13560 else if ((fnmask
& RS6000_BTM_PAIRED
) != 0)
13561 error ("Builtin function %s requires the -mpaired option", name
);
13562 else if ((fnmask
& RS6000_BTM_SPE
) != 0)
13563 error ("Builtin function %s requires the -mspe option", name
);
13564 else if ((fnmask
& (RS6000_BTM_DFP
| RS6000_BTM_P8_VECTOR
))
13565 == (RS6000_BTM_DFP
| RS6000_BTM_P8_VECTOR
))
13566 error ("Builtin function %s requires the -mhard-dfp and"
13567 "-mpower8-vector options", name
);
13568 else if ((fnmask
& RS6000_BTM_DFP
) != 0)
13569 error ("Builtin function %s requires the -mhard-dfp option", name
);
13570 else if ((fnmask
& RS6000_BTM_P8_VECTOR
) != 0)
13571 error ("Builtin function %s requires the -mpower8-vector option", name
);
13572 else if ((fnmask
& RS6000_BTM_HARD_FLOAT
) != 0)
13573 error ("Builtin function %s requires the -mhard-float option", name
);
13575 error ("Builtin function %s is not supported with the current options",
13579 /* Expand an expression EXP that calls a built-in function,
13580 with result going to TARGET if that's convenient
13581 (and in mode MODE if that's convenient).
13582 SUBTARGET may be used as the target for computing one of EXP's operands.
13583 IGNORE is nonzero if the value is to be ignored. */
13586 rs6000_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
13587 enum machine_mode mode ATTRIBUTE_UNUSED
,
13588 int ignore ATTRIBUTE_UNUSED
)
13590 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13591 enum rs6000_builtins fcode
13592 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
13593 size_t uns_fcode
= (size_t)fcode
;
13594 const struct builtin_description
*d
;
13598 HOST_WIDE_INT mask
= rs6000_builtin_info
[uns_fcode
].mask
;
13599 bool func_valid_p
= ((rs6000_builtin_mask
& mask
) == mask
);
13601 if (TARGET_DEBUG_BUILTIN
)
13603 enum insn_code icode
= rs6000_builtin_info
[uns_fcode
].icode
;
13604 const char *name1
= rs6000_builtin_info
[uns_fcode
].name
;
13605 const char *name2
= ((icode
!= CODE_FOR_nothing
)
13606 ? get_insn_name ((int)icode
)
13610 switch (rs6000_builtin_info
[uns_fcode
].attr
& RS6000_BTC_TYPE_MASK
)
13612 default: name3
= "unknown"; break;
13613 case RS6000_BTC_SPECIAL
: name3
= "special"; break;
13614 case RS6000_BTC_UNARY
: name3
= "unary"; break;
13615 case RS6000_BTC_BINARY
: name3
= "binary"; break;
13616 case RS6000_BTC_TERNARY
: name3
= "ternary"; break;
13617 case RS6000_BTC_PREDICATE
: name3
= "predicate"; break;
13618 case RS6000_BTC_ABS
: name3
= "abs"; break;
13619 case RS6000_BTC_EVSEL
: name3
= "evsel"; break;
13620 case RS6000_BTC_DST
: name3
= "dst"; break;
13625 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
13626 (name1
) ? name1
: "---", fcode
,
13627 (name2
) ? name2
: "---", (int)icode
,
13629 func_valid_p
? "" : ", not valid");
13634 rs6000_invalid_builtin (fcode
);
13636 /* Given it is invalid, just generate a normal call. */
13637 return expand_call (exp
, target
, ignore
);
13642 case RS6000_BUILTIN_RECIP
:
13643 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3
, exp
, target
);
13645 case RS6000_BUILTIN_RECIPF
:
13646 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3
, exp
, target
);
13648 case RS6000_BUILTIN_RSQRTF
:
13649 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2
, exp
, target
);
13651 case RS6000_BUILTIN_RSQRT
:
13652 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2
, exp
, target
);
13654 case POWER7_BUILTIN_BPERMD
:
13655 return rs6000_expand_binop_builtin (((TARGET_64BIT
)
13656 ? CODE_FOR_bpermd_di
13657 : CODE_FOR_bpermd_si
), exp
, target
);
13659 case RS6000_BUILTIN_GET_TB
:
13660 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase
,
13663 case RS6000_BUILTIN_MFTB
:
13664 return rs6000_expand_zeroop_builtin (((TARGET_64BIT
)
13665 ? CODE_FOR_rs6000_mftb_di
13666 : CODE_FOR_rs6000_mftb_si
),
13669 case RS6000_BUILTIN_MFFS
:
13670 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs
, target
);
13672 case RS6000_BUILTIN_MTFSF
:
13673 return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf
, exp
);
13675 case ALTIVEC_BUILTIN_MASK_FOR_LOAD
:
13676 case ALTIVEC_BUILTIN_MASK_FOR_STORE
:
13678 int icode
= (BYTES_BIG_ENDIAN
? (int) CODE_FOR_altivec_lvsr
13679 : (int) CODE_FOR_altivec_lvsl
);
13680 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13681 enum machine_mode mode
= insn_data
[icode
].operand
[1].mode
;
13685 gcc_assert (TARGET_ALTIVEC
);
13687 arg
= CALL_EXPR_ARG (exp
, 0);
13688 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg
)));
13689 op
= expand_expr (arg
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
13690 addr
= memory_address (mode
, op
);
13691 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
13695 /* For the load case need to negate the address. */
13696 op
= gen_reg_rtx (GET_MODE (addr
));
13697 emit_insn (gen_rtx_SET (VOIDmode
, op
,
13698 gen_rtx_NEG (GET_MODE (addr
), addr
)));
13700 op
= gen_rtx_MEM (mode
, op
);
13703 || GET_MODE (target
) != tmode
13704 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13705 target
= gen_reg_rtx (tmode
);
13707 /*pat = gen_altivec_lvsr (target, op);*/
13708 pat
= GEN_FCN (icode
) (target
, op
);
13716 case ALTIVEC_BUILTIN_VCFUX
:
13717 case ALTIVEC_BUILTIN_VCFSX
:
13718 case ALTIVEC_BUILTIN_VCTUXS
:
13719 case ALTIVEC_BUILTIN_VCTSXS
:
13720 /* FIXME: There's got to be a nicer way to handle this case than
13721 constructing a new CALL_EXPR. */
13722 if (call_expr_nargs (exp
) == 1)
13724 exp
= build_call_nary (TREE_TYPE (exp
), CALL_EXPR_FN (exp
),
13725 2, CALL_EXPR_ARG (exp
, 0), integer_zero_node
);
13733 if (TARGET_ALTIVEC
)
13735 ret
= altivec_expand_builtin (exp
, target
, &success
);
13742 ret
= spe_expand_builtin (exp
, target
, &success
);
13747 if (TARGET_PAIRED_FLOAT
)
13749 ret
= paired_expand_builtin (exp
, target
, &success
);
13756 ret
= htm_expand_builtin (exp
, target
, &success
);
13762 unsigned attr
= rs6000_builtin_info
[uns_fcode
].attr
& RS6000_BTC_TYPE_MASK
;
13763 gcc_assert (attr
== RS6000_BTC_UNARY
13764 || attr
== RS6000_BTC_BINARY
13765 || attr
== RS6000_BTC_TERNARY
);
13767 /* Handle simple unary operations. */
13769 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
13770 if (d
->code
== fcode
)
13771 return rs6000_expand_unop_builtin (d
->icode
, exp
, target
);
13773 /* Handle simple binary operations. */
13775 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
13776 if (d
->code
== fcode
)
13777 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
13779 /* Handle simple ternary operations. */
13781 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
13782 if (d
->code
== fcode
)
13783 return rs6000_expand_ternop_builtin (d
->icode
, exp
, target
);
13785 gcc_unreachable ();
13789 rs6000_init_builtins (void)
13793 enum machine_mode mode
;
13795 if (TARGET_DEBUG_BUILTIN
)
13796 fprintf (stderr
, "rs6000_init_builtins%s%s%s%s\n",
13797 (TARGET_PAIRED_FLOAT
) ? ", paired" : "",
13798 (TARGET_SPE
) ? ", spe" : "",
13799 (TARGET_ALTIVEC
) ? ", altivec" : "",
13800 (TARGET_VSX
) ? ", vsx" : "");
13802 V2SI_type_node
= build_vector_type (intSI_type_node
, 2);
13803 V2SF_type_node
= build_vector_type (float_type_node
, 2);
13804 V2DI_type_node
= build_vector_type (intDI_type_node
, 2);
13805 V2DF_type_node
= build_vector_type (double_type_node
, 2);
13806 V4HI_type_node
= build_vector_type (intHI_type_node
, 4);
13807 V4SI_type_node
= build_vector_type (intSI_type_node
, 4);
13808 V4SF_type_node
= build_vector_type (float_type_node
, 4);
13809 V8HI_type_node
= build_vector_type (intHI_type_node
, 8);
13810 V16QI_type_node
= build_vector_type (intQI_type_node
, 16);
13812 unsigned_V16QI_type_node
= build_vector_type (unsigned_intQI_type_node
, 16);
13813 unsigned_V8HI_type_node
= build_vector_type (unsigned_intHI_type_node
, 8);
13814 unsigned_V4SI_type_node
= build_vector_type (unsigned_intSI_type_node
, 4);
13815 unsigned_V2DI_type_node
= build_vector_type (unsigned_intDI_type_node
, 2);
13817 opaque_V2SF_type_node
= build_opaque_vector_type (float_type_node
, 2);
13818 opaque_V2SI_type_node
= build_opaque_vector_type (intSI_type_node
, 2);
13819 opaque_p_V2SI_type_node
= build_pointer_type (opaque_V2SI_type_node
);
13820 opaque_V4SI_type_node
= build_opaque_vector_type (intSI_type_node
, 4);
13822 /* We use V1TI mode as a special container to hold __int128_t items that
13823 must live in VSX registers. */
13824 if (intTI_type_node
)
13826 V1TI_type_node
= build_vector_type (intTI_type_node
, 1);
13827 unsigned_V1TI_type_node
= build_vector_type (unsigned_intTI_type_node
, 1);
13830 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
13831 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
13832 'vector unsigned short'. */
13834 bool_char_type_node
= build_distinct_type_copy (unsigned_intQI_type_node
);
13835 bool_short_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
13836 bool_int_type_node
= build_distinct_type_copy (unsigned_intSI_type_node
);
13837 bool_long_type_node
= build_distinct_type_copy (unsigned_intDI_type_node
);
13838 pixel_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
13840 long_integer_type_internal_node
= long_integer_type_node
;
13841 long_unsigned_type_internal_node
= long_unsigned_type_node
;
13842 long_long_integer_type_internal_node
= long_long_integer_type_node
;
13843 long_long_unsigned_type_internal_node
= long_long_unsigned_type_node
;
13844 intQI_type_internal_node
= intQI_type_node
;
13845 uintQI_type_internal_node
= unsigned_intQI_type_node
;
13846 intHI_type_internal_node
= intHI_type_node
;
13847 uintHI_type_internal_node
= unsigned_intHI_type_node
;
13848 intSI_type_internal_node
= intSI_type_node
;
13849 uintSI_type_internal_node
= unsigned_intSI_type_node
;
13850 intDI_type_internal_node
= intDI_type_node
;
13851 uintDI_type_internal_node
= unsigned_intDI_type_node
;
13852 intTI_type_internal_node
= intTI_type_node
;
13853 uintTI_type_internal_node
= unsigned_intTI_type_node
;
13854 float_type_internal_node
= float_type_node
;
13855 double_type_internal_node
= double_type_node
;
13856 long_double_type_internal_node
= long_double_type_node
;
13857 dfloat64_type_internal_node
= dfloat64_type_node
;
13858 dfloat128_type_internal_node
= dfloat128_type_node
;
13859 void_type_internal_node
= void_type_node
;
13861 /* Initialize the modes for builtin_function_type, mapping a machine mode to
13863 builtin_mode_to_type
[QImode
][0] = integer_type_node
;
13864 builtin_mode_to_type
[HImode
][0] = integer_type_node
;
13865 builtin_mode_to_type
[SImode
][0] = intSI_type_node
;
13866 builtin_mode_to_type
[SImode
][1] = unsigned_intSI_type_node
;
13867 builtin_mode_to_type
[DImode
][0] = intDI_type_node
;
13868 builtin_mode_to_type
[DImode
][1] = unsigned_intDI_type_node
;
13869 builtin_mode_to_type
[TImode
][0] = intTI_type_node
;
13870 builtin_mode_to_type
[TImode
][1] = unsigned_intTI_type_node
;
13871 builtin_mode_to_type
[SFmode
][0] = float_type_node
;
13872 builtin_mode_to_type
[DFmode
][0] = double_type_node
;
13873 builtin_mode_to_type
[TFmode
][0] = long_double_type_node
;
13874 builtin_mode_to_type
[DDmode
][0] = dfloat64_type_node
;
13875 builtin_mode_to_type
[TDmode
][0] = dfloat128_type_node
;
13876 builtin_mode_to_type
[V1TImode
][0] = V1TI_type_node
;
13877 builtin_mode_to_type
[V1TImode
][1] = unsigned_V1TI_type_node
;
13878 builtin_mode_to_type
[V2SImode
][0] = V2SI_type_node
;
13879 builtin_mode_to_type
[V2SFmode
][0] = V2SF_type_node
;
13880 builtin_mode_to_type
[V2DImode
][0] = V2DI_type_node
;
13881 builtin_mode_to_type
[V2DImode
][1] = unsigned_V2DI_type_node
;
13882 builtin_mode_to_type
[V2DFmode
][0] = V2DF_type_node
;
13883 builtin_mode_to_type
[V4HImode
][0] = V4HI_type_node
;
13884 builtin_mode_to_type
[V4SImode
][0] = V4SI_type_node
;
13885 builtin_mode_to_type
[V4SImode
][1] = unsigned_V4SI_type_node
;
13886 builtin_mode_to_type
[V4SFmode
][0] = V4SF_type_node
;
13887 builtin_mode_to_type
[V8HImode
][0] = V8HI_type_node
;
13888 builtin_mode_to_type
[V8HImode
][1] = unsigned_V8HI_type_node
;
13889 builtin_mode_to_type
[V16QImode
][0] = V16QI_type_node
;
13890 builtin_mode_to_type
[V16QImode
][1] = unsigned_V16QI_type_node
;
13892 tdecl
= add_builtin_type ("__bool char", bool_char_type_node
);
13893 TYPE_NAME (bool_char_type_node
) = tdecl
;
13895 tdecl
= add_builtin_type ("__bool short", bool_short_type_node
);
13896 TYPE_NAME (bool_short_type_node
) = tdecl
;
13898 tdecl
= add_builtin_type ("__bool int", bool_int_type_node
);
13899 TYPE_NAME (bool_int_type_node
) = tdecl
;
13901 tdecl
= add_builtin_type ("__pixel", pixel_type_node
);
13902 TYPE_NAME (pixel_type_node
) = tdecl
;
13904 bool_V16QI_type_node
= build_vector_type (bool_char_type_node
, 16);
13905 bool_V8HI_type_node
= build_vector_type (bool_short_type_node
, 8);
13906 bool_V4SI_type_node
= build_vector_type (bool_int_type_node
, 4);
13907 bool_V2DI_type_node
= build_vector_type (bool_long_type_node
, 2);
13908 pixel_V8HI_type_node
= build_vector_type (pixel_type_node
, 8);
13910 tdecl
= add_builtin_type ("__vector unsigned char", unsigned_V16QI_type_node
);
13911 TYPE_NAME (unsigned_V16QI_type_node
) = tdecl
;
13913 tdecl
= add_builtin_type ("__vector signed char", V16QI_type_node
);
13914 TYPE_NAME (V16QI_type_node
) = tdecl
;
13916 tdecl
= add_builtin_type ("__vector __bool char", bool_V16QI_type_node
);
13917 TYPE_NAME ( bool_V16QI_type_node
) = tdecl
;
13919 tdecl
= add_builtin_type ("__vector unsigned short", unsigned_V8HI_type_node
);
13920 TYPE_NAME (unsigned_V8HI_type_node
) = tdecl
;
13922 tdecl
= add_builtin_type ("__vector signed short", V8HI_type_node
);
13923 TYPE_NAME (V8HI_type_node
) = tdecl
;
13925 tdecl
= add_builtin_type ("__vector __bool short", bool_V8HI_type_node
);
13926 TYPE_NAME (bool_V8HI_type_node
) = tdecl
;
13928 tdecl
= add_builtin_type ("__vector unsigned int", unsigned_V4SI_type_node
);
13929 TYPE_NAME (unsigned_V4SI_type_node
) = tdecl
;
13931 tdecl
= add_builtin_type ("__vector signed int", V4SI_type_node
);
13932 TYPE_NAME (V4SI_type_node
) = tdecl
;
13934 tdecl
= add_builtin_type ("__vector __bool int", bool_V4SI_type_node
);
13935 TYPE_NAME (bool_V4SI_type_node
) = tdecl
;
13937 tdecl
= add_builtin_type ("__vector float", V4SF_type_node
);
13938 TYPE_NAME (V4SF_type_node
) = tdecl
;
13940 tdecl
= add_builtin_type ("__vector __pixel", pixel_V8HI_type_node
);
13941 TYPE_NAME (pixel_V8HI_type_node
) = tdecl
;
13943 tdecl
= add_builtin_type ("__vector double", V2DF_type_node
);
13944 TYPE_NAME (V2DF_type_node
) = tdecl
;
13946 if (TARGET_POWERPC64
)
13948 tdecl
= add_builtin_type ("__vector long", V2DI_type_node
);
13949 TYPE_NAME (V2DI_type_node
) = tdecl
;
13951 tdecl
= add_builtin_type ("__vector unsigned long",
13952 unsigned_V2DI_type_node
);
13953 TYPE_NAME (unsigned_V2DI_type_node
) = tdecl
;
13955 tdecl
= add_builtin_type ("__vector __bool long", bool_V2DI_type_node
);
13956 TYPE_NAME (bool_V2DI_type_node
) = tdecl
;
13960 tdecl
= add_builtin_type ("__vector long long", V2DI_type_node
);
13961 TYPE_NAME (V2DI_type_node
) = tdecl
;
13963 tdecl
= add_builtin_type ("__vector unsigned long long",
13964 unsigned_V2DI_type_node
);
13965 TYPE_NAME (unsigned_V2DI_type_node
) = tdecl
;
13967 tdecl
= add_builtin_type ("__vector __bool long long",
13968 bool_V2DI_type_node
);
13969 TYPE_NAME (bool_V2DI_type_node
) = tdecl
;
13972 if (V1TI_type_node
)
13974 tdecl
= add_builtin_type ("__vector __int128", V1TI_type_node
);
13975 TYPE_NAME (V1TI_type_node
) = tdecl
;
13977 tdecl
= add_builtin_type ("__vector unsigned __int128",
13978 unsigned_V1TI_type_node
);
13979 TYPE_NAME (unsigned_V1TI_type_node
) = tdecl
;
13982 /* Paired and SPE builtins are only available if you build a compiler with
13983 the appropriate options, so only create those builtins with the
13984 appropriate compiler option. Create Altivec and VSX builtins on machines
13985 with at least the general purpose extensions (970 and newer) to allow the
13986 use of the target attribute. */
13987 if (TARGET_PAIRED_FLOAT
)
13988 paired_init_builtins ();
13990 spe_init_builtins ();
13991 if (TARGET_EXTRA_BUILTINS
)
13992 altivec_init_builtins ();
13994 htm_init_builtins ();
13996 if (TARGET_EXTRA_BUILTINS
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
)
13997 rs6000_common_init_builtins ();
13999 ftype
= builtin_function_type (DFmode
, DFmode
, DFmode
, VOIDmode
,
14000 RS6000_BUILTIN_RECIP
, "__builtin_recipdiv");
14001 def_builtin ("__builtin_recipdiv", ftype
, RS6000_BUILTIN_RECIP
);
14003 ftype
= builtin_function_type (SFmode
, SFmode
, SFmode
, VOIDmode
,
14004 RS6000_BUILTIN_RECIPF
, "__builtin_recipdivf");
14005 def_builtin ("__builtin_recipdivf", ftype
, RS6000_BUILTIN_RECIPF
);
14007 ftype
= builtin_function_type (DFmode
, DFmode
, VOIDmode
, VOIDmode
,
14008 RS6000_BUILTIN_RSQRT
, "__builtin_rsqrt");
14009 def_builtin ("__builtin_rsqrt", ftype
, RS6000_BUILTIN_RSQRT
);
14011 ftype
= builtin_function_type (SFmode
, SFmode
, VOIDmode
, VOIDmode
,
14012 RS6000_BUILTIN_RSQRTF
, "__builtin_rsqrtf");
14013 def_builtin ("__builtin_rsqrtf", ftype
, RS6000_BUILTIN_RSQRTF
);
14015 mode
= (TARGET_64BIT
) ? DImode
: SImode
;
14016 ftype
= builtin_function_type (mode
, mode
, mode
, VOIDmode
,
14017 POWER7_BUILTIN_BPERMD
, "__builtin_bpermd");
14018 def_builtin ("__builtin_bpermd", ftype
, POWER7_BUILTIN_BPERMD
);
14020 ftype
= build_function_type_list (unsigned_intDI_type_node
,
14022 def_builtin ("__builtin_ppc_get_timebase", ftype
, RS6000_BUILTIN_GET_TB
);
14025 ftype
= build_function_type_list (unsigned_intDI_type_node
,
14028 ftype
= build_function_type_list (unsigned_intSI_type_node
,
14030 def_builtin ("__builtin_ppc_mftb", ftype
, RS6000_BUILTIN_MFTB
);
14032 ftype
= build_function_type_list (double_type_node
, NULL_TREE
);
14033 def_builtin ("__builtin_mffs", ftype
, RS6000_BUILTIN_MFFS
);
14035 ftype
= build_function_type_list (void_type_node
,
14036 intSI_type_node
, double_type_node
,
14038 def_builtin ("__builtin_mtfsf", ftype
, RS6000_BUILTIN_MTFSF
);
14041 /* AIX libm provides clog as __clog. */
14042 if ((tdecl
= builtin_decl_explicit (BUILT_IN_CLOG
)) != NULL_TREE
)
14043 set_user_assembler_name (tdecl
, "__clog");
14046 #ifdef SUBTARGET_INIT_BUILTINS
14047 SUBTARGET_INIT_BUILTINS
;
14051 /* Returns the rs6000 builtin decl for CODE. */
14054 rs6000_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
14056 HOST_WIDE_INT fnmask
;
14058 if (code
>= RS6000_BUILTIN_COUNT
)
14059 return error_mark_node
;
14061 fnmask
= rs6000_builtin_info
[code
].mask
;
14062 if ((fnmask
& rs6000_builtin_mask
) != fnmask
)
14064 rs6000_invalid_builtin ((enum rs6000_builtins
)code
);
14065 return error_mark_node
;
14068 return rs6000_builtin_decls
[code
];
14072 spe_init_builtins (void)
14074 tree puint_type_node
= build_pointer_type (unsigned_type_node
);
14075 tree pushort_type_node
= build_pointer_type (short_unsigned_type_node
);
14076 const struct builtin_description
*d
;
14079 tree v2si_ftype_4_v2si
14080 = build_function_type_list (opaque_V2SI_type_node
,
14081 opaque_V2SI_type_node
,
14082 opaque_V2SI_type_node
,
14083 opaque_V2SI_type_node
,
14084 opaque_V2SI_type_node
,
14087 tree v2sf_ftype_4_v2sf
14088 = build_function_type_list (opaque_V2SF_type_node
,
14089 opaque_V2SF_type_node
,
14090 opaque_V2SF_type_node
,
14091 opaque_V2SF_type_node
,
14092 opaque_V2SF_type_node
,
14095 tree int_ftype_int_v2si_v2si
14096 = build_function_type_list (integer_type_node
,
14098 opaque_V2SI_type_node
,
14099 opaque_V2SI_type_node
,
14102 tree int_ftype_int_v2sf_v2sf
14103 = build_function_type_list (integer_type_node
,
14105 opaque_V2SF_type_node
,
14106 opaque_V2SF_type_node
,
14109 tree void_ftype_v2si_puint_int
14110 = build_function_type_list (void_type_node
,
14111 opaque_V2SI_type_node
,
14116 tree void_ftype_v2si_puint_char
14117 = build_function_type_list (void_type_node
,
14118 opaque_V2SI_type_node
,
14123 tree void_ftype_v2si_pv2si_int
14124 = build_function_type_list (void_type_node
,
14125 opaque_V2SI_type_node
,
14126 opaque_p_V2SI_type_node
,
14130 tree void_ftype_v2si_pv2si_char
14131 = build_function_type_list (void_type_node
,
14132 opaque_V2SI_type_node
,
14133 opaque_p_V2SI_type_node
,
14137 tree void_ftype_int
14138 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
14140 tree int_ftype_void
14141 = build_function_type_list (integer_type_node
, NULL_TREE
);
14143 tree v2si_ftype_pv2si_int
14144 = build_function_type_list (opaque_V2SI_type_node
,
14145 opaque_p_V2SI_type_node
,
14149 tree v2si_ftype_puint_int
14150 = build_function_type_list (opaque_V2SI_type_node
,
14155 tree v2si_ftype_pushort_int
14156 = build_function_type_list (opaque_V2SI_type_node
,
14161 tree v2si_ftype_signed_char
14162 = build_function_type_list (opaque_V2SI_type_node
,
14163 signed_char_type_node
,
14166 add_builtin_type ("__ev64_opaque__", opaque_V2SI_type_node
);
14168 /* Initialize irregular SPE builtins. */
14170 def_builtin ("__builtin_spe_mtspefscr", void_ftype_int
, SPE_BUILTIN_MTSPEFSCR
);
14171 def_builtin ("__builtin_spe_mfspefscr", int_ftype_void
, SPE_BUILTIN_MFSPEFSCR
);
14172 def_builtin ("__builtin_spe_evstddx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDDX
);
14173 def_builtin ("__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDHX
);
14174 def_builtin ("__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDWX
);
14175 def_builtin ("__builtin_spe_evstwhex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHEX
);
14176 def_builtin ("__builtin_spe_evstwhox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHOX
);
14177 def_builtin ("__builtin_spe_evstwwex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWEX
);
14178 def_builtin ("__builtin_spe_evstwwox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWOX
);
14179 def_builtin ("__builtin_spe_evstdd", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDD
);
14180 def_builtin ("__builtin_spe_evstdh", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDH
);
14181 def_builtin ("__builtin_spe_evstdw", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDW
);
14182 def_builtin ("__builtin_spe_evstwhe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHE
);
14183 def_builtin ("__builtin_spe_evstwho", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHO
);
14184 def_builtin ("__builtin_spe_evstwwe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWE
);
14185 def_builtin ("__builtin_spe_evstwwo", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWO
);
14186 def_builtin ("__builtin_spe_evsplatfi", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATFI
);
14187 def_builtin ("__builtin_spe_evsplati", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATI
);
14190 def_builtin ("__builtin_spe_evlddx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDDX
);
14191 def_builtin ("__builtin_spe_evldwx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDWX
);
14192 def_builtin ("__builtin_spe_evldhx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDHX
);
14193 def_builtin ("__builtin_spe_evlwhex", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHEX
);
14194 def_builtin ("__builtin_spe_evlwhoux", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOUX
);
14195 def_builtin ("__builtin_spe_evlwhosx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOSX
);
14196 def_builtin ("__builtin_spe_evlwwsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLATX
);
14197 def_builtin ("__builtin_spe_evlwhsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLATX
);
14198 def_builtin ("__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLATX
);
14199 def_builtin ("__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLATX
);
14200 def_builtin ("__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLATX
);
14201 def_builtin ("__builtin_spe_evldd", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDD
);
14202 def_builtin ("__builtin_spe_evldw", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDW
);
14203 def_builtin ("__builtin_spe_evldh", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDH
);
14204 def_builtin ("__builtin_spe_evlhhesplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLAT
);
14205 def_builtin ("__builtin_spe_evlhhossplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLAT
);
14206 def_builtin ("__builtin_spe_evlhhousplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLAT
);
14207 def_builtin ("__builtin_spe_evlwhe", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHE
);
14208 def_builtin ("__builtin_spe_evlwhos", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOS
);
14209 def_builtin ("__builtin_spe_evlwhou", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOU
);
14210 def_builtin ("__builtin_spe_evlwhsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLAT
);
14211 def_builtin ("__builtin_spe_evlwwsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLAT
);
14214 d
= bdesc_spe_predicates
;
14215 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, d
++)
14219 switch (insn_data
[d
->icode
].operand
[1].mode
)
14222 type
= int_ftype_int_v2si_v2si
;
14225 type
= int_ftype_int_v2sf_v2sf
;
14228 gcc_unreachable ();
14231 def_builtin (d
->name
, type
, d
->code
);
14234 /* Evsel predicates. */
14235 d
= bdesc_spe_evsel
;
14236 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, d
++)
14240 switch (insn_data
[d
->icode
].operand
[1].mode
)
14243 type
= v2si_ftype_4_v2si
;
14246 type
= v2sf_ftype_4_v2sf
;
14249 gcc_unreachable ();
14252 def_builtin (d
->name
, type
, d
->code
);
14257 paired_init_builtins (void)
14259 const struct builtin_description
*d
;
14262 tree int_ftype_int_v2sf_v2sf
14263 = build_function_type_list (integer_type_node
,
14268 tree pcfloat_type_node
=
14269 build_pointer_type (build_qualified_type
14270 (float_type_node
, TYPE_QUAL_CONST
));
14272 tree v2sf_ftype_long_pcfloat
= build_function_type_list (V2SF_type_node
,
14273 long_integer_type_node
,
14276 tree void_ftype_v2sf_long_pcfloat
=
14277 build_function_type_list (void_type_node
,
14279 long_integer_type_node
,
14284 def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat
,
14285 PAIRED_BUILTIN_LX
);
14288 def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat
,
14289 PAIRED_BUILTIN_STX
);
14292 d
= bdesc_paired_preds
;
14293 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); ++i
, d
++)
14297 if (TARGET_DEBUG_BUILTIN
)
14298 fprintf (stderr
, "paired pred #%d, insn = %s [%d], mode = %s\n",
14299 (int)i
, get_insn_name (d
->icode
), (int)d
->icode
,
14300 GET_MODE_NAME (insn_data
[d
->icode
].operand
[1].mode
));
14302 switch (insn_data
[d
->icode
].operand
[1].mode
)
14305 type
= int_ftype_int_v2sf_v2sf
;
14308 gcc_unreachable ();
14311 def_builtin (d
->name
, type
, d
->code
);
14316 altivec_init_builtins (void)
14318 const struct builtin_description
*d
;
14323 tree pvoid_type_node
= build_pointer_type (void_type_node
);
14325 tree pcvoid_type_node
14326 = build_pointer_type (build_qualified_type (void_type_node
,
14329 tree int_ftype_opaque
14330 = build_function_type_list (integer_type_node
,
14331 opaque_V4SI_type_node
, NULL_TREE
);
14332 tree opaque_ftype_opaque
14333 = build_function_type_list (integer_type_node
, NULL_TREE
);
14334 tree opaque_ftype_opaque_int
14335 = build_function_type_list (opaque_V4SI_type_node
,
14336 opaque_V4SI_type_node
, integer_type_node
, NULL_TREE
);
14337 tree opaque_ftype_opaque_opaque_int
14338 = build_function_type_list (opaque_V4SI_type_node
,
14339 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
14340 integer_type_node
, NULL_TREE
);
14341 tree int_ftype_int_opaque_opaque
14342 = build_function_type_list (integer_type_node
,
14343 integer_type_node
, opaque_V4SI_type_node
,
14344 opaque_V4SI_type_node
, NULL_TREE
);
14345 tree int_ftype_int_v4si_v4si
14346 = build_function_type_list (integer_type_node
,
14347 integer_type_node
, V4SI_type_node
,
14348 V4SI_type_node
, NULL_TREE
);
14349 tree int_ftype_int_v2di_v2di
14350 = build_function_type_list (integer_type_node
,
14351 integer_type_node
, V2DI_type_node
,
14352 V2DI_type_node
, NULL_TREE
);
14353 tree void_ftype_v4si
14354 = build_function_type_list (void_type_node
, V4SI_type_node
, NULL_TREE
);
14355 tree v8hi_ftype_void
14356 = build_function_type_list (V8HI_type_node
, NULL_TREE
);
14357 tree void_ftype_void
14358 = build_function_type_list (void_type_node
, NULL_TREE
);
14359 tree void_ftype_int
14360 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
14362 tree opaque_ftype_long_pcvoid
14363 = build_function_type_list (opaque_V4SI_type_node
,
14364 long_integer_type_node
, pcvoid_type_node
,
14366 tree v16qi_ftype_long_pcvoid
14367 = build_function_type_list (V16QI_type_node
,
14368 long_integer_type_node
, pcvoid_type_node
,
14370 tree v8hi_ftype_long_pcvoid
14371 = build_function_type_list (V8HI_type_node
,
14372 long_integer_type_node
, pcvoid_type_node
,
14374 tree v4si_ftype_long_pcvoid
14375 = build_function_type_list (V4SI_type_node
,
14376 long_integer_type_node
, pcvoid_type_node
,
14378 tree v4sf_ftype_long_pcvoid
14379 = build_function_type_list (V4SF_type_node
,
14380 long_integer_type_node
, pcvoid_type_node
,
14382 tree v2df_ftype_long_pcvoid
14383 = build_function_type_list (V2DF_type_node
,
14384 long_integer_type_node
, pcvoid_type_node
,
14386 tree v2di_ftype_long_pcvoid
14387 = build_function_type_list (V2DI_type_node
,
14388 long_integer_type_node
, pcvoid_type_node
,
14391 tree void_ftype_opaque_long_pvoid
14392 = build_function_type_list (void_type_node
,
14393 opaque_V4SI_type_node
, long_integer_type_node
,
14394 pvoid_type_node
, NULL_TREE
);
14395 tree void_ftype_v4si_long_pvoid
14396 = build_function_type_list (void_type_node
,
14397 V4SI_type_node
, long_integer_type_node
,
14398 pvoid_type_node
, NULL_TREE
);
14399 tree void_ftype_v16qi_long_pvoid
14400 = build_function_type_list (void_type_node
,
14401 V16QI_type_node
, long_integer_type_node
,
14402 pvoid_type_node
, NULL_TREE
);
14403 tree void_ftype_v8hi_long_pvoid
14404 = build_function_type_list (void_type_node
,
14405 V8HI_type_node
, long_integer_type_node
,
14406 pvoid_type_node
, NULL_TREE
);
14407 tree void_ftype_v4sf_long_pvoid
14408 = build_function_type_list (void_type_node
,
14409 V4SF_type_node
, long_integer_type_node
,
14410 pvoid_type_node
, NULL_TREE
);
14411 tree void_ftype_v2df_long_pvoid
14412 = build_function_type_list (void_type_node
,
14413 V2DF_type_node
, long_integer_type_node
,
14414 pvoid_type_node
, NULL_TREE
);
14415 tree void_ftype_v2di_long_pvoid
14416 = build_function_type_list (void_type_node
,
14417 V2DI_type_node
, long_integer_type_node
,
14418 pvoid_type_node
, NULL_TREE
);
14419 tree int_ftype_int_v8hi_v8hi
14420 = build_function_type_list (integer_type_node
,
14421 integer_type_node
, V8HI_type_node
,
14422 V8HI_type_node
, NULL_TREE
);
14423 tree int_ftype_int_v16qi_v16qi
14424 = build_function_type_list (integer_type_node
,
14425 integer_type_node
, V16QI_type_node
,
14426 V16QI_type_node
, NULL_TREE
);
14427 tree int_ftype_int_v4sf_v4sf
14428 = build_function_type_list (integer_type_node
,
14429 integer_type_node
, V4SF_type_node
,
14430 V4SF_type_node
, NULL_TREE
);
14431 tree int_ftype_int_v2df_v2df
14432 = build_function_type_list (integer_type_node
,
14433 integer_type_node
, V2DF_type_node
,
14434 V2DF_type_node
, NULL_TREE
);
14435 tree v2di_ftype_v2di
14436 = build_function_type_list (V2DI_type_node
, V2DI_type_node
, NULL_TREE
);
14437 tree v4si_ftype_v4si
14438 = build_function_type_list (V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
14439 tree v8hi_ftype_v8hi
14440 = build_function_type_list (V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
14441 tree v16qi_ftype_v16qi
14442 = build_function_type_list (V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
14443 tree v4sf_ftype_v4sf
14444 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
14445 tree v2df_ftype_v2df
14446 = build_function_type_list (V2DF_type_node
, V2DF_type_node
, NULL_TREE
);
14447 tree void_ftype_pcvoid_int_int
14448 = build_function_type_list (void_type_node
,
14449 pcvoid_type_node
, integer_type_node
,
14450 integer_type_node
, NULL_TREE
);
14452 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si
, ALTIVEC_BUILTIN_MTVSCR
);
14453 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void
, ALTIVEC_BUILTIN_MFVSCR
);
14454 def_builtin ("__builtin_altivec_dssall", void_ftype_void
, ALTIVEC_BUILTIN_DSSALL
);
14455 def_builtin ("__builtin_altivec_dss", void_ftype_int
, ALTIVEC_BUILTIN_DSS
);
14456 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSL
);
14457 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSR
);
14458 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEBX
);
14459 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEHX
);
14460 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEWX
);
14461 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVXL
);
14462 def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid
,
14463 ALTIVEC_BUILTIN_LVXL_V2DF
);
14464 def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid
,
14465 ALTIVEC_BUILTIN_LVXL_V2DI
);
14466 def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid
,
14467 ALTIVEC_BUILTIN_LVXL_V4SF
);
14468 def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid
,
14469 ALTIVEC_BUILTIN_LVXL_V4SI
);
14470 def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid
,
14471 ALTIVEC_BUILTIN_LVXL_V8HI
);
14472 def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid
,
14473 ALTIVEC_BUILTIN_LVXL_V16QI
);
14474 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVX
);
14475 def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid
,
14476 ALTIVEC_BUILTIN_LVX_V2DF
);
14477 def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid
,
14478 ALTIVEC_BUILTIN_LVX_V2DI
);
14479 def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid
,
14480 ALTIVEC_BUILTIN_LVX_V4SF
);
14481 def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid
,
14482 ALTIVEC_BUILTIN_LVX_V4SI
);
14483 def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid
,
14484 ALTIVEC_BUILTIN_LVX_V8HI
);
14485 def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid
,
14486 ALTIVEC_BUILTIN_LVX_V16QI
);
14487 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVX
);
14488 def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid
,
14489 ALTIVEC_BUILTIN_STVX_V2DF
);
14490 def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid
,
14491 ALTIVEC_BUILTIN_STVX_V2DI
);
14492 def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid
,
14493 ALTIVEC_BUILTIN_STVX_V4SF
);
14494 def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid
,
14495 ALTIVEC_BUILTIN_STVX_V4SI
);
14496 def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid
,
14497 ALTIVEC_BUILTIN_STVX_V8HI
);
14498 def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid
,
14499 ALTIVEC_BUILTIN_STVX_V16QI
);
14500 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVEWX
);
14501 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVXL
);
14502 def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid
,
14503 ALTIVEC_BUILTIN_STVXL_V2DF
);
14504 def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid
,
14505 ALTIVEC_BUILTIN_STVXL_V2DI
);
14506 def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid
,
14507 ALTIVEC_BUILTIN_STVXL_V4SF
);
14508 def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid
,
14509 ALTIVEC_BUILTIN_STVXL_V4SI
);
14510 def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid
,
14511 ALTIVEC_BUILTIN_STVXL_V8HI
);
14512 def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid
,
14513 ALTIVEC_BUILTIN_STVXL_V16QI
);
14514 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVEBX
);
14515 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid
, ALTIVEC_BUILTIN_STVEHX
);
14516 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LD
);
14517 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDE
);
14518 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDL
);
14519 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSL
);
14520 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSR
);
14521 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEBX
);
14522 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEHX
);
14523 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEWX
);
14524 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_ST
);
14525 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STE
);
14526 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STL
);
14527 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEWX
);
14528 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEBX
);
14529 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEHX
);
14531 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid
,
14532 VSX_BUILTIN_LXVD2X_V2DF
);
14533 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid
,
14534 VSX_BUILTIN_LXVD2X_V2DI
);
14535 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid
,
14536 VSX_BUILTIN_LXVW4X_V4SF
);
14537 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid
,
14538 VSX_BUILTIN_LXVW4X_V4SI
);
14539 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid
,
14540 VSX_BUILTIN_LXVW4X_V8HI
);
14541 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid
,
14542 VSX_BUILTIN_LXVW4X_V16QI
);
14543 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid
,
14544 VSX_BUILTIN_STXVD2X_V2DF
);
14545 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid
,
14546 VSX_BUILTIN_STXVD2X_V2DI
);
14547 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid
,
14548 VSX_BUILTIN_STXVW4X_V4SF
);
14549 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid
,
14550 VSX_BUILTIN_STXVW4X_V4SI
);
14551 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid
,
14552 VSX_BUILTIN_STXVW4X_V8HI
);
14553 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid
,
14554 VSX_BUILTIN_STXVW4X_V16QI
);
14555 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid
,
14556 VSX_BUILTIN_VEC_LD
);
14557 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid
,
14558 VSX_BUILTIN_VEC_ST
);
14560 def_builtin ("__builtin_vec_step", int_ftype_opaque
, ALTIVEC_BUILTIN_VEC_STEP
);
14561 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_SPLATS
);
14562 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_PROMOTE
);
14564 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_SLD
);
14565 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_SPLAT
);
14566 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_EXTRACT
);
14567 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_INSERT
);
14568 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTW
);
14569 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTH
);
14570 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTB
);
14571 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTF
);
14572 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFSX
);
14573 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFUX
);
14574 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTS
);
14575 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTU
);
14577 /* Cell builtins. */
14578 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLX
);
14579 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLXL
);
14580 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRX
);
14581 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRXL
);
14583 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLX
);
14584 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLXL
);
14585 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRX
);
14586 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRXL
);
14588 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLX
);
14589 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLXL
);
14590 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRX
);
14591 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRXL
);
14593 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLX
);
14594 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLXL
);
14595 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRX
);
14596 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRXL
);
14598 /* Add the DST variants. */
14600 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
14601 def_builtin (d
->name
, void_ftype_pcvoid_int_int
, d
->code
);
14603 /* Initialize the predicates. */
14604 d
= bdesc_altivec_preds
;
14605 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
14607 enum machine_mode mode1
;
14610 if (rs6000_overloaded_builtin_p (d
->code
))
14613 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
14618 type
= int_ftype_int_opaque_opaque
;
14621 type
= int_ftype_int_v2di_v2di
;
14624 type
= int_ftype_int_v4si_v4si
;
14627 type
= int_ftype_int_v8hi_v8hi
;
14630 type
= int_ftype_int_v16qi_v16qi
;
14633 type
= int_ftype_int_v4sf_v4sf
;
14636 type
= int_ftype_int_v2df_v2df
;
14639 gcc_unreachable ();
14642 def_builtin (d
->name
, type
, d
->code
);
14645 /* Initialize the abs* operators. */
14647 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
14649 enum machine_mode mode0
;
14652 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
14657 type
= v2di_ftype_v2di
;
14660 type
= v4si_ftype_v4si
;
14663 type
= v8hi_ftype_v8hi
;
14666 type
= v16qi_ftype_v16qi
;
14669 type
= v4sf_ftype_v4sf
;
14672 type
= v2df_ftype_v2df
;
14675 gcc_unreachable ();
14678 def_builtin (d
->name
, type
, d
->code
);
14681 /* Initialize target builtin that implements
14682 targetm.vectorize.builtin_mask_for_load. */
14684 decl
= add_builtin_function ("__builtin_altivec_mask_for_load",
14685 v16qi_ftype_long_pcvoid
,
14686 ALTIVEC_BUILTIN_MASK_FOR_LOAD
,
14687 BUILT_IN_MD
, NULL
, NULL_TREE
);
14688 TREE_READONLY (decl
) = 1;
14689 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
14690 altivec_builtin_mask_for_load
= decl
;
14692 /* Access to the vec_init patterns. */
14693 ftype
= build_function_type_list (V4SI_type_node
, integer_type_node
,
14694 integer_type_node
, integer_type_node
,
14695 integer_type_node
, NULL_TREE
);
14696 def_builtin ("__builtin_vec_init_v4si", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SI
);
14698 ftype
= build_function_type_list (V8HI_type_node
, short_integer_type_node
,
14699 short_integer_type_node
,
14700 short_integer_type_node
,
14701 short_integer_type_node
,
14702 short_integer_type_node
,
14703 short_integer_type_node
,
14704 short_integer_type_node
,
14705 short_integer_type_node
, NULL_TREE
);
14706 def_builtin ("__builtin_vec_init_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V8HI
);
14708 ftype
= build_function_type_list (V16QI_type_node
, char_type_node
,
14709 char_type_node
, char_type_node
,
14710 char_type_node
, char_type_node
,
14711 char_type_node
, char_type_node
,
14712 char_type_node
, char_type_node
,
14713 char_type_node
, char_type_node
,
14714 char_type_node
, char_type_node
,
14715 char_type_node
, char_type_node
,
14716 char_type_node
, NULL_TREE
);
14717 def_builtin ("__builtin_vec_init_v16qi", ftype
,
14718 ALTIVEC_BUILTIN_VEC_INIT_V16QI
);
14720 ftype
= build_function_type_list (V4SF_type_node
, float_type_node
,
14721 float_type_node
, float_type_node
,
14722 float_type_node
, NULL_TREE
);
14723 def_builtin ("__builtin_vec_init_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SF
);
14725 /* VSX builtins. */
14726 ftype
= build_function_type_list (V2DF_type_node
, double_type_node
,
14727 double_type_node
, NULL_TREE
);
14728 def_builtin ("__builtin_vec_init_v2df", ftype
, VSX_BUILTIN_VEC_INIT_V2DF
);
14730 ftype
= build_function_type_list (V2DI_type_node
, intDI_type_node
,
14731 intDI_type_node
, NULL_TREE
);
14732 def_builtin ("__builtin_vec_init_v2di", ftype
, VSX_BUILTIN_VEC_INIT_V2DI
);
14734 /* Access to the vec_set patterns. */
14735 ftype
= build_function_type_list (V4SI_type_node
, V4SI_type_node
,
14737 integer_type_node
, NULL_TREE
);
14738 def_builtin ("__builtin_vec_set_v4si", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SI
);
14740 ftype
= build_function_type_list (V8HI_type_node
, V8HI_type_node
,
14742 integer_type_node
, NULL_TREE
);
14743 def_builtin ("__builtin_vec_set_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V8HI
);
14745 ftype
= build_function_type_list (V16QI_type_node
, V16QI_type_node
,
14747 integer_type_node
, NULL_TREE
);
14748 def_builtin ("__builtin_vec_set_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V16QI
);
14750 ftype
= build_function_type_list (V4SF_type_node
, V4SF_type_node
,
14752 integer_type_node
, NULL_TREE
);
14753 def_builtin ("__builtin_vec_set_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SF
);
14755 ftype
= build_function_type_list (V2DF_type_node
, V2DF_type_node
,
14757 integer_type_node
, NULL_TREE
);
14758 def_builtin ("__builtin_vec_set_v2df", ftype
, VSX_BUILTIN_VEC_SET_V2DF
);
14760 ftype
= build_function_type_list (V2DI_type_node
, V2DI_type_node
,
14762 integer_type_node
, NULL_TREE
);
14763 def_builtin ("__builtin_vec_set_v2di", ftype
, VSX_BUILTIN_VEC_SET_V2DI
);
14765 /* Access to the vec_extract patterns. */
14766 ftype
= build_function_type_list (intSI_type_node
, V4SI_type_node
,
14767 integer_type_node
, NULL_TREE
);
14768 def_builtin ("__builtin_vec_ext_v4si", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SI
);
14770 ftype
= build_function_type_list (intHI_type_node
, V8HI_type_node
,
14771 integer_type_node
, NULL_TREE
);
14772 def_builtin ("__builtin_vec_ext_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V8HI
);
14774 ftype
= build_function_type_list (intQI_type_node
, V16QI_type_node
,
14775 integer_type_node
, NULL_TREE
);
14776 def_builtin ("__builtin_vec_ext_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V16QI
);
14778 ftype
= build_function_type_list (float_type_node
, V4SF_type_node
,
14779 integer_type_node
, NULL_TREE
);
14780 def_builtin ("__builtin_vec_ext_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SF
);
14782 ftype
= build_function_type_list (double_type_node
, V2DF_type_node
,
14783 integer_type_node
, NULL_TREE
);
14784 def_builtin ("__builtin_vec_ext_v2df", ftype
, VSX_BUILTIN_VEC_EXT_V2DF
);
14786 ftype
= build_function_type_list (intDI_type_node
, V2DI_type_node
,
14787 integer_type_node
, NULL_TREE
);
14788 def_builtin ("__builtin_vec_ext_v2di", ftype
, VSX_BUILTIN_VEC_EXT_V2DI
);
14791 if (V1TI_type_node
)
14793 tree v1ti_ftype_long_pcvoid
14794 = build_function_type_list (V1TI_type_node
,
14795 long_integer_type_node
, pcvoid_type_node
,
14797 tree void_ftype_v1ti_long_pvoid
14798 = build_function_type_list (void_type_node
,
14799 V1TI_type_node
, long_integer_type_node
,
14800 pvoid_type_node
, NULL_TREE
);
14801 def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid
,
14802 VSX_BUILTIN_LXVD2X_V1TI
);
14803 def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid
,
14804 VSX_BUILTIN_STXVD2X_V1TI
);
14805 ftype
= build_function_type_list (V1TI_type_node
, intTI_type_node
,
14806 NULL_TREE
, NULL_TREE
);
14807 def_builtin ("__builtin_vec_init_v1ti", ftype
, VSX_BUILTIN_VEC_INIT_V1TI
);
14808 ftype
= build_function_type_list (V1TI_type_node
, V1TI_type_node
,
14810 integer_type_node
, NULL_TREE
);
14811 def_builtin ("__builtin_vec_set_v1ti", ftype
, VSX_BUILTIN_VEC_SET_V1TI
);
14812 ftype
= build_function_type_list (intTI_type_node
, V1TI_type_node
,
14813 integer_type_node
, NULL_TREE
);
14814 def_builtin ("__builtin_vec_ext_v1ti", ftype
, VSX_BUILTIN_VEC_EXT_V1TI
);
14820 htm_init_builtins (void)
14822 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
14823 const struct builtin_description
*d
;
14827 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
14829 tree op
[MAX_HTM_OPERANDS
], type
;
14830 HOST_WIDE_INT mask
= d
->mask
;
14831 unsigned attr
= rs6000_builtin_info
[d
->code
].attr
;
14832 bool void_func
= (attr
& RS6000_BTC_VOID
);
14833 int attr_args
= (attr
& RS6000_BTC_TYPE_MASK
);
14835 tree argtype
= (attr
& RS6000_BTC_SPR
) ? long_unsigned_type_node
14836 : unsigned_type_node
;
14838 if ((mask
& builtin_mask
) != mask
)
14840 if (TARGET_DEBUG_BUILTIN
)
14841 fprintf (stderr
, "htm_builtin, skip binary %s\n", d
->name
);
14847 if (TARGET_DEBUG_BUILTIN
)
14848 fprintf (stderr
, "htm_builtin, bdesc_htm[%ld] no name\n",
14849 (long unsigned) i
);
14853 op
[nopnds
++] = (void_func
) ? void_type_node
: argtype
;
14855 if (attr_args
== RS6000_BTC_UNARY
)
14856 op
[nopnds
++] = argtype
;
14857 else if (attr_args
== RS6000_BTC_BINARY
)
14859 op
[nopnds
++] = argtype
;
14860 op
[nopnds
++] = argtype
;
14862 else if (attr_args
== RS6000_BTC_TERNARY
)
14864 op
[nopnds
++] = argtype
;
14865 op
[nopnds
++] = argtype
;
14866 op
[nopnds
++] = argtype
;
14872 type
= build_function_type_list (op
[0], NULL_TREE
);
14875 type
= build_function_type_list (op
[0], op
[1], NULL_TREE
);
14878 type
= build_function_type_list (op
[0], op
[1], op
[2], NULL_TREE
);
14881 type
= build_function_type_list (op
[0], op
[1], op
[2], op
[3],
14885 gcc_unreachable ();
14888 def_builtin (d
->name
, type
, d
->code
);
14892 /* Hash function for builtin functions with up to 3 arguments and a return
14895 builtin_hash_function (const void *hash_entry
)
14899 const struct builtin_hash_struct
*bh
=
14900 (const struct builtin_hash_struct
*) hash_entry
;
14902 for (i
= 0; i
< 4; i
++)
14904 ret
= (ret
* (unsigned)MAX_MACHINE_MODE
) + ((unsigned)bh
->mode
[i
]);
14905 ret
= (ret
* 2) + bh
->uns_p
[i
];
14911 /* Compare builtin hash entries H1 and H2 for equivalence. */
14913 builtin_hash_eq (const void *h1
, const void *h2
)
14915 const struct builtin_hash_struct
*p1
= (const struct builtin_hash_struct
*) h1
;
14916 const struct builtin_hash_struct
*p2
= (const struct builtin_hash_struct
*) h2
;
14918 return ((p1
->mode
[0] == p2
->mode
[0])
14919 && (p1
->mode
[1] == p2
->mode
[1])
14920 && (p1
->mode
[2] == p2
->mode
[2])
14921 && (p1
->mode
[3] == p2
->mode
[3])
14922 && (p1
->uns_p
[0] == p2
->uns_p
[0])
14923 && (p1
->uns_p
[1] == p2
->uns_p
[1])
14924 && (p1
->uns_p
[2] == p2
->uns_p
[2])
14925 && (p1
->uns_p
[3] == p2
->uns_p
[3]));
14928 /* Map types for builtin functions with an explicit return type and up to 3
14929 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
14930 of the argument. */
14932 builtin_function_type (enum machine_mode mode_ret
, enum machine_mode mode_arg0
,
14933 enum machine_mode mode_arg1
, enum machine_mode mode_arg2
,
14934 enum rs6000_builtins builtin
, const char *name
)
14936 struct builtin_hash_struct h
;
14937 struct builtin_hash_struct
*h2
;
14941 tree ret_type
= NULL_TREE
;
14942 tree arg_type
[3] = { NULL_TREE
, NULL_TREE
, NULL_TREE
};
14944 /* Create builtin_hash_table. */
14945 if (builtin_hash_table
== NULL
)
14946 builtin_hash_table
= htab_create_ggc (1500, builtin_hash_function
,
14947 builtin_hash_eq
, NULL
);
14949 h
.type
= NULL_TREE
;
14950 h
.mode
[0] = mode_ret
;
14951 h
.mode
[1] = mode_arg0
;
14952 h
.mode
[2] = mode_arg1
;
14953 h
.mode
[3] = mode_arg2
;
14959 /* If the builtin is a type that produces unsigned results or takes unsigned
14960 arguments, and it is returned as a decl for the vectorizer (such as
14961 widening multiplies, permute), make sure the arguments and return value
14962 are type correct. */
14965 /* unsigned 1 argument functions. */
14966 case CRYPTO_BUILTIN_VSBOX
:
14967 case P8V_BUILTIN_VGBBD
:
14968 case MISC_BUILTIN_CDTBCD
:
14969 case MISC_BUILTIN_CBCDTD
:
14974 /* unsigned 2 argument functions. */
14975 case ALTIVEC_BUILTIN_VMULEUB_UNS
:
14976 case ALTIVEC_BUILTIN_VMULEUH_UNS
:
14977 case ALTIVEC_BUILTIN_VMULOUB_UNS
:
14978 case ALTIVEC_BUILTIN_VMULOUH_UNS
:
14979 case CRYPTO_BUILTIN_VCIPHER
:
14980 case CRYPTO_BUILTIN_VCIPHERLAST
:
14981 case CRYPTO_BUILTIN_VNCIPHER
:
14982 case CRYPTO_BUILTIN_VNCIPHERLAST
:
14983 case CRYPTO_BUILTIN_VPMSUMB
:
14984 case CRYPTO_BUILTIN_VPMSUMH
:
14985 case CRYPTO_BUILTIN_VPMSUMW
:
14986 case CRYPTO_BUILTIN_VPMSUMD
:
14987 case CRYPTO_BUILTIN_VPMSUM
:
14988 case MISC_BUILTIN_ADDG6S
:
14989 case MISC_BUILTIN_DIVWEU
:
14990 case MISC_BUILTIN_DIVWEUO
:
14991 case MISC_BUILTIN_DIVDEU
:
14992 case MISC_BUILTIN_DIVDEUO
:
14998 /* unsigned 3 argument functions. */
14999 case ALTIVEC_BUILTIN_VPERM_16QI_UNS
:
15000 case ALTIVEC_BUILTIN_VPERM_8HI_UNS
:
15001 case ALTIVEC_BUILTIN_VPERM_4SI_UNS
:
15002 case ALTIVEC_BUILTIN_VPERM_2DI_UNS
:
15003 case ALTIVEC_BUILTIN_VSEL_16QI_UNS
:
15004 case ALTIVEC_BUILTIN_VSEL_8HI_UNS
:
15005 case ALTIVEC_BUILTIN_VSEL_4SI_UNS
:
15006 case ALTIVEC_BUILTIN_VSEL_2DI_UNS
:
15007 case VSX_BUILTIN_VPERM_16QI_UNS
:
15008 case VSX_BUILTIN_VPERM_8HI_UNS
:
15009 case VSX_BUILTIN_VPERM_4SI_UNS
:
15010 case VSX_BUILTIN_VPERM_2DI_UNS
:
15011 case VSX_BUILTIN_XXSEL_16QI_UNS
:
15012 case VSX_BUILTIN_XXSEL_8HI_UNS
:
15013 case VSX_BUILTIN_XXSEL_4SI_UNS
:
15014 case VSX_BUILTIN_XXSEL_2DI_UNS
:
15015 case CRYPTO_BUILTIN_VPERMXOR
:
15016 case CRYPTO_BUILTIN_VPERMXOR_V2DI
:
15017 case CRYPTO_BUILTIN_VPERMXOR_V4SI
:
15018 case CRYPTO_BUILTIN_VPERMXOR_V8HI
:
15019 case CRYPTO_BUILTIN_VPERMXOR_V16QI
:
15020 case CRYPTO_BUILTIN_VSHASIGMAW
:
15021 case CRYPTO_BUILTIN_VSHASIGMAD
:
15022 case CRYPTO_BUILTIN_VSHASIGMA
:
15029 /* signed permute functions with unsigned char mask. */
15030 case ALTIVEC_BUILTIN_VPERM_16QI
:
15031 case ALTIVEC_BUILTIN_VPERM_8HI
:
15032 case ALTIVEC_BUILTIN_VPERM_4SI
:
15033 case ALTIVEC_BUILTIN_VPERM_4SF
:
15034 case ALTIVEC_BUILTIN_VPERM_2DI
:
15035 case ALTIVEC_BUILTIN_VPERM_2DF
:
15036 case VSX_BUILTIN_VPERM_16QI
:
15037 case VSX_BUILTIN_VPERM_8HI
:
15038 case VSX_BUILTIN_VPERM_4SI
:
15039 case VSX_BUILTIN_VPERM_4SF
:
15040 case VSX_BUILTIN_VPERM_2DI
:
15041 case VSX_BUILTIN_VPERM_2DF
:
15045 /* unsigned args, signed return. */
15046 case VSX_BUILTIN_XVCVUXDDP_UNS
:
15047 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF
:
15051 /* signed args, unsigned return. */
15052 case VSX_BUILTIN_XVCVDPUXDS_UNS
:
15053 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI
:
15054 case MISC_BUILTIN_UNPACK_TD
:
15055 case MISC_BUILTIN_UNPACK_V1TI
:
15059 /* unsigned arguments for 128-bit pack instructions. */
15060 case MISC_BUILTIN_PACK_TD
:
15061 case MISC_BUILTIN_PACK_V1TI
:
15070 /* Figure out how many args are present. */
15071 while (num_args
> 0 && h
.mode
[num_args
] == VOIDmode
)
15075 fatal_error ("internal error: builtin function %s had no type", name
);
15077 ret_type
= builtin_mode_to_type
[h
.mode
[0]][h
.uns_p
[0]];
15078 if (!ret_type
&& h
.uns_p
[0])
15079 ret_type
= builtin_mode_to_type
[h
.mode
[0]][0];
15082 fatal_error ("internal error: builtin function %s had an unexpected "
15083 "return type %s", name
, GET_MODE_NAME (h
.mode
[0]));
15085 for (i
= 0; i
< (int) ARRAY_SIZE (arg_type
); i
++)
15086 arg_type
[i
] = NULL_TREE
;
15088 for (i
= 0; i
< num_args
; i
++)
15090 int m
= (int) h
.mode
[i
+1];
15091 int uns_p
= h
.uns_p
[i
+1];
15093 arg_type
[i
] = builtin_mode_to_type
[m
][uns_p
];
15094 if (!arg_type
[i
] && uns_p
)
15095 arg_type
[i
] = builtin_mode_to_type
[m
][0];
15098 fatal_error ("internal error: builtin function %s, argument %d "
15099 "had unexpected argument type %s", name
, i
,
15100 GET_MODE_NAME (m
));
15103 found
= htab_find_slot (builtin_hash_table
, &h
, INSERT
);
15104 if (*found
== NULL
)
15106 h2
= ggc_alloc
<builtin_hash_struct
> ();
15108 *found
= (void *)h2
;
15110 h2
->type
= build_function_type_list (ret_type
, arg_type
[0], arg_type
[1],
15111 arg_type
[2], NULL_TREE
);
15114 return ((struct builtin_hash_struct
*)(*found
))->type
;
15118 rs6000_common_init_builtins (void)
15120 const struct builtin_description
*d
;
15123 tree opaque_ftype_opaque
= NULL_TREE
;
15124 tree opaque_ftype_opaque_opaque
= NULL_TREE
;
15125 tree opaque_ftype_opaque_opaque_opaque
= NULL_TREE
;
15126 tree v2si_ftype_qi
= NULL_TREE
;
15127 tree v2si_ftype_v2si_qi
= NULL_TREE
;
15128 tree v2si_ftype_int_qi
= NULL_TREE
;
15129 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
15131 if (!TARGET_PAIRED_FLOAT
)
15133 builtin_mode_to_type
[V2SImode
][0] = opaque_V2SI_type_node
;
15134 builtin_mode_to_type
[V2SFmode
][0] = opaque_V2SF_type_node
;
15137 /* Paired and SPE builtins are only available if you build a compiler with
15138 the appropriate options, so only create those builtins with the
15139 appropriate compiler option. Create Altivec and VSX builtins on machines
15140 with at least the general purpose extensions (970 and newer) to allow the
15141 use of the target attribute.. */
15143 if (TARGET_EXTRA_BUILTINS
)
15144 builtin_mask
|= RS6000_BTM_COMMON
;
15146 /* Add the ternary operators. */
15148 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
15151 HOST_WIDE_INT mask
= d
->mask
;
15153 if ((mask
& builtin_mask
) != mask
)
15155 if (TARGET_DEBUG_BUILTIN
)
15156 fprintf (stderr
, "rs6000_builtin, skip ternary %s\n", d
->name
);
15160 if (rs6000_overloaded_builtin_p (d
->code
))
15162 if (! (type
= opaque_ftype_opaque_opaque_opaque
))
15163 type
= opaque_ftype_opaque_opaque_opaque
15164 = build_function_type_list (opaque_V4SI_type_node
,
15165 opaque_V4SI_type_node
,
15166 opaque_V4SI_type_node
,
15167 opaque_V4SI_type_node
,
15172 enum insn_code icode
= d
->icode
;
15175 if (TARGET_DEBUG_BUILTIN
)
15176 fprintf (stderr
, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
15182 if (icode
== CODE_FOR_nothing
)
15184 if (TARGET_DEBUG_BUILTIN
)
15185 fprintf (stderr
, "rs6000_builtin, skip ternary %s (no code)\n",
15191 type
= builtin_function_type (insn_data
[icode
].operand
[0].mode
,
15192 insn_data
[icode
].operand
[1].mode
,
15193 insn_data
[icode
].operand
[2].mode
,
15194 insn_data
[icode
].operand
[3].mode
,
15198 def_builtin (d
->name
, type
, d
->code
);
15201 /* Add the binary operators. */
15203 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
15205 enum machine_mode mode0
, mode1
, mode2
;
15207 HOST_WIDE_INT mask
= d
->mask
;
15209 if ((mask
& builtin_mask
) != mask
)
15211 if (TARGET_DEBUG_BUILTIN
)
15212 fprintf (stderr
, "rs6000_builtin, skip binary %s\n", d
->name
);
15216 if (rs6000_overloaded_builtin_p (d
->code
))
15218 if (! (type
= opaque_ftype_opaque_opaque
))
15219 type
= opaque_ftype_opaque_opaque
15220 = build_function_type_list (opaque_V4SI_type_node
,
15221 opaque_V4SI_type_node
,
15222 opaque_V4SI_type_node
,
15227 enum insn_code icode
= d
->icode
;
15230 if (TARGET_DEBUG_BUILTIN
)
15231 fprintf (stderr
, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
15237 if (icode
== CODE_FOR_nothing
)
15239 if (TARGET_DEBUG_BUILTIN
)
15240 fprintf (stderr
, "rs6000_builtin, skip binary %s (no code)\n",
15246 mode0
= insn_data
[icode
].operand
[0].mode
;
15247 mode1
= insn_data
[icode
].operand
[1].mode
;
15248 mode2
= insn_data
[icode
].operand
[2].mode
;
15250 if (mode0
== V2SImode
&& mode1
== V2SImode
&& mode2
== QImode
)
15252 if (! (type
= v2si_ftype_v2si_qi
))
15253 type
= v2si_ftype_v2si_qi
15254 = build_function_type_list (opaque_V2SI_type_node
,
15255 opaque_V2SI_type_node
,
15260 else if (mode0
== V2SImode
&& GET_MODE_CLASS (mode1
) == MODE_INT
15261 && mode2
== QImode
)
15263 if (! (type
= v2si_ftype_int_qi
))
15264 type
= v2si_ftype_int_qi
15265 = build_function_type_list (opaque_V2SI_type_node
,
15272 type
= builtin_function_type (mode0
, mode1
, mode2
, VOIDmode
,
15276 def_builtin (d
->name
, type
, d
->code
);
15279 /* Add the simple unary operators. */
15281 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
15283 enum machine_mode mode0
, mode1
;
15285 HOST_WIDE_INT mask
= d
->mask
;
15287 if ((mask
& builtin_mask
) != mask
)
15289 if (TARGET_DEBUG_BUILTIN
)
15290 fprintf (stderr
, "rs6000_builtin, skip unary %s\n", d
->name
);
15294 if (rs6000_overloaded_builtin_p (d
->code
))
15296 if (! (type
= opaque_ftype_opaque
))
15297 type
= opaque_ftype_opaque
15298 = build_function_type_list (opaque_V4SI_type_node
,
15299 opaque_V4SI_type_node
,
15304 enum insn_code icode
= d
->icode
;
15307 if (TARGET_DEBUG_BUILTIN
)
15308 fprintf (stderr
, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
15314 if (icode
== CODE_FOR_nothing
)
15316 if (TARGET_DEBUG_BUILTIN
)
15317 fprintf (stderr
, "rs6000_builtin, skip unary %s (no code)\n",
15323 mode0
= insn_data
[icode
].operand
[0].mode
;
15324 mode1
= insn_data
[icode
].operand
[1].mode
;
15326 if (mode0
== V2SImode
&& mode1
== QImode
)
15328 if (! (type
= v2si_ftype_qi
))
15329 type
= v2si_ftype_qi
15330 = build_function_type_list (opaque_V2SI_type_node
,
15336 type
= builtin_function_type (mode0
, mode1
, VOIDmode
, VOIDmode
,
15340 def_builtin (d
->name
, type
, d
->code
);
15345 rs6000_init_libfuncs (void)
15347 if (!TARGET_IEEEQUAD
)
15348 /* AIX/Darwin/64-bit Linux quad floating point routines. */
15349 if (!TARGET_XL_COMPAT
)
15351 set_optab_libfunc (add_optab
, TFmode
, "__gcc_qadd");
15352 set_optab_libfunc (sub_optab
, TFmode
, "__gcc_qsub");
15353 set_optab_libfunc (smul_optab
, TFmode
, "__gcc_qmul");
15354 set_optab_libfunc (sdiv_optab
, TFmode
, "__gcc_qdiv");
15356 if (!(TARGET_HARD_FLOAT
&& (TARGET_FPRS
|| TARGET_E500_DOUBLE
)))
15358 set_optab_libfunc (neg_optab
, TFmode
, "__gcc_qneg");
15359 set_optab_libfunc (eq_optab
, TFmode
, "__gcc_qeq");
15360 set_optab_libfunc (ne_optab
, TFmode
, "__gcc_qne");
15361 set_optab_libfunc (gt_optab
, TFmode
, "__gcc_qgt");
15362 set_optab_libfunc (ge_optab
, TFmode
, "__gcc_qge");
15363 set_optab_libfunc (lt_optab
, TFmode
, "__gcc_qlt");
15364 set_optab_libfunc (le_optab
, TFmode
, "__gcc_qle");
15366 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "__gcc_stoq");
15367 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "__gcc_dtoq");
15368 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "__gcc_qtos");
15369 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "__gcc_qtod");
15370 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "__gcc_qtoi");
15371 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "__gcc_qtou");
15372 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "__gcc_itoq");
15373 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "__gcc_utoq");
15376 if (!(TARGET_HARD_FLOAT
&& TARGET_FPRS
))
15377 set_optab_libfunc (unord_optab
, TFmode
, "__gcc_qunord");
15381 set_optab_libfunc (add_optab
, TFmode
, "_xlqadd");
15382 set_optab_libfunc (sub_optab
, TFmode
, "_xlqsub");
15383 set_optab_libfunc (smul_optab
, TFmode
, "_xlqmul");
15384 set_optab_libfunc (sdiv_optab
, TFmode
, "_xlqdiv");
15388 /* 32-bit SVR4 quad floating point routines. */
15390 set_optab_libfunc (add_optab
, TFmode
, "_q_add");
15391 set_optab_libfunc (sub_optab
, TFmode
, "_q_sub");
15392 set_optab_libfunc (neg_optab
, TFmode
, "_q_neg");
15393 set_optab_libfunc (smul_optab
, TFmode
, "_q_mul");
15394 set_optab_libfunc (sdiv_optab
, TFmode
, "_q_div");
15395 if (TARGET_PPC_GPOPT
)
15396 set_optab_libfunc (sqrt_optab
, TFmode
, "_q_sqrt");
15398 set_optab_libfunc (eq_optab
, TFmode
, "_q_feq");
15399 set_optab_libfunc (ne_optab
, TFmode
, "_q_fne");
15400 set_optab_libfunc (gt_optab
, TFmode
, "_q_fgt");
15401 set_optab_libfunc (ge_optab
, TFmode
, "_q_fge");
15402 set_optab_libfunc (lt_optab
, TFmode
, "_q_flt");
15403 set_optab_libfunc (le_optab
, TFmode
, "_q_fle");
15405 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_q_stoq");
15406 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_q_dtoq");
15407 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_q_qtos");
15408 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_q_qtod");
15409 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_q_qtoi");
15410 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_q_qtou");
15411 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_q_itoq");
15412 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_q_utoq");
15417 /* Expand a block clear operation, and return 1 if successful. Return 0
15418 if we should let the compiler generate normal code.
15420 operands[0] is the destination
15421 operands[1] is the length
15422 operands[3] is the alignment */
15425 expand_block_clear (rtx operands
[])
15427 rtx orig_dest
= operands
[0];
15428 rtx bytes_rtx
= operands
[1];
15429 rtx align_rtx
= operands
[3];
15430 bool constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
15431 HOST_WIDE_INT align
;
15432 HOST_WIDE_INT bytes
;
15437 /* If this is not a fixed size move, just call memcpy */
15441 /* This must be a fixed size alignment */
15442 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
15443 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
15445 /* Anything to clear? */
15446 bytes
= INTVAL (bytes_rtx
);
15450 /* Use the builtin memset after a point, to avoid huge code bloat.
15451 When optimize_size, avoid any significant code bloat; calling
15452 memset is about 4 instructions, so allow for one instruction to
15453 load zero and three to do clearing. */
15454 if (TARGET_ALTIVEC
&& align
>= 128)
15456 else if (TARGET_POWERPC64
&& (align
>= 64 || !STRICT_ALIGNMENT
))
15458 else if (TARGET_SPE
&& align
>= 64)
15463 if (optimize_size
&& bytes
> 3 * clear_step
)
15465 if (! optimize_size
&& bytes
> 8 * clear_step
)
15468 for (offset
= 0; bytes
> 0; offset
+= clear_bytes
, bytes
-= clear_bytes
)
15470 enum machine_mode mode
= BLKmode
;
15473 if (bytes
>= 16 && TARGET_ALTIVEC
&& align
>= 128)
15478 else if (bytes
>= 8 && TARGET_SPE
&& align
>= 64)
15483 else if (bytes
>= 8 && TARGET_POWERPC64
15484 && (align
>= 64 || !STRICT_ALIGNMENT
))
15488 if (offset
== 0 && align
< 64)
15492 /* If the address form is reg+offset with offset not a
15493 multiple of four, reload into reg indirect form here
15494 rather than waiting for reload. This way we get one
15495 reload, not one per store. */
15496 addr
= XEXP (orig_dest
, 0);
15497 if ((GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
)
15498 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
15499 && (INTVAL (XEXP (addr
, 1)) & 3) != 0)
15501 addr
= copy_addr_to_reg (addr
);
15502 orig_dest
= replace_equiv_address (orig_dest
, addr
);
15506 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
15507 { /* move 4 bytes */
15511 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
15512 { /* move 2 bytes */
15516 else /* move 1 byte at a time */
15522 dest
= adjust_address (orig_dest
, mode
, offset
);
15524 emit_move_insn (dest
, CONST0_RTX (mode
));
15531 /* Expand a block move operation, and return 1 if successful. Return 0
15532 if we should let the compiler generate normal code.
15534 operands[0] is the destination
15535 operands[1] is the source
15536 operands[2] is the length
15537 operands[3] is the alignment */
15539 #define MAX_MOVE_REG 4
15542 expand_block_move (rtx operands
[])
15544 rtx orig_dest
= operands
[0];
15545 rtx orig_src
= operands
[1];
15546 rtx bytes_rtx
= operands
[2];
15547 rtx align_rtx
= operands
[3];
15548 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
15553 rtx stores
[MAX_MOVE_REG
];
15556 /* If this is not a fixed size move, just call memcpy */
15560 /* This must be a fixed size alignment */
15561 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
15562 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
15564 /* Anything to move? */
15565 bytes
= INTVAL (bytes_rtx
);
15569 if (bytes
> rs6000_block_move_inline_limit
)
15572 for (offset
= 0; bytes
> 0; offset
+= move_bytes
, bytes
-= move_bytes
)
15575 rtx (*movmemsi
) (rtx
, rtx
, rtx
, rtx
);
15576 rtx (*mov
) (rtx
, rtx
);
15578 enum machine_mode mode
= BLKmode
;
15581 /* Altivec first, since it will be faster than a string move
15582 when it applies, and usually not significantly larger. */
15583 if (TARGET_ALTIVEC
&& bytes
>= 16 && align
>= 128)
15587 gen_func
.mov
= gen_movv4si
;
15589 else if (TARGET_SPE
&& bytes
>= 8 && align
>= 64)
15593 gen_func
.mov
= gen_movv2si
;
15595 else if (TARGET_STRING
15596 && bytes
> 24 /* move up to 32 bytes at a time */
15602 && ! fixed_regs
[10]
15603 && ! fixed_regs
[11]
15604 && ! fixed_regs
[12])
15606 move_bytes
= (bytes
> 32) ? 32 : bytes
;
15607 gen_func
.movmemsi
= gen_movmemsi_8reg
;
15609 else if (TARGET_STRING
15610 && bytes
> 16 /* move up to 24 bytes at a time */
15616 && ! fixed_regs
[10])
15618 move_bytes
= (bytes
> 24) ? 24 : bytes
;
15619 gen_func
.movmemsi
= gen_movmemsi_6reg
;
15621 else if (TARGET_STRING
15622 && bytes
> 8 /* move up to 16 bytes at a time */
15626 && ! fixed_regs
[8])
15628 move_bytes
= (bytes
> 16) ? 16 : bytes
;
15629 gen_func
.movmemsi
= gen_movmemsi_4reg
;
15631 else if (bytes
>= 8 && TARGET_POWERPC64
15632 && (align
>= 64 || !STRICT_ALIGNMENT
))
15636 gen_func
.mov
= gen_movdi
;
15637 if (offset
== 0 && align
< 64)
15641 /* If the address form is reg+offset with offset not a
15642 multiple of four, reload into reg indirect form here
15643 rather than waiting for reload. This way we get one
15644 reload, not one per load and/or store. */
15645 addr
= XEXP (orig_dest
, 0);
15646 if ((GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
)
15647 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
15648 && (INTVAL (XEXP (addr
, 1)) & 3) != 0)
15650 addr
= copy_addr_to_reg (addr
);
15651 orig_dest
= replace_equiv_address (orig_dest
, addr
);
15653 addr
= XEXP (orig_src
, 0);
15654 if ((GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
)
15655 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
15656 && (INTVAL (XEXP (addr
, 1)) & 3) != 0)
15658 addr
= copy_addr_to_reg (addr
);
15659 orig_src
= replace_equiv_address (orig_src
, addr
);
15663 else if (TARGET_STRING
&& bytes
> 4 && !TARGET_POWERPC64
)
15664 { /* move up to 8 bytes at a time */
15665 move_bytes
= (bytes
> 8) ? 8 : bytes
;
15666 gen_func
.movmemsi
= gen_movmemsi_2reg
;
15668 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
15669 { /* move 4 bytes */
15672 gen_func
.mov
= gen_movsi
;
15674 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
15675 { /* move 2 bytes */
15678 gen_func
.mov
= gen_movhi
;
15680 else if (TARGET_STRING
&& bytes
> 1)
15681 { /* move up to 4 bytes at a time */
15682 move_bytes
= (bytes
> 4) ? 4 : bytes
;
15683 gen_func
.movmemsi
= gen_movmemsi_1reg
;
15685 else /* move 1 byte at a time */
15689 gen_func
.mov
= gen_movqi
;
15692 src
= adjust_address (orig_src
, mode
, offset
);
15693 dest
= adjust_address (orig_dest
, mode
, offset
);
15695 if (mode
!= BLKmode
)
15697 rtx tmp_reg
= gen_reg_rtx (mode
);
15699 emit_insn ((*gen_func
.mov
) (tmp_reg
, src
));
15700 stores
[num_reg
++] = (*gen_func
.mov
) (dest
, tmp_reg
);
15703 if (mode
== BLKmode
|| num_reg
>= MAX_MOVE_REG
|| bytes
== move_bytes
)
15706 for (i
= 0; i
< num_reg
; i
++)
15707 emit_insn (stores
[i
]);
15711 if (mode
== BLKmode
)
15713 /* Move the address into scratch registers. The movmemsi
15714 patterns require zero offset. */
15715 if (!REG_P (XEXP (src
, 0)))
15717 rtx src_reg
= copy_addr_to_reg (XEXP (src
, 0));
15718 src
= replace_equiv_address (src
, src_reg
);
15720 set_mem_size (src
, move_bytes
);
15722 if (!REG_P (XEXP (dest
, 0)))
15724 rtx dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
15725 dest
= replace_equiv_address (dest
, dest_reg
);
15727 set_mem_size (dest
, move_bytes
);
15729 emit_insn ((*gen_func
.movmemsi
) (dest
, src
,
15730 GEN_INT (move_bytes
& 31),
15739 /* Return a string to perform a load_multiple operation.
15740 operands[0] is the vector.
15741 operands[1] is the source address.
15742 operands[2] is the first destination register. */
15745 rs6000_output_load_multiple (rtx operands
[3])
15747 /* We have to handle the case where the pseudo used to contain the address
15748 is assigned to one of the output registers. */
15750 int words
= XVECLEN (operands
[0], 0);
15753 if (XVECLEN (operands
[0], 0) == 1)
15754 return "lwz %2,0(%1)";
15756 for (i
= 0; i
< words
; i
++)
15757 if (refers_to_regno_p (REGNO (operands
[2]) + i
,
15758 REGNO (operands
[2]) + i
+ 1, operands
[1], 0))
15762 xop
[0] = GEN_INT (4 * (words
-1));
15763 xop
[1] = operands
[1];
15764 xop
[2] = operands
[2];
15765 output_asm_insn ("lswi %2,%1,%0\n\tlwz %1,%0(%1)", xop
);
15770 xop
[0] = GEN_INT (4 * (words
-1));
15771 xop
[1] = operands
[1];
15772 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
15773 output_asm_insn ("addi %1,%1,4\n\tlswi %2,%1,%0\n\tlwz %1,-4(%1)", xop
);
15778 for (j
= 0; j
< words
; j
++)
15781 xop
[0] = GEN_INT (j
* 4);
15782 xop
[1] = operands
[1];
15783 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + j
);
15784 output_asm_insn ("lwz %2,%0(%1)", xop
);
15786 xop
[0] = GEN_INT (i
* 4);
15787 xop
[1] = operands
[1];
15788 output_asm_insn ("lwz %1,%0(%1)", xop
);
15793 return "lswi %2,%1,%N0";
15797 /* A validation routine: say whether CODE, a condition code, and MODE
15798 match. The other alternatives either don't make sense or should
15799 never be generated. */
15802 validate_condition_mode (enum rtx_code code
, enum machine_mode mode
)
15804 gcc_assert ((GET_RTX_CLASS (code
) == RTX_COMPARE
15805 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
15806 && GET_MODE_CLASS (mode
) == MODE_CC
);
15808 /* These don't make sense. */
15809 gcc_assert ((code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
)
15810 || mode
!= CCUNSmode
);
15812 gcc_assert ((code
!= GTU
&& code
!= LTU
&& code
!= GEU
&& code
!= LEU
)
15813 || mode
== CCUNSmode
);
15815 gcc_assert (mode
== CCFPmode
15816 || (code
!= ORDERED
&& code
!= UNORDERED
15817 && code
!= UNEQ
&& code
!= LTGT
15818 && code
!= UNGT
&& code
!= UNLT
15819 && code
!= UNGE
&& code
!= UNLE
));
15821 /* These should never be generated except for
15822 flag_finite_math_only. */
15823 gcc_assert (mode
!= CCFPmode
15824 || flag_finite_math_only
15825 || (code
!= LE
&& code
!= GE
15826 && code
!= UNEQ
&& code
!= LTGT
15827 && code
!= UNGT
&& code
!= UNLT
));
15829 /* These are invalid; the information is not there. */
15830 gcc_assert (mode
!= CCEQmode
|| code
== EQ
|| code
== NE
);
15834 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
15835 mask required to convert the result of a rotate insn into a shift
15836 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
15839 includes_lshift_p (rtx shiftop
, rtx andop
)
15841 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
15843 shift_mask
<<= INTVAL (shiftop
);
15845 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
15848 /* Similar, but for right shift. */
15851 includes_rshift_p (rtx shiftop
, rtx andop
)
15853 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
15855 shift_mask
>>= INTVAL (shiftop
);
15857 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
15860 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
15861 to perform a left shift. It must have exactly SHIFTOP least
15862 significant 0's, then one or more 1's, then zero or more 0's. */
15865 includes_rldic_lshift_p (rtx shiftop
, rtx andop
)
15867 if (GET_CODE (andop
) == CONST_INT
)
15869 HOST_WIDE_INT c
, lsb
, shift_mask
;
15871 c
= INTVAL (andop
);
15872 if (c
== 0 || c
== ~0)
15876 shift_mask
<<= INTVAL (shiftop
);
15878 /* Find the least significant one bit. */
15881 /* It must coincide with the LSB of the shift mask. */
15882 if (-lsb
!= shift_mask
)
15885 /* Invert to look for the next transition (if any). */
15888 /* Remove the low group of ones (originally low group of zeros). */
15891 /* Again find the lsb, and check we have all 1's above. */
15899 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
15900 to perform a left shift. It must have SHIFTOP or more least
15901 significant 0's, with the remainder of the word 1's. */
15904 includes_rldicr_lshift_p (rtx shiftop
, rtx andop
)
15906 if (GET_CODE (andop
) == CONST_INT
)
15908 HOST_WIDE_INT c
, lsb
, shift_mask
;
15911 shift_mask
<<= INTVAL (shiftop
);
15912 c
= INTVAL (andop
);
15914 /* Find the least significant one bit. */
15917 /* It must be covered by the shift mask.
15918 This test also rejects c == 0. */
15919 if ((lsb
& shift_mask
) == 0)
15922 /* Check we have all 1's above the transition, and reject all 1's. */
15923 return c
== -lsb
&& lsb
!= 1;
15929 /* Return 1 if operands will generate a valid arguments to rlwimi
15930 instruction for insert with right shift in 64-bit mode. The mask may
15931 not start on the first bit or stop on the last bit because wrap-around
15932 effects of instruction do not correspond to semantics of RTL insn. */
15935 insvdi_rshift_rlwimi_p (rtx sizeop
, rtx startop
, rtx shiftop
)
15937 if (INTVAL (startop
) > 32
15938 && INTVAL (startop
) < 64
15939 && INTVAL (sizeop
) > 1
15940 && INTVAL (sizeop
) + INTVAL (startop
) < 64
15941 && INTVAL (shiftop
) > 0
15942 && INTVAL (sizeop
) + INTVAL (shiftop
) < 32
15943 && (64 - (INTVAL (shiftop
) & 63)) >= INTVAL (sizeop
))
15949 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
15950 for lfq and stfq insns iff the registers are hard registers. */
15953 registers_ok_for_quad_peep (rtx reg1
, rtx reg2
)
15955 /* We might have been passed a SUBREG. */
15956 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
15959 /* We might have been passed non floating point registers. */
15960 if (!FP_REGNO_P (REGNO (reg1
))
15961 || !FP_REGNO_P (REGNO (reg2
)))
15964 return (REGNO (reg1
) == REGNO (reg2
) - 1);
15967 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
15968 addr1 and addr2 must be in consecutive memory locations
15969 (addr2 == addr1 + 8). */
15972 mems_ok_for_quad_peep (rtx mem1
, rtx mem2
)
15975 unsigned int reg1
, reg2
;
15976 int offset1
, offset2
;
15978 /* The mems cannot be volatile. */
15979 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
15982 addr1
= XEXP (mem1
, 0);
15983 addr2
= XEXP (mem2
, 0);
15985 /* Extract an offset (if used) from the first addr. */
15986 if (GET_CODE (addr1
) == PLUS
)
15988 /* If not a REG, return zero. */
15989 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
15993 reg1
= REGNO (XEXP (addr1
, 0));
15994 /* The offset must be constant! */
15995 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
15997 offset1
= INTVAL (XEXP (addr1
, 1));
16000 else if (GET_CODE (addr1
) != REG
)
16004 reg1
= REGNO (addr1
);
16005 /* This was a simple (mem (reg)) expression. Offset is 0. */
16009 /* And now for the second addr. */
16010 if (GET_CODE (addr2
) == PLUS
)
16012 /* If not a REG, return zero. */
16013 if (GET_CODE (XEXP (addr2
, 0)) != REG
)
16017 reg2
= REGNO (XEXP (addr2
, 0));
16018 /* The offset must be constant. */
16019 if (GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
16021 offset2
= INTVAL (XEXP (addr2
, 1));
16024 else if (GET_CODE (addr2
) != REG
)
16028 reg2
= REGNO (addr2
);
16029 /* This was a simple (mem (reg)) expression. Offset is 0. */
16033 /* Both of these must have the same base register. */
16037 /* The offset for the second addr must be 8 more than the first addr. */
16038 if (offset2
!= offset1
+ 8)
16041 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
16048 rs6000_secondary_memory_needed_rtx (enum machine_mode mode
)
16050 static bool eliminated
= false;
16053 if (mode
!= SDmode
|| TARGET_NO_SDMODE_STACK
)
16054 ret
= assign_stack_local (mode
, GET_MODE_SIZE (mode
), 0);
16057 rtx mem
= cfun
->machine
->sdmode_stack_slot
;
16058 gcc_assert (mem
!= NULL_RTX
);
16062 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
16063 cfun
->machine
->sdmode_stack_slot
= mem
;
16069 if (TARGET_DEBUG_ADDR
)
16071 fprintf (stderr
, "\nrs6000_secondary_memory_needed_rtx, mode %s, rtx:\n",
16072 GET_MODE_NAME (mode
));
16074 fprintf (stderr
, "\tNULL_RTX\n");
16082 /* Return the mode to be used for memory when a secondary memory
16083 location is needed. For SDmode values we need to use DDmode, in
16084 all other cases we can use the same mode. */
16086 rs6000_secondary_memory_needed_mode (enum machine_mode mode
)
16088 if (lra_in_progress
&& mode
== SDmode
)
16094 rs6000_check_sdmode (tree
*tp
, int *walk_subtrees
, void *data ATTRIBUTE_UNUSED
)
16096 /* Don't walk into types. */
16097 if (*tp
== NULL_TREE
|| *tp
== error_mark_node
|| TYPE_P (*tp
))
16099 *walk_subtrees
= 0;
16103 switch (TREE_CODE (*tp
))
16112 case VIEW_CONVERT_EXPR
:
16113 if (TYPE_MODE (TREE_TYPE (*tp
)) == SDmode
)
16123 /* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
16124 on traditional floating point registers, and the VMRGOW/VMRGEW instructions
16125 only work on the traditional altivec registers, note if an altivec register
16128 static enum rs6000_reg_type
16129 register_to_reg_type (rtx reg
, bool *is_altivec
)
16131 HOST_WIDE_INT regno
;
16132 enum reg_class rclass
;
16134 if (GET_CODE (reg
) == SUBREG
)
16135 reg
= SUBREG_REG (reg
);
16138 return NO_REG_TYPE
;
16140 regno
= REGNO (reg
);
16141 if (regno
>= FIRST_PSEUDO_REGISTER
)
16143 if (!lra_in_progress
&& !reload_in_progress
&& !reload_completed
)
16144 return PSEUDO_REG_TYPE
;
16146 regno
= true_regnum (reg
);
16147 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
16148 return PSEUDO_REG_TYPE
;
16151 gcc_assert (regno
>= 0);
16153 if (is_altivec
&& ALTIVEC_REGNO_P (regno
))
16154 *is_altivec
= true;
16156 rclass
= rs6000_regno_regclass
[regno
];
16157 return reg_class_to_reg_type
[(int)rclass
];
16160 /* Helper function for rs6000_secondary_reload to return true if a move to a
16161 different register classe is really a simple move. */
16164 rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type
,
16165 enum rs6000_reg_type from_type
,
16166 enum machine_mode mode
)
16170 /* Add support for various direct moves available. In this function, we only
16171 look at cases where we don't need any extra registers, and one or more
16172 simple move insns are issued. At present, 32-bit integers are not allowed
16173 in FPR/VSX registers. Single precision binary floating is not a simple
16174 move because we need to convert to the single precision memory layout.
16175 The 4-byte SDmode can be moved. */
16176 size
= GET_MODE_SIZE (mode
);
16177 if (TARGET_DIRECT_MOVE
16178 && ((mode
== SDmode
) || (TARGET_POWERPC64
&& size
== 8))
16179 && ((to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
16180 || (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
16183 else if (TARGET_MFPGPR
&& TARGET_POWERPC64
&& size
== 8
16184 && ((to_type
== GPR_REG_TYPE
&& from_type
== FPR_REG_TYPE
)
16185 || (to_type
== FPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
16188 else if ((size
== 4 || (TARGET_POWERPC64
&& size
== 8))
16189 && ((to_type
== GPR_REG_TYPE
&& from_type
== SPR_REG_TYPE
)
16190 || (to_type
== SPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
16196 /* Power8 helper function for rs6000_secondary_reload, handle all of the
16197 special direct moves that involve allocating an extra register, return the
16198 insn code of the helper function if there is such a function or
16199 CODE_FOR_nothing if not. */
16202 rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type
,
16203 enum rs6000_reg_type from_type
,
16204 enum machine_mode mode
,
16205 secondary_reload_info
*sri
,
16209 enum insn_code icode
= CODE_FOR_nothing
;
16211 int size
= GET_MODE_SIZE (mode
);
16213 if (TARGET_POWERPC64
)
16217 /* Handle moving 128-bit values from GPRs to VSX point registers on
16218 power8 when running in 64-bit mode using XXPERMDI to glue the two
16219 64-bit values back together. */
16220 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
16222 cost
= 3; /* 2 mtvsrd's, 1 xxpermdi. */
16223 icode
= reg_addr
[mode
].reload_vsx_gpr
;
16226 /* Handle moving 128-bit values from VSX point registers to GPRs on
16227 power8 when running in 64-bit mode using XXPERMDI to get access to the
16228 bottom 64-bit value. */
16229 else if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
16231 cost
= 3; /* 2 mfvsrd's, 1 xxpermdi. */
16232 icode
= reg_addr
[mode
].reload_gpr_vsx
;
16236 else if (mode
== SFmode
)
16238 if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
16240 cost
= 3; /* xscvdpspn, mfvsrd, and. */
16241 icode
= reg_addr
[mode
].reload_gpr_vsx
;
16244 else if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
16246 cost
= 2; /* mtvsrz, xscvspdpn. */
16247 icode
= reg_addr
[mode
].reload_vsx_gpr
;
16252 if (TARGET_POWERPC64
&& size
== 16)
16254 /* Handle moving 128-bit values from GPRs to VSX point registers on
16255 power8 when running in 64-bit mode using XXPERMDI to glue the two
16256 64-bit values back together. */
16257 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
16259 cost
= 3; /* 2 mtvsrd's, 1 xxpermdi. */
16260 icode
= reg_addr
[mode
].reload_vsx_gpr
;
16263 /* Handle moving 128-bit values from VSX point registers to GPRs on
16264 power8 when running in 64-bit mode using XXPERMDI to get access to the
16265 bottom 64-bit value. */
16266 else if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
16268 cost
= 3; /* 2 mfvsrd's, 1 xxpermdi. */
16269 icode
= reg_addr
[mode
].reload_gpr_vsx
;
16273 else if (!TARGET_POWERPC64
&& size
== 8)
16275 /* Handle moving 64-bit values from GPRs to floating point registers on
16276 power8 when running in 32-bit mode using FMRGOW to glue the two 32-bit
16277 values back together. Altivec register classes must be handled
16278 specially since a different instruction is used, and the secondary
16279 reload support requires a single instruction class in the scratch
16280 register constraint. However, right now TFmode is not allowed in
16281 Altivec registers, so the pattern will never match. */
16282 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
&& !altivec_p
)
16284 cost
= 3; /* 2 mtvsrwz's, 1 fmrgow. */
16285 icode
= reg_addr
[mode
].reload_fpr_gpr
;
16289 if (icode
!= CODE_FOR_nothing
)
16294 sri
->icode
= icode
;
16295 sri
->extra_cost
= cost
;
16302 /* Return whether a move between two register classes can be done either
16303 directly (simple move) or via a pattern that uses a single extra temporary
16304 (using power8's direct move in this case. */
16307 rs6000_secondary_reload_move (enum rs6000_reg_type to_type
,
16308 enum rs6000_reg_type from_type
,
16309 enum machine_mode mode
,
16310 secondary_reload_info
*sri
,
16313 /* Fall back to load/store reloads if either type is not a register. */
16314 if (to_type
== NO_REG_TYPE
|| from_type
== NO_REG_TYPE
)
16317 /* If we haven't allocated registers yet, assume the move can be done for the
16318 standard register types. */
16319 if ((to_type
== PSEUDO_REG_TYPE
&& from_type
== PSEUDO_REG_TYPE
)
16320 || (to_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (from_type
))
16321 || (from_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (to_type
)))
16324 /* Moves to the same set of registers is a simple move for non-specialized
16326 if (to_type
== from_type
&& IS_STD_REG_TYPE (to_type
))
16329 /* Check whether a simple move can be done directly. */
16330 if (rs6000_secondary_reload_simple_move (to_type
, from_type
, mode
))
16334 sri
->icode
= CODE_FOR_nothing
;
16335 sri
->extra_cost
= 0;
16340 /* Now check if we can do it in a few steps. */
16341 return rs6000_secondary_reload_direct_move (to_type
, from_type
, mode
, sri
,
16345 /* Inform reload about cases where moving X with a mode MODE to a register in
16346 RCLASS requires an extra scratch or immediate register. Return the class
16347 needed for the immediate register.
16349 For VSX and Altivec, we may need a register to convert sp+offset into
16352 For misaligned 64-bit gpr loads and stores we need a register to
16353 convert an offset address to indirect. */
16356 rs6000_secondary_reload (bool in_p
,
16358 reg_class_t rclass_i
,
16359 enum machine_mode mode
,
16360 secondary_reload_info
*sri
)
16362 enum reg_class rclass
= (enum reg_class
) rclass_i
;
16363 reg_class_t ret
= ALL_REGS
;
16364 enum insn_code icode
;
16365 bool default_p
= false;
16367 sri
->icode
= CODE_FOR_nothing
;
16369 ? reg_addr
[mode
].reload_load
16370 : reg_addr
[mode
].reload_store
);
16372 if (REG_P (x
) || register_operand (x
, mode
))
16374 enum rs6000_reg_type to_type
= reg_class_to_reg_type
[(int)rclass
];
16375 bool altivec_p
= (rclass
== ALTIVEC_REGS
);
16376 enum rs6000_reg_type from_type
= register_to_reg_type (x
, &altivec_p
);
16380 enum rs6000_reg_type exchange
= to_type
;
16381 to_type
= from_type
;
16382 from_type
= exchange
;
16385 /* Can we do a direct move of some sort? */
16386 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
, sri
,
16389 icode
= (enum insn_code
)sri
->icode
;
16395 /* Handle vector moves with reload helper functions. */
16396 if (ret
== ALL_REGS
&& icode
!= CODE_FOR_nothing
)
16399 sri
->icode
= CODE_FOR_nothing
;
16400 sri
->extra_cost
= 0;
16402 if (GET_CODE (x
) == MEM
)
16404 rtx addr
= XEXP (x
, 0);
16406 /* Loads to and stores from gprs can do reg+offset, and wouldn't need
16407 an extra register in that case, but it would need an extra
16408 register if the addressing is reg+reg or (reg+reg)&(-16). Special
16409 case load/store quad. */
16410 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
)
16412 if (TARGET_POWERPC64
&& TARGET_QUAD_MEMORY
16413 && GET_MODE_SIZE (mode
) == 16
16414 && quad_memory_operand (x
, mode
))
16416 sri
->icode
= icode
;
16417 sri
->extra_cost
= 2;
16420 else if (!legitimate_indirect_address_p (addr
, false)
16421 && !rs6000_legitimate_offset_address_p (PTImode
, addr
,
16424 sri
->icode
= icode
;
16425 /* account for splitting the loads, and converting the
16426 address from reg+reg to reg. */
16427 sri
->extra_cost
= (((TARGET_64BIT
) ? 3 : 5)
16428 + ((GET_CODE (addr
) == AND
) ? 1 : 0));
16431 /* Allow scalar loads to/from the traditional floating point
16432 registers, even if VSX memory is set. */
16433 else if ((rclass
== FLOAT_REGS
|| rclass
== NO_REGS
)
16434 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8)
16435 && (legitimate_indirect_address_p (addr
, false)
16436 || legitimate_indirect_address_p (addr
, false)
16437 || rs6000_legitimate_offset_address_p (mode
, addr
,
16441 /* Loads to and stores from vector registers can only do reg+reg
16442 addressing. Altivec registers can also do (reg+reg)&(-16). Allow
16443 scalar modes loading up the traditional floating point registers
16444 to use offset addresses. */
16445 else if (rclass
== VSX_REGS
|| rclass
== ALTIVEC_REGS
16446 || rclass
== FLOAT_REGS
|| rclass
== NO_REGS
)
16448 if (!VECTOR_MEM_ALTIVEC_P (mode
)
16449 && GET_CODE (addr
) == AND
16450 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
16451 && INTVAL (XEXP (addr
, 1)) == -16
16452 && (legitimate_indirect_address_p (XEXP (addr
, 0), false)
16453 || legitimate_indexed_address_p (XEXP (addr
, 0), false)))
16455 sri
->icode
= icode
;
16456 sri
->extra_cost
= ((GET_CODE (XEXP (addr
, 0)) == PLUS
)
16459 else if (!legitimate_indirect_address_p (addr
, false)
16460 && (rclass
== NO_REGS
16461 || !legitimate_indexed_address_p (addr
, false)))
16463 sri
->icode
= icode
;
16464 sri
->extra_cost
= 1;
16467 icode
= CODE_FOR_nothing
;
16469 /* Any other loads, including to pseudo registers which haven't been
16470 assigned to a register yet, default to require a scratch
16474 sri
->icode
= icode
;
16475 sri
->extra_cost
= 2;
16478 else if (REG_P (x
))
16480 int regno
= true_regnum (x
);
16482 icode
= CODE_FOR_nothing
;
16483 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
16487 enum reg_class xclass
= REGNO_REG_CLASS (regno
);
16488 enum rs6000_reg_type rtype1
= reg_class_to_reg_type
[(int)rclass
];
16489 enum rs6000_reg_type rtype2
= reg_class_to_reg_type
[(int)xclass
];
16491 /* If memory is needed, use default_secondary_reload to create the
16493 if (rtype1
!= rtype2
|| !IS_STD_REG_TYPE (rtype1
))
16502 else if (TARGET_POWERPC64
16503 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
16505 && GET_MODE_SIZE (GET_MODE (x
)) >= UNITS_PER_WORD
)
16507 rtx addr
= XEXP (x
, 0);
16508 rtx off
= address_offset (addr
);
16510 if (off
!= NULL_RTX
)
16512 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
16513 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
16515 /* We need a secondary reload when our legitimate_address_p
16516 says the address is good (as otherwise the entire address
16517 will be reloaded), and the offset is not a multiple of
16518 four or we have an address wrap. Address wrap will only
16519 occur for LO_SUMs since legitimate_offset_address_p
16520 rejects addresses for 16-byte mems that will wrap. */
16521 if (GET_CODE (addr
) == LO_SUM
16522 ? (1 /* legitimate_address_p allows any offset for lo_sum */
16523 && ((offset
& 3) != 0
16524 || ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
))
16525 : (offset
+ 0x8000 < 0x10000 - extra
/* legitimate_address_p */
16526 && (offset
& 3) != 0))
16529 sri
->icode
= CODE_FOR_reload_di_load
;
16531 sri
->icode
= CODE_FOR_reload_di_store
;
16532 sri
->extra_cost
= 2;
16541 else if (!TARGET_POWERPC64
16542 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
16544 && GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
16546 rtx addr
= XEXP (x
, 0);
16547 rtx off
= address_offset (addr
);
16549 if (off
!= NULL_RTX
)
16551 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
16552 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
16554 /* We need a secondary reload when our legitimate_address_p
16555 says the address is good (as otherwise the entire address
16556 will be reloaded), and we have a wrap.
16558 legitimate_lo_sum_address_p allows LO_SUM addresses to
16559 have any offset so test for wrap in the low 16 bits.
16561 legitimate_offset_address_p checks for the range
16562 [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
16563 for mode size of 16. We wrap at [0x7ffc,0x7fff] and
16564 [0x7ff4,0x7fff] respectively, so test for the
16565 intersection of these ranges, [0x7ffc,0x7fff] and
16566 [0x7ff4,0x7ff7] respectively.
16568 Note that the address we see here may have been
16569 manipulated by legitimize_reload_address. */
16570 if (GET_CODE (addr
) == LO_SUM
16571 ? ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
16572 : offset
- (0x8000 - extra
) < UNITS_PER_WORD
)
16575 sri
->icode
= CODE_FOR_reload_si_load
;
16577 sri
->icode
= CODE_FOR_reload_si_store
;
16578 sri
->extra_cost
= 2;
16591 ret
= default_secondary_reload (in_p
, x
, rclass
, mode
, sri
);
16593 gcc_assert (ret
!= ALL_REGS
);
16595 if (TARGET_DEBUG_ADDR
)
16598 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
16600 reg_class_names
[ret
],
16601 in_p
? "true" : "false",
16602 reg_class_names
[rclass
],
16603 GET_MODE_NAME (mode
));
16606 fprintf (stderr
, ", default secondary reload");
16608 if (sri
->icode
!= CODE_FOR_nothing
)
16609 fprintf (stderr
, ", reload func = %s, extra cost = %d\n",
16610 insn_data
[sri
->icode
].name
, sri
->extra_cost
);
16612 fprintf (stderr
, "\n");
16620 /* Better tracing for rs6000_secondary_reload_inner. */
16623 rs6000_secondary_reload_trace (int line
, rtx reg
, rtx mem
, rtx scratch
,
16628 gcc_assert (reg
!= NULL_RTX
&& mem
!= NULL_RTX
&& scratch
!= NULL_RTX
);
16630 fprintf (stderr
, "rs6000_secondary_reload_inner:%d, type = %s\n", line
,
16631 store_p
? "store" : "load");
16634 set
= gen_rtx_SET (VOIDmode
, mem
, reg
);
16636 set
= gen_rtx_SET (VOIDmode
, reg
, mem
);
16638 clobber
= gen_rtx_CLOBBER (VOIDmode
, scratch
);
16639 debug_rtx (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
16643 rs6000_secondary_reload_fail (int line
, rtx reg
, rtx mem
, rtx scratch
,
16646 rs6000_secondary_reload_trace (line
, reg
, mem
, scratch
, store_p
);
16647 gcc_unreachable ();
16650 /* Fixup reload addresses for Altivec or VSX loads/stores to change SP+offset
16651 to SP+reg addressing. */
16654 rs6000_secondary_reload_inner (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
16656 int regno
= true_regnum (reg
);
16657 enum machine_mode mode
= GET_MODE (reg
);
16658 enum reg_class rclass
;
16660 rtx and_op2
= NULL_RTX
;
16663 rtx scratch_or_premodify
= scratch
;
16667 if (TARGET_DEBUG_ADDR
)
16668 rs6000_secondary_reload_trace (__LINE__
, reg
, mem
, scratch
, store_p
);
16670 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
16671 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16673 if (GET_CODE (mem
) != MEM
)
16674 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16676 rclass
= REGNO_REG_CLASS (regno
);
16677 addr
= find_replacement (&XEXP (mem
, 0));
16681 /* GPRs can handle reg + small constant, all other addresses need to use
16682 the scratch register. */
16685 if (GET_CODE (addr
) == AND
)
16687 and_op2
= XEXP (addr
, 1);
16688 addr
= find_replacement (&XEXP (addr
, 0));
16691 if (GET_CODE (addr
) == PRE_MODIFY
)
16693 scratch_or_premodify
= find_replacement (&XEXP (addr
, 0));
16694 if (!REG_P (scratch_or_premodify
))
16695 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16697 addr
= find_replacement (&XEXP (addr
, 1));
16698 if (GET_CODE (addr
) != PLUS
)
16699 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16702 if (GET_CODE (addr
) == PLUS
16703 && (and_op2
!= NULL_RTX
16704 || !rs6000_legitimate_offset_address_p (PTImode
, addr
,
16707 /* find_replacement already recurses into both operands of
16708 PLUS so we don't need to call it here. */
16709 addr_op1
= XEXP (addr
, 0);
16710 addr_op2
= XEXP (addr
, 1);
16711 if (!legitimate_indirect_address_p (addr_op1
, false))
16712 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16714 if (!REG_P (addr_op2
)
16715 && (GET_CODE (addr_op2
) != CONST_INT
16716 || !satisfies_constraint_I (addr_op2
)))
16718 if (TARGET_DEBUG_ADDR
)
16721 "\nMove plus addr to register %s, mode = %s: ",
16722 rs6000_reg_names
[REGNO (scratch
)],
16723 GET_MODE_NAME (mode
));
16724 debug_rtx (addr_op2
);
16726 rs6000_emit_move (scratch
, addr_op2
, Pmode
);
16727 addr_op2
= scratch
;
16730 emit_insn (gen_rtx_SET (VOIDmode
,
16731 scratch_or_premodify
,
16732 gen_rtx_PLUS (Pmode
,
16736 addr
= scratch_or_premodify
;
16737 scratch_or_premodify
= scratch
;
16739 else if (!legitimate_indirect_address_p (addr
, false)
16740 && !rs6000_legitimate_offset_address_p (PTImode
, addr
,
16743 if (TARGET_DEBUG_ADDR
)
16745 fprintf (stderr
, "\nMove addr to register %s, mode = %s: ",
16746 rs6000_reg_names
[REGNO (scratch_or_premodify
)],
16747 GET_MODE_NAME (mode
));
16750 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
16751 addr
= scratch_or_premodify
;
16752 scratch_or_premodify
= scratch
;
16756 /* Float registers can do offset+reg addressing for scalar types. */
16758 if (legitimate_indirect_address_p (addr
, false) /* reg */
16759 || legitimate_indexed_address_p (addr
, false) /* reg+reg */
16760 || ((GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8)
16761 && and_op2
== NULL_RTX
16762 && scratch_or_premodify
== scratch
16763 && rs6000_legitimate_offset_address_p (mode
, addr
, false, false)))
16766 /* If this isn't a legacy floating point load/store, fall through to the
16769 /* VSX/Altivec registers can only handle reg+reg addressing. Move other
16770 addresses into a scratch register. */
16774 /* With float regs, we need to handle the AND ourselves, since we can't
16775 use the Altivec instruction with an implicit AND -16. Allow scalar
16776 loads to float registers to use reg+offset even if VSX. */
16777 if (GET_CODE (addr
) == AND
16778 && (rclass
!= ALTIVEC_REGS
|| GET_MODE_SIZE (mode
) != 16
16779 || GET_CODE (XEXP (addr
, 1)) != CONST_INT
16780 || INTVAL (XEXP (addr
, 1)) != -16
16781 || !VECTOR_MEM_ALTIVEC_P (mode
)))
16783 and_op2
= XEXP (addr
, 1);
16784 addr
= find_replacement (&XEXP (addr
, 0));
16787 /* If we aren't using a VSX load, save the PRE_MODIFY register and use it
16788 as the address later. */
16789 if (GET_CODE (addr
) == PRE_MODIFY
16790 && ((ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
16791 && (rclass
!= FLOAT_REGS
16792 || (GET_MODE_SIZE (mode
) != 4 && GET_MODE_SIZE (mode
) != 8)))
16793 || and_op2
!= NULL_RTX
16794 || !legitimate_indexed_address_p (XEXP (addr
, 1), false)))
16796 scratch_or_premodify
= find_replacement (&XEXP (addr
, 0));
16797 if (!legitimate_indirect_address_p (scratch_or_premodify
, false))
16798 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16800 addr
= find_replacement (&XEXP (addr
, 1));
16801 if (GET_CODE (addr
) != PLUS
)
16802 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16805 if (legitimate_indirect_address_p (addr
, false) /* reg */
16806 || legitimate_indexed_address_p (addr
, false) /* reg+reg */
16807 || (GET_CODE (addr
) == AND
/* Altivec memory */
16808 && rclass
== ALTIVEC_REGS
16809 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
16810 && INTVAL (XEXP (addr
, 1)) == -16
16811 && (legitimate_indirect_address_p (XEXP (addr
, 0), false)
16812 || legitimate_indexed_address_p (XEXP (addr
, 0), false))))
16815 else if (GET_CODE (addr
) == PLUS
)
16817 addr_op1
= XEXP (addr
, 0);
16818 addr_op2
= XEXP (addr
, 1);
16819 if (!REG_P (addr_op1
))
16820 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16822 if (TARGET_DEBUG_ADDR
)
16824 fprintf (stderr
, "\nMove plus addr to register %s, mode = %s: ",
16825 rs6000_reg_names
[REGNO (scratch
)], GET_MODE_NAME (mode
));
16826 debug_rtx (addr_op2
);
16828 rs6000_emit_move (scratch
, addr_op2
, Pmode
);
16829 emit_insn (gen_rtx_SET (VOIDmode
,
16830 scratch_or_premodify
,
16831 gen_rtx_PLUS (Pmode
,
16834 addr
= scratch_or_premodify
;
16835 scratch_or_premodify
= scratch
;
16838 else if (GET_CODE (addr
) == SYMBOL_REF
|| GET_CODE (addr
) == CONST
16839 || GET_CODE (addr
) == CONST_INT
|| GET_CODE (addr
) == LO_SUM
16842 if (TARGET_DEBUG_ADDR
)
16844 fprintf (stderr
, "\nMove addr to register %s, mode = %s: ",
16845 rs6000_reg_names
[REGNO (scratch_or_premodify
)],
16846 GET_MODE_NAME (mode
));
16850 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
16851 addr
= scratch_or_premodify
;
16852 scratch_or_premodify
= scratch
;
16856 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16861 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16864 /* If the original address involved a pre-modify that we couldn't use the VSX
16865 memory instruction with update, and we haven't taken care of already,
16866 store the address in the pre-modify register and use that as the
16868 if (scratch_or_premodify
!= scratch
&& scratch_or_premodify
!= addr
)
16870 emit_insn (gen_rtx_SET (VOIDmode
, scratch_or_premodify
, addr
));
16871 addr
= scratch_or_premodify
;
16874 /* If the original address involved an AND -16 and we couldn't use an ALTIVEC
16875 memory instruction, recreate the AND now, including the clobber which is
16876 generated by the general ANDSI3/ANDDI3 patterns for the
16877 andi. instruction. */
16878 if (and_op2
!= NULL_RTX
)
16880 if (! legitimate_indirect_address_p (addr
, false))
16882 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, addr
));
16886 if (TARGET_DEBUG_ADDR
)
16888 fprintf (stderr
, "\nAnd addr to register %s, mode = %s: ",
16889 rs6000_reg_names
[REGNO (scratch
)], GET_MODE_NAME (mode
));
16890 debug_rtx (and_op2
);
16893 and_rtx
= gen_rtx_SET (VOIDmode
,
16895 gen_rtx_AND (Pmode
,
16899 cc_clobber
= gen_rtx_CLOBBER (CCmode
, gen_rtx_SCRATCH (CCmode
));
16900 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
16901 gen_rtvec (2, and_rtx
, cc_clobber
)));
16905 /* Adjust the address if it changed. */
16906 if (addr
!= XEXP (mem
, 0))
16908 mem
= replace_equiv_address_nv (mem
, addr
);
16909 if (TARGET_DEBUG_ADDR
)
16910 fprintf (stderr
, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
16913 /* Now create the move. */
16915 emit_insn (gen_rtx_SET (VOIDmode
, mem
, reg
));
16917 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
16922 /* Convert reloads involving 64-bit gprs and misaligned offset
16923 addressing, or multiple 32-bit gprs and offsets that are too large,
16924 to use indirect addressing. */
16927 rs6000_secondary_reload_gpr (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
16929 int regno
= true_regnum (reg
);
16930 enum reg_class rclass
;
16932 rtx scratch_or_premodify
= scratch
;
16934 if (TARGET_DEBUG_ADDR
)
16936 fprintf (stderr
, "\nrs6000_secondary_reload_gpr, type = %s\n",
16937 store_p
? "store" : "load");
16938 fprintf (stderr
, "reg:\n");
16940 fprintf (stderr
, "mem:\n");
16942 fprintf (stderr
, "scratch:\n");
16943 debug_rtx (scratch
);
16946 gcc_assert (regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
);
16947 gcc_assert (GET_CODE (mem
) == MEM
);
16948 rclass
= REGNO_REG_CLASS (regno
);
16949 gcc_assert (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
);
16950 addr
= XEXP (mem
, 0);
16952 if (GET_CODE (addr
) == PRE_MODIFY
)
16954 scratch_or_premodify
= XEXP (addr
, 0);
16955 gcc_assert (REG_P (scratch_or_premodify
));
16956 addr
= XEXP (addr
, 1);
16958 gcc_assert (GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
);
16960 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
16962 mem
= replace_equiv_address_nv (mem
, scratch_or_premodify
);
16964 /* Now create the move. */
16966 emit_insn (gen_rtx_SET (VOIDmode
, mem
, reg
));
16968 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
16973 /* Allocate a 64-bit stack slot to be used for copying SDmode values through if
16974 this function has any SDmode references. If we are on a power7 or later, we
16975 don't need the 64-bit stack slot since the LFIWZX and STIFWX instructions
16976 can load/store the value. */
16979 rs6000_alloc_sdmode_stack_slot (void)
16983 gimple_stmt_iterator gsi
;
16985 gcc_assert (cfun
->machine
->sdmode_stack_slot
== NULL_RTX
);
16986 /* We use a different approach for dealing with the secondary
16991 if (TARGET_NO_SDMODE_STACK
)
16994 FOR_EACH_BB_FN (bb
, cfun
)
16995 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
16997 tree ret
= walk_gimple_op (gsi_stmt (gsi
), rs6000_check_sdmode
, NULL
);
17000 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
17001 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
17007 /* Check for any SDmode parameters of the function. */
17008 for (t
= DECL_ARGUMENTS (cfun
->decl
); t
; t
= DECL_CHAIN (t
))
17010 if (TREE_TYPE (t
) == error_mark_node
)
17013 if (TYPE_MODE (TREE_TYPE (t
)) == SDmode
17014 || TYPE_MODE (DECL_ARG_TYPE (t
)) == SDmode
)
17016 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
17017 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
17025 rs6000_instantiate_decls (void)
17027 if (cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
17028 instantiate_decl_rtl (cfun
->machine
->sdmode_stack_slot
);
17031 /* Given an rtx X being reloaded into a reg required to be
17032 in class CLASS, return the class of reg to actually use.
17033 In general this is just CLASS; but on some machines
17034 in some cases it is preferable to use a more restrictive class.
17036 On the RS/6000, we have to return NO_REGS when we want to reload a
17037 floating-point CONST_DOUBLE to force it to be copied to memory.
17039 We also don't want to reload integer values into floating-point
17040 registers if we can at all help it. In fact, this can
17041 cause reload to die, if it tries to generate a reload of CTR
17042 into a FP register and discovers it doesn't have the memory location
17045 ??? Would it be a good idea to have reload do the converse, that is
17046 try to reload floating modes into FP registers if possible?
17049 static enum reg_class
17050 rs6000_preferred_reload_class (rtx x
, enum reg_class rclass
)
17052 enum machine_mode mode
= GET_MODE (x
);
17054 if (TARGET_VSX
&& x
== CONST0_RTX (mode
) && VSX_REG_CLASS_P (rclass
))
17057 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
17058 && (rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
17059 && easy_vector_constant (x
, mode
))
17060 return ALTIVEC_REGS
;
17062 if ((CONSTANT_P (x
) || GET_CODE (x
) == PLUS
))
17064 if (reg_class_subset_p (GENERAL_REGS
, rclass
))
17065 return GENERAL_REGS
;
17066 if (reg_class_subset_p (BASE_REGS
, rclass
))
17071 if (GET_MODE_CLASS (mode
) == MODE_INT
&& rclass
== NON_SPECIAL_REGS
)
17072 return GENERAL_REGS
;
17074 /* For VSX, prefer the traditional registers for 64-bit values because we can
17075 use the non-VSX loads. Prefer the Altivec registers if Altivec is
17076 handling the vector operations (i.e. V16QI, V8HI, and V4SI), or if we
17077 prefer Altivec loads.. */
17078 if (rclass
== VSX_REGS
)
17080 if (GET_MODE_SIZE (mode
) <= 8)
17083 if (VECTOR_UNIT_ALTIVEC_P (mode
) || VECTOR_MEM_ALTIVEC_P (mode
)
17084 || mode
== V1TImode
)
17085 return ALTIVEC_REGS
;
17093 /* Debug version of rs6000_preferred_reload_class. */
17094 static enum reg_class
17095 rs6000_debug_preferred_reload_class (rtx x
, enum reg_class rclass
)
17097 enum reg_class ret
= rs6000_preferred_reload_class (x
, rclass
);
17100 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
17102 reg_class_names
[ret
], reg_class_names
[rclass
],
17103 GET_MODE_NAME (GET_MODE (x
)));
17109 /* If we are copying between FP or AltiVec registers and anything else, we need
17110 a memory location. The exception is when we are targeting ppc64 and the
17111 move to/from fpr to gpr instructions are available. Also, under VSX, you
17112 can copy vector registers from the FP register set to the Altivec register
17113 set and vice versa. */
17116 rs6000_secondary_memory_needed (enum reg_class from_class
,
17117 enum reg_class to_class
,
17118 enum machine_mode mode
)
17120 enum rs6000_reg_type from_type
, to_type
;
17121 bool altivec_p
= ((from_class
== ALTIVEC_REGS
)
17122 || (to_class
== ALTIVEC_REGS
));
17124 /* If a simple/direct move is available, we don't need secondary memory */
17125 from_type
= reg_class_to_reg_type
[(int)from_class
];
17126 to_type
= reg_class_to_reg_type
[(int)to_class
];
17128 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
,
17129 (secondary_reload_info
*)0, altivec_p
))
17132 /* If we have a floating point or vector register class, we need to use
17133 memory to transfer the data. */
17134 if (IS_FP_VECT_REG_TYPE (from_type
) || IS_FP_VECT_REG_TYPE (to_type
))
17140 /* Debug version of rs6000_secondary_memory_needed. */
17142 rs6000_debug_secondary_memory_needed (enum reg_class from_class
,
17143 enum reg_class to_class
,
17144 enum machine_mode mode
)
17146 bool ret
= rs6000_secondary_memory_needed (from_class
, to_class
, mode
);
17149 "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
17150 "to_class = %s, mode = %s\n",
17151 ret
? "true" : "false",
17152 reg_class_names
[from_class
],
17153 reg_class_names
[to_class
],
17154 GET_MODE_NAME (mode
));
17159 /* Return the register class of a scratch register needed to copy IN into
17160 or out of a register in RCLASS in MODE. If it can be done directly,
17161 NO_REGS is returned. */
17163 static enum reg_class
17164 rs6000_secondary_reload_class (enum reg_class rclass
, enum machine_mode mode
,
17169 if (TARGET_ELF
|| (DEFAULT_ABI
== ABI_DARWIN
17171 && MACHOPIC_INDIRECT
17175 /* We cannot copy a symbolic operand directly into anything
17176 other than BASE_REGS for TARGET_ELF. So indicate that a
17177 register from BASE_REGS is needed as an intermediate
17180 On Darwin, pic addresses require a load from memory, which
17181 needs a base register. */
17182 if (rclass
!= BASE_REGS
17183 && (GET_CODE (in
) == SYMBOL_REF
17184 || GET_CODE (in
) == HIGH
17185 || GET_CODE (in
) == LABEL_REF
17186 || GET_CODE (in
) == CONST
))
17190 if (GET_CODE (in
) == REG
)
17192 regno
= REGNO (in
);
17193 if (regno
>= FIRST_PSEUDO_REGISTER
)
17195 regno
= true_regnum (in
);
17196 if (regno
>= FIRST_PSEUDO_REGISTER
)
17200 else if (GET_CODE (in
) == SUBREG
)
17202 regno
= true_regnum (in
);
17203 if (regno
>= FIRST_PSEUDO_REGISTER
)
17209 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
17211 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
17212 || (regno
>= 0 && INT_REGNO_P (regno
)))
17215 /* Constants, memory, and FP registers can go into FP registers. */
17216 if ((regno
== -1 || FP_REGNO_P (regno
))
17217 && (rclass
== FLOAT_REGS
|| rclass
== NON_SPECIAL_REGS
))
17218 return (mode
!= SDmode
|| lra_in_progress
) ? NO_REGS
: GENERAL_REGS
;
17220 /* Memory, and FP/altivec registers can go into fp/altivec registers under
17221 VSX. However, for scalar variables, use the traditional floating point
17222 registers so that we can use offset+register addressing. */
17224 && (regno
== -1 || VSX_REGNO_P (regno
))
17225 && VSX_REG_CLASS_P (rclass
))
17227 if (GET_MODE_SIZE (mode
) < 16)
17233 /* Memory, and AltiVec registers can go into AltiVec registers. */
17234 if ((regno
== -1 || ALTIVEC_REGNO_P (regno
))
17235 && rclass
== ALTIVEC_REGS
)
17238 /* We can copy among the CR registers. */
17239 if ((rclass
== CR_REGS
|| rclass
== CR0_REGS
)
17240 && regno
>= 0 && CR_REGNO_P (regno
))
17243 /* Otherwise, we need GENERAL_REGS. */
17244 return GENERAL_REGS
;
17247 /* Debug version of rs6000_secondary_reload_class. */
17248 static enum reg_class
17249 rs6000_debug_secondary_reload_class (enum reg_class rclass
,
17250 enum machine_mode mode
, rtx in
)
17252 enum reg_class ret
= rs6000_secondary_reload_class (rclass
, mode
, in
);
17254 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
17255 "mode = %s, input rtx:\n",
17256 reg_class_names
[ret
], reg_class_names
[rclass
],
17257 GET_MODE_NAME (mode
));
17263 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
17266 rs6000_cannot_change_mode_class (enum machine_mode from
,
17267 enum machine_mode to
,
17268 enum reg_class rclass
)
17270 unsigned from_size
= GET_MODE_SIZE (from
);
17271 unsigned to_size
= GET_MODE_SIZE (to
);
17273 if (from_size
!= to_size
)
17275 enum reg_class xclass
= (TARGET_VSX
) ? VSX_REGS
: FLOAT_REGS
;
17277 if (reg_classes_intersect_p (xclass
, rclass
))
17279 unsigned to_nregs
= hard_regno_nregs
[FIRST_FPR_REGNO
][to
];
17280 unsigned from_nregs
= hard_regno_nregs
[FIRST_FPR_REGNO
][from
];
17282 /* Don't allow 64-bit types to overlap with 128-bit types that take a
17283 single register under VSX because the scalar part of the register
17284 is in the upper 64-bits, and not the lower 64-bits. Types like
17285 TFmode/TDmode that take 2 scalar register can overlap. 128-bit
17286 IEEE floating point can't overlap, and neither can small
17289 if (TARGET_IEEEQUAD
&& (to
== TFmode
|| from
== TFmode
))
17292 /* TDmode in floating-mode registers must always go into a register
17293 pair with the most significant word in the even-numbered register
17294 to match ISA requirements. In little-endian mode, this does not
17295 match subreg numbering, so we cannot allow subregs. */
17296 if (!BYTES_BIG_ENDIAN
&& (to
== TDmode
|| from
== TDmode
))
17299 if (from_size
< 8 || to_size
< 8)
17302 if (from_size
== 8 && (8 * to_nregs
) != to_size
)
17305 if (to_size
== 8 && (8 * from_nregs
) != from_size
)
17314 if (TARGET_E500_DOUBLE
17315 && ((((to
) == DFmode
) + ((from
) == DFmode
)) == 1
17316 || (((to
) == TFmode
) + ((from
) == TFmode
)) == 1
17317 || (((to
) == DDmode
) + ((from
) == DDmode
)) == 1
17318 || (((to
) == TDmode
) + ((from
) == TDmode
)) == 1
17319 || (((to
) == DImode
) + ((from
) == DImode
)) == 1))
17322 /* Since the VSX register set includes traditional floating point registers
17323 and altivec registers, just check for the size being different instead of
17324 trying to check whether the modes are vector modes. Otherwise it won't
17325 allow say DF and DI to change classes. For types like TFmode and TDmode
17326 that take 2 64-bit registers, rather than a single 128-bit register, don't
17327 allow subregs of those types to other 128 bit types. */
17328 if (TARGET_VSX
&& VSX_REG_CLASS_P (rclass
))
17330 unsigned num_regs
= (from_size
+ 15) / 16;
17331 if (hard_regno_nregs
[FIRST_FPR_REGNO
][to
] > num_regs
17332 || hard_regno_nregs
[FIRST_FPR_REGNO
][from
] > num_regs
)
17335 return (from_size
!= 8 && from_size
!= 16);
17338 if (TARGET_ALTIVEC
&& rclass
== ALTIVEC_REGS
17339 && (ALTIVEC_VECTOR_MODE (from
) + ALTIVEC_VECTOR_MODE (to
)) == 1)
17342 if (TARGET_SPE
&& (SPE_VECTOR_MODE (from
) + SPE_VECTOR_MODE (to
)) == 1
17343 && reg_classes_intersect_p (GENERAL_REGS
, rclass
))
17349 /* Debug version of rs6000_cannot_change_mode_class. */
17351 rs6000_debug_cannot_change_mode_class (enum machine_mode from
,
17352 enum machine_mode to
,
17353 enum reg_class rclass
)
17355 bool ret
= rs6000_cannot_change_mode_class (from
, to
, rclass
);
17358 "rs6000_cannot_change_mode_class, return %s, from = %s, "
17359 "to = %s, rclass = %s\n",
17360 ret
? "true" : "false",
17361 GET_MODE_NAME (from
), GET_MODE_NAME (to
),
17362 reg_class_names
[rclass
]);
17367 /* Return a string to do a move operation of 128 bits of data. */
17370 rs6000_output_move_128bit (rtx operands
[])
17372 rtx dest
= operands
[0];
17373 rtx src
= operands
[1];
17374 enum machine_mode mode
= GET_MODE (dest
);
17377 bool dest_gpr_p
, dest_fp_p
, dest_vmx_p
, dest_vsx_p
;
17378 bool src_gpr_p
, src_fp_p
, src_vmx_p
, src_vsx_p
;
17382 dest_regno
= REGNO (dest
);
17383 dest_gpr_p
= INT_REGNO_P (dest_regno
);
17384 dest_fp_p
= FP_REGNO_P (dest_regno
);
17385 dest_vmx_p
= ALTIVEC_REGNO_P (dest_regno
);
17386 dest_vsx_p
= dest_fp_p
| dest_vmx_p
;
17391 dest_gpr_p
= dest_fp_p
= dest_vmx_p
= dest_vsx_p
= false;
17396 src_regno
= REGNO (src
);
17397 src_gpr_p
= INT_REGNO_P (src_regno
);
17398 src_fp_p
= FP_REGNO_P (src_regno
);
17399 src_vmx_p
= ALTIVEC_REGNO_P (src_regno
);
17400 src_vsx_p
= src_fp_p
| src_vmx_p
;
17405 src_gpr_p
= src_fp_p
= src_vmx_p
= src_vsx_p
= false;
17408 /* Register moves. */
17409 if (dest_regno
>= 0 && src_regno
>= 0)
17416 else if (TARGET_VSX
&& TARGET_DIRECT_MOVE
&& src_vsx_p
)
17420 else if (TARGET_VSX
&& dest_vsx_p
)
17423 return "xxlor %x0,%x1,%x1";
17425 else if (TARGET_DIRECT_MOVE
&& src_gpr_p
)
17429 else if (TARGET_ALTIVEC
&& dest_vmx_p
&& src_vmx_p
)
17430 return "vor %0,%1,%1";
17432 else if (dest_fp_p
&& src_fp_p
)
17437 else if (dest_regno
>= 0 && MEM_P (src
))
17441 if (TARGET_QUAD_MEMORY
&& quad_load_store_p (dest
, src
))
17447 else if (TARGET_ALTIVEC
&& dest_vmx_p
17448 && altivec_indexed_or_indirect_operand (src
, mode
))
17449 return "lvx %0,%y1";
17451 else if (TARGET_VSX
&& dest_vsx_p
)
17453 if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
17454 return "lxvw4x %x0,%y1";
17456 return "lxvd2x %x0,%y1";
17459 else if (TARGET_ALTIVEC
&& dest_vmx_p
)
17460 return "lvx %0,%y1";
17462 else if (dest_fp_p
)
17467 else if (src_regno
>= 0 && MEM_P (dest
))
17471 if (TARGET_QUAD_MEMORY
&& quad_load_store_p (dest
, src
))
17472 return "stq %1,%0";
17477 else if (TARGET_ALTIVEC
&& src_vmx_p
17478 && altivec_indexed_or_indirect_operand (src
, mode
))
17479 return "stvx %1,%y0";
17481 else if (TARGET_VSX
&& src_vsx_p
)
17483 if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
17484 return "stxvw4x %x1,%y0";
17486 return "stxvd2x %x1,%y0";
17489 else if (TARGET_ALTIVEC
&& src_vmx_p
)
17490 return "stvx %1,%y0";
17497 else if (dest_regno
>= 0
17498 && (GET_CODE (src
) == CONST_INT
17499 || GET_CODE (src
) == CONST_WIDE_INT
17500 || GET_CODE (src
) == CONST_DOUBLE
17501 || GET_CODE (src
) == CONST_VECTOR
))
17506 else if (TARGET_VSX
&& dest_vsx_p
&& zero_constant (src
, mode
))
17507 return "xxlxor %x0,%x0,%x0";
17509 else if (TARGET_ALTIVEC
&& dest_vmx_p
)
17510 return output_vec_const_move (operands
);
17513 if (TARGET_DEBUG_ADDR
)
17515 fprintf (stderr
, "\n===== Bad 128 bit move:\n");
17516 debug_rtx (gen_rtx_SET (VOIDmode
, dest
, src
));
17519 gcc_unreachable ();
17522 /* Validate a 128-bit move. */
17524 rs6000_move_128bit_ok_p (rtx operands
[])
17526 enum machine_mode mode
= GET_MODE (operands
[0]);
17527 return (gpc_reg_operand (operands
[0], mode
)
17528 || gpc_reg_operand (operands
[1], mode
));
17531 /* Return true if a 128-bit move needs to be split. */
17533 rs6000_split_128bit_ok_p (rtx operands
[])
17535 if (!reload_completed
)
17538 if (!gpr_or_gpr_p (operands
[0], operands
[1]))
17541 if (quad_load_store_p (operands
[0], operands
[1]))
17548 /* Given a comparison operation, return the bit number in CCR to test. We
17549 know this is a valid comparison.
17551 SCC_P is 1 if this is for an scc. That means that %D will have been
17552 used instead of %C, so the bits will be in different places.
17554 Return -1 if OP isn't a valid comparison for some reason. */
17557 ccr_bit (rtx op
, int scc_p
)
17559 enum rtx_code code
= GET_CODE (op
);
17560 enum machine_mode cc_mode
;
17565 if (!COMPARISON_P (op
))
17568 reg
= XEXP (op
, 0);
17570 gcc_assert (GET_CODE (reg
) == REG
&& CR_REGNO_P (REGNO (reg
)));
17572 cc_mode
= GET_MODE (reg
);
17573 cc_regnum
= REGNO (reg
);
17574 base_bit
= 4 * (cc_regnum
- CR0_REGNO
);
17576 validate_condition_mode (code
, cc_mode
);
17578 /* When generating a sCOND operation, only positive conditions are
17581 || code
== EQ
|| code
== GT
|| code
== LT
|| code
== UNORDERED
17582 || code
== GTU
|| code
== LTU
);
17587 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
17589 return base_bit
+ 2;
17590 case GT
: case GTU
: case UNLE
:
17591 return base_bit
+ 1;
17592 case LT
: case LTU
: case UNGE
:
17594 case ORDERED
: case UNORDERED
:
17595 return base_bit
+ 3;
17598 /* If scc, we will have done a cror to put the bit in the
17599 unordered position. So test that bit. For integer, this is ! LT
17600 unless this is an scc insn. */
17601 return scc_p
? base_bit
+ 3 : base_bit
;
17604 return scc_p
? base_bit
+ 3 : base_bit
+ 1;
17607 gcc_unreachable ();
17611 /* Return the GOT register. */
17614 rs6000_got_register (rtx value ATTRIBUTE_UNUSED
)
17616 /* The second flow pass currently (June 1999) can't update
17617 regs_ever_live without disturbing other parts of the compiler, so
17618 update it here to make the prolog/epilogue code happy. */
17619 if (!can_create_pseudo_p ()
17620 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
17621 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM
, true);
17623 crtl
->uses_pic_offset_table
= 1;
17625 return pic_offset_table_rtx
;
17628 static rs6000_stack_t stack_info
;
17630 /* Function to init struct machine_function.
17631 This will be called, via a pointer variable,
17632 from push_function_context. */
17634 static struct machine_function
*
17635 rs6000_init_machine_status (void)
17637 stack_info
.reload_completed
= 0;
17638 return ggc_cleared_alloc
<machine_function
> ();
17641 #define INT_P(X) (GET_CODE (X) == CONST_INT && GET_MODE (X) == VOIDmode)
17644 extract_MB (rtx op
)
17647 unsigned long val
= INTVAL (op
);
17649 /* If the high bit is zero, the value is the first 1 bit we find
17651 if ((val
& 0x80000000) == 0)
17653 gcc_assert (val
& 0xffffffff);
17656 while (((val
<<= 1) & 0x80000000) == 0)
17661 /* If the high bit is set and the low bit is not, or the mask is all
17662 1's, the value is zero. */
17663 if ((val
& 1) == 0 || (val
& 0xffffffff) == 0xffffffff)
17666 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
17669 while (((val
>>= 1) & 1) != 0)
17676 extract_ME (rtx op
)
17679 unsigned long val
= INTVAL (op
);
17681 /* If the low bit is zero, the value is the first 1 bit we find from
17683 if ((val
& 1) == 0)
17685 gcc_assert (val
& 0xffffffff);
17688 while (((val
>>= 1) & 1) == 0)
17694 /* If the low bit is set and the high bit is not, or the mask is all
17695 1's, the value is 31. */
17696 if ((val
& 0x80000000) == 0 || (val
& 0xffffffff) == 0xffffffff)
17699 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
17702 while (((val
<<= 1) & 0x80000000) != 0)
17708 /* Locate some local-dynamic symbol still in use by this function
17709 so that we can print its name in some tls_ld pattern. */
17711 static const char *
17712 rs6000_get_some_local_dynamic_name (void)
17716 if (cfun
->machine
->some_ld_name
)
17717 return cfun
->machine
->some_ld_name
;
17719 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
17721 && for_each_rtx (&PATTERN (insn
),
17722 rs6000_get_some_local_dynamic_name_1
, 0))
17723 return cfun
->machine
->some_ld_name
;
17725 gcc_unreachable ();
17728 /* Helper function for rs6000_get_some_local_dynamic_name. */
17731 rs6000_get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
17735 if (GET_CODE (x
) == SYMBOL_REF
)
17737 const char *str
= XSTR (x
, 0);
17738 if (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
17740 cfun
->machine
->some_ld_name
= str
;
17748 /* Write out a function code label. */
17751 rs6000_output_function_entry (FILE *file
, const char *fname
)
17753 if (fname
[0] != '.')
17755 switch (DEFAULT_ABI
)
17758 gcc_unreachable ();
17764 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "L.");
17774 RS6000_OUTPUT_BASENAME (file
, fname
);
17777 /* Print an operand. Recognize special options, documented below. */
17780 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
17781 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
17783 #define SMALL_DATA_RELOC "sda21"
17784 #define SMALL_DATA_REG 0
17788 print_operand (FILE *file
, rtx x
, int code
)
17791 unsigned HOST_WIDE_INT uval
;
17795 /* %a is output_address. */
17798 /* If constant, low-order 16 bits of constant, unsigned.
17799 Otherwise, write normally. */
17801 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffff);
17803 print_operand (file
, x
, 0);
17807 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
17808 for 64-bit mask direction. */
17809 putc (((INTVAL (x
) & 1) == 0 ? 'r' : 'l'), file
);
17812 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
17816 /* Like 'J' but get to the GT bit only. */
17817 gcc_assert (REG_P (x
));
17819 /* Bit 1 is GT bit. */
17820 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 1;
17822 /* Add one for shift count in rlinm for scc. */
17823 fprintf (file
, "%d", i
+ 1);
17827 /* X is a CR register. Print the number of the EQ bit of the CR */
17828 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
17829 output_operand_lossage ("invalid %%E value");
17831 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 2);
17835 /* X is a CR register. Print the shift count needed to move it
17836 to the high-order four bits. */
17837 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
17838 output_operand_lossage ("invalid %%f value");
17840 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
));
17844 /* Similar, but print the count for the rotate in the opposite
17846 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
17847 output_operand_lossage ("invalid %%F value");
17849 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - CR0_REGNO
));
17853 /* X is a constant integer. If it is negative, print "m",
17854 otherwise print "z". This is to make an aze or ame insn. */
17855 if (GET_CODE (x
) != CONST_INT
)
17856 output_operand_lossage ("invalid %%G value");
17857 else if (INTVAL (x
) >= 0)
17864 /* If constant, output low-order five bits. Otherwise, write
17867 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 31);
17869 print_operand (file
, x
, 0);
17873 /* If constant, output low-order six bits. Otherwise, write
17876 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 63);
17878 print_operand (file
, x
, 0);
17882 /* Print `i' if this is a constant, else nothing. */
17888 /* Write the bit number in CCR for jump. */
17889 i
= ccr_bit (x
, 0);
17891 output_operand_lossage ("invalid %%j code");
17893 fprintf (file
, "%d", i
);
17897 /* Similar, but add one for shift count in rlinm for scc and pass
17898 scc flag to `ccr_bit'. */
17899 i
= ccr_bit (x
, 1);
17901 output_operand_lossage ("invalid %%J code");
17903 /* If we want bit 31, write a shift count of zero, not 32. */
17904 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
17908 /* X must be a constant. Write the 1's complement of the
17911 output_operand_lossage ("invalid %%k value");
17913 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
17917 /* X must be a symbolic constant on ELF. Write an
17918 expression suitable for an 'addi' that adds in the low 16
17919 bits of the MEM. */
17920 if (GET_CODE (x
) == CONST
)
17922 if (GET_CODE (XEXP (x
, 0)) != PLUS
17923 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
17924 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
17925 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
17926 output_operand_lossage ("invalid %%K value");
17928 print_operand_address (file
, x
);
17929 fputs ("@l", file
);
17932 /* %l is output_asm_label. */
17935 /* Write second word of DImode or DFmode reference. Works on register
17936 or non-indexed memory only. */
17938 fputs (reg_names
[REGNO (x
) + 1], file
);
17939 else if (MEM_P (x
))
17941 /* Handle possible auto-increment. Since it is pre-increment and
17942 we have already done it, we can just use an offset of word. */
17943 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
17944 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
17945 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
17947 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
17948 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
17951 output_address (XEXP (adjust_address_nv (x
, SImode
,
17955 if (small_data_operand (x
, GET_MODE (x
)))
17956 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
17957 reg_names
[SMALL_DATA_REG
]);
17962 /* MB value for a mask operand. */
17963 if (! mask_operand (x
, SImode
))
17964 output_operand_lossage ("invalid %%m value");
17966 fprintf (file
, "%d", extract_MB (x
));
17970 /* ME value for a mask operand. */
17971 if (! mask_operand (x
, SImode
))
17972 output_operand_lossage ("invalid %%M value");
17974 fprintf (file
, "%d", extract_ME (x
));
17977 /* %n outputs the negative of its operand. */
17980 /* Write the number of elements in the vector times 4. */
17981 if (GET_CODE (x
) != PARALLEL
)
17982 output_operand_lossage ("invalid %%N value");
17984 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
17988 /* Similar, but subtract 1 first. */
17989 if (GET_CODE (x
) != PARALLEL
)
17990 output_operand_lossage ("invalid %%O value");
17992 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
17996 /* X is a CONST_INT that is a power of two. Output the logarithm. */
17999 || (i
= exact_log2 (INTVAL (x
))) < 0)
18000 output_operand_lossage ("invalid %%p value");
18002 fprintf (file
, "%d", i
);
18006 /* The operand must be an indirect memory reference. The result
18007 is the register name. */
18008 if (GET_CODE (x
) != MEM
|| GET_CODE (XEXP (x
, 0)) != REG
18009 || REGNO (XEXP (x
, 0)) >= 32)
18010 output_operand_lossage ("invalid %%P value");
18012 fputs (reg_names
[REGNO (XEXP (x
, 0))], file
);
18016 /* This outputs the logical code corresponding to a boolean
18017 expression. The expression may have one or both operands
18018 negated (if one, only the first one). For condition register
18019 logical operations, it will also treat the negated
18020 CR codes as NOTs, but not handle NOTs of them. */
18022 const char *const *t
= 0;
18024 enum rtx_code code
= GET_CODE (x
);
18025 static const char * const tbl
[3][3] = {
18026 { "and", "andc", "nor" },
18027 { "or", "orc", "nand" },
18028 { "xor", "eqv", "xor" } };
18032 else if (code
== IOR
)
18034 else if (code
== XOR
)
18037 output_operand_lossage ("invalid %%q value");
18039 if (GET_CODE (XEXP (x
, 0)) != NOT
)
18043 if (GET_CODE (XEXP (x
, 1)) == NOT
)
18054 if (! TARGET_MFCRF
)
18060 /* X is a CR register. Print the mask for `mtcrf'. */
18061 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
18062 output_operand_lossage ("invalid %%R value");
18064 fprintf (file
, "%d", 128 >> (REGNO (x
) - CR0_REGNO
));
18068 /* Low 5 bits of 32 - value */
18070 output_operand_lossage ("invalid %%s value");
18072 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (32 - INTVAL (x
)) & 31);
18076 /* PowerPC64 mask position. All 0's is excluded.
18077 CONST_INT 32-bit mask is considered sign-extended so any
18078 transition must occur within the CONST_INT, not on the boundary. */
18079 if (! mask64_operand (x
, DImode
))
18080 output_operand_lossage ("invalid %%S value");
18084 if (uval
& 1) /* Clear Left */
18086 #if HOST_BITS_PER_WIDE_INT > 64
18087 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
18091 else /* Clear Right */
18094 #if HOST_BITS_PER_WIDE_INT > 64
18095 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
18101 gcc_assert (i
>= 0);
18102 fprintf (file
, "%d", i
);
18106 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
18107 gcc_assert (REG_P (x
) && GET_MODE (x
) == CCmode
);
18109 /* Bit 3 is OV bit. */
18110 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 3;
18112 /* If we want bit 31, write a shift count of zero, not 32. */
18113 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
18117 /* Print the symbolic name of a branch target register. */
18118 if (GET_CODE (x
) != REG
|| (REGNO (x
) != LR_REGNO
18119 && REGNO (x
) != CTR_REGNO
))
18120 output_operand_lossage ("invalid %%T value");
18121 else if (REGNO (x
) == LR_REGNO
)
18122 fputs ("lr", file
);
18124 fputs ("ctr", file
);
18128 /* High-order 16 bits of constant for use in unsigned operand. */
18130 output_operand_lossage ("invalid %%u value");
18132 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
18133 (INTVAL (x
) >> 16) & 0xffff);
18137 /* High-order 16 bits of constant for use in signed operand. */
18139 output_operand_lossage ("invalid %%v value");
18141 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
18142 (INTVAL (x
) >> 16) & 0xffff);
18146 /* Print `u' if this has an auto-increment or auto-decrement. */
18148 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
18149 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
18150 || GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
))
18155 /* Print the trap code for this operand. */
18156 switch (GET_CODE (x
))
18159 fputs ("eq", file
); /* 4 */
18162 fputs ("ne", file
); /* 24 */
18165 fputs ("lt", file
); /* 16 */
18168 fputs ("le", file
); /* 20 */
18171 fputs ("gt", file
); /* 8 */
18174 fputs ("ge", file
); /* 12 */
18177 fputs ("llt", file
); /* 2 */
18180 fputs ("lle", file
); /* 6 */
18183 fputs ("lgt", file
); /* 1 */
18186 fputs ("lge", file
); /* 5 */
18189 gcc_unreachable ();
18194 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
18197 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
18198 ((INTVAL (x
) & 0xffff) ^ 0x8000) - 0x8000);
18200 print_operand (file
, x
, 0);
18204 /* MB value for a PowerPC64 rldic operand. */
18205 i
= clz_hwi (INTVAL (x
));
18207 fprintf (file
, "%d", i
);
18211 /* X is a FPR or Altivec register used in a VSX context. */
18212 if (GET_CODE (x
) != REG
|| !VSX_REGNO_P (REGNO (x
)))
18213 output_operand_lossage ("invalid %%x value");
18216 int reg
= REGNO (x
);
18217 int vsx_reg
= (FP_REGNO_P (reg
)
18219 : reg
- FIRST_ALTIVEC_REGNO
+ 32);
18221 #ifdef TARGET_REGNAMES
18222 if (TARGET_REGNAMES
)
18223 fprintf (file
, "%%vs%d", vsx_reg
);
18226 fprintf (file
, "%d", vsx_reg
);
18232 && (legitimate_indexed_address_p (XEXP (x
, 0), 0)
18233 || (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
18234 && legitimate_indexed_address_p (XEXP (XEXP (x
, 0), 1), 0))))
18239 /* Like 'L', for third word of TImode/PTImode */
18241 fputs (reg_names
[REGNO (x
) + 2], file
);
18242 else if (MEM_P (x
))
18244 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
18245 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
18246 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 8));
18247 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
18248 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 8));
18250 output_address (XEXP (adjust_address_nv (x
, SImode
, 8), 0));
18251 if (small_data_operand (x
, GET_MODE (x
)))
18252 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
18253 reg_names
[SMALL_DATA_REG
]);
18258 /* X is a SYMBOL_REF. Write out the name preceded by a
18259 period and without any trailing data in brackets. Used for function
18260 names. If we are configured for System V (or the embedded ABI) on
18261 the PowerPC, do not emit the period, since those systems do not use
18262 TOCs and the like. */
18263 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
18265 /* For macho, check to see if we need a stub. */
18268 const char *name
= XSTR (x
, 0);
18270 if (darwin_emit_branch_islands
18271 && MACHOPIC_INDIRECT
18272 && machopic_classify_symbol (x
) == MACHOPIC_UNDEFINED_FUNCTION
)
18273 name
= machopic_indirection_name (x
, /*stub_p=*/true);
18275 assemble_name (file
, name
);
18277 else if (!DOT_SYMBOLS
)
18278 assemble_name (file
, XSTR (x
, 0));
18280 rs6000_output_function_entry (file
, XSTR (x
, 0));
18284 /* Like 'L', for last word of TImode/PTImode. */
18286 fputs (reg_names
[REGNO (x
) + 3], file
);
18287 else if (MEM_P (x
))
18289 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
18290 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
18291 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 12));
18292 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
18293 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 12));
18295 output_address (XEXP (adjust_address_nv (x
, SImode
, 12), 0));
18296 if (small_data_operand (x
, GET_MODE (x
)))
18297 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
18298 reg_names
[SMALL_DATA_REG
]);
18302 /* Print AltiVec or SPE memory operand. */
18307 gcc_assert (MEM_P (x
));
18311 /* Ugly hack because %y is overloaded. */
18312 if ((TARGET_SPE
|| TARGET_E500_DOUBLE
)
18313 && (GET_MODE_SIZE (GET_MODE (x
)) == 8
18314 || GET_MODE (x
) == TFmode
18315 || GET_MODE (x
) == TImode
18316 || GET_MODE (x
) == PTImode
))
18318 /* Handle [reg]. */
18321 fprintf (file
, "0(%s)", reg_names
[REGNO (tmp
)]);
18324 /* Handle [reg+UIMM]. */
18325 else if (GET_CODE (tmp
) == PLUS
&&
18326 GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
18330 gcc_assert (REG_P (XEXP (tmp
, 0)));
18332 x
= INTVAL (XEXP (tmp
, 1));
18333 fprintf (file
, "%d(%s)", x
, reg_names
[REGNO (XEXP (tmp
, 0))]);
18337 /* Fall through. Must be [reg+reg]. */
18339 if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x
))
18340 && GET_CODE (tmp
) == AND
18341 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
18342 && INTVAL (XEXP (tmp
, 1)) == -16)
18343 tmp
= XEXP (tmp
, 0);
18344 else if (VECTOR_MEM_VSX_P (GET_MODE (x
))
18345 && GET_CODE (tmp
) == PRE_MODIFY
)
18346 tmp
= XEXP (tmp
, 1);
18348 fprintf (file
, "0,%s", reg_names
[REGNO (tmp
)]);
18351 if (!GET_CODE (tmp
) == PLUS
18352 || !REG_P (XEXP (tmp
, 0))
18353 || !REG_P (XEXP (tmp
, 1)))
18355 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
18359 if (REGNO (XEXP (tmp
, 0)) == 0)
18360 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 1)) ],
18361 reg_names
[ REGNO (XEXP (tmp
, 0)) ]);
18363 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 0)) ],
18364 reg_names
[ REGNO (XEXP (tmp
, 1)) ]);
18371 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
18372 else if (MEM_P (x
))
18374 /* We need to handle PRE_INC and PRE_DEC here, since we need to
18375 know the width from the mode. */
18376 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
18377 fprintf (file
, "%d(%s)", GET_MODE_SIZE (GET_MODE (x
)),
18378 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
18379 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
18380 fprintf (file
, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x
)),
18381 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
18382 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
18383 output_address (XEXP (XEXP (x
, 0), 1));
18385 output_address (XEXP (x
, 0));
18389 if (toc_relative_expr_p (x
, false))
18390 /* This hack along with a corresponding hack in
18391 rs6000_output_addr_const_extra arranges to output addends
18392 where the assembler expects to find them. eg.
18393 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
18394 without this hack would be output as "x@toc+4". We
18396 output_addr_const (file
, CONST_CAST_RTX (tocrel_base
));
18398 output_addr_const (file
, x
);
18403 assemble_name (file
, rs6000_get_some_local_dynamic_name ());
18407 output_operand_lossage ("invalid %%xn code");
18411 /* Print the address of an operand. */
18414 print_operand_address (FILE *file
, rtx x
)
18417 fprintf (file
, "0(%s)", reg_names
[ REGNO (x
) ]);
18418 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
18419 || GET_CODE (x
) == LABEL_REF
)
18421 output_addr_const (file
, x
);
18422 if (small_data_operand (x
, GET_MODE (x
)))
18423 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
18424 reg_names
[SMALL_DATA_REG
]);
18426 gcc_assert (!TARGET_TOC
);
18428 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
18429 && REG_P (XEXP (x
, 1)))
18431 if (REGNO (XEXP (x
, 0)) == 0)
18432 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 1)) ],
18433 reg_names
[ REGNO (XEXP (x
, 0)) ]);
18435 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 0)) ],
18436 reg_names
[ REGNO (XEXP (x
, 1)) ]);
18438 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
18439 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
18440 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"(%s)",
18441 INTVAL (XEXP (x
, 1)), reg_names
[ REGNO (XEXP (x
, 0)) ]);
18443 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
18444 && CONSTANT_P (XEXP (x
, 1)))
18446 fprintf (file
, "lo16(");
18447 output_addr_const (file
, XEXP (x
, 1));
18448 fprintf (file
, ")(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
18452 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
18453 && CONSTANT_P (XEXP (x
, 1)))
18455 output_addr_const (file
, XEXP (x
, 1));
18456 fprintf (file
, "@l(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
18459 else if (toc_relative_expr_p (x
, false))
18461 /* This hack along with a corresponding hack in
18462 rs6000_output_addr_const_extra arranges to output addends
18463 where the assembler expects to find them. eg.
18465 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
18466 without this hack would be output as "x@toc+8@l(9)". We
18467 want "x+8@toc@l(9)". */
18468 output_addr_const (file
, CONST_CAST_RTX (tocrel_base
));
18469 if (GET_CODE (x
) == LO_SUM
)
18470 fprintf (file
, "@l(%s)", reg_names
[REGNO (XEXP (x
, 0))]);
18472 fprintf (file
, "(%s)", reg_names
[REGNO (XVECEXP (tocrel_base
, 0, 1))]);
18475 gcc_unreachable ();
18478 /* Implement TARGET_OUTPUT_ADDR_CONST_EXTRA. */
18481 rs6000_output_addr_const_extra (FILE *file
, rtx x
)
18483 if (GET_CODE (x
) == UNSPEC
)
18484 switch (XINT (x
, 1))
18486 case UNSPEC_TOCREL
:
18487 gcc_checking_assert (GET_CODE (XVECEXP (x
, 0, 0)) == SYMBOL_REF
18488 && REG_P (XVECEXP (x
, 0, 1))
18489 && REGNO (XVECEXP (x
, 0, 1)) == TOC_REGISTER
);
18490 output_addr_const (file
, XVECEXP (x
, 0, 0));
18491 if (x
== tocrel_base
&& tocrel_offset
!= const0_rtx
)
18493 if (INTVAL (tocrel_offset
) >= 0)
18494 fprintf (file
, "+");
18495 output_addr_const (file
, CONST_CAST_RTX (tocrel_offset
));
18497 if (!TARGET_AIX
|| (TARGET_ELF
&& TARGET_MINIMAL_TOC
))
18500 assemble_name (file
, toc_label_name
);
18502 else if (TARGET_ELF
)
18503 fputs ("@toc", file
);
18507 case UNSPEC_MACHOPIC_OFFSET
:
18508 output_addr_const (file
, XVECEXP (x
, 0, 0));
18510 machopic_output_function_base_name (file
);
18517 /* Target hook for assembling integer objects. The PowerPC version has
18518 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
18519 is defined. It also needs to handle DI-mode objects on 64-bit
18523 rs6000_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
18525 #ifdef RELOCATABLE_NEEDS_FIXUP
18526 /* Special handling for SI values. */
18527 if (RELOCATABLE_NEEDS_FIXUP
&& size
== 4 && aligned_p
)
18529 static int recurse
= 0;
18531 /* For -mrelocatable, we mark all addresses that need to be fixed up in
18532 the .fixup section. Since the TOC section is already relocated, we
18533 don't need to mark it here. We used to skip the text section, but it
18534 should never be valid for relocated addresses to be placed in the text
18536 if (TARGET_RELOCATABLE
18537 && in_section
!= toc_section
18539 && !CONST_SCALAR_INT_P (x
)
18545 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", fixuplabelno
);
18547 ASM_OUTPUT_LABEL (asm_out_file
, buf
);
18548 fprintf (asm_out_file
, "\t.long\t(");
18549 output_addr_const (asm_out_file
, x
);
18550 fprintf (asm_out_file
, ")@fixup\n");
18551 fprintf (asm_out_file
, "\t.section\t\".fixup\",\"aw\"\n");
18552 ASM_OUTPUT_ALIGN (asm_out_file
, 2);
18553 fprintf (asm_out_file
, "\t.long\t");
18554 assemble_name (asm_out_file
, buf
);
18555 fprintf (asm_out_file
, "\n\t.previous\n");
18559 /* Remove initial .'s to turn a -mcall-aixdesc function
18560 address into the address of the descriptor, not the function
18562 else if (GET_CODE (x
) == SYMBOL_REF
18563 && XSTR (x
, 0)[0] == '.'
18564 && DEFAULT_ABI
== ABI_AIX
)
18566 const char *name
= XSTR (x
, 0);
18567 while (*name
== '.')
18570 fprintf (asm_out_file
, "\t.long\t%s\n", name
);
18574 #endif /* RELOCATABLE_NEEDS_FIXUP */
18575 return default_assemble_integer (x
, size
, aligned_p
);
18578 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
18579 /* Emit an assembler directive to set symbol visibility for DECL to
18580 VISIBILITY_TYPE. */
18583 rs6000_assemble_visibility (tree decl
, int vis
)
18588 /* Functions need to have their entry point symbol visibility set as
18589 well as their descriptor symbol visibility. */
18590 if (DEFAULT_ABI
== ABI_AIX
18592 && TREE_CODE (decl
) == FUNCTION_DECL
)
18594 static const char * const visibility_types
[] = {
18595 NULL
, "internal", "hidden", "protected"
18598 const char *name
, *type
;
18600 name
= ((* targetm
.strip_name_encoding
)
18601 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
))));
18602 type
= visibility_types
[vis
];
18604 fprintf (asm_out_file
, "\t.%s\t%s\n", type
, name
);
18605 fprintf (asm_out_file
, "\t.%s\t.%s\n", type
, name
);
18608 default_assemble_visibility (decl
, vis
);
18613 rs6000_reverse_condition (enum machine_mode mode
, enum rtx_code code
)
18615 /* Reversal of FP compares takes care -- an ordered compare
18616 becomes an unordered compare and vice versa. */
18617 if (mode
== CCFPmode
18618 && (!flag_finite_math_only
18619 || code
== UNLT
|| code
== UNLE
|| code
== UNGT
|| code
== UNGE
18620 || code
== UNEQ
|| code
== LTGT
))
18621 return reverse_condition_maybe_unordered (code
);
18623 return reverse_condition (code
);
18626 /* Generate a compare for CODE. Return a brand-new rtx that
18627 represents the result of the compare. */
18630 rs6000_generate_compare (rtx cmp
, enum machine_mode mode
)
18632 enum machine_mode comp_mode
;
18633 rtx compare_result
;
18634 enum rtx_code code
= GET_CODE (cmp
);
18635 rtx op0
= XEXP (cmp
, 0);
18636 rtx op1
= XEXP (cmp
, 1);
18638 if (FLOAT_MODE_P (mode
))
18639 comp_mode
= CCFPmode
;
18640 else if (code
== GTU
|| code
== LTU
18641 || code
== GEU
|| code
== LEU
)
18642 comp_mode
= CCUNSmode
;
18643 else if ((code
== EQ
|| code
== NE
)
18644 && unsigned_reg_p (op0
)
18645 && (unsigned_reg_p (op1
)
18646 || (CONST_INT_P (op1
) && INTVAL (op1
) != 0)))
18647 /* These are unsigned values, perhaps there will be a later
18648 ordering compare that can be shared with this one. */
18649 comp_mode
= CCUNSmode
;
18651 comp_mode
= CCmode
;
18653 /* If we have an unsigned compare, make sure we don't have a signed value as
18655 if (comp_mode
== CCUNSmode
&& GET_CODE (op1
) == CONST_INT
18656 && INTVAL (op1
) < 0)
18658 op0
= copy_rtx_if_shared (op0
);
18659 op1
= force_reg (GET_MODE (op0
), op1
);
18660 cmp
= gen_rtx_fmt_ee (code
, GET_MODE (cmp
), op0
, op1
);
18663 /* First, the compare. */
18664 compare_result
= gen_reg_rtx (comp_mode
);
18666 /* E500 FP compare instructions on the GPRs. Yuck! */
18667 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
)
18668 && FLOAT_MODE_P (mode
))
18670 rtx cmp
, or_result
, compare_result2
;
18671 enum machine_mode op_mode
= GET_MODE (op0
);
18674 if (op_mode
== VOIDmode
)
18675 op_mode
= GET_MODE (op1
);
18677 /* First reverse the condition codes that aren't directly supported. */
18685 code
= reverse_condition_maybe_unordered (code
);
18698 gcc_unreachable ();
18701 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
18702 This explains the following mess. */
18710 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18711 ? gen_tstsfeq_gpr (compare_result
, op0
, op1
)
18712 : gen_cmpsfeq_gpr (compare_result
, op0
, op1
);
18716 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18717 ? gen_tstdfeq_gpr (compare_result
, op0
, op1
)
18718 : gen_cmpdfeq_gpr (compare_result
, op0
, op1
);
18722 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18723 ? gen_tsttfeq_gpr (compare_result
, op0
, op1
)
18724 : gen_cmptfeq_gpr (compare_result
, op0
, op1
);
18728 gcc_unreachable ();
18737 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18738 ? gen_tstsfgt_gpr (compare_result
, op0
, op1
)
18739 : gen_cmpsfgt_gpr (compare_result
, op0
, op1
);
18743 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18744 ? gen_tstdfgt_gpr (compare_result
, op0
, op1
)
18745 : gen_cmpdfgt_gpr (compare_result
, op0
, op1
);
18749 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18750 ? gen_tsttfgt_gpr (compare_result
, op0
, op1
)
18751 : gen_cmptfgt_gpr (compare_result
, op0
, op1
);
18755 gcc_unreachable ();
18764 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18765 ? gen_tstsflt_gpr (compare_result
, op0
, op1
)
18766 : gen_cmpsflt_gpr (compare_result
, op0
, op1
);
18770 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18771 ? gen_tstdflt_gpr (compare_result
, op0
, op1
)
18772 : gen_cmpdflt_gpr (compare_result
, op0
, op1
);
18776 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18777 ? gen_tsttflt_gpr (compare_result
, op0
, op1
)
18778 : gen_cmptflt_gpr (compare_result
, op0
, op1
);
18782 gcc_unreachable ();
18787 gcc_unreachable ();
18790 /* Synthesize LE and GE from LT/GT || EQ. */
18791 if (code
== LE
|| code
== GE
)
18795 compare_result2
= gen_reg_rtx (CCFPmode
);
18801 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18802 ? gen_tstsfeq_gpr (compare_result2
, op0
, op1
)
18803 : gen_cmpsfeq_gpr (compare_result2
, op0
, op1
);
18807 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18808 ? gen_tstdfeq_gpr (compare_result2
, op0
, op1
)
18809 : gen_cmpdfeq_gpr (compare_result2
, op0
, op1
);
18813 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18814 ? gen_tsttfeq_gpr (compare_result2
, op0
, op1
)
18815 : gen_cmptfeq_gpr (compare_result2
, op0
, op1
);
18819 gcc_unreachable ();
18824 /* OR them together. */
18825 or_result
= gen_reg_rtx (CCFPmode
);
18826 cmp
= gen_e500_cr_ior_compare (or_result
, compare_result
,
18828 compare_result
= or_result
;
18831 code
= reverse_p
? NE
: EQ
;
18837 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
18838 CLOBBERs to match cmptf_internal2 pattern. */
18839 if (comp_mode
== CCFPmode
&& TARGET_XL_COMPAT
18840 && GET_MODE (op0
) == TFmode
18841 && !TARGET_IEEEQUAD
18842 && TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_LONG_DOUBLE_128
)
18843 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
18845 gen_rtx_SET (VOIDmode
,
18847 gen_rtx_COMPARE (comp_mode
, op0
, op1
)),
18848 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18849 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18850 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18851 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18852 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18853 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18854 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18855 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18856 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (Pmode
)))));
18857 else if (GET_CODE (op1
) == UNSPEC
18858 && XINT (op1
, 1) == UNSPEC_SP_TEST
)
18860 rtx op1b
= XVECEXP (op1
, 0, 0);
18861 comp_mode
= CCEQmode
;
18862 compare_result
= gen_reg_rtx (CCEQmode
);
18864 emit_insn (gen_stack_protect_testdi (compare_result
, op0
, op1b
));
18866 emit_insn (gen_stack_protect_testsi (compare_result
, op0
, op1b
));
18869 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
18870 gen_rtx_COMPARE (comp_mode
, op0
, op1
)));
18873 /* Some kinds of FP comparisons need an OR operation;
18874 under flag_finite_math_only we don't bother. */
18875 if (FLOAT_MODE_P (mode
)
18876 && !flag_finite_math_only
18877 && !(TARGET_HARD_FLOAT
&& !TARGET_FPRS
)
18878 && (code
== LE
|| code
== GE
18879 || code
== UNEQ
|| code
== LTGT
18880 || code
== UNGT
|| code
== UNLT
))
18882 enum rtx_code or1
, or2
;
18883 rtx or1_rtx
, or2_rtx
, compare2_rtx
;
18884 rtx or_result
= gen_reg_rtx (CCEQmode
);
18888 case LE
: or1
= LT
; or2
= EQ
; break;
18889 case GE
: or1
= GT
; or2
= EQ
; break;
18890 case UNEQ
: or1
= UNORDERED
; or2
= EQ
; break;
18891 case LTGT
: or1
= LT
; or2
= GT
; break;
18892 case UNGT
: or1
= UNORDERED
; or2
= GT
; break;
18893 case UNLT
: or1
= UNORDERED
; or2
= LT
; break;
18894 default: gcc_unreachable ();
18896 validate_condition_mode (or1
, comp_mode
);
18897 validate_condition_mode (or2
, comp_mode
);
18898 or1_rtx
= gen_rtx_fmt_ee (or1
, SImode
, compare_result
, const0_rtx
);
18899 or2_rtx
= gen_rtx_fmt_ee (or2
, SImode
, compare_result
, const0_rtx
);
18900 compare2_rtx
= gen_rtx_COMPARE (CCEQmode
,
18901 gen_rtx_IOR (SImode
, or1_rtx
, or2_rtx
),
18903 emit_insn (gen_rtx_SET (VOIDmode
, or_result
, compare2_rtx
));
18905 compare_result
= or_result
;
18909 validate_condition_mode (code
, GET_MODE (compare_result
));
18911 return gen_rtx_fmt_ee (code
, VOIDmode
, compare_result
, const0_rtx
);
18915 /* Emit the RTL for an sISEL pattern. */
18918 rs6000_emit_sISEL (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx operands
[])
18920 rs6000_emit_int_cmove (operands
[0], operands
[1], const1_rtx
, const0_rtx
);
18924 rs6000_emit_sCOND (enum machine_mode mode
, rtx operands
[])
18927 enum machine_mode op_mode
;
18928 enum rtx_code cond_code
;
18929 rtx result
= operands
[0];
18931 if (TARGET_ISEL
&& (mode
== SImode
|| mode
== DImode
))
18933 rs6000_emit_sISEL (mode
, operands
);
18937 condition_rtx
= rs6000_generate_compare (operands
[1], mode
);
18938 cond_code
= GET_CODE (condition_rtx
);
18940 if (FLOAT_MODE_P (mode
)
18941 && !TARGET_FPRS
&& TARGET_HARD_FLOAT
)
18945 PUT_MODE (condition_rtx
, SImode
);
18946 t
= XEXP (condition_rtx
, 0);
18948 gcc_assert (cond_code
== NE
|| cond_code
== EQ
);
18950 if (cond_code
== NE
)
18951 emit_insn (gen_e500_flip_gt_bit (t
, t
));
18953 emit_insn (gen_move_from_CR_gt_bit (result
, t
));
18957 if (cond_code
== NE
18958 || cond_code
== GE
|| cond_code
== LE
18959 || cond_code
== GEU
|| cond_code
== LEU
18960 || cond_code
== ORDERED
|| cond_code
== UNGE
|| cond_code
== UNLE
)
18962 rtx not_result
= gen_reg_rtx (CCEQmode
);
18963 rtx not_op
, rev_cond_rtx
;
18964 enum machine_mode cc_mode
;
18966 cc_mode
= GET_MODE (XEXP (condition_rtx
, 0));
18968 rev_cond_rtx
= gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode
, cond_code
),
18969 SImode
, XEXP (condition_rtx
, 0), const0_rtx
);
18970 not_op
= gen_rtx_COMPARE (CCEQmode
, rev_cond_rtx
, const0_rtx
);
18971 emit_insn (gen_rtx_SET (VOIDmode
, not_result
, not_op
));
18972 condition_rtx
= gen_rtx_EQ (VOIDmode
, not_result
, const0_rtx
);
18975 op_mode
= GET_MODE (XEXP (operands
[1], 0));
18976 if (op_mode
== VOIDmode
)
18977 op_mode
= GET_MODE (XEXP (operands
[1], 1));
18979 if (TARGET_POWERPC64
&& (op_mode
== DImode
|| FLOAT_MODE_P (mode
)))
18981 PUT_MODE (condition_rtx
, DImode
);
18982 convert_move (result
, condition_rtx
, 0);
18986 PUT_MODE (condition_rtx
, SImode
);
18987 emit_insn (gen_rtx_SET (VOIDmode
, result
, condition_rtx
));
18991 /* Emit a branch of kind CODE to location LOC. */
18994 rs6000_emit_cbranch (enum machine_mode mode
, rtx operands
[])
18996 rtx condition_rtx
, loc_ref
;
18998 condition_rtx
= rs6000_generate_compare (operands
[0], mode
);
18999 loc_ref
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
19000 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
19001 gen_rtx_IF_THEN_ELSE (VOIDmode
, condition_rtx
,
19002 loc_ref
, pc_rtx
)));
19005 /* Return the string to output a conditional branch to LABEL, which is
19006 the operand template of the label, or NULL if the branch is really a
19007 conditional return.
19009 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
19010 condition code register and its mode specifies what kind of
19011 comparison we made.
19013 REVERSED is nonzero if we should reverse the sense of the comparison.
19015 INSN is the insn. */
19018 output_cbranch (rtx op
, const char *label
, int reversed
, rtx insn
)
19020 static char string
[64];
19021 enum rtx_code code
= GET_CODE (op
);
19022 rtx cc_reg
= XEXP (op
, 0);
19023 enum machine_mode mode
= GET_MODE (cc_reg
);
19024 int cc_regno
= REGNO (cc_reg
) - CR0_REGNO
;
19025 int need_longbranch
= label
!= NULL
&& get_attr_length (insn
) == 8;
19026 int really_reversed
= reversed
^ need_longbranch
;
19032 validate_condition_mode (code
, mode
);
19034 /* Work out which way this really branches. We could use
19035 reverse_condition_maybe_unordered here always but this
19036 makes the resulting assembler clearer. */
19037 if (really_reversed
)
19039 /* Reversal of FP compares takes care -- an ordered compare
19040 becomes an unordered compare and vice versa. */
19041 if (mode
== CCFPmode
)
19042 code
= reverse_condition_maybe_unordered (code
);
19044 code
= reverse_condition (code
);
19047 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
) && mode
== CCFPmode
)
19049 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
19054 /* Opposite of GT. */
19063 gcc_unreachable ();
19069 /* Not all of these are actually distinct opcodes, but
19070 we distinguish them for clarity of the resulting assembler. */
19071 case NE
: case LTGT
:
19072 ccode
= "ne"; break;
19073 case EQ
: case UNEQ
:
19074 ccode
= "eq"; break;
19076 ccode
= "ge"; break;
19077 case GT
: case GTU
: case UNGT
:
19078 ccode
= "gt"; break;
19080 ccode
= "le"; break;
19081 case LT
: case LTU
: case UNLT
:
19082 ccode
= "lt"; break;
19083 case UNORDERED
: ccode
= "un"; break;
19084 case ORDERED
: ccode
= "nu"; break;
19085 case UNGE
: ccode
= "nl"; break;
19086 case UNLE
: ccode
= "ng"; break;
19088 gcc_unreachable ();
19091 /* Maybe we have a guess as to how likely the branch is. */
19093 note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
);
19094 if (note
!= NULL_RTX
)
19096 /* PROB is the difference from 50%. */
19097 int prob
= XINT (note
, 0) - REG_BR_PROB_BASE
/ 2;
19099 /* Only hint for highly probable/improbable branches on newer
19100 cpus as static prediction overrides processor dynamic
19101 prediction. For older cpus we may as well always hint, but
19102 assume not taken for branches that are very close to 50% as a
19103 mispredicted taken branch is more expensive than a
19104 mispredicted not-taken branch. */
19105 if (rs6000_always_hint
19106 || (abs (prob
) > REG_BR_PROB_BASE
/ 100 * 48
19107 && br_prob_note_reliable_p (note
)))
19109 if (abs (prob
) > REG_BR_PROB_BASE
/ 20
19110 && ((prob
> 0) ^ need_longbranch
))
19118 s
+= sprintf (s
, "b%slr%s ", ccode
, pred
);
19120 s
+= sprintf (s
, "b%s%s ", ccode
, pred
);
19122 /* We need to escape any '%' characters in the reg_names string.
19123 Assume they'd only be the first character.... */
19124 if (reg_names
[cc_regno
+ CR0_REGNO
][0] == '%')
19126 s
+= sprintf (s
, "%s", reg_names
[cc_regno
+ CR0_REGNO
]);
19130 /* If the branch distance was too far, we may have to use an
19131 unconditional branch to go the distance. */
19132 if (need_longbranch
)
19133 s
+= sprintf (s
, ",$+8\n\tb %s", label
);
19135 s
+= sprintf (s
, ",%s", label
);
19141 /* Return the string to flip the GT bit on a CR. */
19143 output_e500_flip_gt_bit (rtx dst
, rtx src
)
19145 static char string
[64];
19148 gcc_assert (GET_CODE (dst
) == REG
&& CR_REGNO_P (REGNO (dst
))
19149 && GET_CODE (src
) == REG
&& CR_REGNO_P (REGNO (src
)));
19152 a
= 4 * (REGNO (dst
) - CR0_REGNO
) + 1;
19153 b
= 4 * (REGNO (src
) - CR0_REGNO
) + 1;
19155 sprintf (string
, "crnot %d,%d", a
, b
);
19159 /* Return insn for VSX or Altivec comparisons. */
19162 rs6000_emit_vector_compare_inner (enum rtx_code code
, rtx op0
, rtx op1
)
19165 enum machine_mode mode
= GET_MODE (op0
);
19173 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
19183 mask
= gen_reg_rtx (mode
);
19184 emit_insn (gen_rtx_SET (VOIDmode
,
19186 gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
19193 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
19194 DMODE is expected destination mode. This is a recursive function. */
19197 rs6000_emit_vector_compare (enum rtx_code rcode
,
19199 enum machine_mode dmode
)
19202 bool swap_operands
= false;
19203 bool try_again
= false;
19205 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode
));
19206 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
19208 /* See if the comparison works as is. */
19209 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
19217 swap_operands
= true;
19222 swap_operands
= true;
19230 /* Invert condition and try again.
19231 e.g., A != B becomes ~(A==B). */
19233 enum rtx_code rev_code
;
19234 enum insn_code nor_code
;
19237 rev_code
= reverse_condition_maybe_unordered (rcode
);
19238 if (rev_code
== UNKNOWN
)
19241 nor_code
= optab_handler (one_cmpl_optab
, dmode
);
19242 if (nor_code
== CODE_FOR_nothing
)
19245 mask2
= rs6000_emit_vector_compare (rev_code
, op0
, op1
, dmode
);
19249 mask
= gen_reg_rtx (dmode
);
19250 emit_insn (GEN_FCN (nor_code
) (mask
, mask2
));
19258 /* Try GT/GTU/LT/LTU OR EQ */
19261 enum insn_code ior_code
;
19262 enum rtx_code new_code
;
19283 gcc_unreachable ();
19286 ior_code
= optab_handler (ior_optab
, dmode
);
19287 if (ior_code
== CODE_FOR_nothing
)
19290 c_rtx
= rs6000_emit_vector_compare (new_code
, op0
, op1
, dmode
);
19294 eq_rtx
= rs6000_emit_vector_compare (EQ
, op0
, op1
, dmode
);
19298 mask
= gen_reg_rtx (dmode
);
19299 emit_insn (GEN_FCN (ior_code
) (mask
, c_rtx
, eq_rtx
));
19317 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
19322 /* You only get two chances. */
19326 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
19327 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
19328 operands for the relation operation COND. */
19331 rs6000_emit_vector_cond_expr (rtx dest
, rtx op_true
, rtx op_false
,
19332 rtx cond
, rtx cc_op0
, rtx cc_op1
)
19334 enum machine_mode dest_mode
= GET_MODE (dest
);
19335 enum machine_mode mask_mode
= GET_MODE (cc_op0
);
19336 enum rtx_code rcode
= GET_CODE (cond
);
19337 enum machine_mode cc_mode
= CCmode
;
19341 bool invert_move
= false;
19343 if (VECTOR_UNIT_NONE_P (dest_mode
))
19346 gcc_assert (GET_MODE_SIZE (dest_mode
) == GET_MODE_SIZE (mask_mode
)
19347 && GET_MODE_NUNITS (dest_mode
) == GET_MODE_NUNITS (mask_mode
));
19351 /* Swap operands if we can, and fall back to doing the operation as
19352 specified, and doing a NOR to invert the test. */
19358 /* Invert condition and try again.
19359 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
19360 invert_move
= true;
19361 rcode
= reverse_condition_maybe_unordered (rcode
);
19362 if (rcode
== UNKNOWN
)
19366 /* Mark unsigned tests with CCUNSmode. */
19371 cc_mode
= CCUNSmode
;
19378 /* Get the vector mask for the given relational operations. */
19379 mask
= rs6000_emit_vector_compare (rcode
, cc_op0
, cc_op1
, mask_mode
);
19387 op_true
= op_false
;
19391 cond2
= gen_rtx_fmt_ee (NE
, cc_mode
, gen_lowpart (dest_mode
, mask
),
19392 CONST0_RTX (dest_mode
));
19393 emit_insn (gen_rtx_SET (VOIDmode
,
19395 gen_rtx_IF_THEN_ELSE (dest_mode
,
19402 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
19403 operands of the last comparison is nonzero/true, FALSE_COND if it
19404 is zero/false. Return 0 if the hardware has no such operation. */
19407 rs6000_emit_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
19409 enum rtx_code code
= GET_CODE (op
);
19410 rtx op0
= XEXP (op
, 0);
19411 rtx op1
= XEXP (op
, 1);
19412 REAL_VALUE_TYPE c1
;
19413 enum machine_mode compare_mode
= GET_MODE (op0
);
19414 enum machine_mode result_mode
= GET_MODE (dest
);
19416 bool is_against_zero
;
19418 /* These modes should always match. */
19419 if (GET_MODE (op1
) != compare_mode
19420 /* In the isel case however, we can use a compare immediate, so
19421 op1 may be a small constant. */
19422 && (!TARGET_ISEL
|| !short_cint_operand (op1
, VOIDmode
)))
19424 if (GET_MODE (true_cond
) != result_mode
)
19426 if (GET_MODE (false_cond
) != result_mode
)
19429 /* Don't allow using floating point comparisons for integer results for
19431 if (FLOAT_MODE_P (compare_mode
) && !FLOAT_MODE_P (result_mode
))
19434 /* First, work out if the hardware can do this at all, or
19435 if it's too slow.... */
19436 if (!FLOAT_MODE_P (compare_mode
))
19439 return rs6000_emit_int_cmove (dest
, op
, true_cond
, false_cond
);
19442 else if (TARGET_HARD_FLOAT
&& !TARGET_FPRS
19443 && SCALAR_FLOAT_MODE_P (compare_mode
))
19446 is_against_zero
= op1
== CONST0_RTX (compare_mode
);
19448 /* A floating-point subtract might overflow, underflow, or produce
19449 an inexact result, thus changing the floating-point flags, so it
19450 can't be generated if we care about that. It's safe if one side
19451 of the construct is zero, since then no subtract will be
19453 if (SCALAR_FLOAT_MODE_P (compare_mode
)
19454 && flag_trapping_math
&& ! is_against_zero
)
19457 /* Eliminate half of the comparisons by switching operands, this
19458 makes the remaining code simpler. */
19459 if (code
== UNLT
|| code
== UNGT
|| code
== UNORDERED
|| code
== NE
19460 || code
== LTGT
|| code
== LT
|| code
== UNLE
)
19462 code
= reverse_condition_maybe_unordered (code
);
19464 true_cond
= false_cond
;
19468 /* UNEQ and LTGT take four instructions for a comparison with zero,
19469 it'll probably be faster to use a branch here too. */
19470 if (code
== UNEQ
&& HONOR_NANS (compare_mode
))
19473 if (GET_CODE (op1
) == CONST_DOUBLE
)
19474 REAL_VALUE_FROM_CONST_DOUBLE (c1
, op1
);
19476 /* We're going to try to implement comparisons by performing
19477 a subtract, then comparing against zero. Unfortunately,
19478 Inf - Inf is NaN which is not zero, and so if we don't
19479 know that the operand is finite and the comparison
19480 would treat EQ different to UNORDERED, we can't do it. */
19481 if (HONOR_INFINITIES (compare_mode
)
19482 && code
!= GT
&& code
!= UNGE
19483 && (GET_CODE (op1
) != CONST_DOUBLE
|| real_isinf (&c1
))
19484 /* Constructs of the form (a OP b ? a : b) are safe. */
19485 && ((! rtx_equal_p (op0
, false_cond
) && ! rtx_equal_p (op1
, false_cond
))
19486 || (! rtx_equal_p (op0
, true_cond
)
19487 && ! rtx_equal_p (op1
, true_cond
))))
19490 /* At this point we know we can use fsel. */
19492 /* Reduce the comparison to a comparison against zero. */
19493 if (! is_against_zero
)
19495 temp
= gen_reg_rtx (compare_mode
);
19496 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
19497 gen_rtx_MINUS (compare_mode
, op0
, op1
)));
19499 op1
= CONST0_RTX (compare_mode
);
19502 /* If we don't care about NaNs we can reduce some of the comparisons
19503 down to faster ones. */
19504 if (! HONOR_NANS (compare_mode
))
19510 true_cond
= false_cond
;
19523 /* Now, reduce everything down to a GE. */
19530 temp
= gen_reg_rtx (compare_mode
);
19531 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
19536 temp
= gen_reg_rtx (compare_mode
);
19537 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_ABS (compare_mode
, op0
)));
19542 temp
= gen_reg_rtx (compare_mode
);
19543 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
19544 gen_rtx_NEG (compare_mode
,
19545 gen_rtx_ABS (compare_mode
, op0
))));
19550 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
19551 temp
= gen_reg_rtx (result_mode
);
19552 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
19553 gen_rtx_IF_THEN_ELSE (result_mode
,
19554 gen_rtx_GE (VOIDmode
,
19556 true_cond
, false_cond
)));
19557 false_cond
= true_cond
;
19560 temp
= gen_reg_rtx (compare_mode
);
19561 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
19566 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
19567 temp
= gen_reg_rtx (result_mode
);
19568 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
19569 gen_rtx_IF_THEN_ELSE (result_mode
,
19570 gen_rtx_GE (VOIDmode
,
19572 true_cond
, false_cond
)));
19573 true_cond
= false_cond
;
19576 temp
= gen_reg_rtx (compare_mode
);
19577 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
19582 gcc_unreachable ();
19585 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
19586 gen_rtx_IF_THEN_ELSE (result_mode
,
19587 gen_rtx_GE (VOIDmode
,
19589 true_cond
, false_cond
)));
19593 /* Same as above, but for ints (isel). */
19596 rs6000_emit_int_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
19598 rtx condition_rtx
, cr
;
19599 enum machine_mode mode
= GET_MODE (dest
);
19600 enum rtx_code cond_code
;
19601 rtx (*isel_func
) (rtx
, rtx
, rtx
, rtx
, rtx
);
19604 if (mode
!= SImode
&& (!TARGET_POWERPC64
|| mode
!= DImode
))
19607 /* We still have to do the compare, because isel doesn't do a
19608 compare, it just looks at the CRx bits set by a previous compare
19610 condition_rtx
= rs6000_generate_compare (op
, mode
);
19611 cond_code
= GET_CODE (condition_rtx
);
19612 cr
= XEXP (condition_rtx
, 0);
19613 signedp
= GET_MODE (cr
) == CCmode
;
19615 isel_func
= (mode
== SImode
19616 ? (signedp
? gen_isel_signed_si
: gen_isel_unsigned_si
)
19617 : (signedp
? gen_isel_signed_di
: gen_isel_unsigned_di
));
19621 case LT
: case GT
: case LTU
: case GTU
: case EQ
:
19622 /* isel handles these directly. */
19626 /* We need to swap the sense of the comparison. */
19629 true_cond
= false_cond
;
19631 PUT_CODE (condition_rtx
, reverse_condition (cond_code
));
19636 false_cond
= force_reg (mode
, false_cond
);
19637 if (true_cond
!= const0_rtx
)
19638 true_cond
= force_reg (mode
, true_cond
);
19640 emit_insn (isel_func (dest
, condition_rtx
, true_cond
, false_cond
, cr
));
19646 output_isel (rtx
*operands
)
19648 enum rtx_code code
;
19650 code
= GET_CODE (operands
[1]);
19652 if (code
== GE
|| code
== GEU
|| code
== LE
|| code
== LEU
|| code
== NE
)
19654 gcc_assert (GET_CODE (operands
[2]) == REG
19655 && GET_CODE (operands
[3]) == REG
);
19656 PUT_CODE (operands
[1], reverse_condition (code
));
19657 return "isel %0,%3,%2,%j1";
19660 return "isel %0,%2,%3,%j1";
19664 rs6000_emit_minmax (rtx dest
, enum rtx_code code
, rtx op0
, rtx op1
)
19666 enum machine_mode mode
= GET_MODE (op0
);
19670 /* VSX/altivec have direct min/max insns. */
19671 if ((code
== SMAX
|| code
== SMIN
)
19672 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
19673 || (mode
== SFmode
&& VECTOR_UNIT_VSX_P (DFmode
))))
19675 emit_insn (gen_rtx_SET (VOIDmode
,
19677 gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
19681 if (code
== SMAX
|| code
== SMIN
)
19686 if (code
== SMAX
|| code
== UMAX
)
19687 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
19688 op0
, op1
, mode
, 0);
19690 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
19691 op1
, op0
, mode
, 0);
19692 gcc_assert (target
);
19693 if (target
!= dest
)
19694 emit_move_insn (dest
, target
);
19697 /* A subroutine of the atomic operation splitters. Jump to LABEL if
19698 COND is true. Mark the jump as unlikely to be taken. */
19701 emit_unlikely_jump (rtx cond
, rtx label
)
19703 int very_unlikely
= REG_BR_PROB_BASE
/ 100 - 1;
19706 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, label
, pc_rtx
);
19707 x
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, x
));
19708 add_int_reg_note (x
, REG_BR_PROB
, very_unlikely
);
19711 /* A subroutine of the atomic operation splitters. Emit a load-locked
19712 instruction in MODE. For QI/HImode, possibly use a pattern than includes
19713 the zero_extend operation. */
19716 emit_load_locked (enum machine_mode mode
, rtx reg
, rtx mem
)
19718 rtx (*fn
) (rtx
, rtx
) = NULL
;
19723 fn
= gen_load_lockedqi
;
19726 fn
= gen_load_lockedhi
;
19729 if (GET_MODE (mem
) == QImode
)
19730 fn
= gen_load_lockedqi_si
;
19731 else if (GET_MODE (mem
) == HImode
)
19732 fn
= gen_load_lockedhi_si
;
19734 fn
= gen_load_lockedsi
;
19737 fn
= gen_load_lockeddi
;
19740 fn
= gen_load_lockedti
;
19743 gcc_unreachable ();
19745 emit_insn (fn (reg
, mem
));
19748 /* A subroutine of the atomic operation splitters. Emit a store-conditional
19749 instruction in MODE. */
19752 emit_store_conditional (enum machine_mode mode
, rtx res
, rtx mem
, rtx val
)
19754 rtx (*fn
) (rtx
, rtx
, rtx
) = NULL
;
19759 fn
= gen_store_conditionalqi
;
19762 fn
= gen_store_conditionalhi
;
19765 fn
= gen_store_conditionalsi
;
19768 fn
= gen_store_conditionaldi
;
19771 fn
= gen_store_conditionalti
;
19774 gcc_unreachable ();
19777 /* Emit sync before stwcx. to address PPC405 Erratum. */
19778 if (PPC405_ERRATUM77
)
19779 emit_insn (gen_hwsync ());
19781 emit_insn (fn (res
, mem
, val
));
19784 /* Expand barriers before and after a load_locked/store_cond sequence. */
19787 rs6000_pre_atomic_barrier (rtx mem
, enum memmodel model
)
19789 rtx addr
= XEXP (mem
, 0);
19790 int strict_p
= (reload_in_progress
|| reload_completed
);
19792 if (!legitimate_indirect_address_p (addr
, strict_p
)
19793 && !legitimate_indexed_address_p (addr
, strict_p
))
19795 addr
= force_reg (Pmode
, addr
);
19796 mem
= replace_equiv_address_nv (mem
, addr
);
19801 case MEMMODEL_RELAXED
:
19802 case MEMMODEL_CONSUME
:
19803 case MEMMODEL_ACQUIRE
:
19805 case MEMMODEL_RELEASE
:
19806 case MEMMODEL_ACQ_REL
:
19807 emit_insn (gen_lwsync ());
19809 case MEMMODEL_SEQ_CST
:
19810 emit_insn (gen_hwsync ());
19813 gcc_unreachable ();
19819 rs6000_post_atomic_barrier (enum memmodel model
)
19823 case MEMMODEL_RELAXED
:
19824 case MEMMODEL_CONSUME
:
19825 case MEMMODEL_RELEASE
:
19827 case MEMMODEL_ACQUIRE
:
19828 case MEMMODEL_ACQ_REL
:
19829 case MEMMODEL_SEQ_CST
:
19830 emit_insn (gen_isync ());
19833 gcc_unreachable ();
19837 /* A subroutine of the various atomic expanders. For sub-word operations,
19838 we must adjust things to operate on SImode. Given the original MEM,
19839 return a new aligned memory. Also build and return the quantities by
19840 which to shift and mask. */
19843 rs6000_adjust_atomic_subword (rtx orig_mem
, rtx
*pshift
, rtx
*pmask
)
19845 rtx addr
, align
, shift
, mask
, mem
;
19846 HOST_WIDE_INT shift_mask
;
19847 enum machine_mode mode
= GET_MODE (orig_mem
);
19849 /* For smaller modes, we have to implement this via SImode. */
19850 shift_mask
= (mode
== QImode
? 0x18 : 0x10);
19852 addr
= XEXP (orig_mem
, 0);
19853 addr
= force_reg (GET_MODE (addr
), addr
);
19855 /* Aligned memory containing subword. Generate a new memory. We
19856 do not want any of the existing MEM_ATTR data, as we're now
19857 accessing memory outside the original object. */
19858 align
= expand_simple_binop (Pmode
, AND
, addr
, GEN_INT (-4),
19859 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19860 mem
= gen_rtx_MEM (SImode
, align
);
19861 MEM_VOLATILE_P (mem
) = MEM_VOLATILE_P (orig_mem
);
19862 if (MEM_ALIAS_SET (orig_mem
) == ALIAS_SET_MEMORY_BARRIER
)
19863 set_mem_alias_set (mem
, ALIAS_SET_MEMORY_BARRIER
);
19865 /* Shift amount for subword relative to aligned word. */
19866 shift
= gen_reg_rtx (SImode
);
19867 addr
= gen_lowpart (SImode
, addr
);
19868 emit_insn (gen_rlwinm (shift
, addr
, GEN_INT (3), GEN_INT (shift_mask
)));
19869 if (WORDS_BIG_ENDIAN
)
19870 shift
= expand_simple_binop (SImode
, XOR
, shift
, GEN_INT (shift_mask
),
19871 shift
, 1, OPTAB_LIB_WIDEN
);
19874 /* Mask for insertion. */
19875 mask
= expand_simple_binop (SImode
, ASHIFT
, GEN_INT (GET_MODE_MASK (mode
)),
19876 shift
, NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19882 /* A subroutine of the various atomic expanders. For sub-word operands,
19883 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
19886 rs6000_mask_atomic_subword (rtx oldval
, rtx newval
, rtx mask
)
19890 x
= gen_reg_rtx (SImode
);
19891 emit_insn (gen_rtx_SET (VOIDmode
, x
,
19892 gen_rtx_AND (SImode
,
19893 gen_rtx_NOT (SImode
, mask
),
19896 x
= expand_simple_binop (SImode
, IOR
, newval
, x
, x
, 1, OPTAB_LIB_WIDEN
);
19901 /* A subroutine of the various atomic expanders. For sub-word operands,
19902 extract WIDE to NARROW via SHIFT. */
19905 rs6000_finish_atomic_subword (rtx narrow
, rtx wide
, rtx shift
)
19907 wide
= expand_simple_binop (SImode
, LSHIFTRT
, wide
, shift
,
19908 wide
, 1, OPTAB_LIB_WIDEN
);
19909 emit_move_insn (narrow
, gen_lowpart (GET_MODE (narrow
), wide
));
19912 /* Expand an atomic compare and swap operation. */
19915 rs6000_expand_atomic_compare_and_swap (rtx operands
[])
19917 rtx boolval
, retval
, mem
, oldval
, newval
, cond
;
19918 rtx label1
, label2
, x
, mask
, shift
;
19919 enum machine_mode mode
, orig_mode
;
19920 enum memmodel mod_s
, mod_f
;
19923 boolval
= operands
[0];
19924 retval
= operands
[1];
19926 oldval
= operands
[3];
19927 newval
= operands
[4];
19928 is_weak
= (INTVAL (operands
[5]) != 0);
19929 mod_s
= (enum memmodel
) INTVAL (operands
[6]);
19930 mod_f
= (enum memmodel
) INTVAL (operands
[7]);
19931 orig_mode
= mode
= GET_MODE (mem
);
19933 mask
= shift
= NULL_RTX
;
19934 if (mode
== QImode
|| mode
== HImode
)
19936 /* Before power8, we didn't have access to lbarx/lharx, so generate a
19937 lwarx and shift/mask operations. With power8, we need to do the
19938 comparison in SImode, but the store is still done in QI/HImode. */
19939 oldval
= convert_modes (SImode
, mode
, oldval
, 1);
19941 if (!TARGET_SYNC_HI_QI
)
19943 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
19945 /* Shift and mask OLDVAL into position with the word. */
19946 oldval
= expand_simple_binop (SImode
, ASHIFT
, oldval
, shift
,
19947 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19949 /* Shift and mask NEWVAL into position within the word. */
19950 newval
= convert_modes (SImode
, mode
, newval
, 1);
19951 newval
= expand_simple_binop (SImode
, ASHIFT
, newval
, shift
,
19952 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19955 /* Prepare to adjust the return value. */
19956 retval
= gen_reg_rtx (SImode
);
19959 else if (reg_overlap_mentioned_p (retval
, oldval
))
19960 oldval
= copy_to_reg (oldval
);
19962 mem
= rs6000_pre_atomic_barrier (mem
, mod_s
);
19967 label1
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
19968 emit_label (XEXP (label1
, 0));
19970 label2
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
19972 emit_load_locked (mode
, retval
, mem
);
19977 x
= expand_simple_binop (SImode
, AND
, retval
, mask
,
19978 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19981 cond
= gen_reg_rtx (CCmode
);
19982 /* If we have TImode, synthesize a comparison. */
19983 if (mode
!= TImode
)
19984 x
= gen_rtx_COMPARE (CCmode
, x
, oldval
);
19987 rtx xor1_result
= gen_reg_rtx (DImode
);
19988 rtx xor2_result
= gen_reg_rtx (DImode
);
19989 rtx or_result
= gen_reg_rtx (DImode
);
19990 rtx new_word0
= simplify_gen_subreg (DImode
, x
, TImode
, 0);
19991 rtx new_word1
= simplify_gen_subreg (DImode
, x
, TImode
, 8);
19992 rtx old_word0
= simplify_gen_subreg (DImode
, oldval
, TImode
, 0);
19993 rtx old_word1
= simplify_gen_subreg (DImode
, oldval
, TImode
, 8);
19995 emit_insn (gen_xordi3 (xor1_result
, new_word0
, old_word0
));
19996 emit_insn (gen_xordi3 (xor2_result
, new_word1
, old_word1
));
19997 emit_insn (gen_iordi3 (or_result
, xor1_result
, xor2_result
));
19998 x
= gen_rtx_COMPARE (CCmode
, or_result
, const0_rtx
);
20001 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
20003 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
20004 emit_unlikely_jump (x
, label2
);
20008 x
= rs6000_mask_atomic_subword (retval
, newval
, mask
);
20010 emit_store_conditional (orig_mode
, cond
, mem
, x
);
20014 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
20015 emit_unlikely_jump (x
, label1
);
20018 if (mod_f
!= MEMMODEL_RELAXED
)
20019 emit_label (XEXP (label2
, 0));
20021 rs6000_post_atomic_barrier (mod_s
);
20023 if (mod_f
== MEMMODEL_RELAXED
)
20024 emit_label (XEXP (label2
, 0));
20027 rs6000_finish_atomic_subword (operands
[1], retval
, shift
);
20028 else if (mode
!= GET_MODE (operands
[1]))
20029 convert_move (operands
[1], retval
, 1);
20031 /* In all cases, CR0 contains EQ on success, and NE on failure. */
20032 x
= gen_rtx_EQ (SImode
, cond
, const0_rtx
);
20033 emit_insn (gen_rtx_SET (VOIDmode
, boolval
, x
));
20036 /* Expand an atomic exchange operation. */
20039 rs6000_expand_atomic_exchange (rtx operands
[])
20041 rtx retval
, mem
, val
, cond
;
20042 enum machine_mode mode
;
20043 enum memmodel model
;
20044 rtx label
, x
, mask
, shift
;
20046 retval
= operands
[0];
20049 model
= (enum memmodel
) INTVAL (operands
[3]);
20050 mode
= GET_MODE (mem
);
20052 mask
= shift
= NULL_RTX
;
20053 if (!TARGET_SYNC_HI_QI
&& (mode
== QImode
|| mode
== HImode
))
20055 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
20057 /* Shift and mask VAL into position with the word. */
20058 val
= convert_modes (SImode
, mode
, val
, 1);
20059 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
20060 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
20062 /* Prepare to adjust the return value. */
20063 retval
= gen_reg_rtx (SImode
);
20067 mem
= rs6000_pre_atomic_barrier (mem
, model
);
20069 label
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
20070 emit_label (XEXP (label
, 0));
20072 emit_load_locked (mode
, retval
, mem
);
20076 x
= rs6000_mask_atomic_subword (retval
, val
, mask
);
20078 cond
= gen_reg_rtx (CCmode
);
20079 emit_store_conditional (mode
, cond
, mem
, x
);
20081 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
20082 emit_unlikely_jump (x
, label
);
20084 rs6000_post_atomic_barrier (model
);
20087 rs6000_finish_atomic_subword (operands
[0], retval
, shift
);
20090 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
20091 to perform. MEM is the memory on which to operate. VAL is the second
20092 operand of the binary operator. BEFORE and AFTER are optional locations to
20093 return the value of MEM either before of after the operation. MODEL_RTX
20094 is a CONST_INT containing the memory model to use. */
20097 rs6000_expand_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
20098 rtx orig_before
, rtx orig_after
, rtx model_rtx
)
20100 enum memmodel model
= (enum memmodel
) INTVAL (model_rtx
);
20101 enum machine_mode mode
= GET_MODE (mem
);
20102 enum machine_mode store_mode
= mode
;
20103 rtx label
, x
, cond
, mask
, shift
;
20104 rtx before
= orig_before
, after
= orig_after
;
20106 mask
= shift
= NULL_RTX
;
20107 /* On power8, we want to use SImode for the operation. On previous systems,
20108 use the operation in a subword and shift/mask to get the proper byte or
20110 if (mode
== QImode
|| mode
== HImode
)
20112 if (TARGET_SYNC_HI_QI
)
20114 val
= convert_modes (SImode
, mode
, val
, 1);
20116 /* Prepare to adjust the return value. */
20117 before
= gen_reg_rtx (SImode
);
20119 after
= gen_reg_rtx (SImode
);
20124 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
20126 /* Shift and mask VAL into position with the word. */
20127 val
= convert_modes (SImode
, mode
, val
, 1);
20128 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
20129 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
20135 /* We've already zero-extended VAL. That is sufficient to
20136 make certain that it does not affect other bits. */
20141 /* If we make certain that all of the other bits in VAL are
20142 set, that will be sufficient to not affect other bits. */
20143 x
= gen_rtx_NOT (SImode
, mask
);
20144 x
= gen_rtx_IOR (SImode
, x
, val
);
20145 emit_insn (gen_rtx_SET (VOIDmode
, val
, x
));
20152 /* These will all affect bits outside the field and need
20153 adjustment via MASK within the loop. */
20157 gcc_unreachable ();
20160 /* Prepare to adjust the return value. */
20161 before
= gen_reg_rtx (SImode
);
20163 after
= gen_reg_rtx (SImode
);
20164 store_mode
= mode
= SImode
;
20168 mem
= rs6000_pre_atomic_barrier (mem
, model
);
20170 label
= gen_label_rtx ();
20171 emit_label (label
);
20172 label
= gen_rtx_LABEL_REF (VOIDmode
, label
);
20174 if (before
== NULL_RTX
)
20175 before
= gen_reg_rtx (mode
);
20177 emit_load_locked (mode
, before
, mem
);
20181 x
= expand_simple_binop (mode
, AND
, before
, val
,
20182 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
20183 after
= expand_simple_unop (mode
, NOT
, x
, after
, 1);
20187 after
= expand_simple_binop (mode
, code
, before
, val
,
20188 after
, 1, OPTAB_LIB_WIDEN
);
20194 x
= expand_simple_binop (SImode
, AND
, after
, mask
,
20195 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
20196 x
= rs6000_mask_atomic_subword (before
, x
, mask
);
20198 else if (store_mode
!= mode
)
20199 x
= convert_modes (store_mode
, mode
, x
, 1);
20201 cond
= gen_reg_rtx (CCmode
);
20202 emit_store_conditional (store_mode
, cond
, mem
, x
);
20204 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
20205 emit_unlikely_jump (x
, label
);
20207 rs6000_post_atomic_barrier (model
);
20211 /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and
20212 then do the calcuations in a SImode register. */
20214 rs6000_finish_atomic_subword (orig_before
, before
, shift
);
20216 rs6000_finish_atomic_subword (orig_after
, after
, shift
);
20218 else if (store_mode
!= mode
)
20220 /* QImode/HImode on machines with lbarx/lharx where we do the native
20221 operation and then do the calcuations in a SImode register. */
20223 convert_move (orig_before
, before
, 1);
20225 convert_move (orig_after
, after
, 1);
20227 else if (orig_after
&& after
!= orig_after
)
20228 emit_move_insn (orig_after
, after
);
20231 /* Emit instructions to move SRC to DST. Called by splitters for
20232 multi-register moves. It will emit at most one instruction for
20233 each register that is accessed; that is, it won't emit li/lis pairs
20234 (or equivalent for 64-bit code). One of SRC or DST must be a hard
20238 rs6000_split_multireg_move (rtx dst
, rtx src
)
20240 /* The register number of the first register being moved. */
20242 /* The mode that is to be moved. */
20243 enum machine_mode mode
;
20244 /* The mode that the move is being done in, and its size. */
20245 enum machine_mode reg_mode
;
20247 /* The number of registers that will be moved. */
20250 reg
= REG_P (dst
) ? REGNO (dst
) : REGNO (src
);
20251 mode
= GET_MODE (dst
);
20252 nregs
= hard_regno_nregs
[reg
][mode
];
20253 if (FP_REGNO_P (reg
))
20254 reg_mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
:
20255 ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? DFmode
: SFmode
);
20256 else if (ALTIVEC_REGNO_P (reg
))
20257 reg_mode
= V16QImode
;
20258 else if (TARGET_E500_DOUBLE
&& mode
== TFmode
)
20261 reg_mode
= word_mode
;
20262 reg_mode_size
= GET_MODE_SIZE (reg_mode
);
20264 gcc_assert (reg_mode_size
* nregs
== GET_MODE_SIZE (mode
));
20266 /* TDmode residing in FP registers is special, since the ISA requires that
20267 the lower-numbered word of a register pair is always the most significant
20268 word, even in little-endian mode. This does not match the usual subreg
20269 semantics, so we cannnot use simplify_gen_subreg in those cases. Access
20270 the appropriate constituent registers "by hand" in little-endian mode.
20272 Note we do not need to check for destructive overlap here since TDmode
20273 can only reside in even/odd register pairs. */
20274 if (FP_REGNO_P (reg
) && DECIMAL_FLOAT_MODE_P (mode
) && !BYTES_BIG_ENDIAN
)
20279 for (i
= 0; i
< nregs
; i
++)
20281 if (REG_P (src
) && FP_REGNO_P (REGNO (src
)))
20282 p_src
= gen_rtx_REG (reg_mode
, REGNO (src
) + nregs
- 1 - i
);
20284 p_src
= simplify_gen_subreg (reg_mode
, src
, mode
,
20285 i
* reg_mode_size
);
20287 if (REG_P (dst
) && FP_REGNO_P (REGNO (dst
)))
20288 p_dst
= gen_rtx_REG (reg_mode
, REGNO (dst
) + nregs
- 1 - i
);
20290 p_dst
= simplify_gen_subreg (reg_mode
, dst
, mode
,
20291 i
* reg_mode_size
);
20293 emit_insn (gen_rtx_SET (VOIDmode
, p_dst
, p_src
));
20299 if (REG_P (src
) && REG_P (dst
) && (REGNO (src
) < REGNO (dst
)))
20301 /* Move register range backwards, if we might have destructive
20304 for (i
= nregs
- 1; i
>= 0; i
--)
20305 emit_insn (gen_rtx_SET (VOIDmode
,
20306 simplify_gen_subreg (reg_mode
, dst
, mode
,
20307 i
* reg_mode_size
),
20308 simplify_gen_subreg (reg_mode
, src
, mode
,
20309 i
* reg_mode_size
)));
20315 bool used_update
= false;
20316 rtx restore_basereg
= NULL_RTX
;
20318 if (MEM_P (src
) && INT_REGNO_P (reg
))
20322 if (GET_CODE (XEXP (src
, 0)) == PRE_INC
20323 || GET_CODE (XEXP (src
, 0)) == PRE_DEC
)
20326 breg
= XEXP (XEXP (src
, 0), 0);
20327 delta_rtx
= (GET_CODE (XEXP (src
, 0)) == PRE_INC
20328 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src
)))
20329 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src
))));
20330 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
20331 src
= replace_equiv_address (src
, breg
);
20333 else if (! rs6000_offsettable_memref_p (src
, reg_mode
))
20335 if (GET_CODE (XEXP (src
, 0)) == PRE_MODIFY
)
20337 rtx basereg
= XEXP (XEXP (src
, 0), 0);
20340 rtx ndst
= simplify_gen_subreg (reg_mode
, dst
, mode
, 0);
20341 emit_insn (gen_rtx_SET (VOIDmode
, ndst
,
20342 gen_rtx_MEM (reg_mode
, XEXP (src
, 0))));
20343 used_update
= true;
20346 emit_insn (gen_rtx_SET (VOIDmode
, basereg
,
20347 XEXP (XEXP (src
, 0), 1)));
20348 src
= replace_equiv_address (src
, basereg
);
20352 rtx basereg
= gen_rtx_REG (Pmode
, reg
);
20353 emit_insn (gen_rtx_SET (VOIDmode
, basereg
, XEXP (src
, 0)));
20354 src
= replace_equiv_address (src
, basereg
);
20358 breg
= XEXP (src
, 0);
20359 if (GET_CODE (breg
) == PLUS
|| GET_CODE (breg
) == LO_SUM
)
20360 breg
= XEXP (breg
, 0);
20362 /* If the base register we are using to address memory is
20363 also a destination reg, then change that register last. */
20365 && REGNO (breg
) >= REGNO (dst
)
20366 && REGNO (breg
) < REGNO (dst
) + nregs
)
20367 j
= REGNO (breg
) - REGNO (dst
);
20369 else if (MEM_P (dst
) && INT_REGNO_P (reg
))
20373 if (GET_CODE (XEXP (dst
, 0)) == PRE_INC
20374 || GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
20377 breg
= XEXP (XEXP (dst
, 0), 0);
20378 delta_rtx
= (GET_CODE (XEXP (dst
, 0)) == PRE_INC
20379 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst
)))
20380 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst
))));
20382 /* We have to update the breg before doing the store.
20383 Use store with update, if available. */
20387 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
20388 emit_insn (TARGET_32BIT
20389 ? (TARGET_POWERPC64
20390 ? gen_movdi_si_update (breg
, breg
, delta_rtx
, nsrc
)
20391 : gen_movsi_update (breg
, breg
, delta_rtx
, nsrc
))
20392 : gen_movdi_di_update (breg
, breg
, delta_rtx
, nsrc
));
20393 used_update
= true;
20396 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
20397 dst
= replace_equiv_address (dst
, breg
);
20399 else if (!rs6000_offsettable_memref_p (dst
, reg_mode
)
20400 && GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
20402 if (GET_CODE (XEXP (dst
, 0)) == PRE_MODIFY
)
20404 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
20407 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
20408 emit_insn (gen_rtx_SET (VOIDmode
,
20409 gen_rtx_MEM (reg_mode
, XEXP (dst
, 0)), nsrc
));
20410 used_update
= true;
20413 emit_insn (gen_rtx_SET (VOIDmode
, basereg
,
20414 XEXP (XEXP (dst
, 0), 1)));
20415 dst
= replace_equiv_address (dst
, basereg
);
20419 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
20420 rtx offsetreg
= XEXP (XEXP (dst
, 0), 1);
20421 gcc_assert (GET_CODE (XEXP (dst
, 0)) == PLUS
20423 && REG_P (offsetreg
)
20424 && REGNO (basereg
) != REGNO (offsetreg
));
20425 if (REGNO (basereg
) == 0)
20427 rtx tmp
= offsetreg
;
20428 offsetreg
= basereg
;
20431 emit_insn (gen_add3_insn (basereg
, basereg
, offsetreg
));
20432 restore_basereg
= gen_sub3_insn (basereg
, basereg
, offsetreg
);
20433 dst
= replace_equiv_address (dst
, basereg
);
20436 else if (GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
20437 gcc_assert (rs6000_offsettable_memref_p (dst
, reg_mode
));
20440 for (i
= 0; i
< nregs
; i
++)
20442 /* Calculate index to next subword. */
20447 /* If compiler already emitted move of first word by
20448 store with update, no need to do anything. */
20449 if (j
== 0 && used_update
)
20452 emit_insn (gen_rtx_SET (VOIDmode
,
20453 simplify_gen_subreg (reg_mode
, dst
, mode
,
20454 j
* reg_mode_size
),
20455 simplify_gen_subreg (reg_mode
, src
, mode
,
20456 j
* reg_mode_size
)));
20458 if (restore_basereg
!= NULL_RTX
)
20459 emit_insn (restore_basereg
);
20464 /* This page contains routines that are used to determine what the
20465 function prologue and epilogue code will do and write them out. */
20470 return !call_used_regs
[r
] && df_regs_ever_live_p (r
);
20473 /* Return the first fixed-point register that is required to be
20474 saved. 32 if none. */
20477 first_reg_to_save (void)
20481 /* Find lowest numbered live register. */
20482 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
20483 if (save_reg_p (first_reg
))
20486 if (first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
20487 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
20488 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
20489 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
))
20490 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
20491 first_reg
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
20495 && crtl
->uses_pic_offset_table
20496 && first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
20497 return RS6000_PIC_OFFSET_TABLE_REGNUM
;
20503 /* Similar, for FP regs. */
20506 first_fp_reg_to_save (void)
20510 /* Find lowest numbered live register. */
20511 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
20512 if (save_reg_p (first_reg
))
20518 /* Similar, for AltiVec regs. */
20521 first_altivec_reg_to_save (void)
20525 /* Stack frame remains as is unless we are in AltiVec ABI. */
20526 if (! TARGET_ALTIVEC_ABI
)
20527 return LAST_ALTIVEC_REGNO
+ 1;
20529 /* On Darwin, the unwind routines are compiled without
20530 TARGET_ALTIVEC, and use save_world to save/restore the
20531 altivec registers when necessary. */
20532 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
20533 && ! TARGET_ALTIVEC
)
20534 return FIRST_ALTIVEC_REGNO
+ 20;
20536 /* Find lowest numbered live register. */
20537 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
<= LAST_ALTIVEC_REGNO
; ++i
)
20538 if (save_reg_p (i
))
20544 /* Return a 32-bit mask of the AltiVec registers we need to set in
20545 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
20546 the 32-bit word is 0. */
20548 static unsigned int
20549 compute_vrsave_mask (void)
20551 unsigned int i
, mask
= 0;
20553 /* On Darwin, the unwind routines are compiled without
20554 TARGET_ALTIVEC, and use save_world to save/restore the
20555 call-saved altivec registers when necessary. */
20556 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
20557 && ! TARGET_ALTIVEC
)
20560 /* First, find out if we use _any_ altivec registers. */
20561 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
20562 if (df_regs_ever_live_p (i
))
20563 mask
|= ALTIVEC_REG_BIT (i
);
20568 /* Next, remove the argument registers from the set. These must
20569 be in the VRSAVE mask set by the caller, so we don't need to add
20570 them in again. More importantly, the mask we compute here is
20571 used to generate CLOBBERs in the set_vrsave insn, and we do not
20572 wish the argument registers to die. */
20573 for (i
= crtl
->args
.info
.vregno
- 1; i
>= ALTIVEC_ARG_MIN_REG
; --i
)
20574 mask
&= ~ALTIVEC_REG_BIT (i
);
20576 /* Similarly, remove the return value from the set. */
20579 diddle_return_value (is_altivec_return_reg
, &yes
);
20581 mask
&= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN
);
20587 /* For a very restricted set of circumstances, we can cut down the
20588 size of prologues/epilogues by calling our own save/restore-the-world
20592 compute_save_world_info (rs6000_stack_t
*info_ptr
)
20594 info_ptr
->world_save_p
= 1;
20595 info_ptr
->world_save_p
20596 = (WORLD_SAVE_P (info_ptr
)
20597 && DEFAULT_ABI
== ABI_DARWIN
20598 && !cfun
->has_nonlocal_label
20599 && info_ptr
->first_fp_reg_save
== FIRST_SAVED_FP_REGNO
20600 && info_ptr
->first_gp_reg_save
== FIRST_SAVED_GP_REGNO
20601 && info_ptr
->first_altivec_reg_save
== FIRST_SAVED_ALTIVEC_REGNO
20602 && info_ptr
->cr_save_p
);
20604 /* This will not work in conjunction with sibcalls. Make sure there
20605 are none. (This check is expensive, but seldom executed.) */
20606 if (WORLD_SAVE_P (info_ptr
))
20609 for (insn
= get_last_insn_anywhere (); insn
; insn
= PREV_INSN (insn
))
20610 if (CALL_P (insn
) && SIBLING_CALL_P (insn
))
20612 info_ptr
->world_save_p
= 0;
20617 if (WORLD_SAVE_P (info_ptr
))
20619 /* Even if we're not touching VRsave, make sure there's room on the
20620 stack for it, if it looks like we're calling SAVE_WORLD, which
20621 will attempt to save it. */
20622 info_ptr
->vrsave_size
= 4;
20624 /* If we are going to save the world, we need to save the link register too. */
20625 info_ptr
->lr_save_p
= 1;
20627 /* "Save" the VRsave register too if we're saving the world. */
20628 if (info_ptr
->vrsave_mask
== 0)
20629 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
20631 /* Because the Darwin register save/restore routines only handle
20632 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
20634 gcc_assert (info_ptr
->first_fp_reg_save
>= FIRST_SAVED_FP_REGNO
20635 && (info_ptr
->first_altivec_reg_save
20636 >= FIRST_SAVED_ALTIVEC_REGNO
));
20643 is_altivec_return_reg (rtx reg
, void *xyes
)
20645 bool *yes
= (bool *) xyes
;
20646 if (REGNO (reg
) == ALTIVEC_ARG_RETURN
)
20651 /* Look for user-defined global regs in the range FIRST to LAST-1.
20652 We should not restore these, and so cannot use lmw or out-of-line
20653 restore functions if there are any. We also can't save them
20654 (well, emit frame notes for them), because frame unwinding during
20655 exception handling will restore saved registers. */
20658 global_regs_p (unsigned first
, unsigned last
)
20660 while (first
< last
)
20661 if (global_regs
[first
++])
20666 /* Determine the strategy for savings/restoring registers. */
20669 SAVRES_MULTIPLE
= 0x1,
20670 SAVE_INLINE_FPRS
= 0x2,
20671 SAVE_INLINE_GPRS
= 0x4,
20672 REST_INLINE_FPRS
= 0x8,
20673 REST_INLINE_GPRS
= 0x10,
20674 SAVE_NOINLINE_GPRS_SAVES_LR
= 0x20,
20675 SAVE_NOINLINE_FPRS_SAVES_LR
= 0x40,
20676 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
= 0x80,
20677 SAVE_INLINE_VRS
= 0x100,
20678 REST_INLINE_VRS
= 0x200
20682 rs6000_savres_strategy (rs6000_stack_t
*info
,
20683 bool using_static_chain_p
)
20688 if (TARGET_MULTIPLE
20689 && !TARGET_POWERPC64
20690 && !(TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
)
20691 && info
->first_gp_reg_save
< 31
20692 && !global_regs_p (info
->first_gp_reg_save
, 32))
20693 strategy
|= SAVRES_MULTIPLE
;
20695 if (crtl
->calls_eh_return
20696 || cfun
->machine
->ra_need_lr
)
20697 strategy
|= (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
20698 | SAVE_INLINE_GPRS
| REST_INLINE_GPRS
20699 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
20701 if (info
->first_fp_reg_save
== 64
20702 /* The out-of-line FP routines use double-precision stores;
20703 we can't use those routines if we don't have such stores. */
20704 || (TARGET_HARD_FLOAT
&& !TARGET_DOUBLE_FLOAT
)
20705 || global_regs_p (info
->first_fp_reg_save
, 64))
20706 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
20708 if (info
->first_gp_reg_save
== 32
20709 || (!(strategy
& SAVRES_MULTIPLE
)
20710 && global_regs_p (info
->first_gp_reg_save
, 32)))
20711 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20713 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
20714 || global_regs_p (info
->first_altivec_reg_save
, LAST_ALTIVEC_REGNO
+ 1))
20715 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20717 /* Define cutoff for using out-of-line functions to save registers. */
20718 if (DEFAULT_ABI
== ABI_V4
|| TARGET_ELF
)
20720 if (!optimize_size
)
20722 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
20723 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20724 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20728 /* Prefer out-of-line restore if it will exit. */
20729 if (info
->first_fp_reg_save
> 61)
20730 strategy
|= SAVE_INLINE_FPRS
;
20731 if (info
->first_gp_reg_save
> 29)
20733 if (info
->first_fp_reg_save
== 64)
20734 strategy
|= SAVE_INLINE_GPRS
;
20736 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20738 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
)
20739 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20742 else if (DEFAULT_ABI
== ABI_DARWIN
)
20744 if (info
->first_fp_reg_save
> 60)
20745 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
20746 if (info
->first_gp_reg_save
> 29)
20747 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20748 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20752 gcc_checking_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
20753 if (info
->first_fp_reg_save
> 61)
20754 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
20755 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20756 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20759 /* Don't bother to try to save things out-of-line if r11 is occupied
20760 by the static chain. It would require too much fiddling and the
20761 static chain is rarely used anyway. FPRs are saved w.r.t the stack
20762 pointer on Darwin, and AIX uses r1 or r12. */
20763 if (using_static_chain_p
20764 && (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
))
20765 strategy
|= ((DEFAULT_ABI
== ABI_DARWIN
? 0 : SAVE_INLINE_FPRS
)
20767 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
20769 /* We can only use the out-of-line routines to restore if we've
20770 saved all the registers from first_fp_reg_save in the prologue.
20771 Otherwise, we risk loading garbage. */
20772 if ((strategy
& (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
)) == SAVE_INLINE_FPRS
)
20776 for (i
= info
->first_fp_reg_save
; i
< 64; i
++)
20777 if (!save_reg_p (i
))
20779 strategy
|= REST_INLINE_FPRS
;
20784 /* If we are going to use store multiple, then don't even bother
20785 with the out-of-line routines, since the store-multiple
20786 instruction will always be smaller. */
20787 if ((strategy
& SAVRES_MULTIPLE
))
20788 strategy
|= SAVE_INLINE_GPRS
;
20790 /* info->lr_save_p isn't yet set if the only reason lr needs to be
20791 saved is an out-of-line save or restore. Set up the value for
20792 the next test (excluding out-of-line gpr restore). */
20793 lr_save_p
= (info
->lr_save_p
20794 || !(strategy
& SAVE_INLINE_GPRS
)
20795 || !(strategy
& SAVE_INLINE_FPRS
)
20796 || !(strategy
& SAVE_INLINE_VRS
)
20797 || !(strategy
& REST_INLINE_FPRS
)
20798 || !(strategy
& REST_INLINE_VRS
));
20800 /* The situation is more complicated with load multiple. We'd
20801 prefer to use the out-of-line routines for restores, since the
20802 "exit" out-of-line routines can handle the restore of LR and the
20803 frame teardown. However if doesn't make sense to use the
20804 out-of-line routine if that is the only reason we'd need to save
20805 LR, and we can't use the "exit" out-of-line gpr restore if we
20806 have saved some fprs; In those cases it is advantageous to use
20807 load multiple when available. */
20808 if ((strategy
& SAVRES_MULTIPLE
)
20810 || info
->first_fp_reg_save
!= 64))
20811 strategy
|= REST_INLINE_GPRS
;
20813 /* Saving CR interferes with the exit routines used on the SPE, so
20816 && info
->spe_64bit_regs_used
20817 && info
->cr_save_p
)
20818 strategy
|= REST_INLINE_GPRS
;
20820 /* We can only use load multiple or the out-of-line routines to
20821 restore if we've used store multiple or out-of-line routines
20822 in the prologue, i.e. if we've saved all the registers from
20823 first_gp_reg_save. Otherwise, we risk loading garbage. */
20824 if ((strategy
& (SAVE_INLINE_GPRS
| REST_INLINE_GPRS
| SAVRES_MULTIPLE
))
20825 == SAVE_INLINE_GPRS
)
20829 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
20830 if (!save_reg_p (i
))
20832 strategy
|= REST_INLINE_GPRS
;
20837 if (TARGET_ELF
&& TARGET_64BIT
)
20839 if (!(strategy
& SAVE_INLINE_FPRS
))
20840 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
20841 else if (!(strategy
& SAVE_INLINE_GPRS
)
20842 && info
->first_fp_reg_save
== 64)
20843 strategy
|= SAVE_NOINLINE_GPRS_SAVES_LR
;
20845 else if (TARGET_AIX
&& !(strategy
& REST_INLINE_FPRS
))
20846 strategy
|= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
;
20848 if (TARGET_MACHO
&& !(strategy
& SAVE_INLINE_FPRS
))
20849 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
20854 /* Calculate the stack information for the current function. This is
20855 complicated by having two separate calling sequences, the AIX calling
20856 sequence and the V.4 calling sequence.
20858 AIX (and Darwin/Mac OS X) stack frames look like:
20860 SP----> +---------------------------------------+
20861 | back chain to caller | 0 0
20862 +---------------------------------------+
20863 | saved CR | 4 8 (8-11)
20864 +---------------------------------------+
20866 +---------------------------------------+
20867 | reserved for compilers | 12 24
20868 +---------------------------------------+
20869 | reserved for binders | 16 32
20870 +---------------------------------------+
20871 | saved TOC pointer | 20 40
20872 +---------------------------------------+
20873 | Parameter save area (P) | 24 48
20874 +---------------------------------------+
20875 | Alloca space (A) | 24+P etc.
20876 +---------------------------------------+
20877 | Local variable space (L) | 24+P+A
20878 +---------------------------------------+
20879 | Float/int conversion temporary (X) | 24+P+A+L
20880 +---------------------------------------+
20881 | Save area for AltiVec registers (W) | 24+P+A+L+X
20882 +---------------------------------------+
20883 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
20884 +---------------------------------------+
20885 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
20886 +---------------------------------------+
20887 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
20888 +---------------------------------------+
20889 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
20890 +---------------------------------------+
20891 old SP->| back chain to caller's caller |
20892 +---------------------------------------+
20894 The required alignment for AIX configurations is two words (i.e., 8
20897 The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:
20899 SP----> +---------------------------------------+
20900 | Back chain to caller | 0
20901 +---------------------------------------+
20902 | Save area for CR | 8
20903 +---------------------------------------+
20905 +---------------------------------------+
20906 | Saved TOC pointer | 24
20907 +---------------------------------------+
20908 | Parameter save area (P) | 32
20909 +---------------------------------------+
20910 | Alloca space (A) | 32+P
20911 +---------------------------------------+
20912 | Local variable space (L) | 32+P+A
20913 +---------------------------------------+
20914 | Save area for AltiVec registers (W) | 32+P+A+L
20915 +---------------------------------------+
20916 | AltiVec alignment padding (Y) | 32+P+A+L+W
20917 +---------------------------------------+
20918 | Save area for GP registers (G) | 32+P+A+L+W+Y
20919 +---------------------------------------+
20920 | Save area for FP registers (F) | 32+P+A+L+W+Y+G
20921 +---------------------------------------+
20922 old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F
20923 +---------------------------------------+
20926 V.4 stack frames look like:
20928 SP----> +---------------------------------------+
20929 | back chain to caller | 0
20930 +---------------------------------------+
20931 | caller's saved LR | 4
20932 +---------------------------------------+
20933 | Parameter save area (P) | 8
20934 +---------------------------------------+
20935 | Alloca space (A) | 8+P
20936 +---------------------------------------+
20937 | Varargs save area (V) | 8+P+A
20938 +---------------------------------------+
20939 | Local variable space (L) | 8+P+A+V
20940 +---------------------------------------+
20941 | Float/int conversion temporary (X) | 8+P+A+V+L
20942 +---------------------------------------+
20943 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
20944 +---------------------------------------+
20945 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
20946 +---------------------------------------+
20947 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
20948 +---------------------------------------+
20949 | SPE: area for 64-bit GP registers |
20950 +---------------------------------------+
20951 | SPE alignment padding |
20952 +---------------------------------------+
20953 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
20954 +---------------------------------------+
20955 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
20956 +---------------------------------------+
20957 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
20958 +---------------------------------------+
20959 old SP->| back chain to caller's caller |
20960 +---------------------------------------+
20962 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
20963 given. (But note below and in sysv4.h that we require only 8 and
20964 may round up the size of our stack frame anyways. The historical
20965 reason is early versions of powerpc-linux which didn't properly
20966 align the stack at program startup. A happy side-effect is that
20967 -mno-eabi libraries can be used with -meabi programs.)
20969 The EABI configuration defaults to the V.4 layout. However,
20970 the stack alignment requirements may differ. If -mno-eabi is not
20971 given, the required stack alignment is 8 bytes; if -mno-eabi is
20972 given, the required alignment is 16 bytes. (But see V.4 comment
20975 #ifndef ABI_STACK_BOUNDARY
20976 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
20979 static rs6000_stack_t
*
20980 rs6000_stack_info (void)
20982 rs6000_stack_t
*info_ptr
= &stack_info
;
20983 int reg_size
= TARGET_32BIT
? 4 : 8;
20988 HOST_WIDE_INT non_fixed_size
;
20989 bool using_static_chain_p
;
20991 if (reload_completed
&& info_ptr
->reload_completed
)
20994 memset (info_ptr
, 0, sizeof (*info_ptr
));
20995 info_ptr
->reload_completed
= reload_completed
;
20999 /* Cache value so we don't rescan instruction chain over and over. */
21000 if (cfun
->machine
->insn_chain_scanned_p
== 0)
21001 cfun
->machine
->insn_chain_scanned_p
21002 = spe_func_has_64bit_regs_p () + 1;
21003 info_ptr
->spe_64bit_regs_used
= cfun
->machine
->insn_chain_scanned_p
- 1;
21006 /* Select which calling sequence. */
21007 info_ptr
->abi
= DEFAULT_ABI
;
21009 /* Calculate which registers need to be saved & save area size. */
21010 info_ptr
->first_gp_reg_save
= first_reg_to_save ();
21011 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
21012 even if it currently looks like we won't. Reload may need it to
21013 get at a constant; if so, it will have already created a constant
21014 pool entry for it. */
21015 if (((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
21016 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
21017 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
21018 && crtl
->uses_const_pool
21019 && info_ptr
->first_gp_reg_save
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
21020 first_gp
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
21022 first_gp
= info_ptr
->first_gp_reg_save
;
21024 info_ptr
->gp_size
= reg_size
* (32 - first_gp
);
21026 /* For the SPE, we have an additional upper 32-bits on each GPR.
21027 Ideally we should save the entire 64-bits only when the upper
21028 half is used in SIMD instructions. Since we only record
21029 registers live (not the size they are used in), this proves
21030 difficult because we'd have to traverse the instruction chain at
21031 the right time, taking reload into account. This is a real pain,
21032 so we opt to save the GPRs in 64-bits always if but one register
21033 gets used in 64-bits. Otherwise, all the registers in the frame
21034 get saved in 32-bits.
21036 So... since when we save all GPRs (except the SP) in 64-bits, the
21037 traditional GP save area will be empty. */
21038 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
21039 info_ptr
->gp_size
= 0;
21041 info_ptr
->first_fp_reg_save
= first_fp_reg_to_save ();
21042 info_ptr
->fp_size
= 8 * (64 - info_ptr
->first_fp_reg_save
);
21044 info_ptr
->first_altivec_reg_save
= first_altivec_reg_to_save ();
21045 info_ptr
->altivec_size
= 16 * (LAST_ALTIVEC_REGNO
+ 1
21046 - info_ptr
->first_altivec_reg_save
);
21048 /* Does this function call anything? */
21049 info_ptr
->calls_p
= (! crtl
->is_leaf
21050 || cfun
->machine
->ra_needs_full_frame
);
21052 /* Determine if we need to save the condition code registers. */
21053 if (df_regs_ever_live_p (CR2_REGNO
)
21054 || df_regs_ever_live_p (CR3_REGNO
)
21055 || df_regs_ever_live_p (CR4_REGNO
))
21057 info_ptr
->cr_save_p
= 1;
21058 if (DEFAULT_ABI
== ABI_V4
)
21059 info_ptr
->cr_size
= reg_size
;
21062 /* If the current function calls __builtin_eh_return, then we need
21063 to allocate stack space for registers that will hold data for
21064 the exception handler. */
21065 if (crtl
->calls_eh_return
)
21068 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
21071 /* SPE saves EH registers in 64-bits. */
21072 ehrd_size
= i
* (TARGET_SPE_ABI
21073 && info_ptr
->spe_64bit_regs_used
!= 0
21074 ? UNITS_PER_SPE_WORD
: UNITS_PER_WORD
);
21079 /* In the ELFv2 ABI, we also need to allocate space for separate
21080 CR field save areas if the function calls __builtin_eh_return. */
21081 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
21083 /* This hard-codes that we have three call-saved CR fields. */
21084 ehcr_size
= 3 * reg_size
;
21085 /* We do *not* use the regular CR save mechanism. */
21086 info_ptr
->cr_save_p
= 0;
21091 /* Determine various sizes. */
21092 info_ptr
->reg_size
= reg_size
;
21093 info_ptr
->fixed_size
= RS6000_SAVE_AREA
;
21094 info_ptr
->vars_size
= RS6000_ALIGN (get_frame_size (), 8);
21095 info_ptr
->parm_size
= RS6000_ALIGN (crtl
->outgoing_args_size
,
21096 TARGET_ALTIVEC
? 16 : 8);
21097 if (FRAME_GROWS_DOWNWARD
)
21098 info_ptr
->vars_size
21099 += RS6000_ALIGN (info_ptr
->fixed_size
+ info_ptr
->vars_size
21100 + info_ptr
->parm_size
,
21101 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
)
21102 - (info_ptr
->fixed_size
+ info_ptr
->vars_size
21103 + info_ptr
->parm_size
);
21105 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
21106 info_ptr
->spe_gp_size
= 8 * (32 - first_gp
);
21108 info_ptr
->spe_gp_size
= 0;
21110 if (TARGET_ALTIVEC_ABI
)
21111 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
21113 info_ptr
->vrsave_mask
= 0;
21115 if (TARGET_ALTIVEC_VRSAVE
&& info_ptr
->vrsave_mask
)
21116 info_ptr
->vrsave_size
= 4;
21118 info_ptr
->vrsave_size
= 0;
21120 compute_save_world_info (info_ptr
);
21122 /* Calculate the offsets. */
21123 switch (DEFAULT_ABI
)
21127 gcc_unreachable ();
21132 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
21133 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
21135 if (TARGET_ALTIVEC_ABI
)
21137 info_ptr
->vrsave_save_offset
21138 = info_ptr
->gp_save_offset
- info_ptr
->vrsave_size
;
21140 /* Align stack so vector save area is on a quadword boundary.
21141 The padding goes above the vectors. */
21142 if (info_ptr
->altivec_size
!= 0)
21143 info_ptr
->altivec_padding_size
21144 = info_ptr
->vrsave_save_offset
& 0xF;
21146 info_ptr
->altivec_padding_size
= 0;
21148 info_ptr
->altivec_save_offset
21149 = info_ptr
->vrsave_save_offset
21150 - info_ptr
->altivec_padding_size
21151 - info_ptr
->altivec_size
;
21152 gcc_assert (info_ptr
->altivec_size
== 0
21153 || info_ptr
->altivec_save_offset
% 16 == 0);
21155 /* Adjust for AltiVec case. */
21156 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
- ehrd_size
;
21159 info_ptr
->ehrd_offset
= info_ptr
->gp_save_offset
- ehrd_size
;
21161 info_ptr
->ehcr_offset
= info_ptr
->ehrd_offset
- ehcr_size
;
21162 info_ptr
->cr_save_offset
= reg_size
; /* first word when 64-bit. */
21163 info_ptr
->lr_save_offset
= 2*reg_size
;
21167 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
21168 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
21169 info_ptr
->cr_save_offset
= info_ptr
->gp_save_offset
- info_ptr
->cr_size
;
21171 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
21173 /* Align stack so SPE GPR save area is aligned on a
21174 double-word boundary. */
21175 if (info_ptr
->spe_gp_size
!= 0 && info_ptr
->cr_save_offset
!= 0)
21176 info_ptr
->spe_padding_size
21177 = 8 - (-info_ptr
->cr_save_offset
% 8);
21179 info_ptr
->spe_padding_size
= 0;
21181 info_ptr
->spe_gp_save_offset
21182 = info_ptr
->cr_save_offset
21183 - info_ptr
->spe_padding_size
21184 - info_ptr
->spe_gp_size
;
21186 /* Adjust for SPE case. */
21187 info_ptr
->ehrd_offset
= info_ptr
->spe_gp_save_offset
;
21189 else if (TARGET_ALTIVEC_ABI
)
21191 info_ptr
->vrsave_save_offset
21192 = info_ptr
->cr_save_offset
- info_ptr
->vrsave_size
;
21194 /* Align stack so vector save area is on a quadword boundary. */
21195 if (info_ptr
->altivec_size
!= 0)
21196 info_ptr
->altivec_padding_size
21197 = 16 - (-info_ptr
->vrsave_save_offset
% 16);
21199 info_ptr
->altivec_padding_size
= 0;
21201 info_ptr
->altivec_save_offset
21202 = info_ptr
->vrsave_save_offset
21203 - info_ptr
->altivec_padding_size
21204 - info_ptr
->altivec_size
;
21206 /* Adjust for AltiVec case. */
21207 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
;
21210 info_ptr
->ehrd_offset
= info_ptr
->cr_save_offset
;
21211 info_ptr
->ehrd_offset
-= ehrd_size
;
21212 info_ptr
->lr_save_offset
= reg_size
;
21216 save_align
= (TARGET_ALTIVEC_ABI
|| DEFAULT_ABI
== ABI_DARWIN
) ? 16 : 8;
21217 info_ptr
->save_size
= RS6000_ALIGN (info_ptr
->fp_size
21218 + info_ptr
->gp_size
21219 + info_ptr
->altivec_size
21220 + info_ptr
->altivec_padding_size
21221 + info_ptr
->spe_gp_size
21222 + info_ptr
->spe_padding_size
21225 + info_ptr
->cr_size
21226 + info_ptr
->vrsave_size
,
21229 non_fixed_size
= (info_ptr
->vars_size
21230 + info_ptr
->parm_size
21231 + info_ptr
->save_size
);
21233 info_ptr
->total_size
= RS6000_ALIGN (non_fixed_size
+ info_ptr
->fixed_size
,
21234 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
);
21236 /* Determine if we need to save the link register. */
21237 if (info_ptr
->calls_p
21238 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
21240 && !TARGET_PROFILE_KERNEL
)
21241 || (DEFAULT_ABI
== ABI_V4
&& cfun
->calls_alloca
)
21242 #ifdef TARGET_RELOCATABLE
21243 || (TARGET_RELOCATABLE
&& (get_pool_size () != 0))
21245 || rs6000_ra_ever_killed ())
21246 info_ptr
->lr_save_p
= 1;
21248 using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
21249 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
21250 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
21251 info_ptr
->savres_strategy
= rs6000_savres_strategy (info_ptr
,
21252 using_static_chain_p
);
21254 if (!(info_ptr
->savres_strategy
& SAVE_INLINE_GPRS
)
21255 || !(info_ptr
->savres_strategy
& SAVE_INLINE_FPRS
)
21256 || !(info_ptr
->savres_strategy
& SAVE_INLINE_VRS
)
21257 || !(info_ptr
->savres_strategy
& REST_INLINE_GPRS
)
21258 || !(info_ptr
->savres_strategy
& REST_INLINE_FPRS
)
21259 || !(info_ptr
->savres_strategy
& REST_INLINE_VRS
))
21260 info_ptr
->lr_save_p
= 1;
21262 if (info_ptr
->lr_save_p
)
21263 df_set_regs_ever_live (LR_REGNO
, true);
21265 /* Determine if we need to allocate any stack frame:
21267 For AIX we need to push the stack if a frame pointer is needed
21268 (because the stack might be dynamically adjusted), if we are
21269 debugging, if we make calls, or if the sum of fp_save, gp_save,
21270 and local variables are more than the space needed to save all
21271 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
21272 + 18*8 = 288 (GPR13 reserved).
21274 For V.4 we don't have the stack cushion that AIX uses, but assume
21275 that the debugger can handle stackless frames. */
21277 if (info_ptr
->calls_p
)
21278 info_ptr
->push_p
= 1;
21280 else if (DEFAULT_ABI
== ABI_V4
)
21281 info_ptr
->push_p
= non_fixed_size
!= 0;
21283 else if (frame_pointer_needed
)
21284 info_ptr
->push_p
= 1;
21286 else if (TARGET_XCOFF
&& write_symbols
!= NO_DEBUG
)
21287 info_ptr
->push_p
= 1;
21290 info_ptr
->push_p
= non_fixed_size
> (TARGET_32BIT
? 220 : 288);
21292 /* Zero offsets if we're not saving those registers. */
21293 if (info_ptr
->fp_size
== 0)
21294 info_ptr
->fp_save_offset
= 0;
21296 if (info_ptr
->gp_size
== 0)
21297 info_ptr
->gp_save_offset
= 0;
21299 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->altivec_size
== 0)
21300 info_ptr
->altivec_save_offset
= 0;
21302 /* Zero VRSAVE offset if not saved and restored. */
21303 if (! TARGET_ALTIVEC_VRSAVE
|| info_ptr
->vrsave_mask
== 0)
21304 info_ptr
->vrsave_save_offset
= 0;
21306 if (! TARGET_SPE_ABI
21307 || info_ptr
->spe_64bit_regs_used
== 0
21308 || info_ptr
->spe_gp_size
== 0)
21309 info_ptr
->spe_gp_save_offset
= 0;
21311 if (! info_ptr
->lr_save_p
)
21312 info_ptr
->lr_save_offset
= 0;
21314 if (! info_ptr
->cr_save_p
)
21315 info_ptr
->cr_save_offset
= 0;
21320 /* Return true if the current function uses any GPRs in 64-bit SIMD
21324 spe_func_has_64bit_regs_p (void)
21328 /* Functions that save and restore all the call-saved registers will
21329 need to save/restore the registers in 64-bits. */
21330 if (crtl
->calls_eh_return
21331 || cfun
->calls_setjmp
21332 || crtl
->has_nonlocal_goto
)
21335 insns
= get_insns ();
21337 for (insn
= NEXT_INSN (insns
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
21343 /* FIXME: This should be implemented with attributes...
21345 (set_attr "spe64" "true")....then,
21346 if (get_spe64(insn)) return true;
21348 It's the only reliable way to do the stuff below. */
21350 i
= PATTERN (insn
);
21351 if (GET_CODE (i
) == SET
)
21353 enum machine_mode mode
= GET_MODE (SET_SRC (i
));
21355 if (SPE_VECTOR_MODE (mode
))
21357 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
))
21367 debug_stack_info (rs6000_stack_t
*info
)
21369 const char *abi_string
;
21372 info
= rs6000_stack_info ();
21374 fprintf (stderr
, "\nStack information for function %s:\n",
21375 ((current_function_decl
&& DECL_NAME (current_function_decl
))
21376 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
21381 default: abi_string
= "Unknown"; break;
21382 case ABI_NONE
: abi_string
= "NONE"; break;
21383 case ABI_AIX
: abi_string
= "AIX"; break;
21384 case ABI_ELFv2
: abi_string
= "ELFv2"; break;
21385 case ABI_DARWIN
: abi_string
= "Darwin"; break;
21386 case ABI_V4
: abi_string
= "V.4"; break;
21389 fprintf (stderr
, "\tABI = %5s\n", abi_string
);
21391 if (TARGET_ALTIVEC_ABI
)
21392 fprintf (stderr
, "\tALTIVEC ABI extensions enabled.\n");
21394 if (TARGET_SPE_ABI
)
21395 fprintf (stderr
, "\tSPE ABI extensions enabled.\n");
21397 if (info
->first_gp_reg_save
!= 32)
21398 fprintf (stderr
, "\tfirst_gp_reg_save = %5d\n", info
->first_gp_reg_save
);
21400 if (info
->first_fp_reg_save
!= 64)
21401 fprintf (stderr
, "\tfirst_fp_reg_save = %5d\n", info
->first_fp_reg_save
);
21403 if (info
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
)
21404 fprintf (stderr
, "\tfirst_altivec_reg_save = %5d\n",
21405 info
->first_altivec_reg_save
);
21407 if (info
->lr_save_p
)
21408 fprintf (stderr
, "\tlr_save_p = %5d\n", info
->lr_save_p
);
21410 if (info
->cr_save_p
)
21411 fprintf (stderr
, "\tcr_save_p = %5d\n", info
->cr_save_p
);
21413 if (info
->vrsave_mask
)
21414 fprintf (stderr
, "\tvrsave_mask = 0x%x\n", info
->vrsave_mask
);
21417 fprintf (stderr
, "\tpush_p = %5d\n", info
->push_p
);
21420 fprintf (stderr
, "\tcalls_p = %5d\n", info
->calls_p
);
21422 if (info
->gp_save_offset
)
21423 fprintf (stderr
, "\tgp_save_offset = %5d\n", info
->gp_save_offset
);
21425 if (info
->fp_save_offset
)
21426 fprintf (stderr
, "\tfp_save_offset = %5d\n", info
->fp_save_offset
);
21428 if (info
->altivec_save_offset
)
21429 fprintf (stderr
, "\taltivec_save_offset = %5d\n",
21430 info
->altivec_save_offset
);
21432 if (info
->spe_gp_save_offset
)
21433 fprintf (stderr
, "\tspe_gp_save_offset = %5d\n",
21434 info
->spe_gp_save_offset
);
21436 if (info
->vrsave_save_offset
)
21437 fprintf (stderr
, "\tvrsave_save_offset = %5d\n",
21438 info
->vrsave_save_offset
);
21440 if (info
->lr_save_offset
)
21441 fprintf (stderr
, "\tlr_save_offset = %5d\n", info
->lr_save_offset
);
21443 if (info
->cr_save_offset
)
21444 fprintf (stderr
, "\tcr_save_offset = %5d\n", info
->cr_save_offset
);
21446 if (info
->varargs_save_offset
)
21447 fprintf (stderr
, "\tvarargs_save_offset = %5d\n", info
->varargs_save_offset
);
21449 if (info
->total_size
)
21450 fprintf (stderr
, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
21453 if (info
->vars_size
)
21454 fprintf (stderr
, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
21457 if (info
->parm_size
)
21458 fprintf (stderr
, "\tparm_size = %5d\n", info
->parm_size
);
21460 if (info
->fixed_size
)
21461 fprintf (stderr
, "\tfixed_size = %5d\n", info
->fixed_size
);
21464 fprintf (stderr
, "\tgp_size = %5d\n", info
->gp_size
);
21466 if (info
->spe_gp_size
)
21467 fprintf (stderr
, "\tspe_gp_size = %5d\n", info
->spe_gp_size
);
21470 fprintf (stderr
, "\tfp_size = %5d\n", info
->fp_size
);
21472 if (info
->altivec_size
)
21473 fprintf (stderr
, "\taltivec_size = %5d\n", info
->altivec_size
);
21475 if (info
->vrsave_size
)
21476 fprintf (stderr
, "\tvrsave_size = %5d\n", info
->vrsave_size
);
21478 if (info
->altivec_padding_size
)
21479 fprintf (stderr
, "\taltivec_padding_size= %5d\n",
21480 info
->altivec_padding_size
);
21482 if (info
->spe_padding_size
)
21483 fprintf (stderr
, "\tspe_padding_size = %5d\n",
21484 info
->spe_padding_size
);
21487 fprintf (stderr
, "\tcr_size = %5d\n", info
->cr_size
);
21489 if (info
->save_size
)
21490 fprintf (stderr
, "\tsave_size = %5d\n", info
->save_size
);
21492 if (info
->reg_size
!= 4)
21493 fprintf (stderr
, "\treg_size = %5d\n", info
->reg_size
);
21495 fprintf (stderr
, "\tsave-strategy = %04x\n", info
->savres_strategy
);
21497 fprintf (stderr
, "\n");
21501 rs6000_return_addr (int count
, rtx frame
)
21503 /* Currently we don't optimize very well between prolog and body
21504 code and for PIC code the code can be actually quite bad, so
21505 don't try to be too clever here. */
21507 || ((DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
) && flag_pic
))
21509 cfun
->machine
->ra_needs_full_frame
= 1;
21516 plus_constant (Pmode
,
21518 (gen_rtx_MEM (Pmode
,
21519 memory_address (Pmode
, frame
))),
21520 RETURN_ADDRESS_OFFSET
)));
21523 cfun
->machine
->ra_need_lr
= 1;
21524 return get_hard_reg_initial_val (Pmode
, LR_REGNO
);
21527 /* Say whether a function is a candidate for sibcall handling or not. */
21530 rs6000_function_ok_for_sibcall (tree decl
, tree exp
)
21535 fntype
= TREE_TYPE (decl
);
21537 fntype
= TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp
)));
21539 /* We can't do it if the called function has more vector parameters
21540 than the current function; there's nowhere to put the VRsave code. */
21541 if (TARGET_ALTIVEC_ABI
21542 && TARGET_ALTIVEC_VRSAVE
21543 && !(decl
&& decl
== current_function_decl
))
21545 function_args_iterator args_iter
;
21549 /* Functions with vector parameters are required to have a
21550 prototype, so the argument type info must be available
21552 FOREACH_FUNCTION_ARGS(fntype
, type
, args_iter
)
21553 if (TREE_CODE (type
) == VECTOR_TYPE
21554 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
21557 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl
), type
, args_iter
)
21558 if (TREE_CODE (type
) == VECTOR_TYPE
21559 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
21566 /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local
21567 functions, because the callee may have a different TOC pointer to
21568 the caller and there's no way to ensure we restore the TOC when
21569 we return. With the secure-plt SYSV ABI we can't make non-local
21570 calls when -fpic/PIC because the plt call stubs use r30. */
21571 if (DEFAULT_ABI
== ABI_DARWIN
21572 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
21574 && !DECL_EXTERNAL (decl
)
21575 && (*targetm
.binds_local_p
) (decl
))
21576 || (DEFAULT_ABI
== ABI_V4
21577 && (!TARGET_SECURE_PLT
21580 && (*targetm
.binds_local_p
) (decl
)))))
21582 tree attr_list
= TYPE_ATTRIBUTES (fntype
);
21584 if (!lookup_attribute ("longcall", attr_list
)
21585 || lookup_attribute ("shortcall", attr_list
))
21593 rs6000_ra_ever_killed (void)
21599 if (cfun
->is_thunk
)
21602 if (cfun
->machine
->lr_save_state
)
21603 return cfun
->machine
->lr_save_state
- 1;
21605 /* regs_ever_live has LR marked as used if any sibcalls are present,
21606 but this should not force saving and restoring in the
21607 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
21608 clobbers LR, so that is inappropriate. */
21610 /* Also, the prologue can generate a store into LR that
21611 doesn't really count, like this:
21614 bcl to set PIC register
21618 When we're called from the epilogue, we need to avoid counting
21619 this as a store. */
21621 push_topmost_sequence ();
21622 top
= get_insns ();
21623 pop_topmost_sequence ();
21624 reg
= gen_rtx_REG (Pmode
, LR_REGNO
);
21626 for (insn
= NEXT_INSN (top
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
21632 if (!SIBLING_CALL_P (insn
))
21635 else if (find_regno_note (insn
, REG_INC
, LR_REGNO
))
21637 else if (set_of (reg
, insn
) != NULL_RTX
21638 && !prologue_epilogue_contains (insn
))
21645 /* Emit instructions needed to load the TOC register.
21646 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
21647 a constant pool; or for SVR4 -fpic. */
21650 rs6000_emit_load_toc_table (int fromprolog
)
21653 dest
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
21655 if (TARGET_ELF
&& TARGET_SECURE_PLT
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
)
21658 rtx lab
, tmp1
, tmp2
, got
;
21660 lab
= gen_label_rtx ();
21661 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (lab
));
21662 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
21664 got
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
21666 got
= rs6000_got_sym ();
21667 tmp1
= tmp2
= dest
;
21670 tmp1
= gen_reg_rtx (Pmode
);
21671 tmp2
= gen_reg_rtx (Pmode
);
21673 emit_insn (gen_load_toc_v4_PIC_1 (lab
));
21674 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
21675 emit_insn (gen_load_toc_v4_PIC_3b (tmp2
, tmp1
, got
, lab
));
21676 emit_insn (gen_load_toc_v4_PIC_3c (dest
, tmp2
, got
, lab
));
21678 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
21680 emit_insn (gen_load_toc_v4_pic_si ());
21681 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
21683 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 2)
21686 rtx temp0
= (fromprolog
21687 ? gen_rtx_REG (Pmode
, 0)
21688 : gen_reg_rtx (Pmode
));
21694 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
21695 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
21697 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
21698 symL
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
21700 emit_insn (gen_load_toc_v4_PIC_1 (symF
));
21701 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
21702 emit_insn (gen_load_toc_v4_PIC_2 (temp0
, dest
, symL
, symF
));
21708 tocsym
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
21709 lab
= gen_label_rtx ();
21710 emit_insn (gen_load_toc_v4_PIC_1b (tocsym
, lab
));
21711 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
21712 if (TARGET_LINK_STACK
)
21713 emit_insn (gen_addsi3 (dest
, dest
, GEN_INT (4)));
21714 emit_move_insn (temp0
, gen_rtx_MEM (Pmode
, dest
));
21716 emit_insn (gen_addsi3 (dest
, temp0
, dest
));
21718 else if (TARGET_ELF
&& !TARGET_AIX
&& flag_pic
== 0 && TARGET_MINIMAL_TOC
)
21720 /* This is for AIX code running in non-PIC ELF32. */
21723 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
21724 realsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
21726 emit_insn (gen_elf_high (dest
, realsym
));
21727 emit_insn (gen_elf_low (dest
, dest
, realsym
));
21731 gcc_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
21734 emit_insn (gen_load_toc_aix_si (dest
));
21736 emit_insn (gen_load_toc_aix_di (dest
));
21740 /* Emit instructions to restore the link register after determining where
21741 its value has been stored. */
21744 rs6000_emit_eh_reg_restore (rtx source
, rtx scratch
)
21746 rs6000_stack_t
*info
= rs6000_stack_info ();
21749 operands
[0] = source
;
21750 operands
[1] = scratch
;
21752 if (info
->lr_save_p
)
21754 rtx frame_rtx
= stack_pointer_rtx
;
21755 HOST_WIDE_INT sp_offset
= 0;
21758 if (frame_pointer_needed
21759 || cfun
->calls_alloca
21760 || info
->total_size
> 32767)
21762 tmp
= gen_frame_mem (Pmode
, frame_rtx
);
21763 emit_move_insn (operands
[1], tmp
);
21764 frame_rtx
= operands
[1];
21766 else if (info
->push_p
)
21767 sp_offset
= info
->total_size
;
21769 tmp
= plus_constant (Pmode
, frame_rtx
,
21770 info
->lr_save_offset
+ sp_offset
);
21771 tmp
= gen_frame_mem (Pmode
, tmp
);
21772 emit_move_insn (tmp
, operands
[0]);
21775 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
), operands
[0]);
21777 /* Freeze lr_save_p. We've just emitted rtl that depends on the
21778 state of lr_save_p so any change from here on would be a bug. In
21779 particular, stop rs6000_ra_ever_killed from considering the SET
21780 of lr we may have added just above. */
21781 cfun
->machine
->lr_save_state
= info
->lr_save_p
+ 1;
21784 static GTY(()) alias_set_type set
= -1;
21787 get_TOC_alias_set (void)
21790 set
= new_alias_set ();
21794 /* This returns nonzero if the current function uses the TOC. This is
21795 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
21796 is generated by the ABI_V4 load_toc_* patterns. */
21803 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
21806 rtx pat
= PATTERN (insn
);
21809 if (GET_CODE (pat
) == PARALLEL
)
21810 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
21812 rtx sub
= XVECEXP (pat
, 0, i
);
21813 if (GET_CODE (sub
) == USE
)
21815 sub
= XEXP (sub
, 0);
21816 if (GET_CODE (sub
) == UNSPEC
21817 && XINT (sub
, 1) == UNSPEC_TOC
)
21827 create_TOC_reference (rtx symbol
, rtx largetoc_reg
)
21829 rtx tocrel
, tocreg
, hi
;
21831 if (TARGET_DEBUG_ADDR
)
21833 if (GET_CODE (symbol
) == SYMBOL_REF
)
21834 fprintf (stderr
, "\ncreate_TOC_reference, (symbol_ref %s)\n",
21838 fprintf (stderr
, "\ncreate_TOC_reference, code %s:\n",
21839 GET_RTX_NAME (GET_CODE (symbol
)));
21840 debug_rtx (symbol
);
21844 if (!can_create_pseudo_p ())
21845 df_set_regs_ever_live (TOC_REGISTER
, true);
21847 tocreg
= gen_rtx_REG (Pmode
, TOC_REGISTER
);
21848 tocrel
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, symbol
, tocreg
), UNSPEC_TOCREL
);
21849 if (TARGET_CMODEL
== CMODEL_SMALL
|| can_create_pseudo_p ())
21852 hi
= gen_rtx_HIGH (Pmode
, copy_rtx (tocrel
));
21853 if (largetoc_reg
!= NULL
)
21855 emit_move_insn (largetoc_reg
, hi
);
21858 return gen_rtx_LO_SUM (Pmode
, hi
, tocrel
);
21861 /* Issue assembly directives that create a reference to the given DWARF
21862 FRAME_TABLE_LABEL from the current function section. */
21864 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label
)
21866 fprintf (asm_out_file
, "\t.ref %s\n",
21867 (* targetm
.strip_name_encoding
) (frame_table_label
));
21870 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
21871 and the change to the stack pointer. */
21874 rs6000_emit_stack_tie (rtx fp
, bool hard_frame_needed
)
21881 regs
[i
++] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
21882 if (hard_frame_needed
)
21883 regs
[i
++] = gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
);
21884 if (!(REGNO (fp
) == STACK_POINTER_REGNUM
21885 || (hard_frame_needed
21886 && REGNO (fp
) == HARD_FRAME_POINTER_REGNUM
)))
21889 p
= rtvec_alloc (i
);
21892 rtx mem
= gen_frame_mem (BLKmode
, regs
[i
]);
21893 RTVEC_ELT (p
, i
) = gen_rtx_SET (VOIDmode
, mem
, const0_rtx
);
21896 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode
, p
)));
21899 /* Emit the correct code for allocating stack space, as insns.
21900 If COPY_REG, make sure a copy of the old frame is left there.
21901 The generated code may use hard register 0 as a temporary. */
21904 rs6000_emit_allocate_stack (HOST_WIDE_INT size
, rtx copy_reg
, int copy_off
)
21907 rtx stack_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
21908 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
21909 rtx todec
= gen_int_mode (-size
, Pmode
);
21912 if (INTVAL (todec
) != -size
)
21914 warning (0, "stack frame too large");
21915 emit_insn (gen_trap ());
21919 if (crtl
->limit_stack
)
21921 if (REG_P (stack_limit_rtx
)
21922 && REGNO (stack_limit_rtx
) > 1
21923 && REGNO (stack_limit_rtx
) <= 31)
21925 emit_insn (gen_add3_insn (tmp_reg
, stack_limit_rtx
, GEN_INT (size
)));
21926 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
21929 else if (GET_CODE (stack_limit_rtx
) == SYMBOL_REF
21931 && DEFAULT_ABI
== ABI_V4
)
21933 rtx toload
= gen_rtx_CONST (VOIDmode
,
21934 gen_rtx_PLUS (Pmode
,
21938 emit_insn (gen_elf_high (tmp_reg
, toload
));
21939 emit_insn (gen_elf_low (tmp_reg
, tmp_reg
, toload
));
21940 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
21944 warning (0, "stack limit expression is not supported");
21950 emit_insn (gen_add3_insn (copy_reg
, stack_reg
, GEN_INT (copy_off
)));
21952 emit_move_insn (copy_reg
, stack_reg
);
21957 /* Need a note here so that try_split doesn't get confused. */
21958 if (get_last_insn () == NULL_RTX
)
21959 emit_note (NOTE_INSN_DELETED
);
21960 insn
= emit_move_insn (tmp_reg
, todec
);
21961 try_split (PATTERN (insn
), insn
, 0);
21965 insn
= emit_insn (TARGET_32BIT
21966 ? gen_movsi_update_stack (stack_reg
, stack_reg
,
21968 : gen_movdi_di_update_stack (stack_reg
, stack_reg
,
21969 todec
, stack_reg
));
21970 /* Since we didn't use gen_frame_mem to generate the MEM, grab
21971 it now and set the alias set/attributes. The above gen_*_update
21972 calls will generate a PARALLEL with the MEM set being the first
21974 par
= PATTERN (insn
);
21975 gcc_assert (GET_CODE (par
) == PARALLEL
);
21976 set
= XVECEXP (par
, 0, 0);
21977 gcc_assert (GET_CODE (set
) == SET
);
21978 mem
= SET_DEST (set
);
21979 gcc_assert (MEM_P (mem
));
21980 MEM_NOTRAP_P (mem
) = 1;
21981 set_mem_alias_set (mem
, get_frame_alias_set ());
21983 RTX_FRAME_RELATED_P (insn
) = 1;
21984 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
21985 gen_rtx_SET (VOIDmode
, stack_reg
,
21986 gen_rtx_PLUS (Pmode
, stack_reg
,
21987 GEN_INT (-size
))));
21990 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
21992 #if PROBE_INTERVAL > 32768
21993 #error Cannot use indexed addressing mode for stack probing
21996 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
21997 inclusive. These are offsets from the current stack pointer. */
22000 rs6000_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
22002 /* See if we have a constant small number of probes to generate. If so,
22003 that's the easy case. */
22004 if (first
+ size
<= 32768)
22008 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
22009 it exceeds SIZE. If only one probe is needed, this will not
22010 generate any code. Then probe at FIRST + SIZE. */
22011 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
22012 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
22015 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
22019 /* Otherwise, do the same as above, but in a loop. Note that we must be
22020 extra careful with variables wrapping around because we might be at
22021 the very top (or the very bottom) of the address space and we have
22022 to be able to handle this case properly; in particular, we use an
22023 equality test for the loop condition. */
22026 HOST_WIDE_INT rounded_size
;
22027 rtx r12
= gen_rtx_REG (Pmode
, 12);
22028 rtx r0
= gen_rtx_REG (Pmode
, 0);
22030 /* Sanity check for the addressing mode we're going to use. */
22031 gcc_assert (first
<= 32768);
22033 /* Step 1: round SIZE to the previous multiple of the interval. */
22035 rounded_size
= size
& -PROBE_INTERVAL
;
22038 /* Step 2: compute initial and final value of the loop counter. */
22040 /* TEST_ADDR = SP + FIRST. */
22041 emit_insn (gen_rtx_SET (VOIDmode
, r12
,
22042 plus_constant (Pmode
, stack_pointer_rtx
,
22045 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
22046 if (rounded_size
> 32768)
22048 emit_move_insn (r0
, GEN_INT (-rounded_size
));
22049 emit_insn (gen_rtx_SET (VOIDmode
, r0
,
22050 gen_rtx_PLUS (Pmode
, r12
, r0
)));
22053 emit_insn (gen_rtx_SET (VOIDmode
, r0
,
22054 plus_constant (Pmode
, r12
, -rounded_size
)));
22057 /* Step 3: the loop
22059 while (TEST_ADDR != LAST_ADDR)
22061 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
22065 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
22066 until it is equal to ROUNDED_SIZE. */
22069 emit_insn (gen_probe_stack_rangedi (r12
, r12
, r0
));
22071 emit_insn (gen_probe_stack_rangesi (r12
, r12
, r0
));
22074 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
22075 that SIZE is equal to ROUNDED_SIZE. */
22077 if (size
!= rounded_size
)
22078 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
22082 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
22083 absolute addresses. */
22086 output_probe_stack_range (rtx reg1
, rtx reg2
)
22088 static int labelno
= 0;
22089 char loop_lab
[32], end_lab
[32];
22092 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
22093 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
22095 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
22097 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
22101 output_asm_insn ("cmpd 0,%0,%1", xops
);
22103 output_asm_insn ("cmpw 0,%0,%1", xops
);
22105 fputs ("\tbeq 0,", asm_out_file
);
22106 assemble_name_raw (asm_out_file
, end_lab
);
22107 fputc ('\n', asm_out_file
);
22109 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
22110 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
22111 output_asm_insn ("addi %0,%0,%1", xops
);
22113 /* Probe at TEST_ADDR and branch. */
22114 xops
[1] = gen_rtx_REG (Pmode
, 0);
22115 output_asm_insn ("stw %1,0(%0)", xops
);
22116 fprintf (asm_out_file
, "\tb ");
22117 assemble_name_raw (asm_out_file
, loop_lab
);
22118 fputc ('\n', asm_out_file
);
22120 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
22125 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
22126 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
22127 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
22128 deduce these equivalences by itself so it wasn't necessary to hold
22129 its hand so much. Don't be tempted to always supply d2_f_d_e with
22130 the actual cfa register, ie. r31 when we are using a hard frame
22131 pointer. That fails when saving regs off r1, and sched moves the
22132 r31 setup past the reg saves. */
22135 rs6000_frame_related (rtx insn
, rtx reg
, HOST_WIDE_INT val
,
22136 rtx reg2
, rtx rreg
, rtx split_reg
)
22140 if (REGNO (reg
) == STACK_POINTER_REGNUM
&& reg2
== NULL_RTX
)
22142 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
22145 gcc_checking_assert (val
== 0);
22146 real
= PATTERN (insn
);
22147 if (GET_CODE (real
) == PARALLEL
)
22148 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
22149 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
22151 rtx set
= XVECEXP (real
, 0, i
);
22153 RTX_FRAME_RELATED_P (set
) = 1;
22155 RTX_FRAME_RELATED_P (insn
) = 1;
22159 /* copy_rtx will not make unique copies of registers, so we need to
22160 ensure we don't have unwanted sharing here. */
22162 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
22165 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
22167 real
= copy_rtx (PATTERN (insn
));
22169 if (reg2
!= NULL_RTX
)
22170 real
= replace_rtx (real
, reg2
, rreg
);
22172 if (REGNO (reg
) == STACK_POINTER_REGNUM
)
22173 gcc_checking_assert (val
== 0);
22175 real
= replace_rtx (real
, reg
,
22176 gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
,
22177 STACK_POINTER_REGNUM
),
22180 /* We expect that 'real' is either a SET or a PARALLEL containing
22181 SETs (and possibly other stuff). In a PARALLEL, all the SETs
22182 are important so they all have to be marked RTX_FRAME_RELATED_P. */
22184 if (GET_CODE (real
) == SET
)
22188 temp
= simplify_rtx (SET_SRC (set
));
22190 SET_SRC (set
) = temp
;
22191 temp
= simplify_rtx (SET_DEST (set
));
22193 SET_DEST (set
) = temp
;
22194 if (GET_CODE (SET_DEST (set
)) == MEM
)
22196 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
22198 XEXP (SET_DEST (set
), 0) = temp
;
22205 gcc_assert (GET_CODE (real
) == PARALLEL
);
22206 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
22207 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
22209 rtx set
= XVECEXP (real
, 0, i
);
22211 temp
= simplify_rtx (SET_SRC (set
));
22213 SET_SRC (set
) = temp
;
22214 temp
= simplify_rtx (SET_DEST (set
));
22216 SET_DEST (set
) = temp
;
22217 if (GET_CODE (SET_DEST (set
)) == MEM
)
22219 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
22221 XEXP (SET_DEST (set
), 0) = temp
;
22223 RTX_FRAME_RELATED_P (set
) = 1;
22227 /* If a store insn has been split into multiple insns, the
22228 true source register is given by split_reg. */
22229 if (split_reg
!= NULL_RTX
)
22230 real
= gen_rtx_SET (VOIDmode
, SET_DEST (real
), split_reg
);
22232 RTX_FRAME_RELATED_P (insn
) = 1;
22233 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, real
);
22238 /* Returns an insn that has a vrsave set operation with the
22239 appropriate CLOBBERs. */
22242 generate_set_vrsave (rtx reg
, rs6000_stack_t
*info
, int epiloguep
)
22245 rtx insn
, clobs
[TOTAL_ALTIVEC_REGS
+ 1];
22246 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
22249 = gen_rtx_SET (VOIDmode
,
22251 gen_rtx_UNSPEC_VOLATILE (SImode
,
22252 gen_rtvec (2, reg
, vrsave
),
22253 UNSPECV_SET_VRSAVE
));
22257 /* We need to clobber the registers in the mask so the scheduler
22258 does not move sets to VRSAVE before sets of AltiVec registers.
22260 However, if the function receives nonlocal gotos, reload will set
22261 all call saved registers live. We will end up with:
22263 (set (reg 999) (mem))
22264 (parallel [ (set (reg vrsave) (unspec blah))
22265 (clobber (reg 999))])
22267 The clobber will cause the store into reg 999 to be dead, and
22268 flow will attempt to delete an epilogue insn. In this case, we
22269 need an unspec use/set of the register. */
22271 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
22272 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
22274 if (!epiloguep
|| call_used_regs
[i
])
22275 clobs
[nclobs
++] = gen_rtx_CLOBBER (VOIDmode
,
22276 gen_rtx_REG (V4SImode
, i
));
22279 rtx reg
= gen_rtx_REG (V4SImode
, i
);
22282 = gen_rtx_SET (VOIDmode
,
22284 gen_rtx_UNSPEC (V4SImode
,
22285 gen_rtvec (1, reg
), 27));
22289 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nclobs
));
22291 for (i
= 0; i
< nclobs
; ++i
)
22292 XVECEXP (insn
, 0, i
) = clobs
[i
];
22298 gen_frame_set (rtx reg
, rtx frame_reg
, int offset
, bool store
)
22302 addr
= gen_rtx_PLUS (Pmode
, frame_reg
, GEN_INT (offset
));
22303 mem
= gen_frame_mem (GET_MODE (reg
), addr
);
22304 return gen_rtx_SET (VOIDmode
, store
? mem
: reg
, store
? reg
: mem
);
22308 gen_frame_load (rtx reg
, rtx frame_reg
, int offset
)
22310 return gen_frame_set (reg
, frame_reg
, offset
, false);
22314 gen_frame_store (rtx reg
, rtx frame_reg
, int offset
)
22316 return gen_frame_set (reg
, frame_reg
, offset
, true);
22319 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
22320 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
22323 emit_frame_save (rtx frame_reg
, enum machine_mode mode
,
22324 unsigned int regno
, int offset
, HOST_WIDE_INT frame_reg_to_sp
)
22328 /* Some cases that need register indexed addressing. */
22329 gcc_checking_assert (!((TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
22330 || (TARGET_VSX
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
22331 || (TARGET_E500_DOUBLE
&& mode
== DFmode
)
22333 && SPE_VECTOR_MODE (mode
)
22334 && !SPE_CONST_OFFSET_OK (offset
))));
22336 reg
= gen_rtx_REG (mode
, regno
);
22337 insn
= emit_insn (gen_frame_store (reg
, frame_reg
, offset
));
22338 return rs6000_frame_related (insn
, frame_reg
, frame_reg_to_sp
,
22339 NULL_RTX
, NULL_RTX
, NULL_RTX
);
22342 /* Emit an offset memory reference suitable for a frame store, while
22343 converting to a valid addressing mode. */
22346 gen_frame_mem_offset (enum machine_mode mode
, rtx reg
, int offset
)
22348 rtx int_rtx
, offset_rtx
;
22350 int_rtx
= GEN_INT (offset
);
22352 if ((TARGET_SPE_ABI
&& SPE_VECTOR_MODE (mode
) && !SPE_CONST_OFFSET_OK (offset
))
22353 || (TARGET_E500_DOUBLE
&& mode
== DFmode
))
22355 offset_rtx
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
22356 emit_move_insn (offset_rtx
, int_rtx
);
22359 offset_rtx
= int_rtx
;
22361 return gen_frame_mem (mode
, gen_rtx_PLUS (Pmode
, reg
, offset_rtx
));
22364 #ifndef TARGET_FIX_AND_CONTINUE
22365 #define TARGET_FIX_AND_CONTINUE 0
22368 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
22369 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
22370 #define LAST_SAVRES_REGISTER 31
22371 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
22382 static GTY(()) rtx savres_routine_syms
[N_SAVRES_REGISTERS
][12];
22384 /* Temporary holding space for an out-of-line register save/restore
22386 static char savres_routine_name
[30];
22388 /* Return the name for an out-of-line register save/restore routine.
22389 We are saving/restoring GPRs if GPR is true. */
22392 rs6000_savres_routine_name (rs6000_stack_t
*info
, int regno
, int sel
)
22394 const char *prefix
= "";
22395 const char *suffix
= "";
22397 /* Different targets are supposed to define
22398 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
22399 routine name could be defined with:
22401 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
22403 This is a nice idea in practice, but in reality, things are
22404 complicated in several ways:
22406 - ELF targets have save/restore routines for GPRs.
22408 - SPE targets use different prefixes for 32/64-bit registers, and
22409 neither of them fit neatly in the FOO_{PREFIX,SUFFIX} regimen.
22411 - PPC64 ELF targets have routines for save/restore of GPRs that
22412 differ in what they do with the link register, so having a set
22413 prefix doesn't work. (We only use one of the save routines at
22414 the moment, though.)
22416 - PPC32 elf targets have "exit" versions of the restore routines
22417 that restore the link register and can save some extra space.
22418 These require an extra suffix. (There are also "tail" versions
22419 of the restore routines and "GOT" versions of the save routines,
22420 but we don't generate those at present. Same problems apply,
22423 We deal with all this by synthesizing our own prefix/suffix and
22424 using that for the simple sprintf call shown above. */
22427 /* No floating point saves on the SPE. */
22428 gcc_assert ((sel
& SAVRES_REG
) == SAVRES_GPR
);
22430 if ((sel
& SAVRES_SAVE
))
22431 prefix
= info
->spe_64bit_regs_used
? "_save64gpr_" : "_save32gpr_";
22433 prefix
= info
->spe_64bit_regs_used
? "_rest64gpr_" : "_rest32gpr_";
22435 if ((sel
& SAVRES_LR
))
22438 else if (DEFAULT_ABI
== ABI_V4
)
22443 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
22444 prefix
= (sel
& SAVRES_SAVE
) ? "_savegpr_" : "_restgpr_";
22445 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
22446 prefix
= (sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_";
22447 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
22448 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
22452 if ((sel
& SAVRES_LR
))
22455 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
22457 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
22458 /* No out-of-line save/restore routines for GPRs on AIX. */
22459 gcc_assert (!TARGET_AIX
|| (sel
& SAVRES_REG
) != SAVRES_GPR
);
22463 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
22464 prefix
= ((sel
& SAVRES_SAVE
)
22465 ? ((sel
& SAVRES_LR
) ? "_savegpr0_" : "_savegpr1_")
22466 : ((sel
& SAVRES_LR
) ? "_restgpr0_" : "_restgpr1_"));
22467 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
22469 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
22470 if ((sel
& SAVRES_LR
))
22471 prefix
= ((sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_");
22475 prefix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_PREFIX
: RESTORE_FP_PREFIX
;
22476 suffix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_SUFFIX
: RESTORE_FP_SUFFIX
;
22479 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
22480 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
22485 if (DEFAULT_ABI
== ABI_DARWIN
)
22487 /* The Darwin approach is (slightly) different, in order to be
22488 compatible with code generated by the system toolchain. There is a
22489 single symbol for the start of save sequence, and the code here
22490 embeds an offset into that code on the basis of the first register
22492 prefix
= (sel
& SAVRES_SAVE
) ? "save" : "rest" ;
22493 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
22494 sprintf (savres_routine_name
, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix
,
22495 ((sel
& SAVRES_LR
) ? "x" : ""), (regno
== 13 ? "" : "+"),
22496 (regno
- 13) * 4, prefix
, regno
);
22497 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
22498 sprintf (savres_routine_name
, "*%sFP%s%.0d ; %s f%d-f31", prefix
,
22499 (regno
== 14 ? "" : "+"), (regno
- 14) * 4, prefix
, regno
);
22500 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
22501 sprintf (savres_routine_name
, "*%sVEC%s%.0d ; %s v%d-v31", prefix
,
22502 (regno
== 20 ? "" : "+"), (regno
- 20) * 8, prefix
, regno
);
22507 sprintf (savres_routine_name
, "%s%d%s", prefix
, regno
, suffix
);
22509 return savres_routine_name
;
22512 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
22513 We are saving/restoring GPRs if GPR is true. */
22516 rs6000_savres_routine_sym (rs6000_stack_t
*info
, int sel
)
22518 int regno
= ((sel
& SAVRES_REG
) == SAVRES_GPR
22519 ? info
->first_gp_reg_save
22520 : (sel
& SAVRES_REG
) == SAVRES_FPR
22521 ? info
->first_fp_reg_save
- 32
22522 : (sel
& SAVRES_REG
) == SAVRES_VR
22523 ? info
->first_altivec_reg_save
- FIRST_ALTIVEC_REGNO
22528 /* On the SPE, we never have any FPRs, but we do have 32/64-bit
22529 versions of the gpr routines. */
22530 if (TARGET_SPE_ABI
&& (sel
& SAVRES_REG
) == SAVRES_GPR
22531 && info
->spe_64bit_regs_used
)
22532 select
^= SAVRES_FPR
^ SAVRES_GPR
;
22534 /* Don't generate bogus routine names. */
22535 gcc_assert (FIRST_SAVRES_REGISTER
<= regno
22536 && regno
<= LAST_SAVRES_REGISTER
22537 && select
>= 0 && select
<= 12);
22539 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
];
22545 name
= rs6000_savres_routine_name (info
, regno
, sel
);
22547 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
]
22548 = gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
22549 SYMBOL_REF_FLAGS (sym
) |= SYMBOL_FLAG_FUNCTION
;
22555 /* Emit a sequence of insns, including a stack tie if needed, for
22556 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
22557 reset the stack pointer, but move the base of the frame into
22558 reg UPDT_REGNO for use by out-of-line register restore routines. */
22561 rs6000_emit_stack_reset (rs6000_stack_t
*info
,
22562 rtx frame_reg_rtx
, HOST_WIDE_INT frame_off
,
22563 unsigned updt_regno
)
22567 /* This blockage is needed so that sched doesn't decide to move
22568 the sp change before the register restores. */
22569 if (DEFAULT_ABI
== ABI_V4
22571 && info
->spe_64bit_regs_used
!= 0
22572 && info
->first_gp_reg_save
!= 32))
22573 rs6000_emit_stack_tie (frame_reg_rtx
, frame_pointer_needed
);
22575 /* If we are restoring registers out-of-line, we will be using the
22576 "exit" variants of the restore routines, which will reset the
22577 stack for us. But we do need to point updt_reg into the
22578 right place for those routines. */
22579 updt_reg_rtx
= gen_rtx_REG (Pmode
, updt_regno
);
22581 if (frame_off
!= 0)
22582 return emit_insn (gen_add3_insn (updt_reg_rtx
,
22583 frame_reg_rtx
, GEN_INT (frame_off
)));
22584 else if (REGNO (frame_reg_rtx
) != updt_regno
)
22585 return emit_move_insn (updt_reg_rtx
, frame_reg_rtx
);
22590 /* Return the register number used as a pointer by out-of-line
22591 save/restore functions. */
22593 static inline unsigned
22594 ptr_regno_for_savres (int sel
)
22596 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
22597 return (sel
& SAVRES_REG
) == SAVRES_FPR
|| (sel
& SAVRES_LR
) ? 1 : 12;
22598 return DEFAULT_ABI
== ABI_DARWIN
&& (sel
& SAVRES_REG
) == SAVRES_FPR
? 1 : 11;
22601 /* Construct a parallel rtx describing the effect of a call to an
22602 out-of-line register save/restore routine, and emit the insn
22603 or jump_insn as appropriate. */
22606 rs6000_emit_savres_rtx (rs6000_stack_t
*info
,
22607 rtx frame_reg_rtx
, int save_area_offset
, int lr_offset
,
22608 enum machine_mode reg_mode
, int sel
)
22611 int offset
, start_reg
, end_reg
, n_regs
, use_reg
;
22612 int reg_size
= GET_MODE_SIZE (reg_mode
);
22618 start_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
22619 ? info
->first_gp_reg_save
22620 : (sel
& SAVRES_REG
) == SAVRES_FPR
22621 ? info
->first_fp_reg_save
22622 : (sel
& SAVRES_REG
) == SAVRES_VR
22623 ? info
->first_altivec_reg_save
22625 end_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
22627 : (sel
& SAVRES_REG
) == SAVRES_FPR
22629 : (sel
& SAVRES_REG
) == SAVRES_VR
22630 ? LAST_ALTIVEC_REGNO
+ 1
22632 n_regs
= end_reg
- start_reg
;
22633 p
= rtvec_alloc (3 + ((sel
& SAVRES_LR
) ? 1 : 0)
22634 + ((sel
& SAVRES_REG
) == SAVRES_VR
? 1 : 0)
22637 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
22638 RTVEC_ELT (p
, offset
++) = ret_rtx
;
22640 RTVEC_ELT (p
, offset
++)
22641 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
22643 sym
= rs6000_savres_routine_sym (info
, sel
);
22644 RTVEC_ELT (p
, offset
++) = gen_rtx_USE (VOIDmode
, sym
);
22646 use_reg
= ptr_regno_for_savres (sel
);
22647 if ((sel
& SAVRES_REG
) == SAVRES_VR
)
22649 /* Vector regs are saved/restored using [reg+reg] addressing. */
22650 RTVEC_ELT (p
, offset
++)
22651 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
22652 RTVEC_ELT (p
, offset
++)
22653 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 0));
22656 RTVEC_ELT (p
, offset
++)
22657 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
22659 for (i
= 0; i
< end_reg
- start_reg
; i
++)
22660 RTVEC_ELT (p
, i
+ offset
)
22661 = gen_frame_set (gen_rtx_REG (reg_mode
, start_reg
+ i
),
22662 frame_reg_rtx
, save_area_offset
+ reg_size
* i
,
22663 (sel
& SAVRES_SAVE
) != 0);
22665 if ((sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
22666 RTVEC_ELT (p
, i
+ offset
)
22667 = gen_frame_store (gen_rtx_REG (Pmode
, 0), frame_reg_rtx
, lr_offset
);
22669 par
= gen_rtx_PARALLEL (VOIDmode
, p
);
22671 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
22673 insn
= emit_jump_insn (par
);
22674 JUMP_LABEL (insn
) = ret_rtx
;
22677 insn
= emit_insn (par
);
22681 /* Emit code to store CR fields that need to be saved into REG. */
22684 rs6000_emit_move_from_cr (rtx reg
)
22686 /* Only the ELFv2 ABI allows storing only selected fields. */
22687 if (DEFAULT_ABI
== ABI_ELFv2
&& TARGET_MFCRF
)
22689 int i
, cr_reg
[8], count
= 0;
22691 /* Collect CR fields that must be saved. */
22692 for (i
= 0; i
< 8; i
++)
22693 if (save_reg_p (CR0_REGNO
+ i
))
22694 cr_reg
[count
++] = i
;
22696 /* If it's just a single one, use mfcrf. */
22699 rtvec p
= rtvec_alloc (1);
22700 rtvec r
= rtvec_alloc (2);
22701 RTVEC_ELT (r
, 0) = gen_rtx_REG (CCmode
, CR0_REGNO
+ cr_reg
[0]);
22702 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7 - cr_reg
[0]));
22704 = gen_rtx_SET (VOIDmode
, reg
,
22705 gen_rtx_UNSPEC (SImode
, r
, UNSPEC_MOVESI_FROM_CR
));
22707 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
22711 /* ??? It might be better to handle count == 2 / 3 cases here
22712 as well, using logical operations to combine the values. */
22715 emit_insn (gen_movesi_from_cr (reg
));
22718 /* Determine whether the gp REG is really used. */
22721 rs6000_reg_live_or_pic_offset_p (int reg
)
22723 /* If the function calls eh_return, claim used all the registers that would
22724 be checked for liveness otherwise. This is required for the PIC offset
22725 register with -mminimal-toc on AIX, as it is advertised as "fixed" for
22726 register allocation purposes in this case. */
22728 return (((crtl
->calls_eh_return
|| df_regs_ever_live_p (reg
))
22729 && (!call_used_regs
[reg
]
22730 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
22731 && !TARGET_SINGLE_PIC_BASE
22732 && TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
22733 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
22734 && !TARGET_SINGLE_PIC_BASE
22735 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
22736 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
))));
22739 /* Emit function prologue as insns. */
22742 rs6000_emit_prologue (void)
22744 rs6000_stack_t
*info
= rs6000_stack_info ();
22745 enum machine_mode reg_mode
= Pmode
;
22746 int reg_size
= TARGET_32BIT
? 4 : 8;
22747 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
22748 rtx frame_reg_rtx
= sp_reg_rtx
;
22749 unsigned int cr_save_regno
;
22750 rtx cr_save_rtx
= NULL_RTX
;
22753 int using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
22754 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
22755 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
22756 /* Offset to top of frame for frame_reg and sp respectively. */
22757 HOST_WIDE_INT frame_off
= 0;
22758 HOST_WIDE_INT sp_off
= 0;
22760 #ifdef ENABLE_CHECKING
22761 /* Track and check usage of r0, r11, r12. */
22762 int reg_inuse
= using_static_chain_p
? 1 << 11 : 0;
22763 #define START_USE(R) do \
22765 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
22766 reg_inuse |= 1 << (R); \
22768 #define END_USE(R) do \
22770 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
22771 reg_inuse &= ~(1 << (R)); \
22773 #define NOT_INUSE(R) do \
22775 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
22778 #define START_USE(R) do {} while (0)
22779 #define END_USE(R) do {} while (0)
22780 #define NOT_INUSE(R) do {} while (0)
22783 if (DEFAULT_ABI
== ABI_ELFv2
)
22785 cfun
->machine
->r2_setup_needed
= df_regs_ever_live_p (TOC_REGNUM
);
22787 /* With -mminimal-toc we may generate an extra use of r2 below. */
22788 if (!TARGET_SINGLE_PIC_BASE
22789 && TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
22790 cfun
->machine
->r2_setup_needed
= true;
22794 if (flag_stack_usage_info
)
22795 current_function_static_stack_size
= info
->total_size
;
22797 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
22799 HOST_WIDE_INT size
= info
->total_size
;
22801 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
22803 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
22804 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT
,
22805 size
- STACK_CHECK_PROTECT
);
22808 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
22811 if (TARGET_FIX_AND_CONTINUE
)
22813 /* gdb on darwin arranges to forward a function from the old
22814 address by modifying the first 5 instructions of the function
22815 to branch to the overriding function. This is necessary to
22816 permit function pointers that point to the old function to
22817 actually forward to the new function. */
22818 emit_insn (gen_nop ());
22819 emit_insn (gen_nop ());
22820 emit_insn (gen_nop ());
22821 emit_insn (gen_nop ());
22822 emit_insn (gen_nop ());
22825 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
22827 reg_mode
= V2SImode
;
22831 /* Handle world saves specially here. */
22832 if (WORLD_SAVE_P (info
))
22839 /* save_world expects lr in r0. */
22840 reg0
= gen_rtx_REG (Pmode
, 0);
22841 if (info
->lr_save_p
)
22843 insn
= emit_move_insn (reg0
,
22844 gen_rtx_REG (Pmode
, LR_REGNO
));
22845 RTX_FRAME_RELATED_P (insn
) = 1;
22848 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
22849 assumptions about the offsets of various bits of the stack
22851 gcc_assert (info
->gp_save_offset
== -220
22852 && info
->fp_save_offset
== -144
22853 && info
->lr_save_offset
== 8
22854 && info
->cr_save_offset
== 4
22857 && (!crtl
->calls_eh_return
22858 || info
->ehrd_offset
== -432)
22859 && info
->vrsave_save_offset
== -224
22860 && info
->altivec_save_offset
== -416);
22862 treg
= gen_rtx_REG (SImode
, 11);
22863 emit_move_insn (treg
, GEN_INT (-info
->total_size
));
22865 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
22866 in R11. It also clobbers R12, so beware! */
22868 /* Preserve CR2 for save_world prologues */
22870 sz
+= 32 - info
->first_gp_reg_save
;
22871 sz
+= 64 - info
->first_fp_reg_save
;
22872 sz
+= LAST_ALTIVEC_REGNO
- info
->first_altivec_reg_save
+ 1;
22873 p
= rtvec_alloc (sz
);
22875 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
,
22876 gen_rtx_REG (SImode
,
22878 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
22879 gen_rtx_SYMBOL_REF (Pmode
,
22881 /* We do floats first so that the instruction pattern matches
22883 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
22885 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
22887 info
->first_fp_reg_save
+ i
),
22889 info
->fp_save_offset
+ frame_off
+ 8 * i
);
22890 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
22892 = gen_frame_store (gen_rtx_REG (V4SImode
,
22893 info
->first_altivec_reg_save
+ i
),
22895 info
->altivec_save_offset
+ frame_off
+ 16 * i
);
22896 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
22898 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
22900 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
22902 /* CR register traditionally saved as CR2. */
22904 = gen_frame_store (gen_rtx_REG (SImode
, CR2_REGNO
),
22905 frame_reg_rtx
, info
->cr_save_offset
+ frame_off
);
22906 /* Explain about use of R0. */
22907 if (info
->lr_save_p
)
22909 = gen_frame_store (reg0
,
22910 frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
22911 /* Explain what happens to the stack pointer. */
22913 rtx newval
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
, treg
);
22914 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, sp_reg_rtx
, newval
);
22917 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
22918 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
22919 treg
, GEN_INT (-info
->total_size
), NULL_RTX
);
22920 sp_off
= frame_off
= info
->total_size
;
22923 strategy
= info
->savres_strategy
;
22925 /* For V.4, update stack before we do any saving and set back pointer. */
22926 if (! WORLD_SAVE_P (info
)
22928 && (DEFAULT_ABI
== ABI_V4
22929 || crtl
->calls_eh_return
))
22931 bool need_r11
= (TARGET_SPE
22932 ? (!(strategy
& SAVE_INLINE_GPRS
)
22933 && info
->spe_64bit_regs_used
== 0)
22934 : (!(strategy
& SAVE_INLINE_FPRS
)
22935 || !(strategy
& SAVE_INLINE_GPRS
)
22936 || !(strategy
& SAVE_INLINE_VRS
)));
22937 int ptr_regno
= -1;
22938 rtx ptr_reg
= NULL_RTX
;
22941 if (info
->total_size
< 32767)
22942 frame_off
= info
->total_size
;
22945 else if (info
->cr_save_p
22947 || info
->first_fp_reg_save
< 64
22948 || info
->first_gp_reg_save
< 32
22949 || info
->altivec_size
!= 0
22950 || info
->vrsave_mask
!= 0
22951 || crtl
->calls_eh_return
)
22955 /* The prologue won't be saving any regs so there is no need
22956 to set up a frame register to access any frame save area.
22957 We also won't be using frame_off anywhere below, but set
22958 the correct value anyway to protect against future
22959 changes to this function. */
22960 frame_off
= info
->total_size
;
22962 if (ptr_regno
!= -1)
22964 /* Set up the frame offset to that needed by the first
22965 out-of-line save function. */
22966 START_USE (ptr_regno
);
22967 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
22968 frame_reg_rtx
= ptr_reg
;
22969 if (!(strategy
& SAVE_INLINE_FPRS
) && info
->fp_size
!= 0)
22970 gcc_checking_assert (info
->fp_save_offset
+ info
->fp_size
== 0);
22971 else if (!(strategy
& SAVE_INLINE_GPRS
) && info
->first_gp_reg_save
< 32)
22972 ptr_off
= info
->gp_save_offset
+ info
->gp_size
;
22973 else if (!(strategy
& SAVE_INLINE_VRS
) && info
->altivec_size
!= 0)
22974 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
22975 frame_off
= -ptr_off
;
22977 rs6000_emit_allocate_stack (info
->total_size
, ptr_reg
, ptr_off
);
22978 sp_off
= info
->total_size
;
22979 if (frame_reg_rtx
!= sp_reg_rtx
)
22980 rs6000_emit_stack_tie (frame_reg_rtx
, false);
22983 /* If we use the link register, get it into r0. */
22984 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
)
22986 rtx addr
, reg
, mem
;
22988 reg
= gen_rtx_REG (Pmode
, 0);
22990 insn
= emit_move_insn (reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
22991 RTX_FRAME_RELATED_P (insn
) = 1;
22993 if (!(strategy
& (SAVE_NOINLINE_GPRS_SAVES_LR
22994 | SAVE_NOINLINE_FPRS_SAVES_LR
)))
22996 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
22997 GEN_INT (info
->lr_save_offset
+ frame_off
));
22998 mem
= gen_rtx_MEM (Pmode
, addr
);
22999 /* This should not be of rs6000_sr_alias_set, because of
23000 __builtin_return_address. */
23002 insn
= emit_move_insn (mem
, reg
);
23003 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
23004 NULL_RTX
, NULL_RTX
, NULL_RTX
);
23009 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
23010 r12 will be needed by out-of-line gpr restore. */
23011 cr_save_regno
= ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
23012 && !(strategy
& (SAVE_INLINE_GPRS
23013 | SAVE_NOINLINE_GPRS_SAVES_LR
))
23015 if (!WORLD_SAVE_P (info
)
23017 && REGNO (frame_reg_rtx
) != cr_save_regno
23018 && !(using_static_chain_p
&& cr_save_regno
== 11))
23020 cr_save_rtx
= gen_rtx_REG (SImode
, cr_save_regno
);
23021 START_USE (cr_save_regno
);
23022 rs6000_emit_move_from_cr (cr_save_rtx
);
23025 /* Do any required saving of fpr's. If only one or two to save, do
23026 it ourselves. Otherwise, call function. */
23027 if (!WORLD_SAVE_P (info
) && (strategy
& SAVE_INLINE_FPRS
))
23030 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
23031 if (save_reg_p (info
->first_fp_reg_save
+ i
))
23032 emit_frame_save (frame_reg_rtx
,
23033 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
23034 ? DFmode
: SFmode
),
23035 info
->first_fp_reg_save
+ i
,
23036 info
->fp_save_offset
+ frame_off
+ 8 * i
,
23037 sp_off
- frame_off
);
23039 else if (!WORLD_SAVE_P (info
) && info
->first_fp_reg_save
!= 64)
23041 bool lr
= (strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
23042 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
23043 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
23044 rtx ptr_reg
= frame_reg_rtx
;
23046 if (REGNO (frame_reg_rtx
) == ptr_regno
)
23047 gcc_checking_assert (frame_off
== 0);
23050 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
23051 NOT_INUSE (ptr_regno
);
23052 emit_insn (gen_add3_insn (ptr_reg
,
23053 frame_reg_rtx
, GEN_INT (frame_off
)));
23055 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
23056 info
->fp_save_offset
,
23057 info
->lr_save_offset
,
23059 rs6000_frame_related (insn
, ptr_reg
, sp_off
,
23060 NULL_RTX
, NULL_RTX
, NULL_RTX
);
23065 /* Save GPRs. This is done as a PARALLEL if we are using
23066 the store-multiple instructions. */
23067 if (!WORLD_SAVE_P (info
)
23069 && info
->spe_64bit_regs_used
!= 0
23070 && info
->first_gp_reg_save
!= 32)
23073 rtx spe_save_area_ptr
;
23074 HOST_WIDE_INT save_off
;
23075 int ool_adjust
= 0;
23077 /* Determine whether we can address all of the registers that need
23078 to be saved with an offset from frame_reg_rtx that fits in
23079 the small const field for SPE memory instructions. */
23080 int spe_regs_addressable
23081 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ frame_off
23082 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
23083 && (strategy
& SAVE_INLINE_GPRS
));
23085 if (spe_regs_addressable
)
23087 spe_save_area_ptr
= frame_reg_rtx
;
23088 save_off
= frame_off
;
23092 /* Make r11 point to the start of the SPE save area. We need
23093 to be careful here if r11 is holding the static chain. If
23094 it is, then temporarily save it in r0. */
23095 HOST_WIDE_INT offset
;
23097 if (!(strategy
& SAVE_INLINE_GPRS
))
23098 ool_adjust
= 8 * (info
->first_gp_reg_save
- FIRST_SAVED_GP_REGNO
);
23099 offset
= info
->spe_gp_save_offset
+ frame_off
- ool_adjust
;
23100 spe_save_area_ptr
= gen_rtx_REG (Pmode
, 11);
23101 save_off
= frame_off
- offset
;
23103 if (using_static_chain_p
)
23105 rtx r0
= gen_rtx_REG (Pmode
, 0);
23108 gcc_assert (info
->first_gp_reg_save
> 11);
23110 emit_move_insn (r0
, spe_save_area_ptr
);
23112 else if (REGNO (frame_reg_rtx
) != 11)
23115 emit_insn (gen_addsi3 (spe_save_area_ptr
,
23116 frame_reg_rtx
, GEN_INT (offset
)));
23117 if (!using_static_chain_p
&& REGNO (frame_reg_rtx
) == 11)
23118 frame_off
= -info
->spe_gp_save_offset
+ ool_adjust
;
23121 if ((strategy
& SAVE_INLINE_GPRS
))
23123 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
23124 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
23125 emit_frame_save (spe_save_area_ptr
, reg_mode
,
23126 info
->first_gp_reg_save
+ i
,
23127 (info
->spe_gp_save_offset
+ save_off
23129 sp_off
- save_off
);
23133 insn
= rs6000_emit_savres_rtx (info
, spe_save_area_ptr
,
23134 info
->spe_gp_save_offset
+ save_off
,
23136 SAVRES_SAVE
| SAVRES_GPR
);
23138 rs6000_frame_related (insn
, spe_save_area_ptr
, sp_off
- save_off
,
23139 NULL_RTX
, NULL_RTX
, NULL_RTX
);
23142 /* Move the static chain pointer back. */
23143 if (!spe_regs_addressable
)
23145 if (using_static_chain_p
)
23147 emit_move_insn (spe_save_area_ptr
, gen_rtx_REG (Pmode
, 0));
23150 else if (REGNO (frame_reg_rtx
) != 11)
23154 else if (!WORLD_SAVE_P (info
) && !(strategy
& SAVE_INLINE_GPRS
))
23156 bool lr
= (strategy
& SAVE_NOINLINE_GPRS_SAVES_LR
) != 0;
23157 int sel
= SAVRES_SAVE
| SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
23158 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
23159 rtx ptr_reg
= frame_reg_rtx
;
23160 bool ptr_set_up
= REGNO (ptr_reg
) == ptr_regno
;
23161 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
23165 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
23167 /* Need to adjust r11 (r12) if we saved any FPRs. */
23168 if (end_save
+ frame_off
!= 0)
23170 rtx offset
= GEN_INT (end_save
+ frame_off
);
23173 frame_off
= -end_save
;
23175 NOT_INUSE (ptr_regno
);
23176 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
23178 else if (!ptr_set_up
)
23180 NOT_INUSE (ptr_regno
);
23181 emit_move_insn (ptr_reg
, frame_reg_rtx
);
23183 ptr_off
= -end_save
;
23184 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
23185 info
->gp_save_offset
+ ptr_off
,
23186 info
->lr_save_offset
+ ptr_off
,
23188 rs6000_frame_related (insn
, ptr_reg
, sp_off
- ptr_off
,
23189 NULL_RTX
, NULL_RTX
, NULL_RTX
);
23193 else if (!WORLD_SAVE_P (info
) && (strategy
& SAVRES_MULTIPLE
))
23197 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
23198 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
23200 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
23202 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
23203 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
23204 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
23205 NULL_RTX
, NULL_RTX
, NULL_RTX
);
23207 else if (!WORLD_SAVE_P (info
))
23210 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
23211 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
23212 emit_frame_save (frame_reg_rtx
, reg_mode
,
23213 info
->first_gp_reg_save
+ i
,
23214 info
->gp_save_offset
+ frame_off
+ reg_size
* i
,
23215 sp_off
- frame_off
);
23218 if (crtl
->calls_eh_return
)
23225 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
23226 if (regno
== INVALID_REGNUM
)
23230 p
= rtvec_alloc (i
);
23234 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
23235 if (regno
== INVALID_REGNUM
)
23239 = gen_frame_store (gen_rtx_REG (reg_mode
, regno
),
23241 info
->ehrd_offset
+ sp_off
+ reg_size
* (int) i
);
23242 RTVEC_ELT (p
, i
) = insn
;
23243 RTX_FRAME_RELATED_P (insn
) = 1;
23246 insn
= emit_insn (gen_blockage ());
23247 RTX_FRAME_RELATED_P (insn
) = 1;
23248 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, gen_rtx_PARALLEL (VOIDmode
, p
));
23251 /* In AIX ABI we need to make sure r2 is really saved. */
23252 if (TARGET_AIX
&& crtl
->calls_eh_return
)
23254 rtx tmp_reg
, tmp_reg_si
, hi
, lo
, compare_result
, toc_save_done
, jump
;
23255 rtx save_insn
, join_insn
, note
;
23256 long toc_restore_insn
;
23258 tmp_reg
= gen_rtx_REG (Pmode
, 11);
23259 tmp_reg_si
= gen_rtx_REG (SImode
, 11);
23260 if (using_static_chain_p
)
23263 emit_move_insn (gen_rtx_REG (Pmode
, 0), tmp_reg
);
23267 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
23268 /* Peek at instruction to which this function returns. If it's
23269 restoring r2, then we know we've already saved r2. We can't
23270 unconditionally save r2 because the value we have will already
23271 be updated if we arrived at this function via a plt call or
23272 toc adjusting stub. */
23273 emit_move_insn (tmp_reg_si
, gen_rtx_MEM (SImode
, tmp_reg
));
23274 toc_restore_insn
= ((TARGET_32BIT
? 0x80410000 : 0xE8410000)
23275 + RS6000_TOC_SAVE_SLOT
);
23276 hi
= gen_int_mode (toc_restore_insn
& ~0xffff, SImode
);
23277 emit_insn (gen_xorsi3 (tmp_reg_si
, tmp_reg_si
, hi
));
23278 compare_result
= gen_rtx_REG (CCUNSmode
, CR0_REGNO
);
23279 validate_condition_mode (EQ
, CCUNSmode
);
23280 lo
= gen_int_mode (toc_restore_insn
& 0xffff, SImode
);
23281 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
23282 gen_rtx_COMPARE (CCUNSmode
, tmp_reg_si
, lo
)));
23283 toc_save_done
= gen_label_rtx ();
23284 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
23285 gen_rtx_EQ (VOIDmode
, compare_result
,
23287 gen_rtx_LABEL_REF (VOIDmode
, toc_save_done
),
23289 jump
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, jump
));
23290 JUMP_LABEL (jump
) = toc_save_done
;
23291 LABEL_NUSES (toc_save_done
) += 1;
23293 save_insn
= emit_frame_save (frame_reg_rtx
, reg_mode
,
23294 TOC_REGNUM
, frame_off
+ RS6000_TOC_SAVE_SLOT
,
23295 sp_off
- frame_off
);
23297 emit_label (toc_save_done
);
23299 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
23300 have a CFG that has different saves along different paths.
23301 Move the note to a dummy blockage insn, which describes that
23302 R2 is unconditionally saved after the label. */
23303 /* ??? An alternate representation might be a special insn pattern
23304 containing both the branch and the store. That might let the
23305 code that minimizes the number of DW_CFA_advance opcodes better
23306 freedom in placing the annotations. */
23307 note
= find_reg_note (save_insn
, REG_FRAME_RELATED_EXPR
, NULL
);
23309 remove_note (save_insn
, note
);
23311 note
= alloc_reg_note (REG_FRAME_RELATED_EXPR
,
23312 copy_rtx (PATTERN (save_insn
)), NULL_RTX
);
23313 RTX_FRAME_RELATED_P (save_insn
) = 0;
23315 join_insn
= emit_insn (gen_blockage ());
23316 REG_NOTES (join_insn
) = note
;
23317 RTX_FRAME_RELATED_P (join_insn
) = 1;
23319 if (using_static_chain_p
)
23321 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, 0));
23328 /* Save CR if we use any that must be preserved. */
23329 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
)
23331 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
23332 GEN_INT (info
->cr_save_offset
+ frame_off
));
23333 rtx mem
= gen_frame_mem (SImode
, addr
);
23335 /* If we didn't copy cr before, do so now using r0. */
23336 if (cr_save_rtx
== NULL_RTX
)
23339 cr_save_rtx
= gen_rtx_REG (SImode
, 0);
23340 rs6000_emit_move_from_cr (cr_save_rtx
);
23343 /* Saving CR requires a two-instruction sequence: one instruction
23344 to move the CR to a general-purpose register, and a second
23345 instruction that stores the GPR to memory.
23347 We do not emit any DWARF CFI records for the first of these,
23348 because we cannot properly represent the fact that CR is saved in
23349 a register. One reason is that we cannot express that multiple
23350 CR fields are saved; another reason is that on 64-bit, the size
23351 of the CR register in DWARF (4 bytes) differs from the size of
23352 a general-purpose register.
23354 This means if any intervening instruction were to clobber one of
23355 the call-saved CR fields, we'd have incorrect CFI. To prevent
23356 this from happening, we mark the store to memory as a use of
23357 those CR fields, which prevents any such instruction from being
23358 scheduled in between the two instructions. */
23363 crsave_v
[n_crsave
++] = gen_rtx_SET (VOIDmode
, mem
, cr_save_rtx
);
23364 for (i
= 0; i
< 8; i
++)
23365 if (save_reg_p (CR0_REGNO
+ i
))
23366 crsave_v
[n_crsave
++]
23367 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
));
23369 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
,
23370 gen_rtvec_v (n_crsave
, crsave_v
)));
23371 END_USE (REGNO (cr_save_rtx
));
23373 /* Now, there's no way that dwarf2out_frame_debug_expr is going to
23374 understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)',
23375 so we need to construct a frame expression manually. */
23376 RTX_FRAME_RELATED_P (insn
) = 1;
23378 /* Update address to be stack-pointer relative, like
23379 rs6000_frame_related would do. */
23380 addr
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
),
23381 GEN_INT (info
->cr_save_offset
+ sp_off
));
23382 mem
= gen_frame_mem (SImode
, addr
);
23384 if (DEFAULT_ABI
== ABI_ELFv2
)
23386 /* In the ELFv2 ABI we generate separate CFI records for each
23387 CR field that was actually saved. They all point to the
23388 same 32-bit stack slot. */
23392 for (i
= 0; i
< 8; i
++)
23393 if (save_reg_p (CR0_REGNO
+ i
))
23396 = gen_rtx_SET (VOIDmode
, mem
,
23397 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
23399 RTX_FRAME_RELATED_P (crframe
[n_crframe
]) = 1;
23403 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
23404 gen_rtx_PARALLEL (VOIDmode
,
23405 gen_rtvec_v (n_crframe
, crframe
)));
23409 /* In other ABIs, by convention, we use a single CR regnum to
23410 represent the fact that all call-saved CR fields are saved.
23411 We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */
23412 rtx set
= gen_rtx_SET (VOIDmode
, mem
,
23413 gen_rtx_REG (SImode
, CR2_REGNO
));
23414 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
23418 /* In the ELFv2 ABI we need to save all call-saved CR fields into
23419 *separate* slots if the routine calls __builtin_eh_return, so
23420 that they can be independently restored by the unwinder. */
23421 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
23423 int i
, cr_off
= info
->ehcr_offset
;
23426 /* ??? We might get better performance by using multiple mfocrf
23428 crsave
= gen_rtx_REG (SImode
, 0);
23429 emit_insn (gen_movesi_from_cr (crsave
));
23431 for (i
= 0; i
< 8; i
++)
23432 if (!call_used_regs
[CR0_REGNO
+ i
])
23434 rtvec p
= rtvec_alloc (2);
23436 = gen_frame_store (crsave
, frame_reg_rtx
, cr_off
+ frame_off
);
23438 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
));
23440 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
23442 RTX_FRAME_RELATED_P (insn
) = 1;
23443 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
23444 gen_frame_store (gen_rtx_REG (SImode
, CR0_REGNO
+ i
),
23445 sp_reg_rtx
, cr_off
+ sp_off
));
23447 cr_off
+= reg_size
;
23451 /* Update stack and set back pointer unless this is V.4,
23452 for which it was done previously. */
23453 if (!WORLD_SAVE_P (info
) && info
->push_p
23454 && !(DEFAULT_ABI
== ABI_V4
|| crtl
->calls_eh_return
))
23456 rtx ptr_reg
= NULL
;
23459 /* If saving altivec regs we need to be able to address all save
23460 locations using a 16-bit offset. */
23461 if ((strategy
& SAVE_INLINE_VRS
) == 0
23462 || (info
->altivec_size
!= 0
23463 && (info
->altivec_save_offset
+ info
->altivec_size
- 16
23464 + info
->total_size
- frame_off
) > 32767)
23465 || (info
->vrsave_size
!= 0
23466 && (info
->vrsave_save_offset
23467 + info
->total_size
- frame_off
) > 32767))
23469 int sel
= SAVRES_SAVE
| SAVRES_VR
;
23470 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
23472 if (using_static_chain_p
23473 && ptr_regno
== STATIC_CHAIN_REGNUM
)
23475 if (REGNO (frame_reg_rtx
) != ptr_regno
)
23476 START_USE (ptr_regno
);
23477 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
23478 frame_reg_rtx
= ptr_reg
;
23479 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
23480 frame_off
= -ptr_off
;
23482 else if (REGNO (frame_reg_rtx
) == 1)
23483 frame_off
= info
->total_size
;
23484 rs6000_emit_allocate_stack (info
->total_size
, ptr_reg
, ptr_off
);
23485 sp_off
= info
->total_size
;
23486 if (frame_reg_rtx
!= sp_reg_rtx
)
23487 rs6000_emit_stack_tie (frame_reg_rtx
, false);
23490 /* Set frame pointer, if needed. */
23491 if (frame_pointer_needed
)
23493 insn
= emit_move_insn (gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
23495 RTX_FRAME_RELATED_P (insn
) = 1;
23498 /* Save AltiVec registers if needed. Save here because the red zone does
23499 not always include AltiVec registers. */
23500 if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
23501 && info
->altivec_size
!= 0 && (strategy
& SAVE_INLINE_VRS
) == 0)
23503 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
23505 /* Oddly, the vector save/restore functions point r0 at the end
23506 of the save area, then use r11 or r12 to load offsets for
23507 [reg+reg] addressing. */
23508 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
23509 int scratch_regno
= ptr_regno_for_savres (SAVRES_SAVE
| SAVRES_VR
);
23510 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
23512 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
23514 if (end_save
+ frame_off
!= 0)
23516 rtx offset
= GEN_INT (end_save
+ frame_off
);
23518 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
23521 emit_move_insn (ptr_reg
, frame_reg_rtx
);
23523 ptr_off
= -end_save
;
23524 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
23525 info
->altivec_save_offset
+ ptr_off
,
23526 0, V4SImode
, SAVRES_SAVE
| SAVRES_VR
);
23527 rs6000_frame_related (insn
, scratch_reg
, sp_off
- ptr_off
,
23528 NULL_RTX
, NULL_RTX
, NULL_RTX
);
23529 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
23531 /* The oddity mentioned above clobbered our frame reg. */
23532 emit_move_insn (frame_reg_rtx
, ptr_reg
);
23533 frame_off
= ptr_off
;
23536 else if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
23537 && info
->altivec_size
!= 0)
23541 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
23542 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
23544 rtx areg
, savereg
, mem
, split_reg
;
23547 offset
= (info
->altivec_save_offset
+ frame_off
23548 + 16 * (i
- info
->first_altivec_reg_save
));
23550 savereg
= gen_rtx_REG (V4SImode
, i
);
23553 areg
= gen_rtx_REG (Pmode
, 0);
23554 emit_move_insn (areg
, GEN_INT (offset
));
23556 /* AltiVec addressing mode is [reg+reg]. */
23557 mem
= gen_frame_mem (V4SImode
,
23558 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
));
23560 insn
= emit_move_insn (mem
, savereg
);
23562 /* When we split a VSX store into two insns, we need to make
23563 sure the DWARF info knows which register we are storing.
23564 Pass it in to be used on the appropriate note. */
23565 if (!BYTES_BIG_ENDIAN
23566 && GET_CODE (PATTERN (insn
)) == SET
23567 && GET_CODE (SET_SRC (PATTERN (insn
))) == VEC_SELECT
)
23568 split_reg
= savereg
;
23570 split_reg
= NULL_RTX
;
23572 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
23573 areg
, GEN_INT (offset
), split_reg
);
23577 /* VRSAVE is a bit vector representing which AltiVec registers
23578 are used. The OS uses this to determine which vector
23579 registers to save on a context switch. We need to save
23580 VRSAVE on the stack frame, add whatever AltiVec registers we
23581 used in this function, and do the corresponding magic in the
23584 if (!WORLD_SAVE_P (info
)
23586 && TARGET_ALTIVEC_VRSAVE
23587 && info
->vrsave_mask
!= 0)
23593 /* Get VRSAVE onto a GPR. Note that ABI_V4 and ABI_DARWIN might
23594 be using r12 as frame_reg_rtx and r11 as the static chain
23595 pointer for nested functions. */
23597 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
23598 && !using_static_chain_p
)
23600 else if (REGNO (frame_reg_rtx
) == 12)
23603 if (using_static_chain_p
)
23607 NOT_INUSE (save_regno
);
23608 reg
= gen_rtx_REG (SImode
, save_regno
);
23609 vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
23611 emit_insn (gen_get_vrsave_internal (reg
));
23613 emit_insn (gen_rtx_SET (VOIDmode
, reg
, vrsave
));
23616 offset
= info
->vrsave_save_offset
+ frame_off
;
23617 insn
= emit_insn (gen_frame_store (reg
, frame_reg_rtx
, offset
));
23619 /* Include the registers in the mask. */
23620 emit_insn (gen_iorsi3 (reg
, reg
, GEN_INT ((int) info
->vrsave_mask
)));
23622 insn
= emit_insn (generate_set_vrsave (reg
, info
, 0));
23625 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
23626 if (!TARGET_SINGLE_PIC_BASE
23627 && ((TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
23628 || (DEFAULT_ABI
== ABI_V4
23629 && (flag_pic
== 1 || (flag_pic
&& TARGET_SECURE_PLT
))
23630 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))))
23632 /* If emit_load_toc_table will use the link register, we need to save
23633 it. We use R12 for this purpose because emit_load_toc_table
23634 can use register 0. This allows us to use a plain 'blr' to return
23635 from the procedure more often. */
23636 int save_LR_around_toc_setup
= (TARGET_ELF
23637 && DEFAULT_ABI
== ABI_V4
23639 && ! info
->lr_save_p
23640 && EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun
)->preds
) > 0);
23641 if (save_LR_around_toc_setup
)
23643 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
23644 rtx tmp
= gen_rtx_REG (Pmode
, 12);
23646 insn
= emit_move_insn (tmp
, lr
);
23647 RTX_FRAME_RELATED_P (insn
) = 1;
23649 rs6000_emit_load_toc_table (TRUE
);
23651 insn
= emit_move_insn (lr
, tmp
);
23652 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
23653 RTX_FRAME_RELATED_P (insn
) = 1;
23656 rs6000_emit_load_toc_table (TRUE
);
23660 if (!TARGET_SINGLE_PIC_BASE
23661 && DEFAULT_ABI
== ABI_DARWIN
23662 && flag_pic
&& crtl
->uses_pic_offset_table
)
23664 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
23665 rtx src
= gen_rtx_SYMBOL_REF (Pmode
, MACHOPIC_FUNCTION_BASE_NAME
);
23667 /* Save and restore LR locally around this call (in R0). */
23668 if (!info
->lr_save_p
)
23669 emit_move_insn (gen_rtx_REG (Pmode
, 0), lr
);
23671 emit_insn (gen_load_macho_picbase (src
));
23673 emit_move_insn (gen_rtx_REG (Pmode
,
23674 RS6000_PIC_OFFSET_TABLE_REGNUM
),
23677 if (!info
->lr_save_p
)
23678 emit_move_insn (lr
, gen_rtx_REG (Pmode
, 0));
23682 /* If we need to, save the TOC register after doing the stack setup.
23683 Do not emit eh frame info for this save. The unwinder wants info,
23684 conceptually attached to instructions in this function, about
23685 register values in the caller of this function. This R2 may have
23686 already been changed from the value in the caller.
23687 We don't attempt to write accurate DWARF EH frame info for R2
23688 because code emitted by gcc for a (non-pointer) function call
23689 doesn't save and restore R2. Instead, R2 is managed out-of-line
23690 by a linker generated plt call stub when the function resides in
23691 a shared library. This behaviour is costly to describe in DWARF,
23692 both in terms of the size of DWARF info and the time taken in the
23693 unwinder to interpret it. R2 changes, apart from the
23694 calls_eh_return case earlier in this function, are handled by
23695 linux-unwind.h frob_update_context. */
23696 if (rs6000_save_toc_in_prologue_p ())
23698 rtx reg
= gen_rtx_REG (reg_mode
, TOC_REGNUM
);
23699 emit_insn (gen_frame_store (reg
, sp_reg_rtx
, RS6000_TOC_SAVE_SLOT
));
23703 /* Write function prologue. */
23706 rs6000_output_function_prologue (FILE *file
,
23707 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
23709 rs6000_stack_t
*info
= rs6000_stack_info ();
23711 if (TARGET_DEBUG_STACK
)
23712 debug_stack_info (info
);
23714 /* Write .extern for any function we will call to save and restore
23716 if (info
->first_fp_reg_save
< 64
23721 int regno
= info
->first_fp_reg_save
- 32;
23723 if ((info
->savres_strategy
& SAVE_INLINE_FPRS
) == 0)
23725 bool lr
= (info
->savres_strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
23726 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
23727 name
= rs6000_savres_routine_name (info
, regno
, sel
);
23728 fprintf (file
, "\t.extern %s\n", name
);
23730 if ((info
->savres_strategy
& REST_INLINE_FPRS
) == 0)
23732 bool lr
= (info
->savres_strategy
23733 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
23734 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
23735 name
= rs6000_savres_routine_name (info
, regno
, sel
);
23736 fprintf (file
, "\t.extern %s\n", name
);
23740 /* ELFv2 ABI r2 setup code and local entry point. This must follow
23741 immediately after the global entry point label. */
23742 if (DEFAULT_ABI
== ABI_ELFv2
&& cfun
->machine
->r2_setup_needed
)
23744 const char *name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
23746 fprintf (file
, "0:\taddis 2,12,.TOC.-0b@ha\n");
23747 fprintf (file
, "\taddi 2,2,.TOC.-0b@l\n");
23749 fputs ("\t.localentry\t", file
);
23750 assemble_name (file
, name
);
23751 fputs (",.-", file
);
23752 assemble_name (file
, name
);
23753 fputs ("\n", file
);
23756 /* Output -mprofile-kernel code. This needs to be done here instead of
23757 in output_function_profile since it must go after the ELFv2 ABI
23758 local entry point. */
23759 if (TARGET_PROFILE_KERNEL
&& crtl
->profile
)
23761 gcc_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
23762 gcc_assert (!TARGET_32BIT
);
23764 asm_fprintf (file
, "\tmflr %s\n", reg_names
[0]);
23765 asm_fprintf (file
, "\tstd %s,16(%s)\n", reg_names
[0], reg_names
[1]);
23767 /* In the ELFv2 ABI we have no compiler stack word. It must be
23768 the resposibility of _mcount to preserve the static chain
23769 register if required. */
23770 if (DEFAULT_ABI
!= ABI_ELFv2
23771 && cfun
->static_chain_decl
!= NULL
)
23773 asm_fprintf (file
, "\tstd %s,24(%s)\n",
23774 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
23775 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
23776 asm_fprintf (file
, "\tld %s,24(%s)\n",
23777 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
23780 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
23783 rs6000_pic_labelno
++;
23786 /* Non-zero if vmx regs are restored before the frame pop, zero if
23787 we restore after the pop when possible. */
23788 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
23790 /* Restoring cr is a two step process: loading a reg from the frame
23791 save, then moving the reg to cr. For ABI_V4 we must let the
23792 unwinder know that the stack location is no longer valid at or
23793 before the stack deallocation, but we can't emit a cfa_restore for
23794 cr at the stack deallocation like we do for other registers.
23795 The trouble is that it is possible for the move to cr to be
23796 scheduled after the stack deallocation. So say exactly where cr
23797 is located on each of the two insns. */
23800 load_cr_save (int regno
, rtx frame_reg_rtx
, int offset
, bool exit_func
)
23802 rtx mem
= gen_frame_mem_offset (SImode
, frame_reg_rtx
, offset
);
23803 rtx reg
= gen_rtx_REG (SImode
, regno
);
23804 rtx insn
= emit_move_insn (reg
, mem
);
23806 if (!exit_func
&& DEFAULT_ABI
== ABI_V4
)
23808 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
23809 rtx set
= gen_rtx_SET (VOIDmode
, reg
, cr
);
23811 add_reg_note (insn
, REG_CFA_REGISTER
, set
);
23812 RTX_FRAME_RELATED_P (insn
) = 1;
23817 /* Reload CR from REG. */
23820 restore_saved_cr (rtx reg
, int using_mfcr_multiple
, bool exit_func
)
23825 if (using_mfcr_multiple
)
23827 for (i
= 0; i
< 8; i
++)
23828 if (save_reg_p (CR0_REGNO
+ i
))
23830 gcc_assert (count
);
23833 if (using_mfcr_multiple
&& count
> 1)
23839 p
= rtvec_alloc (count
);
23842 for (i
= 0; i
< 8; i
++)
23843 if (save_reg_p (CR0_REGNO
+ i
))
23845 rtvec r
= rtvec_alloc (2);
23846 RTVEC_ELT (r
, 0) = reg
;
23847 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7-i
));
23848 RTVEC_ELT (p
, ndx
) =
23849 gen_rtx_SET (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
),
23850 gen_rtx_UNSPEC (CCmode
, r
, UNSPEC_MOVESI_TO_CR
));
23853 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
23854 gcc_assert (ndx
== count
);
23856 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
23857 CR field separately. */
23858 if (!exit_func
&& DEFAULT_ABI
== ABI_ELFv2
&& flag_shrink_wrap
)
23860 for (i
= 0; i
< 8; i
++)
23861 if (save_reg_p (CR0_REGNO
+ i
))
23862 add_reg_note (insn
, REG_CFA_RESTORE
,
23863 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
23865 RTX_FRAME_RELATED_P (insn
) = 1;
23869 for (i
= 0; i
< 8; i
++)
23870 if (save_reg_p (CR0_REGNO
+ i
))
23872 rtx insn
= emit_insn (gen_movsi_to_cr_one
23873 (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
), reg
));
23875 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
23876 CR field separately, attached to the insn that in fact
23877 restores this particular CR field. */
23878 if (!exit_func
&& DEFAULT_ABI
== ABI_ELFv2
&& flag_shrink_wrap
)
23880 add_reg_note (insn
, REG_CFA_RESTORE
,
23881 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
23883 RTX_FRAME_RELATED_P (insn
) = 1;
23887 /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */
23888 if (!exit_func
&& DEFAULT_ABI
!= ABI_ELFv2
23889 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
23891 rtx insn
= get_last_insn ();
23892 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
23894 add_reg_note (insn
, REG_CFA_RESTORE
, cr
);
23895 RTX_FRAME_RELATED_P (insn
) = 1;
23899 /* Like cr, the move to lr instruction can be scheduled after the
23900 stack deallocation, but unlike cr, its stack frame save is still
23901 valid. So we only need to emit the cfa_restore on the correct
23905 load_lr_save (int regno
, rtx frame_reg_rtx
, int offset
)
23907 rtx mem
= gen_frame_mem_offset (Pmode
, frame_reg_rtx
, offset
);
23908 rtx reg
= gen_rtx_REG (Pmode
, regno
);
23910 emit_move_insn (reg
, mem
);
23914 restore_saved_lr (int regno
, bool exit_func
)
23916 rtx reg
= gen_rtx_REG (Pmode
, regno
);
23917 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
23918 rtx insn
= emit_move_insn (lr
, reg
);
23920 if (!exit_func
&& flag_shrink_wrap
)
23922 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
23923 RTX_FRAME_RELATED_P (insn
) = 1;
23928 add_crlr_cfa_restore (const rs6000_stack_t
*info
, rtx cfa_restores
)
23930 if (DEFAULT_ABI
== ABI_ELFv2
)
23933 for (i
= 0; i
< 8; i
++)
23934 if (save_reg_p (CR0_REGNO
+ i
))
23936 rtx cr
= gen_rtx_REG (SImode
, CR0_REGNO
+ i
);
23937 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, cr
,
23941 else if (info
->cr_save_p
)
23942 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
23943 gen_rtx_REG (SImode
, CR2_REGNO
),
23946 if (info
->lr_save_p
)
23947 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
23948 gen_rtx_REG (Pmode
, LR_REGNO
),
23950 return cfa_restores
;
23953 /* Return true if OFFSET from stack pointer can be clobbered by signals.
23954 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
23955 below stack pointer not cloberred by signals. */
23958 offset_below_red_zone_p (HOST_WIDE_INT offset
)
23960 return offset
< (DEFAULT_ABI
== ABI_V4
23962 : TARGET_32BIT
? -220 : -288);
23965 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
23968 emit_cfa_restores (rtx cfa_restores
)
23970 rtx insn
= get_last_insn ();
23971 rtx
*loc
= ®_NOTES (insn
);
23974 loc
= &XEXP (*loc
, 1);
23975 *loc
= cfa_restores
;
23976 RTX_FRAME_RELATED_P (insn
) = 1;
23979 /* Emit function epilogue as insns. */
23982 rs6000_emit_epilogue (int sibcall
)
23984 rs6000_stack_t
*info
;
23985 int restoring_GPRs_inline
;
23986 int restoring_FPRs_inline
;
23987 int using_load_multiple
;
23988 int using_mtcr_multiple
;
23989 int use_backchain_to_restore_sp
;
23992 HOST_WIDE_INT frame_off
= 0;
23993 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, 1);
23994 rtx frame_reg_rtx
= sp_reg_rtx
;
23995 rtx cfa_restores
= NULL_RTX
;
23997 rtx cr_save_reg
= NULL_RTX
;
23998 enum machine_mode reg_mode
= Pmode
;
23999 int reg_size
= TARGET_32BIT
? 4 : 8;
24002 unsigned ptr_regno
;
24004 info
= rs6000_stack_info ();
24006 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
24008 reg_mode
= V2SImode
;
24012 strategy
= info
->savres_strategy
;
24013 using_load_multiple
= strategy
& SAVRES_MULTIPLE
;
24014 restoring_FPRs_inline
= sibcall
|| (strategy
& REST_INLINE_FPRS
);
24015 restoring_GPRs_inline
= sibcall
|| (strategy
& REST_INLINE_GPRS
);
24016 using_mtcr_multiple
= (rs6000_cpu
== PROCESSOR_PPC601
24017 || rs6000_cpu
== PROCESSOR_PPC603
24018 || rs6000_cpu
== PROCESSOR_PPC750
24020 /* Restore via the backchain when we have a large frame, since this
24021 is more efficient than an addis, addi pair. The second condition
24022 here will not trigger at the moment; We don't actually need a
24023 frame pointer for alloca, but the generic parts of the compiler
24024 give us one anyway. */
24025 use_backchain_to_restore_sp
= (info
->total_size
> 32767 - info
->lr_save_offset
24026 || (cfun
->calls_alloca
24027 && !frame_pointer_needed
));
24028 restore_lr
= (info
->lr_save_p
24029 && (restoring_FPRs_inline
24030 || (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
))
24031 && (restoring_GPRs_inline
24032 || info
->first_fp_reg_save
< 64));
24034 if (WORLD_SAVE_P (info
))
24038 const char *alloc_rname
;
24041 /* eh_rest_world_r10 will return to the location saved in the LR
24042 stack slot (which is not likely to be our caller.)
24043 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
24044 rest_world is similar, except any R10 parameter is ignored.
24045 The exception-handling stuff that was here in 2.95 is no
24046 longer necessary. */
24050 + 32 - info
->first_gp_reg_save
24051 + LAST_ALTIVEC_REGNO
+ 1 - info
->first_altivec_reg_save
24052 + 63 + 1 - info
->first_fp_reg_save
);
24054 strcpy (rname
, ((crtl
->calls_eh_return
) ?
24055 "*eh_rest_world_r10" : "*rest_world"));
24056 alloc_rname
= ggc_strdup (rname
);
24059 RTVEC_ELT (p
, j
++) = ret_rtx
;
24060 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
24061 gen_rtx_REG (Pmode
,
24064 = gen_rtx_USE (VOIDmode
, gen_rtx_SYMBOL_REF (Pmode
, alloc_rname
));
24065 /* The instruction pattern requires a clobber here;
24066 it is shared with the restVEC helper. */
24068 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 11));
24071 /* CR register traditionally saved as CR2. */
24072 rtx reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
24074 = gen_frame_load (reg
, frame_reg_rtx
, info
->cr_save_offset
);
24075 if (flag_shrink_wrap
)
24077 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
24078 gen_rtx_REG (Pmode
, LR_REGNO
),
24080 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24084 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
24086 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
24088 = gen_frame_load (reg
,
24089 frame_reg_rtx
, info
->gp_save_offset
+ reg_size
* i
);
24090 if (flag_shrink_wrap
)
24091 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24093 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
24095 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
24097 = gen_frame_load (reg
,
24098 frame_reg_rtx
, info
->altivec_save_offset
+ 16 * i
);
24099 if (flag_shrink_wrap
)
24100 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24102 for (i
= 0; info
->first_fp_reg_save
+ i
<= 63; i
++)
24104 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
24105 ? DFmode
: SFmode
),
24106 info
->first_fp_reg_save
+ i
);
24108 = gen_frame_load (reg
, frame_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
24109 if (flag_shrink_wrap
)
24110 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24113 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 0));
24115 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 12));
24117 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 7));
24119 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 8));
24121 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, 10));
24122 insn
= emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
24124 if (flag_shrink_wrap
)
24126 REG_NOTES (insn
) = cfa_restores
;
24127 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
24128 RTX_FRAME_RELATED_P (insn
) = 1;
24133 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
24135 frame_off
= info
->total_size
;
24137 /* Restore AltiVec registers if we must do so before adjusting the
24139 if (TARGET_ALTIVEC_ABI
24140 && info
->altivec_size
!= 0
24141 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
24142 || (DEFAULT_ABI
!= ABI_V4
24143 && offset_below_red_zone_p (info
->altivec_save_offset
))))
24146 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
24148 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
24149 if (use_backchain_to_restore_sp
)
24151 int frame_regno
= 11;
24153 if ((strategy
& REST_INLINE_VRS
) == 0)
24155 /* Of r11 and r12, select the one not clobbered by an
24156 out-of-line restore function for the frame register. */
24157 frame_regno
= 11 + 12 - scratch_regno
;
24159 frame_reg_rtx
= gen_rtx_REG (Pmode
, frame_regno
);
24160 emit_move_insn (frame_reg_rtx
,
24161 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
24164 else if (frame_pointer_needed
)
24165 frame_reg_rtx
= hard_frame_pointer_rtx
;
24167 if ((strategy
& REST_INLINE_VRS
) == 0)
24169 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
24171 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
24172 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
24174 if (end_save
+ frame_off
!= 0)
24176 rtx offset
= GEN_INT (end_save
+ frame_off
);
24178 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
24181 emit_move_insn (ptr_reg
, frame_reg_rtx
);
24183 ptr_off
= -end_save
;
24184 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
24185 info
->altivec_save_offset
+ ptr_off
,
24186 0, V4SImode
, SAVRES_VR
);
24190 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
24191 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
24193 rtx addr
, areg
, mem
, reg
;
24195 areg
= gen_rtx_REG (Pmode
, 0);
24197 (areg
, GEN_INT (info
->altivec_save_offset
24199 + 16 * (i
- info
->first_altivec_reg_save
)));
24201 /* AltiVec addressing mode is [reg+reg]. */
24202 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
24203 mem
= gen_frame_mem (V4SImode
, addr
);
24205 reg
= gen_rtx_REG (V4SImode
, i
);
24206 emit_move_insn (reg
, mem
);
24210 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
24211 if (((strategy
& REST_INLINE_VRS
) == 0
24212 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
24213 && (flag_shrink_wrap
24214 || (offset_below_red_zone_p
24215 (info
->altivec_save_offset
24216 + 16 * (i
- info
->first_altivec_reg_save
)))))
24218 rtx reg
= gen_rtx_REG (V4SImode
, i
);
24219 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24223 /* Restore VRSAVE if we must do so before adjusting the stack. */
24225 && TARGET_ALTIVEC_VRSAVE
24226 && info
->vrsave_mask
!= 0
24227 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
24228 || (DEFAULT_ABI
!= ABI_V4
24229 && offset_below_red_zone_p (info
->vrsave_save_offset
))))
24233 if (frame_reg_rtx
== sp_reg_rtx
)
24235 if (use_backchain_to_restore_sp
)
24237 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
24238 emit_move_insn (frame_reg_rtx
,
24239 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
24242 else if (frame_pointer_needed
)
24243 frame_reg_rtx
= hard_frame_pointer_rtx
;
24246 reg
= gen_rtx_REG (SImode
, 12);
24247 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
24248 info
->vrsave_save_offset
+ frame_off
));
24250 emit_insn (generate_set_vrsave (reg
, info
, 1));
24254 /* If we have a large stack frame, restore the old stack pointer
24255 using the backchain. */
24256 if (use_backchain_to_restore_sp
)
24258 if (frame_reg_rtx
== sp_reg_rtx
)
24260 /* Under V.4, don't reset the stack pointer until after we're done
24261 loading the saved registers. */
24262 if (DEFAULT_ABI
== ABI_V4
)
24263 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
24265 insn
= emit_move_insn (frame_reg_rtx
,
24266 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
24269 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
24270 && DEFAULT_ABI
== ABI_V4
)
24271 /* frame_reg_rtx has been set up by the altivec restore. */
24275 insn
= emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
24276 frame_reg_rtx
= sp_reg_rtx
;
24279 /* If we have a frame pointer, we can restore the old stack pointer
24281 else if (frame_pointer_needed
)
24283 frame_reg_rtx
= sp_reg_rtx
;
24284 if (DEFAULT_ABI
== ABI_V4
)
24285 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
24286 /* Prevent reordering memory accesses against stack pointer restore. */
24287 else if (cfun
->calls_alloca
24288 || offset_below_red_zone_p (-info
->total_size
))
24289 rs6000_emit_stack_tie (frame_reg_rtx
, true);
24291 insn
= emit_insn (gen_add3_insn (frame_reg_rtx
, hard_frame_pointer_rtx
,
24292 GEN_INT (info
->total_size
)));
24295 else if (info
->push_p
24296 && DEFAULT_ABI
!= ABI_V4
24297 && !crtl
->calls_eh_return
)
24299 /* Prevent reordering memory accesses against stack pointer restore. */
24300 if (cfun
->calls_alloca
24301 || offset_below_red_zone_p (-info
->total_size
))
24302 rs6000_emit_stack_tie (frame_reg_rtx
, false);
24303 insn
= emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
,
24304 GEN_INT (info
->total_size
)));
24307 if (insn
&& frame_reg_rtx
== sp_reg_rtx
)
24311 REG_NOTES (insn
) = cfa_restores
;
24312 cfa_restores
= NULL_RTX
;
24314 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
24315 RTX_FRAME_RELATED_P (insn
) = 1;
24318 /* Restore AltiVec registers if we have not done so already. */
24319 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
24320 && TARGET_ALTIVEC_ABI
24321 && info
->altivec_size
!= 0
24322 && (DEFAULT_ABI
== ABI_V4
24323 || !offset_below_red_zone_p (info
->altivec_save_offset
)))
24327 if ((strategy
& REST_INLINE_VRS
) == 0)
24329 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
24331 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
24332 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
24333 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
24335 if (end_save
+ frame_off
!= 0)
24337 rtx offset
= GEN_INT (end_save
+ frame_off
);
24339 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
24342 emit_move_insn (ptr_reg
, frame_reg_rtx
);
24344 ptr_off
= -end_save
;
24345 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
24346 info
->altivec_save_offset
+ ptr_off
,
24347 0, V4SImode
, SAVRES_VR
);
24348 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
24350 /* Frame reg was clobbered by out-of-line save. Restore it
24351 from ptr_reg, and if we are calling out-of-line gpr or
24352 fpr restore set up the correct pointer and offset. */
24353 unsigned newptr_regno
= 1;
24354 if (!restoring_GPRs_inline
)
24356 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
24357 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
24358 newptr_regno
= ptr_regno_for_savres (sel
);
24359 end_save
= info
->gp_save_offset
+ info
->gp_size
;
24361 else if (!restoring_FPRs_inline
)
24363 bool lr
= !(strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
);
24364 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
24365 newptr_regno
= ptr_regno_for_savres (sel
);
24366 end_save
= info
->gp_save_offset
+ info
->gp_size
;
24369 if (newptr_regno
!= 1 && REGNO (frame_reg_rtx
) != newptr_regno
)
24370 frame_reg_rtx
= gen_rtx_REG (Pmode
, newptr_regno
);
24372 if (end_save
+ ptr_off
!= 0)
24374 rtx offset
= GEN_INT (end_save
+ ptr_off
);
24376 frame_off
= -end_save
;
24377 emit_insn (gen_add3_insn (frame_reg_rtx
, ptr_reg
, offset
));
24381 frame_off
= ptr_off
;
24382 emit_move_insn (frame_reg_rtx
, ptr_reg
);
24388 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
24389 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
24391 rtx addr
, areg
, mem
, reg
;
24393 areg
= gen_rtx_REG (Pmode
, 0);
24395 (areg
, GEN_INT (info
->altivec_save_offset
24397 + 16 * (i
- info
->first_altivec_reg_save
)));
24399 /* AltiVec addressing mode is [reg+reg]. */
24400 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
24401 mem
= gen_frame_mem (V4SImode
, addr
);
24403 reg
= gen_rtx_REG (V4SImode
, i
);
24404 emit_move_insn (reg
, mem
);
24408 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
24409 if (((strategy
& REST_INLINE_VRS
) == 0
24410 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
24411 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
24413 rtx reg
= gen_rtx_REG (V4SImode
, i
);
24414 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24418 /* Restore VRSAVE if we have not done so already. */
24419 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
24421 && TARGET_ALTIVEC_VRSAVE
24422 && info
->vrsave_mask
!= 0
24423 && (DEFAULT_ABI
== ABI_V4
24424 || !offset_below_red_zone_p (info
->vrsave_save_offset
)))
24428 reg
= gen_rtx_REG (SImode
, 12);
24429 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
24430 info
->vrsave_save_offset
+ frame_off
));
24432 emit_insn (generate_set_vrsave (reg
, info
, 1));
24435 /* If we exit by an out-of-line restore function on ABI_V4 then that
24436 function will deallocate the stack, so we don't need to worry
24437 about the unwinder restoring cr from an invalid stack frame
24439 exit_func
= (!restoring_FPRs_inline
24440 || (!restoring_GPRs_inline
24441 && info
->first_fp_reg_save
== 64));
24443 /* In the ELFv2 ABI we need to restore all call-saved CR fields from
24444 *separate* slots if the routine calls __builtin_eh_return, so
24445 that they can be independently restored by the unwinder. */
24446 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
24448 int i
, cr_off
= info
->ehcr_offset
;
24450 for (i
= 0; i
< 8; i
++)
24451 if (!call_used_regs
[CR0_REGNO
+ i
])
24453 rtx reg
= gen_rtx_REG (SImode
, 0);
24454 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
24455 cr_off
+ frame_off
));
24457 insn
= emit_insn (gen_movsi_to_cr_one
24458 (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
), reg
));
24460 if (!exit_func
&& flag_shrink_wrap
)
24462 add_reg_note (insn
, REG_CFA_RESTORE
,
24463 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
24465 RTX_FRAME_RELATED_P (insn
) = 1;
24468 cr_off
+= reg_size
;
24472 /* Get the old lr if we saved it. If we are restoring registers
24473 out-of-line, then the out-of-line routines can do this for us. */
24474 if (restore_lr
&& restoring_GPRs_inline
)
24475 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
24477 /* Get the old cr if we saved it. */
24478 if (info
->cr_save_p
)
24480 unsigned cr_save_regno
= 12;
24482 if (!restoring_GPRs_inline
)
24484 /* Ensure we don't use the register used by the out-of-line
24485 gpr register restore below. */
24486 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
24487 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
24488 int gpr_ptr_regno
= ptr_regno_for_savres (sel
);
24490 if (gpr_ptr_regno
== 12)
24491 cr_save_regno
= 11;
24492 gcc_checking_assert (REGNO (frame_reg_rtx
) != cr_save_regno
);
24494 else if (REGNO (frame_reg_rtx
) == 12)
24495 cr_save_regno
= 11;
24497 cr_save_reg
= load_cr_save (cr_save_regno
, frame_reg_rtx
,
24498 info
->cr_save_offset
+ frame_off
,
24502 /* Set LR here to try to overlap restores below. */
24503 if (restore_lr
&& restoring_GPRs_inline
)
24504 restore_saved_lr (0, exit_func
);
24506 /* Load exception handler data registers, if needed. */
24507 if (crtl
->calls_eh_return
)
24509 unsigned int i
, regno
;
24513 rtx reg
= gen_rtx_REG (reg_mode
, 2);
24514 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
24515 frame_off
+ RS6000_TOC_SAVE_SLOT
));
24522 regno
= EH_RETURN_DATA_REGNO (i
);
24523 if (regno
== INVALID_REGNUM
)
24526 /* Note: possible use of r0 here to address SPE regs. */
24527 mem
= gen_frame_mem_offset (reg_mode
, frame_reg_rtx
,
24528 info
->ehrd_offset
+ frame_off
24529 + reg_size
* (int) i
);
24531 emit_move_insn (gen_rtx_REG (reg_mode
, regno
), mem
);
24535 /* Restore GPRs. This is done as a PARALLEL if we are using
24536 the load-multiple instructions. */
24538 && info
->spe_64bit_regs_used
24539 && info
->first_gp_reg_save
!= 32)
24541 /* Determine whether we can address all of the registers that need
24542 to be saved with an offset from frame_reg_rtx that fits in
24543 the small const field for SPE memory instructions. */
24544 int spe_regs_addressable
24545 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ frame_off
24546 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
24547 && restoring_GPRs_inline
);
24549 if (!spe_regs_addressable
)
24551 int ool_adjust
= 0;
24552 rtx old_frame_reg_rtx
= frame_reg_rtx
;
24553 /* Make r11 point to the start of the SPE save area. We worried about
24554 not clobbering it when we were saving registers in the prologue.
24555 There's no need to worry here because the static chain is passed
24556 anew to every function. */
24558 if (!restoring_GPRs_inline
)
24559 ool_adjust
= 8 * (info
->first_gp_reg_save
- FIRST_SAVED_GP_REGNO
);
24560 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
24561 emit_insn (gen_addsi3 (frame_reg_rtx
, old_frame_reg_rtx
,
24562 GEN_INT (info
->spe_gp_save_offset
24565 /* Keep the invariant that frame_reg_rtx + frame_off points
24566 at the top of the stack frame. */
24567 frame_off
= -info
->spe_gp_save_offset
+ ool_adjust
;
24570 if (restoring_GPRs_inline
)
24572 HOST_WIDE_INT spe_offset
= info
->spe_gp_save_offset
+ frame_off
;
24574 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
24575 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
24577 rtx offset
, addr
, mem
, reg
;
24579 /* We're doing all this to ensure that the immediate offset
24580 fits into the immediate field of 'evldd'. */
24581 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset
+ reg_size
* i
));
24583 offset
= GEN_INT (spe_offset
+ reg_size
* i
);
24584 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, offset
);
24585 mem
= gen_rtx_MEM (V2SImode
, addr
);
24586 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
24588 emit_move_insn (reg
, mem
);
24592 rs6000_emit_savres_rtx (info
, frame_reg_rtx
,
24593 info
->spe_gp_save_offset
+ frame_off
,
24594 info
->lr_save_offset
+ frame_off
,
24596 SAVRES_GPR
| SAVRES_LR
);
24598 else if (!restoring_GPRs_inline
)
24600 /* We are jumping to an out-of-line function. */
24602 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
24603 bool can_use_exit
= end_save
== 0;
24604 int sel
= SAVRES_GPR
| (can_use_exit
? SAVRES_LR
: 0);
24607 /* Emit stack reset code if we need it. */
24608 ptr_regno
= ptr_regno_for_savres (sel
);
24609 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
24611 rs6000_emit_stack_reset (info
, frame_reg_rtx
, frame_off
, ptr_regno
);
24612 else if (end_save
+ frame_off
!= 0)
24613 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
,
24614 GEN_INT (end_save
+ frame_off
)));
24615 else if (REGNO (frame_reg_rtx
) != ptr_regno
)
24616 emit_move_insn (ptr_reg
, frame_reg_rtx
);
24617 if (REGNO (frame_reg_rtx
) == ptr_regno
)
24618 frame_off
= -end_save
;
24620 if (can_use_exit
&& info
->cr_save_p
)
24621 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, true);
24623 ptr_off
= -end_save
;
24624 rs6000_emit_savres_rtx (info
, ptr_reg
,
24625 info
->gp_save_offset
+ ptr_off
,
24626 info
->lr_save_offset
+ ptr_off
,
24629 else if (using_load_multiple
)
24632 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
24633 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
24635 = gen_frame_load (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
24637 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
24638 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
24642 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
24643 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
24644 emit_insn (gen_frame_load
24645 (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
24647 info
->gp_save_offset
+ frame_off
+ reg_size
* i
));
24650 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
24652 /* If the frame pointer was used then we can't delay emitting
24653 a REG_CFA_DEF_CFA note. This must happen on the insn that
24654 restores the frame pointer, r31. We may have already emitted
24655 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
24656 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
24657 be harmless if emitted. */
24658 if (frame_pointer_needed
)
24660 insn
= get_last_insn ();
24661 add_reg_note (insn
, REG_CFA_DEF_CFA
,
24662 plus_constant (Pmode
, frame_reg_rtx
, frame_off
));
24663 RTX_FRAME_RELATED_P (insn
) = 1;
24666 /* Set up cfa_restores. We always need these when
24667 shrink-wrapping. If not shrink-wrapping then we only need
24668 the cfa_restore when the stack location is no longer valid.
24669 The cfa_restores must be emitted on or before the insn that
24670 invalidates the stack, and of course must not be emitted
24671 before the insn that actually does the restore. The latter
24672 is why it is a bad idea to emit the cfa_restores as a group
24673 on the last instruction here that actually does a restore:
24674 That insn may be reordered with respect to others doing
24676 if (flag_shrink_wrap
24677 && !restoring_GPRs_inline
24678 && info
->first_fp_reg_save
== 64)
24679 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
24681 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
24682 if (!restoring_GPRs_inline
24683 || using_load_multiple
24684 || rs6000_reg_live_or_pic_offset_p (i
))
24686 rtx reg
= gen_rtx_REG (reg_mode
, i
);
24688 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24692 if (!restoring_GPRs_inline
24693 && info
->first_fp_reg_save
== 64)
24695 /* We are jumping to an out-of-line function. */
24697 emit_cfa_restores (cfa_restores
);
24701 if (restore_lr
&& !restoring_GPRs_inline
)
24703 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
24704 restore_saved_lr (0, exit_func
);
24707 /* Restore fpr's if we need to do it without calling a function. */
24708 if (restoring_FPRs_inline
)
24709 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
24710 if (save_reg_p (info
->first_fp_reg_save
+ i
))
24712 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
24713 ? DFmode
: SFmode
),
24714 info
->first_fp_reg_save
+ i
);
24715 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
24716 info
->fp_save_offset
+ frame_off
+ 8 * i
));
24717 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
24718 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24721 /* If we saved cr, restore it here. Just those that were used. */
24722 if (info
->cr_save_p
)
24723 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, exit_func
);
24725 /* If this is V.4, unwind the stack pointer after all of the loads
24726 have been done, or set up r11 if we are restoring fp out of line. */
24728 if (!restoring_FPRs_inline
)
24730 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
24731 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
24732 ptr_regno
= ptr_regno_for_savres (sel
);
24735 insn
= rs6000_emit_stack_reset (info
, frame_reg_rtx
, frame_off
, ptr_regno
);
24736 if (REGNO (frame_reg_rtx
) == ptr_regno
)
24739 if (insn
&& restoring_FPRs_inline
)
24743 REG_NOTES (insn
) = cfa_restores
;
24744 cfa_restores
= NULL_RTX
;
24746 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
24747 RTX_FRAME_RELATED_P (insn
) = 1;
24750 if (crtl
->calls_eh_return
)
24752 rtx sa
= EH_RETURN_STACKADJ_RTX
;
24753 emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
, sa
));
24759 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
24760 if (! restoring_FPRs_inline
)
24762 p
= rtvec_alloc (4 + 64 - info
->first_fp_reg_save
);
24763 RTVEC_ELT (p
, 0) = ret_rtx
;
24769 /* We can't hang the cfa_restores off a simple return,
24770 since the shrink-wrap code sometimes uses an existing
24771 return. This means there might be a path from
24772 pre-prologue code to this return, and dwarf2cfi code
24773 wants the eh_frame unwinder state to be the same on
24774 all paths to any point. So we need to emit the
24775 cfa_restores before the return. For -m64 we really
24776 don't need epilogue cfa_restores at all, except for
24777 this irritating dwarf2cfi with shrink-wrap
24778 requirement; The stack red-zone means eh_frame info
24779 from the prologue telling the unwinder to restore
24780 from the stack is perfectly good right to the end of
24782 emit_insn (gen_blockage ());
24783 emit_cfa_restores (cfa_restores
);
24784 cfa_restores
= NULL_RTX
;
24786 p
= rtvec_alloc (2);
24787 RTVEC_ELT (p
, 0) = simple_return_rtx
;
24790 RTVEC_ELT (p
, 1) = ((restoring_FPRs_inline
|| !lr
)
24791 ? gen_rtx_USE (VOIDmode
,
24792 gen_rtx_REG (Pmode
, LR_REGNO
))
24793 : gen_rtx_CLOBBER (VOIDmode
,
24794 gen_rtx_REG (Pmode
, LR_REGNO
)));
24796 /* If we have to restore more than two FP registers, branch to the
24797 restore function. It will return to our caller. */
24798 if (! restoring_FPRs_inline
)
24804 if (flag_shrink_wrap
)
24805 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
24807 sym
= rs6000_savres_routine_sym (info
,
24808 SAVRES_FPR
| (lr
? SAVRES_LR
: 0));
24809 RTVEC_ELT (p
, 2) = gen_rtx_USE (VOIDmode
, sym
);
24810 reg
= (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)? 1 : 11;
24811 RTVEC_ELT (p
, 3) = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, reg
));
24813 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
24815 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
24817 RTVEC_ELT (p
, i
+ 4)
24818 = gen_frame_load (reg
, sp_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
24819 if (flag_shrink_wrap
)
24820 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
24825 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
24831 /* Ensure the cfa_restores are hung off an insn that won't
24832 be reordered above other restores. */
24833 emit_insn (gen_blockage ());
24835 emit_cfa_restores (cfa_restores
);
24839 /* Write function epilogue. */
24842 rs6000_output_function_epilogue (FILE *file
,
24843 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
24846 macho_branch_islands ();
24847 /* Mach-O doesn't support labels at the end of objects, so if
24848 it looks like we might want one, insert a NOP. */
24850 rtx insn
= get_last_insn ();
24851 rtx deleted_debug_label
= NULL_RTX
;
24854 && NOTE_KIND (insn
) != NOTE_INSN_DELETED_LABEL
)
24856 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
24857 notes only, instead set their CODE_LABEL_NUMBER to -1,
24858 otherwise there would be code generation differences
24859 in between -g and -g0. */
24860 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
24861 deleted_debug_label
= insn
;
24862 insn
= PREV_INSN (insn
);
24867 && NOTE_KIND (insn
) == NOTE_INSN_DELETED_LABEL
)))
24868 fputs ("\tnop\n", file
);
24869 else if (deleted_debug_label
)
24870 for (insn
= deleted_debug_label
; insn
; insn
= NEXT_INSN (insn
))
24871 if (NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
24872 CODE_LABEL_NUMBER (insn
) = -1;
24876 /* Output a traceback table here. See /usr/include/sys/debug.h for info
24879 We don't output a traceback table if -finhibit-size-directive was
24880 used. The documentation for -finhibit-size-directive reads
24881 ``don't output a @code{.size} assembler directive, or anything
24882 else that would cause trouble if the function is split in the
24883 middle, and the two halves are placed at locations far apart in
24884 memory.'' The traceback table has this property, since it
24885 includes the offset from the start of the function to the
24886 traceback table itself.
24888 System V.4 Powerpc's (and the embedded ABI derived from it) use a
24889 different traceback table. */
24890 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
24891 && ! flag_inhibit_size_directive
24892 && rs6000_traceback
!= traceback_none
&& !cfun
->is_thunk
)
24894 const char *fname
= NULL
;
24895 const char *language_string
= lang_hooks
.name
;
24896 int fixed_parms
= 0, float_parms
= 0, parm_info
= 0;
24898 int optional_tbtab
;
24899 rs6000_stack_t
*info
= rs6000_stack_info ();
24901 if (rs6000_traceback
== traceback_full
)
24902 optional_tbtab
= 1;
24903 else if (rs6000_traceback
== traceback_part
)
24904 optional_tbtab
= 0;
24906 optional_tbtab
= !optimize_size
&& !TARGET_ELF
;
24908 if (optional_tbtab
)
24910 fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
24911 while (*fname
== '.') /* V.4 encodes . in the name */
24914 /* Need label immediately before tbtab, so we can compute
24915 its offset from the function start. */
24916 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
24917 ASM_OUTPUT_LABEL (file
, fname
);
24920 /* The .tbtab pseudo-op can only be used for the first eight
24921 expressions, since it can't handle the possibly variable
24922 length fields that follow. However, if you omit the optional
24923 fields, the assembler outputs zeros for all optional fields
24924 anyways, giving each variable length field is minimum length
24925 (as defined in sys/debug.h). Thus we can not use the .tbtab
24926 pseudo-op at all. */
24928 /* An all-zero word flags the start of the tbtab, for debuggers
24929 that have to find it by searching forward from the entry
24930 point or from the current pc. */
24931 fputs ("\t.long 0\n", file
);
24933 /* Tbtab format type. Use format type 0. */
24934 fputs ("\t.byte 0,", file
);
24936 /* Language type. Unfortunately, there does not seem to be any
24937 official way to discover the language being compiled, so we
24938 use language_string.
24939 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
24940 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
24941 a number, so for now use 9. LTO and Go aren't assigned numbers
24942 either, so for now use 0. */
24943 if (! strcmp (language_string
, "GNU C")
24944 || ! strcmp (language_string
, "GNU GIMPLE")
24945 || ! strcmp (language_string
, "GNU Go"))
24947 else if (! strcmp (language_string
, "GNU F77")
24948 || ! strcmp (language_string
, "GNU Fortran"))
24950 else if (! strcmp (language_string
, "GNU Pascal"))
24952 else if (! strcmp (language_string
, "GNU Ada"))
24954 else if (! strcmp (language_string
, "GNU C++")
24955 || ! strcmp (language_string
, "GNU Objective-C++"))
24957 else if (! strcmp (language_string
, "GNU Java"))
24959 else if (! strcmp (language_string
, "GNU Objective-C"))
24962 gcc_unreachable ();
24963 fprintf (file
, "%d,", i
);
24965 /* 8 single bit fields: global linkage (not set for C extern linkage,
24966 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
24967 from start of procedure stored in tbtab, internal function, function
24968 has controlled storage, function has no toc, function uses fp,
24969 function logs/aborts fp operations. */
24970 /* Assume that fp operations are used if any fp reg must be saved. */
24971 fprintf (file
, "%d,",
24972 (optional_tbtab
<< 5) | ((info
->first_fp_reg_save
!= 64) << 1));
24974 /* 6 bitfields: function is interrupt handler, name present in
24975 proc table, function calls alloca, on condition directives
24976 (controls stack walks, 3 bits), saves condition reg, saves
24978 /* The `function calls alloca' bit seems to be set whenever reg 31 is
24979 set up as a frame pointer, even when there is no alloca call. */
24980 fprintf (file
, "%d,",
24981 ((optional_tbtab
<< 6)
24982 | ((optional_tbtab
& frame_pointer_needed
) << 5)
24983 | (info
->cr_save_p
<< 1)
24984 | (info
->lr_save_p
)));
24986 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
24988 fprintf (file
, "%d,",
24989 (info
->push_p
<< 7) | (64 - info
->first_fp_reg_save
));
24991 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
24992 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
24994 if (optional_tbtab
)
24996 /* Compute the parameter info from the function decl argument
24999 int next_parm_info_bit
= 31;
25001 for (decl
= DECL_ARGUMENTS (current_function_decl
);
25002 decl
; decl
= DECL_CHAIN (decl
))
25004 rtx parameter
= DECL_INCOMING_RTL (decl
);
25005 enum machine_mode mode
= GET_MODE (parameter
);
25007 if (GET_CODE (parameter
) == REG
)
25009 if (SCALAR_FLOAT_MODE_P (mode
))
25030 gcc_unreachable ();
25033 /* If only one bit will fit, don't or in this entry. */
25034 if (next_parm_info_bit
> 0)
25035 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
25036 next_parm_info_bit
-= 2;
25040 fixed_parms
+= ((GET_MODE_SIZE (mode
)
25041 + (UNITS_PER_WORD
- 1))
25043 next_parm_info_bit
-= 1;
25049 /* Number of fixed point parameters. */
25050 /* This is actually the number of words of fixed point parameters; thus
25051 an 8 byte struct counts as 2; and thus the maximum value is 8. */
25052 fprintf (file
, "%d,", fixed_parms
);
25054 /* 2 bitfields: number of floating point parameters (7 bits), parameters
25056 /* This is actually the number of fp registers that hold parameters;
25057 and thus the maximum value is 13. */
25058 /* Set parameters on stack bit if parameters are not in their original
25059 registers, regardless of whether they are on the stack? Xlc
25060 seems to set the bit when not optimizing. */
25061 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
25063 if (! optional_tbtab
)
25066 /* Optional fields follow. Some are variable length. */
25068 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
25069 11 double float. */
25070 /* There is an entry for each parameter in a register, in the order that
25071 they occur in the parameter list. Any intervening arguments on the
25072 stack are ignored. If the list overflows a long (max possible length
25073 34 bits) then completely leave off all elements that don't fit. */
25074 /* Only emit this long if there was at least one parameter. */
25075 if (fixed_parms
|| float_parms
)
25076 fprintf (file
, "\t.long %d\n", parm_info
);
25078 /* Offset from start of code to tb table. */
25079 fputs ("\t.long ", file
);
25080 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
25081 RS6000_OUTPUT_BASENAME (file
, fname
);
25083 rs6000_output_function_entry (file
, fname
);
25086 /* Interrupt handler mask. */
25087 /* Omit this long, since we never set the interrupt handler bit
25090 /* Number of CTL (controlled storage) anchors. */
25091 /* Omit this long, since the has_ctl bit is never set above. */
25093 /* Displacement into stack of each CTL anchor. */
25094 /* Omit this list of longs, because there are no CTL anchors. */
25096 /* Length of function name. */
25099 fprintf (file
, "\t.short %d\n", (int) strlen (fname
));
25101 /* Function name. */
25102 assemble_string (fname
, strlen (fname
));
25104 /* Register for alloca automatic storage; this is always reg 31.
25105 Only emit this if the alloca bit was set above. */
25106 if (frame_pointer_needed
)
25107 fputs ("\t.byte 31\n", file
);
25109 fputs ("\t.align 2\n", file
);
25113 /* A C compound statement that outputs the assembler code for a thunk
25114 function, used to implement C++ virtual function calls with
25115 multiple inheritance. The thunk acts as a wrapper around a virtual
25116 function, adjusting the implicit object parameter before handing
25117 control off to the real function.
25119 First, emit code to add the integer DELTA to the location that
25120 contains the incoming first argument. Assume that this argument
25121 contains a pointer, and is the one used to pass the `this' pointer
25122 in C++. This is the incoming argument *before* the function
25123 prologue, e.g. `%o0' on a sparc. The addition must preserve the
25124 values of all other incoming arguments.
25126 After the addition, emit code to jump to FUNCTION, which is a
25127 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
25128 not touch the return address. Hence returning from FUNCTION will
25129 return to whoever called the current `thunk'.
25131 The effect must be as if FUNCTION had been called directly with the
25132 adjusted first argument. This macro is responsible for emitting
25133 all of the code for a thunk function; output_function_prologue()
25134 and output_function_epilogue() are not invoked.
25136 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
25137 been extracted from it.) It might possibly be useful on some
25138 targets, but probably not.
25140 If you do not define this macro, the target-independent code in the
25141 C++ frontend will generate a less efficient heavyweight thunk that
25142 calls FUNCTION instead of jumping to it. The generic approach does
25143 not support varargs. */
25146 rs6000_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
25147 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
25150 rtx this_rtx
, insn
, funexp
;
25152 reload_completed
= 1;
25153 epilogue_completed
= 1;
25155 /* Mark the end of the (empty) prologue. */
25156 emit_note (NOTE_INSN_PROLOGUE_END
);
25158 /* Find the "this" pointer. If the function returns a structure,
25159 the structure return pointer is in r3. */
25160 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
25161 this_rtx
= gen_rtx_REG (Pmode
, 4);
25163 this_rtx
= gen_rtx_REG (Pmode
, 3);
25165 /* Apply the constant offset, if required. */
25167 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, GEN_INT (delta
)));
25169 /* Apply the offset from the vtable, if required. */
25172 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
25173 rtx tmp
= gen_rtx_REG (Pmode
, 12);
25175 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this_rtx
));
25176 if (((unsigned HOST_WIDE_INT
) vcall_offset
) + 0x8000 >= 0x10000)
25178 emit_insn (gen_add3_insn (tmp
, tmp
, vcall_offset_rtx
));
25179 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
25183 rtx loc
= gen_rtx_PLUS (Pmode
, tmp
, vcall_offset_rtx
);
25185 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, loc
));
25187 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, tmp
));
25190 /* Generate a tail call to the target function. */
25191 if (!TREE_USED (function
))
25193 assemble_external (function
);
25194 TREE_USED (function
) = 1;
25196 funexp
= XEXP (DECL_RTL (function
), 0);
25197 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
25200 if (MACHOPIC_INDIRECT
)
25201 funexp
= machopic_indirect_call_target (funexp
);
25204 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
25205 generate sibcall RTL explicitly. */
25206 insn
= emit_call_insn (
25207 gen_rtx_PARALLEL (VOIDmode
,
25209 gen_rtx_CALL (VOIDmode
,
25210 funexp
, const0_rtx
),
25211 gen_rtx_USE (VOIDmode
, const0_rtx
),
25212 gen_rtx_USE (VOIDmode
,
25213 gen_rtx_REG (SImode
,
25215 simple_return_rtx
)));
25216 SIBLING_CALL_P (insn
) = 1;
25219 /* Ensure we have a global entry point for the thunk. ??? We could
25220 avoid that if the target routine doesn't need a global entry point,
25221 but we do not know whether this is the case at this point. */
25222 if (DEFAULT_ABI
== ABI_ELFv2
)
25223 cfun
->machine
->r2_setup_needed
= true;
25225 /* Run just enough of rest_of_compilation to get the insns emitted.
25226 There's not really enough bulk here to make other passes such as
25227 instruction scheduling worth while. Note that use_thunk calls
25228 assemble_start_function and assemble_end_function. */
25229 insn
= get_insns ();
25230 shorten_branches (insn
);
25231 final_start_function (insn
, file
, 1);
25232 final (insn
, file
, 1);
25233 final_end_function ();
25235 reload_completed
= 0;
25236 epilogue_completed
= 0;
25239 /* A quick summary of the various types of 'constant-pool tables'
25242 Target Flags Name One table per
25243 AIX (none) AIX TOC object file
25244 AIX -mfull-toc AIX TOC object file
25245 AIX -mminimal-toc AIX minimal TOC translation unit
25246 SVR4/EABI (none) SVR4 SDATA object file
25247 SVR4/EABI -fpic SVR4 pic object file
25248 SVR4/EABI -fPIC SVR4 PIC translation unit
25249 SVR4/EABI -mrelocatable EABI TOC function
25250 SVR4/EABI -maix AIX TOC object file
25251 SVR4/EABI -maix -mminimal-toc
25252 AIX minimal TOC translation unit
25254 Name Reg. Set by entries contains:
25255 made by addrs? fp? sum?
25257 AIX TOC 2 crt0 as Y option option
25258 AIX minimal TOC 30 prolog gcc Y Y option
25259 SVR4 SDATA 13 crt0 gcc N Y N
25260 SVR4 pic 30 prolog ld Y not yet N
25261 SVR4 PIC 30 prolog gcc Y option option
25262 EABI TOC 30 prolog gcc Y option option
25266 /* Hash functions for the hash table. */
25269 rs6000_hash_constant (rtx k
)
25271 enum rtx_code code
= GET_CODE (k
);
25272 enum machine_mode mode
= GET_MODE (k
);
25273 unsigned result
= (code
<< 3) ^ mode
;
25274 const char *format
;
25277 format
= GET_RTX_FORMAT (code
);
25278 flen
= strlen (format
);
25284 return result
* 1231 + (unsigned) INSN_UID (XEXP (k
, 0));
25286 case CONST_WIDE_INT
:
25289 flen
= CONST_WIDE_INT_NUNITS (k
);
25290 for (i
= 0; i
< flen
; i
++)
25291 result
= result
* 613 + CONST_WIDE_INT_ELT (k
, i
);
25296 if (mode
!= VOIDmode
)
25297 return real_hash (CONST_DOUBLE_REAL_VALUE (k
)) * result
;
25309 for (; fidx
< flen
; fidx
++)
25310 switch (format
[fidx
])
25315 const char *str
= XSTR (k
, fidx
);
25316 len
= strlen (str
);
25317 result
= result
* 613 + len
;
25318 for (i
= 0; i
< len
; i
++)
25319 result
= result
* 613 + (unsigned) str
[i
];
25324 result
= result
* 1231 + rs6000_hash_constant (XEXP (k
, fidx
));
25328 result
= result
* 613 + (unsigned) XINT (k
, fidx
);
25331 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT
))
25332 result
= result
* 613 + (unsigned) XWINT (k
, fidx
);
25336 for (i
= 0; i
< sizeof (HOST_WIDE_INT
) / sizeof (unsigned); i
++)
25337 result
= result
* 613 + (unsigned) (XWINT (k
, fidx
)
25344 gcc_unreachable ();
25351 toc_hash_function (const void *hash_entry
)
25353 const struct toc_hash_struct
*thc
=
25354 (const struct toc_hash_struct
*) hash_entry
;
25355 return rs6000_hash_constant (thc
->key
) ^ thc
->key_mode
;
25358 /* Compare H1 and H2 for equivalence. */
25361 toc_hash_eq (const void *h1
, const void *h2
)
25363 rtx r1
= ((const struct toc_hash_struct
*) h1
)->key
;
25364 rtx r2
= ((const struct toc_hash_struct
*) h2
)->key
;
25366 if (((const struct toc_hash_struct
*) h1
)->key_mode
25367 != ((const struct toc_hash_struct
*) h2
)->key_mode
)
25370 return rtx_equal_p (r1
, r2
);
25373 /* These are the names given by the C++ front-end to vtables, and
25374 vtable-like objects. Ideally, this logic should not be here;
25375 instead, there should be some programmatic way of inquiring as
25376 to whether or not an object is a vtable. */
25378 #define VTABLE_NAME_P(NAME) \
25379 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
25380 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
25381 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
25382 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
25383 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
25385 #ifdef NO_DOLLAR_IN_LABEL
25386 /* Return a GGC-allocated character string translating dollar signs in
25387 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
25390 rs6000_xcoff_strip_dollar (const char *name
)
25396 q
= (const char *) strchr (name
, '$');
25398 if (q
== 0 || q
== name
)
25401 len
= strlen (name
);
25402 strip
= XALLOCAVEC (char, len
+ 1);
25403 strcpy (strip
, name
);
25404 p
= strip
+ (q
- name
);
25408 p
= strchr (p
+ 1, '$');
25411 return ggc_alloc_string (strip
, len
);
25416 rs6000_output_symbol_ref (FILE *file
, rtx x
)
25418 /* Currently C++ toc references to vtables can be emitted before it
25419 is decided whether the vtable is public or private. If this is
25420 the case, then the linker will eventually complain that there is
25421 a reference to an unknown section. Thus, for vtables only,
25422 we emit the TOC reference to reference the symbol and not the
25424 const char *name
= XSTR (x
, 0);
25426 if (VTABLE_NAME_P (name
))
25428 RS6000_OUTPUT_BASENAME (file
, name
);
25431 assemble_name (file
, name
);
25434 /* Output a TOC entry. We derive the entry name from what is being
25438 output_toc (FILE *file
, rtx x
, int labelno
, enum machine_mode mode
)
25441 const char *name
= buf
;
25443 HOST_WIDE_INT offset
= 0;
25445 gcc_assert (!TARGET_NO_TOC
);
25447 /* When the linker won't eliminate them, don't output duplicate
25448 TOC entries (this happens on AIX if there is any kind of TOC,
25449 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
25451 if (TARGET_TOC
&& GET_CODE (x
) != LABEL_REF
)
25453 struct toc_hash_struct
*h
;
25456 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
25457 time because GGC is not initialized at that point. */
25458 if (toc_hash_table
== NULL
)
25459 toc_hash_table
= htab_create_ggc (1021, toc_hash_function
,
25460 toc_hash_eq
, NULL
);
25462 h
= ggc_alloc
<toc_hash_struct
> ();
25464 h
->key_mode
= mode
;
25465 h
->labelno
= labelno
;
25467 found
= htab_find_slot (toc_hash_table
, h
, INSERT
);
25468 if (*found
== NULL
)
25470 else /* This is indeed a duplicate.
25471 Set this label equal to that label. */
25473 fputs ("\t.set ", file
);
25474 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
25475 fprintf (file
, "%d,", labelno
);
25476 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
25477 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
25481 if (TARGET_XCOFF
&& GET_CODE (x
) == SYMBOL_REF
25482 && (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_GLOBAL_DYNAMIC
25483 || SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
))
25485 fputs ("\t.set ", file
);
25486 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
25487 fprintf (file
, "%d,", labelno
);
25488 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
25489 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
25497 /* If we're going to put a double constant in the TOC, make sure it's
25498 aligned properly when strict alignment is on. */
25499 if ((CONST_DOUBLE_P (x
) || CONST_WIDE_INT_P (x
))
25500 && STRICT_ALIGNMENT
25501 && GET_MODE_BITSIZE (mode
) >= 64
25502 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
)) {
25503 ASM_OUTPUT_ALIGN (file
, 3);
25506 (*targetm
.asm_out
.internal_label
) (file
, "LC", labelno
);
25508 /* Handle FP constants specially. Note that if we have a minimal
25509 TOC, things we put here aren't actually in the TOC, so we can allow
25511 if (GET_CODE (x
) == CONST_DOUBLE
&&
25512 (GET_MODE (x
) == TFmode
|| GET_MODE (x
) == TDmode
))
25514 REAL_VALUE_TYPE rv
;
25517 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
25518 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
25519 REAL_VALUE_TO_TARGET_DECIMAL128 (rv
, k
);
25521 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv
, k
);
25525 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25526 fputs (DOUBLE_INT_ASM_OP
, file
);
25528 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
25529 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
25530 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
25531 fprintf (file
, "0x%lx%08lx,0x%lx%08lx\n",
25532 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
25533 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff,
25534 k
[WORDS_BIG_ENDIAN
? 2 : 3] & 0xffffffff,
25535 k
[WORDS_BIG_ENDIAN
? 3 : 2] & 0xffffffff);
25540 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25541 fputs ("\t.long ", file
);
25543 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
25544 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
25545 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
25546 fprintf (file
, "0x%lx,0x%lx,0x%lx,0x%lx\n",
25547 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
25548 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
25552 else if (GET_CODE (x
) == CONST_DOUBLE
&&
25553 (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DDmode
))
25555 REAL_VALUE_TYPE rv
;
25558 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
25560 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
25561 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, k
);
25563 REAL_VALUE_TO_TARGET_DOUBLE (rv
, k
);
25567 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25568 fputs (DOUBLE_INT_ASM_OP
, file
);
25570 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
25571 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
25572 fprintf (file
, "0x%lx%08lx\n",
25573 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
25574 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff);
25579 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25580 fputs ("\t.long ", file
);
25582 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
25583 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
25584 fprintf (file
, "0x%lx,0x%lx\n",
25585 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
25589 else if (GET_CODE (x
) == CONST_DOUBLE
&&
25590 (GET_MODE (x
) == SFmode
|| GET_MODE (x
) == SDmode
))
25592 REAL_VALUE_TYPE rv
;
25595 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
25596 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
25597 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
25599 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
25603 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25604 fputs (DOUBLE_INT_ASM_OP
, file
);
25606 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
25607 if (WORDS_BIG_ENDIAN
)
25608 fprintf (file
, "0x%lx00000000\n", l
& 0xffffffff);
25610 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
25615 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25616 fputs ("\t.long ", file
);
25618 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
25619 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
25623 else if (GET_MODE (x
) == VOIDmode
&& GET_CODE (x
) == CONST_INT
)
25625 unsigned HOST_WIDE_INT low
;
25626 HOST_WIDE_INT high
;
25628 low
= INTVAL (x
) & 0xffffffff;
25629 high
= (HOST_WIDE_INT
) INTVAL (x
) >> 32;
25631 /* TOC entries are always Pmode-sized, so when big-endian
25632 smaller integer constants in the TOC need to be padded.
25633 (This is still a win over putting the constants in
25634 a separate constant pool, because then we'd have
25635 to have both a TOC entry _and_ the actual constant.)
25637 For a 32-bit target, CONST_INT values are loaded and shifted
25638 entirely within `low' and can be stored in one TOC entry. */
25640 /* It would be easy to make this work, but it doesn't now. */
25641 gcc_assert (!TARGET_64BIT
|| POINTER_SIZE
>= GET_MODE_BITSIZE (mode
));
25643 if (WORDS_BIG_ENDIAN
&& POINTER_SIZE
> GET_MODE_BITSIZE (mode
))
25646 low
<<= POINTER_SIZE
- GET_MODE_BITSIZE (mode
);
25647 high
= (HOST_WIDE_INT
) low
>> 32;
25653 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25654 fputs (DOUBLE_INT_ASM_OP
, file
);
25656 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
25657 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
25658 fprintf (file
, "0x%lx%08lx\n",
25659 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
25664 if (POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
25666 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25667 fputs ("\t.long ", file
);
25669 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
25670 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
25671 fprintf (file
, "0x%lx,0x%lx\n",
25672 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
25676 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25677 fputs ("\t.long ", file
);
25679 fprintf (file
, "\t.tc IS_%lx[TC],", (long) low
& 0xffffffff);
25680 fprintf (file
, "0x%lx\n", (long) low
& 0xffffffff);
25686 if (GET_CODE (x
) == CONST
)
25688 gcc_assert (GET_CODE (XEXP (x
, 0)) == PLUS
25689 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
);
25691 base
= XEXP (XEXP (x
, 0), 0);
25692 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
25695 switch (GET_CODE (base
))
25698 name
= XSTR (base
, 0);
25702 ASM_GENERATE_INTERNAL_LABEL (buf
, "L",
25703 CODE_LABEL_NUMBER (XEXP (base
, 0)));
25707 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
25711 gcc_unreachable ();
25714 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25715 fputs (TARGET_32BIT
? "\t.long " : DOUBLE_INT_ASM_OP
, file
);
25718 fputs ("\t.tc ", file
);
25719 RS6000_OUTPUT_BASENAME (file
, name
);
25722 fprintf (file
, ".N" HOST_WIDE_INT_PRINT_UNSIGNED
, - offset
);
25724 fprintf (file
, ".P" HOST_WIDE_INT_PRINT_UNSIGNED
, offset
);
25726 /* Mark large TOC symbols on AIX with [TE] so they are mapped
25727 after other TOC symbols, reducing overflow of small TOC access
25728 to [TC] symbols. */
25729 fputs (TARGET_XCOFF
&& TARGET_CMODEL
!= CMODEL_SMALL
25730 ? "[TE]," : "[TC],", file
);
25733 /* Currently C++ toc references to vtables can be emitted before it
25734 is decided whether the vtable is public or private. If this is
25735 the case, then the linker will eventually complain that there is
25736 a TOC reference to an unknown section. Thus, for vtables only,
25737 we emit the TOC reference to reference the symbol and not the
25739 if (VTABLE_NAME_P (name
))
25741 RS6000_OUTPUT_BASENAME (file
, name
);
25743 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
25744 else if (offset
> 0)
25745 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
25748 output_addr_const (file
, x
);
25751 if (TARGET_XCOFF
&& GET_CODE (base
) == SYMBOL_REF
25752 && SYMBOL_REF_TLS_MODEL (base
) != 0)
25754 if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_LOCAL_EXEC
)
25755 fputs ("@le", file
);
25756 else if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_INITIAL_EXEC
)
25757 fputs ("@ie", file
);
25758 /* Use global-dynamic for local-dynamic. */
25759 else if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_GLOBAL_DYNAMIC
25760 || SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_LOCAL_DYNAMIC
)
25763 (*targetm
.asm_out
.internal_label
) (file
, "LCM", labelno
);
25764 fputs ("\t.tc .", file
);
25765 RS6000_OUTPUT_BASENAME (file
, name
);
25766 fputs ("[TC],", file
);
25767 output_addr_const (file
, x
);
25768 fputs ("@m", file
);
25776 /* Output an assembler pseudo-op to write an ASCII string of N characters
25777 starting at P to FILE.
25779 On the RS/6000, we have to do this using the .byte operation and
25780 write out special characters outside the quoted string.
25781 Also, the assembler is broken; very long strings are truncated,
25782 so we must artificially break them up early. */
25785 output_ascii (FILE *file
, const char *p
, int n
)
25788 int i
, count_string
;
25789 const char *for_string
= "\t.byte \"";
25790 const char *for_decimal
= "\t.byte ";
25791 const char *to_close
= NULL
;
25794 for (i
= 0; i
< n
; i
++)
25797 if (c
>= ' ' && c
< 0177)
25800 fputs (for_string
, file
);
25803 /* Write two quotes to get one. */
25811 for_decimal
= "\"\n\t.byte ";
25815 if (count_string
>= 512)
25817 fputs (to_close
, file
);
25819 for_string
= "\t.byte \"";
25820 for_decimal
= "\t.byte ";
25828 fputs (for_decimal
, file
);
25829 fprintf (file
, "%d", c
);
25831 for_string
= "\n\t.byte \"";
25832 for_decimal
= ", ";
25838 /* Now close the string if we have written one. Then end the line. */
25840 fputs (to_close
, file
);
25843 /* Generate a unique section name for FILENAME for a section type
25844 represented by SECTION_DESC. Output goes into BUF.
25846 SECTION_DESC can be any string, as long as it is different for each
25847 possible section type.
25849 We name the section in the same manner as xlc. The name begins with an
25850 underscore followed by the filename (after stripping any leading directory
25851 names) with the last period replaced by the string SECTION_DESC. If
25852 FILENAME does not contain a period, SECTION_DESC is appended to the end of
25856 rs6000_gen_section_name (char **buf
, const char *filename
,
25857 const char *section_desc
)
25859 const char *q
, *after_last_slash
, *last_period
= 0;
25863 after_last_slash
= filename
;
25864 for (q
= filename
; *q
; q
++)
25867 after_last_slash
= q
+ 1;
25868 else if (*q
== '.')
25872 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
25873 *buf
= (char *) xmalloc (len
);
25878 for (q
= after_last_slash
; *q
; q
++)
25880 if (q
== last_period
)
25882 strcpy (p
, section_desc
);
25883 p
+= strlen (section_desc
);
25887 else if (ISALNUM (*q
))
25891 if (last_period
== 0)
25892 strcpy (p
, section_desc
);
25897 /* Emit profile function. */
25900 output_profile_hook (int labelno ATTRIBUTE_UNUSED
)
25902 /* Non-standard profiling for kernels, which just saves LR then calls
25903 _mcount without worrying about arg saves. The idea is to change
25904 the function prologue as little as possible as it isn't easy to
25905 account for arg save/restore code added just for _mcount. */
25906 if (TARGET_PROFILE_KERNEL
)
25909 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
25911 #ifndef NO_PROFILE_COUNTERS
25912 # define NO_PROFILE_COUNTERS 0
25914 if (NO_PROFILE_COUNTERS
)
25915 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
25916 LCT_NORMAL
, VOIDmode
, 0);
25920 const char *label_name
;
25923 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
25924 label_name
= ggc_strdup ((*targetm
.strip_name_encoding
) (buf
));
25925 fun
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
25927 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
25928 LCT_NORMAL
, VOIDmode
, 1, fun
, Pmode
);
25931 else if (DEFAULT_ABI
== ABI_DARWIN
)
25933 const char *mcount_name
= RS6000_MCOUNT
;
25934 int caller_addr_regno
= LR_REGNO
;
25936 /* Be conservative and always set this, at least for now. */
25937 crtl
->uses_pic_offset_table
= 1;
25940 /* For PIC code, set up a stub and collect the caller's address
25941 from r0, which is where the prologue puts it. */
25942 if (MACHOPIC_INDIRECT
25943 && crtl
->uses_pic_offset_table
)
25944 caller_addr_regno
= 0;
25946 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, mcount_name
),
25947 LCT_NORMAL
, VOIDmode
, 1,
25948 gen_rtx_REG (Pmode
, caller_addr_regno
), Pmode
);
25952 /* Write function profiler code. */
25955 output_function_profiler (FILE *file
, int labelno
)
25959 switch (DEFAULT_ABI
)
25962 gcc_unreachable ();
25967 warning (0, "no profiling of 64-bit code for this ABI");
25970 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
25971 fprintf (file
, "\tmflr %s\n", reg_names
[0]);
25972 if (NO_PROFILE_COUNTERS
)
25974 asm_fprintf (file
, "\tstw %s,4(%s)\n",
25975 reg_names
[0], reg_names
[1]);
25977 else if (TARGET_SECURE_PLT
&& flag_pic
)
25979 if (TARGET_LINK_STACK
)
25982 get_ppc476_thunk_name (name
);
25983 asm_fprintf (file
, "\tbl %s\n", name
);
25986 asm_fprintf (file
, "\tbcl 20,31,1f\n1:\n");
25987 asm_fprintf (file
, "\tstw %s,4(%s)\n",
25988 reg_names
[0], reg_names
[1]);
25989 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
25990 asm_fprintf (file
, "\taddis %s,%s,",
25991 reg_names
[12], reg_names
[12]);
25992 assemble_name (file
, buf
);
25993 asm_fprintf (file
, "-1b@ha\n\tla %s,", reg_names
[0]);
25994 assemble_name (file
, buf
);
25995 asm_fprintf (file
, "-1b@l(%s)\n", reg_names
[12]);
25997 else if (flag_pic
== 1)
25999 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file
);
26000 asm_fprintf (file
, "\tstw %s,4(%s)\n",
26001 reg_names
[0], reg_names
[1]);
26002 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
26003 asm_fprintf (file
, "\tlwz %s,", reg_names
[0]);
26004 assemble_name (file
, buf
);
26005 asm_fprintf (file
, "@got(%s)\n", reg_names
[12]);
26007 else if (flag_pic
> 1)
26009 asm_fprintf (file
, "\tstw %s,4(%s)\n",
26010 reg_names
[0], reg_names
[1]);
26011 /* Now, we need to get the address of the label. */
26012 if (TARGET_LINK_STACK
)
26015 get_ppc476_thunk_name (name
);
26016 asm_fprintf (file
, "\tbl %s\n\tb 1f\n\t.long ", name
);
26017 assemble_name (file
, buf
);
26018 fputs ("-.\n1:", file
);
26019 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
26020 asm_fprintf (file
, "\taddi %s,%s,4\n",
26021 reg_names
[11], reg_names
[11]);
26025 fputs ("\tbcl 20,31,1f\n\t.long ", file
);
26026 assemble_name (file
, buf
);
26027 fputs ("-.\n1:", file
);
26028 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
26030 asm_fprintf (file
, "\tlwz %s,0(%s)\n",
26031 reg_names
[0], reg_names
[11]);
26032 asm_fprintf (file
, "\tadd %s,%s,%s\n",
26033 reg_names
[0], reg_names
[0], reg_names
[11]);
26037 asm_fprintf (file
, "\tlis %s,", reg_names
[12]);
26038 assemble_name (file
, buf
);
26039 fputs ("@ha\n", file
);
26040 asm_fprintf (file
, "\tstw %s,4(%s)\n",
26041 reg_names
[0], reg_names
[1]);
26042 asm_fprintf (file
, "\tla %s,", reg_names
[0]);
26043 assemble_name (file
, buf
);
26044 asm_fprintf (file
, "@l(%s)\n", reg_names
[12]);
26047 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
26048 fprintf (file
, "\tbl %s%s\n",
26049 RS6000_MCOUNT
, flag_pic
? "@plt" : "");
26055 /* Don't do anything, done in output_profile_hook (). */
26062 /* The following variable value is the last issued insn. */
26064 static rtx last_scheduled_insn
;
26066 /* The following variable helps to balance issuing of load and
26067 store instructions */
26069 static int load_store_pendulum
;
26071 /* Power4 load update and store update instructions are cracked into a
26072 load or store and an integer insn which are executed in the same cycle.
26073 Branches have their own dispatch slot which does not count against the
26074 GCC issue rate, but it changes the program flow so there are no other
26075 instructions to issue in this cycle. */
26078 rs6000_variable_issue_1 (rtx insn
, int more
)
26080 last_scheduled_insn
= insn
;
26081 if (GET_CODE (PATTERN (insn
)) == USE
26082 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
26084 cached_can_issue_more
= more
;
26085 return cached_can_issue_more
;
26088 if (insn_terminates_group_p (insn
, current_group
))
26090 cached_can_issue_more
= 0;
26091 return cached_can_issue_more
;
26094 /* If no reservation, but reach here */
26095 if (recog_memoized (insn
) < 0)
26098 if (rs6000_sched_groups
)
26100 if (is_microcoded_insn (insn
))
26101 cached_can_issue_more
= 0;
26102 else if (is_cracked_insn (insn
))
26103 cached_can_issue_more
= more
> 2 ? more
- 2 : 0;
26105 cached_can_issue_more
= more
- 1;
26107 return cached_can_issue_more
;
26110 if (rs6000_cpu_attr
== CPU_CELL
&& is_nonpipeline_insn (insn
))
26113 cached_can_issue_more
= more
- 1;
26114 return cached_can_issue_more
;
26118 rs6000_variable_issue (FILE *stream
, int verbose
, rtx insn
, int more
)
26120 int r
= rs6000_variable_issue_1 (insn
, more
);
26122 fprintf (stream
, "// rs6000_variable_issue (more = %d) = %d\n", more
, r
);
26126 /* Adjust the cost of a scheduling dependency. Return the new cost of
26127 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
26130 rs6000_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
26132 enum attr_type attr_type
;
26134 if (! recog_memoized (insn
))
26137 switch (REG_NOTE_KIND (link
))
26141 /* Data dependency; DEP_INSN writes a register that INSN reads
26142 some cycles later. */
26144 /* Separate a load from a narrower, dependent store. */
26145 if (rs6000_sched_groups
26146 && GET_CODE (PATTERN (insn
)) == SET
26147 && GET_CODE (PATTERN (dep_insn
)) == SET
26148 && GET_CODE (XEXP (PATTERN (insn
), 1)) == MEM
26149 && GET_CODE (XEXP (PATTERN (dep_insn
), 0)) == MEM
26150 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn
), 1)))
26151 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn
), 0)))))
26154 attr_type
= get_attr_type (insn
);
26159 /* Tell the first scheduling pass about the latency between
26160 a mtctr and bctr (and mtlr and br/blr). The first
26161 scheduling pass will not know about this latency since
26162 the mtctr instruction, which has the latency associated
26163 to it, will be generated by reload. */
26166 /* Leave some extra cycles between a compare and its
26167 dependent branch, to inhibit expensive mispredicts. */
26168 if ((rs6000_cpu_attr
== CPU_PPC603
26169 || rs6000_cpu_attr
== CPU_PPC604
26170 || rs6000_cpu_attr
== CPU_PPC604E
26171 || rs6000_cpu_attr
== CPU_PPC620
26172 || rs6000_cpu_attr
== CPU_PPC630
26173 || rs6000_cpu_attr
== CPU_PPC750
26174 || rs6000_cpu_attr
== CPU_PPC7400
26175 || rs6000_cpu_attr
== CPU_PPC7450
26176 || rs6000_cpu_attr
== CPU_PPCE5500
26177 || rs6000_cpu_attr
== CPU_PPCE6500
26178 || rs6000_cpu_attr
== CPU_POWER4
26179 || rs6000_cpu_attr
== CPU_POWER5
26180 || rs6000_cpu_attr
== CPU_POWER7
26181 || rs6000_cpu_attr
== CPU_POWER8
26182 || rs6000_cpu_attr
== CPU_CELL
)
26183 && recog_memoized (dep_insn
)
26184 && (INSN_CODE (dep_insn
) >= 0))
26186 switch (get_attr_type (dep_insn
))
26190 case TYPE_DELAYED_COMPARE
:
26191 case TYPE_IMUL_COMPARE
:
26192 case TYPE_LMUL_COMPARE
:
26193 case TYPE_FPCOMPARE
:
26194 case TYPE_CR_LOGICAL
:
26195 case TYPE_DELAYED_CR
:
26204 if ((rs6000_cpu
== PROCESSOR_POWER6
)
26205 && recog_memoized (dep_insn
)
26206 && (INSN_CODE (dep_insn
) >= 0))
26209 if (GET_CODE (PATTERN (insn
)) != SET
)
26210 /* If this happens, we have to extend this to schedule
26211 optimally. Return default for now. */
26214 /* Adjust the cost for the case where the value written
26215 by a fixed point operation is used as the address
26216 gen value on a store. */
26217 switch (get_attr_type (dep_insn
))
26222 if (! store_data_bypass_p (dep_insn
, insn
))
26223 return get_attr_sign_extend (dep_insn
)
26224 == SIGN_EXTEND_YES
? 6 : 4;
26227 case TYPE_VAR_SHIFT_ROTATE
:
26228 case TYPE_VAR_DELAYED_COMPARE
:
26230 if (! store_data_bypass_p (dep_insn
, insn
))
26236 case TYPE_FAST_COMPARE
:
26239 case TYPE_INSERT_WORD
:
26240 case TYPE_INSERT_DWORD
:
26242 if (! store_data_bypass_p (dep_insn
, insn
))
26250 if (get_attr_update (dep_insn
) == UPDATE_YES
26251 && ! store_data_bypass_p (dep_insn
, insn
))
26259 case TYPE_IMUL_COMPARE
:
26260 case TYPE_LMUL_COMPARE
:
26262 if (! store_data_bypass_p (dep_insn
, insn
))
26268 if (! store_data_bypass_p (dep_insn
, insn
))
26274 if (! store_data_bypass_p (dep_insn
, insn
))
26285 if ((rs6000_cpu
== PROCESSOR_POWER6
)
26286 && recog_memoized (dep_insn
)
26287 && (INSN_CODE (dep_insn
) >= 0))
26290 /* Adjust the cost for the case where the value written
26291 by a fixed point instruction is used within the address
26292 gen portion of a subsequent load(u)(x) */
26293 switch (get_attr_type (dep_insn
))
26298 if (set_to_load_agen (dep_insn
, insn
))
26299 return get_attr_sign_extend (dep_insn
)
26300 == SIGN_EXTEND_YES
? 6 : 4;
26303 case TYPE_VAR_SHIFT_ROTATE
:
26304 case TYPE_VAR_DELAYED_COMPARE
:
26306 if (set_to_load_agen (dep_insn
, insn
))
26312 case TYPE_FAST_COMPARE
:
26315 case TYPE_INSERT_WORD
:
26316 case TYPE_INSERT_DWORD
:
26318 if (set_to_load_agen (dep_insn
, insn
))
26326 if (get_attr_update (dep_insn
) == UPDATE_YES
26327 && set_to_load_agen (dep_insn
, insn
))
26335 case TYPE_IMUL_COMPARE
:
26336 case TYPE_LMUL_COMPARE
:
26338 if (set_to_load_agen (dep_insn
, insn
))
26344 if (set_to_load_agen (dep_insn
, insn
))
26350 if (set_to_load_agen (dep_insn
, insn
))
26361 if ((rs6000_cpu
== PROCESSOR_POWER6
)
26362 && get_attr_update (insn
) == UPDATE_NO
26363 && recog_memoized (dep_insn
)
26364 && (INSN_CODE (dep_insn
) >= 0)
26365 && (get_attr_type (dep_insn
) == TYPE_MFFGPR
))
26372 /* Fall out to return default cost. */
26376 case REG_DEP_OUTPUT
:
26377 /* Output dependency; DEP_INSN writes a register that INSN writes some
26379 if ((rs6000_cpu
== PROCESSOR_POWER6
)
26380 && recog_memoized (dep_insn
)
26381 && (INSN_CODE (dep_insn
) >= 0))
26383 attr_type
= get_attr_type (insn
);
26388 if (get_attr_type (dep_insn
) == TYPE_FP
)
26392 if (get_attr_update (insn
) == UPDATE_NO
26393 && get_attr_type (dep_insn
) == TYPE_MFFGPR
)
26401 /* Anti dependency; DEP_INSN reads a register that INSN writes some
26406 gcc_unreachable ();
26412 /* Debug version of rs6000_adjust_cost. */
26415 rs6000_debug_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
26417 int ret
= rs6000_adjust_cost (insn
, link
, dep_insn
, cost
);
26423 switch (REG_NOTE_KIND (link
))
26425 default: dep
= "unknown depencency"; break;
26426 case REG_DEP_TRUE
: dep
= "data dependency"; break;
26427 case REG_DEP_OUTPUT
: dep
= "output dependency"; break;
26428 case REG_DEP_ANTI
: dep
= "anti depencency"; break;
26432 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
26433 "%s, insn:\n", ret
, cost
, dep
);
26441 /* The function returns a true if INSN is microcoded.
26442 Return false otherwise. */
26445 is_microcoded_insn (rtx insn
)
26447 if (!insn
|| !NONDEBUG_INSN_P (insn
)
26448 || GET_CODE (PATTERN (insn
)) == USE
26449 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
26452 if (rs6000_cpu_attr
== CPU_CELL
)
26453 return get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
;
26455 if (rs6000_sched_groups
26456 && (rs6000_cpu
== PROCESSOR_POWER4
|| rs6000_cpu
== PROCESSOR_POWER5
))
26458 enum attr_type type
= get_attr_type (insn
);
26459 if ((type
== TYPE_LOAD
26460 && get_attr_update (insn
) == UPDATE_YES
26461 && get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
)
26462 || ((type
== TYPE_LOAD
|| type
== TYPE_STORE
)
26463 && get_attr_update (insn
) == UPDATE_YES
26464 && get_attr_indexed (insn
) == INDEXED_YES
)
26465 || type
== TYPE_MFCR
)
26472 /* The function returns true if INSN is cracked into 2 instructions
26473 by the processor (and therefore occupies 2 issue slots). */
26476 is_cracked_insn (rtx insn
)
26478 if (!insn
|| !NONDEBUG_INSN_P (insn
)
26479 || GET_CODE (PATTERN (insn
)) == USE
26480 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
26483 if (rs6000_sched_groups
26484 && (rs6000_cpu
== PROCESSOR_POWER4
|| rs6000_cpu
== PROCESSOR_POWER5
))
26486 enum attr_type type
= get_attr_type (insn
);
26487 if ((type
== TYPE_LOAD
26488 && get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
26489 && get_attr_update (insn
) == UPDATE_NO
)
26490 || (type
== TYPE_LOAD
26491 && get_attr_sign_extend (insn
) == SIGN_EXTEND_NO
26492 && get_attr_update (insn
) == UPDATE_YES
26493 && get_attr_indexed (insn
) == INDEXED_NO
)
26494 || (type
== TYPE_STORE
26495 && get_attr_update (insn
) == UPDATE_YES
26496 && get_attr_indexed (insn
) == INDEXED_NO
)
26497 || ((type
== TYPE_FPLOAD
|| type
== TYPE_FPSTORE
)
26498 && get_attr_update (insn
) == UPDATE_YES
)
26499 || type
== TYPE_DELAYED_CR
26500 || type
== TYPE_COMPARE
|| type
== TYPE_DELAYED_COMPARE
26501 || type
== TYPE_IMUL_COMPARE
|| type
== TYPE_LMUL_COMPARE
26502 || type
== TYPE_IDIV
|| type
== TYPE_LDIV
26503 || type
== TYPE_INSERT_WORD
)
26510 /* The function returns true if INSN can be issued only from
26511 the branch slot. */
26514 is_branch_slot_insn (rtx insn
)
26516 if (!insn
|| !NONDEBUG_INSN_P (insn
)
26517 || GET_CODE (PATTERN (insn
)) == USE
26518 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
26521 if (rs6000_sched_groups
)
26523 enum attr_type type
= get_attr_type (insn
);
26524 if (type
== TYPE_BRANCH
|| type
== TYPE_JMPREG
)
26532 /* The function returns true if out_inst sets a value that is
26533 used in the address generation computation of in_insn */
26535 set_to_load_agen (rtx out_insn
, rtx in_insn
)
26537 rtx out_set
, in_set
;
26539 /* For performance reasons, only handle the simple case where
26540 both loads are a single_set. */
26541 out_set
= single_set (out_insn
);
26544 in_set
= single_set (in_insn
);
26546 return reg_mentioned_p (SET_DEST (out_set
), SET_SRC (in_set
));
26552 /* Try to determine base/offset/size parts of the given MEM.
26553 Return true if successful, false if all the values couldn't
26556 This function only looks for REG or REG+CONST address forms.
26557 REG+REG address form will return false. */
26560 get_memref_parts (rtx mem
, rtx
*base
, HOST_WIDE_INT
*offset
,
26561 HOST_WIDE_INT
*size
)
26564 if MEM_SIZE_KNOWN_P (mem
)
26565 *size
= MEM_SIZE (mem
);
26569 if (GET_CODE (XEXP (mem
, 0)) == PRE_MODIFY
)
26570 addr_rtx
= XEXP (XEXP (mem
, 0), 1);
26572 addr_rtx
= (XEXP (mem
, 0));
26574 if (GET_CODE (addr_rtx
) == REG
)
26579 else if (GET_CODE (addr_rtx
) == PLUS
26580 && CONST_INT_P (XEXP (addr_rtx
, 1)))
26582 *base
= XEXP (addr_rtx
, 0);
26583 *offset
= INTVAL (XEXP (addr_rtx
, 1));
26591 /* The function returns true if the target storage location of
26592 mem1 is adjacent to the target storage location of mem2 */
26593 /* Return 1 if memory locations are adjacent. */
26596 adjacent_mem_locations (rtx mem1
, rtx mem2
)
26599 HOST_WIDE_INT off1
, size1
, off2
, size2
;
26601 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
26602 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
26603 return ((REGNO (reg1
) == REGNO (reg2
))
26604 && ((off1
+ size1
== off2
)
26605 || (off2
+ size2
== off1
)));
26610 /* This function returns true if it can be determined that the two MEM
26611 locations overlap by at least 1 byte based on base reg/offset/size. */
26614 mem_locations_overlap (rtx mem1
, rtx mem2
)
26617 HOST_WIDE_INT off1
, size1
, off2
, size2
;
26619 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
26620 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
26621 return ((REGNO (reg1
) == REGNO (reg2
))
26622 && (((off1
<= off2
) && (off1
+ size1
> off2
))
26623 || ((off2
<= off1
) && (off2
+ size2
> off1
))));
26628 /* A C statement (sans semicolon) to update the integer scheduling
26629 priority INSN_PRIORITY (INSN). Increase the priority to execute the
26630 INSN earlier, reduce the priority to execute INSN later. Do not
26631 define this macro if you do not need to adjust the scheduling
26632 priorities of insns. */
26635 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
26637 rtx load_mem
, str_mem
;
26638 /* On machines (like the 750) which have asymmetric integer units,
26639 where one integer unit can do multiply and divides and the other
26640 can't, reduce the priority of multiply/divide so it is scheduled
26641 before other integer operations. */
26644 if (! INSN_P (insn
))
26647 if (GET_CODE (PATTERN (insn
)) == USE
)
26650 switch (rs6000_cpu_attr
) {
26652 switch (get_attr_type (insn
))
26659 fprintf (stderr
, "priority was %#x (%d) before adjustment\n",
26660 priority
, priority
);
26661 if (priority
>= 0 && priority
< 0x01000000)
26668 if (insn_must_be_first_in_group (insn
)
26669 && reload_completed
26670 && current_sched_info
->sched_max_insns_priority
26671 && rs6000_sched_restricted_insns_priority
)
26674 /* Prioritize insns that can be dispatched only in the first
26676 if (rs6000_sched_restricted_insns_priority
== 1)
26677 /* Attach highest priority to insn. This means that in
26678 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
26679 precede 'priority' (critical path) considerations. */
26680 return current_sched_info
->sched_max_insns_priority
;
26681 else if (rs6000_sched_restricted_insns_priority
== 2)
26682 /* Increase priority of insn by a minimal amount. This means that in
26683 haifa-sched.c:ready_sort(), only 'priority' (critical path)
26684 considerations precede dispatch-slot restriction considerations. */
26685 return (priority
+ 1);
26688 if (rs6000_cpu
== PROCESSOR_POWER6
26689 && ((load_store_pendulum
== -2 && is_load_insn (insn
, &load_mem
))
26690 || (load_store_pendulum
== 2 && is_store_insn (insn
, &str_mem
))))
26691 /* Attach highest priority to insn if the scheduler has just issued two
26692 stores and this instruction is a load, or two loads and this instruction
26693 is a store. Power6 wants loads and stores scheduled alternately
26695 return current_sched_info
->sched_max_insns_priority
;
26700 /* Return true if the instruction is nonpipelined on the Cell. */
26702 is_nonpipeline_insn (rtx insn
)
26704 enum attr_type type
;
26705 if (!insn
|| !NONDEBUG_INSN_P (insn
)
26706 || GET_CODE (PATTERN (insn
)) == USE
26707 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
26710 type
= get_attr_type (insn
);
26711 if (type
== TYPE_IMUL
26712 || type
== TYPE_IMUL2
26713 || type
== TYPE_IMUL3
26714 || type
== TYPE_LMUL
26715 || type
== TYPE_IDIV
26716 || type
== TYPE_LDIV
26717 || type
== TYPE_SDIV
26718 || type
== TYPE_DDIV
26719 || type
== TYPE_SSQRT
26720 || type
== TYPE_DSQRT
26721 || type
== TYPE_MFCR
26722 || type
== TYPE_MFCRF
26723 || type
== TYPE_MFJMPR
)
26731 /* Return how many instructions the machine can issue per cycle. */
26734 rs6000_issue_rate (void)
26736 /* Unless scheduling for register pressure, use issue rate of 1 for
26737 first scheduling pass to decrease degradation. */
26738 if (!reload_completed
&& !flag_sched_pressure
)
26741 switch (rs6000_cpu_attr
) {
26743 case CPU_PPC601
: /* ? */
26753 case CPU_PPCE300C2
:
26754 case CPU_PPCE300C3
:
26755 case CPU_PPCE500MC
:
26756 case CPU_PPCE500MC64
:
26779 /* Return how many instructions to look ahead for better insn
26783 rs6000_use_sched_lookahead (void)
26785 switch (rs6000_cpu_attr
)
26792 return (reload_completed
? 8 : 0);
26799 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
26801 rs6000_use_sched_lookahead_guard (rtx insn
)
26803 if (rs6000_cpu_attr
!= CPU_CELL
)
26806 if (insn
== NULL_RTX
|| !INSN_P (insn
))
26809 if (!reload_completed
26810 || is_nonpipeline_insn (insn
)
26811 || is_microcoded_insn (insn
))
26817 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
26818 and return true. */
26821 find_mem_ref (rtx pat
, rtx
*mem_ref
)
26826 /* stack_tie does not produce any real memory traffic. */
26827 if (tie_operand (pat
, VOIDmode
))
26830 if (GET_CODE (pat
) == MEM
)
26836 /* Recursively process the pattern. */
26837 fmt
= GET_RTX_FORMAT (GET_CODE (pat
));
26839 for (i
= GET_RTX_LENGTH (GET_CODE (pat
)) - 1; i
>= 0; i
--)
26843 if (find_mem_ref (XEXP (pat
, i
), mem_ref
))
26846 else if (fmt
[i
] == 'E')
26847 for (j
= XVECLEN (pat
, i
) - 1; j
>= 0; j
--)
26849 if (find_mem_ref (XVECEXP (pat
, i
, j
), mem_ref
))
26857 /* Determine if PAT is a PATTERN of a load insn. */
26860 is_load_insn1 (rtx pat
, rtx
*load_mem
)
26862 if (!pat
|| pat
== NULL_RTX
)
26865 if (GET_CODE (pat
) == SET
)
26866 return find_mem_ref (SET_SRC (pat
), load_mem
);
26868 if (GET_CODE (pat
) == PARALLEL
)
26872 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
26873 if (is_load_insn1 (XVECEXP (pat
, 0, i
), load_mem
))
26880 /* Determine if INSN loads from memory. */
26883 is_load_insn (rtx insn
, rtx
*load_mem
)
26885 if (!insn
|| !INSN_P (insn
))
26891 return is_load_insn1 (PATTERN (insn
), load_mem
);
26894 /* Determine if PAT is a PATTERN of a store insn. */
26897 is_store_insn1 (rtx pat
, rtx
*str_mem
)
26899 if (!pat
|| pat
== NULL_RTX
)
26902 if (GET_CODE (pat
) == SET
)
26903 return find_mem_ref (SET_DEST (pat
), str_mem
);
26905 if (GET_CODE (pat
) == PARALLEL
)
26909 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
26910 if (is_store_insn1 (XVECEXP (pat
, 0, i
), str_mem
))
26917 /* Determine if INSN stores to memory. */
26920 is_store_insn (rtx insn
, rtx
*str_mem
)
26922 if (!insn
|| !INSN_P (insn
))
26925 return is_store_insn1 (PATTERN (insn
), str_mem
);
26928 /* Returns whether the dependence between INSN and NEXT is considered
26929 costly by the given target. */
26932 rs6000_is_costly_dependence (dep_t dep
, int cost
, int distance
)
26936 rtx load_mem
, str_mem
;
26938 /* If the flag is not enabled - no dependence is considered costly;
26939 allow all dependent insns in the same group.
26940 This is the most aggressive option. */
26941 if (rs6000_sched_costly_dep
== no_dep_costly
)
26944 /* If the flag is set to 1 - a dependence is always considered costly;
26945 do not allow dependent instructions in the same group.
26946 This is the most conservative option. */
26947 if (rs6000_sched_costly_dep
== all_deps_costly
)
26950 insn
= DEP_PRO (dep
);
26951 next
= DEP_CON (dep
);
26953 if (rs6000_sched_costly_dep
== store_to_load_dep_costly
26954 && is_load_insn (next
, &load_mem
)
26955 && is_store_insn (insn
, &str_mem
))
26956 /* Prevent load after store in the same group. */
26959 if (rs6000_sched_costly_dep
== true_store_to_load_dep_costly
26960 && is_load_insn (next
, &load_mem
)
26961 && is_store_insn (insn
, &str_mem
)
26962 && DEP_TYPE (dep
) == REG_DEP_TRUE
26963 && mem_locations_overlap(str_mem
, load_mem
))
26964 /* Prevent load after store in the same group if it is a true
26968 /* The flag is set to X; dependences with latency >= X are considered costly,
26969 and will not be scheduled in the same group. */
26970 if (rs6000_sched_costly_dep
<= max_dep_latency
26971 && ((cost
- distance
) >= (int)rs6000_sched_costly_dep
))
26977 /* Return the next insn after INSN that is found before TAIL is reached,
26978 skipping any "non-active" insns - insns that will not actually occupy
26979 an issue slot. Return NULL_RTX if such an insn is not found. */
26982 get_next_active_insn (rtx insn
, rtx tail
)
26984 if (insn
== NULL_RTX
|| insn
== tail
)
26989 insn
= NEXT_INSN (insn
);
26990 if (insn
== NULL_RTX
|| insn
== tail
)
26994 || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
26995 || (NONJUMP_INSN_P (insn
)
26996 && GET_CODE (PATTERN (insn
)) != USE
26997 && GET_CODE (PATTERN (insn
)) != CLOBBER
26998 && INSN_CODE (insn
) != CODE_FOR_stack_tie
))
27004 /* We are about to begin issuing insns for this clock cycle. */
27007 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED
, int sched_verbose
,
27008 rtx
*ready ATTRIBUTE_UNUSED
,
27009 int *pn_ready ATTRIBUTE_UNUSED
,
27010 int clock_var ATTRIBUTE_UNUSED
)
27012 int n_ready
= *pn_ready
;
27015 fprintf (dump
, "// rs6000_sched_reorder :\n");
27017 /* Reorder the ready list, if the second to last ready insn
27018 is a nonepipeline insn. */
27019 if (rs6000_cpu_attr
== CPU_CELL
&& n_ready
> 1)
27021 if (is_nonpipeline_insn (ready
[n_ready
- 1])
27022 && (recog_memoized (ready
[n_ready
- 2]) > 0))
27023 /* Simply swap first two insns. */
27025 rtx tmp
= ready
[n_ready
- 1];
27026 ready
[n_ready
- 1] = ready
[n_ready
- 2];
27027 ready
[n_ready
- 2] = tmp
;
27031 if (rs6000_cpu
== PROCESSOR_POWER6
)
27032 load_store_pendulum
= 0;
27034 return rs6000_issue_rate ();
27037 /* Like rs6000_sched_reorder, but called after issuing each insn. */
27040 rs6000_sched_reorder2 (FILE *dump
, int sched_verbose
, rtx
*ready
,
27041 int *pn_ready
, int clock_var ATTRIBUTE_UNUSED
)
27044 fprintf (dump
, "// rs6000_sched_reorder2 :\n");
27046 /* For Power6, we need to handle some special cases to try and keep the
27047 store queue from overflowing and triggering expensive flushes.
27049 This code monitors how load and store instructions are being issued
27050 and skews the ready list one way or the other to increase the likelihood
27051 that a desired instruction is issued at the proper time.
27053 A couple of things are done. First, we maintain a "load_store_pendulum"
27054 to track the current state of load/store issue.
27056 - If the pendulum is at zero, then no loads or stores have been
27057 issued in the current cycle so we do nothing.
27059 - If the pendulum is 1, then a single load has been issued in this
27060 cycle and we attempt to locate another load in the ready list to
27063 - If the pendulum is -2, then two stores have already been
27064 issued in this cycle, so we increase the priority of the first load
27065 in the ready list to increase it's likelihood of being chosen first
27068 - If the pendulum is -1, then a single store has been issued in this
27069 cycle and we attempt to locate another store in the ready list to
27070 issue with it, preferring a store to an adjacent memory location to
27071 facilitate store pairing in the store queue.
27073 - If the pendulum is 2, then two loads have already been
27074 issued in this cycle, so we increase the priority of the first store
27075 in the ready list to increase it's likelihood of being chosen first
27078 - If the pendulum < -2 or > 2, then do nothing.
27080 Note: This code covers the most common scenarios. There exist non
27081 load/store instructions which make use of the LSU and which
27082 would need to be accounted for to strictly model the behavior
27083 of the machine. Those instructions are currently unaccounted
27084 for to help minimize compile time overhead of this code.
27086 if (rs6000_cpu
== PROCESSOR_POWER6
&& last_scheduled_insn
)
27090 rtx tmp
, load_mem
, str_mem
;
27092 if (is_store_insn (last_scheduled_insn
, &str_mem
))
27093 /* Issuing a store, swing the load_store_pendulum to the left */
27094 load_store_pendulum
--;
27095 else if (is_load_insn (last_scheduled_insn
, &load_mem
))
27096 /* Issuing a load, swing the load_store_pendulum to the right */
27097 load_store_pendulum
++;
27099 return cached_can_issue_more
;
27101 /* If the pendulum is balanced, or there is only one instruction on
27102 the ready list, then all is well, so return. */
27103 if ((load_store_pendulum
== 0) || (*pn_ready
<= 1))
27104 return cached_can_issue_more
;
27106 if (load_store_pendulum
== 1)
27108 /* A load has been issued in this cycle. Scan the ready list
27109 for another load to issue with it */
27114 if (is_load_insn (ready
[pos
], &load_mem
))
27116 /* Found a load. Move it to the head of the ready list,
27117 and adjust it's priority so that it is more likely to
27120 for (i
=pos
; i
<*pn_ready
-1; i
++)
27121 ready
[i
] = ready
[i
+ 1];
27122 ready
[*pn_ready
-1] = tmp
;
27124 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
27125 INSN_PRIORITY (tmp
)++;
27131 else if (load_store_pendulum
== -2)
27133 /* Two stores have been issued in this cycle. Increase the
27134 priority of the first load in the ready list to favor it for
27135 issuing in the next cycle. */
27140 if (is_load_insn (ready
[pos
], &load_mem
)
27142 && INSN_PRIORITY_KNOWN (ready
[pos
]))
27144 INSN_PRIORITY (ready
[pos
])++;
27146 /* Adjust the pendulum to account for the fact that a load
27147 was found and increased in priority. This is to prevent
27148 increasing the priority of multiple loads */
27149 load_store_pendulum
--;
27156 else if (load_store_pendulum
== -1)
27158 /* A store has been issued in this cycle. Scan the ready list for
27159 another store to issue with it, preferring a store to an adjacent
27161 int first_store_pos
= -1;
27167 if (is_store_insn (ready
[pos
], &str_mem
))
27170 /* Maintain the index of the first store found on the
27172 if (first_store_pos
== -1)
27173 first_store_pos
= pos
;
27175 if (is_store_insn (last_scheduled_insn
, &str_mem2
)
27176 && adjacent_mem_locations (str_mem
, str_mem2
))
27178 /* Found an adjacent store. Move it to the head of the
27179 ready list, and adjust it's priority so that it is
27180 more likely to stay there */
27182 for (i
=pos
; i
<*pn_ready
-1; i
++)
27183 ready
[i
] = ready
[i
+ 1];
27184 ready
[*pn_ready
-1] = tmp
;
27186 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
27187 INSN_PRIORITY (tmp
)++;
27189 first_store_pos
= -1;
27197 if (first_store_pos
>= 0)
27199 /* An adjacent store wasn't found, but a non-adjacent store was,
27200 so move the non-adjacent store to the front of the ready
27201 list, and adjust its priority so that it is more likely to
27203 tmp
= ready
[first_store_pos
];
27204 for (i
=first_store_pos
; i
<*pn_ready
-1; i
++)
27205 ready
[i
] = ready
[i
+ 1];
27206 ready
[*pn_ready
-1] = tmp
;
27207 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
27208 INSN_PRIORITY (tmp
)++;
27211 else if (load_store_pendulum
== 2)
27213 /* Two loads have been issued in this cycle. Increase the priority
27214 of the first store in the ready list to favor it for issuing in
27220 if (is_store_insn (ready
[pos
], &str_mem
)
27222 && INSN_PRIORITY_KNOWN (ready
[pos
]))
27224 INSN_PRIORITY (ready
[pos
])++;
27226 /* Adjust the pendulum to account for the fact that a store
27227 was found and increased in priority. This is to prevent
27228 increasing the priority of multiple stores */
27229 load_store_pendulum
++;
27238 return cached_can_issue_more
;
27241 /* Return whether the presence of INSN causes a dispatch group termination
27242 of group WHICH_GROUP.
27244 If WHICH_GROUP == current_group, this function will return true if INSN
27245 causes the termination of the current group (i.e, the dispatch group to
27246 which INSN belongs). This means that INSN will be the last insn in the
27247 group it belongs to.
27249 If WHICH_GROUP == previous_group, this function will return true if INSN
27250 causes the termination of the previous group (i.e, the dispatch group that
27251 precedes the group to which INSN belongs). This means that INSN will be
27252 the first insn in the group it belongs to). */
27255 insn_terminates_group_p (rtx insn
, enum group_termination which_group
)
27262 first
= insn_must_be_first_in_group (insn
);
27263 last
= insn_must_be_last_in_group (insn
);
27268 if (which_group
== current_group
)
27270 else if (which_group
== previous_group
)
27278 insn_must_be_first_in_group (rtx insn
)
27280 enum attr_type type
;
27284 || DEBUG_INSN_P (insn
)
27285 || GET_CODE (PATTERN (insn
)) == USE
27286 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
27289 switch (rs6000_cpu
)
27291 case PROCESSOR_POWER5
:
27292 if (is_cracked_insn (insn
))
27294 case PROCESSOR_POWER4
:
27295 if (is_microcoded_insn (insn
))
27298 if (!rs6000_sched_groups
)
27301 type
= get_attr_type (insn
);
27308 case TYPE_DELAYED_CR
:
27309 case TYPE_CR_LOGICAL
:
27323 case PROCESSOR_POWER6
:
27324 type
= get_attr_type (insn
);
27328 case TYPE_INSERT_DWORD
:
27332 case TYPE_VAR_SHIFT_ROTATE
:
27339 case TYPE_INSERT_WORD
:
27340 case TYPE_DELAYED_COMPARE
:
27341 case TYPE_IMUL_COMPARE
:
27342 case TYPE_LMUL_COMPARE
:
27343 case TYPE_FPCOMPARE
:
27357 if (get_attr_update (insn
) == UPDATE_YES
)
27365 case PROCESSOR_POWER7
:
27366 type
= get_attr_type (insn
);
27370 case TYPE_CR_LOGICAL
:
27377 case TYPE_DELAYED_COMPARE
:
27378 case TYPE_VAR_DELAYED_COMPARE
:
27386 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
27387 || get_attr_update (insn
) == UPDATE_YES
)
27394 if (get_attr_update (insn
) == UPDATE_YES
)
27402 case PROCESSOR_POWER8
:
27403 type
= get_attr_type (insn
);
27407 case TYPE_CR_LOGICAL
:
27408 case TYPE_DELAYED_CR
:
27413 case TYPE_DELAYED_COMPARE
:
27414 case TYPE_VAR_DELAYED_COMPARE
:
27415 case TYPE_IMUL_COMPARE
:
27416 case TYPE_LMUL_COMPARE
:
27421 case TYPE_VECSTORE
:
27426 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
27427 || get_attr_update (insn
) == UPDATE_YES
)
27432 if (get_attr_update (insn
) == UPDATE_YES
27433 && get_attr_indexed (insn
) == INDEXED_YES
)
27449 insn_must_be_last_in_group (rtx insn
)
27451 enum attr_type type
;
27455 || DEBUG_INSN_P (insn
)
27456 || GET_CODE (PATTERN (insn
)) == USE
27457 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
27460 switch (rs6000_cpu
) {
27461 case PROCESSOR_POWER4
:
27462 case PROCESSOR_POWER5
:
27463 if (is_microcoded_insn (insn
))
27466 if (is_branch_slot_insn (insn
))
27470 case PROCESSOR_POWER6
:
27471 type
= get_attr_type (insn
);
27478 case TYPE_VAR_SHIFT_ROTATE
:
27485 case TYPE_DELAYED_COMPARE
:
27486 case TYPE_IMUL_COMPARE
:
27487 case TYPE_LMUL_COMPARE
:
27488 case TYPE_FPCOMPARE
:
27502 case PROCESSOR_POWER7
:
27503 type
= get_attr_type (insn
);
27513 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
27514 && get_attr_update (insn
) == UPDATE_YES
)
27519 if (get_attr_update (insn
) == UPDATE_YES
27520 && get_attr_indexed (insn
) == INDEXED_YES
)
27528 case PROCESSOR_POWER8
:
27529 type
= get_attr_type (insn
);
27541 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
27542 && get_attr_update (insn
) == UPDATE_YES
)
27547 if (get_attr_update (insn
) == UPDATE_YES
27548 && get_attr_indexed (insn
) == INDEXED_YES
)
27563 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
27564 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
27567 is_costly_group (rtx
*group_insns
, rtx next_insn
)
27570 int issue_rate
= rs6000_issue_rate ();
27572 for (i
= 0; i
< issue_rate
; i
++)
27574 sd_iterator_def sd_it
;
27576 rtx insn
= group_insns
[i
];
27581 FOR_EACH_DEP (insn
, SD_LIST_RES_FORW
, sd_it
, dep
)
27583 rtx next
= DEP_CON (dep
);
27585 if (next
== next_insn
27586 && rs6000_is_costly_dependence (dep
, dep_cost (dep
), 0))
27594 /* Utility of the function redefine_groups.
27595 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
27596 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
27597 to keep it "far" (in a separate group) from GROUP_INSNS, following
27598 one of the following schemes, depending on the value of the flag
27599 -minsert_sched_nops = X:
27600 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
27601 in order to force NEXT_INSN into a separate group.
27602 (2) X < sched_finish_regroup_exact: insert exactly X nops.
27603 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
27604 insertion (has a group just ended, how many vacant issue slots remain in the
27605 last group, and how many dispatch groups were encountered so far). */
27608 force_new_group (int sched_verbose
, FILE *dump
, rtx
*group_insns
,
27609 rtx next_insn
, bool *group_end
, int can_issue_more
,
27614 int issue_rate
= rs6000_issue_rate ();
27615 bool end
= *group_end
;
27618 if (next_insn
== NULL_RTX
|| DEBUG_INSN_P (next_insn
))
27619 return can_issue_more
;
27621 if (rs6000_sched_insert_nops
> sched_finish_regroup_exact
)
27622 return can_issue_more
;
27624 force
= is_costly_group (group_insns
, next_insn
);
27626 return can_issue_more
;
27628 if (sched_verbose
> 6)
27629 fprintf (dump
,"force: group count = %d, can_issue_more = %d\n",
27630 *group_count
,can_issue_more
);
27632 if (rs6000_sched_insert_nops
== sched_finish_regroup_exact
)
27635 can_issue_more
= 0;
27637 /* Since only a branch can be issued in the last issue_slot, it is
27638 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
27639 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
27640 in this case the last nop will start a new group and the branch
27641 will be forced to the new group. */
27642 if (can_issue_more
&& !is_branch_slot_insn (next_insn
))
27645 /* Do we have a special group ending nop? */
27646 if (rs6000_cpu_attr
== CPU_POWER6
|| rs6000_cpu_attr
== CPU_POWER7
27647 || rs6000_cpu_attr
== CPU_POWER8
)
27649 nop
= gen_group_ending_nop ();
27650 emit_insn_before (nop
, next_insn
);
27651 can_issue_more
= 0;
27654 while (can_issue_more
> 0)
27657 emit_insn_before (nop
, next_insn
);
27665 if (rs6000_sched_insert_nops
< sched_finish_regroup_exact
)
27667 int n_nops
= rs6000_sched_insert_nops
;
27669 /* Nops can't be issued from the branch slot, so the effective
27670 issue_rate for nops is 'issue_rate - 1'. */
27671 if (can_issue_more
== 0)
27672 can_issue_more
= issue_rate
;
27674 if (can_issue_more
== 0)
27676 can_issue_more
= issue_rate
- 1;
27679 for (i
= 0; i
< issue_rate
; i
++)
27681 group_insns
[i
] = 0;
27688 emit_insn_before (nop
, next_insn
);
27689 if (can_issue_more
== issue_rate
- 1) /* new group begins */
27692 if (can_issue_more
== 0)
27694 can_issue_more
= issue_rate
- 1;
27697 for (i
= 0; i
< issue_rate
; i
++)
27699 group_insns
[i
] = 0;
27705 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
27708 /* Is next_insn going to start a new group? */
27711 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
27712 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
27713 || (can_issue_more
< issue_rate
&&
27714 insn_terminates_group_p (next_insn
, previous_group
)));
27715 if (*group_end
&& end
)
27718 if (sched_verbose
> 6)
27719 fprintf (dump
, "done force: group count = %d, can_issue_more = %d\n",
27720 *group_count
, can_issue_more
);
27721 return can_issue_more
;
27724 return can_issue_more
;
27727 /* This function tries to synch the dispatch groups that the compiler "sees"
27728 with the dispatch groups that the processor dispatcher is expected to
27729 form in practice. It tries to achieve this synchronization by forcing the
27730 estimated processor grouping on the compiler (as opposed to the function
27731 'pad_goups' which tries to force the scheduler's grouping on the processor).
27733 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
27734 examines the (estimated) dispatch groups that will be formed by the processor
27735 dispatcher. It marks these group boundaries to reflect the estimated
27736 processor grouping, overriding the grouping that the scheduler had marked.
27737 Depending on the value of the flag '-minsert-sched-nops' this function can
27738 force certain insns into separate groups or force a certain distance between
27739 them by inserting nops, for example, if there exists a "costly dependence"
27742 The function estimates the group boundaries that the processor will form as
27743 follows: It keeps track of how many vacant issue slots are available after
27744 each insn. A subsequent insn will start a new group if one of the following
27746 - no more vacant issue slots remain in the current dispatch group.
27747 - only the last issue slot, which is the branch slot, is vacant, but the next
27748 insn is not a branch.
27749 - only the last 2 or less issue slots, including the branch slot, are vacant,
27750 which means that a cracked insn (which occupies two issue slots) can't be
27751 issued in this group.
27752 - less than 'issue_rate' slots are vacant, and the next insn always needs to
27753 start a new group. */
27756 redefine_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
27758 rtx insn
, next_insn
;
27760 int can_issue_more
;
27763 int group_count
= 0;
27767 issue_rate
= rs6000_issue_rate ();
27768 group_insns
= XALLOCAVEC (rtx
, issue_rate
);
27769 for (i
= 0; i
< issue_rate
; i
++)
27771 group_insns
[i
] = 0;
27773 can_issue_more
= issue_rate
;
27775 insn
= get_next_active_insn (prev_head_insn
, tail
);
27778 while (insn
!= NULL_RTX
)
27780 slot
= (issue_rate
- can_issue_more
);
27781 group_insns
[slot
] = insn
;
27783 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
27784 if (insn_terminates_group_p (insn
, current_group
))
27785 can_issue_more
= 0;
27787 next_insn
= get_next_active_insn (insn
, tail
);
27788 if (next_insn
== NULL_RTX
)
27789 return group_count
+ 1;
27791 /* Is next_insn going to start a new group? */
27793 = (can_issue_more
== 0
27794 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
27795 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
27796 || (can_issue_more
< issue_rate
&&
27797 insn_terminates_group_p (next_insn
, previous_group
)));
27799 can_issue_more
= force_new_group (sched_verbose
, dump
, group_insns
,
27800 next_insn
, &group_end
, can_issue_more
,
27806 can_issue_more
= 0;
27807 for (i
= 0; i
< issue_rate
; i
++)
27809 group_insns
[i
] = 0;
27813 if (GET_MODE (next_insn
) == TImode
&& can_issue_more
)
27814 PUT_MODE (next_insn
, VOIDmode
);
27815 else if (!can_issue_more
&& GET_MODE (next_insn
) != TImode
)
27816 PUT_MODE (next_insn
, TImode
);
27819 if (can_issue_more
== 0)
27820 can_issue_more
= issue_rate
;
27823 return group_count
;
27826 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
27827 dispatch group boundaries that the scheduler had marked. Pad with nops
27828 any dispatch groups which have vacant issue slots, in order to force the
27829 scheduler's grouping on the processor dispatcher. The function
27830 returns the number of dispatch groups found. */
27833 pad_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
27835 rtx insn
, next_insn
;
27838 int can_issue_more
;
27840 int group_count
= 0;
27842 /* Initialize issue_rate. */
27843 issue_rate
= rs6000_issue_rate ();
27844 can_issue_more
= issue_rate
;
27846 insn
= get_next_active_insn (prev_head_insn
, tail
);
27847 next_insn
= get_next_active_insn (insn
, tail
);
27849 while (insn
!= NULL_RTX
)
27852 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
27854 group_end
= (next_insn
== NULL_RTX
|| GET_MODE (next_insn
) == TImode
);
27856 if (next_insn
== NULL_RTX
)
27861 /* If the scheduler had marked group termination at this location
27862 (between insn and next_insn), and neither insn nor next_insn will
27863 force group termination, pad the group with nops to force group
27866 && (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
27867 && !insn_terminates_group_p (insn
, current_group
)
27868 && !insn_terminates_group_p (next_insn
, previous_group
))
27870 if (!is_branch_slot_insn (next_insn
))
27873 while (can_issue_more
)
27876 emit_insn_before (nop
, next_insn
);
27881 can_issue_more
= issue_rate
;
27886 next_insn
= get_next_active_insn (insn
, tail
);
27889 return group_count
;
27892 /* We're beginning a new block. Initialize data structures as necessary. */
27895 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
27896 int sched_verbose ATTRIBUTE_UNUSED
,
27897 int max_ready ATTRIBUTE_UNUSED
)
27899 last_scheduled_insn
= NULL_RTX
;
27900 load_store_pendulum
= 0;
27903 /* The following function is called at the end of scheduling BB.
27904 After reload, it inserts nops at insn group bundling. */
27907 rs6000_sched_finish (FILE *dump
, int sched_verbose
)
27912 fprintf (dump
, "=== Finishing schedule.\n");
27914 if (reload_completed
&& rs6000_sched_groups
)
27916 /* Do not run sched_finish hook when selective scheduling enabled. */
27917 if (sel_sched_p ())
27920 if (rs6000_sched_insert_nops
== sched_finish_none
)
27923 if (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
27924 n_groups
= pad_groups (dump
, sched_verbose
,
27925 current_sched_info
->prev_head
,
27926 current_sched_info
->next_tail
);
27928 n_groups
= redefine_groups (dump
, sched_verbose
,
27929 current_sched_info
->prev_head
,
27930 current_sched_info
->next_tail
);
27932 if (sched_verbose
>= 6)
27934 fprintf (dump
, "ngroups = %d\n", n_groups
);
27935 print_rtl (dump
, current_sched_info
->prev_head
);
27936 fprintf (dump
, "Done finish_sched\n");
27941 struct _rs6000_sched_context
27943 short cached_can_issue_more
;
27944 rtx last_scheduled_insn
;
27945 int load_store_pendulum
;
27948 typedef struct _rs6000_sched_context rs6000_sched_context_def
;
27949 typedef rs6000_sched_context_def
*rs6000_sched_context_t
;
27951 /* Allocate store for new scheduling context. */
27953 rs6000_alloc_sched_context (void)
27955 return xmalloc (sizeof (rs6000_sched_context_def
));
27958 /* If CLEAN_P is true then initializes _SC with clean data,
27959 and from the global context otherwise. */
27961 rs6000_init_sched_context (void *_sc
, bool clean_p
)
27963 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
27967 sc
->cached_can_issue_more
= 0;
27968 sc
->last_scheduled_insn
= NULL_RTX
;
27969 sc
->load_store_pendulum
= 0;
27973 sc
->cached_can_issue_more
= cached_can_issue_more
;
27974 sc
->last_scheduled_insn
= last_scheduled_insn
;
27975 sc
->load_store_pendulum
= load_store_pendulum
;
27979 /* Sets the global scheduling context to the one pointed to by _SC. */
27981 rs6000_set_sched_context (void *_sc
)
27983 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
27985 gcc_assert (sc
!= NULL
);
27987 cached_can_issue_more
= sc
->cached_can_issue_more
;
27988 last_scheduled_insn
= sc
->last_scheduled_insn
;
27989 load_store_pendulum
= sc
->load_store_pendulum
;
27994 rs6000_free_sched_context (void *_sc
)
27996 gcc_assert (_sc
!= NULL
);
28002 /* Length in units of the trampoline for entering a nested function. */
28005 rs6000_trampoline_size (void)
28009 switch (DEFAULT_ABI
)
28012 gcc_unreachable ();
28015 ret
= (TARGET_32BIT
) ? 12 : 24;
28019 gcc_assert (!TARGET_32BIT
);
28025 ret
= (TARGET_32BIT
) ? 40 : 48;
28032 /* Emit RTL insns to initialize the variable parts of a trampoline.
28033 FNADDR is an RTX for the address of the function's pure code.
28034 CXT is an RTX for the static chain value for the function. */
28037 rs6000_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
28039 int regsize
= (TARGET_32BIT
) ? 4 : 8;
28040 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
28041 rtx ctx_reg
= force_reg (Pmode
, cxt
);
28042 rtx addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
28044 switch (DEFAULT_ABI
)
28047 gcc_unreachable ();
28049 /* Under AIX, just build the 3 word function descriptor */
28052 rtx fnmem
, fn_reg
, toc_reg
;
28054 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
28055 error ("You cannot take the address of a nested function if you use "
28056 "the -mno-pointers-to-nested-functions option.");
28058 fnmem
= gen_const_mem (Pmode
, force_reg (Pmode
, fnaddr
));
28059 fn_reg
= gen_reg_rtx (Pmode
);
28060 toc_reg
= gen_reg_rtx (Pmode
);
28062 /* Macro to shorten the code expansions below. */
28063 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
28065 m_tramp
= replace_equiv_address (m_tramp
, addr
);
28067 emit_move_insn (fn_reg
, MEM_PLUS (fnmem
, 0));
28068 emit_move_insn (toc_reg
, MEM_PLUS (fnmem
, regsize
));
28069 emit_move_insn (MEM_PLUS (m_tramp
, 0), fn_reg
);
28070 emit_move_insn (MEM_PLUS (m_tramp
, regsize
), toc_reg
);
28071 emit_move_insn (MEM_PLUS (m_tramp
, 2*regsize
), ctx_reg
);
28077 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
28081 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__trampoline_setup"),
28082 LCT_NORMAL
, VOIDmode
, 4,
28084 GEN_INT (rs6000_trampoline_size ()), SImode
,
28092 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
28093 identifier as an argument, so the front end shouldn't look it up. */
28096 rs6000_attribute_takes_identifier_p (const_tree attr_id
)
28098 return is_attribute_p ("altivec", attr_id
);
28101 /* Handle the "altivec" attribute. The attribute may have
28102 arguments as follows:
28104 __attribute__((altivec(vector__)))
28105 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
28106 __attribute__((altivec(bool__))) (always followed by 'unsigned')
28108 and may appear more than once (e.g., 'vector bool char') in a
28109 given declaration. */
28112 rs6000_handle_altivec_attribute (tree
*node
,
28113 tree name ATTRIBUTE_UNUSED
,
28115 int flags ATTRIBUTE_UNUSED
,
28116 bool *no_add_attrs
)
28118 tree type
= *node
, result
= NULL_TREE
;
28119 enum machine_mode mode
;
28122 = ((args
&& TREE_CODE (args
) == TREE_LIST
&& TREE_VALUE (args
)
28123 && TREE_CODE (TREE_VALUE (args
)) == IDENTIFIER_NODE
)
28124 ? *IDENTIFIER_POINTER (TREE_VALUE (args
))
28127 while (POINTER_TYPE_P (type
)
28128 || TREE_CODE (type
) == FUNCTION_TYPE
28129 || TREE_CODE (type
) == METHOD_TYPE
28130 || TREE_CODE (type
) == ARRAY_TYPE
)
28131 type
= TREE_TYPE (type
);
28133 mode
= TYPE_MODE (type
);
28135 /* Check for invalid AltiVec type qualifiers. */
28136 if (type
== long_double_type_node
)
28137 error ("use of %<long double%> in AltiVec types is invalid");
28138 else if (type
== boolean_type_node
)
28139 error ("use of boolean types in AltiVec types is invalid");
28140 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
28141 error ("use of %<complex%> in AltiVec types is invalid");
28142 else if (DECIMAL_FLOAT_MODE_P (mode
))
28143 error ("use of decimal floating point types in AltiVec types is invalid");
28144 else if (!TARGET_VSX
)
28146 if (type
== long_unsigned_type_node
|| type
== long_integer_type_node
)
28149 error ("use of %<long%> in AltiVec types is invalid for "
28150 "64-bit code without -mvsx");
28151 else if (rs6000_warn_altivec_long
)
28152 warning (0, "use of %<long%> in AltiVec types is deprecated; "
28155 else if (type
== long_long_unsigned_type_node
28156 || type
== long_long_integer_type_node
)
28157 error ("use of %<long long%> in AltiVec types is invalid without "
28159 else if (type
== double_type_node
)
28160 error ("use of %<double%> in AltiVec types is invalid without -mvsx");
28163 switch (altivec_type
)
28166 unsigned_p
= TYPE_UNSIGNED (type
);
28170 result
= (unsigned_p
? unsigned_V1TI_type_node
: V1TI_type_node
);
28173 result
= (unsigned_p
? unsigned_V2DI_type_node
: V2DI_type_node
);
28176 result
= (unsigned_p
? unsigned_V4SI_type_node
: V4SI_type_node
);
28179 result
= (unsigned_p
? unsigned_V8HI_type_node
: V8HI_type_node
);
28182 result
= (unsigned_p
? unsigned_V16QI_type_node
: V16QI_type_node
);
28184 case SFmode
: result
= V4SF_type_node
; break;
28185 case DFmode
: result
= V2DF_type_node
; break;
28186 /* If the user says 'vector int bool', we may be handed the 'bool'
28187 attribute _before_ the 'vector' attribute, and so select the
28188 proper type in the 'b' case below. */
28189 case V4SImode
: case V8HImode
: case V16QImode
: case V4SFmode
:
28190 case V2DImode
: case V2DFmode
:
28198 case DImode
: case V2DImode
: result
= bool_V2DI_type_node
; break;
28199 case SImode
: case V4SImode
: result
= bool_V4SI_type_node
; break;
28200 case HImode
: case V8HImode
: result
= bool_V8HI_type_node
; break;
28201 case QImode
: case V16QImode
: result
= bool_V16QI_type_node
;
28208 case V8HImode
: result
= pixel_V8HI_type_node
;
28214 /* Propagate qualifiers attached to the element type
28215 onto the vector type. */
28216 if (result
&& result
!= type
&& TYPE_QUALS (type
))
28217 result
= build_qualified_type (result
, TYPE_QUALS (type
));
28219 *no_add_attrs
= true; /* No need to hang on to the attribute. */
28222 *node
= lang_hooks
.types
.reconstruct_complex_type (*node
, result
);
28227 /* AltiVec defines four built-in scalar types that serve as vector
28228 elements; we must teach the compiler how to mangle them. */
28230 static const char *
28231 rs6000_mangle_type (const_tree type
)
28233 type
= TYPE_MAIN_VARIANT (type
);
28235 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
28236 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
28239 if (type
== bool_char_type_node
) return "U6__boolc";
28240 if (type
== bool_short_type_node
) return "U6__bools";
28241 if (type
== pixel_type_node
) return "u7__pixel";
28242 if (type
== bool_int_type_node
) return "U6__booli";
28243 if (type
== bool_long_type_node
) return "U6__booll";
28245 /* Mangle IBM extended float long double as `g' (__float128) on
28246 powerpc*-linux where long-double-64 previously was the default. */
28247 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
28249 && TARGET_LONG_DOUBLE_128
28250 && !TARGET_IEEEQUAD
)
28253 /* For all other types, use normal C++ mangling. */
28257 /* Handle a "longcall" or "shortcall" attribute; arguments as in
28258 struct attribute_spec.handler. */
28261 rs6000_handle_longcall_attribute (tree
*node
, tree name
,
28262 tree args ATTRIBUTE_UNUSED
,
28263 int flags ATTRIBUTE_UNUSED
,
28264 bool *no_add_attrs
)
28266 if (TREE_CODE (*node
) != FUNCTION_TYPE
28267 && TREE_CODE (*node
) != FIELD_DECL
28268 && TREE_CODE (*node
) != TYPE_DECL
)
28270 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
28272 *no_add_attrs
= true;
28278 /* Set longcall attributes on all functions declared when
28279 rs6000_default_long_calls is true. */
28281 rs6000_set_default_type_attributes (tree type
)
28283 if (rs6000_default_long_calls
28284 && (TREE_CODE (type
) == FUNCTION_TYPE
28285 || TREE_CODE (type
) == METHOD_TYPE
))
28286 TYPE_ATTRIBUTES (type
) = tree_cons (get_identifier ("longcall"),
28288 TYPE_ATTRIBUTES (type
));
28291 darwin_set_default_type_attributes (type
);
28295 /* Return a reference suitable for calling a function with the
28296 longcall attribute. */
28299 rs6000_longcall_ref (rtx call_ref
)
28301 const char *call_name
;
28304 if (GET_CODE (call_ref
) != SYMBOL_REF
)
28307 /* System V adds '.' to the internal name, so skip them. */
28308 call_name
= XSTR (call_ref
, 0);
28309 if (*call_name
== '.')
28311 while (*call_name
== '.')
28314 node
= get_identifier (call_name
);
28315 call_ref
= gen_rtx_SYMBOL_REF (VOIDmode
, IDENTIFIER_POINTER (node
));
28318 return force_reg (Pmode
, call_ref
);
28321 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
28322 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
28325 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
28326 struct attribute_spec.handler. */
28328 rs6000_handle_struct_attribute (tree
*node
, tree name
,
28329 tree args ATTRIBUTE_UNUSED
,
28330 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
28333 if (DECL_P (*node
))
28335 if (TREE_CODE (*node
) == TYPE_DECL
)
28336 type
= &TREE_TYPE (*node
);
28341 if (!(type
&& (TREE_CODE (*type
) == RECORD_TYPE
28342 || TREE_CODE (*type
) == UNION_TYPE
)))
28344 warning (OPT_Wattributes
, "%qE attribute ignored", name
);
28345 *no_add_attrs
= true;
28348 else if ((is_attribute_p ("ms_struct", name
)
28349 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type
)))
28350 || ((is_attribute_p ("gcc_struct", name
)
28351 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type
)))))
28353 warning (OPT_Wattributes
, "%qE incompatible attribute ignored",
28355 *no_add_attrs
= true;
28362 rs6000_ms_bitfield_layout_p (const_tree record_type
)
28364 return (TARGET_USE_MS_BITFIELD_LAYOUT
&&
28365 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type
)))
28366 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type
));
28369 #ifdef USING_ELFOS_H
28371 /* A get_unnamed_section callback, used for switching to toc_section. */
28374 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
28376 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
28377 && TARGET_MINIMAL_TOC
28378 && !TARGET_RELOCATABLE
)
28380 if (!toc_initialized
)
28382 toc_initialized
= 1;
28383 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
28384 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LCTOC", 0);
28385 fprintf (asm_out_file
, "\t.tc ");
28386 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1[TC],");
28387 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
28388 fprintf (asm_out_file
, "\n");
28390 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
28391 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
28392 fprintf (asm_out_file
, " = .+32768\n");
28395 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
28397 else if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
28398 && !TARGET_RELOCATABLE
)
28399 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
28402 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
28403 if (!toc_initialized
)
28405 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
28406 fprintf (asm_out_file
, " = .+32768\n");
28407 toc_initialized
= 1;
28412 /* Implement TARGET_ASM_INIT_SECTIONS. */
28415 rs6000_elf_asm_init_sections (void)
28418 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op
, NULL
);
28421 = get_unnamed_section (SECTION_WRITE
, output_section_asm_op
,
28422 SDATA2_SECTION_ASM_OP
);
28425 /* Implement TARGET_SELECT_RTX_SECTION. */
28428 rs6000_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
28429 unsigned HOST_WIDE_INT align
)
28431 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
28432 return toc_section
;
28434 return default_elf_select_rtx_section (mode
, x
, align
);
28437 /* For a SYMBOL_REF, set generic flags and then perform some
28438 target-specific processing.
28440 When the AIX ABI is requested on a non-AIX system, replace the
28441 function name with the real name (with a leading .) rather than the
28442 function descriptor name. This saves a lot of overriding code to
28443 read the prefixes. */
28445 static void rs6000_elf_encode_section_info (tree
, rtx
, int) ATTRIBUTE_UNUSED
;
28447 rs6000_elf_encode_section_info (tree decl
, rtx rtl
, int first
)
28449 default_encode_section_info (decl
, rtl
, first
);
28452 && TREE_CODE (decl
) == FUNCTION_DECL
28454 && DEFAULT_ABI
== ABI_AIX
)
28456 rtx sym_ref
= XEXP (rtl
, 0);
28457 size_t len
= strlen (XSTR (sym_ref
, 0));
28458 char *str
= XALLOCAVEC (char, len
+ 2);
28460 memcpy (str
+ 1, XSTR (sym_ref
, 0), len
+ 1);
28461 XSTR (sym_ref
, 0) = ggc_alloc_string (str
, len
+ 1);
28466 compare_section_name (const char *section
, const char *templ
)
28470 len
= strlen (templ
);
28471 return (strncmp (section
, templ
, len
) == 0
28472 && (section
[len
] == 0 || section
[len
] == '.'));
28476 rs6000_elf_in_small_data_p (const_tree decl
)
28478 if (rs6000_sdata
== SDATA_NONE
)
28481 /* We want to merge strings, so we never consider them small data. */
28482 if (TREE_CODE (decl
) == STRING_CST
)
28485 /* Functions are never in the small data area. */
28486 if (TREE_CODE (decl
) == FUNCTION_DECL
)
28489 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
))
28491 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
28492 if (compare_section_name (section
, ".sdata")
28493 || compare_section_name (section
, ".sdata2")
28494 || compare_section_name (section
, ".gnu.linkonce.s")
28495 || compare_section_name (section
, ".sbss")
28496 || compare_section_name (section
, ".sbss2")
28497 || compare_section_name (section
, ".gnu.linkonce.sb")
28498 || strcmp (section
, ".PPC.EMB.sdata0") == 0
28499 || strcmp (section
, ".PPC.EMB.sbss0") == 0)
28504 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
28507 && size
<= g_switch_value
28508 /* If it's not public, and we're not going to reference it there,
28509 there's no need to put it in the small data section. */
28510 && (rs6000_sdata
!= SDATA_DATA
|| TREE_PUBLIC (decl
)))
28517 #endif /* USING_ELFOS_H */
28519 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
28522 rs6000_use_blocks_for_constant_p (enum machine_mode mode
, const_rtx x
)
28524 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
);
28527 /* Do not place thread-local symbols refs in the object blocks. */
28530 rs6000_use_blocks_for_decl_p (const_tree decl
)
28532 return !DECL_THREAD_LOCAL_P (decl
);
28535 /* Return a REG that occurs in ADDR with coefficient 1.
28536 ADDR can be effectively incremented by incrementing REG.
28538 r0 is special and we must not select it as an address
28539 register by this routine since our caller will try to
28540 increment the returned register via an "la" instruction. */
28543 find_addr_reg (rtx addr
)
28545 while (GET_CODE (addr
) == PLUS
)
28547 if (GET_CODE (XEXP (addr
, 0)) == REG
28548 && REGNO (XEXP (addr
, 0)) != 0)
28549 addr
= XEXP (addr
, 0);
28550 else if (GET_CODE (XEXP (addr
, 1)) == REG
28551 && REGNO (XEXP (addr
, 1)) != 0)
28552 addr
= XEXP (addr
, 1);
28553 else if (CONSTANT_P (XEXP (addr
, 0)))
28554 addr
= XEXP (addr
, 1);
28555 else if (CONSTANT_P (XEXP (addr
, 1)))
28556 addr
= XEXP (addr
, 0);
28558 gcc_unreachable ();
28560 gcc_assert (GET_CODE (addr
) == REG
&& REGNO (addr
) != 0);
28565 rs6000_fatal_bad_address (rtx op
)
28567 fatal_insn ("bad address", op
);
28572 typedef struct branch_island_d
{
28573 tree function_name
;
28579 static vec
<branch_island
, va_gc
> *branch_islands
;
28581 /* Remember to generate a branch island for far calls to the given
28585 add_compiler_branch_island (tree label_name
, tree function_name
,
28588 branch_island bi
= {function_name
, label_name
, line_number
};
28589 vec_safe_push (branch_islands
, bi
);
28592 /* Generate far-jump branch islands for everything recorded in
28593 branch_islands. Invoked immediately after the last instruction of
28594 the epilogue has been emitted; the branch islands must be appended
28595 to, and contiguous with, the function body. Mach-O stubs are
28596 generated in machopic_output_stub(). */
28599 macho_branch_islands (void)
28603 while (!vec_safe_is_empty (branch_islands
))
28605 branch_island
*bi
= &branch_islands
->last ();
28606 const char *label
= IDENTIFIER_POINTER (bi
->label_name
);
28607 const char *name
= IDENTIFIER_POINTER (bi
->function_name
);
28608 char name_buf
[512];
28609 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
28610 if (name
[0] == '*' || name
[0] == '&')
28611 strcpy (name_buf
, name
+1);
28615 strcpy (name_buf
+1, name
);
28617 strcpy (tmp_buf
, "\n");
28618 strcat (tmp_buf
, label
);
28619 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
28620 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
28621 dbxout_stabd (N_SLINE
, bi
->line_number
);
28622 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
28625 if (TARGET_LINK_STACK
)
28628 get_ppc476_thunk_name (name
);
28629 strcat (tmp_buf
, ":\n\tmflr r0\n\tbl ");
28630 strcat (tmp_buf
, name
);
28631 strcat (tmp_buf
, "\n");
28632 strcat (tmp_buf
, label
);
28633 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
28637 strcat (tmp_buf
, ":\n\tmflr r0\n\tbcl 20,31,");
28638 strcat (tmp_buf
, label
);
28639 strcat (tmp_buf
, "_pic\n");
28640 strcat (tmp_buf
, label
);
28641 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
28644 strcat (tmp_buf
, "\taddis r11,r11,ha16(");
28645 strcat (tmp_buf
, name_buf
);
28646 strcat (tmp_buf
, " - ");
28647 strcat (tmp_buf
, label
);
28648 strcat (tmp_buf
, "_pic)\n");
28650 strcat (tmp_buf
, "\tmtlr r0\n");
28652 strcat (tmp_buf
, "\taddi r12,r11,lo16(");
28653 strcat (tmp_buf
, name_buf
);
28654 strcat (tmp_buf
, " - ");
28655 strcat (tmp_buf
, label
);
28656 strcat (tmp_buf
, "_pic)\n");
28658 strcat (tmp_buf
, "\tmtctr r12\n\tbctr\n");
28662 strcat (tmp_buf
, ":\nlis r12,hi16(");
28663 strcat (tmp_buf
, name_buf
);
28664 strcat (tmp_buf
, ")\n\tori r12,r12,lo16(");
28665 strcat (tmp_buf
, name_buf
);
28666 strcat (tmp_buf
, ")\n\tmtctr r12\n\tbctr");
28668 output_asm_insn (tmp_buf
, 0);
28669 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
28670 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
28671 dbxout_stabd (N_SLINE
, bi
->line_number
);
28672 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
28673 branch_islands
->pop ();
28677 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
28678 already there or not. */
28681 no_previous_def (tree function_name
)
28686 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
28687 if (function_name
== bi
->function_name
)
28692 /* GET_PREV_LABEL gets the label name from the previous definition of
28696 get_prev_label (tree function_name
)
28701 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
28702 if (function_name
== bi
->function_name
)
28703 return bi
->label_name
;
28707 /* INSN is either a function call or a millicode call. It may have an
28708 unconditional jump in its delay slot.
28710 CALL_DEST is the routine we are calling. */
28713 output_call (rtx insn
, rtx
*operands
, int dest_operand_number
,
28714 int cookie_operand_number
)
28716 static char buf
[256];
28717 if (darwin_emit_branch_islands
28718 && GET_CODE (operands
[dest_operand_number
]) == SYMBOL_REF
28719 && (INTVAL (operands
[cookie_operand_number
]) & CALL_LONG
))
28722 tree funname
= get_identifier (XSTR (operands
[dest_operand_number
], 0));
28724 if (no_previous_def (funname
))
28726 rtx label_rtx
= gen_label_rtx ();
28727 char *label_buf
, temp_buf
[256];
28728 ASM_GENERATE_INTERNAL_LABEL (temp_buf
, "L",
28729 CODE_LABEL_NUMBER (label_rtx
));
28730 label_buf
= temp_buf
[0] == '*' ? temp_buf
+ 1 : temp_buf
;
28731 labelname
= get_identifier (label_buf
);
28732 add_compiler_branch_island (labelname
, funname
, insn_line (insn
));
28735 labelname
= get_prev_label (funname
);
28737 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
28738 instruction will reach 'foo', otherwise link as 'bl L42'".
28739 "L42" should be a 'branch island', that will do a far jump to
28740 'foo'. Branch islands are generated in
28741 macho_branch_islands(). */
28742 sprintf (buf
, "jbsr %%z%d,%.246s",
28743 dest_operand_number
, IDENTIFIER_POINTER (labelname
));
28746 sprintf (buf
, "bl %%z%d", dest_operand_number
);
28750 /* Generate PIC and indirect symbol stubs. */
28753 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
28755 unsigned int length
;
28756 char *symbol_name
, *lazy_ptr_name
;
28757 char *local_label_0
;
28758 static int label
= 0;
28760 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
28761 symb
= (*targetm
.strip_name_encoding
) (symb
);
28764 length
= strlen (symb
);
28765 symbol_name
= XALLOCAVEC (char, length
+ 32);
28766 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
28768 lazy_ptr_name
= XALLOCAVEC (char, length
+ 32);
28769 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name
, symb
, length
);
28772 switch_to_section (darwin_sections
[machopic_picsymbol_stub1_section
]);
28774 switch_to_section (darwin_sections
[machopic_symbol_stub1_section
]);
28778 fprintf (file
, "\t.align 5\n");
28780 fprintf (file
, "%s:\n", stub
);
28781 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
28784 local_label_0
= XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
28785 sprintf (local_label_0
, "\"L%011d$spb\"", label
);
28787 fprintf (file
, "\tmflr r0\n");
28788 if (TARGET_LINK_STACK
)
28791 get_ppc476_thunk_name (name
);
28792 fprintf (file
, "\tbl %s\n", name
);
28793 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
28797 fprintf (file
, "\tbcl 20,31,%s\n", local_label_0
);
28798 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
28800 fprintf (file
, "\taddis r11,r11,ha16(%s-%s)\n",
28801 lazy_ptr_name
, local_label_0
);
28802 fprintf (file
, "\tmtlr r0\n");
28803 fprintf (file
, "\t%s r12,lo16(%s-%s)(r11)\n",
28804 (TARGET_64BIT
? "ldu" : "lwzu"),
28805 lazy_ptr_name
, local_label_0
);
28806 fprintf (file
, "\tmtctr r12\n");
28807 fprintf (file
, "\tbctr\n");
28811 fprintf (file
, "\t.align 4\n");
28813 fprintf (file
, "%s:\n", stub
);
28814 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
28816 fprintf (file
, "\tlis r11,ha16(%s)\n", lazy_ptr_name
);
28817 fprintf (file
, "\t%s r12,lo16(%s)(r11)\n",
28818 (TARGET_64BIT
? "ldu" : "lwzu"),
28820 fprintf (file
, "\tmtctr r12\n");
28821 fprintf (file
, "\tbctr\n");
28824 switch_to_section (darwin_sections
[machopic_lazy_symbol_ptr_section
]);
28825 fprintf (file
, "%s:\n", lazy_ptr_name
);
28826 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
28827 fprintf (file
, "%sdyld_stub_binding_helper\n",
28828 (TARGET_64BIT
? DOUBLE_INT_ASM_OP
: "\t.long\t"));
28831 /* Legitimize PIC addresses. If the address is already
28832 position-independent, we return ORIG. Newly generated
28833 position-independent addresses go into a reg. This is REG if non
28834 zero, otherwise we allocate register(s) as necessary. */
28836 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
28839 rs6000_machopic_legitimize_pic_address (rtx orig
, enum machine_mode mode
,
28844 if (reg
== NULL
&& ! reload_in_progress
&& ! reload_completed
)
28845 reg
= gen_reg_rtx (Pmode
);
28847 if (GET_CODE (orig
) == CONST
)
28851 if (GET_CODE (XEXP (orig
, 0)) == PLUS
28852 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
28855 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
28857 /* Use a different reg for the intermediate value, as
28858 it will be marked UNCHANGING. */
28859 reg_temp
= !can_create_pseudo_p () ? reg
: gen_reg_rtx (Pmode
);
28860 base
= rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0),
28863 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
28866 if (GET_CODE (offset
) == CONST_INT
)
28868 if (SMALL_INT (offset
))
28869 return plus_constant (Pmode
, base
, INTVAL (offset
));
28870 else if (! reload_in_progress
&& ! reload_completed
)
28871 offset
= force_reg (Pmode
, offset
);
28874 rtx mem
= force_const_mem (Pmode
, orig
);
28875 return machopic_legitimize_pic_address (mem
, Pmode
, reg
);
28878 return gen_rtx_PLUS (Pmode
, base
, offset
);
28881 /* Fall back on generic machopic code. */
28882 return machopic_legitimize_pic_address (orig
, mode
, reg
);
28885 /* Output a .machine directive for the Darwin assembler, and call
28886 the generic start_file routine. */
28889 rs6000_darwin_file_start (void)
28891 static const struct
28895 HOST_WIDE_INT if_set
;
28897 { "ppc64", "ppc64", MASK_64BIT
},
28898 { "970", "ppc970", MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
28899 { "power4", "ppc970", 0 },
28900 { "G5", "ppc970", 0 },
28901 { "7450", "ppc7450", 0 },
28902 { "7400", "ppc7400", MASK_ALTIVEC
},
28903 { "G4", "ppc7400", 0 },
28904 { "750", "ppc750", 0 },
28905 { "740", "ppc750", 0 },
28906 { "G3", "ppc750", 0 },
28907 { "604e", "ppc604e", 0 },
28908 { "604", "ppc604", 0 },
28909 { "603e", "ppc603", 0 },
28910 { "603", "ppc603", 0 },
28911 { "601", "ppc601", 0 },
28912 { NULL
, "ppc", 0 } };
28913 const char *cpu_id
= "";
28916 rs6000_file_start ();
28917 darwin_file_start ();
28919 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
28921 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
28922 cpu_id
= rs6000_default_cpu
;
28924 if (global_options_set
.x_rs6000_cpu_index
)
28925 cpu_id
= processor_target_table
[rs6000_cpu_index
].name
;
28927 /* Look through the mapping array. Pick the first name that either
28928 matches the argument, has a bit set in IF_SET that is also set
28929 in the target flags, or has a NULL name. */
28932 while (mapping
[i
].arg
!= NULL
28933 && strcmp (mapping
[i
].arg
, cpu_id
) != 0
28934 && (mapping
[i
].if_set
& rs6000_isa_flags
) == 0)
28937 fprintf (asm_out_file
, "\t.machine %s\n", mapping
[i
].name
);
28940 #endif /* TARGET_MACHO */
28944 rs6000_elf_reloc_rw_mask (void)
28948 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
28954 /* Record an element in the table of global constructors. SYMBOL is
28955 a SYMBOL_REF of the function to be called; PRIORITY is a number
28956 between 0 and MAX_INIT_PRIORITY.
28958 This differs from default_named_section_asm_out_constructor in
28959 that we have special handling for -mrelocatable. */
28961 static void rs6000_elf_asm_out_constructor (rtx
, int) ATTRIBUTE_UNUSED
;
28963 rs6000_elf_asm_out_constructor (rtx symbol
, int priority
)
28965 const char *section
= ".ctors";
28968 if (priority
!= DEFAULT_INIT_PRIORITY
)
28970 sprintf (buf
, ".ctors.%.5u",
28971 /* Invert the numbering so the linker puts us in the proper
28972 order; constructors are run from right to left, and the
28973 linker sorts in increasing order. */
28974 MAX_INIT_PRIORITY
- priority
);
28978 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
28979 assemble_align (POINTER_SIZE
);
28981 if (TARGET_RELOCATABLE
)
28983 fputs ("\t.long (", asm_out_file
);
28984 output_addr_const (asm_out_file
, symbol
);
28985 fputs (")@fixup\n", asm_out_file
);
28988 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
28991 static void rs6000_elf_asm_out_destructor (rtx
, int) ATTRIBUTE_UNUSED
;
28993 rs6000_elf_asm_out_destructor (rtx symbol
, int priority
)
28995 const char *section
= ".dtors";
28998 if (priority
!= DEFAULT_INIT_PRIORITY
)
29000 sprintf (buf
, ".dtors.%.5u",
29001 /* Invert the numbering so the linker puts us in the proper
29002 order; constructors are run from right to left, and the
29003 linker sorts in increasing order. */
29004 MAX_INIT_PRIORITY
- priority
);
29008 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
29009 assemble_align (POINTER_SIZE
);
29011 if (TARGET_RELOCATABLE
)
29013 fputs ("\t.long (", asm_out_file
);
29014 output_addr_const (asm_out_file
, symbol
);
29015 fputs (")@fixup\n", asm_out_file
);
29018 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
29022 rs6000_elf_declare_function_name (FILE *file
, const char *name
, tree decl
)
29024 if (TARGET_64BIT
&& DEFAULT_ABI
!= ABI_ELFv2
)
29026 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file
);
29027 ASM_OUTPUT_LABEL (file
, name
);
29028 fputs (DOUBLE_INT_ASM_OP
, file
);
29029 rs6000_output_function_entry (file
, name
);
29030 fputs (",.TOC.@tocbase,0\n\t.previous\n", file
);
29033 fputs ("\t.size\t", file
);
29034 assemble_name (file
, name
);
29035 fputs (",24\n\t.type\t.", file
);
29036 assemble_name (file
, name
);
29037 fputs (",@function\n", file
);
29038 if (TREE_PUBLIC (decl
) && ! DECL_WEAK (decl
))
29040 fputs ("\t.globl\t.", file
);
29041 assemble_name (file
, name
);
29046 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
29047 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
29048 rs6000_output_function_entry (file
, name
);
29049 fputs (":\n", file
);
29053 if (TARGET_RELOCATABLE
29054 && !TARGET_SECURE_PLT
29055 && (get_pool_size () != 0 || crtl
->profile
)
29060 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
29062 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
29063 fprintf (file
, "\t.long ");
29064 assemble_name (file
, buf
);
29066 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
29067 assemble_name (file
, buf
);
29071 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
29072 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
29074 if (DEFAULT_ABI
== ABI_AIX
)
29076 const char *desc_name
, *orig_name
;
29078 orig_name
= (*targetm
.strip_name_encoding
) (name
);
29079 desc_name
= orig_name
;
29080 while (*desc_name
== '.')
29083 if (TREE_PUBLIC (decl
))
29084 fprintf (file
, "\t.globl %s\n", desc_name
);
29086 fprintf (file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
29087 fprintf (file
, "%s:\n", desc_name
);
29088 fprintf (file
, "\t.long %s\n", orig_name
);
29089 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file
);
29090 fputs ("\t.long 0\n", file
);
29091 fprintf (file
, "\t.previous\n");
29093 ASM_OUTPUT_LABEL (file
, name
);
29096 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED
;
29098 rs6000_elf_file_end (void)
29100 #ifdef HAVE_AS_GNU_ATTRIBUTE
29101 if (TARGET_32BIT
&& DEFAULT_ABI
== ABI_V4
)
29103 if (rs6000_passes_float
)
29104 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n",
29105 ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
) ? 1
29106 : (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_SINGLE_FLOAT
) ? 3
29108 if (rs6000_passes_vector
)
29109 fprintf (asm_out_file
, "\t.gnu_attribute 8, %d\n",
29110 (TARGET_ALTIVEC_ABI
? 2
29111 : TARGET_SPE_ABI
? 3
29113 if (rs6000_returns_struct
)
29114 fprintf (asm_out_file
, "\t.gnu_attribute 12, %d\n",
29115 aix_struct_return
? 2 : 1);
29118 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
29119 if (TARGET_32BIT
|| DEFAULT_ABI
== ABI_ELFv2
)
29120 file_end_indicate_exec_stack ();
29127 rs6000_xcoff_asm_output_anchor (rtx symbol
)
29131 sprintf (buffer
, "$ + " HOST_WIDE_INT_PRINT_DEC
,
29132 SYMBOL_REF_BLOCK_OFFSET (symbol
));
29133 ASM_OUTPUT_DEF (asm_out_file
, XSTR (symbol
, 0), buffer
);
29137 rs6000_xcoff_asm_globalize_label (FILE *stream
, const char *name
)
29139 fputs (GLOBAL_ASM_OP
, stream
);
29140 RS6000_OUTPUT_BASENAME (stream
, name
);
29141 putc ('\n', stream
);
29144 /* A get_unnamed_decl callback, used for read-only sections. PTR
29145 points to the section string variable. */
29148 rs6000_xcoff_output_readonly_section_asm_op (const void *directive
)
29150 fprintf (asm_out_file
, "\t.csect %s[RO],%s\n",
29151 *(const char *const *) directive
,
29152 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
29155 /* Likewise for read-write sections. */
29158 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive
)
29160 fprintf (asm_out_file
, "\t.csect %s[RW],%s\n",
29161 *(const char *const *) directive
,
29162 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
29166 rs6000_xcoff_output_tls_section_asm_op (const void *directive
)
29168 fprintf (asm_out_file
, "\t.csect %s[TL],%s\n",
29169 *(const char *const *) directive
,
29170 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
29173 /* A get_unnamed_section callback, used for switching to toc_section. */
29176 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
29178 if (TARGET_MINIMAL_TOC
)
29180 /* toc_section is always selected at least once from
29181 rs6000_xcoff_file_start, so this is guaranteed to
29182 always be defined once and only once in each file. */
29183 if (!toc_initialized
)
29185 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file
);
29186 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file
);
29187 toc_initialized
= 1;
29189 fprintf (asm_out_file
, "\t.csect toc_table[RW]%s\n",
29190 (TARGET_32BIT
? "" : ",3"));
29193 fputs ("\t.toc\n", asm_out_file
);
29196 /* Implement TARGET_ASM_INIT_SECTIONS. */
29199 rs6000_xcoff_asm_init_sections (void)
29201 read_only_data_section
29202 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
29203 &xcoff_read_only_section_name
);
29205 private_data_section
29206 = get_unnamed_section (SECTION_WRITE
,
29207 rs6000_xcoff_output_readwrite_section_asm_op
,
29208 &xcoff_private_data_section_name
);
29211 = get_unnamed_section (SECTION_TLS
,
29212 rs6000_xcoff_output_tls_section_asm_op
,
29213 &xcoff_tls_data_section_name
);
29215 tls_private_data_section
29216 = get_unnamed_section (SECTION_TLS
,
29217 rs6000_xcoff_output_tls_section_asm_op
,
29218 &xcoff_private_data_section_name
);
29220 read_only_private_data_section
29221 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
29222 &xcoff_private_data_section_name
);
29225 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op
, NULL
);
29227 readonly_data_section
= read_only_data_section
;
29228 exception_section
= data_section
;
29232 rs6000_xcoff_reloc_rw_mask (void)
29238 rs6000_xcoff_asm_named_section (const char *name
, unsigned int flags
,
29239 tree decl ATTRIBUTE_UNUSED
)
29242 static const char * const suffix
[4] = { "PR", "RO", "RW", "TL" };
29244 if (flags
& SECTION_CODE
)
29246 else if (flags
& SECTION_TLS
)
29248 else if (flags
& SECTION_WRITE
)
29253 fprintf (asm_out_file
, "\t.csect %s%s[%s],%u\n",
29254 (flags
& SECTION_CODE
) ? "." : "",
29255 name
, suffix
[smclass
], flags
& SECTION_ENTSIZE
);
29258 #define IN_NAMED_SECTION(DECL) \
29259 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
29260 && DECL_SECTION_NAME (DECL) != NULL_TREE)
29263 rs6000_xcoff_select_section (tree decl
, int reloc
,
29264 unsigned HOST_WIDE_INT align
)
29266 /* Place variables with alignment stricter than BIGGEST_ALIGNMENT into
29268 if (align
> BIGGEST_ALIGNMENT
)
29270 resolve_unique_section (decl
, reloc
, true);
29271 if (IN_NAMED_SECTION (decl
))
29272 return get_named_section (decl
, NULL
, reloc
);
29275 if (decl_readonly_section (decl
, reloc
))
29277 if (TREE_PUBLIC (decl
))
29278 return read_only_data_section
;
29280 return read_only_private_data_section
;
29285 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
29287 if (TREE_PUBLIC (decl
))
29288 return tls_data_section
;
29289 else if (bss_initializer_p (decl
))
29291 /* Convert to COMMON to emit in BSS. */
29292 DECL_COMMON (decl
) = 1;
29293 return tls_comm_section
;
29296 return tls_private_data_section
;
29300 if (TREE_PUBLIC (decl
))
29301 return data_section
;
29303 return private_data_section
;
29308 rs6000_xcoff_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
29312 /* Use select_section for private data and uninitialized data with
29313 alignment <= BIGGEST_ALIGNMENT. */
29314 if (!TREE_PUBLIC (decl
)
29315 || DECL_COMMON (decl
)
29316 || (DECL_INITIAL (decl
) == NULL_TREE
29317 && DECL_ALIGN (decl
) <= BIGGEST_ALIGNMENT
)
29318 || DECL_INITIAL (decl
) == error_mark_node
29319 || (flag_zero_initialized_in_bss
29320 && initializer_zerop (DECL_INITIAL (decl
))))
29323 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
29324 name
= (*targetm
.strip_name_encoding
) (name
);
29325 DECL_SECTION_NAME (decl
) = build_string (strlen (name
), name
);
29328 /* Select section for constant in constant pool.
29330 On RS/6000, all constants are in the private read-only data area.
29331 However, if this is being placed in the TOC it must be output as a
29335 rs6000_xcoff_select_rtx_section (enum machine_mode mode
, rtx x
,
29336 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
29338 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
29339 return toc_section
;
29341 return read_only_private_data_section
;
29344 /* Remove any trailing [DS] or the like from the symbol name. */
29346 static const char *
29347 rs6000_xcoff_strip_name_encoding (const char *name
)
29352 len
= strlen (name
);
29353 if (name
[len
- 1] == ']')
29354 return ggc_alloc_string (name
, len
- 4);
29359 /* Section attributes. AIX is always PIC. */
29361 static unsigned int
29362 rs6000_xcoff_section_type_flags (tree decl
, const char *name
, int reloc
)
29364 unsigned int align
;
29365 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
29367 /* Align to at least UNIT size. */
29368 if ((flags
& SECTION_CODE
) != 0 || !decl
|| !DECL_P (decl
))
29369 align
= MIN_UNITS_PER_WORD
;
29371 /* Increase alignment of large objects if not already stricter. */
29372 align
= MAX ((DECL_ALIGN (decl
) / BITS_PER_UNIT
),
29373 int_size_in_bytes (TREE_TYPE (decl
)) > MIN_UNITS_PER_WORD
29374 ? UNITS_PER_FP_WORD
: MIN_UNITS_PER_WORD
);
29376 return flags
| (exact_log2 (align
) & SECTION_ENTSIZE
);
29379 /* Output at beginning of assembler file.
29381 Initialize the section names for the RS/6000 at this point.
29383 Specify filename, including full path, to assembler.
29385 We want to go into the TOC section so at least one .toc will be emitted.
29386 Also, in order to output proper .bs/.es pairs, we need at least one static
29387 [RW] section emitted.
29389 Finally, declare mcount when profiling to make the assembler happy. */
29392 rs6000_xcoff_file_start (void)
29394 rs6000_gen_section_name (&xcoff_bss_section_name
,
29395 main_input_filename
, ".bss_");
29396 rs6000_gen_section_name (&xcoff_private_data_section_name
,
29397 main_input_filename
, ".rw_");
29398 rs6000_gen_section_name (&xcoff_read_only_section_name
,
29399 main_input_filename
, ".ro_");
29400 rs6000_gen_section_name (&xcoff_tls_data_section_name
,
29401 main_input_filename
, ".tls_");
29402 rs6000_gen_section_name (&xcoff_tbss_section_name
,
29403 main_input_filename
, ".tbss_[UL]");
29405 fputs ("\t.file\t", asm_out_file
);
29406 output_quoted_string (asm_out_file
, main_input_filename
);
29407 fputc ('\n', asm_out_file
);
29408 if (write_symbols
!= NO_DEBUG
)
29409 switch_to_section (private_data_section
);
29410 switch_to_section (text_section
);
29412 fprintf (asm_out_file
, "\t.extern %s\n", RS6000_MCOUNT
);
29413 rs6000_file_start ();
29416 /* Output at end of assembler file.
29417 On the RS/6000, referencing data should automatically pull in text. */
29420 rs6000_xcoff_file_end (void)
29422 switch_to_section (text_section
);
29423 fputs ("_section_.text:\n", asm_out_file
);
29424 switch_to_section (data_section
);
29425 fputs (TARGET_32BIT
29426 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
29432 rs6000_xcoff_encode_section_info (tree decl
, rtx rtl
, int first
)
29437 default_encode_section_info (decl
, rtl
, first
);
29439 /* Careful not to prod global register variables. */
29442 symbol
= XEXP (rtl
, 0);
29443 if (GET_CODE (symbol
) != SYMBOL_REF
)
29446 flags
= SYMBOL_REF_FLAGS (symbol
);
29448 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
29449 flags
&= ~SYMBOL_FLAG_HAS_BLOCK_INFO
;
29451 SYMBOL_REF_FLAGS (symbol
) = flags
;
29453 #endif /* HAVE_AS_TLS */
29454 #endif /* TARGET_XCOFF */
29456 /* Compute a (partial) cost for rtx X. Return true if the complete
29457 cost has been computed, and false if subexpressions should be
29458 scanned. In either case, *TOTAL contains the cost result. */
29461 rs6000_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
29462 int *total
, bool speed
)
29464 enum machine_mode mode
= GET_MODE (x
);
29468 /* On the RS/6000, if it is valid in the insn, it is free. */
29470 if (((outer_code
== SET
29471 || outer_code
== PLUS
29472 || outer_code
== MINUS
)
29473 && (satisfies_constraint_I (x
)
29474 || satisfies_constraint_L (x
)))
29475 || (outer_code
== AND
29476 && (satisfies_constraint_K (x
)
29478 ? satisfies_constraint_L (x
)
29479 : satisfies_constraint_J (x
))
29480 || mask_operand (x
, mode
)
29482 && mask64_operand (x
, DImode
))))
29483 || ((outer_code
== IOR
|| outer_code
== XOR
)
29484 && (satisfies_constraint_K (x
)
29486 ? satisfies_constraint_L (x
)
29487 : satisfies_constraint_J (x
))))
29488 || outer_code
== ASHIFT
29489 || outer_code
== ASHIFTRT
29490 || outer_code
== LSHIFTRT
29491 || outer_code
== ROTATE
29492 || outer_code
== ROTATERT
29493 || outer_code
== ZERO_EXTRACT
29494 || (outer_code
== MULT
29495 && satisfies_constraint_I (x
))
29496 || ((outer_code
== DIV
|| outer_code
== UDIV
29497 || outer_code
== MOD
|| outer_code
== UMOD
)
29498 && exact_log2 (INTVAL (x
)) >= 0)
29499 || (outer_code
== COMPARE
29500 && (satisfies_constraint_I (x
)
29501 || satisfies_constraint_K (x
)))
29502 || ((outer_code
== EQ
|| outer_code
== NE
)
29503 && (satisfies_constraint_I (x
)
29504 || satisfies_constraint_K (x
)
29506 ? satisfies_constraint_L (x
)
29507 : satisfies_constraint_J (x
))))
29508 || (outer_code
== GTU
29509 && satisfies_constraint_I (x
))
29510 || (outer_code
== LTU
29511 && satisfies_constraint_P (x
)))
29516 else if ((outer_code
== PLUS
29517 && reg_or_add_cint_operand (x
, VOIDmode
))
29518 || (outer_code
== MINUS
29519 && reg_or_sub_cint_operand (x
, VOIDmode
))
29520 || ((outer_code
== SET
29521 || outer_code
== IOR
29522 || outer_code
== XOR
)
29524 & ~ (unsigned HOST_WIDE_INT
) 0xffffffff) == 0))
29526 *total
= COSTS_N_INSNS (1);
29532 case CONST_WIDE_INT
:
29537 /* When optimizing for size, MEM should be slightly more expensive
29538 than generating address, e.g., (plus (reg) (const)).
29539 L1 cache latency is about two instructions. */
29540 *total
= !speed
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
29549 if (FLOAT_MODE_P (mode
))
29550 *total
= rs6000_cost
->fp
;
29552 *total
= COSTS_N_INSNS (1);
29556 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
29557 && satisfies_constraint_I (XEXP (x
, 1)))
29559 if (INTVAL (XEXP (x
, 1)) >= -256
29560 && INTVAL (XEXP (x
, 1)) <= 255)
29561 *total
= rs6000_cost
->mulsi_const9
;
29563 *total
= rs6000_cost
->mulsi_const
;
29565 else if (mode
== SFmode
)
29566 *total
= rs6000_cost
->fp
;
29567 else if (FLOAT_MODE_P (mode
))
29568 *total
= rs6000_cost
->dmul
;
29569 else if (mode
== DImode
)
29570 *total
= rs6000_cost
->muldi
;
29572 *total
= rs6000_cost
->mulsi
;
29576 if (mode
== SFmode
)
29577 *total
= rs6000_cost
->fp
;
29579 *total
= rs6000_cost
->dmul
;
29584 if (FLOAT_MODE_P (mode
))
29586 *total
= mode
== DFmode
? rs6000_cost
->ddiv
29587 : rs6000_cost
->sdiv
;
29594 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
29595 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
29597 if (code
== DIV
|| code
== MOD
)
29599 *total
= COSTS_N_INSNS (2);
29602 *total
= COSTS_N_INSNS (1);
29606 if (GET_MODE (XEXP (x
, 1)) == DImode
)
29607 *total
= rs6000_cost
->divdi
;
29609 *total
= rs6000_cost
->divsi
;
29611 /* Add in shift and subtract for MOD. */
29612 if (code
== MOD
|| code
== UMOD
)
29613 *total
+= COSTS_N_INSNS (2);
29618 *total
= COSTS_N_INSNS (4);
29622 *total
= COSTS_N_INSNS (TARGET_POPCNTD
? 1 : 6);
29626 *total
= COSTS_N_INSNS (TARGET_CMPB
? 2 : 6);
29630 if (outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
29642 *total
= COSTS_N_INSNS (1);
29650 /* Handle mul_highpart. */
29651 if (outer_code
== TRUNCATE
29652 && GET_CODE (XEXP (x
, 0)) == MULT
)
29654 if (mode
== DImode
)
29655 *total
= rs6000_cost
->muldi
;
29657 *total
= rs6000_cost
->mulsi
;
29660 else if (outer_code
== AND
)
29663 *total
= COSTS_N_INSNS (1);
29668 if (GET_CODE (XEXP (x
, 0)) == MEM
)
29671 *total
= COSTS_N_INSNS (1);
29677 if (!FLOAT_MODE_P (mode
))
29679 *total
= COSTS_N_INSNS (1);
29685 case UNSIGNED_FLOAT
:
29688 case FLOAT_TRUNCATE
:
29689 *total
= rs6000_cost
->fp
;
29693 if (mode
== DFmode
)
29696 *total
= rs6000_cost
->fp
;
29700 switch (XINT (x
, 1))
29703 *total
= rs6000_cost
->fp
;
29715 *total
= COSTS_N_INSNS (1);
29718 else if (FLOAT_MODE_P (mode
)
29719 && TARGET_PPC_GFXOPT
&& TARGET_HARD_FLOAT
&& TARGET_FPRS
)
29721 *total
= rs6000_cost
->fp
;
29729 /* Carry bit requires mode == Pmode.
29730 NEG or PLUS already counted so only add one. */
29732 && (outer_code
== NEG
|| outer_code
== PLUS
))
29734 *total
= COSTS_N_INSNS (1);
29737 if (outer_code
== SET
)
29739 if (XEXP (x
, 1) == const0_rtx
)
29741 if (TARGET_ISEL
&& !TARGET_MFCRF
)
29742 *total
= COSTS_N_INSNS (8);
29744 *total
= COSTS_N_INSNS (2);
29747 else if (mode
== Pmode
)
29749 *total
= COSTS_N_INSNS (3);
29758 if (outer_code
== SET
&& (XEXP (x
, 1) == const0_rtx
))
29760 if (TARGET_ISEL
&& !TARGET_MFCRF
)
29761 *total
= COSTS_N_INSNS (8);
29763 *total
= COSTS_N_INSNS (2);
29767 if (outer_code
== COMPARE
)
29781 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
29784 rs6000_debug_rtx_costs (rtx x
, int code
, int outer_code
, int opno
, int *total
,
29787 bool ret
= rs6000_rtx_costs (x
, code
, outer_code
, opno
, total
, speed
);
29790 "\nrs6000_rtx_costs, return = %s, code = %s, outer_code = %s, "
29791 "opno = %d, total = %d, speed = %s, x:\n",
29792 ret
? "complete" : "scan inner",
29793 GET_RTX_NAME (code
),
29794 GET_RTX_NAME (outer_code
),
29797 speed
? "true" : "false");
29804 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
29807 rs6000_debug_address_cost (rtx x
, enum machine_mode mode
,
29808 addr_space_t as
, bool speed
)
29810 int ret
= TARGET_ADDRESS_COST (x
, mode
, as
, speed
);
29812 fprintf (stderr
, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
29813 ret
, speed
? "true" : "false");
29820 /* A C expression returning the cost of moving data from a register of class
29821 CLASS1 to one of CLASS2. */
29824 rs6000_register_move_cost (enum machine_mode mode
,
29825 reg_class_t from
, reg_class_t to
)
29829 if (TARGET_DEBUG_COST
)
29832 /* Moves from/to GENERAL_REGS. */
29833 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
29834 || reg_classes_intersect_p (from
, GENERAL_REGS
))
29836 reg_class_t rclass
= from
;
29838 if (! reg_classes_intersect_p (to
, GENERAL_REGS
))
29841 if (rclass
== FLOAT_REGS
|| rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
29842 ret
= (rs6000_memory_move_cost (mode
, rclass
, false)
29843 + rs6000_memory_move_cost (mode
, GENERAL_REGS
, false));
29845 /* It's more expensive to move CR_REGS than CR0_REGS because of the
29847 else if (rclass
== CR_REGS
)
29850 /* For those processors that have slow LR/CTR moves, make them more
29851 expensive than memory in order to bias spills to memory .*/
29852 else if ((rs6000_cpu
== PROCESSOR_POWER6
29853 || rs6000_cpu
== PROCESSOR_POWER7
29854 || rs6000_cpu
== PROCESSOR_POWER8
)
29855 && reg_classes_intersect_p (rclass
, LINK_OR_CTR_REGS
))
29856 ret
= 6 * hard_regno_nregs
[0][mode
];
29859 /* A move will cost one instruction per GPR moved. */
29860 ret
= 2 * hard_regno_nregs
[0][mode
];
29863 /* If we have VSX, we can easily move between FPR or Altivec registers. */
29864 else if (VECTOR_MEM_VSX_P (mode
)
29865 && reg_classes_intersect_p (to
, VSX_REGS
)
29866 && reg_classes_intersect_p (from
, VSX_REGS
))
29867 ret
= 2 * hard_regno_nregs
[32][mode
];
29869 /* Moving between two similar registers is just one instruction. */
29870 else if (reg_classes_intersect_p (to
, from
))
29871 ret
= (mode
== TFmode
|| mode
== TDmode
) ? 4 : 2;
29873 /* Everything else has to go through GENERAL_REGS. */
29875 ret
= (rs6000_register_move_cost (mode
, GENERAL_REGS
, to
)
29876 + rs6000_register_move_cost (mode
, from
, GENERAL_REGS
));
29878 if (TARGET_DEBUG_COST
)
29880 if (dbg_cost_ctrl
== 1)
29882 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
29883 ret
, GET_MODE_NAME (mode
), reg_class_names
[from
],
29884 reg_class_names
[to
]);
29891 /* A C expressions returning the cost of moving data of MODE from a register to
29895 rs6000_memory_move_cost (enum machine_mode mode
, reg_class_t rclass
,
29896 bool in ATTRIBUTE_UNUSED
)
29900 if (TARGET_DEBUG_COST
)
29903 if (reg_classes_intersect_p (rclass
, GENERAL_REGS
))
29904 ret
= 4 * hard_regno_nregs
[0][mode
];
29905 else if ((reg_classes_intersect_p (rclass
, FLOAT_REGS
)
29906 || reg_classes_intersect_p (rclass
, VSX_REGS
)))
29907 ret
= 4 * hard_regno_nregs
[32][mode
];
29908 else if (reg_classes_intersect_p (rclass
, ALTIVEC_REGS
))
29909 ret
= 4 * hard_regno_nregs
[FIRST_ALTIVEC_REGNO
][mode
];
29911 ret
= 4 + rs6000_register_move_cost (mode
, rclass
, GENERAL_REGS
);
29913 if (TARGET_DEBUG_COST
)
29915 if (dbg_cost_ctrl
== 1)
29917 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
29918 ret
, GET_MODE_NAME (mode
), reg_class_names
[rclass
], in
);
29925 /* Returns a code for a target-specific builtin that implements
29926 reciprocal of the function, or NULL_TREE if not available. */
29929 rs6000_builtin_reciprocal (unsigned int fn
, bool md_fn
,
29930 bool sqrt ATTRIBUTE_UNUSED
)
29932 if (optimize_insn_for_size_p ())
29938 case VSX_BUILTIN_XVSQRTDP
:
29939 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode
))
29942 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
29944 case VSX_BUILTIN_XVSQRTSP
:
29945 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode
))
29948 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_4SF
];
29957 case BUILT_IN_SQRT
:
29958 if (!RS6000_RECIP_AUTO_RSQRTE_P (DFmode
))
29961 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRT
];
29963 case BUILT_IN_SQRTF
:
29964 if (!RS6000_RECIP_AUTO_RSQRTE_P (SFmode
))
29967 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRTF
];
29974 /* Load up a constant. If the mode is a vector mode, splat the value across
29975 all of the vector elements. */
29978 rs6000_load_constant_and_splat (enum machine_mode mode
, REAL_VALUE_TYPE dconst
)
29982 if (mode
== SFmode
|| mode
== DFmode
)
29984 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, mode
);
29985 reg
= force_reg (mode
, d
);
29987 else if (mode
== V4SFmode
)
29989 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, SFmode
);
29990 rtvec v
= gen_rtvec (4, d
, d
, d
, d
);
29991 reg
= gen_reg_rtx (mode
);
29992 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
29994 else if (mode
== V2DFmode
)
29996 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, DFmode
);
29997 rtvec v
= gen_rtvec (2, d
, d
);
29998 reg
= gen_reg_rtx (mode
);
29999 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
30002 gcc_unreachable ();
30007 /* Generate an FMA instruction. */
30010 rs6000_emit_madd (rtx target
, rtx m1
, rtx m2
, rtx a
)
30012 enum machine_mode mode
= GET_MODE (target
);
30015 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
30016 gcc_assert (dst
!= NULL
);
30019 emit_move_insn (target
, dst
);
30022 /* Generate a FMSUB instruction: dst = fma(m1, m2, -a). */
30025 rs6000_emit_msub (rtx target
, rtx m1
, rtx m2
, rtx a
)
30027 enum machine_mode mode
= GET_MODE (target
);
30030 /* Altivec does not support fms directly;
30031 generate in terms of fma in that case. */
30032 if (optab_handler (fms_optab
, mode
) != CODE_FOR_nothing
)
30033 dst
= expand_ternary_op (mode
, fms_optab
, m1
, m2
, a
, target
, 0);
30036 a
= expand_unop (mode
, neg_optab
, a
, NULL_RTX
, 0);
30037 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
30039 gcc_assert (dst
!= NULL
);
30042 emit_move_insn (target
, dst
);
30045 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
30048 rs6000_emit_nmsub (rtx dst
, rtx m1
, rtx m2
, rtx a
)
30050 enum machine_mode mode
= GET_MODE (dst
);
30053 /* This is a tad more complicated, since the fnma_optab is for
30054 a different expression: fma(-m1, m2, a), which is the same
30055 thing except in the case of signed zeros.
30057 Fortunately we know that if FMA is supported that FNMSUB is
30058 also supported in the ISA. Just expand it directly. */
30060 gcc_assert (optab_handler (fma_optab
, mode
) != CODE_FOR_nothing
);
30062 r
= gen_rtx_NEG (mode
, a
);
30063 r
= gen_rtx_FMA (mode
, m1
, m2
, r
);
30064 r
= gen_rtx_NEG (mode
, r
);
30065 emit_insn (gen_rtx_SET (VOIDmode
, dst
, r
));
30068 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
30069 add a reg_note saying that this was a division. Support both scalar and
30070 vector divide. Assumes no trapping math and finite arguments. */
30073 rs6000_emit_swdiv (rtx dst
, rtx n
, rtx d
, bool note_p
)
30075 enum machine_mode mode
= GET_MODE (dst
);
30076 rtx one
, x0
, e0
, x1
, xprev
, eprev
, xnext
, enext
, u
, v
;
30079 /* Low precision estimates guarantee 5 bits of accuracy. High
30080 precision estimates guarantee 14 bits of accuracy. SFmode
30081 requires 23 bits of accuracy. DFmode requires 52 bits of
30082 accuracy. Each pass at least doubles the accuracy, leading
30083 to the following. */
30084 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
30085 if (mode
== DFmode
|| mode
== V2DFmode
)
30088 enum insn_code code
= optab_handler (smul_optab
, mode
);
30089 insn_gen_fn gen_mul
= GEN_FCN (code
);
30091 gcc_assert (code
!= CODE_FOR_nothing
);
30093 one
= rs6000_load_constant_and_splat (mode
, dconst1
);
30095 /* x0 = 1./d estimate */
30096 x0
= gen_reg_rtx (mode
);
30097 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
30098 gen_rtx_UNSPEC (mode
, gen_rtvec (1, d
),
30101 /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
30104 /* e0 = 1. - d * x0 */
30105 e0
= gen_reg_rtx (mode
);
30106 rs6000_emit_nmsub (e0
, d
, x0
, one
);
30108 /* x1 = x0 + e0 * x0 */
30109 x1
= gen_reg_rtx (mode
);
30110 rs6000_emit_madd (x1
, e0
, x0
, x0
);
30112 for (i
= 0, xprev
= x1
, eprev
= e0
; i
< passes
- 2;
30113 ++i
, xprev
= xnext
, eprev
= enext
) {
30115 /* enext = eprev * eprev */
30116 enext
= gen_reg_rtx (mode
);
30117 emit_insn (gen_mul (enext
, eprev
, eprev
));
30119 /* xnext = xprev + enext * xprev */
30120 xnext
= gen_reg_rtx (mode
);
30121 rs6000_emit_madd (xnext
, enext
, xprev
, xprev
);
30127 /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
30129 /* u = n * xprev */
30130 u
= gen_reg_rtx (mode
);
30131 emit_insn (gen_mul (u
, n
, xprev
));
30133 /* v = n - (d * u) */
30134 v
= gen_reg_rtx (mode
);
30135 rs6000_emit_nmsub (v
, d
, u
, n
);
30137 /* dst = (v * xprev) + u */
30138 rs6000_emit_madd (dst
, v
, xprev
, u
);
30141 add_reg_note (get_last_insn (), REG_EQUAL
, gen_rtx_DIV (mode
, n
, d
));
30144 /* Newton-Raphson approximation of single/double-precision floating point
30145 rsqrt. Assumes no trapping math and finite arguments. */
30148 rs6000_emit_swrsqrt (rtx dst
, rtx src
)
30150 enum machine_mode mode
= GET_MODE (src
);
30151 rtx x0
= gen_reg_rtx (mode
);
30152 rtx y
= gen_reg_rtx (mode
);
30154 /* Low precision estimates guarantee 5 bits of accuracy. High
30155 precision estimates guarantee 14 bits of accuracy. SFmode
30156 requires 23 bits of accuracy. DFmode requires 52 bits of
30157 accuracy. Each pass at least doubles the accuracy, leading
30158 to the following. */
30159 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
30160 if (mode
== DFmode
|| mode
== V2DFmode
)
30163 REAL_VALUE_TYPE dconst3_2
;
30166 enum insn_code code
= optab_handler (smul_optab
, mode
);
30167 insn_gen_fn gen_mul
= GEN_FCN (code
);
30169 gcc_assert (code
!= CODE_FOR_nothing
);
30171 /* Load up the constant 1.5 either as a scalar, or as a vector. */
30172 real_from_integer (&dconst3_2
, VOIDmode
, 3, SIGNED
);
30173 SET_REAL_EXP (&dconst3_2
, REAL_EXP (&dconst3_2
) - 1);
30175 halfthree
= rs6000_load_constant_and_splat (mode
, dconst3_2
);
30177 /* x0 = rsqrt estimate */
30178 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
30179 gen_rtx_UNSPEC (mode
, gen_rtvec (1, src
),
30182 /* y = 0.5 * src = 1.5 * src - src -> fewer constants */
30183 rs6000_emit_msub (y
, src
, halfthree
, src
);
30185 for (i
= 0; i
< passes
; i
++)
30187 rtx x1
= gen_reg_rtx (mode
);
30188 rtx u
= gen_reg_rtx (mode
);
30189 rtx v
= gen_reg_rtx (mode
);
30191 /* x1 = x0 * (1.5 - y * (x0 * x0)) */
30192 emit_insn (gen_mul (u
, x0
, x0
));
30193 rs6000_emit_nmsub (v
, y
, u
, halfthree
);
30194 emit_insn (gen_mul (x1
, x0
, v
));
30198 emit_move_insn (dst
, x0
);
30202 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
30203 (Power7) targets. DST is the target, and SRC is the argument operand. */
30206 rs6000_emit_popcount (rtx dst
, rtx src
)
30208 enum machine_mode mode
= GET_MODE (dst
);
30211 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
30212 if (TARGET_POPCNTD
)
30214 if (mode
== SImode
)
30215 emit_insn (gen_popcntdsi2 (dst
, src
));
30217 emit_insn (gen_popcntddi2 (dst
, src
));
30221 tmp1
= gen_reg_rtx (mode
);
30223 if (mode
== SImode
)
30225 emit_insn (gen_popcntbsi2 (tmp1
, src
));
30226 tmp2
= expand_mult (SImode
, tmp1
, GEN_INT (0x01010101),
30228 tmp2
= force_reg (SImode
, tmp2
);
30229 emit_insn (gen_lshrsi3 (dst
, tmp2
, GEN_INT (24)));
30233 emit_insn (gen_popcntbdi2 (tmp1
, src
));
30234 tmp2
= expand_mult (DImode
, tmp1
,
30235 GEN_INT ((HOST_WIDE_INT
)
30236 0x01010101 << 32 | 0x01010101),
30238 tmp2
= force_reg (DImode
, tmp2
);
30239 emit_insn (gen_lshrdi3 (dst
, tmp2
, GEN_INT (56)));
30244 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
30245 target, and SRC is the argument operand. */
30248 rs6000_emit_parity (rtx dst
, rtx src
)
30250 enum machine_mode mode
= GET_MODE (dst
);
30253 tmp
= gen_reg_rtx (mode
);
30255 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
30258 if (mode
== SImode
)
30260 emit_insn (gen_popcntbsi2 (tmp
, src
));
30261 emit_insn (gen_paritysi2_cmpb (dst
, tmp
));
30265 emit_insn (gen_popcntbdi2 (tmp
, src
));
30266 emit_insn (gen_paritydi2_cmpb (dst
, tmp
));
30271 if (mode
== SImode
)
30273 /* Is mult+shift >= shift+xor+shift+xor? */
30274 if (rs6000_cost
->mulsi_const
>= COSTS_N_INSNS (3))
30276 rtx tmp1
, tmp2
, tmp3
, tmp4
;
30278 tmp1
= gen_reg_rtx (SImode
);
30279 emit_insn (gen_popcntbsi2 (tmp1
, src
));
30281 tmp2
= gen_reg_rtx (SImode
);
30282 emit_insn (gen_lshrsi3 (tmp2
, tmp1
, GEN_INT (16)));
30283 tmp3
= gen_reg_rtx (SImode
);
30284 emit_insn (gen_xorsi3 (tmp3
, tmp1
, tmp2
));
30286 tmp4
= gen_reg_rtx (SImode
);
30287 emit_insn (gen_lshrsi3 (tmp4
, tmp3
, GEN_INT (8)));
30288 emit_insn (gen_xorsi3 (tmp
, tmp3
, tmp4
));
30291 rs6000_emit_popcount (tmp
, src
);
30292 emit_insn (gen_andsi3 (dst
, tmp
, const1_rtx
));
30296 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
30297 if (rs6000_cost
->muldi
>= COSTS_N_INSNS (5))
30299 rtx tmp1
, tmp2
, tmp3
, tmp4
, tmp5
, tmp6
;
30301 tmp1
= gen_reg_rtx (DImode
);
30302 emit_insn (gen_popcntbdi2 (tmp1
, src
));
30304 tmp2
= gen_reg_rtx (DImode
);
30305 emit_insn (gen_lshrdi3 (tmp2
, tmp1
, GEN_INT (32)));
30306 tmp3
= gen_reg_rtx (DImode
);
30307 emit_insn (gen_xordi3 (tmp3
, tmp1
, tmp2
));
30309 tmp4
= gen_reg_rtx (DImode
);
30310 emit_insn (gen_lshrdi3 (tmp4
, tmp3
, GEN_INT (16)));
30311 tmp5
= gen_reg_rtx (DImode
);
30312 emit_insn (gen_xordi3 (tmp5
, tmp3
, tmp4
));
30314 tmp6
= gen_reg_rtx (DImode
);
30315 emit_insn (gen_lshrdi3 (tmp6
, tmp5
, GEN_INT (8)));
30316 emit_insn (gen_xordi3 (tmp
, tmp5
, tmp6
));
30319 rs6000_emit_popcount (tmp
, src
);
30320 emit_insn (gen_anddi3 (dst
, tmp
, const1_rtx
));
30324 /* Expand an Altivec constant permutation for little endian mode.
30325 There are two issues: First, the two input operands must be
30326 swapped so that together they form a double-wide array in LE
30327 order. Second, the vperm instruction has surprising behavior
30328 in LE mode: it interprets the elements of the source vectors
30329 in BE mode ("left to right") and interprets the elements of
30330 the destination vector in LE mode ("right to left"). To
30331 correct for this, we must subtract each element of the permute
30332 control vector from 31.
30334 For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}
30335 with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.
30336 We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to
30337 serve as the permute control vector. Then, in BE mode,
30341 places the desired result in vr9. However, in LE mode the
30342 vector contents will be
30344 vr10 = 00000003 00000002 00000001 00000000
30345 vr11 = 00000007 00000006 00000005 00000004
30347 The result of the vperm using the same permute control vector is
30349 vr9 = 05000000 07000000 01000000 03000000
30351 That is, the leftmost 4 bytes of vr10 are interpreted as the
30352 source for the rightmost 4 bytes of vr9, and so on.
30354 If we change the permute control vector to
30356 vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}
30364 vr9 = 00000006 00000004 00000002 00000000. */
30367 altivec_expand_vec_perm_const_le (rtx operands
[4])
30371 rtx constv
, unspec
;
30372 rtx target
= operands
[0];
30373 rtx op0
= operands
[1];
30374 rtx op1
= operands
[2];
30375 rtx sel
= operands
[3];
30377 /* Unpack and adjust the constant selector. */
30378 for (i
= 0; i
< 16; ++i
)
30380 rtx e
= XVECEXP (sel
, 0, i
);
30381 unsigned int elt
= 31 - (INTVAL (e
) & 31);
30382 perm
[i
] = GEN_INT (elt
);
30385 /* Expand to a permute, swapping the inputs and using the
30386 adjusted selector. */
30388 op0
= force_reg (V16QImode
, op0
);
30390 op1
= force_reg (V16QImode
, op1
);
30392 constv
= gen_rtx_CONST_VECTOR (V16QImode
, gen_rtvec_v (16, perm
));
30393 constv
= force_reg (V16QImode
, constv
);
30394 unspec
= gen_rtx_UNSPEC (V16QImode
, gen_rtvec (3, op1
, op0
, constv
),
30396 if (!REG_P (target
))
30398 rtx tmp
= gen_reg_rtx (V16QImode
);
30399 emit_move_insn (tmp
, unspec
);
30403 emit_move_insn (target
, unspec
);
30406 /* Similarly to altivec_expand_vec_perm_const_le, we must adjust the
30407 permute control vector. But here it's not a constant, so we must
30408 generate a vector NAND or NOR to do the adjustment. */
30411 altivec_expand_vec_perm_le (rtx operands
[4])
30413 rtx notx
, iorx
, unspec
;
30414 rtx target
= operands
[0];
30415 rtx op0
= operands
[1];
30416 rtx op1
= operands
[2];
30417 rtx sel
= operands
[3];
30419 rtx norreg
= gen_reg_rtx (V16QImode
);
30420 enum machine_mode mode
= GET_MODE (target
);
30422 /* Get everything in regs so the pattern matches. */
30424 op0
= force_reg (mode
, op0
);
30426 op1
= force_reg (mode
, op1
);
30428 sel
= force_reg (V16QImode
, sel
);
30429 if (!REG_P (target
))
30430 tmp
= gen_reg_rtx (mode
);
30432 /* Invert the selector with a VNAND if available, else a VNOR.
30433 The VNAND is preferred for future fusion opportunities. */
30434 notx
= gen_rtx_NOT (V16QImode
, sel
);
30435 iorx
= (TARGET_P8_VECTOR
30436 ? gen_rtx_IOR (V16QImode
, notx
, notx
)
30437 : gen_rtx_AND (V16QImode
, notx
, notx
));
30438 emit_insn (gen_rtx_SET (VOIDmode
, norreg
, iorx
));
30440 /* Permute with operands reversed and adjusted selector. */
30441 unspec
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op0
, norreg
),
30444 /* Copy into target, possibly by way of a register. */
30445 if (!REG_P (target
))
30447 emit_move_insn (tmp
, unspec
);
30451 emit_move_insn (target
, unspec
);
30454 /* Expand an Altivec constant permutation. Return true if we match
30455 an efficient implementation; false to fall back to VPERM. */
30458 altivec_expand_vec_perm_const (rtx operands
[4])
30460 struct altivec_perm_insn
{
30461 HOST_WIDE_INT mask
;
30462 enum insn_code impl
;
30463 unsigned char perm
[16];
30465 static const struct altivec_perm_insn patterns
[] = {
30466 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhum_direct
,
30467 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
30468 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwum_direct
,
30469 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
30470 { OPTION_MASK_ALTIVEC
,
30471 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghb_direct
30472 : CODE_FOR_altivec_vmrglb_direct
),
30473 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
30474 { OPTION_MASK_ALTIVEC
,
30475 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghh_direct
30476 : CODE_FOR_altivec_vmrglh_direct
),
30477 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
30478 { OPTION_MASK_ALTIVEC
,
30479 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghw_direct
30480 : CODE_FOR_altivec_vmrglw_direct
),
30481 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
30482 { OPTION_MASK_ALTIVEC
,
30483 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglb_direct
30484 : CODE_FOR_altivec_vmrghb_direct
),
30485 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
30486 { OPTION_MASK_ALTIVEC
,
30487 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglh_direct
30488 : CODE_FOR_altivec_vmrghh_direct
),
30489 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
30490 { OPTION_MASK_ALTIVEC
,
30491 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglw_direct
30492 : CODE_FOR_altivec_vmrghw_direct
),
30493 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
30494 { OPTION_MASK_P8_VECTOR
, CODE_FOR_p8_vmrgew
,
30495 { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
30496 { OPTION_MASK_P8_VECTOR
, CODE_FOR_p8_vmrgow
,
30497 { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
30500 unsigned int i
, j
, elt
, which
;
30501 unsigned char perm
[16];
30502 rtx target
, op0
, op1
, sel
, x
;
30505 target
= operands
[0];
30510 /* Unpack the constant selector. */
30511 for (i
= which
= 0; i
< 16; ++i
)
30513 rtx e
= XVECEXP (sel
, 0, i
);
30514 elt
= INTVAL (e
) & 31;
30515 which
|= (elt
< 16 ? 1 : 2);
30519 /* Simplify the constant selector based on operands. */
30523 gcc_unreachable ();
30527 if (!rtx_equal_p (op0
, op1
))
30532 for (i
= 0; i
< 16; ++i
)
30544 /* Look for splat patterns. */
30549 for (i
= 0; i
< 16; ++i
)
30550 if (perm
[i
] != elt
)
30554 if (!BYTES_BIG_ENDIAN
)
30556 emit_insn (gen_altivec_vspltb_direct (target
, op0
, GEN_INT (elt
)));
30562 for (i
= 0; i
< 16; i
+= 2)
30563 if (perm
[i
] != elt
|| perm
[i
+ 1] != elt
+ 1)
30567 int field
= BYTES_BIG_ENDIAN
? elt
/ 2 : 7 - elt
/ 2;
30568 x
= gen_reg_rtx (V8HImode
);
30569 emit_insn (gen_altivec_vsplth_direct (x
, gen_lowpart (V8HImode
, op0
),
30571 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
30578 for (i
= 0; i
< 16; i
+= 4)
30580 || perm
[i
+ 1] != elt
+ 1
30581 || perm
[i
+ 2] != elt
+ 2
30582 || perm
[i
+ 3] != elt
+ 3)
30586 int field
= BYTES_BIG_ENDIAN
? elt
/ 4 : 3 - elt
/ 4;
30587 x
= gen_reg_rtx (V4SImode
);
30588 emit_insn (gen_altivec_vspltw_direct (x
, gen_lowpart (V4SImode
, op0
),
30590 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
30596 /* Look for merge and pack patterns. */
30597 for (j
= 0; j
< ARRAY_SIZE (patterns
); ++j
)
30601 if ((patterns
[j
].mask
& rs6000_isa_flags
) == 0)
30604 elt
= patterns
[j
].perm
[0];
30605 if (perm
[0] == elt
)
30607 else if (perm
[0] == elt
+ 16)
30611 for (i
= 1; i
< 16; ++i
)
30613 elt
= patterns
[j
].perm
[i
];
30615 elt
= (elt
>= 16 ? elt
- 16 : elt
+ 16);
30616 else if (one_vec
&& elt
>= 16)
30618 if (perm
[i
] != elt
)
30623 enum insn_code icode
= patterns
[j
].impl
;
30624 enum machine_mode omode
= insn_data
[icode
].operand
[0].mode
;
30625 enum machine_mode imode
= insn_data
[icode
].operand
[1].mode
;
30627 /* For little-endian, don't use vpkuwum and vpkuhum if the
30628 underlying vector type is not V4SI and V8HI, respectively.
30629 For example, using vpkuwum with a V8HI picks up the even
30630 halfwords (BE numbering) when the even halfwords (LE
30631 numbering) are what we need. */
30632 if (!BYTES_BIG_ENDIAN
30633 && icode
== CODE_FOR_altivec_vpkuwum_direct
30634 && ((GET_CODE (op0
) == REG
30635 && GET_MODE (op0
) != V4SImode
)
30636 || (GET_CODE (op0
) == SUBREG
30637 && GET_MODE (XEXP (op0
, 0)) != V4SImode
)))
30639 if (!BYTES_BIG_ENDIAN
30640 && icode
== CODE_FOR_altivec_vpkuhum_direct
30641 && ((GET_CODE (op0
) == REG
30642 && GET_MODE (op0
) != V8HImode
)
30643 || (GET_CODE (op0
) == SUBREG
30644 && GET_MODE (XEXP (op0
, 0)) != V8HImode
)))
30647 /* For little-endian, the two input operands must be swapped
30648 (or swapped back) to ensure proper right-to-left numbering
30650 if (swapped
^ !BYTES_BIG_ENDIAN
)
30651 x
= op0
, op0
= op1
, op1
= x
;
30652 if (imode
!= V16QImode
)
30654 op0
= gen_lowpart (imode
, op0
);
30655 op1
= gen_lowpart (imode
, op1
);
30657 if (omode
== V16QImode
)
30660 x
= gen_reg_rtx (omode
);
30661 emit_insn (GEN_FCN (icode
) (x
, op0
, op1
));
30662 if (omode
!= V16QImode
)
30663 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
30668 if (!BYTES_BIG_ENDIAN
)
30670 altivec_expand_vec_perm_const_le (operands
);
30677 /* Expand a Paired Single, VSX Permute Doubleword, or SPE constant permutation.
30678 Return true if we match an efficient implementation. */
30681 rs6000_expand_vec_perm_const_1 (rtx target
, rtx op0
, rtx op1
,
30682 unsigned char perm0
, unsigned char perm1
)
30686 /* If both selectors come from the same operand, fold to single op. */
30687 if ((perm0
& 2) == (perm1
& 2))
30694 /* If both operands are equal, fold to simpler permutation. */
30695 if (rtx_equal_p (op0
, op1
))
30698 perm1
= (perm1
& 1) + 2;
30700 /* If the first selector comes from the second operand, swap. */
30701 else if (perm0
& 2)
30707 x
= op0
, op0
= op1
, op1
= x
;
30709 /* If the second selector does not come from the second operand, fail. */
30710 else if ((perm1
& 2) == 0)
30714 if (target
!= NULL
)
30716 enum machine_mode vmode
, dmode
;
30719 vmode
= GET_MODE (target
);
30720 gcc_assert (GET_MODE_NUNITS (vmode
) == 2);
30721 dmode
= mode_for_vector (GET_MODE_INNER (vmode
), 4);
30722 x
= gen_rtx_VEC_CONCAT (dmode
, op0
, op1
);
30723 v
= gen_rtvec (2, GEN_INT (perm0
), GEN_INT (perm1
));
30724 x
= gen_rtx_VEC_SELECT (vmode
, x
, gen_rtx_PARALLEL (VOIDmode
, v
));
30725 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
30731 rs6000_expand_vec_perm_const (rtx operands
[4])
30733 rtx target
, op0
, op1
, sel
;
30734 unsigned char perm0
, perm1
;
30736 target
= operands
[0];
30741 /* Unpack the constant selector. */
30742 perm0
= INTVAL (XVECEXP (sel
, 0, 0)) & 3;
30743 perm1
= INTVAL (XVECEXP (sel
, 0, 1)) & 3;
30745 return rs6000_expand_vec_perm_const_1 (target
, op0
, op1
, perm0
, perm1
);
30748 /* Test whether a constant permutation is supported. */
30751 rs6000_vectorize_vec_perm_const_ok (enum machine_mode vmode
,
30752 const unsigned char *sel
)
30754 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
30755 if (TARGET_ALTIVEC
)
30758 /* Check for ps_merge* or evmerge* insns. */
30759 if ((TARGET_PAIRED_FLOAT
&& vmode
== V2SFmode
)
30760 || (TARGET_SPE
&& vmode
== V2SImode
))
30762 rtx op0
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 1);
30763 rtx op1
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 2);
30764 return rs6000_expand_vec_perm_const_1 (NULL
, op0
, op1
, sel
[0], sel
[1]);
30770 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave. */
30773 rs6000_do_expand_vec_perm (rtx target
, rtx op0
, rtx op1
,
30774 enum machine_mode vmode
, unsigned nelt
, rtx perm
[])
30776 enum machine_mode imode
;
30780 if (GET_MODE_CLASS (vmode
) != MODE_VECTOR_INT
)
30782 imode
= GET_MODE_INNER (vmode
);
30783 imode
= mode_for_size (GET_MODE_BITSIZE (imode
), MODE_INT
, 0);
30784 imode
= mode_for_vector (imode
, nelt
);
30787 x
= gen_rtx_CONST_VECTOR (imode
, gen_rtvec_v (nelt
, perm
));
30788 x
= expand_vec_perm (vmode
, op0
, op1
, x
, target
);
30790 emit_move_insn (target
, x
);
30793 /* Expand an extract even operation. */
30796 rs6000_expand_extract_even (rtx target
, rtx op0
, rtx op1
)
30798 enum machine_mode vmode
= GET_MODE (target
);
30799 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
30802 for (i
= 0; i
< nelt
; i
++)
30803 perm
[i
] = GEN_INT (i
* 2);
30805 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
30808 /* Expand a vector interleave operation. */
30811 rs6000_expand_interleave (rtx target
, rtx op0
, rtx op1
, bool highp
)
30813 enum machine_mode vmode
= GET_MODE (target
);
30814 unsigned i
, high
, nelt
= GET_MODE_NUNITS (vmode
);
30817 high
= (highp
? 0 : nelt
/ 2);
30818 for (i
= 0; i
< nelt
/ 2; i
++)
30820 perm
[i
* 2] = GEN_INT (i
+ high
);
30821 perm
[i
* 2 + 1] = GEN_INT (i
+ nelt
+ high
);
30824 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
30827 /* Return an RTX representing where to find the function value of a
30828 function returning MODE. */
30830 rs6000_complex_function_value (enum machine_mode mode
)
30832 unsigned int regno
;
30834 enum machine_mode inner
= GET_MODE_INNER (mode
);
30835 unsigned int inner_bytes
= GET_MODE_SIZE (inner
);
30837 if (FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
30838 regno
= FP_ARG_RETURN
;
30841 regno
= GP_ARG_RETURN
;
30843 /* 32-bit is OK since it'll go in r3/r4. */
30844 if (TARGET_32BIT
&& inner_bytes
>= 4)
30845 return gen_rtx_REG (mode
, regno
);
30848 if (inner_bytes
>= 8)
30849 return gen_rtx_REG (mode
, regno
);
30851 r1
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
),
30853 r2
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
+ 1),
30854 GEN_INT (inner_bytes
));
30855 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
30858 /* Target hook for TARGET_FUNCTION_VALUE.
30860 On the SPE, both FPs and vectors are returned in r3.
30862 On RS/6000 an integer value is in r3 and a floating-point value is in
30863 fp1, unless -msoft-float. */
30866 rs6000_function_value (const_tree valtype
,
30867 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
30868 bool outgoing ATTRIBUTE_UNUSED
)
30870 enum machine_mode mode
;
30871 unsigned int regno
;
30872 enum machine_mode elt_mode
;
30875 /* Special handling for structs in darwin64. */
30877 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype
), valtype
))
30879 CUMULATIVE_ARGS valcum
;
30883 valcum
.fregno
= FP_ARG_MIN_REG
;
30884 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
30885 /* Do a trial code generation as if this were going to be passed as
30886 an argument; if any part goes in memory, we return NULL. */
30887 valret
= rs6000_darwin64_record_arg (&valcum
, valtype
, true, /* retval= */ true);
30890 /* Otherwise fall through to standard ABI rules. */
30893 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */
30894 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (valtype
), valtype
,
30895 &elt_mode
, &n_elts
))
30897 int first_reg
, n_regs
, i
;
30900 if (SCALAR_FLOAT_MODE_P (elt_mode
))
30902 /* _Decimal128 must use even/odd register pairs. */
30903 first_reg
= (elt_mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
30904 n_regs
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
30908 first_reg
= ALTIVEC_ARG_RETURN
;
30912 par
= gen_rtx_PARALLEL (TYPE_MODE (valtype
), rtvec_alloc (n_elts
));
30913 for (i
= 0; i
< n_elts
; i
++)
30915 rtx r
= gen_rtx_REG (elt_mode
, first_reg
+ i
* n_regs
);
30916 rtx off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
30917 XVECEXP (par
, 0, i
) = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
30923 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DImode
)
30925 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
30926 return gen_rtx_PARALLEL (DImode
,
30928 gen_rtx_EXPR_LIST (VOIDmode
,
30929 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
30931 gen_rtx_EXPR_LIST (VOIDmode
,
30932 gen_rtx_REG (SImode
,
30933 GP_ARG_RETURN
+ 1),
30936 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DCmode
)
30938 return gen_rtx_PARALLEL (DCmode
,
30940 gen_rtx_EXPR_LIST (VOIDmode
,
30941 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
30943 gen_rtx_EXPR_LIST (VOIDmode
,
30944 gen_rtx_REG (SImode
,
30945 GP_ARG_RETURN
+ 1),
30947 gen_rtx_EXPR_LIST (VOIDmode
,
30948 gen_rtx_REG (SImode
,
30949 GP_ARG_RETURN
+ 2),
30951 gen_rtx_EXPR_LIST (VOIDmode
,
30952 gen_rtx_REG (SImode
,
30953 GP_ARG_RETURN
+ 3),
30957 mode
= TYPE_MODE (valtype
);
30958 if ((INTEGRAL_TYPE_P (valtype
) && GET_MODE_BITSIZE (mode
) < BITS_PER_WORD
)
30959 || POINTER_TYPE_P (valtype
))
30960 mode
= TARGET_32BIT
? SImode
: DImode
;
30962 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
30963 /* _Decimal128 must use an even/odd register pair. */
30964 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
30965 else if (SCALAR_FLOAT_TYPE_P (valtype
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
30966 && ((TARGET_SINGLE_FLOAT
&& (mode
== SFmode
)) || TARGET_DOUBLE_FLOAT
))
30967 regno
= FP_ARG_RETURN
;
30968 else if (TREE_CODE (valtype
) == COMPLEX_TYPE
30969 && targetm
.calls
.split_complex_arg
)
30970 return rs6000_complex_function_value (mode
);
30971 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
30972 return register is used in both cases, and we won't see V2DImode/V2DFmode
30973 for pure altivec, combine the two cases. */
30974 else if (TREE_CODE (valtype
) == VECTOR_TYPE
30975 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
30976 && ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
30977 regno
= ALTIVEC_ARG_RETURN
;
30978 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
30979 && (mode
== DFmode
|| mode
== DCmode
30980 || mode
== TFmode
|| mode
== TCmode
))
30981 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
30983 regno
= GP_ARG_RETURN
;
30985 return gen_rtx_REG (mode
, regno
);
30988 /* Define how to find the value returned by a library function
30989 assuming the value has mode MODE. */
30991 rs6000_libcall_value (enum machine_mode mode
)
30993 unsigned int regno
;
30995 if (TARGET_32BIT
&& TARGET_POWERPC64
&& mode
== DImode
)
30997 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
30998 return gen_rtx_PARALLEL (DImode
,
31000 gen_rtx_EXPR_LIST (VOIDmode
,
31001 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
31003 gen_rtx_EXPR_LIST (VOIDmode
,
31004 gen_rtx_REG (SImode
,
31005 GP_ARG_RETURN
+ 1),
31009 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
31010 /* _Decimal128 must use an even/odd register pair. */
31011 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
31012 else if (SCALAR_FLOAT_MODE_P (mode
)
31013 && TARGET_HARD_FLOAT
&& TARGET_FPRS
31014 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
) || TARGET_DOUBLE_FLOAT
))
31015 regno
= FP_ARG_RETURN
;
31016 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
31017 return register is used in both cases, and we won't see V2DImode/V2DFmode
31018 for pure altivec, combine the two cases. */
31019 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
31020 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
)
31021 regno
= ALTIVEC_ARG_RETURN
;
31022 else if (COMPLEX_MODE_P (mode
) && targetm
.calls
.split_complex_arg
)
31023 return rs6000_complex_function_value (mode
);
31024 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
31025 && (mode
== DFmode
|| mode
== DCmode
31026 || mode
== TFmode
|| mode
== TCmode
))
31027 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
31029 regno
= GP_ARG_RETURN
;
31031 return gen_rtx_REG (mode
, regno
);
31035 /* Return true if we use LRA instead of reload pass. */
31037 rs6000_lra_p (void)
31039 return rs6000_lra_flag
;
31042 /* Given FROM and TO register numbers, say whether this elimination is allowed.
31043 Frame pointer elimination is automatically handled.
31045 For the RS/6000, if frame pointer elimination is being done, we would like
31046 to convert ap into fp, not sp.
31048 We need r30 if -mminimal-toc was specified, and there are constant pool
31052 rs6000_can_eliminate (const int from
, const int to
)
31054 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
31055 ? ! frame_pointer_needed
31056 : from
== RS6000_PIC_OFFSET_TABLE_REGNUM
31057 ? ! TARGET_MINIMAL_TOC
|| TARGET_NO_TOC
|| get_pool_size () == 0
31061 /* Define the offset between two registers, FROM to be eliminated and its
31062 replacement TO, at the start of a routine. */
31064 rs6000_initial_elimination_offset (int from
, int to
)
31066 rs6000_stack_t
*info
= rs6000_stack_info ();
31067 HOST_WIDE_INT offset
;
31069 if (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
31070 offset
= info
->push_p
? 0 : -info
->total_size
;
31071 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
31073 offset
= info
->push_p
? 0 : -info
->total_size
;
31074 if (FRAME_GROWS_DOWNWARD
)
31075 offset
+= info
->fixed_size
+ info
->vars_size
+ info
->parm_size
;
31077 else if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
31078 offset
= FRAME_GROWS_DOWNWARD
31079 ? info
->fixed_size
+ info
->vars_size
+ info
->parm_size
31081 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
31082 offset
= info
->total_size
;
31083 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
31084 offset
= info
->push_p
? info
->total_size
: 0;
31085 else if (from
== RS6000_PIC_OFFSET_TABLE_REGNUM
)
31088 gcc_unreachable ();
31094 rs6000_dwarf_register_span (rtx reg
)
31098 unsigned regno
= REGNO (reg
);
31099 enum machine_mode mode
= GET_MODE (reg
);
31103 && (SPE_VECTOR_MODE (GET_MODE (reg
))
31104 || (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
)
31105 && mode
!= SFmode
&& mode
!= SDmode
&& mode
!= SCmode
)))
31110 regno
= REGNO (reg
);
31112 /* The duality of the SPE register size wreaks all kinds of havoc.
31113 This is a way of distinguishing r0 in 32-bits from r0 in
31115 words
= (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
31116 gcc_assert (words
<= 4);
31117 for (i
= 0; i
< words
; i
++, regno
++)
31119 if (BYTES_BIG_ENDIAN
)
31121 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
+ 1200);
31122 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
);
31126 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
);
31127 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
+ 1200);
31131 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (words
* 2, parts
));
31134 /* Fill in sizes for SPE register high parts in table used by unwinder. */
31137 rs6000_init_dwarf_reg_sizes_extra (tree address
)
31142 enum machine_mode mode
= TYPE_MODE (char_type_node
);
31143 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
31144 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
31145 rtx value
= gen_int_mode (4, mode
);
31147 for (i
= 1201; i
< 1232; i
++)
31149 int column
= DWARF_REG_TO_UNWIND_COLUMN (i
);
31150 HOST_WIDE_INT offset
31151 = DWARF_FRAME_REGNUM (column
) * GET_MODE_SIZE (mode
);
31153 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
31157 if (TARGET_MACHO
&& ! TARGET_ALTIVEC
)
31160 enum machine_mode mode
= TYPE_MODE (char_type_node
);
31161 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
31162 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
31163 rtx value
= gen_int_mode (16, mode
);
31165 /* On Darwin, libgcc may be built to run on both G3 and G4/5.
31166 The unwinder still needs to know the size of Altivec registers. */
31168 for (i
= FIRST_ALTIVEC_REGNO
; i
< LAST_ALTIVEC_REGNO
+1; i
++)
31170 int column
= DWARF_REG_TO_UNWIND_COLUMN (i
);
31171 HOST_WIDE_INT offset
31172 = DWARF_FRAME_REGNUM (column
) * GET_MODE_SIZE (mode
);
31174 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
31179 /* Map internal gcc register numbers to DWARF2 register numbers. */
31182 rs6000_dbx_register_number (unsigned int regno
)
31184 if (regno
<= 63 || write_symbols
!= DWARF2_DEBUG
)
31186 if (regno
== LR_REGNO
)
31188 if (regno
== CTR_REGNO
)
31190 if (CR_REGNO_P (regno
))
31191 return regno
- CR0_REGNO
+ 86;
31192 if (regno
== CA_REGNO
)
31193 return 101; /* XER */
31194 if (ALTIVEC_REGNO_P (regno
))
31195 return regno
- FIRST_ALTIVEC_REGNO
+ 1124;
31196 if (regno
== VRSAVE_REGNO
)
31198 if (regno
== VSCR_REGNO
)
31200 if (regno
== SPE_ACC_REGNO
)
31202 if (regno
== SPEFSCR_REGNO
)
31204 /* SPE high reg number. We get these values of regno from
31205 rs6000_dwarf_register_span. */
31206 gcc_assert (regno
>= 1200 && regno
< 1232);
31210 /* target hook eh_return_filter_mode */
31211 static enum machine_mode
31212 rs6000_eh_return_filter_mode (void)
31214 return TARGET_32BIT
? SImode
: word_mode
;
31217 /* Target hook for scalar_mode_supported_p. */
31219 rs6000_scalar_mode_supported_p (enum machine_mode mode
)
31221 if (DECIMAL_FLOAT_MODE_P (mode
))
31222 return default_decimal_float_supported_p ();
31224 return default_scalar_mode_supported_p (mode
);
31227 /* Target hook for vector_mode_supported_p. */
31229 rs6000_vector_mode_supported_p (enum machine_mode mode
)
31232 if (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (mode
))
31235 if (TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
31238 else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
31245 /* Target hook for invalid_arg_for_unprototyped_fn. */
31246 static const char *
31247 invalid_arg_for_unprototyped_fn (const_tree typelist
, const_tree funcdecl
, const_tree val
)
31249 return (!rs6000_darwin64_abi
31251 && TREE_CODE (TREE_TYPE (val
)) == VECTOR_TYPE
31252 && (funcdecl
== NULL_TREE
31253 || (TREE_CODE (funcdecl
) == FUNCTION_DECL
31254 && DECL_BUILT_IN_CLASS (funcdecl
) != BUILT_IN_MD
)))
31255 ? N_("AltiVec argument passed to unprototyped function")
31259 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
31260 setup by using __stack_chk_fail_local hidden function instead of
31261 calling __stack_chk_fail directly. Otherwise it is better to call
31262 __stack_chk_fail directly. */
31264 static tree ATTRIBUTE_UNUSED
31265 rs6000_stack_protect_fail (void)
31267 return (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
31268 ? default_hidden_stack_protect_fail ()
31269 : default_external_stack_protect_fail ();
31273 rs6000_final_prescan_insn (rtx insn
, rtx
*operand ATTRIBUTE_UNUSED
,
31274 int num_operands ATTRIBUTE_UNUSED
)
31276 if (rs6000_warn_cell_microcode
)
31279 int insn_code_number
= recog_memoized (insn
);
31280 location_t location
= INSN_LOCATION (insn
);
31282 /* Punt on insns we cannot recognize. */
31283 if (insn_code_number
< 0)
31286 temp
= get_insn_template (insn_code_number
, insn
);
31288 if (get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
)
31289 warning_at (location
, OPT_mwarn_cell_microcode
,
31290 "emitting microcode insn %s\t[%s] #%d",
31291 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
31292 else if (get_attr_cell_micro (insn
) == CELL_MICRO_CONDITIONAL
)
31293 warning_at (location
, OPT_mwarn_cell_microcode
,
31294 "emitting conditional microcode insn %s\t[%s] #%d",
31295 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
31299 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
31302 static unsigned HOST_WIDE_INT
31303 rs6000_asan_shadow_offset (void)
31305 return (unsigned HOST_WIDE_INT
) 1 << (TARGET_64BIT
? 41 : 29);
31309 /* Mask options that we want to support inside of attribute((target)) and
31310 #pragma GCC target operations. Note, we do not include things like
31311 64/32-bit, endianess, hard/soft floating point, etc. that would have
31312 different calling sequences. */
31314 struct rs6000_opt_mask
{
31315 const char *name
; /* option name */
31316 HOST_WIDE_INT mask
; /* mask to set */
31317 bool invert
; /* invert sense of mask */
31318 bool valid_target
; /* option is a target option */
31321 static struct rs6000_opt_mask
const rs6000_opt_masks
[] =
31323 { "altivec", OPTION_MASK_ALTIVEC
, false, true },
31324 { "cmpb", OPTION_MASK_CMPB
, false, true },
31325 { "crypto", OPTION_MASK_CRYPTO
, false, true },
31326 { "direct-move", OPTION_MASK_DIRECT_MOVE
, false, true },
31327 { "dlmzb", OPTION_MASK_DLMZB
, false, true },
31328 { "fprnd", OPTION_MASK_FPRND
, false, true },
31329 { "hard-dfp", OPTION_MASK_DFP
, false, true },
31330 { "htm", OPTION_MASK_HTM
, false, true },
31331 { "isel", OPTION_MASK_ISEL
, false, true },
31332 { "mfcrf", OPTION_MASK_MFCRF
, false, true },
31333 { "mfpgpr", OPTION_MASK_MFPGPR
, false, true },
31334 { "mulhw", OPTION_MASK_MULHW
, false, true },
31335 { "multiple", OPTION_MASK_MULTIPLE
, false, true },
31336 { "popcntb", OPTION_MASK_POPCNTB
, false, true },
31337 { "popcntd", OPTION_MASK_POPCNTD
, false, true },
31338 { "power8-fusion", OPTION_MASK_P8_FUSION
, false, true },
31339 { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN
, false, true },
31340 { "power8-vector", OPTION_MASK_P8_VECTOR
, false, true },
31341 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT
, false, true },
31342 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT
, false, true },
31343 { "quad-memory", OPTION_MASK_QUAD_MEMORY
, false, true },
31344 { "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC
, false, true },
31345 { "recip-precision", OPTION_MASK_RECIP_PRECISION
, false, true },
31346 { "string", OPTION_MASK_STRING
, false, true },
31347 { "update", OPTION_MASK_NO_UPDATE
, true , true },
31348 { "upper-regs-df", OPTION_MASK_UPPER_REGS_DF
, false, false },
31349 { "upper-regs-sf", OPTION_MASK_UPPER_REGS_SF
, false, false },
31350 { "vsx", OPTION_MASK_VSX
, false, true },
31351 { "vsx-timode", OPTION_MASK_VSX_TIMODE
, false, true },
31352 #ifdef OPTION_MASK_64BIT
31354 { "aix64", OPTION_MASK_64BIT
, false, false },
31355 { "aix32", OPTION_MASK_64BIT
, true, false },
31357 { "64", OPTION_MASK_64BIT
, false, false },
31358 { "32", OPTION_MASK_64BIT
, true, false },
31361 #ifdef OPTION_MASK_EABI
31362 { "eabi", OPTION_MASK_EABI
, false, false },
31364 #ifdef OPTION_MASK_LITTLE_ENDIAN
31365 { "little", OPTION_MASK_LITTLE_ENDIAN
, false, false },
31366 { "big", OPTION_MASK_LITTLE_ENDIAN
, true, false },
31368 #ifdef OPTION_MASK_RELOCATABLE
31369 { "relocatable", OPTION_MASK_RELOCATABLE
, false, false },
31371 #ifdef OPTION_MASK_STRICT_ALIGN
31372 { "strict-align", OPTION_MASK_STRICT_ALIGN
, false, false },
31374 { "soft-float", OPTION_MASK_SOFT_FLOAT
, false, false },
31375 { "string", OPTION_MASK_STRING
, false, false },
31378 /* Builtin mask mapping for printing the flags. */
31379 static struct rs6000_opt_mask
const rs6000_builtin_mask_names
[] =
31381 { "altivec", RS6000_BTM_ALTIVEC
, false, false },
31382 { "vsx", RS6000_BTM_VSX
, false, false },
31383 { "spe", RS6000_BTM_SPE
, false, false },
31384 { "paired", RS6000_BTM_PAIRED
, false, false },
31385 { "fre", RS6000_BTM_FRE
, false, false },
31386 { "fres", RS6000_BTM_FRES
, false, false },
31387 { "frsqrte", RS6000_BTM_FRSQRTE
, false, false },
31388 { "frsqrtes", RS6000_BTM_FRSQRTES
, false, false },
31389 { "popcntd", RS6000_BTM_POPCNTD
, false, false },
31390 { "cell", RS6000_BTM_CELL
, false, false },
31391 { "power8-vector", RS6000_BTM_P8_VECTOR
, false, false },
31392 { "crypto", RS6000_BTM_CRYPTO
, false, false },
31393 { "htm", RS6000_BTM_HTM
, false, false },
31394 { "hard-dfp", RS6000_BTM_DFP
, false, false },
31395 { "hard-float", RS6000_BTM_HARD_FLOAT
, false, false },
31398 /* Option variables that we want to support inside attribute((target)) and
31399 #pragma GCC target operations. */
31401 struct rs6000_opt_var
{
31402 const char *name
; /* option name */
31403 size_t global_offset
; /* offset of the option in global_options. */
31404 size_t target_offset
; /* offset of the option in target optiosn. */
31407 static struct rs6000_opt_var
const rs6000_opt_vars
[] =
31410 offsetof (struct gcc_options
, x_TARGET_FRIZ
),
31411 offsetof (struct cl_target_option
, x_TARGET_FRIZ
), },
31412 { "avoid-indexed-addresses",
31413 offsetof (struct gcc_options
, x_TARGET_AVOID_XFORM
),
31414 offsetof (struct cl_target_option
, x_TARGET_AVOID_XFORM
) },
31416 offsetof (struct gcc_options
, x_rs6000_paired_float
),
31417 offsetof (struct cl_target_option
, x_rs6000_paired_float
), },
31419 offsetof (struct gcc_options
, x_rs6000_default_long_calls
),
31420 offsetof (struct cl_target_option
, x_rs6000_default_long_calls
), },
31423 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
31424 parsing. Return true if there were no errors. */
31427 rs6000_inner_target_options (tree args
, bool attr_p
)
31431 if (args
== NULL_TREE
)
31434 else if (TREE_CODE (args
) == STRING_CST
)
31436 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
31439 while ((q
= strtok (p
, ",")) != NULL
)
31441 bool error_p
= false;
31442 bool not_valid_p
= false;
31443 const char *cpu_opt
= NULL
;
31446 if (strncmp (q
, "cpu=", 4) == 0)
31448 int cpu_index
= rs6000_cpu_name_lookup (q
+4);
31449 if (cpu_index
>= 0)
31450 rs6000_cpu_index
= cpu_index
;
31457 else if (strncmp (q
, "tune=", 5) == 0)
31459 int tune_index
= rs6000_cpu_name_lookup (q
+5);
31460 if (tune_index
>= 0)
31461 rs6000_tune_index
= tune_index
;
31471 bool invert
= false;
31475 if (strncmp (r
, "no-", 3) == 0)
31481 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_masks
); i
++)
31482 if (strcmp (r
, rs6000_opt_masks
[i
].name
) == 0)
31484 HOST_WIDE_INT mask
= rs6000_opt_masks
[i
].mask
;
31486 if (!rs6000_opt_masks
[i
].valid_target
)
31487 not_valid_p
= true;
31491 rs6000_isa_flags_explicit
|= mask
;
31493 /* VSX needs altivec, so -mvsx automagically sets
31495 if (mask
== OPTION_MASK_VSX
&& !invert
)
31496 mask
|= OPTION_MASK_ALTIVEC
;
31498 if (rs6000_opt_masks
[i
].invert
)
31502 rs6000_isa_flags
&= ~mask
;
31504 rs6000_isa_flags
|= mask
;
31509 if (error_p
&& !not_valid_p
)
31511 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_vars
); i
++)
31512 if (strcmp (r
, rs6000_opt_vars
[i
].name
) == 0)
31514 size_t j
= rs6000_opt_vars
[i
].global_offset
;
31515 *((int *) ((char *)&global_options
+ j
)) = !invert
;
31524 const char *eprefix
, *esuffix
;
31529 eprefix
= "__attribute__((__target__(";
31534 eprefix
= "#pragma GCC target ";
31539 error ("invalid cpu \"%s\" for %s\"%s\"%s", cpu_opt
, eprefix
,
31541 else if (not_valid_p
)
31542 error ("%s\"%s\"%s is not allowed", eprefix
, q
, esuffix
);
31544 error ("%s\"%s\"%s is invalid", eprefix
, q
, esuffix
);
31549 else if (TREE_CODE (args
) == TREE_LIST
)
31553 tree value
= TREE_VALUE (args
);
31556 bool ret2
= rs6000_inner_target_options (value
, attr_p
);
31560 args
= TREE_CHAIN (args
);
31562 while (args
!= NULL_TREE
);
31566 gcc_unreachable ();
31571 /* Print out the target options as a list for -mdebug=target. */
31574 rs6000_debug_target_options (tree args
, const char *prefix
)
31576 if (args
== NULL_TREE
)
31577 fprintf (stderr
, "%s<NULL>", prefix
);
31579 else if (TREE_CODE (args
) == STRING_CST
)
31581 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
31584 while ((q
= strtok (p
, ",")) != NULL
)
31587 fprintf (stderr
, "%s\"%s\"", prefix
, q
);
31592 else if (TREE_CODE (args
) == TREE_LIST
)
31596 tree value
= TREE_VALUE (args
);
31599 rs6000_debug_target_options (value
, prefix
);
31602 args
= TREE_CHAIN (args
);
31604 while (args
!= NULL_TREE
);
31608 gcc_unreachable ();
31614 /* Hook to validate attribute((target("..."))). */
31617 rs6000_valid_attribute_p (tree fndecl
,
31618 tree
ARG_UNUSED (name
),
31622 struct cl_target_option cur_target
;
31624 tree old_optimize
= build_optimization_node (&global_options
);
31625 tree new_target
, new_optimize
;
31626 tree func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
31628 gcc_assert ((fndecl
!= NULL_TREE
) && (args
!= NULL_TREE
));
31630 if (TARGET_DEBUG_TARGET
)
31632 tree tname
= DECL_NAME (fndecl
);
31633 fprintf (stderr
, "\n==================== rs6000_valid_attribute_p:\n");
31635 fprintf (stderr
, "function: %.*s\n",
31636 (int) IDENTIFIER_LENGTH (tname
),
31637 IDENTIFIER_POINTER (tname
));
31639 fprintf (stderr
, "function: unknown\n");
31641 fprintf (stderr
, "args:");
31642 rs6000_debug_target_options (args
, " ");
31643 fprintf (stderr
, "\n");
31646 fprintf (stderr
, "flags: 0x%x\n", flags
);
31648 fprintf (stderr
, "--------------------\n");
31651 old_optimize
= build_optimization_node (&global_options
);
31652 func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
31654 /* If the function changed the optimization levels as well as setting target
31655 options, start with the optimizations specified. */
31656 if (func_optimize
&& func_optimize
!= old_optimize
)
31657 cl_optimization_restore (&global_options
,
31658 TREE_OPTIMIZATION (func_optimize
));
31660 /* The target attributes may also change some optimization flags, so update
31661 the optimization options if necessary. */
31662 cl_target_option_save (&cur_target
, &global_options
);
31663 rs6000_cpu_index
= rs6000_tune_index
= -1;
31664 ret
= rs6000_inner_target_options (args
, true);
31666 /* Set up any additional state. */
31669 ret
= rs6000_option_override_internal (false);
31670 new_target
= build_target_option_node (&global_options
);
31675 new_optimize
= build_optimization_node (&global_options
);
31682 DECL_FUNCTION_SPECIFIC_TARGET (fndecl
) = new_target
;
31684 if (old_optimize
!= new_optimize
)
31685 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
) = new_optimize
;
31688 cl_target_option_restore (&global_options
, &cur_target
);
31690 if (old_optimize
!= new_optimize
)
31691 cl_optimization_restore (&global_options
,
31692 TREE_OPTIMIZATION (old_optimize
));
31698 /* Hook to validate the current #pragma GCC target and set the state, and
31699 update the macros based on what was changed. If ARGS is NULL, then
31700 POP_TARGET is used to reset the options. */
31703 rs6000_pragma_target_parse (tree args
, tree pop_target
)
31705 tree prev_tree
= build_target_option_node (&global_options
);
31707 struct cl_target_option
*prev_opt
, *cur_opt
;
31708 HOST_WIDE_INT prev_flags
, cur_flags
, diff_flags
;
31709 HOST_WIDE_INT prev_bumask
, cur_bumask
, diff_bumask
;
31711 if (TARGET_DEBUG_TARGET
)
31713 fprintf (stderr
, "\n==================== rs6000_pragma_target_parse\n");
31714 fprintf (stderr
, "args:");
31715 rs6000_debug_target_options (args
, " ");
31716 fprintf (stderr
, "\n");
31720 fprintf (stderr
, "pop_target:\n");
31721 debug_tree (pop_target
);
31724 fprintf (stderr
, "pop_target: <NULL>\n");
31726 fprintf (stderr
, "--------------------\n");
31731 cur_tree
= ((pop_target
)
31733 : target_option_default_node
);
31734 cl_target_option_restore (&global_options
,
31735 TREE_TARGET_OPTION (cur_tree
));
31739 rs6000_cpu_index
= rs6000_tune_index
= -1;
31740 if (!rs6000_inner_target_options (args
, false)
31741 || !rs6000_option_override_internal (false)
31742 || (cur_tree
= build_target_option_node (&global_options
))
31745 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
31746 fprintf (stderr
, "invalid pragma\n");
31752 target_option_current_node
= cur_tree
;
31754 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
31755 change the macros that are defined. */
31756 if (rs6000_target_modify_macros_ptr
)
31758 prev_opt
= TREE_TARGET_OPTION (prev_tree
);
31759 prev_bumask
= prev_opt
->x_rs6000_builtin_mask
;
31760 prev_flags
= prev_opt
->x_rs6000_isa_flags
;
31762 cur_opt
= TREE_TARGET_OPTION (cur_tree
);
31763 cur_flags
= cur_opt
->x_rs6000_isa_flags
;
31764 cur_bumask
= cur_opt
->x_rs6000_builtin_mask
;
31766 diff_bumask
= (prev_bumask
^ cur_bumask
);
31767 diff_flags
= (prev_flags
^ cur_flags
);
31769 if ((diff_flags
!= 0) || (diff_bumask
!= 0))
31771 /* Delete old macros. */
31772 rs6000_target_modify_macros_ptr (false,
31773 prev_flags
& diff_flags
,
31774 prev_bumask
& diff_bumask
);
31776 /* Define new macros. */
31777 rs6000_target_modify_macros_ptr (true,
31778 cur_flags
& diff_flags
,
31779 cur_bumask
& diff_bumask
);
31787 /* Remember the last target of rs6000_set_current_function. */
31788 static GTY(()) tree rs6000_previous_fndecl
;
31790 /* Establish appropriate back-end context for processing the function
31791 FNDECL. The argument might be NULL to indicate processing at top
31792 level, outside of any function scope. */
31794 rs6000_set_current_function (tree fndecl
)
31796 tree old_tree
= (rs6000_previous_fndecl
31797 ? DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl
)
31800 tree new_tree
= (fndecl
31801 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl
)
31804 if (TARGET_DEBUG_TARGET
)
31806 bool print_final
= false;
31807 fprintf (stderr
, "\n==================== rs6000_set_current_function");
31810 fprintf (stderr
, ", fndecl %s (%p)",
31811 (DECL_NAME (fndecl
)
31812 ? IDENTIFIER_POINTER (DECL_NAME (fndecl
))
31813 : "<unknown>"), (void *)fndecl
);
31815 if (rs6000_previous_fndecl
)
31816 fprintf (stderr
, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl
);
31818 fprintf (stderr
, "\n");
31821 fprintf (stderr
, "\nnew fndecl target specific options:\n");
31822 debug_tree (new_tree
);
31823 print_final
= true;
31828 fprintf (stderr
, "\nold fndecl target specific options:\n");
31829 debug_tree (old_tree
);
31830 print_final
= true;
31834 fprintf (stderr
, "--------------------\n");
31837 /* Only change the context if the function changes. This hook is called
31838 several times in the course of compiling a function, and we don't want to
31839 slow things down too much or call target_reinit when it isn't safe. */
31840 if (fndecl
&& fndecl
!= rs6000_previous_fndecl
)
31842 rs6000_previous_fndecl
= fndecl
;
31843 if (old_tree
== new_tree
)
31848 cl_target_option_restore (&global_options
,
31849 TREE_TARGET_OPTION (new_tree
));
31850 if (TREE_TARGET_GLOBALS (new_tree
))
31851 restore_target_globals (TREE_TARGET_GLOBALS (new_tree
));
31853 TREE_TARGET_GLOBALS (new_tree
)
31854 = save_target_globals_default_opts ();
31859 new_tree
= target_option_current_node
;
31860 cl_target_option_restore (&global_options
,
31861 TREE_TARGET_OPTION (new_tree
));
31862 if (TREE_TARGET_GLOBALS (new_tree
))
31863 restore_target_globals (TREE_TARGET_GLOBALS (new_tree
));
31864 else if (new_tree
== target_option_default_node
)
31865 restore_target_globals (&default_target_globals
);
31867 TREE_TARGET_GLOBALS (new_tree
)
31868 = save_target_globals_default_opts ();
31874 /* Save the current options */
31877 rs6000_function_specific_save (struct cl_target_option
*ptr
,
31878 struct gcc_options
*opts
)
31880 ptr
->x_rs6000_isa_flags
= opts
->x_rs6000_isa_flags
;
31881 ptr
->x_rs6000_isa_flags_explicit
= opts
->x_rs6000_isa_flags_explicit
;
31884 /* Restore the current options */
31887 rs6000_function_specific_restore (struct gcc_options
*opts
,
31888 struct cl_target_option
*ptr
)
31891 opts
->x_rs6000_isa_flags
= ptr
->x_rs6000_isa_flags
;
31892 opts
->x_rs6000_isa_flags_explicit
= ptr
->x_rs6000_isa_flags_explicit
;
31893 (void) rs6000_option_override_internal (false);
31896 /* Print the current options */
31899 rs6000_function_specific_print (FILE *file
, int indent
,
31900 struct cl_target_option
*ptr
)
31902 rs6000_print_isa_options (file
, indent
, "Isa options set",
31903 ptr
->x_rs6000_isa_flags
);
31905 rs6000_print_isa_options (file
, indent
, "Isa options explicit",
31906 ptr
->x_rs6000_isa_flags_explicit
);
31909 /* Helper function to print the current isa or misc options on a line. */
31912 rs6000_print_options_internal (FILE *file
,
31914 const char *string
,
31915 HOST_WIDE_INT flags
,
31916 const char *prefix
,
31917 const struct rs6000_opt_mask
*opts
,
31918 size_t num_elements
)
31921 size_t start_column
= 0;
31923 size_t max_column
= 76;
31924 const char *comma
= "";
31927 start_column
+= fprintf (file
, "%*s", indent
, "");
31931 fprintf (stderr
, DEBUG_FMT_S
, string
, "<none>");
31935 start_column
+= fprintf (stderr
, DEBUG_FMT_WX
, string
, flags
);
31937 /* Print the various mask options. */
31938 cur_column
= start_column
;
31939 for (i
= 0; i
< num_elements
; i
++)
31941 if ((flags
& opts
[i
].mask
) != 0)
31943 const char *no_str
= rs6000_opt_masks
[i
].invert
? "no-" : "";
31944 size_t len
= (strlen (comma
)
31947 + strlen (rs6000_opt_masks
[i
].name
));
31950 if (cur_column
> max_column
)
31952 fprintf (stderr
, ", \\\n%*s", (int)start_column
, "");
31953 cur_column
= start_column
+ len
;
31957 fprintf (file
, "%s%s%s%s", comma
, prefix
, no_str
,
31958 rs6000_opt_masks
[i
].name
);
31959 flags
&= ~ opts
[i
].mask
;
31964 fputs ("\n", file
);
31967 /* Helper function to print the current isa options on a line. */
31970 rs6000_print_isa_options (FILE *file
, int indent
, const char *string
,
31971 HOST_WIDE_INT flags
)
31973 rs6000_print_options_internal (file
, indent
, string
, flags
, "-m",
31974 &rs6000_opt_masks
[0],
31975 ARRAY_SIZE (rs6000_opt_masks
));
31979 rs6000_print_builtin_options (FILE *file
, int indent
, const char *string
,
31980 HOST_WIDE_INT flags
)
31982 rs6000_print_options_internal (file
, indent
, string
, flags
, "",
31983 &rs6000_builtin_mask_names
[0],
31984 ARRAY_SIZE (rs6000_builtin_mask_names
));
31988 /* Hook to determine if one function can safely inline another. */
31991 rs6000_can_inline_p (tree caller
, tree callee
)
31994 tree caller_tree
= DECL_FUNCTION_SPECIFIC_TARGET (caller
);
31995 tree callee_tree
= DECL_FUNCTION_SPECIFIC_TARGET (callee
);
31997 /* If callee has no option attributes, then it is ok to inline. */
32001 /* If caller has no option attributes, but callee does then it is not ok to
32003 else if (!caller_tree
)
32008 struct cl_target_option
*caller_opts
= TREE_TARGET_OPTION (caller_tree
);
32009 struct cl_target_option
*callee_opts
= TREE_TARGET_OPTION (callee_tree
);
32011 /* Callee's options should a subset of the caller's, i.e. a vsx function
32012 can inline an altivec function but a non-vsx function can't inline a
32014 if ((caller_opts
->x_rs6000_isa_flags
& callee_opts
->x_rs6000_isa_flags
)
32015 == callee_opts
->x_rs6000_isa_flags
)
32019 if (TARGET_DEBUG_TARGET
)
32020 fprintf (stderr
, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
32021 (DECL_NAME (caller
)
32022 ? IDENTIFIER_POINTER (DECL_NAME (caller
))
32024 (DECL_NAME (callee
)
32025 ? IDENTIFIER_POINTER (DECL_NAME (callee
))
32027 (ret
? "can" : "cannot"));
32032 /* Allocate a stack temp and fixup the address so it meets the particular
32033 memory requirements (either offetable or REG+REG addressing). */
32036 rs6000_allocate_stack_temp (enum machine_mode mode
,
32037 bool offsettable_p
,
32040 rtx stack
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
32041 rtx addr
= XEXP (stack
, 0);
32042 int strict_p
= (reload_in_progress
|| reload_completed
);
32044 if (!legitimate_indirect_address_p (addr
, strict_p
))
32047 && !rs6000_legitimate_offset_address_p (mode
, addr
, strict_p
, true))
32048 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
32050 else if (reg_reg_p
&& !legitimate_indexed_address_p (addr
, strict_p
))
32051 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
32057 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
32058 to such a form to deal with memory reference instructions like STFIWX that
32059 only take reg+reg addressing. */
32062 rs6000_address_for_fpconvert (rtx x
)
32064 int strict_p
= (reload_in_progress
|| reload_completed
);
32067 gcc_assert (MEM_P (x
));
32068 addr
= XEXP (x
, 0);
32069 if (! legitimate_indirect_address_p (addr
, strict_p
)
32070 && ! legitimate_indexed_address_p (addr
, strict_p
))
32072 if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
32074 rtx reg
= XEXP (addr
, 0);
32075 HOST_WIDE_INT size
= GET_MODE_SIZE (GET_MODE (x
));
32076 rtx size_rtx
= GEN_INT ((GET_CODE (addr
) == PRE_DEC
) ? -size
: size
);
32077 gcc_assert (REG_P (reg
));
32078 emit_insn (gen_add3_insn (reg
, reg
, size_rtx
));
32081 else if (GET_CODE (addr
) == PRE_MODIFY
)
32083 rtx reg
= XEXP (addr
, 0);
32084 rtx expr
= XEXP (addr
, 1);
32085 gcc_assert (REG_P (reg
));
32086 gcc_assert (GET_CODE (expr
) == PLUS
);
32087 emit_insn (gen_add3_insn (reg
, XEXP (expr
, 0), XEXP (expr
, 1)));
32091 x
= replace_equiv_address (x
, copy_addr_to_reg (addr
));
32097 /* Given a memory reference, if it is not in the form for altivec memory
32098 reference instructions (i.e. reg or reg+reg addressing with AND of -16),
32099 convert to the altivec format. */
32102 rs6000_address_for_altivec (rtx x
)
32104 gcc_assert (MEM_P (x
));
32105 if (!altivec_indexed_or_indirect_operand (x
, GET_MODE (x
)))
32107 rtx addr
= XEXP (x
, 0);
32108 int strict_p
= (reload_in_progress
|| reload_completed
);
32110 if (!legitimate_indexed_address_p (addr
, strict_p
)
32111 && !legitimate_indirect_address_p (addr
, strict_p
))
32112 addr
= copy_to_mode_reg (Pmode
, addr
);
32114 addr
= gen_rtx_AND (Pmode
, addr
, GEN_INT (-16));
32115 x
= change_address (x
, GET_MODE (x
), addr
);
32121 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
32123 On the RS/6000, all integer constants are acceptable, most won't be valid
32124 for particular insns, though. Only easy FP constants are acceptable. */
32127 rs6000_legitimate_constant_p (enum machine_mode mode
, rtx x
)
32129 if (TARGET_ELF
&& rs6000_tls_referenced_p (x
))
32132 return ((GET_CODE (x
) != CONST_DOUBLE
&& GET_CODE (x
) != CONST_VECTOR
)
32133 || GET_MODE (x
) == VOIDmode
32134 || (TARGET_POWERPC64
&& mode
== DImode
)
32135 || easy_fp_constant (x
, mode
)
32136 || easy_vector_constant (x
, mode
));
32141 /* Expand code to perform a call under the AIX or ELFv2 ABI. */
32144 rs6000_call_aix (rtx value
, rtx func_desc
, rtx flag
, rtx cookie
)
32146 rtx toc_reg
= gen_rtx_REG (Pmode
, TOC_REGNUM
);
32147 rtx toc_load
= NULL_RTX
;
32148 rtx toc_restore
= NULL_RTX
;
32150 rtx abi_reg
= NULL_RTX
;
32155 /* Handle longcall attributes. */
32156 if (INTVAL (cookie
) & CALL_LONG
)
32157 func_desc
= rs6000_longcall_ref (func_desc
);
32159 /* Handle indirect calls. */
32160 if (GET_CODE (func_desc
) != SYMBOL_REF
32161 || (DEFAULT_ABI
== ABI_AIX
&& !SYMBOL_REF_FUNCTION_P (func_desc
)))
32163 /* Save the TOC into its reserved slot before the call,
32164 and prepare to restore it after the call. */
32165 rtx stack_ptr
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
32166 rtx stack_toc_offset
= GEN_INT (RS6000_TOC_SAVE_SLOT
);
32167 rtx stack_toc_mem
= gen_frame_mem (Pmode
,
32168 gen_rtx_PLUS (Pmode
, stack_ptr
,
32169 stack_toc_offset
));
32170 toc_restore
= gen_rtx_SET (VOIDmode
, toc_reg
, stack_toc_mem
);
32172 /* Can we optimize saving the TOC in the prologue or
32173 do we need to do it at every call? */
32174 if (TARGET_SAVE_TOC_INDIRECT
&& !cfun
->calls_alloca
)
32175 cfun
->machine
->save_toc_in_prologue
= true;
32178 MEM_VOLATILE_P (stack_toc_mem
) = 1;
32179 emit_move_insn (stack_toc_mem
, toc_reg
);
32182 if (DEFAULT_ABI
== ABI_ELFv2
)
32184 /* A function pointer in the ELFv2 ABI is just a plain address, but
32185 the ABI requires it to be loaded into r12 before the call. */
32186 func_addr
= gen_rtx_REG (Pmode
, 12);
32187 emit_move_insn (func_addr
, func_desc
);
32188 abi_reg
= func_addr
;
32192 /* A function pointer under AIX is a pointer to a data area whose
32193 first word contains the actual address of the function, whose
32194 second word contains a pointer to its TOC, and whose third word
32195 contains a value to place in the static chain register (r11).
32196 Note that if we load the static chain, our "trampoline" need
32197 not have any executable code. */
32199 /* Load up address of the actual function. */
32200 func_desc
= force_reg (Pmode
, func_desc
);
32201 func_addr
= gen_reg_rtx (Pmode
);
32202 emit_move_insn (func_addr
, gen_rtx_MEM (Pmode
, func_desc
));
32204 /* Prepare to load the TOC of the called function. Note that the
32205 TOC load must happen immediately before the actual call so
32206 that unwinding the TOC registers works correctly. See the
32207 comment in frob_update_context. */
32208 rtx func_toc_offset
= GEN_INT (GET_MODE_SIZE (Pmode
));
32209 rtx func_toc_mem
= gen_rtx_MEM (Pmode
,
32210 gen_rtx_PLUS (Pmode
, func_desc
,
32212 toc_load
= gen_rtx_USE (VOIDmode
, func_toc_mem
);
32214 /* If we have a static chain, load it up. */
32215 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
32217 rtx sc_reg
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
32218 rtx func_sc_offset
= GEN_INT (2 * GET_MODE_SIZE (Pmode
));
32219 rtx func_sc_mem
= gen_rtx_MEM (Pmode
,
32220 gen_rtx_PLUS (Pmode
, func_desc
,
32222 emit_move_insn (sc_reg
, func_sc_mem
);
32229 /* Direct calls use the TOC: for local calls, the callee will
32230 assume the TOC register is set; for non-local calls, the
32231 PLT stub needs the TOC register. */
32233 func_addr
= func_desc
;
32236 /* Create the call. */
32237 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_addr
), flag
);
32238 if (value
!= NULL_RTX
)
32239 call
[0] = gen_rtx_SET (VOIDmode
, value
, call
[0]);
32243 call
[n_call
++] = toc_load
;
32245 call
[n_call
++] = toc_restore
;
32247 call
[n_call
++] = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
32249 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (n_call
, call
));
32250 insn
= emit_call_insn (insn
);
32252 /* Mention all registers defined by the ABI to hold information
32253 as uses in CALL_INSN_FUNCTION_USAGE. */
32255 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), abi_reg
);
32258 /* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */
32261 rs6000_sibcall_aix (rtx value
, rtx func_desc
, rtx flag
, rtx cookie
)
32266 gcc_assert (INTVAL (cookie
) == 0);
32268 /* Create the call. */
32269 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_desc
), flag
);
32270 if (value
!= NULL_RTX
)
32271 call
[0] = gen_rtx_SET (VOIDmode
, value
, call
[0]);
32273 call
[1] = simple_return_rtx
;
32275 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (2, call
));
32276 insn
= emit_call_insn (insn
);
32278 /* Note use of the TOC register. */
32279 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, TOC_REGNUM
));
32280 /* We need to also mark a use of the link register since the function we
32281 sibling-call to will use it to return to our caller. */
32282 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, LR_REGNO
));
32285 /* Return whether we need to always update the saved TOC pointer when we update
32286 the stack pointer. */
32289 rs6000_save_toc_in_prologue_p (void)
32291 return (cfun
&& cfun
->machine
&& cfun
->machine
->save_toc_in_prologue
);
32294 #ifdef HAVE_GAS_HIDDEN
32295 # define USE_HIDDEN_LINKONCE 1
32297 # define USE_HIDDEN_LINKONCE 0
32300 /* Fills in the label name that should be used for a 476 link stack thunk. */
32303 get_ppc476_thunk_name (char name
[32])
32305 gcc_assert (TARGET_LINK_STACK
);
32307 if (USE_HIDDEN_LINKONCE
)
32308 sprintf (name
, "__ppc476.get_thunk");
32310 ASM_GENERATE_INTERNAL_LABEL (name
, "LPPC476_", 0);
32313 /* This function emits the simple thunk routine that is used to preserve
32314 the link stack on the 476 cpu. */
32316 static void rs6000_code_end (void) ATTRIBUTE_UNUSED
;
32318 rs6000_code_end (void)
32323 if (!TARGET_LINK_STACK
)
32326 get_ppc476_thunk_name (name
);
32328 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
, get_identifier (name
),
32329 build_function_type_list (void_type_node
, NULL_TREE
));
32330 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
32331 NULL_TREE
, void_type_node
);
32332 TREE_PUBLIC (decl
) = 1;
32333 TREE_STATIC (decl
) = 1;
32336 if (USE_HIDDEN_LINKONCE
)
32338 DECL_COMDAT_GROUP (decl
) = DECL_ASSEMBLER_NAME (decl
);
32339 targetm
.asm_out
.unique_section (decl
, 0);
32340 switch_to_section (get_named_section (decl
, NULL
, 0));
32341 DECL_WEAK (decl
) = 1;
32342 ASM_WEAKEN_DECL (asm_out_file
, decl
, name
, 0);
32343 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
32344 targetm
.asm_out
.assemble_visibility (decl
, VISIBILITY_HIDDEN
);
32345 ASM_DECLARE_FUNCTION_NAME (asm_out_file
, name
, decl
);
32350 switch_to_section (text_section
);
32351 ASM_OUTPUT_LABEL (asm_out_file
, name
);
32354 DECL_INITIAL (decl
) = make_node (BLOCK
);
32355 current_function_decl
= decl
;
32356 init_function_start (decl
);
32357 first_function_block_is_cold
= false;
32358 /* Make sure unwind info is emitted for the thunk if needed. */
32359 final_start_function (emit_barrier (), asm_out_file
, 1);
32361 fputs ("\tblr\n", asm_out_file
);
32363 final_end_function ();
32364 init_insn_lengths ();
32365 free_after_compilation (cfun
);
32367 current_function_decl
= NULL
;
32370 /* Add r30 to hard reg set if the prologue sets it up and it is not
32371 pic_offset_table_rtx. */
32374 rs6000_set_up_by_prologue (struct hard_reg_set_container
*set
)
32376 if (!TARGET_SINGLE_PIC_BASE
32378 && TARGET_MINIMAL_TOC
32379 && get_pool_size () != 0)
32380 add_to_hard_reg_set (&set
->set
, Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
32384 /* Helper function for rs6000_split_logical to emit a logical instruction after
32385 spliting the operation to single GPR registers.
32387 DEST is the destination register.
32388 OP1 and OP2 are the input source registers.
32389 CODE is the base operation (AND, IOR, XOR, NOT).
32390 MODE is the machine mode.
32391 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
32392 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
32393 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
32394 CLOBBER_REG is either NULL or a scratch register of type CC to allow
32395 formation of the AND instructions. */
32398 rs6000_split_logical_inner (rtx dest
,
32401 enum rtx_code code
,
32402 enum machine_mode mode
,
32403 bool complement_final_p
,
32404 bool complement_op1_p
,
32405 bool complement_op2_p
,
32411 /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */
32412 if (op2
&& GET_CODE (op2
) == CONST_INT
32413 && (mode
== SImode
|| (mode
== DImode
&& TARGET_POWERPC64
))
32414 && !complement_final_p
&& !complement_op1_p
&& !complement_op2_p
)
32416 HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
32417 HOST_WIDE_INT value
= INTVAL (op2
) & mask
;
32419 /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */
32424 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
32428 else if (value
== mask
)
32430 if (!rtx_equal_p (dest
, op1
))
32431 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op1
));
32436 /* Optimize IOR/XOR of 0 to be a simple move. Split large operations
32437 into separate ORI/ORIS or XORI/XORIS instrucitons. */
32438 else if (code
== IOR
|| code
== XOR
)
32442 if (!rtx_equal_p (dest
, op1
))
32443 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op1
));
32449 if (complement_op1_p
)
32450 op1
= gen_rtx_NOT (mode
, op1
);
32452 if (complement_op2_p
)
32453 op2
= gen_rtx_NOT (mode
, op2
);
32455 bool_rtx
= ((code
== NOT
)
32456 ? gen_rtx_NOT (mode
, op1
)
32457 : gen_rtx_fmt_ee (code
, mode
, op1
, op2
));
32459 if (complement_final_p
)
32460 bool_rtx
= gen_rtx_NOT (mode
, bool_rtx
);
32462 set_rtx
= gen_rtx_SET (VOIDmode
, dest
, bool_rtx
);
32464 /* Is this AND with an explicit clobber? */
32467 rtx clobber
= gen_rtx_CLOBBER (VOIDmode
, clobber_reg
);
32468 set_rtx
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set_rtx
, clobber
));
32471 emit_insn (set_rtx
);
32475 /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These
32476 operations are split immediately during RTL generation to allow for more
32477 optimizations of the AND/IOR/XOR.
32479 OPERANDS is an array containing the destination and two input operands.
32480 CODE is the base operation (AND, IOR, XOR, NOT).
32481 MODE is the machine mode.
32482 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
32483 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
32484 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
32485 CLOBBER_REG is either NULL or a scratch register of type CC to allow
32486 formation of the AND instructions. */
32489 rs6000_split_logical_di (rtx operands
[3],
32490 enum rtx_code code
,
32491 bool complement_final_p
,
32492 bool complement_op1_p
,
32493 bool complement_op2_p
,
32496 const HOST_WIDE_INT lower_32bits
= HOST_WIDE_INT_C(0xffffffff);
32497 const HOST_WIDE_INT upper_32bits
= ~ lower_32bits
;
32498 const HOST_WIDE_INT sign_bit
= HOST_WIDE_INT_C(0x80000000);
32499 enum hi_lo
{ hi
= 0, lo
= 1 };
32500 rtx op0_hi_lo
[2], op1_hi_lo
[2], op2_hi_lo
[2];
32503 op0_hi_lo
[hi
] = gen_highpart (SImode
, operands
[0]);
32504 op1_hi_lo
[hi
] = gen_highpart (SImode
, operands
[1]);
32505 op0_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[0]);
32506 op1_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[1]);
32509 op2_hi_lo
[hi
] = op2_hi_lo
[lo
] = NULL_RTX
;
32512 if (GET_CODE (operands
[2]) != CONST_INT
)
32514 op2_hi_lo
[hi
] = gen_highpart_mode (SImode
, DImode
, operands
[2]);
32515 op2_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[2]);
32519 HOST_WIDE_INT value
= INTVAL (operands
[2]);
32520 HOST_WIDE_INT value_hi_lo
[2];
32522 gcc_assert (!complement_final_p
);
32523 gcc_assert (!complement_op1_p
);
32524 gcc_assert (!complement_op2_p
);
32526 value_hi_lo
[hi
] = value
>> 32;
32527 value_hi_lo
[lo
] = value
& lower_32bits
;
32529 for (i
= 0; i
< 2; i
++)
32531 HOST_WIDE_INT sub_value
= value_hi_lo
[i
];
32533 if (sub_value
& sign_bit
)
32534 sub_value
|= upper_32bits
;
32536 op2_hi_lo
[i
] = GEN_INT (sub_value
);
32538 /* If this is an AND instruction, check to see if we need to load
32539 the value in a register. */
32540 if (code
== AND
&& sub_value
!= -1 && sub_value
!= 0
32541 && !and_operand (op2_hi_lo
[i
], SImode
))
32542 op2_hi_lo
[i
] = force_reg (SImode
, op2_hi_lo
[i
]);
32547 for (i
= 0; i
< 2; i
++)
32549 /* Split large IOR/XOR operations. */
32550 if ((code
== IOR
|| code
== XOR
)
32551 && GET_CODE (op2_hi_lo
[i
]) == CONST_INT
32552 && !complement_final_p
32553 && !complement_op1_p
32554 && !complement_op2_p
32555 && clobber_reg
== NULL_RTX
32556 && !logical_const_operand (op2_hi_lo
[i
], SImode
))
32558 HOST_WIDE_INT value
= INTVAL (op2_hi_lo
[i
]);
32559 HOST_WIDE_INT hi_16bits
= value
& HOST_WIDE_INT_C(0xffff0000);
32560 HOST_WIDE_INT lo_16bits
= value
& HOST_WIDE_INT_C(0x0000ffff);
32561 rtx tmp
= gen_reg_rtx (SImode
);
32563 /* Make sure the constant is sign extended. */
32564 if ((hi_16bits
& sign_bit
) != 0)
32565 hi_16bits
|= upper_32bits
;
32567 rs6000_split_logical_inner (tmp
, op1_hi_lo
[i
], GEN_INT (hi_16bits
),
32568 code
, SImode
, false, false, false,
32571 rs6000_split_logical_inner (op0_hi_lo
[i
], tmp
, GEN_INT (lo_16bits
),
32572 code
, SImode
, false, false, false,
32576 rs6000_split_logical_inner (op0_hi_lo
[i
], op1_hi_lo
[i
], op2_hi_lo
[i
],
32577 code
, SImode
, complement_final_p
,
32578 complement_op1_p
, complement_op2_p
,
32585 /* Split the insns that make up boolean operations operating on multiple GPR
32586 registers. The boolean MD patterns ensure that the inputs either are
32587 exactly the same as the output registers, or there is no overlap.
32589 OPERANDS is an array containing the destination and two input operands.
32590 CODE is the base operation (AND, IOR, XOR, NOT).
32591 MODE is the machine mode.
32592 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
32593 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
32594 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
32595 CLOBBER_REG is either NULL or a scratch register of type CC to allow
32596 formation of the AND instructions. */
32599 rs6000_split_logical (rtx operands
[3],
32600 enum rtx_code code
,
32601 bool complement_final_p
,
32602 bool complement_op1_p
,
32603 bool complement_op2_p
,
32606 enum machine_mode mode
= GET_MODE (operands
[0]);
32607 enum machine_mode sub_mode
;
32609 int sub_size
, regno0
, regno1
, nregs
, i
;
32611 /* If this is DImode, use the specialized version that can run before
32612 register allocation. */
32613 if (mode
== DImode
&& !TARGET_POWERPC64
)
32615 rs6000_split_logical_di (operands
, code
, complement_final_p
,
32616 complement_op1_p
, complement_op2_p
,
32623 op2
= (code
== NOT
) ? NULL_RTX
: operands
[2];
32624 sub_mode
= (TARGET_POWERPC64
) ? DImode
: SImode
;
32625 sub_size
= GET_MODE_SIZE (sub_mode
);
32626 regno0
= REGNO (op0
);
32627 regno1
= REGNO (op1
);
32629 gcc_assert (reload_completed
);
32630 gcc_assert (IN_RANGE (regno0
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
32631 gcc_assert (IN_RANGE (regno1
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
32633 nregs
= rs6000_hard_regno_nregs
[(int)mode
][regno0
];
32634 gcc_assert (nregs
> 1);
32636 if (op2
&& REG_P (op2
))
32637 gcc_assert (IN_RANGE (REGNO (op2
), FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
32639 for (i
= 0; i
< nregs
; i
++)
32641 int offset
= i
* sub_size
;
32642 rtx sub_op0
= simplify_subreg (sub_mode
, op0
, mode
, offset
);
32643 rtx sub_op1
= simplify_subreg (sub_mode
, op1
, mode
, offset
);
32644 rtx sub_op2
= ((code
== NOT
)
32646 : simplify_subreg (sub_mode
, op2
, mode
, offset
));
32648 rs6000_split_logical_inner (sub_op0
, sub_op1
, sub_op2
, code
, sub_mode
,
32649 complement_final_p
, complement_op1_p
,
32650 complement_op2_p
, clobber_reg
);
32657 /* Return true if the peephole2 can combine a load involving a combination of
32658 an addis instruction and a load with an offset that can be fused together on
32662 operands[0] register set with addis
32663 operands[1] value set via addis
32664 operands[2] target register being loaded
32665 operands[3] D-form memory reference using operands[0].
32667 In addition, we are passed a boolean that is true if this is a peephole2,
32668 and we can use see if the addis_reg is dead after the insn and can be
32669 replaced by the target register. */
32672 fusion_gpr_load_p (rtx
*operands
, bool peep2_p
)
32674 rtx addis_reg
= operands
[0];
32675 rtx addis_value
= operands
[1];
32676 rtx target
= operands
[2];
32677 rtx mem
= operands
[3];
32681 /* Validate arguments. */
32682 if (!base_reg_operand (addis_reg
, GET_MODE (addis_reg
)))
32685 if (!base_reg_operand (target
, GET_MODE (target
)))
32688 if (!fusion_gpr_addis (addis_value
, GET_MODE (addis_value
)))
32691 if (!fusion_gpr_mem_load (mem
, GET_MODE (mem
)))
32694 /* Allow sign/zero extension. */
32695 if (GET_CODE (mem
) == ZERO_EXTEND
32696 || (GET_CODE (mem
) == SIGN_EXTEND
&& TARGET_P8_FUSION_SIGN
))
32697 mem
= XEXP (mem
, 0);
32702 addr
= XEXP (mem
, 0); /* either PLUS or LO_SUM. */
32703 if (GET_CODE (addr
) != PLUS
&& GET_CODE (addr
) != LO_SUM
)
32706 /* Validate that the register used to load the high value is either the
32707 register being loaded, or we can safely replace its use in a peephole2.
32709 If this is a peephole2, we assume that there are 2 instructions in the
32710 peephole (addis and load), so we want to check if the target register was
32711 not used in the memory address and the register to hold the addis result
32712 is dead after the peephole. */
32713 if (REGNO (addis_reg
) != REGNO (target
))
32718 if (reg_mentioned_p (target
, mem
))
32721 if (!peep2_reg_dead_p (2, addis_reg
))
32724 /* If the target register being loaded is the stack pointer, we must
32725 avoid loading any other value into it, even temporarily. */
32726 if (REG_P (target
) && REGNO (target
) == STACK_POINTER_REGNUM
)
32730 base_reg
= XEXP (addr
, 0);
32731 return REGNO (addis_reg
) == REGNO (base_reg
);
32734 /* During the peephole2 pass, adjust and expand the insns for a load fusion
32735 sequence. We adjust the addis register to use the target register. If the
32736 load sign extends, we adjust the code to do the zero extending load, and an
32737 explicit sign extension later since the fusion only covers zero extending
32741 operands[0] register set with addis (to be replaced with target)
32742 operands[1] value set via addis
32743 operands[2] target register being loaded
32744 operands[3] D-form memory reference using operands[0]. */
32747 expand_fusion_gpr_load (rtx
*operands
)
32749 rtx addis_value
= operands
[1];
32750 rtx target
= operands
[2];
32751 rtx orig_mem
= operands
[3];
32752 rtx new_addr
, new_mem
, orig_addr
, offset
;
32753 enum rtx_code plus_or_lo_sum
;
32754 enum machine_mode target_mode
= GET_MODE (target
);
32755 enum machine_mode extend_mode
= target_mode
;
32756 enum machine_mode ptr_mode
= Pmode
;
32757 enum rtx_code extend
= UNKNOWN
;
32758 rtx addis_reg
= ((ptr_mode
== target_mode
)
32760 : simplify_subreg (ptr_mode
, target
, target_mode
, 0));
32762 if (GET_CODE (orig_mem
) == ZERO_EXTEND
32763 || (TARGET_P8_FUSION_SIGN
&& GET_CODE (orig_mem
) == SIGN_EXTEND
))
32765 extend
= GET_CODE (orig_mem
);
32766 orig_mem
= XEXP (orig_mem
, 0);
32767 target_mode
= GET_MODE (orig_mem
);
32770 gcc_assert (MEM_P (orig_mem
));
32772 orig_addr
= XEXP (orig_mem
, 0);
32773 plus_or_lo_sum
= GET_CODE (orig_addr
);
32774 gcc_assert (plus_or_lo_sum
== PLUS
|| plus_or_lo_sum
== LO_SUM
);
32776 offset
= XEXP (orig_addr
, 1);
32777 new_addr
= gen_rtx_fmt_ee (plus_or_lo_sum
, ptr_mode
, addis_reg
, offset
);
32778 new_mem
= change_address (orig_mem
, target_mode
, new_addr
);
32780 if (extend
!= UNKNOWN
)
32781 new_mem
= gen_rtx_fmt_e (ZERO_EXTEND
, extend_mode
, new_mem
);
32783 emit_insn (gen_rtx_SET (VOIDmode
, addis_reg
, addis_value
));
32784 emit_insn (gen_rtx_SET (VOIDmode
, target
, new_mem
));
32786 if (extend
== SIGN_EXTEND
)
32788 int sub_off
= ((BYTES_BIG_ENDIAN
)
32789 ? GET_MODE_SIZE (extend_mode
) - GET_MODE_SIZE (target_mode
)
32792 = simplify_subreg (target_mode
, target
, extend_mode
, sub_off
);
32794 emit_insn (gen_rtx_SET (VOIDmode
, target
,
32795 gen_rtx_SIGN_EXTEND (extend_mode
, sign_reg
)));
32801 /* Return a string to fuse an addis instruction with a gpr load to the same
32802 register that we loaded up the addis instruction. The code is complicated,
32803 so we call output_asm_insn directly, and just return "".
32806 operands[0] register set with addis (must be same reg as target).
32807 operands[1] value set via addis
32808 operands[2] target register being loaded
32809 operands[3] D-form memory reference using operands[0]. */
32812 emit_fusion_gpr_load (rtx
*operands
)
32814 rtx addis_reg
= operands
[0];
32815 rtx addis_value
= operands
[1];
32816 rtx target
= operands
[2];
32817 rtx mem
= operands
[3];
32821 const char *addis_str
= NULL
;
32822 const char *load_str
= NULL
;
32823 const char *extend_insn
= NULL
;
32824 const char *mode_name
= NULL
;
32825 char insn_template
[80];
32826 enum machine_mode mode
;
32827 const char *comment_str
= ASM_COMMENT_START
;
32828 bool sign_p
= false;
32830 gcc_assert (REG_P (addis_reg
) && REG_P (target
));
32831 gcc_assert (REGNO (addis_reg
) == REGNO (target
));
32833 if (*comment_str
== ' ')
32836 /* Allow sign/zero extension. */
32837 if (GET_CODE (mem
) == ZERO_EXTEND
)
32838 mem
= XEXP (mem
, 0);
32840 else if (GET_CODE (mem
) == SIGN_EXTEND
&& TARGET_P8_FUSION_SIGN
)
32843 mem
= XEXP (mem
, 0);
32846 gcc_assert (MEM_P (mem
));
32847 addr
= XEXP (mem
, 0);
32848 if (GET_CODE (addr
) != PLUS
&& GET_CODE (addr
) != LO_SUM
)
32849 gcc_unreachable ();
32851 load_offset
= XEXP (addr
, 1);
32853 /* Now emit the load instruction to the same register. */
32854 mode
= GET_MODE (mem
);
32858 mode_name
= "char";
32860 extend_insn
= "extsb %0,%0";
32864 mode_name
= "short";
32866 extend_insn
= "extsh %0,%0";
32872 extend_insn
= "extsw %0,%0";
32876 if (TARGET_POWERPC64
)
32878 mode_name
= "long";
32882 gcc_unreachable ();
32886 gcc_unreachable ();
32889 /* Emit the addis instruction. */
32890 fuse_ops
[0] = target
;
32891 if (satisfies_constraint_L (addis_value
))
32893 fuse_ops
[1] = addis_value
;
32894 addis_str
= "lis %0,%v1";
32897 else if (GET_CODE (addis_value
) == PLUS
)
32899 rtx op0
= XEXP (addis_value
, 0);
32900 rtx op1
= XEXP (addis_value
, 1);
32902 if (REG_P (op0
) && CONST_INT_P (op1
)
32903 && satisfies_constraint_L (op1
))
32907 addis_str
= "addis %0,%1,%v2";
32911 else if (GET_CODE (addis_value
) == HIGH
)
32913 rtx value
= XEXP (addis_value
, 0);
32914 if (GET_CODE (value
) == UNSPEC
&& XINT (value
, 1) == UNSPEC_TOCREL
)
32916 fuse_ops
[1] = XVECEXP (value
, 0, 0); /* symbol ref. */
32917 fuse_ops
[2] = XVECEXP (value
, 0, 1); /* TOC register. */
32919 addis_str
= "addis %0,%2,%1@toc@ha";
32921 else if (TARGET_XCOFF
)
32922 addis_str
= "addis %0,%1@u(%2)";
32925 gcc_unreachable ();
32928 else if (GET_CODE (value
) == PLUS
)
32930 rtx op0
= XEXP (value
, 0);
32931 rtx op1
= XEXP (value
, 1);
32933 if (GET_CODE (op0
) == UNSPEC
32934 && XINT (op0
, 1) == UNSPEC_TOCREL
32935 && CONST_INT_P (op1
))
32937 fuse_ops
[1] = XVECEXP (op0
, 0, 0); /* symbol ref. */
32938 fuse_ops
[2] = XVECEXP (op0
, 0, 1); /* TOC register. */
32941 addis_str
= "addis %0,%2,%1+%3@toc@ha";
32943 else if (TARGET_XCOFF
)
32944 addis_str
= "addis %0,%1+%3@u(%2)";
32947 gcc_unreachable ();
32951 else if (satisfies_constraint_L (value
))
32953 fuse_ops
[1] = value
;
32954 addis_str
= "lis %0,%v1";
32957 else if (TARGET_ELF
&& !TARGET_POWERPC64
&& CONSTANT_P (value
))
32959 fuse_ops
[1] = value
;
32960 addis_str
= "lis %0,%1@ha";
32965 fatal_insn ("Could not generate addis value for fusion", addis_value
);
32967 sprintf (insn_template
, "%s\t\t%s gpr load fusion, type %s", addis_str
,
32968 comment_str
, mode_name
);
32969 output_asm_insn (insn_template
, fuse_ops
);
32971 /* Emit the D-form load instruction. */
32972 if (CONST_INT_P (load_offset
) && satisfies_constraint_I (load_offset
))
32974 sprintf (insn_template
, "%s %%0,%%1(%%0)", load_str
);
32975 fuse_ops
[1] = load_offset
;
32976 output_asm_insn (insn_template
, fuse_ops
);
32979 else if (GET_CODE (load_offset
) == UNSPEC
32980 && XINT (load_offset
, 1) == UNSPEC_TOCREL
)
32983 sprintf (insn_template
, "%s %%0,%%1@toc@l(%%0)", load_str
);
32985 else if (TARGET_XCOFF
)
32986 sprintf (insn_template
, "%s %%0,%%1@l(%%0)", load_str
);
32989 gcc_unreachable ();
32991 fuse_ops
[1] = XVECEXP (load_offset
, 0, 0);
32992 output_asm_insn (insn_template
, fuse_ops
);
32995 else if (GET_CODE (load_offset
) == PLUS
32996 && GET_CODE (XEXP (load_offset
, 0)) == UNSPEC
32997 && XINT (XEXP (load_offset
, 0), 1) == UNSPEC_TOCREL
32998 && CONST_INT_P (XEXP (load_offset
, 1)))
33000 rtx tocrel_unspec
= XEXP (load_offset
, 0);
33002 sprintf (insn_template
, "%s %%0,%%1+%%2@toc@l(%%0)", load_str
);
33004 else if (TARGET_XCOFF
)
33005 sprintf (insn_template
, "%s %%0,%%1+%%2@l(%%0)", load_str
);
33008 gcc_unreachable ();
33010 fuse_ops
[1] = XVECEXP (tocrel_unspec
, 0, 0);
33011 fuse_ops
[2] = XEXP (load_offset
, 1);
33012 output_asm_insn (insn_template
, fuse_ops
);
33015 else if (TARGET_ELF
&& !TARGET_POWERPC64
&& CONSTANT_P (load_offset
))
33017 sprintf (insn_template
, "%s %%0,%%1@l(%%0)", load_str
);
33019 fuse_ops
[1] = load_offset
;
33020 output_asm_insn (insn_template
, fuse_ops
);
33024 fatal_insn ("Unable to generate load offset for fusion", load_offset
);
33026 /* Handle sign extension. The peephole2 pass generates this as a separate
33027 insn, but we handle it just in case it got reattached. */
33030 gcc_assert (extend_insn
!= NULL
);
33031 output_asm_insn (extend_insn
, fuse_ops
);
33038 struct gcc_target targetm
= TARGET_INITIALIZER
;
33040 #include "gt-rs6000.h"