1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
5 Free Software Foundation, Inc.
6 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 3, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
45 #include "diagnostic-core.h"
51 #include "target-def.h"
52 #include "common/common-target.h"
53 #include "langhooks.h"
55 #include "cfglayout.h"
57 #include "sched-int.h"
59 #include "tree-flow.h"
62 #include "tm-constrs.h"
65 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
68 #include "gstab.h" /* for N_SLINE */
71 #ifndef TARGET_NO_PROTOTYPE
72 #define TARGET_NO_PROTOTYPE 0
75 #define min(A,B) ((A) < (B) ? (A) : (B))
76 #define max(A,B) ((A) > (B) ? (A) : (B))
78 /* Structure used to define the rs6000 stack */
79 typedef struct rs6000_stack
{
80 int reload_completed
; /* stack info won't change from here on */
81 int first_gp_reg_save
; /* first callee saved GP register used */
82 int first_fp_reg_save
; /* first callee saved FP register used */
83 int first_altivec_reg_save
; /* first callee saved AltiVec register used */
84 int lr_save_p
; /* true if the link reg needs to be saved */
85 int cr_save_p
; /* true if the CR reg needs to be saved */
86 unsigned int vrsave_mask
; /* mask of vec registers to save */
87 int push_p
; /* true if we need to allocate stack space */
88 int calls_p
; /* true if the function makes any calls */
89 int world_save_p
; /* true if we're saving *everything*:
90 r13-r31, cr, f14-f31, vrsave, v20-v31 */
91 enum rs6000_abi abi
; /* which ABI to use */
92 int gp_save_offset
; /* offset to save GP regs from initial SP */
93 int fp_save_offset
; /* offset to save FP regs from initial SP */
94 int altivec_save_offset
; /* offset to save AltiVec regs from initial SP */
95 int lr_save_offset
; /* offset to save LR from initial SP */
96 int cr_save_offset
; /* offset to save CR from initial SP */
97 int vrsave_save_offset
; /* offset to save VRSAVE from initial SP */
98 int spe_gp_save_offset
; /* offset to save spe 64-bit gprs */
99 int varargs_save_offset
; /* offset to save the varargs registers */
100 int ehrd_offset
; /* offset to EH return data */
101 int reg_size
; /* register size (4 or 8) */
102 HOST_WIDE_INT vars_size
; /* variable save area size */
103 int parm_size
; /* outgoing parameter size */
104 int save_size
; /* save area size */
105 int fixed_size
; /* fixed size of stack frame */
106 int gp_size
; /* size of saved GP registers */
107 int fp_size
; /* size of saved FP registers */
108 int altivec_size
; /* size of saved AltiVec registers */
109 int cr_size
; /* size to hold CR if not in save_size */
110 int vrsave_size
; /* size to hold VRSAVE if not in save_size */
111 int altivec_padding_size
; /* size of altivec alignment padding if
113 int spe_gp_size
; /* size of 64-bit GPR save size for SPE */
114 int spe_padding_size
;
115 HOST_WIDE_INT total_size
; /* total bytes allocated for stack */
116 int spe_64bit_regs_used
;
120 /* A C structure for machine-specific, per-function data.
121 This is added to the cfun structure. */
122 typedef struct GTY(()) machine_function
124 /* Some local-dynamic symbol. */
125 const char *some_ld_name
;
126 /* Whether the instruction chain has been scanned already. */
127 int insn_chain_scanned_p
;
128 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
129 int ra_needs_full_frame
;
130 /* Flags if __builtin_return_address (0) was used. */
132 /* Cache lr_save_p after expansion of builtin_eh_return. */
134 /* Whether we need to save the TOC to the reserved stack location in the
135 function prologue. */
136 bool save_toc_in_prologue
;
137 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
138 varargs save area. */
139 HOST_WIDE_INT varargs_save_offset
;
140 /* Temporary stack slot to use for SDmode copies. This slot is
141 64-bits wide and is allocated early enough so that the offset
142 does not overflow the 16-bit load/store offset field. */
143 rtx sdmode_stack_slot
;
146 /* Support targetm.vectorize.builtin_mask_for_load. */
147 static GTY(()) tree altivec_builtin_mask_for_load
;
149 /* Set to nonzero once AIX common-mode calls have been defined. */
150 static GTY(()) int common_mode_defined
;
152 /* Label number of label created for -mrelocatable, to call to so we can
153 get the address of the GOT section */
154 static int rs6000_pic_labelno
;
157 /* Counter for labels which are to be placed in .fixup. */
158 int fixuplabelno
= 0;
161 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
164 /* Specify the machine mode that pointers have. After generation of rtl, the
165 compiler makes no further distinction between pointers and any other objects
166 of this machine mode. The type is unsigned since not all things that
167 include rs6000.h also include machmode.h. */
168 unsigned rs6000_pmode
;
170 /* Width in bits of a pointer. */
171 unsigned rs6000_pointer_size
;
173 #ifdef HAVE_AS_GNU_ATTRIBUTE
174 /* Flag whether floating point values have been passed/returned. */
175 static bool rs6000_passes_float
;
176 /* Flag whether vector values have been passed/returned. */
177 static bool rs6000_passes_vector
;
178 /* Flag whether small (<= 8 byte) structures have been returned. */
179 static bool rs6000_returns_struct
;
182 /* Value is TRUE if register/mode pair is acceptable. */
183 bool rs6000_hard_regno_mode_ok_p
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
185 /* Maximum number of registers needed for a given register class and mode. */
186 unsigned char rs6000_class_max_nregs
[NUM_MACHINE_MODES
][LIM_REG_CLASSES
];
188 /* How many registers are needed for a given register and mode. */
189 unsigned char rs6000_hard_regno_nregs
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
191 /* Map register number to register class. */
192 enum reg_class rs6000_regno_regclass
[FIRST_PSEUDO_REGISTER
];
194 /* Reload functions based on the type and the vector unit. */
195 static enum insn_code rs6000_vector_reload
[NUM_MACHINE_MODES
][2];
197 static int dbg_cost_ctrl
;
199 /* Built in types. */
200 tree rs6000_builtin_types
[RS6000_BTI_MAX
];
201 tree rs6000_builtin_decls
[RS6000_BUILTIN_COUNT
];
203 /* Flag to say the TOC is initialized */
205 char toc_label_name
[10];
207 /* Cached value of rs6000_variable_issue. This is cached in
208 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
209 static short cached_can_issue_more
;
211 static GTY(()) section
*read_only_data_section
;
212 static GTY(()) section
*private_data_section
;
213 static GTY(()) section
*read_only_private_data_section
;
214 static GTY(()) section
*sdata2_section
;
215 static GTY(()) section
*toc_section
;
217 struct builtin_description
219 const unsigned int mask
;
220 const enum insn_code icode
;
221 const char *const name
;
222 const enum rs6000_builtins code
;
225 /* Describe the vector unit used for modes. */
226 enum rs6000_vector rs6000_vector_unit
[NUM_MACHINE_MODES
];
227 enum rs6000_vector rs6000_vector_mem
[NUM_MACHINE_MODES
];
229 /* Register classes for various constraints that are based on the target
231 enum reg_class rs6000_constraints
[RS6000_CONSTRAINT_MAX
];
233 /* Describe the alignment of a vector. */
234 int rs6000_vector_align
[NUM_MACHINE_MODES
];
236 /* Map selected modes to types for builtins. */
237 static GTY(()) tree builtin_mode_to_type
[MAX_MACHINE_MODE
][2];
239 /* What modes to automatically generate reciprocal divide estimate (fre) and
240 reciprocal sqrt (frsqrte) for. */
241 unsigned char rs6000_recip_bits
[MAX_MACHINE_MODE
];
243 /* Masks to determine which reciprocal esitmate instructions to generate
245 enum rs6000_recip_mask
{
246 RECIP_SF_DIV
= 0x001, /* Use divide estimate */
247 RECIP_DF_DIV
= 0x002,
248 RECIP_V4SF_DIV
= 0x004,
249 RECIP_V2DF_DIV
= 0x008,
251 RECIP_SF_RSQRT
= 0x010, /* Use reciprocal sqrt estimate. */
252 RECIP_DF_RSQRT
= 0x020,
253 RECIP_V4SF_RSQRT
= 0x040,
254 RECIP_V2DF_RSQRT
= 0x080,
256 /* Various combination of flags for -mrecip=xxx. */
258 RECIP_ALL
= (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
259 | RECIP_V2DF_DIV
| RECIP_SF_RSQRT
| RECIP_DF_RSQRT
260 | RECIP_V4SF_RSQRT
| RECIP_V2DF_RSQRT
),
262 RECIP_HIGH_PRECISION
= RECIP_ALL
,
264 /* On low precision machines like the power5, don't enable double precision
265 reciprocal square root estimate, since it isn't accurate enough. */
266 RECIP_LOW_PRECISION
= (RECIP_ALL
& ~(RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
))
269 /* -mrecip options. */
272 const char *string
; /* option name */
273 unsigned int mask
; /* mask bits to set */
274 } recip_options
[] = {
275 { "all", RECIP_ALL
},
276 { "none", RECIP_NONE
},
277 { "div", (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
279 { "divf", (RECIP_SF_DIV
| RECIP_V4SF_DIV
) },
280 { "divd", (RECIP_DF_DIV
| RECIP_V2DF_DIV
) },
281 { "rsqrt", (RECIP_SF_RSQRT
| RECIP_DF_RSQRT
| RECIP_V4SF_RSQRT
282 | RECIP_V2DF_RSQRT
) },
283 { "rsqrtf", (RECIP_SF_RSQRT
| RECIP_V4SF_RSQRT
) },
284 { "rsqrtd", (RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
) },
287 /* 2 argument gen function typedef. */
288 typedef rtx (*gen_2arg_fn_t
) (rtx
, rtx
, rtx
);
290 /* Pointer to function (in rs6000-c.c) that can define or undefine target
291 macros that have changed. Languages that don't support the preprocessor
292 don't link in rs6000-c.c, so we can't call it directly. */
293 void (*rs6000_target_modify_macros_ptr
) (bool, int, unsigned);
296 /* Target cpu costs. */
298 struct processor_costs
{
299 const int mulsi
; /* cost of SImode multiplication. */
300 const int mulsi_const
; /* cost of SImode multiplication by constant. */
301 const int mulsi_const9
; /* cost of SImode mult by short constant. */
302 const int muldi
; /* cost of DImode multiplication. */
303 const int divsi
; /* cost of SImode division. */
304 const int divdi
; /* cost of DImode division. */
305 const int fp
; /* cost of simple SFmode and DFmode insns. */
306 const int dmul
; /* cost of DFmode multiplication (and fmadd). */
307 const int sdiv
; /* cost of SFmode division (fdivs). */
308 const int ddiv
; /* cost of DFmode division (fdiv). */
309 const int cache_line_size
; /* cache line size in bytes. */
310 const int l1_cache_size
; /* size of l1 cache, in kilobytes. */
311 const int l2_cache_size
; /* size of l2 cache, in kilobytes. */
312 const int simultaneous_prefetches
; /* number of parallel prefetch
316 const struct processor_costs
*rs6000_cost
;
318 /* Processor costs (relative to an add) */
320 /* Instruction size costs on 32bit processors. */
322 struct processor_costs size32_cost
= {
323 COSTS_N_INSNS (1), /* mulsi */
324 COSTS_N_INSNS (1), /* mulsi_const */
325 COSTS_N_INSNS (1), /* mulsi_const9 */
326 COSTS_N_INSNS (1), /* muldi */
327 COSTS_N_INSNS (1), /* divsi */
328 COSTS_N_INSNS (1), /* divdi */
329 COSTS_N_INSNS (1), /* fp */
330 COSTS_N_INSNS (1), /* dmul */
331 COSTS_N_INSNS (1), /* sdiv */
332 COSTS_N_INSNS (1), /* ddiv */
339 /* Instruction size costs on 64bit processors. */
341 struct processor_costs size64_cost
= {
342 COSTS_N_INSNS (1), /* mulsi */
343 COSTS_N_INSNS (1), /* mulsi_const */
344 COSTS_N_INSNS (1), /* mulsi_const9 */
345 COSTS_N_INSNS (1), /* muldi */
346 COSTS_N_INSNS (1), /* divsi */
347 COSTS_N_INSNS (1), /* divdi */
348 COSTS_N_INSNS (1), /* fp */
349 COSTS_N_INSNS (1), /* dmul */
350 COSTS_N_INSNS (1), /* sdiv */
351 COSTS_N_INSNS (1), /* ddiv */
358 /* Instruction costs on RIOS1 processors. */
360 struct processor_costs rios1_cost
= {
361 COSTS_N_INSNS (5), /* mulsi */
362 COSTS_N_INSNS (4), /* mulsi_const */
363 COSTS_N_INSNS (3), /* mulsi_const9 */
364 COSTS_N_INSNS (5), /* muldi */
365 COSTS_N_INSNS (19), /* divsi */
366 COSTS_N_INSNS (19), /* divdi */
367 COSTS_N_INSNS (2), /* fp */
368 COSTS_N_INSNS (2), /* dmul */
369 COSTS_N_INSNS (19), /* sdiv */
370 COSTS_N_INSNS (19), /* ddiv */
371 128, /* cache line size */
377 /* Instruction costs on RIOS2 processors. */
379 struct processor_costs rios2_cost
= {
380 COSTS_N_INSNS (2), /* mulsi */
381 COSTS_N_INSNS (2), /* mulsi_const */
382 COSTS_N_INSNS (2), /* mulsi_const9 */
383 COSTS_N_INSNS (2), /* muldi */
384 COSTS_N_INSNS (13), /* divsi */
385 COSTS_N_INSNS (13), /* divdi */
386 COSTS_N_INSNS (2), /* fp */
387 COSTS_N_INSNS (2), /* dmul */
388 COSTS_N_INSNS (17), /* sdiv */
389 COSTS_N_INSNS (17), /* ddiv */
390 256, /* cache line size */
396 /* Instruction costs on RS64A processors. */
398 struct processor_costs rs64a_cost
= {
399 COSTS_N_INSNS (20), /* mulsi */
400 COSTS_N_INSNS (12), /* mulsi_const */
401 COSTS_N_INSNS (8), /* mulsi_const9 */
402 COSTS_N_INSNS (34), /* muldi */
403 COSTS_N_INSNS (65), /* divsi */
404 COSTS_N_INSNS (67), /* divdi */
405 COSTS_N_INSNS (4), /* fp */
406 COSTS_N_INSNS (4), /* dmul */
407 COSTS_N_INSNS (31), /* sdiv */
408 COSTS_N_INSNS (31), /* ddiv */
409 128, /* cache line size */
415 /* Instruction costs on MPCCORE processors. */
417 struct processor_costs mpccore_cost
= {
418 COSTS_N_INSNS (2), /* mulsi */
419 COSTS_N_INSNS (2), /* mulsi_const */
420 COSTS_N_INSNS (2), /* mulsi_const9 */
421 COSTS_N_INSNS (2), /* muldi */
422 COSTS_N_INSNS (6), /* divsi */
423 COSTS_N_INSNS (6), /* divdi */
424 COSTS_N_INSNS (4), /* fp */
425 COSTS_N_INSNS (5), /* dmul */
426 COSTS_N_INSNS (10), /* sdiv */
427 COSTS_N_INSNS (17), /* ddiv */
428 32, /* cache line size */
434 /* Instruction costs on PPC403 processors. */
436 struct processor_costs ppc403_cost
= {
437 COSTS_N_INSNS (4), /* mulsi */
438 COSTS_N_INSNS (4), /* mulsi_const */
439 COSTS_N_INSNS (4), /* mulsi_const9 */
440 COSTS_N_INSNS (4), /* muldi */
441 COSTS_N_INSNS (33), /* divsi */
442 COSTS_N_INSNS (33), /* divdi */
443 COSTS_N_INSNS (11), /* fp */
444 COSTS_N_INSNS (11), /* dmul */
445 COSTS_N_INSNS (11), /* sdiv */
446 COSTS_N_INSNS (11), /* ddiv */
447 32, /* cache line size */
453 /* Instruction costs on PPC405 processors. */
455 struct processor_costs ppc405_cost
= {
456 COSTS_N_INSNS (5), /* mulsi */
457 COSTS_N_INSNS (4), /* mulsi_const */
458 COSTS_N_INSNS (3), /* mulsi_const9 */
459 COSTS_N_INSNS (5), /* muldi */
460 COSTS_N_INSNS (35), /* divsi */
461 COSTS_N_INSNS (35), /* divdi */
462 COSTS_N_INSNS (11), /* fp */
463 COSTS_N_INSNS (11), /* dmul */
464 COSTS_N_INSNS (11), /* sdiv */
465 COSTS_N_INSNS (11), /* ddiv */
466 32, /* cache line size */
472 /* Instruction costs on PPC440 processors. */
474 struct processor_costs ppc440_cost
= {
475 COSTS_N_INSNS (3), /* mulsi */
476 COSTS_N_INSNS (2), /* mulsi_const */
477 COSTS_N_INSNS (2), /* mulsi_const9 */
478 COSTS_N_INSNS (3), /* muldi */
479 COSTS_N_INSNS (34), /* divsi */
480 COSTS_N_INSNS (34), /* divdi */
481 COSTS_N_INSNS (5), /* fp */
482 COSTS_N_INSNS (5), /* dmul */
483 COSTS_N_INSNS (19), /* sdiv */
484 COSTS_N_INSNS (33), /* ddiv */
485 32, /* cache line size */
491 /* Instruction costs on PPC476 processors. */
493 struct processor_costs ppc476_cost
= {
494 COSTS_N_INSNS (4), /* mulsi */
495 COSTS_N_INSNS (4), /* mulsi_const */
496 COSTS_N_INSNS (4), /* mulsi_const9 */
497 COSTS_N_INSNS (4), /* muldi */
498 COSTS_N_INSNS (11), /* divsi */
499 COSTS_N_INSNS (11), /* divdi */
500 COSTS_N_INSNS (6), /* fp */
501 COSTS_N_INSNS (6), /* dmul */
502 COSTS_N_INSNS (19), /* sdiv */
503 COSTS_N_INSNS (33), /* ddiv */
504 32, /* l1 cache line size */
510 /* Instruction costs on PPC601 processors. */
512 struct processor_costs ppc601_cost
= {
513 COSTS_N_INSNS (5), /* mulsi */
514 COSTS_N_INSNS (5), /* mulsi_const */
515 COSTS_N_INSNS (5), /* mulsi_const9 */
516 COSTS_N_INSNS (5), /* muldi */
517 COSTS_N_INSNS (36), /* divsi */
518 COSTS_N_INSNS (36), /* divdi */
519 COSTS_N_INSNS (4), /* fp */
520 COSTS_N_INSNS (5), /* dmul */
521 COSTS_N_INSNS (17), /* sdiv */
522 COSTS_N_INSNS (31), /* ddiv */
523 32, /* cache line size */
529 /* Instruction costs on PPC603 processors. */
531 struct processor_costs ppc603_cost
= {
532 COSTS_N_INSNS (5), /* mulsi */
533 COSTS_N_INSNS (3), /* mulsi_const */
534 COSTS_N_INSNS (2), /* mulsi_const9 */
535 COSTS_N_INSNS (5), /* muldi */
536 COSTS_N_INSNS (37), /* divsi */
537 COSTS_N_INSNS (37), /* divdi */
538 COSTS_N_INSNS (3), /* fp */
539 COSTS_N_INSNS (4), /* dmul */
540 COSTS_N_INSNS (18), /* sdiv */
541 COSTS_N_INSNS (33), /* ddiv */
542 32, /* cache line size */
548 /* Instruction costs on PPC604 processors. */
550 struct processor_costs ppc604_cost
= {
551 COSTS_N_INSNS (4), /* mulsi */
552 COSTS_N_INSNS (4), /* mulsi_const */
553 COSTS_N_INSNS (4), /* mulsi_const9 */
554 COSTS_N_INSNS (4), /* muldi */
555 COSTS_N_INSNS (20), /* divsi */
556 COSTS_N_INSNS (20), /* divdi */
557 COSTS_N_INSNS (3), /* fp */
558 COSTS_N_INSNS (3), /* dmul */
559 COSTS_N_INSNS (18), /* sdiv */
560 COSTS_N_INSNS (32), /* ddiv */
561 32, /* cache line size */
567 /* Instruction costs on PPC604e processors. */
569 struct processor_costs ppc604e_cost
= {
570 COSTS_N_INSNS (2), /* mulsi */
571 COSTS_N_INSNS (2), /* mulsi_const */
572 COSTS_N_INSNS (2), /* mulsi_const9 */
573 COSTS_N_INSNS (2), /* muldi */
574 COSTS_N_INSNS (20), /* divsi */
575 COSTS_N_INSNS (20), /* divdi */
576 COSTS_N_INSNS (3), /* fp */
577 COSTS_N_INSNS (3), /* dmul */
578 COSTS_N_INSNS (18), /* sdiv */
579 COSTS_N_INSNS (32), /* ddiv */
580 32, /* cache line size */
586 /* Instruction costs on PPC620 processors. */
588 struct processor_costs ppc620_cost
= {
589 COSTS_N_INSNS (5), /* mulsi */
590 COSTS_N_INSNS (4), /* mulsi_const */
591 COSTS_N_INSNS (3), /* mulsi_const9 */
592 COSTS_N_INSNS (7), /* muldi */
593 COSTS_N_INSNS (21), /* divsi */
594 COSTS_N_INSNS (37), /* divdi */
595 COSTS_N_INSNS (3), /* fp */
596 COSTS_N_INSNS (3), /* dmul */
597 COSTS_N_INSNS (18), /* sdiv */
598 COSTS_N_INSNS (32), /* ddiv */
599 128, /* cache line size */
605 /* Instruction costs on PPC630 processors. */
607 struct processor_costs ppc630_cost
= {
608 COSTS_N_INSNS (5), /* mulsi */
609 COSTS_N_INSNS (4), /* mulsi_const */
610 COSTS_N_INSNS (3), /* mulsi_const9 */
611 COSTS_N_INSNS (7), /* muldi */
612 COSTS_N_INSNS (21), /* divsi */
613 COSTS_N_INSNS (37), /* divdi */
614 COSTS_N_INSNS (3), /* fp */
615 COSTS_N_INSNS (3), /* dmul */
616 COSTS_N_INSNS (17), /* sdiv */
617 COSTS_N_INSNS (21), /* ddiv */
618 128, /* cache line size */
624 /* Instruction costs on Cell processor. */
625 /* COSTS_N_INSNS (1) ~ one add. */
627 struct processor_costs ppccell_cost
= {
628 COSTS_N_INSNS (9/2)+2, /* mulsi */
629 COSTS_N_INSNS (6/2), /* mulsi_const */
630 COSTS_N_INSNS (6/2), /* mulsi_const9 */
631 COSTS_N_INSNS (15/2)+2, /* muldi */
632 COSTS_N_INSNS (38/2), /* divsi */
633 COSTS_N_INSNS (70/2), /* divdi */
634 COSTS_N_INSNS (10/2), /* fp */
635 COSTS_N_INSNS (10/2), /* dmul */
636 COSTS_N_INSNS (74/2), /* sdiv */
637 COSTS_N_INSNS (74/2), /* ddiv */
638 128, /* cache line size */
644 /* Instruction costs on PPC750 and PPC7400 processors. */
646 struct processor_costs ppc750_cost
= {
647 COSTS_N_INSNS (5), /* mulsi */
648 COSTS_N_INSNS (3), /* mulsi_const */
649 COSTS_N_INSNS (2), /* mulsi_const9 */
650 COSTS_N_INSNS (5), /* muldi */
651 COSTS_N_INSNS (17), /* divsi */
652 COSTS_N_INSNS (17), /* divdi */
653 COSTS_N_INSNS (3), /* fp */
654 COSTS_N_INSNS (3), /* dmul */
655 COSTS_N_INSNS (17), /* sdiv */
656 COSTS_N_INSNS (31), /* ddiv */
657 32, /* cache line size */
663 /* Instruction costs on PPC7450 processors. */
665 struct processor_costs ppc7450_cost
= {
666 COSTS_N_INSNS (4), /* mulsi */
667 COSTS_N_INSNS (3), /* mulsi_const */
668 COSTS_N_INSNS (3), /* mulsi_const9 */
669 COSTS_N_INSNS (4), /* muldi */
670 COSTS_N_INSNS (23), /* divsi */
671 COSTS_N_INSNS (23), /* divdi */
672 COSTS_N_INSNS (5), /* fp */
673 COSTS_N_INSNS (5), /* dmul */
674 COSTS_N_INSNS (21), /* sdiv */
675 COSTS_N_INSNS (35), /* ddiv */
676 32, /* cache line size */
682 /* Instruction costs on PPC8540 processors. */
684 struct processor_costs ppc8540_cost
= {
685 COSTS_N_INSNS (4), /* mulsi */
686 COSTS_N_INSNS (4), /* mulsi_const */
687 COSTS_N_INSNS (4), /* mulsi_const9 */
688 COSTS_N_INSNS (4), /* muldi */
689 COSTS_N_INSNS (19), /* divsi */
690 COSTS_N_INSNS (19), /* divdi */
691 COSTS_N_INSNS (4), /* fp */
692 COSTS_N_INSNS (4), /* dmul */
693 COSTS_N_INSNS (29), /* sdiv */
694 COSTS_N_INSNS (29), /* ddiv */
695 32, /* cache line size */
698 1, /* prefetch streams /*/
701 /* Instruction costs on E300C2 and E300C3 cores. */
703 struct processor_costs ppce300c2c3_cost
= {
704 COSTS_N_INSNS (4), /* mulsi */
705 COSTS_N_INSNS (4), /* mulsi_const */
706 COSTS_N_INSNS (4), /* mulsi_const9 */
707 COSTS_N_INSNS (4), /* muldi */
708 COSTS_N_INSNS (19), /* divsi */
709 COSTS_N_INSNS (19), /* divdi */
710 COSTS_N_INSNS (3), /* fp */
711 COSTS_N_INSNS (4), /* dmul */
712 COSTS_N_INSNS (18), /* sdiv */
713 COSTS_N_INSNS (33), /* ddiv */
717 1, /* prefetch streams /*/
720 /* Instruction costs on PPCE500MC processors. */
722 struct processor_costs ppce500mc_cost
= {
723 COSTS_N_INSNS (4), /* mulsi */
724 COSTS_N_INSNS (4), /* mulsi_const */
725 COSTS_N_INSNS (4), /* mulsi_const9 */
726 COSTS_N_INSNS (4), /* muldi */
727 COSTS_N_INSNS (14), /* divsi */
728 COSTS_N_INSNS (14), /* divdi */
729 COSTS_N_INSNS (8), /* fp */
730 COSTS_N_INSNS (10), /* dmul */
731 COSTS_N_INSNS (36), /* sdiv */
732 COSTS_N_INSNS (66), /* ddiv */
733 64, /* cache line size */
736 1, /* prefetch streams /*/
739 /* Instruction costs on PPCE500MC64 processors. */
741 struct processor_costs ppce500mc64_cost
= {
742 COSTS_N_INSNS (4), /* mulsi */
743 COSTS_N_INSNS (4), /* mulsi_const */
744 COSTS_N_INSNS (4), /* mulsi_const9 */
745 COSTS_N_INSNS (4), /* muldi */
746 COSTS_N_INSNS (14), /* divsi */
747 COSTS_N_INSNS (14), /* divdi */
748 COSTS_N_INSNS (4), /* fp */
749 COSTS_N_INSNS (10), /* dmul */
750 COSTS_N_INSNS (36), /* sdiv */
751 COSTS_N_INSNS (66), /* ddiv */
752 64, /* cache line size */
755 1, /* prefetch streams /*/
758 /* Instruction costs on AppliedMicro Titan processors. */
760 struct processor_costs titan_cost
= {
761 COSTS_N_INSNS (5), /* mulsi */
762 COSTS_N_INSNS (5), /* mulsi_const */
763 COSTS_N_INSNS (5), /* mulsi_const9 */
764 COSTS_N_INSNS (5), /* muldi */
765 COSTS_N_INSNS (18), /* divsi */
766 COSTS_N_INSNS (18), /* divdi */
767 COSTS_N_INSNS (10), /* fp */
768 COSTS_N_INSNS (10), /* dmul */
769 COSTS_N_INSNS (46), /* sdiv */
770 COSTS_N_INSNS (72), /* ddiv */
771 32, /* cache line size */
774 1, /* prefetch streams /*/
777 /* Instruction costs on POWER4 and POWER5 processors. */
779 struct processor_costs power4_cost
= {
780 COSTS_N_INSNS (3), /* mulsi */
781 COSTS_N_INSNS (2), /* mulsi_const */
782 COSTS_N_INSNS (2), /* mulsi_const9 */
783 COSTS_N_INSNS (4), /* muldi */
784 COSTS_N_INSNS (18), /* divsi */
785 COSTS_N_INSNS (34), /* divdi */
786 COSTS_N_INSNS (3), /* fp */
787 COSTS_N_INSNS (3), /* dmul */
788 COSTS_N_INSNS (17), /* sdiv */
789 COSTS_N_INSNS (17), /* ddiv */
790 128, /* cache line size */
793 8, /* prefetch streams /*/
796 /* Instruction costs on POWER6 processors. */
798 struct processor_costs power6_cost
= {
799 COSTS_N_INSNS (8), /* mulsi */
800 COSTS_N_INSNS (8), /* mulsi_const */
801 COSTS_N_INSNS (8), /* mulsi_const9 */
802 COSTS_N_INSNS (8), /* muldi */
803 COSTS_N_INSNS (22), /* divsi */
804 COSTS_N_INSNS (28), /* divdi */
805 COSTS_N_INSNS (3), /* fp */
806 COSTS_N_INSNS (3), /* dmul */
807 COSTS_N_INSNS (13), /* sdiv */
808 COSTS_N_INSNS (16), /* ddiv */
809 128, /* cache line size */
812 16, /* prefetch streams */
815 /* Instruction costs on POWER7 processors. */
817 struct processor_costs power7_cost
= {
818 COSTS_N_INSNS (2), /* mulsi */
819 COSTS_N_INSNS (2), /* mulsi_const */
820 COSTS_N_INSNS (2), /* mulsi_const9 */
821 COSTS_N_INSNS (2), /* muldi */
822 COSTS_N_INSNS (18), /* divsi */
823 COSTS_N_INSNS (34), /* divdi */
824 COSTS_N_INSNS (3), /* fp */
825 COSTS_N_INSNS (3), /* dmul */
826 COSTS_N_INSNS (13), /* sdiv */
827 COSTS_N_INSNS (16), /* ddiv */
828 128, /* cache line size */
831 12, /* prefetch streams */
834 /* Instruction costs on POWER A2 processors. */
836 struct processor_costs ppca2_cost
= {
837 COSTS_N_INSNS (16), /* mulsi */
838 COSTS_N_INSNS (16), /* mulsi_const */
839 COSTS_N_INSNS (16), /* mulsi_const9 */
840 COSTS_N_INSNS (16), /* muldi */
841 COSTS_N_INSNS (22), /* divsi */
842 COSTS_N_INSNS (28), /* divdi */
843 COSTS_N_INSNS (3), /* fp */
844 COSTS_N_INSNS (3), /* dmul */
845 COSTS_N_INSNS (59), /* sdiv */
846 COSTS_N_INSNS (72), /* ddiv */
850 16, /* prefetch streams */
854 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
855 #undef RS6000_BUILTIN_1
856 #undef RS6000_BUILTIN_2
857 #undef RS6000_BUILTIN_3
858 #undef RS6000_BUILTIN_A
859 #undef RS6000_BUILTIN_D
860 #undef RS6000_BUILTIN_E
861 #undef RS6000_BUILTIN_P
862 #undef RS6000_BUILTIN_Q
863 #undef RS6000_BUILTIN_S
864 #undef RS6000_BUILTIN_X
866 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
867 { NAME, ICODE, MASK, ATTR },
869 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
870 { NAME, ICODE, MASK, ATTR },
872 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
873 { NAME, ICODE, MASK, ATTR },
875 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
876 { NAME, ICODE, MASK, ATTR },
878 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
879 { NAME, ICODE, MASK, ATTR },
881 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
882 { NAME, ICODE, MASK, ATTR },
884 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
885 { NAME, ICODE, MASK, ATTR },
887 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
888 { NAME, ICODE, MASK, ATTR },
890 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
891 { NAME, ICODE, MASK, ATTR },
893 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
894 { NAME, ICODE, MASK, ATTR },
896 struct rs6000_builtin_info_type
{
898 const enum insn_code icode
;
903 static const struct rs6000_builtin_info_type rs6000_builtin_info
[] =
905 #include "rs6000-builtin.def"
908 #undef RS6000_BUILTIN_1
909 #undef RS6000_BUILTIN_2
910 #undef RS6000_BUILTIN_3
911 #undef RS6000_BUILTIN_A
912 #undef RS6000_BUILTIN_D
913 #undef RS6000_BUILTIN_E
914 #undef RS6000_BUILTIN_P
915 #undef RS6000_BUILTIN_Q
916 #undef RS6000_BUILTIN_S
917 #undef RS6000_BUILTIN_X
919 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
920 static tree (*rs6000_veclib_handler
) (tree
, tree
, tree
);
923 static bool rs6000_function_ok_for_sibcall (tree
, tree
);
924 static const char *rs6000_invalid_within_doloop (const_rtx
);
925 static bool rs6000_legitimate_address_p (enum machine_mode
, rtx
, bool);
926 static bool rs6000_debug_legitimate_address_p (enum machine_mode
, rtx
, bool);
927 static rtx
rs6000_generate_compare (rtx
, enum machine_mode
);
928 static void rs6000_emit_stack_tie (void);
929 static bool spe_func_has_64bit_regs_p (void);
930 static rtx
gen_frame_mem_offset (enum machine_mode
, rtx
, int);
931 static unsigned rs6000_hash_constant (rtx
);
932 static unsigned toc_hash_function (const void *);
933 static int toc_hash_eq (const void *, const void *);
934 static bool reg_offset_addressing_ok_p (enum machine_mode
);
935 static bool virtual_stack_registers_memory_p (rtx
);
936 static bool constant_pool_expr_p (rtx
);
937 static bool legitimate_small_data_p (enum machine_mode
, rtx
);
938 static bool legitimate_lo_sum_address_p (enum machine_mode
, rtx
, int);
939 static struct machine_function
* rs6000_init_machine_status (void);
940 static bool rs6000_assemble_integer (rtx
, unsigned int, int);
941 static bool no_global_regs_above (int, bool);
942 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
943 static void rs6000_assemble_visibility (tree
, int);
945 static int rs6000_ra_ever_killed (void);
946 static bool rs6000_attribute_takes_identifier_p (const_tree
);
947 static tree
rs6000_handle_longcall_attribute (tree
*, tree
, tree
, int, bool *);
948 static tree
rs6000_handle_altivec_attribute (tree
*, tree
, tree
, int, bool *);
949 static bool rs6000_ms_bitfield_layout_p (const_tree
);
950 static tree
rs6000_handle_struct_attribute (tree
*, tree
, tree
, int, bool *);
951 static void rs6000_eliminate_indexed_memrefs (rtx operands
[2]);
952 static const char *rs6000_mangle_type (const_tree
);
953 static void rs6000_set_default_type_attributes (tree
);
954 static rtx
rs6000_savres_routine_sym (rs6000_stack_t
*, bool, bool, bool);
955 static rtx
rs6000_emit_stack_reset (rs6000_stack_t
*, rtx
, rtx
, int, bool);
956 static bool rs6000_reg_live_or_pic_offset_p (int);
957 static tree
rs6000_builtin_vectorized_libmass (tree
, tree
, tree
);
958 static tree
rs6000_builtin_vectorized_function (tree
, tree
, tree
);
959 static void rs6000_restore_saved_cr (rtx
, int);
960 static bool rs6000_output_addr_const_extra (FILE *, rtx
);
961 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT
);
962 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT
);
963 static void rs6000_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
965 static rtx
rs6000_emit_set_long_const (rtx
, HOST_WIDE_INT
, HOST_WIDE_INT
);
966 static bool rs6000_return_in_memory (const_tree
, const_tree
);
967 static rtx
rs6000_function_value (const_tree
, const_tree
, bool);
968 static void rs6000_file_start (void);
970 static int rs6000_elf_reloc_rw_mask (void);
971 static void rs6000_elf_asm_out_constructor (rtx
, int) ATTRIBUTE_UNUSED
;
972 static void rs6000_elf_asm_out_destructor (rtx
, int) ATTRIBUTE_UNUSED
;
973 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED
;
974 static void rs6000_elf_asm_init_sections (void);
975 static section
*rs6000_elf_select_rtx_section (enum machine_mode
, rtx
,
976 unsigned HOST_WIDE_INT
);
977 static void rs6000_elf_encode_section_info (tree
, rtx
, int)
980 static bool rs6000_use_blocks_for_constant_p (enum machine_mode
, const_rtx
);
981 static void rs6000_alloc_sdmode_stack_slot (void);
982 static void rs6000_instantiate_decls (void);
984 static void rs6000_xcoff_asm_output_anchor (rtx
);
985 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
986 static void rs6000_xcoff_asm_init_sections (void);
987 static int rs6000_xcoff_reloc_rw_mask (void);
988 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree
);
989 static section
*rs6000_xcoff_select_section (tree
, int,
990 unsigned HOST_WIDE_INT
);
991 static void rs6000_xcoff_unique_section (tree
, int);
992 static section
*rs6000_xcoff_select_rtx_section
993 (enum machine_mode
, rtx
, unsigned HOST_WIDE_INT
);
994 static const char * rs6000_xcoff_strip_name_encoding (const char *);
995 static unsigned int rs6000_xcoff_section_type_flags (tree
, const char *, int);
996 static void rs6000_xcoff_file_start (void);
997 static void rs6000_xcoff_file_end (void);
999 static int rs6000_variable_issue (FILE *, int, rtx
, int);
1000 static int rs6000_register_move_cost (enum machine_mode
,
1001 reg_class_t
, reg_class_t
);
1002 static int rs6000_memory_move_cost (enum machine_mode
, reg_class_t
, bool);
1003 static bool rs6000_rtx_costs (rtx
, int, int, int, int *, bool);
1004 static bool rs6000_debug_rtx_costs (rtx
, int, int, int, int *, bool);
1005 static int rs6000_debug_address_cost (rtx
, bool);
1006 static int rs6000_adjust_cost (rtx
, rtx
, rtx
, int);
1007 static int rs6000_debug_adjust_cost (rtx
, rtx
, rtx
, int);
1008 static void rs6000_sched_init (FILE *, int, int);
1009 static bool is_microcoded_insn (rtx
);
1010 static bool is_nonpipeline_insn (rtx
);
1011 static bool is_cracked_insn (rtx
);
1012 static bool is_branch_slot_insn (rtx
);
1013 static bool is_load_insn (rtx
);
1014 static rtx
get_store_dest (rtx pat
);
1015 static bool is_store_insn (rtx
);
1016 static bool set_to_load_agen (rtx
,rtx
);
1017 static bool adjacent_mem_locations (rtx
,rtx
);
1018 static int rs6000_adjust_priority (rtx
, int);
1019 static int rs6000_issue_rate (void);
1020 static bool rs6000_is_costly_dependence (dep_t
, int, int);
1021 static rtx
get_next_active_insn (rtx
, rtx
);
1022 static bool insn_terminates_group_p (rtx
, enum group_termination
);
1023 static bool insn_must_be_first_in_group (rtx
);
1024 static bool insn_must_be_last_in_group (rtx
);
1025 static bool is_costly_group (rtx
*, rtx
);
1026 static int force_new_group (int, FILE *, rtx
*, rtx
, bool *, int, int *);
1027 static int redefine_groups (FILE *, int, rtx
, rtx
);
1028 static int pad_groups (FILE *, int, rtx
, rtx
);
1029 static void rs6000_sched_finish (FILE *, int);
1030 static int rs6000_sched_reorder (FILE *, int, rtx
*, int *, int);
1031 static int rs6000_sched_reorder2 (FILE *, int, rtx
*, int *, int);
1032 static int rs6000_use_sched_lookahead (void);
1033 static int rs6000_use_sched_lookahead_guard (rtx
);
1034 static void * rs6000_alloc_sched_context (void);
1035 static void rs6000_init_sched_context (void *, bool);
1036 static void rs6000_set_sched_context (void *);
1037 static void rs6000_free_sched_context (void *);
1038 static tree
rs6000_builtin_reciprocal (unsigned int, bool, bool);
1039 static tree
rs6000_builtin_mask_for_load (void);
1040 static tree
rs6000_builtin_mul_widen_even (tree
);
1041 static tree
rs6000_builtin_mul_widen_odd (tree
);
1042 static bool rs6000_builtin_support_vector_misalignment (enum
1046 static int rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt
,
1048 static enum machine_mode
rs6000_preferred_simd_mode (enum machine_mode
);
1050 static void def_builtin (const char *, tree
, enum rs6000_builtins
);
1051 static bool rs6000_vector_alignment_reachable (const_tree
, bool);
1052 static void rs6000_init_builtins (void);
1053 static tree
rs6000_builtin_decl (unsigned, bool);
1055 static rtx
rs6000_expand_unop_builtin (enum insn_code
, tree
, rtx
);
1056 static rtx
rs6000_expand_binop_builtin (enum insn_code
, tree
, rtx
);
1057 static rtx
rs6000_expand_ternop_builtin (enum insn_code
, tree
, rtx
);
1058 static rtx
rs6000_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
1059 static void altivec_init_builtins (void);
1060 static unsigned builtin_hash_function (const void *);
1061 static int builtin_hash_eq (const void *, const void *);
1062 static tree
builtin_function_type (enum machine_mode
, enum machine_mode
,
1063 enum machine_mode
, enum machine_mode
,
1064 enum rs6000_builtins
, const char *name
);
1065 static void rs6000_common_init_builtins (void);
1066 static void rs6000_init_libfuncs (void);
1068 static void paired_init_builtins (void);
1069 static rtx
paired_expand_builtin (tree
, rtx
, bool *);
1070 static rtx
paired_expand_lv_builtin (enum insn_code
, tree
, rtx
);
1071 static rtx
paired_expand_stv_builtin (enum insn_code
, tree
);
1072 static rtx
paired_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
1074 static void spe_init_builtins (void);
1075 static rtx
spe_expand_builtin (tree
, rtx
, bool *);
1076 static rtx
spe_expand_stv_builtin (enum insn_code
, tree
);
1077 static rtx
spe_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
1078 static rtx
spe_expand_evsel_builtin (enum insn_code
, tree
, rtx
);
1079 static int rs6000_emit_int_cmove (rtx
, rtx
, rtx
, rtx
);
1080 static rs6000_stack_t
*rs6000_stack_info (void);
1081 static void debug_stack_info (rs6000_stack_t
*);
1083 static rtx
altivec_expand_builtin (tree
, rtx
, bool *);
1084 static rtx
altivec_expand_ld_builtin (tree
, rtx
, bool *);
1085 static rtx
altivec_expand_st_builtin (tree
, rtx
, bool *);
1086 static rtx
altivec_expand_dst_builtin (tree
, rtx
, bool *);
1087 static rtx
altivec_expand_abs_builtin (enum insn_code
, tree
, rtx
);
1088 static rtx
altivec_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
1089 static rtx
altivec_expand_stv_builtin (enum insn_code
, tree
);
1090 static rtx
altivec_expand_vec_init_builtin (tree
, tree
, rtx
);
1091 static rtx
altivec_expand_vec_set_builtin (tree
);
1092 static rtx
altivec_expand_vec_ext_builtin (tree
, rtx
);
1093 static int get_element_number (tree
, tree
);
1094 static void rs6000_option_override (void);
1095 static int rs6000_loop_align_max_skip (rtx
);
1096 static int first_altivec_reg_to_save (void);
1097 static unsigned int compute_vrsave_mask (void);
1098 static void compute_save_world_info (rs6000_stack_t
*info_ptr
);
1099 static void is_altivec_return_reg (rtx
, void *);
1100 static rtx
generate_set_vrsave (rtx
, rs6000_stack_t
*, int);
1101 int easy_vector_constant (rtx
, enum machine_mode
);
1102 static rtx
rs6000_dwarf_register_span (rtx
);
1103 static void rs6000_init_dwarf_reg_sizes_extra (tree
);
1104 static rtx
rs6000_legitimize_address (rtx
, rtx
, enum machine_mode
);
1105 static rtx
rs6000_debug_legitimize_address (rtx
, rtx
, enum machine_mode
);
1106 static rtx
rs6000_legitimize_tls_address (rtx
, enum tls_model
);
1107 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
1108 static rtx
rs6000_delegitimize_address (rtx
);
1109 static bool rs6000_const_not_ok_for_debug_p (rtx
);
1110 static rtx
rs6000_tls_get_addr (void);
1111 static rtx
rs6000_got_sym (void);
1112 static int rs6000_tls_symbol_ref_1 (rtx
*, void *);
1113 static const char *rs6000_get_some_local_dynamic_name (void);
1114 static int rs6000_get_some_local_dynamic_name_1 (rtx
*, void *);
1115 static rtx
rs6000_complex_function_value (enum machine_mode
);
1116 static rtx
rs6000_spe_function_arg (const CUMULATIVE_ARGS
*,
1117 enum machine_mode
, const_tree
);
1118 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*,
1119 HOST_WIDE_INT
, int);
1120 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*,
1123 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*,
1126 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*,
1127 const_tree
, HOST_WIDE_INT
,
1129 static rtx
rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*, const_tree
, bool, bool);
1130 static rtx
rs6000_mixed_function_arg (enum machine_mode
, const_tree
, int);
1131 static void rs6000_function_arg_advance (cumulative_args_t
, enum machine_mode
,
1133 static rtx
rs6000_function_arg (cumulative_args_t
, enum machine_mode
,
1135 static unsigned int rs6000_function_arg_boundary (enum machine_mode
,
1137 static void rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
);
1138 static void setup_incoming_varargs (cumulative_args_t
,
1139 enum machine_mode
, tree
,
1141 static bool rs6000_pass_by_reference (cumulative_args_t
, enum machine_mode
,
1143 static int rs6000_arg_partial_bytes (cumulative_args_t
, enum machine_mode
,
1145 static const char *invalid_arg_for_unprototyped_fn (const_tree
, const_tree
, const_tree
);
1147 static void macho_branch_islands (void);
1148 static int no_previous_def (tree function_name
);
1149 static tree
get_prev_label (tree function_name
);
1150 static void rs6000_darwin_file_start (void);
1153 static tree
rs6000_build_builtin_va_list (void);
1154 static void rs6000_va_start (tree
, rtx
);
1155 static tree
rs6000_gimplify_va_arg (tree
, tree
, gimple_seq
*, gimple_seq
*);
1156 static bool rs6000_must_pass_in_stack (enum machine_mode
, const_tree
);
1157 static bool rs6000_scalar_mode_supported_p (enum machine_mode
);
1158 static bool rs6000_vector_mode_supported_p (enum machine_mode
);
1159 static rtx
rs6000_emit_vector_compare_inner (enum rtx_code
, rtx
, rtx
);
1160 static rtx
rs6000_emit_vector_compare (enum rtx_code
, rtx
, rtx
,
1162 static tree
rs6000_stack_protect_fail (void);
1164 static rtx
rs6000_legitimize_reload_address (rtx
, enum machine_mode
, int, int,
1167 static rtx
rs6000_debug_legitimize_reload_address (rtx
, enum machine_mode
, int,
1170 rtx (*rs6000_legitimize_reload_address_ptr
) (rtx
, enum machine_mode
, int, int,
1172 = rs6000_legitimize_reload_address
;
1174 static bool rs6000_mode_dependent_address_p (const_rtx
);
1175 static bool rs6000_mode_dependent_address (const_rtx
);
1176 static bool rs6000_debug_mode_dependent_address (const_rtx
);
1177 static bool (*rs6000_mode_dependent_address_ptr
) (const_rtx
)
1178 = rs6000_mode_dependent_address
;
1180 static enum reg_class
rs6000_secondary_reload_class (enum reg_class
,
1181 enum machine_mode
, rtx
);
1182 static enum reg_class
rs6000_debug_secondary_reload_class (enum reg_class
,
1185 enum reg_class (*rs6000_secondary_reload_class_ptr
) (enum reg_class
,
1186 enum machine_mode
, rtx
)
1187 = rs6000_secondary_reload_class
;
1189 static enum reg_class
rs6000_preferred_reload_class (rtx
, enum reg_class
);
1190 static enum reg_class
rs6000_debug_preferred_reload_class (rtx
,
1192 enum reg_class (*rs6000_preferred_reload_class_ptr
) (rtx
, enum reg_class
)
1193 = rs6000_preferred_reload_class
;
1195 static bool rs6000_secondary_memory_needed (enum reg_class
, enum reg_class
,
1198 static bool rs6000_debug_secondary_memory_needed (enum reg_class
,
1202 bool (*rs6000_secondary_memory_needed_ptr
) (enum reg_class
, enum reg_class
,
1204 = rs6000_secondary_memory_needed
;
1206 static bool rs6000_cannot_change_mode_class (enum machine_mode
,
1209 static bool rs6000_debug_cannot_change_mode_class (enum machine_mode
,
1213 bool (*rs6000_cannot_change_mode_class_ptr
) (enum machine_mode
,
1216 = rs6000_cannot_change_mode_class
;
1218 static reg_class_t
rs6000_secondary_reload (bool, rtx
, reg_class_t
,
1220 struct secondary_reload_info
*);
1222 const int INSN_NOT_AVAILABLE
= -1;
1223 static enum machine_mode
rs6000_eh_return_filter_mode (void);
1224 static bool rs6000_can_eliminate (const int, const int);
1225 static void rs6000_conditional_register_usage (void);
1226 static void rs6000_trampoline_init (rtx
, tree
, rtx
);
1227 static bool rs6000_cannot_force_const_mem (enum machine_mode
, rtx
);
1228 static bool rs6000_legitimate_constant_p (enum machine_mode
, rtx
);
1229 static bool rs6000_save_toc_in_prologue_p (void);
1230 static void rs6000_code_end (void) ATTRIBUTE_UNUSED
;
1231 static void rs6000_set_up_by_prologue (struct hard_reg_set_container
*);
1233 /* Hash table stuff for keeping track of TOC entries. */
1235 struct GTY(()) toc_hash_struct
1237 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1238 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1240 enum machine_mode key_mode
;
1244 static GTY ((param_is (struct toc_hash_struct
))) htab_t toc_hash_table
;
1246 /* Hash table to keep track of the argument types for builtin functions. */
1248 struct GTY(()) builtin_hash_struct
1251 enum machine_mode mode
[4]; /* return value + 3 arguments. */
1252 unsigned char uns_p
[4]; /* and whether the types are unsigned. */
1255 static GTY ((param_is (struct builtin_hash_struct
))) htab_t builtin_hash_table
;
1257 static bool rs6000_valid_attribute_p (tree
, tree
, tree
, int);
1258 static void rs6000_function_specific_save (struct cl_target_option
*);
1259 static void rs6000_function_specific_restore (struct cl_target_option
*);
1260 static void rs6000_function_specific_print (FILE *, int,
1261 struct cl_target_option
*);
1262 static bool rs6000_can_inline_p (tree
, tree
);
1263 static void rs6000_set_current_function (tree
);
1266 /* Default register names. */
1267 char rs6000_reg_names
[][8] =
1269 "0", "1", "2", "3", "4", "5", "6", "7",
1270 "8", "9", "10", "11", "12", "13", "14", "15",
1271 "16", "17", "18", "19", "20", "21", "22", "23",
1272 "24", "25", "26", "27", "28", "29", "30", "31",
1273 "0", "1", "2", "3", "4", "5", "6", "7",
1274 "8", "9", "10", "11", "12", "13", "14", "15",
1275 "16", "17", "18", "19", "20", "21", "22", "23",
1276 "24", "25", "26", "27", "28", "29", "30", "31",
1277 "mq", "lr", "ctr","ap",
1278 "0", "1", "2", "3", "4", "5", "6", "7",
1280 /* AltiVec registers. */
1281 "0", "1", "2", "3", "4", "5", "6", "7",
1282 "8", "9", "10", "11", "12", "13", "14", "15",
1283 "16", "17", "18", "19", "20", "21", "22", "23",
1284 "24", "25", "26", "27", "28", "29", "30", "31",
1286 /* SPE registers. */
1287 "spe_acc", "spefscr",
1288 /* Soft frame pointer. */
1292 #ifdef TARGET_REGNAMES
1293 static const char alt_reg_names
[][8] =
1295 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1296 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1297 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1298 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1299 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1300 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1301 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1302 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1303 "mq", "lr", "ctr", "ap",
1304 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1306 /* AltiVec registers. */
1307 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1308 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1309 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1310 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1312 /* SPE registers. */
1313 "spe_acc", "spefscr",
1314 /* Soft frame pointer. */
1319 /* Table of valid machine attributes. */
1321 static const struct attribute_spec rs6000_attribute_table
[] =
1323 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
1324 affects_type_identity } */
1325 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute
,
1327 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1329 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1331 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1333 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1335 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1336 SUBTARGET_ATTRIBUTE_TABLE
,
1338 { NULL
, 0, 0, false, false, false, NULL
, false }
1341 #ifndef MASK_STRICT_ALIGN
1342 #define MASK_STRICT_ALIGN 0
1344 #ifndef TARGET_PROFILE_KERNEL
1345 #define TARGET_PROFILE_KERNEL 0
1348 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1349 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1351 /* Initialize the GCC target structure. */
1352 #undef TARGET_ATTRIBUTE_TABLE
1353 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1354 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1355 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1356 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1357 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1359 #undef TARGET_ASM_ALIGNED_DI_OP
1360 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1362 /* Default unaligned ops are only provided for ELF. Find the ops needed
1363 for non-ELF systems. */
1364 #ifndef OBJECT_FORMAT_ELF
1366 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1368 #undef TARGET_ASM_UNALIGNED_HI_OP
1369 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1370 #undef TARGET_ASM_UNALIGNED_SI_OP
1371 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1372 #undef TARGET_ASM_UNALIGNED_DI_OP
1373 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1376 #undef TARGET_ASM_UNALIGNED_HI_OP
1377 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1378 #undef TARGET_ASM_UNALIGNED_SI_OP
1379 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1380 #undef TARGET_ASM_UNALIGNED_DI_OP
1381 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1382 #undef TARGET_ASM_ALIGNED_DI_OP
1383 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1387 /* This hook deals with fixups for relocatable code and DI-mode objects
1389 #undef TARGET_ASM_INTEGER
1390 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1392 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1393 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1394 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1397 #undef TARGET_SET_UP_BY_PROLOGUE
1398 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1400 #undef TARGET_HAVE_TLS
1401 #define TARGET_HAVE_TLS HAVE_AS_TLS
1403 #undef TARGET_CANNOT_FORCE_CONST_MEM
1404 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1406 #undef TARGET_DELEGITIMIZE_ADDRESS
1407 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1409 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1410 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1412 #undef TARGET_ASM_FUNCTION_PROLOGUE
1413 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1414 #undef TARGET_ASM_FUNCTION_EPILOGUE
1415 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1417 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1418 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1420 #undef TARGET_LEGITIMIZE_ADDRESS
1421 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1423 #undef TARGET_SCHED_VARIABLE_ISSUE
1424 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1426 #undef TARGET_SCHED_ISSUE_RATE
1427 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1428 #undef TARGET_SCHED_ADJUST_COST
1429 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1430 #undef TARGET_SCHED_ADJUST_PRIORITY
1431 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1432 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1433 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1434 #undef TARGET_SCHED_INIT
1435 #define TARGET_SCHED_INIT rs6000_sched_init
1436 #undef TARGET_SCHED_FINISH
1437 #define TARGET_SCHED_FINISH rs6000_sched_finish
1438 #undef TARGET_SCHED_REORDER
1439 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1440 #undef TARGET_SCHED_REORDER2
1441 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1443 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1444 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1446 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1447 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1449 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1450 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1451 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1452 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1453 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1454 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1455 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1456 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1458 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1459 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1460 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN
1461 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN rs6000_builtin_mul_widen_even
1462 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD
1463 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD rs6000_builtin_mul_widen_odd
1464 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1465 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1466 rs6000_builtin_support_vector_misalignment
1467 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1468 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1469 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1470 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1471 rs6000_builtin_vectorization_cost
1472 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1473 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1474 rs6000_preferred_simd_mode
1476 #undef TARGET_INIT_BUILTINS
1477 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1478 #undef TARGET_BUILTIN_DECL
1479 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1481 #undef TARGET_EXPAND_BUILTIN
1482 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1484 #undef TARGET_MANGLE_TYPE
1485 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1487 #undef TARGET_INIT_LIBFUNCS
1488 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1491 #undef TARGET_BINDS_LOCAL_P
1492 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1495 #undef TARGET_MS_BITFIELD_LAYOUT_P
1496 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1498 #undef TARGET_ASM_OUTPUT_MI_THUNK
1499 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1501 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1502 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1504 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1505 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1507 #undef TARGET_INVALID_WITHIN_DOLOOP
1508 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
1510 #undef TARGET_REGISTER_MOVE_COST
1511 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1512 #undef TARGET_MEMORY_MOVE_COST
1513 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1514 #undef TARGET_RTX_COSTS
1515 #define TARGET_RTX_COSTS rs6000_rtx_costs
1516 #undef TARGET_ADDRESS_COST
1517 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
1519 #undef TARGET_DWARF_REGISTER_SPAN
1520 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1522 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1523 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1525 /* On rs6000, function arguments are promoted, as are function return
1527 #undef TARGET_PROMOTE_FUNCTION_MODE
1528 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
1530 #undef TARGET_RETURN_IN_MEMORY
1531 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1533 #undef TARGET_SETUP_INCOMING_VARARGS
1534 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1536 /* Always strict argument naming on rs6000. */
1537 #undef TARGET_STRICT_ARGUMENT_NAMING
1538 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1539 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1540 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1541 #undef TARGET_SPLIT_COMPLEX_ARG
1542 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1543 #undef TARGET_MUST_PASS_IN_STACK
1544 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1545 #undef TARGET_PASS_BY_REFERENCE
1546 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1547 #undef TARGET_ARG_PARTIAL_BYTES
1548 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1549 #undef TARGET_FUNCTION_ARG_ADVANCE
1550 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1551 #undef TARGET_FUNCTION_ARG
1552 #define TARGET_FUNCTION_ARG rs6000_function_arg
1553 #undef TARGET_FUNCTION_ARG_BOUNDARY
1554 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1556 #undef TARGET_BUILD_BUILTIN_VA_LIST
1557 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1559 #undef TARGET_EXPAND_BUILTIN_VA_START
1560 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1562 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1563 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1565 #undef TARGET_EH_RETURN_FILTER_MODE
1566 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1568 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1569 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1571 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1572 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1574 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1575 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1577 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1578 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1580 #undef TARGET_OPTION_OVERRIDE
1581 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1583 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1584 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1585 rs6000_builtin_vectorized_function
1588 #undef TARGET_STACK_PROTECT_FAIL
1589 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1592 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1593 The PowerPC architecture requires only weak consistency among
1594 processors--that is, memory accesses between processors need not be
1595 sequentially consistent and memory accesses among processors can occur
1596 in any order. The ability to order memory accesses weakly provides
1597 opportunities for more efficient use of the system bus. Unless a
1598 dependency exists, the 604e allows read operations to precede store
1600 #undef TARGET_RELAXED_ORDERING
1601 #define TARGET_RELAXED_ORDERING true
1604 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1605 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1608 /* Use a 32-bit anchor range. This leads to sequences like:
1610 addis tmp,anchor,high
1613 where tmp itself acts as an anchor, and can be shared between
1614 accesses to the same 64k page. */
1615 #undef TARGET_MIN_ANCHOR_OFFSET
1616 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1617 #undef TARGET_MAX_ANCHOR_OFFSET
1618 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1619 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1620 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1622 #undef TARGET_BUILTIN_RECIPROCAL
1623 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1625 #undef TARGET_EXPAND_TO_RTL_HOOK
1626 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1628 #undef TARGET_INSTANTIATE_DECLS
1629 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1631 #undef TARGET_SECONDARY_RELOAD
1632 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1634 #undef TARGET_LEGITIMATE_ADDRESS_P
1635 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1637 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1638 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1640 #undef TARGET_CAN_ELIMINATE
1641 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1643 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1644 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1646 #undef TARGET_TRAMPOLINE_INIT
1647 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1649 #undef TARGET_FUNCTION_VALUE
1650 #define TARGET_FUNCTION_VALUE rs6000_function_value
1652 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1653 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1655 #undef TARGET_OPTION_SAVE
1656 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1658 #undef TARGET_OPTION_RESTORE
1659 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1661 #undef TARGET_OPTION_PRINT
1662 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1664 #undef TARGET_CAN_INLINE_P
1665 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1667 #undef TARGET_SET_CURRENT_FUNCTION
1668 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1670 #undef TARGET_LEGITIMATE_CONSTANT_P
1671 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1673 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
1674 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok
1677 /* Simplifications for entries below. */
1680 POWERPC_BASE_MASK
= MASK_POWERPC
| MASK_NEW_MNEMONICS
,
1681 POWERPC_7400_MASK
= POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_ALTIVEC
1684 /* Some OSs don't support saving the high part of 64-bit registers on context
1685 switch. Other OSs don't support saving Altivec registers. On those OSs, we
1686 don't touch the MASK_POWERPC64 or MASK_ALTIVEC settings; if the user wants
1687 either, the user must explicitly specify them and we won't interfere with
1688 the user's specification. */
1691 POWER_MASKS
= MASK_POWER
| MASK_POWER2
| MASK_MULTIPLE
| MASK_STRING
,
1692 POWERPC_MASKS
= (POWERPC_BASE_MASK
| MASK_PPC_GPOPT
| MASK_STRICT_ALIGN
1693 | MASK_PPC_GFXOPT
| MASK_POWERPC64
| MASK_ALTIVEC
1694 | MASK_MFCRF
| MASK_POPCNTB
| MASK_FPRND
| MASK_MULHW
1695 | MASK_DLMZB
| MASK_CMPB
| MASK_MFPGPR
| MASK_DFP
1696 | MASK_POPCNTD
| MASK_VSX
| MASK_ISEL
| MASK_NO_UPDATE
1697 | MASK_RECIP_PRECISION
)
1700 /* Masks for instructions set at various powerpc ISAs. */
1702 ISA_2_1_MASKS
= MASK_MFCRF
,
1703 ISA_2_2_MASKS
= (ISA_2_1_MASKS
| MASK_POPCNTB
),
1704 ISA_2_4_MASKS
= (ISA_2_2_MASKS
| MASK_FPRND
),
1706 /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add
1707 ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel,
1708 fre, fsqrt, etc. were no longer documented as optional. Group masks by
1709 server and embedded. */
1710 ISA_2_5_MASKS_EMBEDDED
= (ISA_2_2_MASKS
| MASK_CMPB
| MASK_RECIP_PRECISION
1711 | MASK_PPC_GFXOPT
| MASK_PPC_GPOPT
),
1712 ISA_2_5_MASKS_SERVER
= (ISA_2_5_MASKS_EMBEDDED
| MASK_DFP
),
1714 /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
1715 altivec is a win so enable it. */
1716 ISA_2_6_MASKS_EMBEDDED
= (ISA_2_5_MASKS_EMBEDDED
| MASK_POPCNTD
),
1717 ISA_2_6_MASKS_SERVER
= (ISA_2_5_MASKS_SERVER
| MASK_POPCNTD
| MASK_ALTIVEC
1723 const char *const name
; /* Canonical processor name. */
1724 const enum processor_type processor
; /* Processor type enum value. */
1725 const int target_enable
; /* Target flags to enable. */
1728 static struct rs6000_ptt
const processor_target_table
[] =
1730 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1731 #include "rs6000-cpus.def"
1735 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
1739 rs6000_cpu_name_lookup (const char *name
)
1745 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
1746 if (! strcmp (name
, processor_target_table
[i
].name
))
1754 /* Return number of consecutive hard regs needed starting at reg REGNO
1755 to hold something of mode MODE.
1756 This is ordinarily the length in words of a value of mode MODE
1757 but can be less for certain modes in special long registers.
1759 For the SPE, GPRs are 64 bits but only 32 bits are visible in
1760 scalar instructions. The upper 32 bits are only available to the
1763 POWER and PowerPC GPRs hold 32 bits worth;
1764 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
1767 rs6000_hard_regno_nregs_internal (int regno
, enum machine_mode mode
)
1769 unsigned HOST_WIDE_INT reg_size
;
1771 if (FP_REGNO_P (regno
))
1772 reg_size
= (VECTOR_MEM_VSX_P (mode
)
1773 ? UNITS_PER_VSX_WORD
1774 : UNITS_PER_FP_WORD
);
1776 else if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1777 reg_size
= UNITS_PER_SPE_WORD
;
1779 else if (ALTIVEC_REGNO_P (regno
))
1780 reg_size
= UNITS_PER_ALTIVEC_WORD
;
1782 /* The value returned for SCmode in the E500 double case is 2 for
1783 ABI compatibility; storing an SCmode value in a single register
1784 would require function_arg and rs6000_spe_function_arg to handle
1785 SCmode so as to pass the value correctly in a pair of
1787 else if (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
) && mode
!= SCmode
1788 && !DECIMAL_FLOAT_MODE_P (mode
))
1789 reg_size
= UNITS_PER_FP_WORD
;
1792 reg_size
= UNITS_PER_WORD
;
1794 return (GET_MODE_SIZE (mode
) + reg_size
- 1) / reg_size
;
1797 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1800 rs6000_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
1802 int last_regno
= regno
+ rs6000_hard_regno_nregs
[mode
][regno
] - 1;
1804 /* VSX registers that overlap the FPR registers are larger than for non-VSX
1805 implementations. Don't allow an item to be split between a FP register
1806 and an Altivec register. */
1807 if (VECTOR_MEM_VSX_P (mode
))
1809 if (FP_REGNO_P (regno
))
1810 return FP_REGNO_P (last_regno
);
1812 if (ALTIVEC_REGNO_P (regno
))
1813 return ALTIVEC_REGNO_P (last_regno
);
1816 /* The GPRs can hold any mode, but values bigger than one register
1817 cannot go past R31. */
1818 if (INT_REGNO_P (regno
))
1819 return INT_REGNO_P (last_regno
);
1821 /* The float registers (except for VSX vector modes) can only hold floating
1822 modes and DImode. This excludes the 32-bit decimal float mode for
1824 if (FP_REGNO_P (regno
))
1826 if (SCALAR_FLOAT_MODE_P (mode
)
1827 && (mode
!= TDmode
|| (regno
% 2) == 0)
1828 && FP_REGNO_P (last_regno
))
1831 if (GET_MODE_CLASS (mode
) == MODE_INT
1832 && GET_MODE_SIZE (mode
) == UNITS_PER_FP_WORD
)
1835 if (PAIRED_SIMD_REGNO_P (regno
) && TARGET_PAIRED_FLOAT
1836 && PAIRED_VECTOR_MODE (mode
))
1842 /* The CR register can only hold CC modes. */
1843 if (CR_REGNO_P (regno
))
1844 return GET_MODE_CLASS (mode
) == MODE_CC
;
1846 if (CA_REGNO_P (regno
))
1847 return mode
== BImode
;
1849 /* AltiVec only in AldyVec registers. */
1850 if (ALTIVEC_REGNO_P (regno
))
1851 return VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
);
1853 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1854 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1857 /* We cannot put TImode anywhere except general register and it must be able
1858 to fit within the register set. In the future, allow TImode in the
1859 Altivec or VSX registers. */
1861 return GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
;
1864 /* Print interesting facts about registers. */
1866 rs6000_debug_reg_print (int first_regno
, int last_regno
, const char *reg_name
)
1870 for (r
= first_regno
; r
<= last_regno
; ++r
)
1872 const char *comma
= "";
1875 if (first_regno
== last_regno
)
1876 fprintf (stderr
, "%s:\t", reg_name
);
1878 fprintf (stderr
, "%s%d:\t", reg_name
, r
- first_regno
);
1881 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1882 if (rs6000_hard_regno_mode_ok_p
[m
][r
] && rs6000_hard_regno_nregs
[m
][r
])
1886 fprintf (stderr
, ",\n\t");
1891 if (rs6000_hard_regno_nregs
[m
][r
] > 1)
1892 len
+= fprintf (stderr
, "%s%s/%d", comma
, GET_MODE_NAME (m
),
1893 rs6000_hard_regno_nregs
[m
][r
]);
1895 len
+= fprintf (stderr
, "%s%s", comma
, GET_MODE_NAME (m
));
1900 if (call_used_regs
[r
])
1904 fprintf (stderr
, ",\n\t");
1909 len
+= fprintf (stderr
, "%s%s", comma
, "call-used");
1917 fprintf (stderr
, ",\n\t");
1922 len
+= fprintf (stderr
, "%s%s", comma
, "fixed");
1928 fprintf (stderr
, ",\n\t");
1932 fprintf (stderr
, "%sregno = %d\n", comma
, r
);
1936 #define DEBUG_FMT_D "%-32s= %d\n"
1937 #define DEBUG_FMT_X "%-32s= 0x%x\n"
1938 #define DEBUG_FMT_S "%-32s= %s\n"
1940 /* Print various interesting information with -mdebug=reg. */
1942 rs6000_debug_reg_global (void)
1944 static const char *const tf
[2] = { "false", "true" };
1945 const char *nl
= (const char *)0;
1947 char costly_num
[20];
1949 const char *costly_str
;
1950 const char *nop_str
;
1951 const char *trace_str
;
1952 const char *abi_str
;
1953 const char *cmodel_str
;
1955 /* Map enum rs6000_vector to string. */
1956 static const char *rs6000_debug_vector_unit
[] = {
1965 fprintf (stderr
, "Register information: (last virtual reg = %d)\n",
1966 LAST_VIRTUAL_REGISTER
);
1967 rs6000_debug_reg_print (0, 31, "gr");
1968 rs6000_debug_reg_print (32, 63, "fp");
1969 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO
,
1972 rs6000_debug_reg_print (LR_REGNO
, LR_REGNO
, "lr");
1973 rs6000_debug_reg_print (CTR_REGNO
, CTR_REGNO
, "ctr");
1974 rs6000_debug_reg_print (CR0_REGNO
, CR7_REGNO
, "cr");
1975 rs6000_debug_reg_print (MQ_REGNO
, MQ_REGNO
, "mq");
1976 rs6000_debug_reg_print (CA_REGNO
, CA_REGNO
, "ca");
1977 rs6000_debug_reg_print (VRSAVE_REGNO
, VRSAVE_REGNO
, "vrsave");
1978 rs6000_debug_reg_print (VSCR_REGNO
, VSCR_REGNO
, "vscr");
1979 rs6000_debug_reg_print (SPE_ACC_REGNO
, SPE_ACC_REGNO
, "spe_a");
1980 rs6000_debug_reg_print (SPEFSCR_REGNO
, SPEFSCR_REGNO
, "spe_f");
1984 "d reg_class = %s\n"
1985 "f reg_class = %s\n"
1986 "v reg_class = %s\n"
1987 "wa reg_class = %s\n"
1988 "wd reg_class = %s\n"
1989 "wf reg_class = %s\n"
1990 "ws reg_class = %s\n\n",
1991 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_d
]],
1992 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_f
]],
1993 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_v
]],
1994 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wa
]],
1995 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wd
]],
1996 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wf
]],
1997 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ws
]]);
1999 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2000 if (rs6000_vector_unit
[m
] || rs6000_vector_mem
[m
])
2003 fprintf (stderr
, "Vector mode: %-5s arithmetic: %-8s move: %-8s\n",
2005 rs6000_debug_vector_unit
[ rs6000_vector_unit
[m
] ],
2006 rs6000_debug_vector_unit
[ rs6000_vector_mem
[m
] ]);
2012 if (rs6000_recip_control
)
2014 fprintf (stderr
, "\nReciprocal mask = 0x%x\n", rs6000_recip_control
);
2016 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2017 if (rs6000_recip_bits
[m
])
2020 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2022 (RS6000_RECIP_AUTO_RE_P (m
)
2024 : (RS6000_RECIP_HAVE_RE_P (m
) ? "have" : "none")),
2025 (RS6000_RECIP_AUTO_RSQRTE_P (m
)
2027 : (RS6000_RECIP_HAVE_RSQRTE_P (m
) ? "have" : "none")));
2030 fputs ("\n", stderr
);
2033 if (rs6000_cpu_index
>= 0)
2034 fprintf (stderr
, DEBUG_FMT_S
, "cpu",
2035 processor_target_table
[rs6000_cpu_index
].name
);
2037 if (rs6000_tune_index
>= 0)
2038 fprintf (stderr
, DEBUG_FMT_S
, "tune",
2039 processor_target_table
[rs6000_tune_index
].name
);
2041 switch (rs6000_sched_costly_dep
)
2043 case max_dep_latency
:
2044 costly_str
= "max_dep_latency";
2048 costly_str
= "no_dep_costly";
2051 case all_deps_costly
:
2052 costly_str
= "all_deps_costly";
2055 case true_store_to_load_dep_costly
:
2056 costly_str
= "true_store_to_load_dep_costly";
2059 case store_to_load_dep_costly
:
2060 costly_str
= "store_to_load_dep_costly";
2064 costly_str
= costly_num
;
2065 sprintf (costly_num
, "%d", (int)rs6000_sched_costly_dep
);
2069 fprintf (stderr
, DEBUG_FMT_S
, "sched_costly_dep", costly_str
);
2071 switch (rs6000_sched_insert_nops
)
2073 case sched_finish_regroup_exact
:
2074 nop_str
= "sched_finish_regroup_exact";
2077 case sched_finish_pad_groups
:
2078 nop_str
= "sched_finish_pad_groups";
2081 case sched_finish_none
:
2082 nop_str
= "sched_finish_none";
2087 sprintf (nop_num
, "%d", (int)rs6000_sched_insert_nops
);
2091 fprintf (stderr
, DEBUG_FMT_S
, "sched_insert_nops", nop_str
);
2093 switch (rs6000_sdata
)
2100 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "data");
2104 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "sysv");
2108 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "eabi");
2113 switch (rs6000_traceback
)
2115 case traceback_default
: trace_str
= "default"; break;
2116 case traceback_none
: trace_str
= "none"; break;
2117 case traceback_part
: trace_str
= "part"; break;
2118 case traceback_full
: trace_str
= "full"; break;
2119 default: trace_str
= "unknown"; break;
2122 fprintf (stderr
, DEBUG_FMT_S
, "traceback", trace_str
);
2124 switch (rs6000_current_cmodel
)
2126 case CMODEL_SMALL
: cmodel_str
= "small"; break;
2127 case CMODEL_MEDIUM
: cmodel_str
= "medium"; break;
2128 case CMODEL_LARGE
: cmodel_str
= "large"; break;
2129 default: cmodel_str
= "unknown"; break;
2132 fprintf (stderr
, DEBUG_FMT_S
, "cmodel", cmodel_str
);
2134 switch (rs6000_current_abi
)
2136 case ABI_NONE
: abi_str
= "none"; break;
2137 case ABI_AIX
: abi_str
= "aix"; break;
2138 case ABI_V4
: abi_str
= "V4"; break;
2139 case ABI_DARWIN
: abi_str
= "darwin"; break;
2140 default: abi_str
= "unknown"; break;
2143 fprintf (stderr
, DEBUG_FMT_S
, "abi", abi_str
);
2145 if (rs6000_altivec_abi
)
2146 fprintf (stderr
, DEBUG_FMT_S
, "altivec_abi", "true");
2149 fprintf (stderr
, DEBUG_FMT_S
, "spe_abi", "true");
2151 if (rs6000_darwin64_abi
)
2152 fprintf (stderr
, DEBUG_FMT_S
, "darwin64_abi", "true");
2154 if (rs6000_float_gprs
)
2155 fprintf (stderr
, DEBUG_FMT_S
, "float_gprs", "true");
2157 fprintf (stderr
, DEBUG_FMT_S
, "always_hint", tf
[!!rs6000_always_hint
]);
2158 fprintf (stderr
, DEBUG_FMT_S
, "align_branch",
2159 tf
[!!rs6000_align_branch_targets
]);
2160 fprintf (stderr
, DEBUG_FMT_D
, "tls_size", rs6000_tls_size
);
2161 fprintf (stderr
, DEBUG_FMT_D
, "long_double_size",
2162 rs6000_long_double_type_size
);
2163 fprintf (stderr
, DEBUG_FMT_D
, "sched_restricted_insns_priority",
2164 (int)rs6000_sched_restricted_insns_priority
);
2165 fprintf (stderr
, DEBUG_FMT_D
, "Number of standard builtins",
2167 fprintf (stderr
, DEBUG_FMT_D
, "Number of rs6000 builtins",
2168 (int)RS6000_BUILTIN_COUNT
);
2169 fprintf (stderr
, DEBUG_FMT_X
, "Builtin mask", rs6000_builtin_mask
);
2172 /* Initialize the various global tables that are based on register size. */
2174 rs6000_init_hard_regno_mode_ok (bool global_init_p
)
2180 /* Precalculate REGNO_REG_CLASS. */
2181 rs6000_regno_regclass
[0] = GENERAL_REGS
;
2182 for (r
= 1; r
< 32; ++r
)
2183 rs6000_regno_regclass
[r
] = BASE_REGS
;
2185 for (r
= 32; r
< 64; ++r
)
2186 rs6000_regno_regclass
[r
] = FLOAT_REGS
;
2188 for (r
= 64; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2189 rs6000_regno_regclass
[r
] = NO_REGS
;
2191 for (r
= FIRST_ALTIVEC_REGNO
; r
<= LAST_ALTIVEC_REGNO
; ++r
)
2192 rs6000_regno_regclass
[r
] = ALTIVEC_REGS
;
2194 rs6000_regno_regclass
[CR0_REGNO
] = CR0_REGS
;
2195 for (r
= CR1_REGNO
; r
<= CR7_REGNO
; ++r
)
2196 rs6000_regno_regclass
[r
] = CR_REGS
;
2198 rs6000_regno_regclass
[MQ_REGNO
] = MQ_REGS
;
2199 rs6000_regno_regclass
[LR_REGNO
] = LINK_REGS
;
2200 rs6000_regno_regclass
[CTR_REGNO
] = CTR_REGS
;
2201 rs6000_regno_regclass
[CA_REGNO
] = CA_REGS
;
2202 rs6000_regno_regclass
[VRSAVE_REGNO
] = VRSAVE_REGS
;
2203 rs6000_regno_regclass
[VSCR_REGNO
] = VRSAVE_REGS
;
2204 rs6000_regno_regclass
[SPE_ACC_REGNO
] = SPE_ACC_REGS
;
2205 rs6000_regno_regclass
[SPEFSCR_REGNO
] = SPEFSCR_REGS
;
2206 rs6000_regno_regclass
[ARG_POINTER_REGNUM
] = BASE_REGS
;
2207 rs6000_regno_regclass
[FRAME_POINTER_REGNUM
] = BASE_REGS
;
2209 /* Precalculate vector information, this must be set up before the
2210 rs6000_hard_regno_nregs_internal below. */
2211 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2213 rs6000_vector_unit
[m
] = rs6000_vector_mem
[m
] = VECTOR_NONE
;
2214 rs6000_vector_reload
[m
][0] = CODE_FOR_nothing
;
2215 rs6000_vector_reload
[m
][1] = CODE_FOR_nothing
;
2218 for (c
= 0; c
< (int)(int)RS6000_CONSTRAINT_MAX
; c
++)
2219 rs6000_constraints
[c
] = NO_REGS
;
2221 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
2222 believes it can use native alignment or still uses 128-bit alignment. */
2223 if (TARGET_VSX
&& !TARGET_VSX_ALIGN_128
)
2234 /* V2DF mode, VSX only. */
2237 rs6000_vector_unit
[V2DFmode
] = VECTOR_VSX
;
2238 rs6000_vector_mem
[V2DFmode
] = VECTOR_VSX
;
2239 rs6000_vector_align
[V2DFmode
] = align64
;
2242 /* V4SF mode, either VSX or Altivec. */
2245 rs6000_vector_unit
[V4SFmode
] = VECTOR_VSX
;
2246 rs6000_vector_mem
[V4SFmode
] = VECTOR_VSX
;
2247 rs6000_vector_align
[V4SFmode
] = align32
;
2249 else if (TARGET_ALTIVEC
)
2251 rs6000_vector_unit
[V4SFmode
] = VECTOR_ALTIVEC
;
2252 rs6000_vector_mem
[V4SFmode
] = VECTOR_ALTIVEC
;
2253 rs6000_vector_align
[V4SFmode
] = align32
;
2256 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
2260 rs6000_vector_unit
[V4SImode
] = VECTOR_ALTIVEC
;
2261 rs6000_vector_unit
[V8HImode
] = VECTOR_ALTIVEC
;
2262 rs6000_vector_unit
[V16QImode
] = VECTOR_ALTIVEC
;
2263 rs6000_vector_align
[V4SImode
] = align32
;
2264 rs6000_vector_align
[V8HImode
] = align32
;
2265 rs6000_vector_align
[V16QImode
] = align32
;
2269 rs6000_vector_mem
[V4SImode
] = VECTOR_VSX
;
2270 rs6000_vector_mem
[V8HImode
] = VECTOR_VSX
;
2271 rs6000_vector_mem
[V16QImode
] = VECTOR_VSX
;
2275 rs6000_vector_mem
[V4SImode
] = VECTOR_ALTIVEC
;
2276 rs6000_vector_mem
[V8HImode
] = VECTOR_ALTIVEC
;
2277 rs6000_vector_mem
[V16QImode
] = VECTOR_ALTIVEC
;
2281 /* V2DImode, only allow under VSX, which can do V2DI insert/splat/extract.
2282 Altivec doesn't have 64-bit support. */
2285 rs6000_vector_mem
[V2DImode
] = VECTOR_VSX
;
2286 rs6000_vector_unit
[V2DImode
] = VECTOR_NONE
;
2287 rs6000_vector_align
[V2DImode
] = align64
;
2290 /* DFmode, see if we want to use the VSX unit. */
2291 if (TARGET_VSX
&& TARGET_VSX_SCALAR_DOUBLE
)
2293 rs6000_vector_unit
[DFmode
] = VECTOR_VSX
;
2294 rs6000_vector_mem
[DFmode
]
2295 = (TARGET_VSX_SCALAR_MEMORY
? VECTOR_VSX
: VECTOR_NONE
);
2296 rs6000_vector_align
[DFmode
] = align64
;
2299 /* TODO add SPE and paired floating point vector support. */
2301 /* Register class constaints for the constraints that depend on compile
2303 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
2304 rs6000_constraints
[RS6000_CONSTRAINT_f
] = FLOAT_REGS
;
2306 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
2307 rs6000_constraints
[RS6000_CONSTRAINT_d
] = FLOAT_REGS
;
2311 /* At present, we just use VSX_REGS, but we have different constraints
2312 based on the use, in case we want to fine tune the default register
2313 class used. wa = any VSX register, wf = register class to use for
2314 V4SF, wd = register class to use for V2DF, and ws = register classs to
2315 use for DF scalars. */
2316 rs6000_constraints
[RS6000_CONSTRAINT_wa
] = VSX_REGS
;
2317 rs6000_constraints
[RS6000_CONSTRAINT_wf
] = VSX_REGS
;
2318 rs6000_constraints
[RS6000_CONSTRAINT_wd
] = VSX_REGS
;
2319 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = (TARGET_VSX_SCALAR_MEMORY
2325 rs6000_constraints
[RS6000_CONSTRAINT_v
] = ALTIVEC_REGS
;
2327 /* Set up the reload helper functions. */
2328 if (TARGET_VSX
|| TARGET_ALTIVEC
)
2332 rs6000_vector_reload
[V16QImode
][0] = CODE_FOR_reload_v16qi_di_store
;
2333 rs6000_vector_reload
[V16QImode
][1] = CODE_FOR_reload_v16qi_di_load
;
2334 rs6000_vector_reload
[V8HImode
][0] = CODE_FOR_reload_v8hi_di_store
;
2335 rs6000_vector_reload
[V8HImode
][1] = CODE_FOR_reload_v8hi_di_load
;
2336 rs6000_vector_reload
[V4SImode
][0] = CODE_FOR_reload_v4si_di_store
;
2337 rs6000_vector_reload
[V4SImode
][1] = CODE_FOR_reload_v4si_di_load
;
2338 rs6000_vector_reload
[V2DImode
][0] = CODE_FOR_reload_v2di_di_store
;
2339 rs6000_vector_reload
[V2DImode
][1] = CODE_FOR_reload_v2di_di_load
;
2340 rs6000_vector_reload
[V4SFmode
][0] = CODE_FOR_reload_v4sf_di_store
;
2341 rs6000_vector_reload
[V4SFmode
][1] = CODE_FOR_reload_v4sf_di_load
;
2342 rs6000_vector_reload
[V2DFmode
][0] = CODE_FOR_reload_v2df_di_store
;
2343 rs6000_vector_reload
[V2DFmode
][1] = CODE_FOR_reload_v2df_di_load
;
2344 if (TARGET_VSX
&& TARGET_VSX_SCALAR_MEMORY
)
2346 rs6000_vector_reload
[DFmode
][0] = CODE_FOR_reload_df_di_store
;
2347 rs6000_vector_reload
[DFmode
][1] = CODE_FOR_reload_df_di_load
;
2352 rs6000_vector_reload
[V16QImode
][0] = CODE_FOR_reload_v16qi_si_store
;
2353 rs6000_vector_reload
[V16QImode
][1] = CODE_FOR_reload_v16qi_si_load
;
2354 rs6000_vector_reload
[V8HImode
][0] = CODE_FOR_reload_v8hi_si_store
;
2355 rs6000_vector_reload
[V8HImode
][1] = CODE_FOR_reload_v8hi_si_load
;
2356 rs6000_vector_reload
[V4SImode
][0] = CODE_FOR_reload_v4si_si_store
;
2357 rs6000_vector_reload
[V4SImode
][1] = CODE_FOR_reload_v4si_si_load
;
2358 rs6000_vector_reload
[V2DImode
][0] = CODE_FOR_reload_v2di_si_store
;
2359 rs6000_vector_reload
[V2DImode
][1] = CODE_FOR_reload_v2di_si_load
;
2360 rs6000_vector_reload
[V4SFmode
][0] = CODE_FOR_reload_v4sf_si_store
;
2361 rs6000_vector_reload
[V4SFmode
][1] = CODE_FOR_reload_v4sf_si_load
;
2362 rs6000_vector_reload
[V2DFmode
][0] = CODE_FOR_reload_v2df_si_store
;
2363 rs6000_vector_reload
[V2DFmode
][1] = CODE_FOR_reload_v2df_si_load
;
2364 if (TARGET_VSX
&& TARGET_VSX_SCALAR_MEMORY
)
2366 rs6000_vector_reload
[DFmode
][0] = CODE_FOR_reload_df_si_store
;
2367 rs6000_vector_reload
[DFmode
][1] = CODE_FOR_reload_df_si_load
;
2372 /* Precalculate HARD_REGNO_NREGS. */
2373 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2374 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2375 rs6000_hard_regno_nregs
[m
][r
]
2376 = rs6000_hard_regno_nregs_internal (r
, (enum machine_mode
)m
);
2378 /* Precalculate HARD_REGNO_MODE_OK. */
2379 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2380 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2381 if (rs6000_hard_regno_mode_ok (r
, (enum machine_mode
)m
))
2382 rs6000_hard_regno_mode_ok_p
[m
][r
] = true;
2384 /* Precalculate CLASS_MAX_NREGS sizes. */
2385 for (c
= 0; c
< LIM_REG_CLASSES
; ++c
)
2389 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
))
2390 reg_size
= UNITS_PER_VSX_WORD
;
2392 else if (c
== ALTIVEC_REGS
)
2393 reg_size
= UNITS_PER_ALTIVEC_WORD
;
2395 else if (c
== FLOAT_REGS
)
2396 reg_size
= UNITS_PER_FP_WORD
;
2399 reg_size
= UNITS_PER_WORD
;
2401 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2402 rs6000_class_max_nregs
[m
][c
]
2403 = (GET_MODE_SIZE (m
) + reg_size
- 1) / reg_size
;
2406 if (TARGET_E500_DOUBLE
)
2407 rs6000_class_max_nregs
[DFmode
][GENERAL_REGS
] = 1;
2409 /* Calculate which modes to automatically generate code to use a the
2410 reciprocal divide and square root instructions. In the future, possibly
2411 automatically generate the instructions even if the user did not specify
2412 -mrecip. The older machines double precision reciprocal sqrt estimate is
2413 not accurate enough. */
2414 memset (rs6000_recip_bits
, 0, sizeof (rs6000_recip_bits
));
2416 rs6000_recip_bits
[SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2418 rs6000_recip_bits
[DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2419 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
2420 rs6000_recip_bits
[V4SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2421 if (VECTOR_UNIT_VSX_P (V2DFmode
))
2422 rs6000_recip_bits
[V2DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2424 if (TARGET_FRSQRTES
)
2425 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2427 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2428 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
2429 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2430 if (VECTOR_UNIT_VSX_P (V2DFmode
))
2431 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2433 if (rs6000_recip_control
)
2435 if (!flag_finite_math_only
)
2436 warning (0, "-mrecip requires -ffinite-math or -ffast-math");
2437 if (flag_trapping_math
)
2438 warning (0, "-mrecip requires -fno-trapping-math or -ffast-math");
2439 if (!flag_reciprocal_math
)
2440 warning (0, "-mrecip requires -freciprocal-math or -ffast-math");
2441 if (flag_finite_math_only
&& !flag_trapping_math
&& flag_reciprocal_math
)
2443 if (RS6000_RECIP_HAVE_RE_P (SFmode
)
2444 && (rs6000_recip_control
& RECIP_SF_DIV
) != 0)
2445 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2447 if (RS6000_RECIP_HAVE_RE_P (DFmode
)
2448 && (rs6000_recip_control
& RECIP_DF_DIV
) != 0)
2449 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2451 if (RS6000_RECIP_HAVE_RE_P (V4SFmode
)
2452 && (rs6000_recip_control
& RECIP_V4SF_DIV
) != 0)
2453 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2455 if (RS6000_RECIP_HAVE_RE_P (V2DFmode
)
2456 && (rs6000_recip_control
& RECIP_V2DF_DIV
) != 0)
2457 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2459 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode
)
2460 && (rs6000_recip_control
& RECIP_SF_RSQRT
) != 0)
2461 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2463 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode
)
2464 && (rs6000_recip_control
& RECIP_DF_RSQRT
) != 0)
2465 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2467 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode
)
2468 && (rs6000_recip_control
& RECIP_V4SF_RSQRT
) != 0)
2469 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2471 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode
)
2472 && (rs6000_recip_control
& RECIP_V2DF_RSQRT
) != 0)
2473 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2477 if (global_init_p
|| TARGET_DEBUG_TARGET
)
2479 if (TARGET_DEBUG_REG
)
2480 rs6000_debug_reg_global ();
2482 if (TARGET_DEBUG_COST
|| TARGET_DEBUG_REG
)
2484 "SImode variable mult cost = %d\n"
2485 "SImode constant mult cost = %d\n"
2486 "SImode short constant mult cost = %d\n"
2487 "DImode multipliciation cost = %d\n"
2488 "SImode division cost = %d\n"
2489 "DImode division cost = %d\n"
2490 "Simple fp operation cost = %d\n"
2491 "DFmode multiplication cost = %d\n"
2492 "SFmode division cost = %d\n"
2493 "DFmode division cost = %d\n"
2494 "cache line size = %d\n"
2495 "l1 cache size = %d\n"
2496 "l2 cache size = %d\n"
2497 "simultaneous prefetches = %d\n"
2500 rs6000_cost
->mulsi_const
,
2501 rs6000_cost
->mulsi_const9
,
2509 rs6000_cost
->cache_line_size
,
2510 rs6000_cost
->l1_cache_size
,
2511 rs6000_cost
->l2_cache_size
,
2512 rs6000_cost
->simultaneous_prefetches
);
2517 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
2520 darwin_rs6000_override_options (void)
2522 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
2524 rs6000_altivec_abi
= 1;
2525 TARGET_ALTIVEC_VRSAVE
= 1;
2526 rs6000_current_abi
= ABI_DARWIN
;
2528 if (DEFAULT_ABI
== ABI_DARWIN
2530 darwin_one_byte_bool
= 1;
2532 if (TARGET_64BIT
&& ! TARGET_POWERPC64
)
2534 target_flags
|= MASK_POWERPC64
;
2535 warning (0, "-m64 requires PowerPC64 architecture, enabling");
2539 rs6000_default_long_calls
= 1;
2540 target_flags
|= MASK_SOFT_FLOAT
;
2543 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
2545 if (!flag_mkernel
&& !flag_apple_kext
2547 && ! (target_flags_explicit
& MASK_ALTIVEC
))
2548 target_flags
|= MASK_ALTIVEC
;
2550 /* Unless the user (not the configurer) has explicitly overridden
2551 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
2552 G4 unless targetting the kernel. */
2555 && strverscmp (darwin_macosx_version_min
, "10.5") >= 0
2556 && ! (target_flags_explicit
& MASK_ALTIVEC
)
2557 && ! global_options_set
.x_rs6000_cpu_index
)
2559 target_flags
|= MASK_ALTIVEC
;
2564 /* If not otherwise specified by a target, make 'long double' equivalent to
2567 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
2568 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
2571 /* Return the builtin mask of the various options used that could affect which
2572 builtins were used. In the past we used target_flags, but we've run out of
2573 bits, and some options like SPE and PAIRED are no longer in
2577 rs6000_builtin_mask_calculate (void)
2579 return (((TARGET_ALTIVEC
) ? RS6000_BTM_ALTIVEC
: 0)
2580 | ((TARGET_VSX
) ? RS6000_BTM_VSX
: 0)
2581 | ((TARGET_SPE
) ? RS6000_BTM_SPE
: 0)
2582 | ((TARGET_PAIRED_FLOAT
) ? RS6000_BTM_PAIRED
: 0)
2583 | ((TARGET_FRE
) ? RS6000_BTM_FRE
: 0)
2584 | ((TARGET_FRES
) ? RS6000_BTM_FRES
: 0)
2585 | ((TARGET_FRSQRTE
) ? RS6000_BTM_FRSQRTE
: 0)
2586 | ((TARGET_FRSQRTES
) ? RS6000_BTM_FRSQRTES
: 0)
2587 | ((TARGET_POPCNTD
) ? RS6000_BTM_POPCNTD
: 0)
2588 | ((TARGET_POWERPC
) ? RS6000_BTM_POWERPC
: 0)
2589 | ((rs6000_cpu
== PROCESSOR_CELL
) ? RS6000_BTM_CELL
: 0));
2592 /* Override command line options. Mostly we process the processor type and
2593 sometimes adjust other TARGET_ options. */
2596 rs6000_option_override_internal (bool global_init_p
)
2599 bool have_cpu
= false;
2600 const char *default_cpu
= OPTION_TARGET_CPU_DEFAULT
;
2604 struct cl_target_option
*main_target_opt
2605 = ((global_init_p
|| target_option_default_node
== NULL
)
2606 ? NULL
: TREE_TARGET_OPTION (target_option_default_node
));
2608 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
2609 library functions, so warn about it. The flag may be useful for
2610 performance studies from time to time though, so don't disable it
2612 if (global_options_set
.x_rs6000_alignment_flags
2613 && rs6000_alignment_flags
== MASK_ALIGN_POWER
2614 && DEFAULT_ABI
== ABI_DARWIN
2616 warning (0, "-malign-power is not supported for 64-bit Darwin;"
2617 " it is incompatible with the installed C and C++ libraries");
2619 if (global_options_set
.x_rs6000_spe_abi
2622 error ("not configured for SPE ABI");
2624 /* Numerous experiment shows that IRA based loop pressure
2625 calculation works better for RTL loop invariant motion on targets
2626 with enough (>= 32) registers. It is an expensive optimization.
2627 So it is on only for peak performance. */
2628 if (optimize
>= 3 && global_init_p
)
2629 flag_ira_loop_pressure
= 1;
2631 /* Set the pointer size. */
2634 rs6000_pmode
= (int)DImode
;
2635 rs6000_pointer_size
= 64;
2639 rs6000_pmode
= (int)SImode
;
2640 rs6000_pointer_size
= 32;
2643 set_masks
= POWER_MASKS
| POWERPC_MASKS
| MASK_SOFT_FLOAT
;
2644 #ifdef OS_MISSING_POWERPC64
2645 if (OS_MISSING_POWERPC64
)
2646 set_masks
&= ~MASK_POWERPC64
;
2648 #ifdef OS_MISSING_ALTIVEC
2649 if (OS_MISSING_ALTIVEC
)
2650 set_masks
&= ~MASK_ALTIVEC
;
2653 /* Don't override by the processor default if given explicitly. */
2654 set_masks
&= ~target_flags_explicit
;
2656 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
2657 the cpu in a target attribute or pragma, but did not specify a tuning
2658 option, use the cpu for the tuning option rather than the option specified
2659 with -mtune on the command line. */
2660 if (rs6000_cpu_index
>= 0)
2662 cpu_index
= rs6000_cpu_index
;
2665 else if (main_target_opt
!= NULL
&& main_target_opt
->x_rs6000_cpu_index
>= 0)
2667 rs6000_cpu_index
= cpu_index
= main_target_opt
->x_rs6000_cpu_index
;
2673 default_cpu
= (TARGET_POWERPC64
? "powerpc64" : "powerpc");
2675 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (default_cpu
);
2678 gcc_assert (cpu_index
>= 0);
2680 target_flags
&= ~set_masks
;
2681 target_flags
|= (processor_target_table
[cpu_index
].target_enable
2684 if (rs6000_tune_index
>= 0)
2685 tune_index
= rs6000_tune_index
;
2687 rs6000_tune_index
= tune_index
= cpu_index
;
2691 enum processor_type tune_proc
2692 = (TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
);
2695 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
2696 if (processor_target_table
[i
].processor
== tune_proc
)
2698 rs6000_tune_index
= tune_index
= i
;
2703 gcc_assert (tune_index
>= 0);
2704 rs6000_cpu
= processor_target_table
[tune_index
].processor
;
2706 if (rs6000_cpu
== PROCESSOR_PPCE300C2
|| rs6000_cpu
== PROCESSOR_PPCE300C3
2707 || rs6000_cpu
== PROCESSOR_PPCE500MC
|| rs6000_cpu
== PROCESSOR_PPCE500MC64
)
2710 error ("AltiVec not supported in this target");
2712 error ("SPE not supported in this target");
2715 /* Disable Cell microcode if we are optimizing for the Cell
2716 and not optimizing for size. */
2717 if (rs6000_gen_cell_microcode
== -1)
2718 rs6000_gen_cell_microcode
= !(rs6000_cpu
== PROCESSOR_CELL
2721 /* If we are optimizing big endian systems for space and it's OK to
2722 use instructions that would be microcoded on the Cell, use the
2723 load/store multiple and string instructions. */
2724 if (BYTES_BIG_ENDIAN
&& optimize_size
&& rs6000_gen_cell_microcode
)
2725 target_flags
|= ~target_flags_explicit
& (MASK_MULTIPLE
| MASK_STRING
);
2727 /* Don't allow -mmultiple or -mstring on little endian systems
2728 unless the cpu is a 750, because the hardware doesn't support the
2729 instructions used in little endian mode, and causes an alignment
2730 trap. The 750 does not cause an alignment trap (except when the
2731 target is unaligned). */
2733 if (!BYTES_BIG_ENDIAN
&& rs6000_cpu
!= PROCESSOR_PPC750
)
2735 if (TARGET_MULTIPLE
)
2737 target_flags
&= ~MASK_MULTIPLE
;
2738 if ((target_flags_explicit
& MASK_MULTIPLE
) != 0)
2739 warning (0, "-mmultiple is not supported on little endian systems");
2744 target_flags
&= ~MASK_STRING
;
2745 if ((target_flags_explicit
& MASK_STRING
) != 0)
2746 warning (0, "-mstring is not supported on little endian systems");
2750 /* Add some warnings for VSX. */
2753 const char *msg
= NULL
;
2754 if (!TARGET_HARD_FLOAT
|| !TARGET_FPRS
2755 || !TARGET_SINGLE_FLOAT
|| !TARGET_DOUBLE_FLOAT
)
2757 if (target_flags_explicit
& MASK_VSX
)
2758 msg
= N_("-mvsx requires hardware floating point");
2760 target_flags
&= ~ MASK_VSX
;
2762 else if (TARGET_PAIRED_FLOAT
)
2763 msg
= N_("-mvsx and -mpaired are incompatible");
2764 /* The hardware will allow VSX and little endian, but until we make sure
2765 things like vector select, etc. work don't allow VSX on little endian
2766 systems at this point. */
2767 else if (!BYTES_BIG_ENDIAN
)
2768 msg
= N_("-mvsx used with little endian code");
2769 else if (TARGET_AVOID_XFORM
> 0)
2770 msg
= N_("-mvsx needs indexed addressing");
2771 else if (!TARGET_ALTIVEC
&& (target_flags_explicit
& MASK_ALTIVEC
))
2773 if (target_flags_explicit
& MASK_VSX
)
2774 msg
= N_("-mvsx and -mno-altivec are incompatible");
2776 msg
= N_("-mno-altivec disables vsx");
2782 target_flags
&= ~ MASK_VSX
;
2783 target_flags_explicit
|= MASK_VSX
;
2787 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
2788 unless the user explicitly used the -mno-<option> to disable the code. */
2790 target_flags
|= (ISA_2_6_MASKS_SERVER
& ~target_flags_explicit
);
2791 else if (TARGET_POPCNTD
)
2792 target_flags
|= (ISA_2_6_MASKS_EMBEDDED
& ~target_flags_explicit
);
2793 else if (TARGET_DFP
)
2794 target_flags
|= (ISA_2_5_MASKS_SERVER
& ~target_flags_explicit
);
2795 else if (TARGET_CMPB
)
2796 target_flags
|= (ISA_2_5_MASKS_EMBEDDED
& ~target_flags_explicit
);
2797 else if (TARGET_FPRND
)
2798 target_flags
|= (ISA_2_4_MASKS
& ~target_flags_explicit
);
2799 else if (TARGET_POPCNTB
)
2800 target_flags
|= (ISA_2_2_MASKS
& ~target_flags_explicit
);
2801 else if (TARGET_ALTIVEC
)
2802 target_flags
|= (MASK_PPC_GFXOPT
& ~target_flags_explicit
);
2804 /* E500mc does "better" if we inline more aggressively. Respect the
2805 user's opinion, though. */
2806 if (rs6000_block_move_inline_limit
== 0
2807 && (rs6000_cpu
== PROCESSOR_PPCE500MC
2808 || rs6000_cpu
== PROCESSOR_PPCE500MC64
))
2809 rs6000_block_move_inline_limit
= 128;
2811 /* store_one_arg depends on expand_block_move to handle at least the
2812 size of reg_parm_stack_space. */
2813 if (rs6000_block_move_inline_limit
< (TARGET_POWERPC64
? 64 : 32))
2814 rs6000_block_move_inline_limit
= (TARGET_POWERPC64
? 64 : 32);
2818 /* If the appropriate debug option is enabled, replace the target hooks
2819 with debug versions that call the real version and then prints
2820 debugging information. */
2821 if (TARGET_DEBUG_COST
)
2823 targetm
.rtx_costs
= rs6000_debug_rtx_costs
;
2824 targetm
.address_cost
= rs6000_debug_address_cost
;
2825 targetm
.sched
.adjust_cost
= rs6000_debug_adjust_cost
;
2828 if (TARGET_DEBUG_ADDR
)
2830 targetm
.legitimate_address_p
= rs6000_debug_legitimate_address_p
;
2831 targetm
.legitimize_address
= rs6000_debug_legitimize_address
;
2832 rs6000_secondary_reload_class_ptr
2833 = rs6000_debug_secondary_reload_class
;
2834 rs6000_secondary_memory_needed_ptr
2835 = rs6000_debug_secondary_memory_needed
;
2836 rs6000_cannot_change_mode_class_ptr
2837 = rs6000_debug_cannot_change_mode_class
;
2838 rs6000_preferred_reload_class_ptr
2839 = rs6000_debug_preferred_reload_class
;
2840 rs6000_legitimize_reload_address_ptr
2841 = rs6000_debug_legitimize_reload_address
;
2842 rs6000_mode_dependent_address_ptr
2843 = rs6000_debug_mode_dependent_address
;
2846 if (rs6000_veclibabi_name
)
2848 if (strcmp (rs6000_veclibabi_name
, "mass") == 0)
2849 rs6000_veclib_handler
= rs6000_builtin_vectorized_libmass
;
2852 error ("unknown vectorization library ABI type (%s) for "
2853 "-mveclibabi= switch", rs6000_veclibabi_name
);
2859 if (!global_options_set
.x_rs6000_long_double_type_size
)
2861 if (main_target_opt
!= NULL
2862 && (main_target_opt
->x_rs6000_long_double_type_size
2863 != RS6000_DEFAULT_LONG_DOUBLE_SIZE
))
2864 error ("target attribute or pragma changes long double size");
2866 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
2869 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
2870 if (!global_options_set
.x_rs6000_ieeequad
)
2871 rs6000_ieeequad
= 1;
2874 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
2875 target attribute or pragma which automatically enables both options,
2876 unless the altivec ABI was set. This is set by default for 64-bit, but
2878 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
2879 target_flags
&= ~((MASK_VSX
| MASK_ALTIVEC
) & ~target_flags_explicit
);
2881 /* Enable Altivec ABI for AIX -maltivec. */
2882 if (TARGET_XCOFF
&& (TARGET_ALTIVEC
|| TARGET_VSX
))
2884 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
2885 error ("target attribute or pragma changes AltiVec ABI");
2887 rs6000_altivec_abi
= 1;
2890 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
2891 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
2892 be explicitly overridden in either case. */
2895 if (!global_options_set
.x_rs6000_altivec_abi
2896 && (TARGET_64BIT
|| TARGET_ALTIVEC
|| TARGET_VSX
))
2898 if (main_target_opt
!= NULL
&&
2899 !main_target_opt
->x_rs6000_altivec_abi
)
2900 error ("target attribute or pragma changes AltiVec ABI");
2902 rs6000_altivec_abi
= 1;
2905 /* Enable VRSAVE for AltiVec ABI, unless explicitly overridden. */
2906 if (!global_options_set
.x_TARGET_ALTIVEC_VRSAVE
)
2907 TARGET_ALTIVEC_VRSAVE
= rs6000_altivec_abi
;
2910 /* Set the Darwin64 ABI as default for 64-bit Darwin.
2911 So far, the only darwin64 targets are also MACH-O. */
2913 && DEFAULT_ABI
== ABI_DARWIN
2916 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_darwin64_abi
)
2917 error ("target attribute or pragma changes darwin64 ABI");
2920 rs6000_darwin64_abi
= 1;
2921 /* Default to natural alignment, for better performance. */
2922 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
2926 /* Place FP constants in the constant pool instead of TOC
2927 if section anchors enabled. */
2928 if (flag_section_anchors
)
2929 TARGET_NO_FP_IN_TOC
= 1;
2931 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2932 SUBTARGET_OVERRIDE_OPTIONS
;
2934 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2935 SUBSUBTARGET_OVERRIDE_OPTIONS
;
2937 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
2938 SUB3TARGET_OVERRIDE_OPTIONS
;
2941 if (TARGET_E500
|| rs6000_cpu
== PROCESSOR_PPCE500MC
2942 || rs6000_cpu
== PROCESSOR_PPCE500MC64
)
2944 /* The e500 and e500mc do not have string instructions, and we set
2945 MASK_STRING above when optimizing for size. */
2946 if ((target_flags
& MASK_STRING
) != 0)
2947 target_flags
= target_flags
& ~MASK_STRING
;
2949 else if (global_options_set
.x_rs6000_cpu_index
)
2951 /* For the powerpc-eabispe configuration, we set all these by
2952 default, so let's unset them if we manually set another
2953 CPU that is not the E500. */
2954 if (main_target_opt
!= NULL
2955 && ((main_target_opt
->x_rs6000_spe_abi
!= rs6000_spe_abi
)
2956 || (main_target_opt
->x_rs6000_spe
!= rs6000_spe
)
2957 || (main_target_opt
->x_rs6000_float_gprs
!= rs6000_float_gprs
)))
2958 error ("target attribute or pragma changes SPE ABI");
2961 if (!global_options_set
.x_rs6000_spe_abi
)
2963 if (!global_options_set
.x_rs6000_spe
)
2965 if (!global_options_set
.x_rs6000_float_gprs
)
2966 rs6000_float_gprs
= 0;
2968 if (!(target_flags_explicit
& MASK_ISEL
))
2969 target_flags
&= ~MASK_ISEL
;
2972 /* Detect invalid option combinations with E500. */
2975 rs6000_always_hint
= (rs6000_cpu
!= PROCESSOR_POWER4
2976 && rs6000_cpu
!= PROCESSOR_POWER5
2977 && rs6000_cpu
!= PROCESSOR_POWER6
2978 && rs6000_cpu
!= PROCESSOR_POWER7
2979 && rs6000_cpu
!= PROCESSOR_PPCA2
2980 && rs6000_cpu
!= PROCESSOR_CELL
2981 && rs6000_cpu
!= PROCESSOR_PPC476
);
2982 rs6000_sched_groups
= (rs6000_cpu
== PROCESSOR_POWER4
2983 || rs6000_cpu
== PROCESSOR_POWER5
2984 || rs6000_cpu
== PROCESSOR_POWER7
);
2985 rs6000_align_branch_targets
= (rs6000_cpu
== PROCESSOR_POWER4
2986 || rs6000_cpu
== PROCESSOR_POWER5
2987 || rs6000_cpu
== PROCESSOR_POWER6
2988 || rs6000_cpu
== PROCESSOR_POWER7
2989 || rs6000_cpu
== PROCESSOR_PPCE500MC
2990 || rs6000_cpu
== PROCESSOR_PPCE500MC64
);
2992 /* Allow debug switches to override the above settings. These are set to -1
2993 in rs6000.opt to indicate the user hasn't directly set the switch. */
2994 if (TARGET_ALWAYS_HINT
>= 0)
2995 rs6000_always_hint
= TARGET_ALWAYS_HINT
;
2997 if (TARGET_SCHED_GROUPS
>= 0)
2998 rs6000_sched_groups
= TARGET_SCHED_GROUPS
;
3000 if (TARGET_ALIGN_BRANCH_TARGETS
>= 0)
3001 rs6000_align_branch_targets
= TARGET_ALIGN_BRANCH_TARGETS
;
3003 rs6000_sched_restricted_insns_priority
3004 = (rs6000_sched_groups
? 1 : 0);
3006 /* Handle -msched-costly-dep option. */
3007 rs6000_sched_costly_dep
3008 = (rs6000_sched_groups
? store_to_load_dep_costly
: no_dep_costly
);
3010 if (rs6000_sched_costly_dep_str
)
3012 if (! strcmp (rs6000_sched_costly_dep_str
, "no"))
3013 rs6000_sched_costly_dep
= no_dep_costly
;
3014 else if (! strcmp (rs6000_sched_costly_dep_str
, "all"))
3015 rs6000_sched_costly_dep
= all_deps_costly
;
3016 else if (! strcmp (rs6000_sched_costly_dep_str
, "true_store_to_load"))
3017 rs6000_sched_costly_dep
= true_store_to_load_dep_costly
;
3018 else if (! strcmp (rs6000_sched_costly_dep_str
, "store_to_load"))
3019 rs6000_sched_costly_dep
= store_to_load_dep_costly
;
3021 rs6000_sched_costly_dep
= ((enum rs6000_dependence_cost
)
3022 atoi (rs6000_sched_costly_dep_str
));
3025 /* Handle -minsert-sched-nops option. */
3026 rs6000_sched_insert_nops
3027 = (rs6000_sched_groups
? sched_finish_regroup_exact
: sched_finish_none
);
3029 if (rs6000_sched_insert_nops_str
)
3031 if (! strcmp (rs6000_sched_insert_nops_str
, "no"))
3032 rs6000_sched_insert_nops
= sched_finish_none
;
3033 else if (! strcmp (rs6000_sched_insert_nops_str
, "pad"))
3034 rs6000_sched_insert_nops
= sched_finish_pad_groups
;
3035 else if (! strcmp (rs6000_sched_insert_nops_str
, "regroup_exact"))
3036 rs6000_sched_insert_nops
= sched_finish_regroup_exact
;
3038 rs6000_sched_insert_nops
= ((enum rs6000_nop_insertion
)
3039 atoi (rs6000_sched_insert_nops_str
));
3044 #ifdef TARGET_REGNAMES
3045 /* If the user desires alternate register names, copy in the
3046 alternate names now. */
3047 if (TARGET_REGNAMES
)
3048 memcpy (rs6000_reg_names
, alt_reg_names
, sizeof (rs6000_reg_names
));
3051 /* Set aix_struct_return last, after the ABI is determined.
3052 If -maix-struct-return or -msvr4-struct-return was explicitly
3053 used, don't override with the ABI default. */
3054 if (!global_options_set
.x_aix_struct_return
)
3055 aix_struct_return
= (DEFAULT_ABI
!= ABI_V4
|| DRAFT_V4_STRUCT_RET
);
3058 /* IBM XL compiler defaults to unsigned bitfields. */
3059 if (TARGET_XL_COMPAT
)
3060 flag_signed_bitfields
= 0;
3063 if (TARGET_LONG_DOUBLE_128
&& !TARGET_IEEEQUAD
)
3064 REAL_MODE_FORMAT (TFmode
) = &ibm_extended_format
;
3067 ASM_GENERATE_INTERNAL_LABEL (toc_label_name
, "LCTOC", 1);
3069 /* We can only guarantee the availability of DI pseudo-ops when
3070 assembling for 64-bit targets. */
3073 targetm
.asm_out
.aligned_op
.di
= NULL
;
3074 targetm
.asm_out
.unaligned_op
.di
= NULL
;
3078 /* Set branch target alignment, if not optimizing for size. */
3081 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
3082 aligned 8byte to avoid misprediction by the branch predictor. */
3083 if (rs6000_cpu
== PROCESSOR_TITAN
3084 || rs6000_cpu
== PROCESSOR_CELL
)
3086 if (align_functions
<= 0)
3087 align_functions
= 8;
3088 if (align_jumps
<= 0)
3090 if (align_loops
<= 0)
3093 if (rs6000_align_branch_targets
)
3095 if (align_functions
<= 0)
3096 align_functions
= 16;
3097 if (align_jumps
<= 0)
3099 if (align_loops
<= 0)
3101 can_override_loop_align
= 1;
3105 if (align_jumps_max_skip
<= 0)
3106 align_jumps_max_skip
= 15;
3107 if (align_loops_max_skip
<= 0)
3108 align_loops_max_skip
= 15;
3111 /* Arrange to save and restore machine status around nested functions. */
3112 init_machine_status
= rs6000_init_machine_status
;
3114 /* We should always be splitting complex arguments, but we can't break
3115 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
3116 if (DEFAULT_ABI
!= ABI_AIX
)
3117 targetm
.calls
.split_complex_arg
= NULL
;
3120 /* Initialize rs6000_cost with the appropriate target costs. */
3122 rs6000_cost
= TARGET_POWERPC64
? &size64_cost
: &size32_cost
;
3126 case PROCESSOR_RIOS1
:
3127 rs6000_cost
= &rios1_cost
;
3130 case PROCESSOR_RIOS2
:
3131 rs6000_cost
= &rios2_cost
;
3134 case PROCESSOR_RS64A
:
3135 rs6000_cost
= &rs64a_cost
;
3138 case PROCESSOR_MPCCORE
:
3139 rs6000_cost
= &mpccore_cost
;
3142 case PROCESSOR_PPC403
:
3143 rs6000_cost
= &ppc403_cost
;
3146 case PROCESSOR_PPC405
:
3147 rs6000_cost
= &ppc405_cost
;
3150 case PROCESSOR_PPC440
:
3151 rs6000_cost
= &ppc440_cost
;
3154 case PROCESSOR_PPC476
:
3155 rs6000_cost
= &ppc476_cost
;
3158 case PROCESSOR_PPC601
:
3159 rs6000_cost
= &ppc601_cost
;
3162 case PROCESSOR_PPC603
:
3163 rs6000_cost
= &ppc603_cost
;
3166 case PROCESSOR_PPC604
:
3167 rs6000_cost
= &ppc604_cost
;
3170 case PROCESSOR_PPC604e
:
3171 rs6000_cost
= &ppc604e_cost
;
3174 case PROCESSOR_PPC620
:
3175 rs6000_cost
= &ppc620_cost
;
3178 case PROCESSOR_PPC630
:
3179 rs6000_cost
= &ppc630_cost
;
3182 case PROCESSOR_CELL
:
3183 rs6000_cost
= &ppccell_cost
;
3186 case PROCESSOR_PPC750
:
3187 case PROCESSOR_PPC7400
:
3188 rs6000_cost
= &ppc750_cost
;
3191 case PROCESSOR_PPC7450
:
3192 rs6000_cost
= &ppc7450_cost
;
3195 case PROCESSOR_PPC8540
:
3196 rs6000_cost
= &ppc8540_cost
;
3199 case PROCESSOR_PPCE300C2
:
3200 case PROCESSOR_PPCE300C3
:
3201 rs6000_cost
= &ppce300c2c3_cost
;
3204 case PROCESSOR_PPCE500MC
:
3205 rs6000_cost
= &ppce500mc_cost
;
3208 case PROCESSOR_PPCE500MC64
:
3209 rs6000_cost
= &ppce500mc64_cost
;
3212 case PROCESSOR_TITAN
:
3213 rs6000_cost
= &titan_cost
;
3216 case PROCESSOR_POWER4
:
3217 case PROCESSOR_POWER5
:
3218 rs6000_cost
= &power4_cost
;
3221 case PROCESSOR_POWER6
:
3222 rs6000_cost
= &power6_cost
;
3225 case PROCESSOR_POWER7
:
3226 rs6000_cost
= &power7_cost
;
3229 case PROCESSOR_PPCA2
:
3230 rs6000_cost
= &ppca2_cost
;
3239 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
3240 rs6000_cost
->simultaneous_prefetches
,
3241 global_options
.x_param_values
,
3242 global_options_set
.x_param_values
);
3243 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, rs6000_cost
->l1_cache_size
,
3244 global_options
.x_param_values
,
3245 global_options_set
.x_param_values
);
3246 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
3247 rs6000_cost
->cache_line_size
,
3248 global_options
.x_param_values
,
3249 global_options_set
.x_param_values
);
3250 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, rs6000_cost
->l2_cache_size
,
3251 global_options
.x_param_values
,
3252 global_options_set
.x_param_values
);
3254 /* If using typedef char *va_list, signal that
3255 __builtin_va_start (&ap, 0) can be optimized to
3256 ap = __builtin_next_arg (0). */
3257 if (DEFAULT_ABI
!= ABI_V4
)
3258 targetm
.expand_builtin_va_start
= NULL
;
3261 /* Set up single/double float flags.
3262 If TARGET_HARD_FLOAT is set, but neither single or double is set,
3263 then set both flags. */
3264 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
3265 && rs6000_single_float
== 0 && rs6000_double_float
== 0)
3266 rs6000_single_float
= rs6000_double_float
= 1;
3268 /* Reset single and double FP flags if target is E500. */
3271 rs6000_single_float
= rs6000_double_float
= 0;
3272 if (TARGET_E500_SINGLE
)
3273 rs6000_single_float
= 1;
3274 if (TARGET_E500_DOUBLE
)
3275 rs6000_single_float
= rs6000_double_float
= 1;
3278 if (main_target_opt
)
3280 if (main_target_opt
->x_rs6000_single_float
!= rs6000_single_float
)
3281 error ("target attribute or pragma changes single precision floating "
3283 if (main_target_opt
->x_rs6000_double_float
!= rs6000_double_float
)
3284 error ("target attribute or pragma changes double precision floating "
3288 /* If not explicitly specified via option, decide whether to generate indexed
3289 load/store instructions. */
3290 if (TARGET_AVOID_XFORM
== -1)
3291 /* Avoid indexed addressing when targeting Power6 in order to avoid the
3292 DERAT mispredict penalty. However the LVE and STVE altivec instructions
3293 need indexed accesses and the type used is the scalar type of the element
3294 being loaded or stored. */
3295 TARGET_AVOID_XFORM
= (rs6000_cpu
== PROCESSOR_POWER6
&& TARGET_CMPB
3296 && !TARGET_ALTIVEC
);
3298 /* Set the -mrecip options. */
3299 if (rs6000_recip_name
)
3301 char *p
= ASTRDUP (rs6000_recip_name
);
3303 unsigned int mask
, i
;
3306 while ((q
= strtok (p
, ",")) != NULL
)
3317 if (!strcmp (q
, "default"))
3318 mask
= ((TARGET_RECIP_PRECISION
)
3319 ? RECIP_HIGH_PRECISION
: RECIP_LOW_PRECISION
);
3322 for (i
= 0; i
< ARRAY_SIZE (recip_options
); i
++)
3323 if (!strcmp (q
, recip_options
[i
].string
))
3325 mask
= recip_options
[i
].mask
;
3329 if (i
== ARRAY_SIZE (recip_options
))
3331 error ("unknown option for -mrecip=%s", q
);
3339 rs6000_recip_control
&= ~mask
;
3341 rs6000_recip_control
|= mask
;
3345 /* Set the builtin mask of the various options used that could affect which
3346 builtins were used. In the past we used target_flags, but we've run out
3347 of bits, and some options like SPE and PAIRED are no longer in
3349 rs6000_builtin_mask
= rs6000_builtin_mask_calculate ();
3350 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
3351 fprintf (stderr
, "new builtin mask = 0x%x%s%s%s%s\n", rs6000_builtin_mask
,
3352 (rs6000_builtin_mask
& RS6000_BTM_ALTIVEC
) ? ", altivec" : "",
3353 (rs6000_builtin_mask
& RS6000_BTM_VSX
) ? ", vsx" : "",
3354 (rs6000_builtin_mask
& RS6000_BTM_PAIRED
) ? ", paired" : "",
3355 (rs6000_builtin_mask
& RS6000_BTM_SPE
) ? ", spe" : "");
3357 /* Initialize all of the registers. */
3358 rs6000_init_hard_regno_mode_ok (global_init_p
);
3360 /* Save the initial options in case the user does function specific options */
3362 target_option_default_node
= target_option_current_node
3363 = build_target_option_node ();
3365 /* If not explicitly specified via option, decide whether to generate the
3366 extra blr's required to preserve the link stack on some cpus (eg, 476). */
3367 if (TARGET_LINK_STACK
== -1)
3368 SET_TARGET_LINK_STACK (rs6000_cpu
== PROCESSOR_PPC476
&& flag_pic
);
3373 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
3374 define the target cpu type. */
3377 rs6000_option_override (void)
3379 (void) rs6000_option_override_internal (true);
3383 /* Implement targetm.vectorize.builtin_mask_for_load. */
3385 rs6000_builtin_mask_for_load (void)
3387 if (TARGET_ALTIVEC
|| TARGET_VSX
)
3388 return altivec_builtin_mask_for_load
;
3393 /* Implement LOOP_ALIGN. */
3395 rs6000_loop_align (rtx label
)
3400 /* Don't override loop alignment if -falign-loops was specified. */
3401 if (!can_override_loop_align
)
3402 return align_loops_log
;
3404 bb
= BLOCK_FOR_INSN (label
);
3405 ninsns
= num_loop_insns(bb
->loop_father
);
3407 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
3408 if (ninsns
> 4 && ninsns
<= 8
3409 && (rs6000_cpu
== PROCESSOR_POWER4
3410 || rs6000_cpu
== PROCESSOR_POWER5
3411 || rs6000_cpu
== PROCESSOR_POWER6
3412 || rs6000_cpu
== PROCESSOR_POWER7
))
3415 return align_loops_log
;
3418 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
3420 rs6000_loop_align_max_skip (rtx label
)
3422 return (1 << rs6000_loop_align (label
)) - 1;
3425 /* Implement targetm.vectorize.builtin_mul_widen_even. */
3427 rs6000_builtin_mul_widen_even (tree type
)
3429 if (!TARGET_ALTIVEC
)
3432 switch (TYPE_MODE (type
))
3435 return TYPE_UNSIGNED (type
)
3436 ? rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULEUH_UNS
]
3437 : rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULESH
];
3440 return TYPE_UNSIGNED (type
)
3441 ? rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULEUB_UNS
]
3442 : rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULESB
];
3448 /* Implement targetm.vectorize.builtin_mul_widen_odd. */
3450 rs6000_builtin_mul_widen_odd (tree type
)
3452 if (!TARGET_ALTIVEC
)
3455 switch (TYPE_MODE (type
))
3458 return TYPE_UNSIGNED (type
)
3459 ? rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULOUH_UNS
]
3460 : rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULOSH
];
3463 return TYPE_UNSIGNED (type
)
3464 ? rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULOUB_UNS
]
3465 : rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULOSB
];
3472 /* Return true iff, data reference of TYPE can reach vector alignment (16)
3473 after applying N number of iterations. This routine does not determine
3474 how may iterations are required to reach desired alignment. */
3477 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED
, bool is_packed
)
3484 if (rs6000_alignment_flags
== MASK_ALIGN_NATURAL
)
3487 if (rs6000_alignment_flags
== MASK_ALIGN_POWER
)
3497 /* Assuming that all other types are naturally aligned. CHECKME! */
3502 /* Return true if the vector misalignment factor is supported by the
3505 rs6000_builtin_support_vector_misalignment (enum machine_mode mode
,
3512 /* Return if movmisalign pattern is not supported for this mode. */
3513 if (optab_handler (movmisalign_optab
, mode
) == CODE_FOR_nothing
)
3516 if (misalignment
== -1)
3518 /* Misalignment factor is unknown at compile time but we know
3519 it's word aligned. */
3520 if (rs6000_vector_alignment_reachable (type
, is_packed
))
3522 int element_size
= TREE_INT_CST_LOW (TYPE_SIZE (type
));
3524 if (element_size
== 64 || element_size
== 32)
3531 /* VSX supports word-aligned vector. */
3532 if (misalignment
% 4 == 0)
3538 /* Implement targetm.vectorize.builtin_vectorization_cost. */
3540 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost
,
3541 tree vectype
, int misalign
)
3545 switch (type_of_cost
)
3555 case cond_branch_not_taken
:
3564 case vec_promote_demote
:
3570 case cond_branch_taken
:
3573 case unaligned_load
:
3574 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
3576 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
3578 /* Double word aligned. */
3586 /* Double word aligned. */
3590 /* Unknown misalignment. */
3603 /* Misaligned loads are not supported. */
3608 case unaligned_store
:
3609 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
3611 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
3613 /* Double word aligned. */
3621 /* Double word aligned. */
3625 /* Unknown misalignment. */
3638 /* Misaligned stores are not supported. */
3648 /* Implement targetm.vectorize.preferred_simd_mode. */
3650 static enum machine_mode
3651 rs6000_preferred_simd_mode (enum machine_mode mode
)
3660 if (TARGET_ALTIVEC
|| TARGET_VSX
)
3684 if (TARGET_PAIRED_FLOAT
3690 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
3691 library with vectorized intrinsics. */
3694 rs6000_builtin_vectorized_libmass (tree fndecl
, tree type_out
, tree type_in
)
3697 const char *suffix
= NULL
;
3698 tree fntype
, new_fndecl
, bdecl
= NULL_TREE
;
3701 enum machine_mode el_mode
, in_mode
;
3704 /* Libmass is suitable for unsafe math only as it does not correctly support
3705 parts of IEEE with the required precision such as denormals. Only support
3706 it if we have VSX to use the simd d2 or f4 functions.
3707 XXX: Add variable length support. */
3708 if (!flag_unsafe_math_optimizations
|| !TARGET_VSX
)
3711 el_mode
= TYPE_MODE (TREE_TYPE (type_out
));
3712 n
= TYPE_VECTOR_SUBPARTS (type_out
);
3713 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
3714 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
3715 if (el_mode
!= in_mode
3719 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_NORMAL
)
3721 enum built_in_function fn
= DECL_FUNCTION_CODE (fndecl
);
3724 case BUILT_IN_ATAN2
:
3725 case BUILT_IN_HYPOT
:
3731 case BUILT_IN_ACOSH
:
3733 case BUILT_IN_ASINH
:
3735 case BUILT_IN_ATANH
:
3743 case BUILT_IN_EXPM1
:
3744 case BUILT_IN_LGAMMA
:
3745 case BUILT_IN_LOG10
:
3746 case BUILT_IN_LOG1P
:
3754 bdecl
= builtin_decl_implicit (fn
);
3755 suffix
= "d2"; /* pow -> powd2 */
3756 if (el_mode
!= DFmode
3761 case BUILT_IN_ATAN2F
:
3762 case BUILT_IN_HYPOTF
:
3767 case BUILT_IN_ACOSF
:
3768 case BUILT_IN_ACOSHF
:
3769 case BUILT_IN_ASINF
:
3770 case BUILT_IN_ASINHF
:
3771 case BUILT_IN_ATANF
:
3772 case BUILT_IN_ATANHF
:
3773 case BUILT_IN_CBRTF
:
3775 case BUILT_IN_COSHF
:
3777 case BUILT_IN_ERFCF
:
3778 case BUILT_IN_EXP2F
:
3780 case BUILT_IN_EXPM1F
:
3781 case BUILT_IN_LGAMMAF
:
3782 case BUILT_IN_LOG10F
:
3783 case BUILT_IN_LOG1PF
:
3784 case BUILT_IN_LOG2F
:
3787 case BUILT_IN_SINHF
:
3788 case BUILT_IN_SQRTF
:
3790 case BUILT_IN_TANHF
:
3791 bdecl
= builtin_decl_implicit (fn
);
3792 suffix
= "4"; /* powf -> powf4 */
3793 if (el_mode
!= SFmode
3805 gcc_assert (suffix
!= NULL
);
3806 bname
= IDENTIFIER_POINTER (DECL_NAME (bdecl
));
3807 strcpy (name
, bname
+ sizeof ("__builtin_") - 1);
3808 strcat (name
, suffix
);
3811 fntype
= build_function_type_list (type_out
, type_in
, NULL
);
3812 else if (n_args
== 2)
3813 fntype
= build_function_type_list (type_out
, type_in
, type_in
, NULL
);
3817 /* Build a function declaration for the vectorized function. */
3818 new_fndecl
= build_decl (BUILTINS_LOCATION
,
3819 FUNCTION_DECL
, get_identifier (name
), fntype
);
3820 TREE_PUBLIC (new_fndecl
) = 1;
3821 DECL_EXTERNAL (new_fndecl
) = 1;
3822 DECL_IS_NOVOPS (new_fndecl
) = 1;
3823 TREE_READONLY (new_fndecl
) = 1;
3828 /* Returns a function decl for a vectorized version of the builtin function
3829 with builtin function code FN and the result vector type TYPE, or NULL_TREE
3830 if it is not available. */
3833 rs6000_builtin_vectorized_function (tree fndecl
, tree type_out
,
3836 enum machine_mode in_mode
, out_mode
;
3839 if (TARGET_DEBUG_BUILTIN
)
3840 fprintf (stderr
, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
3841 IDENTIFIER_POINTER (DECL_NAME (fndecl
)),
3842 GET_MODE_NAME (TYPE_MODE (type_out
)),
3843 GET_MODE_NAME (TYPE_MODE (type_in
)));
3845 if (TREE_CODE (type_out
) != VECTOR_TYPE
3846 || TREE_CODE (type_in
) != VECTOR_TYPE
3847 || !TARGET_VECTORIZE_BUILTINS
)
3850 out_mode
= TYPE_MODE (TREE_TYPE (type_out
));
3851 out_n
= TYPE_VECTOR_SUBPARTS (type_out
);
3852 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
3853 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
3855 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_NORMAL
)
3857 enum built_in_function fn
= DECL_FUNCTION_CODE (fndecl
);
3860 case BUILT_IN_COPYSIGN
:
3861 if (VECTOR_UNIT_VSX_P (V2DFmode
)
3862 && out_mode
== DFmode
&& out_n
== 2
3863 && in_mode
== DFmode
&& in_n
== 2)
3864 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNDP
];
3866 case BUILT_IN_COPYSIGNF
:
3867 if (out_mode
!= SFmode
|| out_n
!= 4
3868 || in_mode
!= SFmode
|| in_n
!= 4)
3870 if (VECTOR_UNIT_VSX_P (V4SFmode
))
3871 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNSP
];
3872 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
3873 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_COPYSIGN_V4SF
];
3876 if (VECTOR_UNIT_VSX_P (V2DFmode
)
3877 && out_mode
== DFmode
&& out_n
== 2
3878 && in_mode
== DFmode
&& in_n
== 2)
3879 return rs6000_builtin_decls
[VSX_BUILTIN_XVSQRTDP
];
3881 case BUILT_IN_SQRTF
:
3882 if (VECTOR_UNIT_VSX_P (V4SFmode
)
3883 && out_mode
== SFmode
&& out_n
== 4
3884 && in_mode
== SFmode
&& in_n
== 4)
3885 return rs6000_builtin_decls
[VSX_BUILTIN_XVSQRTSP
];
3888 if (VECTOR_UNIT_VSX_P (V2DFmode
)
3889 && out_mode
== DFmode
&& out_n
== 2
3890 && in_mode
== DFmode
&& in_n
== 2)
3891 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIP
];
3893 case BUILT_IN_CEILF
:
3894 if (out_mode
!= SFmode
|| out_n
!= 4
3895 || in_mode
!= SFmode
|| in_n
!= 4)
3897 if (VECTOR_UNIT_VSX_P (V4SFmode
))
3898 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIP
];
3899 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
3900 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIP
];
3902 case BUILT_IN_FLOOR
:
3903 if (VECTOR_UNIT_VSX_P (V2DFmode
)
3904 && out_mode
== DFmode
&& out_n
== 2
3905 && in_mode
== DFmode
&& in_n
== 2)
3906 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIM
];
3908 case BUILT_IN_FLOORF
:
3909 if (out_mode
!= SFmode
|| out_n
!= 4
3910 || in_mode
!= SFmode
|| in_n
!= 4)
3912 if (VECTOR_UNIT_VSX_P (V4SFmode
))
3913 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIM
];
3914 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
3915 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIM
];
3918 if (VECTOR_UNIT_VSX_P (V2DFmode
)
3919 && out_mode
== DFmode
&& out_n
== 2
3920 && in_mode
== DFmode
&& in_n
== 2)
3921 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDDP
];
3924 if (VECTOR_UNIT_VSX_P (V4SFmode
)
3925 && out_mode
== SFmode
&& out_n
== 4
3926 && in_mode
== SFmode
&& in_n
== 4)
3927 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDSP
];
3928 else if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
3929 && out_mode
== SFmode
&& out_n
== 4
3930 && in_mode
== SFmode
&& in_n
== 4)
3931 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMADDFP
];
3933 case BUILT_IN_TRUNC
:
3934 if (VECTOR_UNIT_VSX_P (V2DFmode
)
3935 && out_mode
== DFmode
&& out_n
== 2
3936 && in_mode
== DFmode
&& in_n
== 2)
3937 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIZ
];
3939 case BUILT_IN_TRUNCF
:
3940 if (out_mode
!= SFmode
|| out_n
!= 4
3941 || in_mode
!= SFmode
|| in_n
!= 4)
3943 if (VECTOR_UNIT_VSX_P (V4SFmode
))
3944 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIZ
];
3945 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
3946 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIZ
];
3948 case BUILT_IN_NEARBYINT
:
3949 if (VECTOR_UNIT_VSX_P (V2DFmode
)
3950 && flag_unsafe_math_optimizations
3951 && out_mode
== DFmode
&& out_n
== 2
3952 && in_mode
== DFmode
&& in_n
== 2)
3953 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPI
];
3955 case BUILT_IN_NEARBYINTF
:
3956 if (VECTOR_UNIT_VSX_P (V4SFmode
)
3957 && flag_unsafe_math_optimizations
3958 && out_mode
== SFmode
&& out_n
== 4
3959 && in_mode
== SFmode
&& in_n
== 4)
3960 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPI
];
3963 if (VECTOR_UNIT_VSX_P (V2DFmode
)
3964 && !flag_trapping_math
3965 && out_mode
== DFmode
&& out_n
== 2
3966 && in_mode
== DFmode
&& in_n
== 2)
3967 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIC
];
3969 case BUILT_IN_RINTF
:
3970 if (VECTOR_UNIT_VSX_P (V4SFmode
)
3971 && !flag_trapping_math
3972 && out_mode
== SFmode
&& out_n
== 4
3973 && in_mode
== SFmode
&& in_n
== 4)
3974 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIC
];
3981 else if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_MD
)
3983 enum rs6000_builtins fn
3984 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
3987 case RS6000_BUILTIN_RSQRTF
:
3988 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
3989 && out_mode
== SFmode
&& out_n
== 4
3990 && in_mode
== SFmode
&& in_n
== 4)
3991 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRSQRTFP
];
3993 case RS6000_BUILTIN_RSQRT
:
3994 if (VECTOR_UNIT_VSX_P (V2DFmode
)
3995 && out_mode
== DFmode
&& out_n
== 2
3996 && in_mode
== DFmode
&& in_n
== 2)
3997 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
3999 case RS6000_BUILTIN_RECIPF
:
4000 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
4001 && out_mode
== SFmode
&& out_n
== 4
4002 && in_mode
== SFmode
&& in_n
== 4)
4003 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRECIPFP
];
4005 case RS6000_BUILTIN_RECIP
:
4006 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4007 && out_mode
== DFmode
&& out_n
== 2
4008 && in_mode
== DFmode
&& in_n
== 2)
4009 return rs6000_builtin_decls
[VSX_BUILTIN_RECIP_V2DF
];
4016 /* Generate calls to libmass if appropriate. */
4017 if (rs6000_veclib_handler
)
4018 return rs6000_veclib_handler (fndecl
, type_out
, type_in
);
4023 /* Default CPU string for rs6000*_file_start functions. */
4024 static const char *rs6000_default_cpu
;
4026 /* Do anything needed at the start of the asm file. */
4029 rs6000_file_start (void)
4032 const char *start
= buffer
;
4033 FILE *file
= asm_out_file
;
4035 rs6000_default_cpu
= TARGET_CPU_DEFAULT
;
4037 default_file_start ();
4039 if (flag_verbose_asm
)
4041 sprintf (buffer
, "\n%s rs6000/powerpc options:", ASM_COMMENT_START
);
4043 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
4045 fprintf (file
, "%s --with-cpu=%s", start
, rs6000_default_cpu
);
4049 if (global_options_set
.x_rs6000_cpu_index
)
4051 fprintf (file
, "%s -mcpu=%s", start
,
4052 processor_target_table
[rs6000_cpu_index
].name
);
4056 if (global_options_set
.x_rs6000_tune_index
)
4058 fprintf (file
, "%s -mtune=%s", start
,
4059 processor_target_table
[rs6000_tune_index
].name
);
4063 if (PPC405_ERRATUM77
)
4065 fprintf (file
, "%s PPC405CR_ERRATUM77", start
);
4069 #ifdef USING_ELFOS_H
4070 switch (rs6000_sdata
)
4072 case SDATA_NONE
: fprintf (file
, "%s -msdata=none", start
); start
= ""; break;
4073 case SDATA_DATA
: fprintf (file
, "%s -msdata=data", start
); start
= ""; break;
4074 case SDATA_SYSV
: fprintf (file
, "%s -msdata=sysv", start
); start
= ""; break;
4075 case SDATA_EABI
: fprintf (file
, "%s -msdata=eabi", start
); start
= ""; break;
4078 if (rs6000_sdata
&& g_switch_value
)
4080 fprintf (file
, "%s -G %d", start
,
4090 if (DEFAULT_ABI
== ABI_AIX
|| (TARGET_ELF
&& flag_pic
== 2))
4092 switch_to_section (toc_section
);
4093 switch_to_section (text_section
);
4098 /* Return nonzero if this function is known to have a null epilogue. */
4101 direct_return (void)
4103 if (reload_completed
)
4105 rs6000_stack_t
*info
= rs6000_stack_info ();
4107 if (info
->first_gp_reg_save
== 32
4108 && info
->first_fp_reg_save
== 64
4109 && info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
4110 && ! info
->lr_save_p
4111 && ! info
->cr_save_p
4112 && info
->vrsave_mask
== 0
4120 /* Return the number of instructions it takes to form a constant in an
4121 integer register. */
4124 num_insns_constant_wide (HOST_WIDE_INT value
)
4126 /* signed constant loadable with {cal|addi} */
4127 if ((unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000)
4130 /* constant loadable with {cau|addis} */
4131 else if ((value
& 0xffff) == 0
4132 && (value
>> 31 == -1 || value
>> 31 == 0))
4135 #if HOST_BITS_PER_WIDE_INT == 64
4136 else if (TARGET_POWERPC64
)
4138 HOST_WIDE_INT low
= ((value
& 0xffffffff) ^ 0x80000000) - 0x80000000;
4139 HOST_WIDE_INT high
= value
>> 31;
4141 if (high
== 0 || high
== -1)
4147 return num_insns_constant_wide (high
) + 1;
4149 return num_insns_constant_wide (low
) + 1;
4151 return (num_insns_constant_wide (high
)
4152 + num_insns_constant_wide (low
) + 1);
4161 num_insns_constant (rtx op
, enum machine_mode mode
)
4163 HOST_WIDE_INT low
, high
;
4165 switch (GET_CODE (op
))
4168 #if HOST_BITS_PER_WIDE_INT == 64
4169 if ((INTVAL (op
) >> 31) != 0 && (INTVAL (op
) >> 31) != -1
4170 && mask64_operand (op
, mode
))
4174 return num_insns_constant_wide (INTVAL (op
));
4177 if (mode
== SFmode
|| mode
== SDmode
)
4182 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
4183 if (DECIMAL_FLOAT_MODE_P (mode
))
4184 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
4186 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
4187 return num_insns_constant_wide ((HOST_WIDE_INT
) l
);
4190 if (mode
== VOIDmode
|| mode
== DImode
)
4192 high
= CONST_DOUBLE_HIGH (op
);
4193 low
= CONST_DOUBLE_LOW (op
);
4200 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
4201 if (DECIMAL_FLOAT_MODE_P (mode
))
4202 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, l
);
4204 REAL_VALUE_TO_TARGET_DOUBLE (rv
, l
);
4205 high
= l
[WORDS_BIG_ENDIAN
== 0];
4206 low
= l
[WORDS_BIG_ENDIAN
!= 0];
4210 return (num_insns_constant_wide (low
)
4211 + num_insns_constant_wide (high
));
4214 if ((high
== 0 && low
>= 0)
4215 || (high
== -1 && low
< 0))
4216 return num_insns_constant_wide (low
);
4218 else if (mask64_operand (op
, mode
))
4222 return num_insns_constant_wide (high
) + 1;
4225 return (num_insns_constant_wide (high
)
4226 + num_insns_constant_wide (low
) + 1);
4234 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
4235 If the mode of OP is MODE_VECTOR_INT, this simply returns the
4236 corresponding element of the vector, but for V4SFmode and V2SFmode,
4237 the corresponding "float" is interpreted as an SImode integer. */
4240 const_vector_elt_as_int (rtx op
, unsigned int elt
)
4244 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
4245 gcc_assert (GET_MODE (op
) != V2DImode
4246 && GET_MODE (op
) != V2DFmode
);
4248 tmp
= CONST_VECTOR_ELT (op
, elt
);
4249 if (GET_MODE (op
) == V4SFmode
4250 || GET_MODE (op
) == V2SFmode
)
4251 tmp
= gen_lowpart (SImode
, tmp
);
4252 return INTVAL (tmp
);
4255 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
4256 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
4257 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
4258 all items are set to the same value and contain COPIES replicas of the
4259 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
4260 operand and the others are set to the value of the operand's msb. */
4263 vspltis_constant (rtx op
, unsigned step
, unsigned copies
)
4265 enum machine_mode mode
= GET_MODE (op
);
4266 enum machine_mode inner
= GET_MODE_INNER (mode
);
4274 HOST_WIDE_INT splat_val
;
4275 HOST_WIDE_INT msb_val
;
4277 if (mode
== V2DImode
|| mode
== V2DFmode
)
4280 nunits
= GET_MODE_NUNITS (mode
);
4281 bitsize
= GET_MODE_BITSIZE (inner
);
4282 mask
= GET_MODE_MASK (inner
);
4284 val
= const_vector_elt_as_int (op
, nunits
- 1);
4286 msb_val
= val
> 0 ? 0 : -1;
4288 /* Construct the value to be splatted, if possible. If not, return 0. */
4289 for (i
= 2; i
<= copies
; i
*= 2)
4291 HOST_WIDE_INT small_val
;
4293 small_val
= splat_val
>> bitsize
;
4295 if (splat_val
!= ((small_val
<< bitsize
) | (small_val
& mask
)))
4297 splat_val
= small_val
;
4300 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
4301 if (EASY_VECTOR_15 (splat_val
))
4304 /* Also check if we can splat, and then add the result to itself. Do so if
4305 the value is positive, of if the splat instruction is using OP's mode;
4306 for splat_val < 0, the splat and the add should use the same mode. */
4307 else if (EASY_VECTOR_15_ADD_SELF (splat_val
)
4308 && (splat_val
>= 0 || (step
== 1 && copies
== 1)))
4311 /* Also check if are loading up the most significant bit which can be done by
4312 loading up -1 and shifting the value left by -1. */
4313 else if (EASY_VECTOR_MSB (splat_val
, inner
))
4319 /* Check if VAL is present in every STEP-th element, and the
4320 other elements are filled with its most significant bit. */
4321 for (i
= 0; i
< nunits
- 1; ++i
)
4323 HOST_WIDE_INT desired_val
;
4324 if (((i
+ 1) & (step
- 1)) == 0)
4327 desired_val
= msb_val
;
4329 if (desired_val
!= const_vector_elt_as_int (op
, i
))
4337 /* Return true if OP is of the given MODE and can be synthesized
4338 with a vspltisb, vspltish or vspltisw. */
4341 easy_altivec_constant (rtx op
, enum machine_mode mode
)
4343 unsigned step
, copies
;
4345 if (mode
== VOIDmode
)
4346 mode
= GET_MODE (op
);
4347 else if (mode
!= GET_MODE (op
))
4350 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
4352 if (mode
== V2DFmode
)
4353 return zero_constant (op
, mode
);
4355 if (mode
== V2DImode
)
4357 /* In case the compiler is built 32-bit, CONST_DOUBLE constants are not
4359 if (GET_CODE (CONST_VECTOR_ELT (op
, 0)) != CONST_INT
4360 || GET_CODE (CONST_VECTOR_ELT (op
, 1)) != CONST_INT
)
4363 if (zero_constant (op
, mode
))
4366 if (INTVAL (CONST_VECTOR_ELT (op
, 0)) == -1
4367 && INTVAL (CONST_VECTOR_ELT (op
, 1)) == -1)
4373 /* Start with a vspltisw. */
4374 step
= GET_MODE_NUNITS (mode
) / 4;
4377 if (vspltis_constant (op
, step
, copies
))
4380 /* Then try with a vspltish. */
4386 if (vspltis_constant (op
, step
, copies
))
4389 /* And finally a vspltisb. */
4395 if (vspltis_constant (op
, step
, copies
))
4401 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
4402 result is OP. Abort if it is not possible. */
4405 gen_easy_altivec_constant (rtx op
)
4407 enum machine_mode mode
= GET_MODE (op
);
4408 int nunits
= GET_MODE_NUNITS (mode
);
4409 rtx last
= CONST_VECTOR_ELT (op
, nunits
- 1);
4410 unsigned step
= nunits
/ 4;
4411 unsigned copies
= 1;
4413 /* Start with a vspltisw. */
4414 if (vspltis_constant (op
, step
, copies
))
4415 return gen_rtx_VEC_DUPLICATE (V4SImode
, gen_lowpart (SImode
, last
));
4417 /* Then try with a vspltish. */
4423 if (vspltis_constant (op
, step
, copies
))
4424 return gen_rtx_VEC_DUPLICATE (V8HImode
, gen_lowpart (HImode
, last
));
4426 /* And finally a vspltisb. */
4432 if (vspltis_constant (op
, step
, copies
))
4433 return gen_rtx_VEC_DUPLICATE (V16QImode
, gen_lowpart (QImode
, last
));
4439 output_vec_const_move (rtx
*operands
)
4442 enum machine_mode mode
;
4447 mode
= GET_MODE (dest
);
4451 if (zero_constant (vec
, mode
))
4452 return "xxlxor %x0,%x0,%x0";
4454 if (mode
== V2DImode
4455 && INTVAL (CONST_VECTOR_ELT (vec
, 0)) == -1
4456 && INTVAL (CONST_VECTOR_ELT (vec
, 1)) == -1)
4457 return "vspltisw %0,-1";
4463 if (zero_constant (vec
, mode
))
4464 return "vxor %0,%0,%0";
4466 splat_vec
= gen_easy_altivec_constant (vec
);
4467 gcc_assert (GET_CODE (splat_vec
) == VEC_DUPLICATE
);
4468 operands
[1] = XEXP (splat_vec
, 0);
4469 if (!EASY_VECTOR_15 (INTVAL (operands
[1])))
4472 switch (GET_MODE (splat_vec
))
4475 return "vspltisw %0,%1";
4478 return "vspltish %0,%1";
4481 return "vspltisb %0,%1";
4488 gcc_assert (TARGET_SPE
);
4490 /* Vector constant 0 is handled as a splitter of V2SI, and in the
4491 pattern of V1DI, V4HI, and V2SF.
4493 FIXME: We should probably return # and add post reload
4494 splitters for these, but this way is so easy ;-). */
4495 cst
= INTVAL (CONST_VECTOR_ELT (vec
, 0));
4496 cst2
= INTVAL (CONST_VECTOR_ELT (vec
, 1));
4497 operands
[1] = CONST_VECTOR_ELT (vec
, 0);
4498 operands
[2] = CONST_VECTOR_ELT (vec
, 1);
4500 return "li %0,%1\n\tevmergelo %0,%0,%0";
4502 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
4505 /* Initialize TARGET of vector PAIRED to VALS. */
4508 paired_expand_vector_init (rtx target
, rtx vals
)
4510 enum machine_mode mode
= GET_MODE (target
);
4511 int n_elts
= GET_MODE_NUNITS (mode
);
4513 rtx x
, new_rtx
, tmp
, constant_op
, op1
, op2
;
4516 for (i
= 0; i
< n_elts
; ++i
)
4518 x
= XVECEXP (vals
, 0, i
);
4519 if (!(CONST_INT_P (x
)
4520 || GET_CODE (x
) == CONST_DOUBLE
4521 || GET_CODE (x
) == CONST_FIXED
))
4526 /* Load from constant pool. */
4527 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
4533 /* The vector is initialized only with non-constants. */
4534 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, XVECEXP (vals
, 0, 0),
4535 XVECEXP (vals
, 0, 1));
4537 emit_move_insn (target
, new_rtx
);
4541 /* One field is non-constant and the other one is a constant. Load the
4542 constant from the constant pool and use ps_merge instruction to
4543 construct the whole vector. */
4544 op1
= XVECEXP (vals
, 0, 0);
4545 op2
= XVECEXP (vals
, 0, 1);
4547 constant_op
= (CONSTANT_P (op1
)) ? op1
: op2
;
4549 tmp
= gen_reg_rtx (GET_MODE (constant_op
));
4550 emit_move_insn (tmp
, constant_op
);
4552 if (CONSTANT_P (op1
))
4553 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, tmp
, op2
);
4555 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, op1
, tmp
);
4557 emit_move_insn (target
, new_rtx
);
4561 paired_expand_vector_move (rtx operands
[])
4563 rtx op0
= operands
[0], op1
= operands
[1];
4565 emit_move_insn (op0
, op1
);
4568 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
4569 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
4570 operands for the relation operation COND. This is a recursive
4574 paired_emit_vector_compare (enum rtx_code rcode
,
4575 rtx dest
, rtx op0
, rtx op1
,
4576 rtx cc_op0
, rtx cc_op1
)
4578 rtx tmp
= gen_reg_rtx (V2SFmode
);
4581 gcc_assert (TARGET_PAIRED_FLOAT
);
4582 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
4588 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
4592 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
4593 emit_insn (gen_selv2sf4 (dest
, tmp
, op0
, op1
, CONST0_RTX (SFmode
)));
4597 paired_emit_vector_compare (GE
, dest
, op0
, op1
, cc_op1
, cc_op0
);
4600 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
4603 tmp1
= gen_reg_rtx (V2SFmode
);
4604 max
= gen_reg_rtx (V2SFmode
);
4605 min
= gen_reg_rtx (V2SFmode
);
4606 gen_reg_rtx (V2SFmode
);
4608 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
4609 emit_insn (gen_selv2sf4
4610 (max
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
4611 emit_insn (gen_subv2sf3 (tmp
, cc_op1
, cc_op0
));
4612 emit_insn (gen_selv2sf4
4613 (min
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
4614 emit_insn (gen_subv2sf3 (tmp1
, min
, max
));
4615 emit_insn (gen_selv2sf4 (dest
, tmp1
, op0
, op1
, CONST0_RTX (SFmode
)));
4618 paired_emit_vector_compare (EQ
, dest
, op1
, op0
, cc_op0
, cc_op1
);
4621 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
4624 paired_emit_vector_compare (LT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
4627 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
4630 paired_emit_vector_compare (GT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
4639 /* Emit vector conditional expression.
4640 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
4641 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
4644 paired_emit_vector_cond_expr (rtx dest
, rtx op1
, rtx op2
,
4645 rtx cond
, rtx cc_op0
, rtx cc_op1
)
4647 enum rtx_code rcode
= GET_CODE (cond
);
4649 if (!TARGET_PAIRED_FLOAT
)
4652 paired_emit_vector_compare (rcode
, dest
, op1
, op2
, cc_op0
, cc_op1
);
4657 /* Initialize vector TARGET to VALS. */
4660 rs6000_expand_vector_init (rtx target
, rtx vals
)
4662 enum machine_mode mode
= GET_MODE (target
);
4663 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
4664 int n_elts
= GET_MODE_NUNITS (mode
);
4665 int n_var
= 0, one_var
= -1;
4666 bool all_same
= true, all_const_zero
= true;
4670 for (i
= 0; i
< n_elts
; ++i
)
4672 x
= XVECEXP (vals
, 0, i
);
4673 if (!(CONST_INT_P (x
)
4674 || GET_CODE (x
) == CONST_DOUBLE
4675 || GET_CODE (x
) == CONST_FIXED
))
4676 ++n_var
, one_var
= i
;
4677 else if (x
!= CONST0_RTX (inner_mode
))
4678 all_const_zero
= false;
4680 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
4686 rtx const_vec
= gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0));
4687 bool int_vector_p
= (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
);
4688 if ((int_vector_p
|| TARGET_VSX
) && all_const_zero
)
4690 /* Zero register. */
4691 emit_insn (gen_rtx_SET (VOIDmode
, target
,
4692 gen_rtx_XOR (mode
, target
, target
)));
4695 else if (int_vector_p
&& easy_vector_constant (const_vec
, mode
))
4697 /* Splat immediate. */
4698 emit_insn (gen_rtx_SET (VOIDmode
, target
, const_vec
));
4703 /* Load from constant pool. */
4704 emit_move_insn (target
, const_vec
);
4709 /* Double word values on VSX can use xxpermdi or lxvdsx. */
4710 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
4712 rtx op0
= XVECEXP (vals
, 0, 0);
4713 rtx op1
= XVECEXP (vals
, 0, 1);
4716 if (!MEM_P (op0
) && !REG_P (op0
))
4717 op0
= force_reg (inner_mode
, op0
);
4718 if (mode
== V2DFmode
)
4719 emit_insn (gen_vsx_splat_v2df (target
, op0
));
4721 emit_insn (gen_vsx_splat_v2di (target
, op0
));
4725 op0
= force_reg (inner_mode
, op0
);
4726 op1
= force_reg (inner_mode
, op1
);
4727 if (mode
== V2DFmode
)
4728 emit_insn (gen_vsx_concat_v2df (target
, op0
, op1
));
4730 emit_insn (gen_vsx_concat_v2di (target
, op0
, op1
));
4735 /* With single precision floating point on VSX, know that internally single
4736 precision is actually represented as a double, and either make 2 V2DF
4737 vectors, and convert these vectors to single precision, or do one
4738 conversion, and splat the result to the other elements. */
4739 if (mode
== V4SFmode
&& VECTOR_MEM_VSX_P (mode
))
4743 rtx freg
= gen_reg_rtx (V4SFmode
);
4744 rtx sreg
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
4746 emit_insn (gen_vsx_xscvdpsp_scalar (freg
, sreg
));
4747 emit_insn (gen_vsx_xxspltw_v4sf (target
, freg
, const0_rtx
));
4751 rtx dbl_even
= gen_reg_rtx (V2DFmode
);
4752 rtx dbl_odd
= gen_reg_rtx (V2DFmode
);
4753 rtx flt_even
= gen_reg_rtx (V4SFmode
);
4754 rtx flt_odd
= gen_reg_rtx (V4SFmode
);
4755 rtx op0
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
4756 rtx op1
= force_reg (SFmode
, XVECEXP (vals
, 0, 1));
4757 rtx op2
= force_reg (SFmode
, XVECEXP (vals
, 0, 2));
4758 rtx op3
= force_reg (SFmode
, XVECEXP (vals
, 0, 3));
4760 emit_insn (gen_vsx_concat_v2sf (dbl_even
, op0
, op1
));
4761 emit_insn (gen_vsx_concat_v2sf (dbl_odd
, op2
, op3
));
4762 emit_insn (gen_vsx_xvcvdpsp (flt_even
, dbl_even
));
4763 emit_insn (gen_vsx_xvcvdpsp (flt_odd
, dbl_odd
));
4764 rs6000_expand_extract_even (target
, flt_even
, flt_odd
);
4769 /* Store value to stack temp. Load vector element. Splat. However, splat
4770 of 64-bit items is not supported on Altivec. */
4771 if (all_same
&& GET_MODE_SIZE (inner_mode
) <= 4)
4773 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
), 0);
4774 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0),
4775 XVECEXP (vals
, 0, 0));
4776 x
= gen_rtx_UNSPEC (VOIDmode
,
4777 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
4778 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
4780 gen_rtx_SET (VOIDmode
,
4783 x
= gen_rtx_VEC_SELECT (inner_mode
, target
,
4784 gen_rtx_PARALLEL (VOIDmode
,
4785 gen_rtvec (1, const0_rtx
)));
4786 emit_insn (gen_rtx_SET (VOIDmode
, target
,
4787 gen_rtx_VEC_DUPLICATE (mode
, x
)));
4791 /* One field is non-constant. Load constant then overwrite
4795 rtx copy
= copy_rtx (vals
);
4797 /* Load constant part of vector, substitute neighboring value for
4799 XVECEXP (copy
, 0, one_var
) = XVECEXP (vals
, 0, (one_var
+ 1) % n_elts
);
4800 rs6000_expand_vector_init (target
, copy
);
4802 /* Insert variable. */
4803 rs6000_expand_vector_set (target
, XVECEXP (vals
, 0, one_var
), one_var
);
4807 /* Construct the vector in memory one field at a time
4808 and load the whole vector. */
4809 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
), 0);
4810 for (i
= 0; i
< n_elts
; i
++)
4811 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
4812 i
* GET_MODE_SIZE (inner_mode
)),
4813 XVECEXP (vals
, 0, i
));
4814 emit_move_insn (target
, mem
);
4817 /* Set field ELT of TARGET to VAL. */
4820 rs6000_expand_vector_set (rtx target
, rtx val
, int elt
)
4822 enum machine_mode mode
= GET_MODE (target
);
4823 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
4824 rtx reg
= gen_reg_rtx (mode
);
4826 int width
= GET_MODE_SIZE (inner_mode
);
4829 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
4831 rtx (*set_func
) (rtx
, rtx
, rtx
, rtx
)
4832 = ((mode
== V2DFmode
) ? gen_vsx_set_v2df
: gen_vsx_set_v2di
);
4833 emit_insn (set_func (target
, target
, val
, GEN_INT (elt
)));
4837 /* Load single variable value. */
4838 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
), 0);
4839 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0), val
);
4840 x
= gen_rtx_UNSPEC (VOIDmode
,
4841 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
4842 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
4844 gen_rtx_SET (VOIDmode
,
4848 /* Linear sequence. */
4849 mask
= gen_rtx_PARALLEL (V16QImode
, rtvec_alloc (16));
4850 for (i
= 0; i
< 16; ++i
)
4851 XVECEXP (mask
, 0, i
) = GEN_INT (i
);
4853 /* Set permute mask to insert element into target. */
4854 for (i
= 0; i
< width
; ++i
)
4855 XVECEXP (mask
, 0, elt
*width
+ i
)
4856 = GEN_INT (i
+ 0x10);
4857 x
= gen_rtx_CONST_VECTOR (V16QImode
, XVEC (mask
, 0));
4858 x
= gen_rtx_UNSPEC (mode
,
4859 gen_rtvec (3, target
, reg
,
4860 force_reg (V16QImode
, x
)),
4862 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
4865 /* Extract field ELT from VEC into TARGET. */
4868 rs6000_expand_vector_extract (rtx target
, rtx vec
, int elt
)
4870 enum machine_mode mode
= GET_MODE (vec
);
4871 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
4874 if (VECTOR_MEM_VSX_P (mode
))
4881 emit_insn (gen_vsx_extract_v2df (target
, vec
, GEN_INT (elt
)));
4884 emit_insn (gen_vsx_extract_v2di (target
, vec
, GEN_INT (elt
)));
4887 emit_insn (gen_vsx_extract_v4sf (target
, vec
, GEN_INT (elt
)));
4892 /* Allocate mode-sized buffer. */
4893 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
), 0);
4895 emit_move_insn (mem
, vec
);
4897 /* Add offset to field within buffer matching vector element. */
4898 mem
= adjust_address_nv (mem
, inner_mode
, elt
* GET_MODE_SIZE (inner_mode
));
4900 emit_move_insn (target
, adjust_address_nv (mem
, inner_mode
, 0));
4903 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
4904 implement ANDing by the mask IN. */
4906 build_mask64_2_operands (rtx in
, rtx
*out
)
4908 #if HOST_BITS_PER_WIDE_INT >= 64
4909 unsigned HOST_WIDE_INT c
, lsb
, m1
, m2
;
4912 gcc_assert (GET_CODE (in
) == CONST_INT
);
4917 /* Assume c initially something like 0x00fff000000fffff. The idea
4918 is to rotate the word so that the middle ^^^^^^ group of zeros
4919 is at the MS end and can be cleared with an rldicl mask. We then
4920 rotate back and clear off the MS ^^ group of zeros with a
4922 c
= ~c
; /* c == 0xff000ffffff00000 */
4923 lsb
= c
& -c
; /* lsb == 0x0000000000100000 */
4924 m1
= -lsb
; /* m1 == 0xfffffffffff00000 */
4925 c
= ~c
; /* c == 0x00fff000000fffff */
4926 c
&= -lsb
; /* c == 0x00fff00000000000 */
4927 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
4928 c
= ~c
; /* c == 0xff000fffffffffff */
4929 c
&= -lsb
; /* c == 0xff00000000000000 */
4931 while ((lsb
>>= 1) != 0)
4932 shift
++; /* shift == 44 on exit from loop */
4933 m1
<<= 64 - shift
; /* m1 == 0xffffff0000000000 */
4934 m1
= ~m1
; /* m1 == 0x000000ffffffffff */
4935 m2
= ~c
; /* m2 == 0x00ffffffffffffff */
4939 /* Assume c initially something like 0xff000f0000000000. The idea
4940 is to rotate the word so that the ^^^ middle group of zeros
4941 is at the LS end and can be cleared with an rldicr mask. We then
4942 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
4944 lsb
= c
& -c
; /* lsb == 0x0000010000000000 */
4945 m2
= -lsb
; /* m2 == 0xffffff0000000000 */
4946 c
= ~c
; /* c == 0x00fff0ffffffffff */
4947 c
&= -lsb
; /* c == 0x00fff00000000000 */
4948 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
4949 c
= ~c
; /* c == 0xff000fffffffffff */
4950 c
&= -lsb
; /* c == 0xff00000000000000 */
4952 while ((lsb
>>= 1) != 0)
4953 shift
++; /* shift == 44 on exit from loop */
4954 m1
= ~c
; /* m1 == 0x00ffffffffffffff */
4955 m1
>>= shift
; /* m1 == 0x0000000000000fff */
4956 m1
= ~m1
; /* m1 == 0xfffffffffffff000 */
4959 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
4960 masks will be all 1's. We are guaranteed more than one transition. */
4961 out
[0] = GEN_INT (64 - shift
);
4962 out
[1] = GEN_INT (m1
);
4963 out
[2] = GEN_INT (shift
);
4964 out
[3] = GEN_INT (m2
);
4972 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
4975 invalid_e500_subreg (rtx op
, enum machine_mode mode
)
4977 if (TARGET_E500_DOUBLE
)
4979 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
4980 subreg:TI and reg:TF. Decimal float modes are like integer
4981 modes (only low part of each register used) for this
4983 if (GET_CODE (op
) == SUBREG
4984 && (mode
== SImode
|| mode
== DImode
|| mode
== TImode
4985 || mode
== DDmode
|| mode
== TDmode
)
4986 && REG_P (SUBREG_REG (op
))
4987 && (GET_MODE (SUBREG_REG (op
)) == DFmode
4988 || GET_MODE (SUBREG_REG (op
)) == TFmode
))
4991 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
4993 if (GET_CODE (op
) == SUBREG
4994 && (mode
== DFmode
|| mode
== TFmode
)
4995 && REG_P (SUBREG_REG (op
))
4996 && (GET_MODE (SUBREG_REG (op
)) == DImode
4997 || GET_MODE (SUBREG_REG (op
)) == TImode
4998 || GET_MODE (SUBREG_REG (op
)) == DDmode
4999 || GET_MODE (SUBREG_REG (op
)) == TDmode
))
5004 && GET_CODE (op
) == SUBREG
5006 && REG_P (SUBREG_REG (op
))
5007 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op
))))
5013 /* AIX increases natural record alignment to doubleword if the first
5014 field is an FP double while the FP fields remain word aligned. */
5017 rs6000_special_round_type_align (tree type
, unsigned int computed
,
5018 unsigned int specified
)
5020 unsigned int align
= MAX (computed
, specified
);
5021 tree field
= TYPE_FIELDS (type
);
5023 /* Skip all non field decls */
5024 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
5025 field
= DECL_CHAIN (field
);
5027 if (field
!= NULL
&& field
!= type
)
5029 type
= TREE_TYPE (field
);
5030 while (TREE_CODE (type
) == ARRAY_TYPE
)
5031 type
= TREE_TYPE (type
);
5033 if (type
!= error_mark_node
&& TYPE_MODE (type
) == DFmode
)
5034 align
= MAX (align
, 64);
5040 /* Darwin increases record alignment to the natural alignment of
5044 darwin_rs6000_special_round_type_align (tree type
, unsigned int computed
,
5045 unsigned int specified
)
5047 unsigned int align
= MAX (computed
, specified
);
5049 if (TYPE_PACKED (type
))
5052 /* Find the first field, looking down into aggregates. */
5054 tree field
= TYPE_FIELDS (type
);
5055 /* Skip all non field decls */
5056 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
5057 field
= DECL_CHAIN (field
);
5060 /* A packed field does not contribute any extra alignment. */
5061 if (DECL_PACKED (field
))
5063 type
= TREE_TYPE (field
);
5064 while (TREE_CODE (type
) == ARRAY_TYPE
)
5065 type
= TREE_TYPE (type
);
5066 } while (AGGREGATE_TYPE_P (type
));
5068 if (! AGGREGATE_TYPE_P (type
) && type
!= error_mark_node
)
5069 align
= MAX (align
, TYPE_ALIGN (type
));
5074 /* Return 1 for an operand in small memory on V.4/eabi. */
5077 small_data_operand (rtx op ATTRIBUTE_UNUSED
,
5078 enum machine_mode mode ATTRIBUTE_UNUSED
)
5083 if (rs6000_sdata
== SDATA_NONE
|| rs6000_sdata
== SDATA_DATA
)
5086 if (DEFAULT_ABI
!= ABI_V4
)
5089 /* Vector and float memory instructions have a limited offset on the
5090 SPE, so using a vector or float variable directly as an operand is
5093 && (SPE_VECTOR_MODE (mode
) || FLOAT_MODE_P (mode
)))
5096 if (GET_CODE (op
) == SYMBOL_REF
)
5099 else if (GET_CODE (op
) != CONST
5100 || GET_CODE (XEXP (op
, 0)) != PLUS
5101 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
5102 || GET_CODE (XEXP (XEXP (op
, 0), 1)) != CONST_INT
)
5107 rtx sum
= XEXP (op
, 0);
5108 HOST_WIDE_INT summand
;
5110 /* We have to be careful here, because it is the referenced address
5111 that must be 32k from _SDA_BASE_, not just the symbol. */
5112 summand
= INTVAL (XEXP (sum
, 1));
5113 if (summand
< 0 || summand
> g_switch_value
)
5116 sym_ref
= XEXP (sum
, 0);
5119 return SYMBOL_REF_SMALL_P (sym_ref
);
5125 /* Return true if either operand is a general purpose register. */
5128 gpr_or_gpr_p (rtx op0
, rtx op1
)
5130 return ((REG_P (op0
) && INT_REGNO_P (REGNO (op0
)))
5131 || (REG_P (op1
) && INT_REGNO_P (REGNO (op1
))));
5135 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
5138 reg_offset_addressing_ok_p (enum machine_mode mode
)
5148 /* AltiVec/VSX vector modes. Only reg+reg addressing is valid. */
5149 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
5157 /* Paired vector modes. Only reg+reg addressing is valid. */
5158 if (TARGET_PAIRED_FLOAT
)
5170 virtual_stack_registers_memory_p (rtx op
)
5174 if (GET_CODE (op
) == REG
)
5175 regnum
= REGNO (op
);
5177 else if (GET_CODE (op
) == PLUS
5178 && GET_CODE (XEXP (op
, 0)) == REG
5179 && GET_CODE (XEXP (op
, 1)) == CONST_INT
)
5180 regnum
= REGNO (XEXP (op
, 0));
5185 return (regnum
>= FIRST_VIRTUAL_REGISTER
5186 && regnum
<= LAST_VIRTUAL_POINTER_REGISTER
);
5189 /* Return true if memory accesses to OP are known to never straddle
5193 offsettable_ok_by_alignment (rtx op
, HOST_WIDE_INT offset
,
5194 enum machine_mode mode
)
5197 unsigned HOST_WIDE_INT dsize
, dalign
;
5199 if (GET_CODE (op
) != SYMBOL_REF
)
5202 decl
= SYMBOL_REF_DECL (op
);
5205 if (GET_MODE_SIZE (mode
) == 0)
5208 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
5209 replacing memory addresses with an anchor plus offset. We
5210 could find the decl by rummaging around in the block->objects
5211 VEC for the given offset but that seems like too much work. */
5213 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op
)
5214 && SYMBOL_REF_ANCHOR_P (op
)
5215 && SYMBOL_REF_BLOCK (op
) != NULL
)
5217 struct object_block
*block
= SYMBOL_REF_BLOCK (op
);
5218 HOST_WIDE_INT lsb
, mask
;
5220 /* Given the alignment of the block.. */
5221 dalign
= block
->alignment
;
5222 mask
= dalign
/ BITS_PER_UNIT
- 1;
5224 /* ..and the combined offset of the anchor and any offset
5225 to this block object.. */
5226 offset
+= SYMBOL_REF_BLOCK_OFFSET (op
);
5227 lsb
= offset
& -offset
;
5229 /* ..find how many bits of the alignment we know for the
5234 return dalign
>= GET_MODE_SIZE (mode
);
5239 if (TREE_CODE (decl
) == FUNCTION_DECL
)
5242 if (!DECL_SIZE_UNIT (decl
))
5245 if (!host_integerp (DECL_SIZE_UNIT (decl
), 1))
5248 dsize
= tree_low_cst (DECL_SIZE_UNIT (decl
), 1);
5252 dalign
= DECL_ALIGN_UNIT (decl
);
5253 return dalign
>= dsize
;
5256 type
= TREE_TYPE (decl
);
5258 if (TREE_CODE (decl
) == STRING_CST
)
5259 dsize
= TREE_STRING_LENGTH (decl
);
5260 else if (TYPE_SIZE_UNIT (type
)
5261 && host_integerp (TYPE_SIZE_UNIT (type
), 1))
5262 dsize
= tree_low_cst (TYPE_SIZE_UNIT (type
), 1);
5268 dalign
= TYPE_ALIGN (type
);
5269 if (CONSTANT_CLASS_P (decl
))
5270 dalign
= CONSTANT_ALIGNMENT (decl
, dalign
);
5272 dalign
= DATA_ALIGNMENT (decl
, dalign
);
5273 dalign
/= BITS_PER_UNIT
;
5274 return dalign
>= dsize
;
5278 constant_pool_expr_p (rtx op
)
5282 split_const (op
, &base
, &offset
);
5283 return (GET_CODE (base
) == SYMBOL_REF
5284 && CONSTANT_POOL_ADDRESS_P (base
)
5285 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base
), Pmode
));
5288 static rtx tocrel_base
, tocrel_offset
;
5291 toc_relative_expr_p (rtx op
)
5293 if (GET_CODE (op
) != CONST
)
5296 split_const (op
, &tocrel_base
, &tocrel_offset
);
5297 return (GET_CODE (tocrel_base
) == UNSPEC
5298 && XINT (tocrel_base
, 1) == UNSPEC_TOCREL
);
5301 /* Return true if X is a constant pool address, and also for cmodel=medium
5302 if X is a toc-relative address known to be offsettable within MODE. */
5305 legitimate_constant_pool_address_p (const_rtx x
, enum machine_mode mode
,
5309 && (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == LO_SUM
)
5310 && GET_CODE (XEXP (x
, 0)) == REG
5311 && (REGNO (XEXP (x
, 0)) == TOC_REGISTER
5312 || ((TARGET_MINIMAL_TOC
5313 || TARGET_CMODEL
!= CMODEL_SMALL
)
5314 && INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
)))
5315 && toc_relative_expr_p (XEXP (x
, 1))
5316 && (TARGET_CMODEL
!= CMODEL_MEDIUM
5317 || constant_pool_expr_p (XVECEXP (tocrel_base
, 0, 0))
5319 || offsettable_ok_by_alignment (XVECEXP (tocrel_base
, 0, 0),
5320 INTVAL (tocrel_offset
), mode
)));
5324 legitimate_small_data_p (enum machine_mode mode
, rtx x
)
5326 return (DEFAULT_ABI
== ABI_V4
5327 && !flag_pic
&& !TARGET_TOC
5328 && (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
)
5329 && small_data_operand (x
, mode
));
5332 /* SPE offset addressing is limited to 5-bits worth of double words. */
5333 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
5336 rs6000_legitimate_offset_address_p (enum machine_mode mode
, rtx x
, int strict
)
5338 unsigned HOST_WIDE_INT offset
, extra
;
5340 if (GET_CODE (x
) != PLUS
)
5342 if (GET_CODE (XEXP (x
, 0)) != REG
)
5344 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
5346 if (!reg_offset_addressing_ok_p (mode
))
5347 return virtual_stack_registers_memory_p (x
);
5348 if (legitimate_constant_pool_address_p (x
, mode
, strict
))
5350 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
5353 offset
= INTVAL (XEXP (x
, 1));
5361 /* SPE vector modes. */
5362 return SPE_CONST_OFFSET_OK (offset
);
5365 if (TARGET_E500_DOUBLE
)
5366 return SPE_CONST_OFFSET_OK (offset
);
5368 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
5370 if (VECTOR_MEM_VSX_P (DFmode
))
5375 /* On e500v2, we may have:
5377 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
5379 Which gets addressed with evldd instructions. */
5380 if (TARGET_E500_DOUBLE
)
5381 return SPE_CONST_OFFSET_OK (offset
);
5383 if (mode
== DFmode
|| mode
== DDmode
|| !TARGET_POWERPC64
)
5385 else if (offset
& 3)
5390 if (TARGET_E500_DOUBLE
)
5391 return (SPE_CONST_OFFSET_OK (offset
)
5392 && SPE_CONST_OFFSET_OK (offset
+ 8));
5396 if (mode
== TFmode
|| mode
== TDmode
|| !TARGET_POWERPC64
)
5398 else if (offset
& 3)
5409 return offset
< 0x10000 - extra
;
5413 legitimate_indexed_address_p (rtx x
, int strict
)
5417 if (GET_CODE (x
) != PLUS
)
5423 /* Recognize the rtl generated by reload which we know will later be
5424 replaced with proper base and index regs. */
5426 && reload_in_progress
5427 && (REG_P (op0
) || GET_CODE (op0
) == PLUS
)
5431 return (REG_P (op0
) && REG_P (op1
)
5432 && ((INT_REG_OK_FOR_BASE_P (op0
, strict
)
5433 && INT_REG_OK_FOR_INDEX_P (op1
, strict
))
5434 || (INT_REG_OK_FOR_BASE_P (op1
, strict
)
5435 && INT_REG_OK_FOR_INDEX_P (op0
, strict
))));
5439 avoiding_indexed_address_p (enum machine_mode mode
)
5441 /* Avoid indexed addressing for modes that have non-indexed
5442 load/store instruction forms. */
5443 return (TARGET_AVOID_XFORM
&& VECTOR_MEM_NONE_P (mode
));
5447 legitimate_indirect_address_p (rtx x
, int strict
)
5449 return GET_CODE (x
) == REG
&& INT_REG_OK_FOR_BASE_P (x
, strict
);
5453 macho_lo_sum_memory_operand (rtx x
, enum machine_mode mode
)
5455 if (!TARGET_MACHO
|| !flag_pic
5456 || mode
!= SImode
|| GET_CODE (x
) != MEM
)
5460 if (GET_CODE (x
) != LO_SUM
)
5462 if (GET_CODE (XEXP (x
, 0)) != REG
)
5464 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 0))
5468 return CONSTANT_P (x
);
5472 legitimate_lo_sum_address_p (enum machine_mode mode
, rtx x
, int strict
)
5474 if (GET_CODE (x
) != LO_SUM
)
5476 if (GET_CODE (XEXP (x
, 0)) != REG
)
5478 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
5480 /* Restrict addressing for DI because of our SUBREG hackery. */
5481 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
5482 || mode
== DDmode
|| mode
== TDmode
5487 if (TARGET_ELF
|| TARGET_MACHO
)
5489 if (DEFAULT_ABI
!= ABI_AIX
&& DEFAULT_ABI
!= ABI_DARWIN
&& flag_pic
)
5493 if (GET_MODE_NUNITS (mode
) != 1)
5495 if (GET_MODE_BITSIZE (mode
) > 64
5496 || (GET_MODE_BITSIZE (mode
) > 32 && !TARGET_POWERPC64
5497 && !(TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
5498 && (mode
== DFmode
|| mode
== DDmode
))))
5501 return CONSTANT_P (x
);
5508 /* Try machine-dependent ways of modifying an illegitimate address
5509 to be legitimate. If we find one, return the new, valid address.
5510 This is used from only one place: `memory_address' in explow.c.
5512 OLDX is the address as it was before break_out_memory_refs was
5513 called. In some cases it is useful to look at this to decide what
5516 It is always safe for this function to do nothing. It exists to
5517 recognize opportunities to optimize the output.
5519 On RS/6000, first check for the sum of a register with a constant
5520 integer that is out of range. If so, generate code to add the
5521 constant with the low-order 16 bits masked to the register and force
5522 this result into another register (this can be done with `cau').
5523 Then generate an address of REG+(CONST&0xffff), allowing for the
5524 possibility of bit 16 being a one.
5526 Then check for the sum of a register and something not constant, try to
5527 load the other things into a register and return the sum. */
5530 rs6000_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
5531 enum machine_mode mode
)
5533 unsigned int extra
= 0;
5535 if (!reg_offset_addressing_ok_p (mode
))
5537 if (virtual_stack_registers_memory_p (x
))
5540 /* In theory we should not be seeing addresses of the form reg+0,
5541 but just in case it is generated, optimize it away. */
5542 if (GET_CODE (x
) == PLUS
&& XEXP (x
, 1) == const0_rtx
)
5543 return force_reg (Pmode
, XEXP (x
, 0));
5545 /* Make sure both operands are registers. */
5546 else if (GET_CODE (x
) == PLUS
)
5547 return gen_rtx_PLUS (Pmode
,
5548 force_reg (Pmode
, XEXP (x
, 0)),
5549 force_reg (Pmode
, XEXP (x
, 1)));
5551 return force_reg (Pmode
, x
);
5553 if (GET_CODE (x
) == SYMBOL_REF
)
5555 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
5557 return rs6000_legitimize_tls_address (x
, model
);
5567 if (!TARGET_POWERPC64
)
5575 extra
= TARGET_POWERPC64
? 8 : 12;
5581 if (GET_CODE (x
) == PLUS
5582 && GET_CODE (XEXP (x
, 0)) == REG
5583 && GET_CODE (XEXP (x
, 1)) == CONST_INT
5584 && ((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 1)) + 0x8000)
5586 && !((TARGET_POWERPC64
5587 && (mode
== DImode
|| mode
== TImode
)
5588 && (INTVAL (XEXP (x
, 1)) & 3) != 0)
5589 || SPE_VECTOR_MODE (mode
)
5590 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
5591 || mode
== DImode
|| mode
== DDmode
5592 || mode
== TDmode
))))
5594 HOST_WIDE_INT high_int
, low_int
;
5596 low_int
= ((INTVAL (XEXP (x
, 1)) & 0xffff) ^ 0x8000) - 0x8000;
5597 if (low_int
>= 0x8000 - extra
)
5599 high_int
= INTVAL (XEXP (x
, 1)) - low_int
;
5600 sum
= force_operand (gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
5601 GEN_INT (high_int
)), 0);
5602 return plus_constant (sum
, low_int
);
5604 else if (GET_CODE (x
) == PLUS
5605 && GET_CODE (XEXP (x
, 0)) == REG
5606 && GET_CODE (XEXP (x
, 1)) != CONST_INT
5607 && GET_MODE_NUNITS (mode
) == 1
5608 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
5610 || ((mode
!= DImode
&& mode
!= DFmode
&& mode
!= DDmode
)
5611 || (TARGET_E500_DOUBLE
&& mode
!= DDmode
)))
5612 && (TARGET_POWERPC64
|| mode
!= DImode
)
5613 && !avoiding_indexed_address_p (mode
)
5618 return gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
5619 force_reg (Pmode
, force_operand (XEXP (x
, 1), 0)));
5621 else if (SPE_VECTOR_MODE (mode
)
5622 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
5623 || mode
== DDmode
|| mode
== TDmode
5624 || mode
== DImode
)))
5628 /* We accept [reg + reg] and [reg + OFFSET]. */
5630 if (GET_CODE (x
) == PLUS
)
5632 rtx op1
= XEXP (x
, 0);
5633 rtx op2
= XEXP (x
, 1);
5636 op1
= force_reg (Pmode
, op1
);
5638 if (GET_CODE (op2
) != REG
5639 && (GET_CODE (op2
) != CONST_INT
5640 || !SPE_CONST_OFFSET_OK (INTVAL (op2
))
5641 || (GET_MODE_SIZE (mode
) > 8
5642 && !SPE_CONST_OFFSET_OK (INTVAL (op2
) + 8))))
5643 op2
= force_reg (Pmode
, op2
);
5645 /* We can't always do [reg + reg] for these, because [reg +
5646 reg + offset] is not a legitimate addressing mode. */
5647 y
= gen_rtx_PLUS (Pmode
, op1
, op2
);
5649 if ((GET_MODE_SIZE (mode
) > 8 || mode
== DDmode
) && REG_P (op2
))
5650 return force_reg (Pmode
, y
);
5655 return force_reg (Pmode
, x
);
5661 && GET_CODE (x
) != CONST_INT
5662 && GET_CODE (x
) != CONST_DOUBLE
5664 && GET_MODE_NUNITS (mode
) == 1
5665 && (GET_MODE_BITSIZE (mode
) <= 32
5666 || ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
5667 && (mode
== DFmode
|| mode
== DDmode
))))
5669 rtx reg
= gen_reg_rtx (Pmode
);
5670 emit_insn (gen_elf_high (reg
, x
));
5671 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
5673 else if (TARGET_MACHO
&& TARGET_32BIT
&& TARGET_NO_TOC
5676 && ! MACHO_DYNAMIC_NO_PIC_P
5678 && GET_CODE (x
) != CONST_INT
5679 && GET_CODE (x
) != CONST_DOUBLE
5681 && GET_MODE_NUNITS (mode
) == 1
5682 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
5683 || (mode
!= DFmode
&& mode
!= DDmode
))
5687 rtx reg
= gen_reg_rtx (Pmode
);
5688 emit_insn (gen_macho_high (reg
, x
));
5689 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
5692 && GET_CODE (x
) == SYMBOL_REF
5693 && constant_pool_expr_p (x
)
5694 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), Pmode
))
5696 rtx reg
= TARGET_CMODEL
!= CMODEL_SMALL
? gen_reg_rtx (Pmode
) : NULL_RTX
;
5697 return create_TOC_reference (x
, reg
);
5703 /* Debug version of rs6000_legitimize_address. */
5705 rs6000_debug_legitimize_address (rtx x
, rtx oldx
, enum machine_mode mode
)
5711 ret
= rs6000_legitimize_address (x
, oldx
, mode
);
5712 insns
= get_insns ();
5718 "\nrs6000_legitimize_address: mode %s, old code %s, "
5719 "new code %s, modified\n",
5720 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)),
5721 GET_RTX_NAME (GET_CODE (ret
)));
5723 fprintf (stderr
, "Original address:\n");
5726 fprintf (stderr
, "oldx:\n");
5729 fprintf (stderr
, "New address:\n");
5734 fprintf (stderr
, "Insns added:\n");
5735 debug_rtx_list (insns
, 20);
5741 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
5742 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)));
5753 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
5754 We need to emit DTP-relative relocations. */
5757 rs6000_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
5762 fputs ("\t.long\t", file
);
5765 fputs (DOUBLE_INT_ASM_OP
, file
);
5770 output_addr_const (file
, x
);
5771 fputs ("@dtprel+0x8000", file
);
5774 /* In the name of slightly smaller debug output, and to cater to
5775 general assembler lossage, recognize various UNSPEC sequences
5776 and turn them back into a direct symbol reference. */
5779 rs6000_delegitimize_address (rtx orig_x
)
5783 orig_x
= delegitimize_mem_from_attrs (orig_x
);
5788 if (GET_CODE (x
) == (TARGET_CMODEL
!= CMODEL_SMALL
? LO_SUM
: PLUS
)
5789 && GET_CODE (XEXP (x
, 1)) == CONST
)
5791 rtx offset
= NULL_RTX
;
5793 y
= XEXP (XEXP (x
, 1), 0);
5794 if (GET_CODE (y
) == PLUS
5795 && GET_MODE (y
) == Pmode
5796 && CONST_INT_P (XEXP (y
, 1)))
5798 offset
= XEXP (y
, 1);
5801 if (GET_CODE (y
) == UNSPEC
5802 && XINT (y
, 1) == UNSPEC_TOCREL
5803 && ((GET_CODE (XEXP (x
, 0)) == REG
5804 && (REGNO (XEXP (x
, 0)) == TOC_REGISTER
5805 || TARGET_MINIMAL_TOC
5806 || TARGET_CMODEL
!= CMODEL_SMALL
))
5807 || (TARGET_CMODEL
!= CMODEL_SMALL
5808 && GET_CODE (XEXP (x
, 0)) == CONST
5809 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
5810 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == REG
5811 && REGNO (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == TOC_REGISTER
5812 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == HIGH
5813 && rtx_equal_p (XEXP (x
, 1),
5814 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 1), 0)))))
5816 y
= XVECEXP (y
, 0, 0);
5817 if (offset
!= NULL_RTX
)
5818 y
= gen_rtx_PLUS (Pmode
, y
, offset
);
5819 if (!MEM_P (orig_x
))
5822 return replace_equiv_address_nv (orig_x
, y
);
5827 && GET_CODE (orig_x
) == LO_SUM
5828 && GET_CODE (XEXP (orig_x
, 1)) == CONST
)
5830 y
= XEXP (XEXP (orig_x
, 1), 0);
5831 if (GET_CODE (y
) == UNSPEC
5832 && XINT (y
, 1) == UNSPEC_MACHOPIC_OFFSET
)
5833 return XVECEXP (y
, 0, 0);
5839 /* Return true if X shouldn't be emitted into the debug info.
5840 The linker doesn't like .toc section references from
5841 .debug_* sections, so reject .toc section symbols. */
5844 rs6000_const_not_ok_for_debug_p (rtx x
)
5846 if (GET_CODE (x
) == SYMBOL_REF
5847 && CONSTANT_POOL_ADDRESS_P (x
))
5849 rtx c
= get_pool_constant (x
);
5850 enum machine_mode cmode
= get_pool_mode (x
);
5851 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c
, cmode
))
5858 /* Construct the SYMBOL_REF for the tls_get_addr function. */
5860 static GTY(()) rtx rs6000_tls_symbol
;
5862 rs6000_tls_get_addr (void)
5864 if (!rs6000_tls_symbol
)
5865 rs6000_tls_symbol
= init_one_libfunc ("__tls_get_addr");
5867 return rs6000_tls_symbol
;
5870 /* Construct the SYMBOL_REF for TLS GOT references. */
5872 static GTY(()) rtx rs6000_got_symbol
;
5874 rs6000_got_sym (void)
5876 if (!rs6000_got_symbol
)
5878 rs6000_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
5879 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_LOCAL
;
5880 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_EXTERNAL
;
5883 return rs6000_got_symbol
;
5886 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
5887 this (thread-local) address. */
5890 rs6000_legitimize_tls_address (rtx addr
, enum tls_model model
)
5894 dest
= gen_reg_rtx (Pmode
);
5895 if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 16)
5901 tlsreg
= gen_rtx_REG (Pmode
, 13);
5902 insn
= gen_tls_tprel_64 (dest
, tlsreg
, addr
);
5906 tlsreg
= gen_rtx_REG (Pmode
, 2);
5907 insn
= gen_tls_tprel_32 (dest
, tlsreg
, addr
);
5911 else if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 32)
5915 tmp
= gen_reg_rtx (Pmode
);
5918 tlsreg
= gen_rtx_REG (Pmode
, 13);
5919 insn
= gen_tls_tprel_ha_64 (tmp
, tlsreg
, addr
);
5923 tlsreg
= gen_rtx_REG (Pmode
, 2);
5924 insn
= gen_tls_tprel_ha_32 (tmp
, tlsreg
, addr
);
5928 insn
= gen_tls_tprel_lo_64 (dest
, tmp
, addr
);
5930 insn
= gen_tls_tprel_lo_32 (dest
, tmp
, addr
);
5935 rtx r3
, got
, tga
, tmp1
, tmp2
, call_insn
;
5937 /* We currently use relocations like @got@tlsgd for tls, which
5938 means the linker will handle allocation of tls entries, placing
5939 them in the .got section. So use a pointer to the .got section,
5940 not one to secondary TOC sections used by 64-bit -mminimal-toc,
5941 or to secondary GOT sections used by 32-bit -fPIC. */
5943 got
= gen_rtx_REG (Pmode
, 2);
5947 got
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
5950 rtx gsym
= rs6000_got_sym ();
5951 got
= gen_reg_rtx (Pmode
);
5953 rs6000_emit_move (got
, gsym
, Pmode
);
5958 tmp1
= gen_reg_rtx (Pmode
);
5959 tmp2
= gen_reg_rtx (Pmode
);
5960 mem
= gen_const_mem (Pmode
, tmp1
);
5961 lab
= gen_label_rtx ();
5962 emit_insn (gen_load_toc_v4_PIC_1b (gsym
, lab
));
5963 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
5964 if (TARGET_LINK_STACK
)
5965 emit_insn (gen_addsi3 (tmp1
, tmp1
, GEN_INT (4)));
5966 emit_move_insn (tmp2
, mem
);
5967 last
= emit_insn (gen_addsi3 (got
, tmp1
, tmp2
));
5968 set_unique_reg_note (last
, REG_EQUAL
, gsym
);
5973 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
)
5975 tga
= rs6000_tls_get_addr ();
5976 emit_library_call_value (tga
, dest
, LCT_CONST
, Pmode
,
5977 1, const0_rtx
, Pmode
);
5979 r3
= gen_rtx_REG (Pmode
, 3);
5980 if (DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
5981 insn
= gen_tls_gd_aix64 (r3
, got
, addr
, tga
, const0_rtx
);
5982 else if (DEFAULT_ABI
== ABI_AIX
&& !TARGET_64BIT
)
5983 insn
= gen_tls_gd_aix32 (r3
, got
, addr
, tga
, const0_rtx
);
5984 else if (DEFAULT_ABI
== ABI_V4
)
5985 insn
= gen_tls_gd_sysvsi (r3
, got
, addr
, tga
, const0_rtx
);
5988 call_insn
= last_call_insn ();
5989 PATTERN (call_insn
) = insn
;
5990 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
5991 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
5992 pic_offset_table_rtx
);
5994 else if (model
== TLS_MODEL_LOCAL_DYNAMIC
)
5996 tga
= rs6000_tls_get_addr ();
5997 tmp1
= gen_reg_rtx (Pmode
);
5998 emit_library_call_value (tga
, tmp1
, LCT_CONST
, Pmode
,
5999 1, const0_rtx
, Pmode
);
6001 r3
= gen_rtx_REG (Pmode
, 3);
6002 if (DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
6003 insn
= gen_tls_ld_aix64 (r3
, got
, tga
, const0_rtx
);
6004 else if (DEFAULT_ABI
== ABI_AIX
&& !TARGET_64BIT
)
6005 insn
= gen_tls_ld_aix32 (r3
, got
, tga
, const0_rtx
);
6006 else if (DEFAULT_ABI
== ABI_V4
)
6007 insn
= gen_tls_ld_sysvsi (r3
, got
, tga
, const0_rtx
);
6010 call_insn
= last_call_insn ();
6011 PATTERN (call_insn
) = insn
;
6012 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
6013 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
6014 pic_offset_table_rtx
);
6016 if (rs6000_tls_size
== 16)
6019 insn
= gen_tls_dtprel_64 (dest
, tmp1
, addr
);
6021 insn
= gen_tls_dtprel_32 (dest
, tmp1
, addr
);
6023 else if (rs6000_tls_size
== 32)
6025 tmp2
= gen_reg_rtx (Pmode
);
6027 insn
= gen_tls_dtprel_ha_64 (tmp2
, tmp1
, addr
);
6029 insn
= gen_tls_dtprel_ha_32 (tmp2
, tmp1
, addr
);
6032 insn
= gen_tls_dtprel_lo_64 (dest
, tmp2
, addr
);
6034 insn
= gen_tls_dtprel_lo_32 (dest
, tmp2
, addr
);
6038 tmp2
= gen_reg_rtx (Pmode
);
6040 insn
= gen_tls_got_dtprel_64 (tmp2
, got
, addr
);
6042 insn
= gen_tls_got_dtprel_32 (tmp2
, got
, addr
);
6044 insn
= gen_rtx_SET (Pmode
, dest
,
6045 gen_rtx_PLUS (Pmode
, tmp2
, tmp1
));
6051 /* IE, or 64-bit offset LE. */
6052 tmp2
= gen_reg_rtx (Pmode
);
6054 insn
= gen_tls_got_tprel_64 (tmp2
, got
, addr
);
6056 insn
= gen_tls_got_tprel_32 (tmp2
, got
, addr
);
6059 insn
= gen_tls_tls_64 (dest
, tmp2
, addr
);
6061 insn
= gen_tls_tls_32 (dest
, tmp2
, addr
);
6069 /* Return 1 if X contains a thread-local symbol. */
6072 rs6000_tls_referenced_p (rtx x
)
6074 if (! TARGET_HAVE_TLS
)
6077 return for_each_rtx (&x
, &rs6000_tls_symbol_ref_1
, 0);
6080 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
6083 rs6000_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
6085 if (GET_CODE (x
) == CONST
6086 && GET_CODE (XEXP (x
, 0)) == PLUS
6087 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == HIGH
)
6090 return rs6000_tls_referenced_p (x
);
6093 /* Return 1 if *X is a thread-local symbol. This is the same as
6094 rs6000_tls_symbol_ref except for the type of the unused argument. */
6097 rs6000_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
6099 return RS6000_SYMBOL_REF_TLS_P (*x
);
6102 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
6103 replace the input X, or the original X if no replacement is called for.
6104 The output parameter *WIN is 1 if the calling macro should goto WIN,
6107 For RS/6000, we wish to handle large displacements off a base
6108 register by splitting the addend across an addiu/addis and the mem insn.
6109 This cuts number of extra insns needed from 3 to 1.
6111 On Darwin, we use this to generate code for floating point constants.
6112 A movsf_low is generated so we wind up with 2 instructions rather than 3.
6113 The Darwin code is inside #if TARGET_MACHO because only then are the
6114 machopic_* functions defined. */
6116 rs6000_legitimize_reload_address (rtx x
, enum machine_mode mode
,
6117 int opnum
, int type
,
6118 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
6120 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
6122 /* Nasty hack for vsx_splat_V2DF/V2DI load from mem, which takes a
6123 DFmode/DImode MEM. */
6126 && ((mode
== DFmode
&& recog_data
.operand_mode
[0] == V2DFmode
)
6127 || (mode
== DImode
&& recog_data
.operand_mode
[0] == V2DImode
)))
6128 reg_offset_p
= false;
6130 /* We must recognize output that we have already generated ourselves. */
6131 if (GET_CODE (x
) == PLUS
6132 && GET_CODE (XEXP (x
, 0)) == PLUS
6133 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
6134 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6135 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6137 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6138 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
6139 opnum
, (enum reload_type
)type
);
6144 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
6145 if (GET_CODE (x
) == LO_SUM
6146 && GET_CODE (XEXP (x
, 0)) == HIGH
)
6148 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6149 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
6150 opnum
, (enum reload_type
)type
);
6156 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
6157 && GET_CODE (x
) == LO_SUM
6158 && GET_CODE (XEXP (x
, 0)) == PLUS
6159 && XEXP (XEXP (x
, 0), 0) == pic_offset_table_rtx
6160 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == HIGH
6161 && XEXP (XEXP (XEXP (x
, 0), 1), 0) == XEXP (x
, 1)
6162 && machopic_operand_p (XEXP (x
, 1)))
6164 /* Result of previous invocation of this function on Darwin
6165 floating point constant. */
6166 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6167 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
6168 opnum
, (enum reload_type
)type
);
6174 if (TARGET_CMODEL
!= CMODEL_SMALL
6175 && GET_CODE (x
) == LO_SUM
6176 && GET_CODE (XEXP (x
, 0)) == PLUS
6177 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
6178 && REGNO (XEXP (XEXP (x
, 0), 0)) == TOC_REGISTER
6179 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST
6180 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 0)) == HIGH
6181 && GET_CODE (XEXP (x
, 1)) == CONST
6182 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == UNSPEC
6183 && XINT (XEXP (XEXP (x
, 1), 0), 1) == UNSPEC_TOCREL
6184 && rtx_equal_p (XEXP (XEXP (XEXP (XEXP (x
, 0), 1), 0), 0), XEXP (x
, 1)))
6186 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6187 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
6188 opnum
, (enum reload_type
) type
);
6193 /* Force ld/std non-word aligned offset into base register by wrapping
6195 if (GET_CODE (x
) == PLUS
6196 && GET_CODE (XEXP (x
, 0)) == REG
6197 && REGNO (XEXP (x
, 0)) < 32
6198 && INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 1)
6199 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6201 && (INTVAL (XEXP (x
, 1)) & 3) != 0
6202 && VECTOR_MEM_NONE_P (mode
)
6203 && GET_MODE_SIZE (mode
) >= UNITS_PER_WORD
6204 && TARGET_POWERPC64
)
6206 x
= gen_rtx_PLUS (GET_MODE (x
), x
, GEN_INT (0));
6207 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6208 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
6209 opnum
, (enum reload_type
) type
);
6214 if (GET_CODE (x
) == PLUS
6215 && GET_CODE (XEXP (x
, 0)) == REG
6216 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
6217 && INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 1)
6218 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6220 && !SPE_VECTOR_MODE (mode
)
6221 && !(TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
6222 || mode
== DDmode
|| mode
== TDmode
6224 && VECTOR_MEM_NONE_P (mode
))
6226 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
6227 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
6229 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
6231 /* Check for 32-bit overflow. */
6232 if (high
+ low
!= val
)
6238 /* Reload the high part into a base reg; leave the low part
6239 in the mem directly. */
6241 x
= gen_rtx_PLUS (GET_MODE (x
),
6242 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
6246 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6247 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
6248 opnum
, (enum reload_type
)type
);
6253 if (GET_CODE (x
) == SYMBOL_REF
6255 && VECTOR_MEM_NONE_P (mode
)
6256 && !SPE_VECTOR_MODE (mode
)
6258 && DEFAULT_ABI
== ABI_DARWIN
6259 && (flag_pic
|| MACHO_DYNAMIC_NO_PIC_P
)
6260 && machopic_symbol_defined_p (x
)
6262 && DEFAULT_ABI
== ABI_V4
6265 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
6266 The same goes for DImode without 64-bit gprs and DFmode and DDmode
6270 && (mode
!= DImode
|| TARGET_POWERPC64
)
6271 && ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_POWERPC64
6272 || (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)))
6277 rtx offset
= machopic_gen_offset (x
);
6278 x
= gen_rtx_LO_SUM (GET_MODE (x
),
6279 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
6280 gen_rtx_HIGH (Pmode
, offset
)), offset
);
6284 x
= gen_rtx_LO_SUM (GET_MODE (x
),
6285 gen_rtx_HIGH (Pmode
, x
), x
);
6287 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6288 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
6289 opnum
, (enum reload_type
)type
);
6294 /* Reload an offset address wrapped by an AND that represents the
6295 masking of the lower bits. Strip the outer AND and let reload
6296 convert the offset address into an indirect address. For VSX,
6297 force reload to create the address with an AND in a separate
6298 register, because we can't guarantee an altivec register will
6300 if (VECTOR_MEM_ALTIVEC_P (mode
)
6301 && GET_CODE (x
) == AND
6302 && GET_CODE (XEXP (x
, 0)) == PLUS
6303 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
6304 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6305 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6306 && INTVAL (XEXP (x
, 1)) == -16)
6315 && GET_CODE (x
) == SYMBOL_REF
6316 && constant_pool_expr_p (x
)
6317 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), mode
))
6319 x
= create_TOC_reference (x
, NULL_RTX
);
6320 if (TARGET_CMODEL
!= CMODEL_SMALL
)
6321 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
6322 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
6323 opnum
, (enum reload_type
) type
);
6331 /* Debug version of rs6000_legitimize_reload_address. */
6333 rs6000_debug_legitimize_reload_address (rtx x
, enum machine_mode mode
,
6334 int opnum
, int type
,
6335 int ind_levels
, int *win
)
6337 rtx ret
= rs6000_legitimize_reload_address (x
, mode
, opnum
, type
,
6340 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
6341 "type = %d, ind_levels = %d, win = %d, original addr:\n",
6342 GET_MODE_NAME (mode
), opnum
, type
, ind_levels
, *win
);
6346 fprintf (stderr
, "Same address returned\n");
6348 fprintf (stderr
, "NULL returned\n");
6351 fprintf (stderr
, "New address:\n");
6358 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
6359 that is a valid memory address for an instruction.
6360 The MODE argument is the machine mode for the MEM expression
6361 that wants to use this address.
6363 On the RS/6000, there are four valid address: a SYMBOL_REF that
6364 refers to a constant pool entry of an address (or the sum of it
6365 plus a constant), a short (16-bit signed) constant plus a register,
6366 the sum of two registers, or a register indirect, possibly with an
6367 auto-increment. For DFmode, DDmode and DImode with a constant plus
6368 register, we must ensure that both words are addressable or PowerPC64
6369 with offset word aligned.
6371 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
6372 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
6373 because adjacent memory cells are accessed by adding word-sized offsets
6374 during assembly output. */
6376 rs6000_legitimate_address_p (enum machine_mode mode
, rtx x
, bool reg_ok_strict
)
6378 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
6380 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
6381 if (VECTOR_MEM_ALTIVEC_P (mode
)
6382 && GET_CODE (x
) == AND
6383 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6384 && INTVAL (XEXP (x
, 1)) == -16)
6387 if (RS6000_SYMBOL_REF_TLS_P (x
))
6389 if (legitimate_indirect_address_p (x
, reg_ok_strict
))
6391 if ((GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
6392 && !VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
)
6393 && !SPE_VECTOR_MODE (mode
)
6396 /* Restrict addressing for DI because of our SUBREG hackery. */
6397 && !(TARGET_E500_DOUBLE
6398 && (mode
== DFmode
|| mode
== DDmode
|| mode
== DImode
))
6400 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
))
6402 if (virtual_stack_registers_memory_p (x
))
6404 if (reg_offset_p
&& legitimate_small_data_p (mode
, x
))
6407 && legitimate_constant_pool_address_p (x
, mode
, reg_ok_strict
))
6409 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
6412 && GET_CODE (x
) == PLUS
6413 && GET_CODE (XEXP (x
, 0)) == REG
6414 && (XEXP (x
, 0) == virtual_stack_vars_rtx
6415 || XEXP (x
, 0) == arg_pointer_rtx
)
6416 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6418 if (rs6000_legitimate_offset_address_p (mode
, x
, reg_ok_strict
))
6423 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
6425 || (mode
!= DFmode
&& mode
!= DDmode
)
6426 || (TARGET_E500_DOUBLE
&& mode
!= DDmode
))
6427 && (TARGET_POWERPC64
|| mode
!= DImode
)
6428 && !avoiding_indexed_address_p (mode
)
6429 && legitimate_indexed_address_p (x
, reg_ok_strict
))
6431 if (GET_CODE (x
) == PRE_MODIFY
6435 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
6437 || ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_E500_DOUBLE
))
6438 && (TARGET_POWERPC64
|| mode
!= DImode
)
6439 && !VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
)
6440 && !SPE_VECTOR_MODE (mode
)
6441 /* Restrict addressing for DI because of our SUBREG hackery. */
6442 && !(TARGET_E500_DOUBLE
6443 && (mode
== DFmode
|| mode
== DDmode
|| mode
== DImode
))
6445 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
)
6446 && (rs6000_legitimate_offset_address_p (mode
, XEXP (x
, 1), reg_ok_strict
)
6447 || (!avoiding_indexed_address_p (mode
)
6448 && legitimate_indexed_address_p (XEXP (x
, 1), reg_ok_strict
)))
6449 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
6451 if (reg_offset_p
&& legitimate_lo_sum_address_p (mode
, x
, reg_ok_strict
))
6456 /* Debug version of rs6000_legitimate_address_p. */
6458 rs6000_debug_legitimate_address_p (enum machine_mode mode
, rtx x
,
6461 bool ret
= rs6000_legitimate_address_p (mode
, x
, reg_ok_strict
);
6463 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
6464 "strict = %d, code = %s\n",
6465 ret
? "true" : "false",
6466 GET_MODE_NAME (mode
),
6468 GET_RTX_NAME (GET_CODE (x
)));
6474 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
6477 rs6000_mode_dependent_address_p (const_rtx addr
)
6479 return rs6000_mode_dependent_address_ptr (addr
);
6482 /* Go to LABEL if ADDR (a legitimate address expression)
6483 has an effect that depends on the machine mode it is used for.
6485 On the RS/6000 this is true of all integral offsets (since AltiVec
6486 and VSX modes don't allow them) or is a pre-increment or decrement.
6488 ??? Except that due to conceptual problems in offsettable_address_p
6489 we can't really report the problems of integral offsets. So leave
6490 this assuming that the adjustable offset must be valid for the
6491 sub-words of a TFmode operand, which is what we had before. */
6494 rs6000_mode_dependent_address (const_rtx addr
)
6496 switch (GET_CODE (addr
))
6499 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
6500 is considered a legitimate address before reload, so there
6501 are no offset restrictions in that case. Note that this
6502 condition is safe in strict mode because any address involving
6503 virtual_stack_vars_rtx or arg_pointer_rtx would already have
6504 been rejected as illegitimate. */
6505 if (XEXP (addr
, 0) != virtual_stack_vars_rtx
6506 && XEXP (addr
, 0) != arg_pointer_rtx
6507 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
6509 unsigned HOST_WIDE_INT val
= INTVAL (XEXP (addr
, 1));
6510 return val
+ 12 + 0x8000 >= 0x10000;
6515 /* Anything in the constant pool is sufficiently aligned that
6516 all bytes have the same high part address. */
6517 return !legitimate_constant_pool_address_p (addr
, QImode
, false);
6519 /* Auto-increment cases are now treated generically in recog.c. */
6521 return TARGET_UPDATE
;
6523 /* AND is only allowed in Altivec loads. */
6534 /* Debug version of rs6000_mode_dependent_address. */
6536 rs6000_debug_mode_dependent_address (const_rtx addr
)
6538 bool ret
= rs6000_mode_dependent_address (addr
);
6540 fprintf (stderr
, "\nrs6000_mode_dependent_address: ret = %s\n",
6541 ret
? "true" : "false");
6547 /* Implement FIND_BASE_TERM. */
6550 rs6000_find_base_term (rtx op
)
6554 split_const (op
, &base
, &offset
);
6555 if (GET_CODE (base
) == UNSPEC
)
6556 switch (XINT (base
, 1))
6559 case UNSPEC_MACHOPIC_OFFSET
:
6560 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
6561 for aliasing purposes. */
6562 return XVECEXP (base
, 0, 0);
6568 /* More elaborate version of recog's offsettable_memref_p predicate
6569 that works around the ??? note of rs6000_mode_dependent_address.
6570 In particular it accepts
6572 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
6574 in 32-bit mode, that the recog predicate rejects. */
6577 rs6000_offsettable_memref_p (rtx op
)
6582 /* First mimic offsettable_memref_p. */
6583 if (offsettable_address_p (1, GET_MODE (op
), XEXP (op
, 0)))
6586 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
6587 the latter predicate knows nothing about the mode of the memory
6588 reference and, therefore, assumes that it is the largest supported
6589 mode (TFmode). As a consequence, legitimate offsettable memory
6590 references are rejected. rs6000_legitimate_offset_address_p contains
6591 the correct logic for the PLUS case of rs6000_mode_dependent_address. */
6592 return rs6000_legitimate_offset_address_p (GET_MODE (op
), XEXP (op
, 0), 1);
6595 /* Change register usage conditional on target flags. */
6597 rs6000_conditional_register_usage (void)
6601 if (TARGET_DEBUG_TARGET
)
6602 fprintf (stderr
, "rs6000_conditional_register_usage called\n");
6604 /* Set MQ register fixed (already call_used) if not POWER
6605 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
6610 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
6612 fixed_regs
[13] = call_used_regs
[13]
6613 = call_really_used_regs
[13] = 1;
6615 /* Conditionally disable FPRs. */
6616 if (TARGET_SOFT_FLOAT
|| !TARGET_FPRS
)
6617 for (i
= 32; i
< 64; i
++)
6618 fixed_regs
[i
] = call_used_regs
[i
]
6619 = call_really_used_regs
[i
] = 1;
6621 /* The TOC register is not killed across calls in a way that is
6622 visible to the compiler. */
6623 if (DEFAULT_ABI
== ABI_AIX
)
6624 call_really_used_regs
[2] = 0;
6626 if (DEFAULT_ABI
== ABI_V4
6627 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
6629 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
6631 if (DEFAULT_ABI
== ABI_V4
6632 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
6634 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
6635 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
6636 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
6638 if (DEFAULT_ABI
== ABI_DARWIN
6639 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
6640 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
6641 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
6642 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
6644 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
)
6645 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
6646 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
6650 global_regs
[SPEFSCR_REGNO
] = 1;
6651 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
6652 registers in prologues and epilogues. We no longer use r14
6653 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
6654 pool for link-compatibility with older versions of GCC. Once
6655 "old" code has died out, we can return r14 to the allocation
6658 = call_used_regs
[14]
6659 = call_really_used_regs
[14] = 1;
6662 if (!TARGET_ALTIVEC
&& !TARGET_VSX
)
6664 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
6665 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
6666 call_really_used_regs
[VRSAVE_REGNO
] = 1;
6669 if (TARGET_ALTIVEC
|| TARGET_VSX
)
6670 global_regs
[VSCR_REGNO
] = 1;
6672 if (TARGET_ALTIVEC_ABI
)
6674 for (i
= FIRST_ALTIVEC_REGNO
; i
< FIRST_ALTIVEC_REGNO
+ 20; ++i
)
6675 call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
6677 /* AIX reserves VR20:31 in non-extended ABI mode. */
6679 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
< FIRST_ALTIVEC_REGNO
+ 32; ++i
)
6680 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
6684 /* Try to output insns to set TARGET equal to the constant C if it can
6685 be done in less than N insns. Do all computations in MODE.
6686 Returns the place where the output has been placed if it can be
6687 done and the insns have been emitted. If it would take more than N
6688 insns, zero is returned and no insns and emitted. */
6691 rs6000_emit_set_const (rtx dest
, enum machine_mode mode
,
6692 rtx source
, int n ATTRIBUTE_UNUSED
)
6694 rtx result
, insn
, set
;
6695 HOST_WIDE_INT c0
, c1
;
6702 dest
= gen_reg_rtx (mode
);
6703 emit_insn (gen_rtx_SET (VOIDmode
, dest
, source
));
6707 result
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (SImode
);
6709 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (result
),
6710 GEN_INT (INTVAL (source
)
6711 & (~ (HOST_WIDE_INT
) 0xffff))));
6712 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
6713 gen_rtx_IOR (SImode
, copy_rtx (result
),
6714 GEN_INT (INTVAL (source
) & 0xffff))));
6719 switch (GET_CODE (source
))
6722 c0
= INTVAL (source
);
6727 #if HOST_BITS_PER_WIDE_INT >= 64
6728 c0
= CONST_DOUBLE_LOW (source
);
6731 c0
= CONST_DOUBLE_LOW (source
);
6732 c1
= CONST_DOUBLE_HIGH (source
);
6740 result
= rs6000_emit_set_long_const (dest
, c0
, c1
);
6747 insn
= get_last_insn ();
6748 set
= single_set (insn
);
6749 if (! CONSTANT_P (SET_SRC (set
)))
6750 set_unique_reg_note (insn
, REG_EQUAL
, source
);
6755 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
6756 fall back to a straight forward decomposition. We do this to avoid
6757 exponential run times encountered when looking for longer sequences
6758 with rs6000_emit_set_const. */
6760 rs6000_emit_set_long_const (rtx dest
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
6762 if (!TARGET_POWERPC64
)
6764 rtx operand1
, operand2
;
6766 operand1
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
== 0,
6768 operand2
= operand_subword_force (copy_rtx (dest
), WORDS_BIG_ENDIAN
!= 0,
6770 emit_move_insn (operand1
, GEN_INT (c1
));
6771 emit_move_insn (operand2
, GEN_INT (c2
));
6775 HOST_WIDE_INT ud1
, ud2
, ud3
, ud4
;
6778 ud2
= (c1
& 0xffff0000) >> 16;
6779 #if HOST_BITS_PER_WIDE_INT >= 64
6783 ud4
= (c2
& 0xffff0000) >> 16;
6785 if ((ud4
== 0xffff && ud3
== 0xffff && ud2
== 0xffff && (ud1
& 0x8000))
6786 || (ud4
== 0 && ud3
== 0 && ud2
== 0 && ! (ud1
& 0x8000)))
6789 emit_move_insn (dest
, GEN_INT (((ud1
^ 0x8000) - 0x8000)));
6791 emit_move_insn (dest
, GEN_INT (ud1
));
6794 else if ((ud4
== 0xffff && ud3
== 0xffff && (ud2
& 0x8000))
6795 || (ud4
== 0 && ud3
== 0 && ! (ud2
& 0x8000)))
6798 emit_move_insn (dest
, GEN_INT (((ud2
<< 16) ^ 0x80000000)
6801 emit_move_insn (dest
, GEN_INT (ud2
<< 16));
6803 emit_move_insn (copy_rtx (dest
),
6804 gen_rtx_IOR (DImode
, copy_rtx (dest
),
6807 else if (ud3
== 0 && ud4
== 0)
6809 gcc_assert (ud2
& 0x8000);
6810 emit_move_insn (dest
, GEN_INT (((ud2
<< 16) ^ 0x80000000)
6813 emit_move_insn (copy_rtx (dest
),
6814 gen_rtx_IOR (DImode
, copy_rtx (dest
),
6816 emit_move_insn (copy_rtx (dest
),
6817 gen_rtx_ZERO_EXTEND (DImode
,
6818 gen_lowpart (SImode
,
6821 else if ((ud4
== 0xffff && (ud3
& 0x8000))
6822 || (ud4
== 0 && ! (ud3
& 0x8000)))
6825 emit_move_insn (dest
, GEN_INT (((ud3
<< 16) ^ 0x80000000)
6828 emit_move_insn (dest
, GEN_INT (ud3
<< 16));
6831 emit_move_insn (copy_rtx (dest
),
6832 gen_rtx_IOR (DImode
, copy_rtx (dest
),
6834 emit_move_insn (copy_rtx (dest
),
6835 gen_rtx_ASHIFT (DImode
, copy_rtx (dest
),
6838 emit_move_insn (copy_rtx (dest
),
6839 gen_rtx_IOR (DImode
, copy_rtx (dest
),
6845 emit_move_insn (dest
, GEN_INT (((ud4
<< 16) ^ 0x80000000)
6848 emit_move_insn (dest
, GEN_INT (ud4
<< 16));
6851 emit_move_insn (copy_rtx (dest
),
6852 gen_rtx_IOR (DImode
, copy_rtx (dest
),
6855 emit_move_insn (copy_rtx (dest
),
6856 gen_rtx_ASHIFT (DImode
, copy_rtx (dest
),
6859 emit_move_insn (copy_rtx (dest
),
6860 gen_rtx_IOR (DImode
, copy_rtx (dest
),
6861 GEN_INT (ud2
<< 16)));
6863 emit_move_insn (copy_rtx (dest
),
6864 gen_rtx_IOR (DImode
, copy_rtx (dest
), GEN_INT (ud1
)));
6870 /* Helper for the following. Get rid of [r+r] memory refs
6871 in cases where it won't work (TImode, TFmode, TDmode). */
6874 rs6000_eliminate_indexed_memrefs (rtx operands
[2])
6876 if (reload_in_progress
)
6879 if (GET_CODE (operands
[0]) == MEM
6880 && GET_CODE (XEXP (operands
[0], 0)) != REG
6881 && ! legitimate_constant_pool_address_p (XEXP (operands
[0], 0),
6882 GET_MODE (operands
[0]), false))
6884 = replace_equiv_address (operands
[0],
6885 copy_addr_to_reg (XEXP (operands
[0], 0)));
6887 if (GET_CODE (operands
[1]) == MEM
6888 && GET_CODE (XEXP (operands
[1], 0)) != REG
6889 && ! legitimate_constant_pool_address_p (XEXP (operands
[1], 0),
6890 GET_MODE (operands
[1]), false))
6892 = replace_equiv_address (operands
[1],
6893 copy_addr_to_reg (XEXP (operands
[1], 0)));
6896 /* Emit a move from SOURCE to DEST in mode MODE. */
6898 rs6000_emit_move (rtx dest
, rtx source
, enum machine_mode mode
)
6902 operands
[1] = source
;
6904 if (TARGET_DEBUG_ADDR
)
6907 "\nrs6000_emit_move: mode = %s, reload_in_progress = %d, "
6908 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
6909 GET_MODE_NAME (mode
),
6912 can_create_pseudo_p ());
6914 fprintf (stderr
, "source:\n");
6918 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
6919 if (GET_CODE (operands
[1]) == CONST_DOUBLE
6920 && ! FLOAT_MODE_P (mode
)
6921 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
6923 /* FIXME. This should never happen. */
6924 /* Since it seems that it does, do the safe thing and convert
6926 operands
[1] = gen_int_mode (CONST_DOUBLE_LOW (operands
[1]), mode
);
6928 gcc_assert (GET_CODE (operands
[1]) != CONST_DOUBLE
6929 || FLOAT_MODE_P (mode
)
6930 || ((CONST_DOUBLE_HIGH (operands
[1]) != 0
6931 || CONST_DOUBLE_LOW (operands
[1]) < 0)
6932 && (CONST_DOUBLE_HIGH (operands
[1]) != -1
6933 || CONST_DOUBLE_LOW (operands
[1]) >= 0)));
6935 /* Check if GCC is setting up a block move that will end up using FP
6936 registers as temporaries. We must make sure this is acceptable. */
6937 if (GET_CODE (operands
[0]) == MEM
6938 && GET_CODE (operands
[1]) == MEM
6940 && (SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[0]))
6941 || SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[1])))
6942 && ! (SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[0]) > 32
6943 ? 32 : MEM_ALIGN (operands
[0])))
6944 || SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[1]) > 32
6946 : MEM_ALIGN (operands
[1]))))
6947 && ! MEM_VOLATILE_P (operands
[0])
6948 && ! MEM_VOLATILE_P (operands
[1]))
6950 emit_move_insn (adjust_address (operands
[0], SImode
, 0),
6951 adjust_address (operands
[1], SImode
, 0));
6952 emit_move_insn (adjust_address (copy_rtx (operands
[0]), SImode
, 4),
6953 adjust_address (copy_rtx (operands
[1]), SImode
, 4));
6957 if (can_create_pseudo_p () && GET_CODE (operands
[0]) == MEM
6958 && !gpc_reg_operand (operands
[1], mode
))
6959 operands
[1] = force_reg (mode
, operands
[1]);
6961 if (mode
== SFmode
&& ! TARGET_POWERPC
6962 && TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
6963 && GET_CODE (operands
[0]) == MEM
)
6967 if (reload_in_progress
|| reload_completed
)
6968 regnum
= true_regnum (operands
[1]);
6969 else if (GET_CODE (operands
[1]) == REG
)
6970 regnum
= REGNO (operands
[1]);
6974 /* If operands[1] is a register, on POWER it may have
6975 double-precision data in it, so truncate it to single
6977 if (FP_REGNO_P (regnum
) || regnum
>= FIRST_PSEUDO_REGISTER
)
6980 newreg
= (!can_create_pseudo_p () ? copy_rtx (operands
[1])
6981 : gen_reg_rtx (mode
));
6982 emit_insn (gen_aux_truncdfsf2 (newreg
, operands
[1]));
6983 operands
[1] = newreg
;
6987 /* Recognize the case where operand[1] is a reference to thread-local
6988 data and load its address to a register. */
6989 if (rs6000_tls_referenced_p (operands
[1]))
6991 enum tls_model model
;
6992 rtx tmp
= operands
[1];
6995 if (GET_CODE (tmp
) == CONST
&& GET_CODE (XEXP (tmp
, 0)) == PLUS
)
6997 addend
= XEXP (XEXP (tmp
, 0), 1);
6998 tmp
= XEXP (XEXP (tmp
, 0), 0);
7001 gcc_assert (GET_CODE (tmp
) == SYMBOL_REF
);
7002 model
= SYMBOL_REF_TLS_MODEL (tmp
);
7003 gcc_assert (model
!= 0);
7005 tmp
= rs6000_legitimize_tls_address (tmp
, model
);
7008 tmp
= gen_rtx_PLUS (mode
, tmp
, addend
);
7009 tmp
= force_operand (tmp
, operands
[0]);
7014 /* Handle the case where reload calls us with an invalid address. */
7015 if (reload_in_progress
&& mode
== Pmode
7016 && (! general_operand (operands
[1], mode
)
7017 || ! nonimmediate_operand (operands
[0], mode
)))
7020 /* 128-bit constant floating-point values on Darwin should really be
7021 loaded as two parts. */
7022 if (!TARGET_IEEEQUAD
&& TARGET_LONG_DOUBLE_128
7023 && mode
== TFmode
&& GET_CODE (operands
[1]) == CONST_DOUBLE
)
7025 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
, 0),
7026 simplify_gen_subreg (DFmode
, operands
[1], mode
, 0),
7028 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
,
7029 GET_MODE_SIZE (DFmode
)),
7030 simplify_gen_subreg (DFmode
, operands
[1], mode
,
7031 GET_MODE_SIZE (DFmode
)),
7036 if (reload_in_progress
&& cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
7037 cfun
->machine
->sdmode_stack_slot
=
7038 eliminate_regs (cfun
->machine
->sdmode_stack_slot
, VOIDmode
, NULL_RTX
);
7040 if (reload_in_progress
7042 && MEM_P (operands
[0])
7043 && rtx_equal_p (operands
[0], cfun
->machine
->sdmode_stack_slot
)
7044 && REG_P (operands
[1]))
7046 if (FP_REGNO_P (REGNO (operands
[1])))
7048 rtx mem
= adjust_address_nv (operands
[0], DDmode
, 0);
7049 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
7050 emit_insn (gen_movsd_store (mem
, operands
[1]));
7052 else if (INT_REGNO_P (REGNO (operands
[1])))
7054 rtx mem
= adjust_address_nv (operands
[0], mode
, 4);
7055 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
7056 emit_insn (gen_movsd_hardfloat (mem
, operands
[1]));
7062 if (reload_in_progress
7064 && REG_P (operands
[0])
7065 && MEM_P (operands
[1])
7066 && rtx_equal_p (operands
[1], cfun
->machine
->sdmode_stack_slot
))
7068 if (FP_REGNO_P (REGNO (operands
[0])))
7070 rtx mem
= adjust_address_nv (operands
[1], DDmode
, 0);
7071 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
7072 emit_insn (gen_movsd_load (operands
[0], mem
));
7074 else if (INT_REGNO_P (REGNO (operands
[0])))
7076 rtx mem
= adjust_address_nv (operands
[1], mode
, 4);
7077 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
7078 emit_insn (gen_movsd_hardfloat (operands
[0], mem
));
7085 /* FIXME: In the long term, this switch statement should go away
7086 and be replaced by a sequence of tests based on things like
7092 if (CONSTANT_P (operands
[1])
7093 && GET_CODE (operands
[1]) != CONST_INT
)
7094 operands
[1] = force_const_mem (mode
, operands
[1]);
7099 rs6000_eliminate_indexed_memrefs (operands
);
7106 if (CONSTANT_P (operands
[1])
7107 && ! easy_fp_constant (operands
[1], mode
))
7108 operands
[1] = force_const_mem (mode
, operands
[1]);
7121 if (CONSTANT_P (operands
[1])
7122 && !easy_vector_constant (operands
[1], mode
))
7123 operands
[1] = force_const_mem (mode
, operands
[1]);
7128 /* Use default pattern for address of ELF small data */
7131 && DEFAULT_ABI
== ABI_V4
7132 && (GET_CODE (operands
[1]) == SYMBOL_REF
7133 || GET_CODE (operands
[1]) == CONST
)
7134 && small_data_operand (operands
[1], mode
))
7136 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
7140 if (DEFAULT_ABI
== ABI_V4
7141 && mode
== Pmode
&& mode
== SImode
7142 && flag_pic
== 1 && got_operand (operands
[1], mode
))
7144 emit_insn (gen_movsi_got (operands
[0], operands
[1]));
7148 if ((TARGET_ELF
|| DEFAULT_ABI
== ABI_DARWIN
)
7152 && CONSTANT_P (operands
[1])
7153 && GET_CODE (operands
[1]) != HIGH
7154 && GET_CODE (operands
[1]) != CONST_INT
)
7156 rtx target
= (!can_create_pseudo_p ()
7158 : gen_reg_rtx (mode
));
7160 /* If this is a function address on -mcall-aixdesc,
7161 convert it to the address of the descriptor. */
7162 if (DEFAULT_ABI
== ABI_AIX
7163 && GET_CODE (operands
[1]) == SYMBOL_REF
7164 && XSTR (operands
[1], 0)[0] == '.')
7166 const char *name
= XSTR (operands
[1], 0);
7168 while (*name
== '.')
7170 new_ref
= gen_rtx_SYMBOL_REF (Pmode
, name
);
7171 CONSTANT_POOL_ADDRESS_P (new_ref
)
7172 = CONSTANT_POOL_ADDRESS_P (operands
[1]);
7173 SYMBOL_REF_FLAGS (new_ref
) = SYMBOL_REF_FLAGS (operands
[1]);
7174 SYMBOL_REF_USED (new_ref
) = SYMBOL_REF_USED (operands
[1]);
7175 SYMBOL_REF_DATA (new_ref
) = SYMBOL_REF_DATA (operands
[1]);
7176 operands
[1] = new_ref
;
7179 if (DEFAULT_ABI
== ABI_DARWIN
)
7182 if (MACHO_DYNAMIC_NO_PIC_P
)
7184 /* Take care of any required data indirection. */
7185 operands
[1] = rs6000_machopic_legitimize_pic_address (
7186 operands
[1], mode
, operands
[0]);
7187 if (operands
[0] != operands
[1])
7188 emit_insn (gen_rtx_SET (VOIDmode
,
7189 operands
[0], operands
[1]));
7193 emit_insn (gen_macho_high (target
, operands
[1]));
7194 emit_insn (gen_macho_low (operands
[0], target
, operands
[1]));
7198 emit_insn (gen_elf_high (target
, operands
[1]));
7199 emit_insn (gen_elf_low (operands
[0], target
, operands
[1]));
7203 /* If this is a SYMBOL_REF that refers to a constant pool entry,
7204 and we have put it in the TOC, we just need to make a TOC-relative
7207 && GET_CODE (operands
[1]) == SYMBOL_REF
7208 && constant_pool_expr_p (operands
[1])
7209 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands
[1]),
7210 get_pool_mode (operands
[1])))
7211 || (TARGET_CMODEL
== CMODEL_MEDIUM
7212 && GET_CODE (operands
[1]) == SYMBOL_REF
7213 && !CONSTANT_POOL_ADDRESS_P (operands
[1])
7214 && SYMBOL_REF_LOCAL_P (operands
[1])))
7217 if (TARGET_CMODEL
!= CMODEL_SMALL
)
7219 if (can_create_pseudo_p ())
7220 reg
= gen_reg_rtx (Pmode
);
7224 operands
[1] = create_TOC_reference (operands
[1], reg
);
7226 else if (mode
== Pmode
7227 && CONSTANT_P (operands
[1])
7228 && GET_CODE (operands
[1]) != HIGH
7229 && !(TARGET_CMODEL
!= CMODEL_SMALL
7230 && GET_CODE (operands
[1]) == CONST
7231 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
7232 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == HIGH
)
7233 && ((GET_CODE (operands
[1]) != CONST_INT
7234 && ! easy_fp_constant (operands
[1], mode
))
7235 || (GET_CODE (operands
[1]) == CONST_INT
7236 && (num_insns_constant (operands
[1], mode
)
7237 > (TARGET_CMODEL
!= CMODEL_SMALL
? 3 : 2)))
7238 || (GET_CODE (operands
[0]) == REG
7239 && FP_REGNO_P (REGNO (operands
[0]))))
7240 && ! legitimate_constant_pool_address_p (operands
[1], mode
,
7242 && ! toc_relative_expr_p (operands
[1])
7243 && (TARGET_CMODEL
== CMODEL_SMALL
7244 || can_create_pseudo_p ()
7245 || (REG_P (operands
[0])
7246 && INT_REG_OK_FOR_BASE_P (operands
[0], true))))
7250 /* Darwin uses a special PIC legitimizer. */
7251 if (DEFAULT_ABI
== ABI_DARWIN
&& MACHOPIC_INDIRECT
)
7254 rs6000_machopic_legitimize_pic_address (operands
[1], mode
,
7256 if (operands
[0] != operands
[1])
7257 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
7262 /* If we are to limit the number of things we put in the TOC and
7263 this is a symbol plus a constant we can add in one insn,
7264 just put the symbol in the TOC and add the constant. Don't do
7265 this if reload is in progress. */
7266 if (GET_CODE (operands
[1]) == CONST
7267 && TARGET_NO_SUM_IN_TOC
&& ! reload_in_progress
7268 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
7269 && add_operand (XEXP (XEXP (operands
[1], 0), 1), mode
)
7270 && (GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
7271 || GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == SYMBOL_REF
)
7272 && ! side_effects_p (operands
[0]))
7275 force_const_mem (mode
, XEXP (XEXP (operands
[1], 0), 0));
7276 rtx other
= XEXP (XEXP (operands
[1], 0), 1);
7278 sym
= force_reg (mode
, sym
);
7279 emit_insn (gen_add3_insn (operands
[0], sym
, other
));
7283 operands
[1] = force_const_mem (mode
, operands
[1]);
7286 && GET_CODE (XEXP (operands
[1], 0)) == SYMBOL_REF
7287 && constant_pool_expr_p (XEXP (operands
[1], 0))
7288 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
7289 get_pool_constant (XEXP (operands
[1], 0)),
7290 get_pool_mode (XEXP (operands
[1], 0))))
7294 if (TARGET_CMODEL
!= CMODEL_SMALL
)
7296 if (can_create_pseudo_p ())
7297 reg
= gen_reg_rtx (Pmode
);
7301 tocref
= create_TOC_reference (XEXP (operands
[1], 0), reg
);
7302 operands
[1] = gen_const_mem (mode
, tocref
);
7303 set_mem_alias_set (operands
[1], get_TOC_alias_set ());
7309 rs6000_eliminate_indexed_memrefs (operands
);
7313 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
7315 gen_rtx_SET (VOIDmode
,
7316 operands
[0], operands
[1]),
7317 gen_rtx_CLOBBER (VOIDmode
,
7318 gen_rtx_SCRATCH (SImode
)))));
7324 fatal_insn ("bad move", gen_rtx_SET (VOIDmode
, dest
, source
));
7327 /* Above, we may have called force_const_mem which may have returned
7328 an invalid address. If we can, fix this up; otherwise, reload will
7329 have to deal with it. */
7330 if (GET_CODE (operands
[1]) == MEM
&& ! reload_in_progress
)
7331 operands
[1] = validize_mem (operands
[1]);
7334 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
7337 /* Nonzero if we can use a floating-point register to pass this arg. */
7338 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
7339 (SCALAR_FLOAT_MODE_P (MODE) \
7340 && (CUM)->fregno <= FP_ARG_MAX_REG \
7341 && TARGET_HARD_FLOAT && TARGET_FPRS)
7343 /* Nonzero if we can use an AltiVec register to pass this arg. */
7344 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
7345 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
7346 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
7347 && TARGET_ALTIVEC_ABI \
7350 /* Return a nonzero value to say to return the function value in
7351 memory, just as large structures are always returned. TYPE will be
7352 the data type of the value, and FNTYPE will be the type of the
7353 function doing the returning, or @code{NULL} for libcalls.
7355 The AIX ABI for the RS/6000 specifies that all structures are
7356 returned in memory. The Darwin ABI does the same.
7358 For the Darwin 64 Bit ABI, a function result can be returned in
7359 registers or in memory, depending on the size of the return data
7360 type. If it is returned in registers, the value occupies the same
7361 registers as it would if it were the first and only function
7362 argument. Otherwise, the function places its result in memory at
7363 the location pointed to by GPR3.
7365 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
7366 but a draft put them in memory, and GCC used to implement the draft
7367 instead of the final standard. Therefore, aix_struct_return
7368 controls this instead of DEFAULT_ABI; V.4 targets needing backward
7369 compatibility can change DRAFT_V4_STRUCT_RET to override the
7370 default, and -m switches get the final word. See
7371 rs6000_option_override_internal for more details.
7373 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
7374 long double support is enabled. These values are returned in memory.
7376 int_size_in_bytes returns -1 for variable size objects, which go in
7377 memory always. The cast to unsigned makes -1 > 8. */
7380 rs6000_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
7382 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
7384 && rs6000_darwin64_abi
7385 && TREE_CODE (type
) == RECORD_TYPE
7386 && int_size_in_bytes (type
) > 0)
7388 CUMULATIVE_ARGS valcum
;
7392 valcum
.fregno
= FP_ARG_MIN_REG
;
7393 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
7394 /* Do a trial code generation as if this were going to be passed
7395 as an argument; if any part goes in memory, we return NULL. */
7396 valret
= rs6000_darwin64_record_arg (&valcum
, type
, true, true);
7399 /* Otherwise fall through to more conventional ABI rules. */
7402 if (AGGREGATE_TYPE_P (type
)
7403 && (aix_struct_return
7404 || (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8))
7407 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
7408 modes only exist for GCC vector types if -maltivec. */
7409 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
7410 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
7413 /* Return synthetic vectors in memory. */
7414 if (TREE_CODE (type
) == VECTOR_TYPE
7415 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
7417 static bool warned_for_return_big_vectors
= false;
7418 if (!warned_for_return_big_vectors
)
7420 warning (0, "GCC vector returned by reference: "
7421 "non-standard ABI extension with no compatibility guarantee");
7422 warned_for_return_big_vectors
= true;
7427 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& TYPE_MODE (type
) == TFmode
)
7433 #ifdef HAVE_AS_GNU_ATTRIBUTE
7434 /* Return TRUE if a call to function FNDECL may be one that
7435 potentially affects the function calling ABI of the object file. */
7438 call_ABI_of_interest (tree fndecl
)
7440 if (cgraph_state
== CGRAPH_STATE_EXPANSION
)
7442 struct cgraph_node
*c_node
;
7444 /* Libcalls are always interesting. */
7445 if (fndecl
== NULL_TREE
)
7448 /* Any call to an external function is interesting. */
7449 if (DECL_EXTERNAL (fndecl
))
7452 /* Interesting functions that we are emitting in this object file. */
7453 c_node
= cgraph_get_node (fndecl
);
7454 c_node
= cgraph_function_or_thunk_node (c_node
, NULL
);
7455 return !cgraph_only_called_directly_p (c_node
);
7461 /* Initialize a variable CUM of type CUMULATIVE_ARGS
7462 for a call to a function whose data type is FNTYPE.
7463 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
7465 For incoming args we set the number of arguments in the prototype large
7466 so we never return a PARALLEL. */
7469 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
7470 rtx libname ATTRIBUTE_UNUSED
, int incoming
,
7471 int libcall
, int n_named_args
,
7472 tree fndecl ATTRIBUTE_UNUSED
,
7473 enum machine_mode return_mode ATTRIBUTE_UNUSED
)
7475 static CUMULATIVE_ARGS zero_cumulative
;
7477 *cum
= zero_cumulative
;
7479 cum
->fregno
= FP_ARG_MIN_REG
;
7480 cum
->vregno
= ALTIVEC_ARG_MIN_REG
;
7481 cum
->prototype
= (fntype
&& prototype_p (fntype
));
7482 cum
->call_cookie
= ((DEFAULT_ABI
== ABI_V4
&& libcall
)
7483 ? CALL_LIBCALL
: CALL_NORMAL
);
7484 cum
->sysv_gregno
= GP_ARG_MIN_REG
;
7485 cum
->stdarg
= stdarg_p (fntype
);
7487 cum
->nargs_prototype
= 0;
7488 if (incoming
|| cum
->prototype
)
7489 cum
->nargs_prototype
= n_named_args
;
7491 /* Check for a longcall attribute. */
7492 if ((!fntype
&& rs6000_default_long_calls
)
7494 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
))
7495 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
))))
7496 cum
->call_cookie
|= CALL_LONG
;
7498 if (TARGET_DEBUG_ARG
)
7500 fprintf (stderr
, "\ninit_cumulative_args:");
7503 tree ret_type
= TREE_TYPE (fntype
);
7504 fprintf (stderr
, " ret code = %s,",
7505 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
7508 if (cum
->call_cookie
& CALL_LONG
)
7509 fprintf (stderr
, " longcall,");
7511 fprintf (stderr
, " proto = %d, nargs = %d\n",
7512 cum
->prototype
, cum
->nargs_prototype
);
7515 #ifdef HAVE_AS_GNU_ATTRIBUTE
7516 if (DEFAULT_ABI
== ABI_V4
)
7518 cum
->escapes
= call_ABI_of_interest (fndecl
);
7525 return_type
= TREE_TYPE (fntype
);
7526 return_mode
= TYPE_MODE (return_type
);
7529 return_type
= lang_hooks
.types
.type_for_mode (return_mode
, 0);
7531 if (return_type
!= NULL
)
7533 if (TREE_CODE (return_type
) == RECORD_TYPE
7534 && TYPE_TRANSPARENT_AGGR (return_type
))
7536 return_type
= TREE_TYPE (first_field (return_type
));
7537 return_mode
= TYPE_MODE (return_type
);
7539 if (AGGREGATE_TYPE_P (return_type
)
7540 && ((unsigned HOST_WIDE_INT
) int_size_in_bytes (return_type
)
7542 rs6000_returns_struct
= true;
7544 if (SCALAR_FLOAT_MODE_P (return_mode
))
7545 rs6000_passes_float
= true;
7546 else if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode
)
7547 || SPE_VECTOR_MODE (return_mode
))
7548 rs6000_passes_vector
= true;
7555 && TARGET_ALTIVEC_ABI
7556 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype
))))
7558 error ("cannot return value in vector register because"
7559 " altivec instructions are disabled, use -maltivec"
7564 /* Return true if TYPE must be passed on the stack and not in registers. */
7567 rs6000_must_pass_in_stack (enum machine_mode mode
, const_tree type
)
7569 if (DEFAULT_ABI
== ABI_AIX
|| TARGET_64BIT
)
7570 return must_pass_in_stack_var_size (mode
, type
);
7572 return must_pass_in_stack_var_size_or_pad (mode
, type
);
7575 /* If defined, a C expression which determines whether, and in which
7576 direction, to pad out an argument with extra space. The value
7577 should be of type `enum direction': either `upward' to pad above
7578 the argument, `downward' to pad below, or `none' to inhibit
7581 For the AIX ABI structs are always stored left shifted in their
7585 function_arg_padding (enum machine_mode mode
, const_tree type
)
7587 #ifndef AGGREGATE_PADDING_FIXED
7588 #define AGGREGATE_PADDING_FIXED 0
7590 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
7591 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
7594 if (!AGGREGATE_PADDING_FIXED
)
7596 /* GCC used to pass structures of the same size as integer types as
7597 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
7598 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
7599 passed padded downward, except that -mstrict-align further
7600 muddied the water in that multi-component structures of 2 and 4
7601 bytes in size were passed padded upward.
7603 The following arranges for best compatibility with previous
7604 versions of gcc, but removes the -mstrict-align dependency. */
7605 if (BYTES_BIG_ENDIAN
)
7607 HOST_WIDE_INT size
= 0;
7609 if (mode
== BLKmode
)
7611 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
7612 size
= int_size_in_bytes (type
);
7615 size
= GET_MODE_SIZE (mode
);
7617 if (size
== 1 || size
== 2 || size
== 4)
7623 if (AGGREGATES_PAD_UPWARD_ALWAYS
)
7625 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
7629 /* Fall back to the default. */
7630 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
7633 /* If defined, a C expression that gives the alignment boundary, in bits,
7634 of an argument with the specified mode and type. If it is not defined,
7635 PARM_BOUNDARY is used for all arguments.
7637 V.4 wants long longs and doubles to be double word aligned. Just
7638 testing the mode size is a boneheaded way to do this as it means
7639 that other types such as complex int are also double word aligned.
7640 However, we're stuck with this because changing the ABI might break
7641 existing library interfaces.
7643 Doubleword align SPE vectors.
7644 Quadword align Altivec/VSX vectors.
7645 Quadword align large synthetic vector types. */
7648 rs6000_function_arg_boundary (enum machine_mode mode
, const_tree type
)
7650 if (DEFAULT_ABI
== ABI_V4
7651 && (GET_MODE_SIZE (mode
) == 8
7652 || (TARGET_HARD_FLOAT
7654 && (mode
== TFmode
|| mode
== TDmode
))))
7656 else if (SPE_VECTOR_MODE (mode
)
7657 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
7658 && int_size_in_bytes (type
) >= 8
7659 && int_size_in_bytes (type
) < 16))
7661 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
7662 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
7663 && int_size_in_bytes (type
) >= 16))
7665 else if (TARGET_MACHO
7666 && rs6000_darwin64_abi
7668 && type
&& TYPE_ALIGN (type
) > 64)
7671 return PARM_BOUNDARY
;
7674 /* For a function parm of MODE and TYPE, return the starting word in
7675 the parameter area. NWORDS of the parameter area are already used. */
7678 rs6000_parm_start (enum machine_mode mode
, const_tree type
,
7679 unsigned int nwords
)
7682 unsigned int parm_offset
;
7684 align
= rs6000_function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
7685 parm_offset
= DEFAULT_ABI
== ABI_V4
? 2 : 6;
7686 return nwords
+ (-(parm_offset
+ nwords
) & align
);
7689 /* Compute the size (in words) of a function argument. */
7691 static unsigned long
7692 rs6000_arg_size (enum machine_mode mode
, const_tree type
)
7696 if (mode
!= BLKmode
)
7697 size
= GET_MODE_SIZE (mode
);
7699 size
= int_size_in_bytes (type
);
7702 return (size
+ 3) >> 2;
7704 return (size
+ 7) >> 3;
7707 /* Use this to flush pending int fields. */
7710 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*cum
,
7711 HOST_WIDE_INT bitpos
, int final
)
7713 unsigned int startbit
, endbit
;
7714 int intregs
, intoffset
;
7715 enum machine_mode mode
;
7717 /* Handle the situations where a float is taking up the first half
7718 of the GPR, and the other half is empty (typically due to
7719 alignment restrictions). We can detect this by a 8-byte-aligned
7720 int field, or by seeing that this is the final flush for this
7721 argument. Count the word and continue on. */
7722 if (cum
->floats_in_gpr
== 1
7723 && (cum
->intoffset
% 64 == 0
7724 || (cum
->intoffset
== -1 && final
)))
7727 cum
->floats_in_gpr
= 0;
7730 if (cum
->intoffset
== -1)
7733 intoffset
= cum
->intoffset
;
7734 cum
->intoffset
= -1;
7735 cum
->floats_in_gpr
= 0;
7737 if (intoffset
% BITS_PER_WORD
!= 0)
7739 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
7741 if (mode
== BLKmode
)
7743 /* We couldn't find an appropriate mode, which happens,
7744 e.g., in packed structs when there are 3 bytes to load.
7745 Back intoffset back to the beginning of the word in this
7747 intoffset
= intoffset
& -BITS_PER_WORD
;
7751 startbit
= intoffset
& -BITS_PER_WORD
;
7752 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
7753 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
7754 cum
->words
+= intregs
;
7755 /* words should be unsigned. */
7756 if ((unsigned)cum
->words
< (endbit
/BITS_PER_WORD
))
7758 int pad
= (endbit
/BITS_PER_WORD
) - cum
->words
;
7763 /* The darwin64 ABI calls for us to recurse down through structs,
7764 looking for elements passed in registers. Unfortunately, we have
7765 to track int register count here also because of misalignments
7766 in powerpc alignment mode. */
7769 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*cum
,
7771 HOST_WIDE_INT startbitpos
)
7775 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
7776 if (TREE_CODE (f
) == FIELD_DECL
)
7778 HOST_WIDE_INT bitpos
= startbitpos
;
7779 tree ftype
= TREE_TYPE (f
);
7780 enum machine_mode mode
;
7781 if (ftype
== error_mark_node
)
7783 mode
= TYPE_MODE (ftype
);
7785 if (DECL_SIZE (f
) != 0
7786 && host_integerp (bit_position (f
), 1))
7787 bitpos
+= int_bit_position (f
);
7789 /* ??? FIXME: else assume zero offset. */
7791 if (TREE_CODE (ftype
) == RECORD_TYPE
)
7792 rs6000_darwin64_record_arg_advance_recurse (cum
, ftype
, bitpos
);
7793 else if (USE_FP_FOR_ARG_P (cum
, mode
, ftype
))
7795 unsigned n_fpregs
= (GET_MODE_SIZE (mode
) + 7) >> 3;
7796 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
7797 cum
->fregno
+= n_fpregs
;
7798 /* Single-precision floats present a special problem for
7799 us, because they are smaller than an 8-byte GPR, and so
7800 the structure-packing rules combined with the standard
7801 varargs behavior mean that we want to pack float/float
7802 and float/int combinations into a single register's
7803 space. This is complicated by the arg advance flushing,
7804 which works on arbitrarily large groups of int-type
7808 if (cum
->floats_in_gpr
== 1)
7810 /* Two floats in a word; count the word and reset
7813 cum
->floats_in_gpr
= 0;
7815 else if (bitpos
% 64 == 0)
7817 /* A float at the beginning of an 8-byte word;
7818 count it and put off adjusting cum->words until
7819 we see if a arg advance flush is going to do it
7821 cum
->floats_in_gpr
++;
7825 /* The float is at the end of a word, preceded
7826 by integer fields, so the arg advance flush
7827 just above has already set cum->words and
7828 everything is taken care of. */
7832 cum
->words
+= n_fpregs
;
7834 else if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, 1))
7836 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
7840 else if (cum
->intoffset
== -1)
7841 cum
->intoffset
= bitpos
;
7845 /* Check for an item that needs to be considered specially under the darwin 64
7846 bit ABI. These are record types where the mode is BLK or the structure is
7849 rs6000_darwin64_struct_check_p (enum machine_mode mode
, const_tree type
)
7851 return rs6000_darwin64_abi
7852 && ((mode
== BLKmode
7853 && TREE_CODE (type
) == RECORD_TYPE
7854 && int_size_in_bytes (type
) > 0)
7855 || (type
&& TREE_CODE (type
) == RECORD_TYPE
7856 && int_size_in_bytes (type
) == 8)) ? 1 : 0;
7859 /* Update the data in CUM to advance over an argument
7860 of mode MODE and data type TYPE.
7861 (TYPE is null for libcalls where that information may not be available.)
7863 Note that for args passed by reference, function_arg will be called
7864 with MODE and TYPE set to that of the pointer to the arg, not the arg
7868 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
7869 const_tree type
, bool named
, int depth
)
7871 /* Only tick off an argument if we're not recursing. */
7873 cum
->nargs_prototype
--;
7875 #ifdef HAVE_AS_GNU_ATTRIBUTE
7876 if (DEFAULT_ABI
== ABI_V4
7879 if (SCALAR_FLOAT_MODE_P (mode
))
7880 rs6000_passes_float
= true;
7881 else if (named
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
7882 rs6000_passes_vector
= true;
7883 else if (SPE_VECTOR_MODE (mode
)
7885 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
7886 rs6000_passes_vector
= true;
7890 if (TARGET_ALTIVEC_ABI
7891 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
7892 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
7893 && int_size_in_bytes (type
) == 16)))
7897 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
))
7900 if (!TARGET_ALTIVEC
)
7901 error ("cannot pass argument in vector register because"
7902 " altivec instructions are disabled, use -maltivec"
7905 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
7906 even if it is going to be passed in a vector register.
7907 Darwin does the same for variable-argument functions. */
7908 if ((DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
7909 || (cum
->stdarg
&& DEFAULT_ABI
!= ABI_V4
))
7919 /* Vector parameters must be 16-byte aligned. This places
7920 them at 2 mod 4 in terms of words in 32-bit mode, since
7921 the parameter save area starts at offset 24 from the
7922 stack. In 64-bit mode, they just have to start on an
7923 even word, since the parameter save area is 16-byte
7924 aligned. Space for GPRs is reserved even if the argument
7925 will be passed in memory. */
7927 align
= (2 - cum
->words
) & 3;
7929 align
= cum
->words
& 1;
7930 cum
->words
+= align
+ rs6000_arg_size (mode
, type
);
7932 if (TARGET_DEBUG_ARG
)
7934 fprintf (stderr
, "function_adv: words = %2d, align=%d, ",
7936 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s\n",
7937 cum
->nargs_prototype
, cum
->prototype
,
7938 GET_MODE_NAME (mode
));
7942 else if (TARGET_SPE_ABI
&& TARGET_SPE
&& SPE_VECTOR_MODE (mode
)
7944 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
7947 else if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
7949 int size
= int_size_in_bytes (type
);
7950 /* Variable sized types have size == -1 and are
7951 treated as if consisting entirely of ints.
7952 Pad to 16 byte boundary if needed. */
7953 if (TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
7954 && (cum
->words
% 2) != 0)
7956 /* For varargs, we can just go up by the size of the struct. */
7958 cum
->words
+= (size
+ 7) / 8;
7961 /* It is tempting to say int register count just goes up by
7962 sizeof(type)/8, but this is wrong in a case such as
7963 { int; double; int; } [powerpc alignment]. We have to
7964 grovel through the fields for these too. */
7966 cum
->floats_in_gpr
= 0;
7967 rs6000_darwin64_record_arg_advance_recurse (cum
, type
, 0);
7968 rs6000_darwin64_record_arg_advance_flush (cum
,
7969 size
* BITS_PER_UNIT
, 1);
7971 if (TARGET_DEBUG_ARG
)
7973 fprintf (stderr
, "function_adv: words = %2d, align=%d, size=%d",
7974 cum
->words
, TYPE_ALIGN (type
), size
);
7976 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
7977 cum
->nargs_prototype
, cum
->prototype
,
7978 GET_MODE_NAME (mode
));
7981 else if (DEFAULT_ABI
== ABI_V4
)
7983 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
7984 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
7985 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
7986 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
7987 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
7989 /* _Decimal128 must use an even/odd register pair. This assumes
7990 that the register number is odd when fregno is odd. */
7991 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
7994 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
7995 <= FP_ARG_V4_MAX_REG
)
7996 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
7999 cum
->fregno
= FP_ARG_V4_MAX_REG
+ 1;
8000 if (mode
== DFmode
|| mode
== TFmode
8001 || mode
== DDmode
|| mode
== TDmode
)
8002 cum
->words
+= cum
->words
& 1;
8003 cum
->words
+= rs6000_arg_size (mode
, type
);
8008 int n_words
= rs6000_arg_size (mode
, type
);
8009 int gregno
= cum
->sysv_gregno
;
8011 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
8012 (r7,r8) or (r9,r10). As does any other 2 word item such
8013 as complex int due to a historical mistake. */
8015 gregno
+= (1 - gregno
) & 1;
8017 /* Multi-reg args are not split between registers and stack. */
8018 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
8020 /* Long long and SPE vectors are aligned on the stack.
8021 So are other 2 word items such as complex int due to
8022 a historical mistake. */
8024 cum
->words
+= cum
->words
& 1;
8025 cum
->words
+= n_words
;
8028 /* Note: continuing to accumulate gregno past when we've started
8029 spilling to the stack indicates the fact that we've started
8030 spilling to the stack to expand_builtin_saveregs. */
8031 cum
->sysv_gregno
= gregno
+ n_words
;
8034 if (TARGET_DEBUG_ARG
)
8036 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
8037 cum
->words
, cum
->fregno
);
8038 fprintf (stderr
, "gregno = %2d, nargs = %4d, proto = %d, ",
8039 cum
->sysv_gregno
, cum
->nargs_prototype
, cum
->prototype
);
8040 fprintf (stderr
, "mode = %4s, named = %d\n",
8041 GET_MODE_NAME (mode
), named
);
8046 int n_words
= rs6000_arg_size (mode
, type
);
8047 int start_words
= cum
->words
;
8048 int align_words
= rs6000_parm_start (mode
, type
, start_words
);
8050 cum
->words
= align_words
+ n_words
;
8052 if (SCALAR_FLOAT_MODE_P (mode
)
8053 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
8055 /* _Decimal128 must be passed in an even/odd float register pair.
8056 This assumes that the register number is odd when fregno is
8058 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
8060 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
8063 if (TARGET_DEBUG_ARG
)
8065 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
8066 cum
->words
, cum
->fregno
);
8067 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s, ",
8068 cum
->nargs_prototype
, cum
->prototype
, GET_MODE_NAME (mode
));
8069 fprintf (stderr
, "named = %d, align = %d, depth = %d\n",
8070 named
, align_words
- start_words
, depth
);
8076 rs6000_function_arg_advance (cumulative_args_t cum
, enum machine_mode mode
,
8077 const_tree type
, bool named
)
8079 rs6000_function_arg_advance_1 (get_cumulative_args (cum
), mode
, type
, named
,
8084 spe_build_register_parallel (enum machine_mode mode
, int gregno
)
8091 r1
= gen_rtx_REG (DImode
, gregno
);
8092 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
8093 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, r1
));
8097 r1
= gen_rtx_REG (DImode
, gregno
);
8098 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
8099 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
8100 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
8101 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r3
));
8104 r1
= gen_rtx_REG (DImode
, gregno
);
8105 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
8106 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
8107 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
8108 r5
= gen_rtx_REG (DImode
, gregno
+ 4);
8109 r5
= gen_rtx_EXPR_LIST (VOIDmode
, r5
, GEN_INT (16));
8110 r7
= gen_rtx_REG (DImode
, gregno
+ 6);
8111 r7
= gen_rtx_EXPR_LIST (VOIDmode
, r7
, GEN_INT (24));
8112 return gen_rtx_PARALLEL (mode
, gen_rtvec (4, r1
, r3
, r5
, r7
));
8119 /* Determine where to put a SIMD argument on the SPE. */
8121 rs6000_spe_function_arg (const CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
8124 int gregno
= cum
->sysv_gregno
;
8126 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
8127 are passed and returned in a pair of GPRs for ABI compatibility. */
8128 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
8129 || mode
== DCmode
|| mode
== TCmode
))
8131 int n_words
= rs6000_arg_size (mode
, type
);
8133 /* Doubles go in an odd/even register pair (r5/r6, etc). */
8135 gregno
+= (1 - gregno
) & 1;
8137 /* Multi-reg args are not split between registers and stack. */
8138 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
8141 return spe_build_register_parallel (mode
, gregno
);
8145 int n_words
= rs6000_arg_size (mode
, type
);
8147 /* SPE vectors are put in odd registers. */
8148 if (n_words
== 2 && (gregno
& 1) == 0)
8151 if (gregno
+ n_words
- 1 <= GP_ARG_MAX_REG
)
8154 enum machine_mode m
= SImode
;
8156 r1
= gen_rtx_REG (m
, gregno
);
8157 r1
= gen_rtx_EXPR_LIST (m
, r1
, const0_rtx
);
8158 r2
= gen_rtx_REG (m
, gregno
+ 1);
8159 r2
= gen_rtx_EXPR_LIST (m
, r2
, GEN_INT (4));
8160 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
8167 if (gregno
<= GP_ARG_MAX_REG
)
8168 return gen_rtx_REG (mode
, gregno
);
8174 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
8175 structure between cum->intoffset and bitpos to integer registers. */
8178 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*cum
,
8179 HOST_WIDE_INT bitpos
, rtx rvec
[], int *k
)
8181 enum machine_mode mode
;
8183 unsigned int startbit
, endbit
;
8184 int this_regno
, intregs
, intoffset
;
8187 if (cum
->intoffset
== -1)
8190 intoffset
= cum
->intoffset
;
8191 cum
->intoffset
= -1;
8193 /* If this is the trailing part of a word, try to only load that
8194 much into the register. Otherwise load the whole register. Note
8195 that in the latter case we may pick up unwanted bits. It's not a
8196 problem at the moment but may wish to revisit. */
8198 if (intoffset
% BITS_PER_WORD
!= 0)
8200 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
8202 if (mode
== BLKmode
)
8204 /* We couldn't find an appropriate mode, which happens,
8205 e.g., in packed structs when there are 3 bytes to load.
8206 Back intoffset back to the beginning of the word in this
8208 intoffset
= intoffset
& -BITS_PER_WORD
;
8215 startbit
= intoffset
& -BITS_PER_WORD
;
8216 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
8217 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
8218 this_regno
= cum
->words
+ intoffset
/ BITS_PER_WORD
;
8220 if (intregs
> 0 && intregs
> GP_ARG_NUM_REG
- this_regno
)
8223 intregs
= MIN (intregs
, GP_ARG_NUM_REG
- this_regno
);
8227 intoffset
/= BITS_PER_UNIT
;
8230 regno
= GP_ARG_MIN_REG
+ this_regno
;
8231 reg
= gen_rtx_REG (mode
, regno
);
8233 gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
8236 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
8240 while (intregs
> 0);
8243 /* Recursive workhorse for the following. */
8246 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*cum
, const_tree type
,
8247 HOST_WIDE_INT startbitpos
, rtx rvec
[],
8252 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
8253 if (TREE_CODE (f
) == FIELD_DECL
)
8255 HOST_WIDE_INT bitpos
= startbitpos
;
8256 tree ftype
= TREE_TYPE (f
);
8257 enum machine_mode mode
;
8258 if (ftype
== error_mark_node
)
8260 mode
= TYPE_MODE (ftype
);
8262 if (DECL_SIZE (f
) != 0
8263 && host_integerp (bit_position (f
), 1))
8264 bitpos
+= int_bit_position (f
);
8266 /* ??? FIXME: else assume zero offset. */
8268 if (TREE_CODE (ftype
) == RECORD_TYPE
)
8269 rs6000_darwin64_record_arg_recurse (cum
, ftype
, bitpos
, rvec
, k
);
8270 else if (cum
->named
&& USE_FP_FOR_ARG_P (cum
, mode
, ftype
))
8272 unsigned n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
8276 case SCmode
: mode
= SFmode
; break;
8277 case DCmode
: mode
= DFmode
; break;
8278 case TCmode
: mode
= TFmode
; break;
8282 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
8283 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
8285 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
8286 && (mode
== TFmode
|| mode
== TDmode
));
8287 /* Long double or _Decimal128 split over regs and memory. */
8288 mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
: DFmode
;
8292 = gen_rtx_EXPR_LIST (VOIDmode
,
8293 gen_rtx_REG (mode
, cum
->fregno
++),
8294 GEN_INT (bitpos
/ BITS_PER_UNIT
));
8295 if (mode
== TFmode
|| mode
== TDmode
)
8298 else if (cum
->named
&& USE_ALTIVEC_FOR_ARG_P (cum
, mode
, ftype
, 1))
8300 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
8302 = gen_rtx_EXPR_LIST (VOIDmode
,
8303 gen_rtx_REG (mode
, cum
->vregno
++),
8304 GEN_INT (bitpos
/ BITS_PER_UNIT
));
8306 else if (cum
->intoffset
== -1)
8307 cum
->intoffset
= bitpos
;
8311 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
8312 the register(s) to be used for each field and subfield of a struct
8313 being passed by value, along with the offset of where the
8314 register's value may be found in the block. FP fields go in FP
8315 register, vector fields go in vector registers, and everything
8316 else goes in int registers, packed as in memory.
8318 This code is also used for function return values. RETVAL indicates
8319 whether this is the case.
8321 Much of this is taken from the SPARC V9 port, which has a similar
8322 calling convention. */
8325 rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*orig_cum
, const_tree type
,
8326 bool named
, bool retval
)
8328 rtx rvec
[FIRST_PSEUDO_REGISTER
];
8329 int k
= 1, kbase
= 1;
8330 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
8331 /* This is a copy; modifications are not visible to our caller. */
8332 CUMULATIVE_ARGS copy_cum
= *orig_cum
;
8333 CUMULATIVE_ARGS
*cum
= ©_cum
;
8335 /* Pad to 16 byte boundary if needed. */
8336 if (!retval
&& TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
8337 && (cum
->words
% 2) != 0)
8344 /* Put entries into rvec[] for individual FP and vector fields, and
8345 for the chunks of memory that go in int regs. Note we start at
8346 element 1; 0 is reserved for an indication of using memory, and
8347 may or may not be filled in below. */
8348 rs6000_darwin64_record_arg_recurse (cum
, type
, /* startbit pos= */ 0, rvec
, &k
);
8349 rs6000_darwin64_record_arg_flush (cum
, typesize
* BITS_PER_UNIT
, rvec
, &k
);
8351 /* If any part of the struct went on the stack put all of it there.
8352 This hack is because the generic code for
8353 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
8354 parts of the struct are not at the beginning. */
8358 return NULL_RTX
; /* doesn't go in registers at all */
8360 rvec
[0] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
8362 if (k
> 1 || cum
->use_stack
)
8363 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (k
- kbase
, &rvec
[kbase
]));
8368 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
8371 rs6000_mixed_function_arg (enum machine_mode mode
, const_tree type
,
8376 rtx rvec
[GP_ARG_NUM_REG
+ 1];
8378 if (align_words
>= GP_ARG_NUM_REG
)
8381 n_units
= rs6000_arg_size (mode
, type
);
8383 /* Optimize the simple case where the arg fits in one gpr, except in
8384 the case of BLKmode due to assign_parms assuming that registers are
8385 BITS_PER_WORD wide. */
8387 || (n_units
== 1 && mode
!= BLKmode
))
8388 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
8391 if (align_words
+ n_units
> GP_ARG_NUM_REG
)
8392 /* Not all of the arg fits in gprs. Say that it goes in memory too,
8393 using a magic NULL_RTX component.
8394 This is not strictly correct. Only some of the arg belongs in
8395 memory, not all of it. However, the normal scheme using
8396 function_arg_partial_nregs can result in unusual subregs, eg.
8397 (subreg:SI (reg:DF) 4), which are not handled well. The code to
8398 store the whole arg to memory is often more efficient than code
8399 to store pieces, and we know that space is available in the right
8400 place for the whole arg. */
8401 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
8406 rtx r
= gen_rtx_REG (SImode
, GP_ARG_MIN_REG
+ align_words
);
8407 rtx off
= GEN_INT (i
++ * 4);
8408 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
8410 while (++align_words
< GP_ARG_NUM_REG
&& --n_units
!= 0);
8412 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
8415 /* Determine where to put an argument to a function.
8416 Value is zero to push the argument on the stack,
8417 or a hard register in which to store the argument.
8419 MODE is the argument's machine mode.
8420 TYPE is the data type of the argument (as a tree).
8421 This is null for libcalls where that information may
8423 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8424 the preceding args and about the function being called. It is
8425 not modified in this routine.
8426 NAMED is nonzero if this argument is a named parameter
8427 (otherwise it is an extra parameter matching an ellipsis).
8429 On RS/6000 the first eight words of non-FP are normally in registers
8430 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
8431 Under V.4, the first 8 FP args are in registers.
8433 If this is floating-point and no prototype is specified, we use
8434 both an FP and integer register (or possibly FP reg and stack). Library
8435 functions (when CALL_LIBCALL is set) always have the proper types for args,
8436 so we can pass the FP value just in one register. emit_library_function
8437 doesn't support PARALLEL anyway.
8439 Note that for args passed by reference, function_arg will be called
8440 with MODE and TYPE set to that of the pointer to the arg, not the arg
8444 rs6000_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
8445 const_tree type
, bool named
)
8447 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
8448 enum rs6000_abi abi
= DEFAULT_ABI
;
8450 /* Return a marker to indicate whether CR1 needs to set or clear the
8451 bit that V.4 uses to say fp args were passed in registers.
8452 Assume that we don't need the marker for software floating point,
8453 or compiler generated library calls. */
8454 if (mode
== VOIDmode
)
8457 && (cum
->call_cookie
& CALL_LIBCALL
) == 0
8459 || (cum
->nargs_prototype
< 0
8460 && (cum
->prototype
|| TARGET_NO_PROTOTYPE
))))
8462 /* For the SPE, we need to crxor CR6 always. */
8464 return GEN_INT (cum
->call_cookie
| CALL_V4_SET_FP_ARGS
);
8465 else if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
8466 return GEN_INT (cum
->call_cookie
8467 | ((cum
->fregno
== FP_ARG_MIN_REG
)
8468 ? CALL_V4_SET_FP_ARGS
8469 : CALL_V4_CLEAR_FP_ARGS
));
8472 return GEN_INT (cum
->call_cookie
& ~CALL_LIBCALL
);
8475 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
8477 rtx rslt
= rs6000_darwin64_record_arg (cum
, type
, named
, /*retval= */false);
8478 if (rslt
!= NULL_RTX
)
8480 /* Else fall through to usual handling. */
8483 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
))
8484 if (TARGET_64BIT
&& ! cum
->prototype
)
8486 /* Vector parameters get passed in vector register
8487 and also in GPRs or memory, in absence of prototype. */
8490 align_words
= (cum
->words
+ 1) & ~1;
8492 if (align_words
>= GP_ARG_NUM_REG
)
8498 slot
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
8500 return gen_rtx_PARALLEL (mode
,
8502 gen_rtx_EXPR_LIST (VOIDmode
,
8504 gen_rtx_EXPR_LIST (VOIDmode
,
8505 gen_rtx_REG (mode
, cum
->vregno
),
8509 return gen_rtx_REG (mode
, cum
->vregno
);
8510 else if (TARGET_ALTIVEC_ABI
8511 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
8512 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
8513 && int_size_in_bytes (type
) == 16)))
8515 if (named
|| abi
== ABI_V4
)
8519 /* Vector parameters to varargs functions under AIX or Darwin
8520 get passed in memory and possibly also in GPRs. */
8521 int align
, align_words
, n_words
;
8522 enum machine_mode part_mode
;
8524 /* Vector parameters must be 16-byte aligned. This places them at
8525 2 mod 4 in terms of words in 32-bit mode, since the parameter
8526 save area starts at offset 24 from the stack. In 64-bit mode,
8527 they just have to start on an even word, since the parameter
8528 save area is 16-byte aligned. */
8530 align
= (2 - cum
->words
) & 3;
8532 align
= cum
->words
& 1;
8533 align_words
= cum
->words
+ align
;
8535 /* Out of registers? Memory, then. */
8536 if (align_words
>= GP_ARG_NUM_REG
)
8539 if (TARGET_32BIT
&& TARGET_POWERPC64
)
8540 return rs6000_mixed_function_arg (mode
, type
, align_words
);
8542 /* The vector value goes in GPRs. Only the part of the
8543 value in GPRs is reported here. */
8545 n_words
= rs6000_arg_size (mode
, type
);
8546 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
8547 /* Fortunately, there are only two possibilities, the value
8548 is either wholly in GPRs or half in GPRs and half not. */
8551 return gen_rtx_REG (part_mode
, GP_ARG_MIN_REG
+ align_words
);
8554 else if (TARGET_SPE_ABI
&& TARGET_SPE
8555 && (SPE_VECTOR_MODE (mode
)
8556 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
8559 || mode
== TCmode
))))
8560 return rs6000_spe_function_arg (cum
, mode
, type
);
8562 else if (abi
== ABI_V4
)
8564 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
8565 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
8566 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
8567 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
8568 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
8570 /* _Decimal128 must use an even/odd register pair. This assumes
8571 that the register number is odd when fregno is odd. */
8572 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
8575 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
8576 <= FP_ARG_V4_MAX_REG
)
8577 return gen_rtx_REG (mode
, cum
->fregno
);
8583 int n_words
= rs6000_arg_size (mode
, type
);
8584 int gregno
= cum
->sysv_gregno
;
8586 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
8587 (r7,r8) or (r9,r10). As does any other 2 word item such
8588 as complex int due to a historical mistake. */
8590 gregno
+= (1 - gregno
) & 1;
8592 /* Multi-reg args are not split between registers and stack. */
8593 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
8596 if (TARGET_32BIT
&& TARGET_POWERPC64
)
8597 return rs6000_mixed_function_arg (mode
, type
,
8598 gregno
- GP_ARG_MIN_REG
);
8599 return gen_rtx_REG (mode
, gregno
);
8604 int align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
8606 /* _Decimal128 must be passed in an even/odd float register pair.
8607 This assumes that the register number is odd when fregno is odd. */
8608 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
8611 if (USE_FP_FOR_ARG_P (cum
, mode
, type
))
8613 rtx rvec
[GP_ARG_NUM_REG
+ 1];
8617 enum machine_mode fmode
= mode
;
8618 unsigned long n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
8620 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
8622 /* Currently, we only ever need one reg here because complex
8623 doubles are split. */
8624 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
8625 && (fmode
== TFmode
|| fmode
== TDmode
));
8627 /* Long double or _Decimal128 split over regs and memory. */
8628 fmode
= DECIMAL_FLOAT_MODE_P (fmode
) ? DDmode
: DFmode
;
8631 /* Do we also need to pass this arg in the parameter save
8634 && (cum
->nargs_prototype
<= 0
8635 || (DEFAULT_ABI
== ABI_AIX
8637 && align_words
>= GP_ARG_NUM_REG
)));
8639 if (!needs_psave
&& mode
== fmode
)
8640 return gen_rtx_REG (fmode
, cum
->fregno
);
8645 /* Describe the part that goes in gprs or the stack.
8646 This piece must come first, before the fprs. */
8647 if (align_words
< GP_ARG_NUM_REG
)
8649 unsigned long n_words
= rs6000_arg_size (mode
, type
);
8651 if (align_words
+ n_words
> GP_ARG_NUM_REG
8652 || (TARGET_32BIT
&& TARGET_POWERPC64
))
8654 /* If this is partially on the stack, then we only
8655 include the portion actually in registers here. */
8656 enum machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
8659 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
8660 /* Not all of the arg fits in gprs. Say that it
8661 goes in memory too, using a magic NULL_RTX
8662 component. Also see comment in
8663 rs6000_mixed_function_arg for why the normal
8664 function_arg_partial_nregs scheme doesn't work
8666 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
,
8670 r
= gen_rtx_REG (rmode
,
8671 GP_ARG_MIN_REG
+ align_words
);
8672 off
= GEN_INT (i
++ * GET_MODE_SIZE (rmode
));
8673 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
8675 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
8679 /* The whole arg fits in gprs. */
8680 r
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
8681 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
8685 /* It's entirely in memory. */
8686 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
8689 /* Describe where this piece goes in the fprs. */
8690 r
= gen_rtx_REG (fmode
, cum
->fregno
);
8691 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
8693 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
8695 else if (align_words
< GP_ARG_NUM_REG
)
8697 if (TARGET_32BIT
&& TARGET_POWERPC64
)
8698 return rs6000_mixed_function_arg (mode
, type
, align_words
);
8700 if (mode
== BLKmode
)
8703 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
8710 /* For an arg passed partly in registers and partly in memory, this is
8711 the number of bytes passed in registers. For args passed entirely in
8712 registers or entirely in memory, zero. When an arg is described by a
8713 PARALLEL, perhaps using more than one register type, this function
8714 returns the number of bytes used by the first element of the PARALLEL. */
8717 rs6000_arg_partial_bytes (cumulative_args_t cum_v
, enum machine_mode mode
,
8718 tree type
, bool named
)
8720 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
8724 if (DEFAULT_ABI
== ABI_V4
)
8727 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
)
8728 && cum
->nargs_prototype
>= 0)
8731 /* In this complicated case we just disable the partial_nregs code. */
8732 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
8735 align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
8737 if (USE_FP_FOR_ARG_P (cum
, mode
, type
))
8739 /* If we are passing this arg in the fixed parameter save area
8740 (gprs or memory) as well as fprs, then this function should
8741 return the number of partial bytes passed in the parameter
8742 save area rather than partial bytes passed in fprs. */
8744 && (cum
->nargs_prototype
<= 0
8745 || (DEFAULT_ABI
== ABI_AIX
8747 && align_words
>= GP_ARG_NUM_REG
)))
8749 else if (cum
->fregno
+ ((GET_MODE_SIZE (mode
) + 7) >> 3)
8750 > FP_ARG_MAX_REG
+ 1)
8751 ret
= (FP_ARG_MAX_REG
+ 1 - cum
->fregno
) * 8;
8752 else if (cum
->nargs_prototype
>= 0)
8756 if (align_words
< GP_ARG_NUM_REG
8757 && GP_ARG_NUM_REG
< align_words
+ rs6000_arg_size (mode
, type
))
8758 ret
= (GP_ARG_NUM_REG
- align_words
) * (TARGET_32BIT
? 4 : 8);
8760 if (ret
!= 0 && TARGET_DEBUG_ARG
)
8761 fprintf (stderr
, "rs6000_arg_partial_bytes: %d\n", ret
);
8766 /* A C expression that indicates when an argument must be passed by
8767 reference. If nonzero for an argument, a copy of that argument is
8768 made in memory and a pointer to the argument is passed instead of
8769 the argument itself. The pointer is passed in whatever way is
8770 appropriate for passing a pointer to that type.
8772 Under V.4, aggregates and long double are passed by reference.
8774 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
8775 reference unless the AltiVec vector extension ABI is in force.
8777 As an extension to all ABIs, variable sized types are passed by
8781 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
8782 enum machine_mode mode
, const_tree type
,
8783 bool named ATTRIBUTE_UNUSED
)
8785 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& mode
== TFmode
)
8787 if (TARGET_DEBUG_ARG
)
8788 fprintf (stderr
, "function_arg_pass_by_reference: V4 long double\n");
8795 if (DEFAULT_ABI
== ABI_V4
&& AGGREGATE_TYPE_P (type
))
8797 if (TARGET_DEBUG_ARG
)
8798 fprintf (stderr
, "function_arg_pass_by_reference: V4 aggregate\n");
8802 if (int_size_in_bytes (type
) < 0)
8804 if (TARGET_DEBUG_ARG
)
8805 fprintf (stderr
, "function_arg_pass_by_reference: variable size\n");
8809 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
8810 modes only exist for GCC vector types if -maltivec. */
8811 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
8813 if (TARGET_DEBUG_ARG
)
8814 fprintf (stderr
, "function_arg_pass_by_reference: AltiVec\n");
8818 /* Pass synthetic vectors in memory. */
8819 if (TREE_CODE (type
) == VECTOR_TYPE
8820 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
8822 static bool warned_for_pass_big_vectors
= false;
8823 if (TARGET_DEBUG_ARG
)
8824 fprintf (stderr
, "function_arg_pass_by_reference: synthetic vector\n");
8825 if (!warned_for_pass_big_vectors
)
8827 warning (0, "GCC vector passed by reference: "
8828 "non-standard ABI extension with no compatibility guarantee");
8829 warned_for_pass_big_vectors
= true;
8838 rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
)
8841 enum machine_mode reg_mode
= TARGET_32BIT
? SImode
: DImode
;
8846 for (i
= 0; i
< nregs
; i
++)
8848 rtx tem
= adjust_address_nv (x
, reg_mode
, i
* GET_MODE_SIZE (reg_mode
));
8849 if (reload_completed
)
8851 if (! strict_memory_address_p (reg_mode
, XEXP (tem
, 0)))
8854 tem
= simplify_gen_subreg (reg_mode
, x
, BLKmode
,
8855 i
* GET_MODE_SIZE (reg_mode
));
8858 tem
= replace_equiv_address (tem
, XEXP (tem
, 0));
8862 emit_move_insn (tem
, gen_rtx_REG (reg_mode
, regno
+ i
));
8866 /* Perform any needed actions needed for a function that is receiving a
8867 variable number of arguments.
8871 MODE and TYPE are the mode and type of the current parameter.
8873 PRETEND_SIZE is a variable that should be set to the amount of stack
8874 that must be pushed by the prolog to pretend that our caller pushed
8877 Normally, this macro will push all remaining incoming registers on the
8878 stack and set PRETEND_SIZE to the length of the registers pushed. */
8881 setup_incoming_varargs (cumulative_args_t cum
, enum machine_mode mode
,
8882 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
8885 CUMULATIVE_ARGS next_cum
;
8886 int reg_size
= TARGET_32BIT
? 4 : 8;
8887 rtx save_area
= NULL_RTX
, mem
;
8888 int first_reg_offset
;
8891 /* Skip the last named argument. */
8892 next_cum
= *get_cumulative_args (cum
);
8893 rs6000_function_arg_advance_1 (&next_cum
, mode
, type
, true, 0);
8895 if (DEFAULT_ABI
== ABI_V4
)
8897 first_reg_offset
= next_cum
.sysv_gregno
- GP_ARG_MIN_REG
;
8901 int gpr_reg_num
= 0, gpr_size
= 0, fpr_size
= 0;
8902 HOST_WIDE_INT offset
= 0;
8904 /* Try to optimize the size of the varargs save area.
8905 The ABI requires that ap.reg_save_area is doubleword
8906 aligned, but we don't need to allocate space for all
8907 the bytes, only those to which we actually will save
8909 if (cfun
->va_list_gpr_size
&& first_reg_offset
< GP_ARG_NUM_REG
)
8910 gpr_reg_num
= GP_ARG_NUM_REG
- first_reg_offset
;
8911 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
8912 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
8913 && cfun
->va_list_fpr_size
)
8916 fpr_size
= (next_cum
.fregno
- FP_ARG_MIN_REG
)
8917 * UNITS_PER_FP_WORD
;
8918 if (cfun
->va_list_fpr_size
8919 < FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
8920 fpr_size
+= cfun
->va_list_fpr_size
* UNITS_PER_FP_WORD
;
8922 fpr_size
+= (FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
8923 * UNITS_PER_FP_WORD
;
8927 offset
= -((first_reg_offset
* reg_size
) & ~7);
8928 if (!fpr_size
&& gpr_reg_num
> cfun
->va_list_gpr_size
)
8930 gpr_reg_num
= cfun
->va_list_gpr_size
;
8931 if (reg_size
== 4 && (first_reg_offset
& 1))
8934 gpr_size
= (gpr_reg_num
* reg_size
+ 7) & ~7;
8937 offset
= - (int) (next_cum
.fregno
- FP_ARG_MIN_REG
)
8939 - (int) (GP_ARG_NUM_REG
* reg_size
);
8941 if (gpr_size
+ fpr_size
)
8944 = assign_stack_local (BLKmode
, gpr_size
+ fpr_size
, 64);
8945 gcc_assert (GET_CODE (reg_save_area
) == MEM
);
8946 reg_save_area
= XEXP (reg_save_area
, 0);
8947 if (GET_CODE (reg_save_area
) == PLUS
)
8949 gcc_assert (XEXP (reg_save_area
, 0)
8950 == virtual_stack_vars_rtx
);
8951 gcc_assert (GET_CODE (XEXP (reg_save_area
, 1)) == CONST_INT
);
8952 offset
+= INTVAL (XEXP (reg_save_area
, 1));
8955 gcc_assert (reg_save_area
== virtual_stack_vars_rtx
);
8958 cfun
->machine
->varargs_save_offset
= offset
;
8959 save_area
= plus_constant (virtual_stack_vars_rtx
, offset
);
8964 first_reg_offset
= next_cum
.words
;
8965 save_area
= virtual_incoming_args_rtx
;
8967 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
8968 first_reg_offset
+= rs6000_arg_size (TYPE_MODE (type
), type
);
8971 set
= get_varargs_alias_set ();
8972 if (! no_rtl
&& first_reg_offset
< GP_ARG_NUM_REG
8973 && cfun
->va_list_gpr_size
)
8975 int nregs
= GP_ARG_NUM_REG
- first_reg_offset
;
8977 if (va_list_gpr_counter_field
)
8979 /* V4 va_list_gpr_size counts number of registers needed. */
8980 if (nregs
> cfun
->va_list_gpr_size
)
8981 nregs
= cfun
->va_list_gpr_size
;
8985 /* char * va_list instead counts number of bytes needed. */
8986 if (nregs
> cfun
->va_list_gpr_size
/ reg_size
)
8987 nregs
= cfun
->va_list_gpr_size
/ reg_size
;
8990 mem
= gen_rtx_MEM (BLKmode
,
8991 plus_constant (save_area
,
8992 first_reg_offset
* reg_size
));
8993 MEM_NOTRAP_P (mem
) = 1;
8994 set_mem_alias_set (mem
, set
);
8995 set_mem_align (mem
, BITS_PER_WORD
);
8997 rs6000_move_block_from_reg (GP_ARG_MIN_REG
+ first_reg_offset
, mem
,
9001 /* Save FP registers if needed. */
9002 if (DEFAULT_ABI
== ABI_V4
9003 && TARGET_HARD_FLOAT
&& TARGET_FPRS
9005 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
9006 && cfun
->va_list_fpr_size
)
9008 int fregno
= next_cum
.fregno
, nregs
;
9009 rtx cr1
= gen_rtx_REG (CCmode
, CR1_REGNO
);
9010 rtx lab
= gen_label_rtx ();
9011 int off
= (GP_ARG_NUM_REG
* reg_size
) + ((fregno
- FP_ARG_MIN_REG
)
9012 * UNITS_PER_FP_WORD
);
9015 (gen_rtx_SET (VOIDmode
,
9017 gen_rtx_IF_THEN_ELSE (VOIDmode
,
9018 gen_rtx_NE (VOIDmode
, cr1
,
9020 gen_rtx_LABEL_REF (VOIDmode
, lab
),
9024 fregno
<= FP_ARG_V4_MAX_REG
&& nregs
< cfun
->va_list_fpr_size
;
9025 fregno
++, off
+= UNITS_PER_FP_WORD
, nregs
++)
9027 mem
= gen_rtx_MEM ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
9029 plus_constant (save_area
, off
));
9030 MEM_NOTRAP_P (mem
) = 1;
9031 set_mem_alias_set (mem
, set
);
9032 set_mem_align (mem
, GET_MODE_ALIGNMENT (
9033 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
9034 ? DFmode
: SFmode
));
9035 emit_move_insn (mem
, gen_rtx_REG (
9036 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
9037 ? DFmode
: SFmode
, fregno
));
9044 /* Create the va_list data type. */
9047 rs6000_build_builtin_va_list (void)
9049 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
, record
, type_decl
;
9051 /* For AIX, prefer 'char *' because that's what the system
9052 header files like. */
9053 if (DEFAULT_ABI
!= ABI_V4
)
9054 return build_pointer_type (char_type_node
);
9056 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
9057 type_decl
= build_decl (BUILTINS_LOCATION
, TYPE_DECL
,
9058 get_identifier ("__va_list_tag"), record
);
9060 f_gpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("gpr"),
9061 unsigned_char_type_node
);
9062 f_fpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("fpr"),
9063 unsigned_char_type_node
);
9064 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
9066 f_res
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
9067 get_identifier ("reserved"), short_unsigned_type_node
);
9068 f_ovf
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
9069 get_identifier ("overflow_arg_area"),
9071 f_sav
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
9072 get_identifier ("reg_save_area"),
9075 va_list_gpr_counter_field
= f_gpr
;
9076 va_list_fpr_counter_field
= f_fpr
;
9078 DECL_FIELD_CONTEXT (f_gpr
) = record
;
9079 DECL_FIELD_CONTEXT (f_fpr
) = record
;
9080 DECL_FIELD_CONTEXT (f_res
) = record
;
9081 DECL_FIELD_CONTEXT (f_ovf
) = record
;
9082 DECL_FIELD_CONTEXT (f_sav
) = record
;
9084 TYPE_STUB_DECL (record
) = type_decl
;
9085 TYPE_NAME (record
) = type_decl
;
9086 TYPE_FIELDS (record
) = f_gpr
;
9087 DECL_CHAIN (f_gpr
) = f_fpr
;
9088 DECL_CHAIN (f_fpr
) = f_res
;
9089 DECL_CHAIN (f_res
) = f_ovf
;
9090 DECL_CHAIN (f_ovf
) = f_sav
;
9092 layout_type (record
);
9094 /* The correct type is an array type of one element. */
9095 return build_array_type (record
, build_index_type (size_zero_node
));
9098 /* Implement va_start. */
9101 rs6000_va_start (tree valist
, rtx nextarg
)
9103 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
9104 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
9105 tree gpr
, fpr
, ovf
, sav
, t
;
9107 /* Only SVR4 needs something special. */
9108 if (DEFAULT_ABI
!= ABI_V4
)
9110 std_expand_builtin_va_start (valist
, nextarg
);
9114 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
9115 f_fpr
= DECL_CHAIN (f_gpr
);
9116 f_res
= DECL_CHAIN (f_fpr
);
9117 f_ovf
= DECL_CHAIN (f_res
);
9118 f_sav
= DECL_CHAIN (f_ovf
);
9120 valist
= build_simple_mem_ref (valist
);
9121 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
9122 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
9124 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
9126 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
9129 /* Count number of gp and fp argument registers used. */
9130 words
= crtl
->args
.info
.words
;
9131 n_gpr
= MIN (crtl
->args
.info
.sysv_gregno
- GP_ARG_MIN_REG
,
9133 n_fpr
= MIN (crtl
->args
.info
.fregno
- FP_ARG_MIN_REG
,
9136 if (TARGET_DEBUG_ARG
)
9137 fprintf (stderr
, "va_start: words = "HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
9138 HOST_WIDE_INT_PRINT_DEC
", n_fpr = "HOST_WIDE_INT_PRINT_DEC
"\n",
9139 words
, n_gpr
, n_fpr
);
9141 if (cfun
->va_list_gpr_size
)
9143 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
9144 build_int_cst (NULL_TREE
, n_gpr
));
9145 TREE_SIDE_EFFECTS (t
) = 1;
9146 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9149 if (cfun
->va_list_fpr_size
)
9151 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
9152 build_int_cst (NULL_TREE
, n_fpr
));
9153 TREE_SIDE_EFFECTS (t
) = 1;
9154 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9156 #ifdef HAVE_AS_GNU_ATTRIBUTE
9157 if (call_ABI_of_interest (cfun
->decl
))
9158 rs6000_passes_float
= true;
9162 /* Find the overflow area. */
9163 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
9165 t
= fold_build_pointer_plus_hwi (t
, words
* UNITS_PER_WORD
);
9166 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
9167 TREE_SIDE_EFFECTS (t
) = 1;
9168 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9170 /* If there were no va_arg invocations, don't set up the register
9172 if (!cfun
->va_list_gpr_size
9173 && !cfun
->va_list_fpr_size
9174 && n_gpr
< GP_ARG_NUM_REG
9175 && n_fpr
< FP_ARG_V4_MAX_REG
)
9178 /* Find the register save area. */
9179 t
= make_tree (TREE_TYPE (sav
), virtual_stack_vars_rtx
);
9180 if (cfun
->machine
->varargs_save_offset
)
9181 t
= fold_build_pointer_plus_hwi (t
, cfun
->machine
->varargs_save_offset
);
9182 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
9183 TREE_SIDE_EFFECTS (t
) = 1;
9184 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
9187 /* Implement va_arg. */
9190 rs6000_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
9193 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
9194 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
9195 int size
, rsize
, n_reg
, sav_ofs
, sav_scale
;
9196 tree lab_false
, lab_over
, addr
;
9198 tree ptrtype
= build_pointer_type_for_mode (type
, ptr_mode
, true);
9202 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
9204 t
= rs6000_gimplify_va_arg (valist
, ptrtype
, pre_p
, post_p
);
9205 return build_va_arg_indirect_ref (t
);
9208 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
9209 earlier version of gcc, with the property that it always applied alignment
9210 adjustments to the va-args (even for zero-sized types). The cheapest way
9211 to deal with this is to replicate the effect of the part of
9212 std_gimplify_va_arg_expr that carries out the align adjust, for the case
9214 We don't need to check for pass-by-reference because of the test above.
9215 We can return a simplifed answer, since we know there's no offset to add. */
9218 && rs6000_darwin64_abi
9219 && integer_zerop (TYPE_SIZE (type
)))
9221 unsigned HOST_WIDE_INT align
, boundary
;
9222 tree valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
9223 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
9224 boundary
= rs6000_function_arg_boundary (TYPE_MODE (type
), type
);
9225 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
9226 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
9227 boundary
/= BITS_PER_UNIT
;
9228 if (boundary
> align
)
9231 /* This updates arg ptr by the amount that would be necessary
9232 to align the zero-sized (but not zero-alignment) item. */
9233 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
9234 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
9235 gimplify_and_add (t
, pre_p
);
9237 t
= fold_convert (sizetype
, valist_tmp
);
9238 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
9239 fold_convert (TREE_TYPE (valist
),
9240 fold_build2 (BIT_AND_EXPR
, sizetype
, t
,
9241 size_int (-boundary
))));
9242 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
9243 gimplify_and_add (t
, pre_p
);
9245 /* Since it is zero-sized there's no increment for the item itself. */
9246 valist_tmp
= fold_convert (build_pointer_type (type
), valist_tmp
);
9247 return build_va_arg_indirect_ref (valist_tmp
);
9250 if (DEFAULT_ABI
!= ABI_V4
)
9252 if (targetm
.calls
.split_complex_arg
&& TREE_CODE (type
) == COMPLEX_TYPE
)
9254 tree elem_type
= TREE_TYPE (type
);
9255 enum machine_mode elem_mode
= TYPE_MODE (elem_type
);
9256 int elem_size
= GET_MODE_SIZE (elem_mode
);
9258 if (elem_size
< UNITS_PER_WORD
)
9260 tree real_part
, imag_part
;
9261 gimple_seq post
= NULL
;
9263 real_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
9265 /* Copy the value into a temporary, lest the formal temporary
9266 be reused out from under us. */
9267 real_part
= get_initialized_tmp_var (real_part
, pre_p
, &post
);
9268 gimple_seq_add_seq (pre_p
, post
);
9270 imag_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
9273 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
9277 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
9280 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
9281 f_fpr
= DECL_CHAIN (f_gpr
);
9282 f_res
= DECL_CHAIN (f_fpr
);
9283 f_ovf
= DECL_CHAIN (f_res
);
9284 f_sav
= DECL_CHAIN (f_ovf
);
9286 valist
= build_va_arg_indirect_ref (valist
);
9287 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
9288 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
9290 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
9292 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
9295 size
= int_size_in_bytes (type
);
9296 rsize
= (size
+ 3) / 4;
9299 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
9300 && ((TARGET_SINGLE_FLOAT
&& TYPE_MODE (type
) == SFmode
)
9301 || (TARGET_DOUBLE_FLOAT
9302 && (TYPE_MODE (type
) == DFmode
9303 || TYPE_MODE (type
) == TFmode
9304 || TYPE_MODE (type
) == SDmode
9305 || TYPE_MODE (type
) == DDmode
9306 || TYPE_MODE (type
) == TDmode
))))
9308 /* FP args go in FP registers, if present. */
9310 n_reg
= (size
+ 7) / 8;
9311 sav_ofs
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4) * 4;
9312 sav_scale
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4);
9313 if (TYPE_MODE (type
) != SFmode
&& TYPE_MODE (type
) != SDmode
)
9318 /* Otherwise into GP registers. */
9327 /* Pull the value out of the saved registers.... */
9330 addr
= create_tmp_var (ptr_type_node
, "addr");
9332 /* AltiVec vectors never go in registers when -mabi=altivec. */
9333 if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
9337 lab_false
= create_artificial_label (input_location
);
9338 lab_over
= create_artificial_label (input_location
);
9340 /* Long long and SPE vectors are aligned in the registers.
9341 As are any other 2 gpr item such as complex int due to a
9342 historical mistake. */
9344 if (n_reg
== 2 && reg
== gpr
)
9347 u
= build2 (BIT_AND_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
9348 build_int_cst (TREE_TYPE (reg
), n_reg
- 1));
9349 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
),
9350 unshare_expr (reg
), u
);
9352 /* _Decimal128 is passed in even/odd fpr pairs; the stored
9353 reg number is 0 for f1, so we want to make it odd. */
9354 else if (reg
== fpr
&& TYPE_MODE (type
) == TDmode
)
9356 t
= build2 (BIT_IOR_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
9357 build_int_cst (TREE_TYPE (reg
), 1));
9358 u
= build2 (MODIFY_EXPR
, void_type_node
, unshare_expr (reg
), t
);
9361 t
= fold_convert (TREE_TYPE (reg
), size_int (8 - n_reg
+ 1));
9362 t
= build2 (GE_EXPR
, boolean_type_node
, u
, t
);
9363 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
9364 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
9365 gimplify_and_add (t
, pre_p
);
9369 t
= fold_build_pointer_plus_hwi (sav
, sav_ofs
);
9371 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
9372 build_int_cst (TREE_TYPE (reg
), n_reg
));
9373 u
= fold_convert (sizetype
, u
);
9374 u
= build2 (MULT_EXPR
, sizetype
, u
, size_int (sav_scale
));
9375 t
= fold_build_pointer_plus (t
, u
);
9377 /* _Decimal32 varargs are located in the second word of the 64-bit
9378 FP register for 32-bit binaries. */
9379 if (!TARGET_POWERPC64
9380 && TARGET_HARD_FLOAT
&& TARGET_FPRS
9381 && TYPE_MODE (type
) == SDmode
)
9382 t
= fold_build_pointer_plus_hwi (t
, size
);
9384 gimplify_assign (addr
, t
, pre_p
);
9386 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
9388 stmt
= gimple_build_label (lab_false
);
9389 gimple_seq_add_stmt (pre_p
, stmt
);
9391 if ((n_reg
== 2 && !regalign
) || n_reg
> 2)
9393 /* Ensure that we don't find any more args in regs.
9394 Alignment has taken care of for special cases. */
9395 gimplify_assign (reg
, build_int_cst (TREE_TYPE (reg
), 8), pre_p
);
9399 /* ... otherwise out of the overflow area. */
9401 /* Care for on-stack alignment if needed. */
9405 t
= fold_build_pointer_plus_hwi (t
, align
- 1);
9406 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
9407 build_int_cst (TREE_TYPE (t
), -align
));
9409 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
9411 gimplify_assign (unshare_expr (addr
), t
, pre_p
);
9413 t
= fold_build_pointer_plus_hwi (t
, size
);
9414 gimplify_assign (unshare_expr (ovf
), t
, pre_p
);
9418 stmt
= gimple_build_label (lab_over
);
9419 gimple_seq_add_stmt (pre_p
, stmt
);
9422 if (STRICT_ALIGNMENT
9423 && (TYPE_ALIGN (type
)
9424 > (unsigned) BITS_PER_UNIT
* (align
< 4 ? 4 : align
)))
9426 /* The value (of type complex double, for example) may not be
9427 aligned in memory in the saved registers, so copy via a
9428 temporary. (This is the same code as used for SPARC.) */
9429 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
9430 tree dest_addr
= build_fold_addr_expr (tmp
);
9432 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
9433 3, dest_addr
, addr
, size_int (rsize
* 4));
9435 gimplify_and_add (copy
, pre_p
);
9439 addr
= fold_convert (ptrtype
, addr
);
9440 return build_va_arg_indirect_ref (addr
);
9446 def_builtin (const char *name
, tree type
, enum rs6000_builtins code
)
9449 unsigned classify
= rs6000_builtin_info
[(int)code
].attr
;
9450 const char *attr_string
= "";
9452 gcc_assert (name
!= NULL
);
9453 gcc_assert (IN_RANGE ((int)code
, 0, (int)RS6000_BUILTIN_COUNT
));
9455 if (rs6000_builtin_decls
[(int)code
])
9456 fatal_error ("internal error: builtin function %s already processed", name
);
9458 rs6000_builtin_decls
[(int)code
] = t
=
9459 add_builtin_function (name
, type
, (int)code
, BUILT_IN_MD
, NULL
, NULL_TREE
);
9461 /* Set any special attributes. */
9462 if ((classify
& RS6000_BTC_CONST
) != 0)
9464 /* const function, function only depends on the inputs. */
9465 TREE_READONLY (t
) = 1;
9466 TREE_NOTHROW (t
) = 1;
9467 attr_string
= ", pure";
9469 else if ((classify
& RS6000_BTC_PURE
) != 0)
9471 /* pure function, function can read global memory, but does not set any
9473 DECL_PURE_P (t
) = 1;
9474 TREE_NOTHROW (t
) = 1;
9475 attr_string
= ", const";
9477 else if ((classify
& RS6000_BTC_FP
) != 0)
9479 /* Function is a math function. If rounding mode is on, then treat the
9480 function as not reading global memory, but it can have arbitrary side
9481 effects. If it is off, then assume the function is a const function.
9482 This mimics the ATTR_MATHFN_FPROUNDING attribute in
9483 builtin-attribute.def that is used for the math functions. */
9484 TREE_NOTHROW (t
) = 1;
9485 if (flag_rounding_math
)
9487 DECL_PURE_P (t
) = 1;
9488 DECL_IS_NOVOPS (t
) = 1;
9489 attr_string
= ", fp, pure";
9493 TREE_READONLY (t
) = 1;
9494 attr_string
= ", fp, const";
9497 else if ((classify
& RS6000_BTC_ATTR_MASK
) != 0)
9500 if (TARGET_DEBUG_BUILTIN
)
9501 fprintf (stderr
, "rs6000_builtin, code = %4d, %s%s\n",
9502 (int)code
, name
, attr_string
);
9505 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
9507 #undef RS6000_BUILTIN_1
9508 #undef RS6000_BUILTIN_2
9509 #undef RS6000_BUILTIN_3
9510 #undef RS6000_BUILTIN_A
9511 #undef RS6000_BUILTIN_D
9512 #undef RS6000_BUILTIN_E
9513 #undef RS6000_BUILTIN_P
9514 #undef RS6000_BUILTIN_Q
9515 #undef RS6000_BUILTIN_S
9516 #undef RS6000_BUILTIN_X
9518 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9519 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9520 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
9521 { MASK, ICODE, NAME, ENUM },
9523 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9524 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9525 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9526 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9527 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9528 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9529 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9531 static const struct builtin_description bdesc_3arg
[] =
9533 #include "rs6000-builtin.def"
9536 /* DST operations: void foo (void *, const int, const char). */
9538 #undef RS6000_BUILTIN_1
9539 #undef RS6000_BUILTIN_2
9540 #undef RS6000_BUILTIN_3
9541 #undef RS6000_BUILTIN_A
9542 #undef RS6000_BUILTIN_D
9543 #undef RS6000_BUILTIN_E
9544 #undef RS6000_BUILTIN_P
9545 #undef RS6000_BUILTIN_Q
9546 #undef RS6000_BUILTIN_S
9547 #undef RS6000_BUILTIN_X
9549 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9550 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9551 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9552 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9553 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
9554 { MASK, ICODE, NAME, ENUM },
9556 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9557 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9558 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9559 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9560 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9562 static const struct builtin_description bdesc_dst
[] =
9564 #include "rs6000-builtin.def"
9567 /* Simple binary operations: VECc = foo (VECa, VECb). */
9569 #undef RS6000_BUILTIN_1
9570 #undef RS6000_BUILTIN_2
9571 #undef RS6000_BUILTIN_3
9572 #undef RS6000_BUILTIN_A
9573 #undef RS6000_BUILTIN_D
9574 #undef RS6000_BUILTIN_E
9575 #undef RS6000_BUILTIN_P
9576 #undef RS6000_BUILTIN_Q
9577 #undef RS6000_BUILTIN_S
9578 #undef RS6000_BUILTIN_X
9580 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9581 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
9582 { MASK, ICODE, NAME, ENUM },
9584 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9585 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9586 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9587 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9588 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9589 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9590 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9591 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9593 static const struct builtin_description bdesc_2arg
[] =
9595 #include "rs6000-builtin.def"
9598 #undef RS6000_BUILTIN_1
9599 #undef RS6000_BUILTIN_2
9600 #undef RS6000_BUILTIN_3
9601 #undef RS6000_BUILTIN_A
9602 #undef RS6000_BUILTIN_D
9603 #undef RS6000_BUILTIN_E
9604 #undef RS6000_BUILTIN_P
9605 #undef RS6000_BUILTIN_Q
9606 #undef RS6000_BUILTIN_S
9607 #undef RS6000_BUILTIN_X
9609 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9610 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9611 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9612 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9613 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9614 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9615 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
9616 { MASK, ICODE, NAME, ENUM },
9618 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9619 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9620 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9622 /* AltiVec predicates. */
9624 static const struct builtin_description bdesc_altivec_preds
[] =
9626 #include "rs6000-builtin.def"
9629 /* SPE predicates. */
9630 #undef RS6000_BUILTIN_1
9631 #undef RS6000_BUILTIN_2
9632 #undef RS6000_BUILTIN_3
9633 #undef RS6000_BUILTIN_A
9634 #undef RS6000_BUILTIN_D
9635 #undef RS6000_BUILTIN_E
9636 #undef RS6000_BUILTIN_P
9637 #undef RS6000_BUILTIN_Q
9638 #undef RS6000_BUILTIN_S
9639 #undef RS6000_BUILTIN_X
9641 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9642 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9643 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9644 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9645 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9646 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9647 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9648 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9649 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
9650 { MASK, ICODE, NAME, ENUM },
9652 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9654 static const struct builtin_description bdesc_spe_predicates
[] =
9656 #include "rs6000-builtin.def"
9659 /* SPE evsel predicates. */
9660 #undef RS6000_BUILTIN_1
9661 #undef RS6000_BUILTIN_2
9662 #undef RS6000_BUILTIN_3
9663 #undef RS6000_BUILTIN_A
9664 #undef RS6000_BUILTIN_D
9665 #undef RS6000_BUILTIN_E
9666 #undef RS6000_BUILTIN_P
9667 #undef RS6000_BUILTIN_Q
9668 #undef RS6000_BUILTIN_S
9669 #undef RS6000_BUILTIN_X
9671 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9672 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9673 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9674 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9675 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9676 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
9677 { MASK, ICODE, NAME, ENUM },
9679 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9680 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9681 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9682 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9684 static const struct builtin_description bdesc_spe_evsel
[] =
9686 #include "rs6000-builtin.def"
9689 /* PAIRED predicates. */
9690 #undef RS6000_BUILTIN_1
9691 #undef RS6000_BUILTIN_2
9692 #undef RS6000_BUILTIN_3
9693 #undef RS6000_BUILTIN_A
9694 #undef RS6000_BUILTIN_D
9695 #undef RS6000_BUILTIN_E
9696 #undef RS6000_BUILTIN_P
9697 #undef RS6000_BUILTIN_Q
9698 #undef RS6000_BUILTIN_S
9699 #undef RS6000_BUILTIN_X
9701 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9702 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9703 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9704 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9705 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9706 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9707 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9708 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
9709 { MASK, ICODE, NAME, ENUM },
9711 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9712 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9714 static const struct builtin_description bdesc_paired_preds
[] =
9716 #include "rs6000-builtin.def"
9719 /* ABS* operations. */
9721 #undef RS6000_BUILTIN_1
9722 #undef RS6000_BUILTIN_2
9723 #undef RS6000_BUILTIN_3
9724 #undef RS6000_BUILTIN_A
9725 #undef RS6000_BUILTIN_D
9726 #undef RS6000_BUILTIN_E
9727 #undef RS6000_BUILTIN_P
9728 #undef RS6000_BUILTIN_Q
9729 #undef RS6000_BUILTIN_S
9730 #undef RS6000_BUILTIN_X
9732 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9733 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9734 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9735 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
9736 { MASK, ICODE, NAME, ENUM },
9738 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9739 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9740 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9741 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9742 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9743 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9745 static const struct builtin_description bdesc_abs
[] =
9747 #include "rs6000-builtin.def"
9750 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
9753 #undef RS6000_BUILTIN_1
9754 #undef RS6000_BUILTIN_2
9755 #undef RS6000_BUILTIN_3
9756 #undef RS6000_BUILTIN_A
9757 #undef RS6000_BUILTIN_E
9758 #undef RS6000_BUILTIN_D
9759 #undef RS6000_BUILTIN_P
9760 #undef RS6000_BUILTIN_Q
9761 #undef RS6000_BUILTIN_S
9762 #undef RS6000_BUILTIN_X
9764 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
9765 { MASK, ICODE, NAME, ENUM },
9767 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9768 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9769 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9770 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9771 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9772 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9773 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9774 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9775 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9777 static const struct builtin_description bdesc_1arg
[] =
9779 #include "rs6000-builtin.def"
9782 #undef RS6000_BUILTIN_1
9783 #undef RS6000_BUILTIN_2
9784 #undef RS6000_BUILTIN_3
9785 #undef RS6000_BUILTIN_A
9786 #undef RS6000_BUILTIN_D
9787 #undef RS6000_BUILTIN_E
9788 #undef RS6000_BUILTIN_P
9789 #undef RS6000_BUILTIN_Q
9790 #undef RS6000_BUILTIN_S
9791 #undef RS6000_BUILTIN_X
9793 /* Return true if a builtin function is overloaded. */
9795 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode
)
9797 return (rs6000_builtin_info
[(int)fncode
].attr
& RS6000_BTC_OVERLOADED
) != 0;
9802 rs6000_expand_unop_builtin (enum insn_code icode
, tree exp
, rtx target
)
9805 tree arg0
= CALL_EXPR_ARG (exp
, 0);
9806 rtx op0
= expand_normal (arg0
);
9807 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
9808 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
9810 if (icode
== CODE_FOR_nothing
)
9811 /* Builtin not supported on this processor. */
9814 /* If we got invalid arguments bail out before generating bad rtl. */
9815 if (arg0
== error_mark_node
)
9818 if (icode
== CODE_FOR_altivec_vspltisb
9819 || icode
== CODE_FOR_altivec_vspltish
9820 || icode
== CODE_FOR_altivec_vspltisw
9821 || icode
== CODE_FOR_spe_evsplatfi
9822 || icode
== CODE_FOR_spe_evsplati
)
9824 /* Only allow 5-bit *signed* literals. */
9825 if (GET_CODE (op0
) != CONST_INT
9826 || INTVAL (op0
) > 15
9827 || INTVAL (op0
) < -16)
9829 error ("argument 1 must be a 5-bit signed literal");
9835 || GET_MODE (target
) != tmode
9836 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
9837 target
= gen_reg_rtx (tmode
);
9839 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
9840 op0
= copy_to_mode_reg (mode0
, op0
);
9842 pat
= GEN_FCN (icode
) (target
, op0
);
9851 altivec_expand_abs_builtin (enum insn_code icode
, tree exp
, rtx target
)
9853 rtx pat
, scratch1
, scratch2
;
9854 tree arg0
= CALL_EXPR_ARG (exp
, 0);
9855 rtx op0
= expand_normal (arg0
);
9856 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
9857 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
9859 /* If we have invalid arguments, bail out before generating bad rtl. */
9860 if (arg0
== error_mark_node
)
9864 || GET_MODE (target
) != tmode
9865 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
9866 target
= gen_reg_rtx (tmode
);
9868 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
9869 op0
= copy_to_mode_reg (mode0
, op0
);
9871 scratch1
= gen_reg_rtx (mode0
);
9872 scratch2
= gen_reg_rtx (mode0
);
9874 pat
= GEN_FCN (icode
) (target
, op0
, scratch1
, scratch2
);
9883 rs6000_expand_binop_builtin (enum insn_code icode
, tree exp
, rtx target
)
9886 tree arg0
= CALL_EXPR_ARG (exp
, 0);
9887 tree arg1
= CALL_EXPR_ARG (exp
, 1);
9888 rtx op0
= expand_normal (arg0
);
9889 rtx op1
= expand_normal (arg1
);
9890 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
9891 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
9892 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
9894 if (icode
== CODE_FOR_nothing
)
9895 /* Builtin not supported on this processor. */
9898 /* If we got invalid arguments bail out before generating bad rtl. */
9899 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
9902 if (icode
== CODE_FOR_altivec_vcfux
9903 || icode
== CODE_FOR_altivec_vcfsx
9904 || icode
== CODE_FOR_altivec_vctsxs
9905 || icode
== CODE_FOR_altivec_vctuxs
9906 || icode
== CODE_FOR_altivec_vspltb
9907 || icode
== CODE_FOR_altivec_vsplth
9908 || icode
== CODE_FOR_altivec_vspltw
9909 || icode
== CODE_FOR_spe_evaddiw
9910 || icode
== CODE_FOR_spe_evldd
9911 || icode
== CODE_FOR_spe_evldh
9912 || icode
== CODE_FOR_spe_evldw
9913 || icode
== CODE_FOR_spe_evlhhesplat
9914 || icode
== CODE_FOR_spe_evlhhossplat
9915 || icode
== CODE_FOR_spe_evlhhousplat
9916 || icode
== CODE_FOR_spe_evlwhe
9917 || icode
== CODE_FOR_spe_evlwhos
9918 || icode
== CODE_FOR_spe_evlwhou
9919 || icode
== CODE_FOR_spe_evlwhsplat
9920 || icode
== CODE_FOR_spe_evlwwsplat
9921 || icode
== CODE_FOR_spe_evrlwi
9922 || icode
== CODE_FOR_spe_evslwi
9923 || icode
== CODE_FOR_spe_evsrwis
9924 || icode
== CODE_FOR_spe_evsubifw
9925 || icode
== CODE_FOR_spe_evsrwiu
)
9927 /* Only allow 5-bit unsigned literals. */
9929 if (TREE_CODE (arg1
) != INTEGER_CST
9930 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
9932 error ("argument 2 must be a 5-bit unsigned literal");
9938 || GET_MODE (target
) != tmode
9939 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
9940 target
= gen_reg_rtx (tmode
);
9942 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
9943 op0
= copy_to_mode_reg (mode0
, op0
);
9944 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
9945 op1
= copy_to_mode_reg (mode1
, op1
);
9947 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
9956 altivec_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
9959 tree cr6_form
= CALL_EXPR_ARG (exp
, 0);
9960 tree arg0
= CALL_EXPR_ARG (exp
, 1);
9961 tree arg1
= CALL_EXPR_ARG (exp
, 2);
9962 rtx op0
= expand_normal (arg0
);
9963 rtx op1
= expand_normal (arg1
);
9964 enum machine_mode tmode
= SImode
;
9965 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
9966 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
9969 if (TREE_CODE (cr6_form
) != INTEGER_CST
)
9971 error ("argument 1 of __builtin_altivec_predicate must be a constant");
9975 cr6_form_int
= TREE_INT_CST_LOW (cr6_form
);
9977 gcc_assert (mode0
== mode1
);
9979 /* If we have invalid arguments, bail out before generating bad rtl. */
9980 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
9984 || GET_MODE (target
) != tmode
9985 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
9986 target
= gen_reg_rtx (tmode
);
9988 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
9989 op0
= copy_to_mode_reg (mode0
, op0
);
9990 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
9991 op1
= copy_to_mode_reg (mode1
, op1
);
9993 scratch
= gen_reg_rtx (mode0
);
9995 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
10000 /* The vec_any* and vec_all* predicates use the same opcodes for two
10001 different operations, but the bits in CR6 will be different
10002 depending on what information we want. So we have to play tricks
10003 with CR6 to get the right bits out.
10005 If you think this is disgusting, look at the specs for the
10006 AltiVec predicates. */
10008 switch (cr6_form_int
)
10011 emit_insn (gen_cr6_test_for_zero (target
));
10014 emit_insn (gen_cr6_test_for_zero_reverse (target
));
10017 emit_insn (gen_cr6_test_for_lt (target
));
10020 emit_insn (gen_cr6_test_for_lt_reverse (target
));
10023 error ("argument 1 of __builtin_altivec_predicate is out of range");
10031 paired_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
)
10034 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10035 tree arg1
= CALL_EXPR_ARG (exp
, 1);
10036 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10037 enum machine_mode mode0
= Pmode
;
10038 enum machine_mode mode1
= Pmode
;
10039 rtx op0
= expand_normal (arg0
);
10040 rtx op1
= expand_normal (arg1
);
10042 if (icode
== CODE_FOR_nothing
)
10043 /* Builtin not supported on this processor. */
10046 /* If we got invalid arguments bail out before generating bad rtl. */
10047 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
10051 || GET_MODE (target
) != tmode
10052 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10053 target
= gen_reg_rtx (tmode
);
10055 op1
= copy_to_mode_reg (mode1
, op1
);
10057 if (op0
== const0_rtx
)
10059 addr
= gen_rtx_MEM (tmode
, op1
);
10063 op0
= copy_to_mode_reg (mode0
, op0
);
10064 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
10067 pat
= GEN_FCN (icode
) (target
, addr
);
10077 altivec_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
, bool blk
)
10080 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10081 tree arg1
= CALL_EXPR_ARG (exp
, 1);
10082 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10083 enum machine_mode mode0
= Pmode
;
10084 enum machine_mode mode1
= Pmode
;
10085 rtx op0
= expand_normal (arg0
);
10086 rtx op1
= expand_normal (arg1
);
10088 if (icode
== CODE_FOR_nothing
)
10089 /* Builtin not supported on this processor. */
10092 /* If we got invalid arguments bail out before generating bad rtl. */
10093 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
10097 || GET_MODE (target
) != tmode
10098 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10099 target
= gen_reg_rtx (tmode
);
10101 op1
= copy_to_mode_reg (mode1
, op1
);
10103 if (op0
== const0_rtx
)
10105 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, op1
);
10109 op0
= copy_to_mode_reg (mode0
, op0
);
10110 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
10113 pat
= GEN_FCN (icode
) (target
, addr
);
10123 spe_expand_stv_builtin (enum insn_code icode
, tree exp
)
10125 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10126 tree arg1
= CALL_EXPR_ARG (exp
, 1);
10127 tree arg2
= CALL_EXPR_ARG (exp
, 2);
10128 rtx op0
= expand_normal (arg0
);
10129 rtx op1
= expand_normal (arg1
);
10130 rtx op2
= expand_normal (arg2
);
10132 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
10133 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
10134 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
10136 /* Invalid arguments. Bail before doing anything stoopid! */
10137 if (arg0
== error_mark_node
10138 || arg1
== error_mark_node
10139 || arg2
== error_mark_node
)
10142 if (! (*insn_data
[icode
].operand
[2].predicate
) (op0
, mode2
))
10143 op0
= copy_to_mode_reg (mode2
, op0
);
10144 if (! (*insn_data
[icode
].operand
[0].predicate
) (op1
, mode0
))
10145 op1
= copy_to_mode_reg (mode0
, op1
);
10146 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
10147 op2
= copy_to_mode_reg (mode1
, op2
);
10149 pat
= GEN_FCN (icode
) (op1
, op2
, op0
);
10156 paired_expand_stv_builtin (enum insn_code icode
, tree exp
)
10158 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10159 tree arg1
= CALL_EXPR_ARG (exp
, 1);
10160 tree arg2
= CALL_EXPR_ARG (exp
, 2);
10161 rtx op0
= expand_normal (arg0
);
10162 rtx op1
= expand_normal (arg1
);
10163 rtx op2
= expand_normal (arg2
);
10165 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10166 enum machine_mode mode1
= Pmode
;
10167 enum machine_mode mode2
= Pmode
;
10169 /* Invalid arguments. Bail before doing anything stoopid! */
10170 if (arg0
== error_mark_node
10171 || arg1
== error_mark_node
10172 || arg2
== error_mark_node
)
10175 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
10176 op0
= copy_to_mode_reg (tmode
, op0
);
10178 op2
= copy_to_mode_reg (mode2
, op2
);
10180 if (op1
== const0_rtx
)
10182 addr
= gen_rtx_MEM (tmode
, op2
);
10186 op1
= copy_to_mode_reg (mode1
, op1
);
10187 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
10190 pat
= GEN_FCN (icode
) (addr
, op0
);
10197 altivec_expand_stv_builtin (enum insn_code icode
, tree exp
)
10199 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10200 tree arg1
= CALL_EXPR_ARG (exp
, 1);
10201 tree arg2
= CALL_EXPR_ARG (exp
, 2);
10202 rtx op0
= expand_normal (arg0
);
10203 rtx op1
= expand_normal (arg1
);
10204 rtx op2
= expand_normal (arg2
);
10206 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10207 enum machine_mode smode
= insn_data
[icode
].operand
[1].mode
;
10208 enum machine_mode mode1
= Pmode
;
10209 enum machine_mode mode2
= Pmode
;
10211 /* Invalid arguments. Bail before doing anything stoopid! */
10212 if (arg0
== error_mark_node
10213 || arg1
== error_mark_node
10214 || arg2
== error_mark_node
)
10217 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, smode
))
10218 op0
= copy_to_mode_reg (smode
, op0
);
10220 op2
= copy_to_mode_reg (mode2
, op2
);
10222 if (op1
== const0_rtx
)
10224 addr
= gen_rtx_MEM (tmode
, op2
);
10228 op1
= copy_to_mode_reg (mode1
, op1
);
10229 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
10232 pat
= GEN_FCN (icode
) (addr
, op0
);
10239 rs6000_expand_ternop_builtin (enum insn_code icode
, tree exp
, rtx target
)
10242 tree arg0
= CALL_EXPR_ARG (exp
, 0);
10243 tree arg1
= CALL_EXPR_ARG (exp
, 1);
10244 tree arg2
= CALL_EXPR_ARG (exp
, 2);
10245 rtx op0
= expand_normal (arg0
);
10246 rtx op1
= expand_normal (arg1
);
10247 rtx op2
= expand_normal (arg2
);
10248 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10249 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
10250 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
10251 enum machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
10253 if (icode
== CODE_FOR_nothing
)
10254 /* Builtin not supported on this processor. */
10257 /* If we got invalid arguments bail out before generating bad rtl. */
10258 if (arg0
== error_mark_node
10259 || arg1
== error_mark_node
10260 || arg2
== error_mark_node
)
10263 /* Check and prepare argument depending on the instruction code.
10265 Note that a switch statement instead of the sequence of tests
10266 would be incorrect as many of the CODE_FOR values could be
10267 CODE_FOR_nothing and that would yield multiple alternatives
10268 with identical values. We'd never reach here at runtime in
10270 if (icode
== CODE_FOR_altivec_vsldoi_v4sf
10271 || icode
== CODE_FOR_altivec_vsldoi_v4si
10272 || icode
== CODE_FOR_altivec_vsldoi_v8hi
10273 || icode
== CODE_FOR_altivec_vsldoi_v16qi
)
10275 /* Only allow 4-bit unsigned literals. */
10277 if (TREE_CODE (arg2
) != INTEGER_CST
10278 || TREE_INT_CST_LOW (arg2
) & ~0xf)
10280 error ("argument 3 must be a 4-bit unsigned literal");
10284 else if (icode
== CODE_FOR_vsx_xxpermdi_v2df
10285 || icode
== CODE_FOR_vsx_xxpermdi_v2di
10286 || icode
== CODE_FOR_vsx_xxsldwi_v16qi
10287 || icode
== CODE_FOR_vsx_xxsldwi_v8hi
10288 || icode
== CODE_FOR_vsx_xxsldwi_v4si
10289 || icode
== CODE_FOR_vsx_xxsldwi_v4sf
10290 || icode
== CODE_FOR_vsx_xxsldwi_v2di
10291 || icode
== CODE_FOR_vsx_xxsldwi_v2df
)
10293 /* Only allow 2-bit unsigned literals. */
10295 if (TREE_CODE (arg2
) != INTEGER_CST
10296 || TREE_INT_CST_LOW (arg2
) & ~0x3)
10298 error ("argument 3 must be a 2-bit unsigned literal");
10302 else if (icode
== CODE_FOR_vsx_set_v2df
10303 || icode
== CODE_FOR_vsx_set_v2di
)
10305 /* Only allow 1-bit unsigned literals. */
10307 if (TREE_CODE (arg2
) != INTEGER_CST
10308 || TREE_INT_CST_LOW (arg2
) & ~0x1)
10310 error ("argument 3 must be a 1-bit unsigned literal");
10316 || GET_MODE (target
) != tmode
10317 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10318 target
= gen_reg_rtx (tmode
);
10320 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
10321 op0
= copy_to_mode_reg (mode0
, op0
);
10322 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
10323 op1
= copy_to_mode_reg (mode1
, op1
);
10324 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
10325 op2
= copy_to_mode_reg (mode2
, op2
);
10327 if (TARGET_PAIRED_FLOAT
&& icode
== CODE_FOR_selv2sf4
)
10328 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
, CONST0_RTX (SFmode
));
10330 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
10338 /* Expand the lvx builtins. */
10340 altivec_expand_ld_builtin (tree exp
, rtx target
, bool *expandedp
)
10342 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10343 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
10345 enum machine_mode tmode
, mode0
;
10347 enum insn_code icode
;
10351 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi
:
10352 icode
= CODE_FOR_vector_altivec_load_v16qi
;
10354 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi
:
10355 icode
= CODE_FOR_vector_altivec_load_v8hi
;
10357 case ALTIVEC_BUILTIN_LD_INTERNAL_4si
:
10358 icode
= CODE_FOR_vector_altivec_load_v4si
;
10360 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf
:
10361 icode
= CODE_FOR_vector_altivec_load_v4sf
;
10363 case ALTIVEC_BUILTIN_LD_INTERNAL_2df
:
10364 icode
= CODE_FOR_vector_altivec_load_v2df
;
10366 case ALTIVEC_BUILTIN_LD_INTERNAL_2di
:
10367 icode
= CODE_FOR_vector_altivec_load_v2di
;
10370 *expandedp
= false;
10376 arg0
= CALL_EXPR_ARG (exp
, 0);
10377 op0
= expand_normal (arg0
);
10378 tmode
= insn_data
[icode
].operand
[0].mode
;
10379 mode0
= insn_data
[icode
].operand
[1].mode
;
10382 || GET_MODE (target
) != tmode
10383 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10384 target
= gen_reg_rtx (tmode
);
10386 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
10387 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
10389 pat
= GEN_FCN (icode
) (target
, op0
);
10396 /* Expand the stvx builtins. */
10398 altivec_expand_st_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
10401 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10402 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
10404 enum machine_mode mode0
, mode1
;
10406 enum insn_code icode
;
10410 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi
:
10411 icode
= CODE_FOR_vector_altivec_store_v16qi
;
10413 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi
:
10414 icode
= CODE_FOR_vector_altivec_store_v8hi
;
10416 case ALTIVEC_BUILTIN_ST_INTERNAL_4si
:
10417 icode
= CODE_FOR_vector_altivec_store_v4si
;
10419 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf
:
10420 icode
= CODE_FOR_vector_altivec_store_v4sf
;
10422 case ALTIVEC_BUILTIN_ST_INTERNAL_2df
:
10423 icode
= CODE_FOR_vector_altivec_store_v2df
;
10425 case ALTIVEC_BUILTIN_ST_INTERNAL_2di
:
10426 icode
= CODE_FOR_vector_altivec_store_v2di
;
10429 *expandedp
= false;
10433 arg0
= CALL_EXPR_ARG (exp
, 0);
10434 arg1
= CALL_EXPR_ARG (exp
, 1);
10435 op0
= expand_normal (arg0
);
10436 op1
= expand_normal (arg1
);
10437 mode0
= insn_data
[icode
].operand
[0].mode
;
10438 mode1
= insn_data
[icode
].operand
[1].mode
;
10440 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
10441 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
10442 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
10443 op1
= copy_to_mode_reg (mode1
, op1
);
10445 pat
= GEN_FCN (icode
) (op0
, op1
);
10453 /* Expand the dst builtins. */
10455 altivec_expand_dst_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
10458 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10459 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
10460 tree arg0
, arg1
, arg2
;
10461 enum machine_mode mode0
, mode1
;
10462 rtx pat
, op0
, op1
, op2
;
10463 const struct builtin_description
*d
;
10466 *expandedp
= false;
10468 /* Handle DST variants. */
10470 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
10471 if (d
->code
== fcode
)
10473 arg0
= CALL_EXPR_ARG (exp
, 0);
10474 arg1
= CALL_EXPR_ARG (exp
, 1);
10475 arg2
= CALL_EXPR_ARG (exp
, 2);
10476 op0
= expand_normal (arg0
);
10477 op1
= expand_normal (arg1
);
10478 op2
= expand_normal (arg2
);
10479 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
10480 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
10482 /* Invalid arguments, bail out before generating bad rtl. */
10483 if (arg0
== error_mark_node
10484 || arg1
== error_mark_node
10485 || arg2
== error_mark_node
)
10490 if (TREE_CODE (arg2
) != INTEGER_CST
10491 || TREE_INT_CST_LOW (arg2
) & ~0x3)
10493 error ("argument to %qs must be a 2-bit unsigned literal", d
->name
);
10497 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
10498 op0
= copy_to_mode_reg (Pmode
, op0
);
10499 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
10500 op1
= copy_to_mode_reg (mode1
, op1
);
10502 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
10512 /* Expand vec_init builtin. */
10514 altivec_expand_vec_init_builtin (tree type
, tree exp
, rtx target
)
10516 enum machine_mode tmode
= TYPE_MODE (type
);
10517 enum machine_mode inner_mode
= GET_MODE_INNER (tmode
);
10518 int i
, n_elt
= GET_MODE_NUNITS (tmode
);
10519 rtvec v
= rtvec_alloc (n_elt
);
10521 gcc_assert (VECTOR_MODE_P (tmode
));
10522 gcc_assert (n_elt
== call_expr_nargs (exp
));
10524 for (i
= 0; i
< n_elt
; ++i
)
10526 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, i
));
10527 RTVEC_ELT (v
, i
) = gen_lowpart (inner_mode
, x
);
10530 if (!target
|| !register_operand (target
, tmode
))
10531 target
= gen_reg_rtx (tmode
);
10533 rs6000_expand_vector_init (target
, gen_rtx_PARALLEL (tmode
, v
));
10537 /* Return the integer constant in ARG. Constrain it to be in the range
10538 of the subparts of VEC_TYPE; issue an error if not. */
10541 get_element_number (tree vec_type
, tree arg
)
10543 unsigned HOST_WIDE_INT elt
, max
= TYPE_VECTOR_SUBPARTS (vec_type
) - 1;
10545 if (!host_integerp (arg
, 1)
10546 || (elt
= tree_low_cst (arg
, 1), elt
> max
))
10548 error ("selector must be an integer constant in the range 0..%wi", max
);
10555 /* Expand vec_set builtin. */
10557 altivec_expand_vec_set_builtin (tree exp
)
10559 enum machine_mode tmode
, mode1
;
10560 tree arg0
, arg1
, arg2
;
10564 arg0
= CALL_EXPR_ARG (exp
, 0);
10565 arg1
= CALL_EXPR_ARG (exp
, 1);
10566 arg2
= CALL_EXPR_ARG (exp
, 2);
10568 tmode
= TYPE_MODE (TREE_TYPE (arg0
));
10569 mode1
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
10570 gcc_assert (VECTOR_MODE_P (tmode
));
10572 op0
= expand_expr (arg0
, NULL_RTX
, tmode
, EXPAND_NORMAL
);
10573 op1
= expand_expr (arg1
, NULL_RTX
, mode1
, EXPAND_NORMAL
);
10574 elt
= get_element_number (TREE_TYPE (arg0
), arg2
);
10576 if (GET_MODE (op1
) != mode1
&& GET_MODE (op1
) != VOIDmode
)
10577 op1
= convert_modes (mode1
, GET_MODE (op1
), op1
, true);
10579 op0
= force_reg (tmode
, op0
);
10580 op1
= force_reg (mode1
, op1
);
10582 rs6000_expand_vector_set (op0
, op1
, elt
);
10587 /* Expand vec_ext builtin. */
10589 altivec_expand_vec_ext_builtin (tree exp
, rtx target
)
10591 enum machine_mode tmode
, mode0
;
10596 arg0
= CALL_EXPR_ARG (exp
, 0);
10597 arg1
= CALL_EXPR_ARG (exp
, 1);
10599 op0
= expand_normal (arg0
);
10600 elt
= get_element_number (TREE_TYPE (arg0
), arg1
);
10602 tmode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
10603 mode0
= TYPE_MODE (TREE_TYPE (arg0
));
10604 gcc_assert (VECTOR_MODE_P (mode0
));
10606 op0
= force_reg (mode0
, op0
);
10608 if (optimize
|| !target
|| !register_operand (target
, tmode
))
10609 target
= gen_reg_rtx (tmode
);
10611 rs6000_expand_vector_extract (target
, op0
, elt
);
10616 /* Expand the builtin in EXP and store the result in TARGET. Store
10617 true in *EXPANDEDP if we found a builtin to expand. */
10619 altivec_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
10621 const struct builtin_description
*d
;
10623 enum insn_code icode
;
10624 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10627 enum machine_mode tmode
, mode0
;
10628 enum rs6000_builtins fcode
10629 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
10631 if (rs6000_overloaded_builtin_p (fcode
))
10634 error ("unresolved overload for Altivec builtin %qF", fndecl
);
10636 /* Given it is invalid, just generate a normal call. */
10637 return expand_call (exp
, target
, false);
10640 target
= altivec_expand_ld_builtin (exp
, target
, expandedp
);
10644 target
= altivec_expand_st_builtin (exp
, target
, expandedp
);
10648 target
= altivec_expand_dst_builtin (exp
, target
, expandedp
);
10656 case ALTIVEC_BUILTIN_STVX
:
10657 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si
, exp
);
10658 case ALTIVEC_BUILTIN_STVEBX
:
10659 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx
, exp
);
10660 case ALTIVEC_BUILTIN_STVEHX
:
10661 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx
, exp
);
10662 case ALTIVEC_BUILTIN_STVEWX
:
10663 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx
, exp
);
10664 case ALTIVEC_BUILTIN_STVXL
:
10665 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl
, exp
);
10667 case ALTIVEC_BUILTIN_STVLX
:
10668 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx
, exp
);
10669 case ALTIVEC_BUILTIN_STVLXL
:
10670 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl
, exp
);
10671 case ALTIVEC_BUILTIN_STVRX
:
10672 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx
, exp
);
10673 case ALTIVEC_BUILTIN_STVRXL
:
10674 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl
, exp
);
10676 case VSX_BUILTIN_STXVD2X_V2DF
:
10677 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df
, exp
);
10678 case VSX_BUILTIN_STXVD2X_V2DI
:
10679 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di
, exp
);
10680 case VSX_BUILTIN_STXVW4X_V4SF
:
10681 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf
, exp
);
10682 case VSX_BUILTIN_STXVW4X_V4SI
:
10683 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si
, exp
);
10684 case VSX_BUILTIN_STXVW4X_V8HI
:
10685 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi
, exp
);
10686 case VSX_BUILTIN_STXVW4X_V16QI
:
10687 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi
, exp
);
10689 case ALTIVEC_BUILTIN_MFVSCR
:
10690 icode
= CODE_FOR_altivec_mfvscr
;
10691 tmode
= insn_data
[icode
].operand
[0].mode
;
10694 || GET_MODE (target
) != tmode
10695 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10696 target
= gen_reg_rtx (tmode
);
10698 pat
= GEN_FCN (icode
) (target
);
10704 case ALTIVEC_BUILTIN_MTVSCR
:
10705 icode
= CODE_FOR_altivec_mtvscr
;
10706 arg0
= CALL_EXPR_ARG (exp
, 0);
10707 op0
= expand_normal (arg0
);
10708 mode0
= insn_data
[icode
].operand
[0].mode
;
10710 /* If we got invalid arguments bail out before generating bad rtl. */
10711 if (arg0
== error_mark_node
)
10714 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
10715 op0
= copy_to_mode_reg (mode0
, op0
);
10717 pat
= GEN_FCN (icode
) (op0
);
10722 case ALTIVEC_BUILTIN_DSSALL
:
10723 emit_insn (gen_altivec_dssall ());
10726 case ALTIVEC_BUILTIN_DSS
:
10727 icode
= CODE_FOR_altivec_dss
;
10728 arg0
= CALL_EXPR_ARG (exp
, 0);
10730 op0
= expand_normal (arg0
);
10731 mode0
= insn_data
[icode
].operand
[0].mode
;
10733 /* If we got invalid arguments bail out before generating bad rtl. */
10734 if (arg0
== error_mark_node
)
10737 if (TREE_CODE (arg0
) != INTEGER_CST
10738 || TREE_INT_CST_LOW (arg0
) & ~0x3)
10740 error ("argument to dss must be a 2-bit unsigned literal");
10744 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
10745 op0
= copy_to_mode_reg (mode0
, op0
);
10747 emit_insn (gen_altivec_dss (op0
));
10750 case ALTIVEC_BUILTIN_VEC_INIT_V4SI
:
10751 case ALTIVEC_BUILTIN_VEC_INIT_V8HI
:
10752 case ALTIVEC_BUILTIN_VEC_INIT_V16QI
:
10753 case ALTIVEC_BUILTIN_VEC_INIT_V4SF
:
10754 case VSX_BUILTIN_VEC_INIT_V2DF
:
10755 case VSX_BUILTIN_VEC_INIT_V2DI
:
10756 return altivec_expand_vec_init_builtin (TREE_TYPE (exp
), exp
, target
);
10758 case ALTIVEC_BUILTIN_VEC_SET_V4SI
:
10759 case ALTIVEC_BUILTIN_VEC_SET_V8HI
:
10760 case ALTIVEC_BUILTIN_VEC_SET_V16QI
:
10761 case ALTIVEC_BUILTIN_VEC_SET_V4SF
:
10762 case VSX_BUILTIN_VEC_SET_V2DF
:
10763 case VSX_BUILTIN_VEC_SET_V2DI
:
10764 return altivec_expand_vec_set_builtin (exp
);
10766 case ALTIVEC_BUILTIN_VEC_EXT_V4SI
:
10767 case ALTIVEC_BUILTIN_VEC_EXT_V8HI
:
10768 case ALTIVEC_BUILTIN_VEC_EXT_V16QI
:
10769 case ALTIVEC_BUILTIN_VEC_EXT_V4SF
:
10770 case VSX_BUILTIN_VEC_EXT_V2DF
:
10771 case VSX_BUILTIN_VEC_EXT_V2DI
:
10772 return altivec_expand_vec_ext_builtin (exp
, target
);
10776 /* Fall through. */
10779 /* Expand abs* operations. */
10781 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
10782 if (d
->code
== fcode
)
10783 return altivec_expand_abs_builtin (d
->icode
, exp
, target
);
10785 /* Expand the AltiVec predicates. */
10786 d
= bdesc_altivec_preds
;
10787 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
10788 if (d
->code
== fcode
)
10789 return altivec_expand_predicate_builtin (d
->icode
, exp
, target
);
10791 /* LV* are funky. We initialized them differently. */
10794 case ALTIVEC_BUILTIN_LVSL
:
10795 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl
,
10796 exp
, target
, false);
10797 case ALTIVEC_BUILTIN_LVSR
:
10798 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr
,
10799 exp
, target
, false);
10800 case ALTIVEC_BUILTIN_LVEBX
:
10801 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx
,
10802 exp
, target
, false);
10803 case ALTIVEC_BUILTIN_LVEHX
:
10804 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx
,
10805 exp
, target
, false);
10806 case ALTIVEC_BUILTIN_LVEWX
:
10807 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx
,
10808 exp
, target
, false);
10809 case ALTIVEC_BUILTIN_LVXL
:
10810 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl
,
10811 exp
, target
, false);
10812 case ALTIVEC_BUILTIN_LVX
:
10813 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si
,
10814 exp
, target
, false);
10815 case ALTIVEC_BUILTIN_LVLX
:
10816 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx
,
10817 exp
, target
, true);
10818 case ALTIVEC_BUILTIN_LVLXL
:
10819 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl
,
10820 exp
, target
, true);
10821 case ALTIVEC_BUILTIN_LVRX
:
10822 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx
,
10823 exp
, target
, true);
10824 case ALTIVEC_BUILTIN_LVRXL
:
10825 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl
,
10826 exp
, target
, true);
10827 case VSX_BUILTIN_LXVD2X_V2DF
:
10828 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df
,
10829 exp
, target
, false);
10830 case VSX_BUILTIN_LXVD2X_V2DI
:
10831 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di
,
10832 exp
, target
, false);
10833 case VSX_BUILTIN_LXVW4X_V4SF
:
10834 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf
,
10835 exp
, target
, false);
10836 case VSX_BUILTIN_LXVW4X_V4SI
:
10837 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si
,
10838 exp
, target
, false);
10839 case VSX_BUILTIN_LXVW4X_V8HI
:
10840 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi
,
10841 exp
, target
, false);
10842 case VSX_BUILTIN_LXVW4X_V16QI
:
10843 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi
,
10844 exp
, target
, false);
10848 /* Fall through. */
10851 *expandedp
= false;
10855 /* Expand the builtin in EXP and store the result in TARGET. Store
10856 true in *EXPANDEDP if we found a builtin to expand. */
10858 paired_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
10860 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10861 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
10862 const struct builtin_description
*d
;
10869 case PAIRED_BUILTIN_STX
:
10870 return paired_expand_stv_builtin (CODE_FOR_paired_stx
, exp
);
10871 case PAIRED_BUILTIN_LX
:
10872 return paired_expand_lv_builtin (CODE_FOR_paired_lx
, exp
, target
);
10875 /* Fall through. */
10878 /* Expand the paired predicates. */
10879 d
= bdesc_paired_preds
;
10880 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); i
++, d
++)
10881 if (d
->code
== fcode
)
10882 return paired_expand_predicate_builtin (d
->icode
, exp
, target
);
10884 *expandedp
= false;
10888 /* Binops that need to be initialized manually, but can be expanded
10889 automagically by rs6000_expand_binop_builtin. */
10890 static const struct builtin_description bdesc_2arg_spe
[] =
10892 { RS6000_BTM_SPE
, CODE_FOR_spe_evlddx
, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX
},
10893 { RS6000_BTM_SPE
, CODE_FOR_spe_evldwx
, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX
},
10894 { RS6000_BTM_SPE
, CODE_FOR_spe_evldhx
, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX
},
10895 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhex
, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX
},
10896 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhoux
, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX
},
10897 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhosx
, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX
},
10898 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplatx
, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX
},
10899 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplatx
, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX
},
10900 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplatx
, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX
},
10901 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplatx
, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX
},
10902 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplatx
, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX
},
10903 { RS6000_BTM_SPE
, CODE_FOR_spe_evldd
, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD
},
10904 { RS6000_BTM_SPE
, CODE_FOR_spe_evldw
, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW
},
10905 { RS6000_BTM_SPE
, CODE_FOR_spe_evldh
, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH
},
10906 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhe
, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE
},
10907 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhou
, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU
},
10908 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhos
, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS
},
10909 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplat
, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT
},
10910 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplat
, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT
},
10911 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplat
, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT
},
10912 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplat
, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT
},
10913 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplat
, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT
}
10916 /* Expand the builtin in EXP and store the result in TARGET. Store
10917 true in *EXPANDEDP if we found a builtin to expand.
10919 This expands the SPE builtins that are not simple unary and binary
10922 spe_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
10924 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10926 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
10927 enum insn_code icode
;
10928 enum machine_mode tmode
, mode0
;
10930 const struct builtin_description
*d
;
10935 /* Syntax check for a 5-bit unsigned immediate. */
10938 case SPE_BUILTIN_EVSTDD
:
10939 case SPE_BUILTIN_EVSTDH
:
10940 case SPE_BUILTIN_EVSTDW
:
10941 case SPE_BUILTIN_EVSTWHE
:
10942 case SPE_BUILTIN_EVSTWHO
:
10943 case SPE_BUILTIN_EVSTWWE
:
10944 case SPE_BUILTIN_EVSTWWO
:
10945 arg1
= CALL_EXPR_ARG (exp
, 2);
10946 if (TREE_CODE (arg1
) != INTEGER_CST
10947 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
10949 error ("argument 2 must be a 5-bit unsigned literal");
10957 /* The evsplat*i instructions are not quite generic. */
10960 case SPE_BUILTIN_EVSPLATFI
:
10961 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi
,
10963 case SPE_BUILTIN_EVSPLATI
:
10964 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati
,
10970 d
= bdesc_2arg_spe
;
10971 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg_spe
); ++i
, ++d
)
10972 if (d
->code
== fcode
)
10973 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
10975 d
= bdesc_spe_predicates
;
10976 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, ++d
)
10977 if (d
->code
== fcode
)
10978 return spe_expand_predicate_builtin (d
->icode
, exp
, target
);
10980 d
= bdesc_spe_evsel
;
10981 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, ++d
)
10982 if (d
->code
== fcode
)
10983 return spe_expand_evsel_builtin (d
->icode
, exp
, target
);
10987 case SPE_BUILTIN_EVSTDDX
:
10988 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx
, exp
);
10989 case SPE_BUILTIN_EVSTDHX
:
10990 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx
, exp
);
10991 case SPE_BUILTIN_EVSTDWX
:
10992 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx
, exp
);
10993 case SPE_BUILTIN_EVSTWHEX
:
10994 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex
, exp
);
10995 case SPE_BUILTIN_EVSTWHOX
:
10996 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox
, exp
);
10997 case SPE_BUILTIN_EVSTWWEX
:
10998 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex
, exp
);
10999 case SPE_BUILTIN_EVSTWWOX
:
11000 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox
, exp
);
11001 case SPE_BUILTIN_EVSTDD
:
11002 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd
, exp
);
11003 case SPE_BUILTIN_EVSTDH
:
11004 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh
, exp
);
11005 case SPE_BUILTIN_EVSTDW
:
11006 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw
, exp
);
11007 case SPE_BUILTIN_EVSTWHE
:
11008 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe
, exp
);
11009 case SPE_BUILTIN_EVSTWHO
:
11010 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho
, exp
);
11011 case SPE_BUILTIN_EVSTWWE
:
11012 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe
, exp
);
11013 case SPE_BUILTIN_EVSTWWO
:
11014 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo
, exp
);
11015 case SPE_BUILTIN_MFSPEFSCR
:
11016 icode
= CODE_FOR_spe_mfspefscr
;
11017 tmode
= insn_data
[icode
].operand
[0].mode
;
11020 || GET_MODE (target
) != tmode
11021 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11022 target
= gen_reg_rtx (tmode
);
11024 pat
= GEN_FCN (icode
) (target
);
11029 case SPE_BUILTIN_MTSPEFSCR
:
11030 icode
= CODE_FOR_spe_mtspefscr
;
11031 arg0
= CALL_EXPR_ARG (exp
, 0);
11032 op0
= expand_normal (arg0
);
11033 mode0
= insn_data
[icode
].operand
[0].mode
;
11035 if (arg0
== error_mark_node
)
11038 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
11039 op0
= copy_to_mode_reg (mode0
, op0
);
11041 pat
= GEN_FCN (icode
) (op0
);
11049 *expandedp
= false;
11054 paired_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
11056 rtx pat
, scratch
, tmp
;
11057 tree form
= CALL_EXPR_ARG (exp
, 0);
11058 tree arg0
= CALL_EXPR_ARG (exp
, 1);
11059 tree arg1
= CALL_EXPR_ARG (exp
, 2);
11060 rtx op0
= expand_normal (arg0
);
11061 rtx op1
= expand_normal (arg1
);
11062 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11063 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
11065 enum rtx_code code
;
11067 if (TREE_CODE (form
) != INTEGER_CST
)
11069 error ("argument 1 of __builtin_paired_predicate must be a constant");
11073 form_int
= TREE_INT_CST_LOW (form
);
11075 gcc_assert (mode0
== mode1
);
11077 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11081 || GET_MODE (target
) != SImode
11082 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
11083 target
= gen_reg_rtx (SImode
);
11084 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11085 op0
= copy_to_mode_reg (mode0
, op0
);
11086 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11087 op1
= copy_to_mode_reg (mode1
, op1
);
11089 scratch
= gen_reg_rtx (CCFPmode
);
11091 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
11113 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
11116 error ("argument 1 of __builtin_paired_predicate is out of range");
11120 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
11121 emit_move_insn (target
, tmp
);
11126 spe_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
11128 rtx pat
, scratch
, tmp
;
11129 tree form
= CALL_EXPR_ARG (exp
, 0);
11130 tree arg0
= CALL_EXPR_ARG (exp
, 1);
11131 tree arg1
= CALL_EXPR_ARG (exp
, 2);
11132 rtx op0
= expand_normal (arg0
);
11133 rtx op1
= expand_normal (arg1
);
11134 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11135 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
11137 enum rtx_code code
;
11139 if (TREE_CODE (form
) != INTEGER_CST
)
11141 error ("argument 1 of __builtin_spe_predicate must be a constant");
11145 form_int
= TREE_INT_CST_LOW (form
);
11147 gcc_assert (mode0
== mode1
);
11149 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11153 || GET_MODE (target
) != SImode
11154 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
11155 target
= gen_reg_rtx (SImode
);
11157 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11158 op0
= copy_to_mode_reg (mode0
, op0
);
11159 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11160 op1
= copy_to_mode_reg (mode1
, op1
);
11162 scratch
= gen_reg_rtx (CCmode
);
11164 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
11169 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
11170 _lower_. We use one compare, but look in different bits of the
11171 CR for each variant.
11173 There are 2 elements in each SPE simd type (upper/lower). The CR
11174 bits are set as follows:
11176 BIT0 | BIT 1 | BIT 2 | BIT 3
11177 U | L | (U | L) | (U & L)
11179 So, for an "all" relationship, BIT 3 would be set.
11180 For an "any" relationship, BIT 2 would be set. Etc.
11182 Following traditional nomenclature, these bits map to:
11184 BIT0 | BIT 1 | BIT 2 | BIT 3
11187 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
11192 /* All variant. OV bit. */
11194 /* We need to get to the OV bit, which is the ORDERED bit. We
11195 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
11196 that's ugly and will make validate_condition_mode die.
11197 So let's just use another pattern. */
11198 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
11200 /* Any variant. EQ bit. */
11204 /* Upper variant. LT bit. */
11208 /* Lower variant. GT bit. */
11213 error ("argument 1 of __builtin_spe_predicate is out of range");
11217 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
11218 emit_move_insn (target
, tmp
);
11223 /* The evsel builtins look like this:
11225 e = __builtin_spe_evsel_OP (a, b, c, d);
11227 and work like this:
11229 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
11230 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
11234 spe_expand_evsel_builtin (enum insn_code icode
, tree exp
, rtx target
)
11237 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11238 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11239 tree arg2
= CALL_EXPR_ARG (exp
, 2);
11240 tree arg3
= CALL_EXPR_ARG (exp
, 3);
11241 rtx op0
= expand_normal (arg0
);
11242 rtx op1
= expand_normal (arg1
);
11243 rtx op2
= expand_normal (arg2
);
11244 rtx op3
= expand_normal (arg3
);
11245 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11246 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
11248 gcc_assert (mode0
== mode1
);
11250 if (arg0
== error_mark_node
|| arg1
== error_mark_node
11251 || arg2
== error_mark_node
|| arg3
== error_mark_node
)
11255 || GET_MODE (target
) != mode0
11256 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode0
))
11257 target
= gen_reg_rtx (mode0
);
11259 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11260 op0
= copy_to_mode_reg (mode0
, op0
);
11261 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
11262 op1
= copy_to_mode_reg (mode0
, op1
);
11263 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
11264 op2
= copy_to_mode_reg (mode0
, op2
);
11265 if (! (*insn_data
[icode
].operand
[1].predicate
) (op3
, mode1
))
11266 op3
= copy_to_mode_reg (mode0
, op3
);
11268 /* Generate the compare. */
11269 scratch
= gen_reg_rtx (CCmode
);
11270 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
11275 if (mode0
== V2SImode
)
11276 emit_insn (gen_spe_evsel (target
, op2
, op3
, scratch
));
11278 emit_insn (gen_spe_evsel_fs (target
, op2
, op3
, scratch
));
11283 /* Raise an error message for a builtin function that is called without the
11284 appropriate target options being set. */
11287 rs6000_invalid_builtin (enum rs6000_builtins fncode
)
11289 size_t uns_fncode
= (size_t)fncode
;
11290 const char *name
= rs6000_builtin_info
[uns_fncode
].name
;
11291 unsigned fnmask
= rs6000_builtin_info
[uns_fncode
].mask
;
11293 gcc_assert (name
!= NULL
);
11294 if ((fnmask
& RS6000_BTM_CELL
) != 0)
11295 error ("Builtin function %s is only valid for the cell processor", name
);
11296 else if ((fnmask
& RS6000_BTM_VSX
) != 0)
11297 error ("Builtin function %s requires the -mvsx option", name
);
11298 else if ((fnmask
& RS6000_BTM_ALTIVEC
) != 0)
11299 error ("Builtin function %s requires the -maltivec option", name
);
11300 else if ((fnmask
& RS6000_BTM_PAIRED
) != 0)
11301 error ("Builtin function %s requires the -mpaired option", name
);
11302 else if ((fnmask
& RS6000_BTM_SPE
) != 0)
11303 error ("Builtin function %s requires the -mspe option", name
);
11305 error ("Builtin function %s is not supported with the current options",
11309 /* Expand an expression EXP that calls a built-in function,
11310 with result going to TARGET if that's convenient
11311 (and in mode MODE if that's convenient).
11312 SUBTARGET may be used as the target for computing one of EXP's operands.
11313 IGNORE is nonzero if the value is to be ignored. */
11316 rs6000_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
11317 enum machine_mode mode ATTRIBUTE_UNUSED
,
11318 int ignore ATTRIBUTE_UNUSED
)
11320 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11321 enum rs6000_builtins fcode
11322 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
11323 size_t uns_fcode
= (size_t)fcode
;
11324 const struct builtin_description
*d
;
11328 unsigned mask
= rs6000_builtin_info
[uns_fcode
].mask
;
11329 bool func_valid_p
= ((rs6000_builtin_mask
& mask
) == mask
);
11331 if (TARGET_DEBUG_BUILTIN
)
11333 enum insn_code icode
= rs6000_builtin_info
[uns_fcode
].icode
;
11334 const char *name1
= rs6000_builtin_info
[uns_fcode
].name
;
11335 const char *name2
= ((icode
!= CODE_FOR_nothing
)
11336 ? get_insn_name ((int)icode
)
11340 switch (rs6000_builtin_info
[uns_fcode
].attr
& RS6000_BTC_TYPE_MASK
)
11342 default: name3
= "unknown"; break;
11343 case RS6000_BTC_SPECIAL
: name3
= "special"; break;
11344 case RS6000_BTC_UNARY
: name3
= "unary"; break;
11345 case RS6000_BTC_BINARY
: name3
= "binary"; break;
11346 case RS6000_BTC_TERNARY
: name3
= "ternary"; break;
11347 case RS6000_BTC_PREDICATE
: name3
= "predicate"; break;
11348 case RS6000_BTC_ABS
: name3
= "abs"; break;
11349 case RS6000_BTC_EVSEL
: name3
= "evsel"; break;
11350 case RS6000_BTC_DST
: name3
= "dst"; break;
11355 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
11356 (name1
) ? name1
: "---", fcode
,
11357 (name2
) ? name2
: "---", (int)icode
,
11359 func_valid_p
? "" : ", not valid");
11364 rs6000_invalid_builtin (fcode
);
11366 /* Given it is invalid, just generate a normal call. */
11367 return expand_call (exp
, target
, ignore
);
11372 case RS6000_BUILTIN_RECIP
:
11373 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3
, exp
, target
);
11375 case RS6000_BUILTIN_RECIPF
:
11376 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3
, exp
, target
);
11378 case RS6000_BUILTIN_RSQRTF
:
11379 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2
, exp
, target
);
11381 case RS6000_BUILTIN_RSQRT
:
11382 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2
, exp
, target
);
11384 case POWER7_BUILTIN_BPERMD
:
11385 return rs6000_expand_binop_builtin (((TARGET_64BIT
)
11386 ? CODE_FOR_bpermd_di
11387 : CODE_FOR_bpermd_si
), exp
, target
);
11389 case ALTIVEC_BUILTIN_MASK_FOR_LOAD
:
11390 case ALTIVEC_BUILTIN_MASK_FOR_STORE
:
11392 int icode
= (int) CODE_FOR_altivec_lvsr
;
11393 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11394 enum machine_mode mode
= insn_data
[icode
].operand
[1].mode
;
11398 gcc_assert (TARGET_ALTIVEC
);
11400 arg
= CALL_EXPR_ARG (exp
, 0);
11401 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg
)));
11402 op
= expand_expr (arg
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
11403 addr
= memory_address (mode
, op
);
11404 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
11408 /* For the load case need to negate the address. */
11409 op
= gen_reg_rtx (GET_MODE (addr
));
11410 emit_insn (gen_rtx_SET (VOIDmode
, op
,
11411 gen_rtx_NEG (GET_MODE (addr
), addr
)));
11413 op
= gen_rtx_MEM (mode
, op
);
11416 || GET_MODE (target
) != tmode
11417 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11418 target
= gen_reg_rtx (tmode
);
11420 /*pat = gen_altivec_lvsr (target, op);*/
11421 pat
= GEN_FCN (icode
) (target
, op
);
11429 case ALTIVEC_BUILTIN_VCFUX
:
11430 case ALTIVEC_BUILTIN_VCFSX
:
11431 case ALTIVEC_BUILTIN_VCTUXS
:
11432 case ALTIVEC_BUILTIN_VCTSXS
:
11433 /* FIXME: There's got to be a nicer way to handle this case than
11434 constructing a new CALL_EXPR. */
11435 if (call_expr_nargs (exp
) == 1)
11437 exp
= build_call_nary (TREE_TYPE (exp
), CALL_EXPR_FN (exp
),
11438 2, CALL_EXPR_ARG (exp
, 0), integer_zero_node
);
11446 if (TARGET_ALTIVEC
)
11448 ret
= altivec_expand_builtin (exp
, target
, &success
);
11455 ret
= spe_expand_builtin (exp
, target
, &success
);
11460 if (TARGET_PAIRED_FLOAT
)
11462 ret
= paired_expand_builtin (exp
, target
, &success
);
11468 gcc_assert (TARGET_ALTIVEC
|| TARGET_VSX
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
);
11470 /* Handle simple unary operations. */
11472 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
11473 if (d
->code
== fcode
)
11474 return rs6000_expand_unop_builtin (d
->icode
, exp
, target
);
11476 /* Handle simple binary operations. */
11478 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
11479 if (d
->code
== fcode
)
11480 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
11482 /* Handle simple ternary operations. */
11484 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
11485 if (d
->code
== fcode
)
11486 return rs6000_expand_ternop_builtin (d
->icode
, exp
, target
);
11488 gcc_unreachable ();
11492 rs6000_init_builtins (void)
11496 enum machine_mode mode
;
11498 if (TARGET_DEBUG_BUILTIN
)
11499 fprintf (stderr
, "rs6000_init_builtins%s%s%s%s\n",
11500 (TARGET_PAIRED_FLOAT
) ? ", paired" : "",
11501 (TARGET_SPE
) ? ", spe" : "",
11502 (TARGET_ALTIVEC
) ? ", altivec" : "",
11503 (TARGET_VSX
) ? ", vsx" : "");
11505 V2SI_type_node
= build_vector_type (intSI_type_node
, 2);
11506 V2SF_type_node
= build_vector_type (float_type_node
, 2);
11507 V2DI_type_node
= build_vector_type (intDI_type_node
, 2);
11508 V2DF_type_node
= build_vector_type (double_type_node
, 2);
11509 V4HI_type_node
= build_vector_type (intHI_type_node
, 4);
11510 V4SI_type_node
= build_vector_type (intSI_type_node
, 4);
11511 V4SF_type_node
= build_vector_type (float_type_node
, 4);
11512 V8HI_type_node
= build_vector_type (intHI_type_node
, 8);
11513 V16QI_type_node
= build_vector_type (intQI_type_node
, 16);
11515 unsigned_V16QI_type_node
= build_vector_type (unsigned_intQI_type_node
, 16);
11516 unsigned_V8HI_type_node
= build_vector_type (unsigned_intHI_type_node
, 8);
11517 unsigned_V4SI_type_node
= build_vector_type (unsigned_intSI_type_node
, 4);
11518 unsigned_V2DI_type_node
= build_vector_type (unsigned_intDI_type_node
, 2);
11520 opaque_V2SF_type_node
= build_opaque_vector_type (float_type_node
, 2);
11521 opaque_V2SI_type_node
= build_opaque_vector_type (intSI_type_node
, 2);
11522 opaque_p_V2SI_type_node
= build_pointer_type (opaque_V2SI_type_node
);
11523 opaque_V4SI_type_node
= build_opaque_vector_type (intSI_type_node
, 4);
11525 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
11526 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
11527 'vector unsigned short'. */
11529 bool_char_type_node
= build_distinct_type_copy (unsigned_intQI_type_node
);
11530 bool_short_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
11531 bool_int_type_node
= build_distinct_type_copy (unsigned_intSI_type_node
);
11532 bool_long_type_node
= build_distinct_type_copy (unsigned_intDI_type_node
);
11533 pixel_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
11535 long_integer_type_internal_node
= long_integer_type_node
;
11536 long_unsigned_type_internal_node
= long_unsigned_type_node
;
11537 long_long_integer_type_internal_node
= long_long_integer_type_node
;
11538 long_long_unsigned_type_internal_node
= long_long_unsigned_type_node
;
11539 intQI_type_internal_node
= intQI_type_node
;
11540 uintQI_type_internal_node
= unsigned_intQI_type_node
;
11541 intHI_type_internal_node
= intHI_type_node
;
11542 uintHI_type_internal_node
= unsigned_intHI_type_node
;
11543 intSI_type_internal_node
= intSI_type_node
;
11544 uintSI_type_internal_node
= unsigned_intSI_type_node
;
11545 intDI_type_internal_node
= intDI_type_node
;
11546 uintDI_type_internal_node
= unsigned_intDI_type_node
;
11547 float_type_internal_node
= float_type_node
;
11548 double_type_internal_node
= double_type_node
;
11549 void_type_internal_node
= void_type_node
;
11551 /* Initialize the modes for builtin_function_type, mapping a machine mode to
11553 builtin_mode_to_type
[QImode
][0] = integer_type_node
;
11554 builtin_mode_to_type
[HImode
][0] = integer_type_node
;
11555 builtin_mode_to_type
[SImode
][0] = intSI_type_node
;
11556 builtin_mode_to_type
[SImode
][1] = unsigned_intSI_type_node
;
11557 builtin_mode_to_type
[DImode
][0] = intDI_type_node
;
11558 builtin_mode_to_type
[DImode
][1] = unsigned_intDI_type_node
;
11559 builtin_mode_to_type
[SFmode
][0] = float_type_node
;
11560 builtin_mode_to_type
[DFmode
][0] = double_type_node
;
11561 builtin_mode_to_type
[V2SImode
][0] = V2SI_type_node
;
11562 builtin_mode_to_type
[V2SFmode
][0] = V2SF_type_node
;
11563 builtin_mode_to_type
[V2DImode
][0] = V2DI_type_node
;
11564 builtin_mode_to_type
[V2DImode
][1] = unsigned_V2DI_type_node
;
11565 builtin_mode_to_type
[V2DFmode
][0] = V2DF_type_node
;
11566 builtin_mode_to_type
[V4HImode
][0] = V4HI_type_node
;
11567 builtin_mode_to_type
[V4SImode
][0] = V4SI_type_node
;
11568 builtin_mode_to_type
[V4SImode
][1] = unsigned_V4SI_type_node
;
11569 builtin_mode_to_type
[V4SFmode
][0] = V4SF_type_node
;
11570 builtin_mode_to_type
[V8HImode
][0] = V8HI_type_node
;
11571 builtin_mode_to_type
[V8HImode
][1] = unsigned_V8HI_type_node
;
11572 builtin_mode_to_type
[V16QImode
][0] = V16QI_type_node
;
11573 builtin_mode_to_type
[V16QImode
][1] = unsigned_V16QI_type_node
;
11575 tdecl
= add_builtin_type ("__bool char", bool_char_type_node
);
11576 TYPE_NAME (bool_char_type_node
) = tdecl
;
11578 tdecl
= add_builtin_type ("__bool short", bool_short_type_node
);
11579 TYPE_NAME (bool_short_type_node
) = tdecl
;
11581 tdecl
= add_builtin_type ("__bool int", bool_int_type_node
);
11582 TYPE_NAME (bool_int_type_node
) = tdecl
;
11584 tdecl
= add_builtin_type ("__pixel", pixel_type_node
);
11585 TYPE_NAME (pixel_type_node
) = tdecl
;
11587 bool_V16QI_type_node
= build_vector_type (bool_char_type_node
, 16);
11588 bool_V8HI_type_node
= build_vector_type (bool_short_type_node
, 8);
11589 bool_V4SI_type_node
= build_vector_type (bool_int_type_node
, 4);
11590 bool_V2DI_type_node
= build_vector_type (bool_long_type_node
, 2);
11591 pixel_V8HI_type_node
= build_vector_type (pixel_type_node
, 8);
11593 tdecl
= add_builtin_type ("__vector unsigned char", unsigned_V16QI_type_node
);
11594 TYPE_NAME (unsigned_V16QI_type_node
) = tdecl
;
11596 tdecl
= add_builtin_type ("__vector signed char", V16QI_type_node
);
11597 TYPE_NAME (V16QI_type_node
) = tdecl
;
11599 tdecl
= add_builtin_type ("__vector __bool char", bool_V16QI_type_node
);
11600 TYPE_NAME ( bool_V16QI_type_node
) = tdecl
;
11602 tdecl
= add_builtin_type ("__vector unsigned short", unsigned_V8HI_type_node
);
11603 TYPE_NAME (unsigned_V8HI_type_node
) = tdecl
;
11605 tdecl
= add_builtin_type ("__vector signed short", V8HI_type_node
);
11606 TYPE_NAME (V8HI_type_node
) = tdecl
;
11608 tdecl
= add_builtin_type ("__vector __bool short", bool_V8HI_type_node
);
11609 TYPE_NAME (bool_V8HI_type_node
) = tdecl
;
11611 tdecl
= add_builtin_type ("__vector unsigned int", unsigned_V4SI_type_node
);
11612 TYPE_NAME (unsigned_V4SI_type_node
) = tdecl
;
11614 tdecl
= add_builtin_type ("__vector signed int", V4SI_type_node
);
11615 TYPE_NAME (V4SI_type_node
) = tdecl
;
11617 tdecl
= add_builtin_type ("__vector __bool int", bool_V4SI_type_node
);
11618 TYPE_NAME (bool_V4SI_type_node
) = tdecl
;
11620 tdecl
= add_builtin_type ("__vector float", V4SF_type_node
);
11621 TYPE_NAME (V4SF_type_node
) = tdecl
;
11623 tdecl
= add_builtin_type ("__vector __pixel", pixel_V8HI_type_node
);
11624 TYPE_NAME (pixel_V8HI_type_node
) = tdecl
;
11626 tdecl
= add_builtin_type ("__vector double", V2DF_type_node
);
11627 TYPE_NAME (V2DF_type_node
) = tdecl
;
11629 tdecl
= add_builtin_type ("__vector long", V2DI_type_node
);
11630 TYPE_NAME (V2DI_type_node
) = tdecl
;
11632 tdecl
= add_builtin_type ("__vector unsigned long", unsigned_V2DI_type_node
);
11633 TYPE_NAME (unsigned_V2DI_type_node
) = tdecl
;
11635 tdecl
= add_builtin_type ("__vector __bool long", bool_V2DI_type_node
);
11636 TYPE_NAME (bool_V2DI_type_node
) = tdecl
;
11638 /* Paired and SPE builtins are only available if you build a compiler with
11639 the appropriate options, so only create those builtins with the
11640 appropriate compiler option. Create Altivec and VSX builtins on machines
11641 with at least the general purpose extensions (970 and newer) to allow the
11642 use of the target attribute. */
11643 if (TARGET_PAIRED_FLOAT
)
11644 paired_init_builtins ();
11646 spe_init_builtins ();
11647 if (TARGET_EXTRA_BUILTINS
)
11648 altivec_init_builtins ();
11649 if (TARGET_EXTRA_BUILTINS
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
)
11650 rs6000_common_init_builtins ();
11652 ftype
= builtin_function_type (DFmode
, DFmode
, DFmode
, VOIDmode
,
11653 RS6000_BUILTIN_RECIP
, "__builtin_recipdiv");
11654 def_builtin ("__builtin_recipdiv", ftype
, RS6000_BUILTIN_RECIP
);
11656 ftype
= builtin_function_type (SFmode
, SFmode
, SFmode
, VOIDmode
,
11657 RS6000_BUILTIN_RECIPF
, "__builtin_recipdivf");
11658 def_builtin ("__builtin_recipdivf", ftype
, RS6000_BUILTIN_RECIPF
);
11660 ftype
= builtin_function_type (DFmode
, DFmode
, VOIDmode
, VOIDmode
,
11661 RS6000_BUILTIN_RSQRT
, "__builtin_rsqrt");
11662 def_builtin ("__builtin_rsqrt", ftype
, RS6000_BUILTIN_RSQRT
);
11664 ftype
= builtin_function_type (SFmode
, SFmode
, VOIDmode
, VOIDmode
,
11665 RS6000_BUILTIN_RSQRTF
, "__builtin_rsqrtf");
11666 def_builtin ("__builtin_rsqrtf", ftype
, RS6000_BUILTIN_RSQRTF
);
11668 mode
= (TARGET_64BIT
) ? DImode
: SImode
;
11669 ftype
= builtin_function_type (mode
, mode
, mode
, VOIDmode
,
11670 POWER7_BUILTIN_BPERMD
, "__builtin_bpermd");
11671 def_builtin ("__builtin_bpermd", ftype
, POWER7_BUILTIN_BPERMD
);
11674 /* AIX libm provides clog as __clog. */
11675 if ((tdecl
= builtin_decl_explicit (BUILT_IN_CLOG
)) != NULL_TREE
)
11676 set_user_assembler_name (tdecl
, "__clog");
11679 #ifdef SUBTARGET_INIT_BUILTINS
11680 SUBTARGET_INIT_BUILTINS
;
11684 /* Returns the rs6000 builtin decl for CODE. */
11687 rs6000_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
11691 if (code
>= RS6000_BUILTIN_COUNT
)
11692 return error_mark_node
;
11694 fnmask
= rs6000_builtin_info
[code
].mask
;
11695 if ((fnmask
& rs6000_builtin_mask
) != fnmask
)
11697 rs6000_invalid_builtin ((enum rs6000_builtins
)code
);
11698 return error_mark_node
;
11701 return rs6000_builtin_decls
[code
];
11705 spe_init_builtins (void)
11707 tree puint_type_node
= build_pointer_type (unsigned_type_node
);
11708 tree pushort_type_node
= build_pointer_type (short_unsigned_type_node
);
11709 const struct builtin_description
*d
;
11712 tree v2si_ftype_4_v2si
11713 = build_function_type_list (opaque_V2SI_type_node
,
11714 opaque_V2SI_type_node
,
11715 opaque_V2SI_type_node
,
11716 opaque_V2SI_type_node
,
11717 opaque_V2SI_type_node
,
11720 tree v2sf_ftype_4_v2sf
11721 = build_function_type_list (opaque_V2SF_type_node
,
11722 opaque_V2SF_type_node
,
11723 opaque_V2SF_type_node
,
11724 opaque_V2SF_type_node
,
11725 opaque_V2SF_type_node
,
11728 tree int_ftype_int_v2si_v2si
11729 = build_function_type_list (integer_type_node
,
11731 opaque_V2SI_type_node
,
11732 opaque_V2SI_type_node
,
11735 tree int_ftype_int_v2sf_v2sf
11736 = build_function_type_list (integer_type_node
,
11738 opaque_V2SF_type_node
,
11739 opaque_V2SF_type_node
,
11742 tree void_ftype_v2si_puint_int
11743 = build_function_type_list (void_type_node
,
11744 opaque_V2SI_type_node
,
11749 tree void_ftype_v2si_puint_char
11750 = build_function_type_list (void_type_node
,
11751 opaque_V2SI_type_node
,
11756 tree void_ftype_v2si_pv2si_int
11757 = build_function_type_list (void_type_node
,
11758 opaque_V2SI_type_node
,
11759 opaque_p_V2SI_type_node
,
11763 tree void_ftype_v2si_pv2si_char
11764 = build_function_type_list (void_type_node
,
11765 opaque_V2SI_type_node
,
11766 opaque_p_V2SI_type_node
,
11770 tree void_ftype_int
11771 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
11773 tree int_ftype_void
11774 = build_function_type_list (integer_type_node
, NULL_TREE
);
11776 tree v2si_ftype_pv2si_int
11777 = build_function_type_list (opaque_V2SI_type_node
,
11778 opaque_p_V2SI_type_node
,
11782 tree v2si_ftype_puint_int
11783 = build_function_type_list (opaque_V2SI_type_node
,
11788 tree v2si_ftype_pushort_int
11789 = build_function_type_list (opaque_V2SI_type_node
,
11794 tree v2si_ftype_signed_char
11795 = build_function_type_list (opaque_V2SI_type_node
,
11796 signed_char_type_node
,
11799 add_builtin_type ("__ev64_opaque__", opaque_V2SI_type_node
);
11801 /* Initialize irregular SPE builtins. */
11803 def_builtin ("__builtin_spe_mtspefscr", void_ftype_int
, SPE_BUILTIN_MTSPEFSCR
);
11804 def_builtin ("__builtin_spe_mfspefscr", int_ftype_void
, SPE_BUILTIN_MFSPEFSCR
);
11805 def_builtin ("__builtin_spe_evstddx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDDX
);
11806 def_builtin ("__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDHX
);
11807 def_builtin ("__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDWX
);
11808 def_builtin ("__builtin_spe_evstwhex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHEX
);
11809 def_builtin ("__builtin_spe_evstwhox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHOX
);
11810 def_builtin ("__builtin_spe_evstwwex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWEX
);
11811 def_builtin ("__builtin_spe_evstwwox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWOX
);
11812 def_builtin ("__builtin_spe_evstdd", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDD
);
11813 def_builtin ("__builtin_spe_evstdh", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDH
);
11814 def_builtin ("__builtin_spe_evstdw", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDW
);
11815 def_builtin ("__builtin_spe_evstwhe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHE
);
11816 def_builtin ("__builtin_spe_evstwho", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHO
);
11817 def_builtin ("__builtin_spe_evstwwe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWE
);
11818 def_builtin ("__builtin_spe_evstwwo", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWO
);
11819 def_builtin ("__builtin_spe_evsplatfi", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATFI
);
11820 def_builtin ("__builtin_spe_evsplati", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATI
);
11823 def_builtin ("__builtin_spe_evlddx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDDX
);
11824 def_builtin ("__builtin_spe_evldwx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDWX
);
11825 def_builtin ("__builtin_spe_evldhx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDHX
);
11826 def_builtin ("__builtin_spe_evlwhex", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHEX
);
11827 def_builtin ("__builtin_spe_evlwhoux", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOUX
);
11828 def_builtin ("__builtin_spe_evlwhosx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOSX
);
11829 def_builtin ("__builtin_spe_evlwwsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLATX
);
11830 def_builtin ("__builtin_spe_evlwhsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLATX
);
11831 def_builtin ("__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLATX
);
11832 def_builtin ("__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLATX
);
11833 def_builtin ("__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLATX
);
11834 def_builtin ("__builtin_spe_evldd", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDD
);
11835 def_builtin ("__builtin_spe_evldw", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDW
);
11836 def_builtin ("__builtin_spe_evldh", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDH
);
11837 def_builtin ("__builtin_spe_evlhhesplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLAT
);
11838 def_builtin ("__builtin_spe_evlhhossplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLAT
);
11839 def_builtin ("__builtin_spe_evlhhousplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLAT
);
11840 def_builtin ("__builtin_spe_evlwhe", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHE
);
11841 def_builtin ("__builtin_spe_evlwhos", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOS
);
11842 def_builtin ("__builtin_spe_evlwhou", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOU
);
11843 def_builtin ("__builtin_spe_evlwhsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLAT
);
11844 def_builtin ("__builtin_spe_evlwwsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLAT
);
11847 d
= bdesc_spe_predicates
;
11848 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, d
++)
11852 switch (insn_data
[d
->icode
].operand
[1].mode
)
11855 type
= int_ftype_int_v2si_v2si
;
11858 type
= int_ftype_int_v2sf_v2sf
;
11861 gcc_unreachable ();
11864 def_builtin (d
->name
, type
, d
->code
);
11867 /* Evsel predicates. */
11868 d
= bdesc_spe_evsel
;
11869 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, d
++)
11873 switch (insn_data
[d
->icode
].operand
[1].mode
)
11876 type
= v2si_ftype_4_v2si
;
11879 type
= v2sf_ftype_4_v2sf
;
11882 gcc_unreachable ();
11885 def_builtin (d
->name
, type
, d
->code
);
11890 paired_init_builtins (void)
11892 const struct builtin_description
*d
;
11895 tree int_ftype_int_v2sf_v2sf
11896 = build_function_type_list (integer_type_node
,
11901 tree pcfloat_type_node
=
11902 build_pointer_type (build_qualified_type
11903 (float_type_node
, TYPE_QUAL_CONST
));
11905 tree v2sf_ftype_long_pcfloat
= build_function_type_list (V2SF_type_node
,
11906 long_integer_type_node
,
11909 tree void_ftype_v2sf_long_pcfloat
=
11910 build_function_type_list (void_type_node
,
11912 long_integer_type_node
,
11917 def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat
,
11918 PAIRED_BUILTIN_LX
);
11921 def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat
,
11922 PAIRED_BUILTIN_STX
);
11925 d
= bdesc_paired_preds
;
11926 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); ++i
, d
++)
11930 if (TARGET_DEBUG_BUILTIN
)
11931 fprintf (stderr
, "paired pred #%d, insn = %s [%d], mode = %s\n",
11932 (int)i
, get_insn_name (d
->icode
), (int)d
->icode
,
11933 GET_MODE_NAME (insn_data
[d
->icode
].operand
[1].mode
));
11935 switch (insn_data
[d
->icode
].operand
[1].mode
)
11938 type
= int_ftype_int_v2sf_v2sf
;
11941 gcc_unreachable ();
11944 def_builtin (d
->name
, type
, d
->code
);
11949 altivec_init_builtins (void)
11951 const struct builtin_description
*d
;
11956 tree pvoid_type_node
= build_pointer_type (void_type_node
);
11958 tree pcvoid_type_node
11959 = build_pointer_type (build_qualified_type (void_type_node
,
11962 tree int_ftype_opaque
11963 = build_function_type_list (integer_type_node
,
11964 opaque_V4SI_type_node
, NULL_TREE
);
11965 tree opaque_ftype_opaque
11966 = build_function_type_list (integer_type_node
, NULL_TREE
);
11967 tree opaque_ftype_opaque_int
11968 = build_function_type_list (opaque_V4SI_type_node
,
11969 opaque_V4SI_type_node
, integer_type_node
, NULL_TREE
);
11970 tree opaque_ftype_opaque_opaque_int
11971 = build_function_type_list (opaque_V4SI_type_node
,
11972 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
11973 integer_type_node
, NULL_TREE
);
11974 tree int_ftype_int_opaque_opaque
11975 = build_function_type_list (integer_type_node
,
11976 integer_type_node
, opaque_V4SI_type_node
,
11977 opaque_V4SI_type_node
, NULL_TREE
);
11978 tree int_ftype_int_v4si_v4si
11979 = build_function_type_list (integer_type_node
,
11980 integer_type_node
, V4SI_type_node
,
11981 V4SI_type_node
, NULL_TREE
);
11982 tree void_ftype_v4si
11983 = build_function_type_list (void_type_node
, V4SI_type_node
, NULL_TREE
);
11984 tree v8hi_ftype_void
11985 = build_function_type_list (V8HI_type_node
, NULL_TREE
);
11986 tree void_ftype_void
11987 = build_function_type_list (void_type_node
, NULL_TREE
);
11988 tree void_ftype_int
11989 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
11991 tree opaque_ftype_long_pcvoid
11992 = build_function_type_list (opaque_V4SI_type_node
,
11993 long_integer_type_node
, pcvoid_type_node
,
11995 tree v16qi_ftype_long_pcvoid
11996 = build_function_type_list (V16QI_type_node
,
11997 long_integer_type_node
, pcvoid_type_node
,
11999 tree v8hi_ftype_long_pcvoid
12000 = build_function_type_list (V8HI_type_node
,
12001 long_integer_type_node
, pcvoid_type_node
,
12003 tree v4si_ftype_long_pcvoid
12004 = build_function_type_list (V4SI_type_node
,
12005 long_integer_type_node
, pcvoid_type_node
,
12007 tree v4sf_ftype_long_pcvoid
12008 = build_function_type_list (V4SF_type_node
,
12009 long_integer_type_node
, pcvoid_type_node
,
12011 tree v2df_ftype_long_pcvoid
12012 = build_function_type_list (V2DF_type_node
,
12013 long_integer_type_node
, pcvoid_type_node
,
12015 tree v2di_ftype_long_pcvoid
12016 = build_function_type_list (V2DI_type_node
,
12017 long_integer_type_node
, pcvoid_type_node
,
12020 tree void_ftype_opaque_long_pvoid
12021 = build_function_type_list (void_type_node
,
12022 opaque_V4SI_type_node
, long_integer_type_node
,
12023 pvoid_type_node
, NULL_TREE
);
12024 tree void_ftype_v4si_long_pvoid
12025 = build_function_type_list (void_type_node
,
12026 V4SI_type_node
, long_integer_type_node
,
12027 pvoid_type_node
, NULL_TREE
);
12028 tree void_ftype_v16qi_long_pvoid
12029 = build_function_type_list (void_type_node
,
12030 V16QI_type_node
, long_integer_type_node
,
12031 pvoid_type_node
, NULL_TREE
);
12032 tree void_ftype_v8hi_long_pvoid
12033 = build_function_type_list (void_type_node
,
12034 V8HI_type_node
, long_integer_type_node
,
12035 pvoid_type_node
, NULL_TREE
);
12036 tree void_ftype_v4sf_long_pvoid
12037 = build_function_type_list (void_type_node
,
12038 V4SF_type_node
, long_integer_type_node
,
12039 pvoid_type_node
, NULL_TREE
);
12040 tree void_ftype_v2df_long_pvoid
12041 = build_function_type_list (void_type_node
,
12042 V2DF_type_node
, long_integer_type_node
,
12043 pvoid_type_node
, NULL_TREE
);
12044 tree void_ftype_v2di_long_pvoid
12045 = build_function_type_list (void_type_node
,
12046 V2DI_type_node
, long_integer_type_node
,
12047 pvoid_type_node
, NULL_TREE
);
12048 tree int_ftype_int_v8hi_v8hi
12049 = build_function_type_list (integer_type_node
,
12050 integer_type_node
, V8HI_type_node
,
12051 V8HI_type_node
, NULL_TREE
);
12052 tree int_ftype_int_v16qi_v16qi
12053 = build_function_type_list (integer_type_node
,
12054 integer_type_node
, V16QI_type_node
,
12055 V16QI_type_node
, NULL_TREE
);
12056 tree int_ftype_int_v4sf_v4sf
12057 = build_function_type_list (integer_type_node
,
12058 integer_type_node
, V4SF_type_node
,
12059 V4SF_type_node
, NULL_TREE
);
12060 tree int_ftype_int_v2df_v2df
12061 = build_function_type_list (integer_type_node
,
12062 integer_type_node
, V2DF_type_node
,
12063 V2DF_type_node
, NULL_TREE
);
12064 tree v4si_ftype_v4si
12065 = build_function_type_list (V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
12066 tree v8hi_ftype_v8hi
12067 = build_function_type_list (V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
12068 tree v16qi_ftype_v16qi
12069 = build_function_type_list (V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
12070 tree v4sf_ftype_v4sf
12071 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
12072 tree v2df_ftype_v2df
12073 = build_function_type_list (V2DF_type_node
, V2DF_type_node
, NULL_TREE
);
12074 tree void_ftype_pcvoid_int_int
12075 = build_function_type_list (void_type_node
,
12076 pcvoid_type_node
, integer_type_node
,
12077 integer_type_node
, NULL_TREE
);
12079 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si
, ALTIVEC_BUILTIN_MTVSCR
);
12080 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void
, ALTIVEC_BUILTIN_MFVSCR
);
12081 def_builtin ("__builtin_altivec_dssall", void_ftype_void
, ALTIVEC_BUILTIN_DSSALL
);
12082 def_builtin ("__builtin_altivec_dss", void_ftype_int
, ALTIVEC_BUILTIN_DSS
);
12083 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSL
);
12084 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSR
);
12085 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEBX
);
12086 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEHX
);
12087 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEWX
);
12088 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVXL
);
12089 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVX
);
12090 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVX
);
12091 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVEWX
);
12092 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVXL
);
12093 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVEBX
);
12094 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid
, ALTIVEC_BUILTIN_STVEHX
);
12095 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LD
);
12096 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDE
);
12097 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDL
);
12098 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSL
);
12099 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSR
);
12100 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEBX
);
12101 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEHX
);
12102 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEWX
);
12103 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_ST
);
12104 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STE
);
12105 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STL
);
12106 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEWX
);
12107 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEBX
);
12108 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEHX
);
12110 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid
,
12111 VSX_BUILTIN_LXVD2X_V2DF
);
12112 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid
,
12113 VSX_BUILTIN_LXVD2X_V2DI
);
12114 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid
,
12115 VSX_BUILTIN_LXVW4X_V4SF
);
12116 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid
,
12117 VSX_BUILTIN_LXVW4X_V4SI
);
12118 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid
,
12119 VSX_BUILTIN_LXVW4X_V8HI
);
12120 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid
,
12121 VSX_BUILTIN_LXVW4X_V16QI
);
12122 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid
,
12123 VSX_BUILTIN_STXVD2X_V2DF
);
12124 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid
,
12125 VSX_BUILTIN_STXVD2X_V2DI
);
12126 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid
,
12127 VSX_BUILTIN_STXVW4X_V4SF
);
12128 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid
,
12129 VSX_BUILTIN_STXVW4X_V4SI
);
12130 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid
,
12131 VSX_BUILTIN_STXVW4X_V8HI
);
12132 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid
,
12133 VSX_BUILTIN_STXVW4X_V16QI
);
12134 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid
,
12135 VSX_BUILTIN_VEC_LD
);
12136 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid
,
12137 VSX_BUILTIN_VEC_ST
);
12139 def_builtin ("__builtin_vec_step", int_ftype_opaque
, ALTIVEC_BUILTIN_VEC_STEP
);
12140 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_SPLATS
);
12141 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_PROMOTE
);
12143 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_SLD
);
12144 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_SPLAT
);
12145 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_EXTRACT
);
12146 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_INSERT
);
12147 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTW
);
12148 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTH
);
12149 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTB
);
12150 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTF
);
12151 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFSX
);
12152 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFUX
);
12153 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTS
);
12154 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTU
);
12156 /* Cell builtins. */
12157 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLX
);
12158 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLXL
);
12159 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRX
);
12160 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRXL
);
12162 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLX
);
12163 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLXL
);
12164 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRX
);
12165 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRXL
);
12167 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLX
);
12168 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLXL
);
12169 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRX
);
12170 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRXL
);
12172 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLX
);
12173 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLXL
);
12174 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRX
);
12175 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRXL
);
12177 /* Add the DST variants. */
12179 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
12180 def_builtin (d
->name
, void_ftype_pcvoid_int_int
, d
->code
);
12182 /* Initialize the predicates. */
12183 d
= bdesc_altivec_preds
;
12184 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
12186 enum machine_mode mode1
;
12189 if (rs6000_overloaded_builtin_p (d
->code
))
12192 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
12197 type
= int_ftype_int_opaque_opaque
;
12200 type
= int_ftype_int_v4si_v4si
;
12203 type
= int_ftype_int_v8hi_v8hi
;
12206 type
= int_ftype_int_v16qi_v16qi
;
12209 type
= int_ftype_int_v4sf_v4sf
;
12212 type
= int_ftype_int_v2df_v2df
;
12215 gcc_unreachable ();
12218 def_builtin (d
->name
, type
, d
->code
);
12221 /* Initialize the abs* operators. */
12223 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
12225 enum machine_mode mode0
;
12228 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
12233 type
= v4si_ftype_v4si
;
12236 type
= v8hi_ftype_v8hi
;
12239 type
= v16qi_ftype_v16qi
;
12242 type
= v4sf_ftype_v4sf
;
12245 type
= v2df_ftype_v2df
;
12248 gcc_unreachable ();
12251 def_builtin (d
->name
, type
, d
->code
);
12254 /* Initialize target builtin that implements
12255 targetm.vectorize.builtin_mask_for_load. */
12257 decl
= add_builtin_function ("__builtin_altivec_mask_for_load",
12258 v16qi_ftype_long_pcvoid
,
12259 ALTIVEC_BUILTIN_MASK_FOR_LOAD
,
12260 BUILT_IN_MD
, NULL
, NULL_TREE
);
12261 TREE_READONLY (decl
) = 1;
12262 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
12263 altivec_builtin_mask_for_load
= decl
;
12265 /* Access to the vec_init patterns. */
12266 ftype
= build_function_type_list (V4SI_type_node
, integer_type_node
,
12267 integer_type_node
, integer_type_node
,
12268 integer_type_node
, NULL_TREE
);
12269 def_builtin ("__builtin_vec_init_v4si", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SI
);
12271 ftype
= build_function_type_list (V8HI_type_node
, short_integer_type_node
,
12272 short_integer_type_node
,
12273 short_integer_type_node
,
12274 short_integer_type_node
,
12275 short_integer_type_node
,
12276 short_integer_type_node
,
12277 short_integer_type_node
,
12278 short_integer_type_node
, NULL_TREE
);
12279 def_builtin ("__builtin_vec_init_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V8HI
);
12281 ftype
= build_function_type_list (V16QI_type_node
, char_type_node
,
12282 char_type_node
, char_type_node
,
12283 char_type_node
, char_type_node
,
12284 char_type_node
, char_type_node
,
12285 char_type_node
, char_type_node
,
12286 char_type_node
, char_type_node
,
12287 char_type_node
, char_type_node
,
12288 char_type_node
, char_type_node
,
12289 char_type_node
, NULL_TREE
);
12290 def_builtin ("__builtin_vec_init_v16qi", ftype
,
12291 ALTIVEC_BUILTIN_VEC_INIT_V16QI
);
12293 ftype
= build_function_type_list (V4SF_type_node
, float_type_node
,
12294 float_type_node
, float_type_node
,
12295 float_type_node
, NULL_TREE
);
12296 def_builtin ("__builtin_vec_init_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SF
);
12298 /* VSX builtins. */
12299 ftype
= build_function_type_list (V2DF_type_node
, double_type_node
,
12300 double_type_node
, NULL_TREE
);
12301 def_builtin ("__builtin_vec_init_v2df", ftype
, VSX_BUILTIN_VEC_INIT_V2DF
);
12303 ftype
= build_function_type_list (V2DI_type_node
, intDI_type_node
,
12304 intDI_type_node
, NULL_TREE
);
12305 def_builtin ("__builtin_vec_init_v2di", ftype
, VSX_BUILTIN_VEC_INIT_V2DI
);
12307 /* Access to the vec_set patterns. */
12308 ftype
= build_function_type_list (V4SI_type_node
, V4SI_type_node
,
12310 integer_type_node
, NULL_TREE
);
12311 def_builtin ("__builtin_vec_set_v4si", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SI
);
12313 ftype
= build_function_type_list (V8HI_type_node
, V8HI_type_node
,
12315 integer_type_node
, NULL_TREE
);
12316 def_builtin ("__builtin_vec_set_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V8HI
);
12318 ftype
= build_function_type_list (V16QI_type_node
, V16QI_type_node
,
12320 integer_type_node
, NULL_TREE
);
12321 def_builtin ("__builtin_vec_set_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V16QI
);
12323 ftype
= build_function_type_list (V4SF_type_node
, V4SF_type_node
,
12325 integer_type_node
, NULL_TREE
);
12326 def_builtin ("__builtin_vec_set_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SF
);
12328 ftype
= build_function_type_list (V2DF_type_node
, V2DF_type_node
,
12330 integer_type_node
, NULL_TREE
);
12331 def_builtin ("__builtin_vec_set_v2df", ftype
, VSX_BUILTIN_VEC_SET_V2DF
);
12333 ftype
= build_function_type_list (V2DI_type_node
, V2DI_type_node
,
12335 integer_type_node
, NULL_TREE
);
12336 def_builtin ("__builtin_vec_set_v2di", ftype
, VSX_BUILTIN_VEC_SET_V2DI
);
12338 /* Access to the vec_extract patterns. */
12339 ftype
= build_function_type_list (intSI_type_node
, V4SI_type_node
,
12340 integer_type_node
, NULL_TREE
);
12341 def_builtin ("__builtin_vec_ext_v4si", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SI
);
12343 ftype
= build_function_type_list (intHI_type_node
, V8HI_type_node
,
12344 integer_type_node
, NULL_TREE
);
12345 def_builtin ("__builtin_vec_ext_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V8HI
);
12347 ftype
= build_function_type_list (intQI_type_node
, V16QI_type_node
,
12348 integer_type_node
, NULL_TREE
);
12349 def_builtin ("__builtin_vec_ext_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V16QI
);
12351 ftype
= build_function_type_list (float_type_node
, V4SF_type_node
,
12352 integer_type_node
, NULL_TREE
);
12353 def_builtin ("__builtin_vec_ext_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SF
);
12355 ftype
= build_function_type_list (double_type_node
, V2DF_type_node
,
12356 integer_type_node
, NULL_TREE
);
12357 def_builtin ("__builtin_vec_ext_v2df", ftype
, VSX_BUILTIN_VEC_EXT_V2DF
);
12359 ftype
= build_function_type_list (intDI_type_node
, V2DI_type_node
,
12360 integer_type_node
, NULL_TREE
);
12361 def_builtin ("__builtin_vec_ext_v2di", ftype
, VSX_BUILTIN_VEC_EXT_V2DI
);
12364 /* Hash function for builtin functions with up to 3 arguments and a return
12367 builtin_hash_function (const void *hash_entry
)
12371 const struct builtin_hash_struct
*bh
=
12372 (const struct builtin_hash_struct
*) hash_entry
;
12374 for (i
= 0; i
< 4; i
++)
12376 ret
= (ret
* (unsigned)MAX_MACHINE_MODE
) + ((unsigned)bh
->mode
[i
]);
12377 ret
= (ret
* 2) + bh
->uns_p
[i
];
12383 /* Compare builtin hash entries H1 and H2 for equivalence. */
12385 builtin_hash_eq (const void *h1
, const void *h2
)
12387 const struct builtin_hash_struct
*p1
= (const struct builtin_hash_struct
*) h1
;
12388 const struct builtin_hash_struct
*p2
= (const struct builtin_hash_struct
*) h2
;
12390 return ((p1
->mode
[0] == p2
->mode
[0])
12391 && (p1
->mode
[1] == p2
->mode
[1])
12392 && (p1
->mode
[2] == p2
->mode
[2])
12393 && (p1
->mode
[3] == p2
->mode
[3])
12394 && (p1
->uns_p
[0] == p2
->uns_p
[0])
12395 && (p1
->uns_p
[1] == p2
->uns_p
[1])
12396 && (p1
->uns_p
[2] == p2
->uns_p
[2])
12397 && (p1
->uns_p
[3] == p2
->uns_p
[3]));
12400 /* Map types for builtin functions with an explicit return type and up to 3
12401 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
12402 of the argument. */
12404 builtin_function_type (enum machine_mode mode_ret
, enum machine_mode mode_arg0
,
12405 enum machine_mode mode_arg1
, enum machine_mode mode_arg2
,
12406 enum rs6000_builtins builtin
, const char *name
)
12408 struct builtin_hash_struct h
;
12409 struct builtin_hash_struct
*h2
;
12413 tree ret_type
= NULL_TREE
;
12414 tree arg_type
[3] = { NULL_TREE
, NULL_TREE
, NULL_TREE
};
12416 /* Create builtin_hash_table. */
12417 if (builtin_hash_table
== NULL
)
12418 builtin_hash_table
= htab_create_ggc (1500, builtin_hash_function
,
12419 builtin_hash_eq
, NULL
);
12421 h
.type
= NULL_TREE
;
12422 h
.mode
[0] = mode_ret
;
12423 h
.mode
[1] = mode_arg0
;
12424 h
.mode
[2] = mode_arg1
;
12425 h
.mode
[3] = mode_arg2
;
12431 /* If the builtin is a type that produces unsigned results or takes unsigned
12432 arguments, and it is returned as a decl for the vectorizer (such as
12433 widening multiplies, permute), make sure the arguments and return value
12434 are type correct. */
12437 /* unsigned 2 argument functions. */
12438 case ALTIVEC_BUILTIN_VMULEUB_UNS
:
12439 case ALTIVEC_BUILTIN_VMULEUH_UNS
:
12440 case ALTIVEC_BUILTIN_VMULOUB_UNS
:
12441 case ALTIVEC_BUILTIN_VMULOUH_UNS
:
12447 /* unsigned 3 argument functions. */
12448 case ALTIVEC_BUILTIN_VPERM_16QI_UNS
:
12449 case ALTIVEC_BUILTIN_VPERM_8HI_UNS
:
12450 case ALTIVEC_BUILTIN_VPERM_4SI_UNS
:
12451 case ALTIVEC_BUILTIN_VPERM_2DI_UNS
:
12452 case ALTIVEC_BUILTIN_VSEL_16QI_UNS
:
12453 case ALTIVEC_BUILTIN_VSEL_8HI_UNS
:
12454 case ALTIVEC_BUILTIN_VSEL_4SI_UNS
:
12455 case ALTIVEC_BUILTIN_VSEL_2DI_UNS
:
12456 case VSX_BUILTIN_VPERM_16QI_UNS
:
12457 case VSX_BUILTIN_VPERM_8HI_UNS
:
12458 case VSX_BUILTIN_VPERM_4SI_UNS
:
12459 case VSX_BUILTIN_VPERM_2DI_UNS
:
12460 case VSX_BUILTIN_XXSEL_16QI_UNS
:
12461 case VSX_BUILTIN_XXSEL_8HI_UNS
:
12462 case VSX_BUILTIN_XXSEL_4SI_UNS
:
12463 case VSX_BUILTIN_XXSEL_2DI_UNS
:
12470 /* signed permute functions with unsigned char mask. */
12471 case ALTIVEC_BUILTIN_VPERM_16QI
:
12472 case ALTIVEC_BUILTIN_VPERM_8HI
:
12473 case ALTIVEC_BUILTIN_VPERM_4SI
:
12474 case ALTIVEC_BUILTIN_VPERM_4SF
:
12475 case ALTIVEC_BUILTIN_VPERM_2DI
:
12476 case ALTIVEC_BUILTIN_VPERM_2DF
:
12477 case VSX_BUILTIN_VPERM_16QI
:
12478 case VSX_BUILTIN_VPERM_8HI
:
12479 case VSX_BUILTIN_VPERM_4SI
:
12480 case VSX_BUILTIN_VPERM_4SF
:
12481 case VSX_BUILTIN_VPERM_2DI
:
12482 case VSX_BUILTIN_VPERM_2DF
:
12486 /* unsigned args, signed return. */
12487 case VSX_BUILTIN_XVCVUXDDP_UNS
:
12488 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF
:
12492 /* signed args, unsigned return. */
12493 case VSX_BUILTIN_XVCVDPUXDS_UNS
:
12494 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI
:
12502 /* Figure out how many args are present. */
12503 while (num_args
> 0 && h
.mode
[num_args
] == VOIDmode
)
12507 fatal_error ("internal error: builtin function %s had no type", name
);
12509 ret_type
= builtin_mode_to_type
[h
.mode
[0]][h
.uns_p
[0]];
12510 if (!ret_type
&& h
.uns_p
[0])
12511 ret_type
= builtin_mode_to_type
[h
.mode
[0]][0];
12514 fatal_error ("internal error: builtin function %s had an unexpected "
12515 "return type %s", name
, GET_MODE_NAME (h
.mode
[0]));
12517 for (i
= 0; i
< (int) ARRAY_SIZE (arg_type
); i
++)
12518 arg_type
[i
] = NULL_TREE
;
12520 for (i
= 0; i
< num_args
; i
++)
12522 int m
= (int) h
.mode
[i
+1];
12523 int uns_p
= h
.uns_p
[i
+1];
12525 arg_type
[i
] = builtin_mode_to_type
[m
][uns_p
];
12526 if (!arg_type
[i
] && uns_p
)
12527 arg_type
[i
] = builtin_mode_to_type
[m
][0];
12530 fatal_error ("internal error: builtin function %s, argument %d "
12531 "had unexpected argument type %s", name
, i
,
12532 GET_MODE_NAME (m
));
12535 found
= htab_find_slot (builtin_hash_table
, &h
, INSERT
);
12536 if (*found
== NULL
)
12538 h2
= ggc_alloc_builtin_hash_struct ();
12540 *found
= (void *)h2
;
12542 h2
->type
= build_function_type_list (ret_type
, arg_type
[0], arg_type
[1],
12543 arg_type
[2], NULL_TREE
);
12546 return ((struct builtin_hash_struct
*)(*found
))->type
;
12550 rs6000_common_init_builtins (void)
12552 const struct builtin_description
*d
;
12555 tree opaque_ftype_opaque
= NULL_TREE
;
12556 tree opaque_ftype_opaque_opaque
= NULL_TREE
;
12557 tree opaque_ftype_opaque_opaque_opaque
= NULL_TREE
;
12558 tree v2si_ftype_qi
= NULL_TREE
;
12559 tree v2si_ftype_v2si_qi
= NULL_TREE
;
12560 tree v2si_ftype_int_qi
= NULL_TREE
;
12561 unsigned builtin_mask
= rs6000_builtin_mask
;
12563 if (!TARGET_PAIRED_FLOAT
)
12565 builtin_mode_to_type
[V2SImode
][0] = opaque_V2SI_type_node
;
12566 builtin_mode_to_type
[V2SFmode
][0] = opaque_V2SF_type_node
;
12569 /* Paired and SPE builtins are only available if you build a compiler with
12570 the appropriate options, so only create those builtins with the
12571 appropriate compiler option. Create Altivec and VSX builtins on machines
12572 with at least the general purpose extensions (970 and newer) to allow the
12573 use of the target attribute.. */
12575 if (TARGET_EXTRA_BUILTINS
)
12576 builtin_mask
|= RS6000_BTM_COMMON
;
12578 /* Add the ternary operators. */
12580 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
12583 unsigned mask
= d
->mask
;
12585 if ((mask
& builtin_mask
) != mask
)
12587 if (TARGET_DEBUG_BUILTIN
)
12588 fprintf (stderr
, "rs6000_builtin, skip ternary %s\n", d
->name
);
12592 if (rs6000_overloaded_builtin_p (d
->code
))
12594 if (! (type
= opaque_ftype_opaque_opaque_opaque
))
12595 type
= opaque_ftype_opaque_opaque_opaque
12596 = build_function_type_list (opaque_V4SI_type_node
,
12597 opaque_V4SI_type_node
,
12598 opaque_V4SI_type_node
,
12599 opaque_V4SI_type_node
,
12604 enum insn_code icode
= d
->icode
;
12605 if (d
->name
== 0 || icode
== CODE_FOR_nothing
)
12608 type
= builtin_function_type (insn_data
[icode
].operand
[0].mode
,
12609 insn_data
[icode
].operand
[1].mode
,
12610 insn_data
[icode
].operand
[2].mode
,
12611 insn_data
[icode
].operand
[3].mode
,
12615 def_builtin (d
->name
, type
, d
->code
);
12618 /* Add the binary operators. */
12620 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12622 enum machine_mode mode0
, mode1
, mode2
;
12624 unsigned mask
= d
->mask
;
12626 if ((mask
& builtin_mask
) != mask
)
12628 if (TARGET_DEBUG_BUILTIN
)
12629 fprintf (stderr
, "rs6000_builtin, skip binary %s\n", d
->name
);
12633 if (rs6000_overloaded_builtin_p (d
->code
))
12635 if (! (type
= opaque_ftype_opaque_opaque
))
12636 type
= opaque_ftype_opaque_opaque
12637 = build_function_type_list (opaque_V4SI_type_node
,
12638 opaque_V4SI_type_node
,
12639 opaque_V4SI_type_node
,
12644 enum insn_code icode
= d
->icode
;
12645 if (d
->name
== 0 || icode
== CODE_FOR_nothing
)
12648 mode0
= insn_data
[icode
].operand
[0].mode
;
12649 mode1
= insn_data
[icode
].operand
[1].mode
;
12650 mode2
= insn_data
[icode
].operand
[2].mode
;
12652 if (mode0
== V2SImode
&& mode1
== V2SImode
&& mode2
== QImode
)
12654 if (! (type
= v2si_ftype_v2si_qi
))
12655 type
= v2si_ftype_v2si_qi
12656 = build_function_type_list (opaque_V2SI_type_node
,
12657 opaque_V2SI_type_node
,
12662 else if (mode0
== V2SImode
&& GET_MODE_CLASS (mode1
) == MODE_INT
12663 && mode2
== QImode
)
12665 if (! (type
= v2si_ftype_int_qi
))
12666 type
= v2si_ftype_int_qi
12667 = build_function_type_list (opaque_V2SI_type_node
,
12674 type
= builtin_function_type (mode0
, mode1
, mode2
, VOIDmode
,
12678 def_builtin (d
->name
, type
, d
->code
);
12681 /* Add the simple unary operators. */
12683 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
12685 enum machine_mode mode0
, mode1
;
12687 unsigned mask
= d
->mask
;
12689 if ((mask
& builtin_mask
) != mask
)
12691 if (TARGET_DEBUG_BUILTIN
)
12692 fprintf (stderr
, "rs6000_builtin, skip unary %s\n", d
->name
);
12696 if (rs6000_overloaded_builtin_p (d
->code
))
12698 if (! (type
= opaque_ftype_opaque
))
12699 type
= opaque_ftype_opaque
12700 = build_function_type_list (opaque_V4SI_type_node
,
12701 opaque_V4SI_type_node
,
12706 enum insn_code icode
= d
->icode
;
12707 if (d
->name
== 0 || icode
== CODE_FOR_nothing
)
12710 mode0
= insn_data
[icode
].operand
[0].mode
;
12711 mode1
= insn_data
[icode
].operand
[1].mode
;
12713 if (mode0
== V2SImode
&& mode1
== QImode
)
12715 if (! (type
= v2si_ftype_qi
))
12716 type
= v2si_ftype_qi
12717 = build_function_type_list (opaque_V2SI_type_node
,
12723 type
= builtin_function_type (mode0
, mode1
, VOIDmode
, VOIDmode
,
12727 def_builtin (d
->name
, type
, d
->code
);
12732 rs6000_init_libfuncs (void)
12734 if (DEFAULT_ABI
!= ABI_V4
&& TARGET_XCOFF
12735 && !TARGET_POWER2
&& !TARGET_POWERPC
)
12737 /* AIX library routines for float->int conversion. */
12738 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__itrunc");
12739 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__uitrunc");
12740 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_qitrunc");
12741 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_quitrunc");
12744 if (!TARGET_IEEEQUAD
)
12745 /* AIX/Darwin/64-bit Linux quad floating point routines. */
12746 if (!TARGET_XL_COMPAT
)
12748 set_optab_libfunc (add_optab
, TFmode
, "__gcc_qadd");
12749 set_optab_libfunc (sub_optab
, TFmode
, "__gcc_qsub");
12750 set_optab_libfunc (smul_optab
, TFmode
, "__gcc_qmul");
12751 set_optab_libfunc (sdiv_optab
, TFmode
, "__gcc_qdiv");
12753 if (!(TARGET_HARD_FLOAT
&& (TARGET_FPRS
|| TARGET_E500_DOUBLE
)))
12755 set_optab_libfunc (neg_optab
, TFmode
, "__gcc_qneg");
12756 set_optab_libfunc (eq_optab
, TFmode
, "__gcc_qeq");
12757 set_optab_libfunc (ne_optab
, TFmode
, "__gcc_qne");
12758 set_optab_libfunc (gt_optab
, TFmode
, "__gcc_qgt");
12759 set_optab_libfunc (ge_optab
, TFmode
, "__gcc_qge");
12760 set_optab_libfunc (lt_optab
, TFmode
, "__gcc_qlt");
12761 set_optab_libfunc (le_optab
, TFmode
, "__gcc_qle");
12763 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "__gcc_stoq");
12764 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "__gcc_dtoq");
12765 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "__gcc_qtos");
12766 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "__gcc_qtod");
12767 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "__gcc_qtoi");
12768 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "__gcc_qtou");
12769 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "__gcc_itoq");
12770 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "__gcc_utoq");
12773 if (!(TARGET_HARD_FLOAT
&& TARGET_FPRS
))
12774 set_optab_libfunc (unord_optab
, TFmode
, "__gcc_qunord");
12778 set_optab_libfunc (add_optab
, TFmode
, "_xlqadd");
12779 set_optab_libfunc (sub_optab
, TFmode
, "_xlqsub");
12780 set_optab_libfunc (smul_optab
, TFmode
, "_xlqmul");
12781 set_optab_libfunc (sdiv_optab
, TFmode
, "_xlqdiv");
12785 /* 32-bit SVR4 quad floating point routines. */
12787 set_optab_libfunc (add_optab
, TFmode
, "_q_add");
12788 set_optab_libfunc (sub_optab
, TFmode
, "_q_sub");
12789 set_optab_libfunc (neg_optab
, TFmode
, "_q_neg");
12790 set_optab_libfunc (smul_optab
, TFmode
, "_q_mul");
12791 set_optab_libfunc (sdiv_optab
, TFmode
, "_q_div");
12792 if (TARGET_PPC_GPOPT
|| TARGET_POWER2
)
12793 set_optab_libfunc (sqrt_optab
, TFmode
, "_q_sqrt");
12795 set_optab_libfunc (eq_optab
, TFmode
, "_q_feq");
12796 set_optab_libfunc (ne_optab
, TFmode
, "_q_fne");
12797 set_optab_libfunc (gt_optab
, TFmode
, "_q_fgt");
12798 set_optab_libfunc (ge_optab
, TFmode
, "_q_fge");
12799 set_optab_libfunc (lt_optab
, TFmode
, "_q_flt");
12800 set_optab_libfunc (le_optab
, TFmode
, "_q_fle");
12802 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_q_stoq");
12803 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_q_dtoq");
12804 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_q_qtos");
12805 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_q_qtod");
12806 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_q_qtoi");
12807 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_q_qtou");
12808 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_q_itoq");
12809 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_q_utoq");
12814 /* Expand a block clear operation, and return 1 if successful. Return 0
12815 if we should let the compiler generate normal code.
12817 operands[0] is the destination
12818 operands[1] is the length
12819 operands[3] is the alignment */
12822 expand_block_clear (rtx operands
[])
12824 rtx orig_dest
= operands
[0];
12825 rtx bytes_rtx
= operands
[1];
12826 rtx align_rtx
= operands
[3];
12827 bool constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
12828 HOST_WIDE_INT align
;
12829 HOST_WIDE_INT bytes
;
12834 /* If this is not a fixed size move, just call memcpy */
12838 /* This must be a fixed size alignment */
12839 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
12840 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
12842 /* Anything to clear? */
12843 bytes
= INTVAL (bytes_rtx
);
12847 /* Use the builtin memset after a point, to avoid huge code bloat.
12848 When optimize_size, avoid any significant code bloat; calling
12849 memset is about 4 instructions, so allow for one instruction to
12850 load zero and three to do clearing. */
12851 if (TARGET_ALTIVEC
&& align
>= 128)
12853 else if (TARGET_POWERPC64
&& align
>= 32)
12855 else if (TARGET_SPE
&& align
>= 64)
12860 if (optimize_size
&& bytes
> 3 * clear_step
)
12862 if (! optimize_size
&& bytes
> 8 * clear_step
)
12865 for (offset
= 0; bytes
> 0; offset
+= clear_bytes
, bytes
-= clear_bytes
)
12867 enum machine_mode mode
= BLKmode
;
12870 if (bytes
>= 16 && TARGET_ALTIVEC
&& align
>= 128)
12875 else if (bytes
>= 8 && TARGET_SPE
&& align
>= 64)
12880 else if (bytes
>= 8 && TARGET_POWERPC64
12881 /* 64-bit loads and stores require word-aligned
12883 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
12888 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
12889 { /* move 4 bytes */
12893 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
12894 { /* move 2 bytes */
12898 else /* move 1 byte at a time */
12904 dest
= adjust_address (orig_dest
, mode
, offset
);
12906 emit_move_insn (dest
, CONST0_RTX (mode
));
12913 /* Expand a block move operation, and return 1 if successful. Return 0
12914 if we should let the compiler generate normal code.
12916 operands[0] is the destination
12917 operands[1] is the source
12918 operands[2] is the length
12919 operands[3] is the alignment */
12921 #define MAX_MOVE_REG 4
12924 expand_block_move (rtx operands
[])
12926 rtx orig_dest
= operands
[0];
12927 rtx orig_src
= operands
[1];
12928 rtx bytes_rtx
= operands
[2];
12929 rtx align_rtx
= operands
[3];
12930 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
12935 rtx stores
[MAX_MOVE_REG
];
12938 /* If this is not a fixed size move, just call memcpy */
12942 /* This must be a fixed size alignment */
12943 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
12944 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
12946 /* Anything to move? */
12947 bytes
= INTVAL (bytes_rtx
);
12951 if (bytes
> rs6000_block_move_inline_limit
)
12954 for (offset
= 0; bytes
> 0; offset
+= move_bytes
, bytes
-= move_bytes
)
12957 rtx (*movmemsi
) (rtx
, rtx
, rtx
, rtx
);
12958 rtx (*mov
) (rtx
, rtx
);
12960 enum machine_mode mode
= BLKmode
;
12963 /* Altivec first, since it will be faster than a string move
12964 when it applies, and usually not significantly larger. */
12965 if (TARGET_ALTIVEC
&& bytes
>= 16 && align
>= 128)
12969 gen_func
.mov
= gen_movv4si
;
12971 else if (TARGET_SPE
&& bytes
>= 8 && align
>= 64)
12975 gen_func
.mov
= gen_movv2si
;
12977 else if (TARGET_STRING
12978 && bytes
> 24 /* move up to 32 bytes at a time */
12984 && ! fixed_regs
[10]
12985 && ! fixed_regs
[11]
12986 && ! fixed_regs
[12])
12988 move_bytes
= (bytes
> 32) ? 32 : bytes
;
12989 gen_func
.movmemsi
= gen_movmemsi_8reg
;
12991 else if (TARGET_STRING
12992 && bytes
> 16 /* move up to 24 bytes at a time */
12998 && ! fixed_regs
[10])
13000 move_bytes
= (bytes
> 24) ? 24 : bytes
;
13001 gen_func
.movmemsi
= gen_movmemsi_6reg
;
13003 else if (TARGET_STRING
13004 && bytes
> 8 /* move up to 16 bytes at a time */
13008 && ! fixed_regs
[8])
13010 move_bytes
= (bytes
> 16) ? 16 : bytes
;
13011 gen_func
.movmemsi
= gen_movmemsi_4reg
;
13013 else if (bytes
>= 8 && TARGET_POWERPC64
13014 /* 64-bit loads and stores require word-aligned
13016 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
13020 gen_func
.mov
= gen_movdi
;
13022 else if (TARGET_STRING
&& bytes
> 4 && !TARGET_POWERPC64
)
13023 { /* move up to 8 bytes at a time */
13024 move_bytes
= (bytes
> 8) ? 8 : bytes
;
13025 gen_func
.movmemsi
= gen_movmemsi_2reg
;
13027 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
13028 { /* move 4 bytes */
13031 gen_func
.mov
= gen_movsi
;
13033 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
13034 { /* move 2 bytes */
13037 gen_func
.mov
= gen_movhi
;
13039 else if (TARGET_STRING
&& bytes
> 1)
13040 { /* move up to 4 bytes at a time */
13041 move_bytes
= (bytes
> 4) ? 4 : bytes
;
13042 gen_func
.movmemsi
= gen_movmemsi_1reg
;
13044 else /* move 1 byte at a time */
13048 gen_func
.mov
= gen_movqi
;
13051 src
= adjust_address (orig_src
, mode
, offset
);
13052 dest
= adjust_address (orig_dest
, mode
, offset
);
13054 if (mode
!= BLKmode
)
13056 rtx tmp_reg
= gen_reg_rtx (mode
);
13058 emit_insn ((*gen_func
.mov
) (tmp_reg
, src
));
13059 stores
[num_reg
++] = (*gen_func
.mov
) (dest
, tmp_reg
);
13062 if (mode
== BLKmode
|| num_reg
>= MAX_MOVE_REG
|| bytes
== move_bytes
)
13065 for (i
= 0; i
< num_reg
; i
++)
13066 emit_insn (stores
[i
]);
13070 if (mode
== BLKmode
)
13072 /* Move the address into scratch registers. The movmemsi
13073 patterns require zero offset. */
13074 if (!REG_P (XEXP (src
, 0)))
13076 rtx src_reg
= copy_addr_to_reg (XEXP (src
, 0));
13077 src
= replace_equiv_address (src
, src_reg
);
13079 set_mem_size (src
, move_bytes
);
13081 if (!REG_P (XEXP (dest
, 0)))
13083 rtx dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
13084 dest
= replace_equiv_address (dest
, dest_reg
);
13086 set_mem_size (dest
, move_bytes
);
13088 emit_insn ((*gen_func
.movmemsi
) (dest
, src
,
13089 GEN_INT (move_bytes
& 31),
13098 /* Return a string to perform a load_multiple operation.
13099 operands[0] is the vector.
13100 operands[1] is the source address.
13101 operands[2] is the first destination register. */
13104 rs6000_output_load_multiple (rtx operands
[3])
13106 /* We have to handle the case where the pseudo used to contain the address
13107 is assigned to one of the output registers. */
13109 int words
= XVECLEN (operands
[0], 0);
13112 if (XVECLEN (operands
[0], 0) == 1)
13113 return "{l|lwz} %2,0(%1)";
13115 for (i
= 0; i
< words
; i
++)
13116 if (refers_to_regno_p (REGNO (operands
[2]) + i
,
13117 REGNO (operands
[2]) + i
+ 1, operands
[1], 0))
13121 xop
[0] = GEN_INT (4 * (words
-1));
13122 xop
[1] = operands
[1];
13123 xop
[2] = operands
[2];
13124 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop
);
13129 xop
[0] = GEN_INT (4 * (words
-1));
13130 xop
[1] = operands
[1];
13131 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
13132 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop
);
13137 for (j
= 0; j
< words
; j
++)
13140 xop
[0] = GEN_INT (j
* 4);
13141 xop
[1] = operands
[1];
13142 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + j
);
13143 output_asm_insn ("{l|lwz} %2,%0(%1)", xop
);
13145 xop
[0] = GEN_INT (i
* 4);
13146 xop
[1] = operands
[1];
13147 output_asm_insn ("{l|lwz} %1,%0(%1)", xop
);
13152 return "{lsi|lswi} %2,%1,%N0";
13156 /* A validation routine: say whether CODE, a condition code, and MODE
13157 match. The other alternatives either don't make sense or should
13158 never be generated. */
13161 validate_condition_mode (enum rtx_code code
, enum machine_mode mode
)
13163 gcc_assert ((GET_RTX_CLASS (code
) == RTX_COMPARE
13164 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
13165 && GET_MODE_CLASS (mode
) == MODE_CC
);
13167 /* These don't make sense. */
13168 gcc_assert ((code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
)
13169 || mode
!= CCUNSmode
);
13171 gcc_assert ((code
!= GTU
&& code
!= LTU
&& code
!= GEU
&& code
!= LEU
)
13172 || mode
== CCUNSmode
);
13174 gcc_assert (mode
== CCFPmode
13175 || (code
!= ORDERED
&& code
!= UNORDERED
13176 && code
!= UNEQ
&& code
!= LTGT
13177 && code
!= UNGT
&& code
!= UNLT
13178 && code
!= UNGE
&& code
!= UNLE
));
13180 /* These should never be generated except for
13181 flag_finite_math_only. */
13182 gcc_assert (mode
!= CCFPmode
13183 || flag_finite_math_only
13184 || (code
!= LE
&& code
!= GE
13185 && code
!= UNEQ
&& code
!= LTGT
13186 && code
!= UNGT
&& code
!= UNLT
));
13188 /* These are invalid; the information is not there. */
13189 gcc_assert (mode
!= CCEQmode
|| code
== EQ
|| code
== NE
);
13193 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
13194 mask required to convert the result of a rotate insn into a shift
13195 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
13198 includes_lshift_p (rtx shiftop
, rtx andop
)
13200 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
13202 shift_mask
<<= INTVAL (shiftop
);
13204 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
13207 /* Similar, but for right shift. */
13210 includes_rshift_p (rtx shiftop
, rtx andop
)
13212 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
13214 shift_mask
>>= INTVAL (shiftop
);
13216 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
13219 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
13220 to perform a left shift. It must have exactly SHIFTOP least
13221 significant 0's, then one or more 1's, then zero or more 0's. */
13224 includes_rldic_lshift_p (rtx shiftop
, rtx andop
)
13226 if (GET_CODE (andop
) == CONST_INT
)
13228 HOST_WIDE_INT c
, lsb
, shift_mask
;
13230 c
= INTVAL (andop
);
13231 if (c
== 0 || c
== ~0)
13235 shift_mask
<<= INTVAL (shiftop
);
13237 /* Find the least significant one bit. */
13240 /* It must coincide with the LSB of the shift mask. */
13241 if (-lsb
!= shift_mask
)
13244 /* Invert to look for the next transition (if any). */
13247 /* Remove the low group of ones (originally low group of zeros). */
13250 /* Again find the lsb, and check we have all 1's above. */
13254 else if (GET_CODE (andop
) == CONST_DOUBLE
13255 && (GET_MODE (andop
) == VOIDmode
|| GET_MODE (andop
) == DImode
))
13257 HOST_WIDE_INT low
, high
, lsb
;
13258 HOST_WIDE_INT shift_mask_low
, shift_mask_high
;
13260 low
= CONST_DOUBLE_LOW (andop
);
13261 if (HOST_BITS_PER_WIDE_INT
< 64)
13262 high
= CONST_DOUBLE_HIGH (andop
);
13264 if ((low
== 0 && (HOST_BITS_PER_WIDE_INT
>= 64 || high
== 0))
13265 || (low
== ~0 && (HOST_BITS_PER_WIDE_INT
>= 64 || high
== ~0)))
13268 if (HOST_BITS_PER_WIDE_INT
< 64 && low
== 0)
13270 shift_mask_high
= ~0;
13271 if (INTVAL (shiftop
) > 32)
13272 shift_mask_high
<<= INTVAL (shiftop
) - 32;
13274 lsb
= high
& -high
;
13276 if (-lsb
!= shift_mask_high
|| INTVAL (shiftop
) < 32)
13282 lsb
= high
& -high
;
13283 return high
== -lsb
;
13286 shift_mask_low
= ~0;
13287 shift_mask_low
<<= INTVAL (shiftop
);
13291 if (-lsb
!= shift_mask_low
)
13294 if (HOST_BITS_PER_WIDE_INT
< 64)
13299 if (HOST_BITS_PER_WIDE_INT
< 64 && low
== 0)
13301 lsb
= high
& -high
;
13302 return high
== -lsb
;
13306 return low
== -lsb
&& (HOST_BITS_PER_WIDE_INT
>= 64 || high
== ~0);
13312 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
13313 to perform a left shift. It must have SHIFTOP or more least
13314 significant 0's, with the remainder of the word 1's. */
13317 includes_rldicr_lshift_p (rtx shiftop
, rtx andop
)
13319 if (GET_CODE (andop
) == CONST_INT
)
13321 HOST_WIDE_INT c
, lsb
, shift_mask
;
13324 shift_mask
<<= INTVAL (shiftop
);
13325 c
= INTVAL (andop
);
13327 /* Find the least significant one bit. */
13330 /* It must be covered by the shift mask.
13331 This test also rejects c == 0. */
13332 if ((lsb
& shift_mask
) == 0)
13335 /* Check we have all 1's above the transition, and reject all 1's. */
13336 return c
== -lsb
&& lsb
!= 1;
13338 else if (GET_CODE (andop
) == CONST_DOUBLE
13339 && (GET_MODE (andop
) == VOIDmode
|| GET_MODE (andop
) == DImode
))
13341 HOST_WIDE_INT low
, lsb
, shift_mask_low
;
13343 low
= CONST_DOUBLE_LOW (andop
);
13345 if (HOST_BITS_PER_WIDE_INT
< 64)
13347 HOST_WIDE_INT high
, shift_mask_high
;
13349 high
= CONST_DOUBLE_HIGH (andop
);
13353 shift_mask_high
= ~0;
13354 if (INTVAL (shiftop
) > 32)
13355 shift_mask_high
<<= INTVAL (shiftop
) - 32;
13357 lsb
= high
& -high
;
13359 if ((lsb
& shift_mask_high
) == 0)
13362 return high
== -lsb
;
13368 shift_mask_low
= ~0;
13369 shift_mask_low
<<= INTVAL (shiftop
);
13373 if ((lsb
& shift_mask_low
) == 0)
13376 return low
== -lsb
&& lsb
!= 1;
13382 /* Return 1 if operands will generate a valid arguments to rlwimi
13383 instruction for insert with right shift in 64-bit mode. The mask may
13384 not start on the first bit or stop on the last bit because wrap-around
13385 effects of instruction do not correspond to semantics of RTL insn. */
13388 insvdi_rshift_rlwimi_p (rtx sizeop
, rtx startop
, rtx shiftop
)
13390 if (INTVAL (startop
) > 32
13391 && INTVAL (startop
) < 64
13392 && INTVAL (sizeop
) > 1
13393 && INTVAL (sizeop
) + INTVAL (startop
) < 64
13394 && INTVAL (shiftop
) > 0
13395 && INTVAL (sizeop
) + INTVAL (shiftop
) < 32
13396 && (64 - (INTVAL (shiftop
) & 63)) >= INTVAL (sizeop
))
13402 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
13403 for lfq and stfq insns iff the registers are hard registers. */
13406 registers_ok_for_quad_peep (rtx reg1
, rtx reg2
)
13408 /* We might have been passed a SUBREG. */
13409 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
13412 /* We might have been passed non floating point registers. */
13413 if (!FP_REGNO_P (REGNO (reg1
))
13414 || !FP_REGNO_P (REGNO (reg2
)))
13417 return (REGNO (reg1
) == REGNO (reg2
) - 1);
13420 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
13421 addr1 and addr2 must be in consecutive memory locations
13422 (addr2 == addr1 + 8). */
13425 mems_ok_for_quad_peep (rtx mem1
, rtx mem2
)
13428 unsigned int reg1
, reg2
;
13429 int offset1
, offset2
;
13431 /* The mems cannot be volatile. */
13432 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
13435 addr1
= XEXP (mem1
, 0);
13436 addr2
= XEXP (mem2
, 0);
13438 /* Extract an offset (if used) from the first addr. */
13439 if (GET_CODE (addr1
) == PLUS
)
13441 /* If not a REG, return zero. */
13442 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
13446 reg1
= REGNO (XEXP (addr1
, 0));
13447 /* The offset must be constant! */
13448 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
13450 offset1
= INTVAL (XEXP (addr1
, 1));
13453 else if (GET_CODE (addr1
) != REG
)
13457 reg1
= REGNO (addr1
);
13458 /* This was a simple (mem (reg)) expression. Offset is 0. */
13462 /* And now for the second addr. */
13463 if (GET_CODE (addr2
) == PLUS
)
13465 /* If not a REG, return zero. */
13466 if (GET_CODE (XEXP (addr2
, 0)) != REG
)
13470 reg2
= REGNO (XEXP (addr2
, 0));
13471 /* The offset must be constant. */
13472 if (GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
13474 offset2
= INTVAL (XEXP (addr2
, 1));
13477 else if (GET_CODE (addr2
) != REG
)
13481 reg2
= REGNO (addr2
);
13482 /* This was a simple (mem (reg)) expression. Offset is 0. */
13486 /* Both of these must have the same base register. */
13490 /* The offset for the second addr must be 8 more than the first addr. */
13491 if (offset2
!= offset1
+ 8)
13494 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
13501 rs6000_secondary_memory_needed_rtx (enum machine_mode mode
)
13503 static bool eliminated
= false;
13506 if (mode
!= SDmode
)
13507 ret
= assign_stack_local (mode
, GET_MODE_SIZE (mode
), 0);
13510 rtx mem
= cfun
->machine
->sdmode_stack_slot
;
13511 gcc_assert (mem
!= NULL_RTX
);
13515 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
13516 cfun
->machine
->sdmode_stack_slot
= mem
;
13522 if (TARGET_DEBUG_ADDR
)
13524 fprintf (stderr
, "\nrs6000_secondary_memory_needed_rtx, mode %s, rtx:\n",
13525 GET_MODE_NAME (mode
));
13527 fprintf (stderr
, "\tNULL_RTX\n");
13536 rs6000_check_sdmode (tree
*tp
, int *walk_subtrees
, void *data ATTRIBUTE_UNUSED
)
13538 /* Don't walk into types. */
13539 if (*tp
== NULL_TREE
|| *tp
== error_mark_node
|| TYPE_P (*tp
))
13541 *walk_subtrees
= 0;
13545 switch (TREE_CODE (*tp
))
13554 case VIEW_CONVERT_EXPR
:
13555 if (TYPE_MODE (TREE_TYPE (*tp
)) == SDmode
)
13565 enum reload_reg_type
{
13567 VECTOR_REGISTER_TYPE
,
13568 OTHER_REGISTER_TYPE
13571 static enum reload_reg_type
13572 rs6000_reload_register_type (enum reg_class rclass
)
13578 return GPR_REGISTER_TYPE
;
13583 return VECTOR_REGISTER_TYPE
;
13586 return OTHER_REGISTER_TYPE
;
13590 /* Inform reload about cases where moving X with a mode MODE to a register in
13591 RCLASS requires an extra scratch or immediate register. Return the class
13592 needed for the immediate register.
13594 For VSX and Altivec, we may need a register to convert sp+offset into
13597 For misaligned 64-bit gpr loads and stores we need a register to
13598 convert an offset address to indirect. */
13601 rs6000_secondary_reload (bool in_p
,
13603 reg_class_t rclass_i
,
13604 enum machine_mode mode
,
13605 secondary_reload_info
*sri
)
13607 enum reg_class rclass
= (enum reg_class
) rclass_i
;
13608 reg_class_t ret
= ALL_REGS
;
13609 enum insn_code icode
;
13610 bool default_p
= false;
13612 sri
->icode
= CODE_FOR_nothing
;
13614 /* Convert vector loads and stores into gprs to use an additional base
13616 icode
= rs6000_vector_reload
[mode
][in_p
!= false];
13617 if (icode
!= CODE_FOR_nothing
)
13620 sri
->icode
= CODE_FOR_nothing
;
13621 sri
->extra_cost
= 0;
13623 if (GET_CODE (x
) == MEM
)
13625 rtx addr
= XEXP (x
, 0);
13627 /* Loads to and stores from gprs can do reg+offset, and wouldn't need
13628 an extra register in that case, but it would need an extra
13629 register if the addressing is reg+reg or (reg+reg)&(-16). */
13630 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
)
13632 if (!legitimate_indirect_address_p (addr
, false)
13633 && !rs6000_legitimate_offset_address_p (TImode
, addr
, false))
13635 sri
->icode
= icode
;
13636 /* account for splitting the loads, and converting the
13637 address from reg+reg to reg. */
13638 sri
->extra_cost
= (((TARGET_64BIT
) ? 3 : 5)
13639 + ((GET_CODE (addr
) == AND
) ? 1 : 0));
13642 /* Loads to and stores from vector registers can only do reg+reg
13643 addressing. Altivec registers can also do (reg+reg)&(-16). */
13644 else if (rclass
== VSX_REGS
|| rclass
== ALTIVEC_REGS
13645 || rclass
== FLOAT_REGS
|| rclass
== NO_REGS
)
13647 if (!VECTOR_MEM_ALTIVEC_P (mode
)
13648 && GET_CODE (addr
) == AND
13649 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
13650 && INTVAL (XEXP (addr
, 1)) == -16
13651 && (legitimate_indirect_address_p (XEXP (addr
, 0), false)
13652 || legitimate_indexed_address_p (XEXP (addr
, 0), false)))
13654 sri
->icode
= icode
;
13655 sri
->extra_cost
= ((GET_CODE (XEXP (addr
, 0)) == PLUS
)
13658 else if (!legitimate_indirect_address_p (addr
, false)
13659 && (rclass
== NO_REGS
13660 || !legitimate_indexed_address_p (addr
, false)))
13662 sri
->icode
= icode
;
13663 sri
->extra_cost
= 1;
13666 icode
= CODE_FOR_nothing
;
13668 /* Any other loads, including to pseudo registers which haven't been
13669 assigned to a register yet, default to require a scratch
13673 sri
->icode
= icode
;
13674 sri
->extra_cost
= 2;
13677 else if (REG_P (x
))
13679 int regno
= true_regnum (x
);
13681 icode
= CODE_FOR_nothing
;
13682 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
13686 enum reg_class xclass
= REGNO_REG_CLASS (regno
);
13687 enum reload_reg_type rtype1
= rs6000_reload_register_type (rclass
);
13688 enum reload_reg_type rtype2
= rs6000_reload_register_type (xclass
);
13690 /* If memory is needed, use default_secondary_reload to create the
13692 if (rtype1
!= rtype2
|| rtype1
== OTHER_REGISTER_TYPE
)
13701 else if (TARGET_POWERPC64
13702 && rs6000_reload_register_type (rclass
) == GPR_REGISTER_TYPE
13704 && GET_MODE_SIZE (GET_MODE (x
)) >= UNITS_PER_WORD
)
13706 rtx addr
= XEXP (x
, 0);
13708 if (GET_CODE (addr
) == PRE_MODIFY
)
13709 addr
= XEXP (addr
, 1);
13710 else if (GET_CODE (addr
) == LO_SUM
13711 && GET_CODE (XEXP (addr
, 0)) == REG
13712 && GET_CODE (XEXP (addr
, 1)) == CONST
)
13713 addr
= XEXP (XEXP (addr
, 1), 0);
13715 if (GET_CODE (addr
) == PLUS
13716 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
13717 && (INTVAL (XEXP (addr
, 1)) & 3) != 0)
13720 sri
->icode
= CODE_FOR_reload_di_load
;
13722 sri
->icode
= CODE_FOR_reload_di_store
;
13723 sri
->extra_cost
= 2;
13733 ret
= default_secondary_reload (in_p
, x
, rclass
, mode
, sri
);
13735 gcc_assert (ret
!= ALL_REGS
);
13737 if (TARGET_DEBUG_ADDR
)
13740 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
13742 reg_class_names
[ret
],
13743 in_p
? "true" : "false",
13744 reg_class_names
[rclass
],
13745 GET_MODE_NAME (mode
));
13748 fprintf (stderr
, ", default secondary reload");
13750 if (sri
->icode
!= CODE_FOR_nothing
)
13751 fprintf (stderr
, ", reload func = %s, extra cost = %d\n",
13752 insn_data
[sri
->icode
].name
, sri
->extra_cost
);
13754 fprintf (stderr
, "\n");
13762 /* Fixup reload addresses for Altivec or VSX loads/stores to change SP+offset
13763 to SP+reg addressing. */
13766 rs6000_secondary_reload_inner (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
13768 int regno
= true_regnum (reg
);
13769 enum machine_mode mode
= GET_MODE (reg
);
13770 enum reg_class rclass
;
13772 rtx and_op2
= NULL_RTX
;
13775 rtx scratch_or_premodify
= scratch
;
13779 if (TARGET_DEBUG_ADDR
)
13781 fprintf (stderr
, "\nrs6000_secondary_reload_inner, type = %s\n",
13782 store_p
? "store" : "load");
13783 fprintf (stderr
, "reg:\n");
13785 fprintf (stderr
, "mem:\n");
13787 fprintf (stderr
, "scratch:\n");
13788 debug_rtx (scratch
);
13791 gcc_assert (regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
);
13792 gcc_assert (GET_CODE (mem
) == MEM
);
13793 rclass
= REGNO_REG_CLASS (regno
);
13794 addr
= XEXP (mem
, 0);
13798 /* GPRs can handle reg + small constant, all other addresses need to use
13799 the scratch register. */
13802 if (GET_CODE (addr
) == AND
)
13804 and_op2
= XEXP (addr
, 1);
13805 addr
= XEXP (addr
, 0);
13808 if (GET_CODE (addr
) == PRE_MODIFY
)
13810 scratch_or_premodify
= XEXP (addr
, 0);
13811 gcc_assert (REG_P (scratch_or_premodify
));
13812 gcc_assert (GET_CODE (XEXP (addr
, 1)) == PLUS
);
13813 addr
= XEXP (addr
, 1);
13816 if (GET_CODE (addr
) == PLUS
13817 && (!rs6000_legitimate_offset_address_p (TImode
, addr
, false)
13818 || and_op2
!= NULL_RTX
))
13820 addr_op1
= XEXP (addr
, 0);
13821 addr_op2
= XEXP (addr
, 1);
13822 gcc_assert (legitimate_indirect_address_p (addr_op1
, false));
13824 if (!REG_P (addr_op2
)
13825 && (GET_CODE (addr_op2
) != CONST_INT
13826 || !satisfies_constraint_I (addr_op2
)))
13828 if (TARGET_DEBUG_ADDR
)
13831 "\nMove plus addr to register %s, mode = %s: ",
13832 rs6000_reg_names
[REGNO (scratch
)],
13833 GET_MODE_NAME (mode
));
13834 debug_rtx (addr_op2
);
13836 rs6000_emit_move (scratch
, addr_op2
, Pmode
);
13837 addr_op2
= scratch
;
13840 emit_insn (gen_rtx_SET (VOIDmode
,
13841 scratch_or_premodify
,
13842 gen_rtx_PLUS (Pmode
,
13846 addr
= scratch_or_premodify
;
13847 scratch_or_premodify
= scratch
;
13849 else if (!legitimate_indirect_address_p (addr
, false)
13850 && !rs6000_legitimate_offset_address_p (TImode
, addr
, false))
13852 if (TARGET_DEBUG_ADDR
)
13854 fprintf (stderr
, "\nMove addr to register %s, mode = %s: ",
13855 rs6000_reg_names
[REGNO (scratch_or_premodify
)],
13856 GET_MODE_NAME (mode
));
13859 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
13860 addr
= scratch_or_premodify
;
13861 scratch_or_premodify
= scratch
;
13865 /* Float/Altivec registers can only handle reg+reg addressing. Move
13866 other addresses into a scratch register. */
13871 /* With float regs, we need to handle the AND ourselves, since we can't
13872 use the Altivec instruction with an implicit AND -16. Allow scalar
13873 loads to float registers to use reg+offset even if VSX. */
13874 if (GET_CODE (addr
) == AND
13875 && (rclass
!= ALTIVEC_REGS
|| GET_MODE_SIZE (mode
) != 16
13876 || GET_CODE (XEXP (addr
, 1)) != CONST_INT
13877 || INTVAL (XEXP (addr
, 1)) != -16
13878 || !VECTOR_MEM_ALTIVEC_P (mode
)))
13880 and_op2
= XEXP (addr
, 1);
13881 addr
= XEXP (addr
, 0);
13884 /* If we aren't using a VSX load, save the PRE_MODIFY register and use it
13885 as the address later. */
13886 if (GET_CODE (addr
) == PRE_MODIFY
13887 && (!VECTOR_MEM_VSX_P (mode
)
13888 || and_op2
!= NULL_RTX
13889 || !legitimate_indexed_address_p (XEXP (addr
, 1), false)))
13891 scratch_or_premodify
= XEXP (addr
, 0);
13892 gcc_assert (legitimate_indirect_address_p (scratch_or_premodify
,
13894 gcc_assert (GET_CODE (XEXP (addr
, 1)) == PLUS
);
13895 addr
= XEXP (addr
, 1);
13898 if (legitimate_indirect_address_p (addr
, false) /* reg */
13899 || legitimate_indexed_address_p (addr
, false) /* reg+reg */
13900 || GET_CODE (addr
) == PRE_MODIFY
/* VSX pre-modify */
13901 || (GET_CODE (addr
) == AND
/* Altivec memory */
13902 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
13903 && INTVAL (XEXP (addr
, 1)) == -16
13904 && VECTOR_MEM_ALTIVEC_P (mode
))
13905 || (rclass
== FLOAT_REGS
/* legacy float mem */
13906 && GET_MODE_SIZE (mode
) == 8
13907 && and_op2
== NULL_RTX
13908 && scratch_or_premodify
== scratch
13909 && rs6000_legitimate_offset_address_p (mode
, addr
, false)))
13912 else if (GET_CODE (addr
) == PLUS
)
13914 addr_op1
= XEXP (addr
, 0);
13915 addr_op2
= XEXP (addr
, 1);
13916 gcc_assert (REG_P (addr_op1
));
13918 if (TARGET_DEBUG_ADDR
)
13920 fprintf (stderr
, "\nMove plus addr to register %s, mode = %s: ",
13921 rs6000_reg_names
[REGNO (scratch
)], GET_MODE_NAME (mode
));
13922 debug_rtx (addr_op2
);
13924 rs6000_emit_move (scratch
, addr_op2
, Pmode
);
13925 emit_insn (gen_rtx_SET (VOIDmode
,
13926 scratch_or_premodify
,
13927 gen_rtx_PLUS (Pmode
,
13930 addr
= scratch_or_premodify
;
13931 scratch_or_premodify
= scratch
;
13934 else if (GET_CODE (addr
) == SYMBOL_REF
|| GET_CODE (addr
) == CONST
13935 || GET_CODE (addr
) == CONST_INT
|| REG_P (addr
))
13937 if (TARGET_DEBUG_ADDR
)
13939 fprintf (stderr
, "\nMove addr to register %s, mode = %s: ",
13940 rs6000_reg_names
[REGNO (scratch_or_premodify
)],
13941 GET_MODE_NAME (mode
));
13945 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
13946 addr
= scratch_or_premodify
;
13947 scratch_or_premodify
= scratch
;
13951 gcc_unreachable ();
13956 gcc_unreachable ();
13959 /* If the original address involved a pre-modify that we couldn't use the VSX
13960 memory instruction with update, and we haven't taken care of already,
13961 store the address in the pre-modify register and use that as the
13963 if (scratch_or_premodify
!= scratch
&& scratch_or_premodify
!= addr
)
13965 emit_insn (gen_rtx_SET (VOIDmode
, scratch_or_premodify
, addr
));
13966 addr
= scratch_or_premodify
;
13969 /* If the original address involved an AND -16 and we couldn't use an ALTIVEC
13970 memory instruction, recreate the AND now, including the clobber which is
13971 generated by the general ANDSI3/ANDDI3 patterns for the
13972 andi. instruction. */
13973 if (and_op2
!= NULL_RTX
)
13975 if (! legitimate_indirect_address_p (addr
, false))
13977 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, addr
));
13981 if (TARGET_DEBUG_ADDR
)
13983 fprintf (stderr
, "\nAnd addr to register %s, mode = %s: ",
13984 rs6000_reg_names
[REGNO (scratch
)], GET_MODE_NAME (mode
));
13985 debug_rtx (and_op2
);
13988 and_rtx
= gen_rtx_SET (VOIDmode
,
13990 gen_rtx_AND (Pmode
,
13994 cc_clobber
= gen_rtx_CLOBBER (CCmode
, gen_rtx_SCRATCH (CCmode
));
13995 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
13996 gen_rtvec (2, and_rtx
, cc_clobber
)));
14000 /* Adjust the address if it changed. */
14001 if (addr
!= XEXP (mem
, 0))
14003 mem
= change_address (mem
, mode
, addr
);
14004 if (TARGET_DEBUG_ADDR
)
14005 fprintf (stderr
, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
14008 /* Now create the move. */
14010 emit_insn (gen_rtx_SET (VOIDmode
, mem
, reg
));
14012 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
14017 /* Convert reloads involving 64-bit gprs and misaligned offset
14018 addressing to use indirect addressing. */
14021 rs6000_secondary_reload_ppc64 (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
14023 int regno
= true_regnum (reg
);
14024 enum reg_class rclass
;
14026 rtx scratch_or_premodify
= scratch
;
14028 if (TARGET_DEBUG_ADDR
)
14030 fprintf (stderr
, "\nrs6000_secondary_reload_ppc64, type = %s\n",
14031 store_p
? "store" : "load");
14032 fprintf (stderr
, "reg:\n");
14034 fprintf (stderr
, "mem:\n");
14036 fprintf (stderr
, "scratch:\n");
14037 debug_rtx (scratch
);
14040 gcc_assert (regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
);
14041 gcc_assert (GET_CODE (mem
) == MEM
);
14042 rclass
= REGNO_REG_CLASS (regno
);
14043 gcc_assert (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
);
14044 addr
= XEXP (mem
, 0);
14046 if (GET_CODE (addr
) == PRE_MODIFY
)
14048 scratch_or_premodify
= XEXP (addr
, 0);
14049 gcc_assert (REG_P (scratch_or_premodify
));
14050 addr
= XEXP (addr
, 1);
14052 gcc_assert (GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
);
14054 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
14056 mem
= replace_equiv_address_nv (mem
, scratch_or_premodify
);
14058 /* Now create the move. */
14060 emit_insn (gen_rtx_SET (VOIDmode
, mem
, reg
));
14062 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
14067 /* Allocate a 64-bit stack slot to be used for copying SDmode
14068 values through if this function has any SDmode references. */
14071 rs6000_alloc_sdmode_stack_slot (void)
14075 gimple_stmt_iterator gsi
;
14077 gcc_assert (cfun
->machine
->sdmode_stack_slot
== NULL_RTX
);
14080 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
14082 tree ret
= walk_gimple_op (gsi_stmt (gsi
), rs6000_check_sdmode
, NULL
);
14085 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
14086 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
14092 /* Check for any SDmode parameters of the function. */
14093 for (t
= DECL_ARGUMENTS (cfun
->decl
); t
; t
= DECL_CHAIN (t
))
14095 if (TREE_TYPE (t
) == error_mark_node
)
14098 if (TYPE_MODE (TREE_TYPE (t
)) == SDmode
14099 || TYPE_MODE (DECL_ARG_TYPE (t
)) == SDmode
)
14101 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
14102 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
14110 rs6000_instantiate_decls (void)
14112 if (cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
14113 instantiate_decl_rtl (cfun
->machine
->sdmode_stack_slot
);
14116 /* Given an rtx X being reloaded into a reg required to be
14117 in class CLASS, return the class of reg to actually use.
14118 In general this is just CLASS; but on some machines
14119 in some cases it is preferable to use a more restrictive class.
14121 On the RS/6000, we have to return NO_REGS when we want to reload a
14122 floating-point CONST_DOUBLE to force it to be copied to memory.
14124 We also don't want to reload integer values into floating-point
14125 registers if we can at all help it. In fact, this can
14126 cause reload to die, if it tries to generate a reload of CTR
14127 into a FP register and discovers it doesn't have the memory location
14130 ??? Would it be a good idea to have reload do the converse, that is
14131 try to reload floating modes into FP registers if possible?
14134 static enum reg_class
14135 rs6000_preferred_reload_class (rtx x
, enum reg_class rclass
)
14137 enum machine_mode mode
= GET_MODE (x
);
14139 if (VECTOR_UNIT_VSX_P (mode
)
14140 && x
== CONST0_RTX (mode
) && VSX_REG_CLASS_P (rclass
))
14143 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
14144 && (rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
14145 && easy_vector_constant (x
, mode
))
14146 return ALTIVEC_REGS
;
14148 if (CONSTANT_P (x
) && reg_classes_intersect_p (rclass
, FLOAT_REGS
))
14151 if (GET_MODE_CLASS (mode
) == MODE_INT
&& rclass
== NON_SPECIAL_REGS
)
14152 return GENERAL_REGS
;
14154 /* For VSX, prefer the traditional registers for 64-bit values because we can
14155 use the non-VSX loads. Prefer the Altivec registers if Altivec is
14156 handling the vector operations (i.e. V16QI, V8HI, and V4SI), or if we
14157 prefer Altivec loads.. */
14158 if (rclass
== VSX_REGS
)
14160 if (GET_MODE_SIZE (mode
) <= 8)
14163 if (VECTOR_UNIT_ALTIVEC_P (mode
) || VECTOR_MEM_ALTIVEC_P (mode
))
14164 return ALTIVEC_REGS
;
14172 /* Debug version of rs6000_preferred_reload_class. */
14173 static enum reg_class
14174 rs6000_debug_preferred_reload_class (rtx x
, enum reg_class rclass
)
14176 enum reg_class ret
= rs6000_preferred_reload_class (x
, rclass
);
14179 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
14181 reg_class_names
[ret
], reg_class_names
[rclass
],
14182 GET_MODE_NAME (GET_MODE (x
)));
14188 /* If we are copying between FP or AltiVec registers and anything else, we need
14189 a memory location. The exception is when we are targeting ppc64 and the
14190 move to/from fpr to gpr instructions are available. Also, under VSX, you
14191 can copy vector registers from the FP register set to the Altivec register
14192 set and vice versa. */
14195 rs6000_secondary_memory_needed (enum reg_class class1
,
14196 enum reg_class class2
,
14197 enum machine_mode mode
)
14199 if (class1
== class2
)
14202 /* Under VSX, there are 3 register classes that values could be in (VSX_REGS,
14203 ALTIVEC_REGS, and FLOAT_REGS). We don't need to use memory to copy
14204 between these classes. But we need memory for other things that can go in
14205 FLOAT_REGS like SFmode. */
14207 && (VECTOR_MEM_VSX_P (mode
) || VECTOR_UNIT_VSX_P (mode
))
14208 && (class1
== VSX_REGS
|| class1
== ALTIVEC_REGS
14209 || class1
== FLOAT_REGS
))
14210 return (class2
!= VSX_REGS
&& class2
!= ALTIVEC_REGS
14211 && class2
!= FLOAT_REGS
);
14213 if (class1
== VSX_REGS
|| class2
== VSX_REGS
)
14216 if (class1
== FLOAT_REGS
14217 && (!TARGET_MFPGPR
|| !TARGET_POWERPC64
14218 || ((mode
!= DFmode
)
14219 && (mode
!= DDmode
)
14220 && (mode
!= DImode
))))
14223 if (class2
== FLOAT_REGS
14224 && (!TARGET_MFPGPR
|| !TARGET_POWERPC64
14225 || ((mode
!= DFmode
)
14226 && (mode
!= DDmode
)
14227 && (mode
!= DImode
))))
14230 if (class1
== ALTIVEC_REGS
|| class2
== ALTIVEC_REGS
)
14236 /* Debug version of rs6000_secondary_memory_needed. */
14238 rs6000_debug_secondary_memory_needed (enum reg_class class1
,
14239 enum reg_class class2
,
14240 enum machine_mode mode
)
14242 bool ret
= rs6000_secondary_memory_needed (class1
, class2
, mode
);
14245 "rs6000_secondary_memory_needed, return: %s, class1 = %s, "
14246 "class2 = %s, mode = %s\n",
14247 ret
? "true" : "false", reg_class_names
[class1
],
14248 reg_class_names
[class2
], GET_MODE_NAME (mode
));
14253 /* Return the register class of a scratch register needed to copy IN into
14254 or out of a register in RCLASS in MODE. If it can be done directly,
14255 NO_REGS is returned. */
14257 static enum reg_class
14258 rs6000_secondary_reload_class (enum reg_class rclass
, enum machine_mode mode
,
14263 if (TARGET_ELF
|| (DEFAULT_ABI
== ABI_DARWIN
14265 && MACHOPIC_INDIRECT
14269 /* We cannot copy a symbolic operand directly into anything
14270 other than BASE_REGS for TARGET_ELF. So indicate that a
14271 register from BASE_REGS is needed as an intermediate
14274 On Darwin, pic addresses require a load from memory, which
14275 needs a base register. */
14276 if (rclass
!= BASE_REGS
14277 && (GET_CODE (in
) == SYMBOL_REF
14278 || GET_CODE (in
) == HIGH
14279 || GET_CODE (in
) == LABEL_REF
14280 || GET_CODE (in
) == CONST
))
14284 if (GET_CODE (in
) == REG
)
14286 regno
= REGNO (in
);
14287 if (regno
>= FIRST_PSEUDO_REGISTER
)
14289 regno
= true_regnum (in
);
14290 if (regno
>= FIRST_PSEUDO_REGISTER
)
14294 else if (GET_CODE (in
) == SUBREG
)
14296 regno
= true_regnum (in
);
14297 if (regno
>= FIRST_PSEUDO_REGISTER
)
14303 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
14305 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
14306 || (regno
>= 0 && INT_REGNO_P (regno
)))
14309 /* Constants, memory, and FP registers can go into FP registers. */
14310 if ((regno
== -1 || FP_REGNO_P (regno
))
14311 && (rclass
== FLOAT_REGS
|| rclass
== NON_SPECIAL_REGS
))
14312 return (mode
!= SDmode
) ? NO_REGS
: GENERAL_REGS
;
14314 /* Memory, and FP/altivec registers can go into fp/altivec registers under
14317 && (regno
== -1 || VSX_REGNO_P (regno
))
14318 && VSX_REG_CLASS_P (rclass
))
14321 /* Memory, and AltiVec registers can go into AltiVec registers. */
14322 if ((regno
== -1 || ALTIVEC_REGNO_P (regno
))
14323 && rclass
== ALTIVEC_REGS
)
14326 /* We can copy among the CR registers. */
14327 if ((rclass
== CR_REGS
|| rclass
== CR0_REGS
)
14328 && regno
>= 0 && CR_REGNO_P (regno
))
14331 /* Otherwise, we need GENERAL_REGS. */
14332 return GENERAL_REGS
;
14335 /* Debug version of rs6000_secondary_reload_class. */
14336 static enum reg_class
14337 rs6000_debug_secondary_reload_class (enum reg_class rclass
,
14338 enum machine_mode mode
, rtx in
)
14340 enum reg_class ret
= rs6000_secondary_reload_class (rclass
, mode
, in
);
14342 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
14343 "mode = %s, input rtx:\n",
14344 reg_class_names
[ret
], reg_class_names
[rclass
],
14345 GET_MODE_NAME (mode
));
14351 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
14354 rs6000_cannot_change_mode_class (enum machine_mode from
,
14355 enum machine_mode to
,
14356 enum reg_class rclass
)
14358 unsigned from_size
= GET_MODE_SIZE (from
);
14359 unsigned to_size
= GET_MODE_SIZE (to
);
14361 if (from_size
!= to_size
)
14363 enum reg_class xclass
= (TARGET_VSX
) ? VSX_REGS
: FLOAT_REGS
;
14364 return ((from_size
< 8 || to_size
< 8 || TARGET_IEEEQUAD
)
14365 && reg_classes_intersect_p (xclass
, rclass
));
14368 if (TARGET_E500_DOUBLE
14369 && ((((to
) == DFmode
) + ((from
) == DFmode
)) == 1
14370 || (((to
) == TFmode
) + ((from
) == TFmode
)) == 1
14371 || (((to
) == DDmode
) + ((from
) == DDmode
)) == 1
14372 || (((to
) == TDmode
) + ((from
) == TDmode
)) == 1
14373 || (((to
) == DImode
) + ((from
) == DImode
)) == 1))
14376 /* Since the VSX register set includes traditional floating point registers
14377 and altivec registers, just check for the size being different instead of
14378 trying to check whether the modes are vector modes. Otherwise it won't
14379 allow say DF and DI to change classes. */
14380 if (TARGET_VSX
&& VSX_REG_CLASS_P (rclass
))
14381 return (from_size
!= 8 && from_size
!= 16);
14383 if (TARGET_ALTIVEC
&& rclass
== ALTIVEC_REGS
14384 && (ALTIVEC_VECTOR_MODE (from
) + ALTIVEC_VECTOR_MODE (to
)) == 1)
14387 if (TARGET_SPE
&& (SPE_VECTOR_MODE (from
) + SPE_VECTOR_MODE (to
)) == 1
14388 && reg_classes_intersect_p (GENERAL_REGS
, rclass
))
14394 /* Debug version of rs6000_cannot_change_mode_class. */
14396 rs6000_debug_cannot_change_mode_class (enum machine_mode from
,
14397 enum machine_mode to
,
14398 enum reg_class rclass
)
14400 bool ret
= rs6000_cannot_change_mode_class (from
, to
, rclass
);
14403 "rs6000_cannot_change_mode_class, return %s, from = %s, "
14404 "to = %s, rclass = %s\n",
14405 ret
? "true" : "false",
14406 GET_MODE_NAME (from
), GET_MODE_NAME (to
),
14407 reg_class_names
[rclass
]);
14412 /* Given a comparison operation, return the bit number in CCR to test. We
14413 know this is a valid comparison.
14415 SCC_P is 1 if this is for an scc. That means that %D will have been
14416 used instead of %C, so the bits will be in different places.
14418 Return -1 if OP isn't a valid comparison for some reason. */
14421 ccr_bit (rtx op
, int scc_p
)
14423 enum rtx_code code
= GET_CODE (op
);
14424 enum machine_mode cc_mode
;
14429 if (!COMPARISON_P (op
))
14432 reg
= XEXP (op
, 0);
14434 gcc_assert (GET_CODE (reg
) == REG
&& CR_REGNO_P (REGNO (reg
)));
14436 cc_mode
= GET_MODE (reg
);
14437 cc_regnum
= REGNO (reg
);
14438 base_bit
= 4 * (cc_regnum
- CR0_REGNO
);
14440 validate_condition_mode (code
, cc_mode
);
14442 /* When generating a sCOND operation, only positive conditions are
14445 || code
== EQ
|| code
== GT
|| code
== LT
|| code
== UNORDERED
14446 || code
== GTU
|| code
== LTU
);
14451 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
14453 return base_bit
+ 2;
14454 case GT
: case GTU
: case UNLE
:
14455 return base_bit
+ 1;
14456 case LT
: case LTU
: case UNGE
:
14458 case ORDERED
: case UNORDERED
:
14459 return base_bit
+ 3;
14462 /* If scc, we will have done a cror to put the bit in the
14463 unordered position. So test that bit. For integer, this is ! LT
14464 unless this is an scc insn. */
14465 return scc_p
? base_bit
+ 3 : base_bit
;
14468 return scc_p
? base_bit
+ 3 : base_bit
+ 1;
14471 gcc_unreachable ();
14475 /* Return the GOT register. */
14478 rs6000_got_register (rtx value ATTRIBUTE_UNUSED
)
14480 /* The second flow pass currently (June 1999) can't update
14481 regs_ever_live without disturbing other parts of the compiler, so
14482 update it here to make the prolog/epilogue code happy. */
14483 if (!can_create_pseudo_p ()
14484 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
14485 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM
, true);
14487 crtl
->uses_pic_offset_table
= 1;
14489 return pic_offset_table_rtx
;
14492 static rs6000_stack_t stack_info
;
14494 /* Function to init struct machine_function.
14495 This will be called, via a pointer variable,
14496 from push_function_context. */
14498 static struct machine_function
*
14499 rs6000_init_machine_status (void)
14501 stack_info
.reload_completed
= 0;
14502 return ggc_alloc_cleared_machine_function ();
14505 /* These macros test for integers and extract the low-order bits. */
14507 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
14508 && GET_MODE (X) == VOIDmode)
14510 #define INT_LOWPART(X) \
14511 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
14514 extract_MB (rtx op
)
14517 unsigned long val
= INT_LOWPART (op
);
14519 /* If the high bit is zero, the value is the first 1 bit we find
14521 if ((val
& 0x80000000) == 0)
14523 gcc_assert (val
& 0xffffffff);
14526 while (((val
<<= 1) & 0x80000000) == 0)
14531 /* If the high bit is set and the low bit is not, or the mask is all
14532 1's, the value is zero. */
14533 if ((val
& 1) == 0 || (val
& 0xffffffff) == 0xffffffff)
14536 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
14539 while (((val
>>= 1) & 1) != 0)
14546 extract_ME (rtx op
)
14549 unsigned long val
= INT_LOWPART (op
);
14551 /* If the low bit is zero, the value is the first 1 bit we find from
14553 if ((val
& 1) == 0)
14555 gcc_assert (val
& 0xffffffff);
14558 while (((val
>>= 1) & 1) == 0)
14564 /* If the low bit is set and the high bit is not, or the mask is all
14565 1's, the value is 31. */
14566 if ((val
& 0x80000000) == 0 || (val
& 0xffffffff) == 0xffffffff)
14569 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
14572 while (((val
<<= 1) & 0x80000000) != 0)
14578 /* Locate some local-dynamic symbol still in use by this function
14579 so that we can print its name in some tls_ld pattern. */
14581 static const char *
14582 rs6000_get_some_local_dynamic_name (void)
14586 if (cfun
->machine
->some_ld_name
)
14587 return cfun
->machine
->some_ld_name
;
14589 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
14591 && for_each_rtx (&PATTERN (insn
),
14592 rs6000_get_some_local_dynamic_name_1
, 0))
14593 return cfun
->machine
->some_ld_name
;
14595 gcc_unreachable ();
14598 /* Helper function for rs6000_get_some_local_dynamic_name. */
14601 rs6000_get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
14605 if (GET_CODE (x
) == SYMBOL_REF
)
14607 const char *str
= XSTR (x
, 0);
14608 if (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
14610 cfun
->machine
->some_ld_name
= str
;
14618 /* Write out a function code label. */
14621 rs6000_output_function_entry (FILE *file
, const char *fname
)
14623 if (fname
[0] != '.')
14625 switch (DEFAULT_ABI
)
14628 gcc_unreachable ();
14634 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "L.");
14643 RS6000_OUTPUT_BASENAME (file
, fname
);
14646 /* Print an operand. Recognize special options, documented below. */
14649 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
14650 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
14652 #define SMALL_DATA_RELOC "sda21"
14653 #define SMALL_DATA_REG 0
14657 print_operand (FILE *file
, rtx x
, int code
)
14661 unsigned HOST_WIDE_INT uval
;
14666 /* Write out an instruction after the call which may be replaced
14667 with glue code by the loader. This depends on the AIX version. */
14668 asm_fprintf (file
, RS6000_CALL_GLUE
);
14671 /* %a is output_address. */
14674 /* If X is a constant integer whose low-order 5 bits are zero,
14675 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
14676 in the AIX assembler where "sri" with a zero shift count
14677 writes a trash instruction. */
14678 if (GET_CODE (x
) == CONST_INT
&& (INTVAL (x
) & 31) == 0)
14685 /* If constant, low-order 16 bits of constant, unsigned.
14686 Otherwise, write normally. */
14688 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 0xffff);
14690 print_operand (file
, x
, 0);
14694 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
14695 for 64-bit mask direction. */
14696 putc (((INT_LOWPART (x
) & 1) == 0 ? 'r' : 'l'), file
);
14699 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
14703 /* X is a CR register. Print the number of the GT bit of the CR. */
14704 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
14705 output_operand_lossage ("invalid %%c value");
14707 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 1);
14711 /* Like 'J' but get to the GT bit only. */
14712 gcc_assert (GET_CODE (x
) == REG
);
14714 /* Bit 1 is GT bit. */
14715 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 1;
14717 /* Add one for shift count in rlinm for scc. */
14718 fprintf (file
, "%d", i
+ 1);
14722 /* X is a CR register. Print the number of the EQ bit of the CR */
14723 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
14724 output_operand_lossage ("invalid %%E value");
14726 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 2);
14730 /* X is a CR register. Print the shift count needed to move it
14731 to the high-order four bits. */
14732 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
14733 output_operand_lossage ("invalid %%f value");
14735 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
));
14739 /* Similar, but print the count for the rotate in the opposite
14741 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
14742 output_operand_lossage ("invalid %%F value");
14744 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - CR0_REGNO
));
14748 /* X is a constant integer. If it is negative, print "m",
14749 otherwise print "z". This is to make an aze or ame insn. */
14750 if (GET_CODE (x
) != CONST_INT
)
14751 output_operand_lossage ("invalid %%G value");
14752 else if (INTVAL (x
) >= 0)
14759 /* If constant, output low-order five bits. Otherwise, write
14762 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 31);
14764 print_operand (file
, x
, 0);
14768 /* If constant, output low-order six bits. Otherwise, write
14771 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 63);
14773 print_operand (file
, x
, 0);
14777 /* Print `i' if this is a constant, else nothing. */
14783 /* Write the bit number in CCR for jump. */
14784 i
= ccr_bit (x
, 0);
14786 output_operand_lossage ("invalid %%j code");
14788 fprintf (file
, "%d", i
);
14792 /* Similar, but add one for shift count in rlinm for scc and pass
14793 scc flag to `ccr_bit'. */
14794 i
= ccr_bit (x
, 1);
14796 output_operand_lossage ("invalid %%J code");
14798 /* If we want bit 31, write a shift count of zero, not 32. */
14799 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
14803 /* X must be a constant. Write the 1's complement of the
14806 output_operand_lossage ("invalid %%k value");
14808 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INT_LOWPART (x
));
14812 /* X must be a symbolic constant on ELF. Write an
14813 expression suitable for an 'addi' that adds in the low 16
14814 bits of the MEM. */
14815 if (GET_CODE (x
) == CONST
)
14817 if (GET_CODE (XEXP (x
, 0)) != PLUS
14818 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
14819 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
14820 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
14821 output_operand_lossage ("invalid %%K value");
14823 print_operand_address (file
, x
);
14824 fputs ("@l", file
);
14827 /* %l is output_asm_label. */
14830 /* Write second word of DImode or DFmode reference. Works on register
14831 or non-indexed memory only. */
14832 if (GET_CODE (x
) == REG
)
14833 fputs (reg_names
[REGNO (x
) + 1], file
);
14834 else if (GET_CODE (x
) == MEM
)
14836 /* Handle possible auto-increment. Since it is pre-increment and
14837 we have already done it, we can just use an offset of word. */
14838 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
14839 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
14840 output_address (plus_constant (XEXP (XEXP (x
, 0), 0),
14842 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
14843 output_address (plus_constant (XEXP (XEXP (x
, 0), 0),
14846 output_address (XEXP (adjust_address_nv (x
, SImode
,
14850 if (small_data_operand (x
, GET_MODE (x
)))
14851 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
14852 reg_names
[SMALL_DATA_REG
]);
14857 /* MB value for a mask operand. */
14858 if (! mask_operand (x
, SImode
))
14859 output_operand_lossage ("invalid %%m value");
14861 fprintf (file
, "%d", extract_MB (x
));
14865 /* ME value for a mask operand. */
14866 if (! mask_operand (x
, SImode
))
14867 output_operand_lossage ("invalid %%M value");
14869 fprintf (file
, "%d", extract_ME (x
));
14872 /* %n outputs the negative of its operand. */
14875 /* Write the number of elements in the vector times 4. */
14876 if (GET_CODE (x
) != PARALLEL
)
14877 output_operand_lossage ("invalid %%N value");
14879 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
14883 /* Similar, but subtract 1 first. */
14884 if (GET_CODE (x
) != PARALLEL
)
14885 output_operand_lossage ("invalid %%O value");
14887 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
14891 /* X is a CONST_INT that is a power of two. Output the logarithm. */
14893 || INT_LOWPART (x
) < 0
14894 || (i
= exact_log2 (INT_LOWPART (x
))) < 0)
14895 output_operand_lossage ("invalid %%p value");
14897 fprintf (file
, "%d", i
);
14901 /* The operand must be an indirect memory reference. The result
14902 is the register name. */
14903 if (GET_CODE (x
) != MEM
|| GET_CODE (XEXP (x
, 0)) != REG
14904 || REGNO (XEXP (x
, 0)) >= 32)
14905 output_operand_lossage ("invalid %%P value");
14907 fputs (reg_names
[REGNO (XEXP (x
, 0))], file
);
14911 /* This outputs the logical code corresponding to a boolean
14912 expression. The expression may have one or both operands
14913 negated (if one, only the first one). For condition register
14914 logical operations, it will also treat the negated
14915 CR codes as NOTs, but not handle NOTs of them. */
14917 const char *const *t
= 0;
14919 enum rtx_code code
= GET_CODE (x
);
14920 static const char * const tbl
[3][3] = {
14921 { "and", "andc", "nor" },
14922 { "or", "orc", "nand" },
14923 { "xor", "eqv", "xor" } };
14927 else if (code
== IOR
)
14929 else if (code
== XOR
)
14932 output_operand_lossage ("invalid %%q value");
14934 if (GET_CODE (XEXP (x
, 0)) != NOT
)
14938 if (GET_CODE (XEXP (x
, 1)) == NOT
)
14956 /* X is a CR register. Print the mask for `mtcrf'. */
14957 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
14958 output_operand_lossage ("invalid %%R value");
14960 fprintf (file
, "%d", 128 >> (REGNO (x
) - CR0_REGNO
));
14964 /* Low 5 bits of 32 - value */
14966 output_operand_lossage ("invalid %%s value");
14968 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (32 - INT_LOWPART (x
)) & 31);
14972 /* PowerPC64 mask position. All 0's is excluded.
14973 CONST_INT 32-bit mask is considered sign-extended so any
14974 transition must occur within the CONST_INT, not on the boundary. */
14975 if (! mask64_operand (x
, DImode
))
14976 output_operand_lossage ("invalid %%S value");
14978 uval
= INT_LOWPART (x
);
14980 if (uval
& 1) /* Clear Left */
14982 #if HOST_BITS_PER_WIDE_INT > 64
14983 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
14987 else /* Clear Right */
14990 #if HOST_BITS_PER_WIDE_INT > 64
14991 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
14997 gcc_assert (i
>= 0);
14998 fprintf (file
, "%d", i
);
15002 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
15003 gcc_assert (GET_CODE (x
) == REG
&& GET_MODE (x
) == CCmode
);
15005 /* Bit 3 is OV bit. */
15006 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 3;
15008 /* If we want bit 31, write a shift count of zero, not 32. */
15009 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
15013 /* Print the symbolic name of a branch target register. */
15014 if (GET_CODE (x
) != REG
|| (REGNO (x
) != LR_REGNO
15015 && REGNO (x
) != CTR_REGNO
))
15016 output_operand_lossage ("invalid %%T value");
15017 else if (REGNO (x
) == LR_REGNO
)
15018 fputs (TARGET_NEW_MNEMONICS
? "lr" : "r", file
);
15020 fputs ("ctr", file
);
15024 /* High-order 16 bits of constant for use in unsigned operand. */
15026 output_operand_lossage ("invalid %%u value");
15028 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
15029 (INT_LOWPART (x
) >> 16) & 0xffff);
15033 /* High-order 16 bits of constant for use in signed operand. */
15035 output_operand_lossage ("invalid %%v value");
15037 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
15038 (INT_LOWPART (x
) >> 16) & 0xffff);
15042 /* Print `u' if this has an auto-increment or auto-decrement. */
15043 if (GET_CODE (x
) == MEM
15044 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
15045 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
15046 || GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
))
15051 /* Print the trap code for this operand. */
15052 switch (GET_CODE (x
))
15055 fputs ("eq", file
); /* 4 */
15058 fputs ("ne", file
); /* 24 */
15061 fputs ("lt", file
); /* 16 */
15064 fputs ("le", file
); /* 20 */
15067 fputs ("gt", file
); /* 8 */
15070 fputs ("ge", file
); /* 12 */
15073 fputs ("llt", file
); /* 2 */
15076 fputs ("lle", file
); /* 6 */
15079 fputs ("lgt", file
); /* 1 */
15082 fputs ("lge", file
); /* 5 */
15085 gcc_unreachable ();
15090 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
15093 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
15094 ((INT_LOWPART (x
) & 0xffff) ^ 0x8000) - 0x8000);
15096 print_operand (file
, x
, 0);
15100 /* MB value for a PowerPC64 rldic operand. */
15101 val
= (GET_CODE (x
) == CONST_INT
15102 ? INTVAL (x
) : CONST_DOUBLE_HIGH (x
));
15107 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
; i
++)
15108 if ((val
<<= 1) < 0)
15111 #if HOST_BITS_PER_WIDE_INT == 32
15112 if (GET_CODE (x
) == CONST_INT
&& i
>= 0)
15113 i
+= 32; /* zero-extend high-part was all 0's */
15114 else if (GET_CODE (x
) == CONST_DOUBLE
&& i
== 32)
15116 val
= CONST_DOUBLE_LOW (x
);
15122 for ( ; i
< 64; i
++)
15123 if ((val
<<= 1) < 0)
15128 fprintf (file
, "%d", i
+ 1);
15132 /* X is a FPR or Altivec register used in a VSX context. */
15133 if (GET_CODE (x
) != REG
|| !VSX_REGNO_P (REGNO (x
)))
15134 output_operand_lossage ("invalid %%x value");
15137 int reg
= REGNO (x
);
15138 int vsx_reg
= (FP_REGNO_P (reg
)
15140 : reg
- FIRST_ALTIVEC_REGNO
+ 32);
15142 #ifdef TARGET_REGNAMES
15143 if (TARGET_REGNAMES
)
15144 fprintf (file
, "%%vs%d", vsx_reg
);
15147 fprintf (file
, "%d", vsx_reg
);
15152 if (GET_CODE (x
) == MEM
15153 && (legitimate_indexed_address_p (XEXP (x
, 0), 0)
15154 || (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
15155 && legitimate_indexed_address_p (XEXP (XEXP (x
, 0), 1), 0))))
15160 /* Like 'L', for third word of TImode */
15161 if (GET_CODE (x
) == REG
)
15162 fputs (reg_names
[REGNO (x
) + 2], file
);
15163 else if (GET_CODE (x
) == MEM
)
15165 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
15166 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
15167 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 8));
15168 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
15169 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 8));
15171 output_address (XEXP (adjust_address_nv (x
, SImode
, 8), 0));
15172 if (small_data_operand (x
, GET_MODE (x
)))
15173 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
15174 reg_names
[SMALL_DATA_REG
]);
15179 /* X is a SYMBOL_REF. Write out the name preceded by a
15180 period and without any trailing data in brackets. Used for function
15181 names. If we are configured for System V (or the embedded ABI) on
15182 the PowerPC, do not emit the period, since those systems do not use
15183 TOCs and the like. */
15184 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
15186 /* Mark the decl as referenced so that cgraph will output the
15188 if (SYMBOL_REF_DECL (x
))
15189 mark_decl_referenced (SYMBOL_REF_DECL (x
));
15191 /* For macho, check to see if we need a stub. */
15194 const char *name
= XSTR (x
, 0);
15196 if (darwin_emit_branch_islands
15197 && MACHOPIC_INDIRECT
15198 && machopic_classify_symbol (x
) == MACHOPIC_UNDEFINED_FUNCTION
)
15199 name
= machopic_indirection_name (x
, /*stub_p=*/true);
15201 assemble_name (file
, name
);
15203 else if (!DOT_SYMBOLS
)
15204 assemble_name (file
, XSTR (x
, 0));
15206 rs6000_output_function_entry (file
, XSTR (x
, 0));
15210 /* Like 'L', for last word of TImode. */
15211 if (GET_CODE (x
) == REG
)
15212 fputs (reg_names
[REGNO (x
) + 3], file
);
15213 else if (GET_CODE (x
) == MEM
)
15215 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
15216 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
15217 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 12));
15218 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
15219 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 12));
15221 output_address (XEXP (adjust_address_nv (x
, SImode
, 12), 0));
15222 if (small_data_operand (x
, GET_MODE (x
)))
15223 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
15224 reg_names
[SMALL_DATA_REG
]);
15228 /* Print AltiVec or SPE memory operand. */
15233 gcc_assert (GET_CODE (x
) == MEM
);
15237 /* Ugly hack because %y is overloaded. */
15238 if ((TARGET_SPE
|| TARGET_E500_DOUBLE
)
15239 && (GET_MODE_SIZE (GET_MODE (x
)) == 8
15240 || GET_MODE (x
) == TFmode
15241 || GET_MODE (x
) == TImode
))
15243 /* Handle [reg]. */
15244 if (GET_CODE (tmp
) == REG
)
15246 fprintf (file
, "0(%s)", reg_names
[REGNO (tmp
)]);
15249 /* Handle [reg+UIMM]. */
15250 else if (GET_CODE (tmp
) == PLUS
&&
15251 GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
15255 gcc_assert (GET_CODE (XEXP (tmp
, 0)) == REG
);
15257 x
= INTVAL (XEXP (tmp
, 1));
15258 fprintf (file
, "%d(%s)", x
, reg_names
[REGNO (XEXP (tmp
, 0))]);
15262 /* Fall through. Must be [reg+reg]. */
15264 if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x
))
15265 && GET_CODE (tmp
) == AND
15266 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
15267 && INTVAL (XEXP (tmp
, 1)) == -16)
15268 tmp
= XEXP (tmp
, 0);
15269 else if (VECTOR_MEM_VSX_P (GET_MODE (x
))
15270 && GET_CODE (tmp
) == PRE_MODIFY
)
15271 tmp
= XEXP (tmp
, 1);
15272 if (GET_CODE (tmp
) == REG
)
15273 fprintf (file
, "0,%s", reg_names
[REGNO (tmp
)]);
15276 if (!GET_CODE (tmp
) == PLUS
15277 || !REG_P (XEXP (tmp
, 0))
15278 || !REG_P (XEXP (tmp
, 1)))
15280 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
15284 if (REGNO (XEXP (tmp
, 0)) == 0)
15285 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 1)) ],
15286 reg_names
[ REGNO (XEXP (tmp
, 0)) ]);
15288 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 0)) ],
15289 reg_names
[ REGNO (XEXP (tmp
, 1)) ]);
15295 if (GET_CODE (x
) == REG
)
15296 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
15297 else if (GET_CODE (x
) == MEM
)
15299 /* We need to handle PRE_INC and PRE_DEC here, since we need to
15300 know the width from the mode. */
15301 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
15302 fprintf (file
, "%d(%s)", GET_MODE_SIZE (GET_MODE (x
)),
15303 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
15304 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
15305 fprintf (file
, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x
)),
15306 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
15307 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
15308 output_address (XEXP (XEXP (x
, 0), 1));
15310 output_address (XEXP (x
, 0));
15314 if (toc_relative_expr_p (x
))
15315 /* This hack along with a corresponding hack in
15316 rs6000_output_addr_const_extra arranges to output addends
15317 where the assembler expects to find them. eg.
15318 (const (plus (unspec [symbol_ref ("x") tocrel]) 4))
15319 without this hack would be output as "x@toc+4". We
15321 output_addr_const (file
, tocrel_base
);
15323 output_addr_const (file
, x
);
15328 assemble_name (file
, rs6000_get_some_local_dynamic_name ());
15332 output_operand_lossage ("invalid %%xn code");
15336 /* Print the address of an operand. */
15339 print_operand_address (FILE *file
, rtx x
)
15341 if (GET_CODE (x
) == REG
)
15342 fprintf (file
, "0(%s)", reg_names
[ REGNO (x
) ]);
15343 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
15344 || GET_CODE (x
) == LABEL_REF
)
15346 output_addr_const (file
, x
);
15347 if (small_data_operand (x
, GET_MODE (x
)))
15348 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
15349 reg_names
[SMALL_DATA_REG
]);
15351 gcc_assert (!TARGET_TOC
);
15353 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == REG
)
15355 gcc_assert (REG_P (XEXP (x
, 0)));
15356 if (REGNO (XEXP (x
, 0)) == 0)
15357 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 1)) ],
15358 reg_names
[ REGNO (XEXP (x
, 0)) ]);
15360 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 0)) ],
15361 reg_names
[ REGNO (XEXP (x
, 1)) ]);
15363 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
15364 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"(%s)",
15365 INTVAL (XEXP (x
, 1)), reg_names
[ REGNO (XEXP (x
, 0)) ]);
15367 else if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == REG
15368 && CONSTANT_P (XEXP (x
, 1)))
15370 fprintf (file
, "lo16(");
15371 output_addr_const (file
, XEXP (x
, 1));
15372 fprintf (file
, ")(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
15375 else if (legitimate_constant_pool_address_p (x
, QImode
, true))
15377 /* This hack along with a corresponding hack in
15378 rs6000_output_addr_const_extra arranges to output addends
15379 where the assembler expects to find them. eg.
15381 . (const (plus (unspec [symbol_ref ("x") tocrel]) 8)))
15382 without this hack would be output as "x@toc+8@l(9)". We
15383 want "x+8@toc@l(9)". */
15384 output_addr_const (file
, tocrel_base
);
15385 if (GET_CODE (x
) == LO_SUM
)
15386 fprintf (file
, "@l(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
15388 fprintf (file
, "(%s)", reg_names
[REGNO (XEXP (x
, 0))]);
15391 else if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == REG
15392 && CONSTANT_P (XEXP (x
, 1)))
15394 output_addr_const (file
, XEXP (x
, 1));
15395 fprintf (file
, "@l(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
15399 gcc_unreachable ();
15402 /* Implement TARGET_OUTPUT_ADDR_CONST_EXTRA. */
15405 rs6000_output_addr_const_extra (FILE *file
, rtx x
)
15407 if (GET_CODE (x
) == UNSPEC
)
15408 switch (XINT (x
, 1))
15410 case UNSPEC_TOCREL
:
15411 gcc_assert (GET_CODE (XVECEXP (x
, 0, 0)) == SYMBOL_REF
);
15412 output_addr_const (file
, XVECEXP (x
, 0, 0));
15413 if (x
== tocrel_base
&& tocrel_offset
!= const0_rtx
)
15415 if (INTVAL (tocrel_offset
) >= 0)
15416 fprintf (file
, "+");
15417 output_addr_const (file
, tocrel_offset
);
15419 if (!TARGET_AIX
|| (TARGET_ELF
&& TARGET_MINIMAL_TOC
))
15422 assemble_name (file
, toc_label_name
);
15424 else if (TARGET_ELF
)
15425 fputs ("@toc", file
);
15429 case UNSPEC_MACHOPIC_OFFSET
:
15430 output_addr_const (file
, XVECEXP (x
, 0, 0));
15432 machopic_output_function_base_name (file
);
15439 /* Target hook for assembling integer objects. The PowerPC version has
15440 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
15441 is defined. It also needs to handle DI-mode objects on 64-bit
15445 rs6000_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
15447 #ifdef RELOCATABLE_NEEDS_FIXUP
15448 /* Special handling for SI values. */
15449 if (RELOCATABLE_NEEDS_FIXUP
&& size
== 4 && aligned_p
)
15451 static int recurse
= 0;
15453 /* For -mrelocatable, we mark all addresses that need to be fixed up in
15454 the .fixup section. Since the TOC section is already relocated, we
15455 don't need to mark it here. We used to skip the text section, but it
15456 should never be valid for relocated addresses to be placed in the text
15458 if (TARGET_RELOCATABLE
15459 && in_section
!= toc_section
15461 && GET_CODE (x
) != CONST_INT
15462 && GET_CODE (x
) != CONST_DOUBLE
15468 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", fixuplabelno
);
15470 ASM_OUTPUT_LABEL (asm_out_file
, buf
);
15471 fprintf (asm_out_file
, "\t.long\t(");
15472 output_addr_const (asm_out_file
, x
);
15473 fprintf (asm_out_file
, ")@fixup\n");
15474 fprintf (asm_out_file
, "\t.section\t\".fixup\",\"aw\"\n");
15475 ASM_OUTPUT_ALIGN (asm_out_file
, 2);
15476 fprintf (asm_out_file
, "\t.long\t");
15477 assemble_name (asm_out_file
, buf
);
15478 fprintf (asm_out_file
, "\n\t.previous\n");
15482 /* Remove initial .'s to turn a -mcall-aixdesc function
15483 address into the address of the descriptor, not the function
15485 else if (GET_CODE (x
) == SYMBOL_REF
15486 && XSTR (x
, 0)[0] == '.'
15487 && DEFAULT_ABI
== ABI_AIX
)
15489 const char *name
= XSTR (x
, 0);
15490 while (*name
== '.')
15493 fprintf (asm_out_file
, "\t.long\t%s\n", name
);
15497 #endif /* RELOCATABLE_NEEDS_FIXUP */
15498 return default_assemble_integer (x
, size
, aligned_p
);
15501 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
15502 /* Emit an assembler directive to set symbol visibility for DECL to
15503 VISIBILITY_TYPE. */
15506 rs6000_assemble_visibility (tree decl
, int vis
)
15508 /* Functions need to have their entry point symbol visibility set as
15509 well as their descriptor symbol visibility. */
15510 if (DEFAULT_ABI
== ABI_AIX
15512 && TREE_CODE (decl
) == FUNCTION_DECL
)
15514 static const char * const visibility_types
[] = {
15515 NULL
, "internal", "hidden", "protected"
15518 const char *name
, *type
;
15520 name
= ((* targetm
.strip_name_encoding
)
15521 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
))));
15522 type
= visibility_types
[vis
];
15524 fprintf (asm_out_file
, "\t.%s\t%s\n", type
, name
);
15525 fprintf (asm_out_file
, "\t.%s\t.%s\n", type
, name
);
15528 default_assemble_visibility (decl
, vis
);
15533 rs6000_reverse_condition (enum machine_mode mode
, enum rtx_code code
)
15535 /* Reversal of FP compares takes care -- an ordered compare
15536 becomes an unordered compare and vice versa. */
15537 if (mode
== CCFPmode
15538 && (!flag_finite_math_only
15539 || code
== UNLT
|| code
== UNLE
|| code
== UNGT
|| code
== UNGE
15540 || code
== UNEQ
|| code
== LTGT
))
15541 return reverse_condition_maybe_unordered (code
);
15543 return reverse_condition (code
);
15546 /* Generate a compare for CODE. Return a brand-new rtx that
15547 represents the result of the compare. */
15550 rs6000_generate_compare (rtx cmp
, enum machine_mode mode
)
15552 enum machine_mode comp_mode
;
15553 rtx compare_result
;
15554 enum rtx_code code
= GET_CODE (cmp
);
15555 rtx op0
= XEXP (cmp
, 0);
15556 rtx op1
= XEXP (cmp
, 1);
15558 if (FLOAT_MODE_P (mode
))
15559 comp_mode
= CCFPmode
;
15560 else if (code
== GTU
|| code
== LTU
15561 || code
== GEU
|| code
== LEU
)
15562 comp_mode
= CCUNSmode
;
15563 else if ((code
== EQ
|| code
== NE
)
15564 && GET_CODE (op0
) == SUBREG
15565 && GET_CODE (op1
) == SUBREG
15566 && SUBREG_PROMOTED_UNSIGNED_P (op0
)
15567 && SUBREG_PROMOTED_UNSIGNED_P (op1
))
15568 /* These are unsigned values, perhaps there will be a later
15569 ordering compare that can be shared with this one.
15570 Unfortunately we cannot detect the signedness of the operands
15571 for non-subregs. */
15572 comp_mode
= CCUNSmode
;
15574 comp_mode
= CCmode
;
15576 /* First, the compare. */
15577 compare_result
= gen_reg_rtx (comp_mode
);
15579 /* E500 FP compare instructions on the GPRs. Yuck! */
15580 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
)
15581 && FLOAT_MODE_P (mode
))
15583 rtx cmp
, or_result
, compare_result2
;
15584 enum machine_mode op_mode
= GET_MODE (op0
);
15586 if (op_mode
== VOIDmode
)
15587 op_mode
= GET_MODE (op1
);
15589 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
15590 This explains the following mess. */
15594 case EQ
: case UNEQ
: case NE
: case LTGT
:
15598 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15599 ? gen_tstsfeq_gpr (compare_result
, op0
, op1
)
15600 : gen_cmpsfeq_gpr (compare_result
, op0
, op1
);
15604 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15605 ? gen_tstdfeq_gpr (compare_result
, op0
, op1
)
15606 : gen_cmpdfeq_gpr (compare_result
, op0
, op1
);
15610 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15611 ? gen_tsttfeq_gpr (compare_result
, op0
, op1
)
15612 : gen_cmptfeq_gpr (compare_result
, op0
, op1
);
15616 gcc_unreachable ();
15620 case GT
: case GTU
: case UNGT
: case UNGE
: case GE
: case GEU
:
15624 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15625 ? gen_tstsfgt_gpr (compare_result
, op0
, op1
)
15626 : gen_cmpsfgt_gpr (compare_result
, op0
, op1
);
15630 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15631 ? gen_tstdfgt_gpr (compare_result
, op0
, op1
)
15632 : gen_cmpdfgt_gpr (compare_result
, op0
, op1
);
15636 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15637 ? gen_tsttfgt_gpr (compare_result
, op0
, op1
)
15638 : gen_cmptfgt_gpr (compare_result
, op0
, op1
);
15642 gcc_unreachable ();
15646 case LT
: case LTU
: case UNLT
: case UNLE
: case LE
: case LEU
:
15650 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15651 ? gen_tstsflt_gpr (compare_result
, op0
, op1
)
15652 : gen_cmpsflt_gpr (compare_result
, op0
, op1
);
15656 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15657 ? gen_tstdflt_gpr (compare_result
, op0
, op1
)
15658 : gen_cmpdflt_gpr (compare_result
, op0
, op1
);
15662 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15663 ? gen_tsttflt_gpr (compare_result
, op0
, op1
)
15664 : gen_cmptflt_gpr (compare_result
, op0
, op1
);
15668 gcc_unreachable ();
15672 gcc_unreachable ();
15675 /* Synthesize LE and GE from LT/GT || EQ. */
15676 if (code
== LE
|| code
== GE
|| code
== LEU
|| code
== GEU
)
15682 case LE
: code
= LT
; break;
15683 case GE
: code
= GT
; break;
15684 case LEU
: code
= LT
; break;
15685 case GEU
: code
= GT
; break;
15686 default: gcc_unreachable ();
15689 compare_result2
= gen_reg_rtx (CCFPmode
);
15695 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15696 ? gen_tstsfeq_gpr (compare_result2
, op0
, op1
)
15697 : gen_cmpsfeq_gpr (compare_result2
, op0
, op1
);
15701 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15702 ? gen_tstdfeq_gpr (compare_result2
, op0
, op1
)
15703 : gen_cmpdfeq_gpr (compare_result2
, op0
, op1
);
15707 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
15708 ? gen_tsttfeq_gpr (compare_result2
, op0
, op1
)
15709 : gen_cmptfeq_gpr (compare_result2
, op0
, op1
);
15713 gcc_unreachable ();
15717 /* OR them together. */
15718 or_result
= gen_reg_rtx (CCFPmode
);
15719 cmp
= gen_e500_cr_ior_compare (or_result
, compare_result
,
15721 compare_result
= or_result
;
15726 if (code
== NE
|| code
== LTGT
)
15736 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
15737 CLOBBERs to match cmptf_internal2 pattern. */
15738 if (comp_mode
== CCFPmode
&& TARGET_XL_COMPAT
15739 && GET_MODE (op0
) == TFmode
15740 && !TARGET_IEEEQUAD
15741 && TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_LONG_DOUBLE_128
)
15742 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
15744 gen_rtx_SET (VOIDmode
,
15746 gen_rtx_COMPARE (comp_mode
, op0
, op1
)),
15747 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
15748 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
15749 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
15750 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
15751 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
15752 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
15753 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
15754 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
15755 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (Pmode
)))));
15756 else if (GET_CODE (op1
) == UNSPEC
15757 && XINT (op1
, 1) == UNSPEC_SP_TEST
)
15759 rtx op1b
= XVECEXP (op1
, 0, 0);
15760 comp_mode
= CCEQmode
;
15761 compare_result
= gen_reg_rtx (CCEQmode
);
15763 emit_insn (gen_stack_protect_testdi (compare_result
, op0
, op1b
));
15765 emit_insn (gen_stack_protect_testsi (compare_result
, op0
, op1b
));
15768 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
15769 gen_rtx_COMPARE (comp_mode
, op0
, op1
)));
15772 /* Some kinds of FP comparisons need an OR operation;
15773 under flag_finite_math_only we don't bother. */
15774 if (FLOAT_MODE_P (mode
)
15775 && !flag_finite_math_only
15776 && !(TARGET_HARD_FLOAT
&& !TARGET_FPRS
)
15777 && (code
== LE
|| code
== GE
15778 || code
== UNEQ
|| code
== LTGT
15779 || code
== UNGT
|| code
== UNLT
))
15781 enum rtx_code or1
, or2
;
15782 rtx or1_rtx
, or2_rtx
, compare2_rtx
;
15783 rtx or_result
= gen_reg_rtx (CCEQmode
);
15787 case LE
: or1
= LT
; or2
= EQ
; break;
15788 case GE
: or1
= GT
; or2
= EQ
; break;
15789 case UNEQ
: or1
= UNORDERED
; or2
= EQ
; break;
15790 case LTGT
: or1
= LT
; or2
= GT
; break;
15791 case UNGT
: or1
= UNORDERED
; or2
= GT
; break;
15792 case UNLT
: or1
= UNORDERED
; or2
= LT
; break;
15793 default: gcc_unreachable ();
15795 validate_condition_mode (or1
, comp_mode
);
15796 validate_condition_mode (or2
, comp_mode
);
15797 or1_rtx
= gen_rtx_fmt_ee (or1
, SImode
, compare_result
, const0_rtx
);
15798 or2_rtx
= gen_rtx_fmt_ee (or2
, SImode
, compare_result
, const0_rtx
);
15799 compare2_rtx
= gen_rtx_COMPARE (CCEQmode
,
15800 gen_rtx_IOR (SImode
, or1_rtx
, or2_rtx
),
15802 emit_insn (gen_rtx_SET (VOIDmode
, or_result
, compare2_rtx
));
15804 compare_result
= or_result
;
15808 validate_condition_mode (code
, GET_MODE (compare_result
));
15810 return gen_rtx_fmt_ee (code
, VOIDmode
, compare_result
, const0_rtx
);
15814 /* Emit the RTL for an sISEL pattern. */
15817 rs6000_emit_sISEL (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx operands
[])
15819 rs6000_emit_int_cmove (operands
[0], operands
[1], const1_rtx
, const0_rtx
);
15823 rs6000_emit_sCOND (enum machine_mode mode
, rtx operands
[])
15826 enum machine_mode op_mode
;
15827 enum rtx_code cond_code
;
15828 rtx result
= operands
[0];
15830 if (TARGET_ISEL
&& (mode
== SImode
|| mode
== DImode
))
15832 rs6000_emit_sISEL (mode
, operands
);
15836 condition_rtx
= rs6000_generate_compare (operands
[1], mode
);
15837 cond_code
= GET_CODE (condition_rtx
);
15839 if (FLOAT_MODE_P (mode
)
15840 && !TARGET_FPRS
&& TARGET_HARD_FLOAT
)
15844 PUT_MODE (condition_rtx
, SImode
);
15845 t
= XEXP (condition_rtx
, 0);
15847 gcc_assert (cond_code
== NE
|| cond_code
== EQ
);
15849 if (cond_code
== NE
)
15850 emit_insn (gen_e500_flip_gt_bit (t
, t
));
15852 emit_insn (gen_move_from_CR_gt_bit (result
, t
));
15856 if (cond_code
== NE
15857 || cond_code
== GE
|| cond_code
== LE
15858 || cond_code
== GEU
|| cond_code
== LEU
15859 || cond_code
== ORDERED
|| cond_code
== UNGE
|| cond_code
== UNLE
)
15861 rtx not_result
= gen_reg_rtx (CCEQmode
);
15862 rtx not_op
, rev_cond_rtx
;
15863 enum machine_mode cc_mode
;
15865 cc_mode
= GET_MODE (XEXP (condition_rtx
, 0));
15867 rev_cond_rtx
= gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode
, cond_code
),
15868 SImode
, XEXP (condition_rtx
, 0), const0_rtx
);
15869 not_op
= gen_rtx_COMPARE (CCEQmode
, rev_cond_rtx
, const0_rtx
);
15870 emit_insn (gen_rtx_SET (VOIDmode
, not_result
, not_op
));
15871 condition_rtx
= gen_rtx_EQ (VOIDmode
, not_result
, const0_rtx
);
15874 op_mode
= GET_MODE (XEXP (operands
[1], 0));
15875 if (op_mode
== VOIDmode
)
15876 op_mode
= GET_MODE (XEXP (operands
[1], 1));
15878 if (TARGET_POWERPC64
&& (op_mode
== DImode
|| FLOAT_MODE_P (mode
)))
15880 PUT_MODE (condition_rtx
, DImode
);
15881 convert_move (result
, condition_rtx
, 0);
15885 PUT_MODE (condition_rtx
, SImode
);
15886 emit_insn (gen_rtx_SET (VOIDmode
, result
, condition_rtx
));
15890 /* Emit a branch of kind CODE to location LOC. */
15893 rs6000_emit_cbranch (enum machine_mode mode
, rtx operands
[])
15895 rtx condition_rtx
, loc_ref
;
15897 condition_rtx
= rs6000_generate_compare (operands
[0], mode
);
15898 loc_ref
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
15899 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
15900 gen_rtx_IF_THEN_ELSE (VOIDmode
, condition_rtx
,
15901 loc_ref
, pc_rtx
)));
15904 /* Return the string to output a conditional branch to LABEL, which is
15905 the operand number of the label, or -1 if the branch is really a
15906 conditional return.
15908 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
15909 condition code register and its mode specifies what kind of
15910 comparison we made.
15912 REVERSED is nonzero if we should reverse the sense of the comparison.
15914 INSN is the insn. */
15917 output_cbranch (rtx op
, const char *label
, int reversed
, rtx insn
)
15919 static char string
[64];
15920 enum rtx_code code
= GET_CODE (op
);
15921 rtx cc_reg
= XEXP (op
, 0);
15922 enum machine_mode mode
= GET_MODE (cc_reg
);
15923 int cc_regno
= REGNO (cc_reg
) - CR0_REGNO
;
15924 int need_longbranch
= label
!= NULL
&& get_attr_length (insn
) == 8;
15925 int really_reversed
= reversed
^ need_longbranch
;
15931 validate_condition_mode (code
, mode
);
15933 /* Work out which way this really branches. We could use
15934 reverse_condition_maybe_unordered here always but this
15935 makes the resulting assembler clearer. */
15936 if (really_reversed
)
15938 /* Reversal of FP compares takes care -- an ordered compare
15939 becomes an unordered compare and vice versa. */
15940 if (mode
== CCFPmode
)
15941 code
= reverse_condition_maybe_unordered (code
);
15943 code
= reverse_condition (code
);
15946 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
) && mode
== CCFPmode
)
15948 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
15953 /* Opposite of GT. */
15962 gcc_unreachable ();
15968 /* Not all of these are actually distinct opcodes, but
15969 we distinguish them for clarity of the resulting assembler. */
15970 case NE
: case LTGT
:
15971 ccode
= "ne"; break;
15972 case EQ
: case UNEQ
:
15973 ccode
= "eq"; break;
15975 ccode
= "ge"; break;
15976 case GT
: case GTU
: case UNGT
:
15977 ccode
= "gt"; break;
15979 ccode
= "le"; break;
15980 case LT
: case LTU
: case UNLT
:
15981 ccode
= "lt"; break;
15982 case UNORDERED
: ccode
= "un"; break;
15983 case ORDERED
: ccode
= "nu"; break;
15984 case UNGE
: ccode
= "nl"; break;
15985 case UNLE
: ccode
= "ng"; break;
15987 gcc_unreachable ();
15990 /* Maybe we have a guess as to how likely the branch is.
15991 The old mnemonics don't have a way to specify this information. */
15993 note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
);
15994 if (note
!= NULL_RTX
)
15996 /* PROB is the difference from 50%. */
15997 int prob
= INTVAL (XEXP (note
, 0)) - REG_BR_PROB_BASE
/ 2;
15999 /* Only hint for highly probable/improbable branches on newer
16000 cpus as static prediction overrides processor dynamic
16001 prediction. For older cpus we may as well always hint, but
16002 assume not taken for branches that are very close to 50% as a
16003 mispredicted taken branch is more expensive than a
16004 mispredicted not-taken branch. */
16005 if (rs6000_always_hint
16006 || (abs (prob
) > REG_BR_PROB_BASE
/ 100 * 48
16007 && br_prob_note_reliable_p (note
)))
16009 if (abs (prob
) > REG_BR_PROB_BASE
/ 20
16010 && ((prob
> 0) ^ need_longbranch
))
16018 s
+= sprintf (s
, "{b%sr|b%slr%s} ", ccode
, ccode
, pred
);
16020 s
+= sprintf (s
, "{b%s|b%s%s} ", ccode
, ccode
, pred
);
16022 /* We need to escape any '%' characters in the reg_names string.
16023 Assume they'd only be the first character.... */
16024 if (reg_names
[cc_regno
+ CR0_REGNO
][0] == '%')
16026 s
+= sprintf (s
, "%s", reg_names
[cc_regno
+ CR0_REGNO
]);
16030 /* If the branch distance was too far, we may have to use an
16031 unconditional branch to go the distance. */
16032 if (need_longbranch
)
16033 s
+= sprintf (s
, ",$+8\n\tb %s", label
);
16035 s
+= sprintf (s
, ",%s", label
);
16041 /* Return the string to flip the GT bit on a CR. */
16043 output_e500_flip_gt_bit (rtx dst
, rtx src
)
16045 static char string
[64];
16048 gcc_assert (GET_CODE (dst
) == REG
&& CR_REGNO_P (REGNO (dst
))
16049 && GET_CODE (src
) == REG
&& CR_REGNO_P (REGNO (src
)));
16052 a
= 4 * (REGNO (dst
) - CR0_REGNO
) + 1;
16053 b
= 4 * (REGNO (src
) - CR0_REGNO
) + 1;
16055 sprintf (string
, "crnot %d,%d", a
, b
);
16059 /* Return insn for VSX or Altivec comparisons. */
16062 rs6000_emit_vector_compare_inner (enum rtx_code code
, rtx op0
, rtx op1
)
16065 enum machine_mode mode
= GET_MODE (op0
);
16073 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
16083 mask
= gen_reg_rtx (mode
);
16084 emit_insn (gen_rtx_SET (VOIDmode
,
16086 gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
16093 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
16094 DMODE is expected destination mode. This is a recursive function. */
16097 rs6000_emit_vector_compare (enum rtx_code rcode
,
16099 enum machine_mode dmode
)
16102 bool swap_operands
= false;
16103 bool try_again
= false;
16105 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode
));
16106 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
16108 /* See if the comparison works as is. */
16109 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
16117 swap_operands
= true;
16122 swap_operands
= true;
16130 /* Invert condition and try again.
16131 e.g., A != B becomes ~(A==B). */
16133 enum rtx_code rev_code
;
16134 enum insn_code nor_code
;
16137 rev_code
= reverse_condition_maybe_unordered (rcode
);
16138 if (rev_code
== UNKNOWN
)
16141 nor_code
= optab_handler (one_cmpl_optab
, dmode
);
16142 if (nor_code
== CODE_FOR_nothing
)
16145 mask2
= rs6000_emit_vector_compare (rev_code
, op0
, op1
, dmode
);
16149 mask
= gen_reg_rtx (dmode
);
16150 emit_insn (GEN_FCN (nor_code
) (mask
, mask2
));
16158 /* Try GT/GTU/LT/LTU OR EQ */
16161 enum insn_code ior_code
;
16162 enum rtx_code new_code
;
16183 gcc_unreachable ();
16186 ior_code
= optab_handler (ior_optab
, dmode
);
16187 if (ior_code
== CODE_FOR_nothing
)
16190 c_rtx
= rs6000_emit_vector_compare (new_code
, op0
, op1
, dmode
);
16194 eq_rtx
= rs6000_emit_vector_compare (EQ
, op0
, op1
, dmode
);
16198 mask
= gen_reg_rtx (dmode
);
16199 emit_insn (GEN_FCN (ior_code
) (mask
, c_rtx
, eq_rtx
));
16217 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
16222 /* You only get two chances. */
16226 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
16227 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
16228 operands for the relation operation COND. */
16231 rs6000_emit_vector_cond_expr (rtx dest
, rtx op_true
, rtx op_false
,
16232 rtx cond
, rtx cc_op0
, rtx cc_op1
)
16234 enum machine_mode dest_mode
= GET_MODE (dest
);
16235 enum machine_mode mask_mode
= GET_MODE (cc_op0
);
16236 enum rtx_code rcode
= GET_CODE (cond
);
16237 enum machine_mode cc_mode
= CCmode
;
16241 bool invert_move
= false;
16243 if (VECTOR_UNIT_NONE_P (dest_mode
))
16246 gcc_assert (GET_MODE_SIZE (dest_mode
) == GET_MODE_SIZE (mask_mode
)
16247 && GET_MODE_NUNITS (dest_mode
) == GET_MODE_NUNITS (mask_mode
));
16251 /* Swap operands if we can, and fall back to doing the operation as
16252 specified, and doing a NOR to invert the test. */
16258 /* Invert condition and try again.
16259 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
16260 invert_move
= true;
16261 rcode
= reverse_condition_maybe_unordered (rcode
);
16262 if (rcode
== UNKNOWN
)
16266 /* Mark unsigned tests with CCUNSmode. */
16271 cc_mode
= CCUNSmode
;
16278 /* Get the vector mask for the given relational operations. */
16279 mask
= rs6000_emit_vector_compare (rcode
, cc_op0
, cc_op1
, mask_mode
);
16287 op_true
= op_false
;
16291 cond2
= gen_rtx_fmt_ee (NE
, cc_mode
, gen_lowpart (dest_mode
, mask
),
16292 CONST0_RTX (dest_mode
));
16293 emit_insn (gen_rtx_SET (VOIDmode
,
16295 gen_rtx_IF_THEN_ELSE (dest_mode
,
16302 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
16303 operands of the last comparison is nonzero/true, FALSE_COND if it
16304 is zero/false. Return 0 if the hardware has no such operation. */
16307 rs6000_emit_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
16309 enum rtx_code code
= GET_CODE (op
);
16310 rtx op0
= XEXP (op
, 0);
16311 rtx op1
= XEXP (op
, 1);
16312 REAL_VALUE_TYPE c1
;
16313 enum machine_mode compare_mode
= GET_MODE (op0
);
16314 enum machine_mode result_mode
= GET_MODE (dest
);
16316 bool is_against_zero
;
16318 /* These modes should always match. */
16319 if (GET_MODE (op1
) != compare_mode
16320 /* In the isel case however, we can use a compare immediate, so
16321 op1 may be a small constant. */
16322 && (!TARGET_ISEL
|| !short_cint_operand (op1
, VOIDmode
)))
16324 if (GET_MODE (true_cond
) != result_mode
)
16326 if (GET_MODE (false_cond
) != result_mode
)
16329 /* First, work out if the hardware can do this at all, or
16330 if it's too slow.... */
16331 if (!FLOAT_MODE_P (compare_mode
))
16334 return rs6000_emit_int_cmove (dest
, op
, true_cond
, false_cond
);
16337 else if (TARGET_HARD_FLOAT
&& !TARGET_FPRS
16338 && SCALAR_FLOAT_MODE_P (compare_mode
))
16341 is_against_zero
= op1
== CONST0_RTX (compare_mode
);
16343 /* A floating-point subtract might overflow, underflow, or produce
16344 an inexact result, thus changing the floating-point flags, so it
16345 can't be generated if we care about that. It's safe if one side
16346 of the construct is zero, since then no subtract will be
16348 if (SCALAR_FLOAT_MODE_P (compare_mode
)
16349 && flag_trapping_math
&& ! is_against_zero
)
16352 /* Eliminate half of the comparisons by switching operands, this
16353 makes the remaining code simpler. */
16354 if (code
== UNLT
|| code
== UNGT
|| code
== UNORDERED
|| code
== NE
16355 || code
== LTGT
|| code
== LT
|| code
== UNLE
)
16357 code
= reverse_condition_maybe_unordered (code
);
16359 true_cond
= false_cond
;
16363 /* UNEQ and LTGT take four instructions for a comparison with zero,
16364 it'll probably be faster to use a branch here too. */
16365 if (code
== UNEQ
&& HONOR_NANS (compare_mode
))
16368 if (GET_CODE (op1
) == CONST_DOUBLE
)
16369 REAL_VALUE_FROM_CONST_DOUBLE (c1
, op1
);
16371 /* We're going to try to implement comparisons by performing
16372 a subtract, then comparing against zero. Unfortunately,
16373 Inf - Inf is NaN which is not zero, and so if we don't
16374 know that the operand is finite and the comparison
16375 would treat EQ different to UNORDERED, we can't do it. */
16376 if (HONOR_INFINITIES (compare_mode
)
16377 && code
!= GT
&& code
!= UNGE
16378 && (GET_CODE (op1
) != CONST_DOUBLE
|| real_isinf (&c1
))
16379 /* Constructs of the form (a OP b ? a : b) are safe. */
16380 && ((! rtx_equal_p (op0
, false_cond
) && ! rtx_equal_p (op1
, false_cond
))
16381 || (! rtx_equal_p (op0
, true_cond
)
16382 && ! rtx_equal_p (op1
, true_cond
))))
16385 /* At this point we know we can use fsel. */
16387 /* Reduce the comparison to a comparison against zero. */
16388 if (! is_against_zero
)
16390 temp
= gen_reg_rtx (compare_mode
);
16391 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
16392 gen_rtx_MINUS (compare_mode
, op0
, op1
)));
16394 op1
= CONST0_RTX (compare_mode
);
16397 /* If we don't care about NaNs we can reduce some of the comparisons
16398 down to faster ones. */
16399 if (! HONOR_NANS (compare_mode
))
16405 true_cond
= false_cond
;
16418 /* Now, reduce everything down to a GE. */
16425 temp
= gen_reg_rtx (compare_mode
);
16426 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
16431 temp
= gen_reg_rtx (compare_mode
);
16432 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_ABS (compare_mode
, op0
)));
16437 temp
= gen_reg_rtx (compare_mode
);
16438 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
16439 gen_rtx_NEG (compare_mode
,
16440 gen_rtx_ABS (compare_mode
, op0
))));
16445 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
16446 temp
= gen_reg_rtx (result_mode
);
16447 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
16448 gen_rtx_IF_THEN_ELSE (result_mode
,
16449 gen_rtx_GE (VOIDmode
,
16451 true_cond
, false_cond
)));
16452 false_cond
= true_cond
;
16455 temp
= gen_reg_rtx (compare_mode
);
16456 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
16461 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
16462 temp
= gen_reg_rtx (result_mode
);
16463 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
16464 gen_rtx_IF_THEN_ELSE (result_mode
,
16465 gen_rtx_GE (VOIDmode
,
16467 true_cond
, false_cond
)));
16468 true_cond
= false_cond
;
16471 temp
= gen_reg_rtx (compare_mode
);
16472 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
16477 gcc_unreachable ();
16480 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
16481 gen_rtx_IF_THEN_ELSE (result_mode
,
16482 gen_rtx_GE (VOIDmode
,
16484 true_cond
, false_cond
)));
16488 /* Same as above, but for ints (isel). */
16491 rs6000_emit_int_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
16493 rtx condition_rtx
, cr
;
16494 enum machine_mode mode
= GET_MODE (dest
);
16495 enum rtx_code cond_code
;
16496 rtx (*isel_func
) (rtx
, rtx
, rtx
, rtx
, rtx
);
16499 if (mode
!= SImode
&& (!TARGET_POWERPC64
|| mode
!= DImode
))
16502 /* We still have to do the compare, because isel doesn't do a
16503 compare, it just looks at the CRx bits set by a previous compare
16505 condition_rtx
= rs6000_generate_compare (op
, mode
);
16506 cond_code
= GET_CODE (condition_rtx
);
16507 cr
= XEXP (condition_rtx
, 0);
16508 signedp
= GET_MODE (cr
) == CCmode
;
16510 isel_func
= (mode
== SImode
16511 ? (signedp
? gen_isel_signed_si
: gen_isel_unsigned_si
)
16512 : (signedp
? gen_isel_signed_di
: gen_isel_unsigned_di
));
16516 case LT
: case GT
: case LTU
: case GTU
: case EQ
:
16517 /* isel handles these directly. */
16521 /* We need to swap the sense of the comparison. */
16524 true_cond
= false_cond
;
16526 PUT_CODE (condition_rtx
, reverse_condition (cond_code
));
16531 false_cond
= force_reg (mode
, false_cond
);
16532 if (true_cond
!= const0_rtx
)
16533 true_cond
= force_reg (mode
, true_cond
);
16535 emit_insn (isel_func (dest
, condition_rtx
, true_cond
, false_cond
, cr
));
16541 output_isel (rtx
*operands
)
16543 enum rtx_code code
;
16545 code
= GET_CODE (operands
[1]);
16547 if (code
== GE
|| code
== GEU
|| code
== LE
|| code
== LEU
|| code
== NE
)
16549 gcc_assert (GET_CODE (operands
[2]) == REG
16550 && GET_CODE (operands
[3]) == REG
);
16551 PUT_CODE (operands
[1], reverse_condition (code
));
16552 return "isel %0,%3,%2,%j1";
16555 return "isel %0,%2,%3,%j1";
16559 rs6000_emit_minmax (rtx dest
, enum rtx_code code
, rtx op0
, rtx op1
)
16561 enum machine_mode mode
= GET_MODE (op0
);
16565 /* VSX/altivec have direct min/max insns. */
16566 if ((code
== SMAX
|| code
== SMIN
)
16567 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
16568 || (mode
== SFmode
&& VECTOR_UNIT_VSX_P (DFmode
))))
16570 emit_insn (gen_rtx_SET (VOIDmode
,
16572 gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
16576 if (code
== SMAX
|| code
== SMIN
)
16581 if (code
== SMAX
|| code
== UMAX
)
16582 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
16583 op0
, op1
, mode
, 0);
16585 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
16586 op1
, op0
, mode
, 0);
16587 gcc_assert (target
);
16588 if (target
!= dest
)
16589 emit_move_insn (dest
, target
);
16592 /* A subroutine of the atomic operation splitters. Jump to LABEL if
16593 COND is true. Mark the jump as unlikely to be taken. */
16596 emit_unlikely_jump (rtx cond
, rtx label
)
16598 rtx very_unlikely
= GEN_INT (REG_BR_PROB_BASE
/ 100 - 1);
16601 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, label
, pc_rtx
);
16602 x
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, x
));
16603 add_reg_note (x
, REG_BR_PROB
, very_unlikely
);
16606 /* A subroutine of the atomic operation splitters. Emit a load-locked
16607 instruction in MODE. */
16610 emit_load_locked (enum machine_mode mode
, rtx reg
, rtx mem
)
16612 rtx (*fn
) (rtx
, rtx
) = NULL
;
16617 fn
= gen_load_lockedsi
;
16620 fn
= gen_load_lockeddi
;
16623 gcc_unreachable ();
16625 emit_insn (fn (reg
, mem
));
16628 /* A subroutine of the atomic operation splitters. Emit a store-conditional
16629 instruction in MODE. */
16632 emit_store_conditional (enum machine_mode mode
, rtx res
, rtx mem
, rtx val
)
16634 rtx (*fn
) (rtx
, rtx
, rtx
) = NULL
;
16639 fn
= gen_store_conditionalsi
;
16642 fn
= gen_store_conditionaldi
;
16645 gcc_unreachable ();
16648 /* Emit sync before stwcx. to address PPC405 Erratum. */
16649 if (PPC405_ERRATUM77
)
16650 emit_insn (gen_hwsync ());
16652 emit_insn (fn (res
, mem
, val
));
16655 /* Expand barriers before and after a load_locked/store_cond sequence. */
16658 rs6000_pre_atomic_barrier (enum memmodel model
)
16662 case MEMMODEL_RELAXED
:
16663 case MEMMODEL_CONSUME
:
16664 case MEMMODEL_ACQUIRE
:
16666 case MEMMODEL_RELEASE
:
16667 case MEMMODEL_ACQ_REL
:
16668 emit_insn (gen_lwsync ());
16670 case MEMMODEL_SEQ_CST
:
16671 emit_insn (gen_hwsync ());
16674 gcc_unreachable ();
16679 rs6000_post_atomic_barrier (enum memmodel model
)
16683 case MEMMODEL_RELAXED
:
16684 case MEMMODEL_CONSUME
:
16685 case MEMMODEL_RELEASE
:
16687 case MEMMODEL_ACQUIRE
:
16688 case MEMMODEL_ACQ_REL
:
16689 case MEMMODEL_SEQ_CST
:
16690 emit_insn (gen_isync ());
16693 gcc_unreachable ();
16697 /* A subroutine of the various atomic expanders. For sub-word operations,
16698 we must adjust things to operate on SImode. Given the original MEM,
16699 return a new aligned memory. Also build and return the quantities by
16700 which to shift and mask. */
16703 rs6000_adjust_atomic_subword (rtx orig_mem
, rtx
*pshift
, rtx
*pmask
)
16705 rtx addr
, align
, shift
, mask
, mem
;
16706 HOST_WIDE_INT shift_mask
;
16707 enum machine_mode mode
= GET_MODE (orig_mem
);
16709 /* For smaller modes, we have to implement this via SImode. */
16710 shift_mask
= (mode
== QImode
? 0x18 : 0x10);
16712 addr
= XEXP (orig_mem
, 0);
16713 addr
= force_reg (GET_MODE (addr
), addr
);
16715 /* Aligned memory containing subword. Generate a new memory. We
16716 do not want any of the existing MEM_ATTR data, as we're now
16717 accessing memory outside the original object. */
16718 align
= expand_simple_binop (Pmode
, AND
, addr
, GEN_INT (-4),
16719 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
16720 mem
= gen_rtx_MEM (SImode
, align
);
16721 MEM_VOLATILE_P (mem
) = MEM_VOLATILE_P (orig_mem
);
16722 if (MEM_ALIAS_SET (orig_mem
) == ALIAS_SET_MEMORY_BARRIER
)
16723 set_mem_alias_set (mem
, ALIAS_SET_MEMORY_BARRIER
);
16725 /* Shift amount for subword relative to aligned word. */
16726 shift
= gen_reg_rtx (SImode
);
16727 addr
= gen_lowpart (SImode
, addr
);
16728 emit_insn (gen_rlwinm (shift
, addr
, GEN_INT (3), GEN_INT (shift_mask
)));
16729 shift
= expand_simple_binop (SImode
, XOR
, shift
, GEN_INT (shift_mask
),
16730 shift
, 1, OPTAB_LIB_WIDEN
);
16733 /* Mask for insertion. */
16734 mask
= expand_simple_binop (SImode
, ASHIFT
, GEN_INT (GET_MODE_MASK (mode
)),
16735 shift
, NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
16741 /* A subroutine of the various atomic expanders. For sub-word operands,
16742 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
16745 rs6000_mask_atomic_subword (rtx oldval
, rtx newval
, rtx mask
)
16749 x
= gen_reg_rtx (SImode
);
16750 emit_insn (gen_rtx_SET (VOIDmode
, x
,
16751 gen_rtx_AND (SImode
,
16752 gen_rtx_NOT (SImode
, mask
),
16755 x
= expand_simple_binop (SImode
, IOR
, newval
, x
, x
, 1, OPTAB_LIB_WIDEN
);
16760 /* A subroutine of the various atomic expanders. For sub-word operands,
16761 extract WIDE to NARROW via SHIFT. */
16764 rs6000_finish_atomic_subword (rtx narrow
, rtx wide
, rtx shift
)
16766 wide
= expand_simple_binop (SImode
, LSHIFTRT
, wide
, shift
,
16767 wide
, 1, OPTAB_LIB_WIDEN
);
16768 emit_move_insn (narrow
, gen_lowpart (GET_MODE (narrow
), wide
));
16771 /* Expand an atomic compare and swap operation. */
16774 rs6000_expand_atomic_compare_and_swap (rtx operands
[])
16776 rtx boolval
, retval
, mem
, oldval
, newval
, cond
;
16777 rtx label1
, label2
, x
, mask
, shift
;
16778 enum machine_mode mode
;
16779 enum memmodel mod_s
, mod_f
;
16782 boolval
= operands
[0];
16783 retval
= operands
[1];
16785 oldval
= operands
[3];
16786 newval
= operands
[4];
16787 is_weak
= (INTVAL (operands
[5]) != 0);
16788 mod_s
= (enum memmodel
) INTVAL (operands
[6]);
16789 mod_f
= (enum memmodel
) INTVAL (operands
[7]);
16790 mode
= GET_MODE (mem
);
16792 mask
= shift
= NULL_RTX
;
16793 if (mode
== QImode
|| mode
== HImode
)
16795 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
16797 /* Shift and mask OLDVAL into position with the word. */
16798 oldval
= convert_modes (SImode
, mode
, oldval
, 1);
16799 oldval
= expand_simple_binop (SImode
, ASHIFT
, oldval
, shift
,
16800 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
16802 /* Shift and mask NEWVAL into position within the word. */
16803 newval
= convert_modes (SImode
, mode
, newval
, 1);
16804 newval
= expand_simple_binop (SImode
, ASHIFT
, newval
, shift
,
16805 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
16807 /* Prepare to adjust the return value. */
16808 retval
= gen_reg_rtx (SImode
);
16811 else if (reg_overlap_mentioned_p (retval
, oldval
))
16812 oldval
= copy_to_reg (oldval
);
16814 rs6000_pre_atomic_barrier (mod_s
);
16819 label1
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
16820 emit_label (XEXP (label1
, 0));
16822 label2
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
16824 emit_load_locked (mode
, retval
, mem
);
16829 x
= expand_simple_binop (SImode
, AND
, retval
, mask
,
16830 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
16833 cond
= gen_reg_rtx (CCmode
);
16834 x
= gen_rtx_COMPARE (CCmode
, x
, oldval
);
16835 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
16837 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
16838 emit_unlikely_jump (x
, label2
);
16842 x
= rs6000_mask_atomic_subword (retval
, newval
, mask
);
16844 emit_store_conditional (mode
, cond
, mem
, x
);
16848 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
16849 emit_unlikely_jump (x
, label1
);
16852 if (mod_f
!= MEMMODEL_RELAXED
)
16853 emit_label (XEXP (label2
, 0));
16855 rs6000_post_atomic_barrier (mod_s
);
16857 if (mod_f
== MEMMODEL_RELAXED
)
16858 emit_label (XEXP (label2
, 0));
16861 rs6000_finish_atomic_subword (operands
[1], retval
, shift
);
16863 /* In all cases, CR0 contains EQ on success, and NE on failure. */
16864 x
= gen_rtx_EQ (SImode
, cond
, const0_rtx
);
16865 emit_insn (gen_rtx_SET (VOIDmode
, boolval
, x
));
16868 /* Expand an atomic exchange operation. */
16871 rs6000_expand_atomic_exchange (rtx operands
[])
16873 rtx retval
, mem
, val
, cond
;
16874 enum machine_mode mode
;
16875 enum memmodel model
;
16876 rtx label
, x
, mask
, shift
;
16878 retval
= operands
[0];
16881 model
= (enum memmodel
) INTVAL (operands
[3]);
16882 mode
= GET_MODE (mem
);
16884 mask
= shift
= NULL_RTX
;
16885 if (mode
== QImode
|| mode
== HImode
)
16887 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
16889 /* Shift and mask VAL into position with the word. */
16890 val
= convert_modes (SImode
, mode
, val
, 1);
16891 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
16892 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
16894 /* Prepare to adjust the return value. */
16895 retval
= gen_reg_rtx (SImode
);
16899 rs6000_pre_atomic_barrier (model
);
16901 label
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
16902 emit_label (XEXP (label
, 0));
16904 emit_load_locked (mode
, retval
, mem
);
16908 x
= rs6000_mask_atomic_subword (retval
, val
, mask
);
16910 cond
= gen_reg_rtx (CCmode
);
16911 emit_store_conditional (mode
, cond
, mem
, x
);
16913 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
16914 emit_unlikely_jump (x
, label
);
16916 rs6000_post_atomic_barrier (model
);
16919 rs6000_finish_atomic_subword (operands
[0], retval
, shift
);
16922 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
16923 to perform. MEM is the memory on which to operate. VAL is the second
16924 operand of the binary operator. BEFORE and AFTER are optional locations to
16925 return the value of MEM either before of after the operation. MODEL_RTX
16926 is a CONST_INT containing the memory model to use. */
16929 rs6000_expand_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
16930 rtx orig_before
, rtx orig_after
, rtx model_rtx
)
16932 enum memmodel model
= (enum memmodel
) INTVAL (model_rtx
);
16933 enum machine_mode mode
= GET_MODE (mem
);
16934 rtx label
, x
, cond
, mask
, shift
;
16935 rtx before
= orig_before
, after
= orig_after
;
16937 mask
= shift
= NULL_RTX
;
16938 if (mode
== QImode
|| mode
== HImode
)
16940 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
16942 /* Shift and mask VAL into position with the word. */
16943 val
= convert_modes (SImode
, mode
, val
, 1);
16944 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
16945 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
16951 /* We've already zero-extended VAL. That is sufficient to
16952 make certain that it does not affect other bits. */
16957 /* If we make certain that all of the other bits in VAL are
16958 set, that will be sufficient to not affect other bits. */
16959 x
= gen_rtx_NOT (SImode
, mask
);
16960 x
= gen_rtx_IOR (SImode
, x
, val
);
16961 emit_insn (gen_rtx_SET (VOIDmode
, val
, x
));
16968 /* These will all affect bits outside the field and need
16969 adjustment via MASK within the loop. */
16973 gcc_unreachable ();
16976 /* Prepare to adjust the return value. */
16977 before
= gen_reg_rtx (SImode
);
16979 after
= gen_reg_rtx (SImode
);
16983 rs6000_pre_atomic_barrier (model
);
16985 label
= gen_label_rtx ();
16986 emit_label (label
);
16987 label
= gen_rtx_LABEL_REF (VOIDmode
, label
);
16989 if (before
== NULL_RTX
)
16990 before
= gen_reg_rtx (mode
);
16992 emit_load_locked (mode
, before
, mem
);
16996 x
= expand_simple_binop (mode
, AND
, before
, val
,
16997 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
16998 after
= expand_simple_unop (mode
, NOT
, x
, after
, 1);
17002 after
= expand_simple_binop (mode
, code
, before
, val
,
17003 after
, 1, OPTAB_LIB_WIDEN
);
17009 x
= expand_simple_binop (SImode
, AND
, after
, mask
,
17010 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
17011 x
= rs6000_mask_atomic_subword (before
, x
, mask
);
17014 cond
= gen_reg_rtx (CCmode
);
17015 emit_store_conditional (mode
, cond
, mem
, x
);
17017 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
17018 emit_unlikely_jump (x
, label
);
17020 rs6000_post_atomic_barrier (model
);
17025 rs6000_finish_atomic_subword (orig_before
, before
, shift
);
17027 rs6000_finish_atomic_subword (orig_after
, after
, shift
);
17029 else if (orig_after
&& after
!= orig_after
)
17030 emit_move_insn (orig_after
, after
);
17033 /* Emit instructions to move SRC to DST. Called by splitters for
17034 multi-register moves. It will emit at most one instruction for
17035 each register that is accessed; that is, it won't emit li/lis pairs
17036 (or equivalent for 64-bit code). One of SRC or DST must be a hard
17040 rs6000_split_multireg_move (rtx dst
, rtx src
)
17042 /* The register number of the first register being moved. */
17044 /* The mode that is to be moved. */
17045 enum machine_mode mode
;
17046 /* The mode that the move is being done in, and its size. */
17047 enum machine_mode reg_mode
;
17049 /* The number of registers that will be moved. */
17052 reg
= REG_P (dst
) ? REGNO (dst
) : REGNO (src
);
17053 mode
= GET_MODE (dst
);
17054 nregs
= hard_regno_nregs
[reg
][mode
];
17055 if (FP_REGNO_P (reg
))
17056 reg_mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
:
17057 ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? DFmode
: SFmode
);
17058 else if (ALTIVEC_REGNO_P (reg
))
17059 reg_mode
= V16QImode
;
17060 else if (TARGET_E500_DOUBLE
&& mode
== TFmode
)
17063 reg_mode
= word_mode
;
17064 reg_mode_size
= GET_MODE_SIZE (reg_mode
);
17066 gcc_assert (reg_mode_size
* nregs
== GET_MODE_SIZE (mode
));
17068 if (REG_P (src
) && REG_P (dst
) && (REGNO (src
) < REGNO (dst
)))
17070 /* Move register range backwards, if we might have destructive
17073 for (i
= nregs
- 1; i
>= 0; i
--)
17074 emit_insn (gen_rtx_SET (VOIDmode
,
17075 simplify_gen_subreg (reg_mode
, dst
, mode
,
17076 i
* reg_mode_size
),
17077 simplify_gen_subreg (reg_mode
, src
, mode
,
17078 i
* reg_mode_size
)));
17084 bool used_update
= false;
17085 rtx restore_basereg
= NULL_RTX
;
17087 if (MEM_P (src
) && INT_REGNO_P (reg
))
17091 if (GET_CODE (XEXP (src
, 0)) == PRE_INC
17092 || GET_CODE (XEXP (src
, 0)) == PRE_DEC
)
17095 breg
= XEXP (XEXP (src
, 0), 0);
17096 delta_rtx
= (GET_CODE (XEXP (src
, 0)) == PRE_INC
17097 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src
)))
17098 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src
))));
17099 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
17100 src
= replace_equiv_address (src
, breg
);
17102 else if (! rs6000_offsettable_memref_p (src
))
17104 if (GET_CODE (XEXP (src
, 0)) == PRE_MODIFY
)
17106 rtx basereg
= XEXP (XEXP (src
, 0), 0);
17109 rtx ndst
= simplify_gen_subreg (reg_mode
, dst
, mode
, 0);
17110 emit_insn (gen_rtx_SET (VOIDmode
, ndst
,
17111 gen_rtx_MEM (reg_mode
, XEXP (src
, 0))));
17112 used_update
= true;
17115 emit_insn (gen_rtx_SET (VOIDmode
, basereg
,
17116 XEXP (XEXP (src
, 0), 1)));
17117 src
= replace_equiv_address (src
, basereg
);
17121 rtx basereg
= gen_rtx_REG (Pmode
, reg
);
17122 emit_insn (gen_rtx_SET (VOIDmode
, basereg
, XEXP (src
, 0)));
17123 src
= replace_equiv_address (src
, basereg
);
17127 breg
= XEXP (src
, 0);
17128 if (GET_CODE (breg
) == PLUS
|| GET_CODE (breg
) == LO_SUM
)
17129 breg
= XEXP (breg
, 0);
17131 /* If the base register we are using to address memory is
17132 also a destination reg, then change that register last. */
17134 && REGNO (breg
) >= REGNO (dst
)
17135 && REGNO (breg
) < REGNO (dst
) + nregs
)
17136 j
= REGNO (breg
) - REGNO (dst
);
17138 else if (MEM_P (dst
) && INT_REGNO_P (reg
))
17142 if (GET_CODE (XEXP (dst
, 0)) == PRE_INC
17143 || GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
17146 breg
= XEXP (XEXP (dst
, 0), 0);
17147 delta_rtx
= (GET_CODE (XEXP (dst
, 0)) == PRE_INC
17148 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst
)))
17149 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst
))));
17151 /* We have to update the breg before doing the store.
17152 Use store with update, if available. */
17156 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
17157 emit_insn (TARGET_32BIT
17158 ? (TARGET_POWERPC64
17159 ? gen_movdi_si_update (breg
, breg
, delta_rtx
, nsrc
)
17160 : gen_movsi_update (breg
, breg
, delta_rtx
, nsrc
))
17161 : gen_movdi_di_update (breg
, breg
, delta_rtx
, nsrc
));
17162 used_update
= true;
17165 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
17166 dst
= replace_equiv_address (dst
, breg
);
17168 else if (!rs6000_offsettable_memref_p (dst
)
17169 && GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
17171 if (GET_CODE (XEXP (dst
, 0)) == PRE_MODIFY
)
17173 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
17176 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
17177 emit_insn (gen_rtx_SET (VOIDmode
,
17178 gen_rtx_MEM (reg_mode
, XEXP (dst
, 0)), nsrc
));
17179 used_update
= true;
17182 emit_insn (gen_rtx_SET (VOIDmode
, basereg
,
17183 XEXP (XEXP (dst
, 0), 1)));
17184 dst
= replace_equiv_address (dst
, basereg
);
17188 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
17189 rtx offsetreg
= XEXP (XEXP (dst
, 0), 1);
17190 gcc_assert (GET_CODE (XEXP (dst
, 0)) == PLUS
17192 && REG_P (offsetreg
)
17193 && REGNO (basereg
) != REGNO (offsetreg
));
17194 if (REGNO (basereg
) == 0)
17196 rtx tmp
= offsetreg
;
17197 offsetreg
= basereg
;
17200 emit_insn (gen_add3_insn (basereg
, basereg
, offsetreg
));
17201 restore_basereg
= gen_sub3_insn (basereg
, basereg
, offsetreg
);
17202 dst
= replace_equiv_address (dst
, basereg
);
17205 else if (GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
17206 gcc_assert (rs6000_offsettable_memref_p (dst
));
17209 for (i
= 0; i
< nregs
; i
++)
17211 /* Calculate index to next subword. */
17216 /* If compiler already emitted move of first word by
17217 store with update, no need to do anything. */
17218 if (j
== 0 && used_update
)
17221 emit_insn (gen_rtx_SET (VOIDmode
,
17222 simplify_gen_subreg (reg_mode
, dst
, mode
,
17223 j
* reg_mode_size
),
17224 simplify_gen_subreg (reg_mode
, src
, mode
,
17225 j
* reg_mode_size
)));
17227 if (restore_basereg
!= NULL_RTX
)
17228 emit_insn (restore_basereg
);
17233 /* This page contains routines that are used to determine what the
17234 function prologue and epilogue code will do and write them out. */
17236 /* Return the first fixed-point register that is required to be
17237 saved. 32 if none. */
17240 first_reg_to_save (void)
17244 /* Find lowest numbered live register. */
17245 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
17246 if (df_regs_ever_live_p (first_reg
)
17247 && (! call_used_regs
[first_reg
]
17248 || (first_reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
17249 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
17250 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
17251 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
)))))
17256 && crtl
->uses_pic_offset_table
17257 && first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
17258 return RS6000_PIC_OFFSET_TABLE_REGNUM
;
17264 /* Similar, for FP regs. */
17267 first_fp_reg_to_save (void)
17271 /* Find lowest numbered live register. */
17272 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
17273 if (df_regs_ever_live_p (first_reg
))
17279 /* Similar, for AltiVec regs. */
17282 first_altivec_reg_to_save (void)
17286 /* Stack frame remains as is unless we are in AltiVec ABI. */
17287 if (! TARGET_ALTIVEC_ABI
)
17288 return LAST_ALTIVEC_REGNO
+ 1;
17290 /* On Darwin, the unwind routines are compiled without
17291 TARGET_ALTIVEC, and use save_world to save/restore the
17292 altivec registers when necessary. */
17293 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
17294 && ! TARGET_ALTIVEC
)
17295 return FIRST_ALTIVEC_REGNO
+ 20;
17297 /* Find lowest numbered live register. */
17298 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
<= LAST_ALTIVEC_REGNO
; ++i
)
17299 if (df_regs_ever_live_p (i
))
17305 /* Return a 32-bit mask of the AltiVec registers we need to set in
17306 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
17307 the 32-bit word is 0. */
17309 static unsigned int
17310 compute_vrsave_mask (void)
17312 unsigned int i
, mask
= 0;
17314 /* On Darwin, the unwind routines are compiled without
17315 TARGET_ALTIVEC, and use save_world to save/restore the
17316 call-saved altivec registers when necessary. */
17317 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
17318 && ! TARGET_ALTIVEC
)
17321 /* First, find out if we use _any_ altivec registers. */
17322 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
17323 if (df_regs_ever_live_p (i
))
17324 mask
|= ALTIVEC_REG_BIT (i
);
17329 /* Next, remove the argument registers from the set. These must
17330 be in the VRSAVE mask set by the caller, so we don't need to add
17331 them in again. More importantly, the mask we compute here is
17332 used to generate CLOBBERs in the set_vrsave insn, and we do not
17333 wish the argument registers to die. */
17334 for (i
= crtl
->args
.info
.vregno
- 1; i
>= ALTIVEC_ARG_MIN_REG
; --i
)
17335 mask
&= ~ALTIVEC_REG_BIT (i
);
17337 /* Similarly, remove the return value from the set. */
17340 diddle_return_value (is_altivec_return_reg
, &yes
);
17342 mask
&= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN
);
17348 /* For a very restricted set of circumstances, we can cut down the
17349 size of prologues/epilogues by calling our own save/restore-the-world
17353 compute_save_world_info (rs6000_stack_t
*info_ptr
)
17355 info_ptr
->world_save_p
= 1;
17356 info_ptr
->world_save_p
17357 = (WORLD_SAVE_P (info_ptr
)
17358 && DEFAULT_ABI
== ABI_DARWIN
17359 && !cfun
->has_nonlocal_label
17360 && info_ptr
->first_fp_reg_save
== FIRST_SAVED_FP_REGNO
17361 && info_ptr
->first_gp_reg_save
== FIRST_SAVED_GP_REGNO
17362 && info_ptr
->first_altivec_reg_save
== FIRST_SAVED_ALTIVEC_REGNO
17363 && info_ptr
->cr_save_p
);
17365 /* This will not work in conjunction with sibcalls. Make sure there
17366 are none. (This check is expensive, but seldom executed.) */
17367 if (WORLD_SAVE_P (info_ptr
))
17370 for ( insn
= get_last_insn_anywhere (); insn
; insn
= PREV_INSN (insn
))
17371 if ( GET_CODE (insn
) == CALL_INSN
17372 && SIBLING_CALL_P (insn
))
17374 info_ptr
->world_save_p
= 0;
17379 if (WORLD_SAVE_P (info_ptr
))
17381 /* Even if we're not touching VRsave, make sure there's room on the
17382 stack for it, if it looks like we're calling SAVE_WORLD, which
17383 will attempt to save it. */
17384 info_ptr
->vrsave_size
= 4;
17386 /* If we are going to save the world, we need to save the link register too. */
17387 info_ptr
->lr_save_p
= 1;
17389 /* "Save" the VRsave register too if we're saving the world. */
17390 if (info_ptr
->vrsave_mask
== 0)
17391 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
17393 /* Because the Darwin register save/restore routines only handle
17394 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
17396 gcc_assert (info_ptr
->first_fp_reg_save
>= FIRST_SAVED_FP_REGNO
17397 && (info_ptr
->first_altivec_reg_save
17398 >= FIRST_SAVED_ALTIVEC_REGNO
));
17405 is_altivec_return_reg (rtx reg
, void *xyes
)
17407 bool *yes
= (bool *) xyes
;
17408 if (REGNO (reg
) == ALTIVEC_ARG_RETURN
)
17413 /* Determine the strategy for savings/restoring registers. */
17416 SAVRES_MULTIPLE
= 0x1,
17417 SAVE_INLINE_FPRS
= 0x2,
17418 SAVE_INLINE_GPRS
= 0x4,
17419 REST_INLINE_FPRS
= 0x8,
17420 REST_INLINE_GPRS
= 0x10,
17421 SAVE_NOINLINE_GPRS_SAVES_LR
= 0x20,
17422 SAVE_NOINLINE_FPRS_SAVES_LR
= 0x40,
17423 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
= 0x80
17427 rs6000_savres_strategy (rs6000_stack_t
*info
,
17428 bool using_static_chain_p
)
17432 if (TARGET_MULTIPLE
17433 && !TARGET_POWERPC64
17434 && !(TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
)
17435 && info
->first_gp_reg_save
< 31
17436 && no_global_regs_above (info
->first_gp_reg_save
, /*gpr=*/true))
17437 strategy
|= SAVRES_MULTIPLE
;
17439 if (crtl
->calls_eh_return
17440 || cfun
->machine
->ra_need_lr
17441 || info
->total_size
> 32767)
17442 strategy
|= (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
17443 | SAVE_INLINE_GPRS
| REST_INLINE_GPRS
);
17445 if (info
->first_fp_reg_save
== 64
17446 || FP_SAVE_INLINE (info
->first_fp_reg_save
)
17447 /* The out-of-line FP routines use double-precision stores;
17448 we can't use those routines if we don't have such stores. */
17449 || (TARGET_HARD_FLOAT
&& !TARGET_DOUBLE_FLOAT
)
17450 || !no_global_regs_above (info
->first_fp_reg_save
, /*gpr=*/false))
17451 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
17453 if (info
->first_gp_reg_save
== 32
17454 || GP_SAVE_INLINE (info
->first_gp_reg_save
)
17455 || !((strategy
& SAVRES_MULTIPLE
)
17456 || no_global_regs_above (info
->first_gp_reg_save
, /*gpr=*/true)))
17457 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
17459 /* Don't bother to try to save things out-of-line if r11 is occupied
17460 by the static chain. It would require too much fiddling and the
17461 static chain is rarely used anyway. FPRs are saved w.r.t the stack
17462 pointer on Darwin. */
17463 if (using_static_chain_p
)
17464 strategy
|= (DEFAULT_ABI
== ABI_DARWIN
? 0 : SAVE_INLINE_FPRS
)
17465 | SAVE_INLINE_GPRS
;
17467 /* If we are going to use store multiple, then don't even bother
17468 with the out-of-line routines, since the store-multiple
17469 instruction will always be smaller. */
17470 if ((strategy
& SAVRES_MULTIPLE
))
17471 strategy
|= SAVE_INLINE_GPRS
;
17473 /* The situation is more complicated with load multiple. We'd
17474 prefer to use the out-of-line routines for restores, since the
17475 "exit" out-of-line routines can handle the restore of LR and the
17476 frame teardown. However if doesn't make sense to use the
17477 out-of-line routine if that is the only reason we'd need to save
17478 LR, and we can't use the "exit" out-of-line gpr restore if we
17479 have saved some fprs; In those cases it is advantageous to use
17480 load multiple when available. */
17481 if ((strategy
& SAVRES_MULTIPLE
)
17482 && (!info
->lr_save_p
17483 || info
->first_fp_reg_save
!= 64))
17484 strategy
|= REST_INLINE_GPRS
;
17486 /* We can only use load multiple or the out-of-line routines to
17487 restore if we've used store multiple or out-of-line routines
17488 in the prologue, i.e. if we've saved all the registers from
17489 first_gp_reg_save. Otherwise, we risk loading garbage. */
17490 if ((strategy
& (SAVE_INLINE_GPRS
| SAVRES_MULTIPLE
)) == SAVE_INLINE_GPRS
)
17491 strategy
|= REST_INLINE_GPRS
;
17493 /* Saving CR interferes with the exit routines used on the SPE, so
17496 && info
->spe_64bit_regs_used
17497 && info
->cr_save_p
)
17498 strategy
|= REST_INLINE_GPRS
;
17500 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
17503 if (!(strategy
& SAVE_INLINE_FPRS
))
17504 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
17505 else if (!(strategy
& SAVE_INLINE_GPRS
)
17506 && info
->first_fp_reg_save
== 64)
17507 strategy
|= SAVE_NOINLINE_GPRS_SAVES_LR
;
17510 if (TARGET_AIX
&& !(strategy
& REST_INLINE_FPRS
))
17511 strategy
|= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
;
17513 if (TARGET_MACHO
&& !(strategy
& SAVE_INLINE_FPRS
))
17514 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
17519 /* Calculate the stack information for the current function. This is
17520 complicated by having two separate calling sequences, the AIX calling
17521 sequence and the V.4 calling sequence.
17523 AIX (and Darwin/Mac OS X) stack frames look like:
17525 SP----> +---------------------------------------+
17526 | back chain to caller | 0 0
17527 +---------------------------------------+
17528 | saved CR | 4 8 (8-11)
17529 +---------------------------------------+
17531 +---------------------------------------+
17532 | reserved for compilers | 12 24
17533 +---------------------------------------+
17534 | reserved for binders | 16 32
17535 +---------------------------------------+
17536 | saved TOC pointer | 20 40
17537 +---------------------------------------+
17538 | Parameter save area (P) | 24 48
17539 +---------------------------------------+
17540 | Alloca space (A) | 24+P etc.
17541 +---------------------------------------+
17542 | Local variable space (L) | 24+P+A
17543 +---------------------------------------+
17544 | Float/int conversion temporary (X) | 24+P+A+L
17545 +---------------------------------------+
17546 | Save area for AltiVec registers (W) | 24+P+A+L+X
17547 +---------------------------------------+
17548 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
17549 +---------------------------------------+
17550 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
17551 +---------------------------------------+
17552 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
17553 +---------------------------------------+
17554 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
17555 +---------------------------------------+
17556 old SP->| back chain to caller's caller |
17557 +---------------------------------------+
17559 The required alignment for AIX configurations is two words (i.e., 8
17563 V.4 stack frames look like:
17565 SP----> +---------------------------------------+
17566 | back chain to caller | 0
17567 +---------------------------------------+
17568 | caller's saved LR | 4
17569 +---------------------------------------+
17570 | Parameter save area (P) | 8
17571 +---------------------------------------+
17572 | Alloca space (A) | 8+P
17573 +---------------------------------------+
17574 | Varargs save area (V) | 8+P+A
17575 +---------------------------------------+
17576 | Local variable space (L) | 8+P+A+V
17577 +---------------------------------------+
17578 | Float/int conversion temporary (X) | 8+P+A+V+L
17579 +---------------------------------------+
17580 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
17581 +---------------------------------------+
17582 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
17583 +---------------------------------------+
17584 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
17585 +---------------------------------------+
17586 | SPE: area for 64-bit GP registers |
17587 +---------------------------------------+
17588 | SPE alignment padding |
17589 +---------------------------------------+
17590 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
17591 +---------------------------------------+
17592 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
17593 +---------------------------------------+
17594 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
17595 +---------------------------------------+
17596 old SP->| back chain to caller's caller |
17597 +---------------------------------------+
17599 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
17600 given. (But note below and in sysv4.h that we require only 8 and
17601 may round up the size of our stack frame anyways. The historical
17602 reason is early versions of powerpc-linux which didn't properly
17603 align the stack at program startup. A happy side-effect is that
17604 -mno-eabi libraries can be used with -meabi programs.)
17606 The EABI configuration defaults to the V.4 layout. However,
17607 the stack alignment requirements may differ. If -mno-eabi is not
17608 given, the required stack alignment is 8 bytes; if -mno-eabi is
17609 given, the required alignment is 16 bytes. (But see V.4 comment
17612 #ifndef ABI_STACK_BOUNDARY
17613 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
17616 static rs6000_stack_t
*
17617 rs6000_stack_info (void)
17619 rs6000_stack_t
*info_ptr
= &stack_info
;
17620 int reg_size
= TARGET_32BIT
? 4 : 8;
17624 HOST_WIDE_INT non_fixed_size
;
17625 bool using_static_chain_p
;
17627 if (reload_completed
&& info_ptr
->reload_completed
)
17630 memset (info_ptr
, 0, sizeof (*info_ptr
));
17631 info_ptr
->reload_completed
= reload_completed
;
17635 /* Cache value so we don't rescan instruction chain over and over. */
17636 if (cfun
->machine
->insn_chain_scanned_p
== 0)
17637 cfun
->machine
->insn_chain_scanned_p
17638 = spe_func_has_64bit_regs_p () + 1;
17639 info_ptr
->spe_64bit_regs_used
= cfun
->machine
->insn_chain_scanned_p
- 1;
17642 /* Select which calling sequence. */
17643 info_ptr
->abi
= DEFAULT_ABI
;
17645 /* Calculate which registers need to be saved & save area size. */
17646 info_ptr
->first_gp_reg_save
= first_reg_to_save ();
17647 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
17648 even if it currently looks like we won't. Reload may need it to
17649 get at a constant; if so, it will have already created a constant
17650 pool entry for it. */
17651 if (((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
17652 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
17653 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
17654 && crtl
->uses_const_pool
17655 && info_ptr
->first_gp_reg_save
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
17656 first_gp
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
17658 first_gp
= info_ptr
->first_gp_reg_save
;
17660 info_ptr
->gp_size
= reg_size
* (32 - first_gp
);
17662 /* For the SPE, we have an additional upper 32-bits on each GPR.
17663 Ideally we should save the entire 64-bits only when the upper
17664 half is used in SIMD instructions. Since we only record
17665 registers live (not the size they are used in), this proves
17666 difficult because we'd have to traverse the instruction chain at
17667 the right time, taking reload into account. This is a real pain,
17668 so we opt to save the GPRs in 64-bits always if but one register
17669 gets used in 64-bits. Otherwise, all the registers in the frame
17670 get saved in 32-bits.
17672 So... since when we save all GPRs (except the SP) in 64-bits, the
17673 traditional GP save area will be empty. */
17674 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
17675 info_ptr
->gp_size
= 0;
17677 info_ptr
->first_fp_reg_save
= first_fp_reg_to_save ();
17678 info_ptr
->fp_size
= 8 * (64 - info_ptr
->first_fp_reg_save
);
17680 info_ptr
->first_altivec_reg_save
= first_altivec_reg_to_save ();
17681 info_ptr
->altivec_size
= 16 * (LAST_ALTIVEC_REGNO
+ 1
17682 - info_ptr
->first_altivec_reg_save
);
17684 /* Does this function call anything? */
17685 info_ptr
->calls_p
= (! current_function_is_leaf
17686 || cfun
->machine
->ra_needs_full_frame
);
17688 /* Determine if we need to save the condition code registers. */
17689 if (df_regs_ever_live_p (CR2_REGNO
)
17690 || df_regs_ever_live_p (CR3_REGNO
)
17691 || df_regs_ever_live_p (CR4_REGNO
))
17693 info_ptr
->cr_save_p
= 1;
17694 if (DEFAULT_ABI
== ABI_V4
)
17695 info_ptr
->cr_size
= reg_size
;
17698 /* If the current function calls __builtin_eh_return, then we need
17699 to allocate stack space for registers that will hold data for
17700 the exception handler. */
17701 if (crtl
->calls_eh_return
)
17704 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
17707 /* SPE saves EH registers in 64-bits. */
17708 ehrd_size
= i
* (TARGET_SPE_ABI
17709 && info_ptr
->spe_64bit_regs_used
!= 0
17710 ? UNITS_PER_SPE_WORD
: UNITS_PER_WORD
);
17715 /* Determine various sizes. */
17716 info_ptr
->reg_size
= reg_size
;
17717 info_ptr
->fixed_size
= RS6000_SAVE_AREA
;
17718 info_ptr
->vars_size
= RS6000_ALIGN (get_frame_size (), 8);
17719 info_ptr
->parm_size
= RS6000_ALIGN (crtl
->outgoing_args_size
,
17720 TARGET_ALTIVEC
? 16 : 8);
17721 if (FRAME_GROWS_DOWNWARD
)
17722 info_ptr
->vars_size
17723 += RS6000_ALIGN (info_ptr
->fixed_size
+ info_ptr
->vars_size
17724 + info_ptr
->parm_size
,
17725 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
)
17726 - (info_ptr
->fixed_size
+ info_ptr
->vars_size
17727 + info_ptr
->parm_size
);
17729 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
17730 info_ptr
->spe_gp_size
= 8 * (32 - first_gp
);
17732 info_ptr
->spe_gp_size
= 0;
17734 if (TARGET_ALTIVEC_ABI
)
17735 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
17737 info_ptr
->vrsave_mask
= 0;
17739 if (TARGET_ALTIVEC_VRSAVE
&& info_ptr
->vrsave_mask
)
17740 info_ptr
->vrsave_size
= 4;
17742 info_ptr
->vrsave_size
= 0;
17744 compute_save_world_info (info_ptr
);
17746 /* Calculate the offsets. */
17747 switch (DEFAULT_ABI
)
17751 gcc_unreachable ();
17755 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
17756 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
17758 if (TARGET_ALTIVEC_ABI
)
17760 info_ptr
->vrsave_save_offset
17761 = info_ptr
->gp_save_offset
- info_ptr
->vrsave_size
;
17763 /* Align stack so vector save area is on a quadword boundary.
17764 The padding goes above the vectors. */
17765 if (info_ptr
->altivec_size
!= 0)
17766 info_ptr
->altivec_padding_size
17767 = info_ptr
->vrsave_save_offset
& 0xF;
17769 info_ptr
->altivec_padding_size
= 0;
17771 info_ptr
->altivec_save_offset
17772 = info_ptr
->vrsave_save_offset
17773 - info_ptr
->altivec_padding_size
17774 - info_ptr
->altivec_size
;
17775 gcc_assert (info_ptr
->altivec_size
== 0
17776 || info_ptr
->altivec_save_offset
% 16 == 0);
17778 /* Adjust for AltiVec case. */
17779 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
- ehrd_size
;
17782 info_ptr
->ehrd_offset
= info_ptr
->gp_save_offset
- ehrd_size
;
17783 info_ptr
->cr_save_offset
= reg_size
; /* first word when 64-bit. */
17784 info_ptr
->lr_save_offset
= 2*reg_size
;
17788 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
17789 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
17790 info_ptr
->cr_save_offset
= info_ptr
->gp_save_offset
- info_ptr
->cr_size
;
17792 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
17794 /* Align stack so SPE GPR save area is aligned on a
17795 double-word boundary. */
17796 if (info_ptr
->spe_gp_size
!= 0 && info_ptr
->cr_save_offset
!= 0)
17797 info_ptr
->spe_padding_size
17798 = 8 - (-info_ptr
->cr_save_offset
% 8);
17800 info_ptr
->spe_padding_size
= 0;
17802 info_ptr
->spe_gp_save_offset
17803 = info_ptr
->cr_save_offset
17804 - info_ptr
->spe_padding_size
17805 - info_ptr
->spe_gp_size
;
17807 /* Adjust for SPE case. */
17808 info_ptr
->ehrd_offset
= info_ptr
->spe_gp_save_offset
;
17810 else if (TARGET_ALTIVEC_ABI
)
17812 info_ptr
->vrsave_save_offset
17813 = info_ptr
->cr_save_offset
- info_ptr
->vrsave_size
;
17815 /* Align stack so vector save area is on a quadword boundary. */
17816 if (info_ptr
->altivec_size
!= 0)
17817 info_ptr
->altivec_padding_size
17818 = 16 - (-info_ptr
->vrsave_save_offset
% 16);
17820 info_ptr
->altivec_padding_size
= 0;
17822 info_ptr
->altivec_save_offset
17823 = info_ptr
->vrsave_save_offset
17824 - info_ptr
->altivec_padding_size
17825 - info_ptr
->altivec_size
;
17827 /* Adjust for AltiVec case. */
17828 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
;
17831 info_ptr
->ehrd_offset
= info_ptr
->cr_save_offset
;
17832 info_ptr
->ehrd_offset
-= ehrd_size
;
17833 info_ptr
->lr_save_offset
= reg_size
;
17837 save_align
= (TARGET_ALTIVEC_ABI
|| DEFAULT_ABI
== ABI_DARWIN
) ? 16 : 8;
17838 info_ptr
->save_size
= RS6000_ALIGN (info_ptr
->fp_size
17839 + info_ptr
->gp_size
17840 + info_ptr
->altivec_size
17841 + info_ptr
->altivec_padding_size
17842 + info_ptr
->spe_gp_size
17843 + info_ptr
->spe_padding_size
17845 + info_ptr
->cr_size
17846 + info_ptr
->vrsave_size
,
17849 non_fixed_size
= (info_ptr
->vars_size
17850 + info_ptr
->parm_size
17851 + info_ptr
->save_size
);
17853 info_ptr
->total_size
= RS6000_ALIGN (non_fixed_size
+ info_ptr
->fixed_size
,
17854 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
);
17856 /* Determine if we need to save the link register. */
17857 if (info_ptr
->calls_p
17858 || (DEFAULT_ABI
== ABI_AIX
17860 && !TARGET_PROFILE_KERNEL
)
17861 || (DEFAULT_ABI
== ABI_V4
&& cfun
->calls_alloca
)
17862 #ifdef TARGET_RELOCATABLE
17863 || (TARGET_RELOCATABLE
&& (get_pool_size () != 0))
17865 || rs6000_ra_ever_killed ())
17866 info_ptr
->lr_save_p
= 1;
17868 using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
17869 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
17870 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
17871 info_ptr
->savres_strategy
= rs6000_savres_strategy (info_ptr
,
17872 using_static_chain_p
);
17874 if (!(info_ptr
->savres_strategy
& SAVE_INLINE_GPRS
)
17875 || !(info_ptr
->savres_strategy
& SAVE_INLINE_FPRS
)
17876 || !(info_ptr
->savres_strategy
& REST_INLINE_GPRS
)
17877 || !(info_ptr
->savres_strategy
& REST_INLINE_FPRS
))
17878 info_ptr
->lr_save_p
= 1;
17880 if (info_ptr
->lr_save_p
)
17881 df_set_regs_ever_live (LR_REGNO
, true);
17883 /* Determine if we need to allocate any stack frame:
17885 For AIX we need to push the stack if a frame pointer is needed
17886 (because the stack might be dynamically adjusted), if we are
17887 debugging, if we make calls, or if the sum of fp_save, gp_save,
17888 and local variables are more than the space needed to save all
17889 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
17890 + 18*8 = 288 (GPR13 reserved).
17892 For V.4 we don't have the stack cushion that AIX uses, but assume
17893 that the debugger can handle stackless frames. */
17895 if (info_ptr
->calls_p
)
17896 info_ptr
->push_p
= 1;
17898 else if (DEFAULT_ABI
== ABI_V4
)
17899 info_ptr
->push_p
= non_fixed_size
!= 0;
17901 else if (frame_pointer_needed
)
17902 info_ptr
->push_p
= 1;
17904 else if (TARGET_XCOFF
&& write_symbols
!= NO_DEBUG
)
17905 info_ptr
->push_p
= 1;
17908 info_ptr
->push_p
= non_fixed_size
> (TARGET_32BIT
? 220 : 288);
17910 /* Zero offsets if we're not saving those registers. */
17911 if (info_ptr
->fp_size
== 0)
17912 info_ptr
->fp_save_offset
= 0;
17914 if (info_ptr
->gp_size
== 0)
17915 info_ptr
->gp_save_offset
= 0;
17917 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->altivec_size
== 0)
17918 info_ptr
->altivec_save_offset
= 0;
17920 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->vrsave_mask
== 0)
17921 info_ptr
->vrsave_save_offset
= 0;
17923 if (! TARGET_SPE_ABI
17924 || info_ptr
->spe_64bit_regs_used
== 0
17925 || info_ptr
->spe_gp_size
== 0)
17926 info_ptr
->spe_gp_save_offset
= 0;
17928 if (! info_ptr
->lr_save_p
)
17929 info_ptr
->lr_save_offset
= 0;
17931 if (! info_ptr
->cr_save_p
)
17932 info_ptr
->cr_save_offset
= 0;
17937 /* Return true if the current function uses any GPRs in 64-bit SIMD
17941 spe_func_has_64bit_regs_p (void)
17945 /* Functions that save and restore all the call-saved registers will
17946 need to save/restore the registers in 64-bits. */
17947 if (crtl
->calls_eh_return
17948 || cfun
->calls_setjmp
17949 || crtl
->has_nonlocal_goto
)
17952 insns
= get_insns ();
17954 for (insn
= NEXT_INSN (insns
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
17960 /* FIXME: This should be implemented with attributes...
17962 (set_attr "spe64" "true")....then,
17963 if (get_spe64(insn)) return true;
17965 It's the only reliable way to do the stuff below. */
17967 i
= PATTERN (insn
);
17968 if (GET_CODE (i
) == SET
)
17970 enum machine_mode mode
= GET_MODE (SET_SRC (i
));
17972 if (SPE_VECTOR_MODE (mode
))
17974 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
))
17984 debug_stack_info (rs6000_stack_t
*info
)
17986 const char *abi_string
;
17989 info
= rs6000_stack_info ();
17991 fprintf (stderr
, "\nStack information for function %s:\n",
17992 ((current_function_decl
&& DECL_NAME (current_function_decl
))
17993 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
17998 default: abi_string
= "Unknown"; break;
17999 case ABI_NONE
: abi_string
= "NONE"; break;
18000 case ABI_AIX
: abi_string
= "AIX"; break;
18001 case ABI_DARWIN
: abi_string
= "Darwin"; break;
18002 case ABI_V4
: abi_string
= "V.4"; break;
18005 fprintf (stderr
, "\tABI = %5s\n", abi_string
);
18007 if (TARGET_ALTIVEC_ABI
)
18008 fprintf (stderr
, "\tALTIVEC ABI extensions enabled.\n");
18010 if (TARGET_SPE_ABI
)
18011 fprintf (stderr
, "\tSPE ABI extensions enabled.\n");
18013 if (info
->first_gp_reg_save
!= 32)
18014 fprintf (stderr
, "\tfirst_gp_reg_save = %5d\n", info
->first_gp_reg_save
);
18016 if (info
->first_fp_reg_save
!= 64)
18017 fprintf (stderr
, "\tfirst_fp_reg_save = %5d\n", info
->first_fp_reg_save
);
18019 if (info
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
)
18020 fprintf (stderr
, "\tfirst_altivec_reg_save = %5d\n",
18021 info
->first_altivec_reg_save
);
18023 if (info
->lr_save_p
)
18024 fprintf (stderr
, "\tlr_save_p = %5d\n", info
->lr_save_p
);
18026 if (info
->cr_save_p
)
18027 fprintf (stderr
, "\tcr_save_p = %5d\n", info
->cr_save_p
);
18029 if (info
->vrsave_mask
)
18030 fprintf (stderr
, "\tvrsave_mask = 0x%x\n", info
->vrsave_mask
);
18033 fprintf (stderr
, "\tpush_p = %5d\n", info
->push_p
);
18036 fprintf (stderr
, "\tcalls_p = %5d\n", info
->calls_p
);
18038 if (info
->gp_save_offset
)
18039 fprintf (stderr
, "\tgp_save_offset = %5d\n", info
->gp_save_offset
);
18041 if (info
->fp_save_offset
)
18042 fprintf (stderr
, "\tfp_save_offset = %5d\n", info
->fp_save_offset
);
18044 if (info
->altivec_save_offset
)
18045 fprintf (stderr
, "\taltivec_save_offset = %5d\n",
18046 info
->altivec_save_offset
);
18048 if (info
->spe_gp_save_offset
)
18049 fprintf (stderr
, "\tspe_gp_save_offset = %5d\n",
18050 info
->spe_gp_save_offset
);
18052 if (info
->vrsave_save_offset
)
18053 fprintf (stderr
, "\tvrsave_save_offset = %5d\n",
18054 info
->vrsave_save_offset
);
18056 if (info
->lr_save_offset
)
18057 fprintf (stderr
, "\tlr_save_offset = %5d\n", info
->lr_save_offset
);
18059 if (info
->cr_save_offset
)
18060 fprintf (stderr
, "\tcr_save_offset = %5d\n", info
->cr_save_offset
);
18062 if (info
->varargs_save_offset
)
18063 fprintf (stderr
, "\tvarargs_save_offset = %5d\n", info
->varargs_save_offset
);
18065 if (info
->total_size
)
18066 fprintf (stderr
, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
18069 if (info
->vars_size
)
18070 fprintf (stderr
, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
18073 if (info
->parm_size
)
18074 fprintf (stderr
, "\tparm_size = %5d\n", info
->parm_size
);
18076 if (info
->fixed_size
)
18077 fprintf (stderr
, "\tfixed_size = %5d\n", info
->fixed_size
);
18080 fprintf (stderr
, "\tgp_size = %5d\n", info
->gp_size
);
18082 if (info
->spe_gp_size
)
18083 fprintf (stderr
, "\tspe_gp_size = %5d\n", info
->spe_gp_size
);
18086 fprintf (stderr
, "\tfp_size = %5d\n", info
->fp_size
);
18088 if (info
->altivec_size
)
18089 fprintf (stderr
, "\taltivec_size = %5d\n", info
->altivec_size
);
18091 if (info
->vrsave_size
)
18092 fprintf (stderr
, "\tvrsave_size = %5d\n", info
->vrsave_size
);
18094 if (info
->altivec_padding_size
)
18095 fprintf (stderr
, "\taltivec_padding_size= %5d\n",
18096 info
->altivec_padding_size
);
18098 if (info
->spe_padding_size
)
18099 fprintf (stderr
, "\tspe_padding_size = %5d\n",
18100 info
->spe_padding_size
);
18103 fprintf (stderr
, "\tcr_size = %5d\n", info
->cr_size
);
18105 if (info
->save_size
)
18106 fprintf (stderr
, "\tsave_size = %5d\n", info
->save_size
);
18108 if (info
->reg_size
!= 4)
18109 fprintf (stderr
, "\treg_size = %5d\n", info
->reg_size
);
18111 fprintf (stderr
, "\tsave-strategy = %04x\n", info
->savres_strategy
);
18113 fprintf (stderr
, "\n");
18117 rs6000_return_addr (int count
, rtx frame
)
18119 /* Currently we don't optimize very well between prolog and body
18120 code and for PIC code the code can be actually quite bad, so
18121 don't try to be too clever here. */
18122 if (count
!= 0 || (DEFAULT_ABI
!= ABI_AIX
&& flag_pic
))
18124 cfun
->machine
->ra_needs_full_frame
= 1;
18131 plus_constant (copy_to_reg
18132 (gen_rtx_MEM (Pmode
,
18133 memory_address (Pmode
, frame
))),
18134 RETURN_ADDRESS_OFFSET
)));
18137 cfun
->machine
->ra_need_lr
= 1;
18138 return get_hard_reg_initial_val (Pmode
, LR_REGNO
);
18141 /* Say whether a function is a candidate for sibcall handling or not. */
18144 rs6000_function_ok_for_sibcall (tree decl
, tree exp
)
18149 fntype
= TREE_TYPE (decl
);
18151 fntype
= TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp
)));
18153 /* We can't do it if the called function has more vector parameters
18154 than the current function; there's nowhere to put the VRsave code. */
18155 if (TARGET_ALTIVEC_ABI
18156 && TARGET_ALTIVEC_VRSAVE
18157 && !(decl
&& decl
== current_function_decl
))
18159 function_args_iterator args_iter
;
18163 /* Functions with vector parameters are required to have a
18164 prototype, so the argument type info must be available
18166 FOREACH_FUNCTION_ARGS(fntype
, type
, args_iter
)
18167 if (TREE_CODE (type
) == VECTOR_TYPE
18168 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
18171 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl
), type
, args_iter
)
18172 if (TREE_CODE (type
) == VECTOR_TYPE
18173 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
18180 /* Under the AIX ABI we can't allow calls to non-local functions,
18181 because the callee may have a different TOC pointer to the
18182 caller and there's no way to ensure we restore the TOC when we
18183 return. With the secure-plt SYSV ABI we can't make non-local
18184 calls when -fpic/PIC because the plt call stubs use r30. */
18185 if (DEFAULT_ABI
== ABI_DARWIN
18186 || (DEFAULT_ABI
== ABI_AIX
18188 && !DECL_EXTERNAL (decl
)
18189 && (*targetm
.binds_local_p
) (decl
))
18190 || (DEFAULT_ABI
== ABI_V4
18191 && (!TARGET_SECURE_PLT
18194 && (*targetm
.binds_local_p
) (decl
)))))
18196 tree attr_list
= TYPE_ATTRIBUTES (fntype
);
18198 if (!lookup_attribute ("longcall", attr_list
)
18199 || lookup_attribute ("shortcall", attr_list
))
18206 /* NULL if INSN insn is valid within a low-overhead loop.
18207 Otherwise return why doloop cannot be applied.
18208 PowerPC uses the COUNT register for branch on table instructions. */
18210 static const char *
18211 rs6000_invalid_within_doloop (const_rtx insn
)
18214 return "Function call in the loop.";
18217 && (GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
18218 || GET_CODE (PATTERN (insn
)) == ADDR_VEC
))
18219 return "Computed branch in the loop.";
18225 rs6000_ra_ever_killed (void)
18231 if (cfun
->is_thunk
)
18234 if (cfun
->machine
->lr_save_state
)
18235 return cfun
->machine
->lr_save_state
- 1;
18237 /* regs_ever_live has LR marked as used if any sibcalls are present,
18238 but this should not force saving and restoring in the
18239 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
18240 clobbers LR, so that is inappropriate. */
18242 /* Also, the prologue can generate a store into LR that
18243 doesn't really count, like this:
18246 bcl to set PIC register
18250 When we're called from the epilogue, we need to avoid counting
18251 this as a store. */
18253 push_topmost_sequence ();
18254 top
= get_insns ();
18255 pop_topmost_sequence ();
18256 reg
= gen_rtx_REG (Pmode
, LR_REGNO
);
18258 for (insn
= NEXT_INSN (top
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
18264 if (!SIBLING_CALL_P (insn
))
18267 else if (find_regno_note (insn
, REG_INC
, LR_REGNO
))
18269 else if (set_of (reg
, insn
) != NULL_RTX
18270 && !prologue_epilogue_contains (insn
))
18277 /* Emit instructions needed to load the TOC register.
18278 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
18279 a constant pool; or for SVR4 -fpic. */
18282 rs6000_emit_load_toc_table (int fromprolog
)
18285 dest
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
18287 if (TARGET_ELF
&& TARGET_SECURE_PLT
&& DEFAULT_ABI
!= ABI_AIX
&& flag_pic
)
18290 rtx lab
, tmp1
, tmp2
, got
;
18292 lab
= gen_label_rtx ();
18293 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (lab
));
18294 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
18296 got
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
18298 got
= rs6000_got_sym ();
18299 tmp1
= tmp2
= dest
;
18302 tmp1
= gen_reg_rtx (Pmode
);
18303 tmp2
= gen_reg_rtx (Pmode
);
18305 emit_insn (gen_load_toc_v4_PIC_1 (lab
));
18306 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
18307 emit_insn (gen_load_toc_v4_PIC_3b (tmp2
, tmp1
, got
, lab
));
18308 emit_insn (gen_load_toc_v4_PIC_3c (dest
, tmp2
, got
, lab
));
18310 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
18312 emit_insn (gen_load_toc_v4_pic_si ());
18313 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
18315 else if (TARGET_ELF
&& DEFAULT_ABI
!= ABI_AIX
&& flag_pic
== 2)
18318 rtx temp0
= (fromprolog
18319 ? gen_rtx_REG (Pmode
, 0)
18320 : gen_reg_rtx (Pmode
));
18326 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
18327 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
18329 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
18330 symL
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
18332 emit_insn (gen_load_toc_v4_PIC_1 (symF
));
18333 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
18334 emit_insn (gen_load_toc_v4_PIC_2 (temp0
, dest
, symL
, symF
));
18340 tocsym
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
18341 lab
= gen_label_rtx ();
18342 emit_insn (gen_load_toc_v4_PIC_1b (tocsym
, lab
));
18343 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
18344 if (TARGET_LINK_STACK
)
18345 emit_insn (gen_addsi3 (dest
, dest
, GEN_INT (4)));
18346 emit_move_insn (temp0
, gen_rtx_MEM (Pmode
, dest
));
18348 emit_insn (gen_addsi3 (dest
, temp0
, dest
));
18350 else if (TARGET_ELF
&& !TARGET_AIX
&& flag_pic
== 0 && TARGET_MINIMAL_TOC
)
18352 /* This is for AIX code running in non-PIC ELF32. */
18355 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
18356 realsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
18358 emit_insn (gen_elf_high (dest
, realsym
));
18359 emit_insn (gen_elf_low (dest
, dest
, realsym
));
18363 gcc_assert (DEFAULT_ABI
== ABI_AIX
);
18366 emit_insn (gen_load_toc_aix_si (dest
));
18368 emit_insn (gen_load_toc_aix_di (dest
));
18372 /* Emit instructions to restore the link register after determining where
18373 its value has been stored. */
18376 rs6000_emit_eh_reg_restore (rtx source
, rtx scratch
)
18378 rs6000_stack_t
*info
= rs6000_stack_info ();
18381 operands
[0] = source
;
18382 operands
[1] = scratch
;
18384 if (info
->lr_save_p
)
18386 rtx frame_rtx
= stack_pointer_rtx
;
18387 HOST_WIDE_INT sp_offset
= 0;
18390 if (frame_pointer_needed
18391 || cfun
->calls_alloca
18392 || info
->total_size
> 32767)
18394 tmp
= gen_frame_mem (Pmode
, frame_rtx
);
18395 emit_move_insn (operands
[1], tmp
);
18396 frame_rtx
= operands
[1];
18398 else if (info
->push_p
)
18399 sp_offset
= info
->total_size
;
18401 tmp
= plus_constant (frame_rtx
, info
->lr_save_offset
+ sp_offset
);
18402 tmp
= gen_frame_mem (Pmode
, tmp
);
18403 emit_move_insn (tmp
, operands
[0]);
18406 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
), operands
[0]);
18408 /* Freeze lr_save_p. We've just emitted rtl that depends on the
18409 state of lr_save_p so any change from here on would be a bug. In
18410 particular, stop rs6000_ra_ever_killed from considering the SET
18411 of lr we may have added just above. */
18412 cfun
->machine
->lr_save_state
= info
->lr_save_p
+ 1;
18415 static GTY(()) alias_set_type set
= -1;
18418 get_TOC_alias_set (void)
18421 set
= new_alias_set ();
18425 /* This returns nonzero if the current function uses the TOC. This is
18426 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
18427 is generated by the ABI_V4 load_toc_* patterns. */
18434 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
18437 rtx pat
= PATTERN (insn
);
18440 if (GET_CODE (pat
) == PARALLEL
)
18441 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
18443 rtx sub
= XVECEXP (pat
, 0, i
);
18444 if (GET_CODE (sub
) == USE
)
18446 sub
= XEXP (sub
, 0);
18447 if (GET_CODE (sub
) == UNSPEC
18448 && XINT (sub
, 1) == UNSPEC_TOC
)
18458 create_TOC_reference (rtx symbol
, rtx largetoc_reg
)
18460 rtx tocrel
, tocreg
;
18462 if (TARGET_DEBUG_ADDR
)
18464 if (GET_CODE (symbol
) == SYMBOL_REF
)
18465 fprintf (stderr
, "\ncreate_TOC_reference, (symbol_ref %s)\n",
18469 fprintf (stderr
, "\ncreate_TOC_reference, code %s:\n",
18470 GET_RTX_NAME (GET_CODE (symbol
)));
18471 debug_rtx (symbol
);
18475 if (!can_create_pseudo_p ())
18476 df_set_regs_ever_live (TOC_REGISTER
, true);
18478 tocrel
= gen_rtx_CONST (Pmode
,
18479 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, symbol
),
18481 tocreg
= gen_rtx_REG (Pmode
, TOC_REGISTER
);
18482 if (TARGET_CMODEL
!= CMODEL_SMALL
)
18484 rtx hi
= gen_rtx_CONST (Pmode
,
18485 gen_rtx_PLUS (Pmode
, tocreg
,
18486 gen_rtx_HIGH (Pmode
, tocrel
)));
18487 if (largetoc_reg
!= NULL
)
18489 emit_move_insn (largetoc_reg
, hi
);
18492 return gen_rtx_LO_SUM (Pmode
, hi
, copy_rtx (tocrel
));
18495 return gen_rtx_PLUS (Pmode
, tocreg
, tocrel
);
18498 /* Issue assembly directives that create a reference to the given DWARF
18499 FRAME_TABLE_LABEL from the current function section. */
18501 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label
)
18503 fprintf (asm_out_file
, "\t.ref %s\n",
18504 TARGET_STRIP_NAME_ENCODING (frame_table_label
));
18507 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
18508 and the change to the stack pointer. */
18511 rs6000_emit_stack_tie (void)
18513 rtx mem
= gen_frame_mem (BLKmode
,
18514 gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
));
18516 emit_insn (gen_stack_tie (mem
));
18519 /* Emit the correct code for allocating stack space, as insns.
18520 If COPY_REG, make sure a copy of the old frame is left there.
18521 The generated code may use hard register 0 as a temporary. */
18524 rs6000_emit_allocate_stack (HOST_WIDE_INT size
, rtx copy_reg
)
18527 rtx stack_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
18528 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
18529 rtx todec
= gen_int_mode (-size
, Pmode
);
18532 if (INTVAL (todec
) != -size
)
18534 warning (0, "stack frame too large");
18535 emit_insn (gen_trap ());
18539 if (crtl
->limit_stack
)
18541 if (REG_P (stack_limit_rtx
)
18542 && REGNO (stack_limit_rtx
) > 1
18543 && REGNO (stack_limit_rtx
) <= 31)
18545 emit_insn (gen_add3_insn (tmp_reg
, stack_limit_rtx
, GEN_INT (size
)));
18546 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
18549 else if (GET_CODE (stack_limit_rtx
) == SYMBOL_REF
18551 && DEFAULT_ABI
== ABI_V4
)
18553 rtx toload
= gen_rtx_CONST (VOIDmode
,
18554 gen_rtx_PLUS (Pmode
,
18558 emit_insn (gen_elf_high (tmp_reg
, toload
));
18559 emit_insn (gen_elf_low (tmp_reg
, tmp_reg
, toload
));
18560 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
18564 warning (0, "stack limit expression is not supported");
18568 emit_move_insn (copy_reg
, stack_reg
);
18572 /* Need a note here so that try_split doesn't get confused. */
18573 if (get_last_insn () == NULL_RTX
)
18574 emit_note (NOTE_INSN_DELETED
);
18575 insn
= emit_move_insn (tmp_reg
, todec
);
18576 try_split (PATTERN (insn
), insn
, 0);
18580 insn
= emit_insn (TARGET_32BIT
18581 ? gen_movsi_update_stack (stack_reg
, stack_reg
,
18583 : gen_movdi_di_update_stack (stack_reg
, stack_reg
,
18584 todec
, stack_reg
));
18585 /* Since we didn't use gen_frame_mem to generate the MEM, grab
18586 it now and set the alias set/attributes. The above gen_*_update
18587 calls will generate a PARALLEL with the MEM set being the first
18589 par
= PATTERN (insn
);
18590 gcc_assert (GET_CODE (par
) == PARALLEL
);
18591 set
= XVECEXP (par
, 0, 0);
18592 gcc_assert (GET_CODE (set
) == SET
);
18593 mem
= SET_DEST (set
);
18594 gcc_assert (MEM_P (mem
));
18595 MEM_NOTRAP_P (mem
) = 1;
18596 set_mem_alias_set (mem
, get_frame_alias_set ());
18598 RTX_FRAME_RELATED_P (insn
) = 1;
18599 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
18600 gen_rtx_SET (VOIDmode
, stack_reg
,
18601 gen_rtx_PLUS (Pmode
, stack_reg
,
18602 GEN_INT (-size
))));
18605 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
18607 #if PROBE_INTERVAL > 32768
18608 #error Cannot use indexed addressing mode for stack probing
18611 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
18612 inclusive. These are offsets from the current stack pointer. */
18615 rs6000_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
18617 /* See if we have a constant small number of probes to generate. If so,
18618 that's the easy case. */
18619 if (first
+ size
<= 32768)
18623 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
18624 it exceeds SIZE. If only one probe is needed, this will not
18625 generate any code. Then probe at FIRST + SIZE. */
18626 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
18627 emit_stack_probe (plus_constant (stack_pointer_rtx
, -(first
+ i
)));
18629 emit_stack_probe (plus_constant (stack_pointer_rtx
, -(first
+ size
)));
18632 /* Otherwise, do the same as above, but in a loop. Note that we must be
18633 extra careful with variables wrapping around because we might be at
18634 the very top (or the very bottom) of the address space and we have
18635 to be able to handle this case properly; in particular, we use an
18636 equality test for the loop condition. */
18639 HOST_WIDE_INT rounded_size
;
18640 rtx r12
= gen_rtx_REG (Pmode
, 12);
18641 rtx r0
= gen_rtx_REG (Pmode
, 0);
18643 /* Sanity check for the addressing mode we're going to use. */
18644 gcc_assert (first
<= 32768);
18646 /* Step 1: round SIZE to the previous multiple of the interval. */
18648 rounded_size
= size
& -PROBE_INTERVAL
;
18651 /* Step 2: compute initial and final value of the loop counter. */
18653 /* TEST_ADDR = SP + FIRST. */
18654 emit_insn (gen_rtx_SET (VOIDmode
, r12
,
18655 plus_constant (stack_pointer_rtx
, -first
)));
18657 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
18658 if (rounded_size
> 32768)
18660 emit_move_insn (r0
, GEN_INT (-rounded_size
));
18661 emit_insn (gen_rtx_SET (VOIDmode
, r0
,
18662 gen_rtx_PLUS (Pmode
, r12
, r0
)));
18665 emit_insn (gen_rtx_SET (VOIDmode
, r0
,
18666 plus_constant (r12
, -rounded_size
)));
18669 /* Step 3: the loop
18671 while (TEST_ADDR != LAST_ADDR)
18673 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
18677 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
18678 until it is equal to ROUNDED_SIZE. */
18681 emit_insn (gen_probe_stack_rangedi (r12
, r12
, r0
));
18683 emit_insn (gen_probe_stack_rangesi (r12
, r12
, r0
));
18686 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
18687 that SIZE is equal to ROUNDED_SIZE. */
18689 if (size
!= rounded_size
)
18690 emit_stack_probe (plus_constant (r12
, rounded_size
- size
));
18694 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
18695 absolute addresses. */
18698 output_probe_stack_range (rtx reg1
, rtx reg2
)
18700 static int labelno
= 0;
18701 char loop_lab
[32], end_lab
[32];
18704 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
18705 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
18707 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
18709 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
18713 output_asm_insn ("{cmp|cmpd} 0,%0,%1", xops
);
18715 output_asm_insn ("{cmp|cmpw} 0,%0,%1", xops
);
18717 fputs ("\tbeq 0,", asm_out_file
);
18718 assemble_name_raw (asm_out_file
, end_lab
);
18719 fputc ('\n', asm_out_file
);
18721 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
18722 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
18723 output_asm_insn ("{cal %0,%1(%0)|addi %0,%0,%1}", xops
);
18725 /* Probe at TEST_ADDR and branch. */
18726 xops
[1] = gen_rtx_REG (Pmode
, 0);
18727 output_asm_insn ("{st|stw} %1,0(%0)", xops
);
18728 fprintf (asm_out_file
, "\tb ");
18729 assemble_name_raw (asm_out_file
, loop_lab
);
18730 fputc ('\n', asm_out_file
);
18732 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
18737 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
18738 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
18739 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
18740 deduce these equivalences by itself so it wasn't necessary to hold
18741 its hand so much. */
18744 rs6000_frame_related (rtx insn
, rtx reg
, HOST_WIDE_INT val
,
18745 rtx reg2
, rtx rreg
)
18749 /* copy_rtx will not make unique copies of registers, so we need to
18750 ensure we don't have unwanted sharing here. */
18752 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
18755 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
18757 real
= copy_rtx (PATTERN (insn
));
18759 if (reg2
!= NULL_RTX
)
18760 real
= replace_rtx (real
, reg2
, rreg
);
18762 real
= replace_rtx (real
, reg
,
18763 gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
,
18764 STACK_POINTER_REGNUM
),
18767 /* We expect that 'real' is either a SET or a PARALLEL containing
18768 SETs (and possibly other stuff). In a PARALLEL, all the SETs
18769 are important so they all have to be marked RTX_FRAME_RELATED_P. */
18771 if (GET_CODE (real
) == SET
)
18775 temp
= simplify_rtx (SET_SRC (set
));
18777 SET_SRC (set
) = temp
;
18778 temp
= simplify_rtx (SET_DEST (set
));
18780 SET_DEST (set
) = temp
;
18781 if (GET_CODE (SET_DEST (set
)) == MEM
)
18783 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
18785 XEXP (SET_DEST (set
), 0) = temp
;
18792 gcc_assert (GET_CODE (real
) == PARALLEL
);
18793 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
18794 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
18796 rtx set
= XVECEXP (real
, 0, i
);
18798 temp
= simplify_rtx (SET_SRC (set
));
18800 SET_SRC (set
) = temp
;
18801 temp
= simplify_rtx (SET_DEST (set
));
18803 SET_DEST (set
) = temp
;
18804 if (GET_CODE (SET_DEST (set
)) == MEM
)
18806 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
18808 XEXP (SET_DEST (set
), 0) = temp
;
18810 RTX_FRAME_RELATED_P (set
) = 1;
18814 RTX_FRAME_RELATED_P (insn
) = 1;
18815 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, real
);
18820 /* Returns an insn that has a vrsave set operation with the
18821 appropriate CLOBBERs. */
18824 generate_set_vrsave (rtx reg
, rs6000_stack_t
*info
, int epiloguep
)
18827 rtx insn
, clobs
[TOTAL_ALTIVEC_REGS
+ 1];
18828 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
18831 = gen_rtx_SET (VOIDmode
,
18833 gen_rtx_UNSPEC_VOLATILE (SImode
,
18834 gen_rtvec (2, reg
, vrsave
),
18835 UNSPECV_SET_VRSAVE
));
18839 /* We need to clobber the registers in the mask so the scheduler
18840 does not move sets to VRSAVE before sets of AltiVec registers.
18842 However, if the function receives nonlocal gotos, reload will set
18843 all call saved registers live. We will end up with:
18845 (set (reg 999) (mem))
18846 (parallel [ (set (reg vrsave) (unspec blah))
18847 (clobber (reg 999))])
18849 The clobber will cause the store into reg 999 to be dead, and
18850 flow will attempt to delete an epilogue insn. In this case, we
18851 need an unspec use/set of the register. */
18853 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
18854 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
18856 if (!epiloguep
|| call_used_regs
[i
])
18857 clobs
[nclobs
++] = gen_rtx_CLOBBER (VOIDmode
,
18858 gen_rtx_REG (V4SImode
, i
));
18861 rtx reg
= gen_rtx_REG (V4SImode
, i
);
18864 = gen_rtx_SET (VOIDmode
,
18866 gen_rtx_UNSPEC (V4SImode
,
18867 gen_rtvec (1, reg
), 27));
18871 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nclobs
));
18873 for (i
= 0; i
< nclobs
; ++i
)
18874 XVECEXP (insn
, 0, i
) = clobs
[i
];
18879 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
18880 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
18883 emit_frame_save (rtx frame_reg
, rtx frame_ptr
, enum machine_mode mode
,
18884 unsigned int regno
, int offset
, HOST_WIDE_INT total_size
)
18886 rtx reg
, offset_rtx
, insn
, mem
, addr
, int_rtx
;
18887 rtx replacea
, replaceb
;
18889 int_rtx
= GEN_INT (offset
);
18891 /* Some cases that need register indexed addressing. */
18892 if ((TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
18893 || (TARGET_VSX
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
18894 || (TARGET_E500_DOUBLE
&& mode
== DFmode
)
18896 && SPE_VECTOR_MODE (mode
)
18897 && !SPE_CONST_OFFSET_OK (offset
)))
18899 /* Whomever calls us must make sure r11 is available in the
18900 flow path of instructions in the prologue. */
18901 offset_rtx
= gen_rtx_REG (Pmode
, 11);
18902 emit_move_insn (offset_rtx
, int_rtx
);
18904 replacea
= offset_rtx
;
18905 replaceb
= int_rtx
;
18909 offset_rtx
= int_rtx
;
18910 replacea
= NULL_RTX
;
18911 replaceb
= NULL_RTX
;
18914 reg
= gen_rtx_REG (mode
, regno
);
18915 addr
= gen_rtx_PLUS (Pmode
, frame_reg
, offset_rtx
);
18916 mem
= gen_frame_mem (mode
, addr
);
18918 insn
= emit_move_insn (mem
, reg
);
18920 return rs6000_frame_related (insn
, frame_ptr
, total_size
, replacea
, replaceb
);
18923 /* Emit an offset memory reference suitable for a frame store, while
18924 converting to a valid addressing mode. */
18927 gen_frame_mem_offset (enum machine_mode mode
, rtx reg
, int offset
)
18929 rtx int_rtx
, offset_rtx
;
18931 int_rtx
= GEN_INT (offset
);
18933 if ((TARGET_SPE_ABI
&& SPE_VECTOR_MODE (mode
))
18934 || (TARGET_E500_DOUBLE
&& mode
== DFmode
))
18936 offset_rtx
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
18937 emit_move_insn (offset_rtx
, int_rtx
);
18940 offset_rtx
= int_rtx
;
18942 return gen_frame_mem (mode
, gen_rtx_PLUS (Pmode
, reg
, offset_rtx
));
18945 /* Look for user-defined global regs. We should not save and restore these,
18946 and cannot use stmw/lmw if there are any in its range. */
18949 no_global_regs_above (int first
, bool gpr
)
18952 int last
= gpr
? 32 : 64;
18953 for (i
= first
; i
< last
; i
++)
18954 if (global_regs
[i
])
18959 #ifndef TARGET_FIX_AND_CONTINUE
18960 #define TARGET_FIX_AND_CONTINUE 0
18963 /* It's really GPR 13 and FPR 14, but we need the smaller of the two. */
18964 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
18965 #define LAST_SAVRES_REGISTER 31
18966 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
18968 static GTY(()) rtx savres_routine_syms
[N_SAVRES_REGISTERS
][8];
18970 /* Temporary holding space for an out-of-line register save/restore
18972 static char savres_routine_name
[30];
18974 /* Return the name for an out-of-line register save/restore routine.
18975 We are saving/restoring GPRs if GPR is true. */
18978 rs6000_savres_routine_name (rs6000_stack_t
*info
, int regno
,
18979 bool savep
, bool gpr
, bool lr
)
18981 const char *prefix
= "";
18982 const char *suffix
= "";
18984 /* Different targets are supposed to define
18985 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
18986 routine name could be defined with:
18988 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
18990 This is a nice idea in practice, but in reality, things are
18991 complicated in several ways:
18993 - ELF targets have save/restore routines for GPRs.
18995 - SPE targets use different prefixes for 32/64-bit registers, and
18996 neither of them fit neatly in the FOO_{PREFIX,SUFFIX} regimen.
18998 - PPC64 ELF targets have routines for save/restore of GPRs that
18999 differ in what they do with the link register, so having a set
19000 prefix doesn't work. (We only use one of the save routines at
19001 the moment, though.)
19003 - PPC32 elf targets have "exit" versions of the restore routines
19004 that restore the link register and can save some extra space.
19005 These require an extra suffix. (There are also "tail" versions
19006 of the restore routines and "GOT" versions of the save routines,
19007 but we don't generate those at present. Same problems apply,
19010 We deal with all this by synthesizing our own prefix/suffix and
19011 using that for the simple sprintf call shown above. */
19014 /* No floating point saves on the SPE. */
19018 prefix
= info
->spe_64bit_regs_used
? "_save64gpr_" : "_save32gpr_";
19020 prefix
= info
->spe_64bit_regs_used
? "_rest64gpr_" : "_rest32gpr_";
19025 else if (DEFAULT_ABI
== ABI_V4
)
19031 prefix
= savep
? "_savegpr_" : "_restgpr_";
19033 prefix
= savep
? "_savefpr_" : "_restfpr_";
19038 else if (DEFAULT_ABI
== ABI_AIX
)
19040 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
19041 /* No out-of-line save/restore routines for GPRs on AIX. */
19042 gcc_assert (!TARGET_AIX
|| !gpr
);
19048 ? (lr
? "_savegpr0_" : "_savegpr1_")
19049 : (lr
? "_restgpr0_" : "_restgpr1_"));
19050 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
19052 prefix
= (savep
? "_savefpr_" : "_restfpr_");
19056 prefix
= savep
? SAVE_FP_PREFIX
: RESTORE_FP_PREFIX
;
19057 suffix
= savep
? SAVE_FP_SUFFIX
: RESTORE_FP_SUFFIX
;
19061 if (DEFAULT_ABI
== ABI_DARWIN
)
19063 /* The Darwin approach is (slightly) different, in order to be
19064 compatible with code generated by the system toolchain. There is a
19065 single symbol for the start of save sequence, and the code here
19066 embeds an offset into that code on the basis of the first register
19068 prefix
= savep
? "save" : "rest" ;
19070 sprintf (savres_routine_name
, "*%sGPR%s%s%.0d ; %s r%d-r31",
19071 prefix
, (lr
? "x" : ""), (regno
== 13 ? "" : "+"),
19072 (regno
-13) * 4, prefix
, regno
);
19074 sprintf (savres_routine_name
, "*%sFP%s%.0d ; %s f%d-f31",
19075 prefix
, (regno
== 14 ? "" : "+"), (regno
-14) * 4, prefix
, regno
);
19078 sprintf (savres_routine_name
, "%s%d%s", prefix
, regno
, suffix
);
19080 return savres_routine_name
;
19083 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
19084 We are saving/restoring GPRs if GPR is true. */
19087 rs6000_savres_routine_sym (rs6000_stack_t
*info
, bool savep
,
19090 int regno
= gpr
? info
->first_gp_reg_save
: (info
->first_fp_reg_save
- 32);
19092 int select
= ((savep
? 1 : 0) << 2
19094 /* On the SPE, we never have any FPRs, but we do have
19095 32/64-bit versions of the routines. */
19096 ? (info
->spe_64bit_regs_used
? 1 : 0)
19097 : (gpr
? 1 : 0)) << 1)
19100 /* Don't generate bogus routine names. */
19101 gcc_assert (FIRST_SAVRES_REGISTER
<= regno
19102 && regno
<= LAST_SAVRES_REGISTER
);
19104 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
];
19110 name
= rs6000_savres_routine_name (info
, regno
, savep
, gpr
, lr
);
19112 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
]
19113 = gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
19114 SYMBOL_REF_FLAGS (sym
) |= SYMBOL_FLAG_FUNCTION
;
19120 /* Emit a sequence of insns, including a stack tie if needed, for
19121 resetting the stack pointer. If SAVRES is true, then don't reset the
19122 stack pointer, but move the base of the frame into r11 for use by
19123 out-of-line register restore routines. */
19126 rs6000_emit_stack_reset (rs6000_stack_t
*info
,
19127 rtx sp_reg_rtx
, rtx frame_reg_rtx
,
19128 int sp_offset
, bool savres
)
19130 /* This blockage is needed so that sched doesn't decide to move
19131 the sp change before the register restores. */
19132 if (DEFAULT_ABI
== ABI_V4
19134 && info
->spe_64bit_regs_used
!= 0
19135 && info
->first_gp_reg_save
!= 32))
19136 rs6000_emit_stack_tie ();
19138 if (frame_reg_rtx
!= sp_reg_rtx
)
19140 if (sp_offset
!= 0)
19142 rtx dest_reg
= savres
? gen_rtx_REG (Pmode
, 11) : sp_reg_rtx
;
19143 rtx insn
= emit_insn (gen_add3_insn (dest_reg
, frame_reg_rtx
,
19144 GEN_INT (sp_offset
)));
19149 return emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
19151 else if (sp_offset
!= 0)
19153 /* If we are restoring registers out-of-line, we will be using the
19154 "exit" variants of the restore routines, which will reset the
19155 stack for us. But we do need to point r11 into the right place
19156 for those routines. */
19157 rtx dest_reg
= (savres
19158 ? gen_rtx_REG (Pmode
, 11)
19161 rtx insn
= emit_insn (gen_add3_insn (dest_reg
, sp_reg_rtx
,
19162 GEN_INT (sp_offset
)));
19169 /* Construct a parallel rtx describing the effect of a call to an
19170 out-of-line register save/restore routine, and emit the insn
19171 or jump_insn as appropriate. */
19174 rs6000_emit_savres_rtx (rs6000_stack_t
*info
,
19175 rtx frame_reg_rtx
, int save_area_offset
,
19176 enum machine_mode reg_mode
,
19177 bool savep
, bool gpr
, bool lr
)
19180 int offset
, start_reg
, end_reg
, n_regs
, use_reg
;
19181 int reg_size
= GET_MODE_SIZE (reg_mode
);
19188 ? info
->first_gp_reg_save
19189 : info
->first_fp_reg_save
);
19190 end_reg
= gpr
? 32 : 64;
19191 n_regs
= end_reg
- start_reg
;
19192 p
= rtvec_alloc ((lr
? 4 : 3) + n_regs
);
19195 RTVEC_ELT (p
, offset
++) = ret_rtx
;
19197 RTVEC_ELT (p
, offset
++)
19198 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
19200 sym
= rs6000_savres_routine_sym (info
, savep
, gpr
, lr
);
19201 RTVEC_ELT (p
, offset
++) = gen_rtx_USE (VOIDmode
, sym
);
19202 use_reg
= DEFAULT_ABI
== ABI_AIX
? (gpr
&& !lr
? 12 : 1)
19203 : DEFAULT_ABI
== ABI_DARWIN
&& !gpr
? 1
19205 RTVEC_ELT (p
, offset
++)
19206 = gen_rtx_USE (VOIDmode
,
19207 gen_rtx_REG (Pmode
, use_reg
));
19209 for (i
= 0; i
< end_reg
- start_reg
; i
++)
19211 rtx addr
, reg
, mem
;
19212 reg
= gen_rtx_REG (reg_mode
, start_reg
+ i
);
19213 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
19214 GEN_INT (save_area_offset
+ reg_size
*i
));
19215 mem
= gen_frame_mem (reg_mode
, addr
);
19217 RTVEC_ELT (p
, i
+ offset
) = gen_rtx_SET (VOIDmode
,
19219 savep
? reg
: mem
);
19224 rtx addr
, reg
, mem
;
19225 reg
= gen_rtx_REG (Pmode
, 0);
19226 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
19227 GEN_INT (info
->lr_save_offset
));
19228 mem
= gen_frame_mem (Pmode
, addr
);
19229 RTVEC_ELT (p
, i
+ offset
) = gen_rtx_SET (VOIDmode
, mem
, reg
);
19232 par
= gen_rtx_PARALLEL (VOIDmode
, p
);
19236 insn
= emit_jump_insn (par
);
19237 JUMP_LABEL (insn
) = ret_rtx
;
19240 insn
= emit_insn (par
);
19244 /* Determine whether the gp REG is really used. */
19247 rs6000_reg_live_or_pic_offset_p (int reg
)
19249 /* If the function calls eh_return, claim used all the registers that would
19250 be checked for liveness otherwise. This is required for the PIC offset
19251 register with -mminimal-toc on AIX, as it is advertised as "fixed" for
19252 register allocation purposes in this case. */
19254 return (((crtl
->calls_eh_return
|| df_regs_ever_live_p (reg
))
19255 && (!call_used_regs
[reg
]
19256 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
19257 && !TARGET_SINGLE_PIC_BASE
19258 && TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
19259 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
19260 && !TARGET_SINGLE_PIC_BASE
19261 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
19262 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
))));
19265 /* Emit function prologue as insns. */
19268 rs6000_emit_prologue (void)
19270 rs6000_stack_t
*info
= rs6000_stack_info ();
19271 enum machine_mode reg_mode
= Pmode
;
19272 int reg_size
= TARGET_32BIT
? 4 : 8;
19273 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
19274 rtx frame_ptr_rtx
= gen_rtx_REG (Pmode
, 12);
19275 rtx frame_reg_rtx
= sp_reg_rtx
;
19276 rtx cr_save_rtx
= NULL_RTX
;
19279 int saving_FPRs_inline
;
19280 int saving_GPRs_inline
;
19281 int using_store_multiple
;
19282 int using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
19283 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
19284 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
19285 HOST_WIDE_INT sp_offset
= 0;
19287 if (flag_stack_usage_info
)
19288 current_function_static_stack_size
= info
->total_size
;
19290 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
&& info
->total_size
)
19291 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT
, info
->total_size
);
19293 if (TARGET_FIX_AND_CONTINUE
)
19295 /* gdb on darwin arranges to forward a function from the old
19296 address by modifying the first 5 instructions of the function
19297 to branch to the overriding function. This is necessary to
19298 permit function pointers that point to the old function to
19299 actually forward to the new function. */
19300 emit_insn (gen_nop ());
19301 emit_insn (gen_nop ());
19302 emit_insn (gen_nop ());
19303 emit_insn (gen_nop ());
19304 emit_insn (gen_nop ());
19307 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
19309 reg_mode
= V2SImode
;
19313 strategy
= info
->savres_strategy
;
19314 using_store_multiple
= strategy
& SAVRES_MULTIPLE
;
19315 saving_FPRs_inline
= strategy
& SAVE_INLINE_FPRS
;
19316 saving_GPRs_inline
= strategy
& SAVE_INLINE_GPRS
;
19318 /* For V.4, update stack before we do any saving and set back pointer. */
19319 if (! WORLD_SAVE_P (info
)
19321 && (DEFAULT_ABI
== ABI_V4
19322 || crtl
->calls_eh_return
))
19324 bool need_r11
= (TARGET_SPE
19325 ? (!saving_GPRs_inline
19326 && info
->spe_64bit_regs_used
== 0)
19327 : (!saving_FPRs_inline
|| !saving_GPRs_inline
));
19328 rtx copy_reg
= need_r11
? gen_rtx_REG (Pmode
, 11) : NULL
;
19330 if (info
->total_size
< 32767)
19331 sp_offset
= info
->total_size
;
19333 frame_reg_rtx
= copy_reg
;
19334 else if (info
->cr_save_p
19336 || info
->first_fp_reg_save
< 64
19337 || info
->first_gp_reg_save
< 32
19338 || info
->altivec_size
!= 0
19339 || info
->vrsave_mask
!= 0
19340 || crtl
->calls_eh_return
)
19342 copy_reg
= frame_ptr_rtx
;
19343 frame_reg_rtx
= copy_reg
;
19347 /* The prologue won't be saving any regs so there is no need
19348 to set up a frame register to access any frame save area.
19349 We also won't be using sp_offset anywhere below, but set
19350 the correct value anyway to protect against future
19351 changes to this function. */
19352 sp_offset
= info
->total_size
;
19354 rs6000_emit_allocate_stack (info
->total_size
, copy_reg
);
19355 if (frame_reg_rtx
!= sp_reg_rtx
)
19356 rs6000_emit_stack_tie ();
19359 /* Handle world saves specially here. */
19360 if (WORLD_SAVE_P (info
))
19367 /* save_world expects lr in r0. */
19368 reg0
= gen_rtx_REG (Pmode
, 0);
19369 if (info
->lr_save_p
)
19371 insn
= emit_move_insn (reg0
,
19372 gen_rtx_REG (Pmode
, LR_REGNO
));
19373 RTX_FRAME_RELATED_P (insn
) = 1;
19376 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
19377 assumptions about the offsets of various bits of the stack
19379 gcc_assert (info
->gp_save_offset
== -220
19380 && info
->fp_save_offset
== -144
19381 && info
->lr_save_offset
== 8
19382 && info
->cr_save_offset
== 4
19385 && (!crtl
->calls_eh_return
19386 || info
->ehrd_offset
== -432)
19387 && info
->vrsave_save_offset
== -224
19388 && info
->altivec_save_offset
== -416);
19390 treg
= gen_rtx_REG (SImode
, 11);
19391 emit_move_insn (treg
, GEN_INT (-info
->total_size
));
19393 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
19394 in R11. It also clobbers R12, so beware! */
19396 /* Preserve CR2 for save_world prologues */
19398 sz
+= 32 - info
->first_gp_reg_save
;
19399 sz
+= 64 - info
->first_fp_reg_save
;
19400 sz
+= LAST_ALTIVEC_REGNO
- info
->first_altivec_reg_save
+ 1;
19401 p
= rtvec_alloc (sz
);
19403 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
,
19404 gen_rtx_REG (SImode
,
19406 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
19407 gen_rtx_SYMBOL_REF (Pmode
,
19409 /* We do floats first so that the instruction pattern matches
19411 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
19413 rtx reg
= gen_rtx_REG (((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
19414 ? DFmode
: SFmode
),
19415 info
->first_fp_reg_save
+ i
);
19416 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
19417 GEN_INT (info
->fp_save_offset
19418 + sp_offset
+ 8 * i
));
19419 rtx mem
= gen_frame_mem (((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
19420 ? DFmode
: SFmode
), addr
);
19422 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
19424 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
19426 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
19427 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
19428 GEN_INT (info
->altivec_save_offset
19429 + sp_offset
+ 16 * i
));
19430 rtx mem
= gen_frame_mem (V4SImode
, addr
);
19432 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
19434 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
19436 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
19437 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
19438 GEN_INT (info
->gp_save_offset
19439 + sp_offset
+ reg_size
* i
));
19440 rtx mem
= gen_frame_mem (reg_mode
, addr
);
19442 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
19446 /* CR register traditionally saved as CR2. */
19447 rtx reg
= gen_rtx_REG (reg_mode
, CR2_REGNO
);
19448 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
19449 GEN_INT (info
->cr_save_offset
19451 rtx mem
= gen_frame_mem (reg_mode
, addr
);
19453 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
19455 /* Explain about use of R0. */
19456 if (info
->lr_save_p
)
19458 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
19459 GEN_INT (info
->lr_save_offset
19461 rtx mem
= gen_frame_mem (reg_mode
, addr
);
19463 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg0
);
19465 /* Explain what happens to the stack pointer. */
19467 rtx newval
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
, treg
);
19468 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, sp_reg_rtx
, newval
);
19471 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
19472 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
19473 treg
, GEN_INT (-info
->total_size
));
19474 sp_offset
= info
->total_size
;
19477 /* If we use the link register, get it into r0. */
19478 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
)
19480 rtx addr
, reg
, mem
;
19482 insn
= emit_move_insn (gen_rtx_REG (Pmode
, 0),
19483 gen_rtx_REG (Pmode
, LR_REGNO
));
19484 RTX_FRAME_RELATED_P (insn
) = 1;
19486 if (!(strategy
& (SAVE_NOINLINE_GPRS_SAVES_LR
19487 | SAVE_NOINLINE_FPRS_SAVES_LR
)))
19489 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
19490 GEN_INT (info
->lr_save_offset
+ sp_offset
));
19491 reg
= gen_rtx_REG (Pmode
, 0);
19492 mem
= gen_rtx_MEM (Pmode
, addr
);
19493 /* This should not be of rs6000_sr_alias_set, because of
19494 __builtin_return_address. */
19496 insn
= emit_move_insn (mem
, reg
);
19497 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
19498 NULL_RTX
, NULL_RTX
);
19502 /* If we need to save CR, put it into r12 or r11. */
19503 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
&& frame_reg_rtx
!= frame_ptr_rtx
)
19508 = gen_rtx_REG (SImode
, DEFAULT_ABI
== ABI_AIX
&& !saving_GPRs_inline
19510 insn
= emit_insn (gen_movesi_from_cr (cr_save_rtx
));
19511 RTX_FRAME_RELATED_P (insn
) = 1;
19512 /* Now, there's no way that dwarf2out_frame_debug_expr is going
19513 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
19514 But that's OK. All we have to do is specify that _one_ condition
19515 code register is saved in this stack slot. The thrower's epilogue
19516 will then restore all the call-saved registers.
19517 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
19518 set
= gen_rtx_SET (VOIDmode
, cr_save_rtx
,
19519 gen_rtx_REG (SImode
, CR2_REGNO
));
19520 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
19523 /* Do any required saving of fpr's. If only one or two to save, do
19524 it ourselves. Otherwise, call function. */
19525 if (!WORLD_SAVE_P (info
) && saving_FPRs_inline
)
19528 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
19529 if ((df_regs_ever_live_p (info
->first_fp_reg_save
+i
)
19530 && ! call_used_regs
[info
->first_fp_reg_save
+i
]))
19531 emit_frame_save (frame_reg_rtx
, frame_ptr_rtx
,
19532 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
19534 info
->first_fp_reg_save
+ i
,
19535 info
->fp_save_offset
+ sp_offset
+ 8 * i
,
19538 else if (!WORLD_SAVE_P (info
) && info
->first_fp_reg_save
!= 64)
19540 insn
= rs6000_emit_savres_rtx (info
, frame_reg_rtx
,
19541 info
->fp_save_offset
+ sp_offset
,
19543 /*savep=*/true, /*gpr=*/false,
19545 & SAVE_NOINLINE_FPRS_SAVES_LR
)
19547 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
19548 NULL_RTX
, NULL_RTX
);
19551 /* Save GPRs. This is done as a PARALLEL if we are using
19552 the store-multiple instructions. */
19553 if (!WORLD_SAVE_P (info
)
19555 && info
->spe_64bit_regs_used
!= 0
19556 && info
->first_gp_reg_save
!= 32)
19559 rtx spe_save_area_ptr
;
19560 int save_ptr_to_sp
;
19561 int ool_adjust
= 0;
19563 /* Determine whether we can address all of the registers that need
19564 to be saved with an offset from frame_reg_rtx that fits in
19565 the small const field for SPE memory instructions. */
19566 int spe_regs_addressable
19567 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ sp_offset
19568 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
19569 && saving_GPRs_inline
);
19572 if (spe_regs_addressable
)
19574 spe_save_area_ptr
= frame_reg_rtx
;
19575 save_ptr_to_sp
= info
->total_size
- sp_offset
;
19576 spe_offset
= info
->spe_gp_save_offset
+ sp_offset
;
19580 /* Make r11 point to the start of the SPE save area. We need
19581 to be careful here if r11 is holding the static chain. If
19582 it is, then temporarily save it in r0. */
19585 if (!saving_GPRs_inline
)
19586 ool_adjust
= 8 * (info
->first_gp_reg_save
19587 - (FIRST_SAVRES_REGISTER
+ 1));
19588 offset
= info
->spe_gp_save_offset
+ sp_offset
- ool_adjust
;
19589 spe_save_area_ptr
= gen_rtx_REG (Pmode
, 11);
19590 save_ptr_to_sp
= info
->total_size
- sp_offset
+ offset
;
19593 if (using_static_chain_p
)
19595 rtx r0
= gen_rtx_REG (Pmode
, 0);
19596 gcc_assert (info
->first_gp_reg_save
> 11);
19598 emit_move_insn (r0
, spe_save_area_ptr
);
19600 emit_insn (gen_addsi3 (spe_save_area_ptr
,
19601 frame_reg_rtx
, GEN_INT (offset
)));
19602 if (REGNO (frame_reg_rtx
) == 11)
19603 sp_offset
= -info
->spe_gp_save_offset
+ ool_adjust
;
19606 if (saving_GPRs_inline
)
19608 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
19609 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
19611 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
19612 rtx offset
, addr
, mem
;
19614 /* We're doing all this to ensure that the offset fits into
19615 the immediate offset of 'evstdd'. */
19616 gcc_assert (SPE_CONST_OFFSET_OK (reg_size
* i
+ spe_offset
));
19618 offset
= GEN_INT (reg_size
* i
+ spe_offset
);
19619 addr
= gen_rtx_PLUS (Pmode
, spe_save_area_ptr
, offset
);
19620 mem
= gen_rtx_MEM (V2SImode
, addr
);
19622 insn
= emit_move_insn (mem
, reg
);
19624 rs6000_frame_related (insn
,
19625 spe_save_area_ptr
, save_ptr_to_sp
,
19626 NULL_RTX
, NULL_RTX
);
19631 insn
= rs6000_emit_savres_rtx (info
, spe_save_area_ptr
,
19632 ool_adjust
, reg_mode
,
19633 /*savep=*/true, /*gpr=*/true,
19636 rs6000_frame_related (insn
, spe_save_area_ptr
, save_ptr_to_sp
,
19637 NULL_RTX
, NULL_RTX
);
19640 /* Move the static chain pointer back. */
19641 if (using_static_chain_p
&& !spe_regs_addressable
)
19642 emit_move_insn (spe_save_area_ptr
, gen_rtx_REG (Pmode
, 0));
19644 else if (!WORLD_SAVE_P (info
) && !saving_GPRs_inline
)
19646 if (DEFAULT_ABI
== ABI_DARWIN
)
19648 rtx dest_reg
= gen_rtx_REG (Pmode
, 11);
19649 if (info
->first_fp_reg_save
== 64)
19651 /* we only need a copy, no fprs were saved. */
19652 if (dest_reg
!= frame_reg_rtx
)
19653 emit_move_insn (dest_reg
, frame_reg_rtx
);
19657 int save_off
= 8 * (64 - info
->first_fp_reg_save
);
19658 rtx offset
= GEN_INT (sp_offset
- save_off
);
19660 if (REGNO (dest_reg
) == REGNO (frame_reg_rtx
))
19661 sp_offset
= save_off
;
19662 emit_insn (gen_add3_insn (dest_reg
, frame_reg_rtx
, offset
));
19665 /* Need to adjust r11 (r12) if we saved any FPRs. */
19666 else if (info
->first_fp_reg_save
!= 64)
19668 rtx dest_reg
= gen_rtx_REG (Pmode
, DEFAULT_ABI
== ABI_AIX
? 12 : 11);
19669 int save_off
= 8 * (64 - info
->first_fp_reg_save
);
19670 rtx offset
= GEN_INT (sp_offset
- save_off
);
19672 if (REGNO (dest_reg
) == REGNO (frame_reg_rtx
))
19673 sp_offset
= save_off
;
19674 emit_insn (gen_add3_insn (dest_reg
, frame_reg_rtx
, offset
));
19677 insn
= rs6000_emit_savres_rtx (info
, frame_reg_rtx
,
19678 info
->gp_save_offset
+ sp_offset
,
19680 /*savep=*/true, /*gpr=*/true,
19682 & SAVE_NOINLINE_GPRS_SAVES_LR
)
19684 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
19685 NULL_RTX
, NULL_RTX
);
19687 else if (!WORLD_SAVE_P (info
) && using_store_multiple
)
19691 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
19692 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
19694 rtx addr
, reg
, mem
;
19695 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
19696 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
19697 GEN_INT (info
->gp_save_offset
19700 mem
= gen_frame_mem (reg_mode
, addr
);
19702 RTVEC_ELT (p
, i
) = gen_rtx_SET (VOIDmode
, mem
, reg
);
19704 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
19705 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
19706 NULL_RTX
, NULL_RTX
);
19708 else if (!WORLD_SAVE_P (info
))
19711 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
19712 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
19714 rtx addr
, reg
, mem
;
19715 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
19717 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
19718 GEN_INT (info
->gp_save_offset
19721 mem
= gen_frame_mem (reg_mode
, addr
);
19723 insn
= emit_move_insn (mem
, reg
);
19724 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
19725 NULL_RTX
, NULL_RTX
);
19729 /* ??? There's no need to emit actual instructions here, but it's the
19730 easiest way to get the frame unwind information emitted. */
19731 if (crtl
->calls_eh_return
)
19733 unsigned int i
, regno
;
19737 regno
= EH_RETURN_DATA_REGNO (i
);
19738 if (regno
== INVALID_REGNUM
)
19741 emit_frame_save (frame_reg_rtx
, frame_ptr_rtx
, reg_mode
, regno
,
19742 info
->ehrd_offset
+ sp_offset
19743 + reg_size
* (int) i
,
19748 /* In AIX ABI we need to make sure r2 is really saved. */
19749 if (TARGET_AIX
&& crtl
->calls_eh_return
)
19751 rtx tmp_reg
, tmp_reg_si
, hi
, lo
, compare_result
, toc_save_done
, jump
;
19752 rtx save_insn
, join_insn
, note
;
19753 long toc_restore_insn
;
19755 gcc_assert (frame_reg_rtx
== frame_ptr_rtx
19756 || frame_reg_rtx
== sp_reg_rtx
);
19757 tmp_reg
= gen_rtx_REG (Pmode
, 11);
19758 tmp_reg_si
= gen_rtx_REG (SImode
, 11);
19759 if (using_static_chain_p
)
19760 emit_move_insn (gen_rtx_REG (Pmode
, 0), tmp_reg
);
19761 gcc_assert (saving_GPRs_inline
&& saving_FPRs_inline
);
19762 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
19763 /* Peek at instruction to which this function returns. If it's
19764 restoring r2, then we know we've already saved r2. We can't
19765 unconditionally save r2 because the value we have will already
19766 be updated if we arrived at this function via a plt call or
19767 toc adjusting stub. */
19768 emit_move_insn (tmp_reg_si
, gen_rtx_MEM (SImode
, tmp_reg
));
19769 toc_restore_insn
= TARGET_32BIT
? 0x80410014 : 0xE8410028;
19770 hi
= gen_int_mode (toc_restore_insn
& ~0xffff, SImode
);
19771 emit_insn (gen_xorsi3 (tmp_reg_si
, tmp_reg_si
, hi
));
19772 compare_result
= gen_rtx_REG (CCUNSmode
, CR0_REGNO
);
19773 validate_condition_mode (EQ
, CCUNSmode
);
19774 lo
= gen_int_mode (toc_restore_insn
& 0xffff, SImode
);
19775 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
19776 gen_rtx_COMPARE (CCUNSmode
, tmp_reg_si
, lo
)));
19777 toc_save_done
= gen_label_rtx ();
19778 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
19779 gen_rtx_EQ (VOIDmode
, compare_result
,
19781 gen_rtx_LABEL_REF (VOIDmode
, toc_save_done
),
19783 jump
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, jump
));
19784 JUMP_LABEL (jump
) = toc_save_done
;
19785 LABEL_NUSES (toc_save_done
) += 1;
19787 save_insn
= emit_frame_save (frame_reg_rtx
, frame_ptr_rtx
, reg_mode
,
19788 TOC_REGNUM
, sp_offset
+ 5 * reg_size
,
19791 emit_label (toc_save_done
);
19793 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
19794 have a CFG that has different saves along different paths.
19795 Move the note to a dummy blockage insn, which describes that
19796 R2 is unconditionally saved after the label. */
19797 /* ??? An alternate representation might be a special insn pattern
19798 containing both the branch and the store. That might let the
19799 code that minimizes the number of DW_CFA_advance opcodes better
19800 freedom in placing the annotations. */
19801 note
= find_reg_note (save_insn
, REG_FRAME_RELATED_EXPR
, NULL
);
19803 remove_note (save_insn
, note
);
19804 RTX_FRAME_RELATED_P (save_insn
) = 0;
19806 join_insn
= emit_insn (gen_blockage ());
19807 REG_NOTES (join_insn
) = note
;
19808 RTX_FRAME_RELATED_P (join_insn
) = 1;
19810 if (using_static_chain_p
)
19811 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, 0));
19814 /* Save CR if we use any that must be preserved. */
19815 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
)
19817 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
19818 GEN_INT (info
->cr_save_offset
+ sp_offset
));
19819 rtx mem
= gen_frame_mem (SImode
, addr
);
19820 /* See the large comment above about why CR2_REGNO is used. */
19821 rtx magic_eh_cr_reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
19823 /* If r12 was used to hold the original sp, copy cr into r0 now
19825 if (REGNO (frame_reg_rtx
) == 12)
19829 cr_save_rtx
= gen_rtx_REG (SImode
, 0);
19830 insn
= emit_insn (gen_movesi_from_cr (cr_save_rtx
));
19831 RTX_FRAME_RELATED_P (insn
) = 1;
19832 set
= gen_rtx_SET (VOIDmode
, cr_save_rtx
, magic_eh_cr_reg
);
19833 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
19835 insn
= emit_move_insn (mem
, cr_save_rtx
);
19837 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
19838 NULL_RTX
, NULL_RTX
);
19841 /* Update stack and set back pointer unless this is V.4,
19842 for which it was done previously. */
19843 if (!WORLD_SAVE_P (info
) && info
->push_p
19844 && !(DEFAULT_ABI
== ABI_V4
|| crtl
->calls_eh_return
))
19846 rtx copy_reg
= NULL
;
19848 if (info
->total_size
< 32767)
19849 sp_offset
= info
->total_size
;
19850 else if (info
->altivec_size
!= 0
19851 || info
->vrsave_mask
!= 0)
19853 copy_reg
= frame_ptr_rtx
;
19854 frame_reg_rtx
= copy_reg
;
19857 sp_offset
= info
->total_size
;
19858 rs6000_emit_allocate_stack (info
->total_size
, copy_reg
);
19859 if (frame_reg_rtx
!= sp_reg_rtx
)
19860 rs6000_emit_stack_tie ();
19863 /* Set frame pointer, if needed. */
19864 if (frame_pointer_needed
)
19866 insn
= emit_move_insn (gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
19868 RTX_FRAME_RELATED_P (insn
) = 1;
19871 /* Save AltiVec registers if needed. Save here because the red zone does
19872 not include AltiVec registers. */
19873 if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
&& info
->altivec_size
!= 0)
19877 /* There should be a non inline version of this, for when we
19878 are saving lots of vector registers. */
19879 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
19880 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
19882 rtx areg
, savereg
, mem
;
19885 offset
= info
->altivec_save_offset
+ sp_offset
19886 + 16 * (i
- info
->first_altivec_reg_save
);
19888 savereg
= gen_rtx_REG (V4SImode
, i
);
19890 areg
= gen_rtx_REG (Pmode
, 0);
19891 emit_move_insn (areg
, GEN_INT (offset
));
19893 /* AltiVec addressing mode is [reg+reg]. */
19894 mem
= gen_frame_mem (V4SImode
,
19895 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
));
19897 insn
= emit_move_insn (mem
, savereg
);
19899 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
19900 areg
, GEN_INT (offset
));
19904 /* VRSAVE is a bit vector representing which AltiVec registers
19905 are used. The OS uses this to determine which vector
19906 registers to save on a context switch. We need to save
19907 VRSAVE on the stack frame, add whatever AltiVec registers we
19908 used in this function, and do the corresponding magic in the
19911 if (!WORLD_SAVE_P (info
)
19913 && TARGET_ALTIVEC_VRSAVE
19914 && info
->vrsave_mask
!= 0)
19916 rtx reg
, mem
, vrsave
;
19919 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
19920 as frame_reg_rtx and r11 as the static chain pointer for
19921 nested functions. */
19922 reg
= gen_rtx_REG (SImode
, 0);
19923 vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
19925 emit_insn (gen_get_vrsave_internal (reg
));
19927 emit_insn (gen_rtx_SET (VOIDmode
, reg
, vrsave
));
19930 offset
= info
->vrsave_save_offset
+ sp_offset
;
19931 mem
= gen_frame_mem (SImode
,
19932 gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
19933 GEN_INT (offset
)));
19934 insn
= emit_move_insn (mem
, reg
);
19936 /* Include the registers in the mask. */
19937 emit_insn (gen_iorsi3 (reg
, reg
, GEN_INT ((int) info
->vrsave_mask
)));
19939 insn
= emit_insn (generate_set_vrsave (reg
, info
, 0));
19942 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
19943 if (!TARGET_SINGLE_PIC_BASE
19944 && ((TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
19945 || (DEFAULT_ABI
== ABI_V4
19946 && (flag_pic
== 1 || (flag_pic
&& TARGET_SECURE_PLT
))
19947 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))))
19949 /* If emit_load_toc_table will use the link register, we need to save
19950 it. We use R12 for this purpose because emit_load_toc_table
19951 can use register 0. This allows us to use a plain 'blr' to return
19952 from the procedure more often. */
19953 int save_LR_around_toc_setup
= (TARGET_ELF
19954 && DEFAULT_ABI
!= ABI_AIX
19956 && ! info
->lr_save_p
19957 && EDGE_COUNT (EXIT_BLOCK_PTR
->preds
) > 0);
19958 if (save_LR_around_toc_setup
)
19960 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
19962 insn
= emit_move_insn (frame_ptr_rtx
, lr
);
19963 RTX_FRAME_RELATED_P (insn
) = 1;
19965 rs6000_emit_load_toc_table (TRUE
);
19967 insn
= emit_move_insn (lr
, frame_ptr_rtx
);
19968 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
19969 RTX_FRAME_RELATED_P (insn
) = 1;
19972 rs6000_emit_load_toc_table (TRUE
);
19976 if (!TARGET_SINGLE_PIC_BASE
19977 && DEFAULT_ABI
== ABI_DARWIN
19978 && flag_pic
&& crtl
->uses_pic_offset_table
)
19980 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
19981 rtx src
= gen_rtx_SYMBOL_REF (Pmode
, MACHOPIC_FUNCTION_BASE_NAME
);
19983 /* Save and restore LR locally around this call (in R0). */
19984 if (!info
->lr_save_p
)
19985 emit_move_insn (gen_rtx_REG (Pmode
, 0), lr
);
19987 emit_insn (gen_load_macho_picbase (src
));
19989 emit_move_insn (gen_rtx_REG (Pmode
,
19990 RS6000_PIC_OFFSET_TABLE_REGNUM
),
19993 if (!info
->lr_save_p
)
19994 emit_move_insn (lr
, gen_rtx_REG (Pmode
, 0));
19998 /* If we need to, save the TOC register after doing the stack setup.
19999 Do not emit eh frame info for this save. The unwinder wants info,
20000 conceptually attached to instructions in this function, about
20001 register values in the caller of this function. This R2 may have
20002 already been changed from the value in the caller.
20003 We don't attempt to write accurate DWARF EH frame info for R2
20004 because code emitted by gcc for a (non-pointer) function call
20005 doesn't save and restore R2. Instead, R2 is managed out-of-line
20006 by a linker generated plt call stub when the function resides in
20007 a shared library. This behaviour is costly to describe in DWARF,
20008 both in terms of the size of DWARF info and the time taken in the
20009 unwinder to interpret it. R2 changes, apart from the
20010 calls_eh_return case earlier in this function, are handled by
20011 linux-unwind.h frob_update_context. */
20012 if (rs6000_save_toc_in_prologue_p ())
20014 rtx addr
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
, GEN_INT (5 * reg_size
));
20015 rtx mem
= gen_frame_mem (reg_mode
, addr
);
20016 emit_move_insn (mem
, gen_rtx_REG (reg_mode
, TOC_REGNUM
));
20020 /* Write function prologue. */
20023 rs6000_output_function_prologue (FILE *file
,
20024 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
20026 rs6000_stack_t
*info
= rs6000_stack_info ();
20028 if (TARGET_DEBUG_STACK
)
20029 debug_stack_info (info
);
20031 /* Write .extern for any function we will call to save and restore
20033 if (info
->first_fp_reg_save
< 64
20037 int regno
= info
->first_fp_reg_save
- 32;
20039 if ((info
->savres_strategy
& SAVE_INLINE_FPRS
) == 0)
20041 name
= rs6000_savres_routine_name (info
, regno
, /*savep=*/true,
20042 /*gpr=*/false, /*lr=*/false);
20043 fprintf (file
, "\t.extern %s\n", name
);
20045 if ((info
->savres_strategy
& REST_INLINE_FPRS
) == 0)
20047 name
= rs6000_savres_routine_name (info
, regno
, /*savep=*/false,
20048 /*gpr=*/false, /*lr=*/true);
20049 fprintf (file
, "\t.extern %s\n", name
);
20053 /* Write .extern for AIX common mode routines, if needed. */
20054 if (! TARGET_POWER
&& ! TARGET_POWERPC
&& ! common_mode_defined
)
20056 fputs ("\t.extern __mulh\n", file
);
20057 fputs ("\t.extern __mull\n", file
);
20058 fputs ("\t.extern __divss\n", file
);
20059 fputs ("\t.extern __divus\n", file
);
20060 fputs ("\t.extern __quoss\n", file
);
20061 fputs ("\t.extern __quous\n", file
);
20062 common_mode_defined
= 1;
20065 rs6000_pic_labelno
++;
20068 /* Non-zero if vmx regs are restored before the frame pop, zero if
20069 we restore after the pop when possible. */
20070 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
20072 /* Reload CR from REG. */
20075 rs6000_restore_saved_cr (rtx reg
, int using_mfcr_multiple
)
20080 if (using_mfcr_multiple
)
20082 for (i
= 0; i
< 8; i
++)
20083 if (df_regs_ever_live_p (CR0_REGNO
+i
) && ! call_used_regs
[CR0_REGNO
+i
])
20085 gcc_assert (count
);
20088 if (using_mfcr_multiple
&& count
> 1)
20093 p
= rtvec_alloc (count
);
20096 for (i
= 0; i
< 8; i
++)
20097 if (df_regs_ever_live_p (CR0_REGNO
+i
) && ! call_used_regs
[CR0_REGNO
+i
])
20099 rtvec r
= rtvec_alloc (2);
20100 RTVEC_ELT (r
, 0) = reg
;
20101 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7-i
));
20102 RTVEC_ELT (p
, ndx
) =
20103 gen_rtx_SET (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+i
),
20104 gen_rtx_UNSPEC (CCmode
, r
, UNSPEC_MOVESI_TO_CR
));
20107 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
20108 gcc_assert (ndx
== count
);
20111 for (i
= 0; i
< 8; i
++)
20112 if (df_regs_ever_live_p (CR0_REGNO
+i
) && ! call_used_regs
[CR0_REGNO
+i
])
20114 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode
,
20120 /* Return true if OFFSET from stack pointer can be clobbered by signals.
20121 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
20122 below stack pointer not cloberred by signals. */
20125 offset_below_red_zone_p (HOST_WIDE_INT offset
)
20127 return offset
< (DEFAULT_ABI
== ABI_V4
20129 : TARGET_32BIT
? -220 : -288);
20132 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
20135 emit_cfa_restores (rtx cfa_restores
)
20137 rtx insn
= get_last_insn ();
20138 rtx
*loc
= ®_NOTES (insn
);
20141 loc
= &XEXP (*loc
, 1);
20142 *loc
= cfa_restores
;
20143 RTX_FRAME_RELATED_P (insn
) = 1;
20146 /* Emit function epilogue as insns. */
20149 rs6000_emit_epilogue (int sibcall
)
20151 rs6000_stack_t
*info
;
20152 int restoring_GPRs_inline
;
20153 int restoring_FPRs_inline
;
20154 int using_load_multiple
;
20155 int using_mtcr_multiple
;
20156 int use_backchain_to_restore_sp
;
20160 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, 1);
20161 rtx frame_reg_rtx
= sp_reg_rtx
;
20162 rtx cfa_restores
= NULL_RTX
;
20164 rtx cr_save_reg
= NULL_RTX
;
20165 enum machine_mode reg_mode
= Pmode
;
20166 int reg_size
= TARGET_32BIT
? 4 : 8;
20169 info
= rs6000_stack_info ();
20171 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
20173 reg_mode
= V2SImode
;
20177 strategy
= info
->savres_strategy
;
20178 using_load_multiple
= strategy
& SAVRES_MULTIPLE
;
20179 restoring_FPRs_inline
= sibcall
|| (strategy
& REST_INLINE_FPRS
);
20180 restoring_GPRs_inline
= sibcall
|| (strategy
& REST_INLINE_GPRS
);
20181 using_mtcr_multiple
= (rs6000_cpu
== PROCESSOR_PPC601
20182 || rs6000_cpu
== PROCESSOR_PPC603
20183 || rs6000_cpu
== PROCESSOR_PPC750
20185 /* Restore via the backchain when we have a large frame, since this
20186 is more efficient than an addis, addi pair. The second condition
20187 here will not trigger at the moment; We don't actually need a
20188 frame pointer for alloca, but the generic parts of the compiler
20189 give us one anyway. */
20190 use_backchain_to_restore_sp
= (info
->total_size
> 32767 - info
->lr_save_offset
20191 || (cfun
->calls_alloca
20192 && !frame_pointer_needed
));
20193 restore_lr
= (info
->lr_save_p
20194 && (restoring_FPRs_inline
20195 || (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
))
20196 && (restoring_GPRs_inline
20197 || info
->first_fp_reg_save
< 64));
20199 if (WORLD_SAVE_P (info
))
20203 const char *alloc_rname
;
20206 /* eh_rest_world_r10 will return to the location saved in the LR
20207 stack slot (which is not likely to be our caller.)
20208 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
20209 rest_world is similar, except any R10 parameter is ignored.
20210 The exception-handling stuff that was here in 2.95 is no
20211 longer necessary. */
20215 + 32 - info
->first_gp_reg_save
20216 + LAST_ALTIVEC_REGNO
+ 1 - info
->first_altivec_reg_save
20217 + 63 + 1 - info
->first_fp_reg_save
);
20219 strcpy (rname
, ((crtl
->calls_eh_return
) ?
20220 "*eh_rest_world_r10" : "*rest_world"));
20221 alloc_rname
= ggc_strdup (rname
);
20224 RTVEC_ELT (p
, j
++) = ret_rtx
;
20225 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
20226 gen_rtx_REG (Pmode
,
20229 = gen_rtx_USE (VOIDmode
, gen_rtx_SYMBOL_REF (Pmode
, alloc_rname
));
20230 /* The instruction pattern requires a clobber here;
20231 it is shared with the restVEC helper. */
20233 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 11));
20236 /* CR register traditionally saved as CR2. */
20237 rtx reg
= gen_rtx_REG (reg_mode
, CR2_REGNO
);
20238 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
20239 GEN_INT (info
->cr_save_offset
));
20240 rtx mem
= gen_frame_mem (reg_mode
, addr
);
20242 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
20244 if (flag_shrink_wrap
)
20246 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
20247 gen_rtx_REG (Pmode
, LR_REGNO
),
20249 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
20253 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
20255 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
20256 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
20257 GEN_INT (info
->gp_save_offset
20259 rtx mem
= gen_frame_mem (reg_mode
, addr
);
20261 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
20262 if (flag_shrink_wrap
)
20263 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
20265 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
20267 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
20268 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
20269 GEN_INT (info
->altivec_save_offset
20271 rtx mem
= gen_frame_mem (V4SImode
, addr
);
20273 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
20274 if (flag_shrink_wrap
)
20275 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
20277 for (i
= 0; info
->first_fp_reg_save
+ i
<= 63; i
++)
20279 rtx reg
= gen_rtx_REG (((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
20280 ? DFmode
: SFmode
),
20281 info
->first_fp_reg_save
+ i
);
20282 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
20283 GEN_INT (info
->fp_save_offset
20285 rtx mem
= gen_frame_mem (((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
20286 ? DFmode
: SFmode
), addr
);
20288 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
20289 if (flag_shrink_wrap
)
20290 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
20293 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 0));
20295 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 12));
20297 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 7));
20299 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 8));
20301 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, 10));
20302 insn
= emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
20304 if (flag_shrink_wrap
)
20306 REG_NOTES (insn
) = cfa_restores
;
20307 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
20308 RTX_FRAME_RELATED_P (insn
) = 1;
20313 /* frame_reg_rtx + sp_offset points to the top of this stack frame. */
20315 sp_offset
= info
->total_size
;
20317 /* Restore AltiVec registers if we must do so before adjusting the
20319 if (TARGET_ALTIVEC_ABI
20320 && info
->altivec_size
!= 0
20321 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20322 || (DEFAULT_ABI
!= ABI_V4
20323 && offset_below_red_zone_p (info
->altivec_save_offset
))))
20327 if (use_backchain_to_restore_sp
)
20329 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
20330 emit_move_insn (frame_reg_rtx
,
20331 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
20334 else if (frame_pointer_needed
)
20335 frame_reg_rtx
= hard_frame_pointer_rtx
;
20337 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
20338 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
20340 rtx addr
, areg
, mem
, reg
;
20342 areg
= gen_rtx_REG (Pmode
, 0);
20344 (areg
, GEN_INT (info
->altivec_save_offset
20346 + 16 * (i
- info
->first_altivec_reg_save
)));
20348 /* AltiVec addressing mode is [reg+reg]. */
20349 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
20350 mem
= gen_frame_mem (V4SImode
, addr
);
20352 reg
= gen_rtx_REG (V4SImode
, i
);
20353 emit_move_insn (reg
, mem
);
20354 if (flag_shrink_wrap
20355 || offset_below_red_zone_p (info
->altivec_save_offset
20356 + (i
- info
->first_altivec_reg_save
)
20358 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
20363 /* Restore VRSAVE if we must do so before adjusting the stack. */
20365 && TARGET_ALTIVEC_VRSAVE
20366 && info
->vrsave_mask
!= 0
20367 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20368 || (DEFAULT_ABI
!= ABI_V4
20369 && offset_below_red_zone_p (info
->vrsave_save_offset
))))
20371 rtx addr
, mem
, reg
;
20373 if (frame_reg_rtx
== sp_reg_rtx
)
20375 if (use_backchain_to_restore_sp
)
20377 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
20378 emit_move_insn (frame_reg_rtx
,
20379 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
20382 else if (frame_pointer_needed
)
20383 frame_reg_rtx
= hard_frame_pointer_rtx
;
20386 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
20387 GEN_INT (info
->vrsave_save_offset
+ sp_offset
));
20388 mem
= gen_frame_mem (SImode
, addr
);
20389 reg
= gen_rtx_REG (SImode
, 12);
20390 emit_move_insn (reg
, mem
);
20392 emit_insn (generate_set_vrsave (reg
, info
, 1));
20396 /* If we have a large stack frame, restore the old stack pointer
20397 using the backchain. */
20398 if (use_backchain_to_restore_sp
)
20400 if (frame_reg_rtx
== sp_reg_rtx
)
20402 /* Under V.4, don't reset the stack pointer until after we're done
20403 loading the saved registers. */
20404 if (DEFAULT_ABI
== ABI_V4
)
20405 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
20407 insn
= emit_move_insn (frame_reg_rtx
,
20408 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
20411 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20412 && DEFAULT_ABI
== ABI_V4
)
20413 /* frame_reg_rtx has been set up by the altivec restore. */
20417 insn
= emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
20418 frame_reg_rtx
= sp_reg_rtx
;
20421 /* If we have a frame pointer, we can restore the old stack pointer
20423 else if (frame_pointer_needed
)
20425 frame_reg_rtx
= sp_reg_rtx
;
20426 if (DEFAULT_ABI
== ABI_V4
)
20427 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
20428 /* Prevent reordering memory accesses against stack pointer restore. */
20429 else if (cfun
->calls_alloca
20430 || offset_below_red_zone_p (-info
->total_size
))
20432 rtx mem1
= gen_rtx_MEM (BLKmode
, hard_frame_pointer_rtx
);
20433 rtx mem2
= gen_rtx_MEM (BLKmode
, sp_reg_rtx
);
20434 MEM_NOTRAP_P (mem1
) = 1;
20435 MEM_NOTRAP_P (mem2
) = 1;
20436 emit_insn (gen_frame_tie (mem1
, mem2
));
20439 insn
= emit_insn (gen_add3_insn (frame_reg_rtx
, hard_frame_pointer_rtx
,
20440 GEN_INT (info
->total_size
)));
20443 else if (info
->push_p
20444 && DEFAULT_ABI
!= ABI_V4
20445 && !crtl
->calls_eh_return
)
20447 /* Prevent reordering memory accesses against stack pointer restore. */
20448 if (cfun
->calls_alloca
20449 || offset_below_red_zone_p (-info
->total_size
))
20451 rtx mem
= gen_rtx_MEM (BLKmode
, sp_reg_rtx
);
20452 MEM_NOTRAP_P (mem
) = 1;
20453 emit_insn (gen_stack_tie (mem
));
20455 insn
= emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
,
20456 GEN_INT (info
->total_size
)));
20459 if (insn
&& frame_reg_rtx
== sp_reg_rtx
)
20463 REG_NOTES (insn
) = cfa_restores
;
20464 cfa_restores
= NULL_RTX
;
20466 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
20467 RTX_FRAME_RELATED_P (insn
) = 1;
20470 /* Restore AltiVec registers if we have not done so already. */
20471 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20472 && TARGET_ALTIVEC_ABI
20473 && info
->altivec_size
!= 0
20474 && (DEFAULT_ABI
== ABI_V4
20475 || !offset_below_red_zone_p (info
->altivec_save_offset
)))
20479 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
20480 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
20482 rtx addr
, areg
, mem
, reg
;
20484 areg
= gen_rtx_REG (Pmode
, 0);
20486 (areg
, GEN_INT (info
->altivec_save_offset
20488 + 16 * (i
- info
->first_altivec_reg_save
)));
20490 /* AltiVec addressing mode is [reg+reg]. */
20491 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
20492 mem
= gen_frame_mem (V4SImode
, addr
);
20494 reg
= gen_rtx_REG (V4SImode
, i
);
20495 emit_move_insn (reg
, mem
);
20496 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
20497 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
20502 /* Restore VRSAVE if we have not done so already. */
20503 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20505 && TARGET_ALTIVEC_VRSAVE
20506 && info
->vrsave_mask
!= 0
20507 && (DEFAULT_ABI
== ABI_V4
20508 || !offset_below_red_zone_p (info
->vrsave_save_offset
)))
20510 rtx addr
, mem
, reg
;
20512 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
20513 GEN_INT (info
->vrsave_save_offset
+ sp_offset
));
20514 mem
= gen_frame_mem (SImode
, addr
);
20515 reg
= gen_rtx_REG (SImode
, 12);
20516 emit_move_insn (reg
, mem
);
20518 emit_insn (generate_set_vrsave (reg
, info
, 1));
20521 /* Get the old lr if we saved it. If we are restoring registers
20522 out-of-line, then the out-of-line routines can do this for us. */
20523 if (restore_lr
&& restoring_GPRs_inline
)
20525 rtx mem
= gen_frame_mem_offset (Pmode
, frame_reg_rtx
,
20526 info
->lr_save_offset
+ sp_offset
);
20528 emit_move_insn (gen_rtx_REG (Pmode
, 0), mem
);
20531 /* Get the old cr if we saved it. */
20532 if (info
->cr_save_p
)
20534 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
20535 GEN_INT (info
->cr_save_offset
+ sp_offset
));
20536 rtx mem
= gen_frame_mem (SImode
, addr
);
20538 cr_save_reg
= gen_rtx_REG (SImode
,
20539 DEFAULT_ABI
== ABI_AIX
20540 && !restoring_GPRs_inline
20541 && info
->first_fp_reg_save
< 64
20543 emit_move_insn (cr_save_reg
, mem
);
20546 /* Set LR here to try to overlap restores below. */
20547 if (restore_lr
&& restoring_GPRs_inline
)
20548 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
),
20549 gen_rtx_REG (Pmode
, 0));
20551 /* Load exception handler data registers, if needed. */
20552 if (crtl
->calls_eh_return
)
20554 unsigned int i
, regno
;
20558 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
20559 GEN_INT (sp_offset
+ 5 * reg_size
));
20560 rtx mem
= gen_frame_mem (reg_mode
, addr
);
20562 emit_move_insn (gen_rtx_REG (reg_mode
, 2), mem
);
20569 regno
= EH_RETURN_DATA_REGNO (i
);
20570 if (regno
== INVALID_REGNUM
)
20573 mem
= gen_frame_mem_offset (reg_mode
, frame_reg_rtx
,
20574 info
->ehrd_offset
+ sp_offset
20575 + reg_size
* (int) i
);
20577 emit_move_insn (gen_rtx_REG (reg_mode
, regno
), mem
);
20581 /* Restore GPRs. This is done as a PARALLEL if we are using
20582 the load-multiple instructions. */
20584 && info
->spe_64bit_regs_used
20585 && info
->first_gp_reg_save
!= 32)
20587 /* Determine whether we can address all of the registers that need
20588 to be saved with an offset from frame_reg_rtx that fits in
20589 the small const field for SPE memory instructions. */
20590 int spe_regs_addressable
20591 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ sp_offset
20592 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
20593 && restoring_GPRs_inline
);
20595 int ool_adjust
= 0;
20597 if (spe_regs_addressable
)
20598 spe_offset
= info
->spe_gp_save_offset
+ sp_offset
;
20601 rtx old_frame_reg_rtx
= frame_reg_rtx
;
20602 /* Make r11 point to the start of the SPE save area. We worried about
20603 not clobbering it when we were saving registers in the prologue.
20604 There's no need to worry here because the static chain is passed
20605 anew to every function. */
20607 if (!restoring_GPRs_inline
)
20608 ool_adjust
= 8 * (info
->first_gp_reg_save
20609 - (FIRST_SAVRES_REGISTER
+ 1));
20610 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
20611 emit_insn (gen_addsi3 (frame_reg_rtx
, old_frame_reg_rtx
,
20612 GEN_INT (info
->spe_gp_save_offset
20615 /* Keep the invariant that frame_reg_rtx + sp_offset points
20616 at the top of the stack frame. */
20617 sp_offset
= -info
->spe_gp_save_offset
+ ool_adjust
;
20622 if (restoring_GPRs_inline
)
20624 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
20625 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
20627 rtx offset
, addr
, mem
, reg
;
20629 /* We're doing all this to ensure that the immediate offset
20630 fits into the immediate field of 'evldd'. */
20631 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset
+ reg_size
* i
));
20633 offset
= GEN_INT (spe_offset
+ reg_size
* i
);
20634 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, offset
);
20635 mem
= gen_rtx_MEM (V2SImode
, addr
);
20636 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
20638 emit_move_insn (reg
, mem
);
20642 rs6000_emit_savres_rtx (info
, frame_reg_rtx
,
20643 ool_adjust
, reg_mode
,
20644 /*savep=*/false, /*gpr=*/true,
20647 else if (!restoring_GPRs_inline
)
20649 /* We are jumping to an out-of-line function. */
20650 bool can_use_exit
= info
->first_fp_reg_save
== 64;
20652 /* Emit stack reset code if we need it. */
20655 rs6000_emit_stack_reset (info
, sp_reg_rtx
, frame_reg_rtx
,
20656 sp_offset
, can_use_exit
);
20657 if (DEFAULT_ABI
== ABI_DARWIN
)
20658 /* we only need a copy, no fprs were saved. */
20659 emit_move_insn (gen_rtx_REG (Pmode
, 11), frame_reg_rtx
);
20661 if (info
->cr_save_p
)
20662 rs6000_restore_saved_cr (cr_save_reg
, using_mtcr_multiple
);
20666 rtx src_reg
= gen_rtx_REG (Pmode
, DEFAULT_ABI
== ABI_AIX
? 12 : 11);
20668 emit_insn (gen_add3_insn (src_reg
, frame_reg_rtx
,
20669 GEN_INT (sp_offset
- info
->fp_size
)));
20670 if (REGNO (frame_reg_rtx
) == REGNO (src_reg
))
20671 sp_offset
= info
->fp_size
;
20674 rs6000_emit_savres_rtx (info
, frame_reg_rtx
,
20675 info
->gp_save_offset
, reg_mode
,
20676 /*savep=*/false, /*gpr=*/true,
20677 /*lr=*/can_use_exit
);
20679 else if (using_load_multiple
)
20682 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
20683 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
20685 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
20686 GEN_INT (info
->gp_save_offset
20689 rtx mem
= gen_frame_mem (reg_mode
, addr
);
20690 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
20692 RTVEC_ELT (p
, i
) = gen_rtx_SET (VOIDmode
, reg
, mem
);
20694 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
20698 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
20699 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
20701 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
20702 GEN_INT (info
->gp_save_offset
20705 rtx mem
= gen_frame_mem (reg_mode
, addr
);
20706 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
20708 emit_move_insn (reg
, mem
);
20712 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
20714 /* If the frame pointer was used then we can't delay emitting
20715 a REG_CFA_DEF_CFA note. This must happen on the insn that
20716 restores the frame pointer, r31. We may have already emitted
20717 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
20718 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
20719 be harmless if emitted. */
20720 if (frame_pointer_needed
)
20722 insn
= get_last_insn ();
20723 add_reg_note (insn
, REG_CFA_DEF_CFA
,
20724 plus_constant (frame_reg_rtx
, sp_offset
));
20725 RTX_FRAME_RELATED_P (insn
) = 1;
20728 /* Set up cfa_restores. We always need these when
20729 shrink-wrapping. If not shrink-wrapping then we only need
20730 the cfa_restore when the stack location is no longer valid.
20731 The cfa_restores must be emitted on or before the insn that
20732 invalidates the stack, and of course must not be emitted
20733 before the insn that actually does the restore. The latter
20734 is why the LR cfa_restore condition below is a little
20735 complicated. It's also why it is a bad idea to emit the
20736 cfa_restores as a group on the last instruction here that
20737 actually does a restore: That insn may be reordered with
20738 respect to others doing restores. */
20739 if (info
->cr_save_p
)
20740 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
20741 gen_rtx_REG (SImode
, CR2_REGNO
),
20743 if (flag_shrink_wrap
20745 || (info
->lr_save_p
20746 && !restoring_GPRs_inline
20747 && info
->first_fp_reg_save
== 64)))
20748 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
20749 gen_rtx_REG (Pmode
, LR_REGNO
),
20752 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
20753 if (!restoring_GPRs_inline
20754 || using_load_multiple
20755 || rs6000_reg_live_or_pic_offset_p (i
))
20757 rtx reg
= gen_rtx_REG (reg_mode
, i
);
20759 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
20763 if (!restoring_GPRs_inline
20764 && info
->first_fp_reg_save
== 64)
20766 /* We are jumping to an out-of-line function. */
20768 emit_cfa_restores (cfa_restores
);
20772 if (restore_lr
&& !restoring_GPRs_inline
)
20774 rtx mem
= gen_frame_mem_offset (Pmode
, frame_reg_rtx
,
20775 info
->lr_save_offset
+ sp_offset
);
20777 emit_move_insn (gen_rtx_REG (Pmode
, 0), mem
);
20778 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
),
20779 gen_rtx_REG (Pmode
, 0));
20782 /* Restore fpr's if we need to do it without calling a function. */
20783 if (restoring_FPRs_inline
)
20784 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
20785 if ((df_regs_ever_live_p (info
->first_fp_reg_save
+ i
)
20786 && !call_used_regs
[info
->first_fp_reg_save
+ i
]))
20788 rtx addr
, mem
, reg
;
20789 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
20790 GEN_INT (info
->fp_save_offset
20793 mem
= gen_frame_mem (((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
20794 ? DFmode
: SFmode
), addr
);
20795 reg
= gen_rtx_REG (((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
20796 ? DFmode
: SFmode
),
20797 info
->first_fp_reg_save
+ i
);
20799 emit_move_insn (reg
, mem
);
20800 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
20801 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
20804 /* If we saved cr, restore it here. Just those that were used. */
20805 if (info
->cr_save_p
)
20806 rs6000_restore_saved_cr (cr_save_reg
, using_mtcr_multiple
);
20808 /* If this is V.4, unwind the stack pointer after all of the loads
20810 insn
= rs6000_emit_stack_reset (info
, sp_reg_rtx
, frame_reg_rtx
,
20811 sp_offset
, !restoring_FPRs_inline
);
20816 REG_NOTES (insn
) = cfa_restores
;
20817 cfa_restores
= NULL_RTX
;
20819 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
20820 RTX_FRAME_RELATED_P (insn
) = 1;
20823 if (crtl
->calls_eh_return
)
20825 rtx sa
= EH_RETURN_STACKADJ_RTX
;
20826 emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
, sa
));
20832 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
20833 if (! restoring_FPRs_inline
)
20835 p
= rtvec_alloc (4 + 64 - info
->first_fp_reg_save
);
20836 RTVEC_ELT (p
, 0) = ret_rtx
;
20842 /* We can't hang the cfa_restores off a simple return,
20843 since the shrink-wrap code sometimes uses an existing
20844 return. This means there might be a path from
20845 pre-prologue code to this return, and dwarf2cfi code
20846 wants the eh_frame unwinder state to be the same on
20847 all paths to any point. So we need to emit the
20848 cfa_restores before the return. For -m64 we really
20849 don't need epilogue cfa_restores at all, except for
20850 this irritating dwarf2cfi with shrink-wrap
20851 requirement; The stack red-zone means eh_frame info
20852 from the prologue telling the unwinder to restore
20853 from the stack is perfectly good right to the end of
20855 emit_insn (gen_blockage ());
20856 emit_cfa_restores (cfa_restores
);
20857 cfa_restores
= NULL_RTX
;
20859 p
= rtvec_alloc (2);
20860 RTVEC_ELT (p
, 0) = simple_return_rtx
;
20863 RTVEC_ELT (p
, 1) = ((restoring_FPRs_inline
|| !lr
)
20864 ? gen_rtx_USE (VOIDmode
,
20865 gen_rtx_REG (Pmode
, LR_REGNO
))
20866 : gen_rtx_CLOBBER (VOIDmode
,
20867 gen_rtx_REG (Pmode
, LR_REGNO
)));
20869 /* If we have to restore more than two FP registers, branch to the
20870 restore function. It will return to our caller. */
20871 if (! restoring_FPRs_inline
)
20876 if ((DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
20878 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
20879 gen_rtx_REG (Pmode
, LR_REGNO
),
20882 sym
= rs6000_savres_routine_sym (info
,
20886 RTVEC_ELT (p
, 2) = gen_rtx_USE (VOIDmode
, sym
);
20887 RTVEC_ELT (p
, 3) = gen_rtx_USE (VOIDmode
,
20888 gen_rtx_REG (Pmode
,
20889 DEFAULT_ABI
== ABI_AIX
20891 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
20893 rtx addr
, mem
, reg
;
20895 addr
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
,
20896 GEN_INT (info
->fp_save_offset
+ 8 * i
));
20897 mem
= gen_frame_mem (DFmode
, addr
);
20898 reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
20900 RTVEC_ELT (p
, i
+ 4) = gen_rtx_SET (VOIDmode
, reg
, mem
);
20901 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
20902 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
20907 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
20913 /* Ensure the cfa_restores are hung off an insn that won't
20914 be reordered above other restores. */
20915 emit_insn (gen_blockage ());
20917 emit_cfa_restores (cfa_restores
);
20921 /* Write function epilogue. */
20924 rs6000_output_function_epilogue (FILE *file
,
20925 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
20928 macho_branch_islands ();
20929 /* Mach-O doesn't support labels at the end of objects, so if
20930 it looks like we might want one, insert a NOP. */
20932 rtx insn
= get_last_insn ();
20933 rtx deleted_debug_label
= NULL_RTX
;
20936 && NOTE_KIND (insn
) != NOTE_INSN_DELETED_LABEL
)
20938 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
20939 notes only, instead set their CODE_LABEL_NUMBER to -1,
20940 otherwise there would be code generation differences
20941 in between -g and -g0. */
20942 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
20943 deleted_debug_label
= insn
;
20944 insn
= PREV_INSN (insn
);
20949 && NOTE_KIND (insn
) == NOTE_INSN_DELETED_LABEL
)))
20950 fputs ("\tnop\n", file
);
20951 else if (deleted_debug_label
)
20952 for (insn
= deleted_debug_label
; insn
; insn
= NEXT_INSN (insn
))
20953 if (NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
20954 CODE_LABEL_NUMBER (insn
) = -1;
20958 /* Output a traceback table here. See /usr/include/sys/debug.h for info
20961 We don't output a traceback table if -finhibit-size-directive was
20962 used. The documentation for -finhibit-size-directive reads
20963 ``don't output a @code{.size} assembler directive, or anything
20964 else that would cause trouble if the function is split in the
20965 middle, and the two halves are placed at locations far apart in
20966 memory.'' The traceback table has this property, since it
20967 includes the offset from the start of the function to the
20968 traceback table itself.
20970 System V.4 Powerpc's (and the embedded ABI derived from it) use a
20971 different traceback table. */
20972 if (DEFAULT_ABI
== ABI_AIX
&& ! flag_inhibit_size_directive
20973 && rs6000_traceback
!= traceback_none
&& !cfun
->is_thunk
)
20975 const char *fname
= NULL
;
20976 const char *language_string
= lang_hooks
.name
;
20977 int fixed_parms
= 0, float_parms
= 0, parm_info
= 0;
20979 int optional_tbtab
;
20980 rs6000_stack_t
*info
= rs6000_stack_info ();
20982 if (rs6000_traceback
== traceback_full
)
20983 optional_tbtab
= 1;
20984 else if (rs6000_traceback
== traceback_part
)
20985 optional_tbtab
= 0;
20987 optional_tbtab
= !optimize_size
&& !TARGET_ELF
;
20989 if (optional_tbtab
)
20991 fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
20992 while (*fname
== '.') /* V.4 encodes . in the name */
20995 /* Need label immediately before tbtab, so we can compute
20996 its offset from the function start. */
20997 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
20998 ASM_OUTPUT_LABEL (file
, fname
);
21001 /* The .tbtab pseudo-op can only be used for the first eight
21002 expressions, since it can't handle the possibly variable
21003 length fields that follow. However, if you omit the optional
21004 fields, the assembler outputs zeros for all optional fields
21005 anyways, giving each variable length field is minimum length
21006 (as defined in sys/debug.h). Thus we can not use the .tbtab
21007 pseudo-op at all. */
21009 /* An all-zero word flags the start of the tbtab, for debuggers
21010 that have to find it by searching forward from the entry
21011 point or from the current pc. */
21012 fputs ("\t.long 0\n", file
);
21014 /* Tbtab format type. Use format type 0. */
21015 fputs ("\t.byte 0,", file
);
21017 /* Language type. Unfortunately, there does not seem to be any
21018 official way to discover the language being compiled, so we
21019 use language_string.
21020 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
21021 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
21022 a number, so for now use 9. LTO and Go aren't assigned numbers
21023 either, so for now use 0. */
21024 if (! strcmp (language_string
, "GNU C")
21025 || ! strcmp (language_string
, "GNU GIMPLE")
21026 || ! strcmp (language_string
, "GNU Go"))
21028 else if (! strcmp (language_string
, "GNU F77")
21029 || ! strcmp (language_string
, "GNU Fortran"))
21031 else if (! strcmp (language_string
, "GNU Pascal"))
21033 else if (! strcmp (language_string
, "GNU Ada"))
21035 else if (! strcmp (language_string
, "GNU C++")
21036 || ! strcmp (language_string
, "GNU Objective-C++"))
21038 else if (! strcmp (language_string
, "GNU Java"))
21040 else if (! strcmp (language_string
, "GNU Objective-C"))
21043 gcc_unreachable ();
21044 fprintf (file
, "%d,", i
);
21046 /* 8 single bit fields: global linkage (not set for C extern linkage,
21047 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
21048 from start of procedure stored in tbtab, internal function, function
21049 has controlled storage, function has no toc, function uses fp,
21050 function logs/aborts fp operations. */
21051 /* Assume that fp operations are used if any fp reg must be saved. */
21052 fprintf (file
, "%d,",
21053 (optional_tbtab
<< 5) | ((info
->first_fp_reg_save
!= 64) << 1));
21055 /* 6 bitfields: function is interrupt handler, name present in
21056 proc table, function calls alloca, on condition directives
21057 (controls stack walks, 3 bits), saves condition reg, saves
21059 /* The `function calls alloca' bit seems to be set whenever reg 31 is
21060 set up as a frame pointer, even when there is no alloca call. */
21061 fprintf (file
, "%d,",
21062 ((optional_tbtab
<< 6)
21063 | ((optional_tbtab
& frame_pointer_needed
) << 5)
21064 | (info
->cr_save_p
<< 1)
21065 | (info
->lr_save_p
)));
21067 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
21069 fprintf (file
, "%d,",
21070 (info
->push_p
<< 7) | (64 - info
->first_fp_reg_save
));
21072 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
21073 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
21075 if (optional_tbtab
)
21077 /* Compute the parameter info from the function decl argument
21080 int next_parm_info_bit
= 31;
21082 for (decl
= DECL_ARGUMENTS (current_function_decl
);
21083 decl
; decl
= DECL_CHAIN (decl
))
21085 rtx parameter
= DECL_INCOMING_RTL (decl
);
21086 enum machine_mode mode
= GET_MODE (parameter
);
21088 if (GET_CODE (parameter
) == REG
)
21090 if (SCALAR_FLOAT_MODE_P (mode
))
21111 gcc_unreachable ();
21114 /* If only one bit will fit, don't or in this entry. */
21115 if (next_parm_info_bit
> 0)
21116 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
21117 next_parm_info_bit
-= 2;
21121 fixed_parms
+= ((GET_MODE_SIZE (mode
)
21122 + (UNITS_PER_WORD
- 1))
21124 next_parm_info_bit
-= 1;
21130 /* Number of fixed point parameters. */
21131 /* This is actually the number of words of fixed point parameters; thus
21132 an 8 byte struct counts as 2; and thus the maximum value is 8. */
21133 fprintf (file
, "%d,", fixed_parms
);
21135 /* 2 bitfields: number of floating point parameters (7 bits), parameters
21137 /* This is actually the number of fp registers that hold parameters;
21138 and thus the maximum value is 13. */
21139 /* Set parameters on stack bit if parameters are not in their original
21140 registers, regardless of whether they are on the stack? Xlc
21141 seems to set the bit when not optimizing. */
21142 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
21144 if (! optional_tbtab
)
21147 /* Optional fields follow. Some are variable length. */
21149 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
21150 11 double float. */
21151 /* There is an entry for each parameter in a register, in the order that
21152 they occur in the parameter list. Any intervening arguments on the
21153 stack are ignored. If the list overflows a long (max possible length
21154 34 bits) then completely leave off all elements that don't fit. */
21155 /* Only emit this long if there was at least one parameter. */
21156 if (fixed_parms
|| float_parms
)
21157 fprintf (file
, "\t.long %d\n", parm_info
);
21159 /* Offset from start of code to tb table. */
21160 fputs ("\t.long ", file
);
21161 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
21162 RS6000_OUTPUT_BASENAME (file
, fname
);
21164 rs6000_output_function_entry (file
, fname
);
21167 /* Interrupt handler mask. */
21168 /* Omit this long, since we never set the interrupt handler bit
21171 /* Number of CTL (controlled storage) anchors. */
21172 /* Omit this long, since the has_ctl bit is never set above. */
21174 /* Displacement into stack of each CTL anchor. */
21175 /* Omit this list of longs, because there are no CTL anchors. */
21177 /* Length of function name. */
21180 fprintf (file
, "\t.short %d\n", (int) strlen (fname
));
21182 /* Function name. */
21183 assemble_string (fname
, strlen (fname
));
21185 /* Register for alloca automatic storage; this is always reg 31.
21186 Only emit this if the alloca bit was set above. */
21187 if (frame_pointer_needed
)
21188 fputs ("\t.byte 31\n", file
);
21190 fputs ("\t.align 2\n", file
);
21194 /* A C compound statement that outputs the assembler code for a thunk
21195 function, used to implement C++ virtual function calls with
21196 multiple inheritance. The thunk acts as a wrapper around a virtual
21197 function, adjusting the implicit object parameter before handing
21198 control off to the real function.
21200 First, emit code to add the integer DELTA to the location that
21201 contains the incoming first argument. Assume that this argument
21202 contains a pointer, and is the one used to pass the `this' pointer
21203 in C++. This is the incoming argument *before* the function
21204 prologue, e.g. `%o0' on a sparc. The addition must preserve the
21205 values of all other incoming arguments.
21207 After the addition, emit code to jump to FUNCTION, which is a
21208 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
21209 not touch the return address. Hence returning from FUNCTION will
21210 return to whoever called the current `thunk'.
21212 The effect must be as if FUNCTION had been called directly with the
21213 adjusted first argument. This macro is responsible for emitting
21214 all of the code for a thunk function; output_function_prologue()
21215 and output_function_epilogue() are not invoked.
21217 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
21218 been extracted from it.) It might possibly be useful on some
21219 targets, but probably not.
21221 If you do not define this macro, the target-independent code in the
21222 C++ frontend will generate a less efficient heavyweight thunk that
21223 calls FUNCTION instead of jumping to it. The generic approach does
21224 not support varargs. */
21227 rs6000_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
21228 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
21231 rtx this_rtx
, insn
, funexp
;
21233 reload_completed
= 1;
21234 epilogue_completed
= 1;
21236 /* Mark the end of the (empty) prologue. */
21237 emit_note (NOTE_INSN_PROLOGUE_END
);
21239 /* Find the "this" pointer. If the function returns a structure,
21240 the structure return pointer is in r3. */
21241 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
21242 this_rtx
= gen_rtx_REG (Pmode
, 4);
21244 this_rtx
= gen_rtx_REG (Pmode
, 3);
21246 /* Apply the constant offset, if required. */
21248 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, GEN_INT (delta
)));
21250 /* Apply the offset from the vtable, if required. */
21253 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
21254 rtx tmp
= gen_rtx_REG (Pmode
, 12);
21256 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this_rtx
));
21257 if (((unsigned HOST_WIDE_INT
) vcall_offset
) + 0x8000 >= 0x10000)
21259 emit_insn (gen_add3_insn (tmp
, tmp
, vcall_offset_rtx
));
21260 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
21264 rtx loc
= gen_rtx_PLUS (Pmode
, tmp
, vcall_offset_rtx
);
21266 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, loc
));
21268 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, tmp
));
21271 /* Generate a tail call to the target function. */
21272 if (!TREE_USED (function
))
21274 assemble_external (function
);
21275 TREE_USED (function
) = 1;
21277 funexp
= XEXP (DECL_RTL (function
), 0);
21278 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
21281 if (MACHOPIC_INDIRECT
)
21282 funexp
= machopic_indirect_call_target (funexp
);
21285 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
21286 generate sibcall RTL explicitly. */
21287 insn
= emit_call_insn (
21288 gen_rtx_PARALLEL (VOIDmode
,
21290 gen_rtx_CALL (VOIDmode
,
21291 funexp
, const0_rtx
),
21292 gen_rtx_USE (VOIDmode
, const0_rtx
),
21293 gen_rtx_USE (VOIDmode
,
21294 gen_rtx_REG (SImode
,
21296 simple_return_rtx
)));
21297 SIBLING_CALL_P (insn
) = 1;
21300 /* Run just enough of rest_of_compilation to get the insns emitted.
21301 There's not really enough bulk here to make other passes such as
21302 instruction scheduling worth while. Note that use_thunk calls
21303 assemble_start_function and assemble_end_function. */
21304 insn
= get_insns ();
21305 insn_locators_alloc ();
21306 shorten_branches (insn
);
21307 final_start_function (insn
, file
, 1);
21308 final (insn
, file
, 1);
21309 final_end_function ();
21311 reload_completed
= 0;
21312 epilogue_completed
= 0;
21315 /* A quick summary of the various types of 'constant-pool tables'
21318 Target Flags Name One table per
21319 AIX (none) AIX TOC object file
21320 AIX -mfull-toc AIX TOC object file
21321 AIX -mminimal-toc AIX minimal TOC translation unit
21322 SVR4/EABI (none) SVR4 SDATA object file
21323 SVR4/EABI -fpic SVR4 pic object file
21324 SVR4/EABI -fPIC SVR4 PIC translation unit
21325 SVR4/EABI -mrelocatable EABI TOC function
21326 SVR4/EABI -maix AIX TOC object file
21327 SVR4/EABI -maix -mminimal-toc
21328 AIX minimal TOC translation unit
21330 Name Reg. Set by entries contains:
21331 made by addrs? fp? sum?
21333 AIX TOC 2 crt0 as Y option option
21334 AIX minimal TOC 30 prolog gcc Y Y option
21335 SVR4 SDATA 13 crt0 gcc N Y N
21336 SVR4 pic 30 prolog ld Y not yet N
21337 SVR4 PIC 30 prolog gcc Y option option
21338 EABI TOC 30 prolog gcc Y option option
21342 /* Hash functions for the hash table. */
21345 rs6000_hash_constant (rtx k
)
21347 enum rtx_code code
= GET_CODE (k
);
21348 enum machine_mode mode
= GET_MODE (k
);
21349 unsigned result
= (code
<< 3) ^ mode
;
21350 const char *format
;
21353 format
= GET_RTX_FORMAT (code
);
21354 flen
= strlen (format
);
21360 return result
* 1231 + (unsigned) INSN_UID (XEXP (k
, 0));
21363 if (mode
!= VOIDmode
)
21364 return real_hash (CONST_DOUBLE_REAL_VALUE (k
)) * result
;
21376 for (; fidx
< flen
; fidx
++)
21377 switch (format
[fidx
])
21382 const char *str
= XSTR (k
, fidx
);
21383 len
= strlen (str
);
21384 result
= result
* 613 + len
;
21385 for (i
= 0; i
< len
; i
++)
21386 result
= result
* 613 + (unsigned) str
[i
];
21391 result
= result
* 1231 + rs6000_hash_constant (XEXP (k
, fidx
));
21395 result
= result
* 613 + (unsigned) XINT (k
, fidx
);
21398 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT
))
21399 result
= result
* 613 + (unsigned) XWINT (k
, fidx
);
21403 for (i
= 0; i
< sizeof (HOST_WIDE_INT
) / sizeof (unsigned); i
++)
21404 result
= result
* 613 + (unsigned) (XWINT (k
, fidx
)
21411 gcc_unreachable ();
21418 toc_hash_function (const void *hash_entry
)
21420 const struct toc_hash_struct
*thc
=
21421 (const struct toc_hash_struct
*) hash_entry
;
21422 return rs6000_hash_constant (thc
->key
) ^ thc
->key_mode
;
21425 /* Compare H1 and H2 for equivalence. */
21428 toc_hash_eq (const void *h1
, const void *h2
)
21430 rtx r1
= ((const struct toc_hash_struct
*) h1
)->key
;
21431 rtx r2
= ((const struct toc_hash_struct
*) h2
)->key
;
21433 if (((const struct toc_hash_struct
*) h1
)->key_mode
21434 != ((const struct toc_hash_struct
*) h2
)->key_mode
)
21437 return rtx_equal_p (r1
, r2
);
21440 /* These are the names given by the C++ front-end to vtables, and
21441 vtable-like objects. Ideally, this logic should not be here;
21442 instead, there should be some programmatic way of inquiring as
21443 to whether or not an object is a vtable. */
21445 #define VTABLE_NAME_P(NAME) \
21446 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
21447 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
21448 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
21449 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
21450 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
21452 #ifdef NO_DOLLAR_IN_LABEL
21453 /* Return a GGC-allocated character string translating dollar signs in
21454 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
21457 rs6000_xcoff_strip_dollar (const char *name
)
21463 q
= (const char *) strchr (name
, '$');
21465 if (q
== 0 || q
== name
)
21468 len
= strlen (name
);
21469 strip
= XALLOCAVEC (char, len
+ 1);
21470 strcpy (strip
, name
);
21471 p
= strip
+ (q
- name
);
21475 p
= strchr (p
+ 1, '$');
21478 return ggc_alloc_string (strip
, len
);
21483 rs6000_output_symbol_ref (FILE *file
, rtx x
)
21485 /* Currently C++ toc references to vtables can be emitted before it
21486 is decided whether the vtable is public or private. If this is
21487 the case, then the linker will eventually complain that there is
21488 a reference to an unknown section. Thus, for vtables only,
21489 we emit the TOC reference to reference the symbol and not the
21491 const char *name
= XSTR (x
, 0);
21493 if (VTABLE_NAME_P (name
))
21495 RS6000_OUTPUT_BASENAME (file
, name
);
21498 assemble_name (file
, name
);
21501 /* Output a TOC entry. We derive the entry name from what is being
21505 output_toc (FILE *file
, rtx x
, int labelno
, enum machine_mode mode
)
21508 const char *name
= buf
;
21510 HOST_WIDE_INT offset
= 0;
21512 gcc_assert (!TARGET_NO_TOC
);
21514 /* When the linker won't eliminate them, don't output duplicate
21515 TOC entries (this happens on AIX if there is any kind of TOC,
21516 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
21518 if (TARGET_TOC
&& GET_CODE (x
) != LABEL_REF
)
21520 struct toc_hash_struct
*h
;
21523 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
21524 time because GGC is not initialized at that point. */
21525 if (toc_hash_table
== NULL
)
21526 toc_hash_table
= htab_create_ggc (1021, toc_hash_function
,
21527 toc_hash_eq
, NULL
);
21529 h
= ggc_alloc_toc_hash_struct ();
21531 h
->key_mode
= mode
;
21532 h
->labelno
= labelno
;
21534 found
= htab_find_slot (toc_hash_table
, h
, INSERT
);
21535 if (*found
== NULL
)
21537 else /* This is indeed a duplicate.
21538 Set this label equal to that label. */
21540 fputs ("\t.set ", file
);
21541 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
21542 fprintf (file
, "%d,", labelno
);
21543 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
21544 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
21550 /* If we're going to put a double constant in the TOC, make sure it's
21551 aligned properly when strict alignment is on. */
21552 if (GET_CODE (x
) == CONST_DOUBLE
21553 && STRICT_ALIGNMENT
21554 && GET_MODE_BITSIZE (mode
) >= 64
21555 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
)) {
21556 ASM_OUTPUT_ALIGN (file
, 3);
21559 (*targetm
.asm_out
.internal_label
) (file
, "LC", labelno
);
21561 /* Handle FP constants specially. Note that if we have a minimal
21562 TOC, things we put here aren't actually in the TOC, so we can allow
21564 if (GET_CODE (x
) == CONST_DOUBLE
&&
21565 (GET_MODE (x
) == TFmode
|| GET_MODE (x
) == TDmode
))
21567 REAL_VALUE_TYPE rv
;
21570 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
21571 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
21572 REAL_VALUE_TO_TARGET_DECIMAL128 (rv
, k
);
21574 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv
, k
);
21578 if (TARGET_MINIMAL_TOC
)
21579 fputs (DOUBLE_INT_ASM_OP
, file
);
21581 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
21582 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
21583 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
21584 fprintf (file
, "0x%lx%08lx,0x%lx%08lx\n",
21585 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
21586 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
21591 if (TARGET_MINIMAL_TOC
)
21592 fputs ("\t.long ", file
);
21594 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
21595 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
21596 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
21597 fprintf (file
, "0x%lx,0x%lx,0x%lx,0x%lx\n",
21598 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
21599 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
21603 else if (GET_CODE (x
) == CONST_DOUBLE
&&
21604 (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DDmode
))
21606 REAL_VALUE_TYPE rv
;
21609 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
21611 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
21612 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, k
);
21614 REAL_VALUE_TO_TARGET_DOUBLE (rv
, k
);
21618 if (TARGET_MINIMAL_TOC
)
21619 fputs (DOUBLE_INT_ASM_OP
, file
);
21621 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
21622 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
21623 fprintf (file
, "0x%lx%08lx\n",
21624 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
21629 if (TARGET_MINIMAL_TOC
)
21630 fputs ("\t.long ", file
);
21632 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
21633 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
21634 fprintf (file
, "0x%lx,0x%lx\n",
21635 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
21639 else if (GET_CODE (x
) == CONST_DOUBLE
&&
21640 (GET_MODE (x
) == SFmode
|| GET_MODE (x
) == SDmode
))
21642 REAL_VALUE_TYPE rv
;
21645 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
21646 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
21647 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
21649 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
21653 if (TARGET_MINIMAL_TOC
)
21654 fputs (DOUBLE_INT_ASM_OP
, file
);
21656 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
21657 fprintf (file
, "0x%lx00000000\n", l
& 0xffffffff);
21662 if (TARGET_MINIMAL_TOC
)
21663 fputs ("\t.long ", file
);
21665 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
21666 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
21670 else if (GET_MODE (x
) == VOIDmode
21671 && (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
))
21673 unsigned HOST_WIDE_INT low
;
21674 HOST_WIDE_INT high
;
21676 if (GET_CODE (x
) == CONST_DOUBLE
)
21678 low
= CONST_DOUBLE_LOW (x
);
21679 high
= CONST_DOUBLE_HIGH (x
);
21682 #if HOST_BITS_PER_WIDE_INT == 32
21685 high
= (low
& 0x80000000) ? ~0 : 0;
21689 low
= INTVAL (x
) & 0xffffffff;
21690 high
= (HOST_WIDE_INT
) INTVAL (x
) >> 32;
21694 /* TOC entries are always Pmode-sized, but since this
21695 is a bigendian machine then if we're putting smaller
21696 integer constants in the TOC we have to pad them.
21697 (This is still a win over putting the constants in
21698 a separate constant pool, because then we'd have
21699 to have both a TOC entry _and_ the actual constant.)
21701 For a 32-bit target, CONST_INT values are loaded and shifted
21702 entirely within `low' and can be stored in one TOC entry. */
21704 /* It would be easy to make this work, but it doesn't now. */
21705 gcc_assert (!TARGET_64BIT
|| POINTER_SIZE
>= GET_MODE_BITSIZE (mode
));
21707 if (POINTER_SIZE
> GET_MODE_BITSIZE (mode
))
21709 #if HOST_BITS_PER_WIDE_INT == 32
21710 lshift_double (low
, high
, POINTER_SIZE
- GET_MODE_BITSIZE (mode
),
21711 POINTER_SIZE
, &low
, &high
, 0);
21714 low
<<= POINTER_SIZE
- GET_MODE_BITSIZE (mode
);
21715 high
= (HOST_WIDE_INT
) low
>> 32;
21722 if (TARGET_MINIMAL_TOC
)
21723 fputs (DOUBLE_INT_ASM_OP
, file
);
21725 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
21726 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
21727 fprintf (file
, "0x%lx%08lx\n",
21728 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
21733 if (POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
21735 if (TARGET_MINIMAL_TOC
)
21736 fputs ("\t.long ", file
);
21738 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
21739 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
21740 fprintf (file
, "0x%lx,0x%lx\n",
21741 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
21745 if (TARGET_MINIMAL_TOC
)
21746 fputs ("\t.long ", file
);
21748 fprintf (file
, "\t.tc IS_%lx[TC],", (long) low
& 0xffffffff);
21749 fprintf (file
, "0x%lx\n", (long) low
& 0xffffffff);
21755 if (GET_CODE (x
) == CONST
)
21757 gcc_assert (GET_CODE (XEXP (x
, 0)) == PLUS
21758 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
);
21760 base
= XEXP (XEXP (x
, 0), 0);
21761 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
21764 switch (GET_CODE (base
))
21767 name
= XSTR (base
, 0);
21771 ASM_GENERATE_INTERNAL_LABEL (buf
, "L",
21772 CODE_LABEL_NUMBER (XEXP (base
, 0)));
21776 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
21780 gcc_unreachable ();
21783 if (TARGET_MINIMAL_TOC
)
21784 fputs (TARGET_32BIT
? "\t.long " : DOUBLE_INT_ASM_OP
, file
);
21787 fputs ("\t.tc ", file
);
21788 RS6000_OUTPUT_BASENAME (file
, name
);
21791 fprintf (file
, ".N" HOST_WIDE_INT_PRINT_UNSIGNED
, - offset
);
21793 fprintf (file
, ".P" HOST_WIDE_INT_PRINT_UNSIGNED
, offset
);
21795 fputs ("[TC],", file
);
21798 /* Currently C++ toc references to vtables can be emitted before it
21799 is decided whether the vtable is public or private. If this is
21800 the case, then the linker will eventually complain that there is
21801 a TOC reference to an unknown section. Thus, for vtables only,
21802 we emit the TOC reference to reference the symbol and not the
21804 if (VTABLE_NAME_P (name
))
21806 RS6000_OUTPUT_BASENAME (file
, name
);
21808 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
21809 else if (offset
> 0)
21810 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
21813 output_addr_const (file
, x
);
21817 /* Output an assembler pseudo-op to write an ASCII string of N characters
21818 starting at P to FILE.
21820 On the RS/6000, we have to do this using the .byte operation and
21821 write out special characters outside the quoted string.
21822 Also, the assembler is broken; very long strings are truncated,
21823 so we must artificially break them up early. */
21826 output_ascii (FILE *file
, const char *p
, int n
)
21829 int i
, count_string
;
21830 const char *for_string
= "\t.byte \"";
21831 const char *for_decimal
= "\t.byte ";
21832 const char *to_close
= NULL
;
21835 for (i
= 0; i
< n
; i
++)
21838 if (c
>= ' ' && c
< 0177)
21841 fputs (for_string
, file
);
21844 /* Write two quotes to get one. */
21852 for_decimal
= "\"\n\t.byte ";
21856 if (count_string
>= 512)
21858 fputs (to_close
, file
);
21860 for_string
= "\t.byte \"";
21861 for_decimal
= "\t.byte ";
21869 fputs (for_decimal
, file
);
21870 fprintf (file
, "%d", c
);
21872 for_string
= "\n\t.byte \"";
21873 for_decimal
= ", ";
21879 /* Now close the string if we have written one. Then end the line. */
21881 fputs (to_close
, file
);
21884 /* Generate a unique section name for FILENAME for a section type
21885 represented by SECTION_DESC. Output goes into BUF.
21887 SECTION_DESC can be any string, as long as it is different for each
21888 possible section type.
21890 We name the section in the same manner as xlc. The name begins with an
21891 underscore followed by the filename (after stripping any leading directory
21892 names) with the last period replaced by the string SECTION_DESC. If
21893 FILENAME does not contain a period, SECTION_DESC is appended to the end of
21897 rs6000_gen_section_name (char **buf
, const char *filename
,
21898 const char *section_desc
)
21900 const char *q
, *after_last_slash
, *last_period
= 0;
21904 after_last_slash
= filename
;
21905 for (q
= filename
; *q
; q
++)
21908 after_last_slash
= q
+ 1;
21909 else if (*q
== '.')
21913 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
21914 *buf
= (char *) xmalloc (len
);
21919 for (q
= after_last_slash
; *q
; q
++)
21921 if (q
== last_period
)
21923 strcpy (p
, section_desc
);
21924 p
+= strlen (section_desc
);
21928 else if (ISALNUM (*q
))
21932 if (last_period
== 0)
21933 strcpy (p
, section_desc
);
21938 /* Emit profile function. */
21941 output_profile_hook (int labelno ATTRIBUTE_UNUSED
)
21943 /* Non-standard profiling for kernels, which just saves LR then calls
21944 _mcount without worrying about arg saves. The idea is to change
21945 the function prologue as little as possible as it isn't easy to
21946 account for arg save/restore code added just for _mcount. */
21947 if (TARGET_PROFILE_KERNEL
)
21950 if (DEFAULT_ABI
== ABI_AIX
)
21952 #ifndef NO_PROFILE_COUNTERS
21953 # define NO_PROFILE_COUNTERS 0
21955 if (NO_PROFILE_COUNTERS
)
21956 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
21957 LCT_NORMAL
, VOIDmode
, 0);
21961 const char *label_name
;
21964 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
21965 label_name
= ggc_strdup ((*targetm
.strip_name_encoding
) (buf
));
21966 fun
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
21968 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
21969 LCT_NORMAL
, VOIDmode
, 1, fun
, Pmode
);
21972 else if (DEFAULT_ABI
== ABI_DARWIN
)
21974 const char *mcount_name
= RS6000_MCOUNT
;
21975 int caller_addr_regno
= LR_REGNO
;
21977 /* Be conservative and always set this, at least for now. */
21978 crtl
->uses_pic_offset_table
= 1;
21981 /* For PIC code, set up a stub and collect the caller's address
21982 from r0, which is where the prologue puts it. */
21983 if (MACHOPIC_INDIRECT
21984 && crtl
->uses_pic_offset_table
)
21985 caller_addr_regno
= 0;
21987 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, mcount_name
),
21988 LCT_NORMAL
, VOIDmode
, 1,
21989 gen_rtx_REG (Pmode
, caller_addr_regno
), Pmode
);
21993 /* Write function profiler code. */
21996 output_function_profiler (FILE *file
, int labelno
)
22000 switch (DEFAULT_ABI
)
22003 gcc_unreachable ();
22008 warning (0, "no profiling of 64-bit code for this ABI");
22011 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
22012 fprintf (file
, "\tmflr %s\n", reg_names
[0]);
22013 if (NO_PROFILE_COUNTERS
)
22015 asm_fprintf (file
, "\t{st|stw} %s,4(%s)\n",
22016 reg_names
[0], reg_names
[1]);
22018 else if (TARGET_SECURE_PLT
&& flag_pic
)
22020 if (TARGET_LINK_STACK
)
22023 get_ppc476_thunk_name (name
);
22024 asm_fprintf (file
, "\tbl %s\n", name
);
22027 asm_fprintf (file
, "\tbcl 20,31,1f\n1:\n");
22028 asm_fprintf (file
, "\t{st|stw} %s,4(%s)\n",
22029 reg_names
[0], reg_names
[1]);
22030 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
22031 asm_fprintf (file
, "\t{cau|addis} %s,%s,",
22032 reg_names
[12], reg_names
[12]);
22033 assemble_name (file
, buf
);
22034 asm_fprintf (file
, "-1b@ha\n\t{cal|la} %s,", reg_names
[0]);
22035 assemble_name (file
, buf
);
22036 asm_fprintf (file
, "-1b@l(%s)\n", reg_names
[12]);
22038 else if (flag_pic
== 1)
22040 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file
);
22041 asm_fprintf (file
, "\t{st|stw} %s,4(%s)\n",
22042 reg_names
[0], reg_names
[1]);
22043 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
22044 asm_fprintf (file
, "\t{l|lwz} %s,", reg_names
[0]);
22045 assemble_name (file
, buf
);
22046 asm_fprintf (file
, "@got(%s)\n", reg_names
[12]);
22048 else if (flag_pic
> 1)
22050 asm_fprintf (file
, "\t{st|stw} %s,4(%s)\n",
22051 reg_names
[0], reg_names
[1]);
22052 /* Now, we need to get the address of the label. */
22053 if (TARGET_LINK_STACK
)
22056 get_ppc476_thunk_name (name
);
22057 asm_fprintf (file
, "\tbl %s\n\tb 1f\n\t.long ", name
);
22058 assemble_name (file
, buf
);
22059 fputs ("-.\n1:", file
);
22060 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
22061 asm_fprintf (file
, "\taddi %s,%s,4\n",
22062 reg_names
[11], reg_names
[11]);
22066 fputs ("\tbcl 20,31,1f\n\t.long ", file
);
22067 assemble_name (file
, buf
);
22068 fputs ("-.\n1:", file
);
22069 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
22071 asm_fprintf (file
, "\t{l|lwz} %s,0(%s)\n",
22072 reg_names
[0], reg_names
[11]);
22073 asm_fprintf (file
, "\t{cax|add} %s,%s,%s\n",
22074 reg_names
[0], reg_names
[0], reg_names
[11]);
22078 asm_fprintf (file
, "\t{liu|lis} %s,", reg_names
[12]);
22079 assemble_name (file
, buf
);
22080 fputs ("@ha\n", file
);
22081 asm_fprintf (file
, "\t{st|stw} %s,4(%s)\n",
22082 reg_names
[0], reg_names
[1]);
22083 asm_fprintf (file
, "\t{cal|la} %s,", reg_names
[0]);
22084 assemble_name (file
, buf
);
22085 asm_fprintf (file
, "@l(%s)\n", reg_names
[12]);
22088 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
22089 fprintf (file
, "\tbl %s%s\n",
22090 RS6000_MCOUNT
, flag_pic
? "@plt" : "");
22095 if (!TARGET_PROFILE_KERNEL
)
22097 /* Don't do anything, done in output_profile_hook (). */
22101 gcc_assert (!TARGET_32BIT
);
22103 asm_fprintf (file
, "\tmflr %s\n", reg_names
[0]);
22104 asm_fprintf (file
, "\tstd %s,16(%s)\n", reg_names
[0], reg_names
[1]);
22106 if (cfun
->static_chain_decl
!= NULL
)
22108 asm_fprintf (file
, "\tstd %s,24(%s)\n",
22109 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
22110 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
22111 asm_fprintf (file
, "\tld %s,24(%s)\n",
22112 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
22115 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
22123 /* The following variable value is the last issued insn. */
22125 static rtx last_scheduled_insn
;
22127 /* The following variable helps to balance issuing of load and
22128 store instructions */
22130 static int load_store_pendulum
;
22132 /* Power4 load update and store update instructions are cracked into a
22133 load or store and an integer insn which are executed in the same cycle.
22134 Branches have their own dispatch slot which does not count against the
22135 GCC issue rate, but it changes the program flow so there are no other
22136 instructions to issue in this cycle. */
22139 rs6000_variable_issue_1 (rtx insn
, int more
)
22141 last_scheduled_insn
= insn
;
22142 if (GET_CODE (PATTERN (insn
)) == USE
22143 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
22145 cached_can_issue_more
= more
;
22146 return cached_can_issue_more
;
22149 if (insn_terminates_group_p (insn
, current_group
))
22151 cached_can_issue_more
= 0;
22152 return cached_can_issue_more
;
22155 /* If no reservation, but reach here */
22156 if (recog_memoized (insn
) < 0)
22159 if (rs6000_sched_groups
)
22161 if (is_microcoded_insn (insn
))
22162 cached_can_issue_more
= 0;
22163 else if (is_cracked_insn (insn
))
22164 cached_can_issue_more
= more
> 2 ? more
- 2 : 0;
22166 cached_can_issue_more
= more
- 1;
22168 return cached_can_issue_more
;
22171 if (rs6000_cpu_attr
== CPU_CELL
&& is_nonpipeline_insn (insn
))
22174 cached_can_issue_more
= more
- 1;
22175 return cached_can_issue_more
;
22179 rs6000_variable_issue (FILE *stream
, int verbose
, rtx insn
, int more
)
22181 int r
= rs6000_variable_issue_1 (insn
, more
);
22183 fprintf (stream
, "// rs6000_variable_issue (more = %d) = %d\n", more
, r
);
22187 /* Adjust the cost of a scheduling dependency. Return the new cost of
22188 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
22191 rs6000_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
22193 enum attr_type attr_type
;
22195 if (! recog_memoized (insn
))
22198 switch (REG_NOTE_KIND (link
))
22202 /* Data dependency; DEP_INSN writes a register that INSN reads
22203 some cycles later. */
22205 /* Separate a load from a narrower, dependent store. */
22206 if (rs6000_sched_groups
22207 && GET_CODE (PATTERN (insn
)) == SET
22208 && GET_CODE (PATTERN (dep_insn
)) == SET
22209 && GET_CODE (XEXP (PATTERN (insn
), 1)) == MEM
22210 && GET_CODE (XEXP (PATTERN (dep_insn
), 0)) == MEM
22211 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn
), 1)))
22212 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn
), 0)))))
22215 attr_type
= get_attr_type (insn
);
22220 /* Tell the first scheduling pass about the latency between
22221 a mtctr and bctr (and mtlr and br/blr). The first
22222 scheduling pass will not know about this latency since
22223 the mtctr instruction, which has the latency associated
22224 to it, will be generated by reload. */
22225 return TARGET_POWER
? 5 : 4;
22227 /* Leave some extra cycles between a compare and its
22228 dependent branch, to inhibit expensive mispredicts. */
22229 if ((rs6000_cpu_attr
== CPU_PPC603
22230 || rs6000_cpu_attr
== CPU_PPC604
22231 || rs6000_cpu_attr
== CPU_PPC604E
22232 || rs6000_cpu_attr
== CPU_PPC620
22233 || rs6000_cpu_attr
== CPU_PPC630
22234 || rs6000_cpu_attr
== CPU_PPC750
22235 || rs6000_cpu_attr
== CPU_PPC7400
22236 || rs6000_cpu_attr
== CPU_PPC7450
22237 || rs6000_cpu_attr
== CPU_POWER4
22238 || rs6000_cpu_attr
== CPU_POWER5
22239 || rs6000_cpu_attr
== CPU_POWER7
22240 || rs6000_cpu_attr
== CPU_CELL
)
22241 && recog_memoized (dep_insn
)
22242 && (INSN_CODE (dep_insn
) >= 0))
22244 switch (get_attr_type (dep_insn
))
22248 case TYPE_DELAYED_COMPARE
:
22249 case TYPE_IMUL_COMPARE
:
22250 case TYPE_LMUL_COMPARE
:
22251 case TYPE_FPCOMPARE
:
22252 case TYPE_CR_LOGICAL
:
22253 case TYPE_DELAYED_CR
:
22262 case TYPE_STORE_UX
:
22264 case TYPE_FPSTORE_U
:
22265 case TYPE_FPSTORE_UX
:
22266 if ((rs6000_cpu
== PROCESSOR_POWER6
)
22267 && recog_memoized (dep_insn
)
22268 && (INSN_CODE (dep_insn
) >= 0))
22271 if (GET_CODE (PATTERN (insn
)) != SET
)
22272 /* If this happens, we have to extend this to schedule
22273 optimally. Return default for now. */
22276 /* Adjust the cost for the case where the value written
22277 by a fixed point operation is used as the address
22278 gen value on a store. */
22279 switch (get_attr_type (dep_insn
))
22286 if (! store_data_bypass_p (dep_insn
, insn
))
22290 case TYPE_LOAD_EXT
:
22291 case TYPE_LOAD_EXT_U
:
22292 case TYPE_LOAD_EXT_UX
:
22293 case TYPE_VAR_SHIFT_ROTATE
:
22294 case TYPE_VAR_DELAYED_COMPARE
:
22296 if (! store_data_bypass_p (dep_insn
, insn
))
22302 case TYPE_FAST_COMPARE
:
22305 case TYPE_INSERT_WORD
:
22306 case TYPE_INSERT_DWORD
:
22307 case TYPE_FPLOAD_U
:
22308 case TYPE_FPLOAD_UX
:
22310 case TYPE_STORE_UX
:
22311 case TYPE_FPSTORE_U
:
22312 case TYPE_FPSTORE_UX
:
22314 if (! store_data_bypass_p (dep_insn
, insn
))
22322 case TYPE_IMUL_COMPARE
:
22323 case TYPE_LMUL_COMPARE
:
22325 if (! store_data_bypass_p (dep_insn
, insn
))
22331 if (! store_data_bypass_p (dep_insn
, insn
))
22337 if (! store_data_bypass_p (dep_insn
, insn
))
22350 case TYPE_LOAD_EXT
:
22351 case TYPE_LOAD_EXT_U
:
22352 case TYPE_LOAD_EXT_UX
:
22353 if ((rs6000_cpu
== PROCESSOR_POWER6
)
22354 && recog_memoized (dep_insn
)
22355 && (INSN_CODE (dep_insn
) >= 0))
22358 /* Adjust the cost for the case where the value written
22359 by a fixed point instruction is used within the address
22360 gen portion of a subsequent load(u)(x) */
22361 switch (get_attr_type (dep_insn
))
22368 if (set_to_load_agen (dep_insn
, insn
))
22372 case TYPE_LOAD_EXT
:
22373 case TYPE_LOAD_EXT_U
:
22374 case TYPE_LOAD_EXT_UX
:
22375 case TYPE_VAR_SHIFT_ROTATE
:
22376 case TYPE_VAR_DELAYED_COMPARE
:
22378 if (set_to_load_agen (dep_insn
, insn
))
22384 case TYPE_FAST_COMPARE
:
22387 case TYPE_INSERT_WORD
:
22388 case TYPE_INSERT_DWORD
:
22389 case TYPE_FPLOAD_U
:
22390 case TYPE_FPLOAD_UX
:
22392 case TYPE_STORE_UX
:
22393 case TYPE_FPSTORE_U
:
22394 case TYPE_FPSTORE_UX
:
22396 if (set_to_load_agen (dep_insn
, insn
))
22404 case TYPE_IMUL_COMPARE
:
22405 case TYPE_LMUL_COMPARE
:
22407 if (set_to_load_agen (dep_insn
, insn
))
22413 if (set_to_load_agen (dep_insn
, insn
))
22419 if (set_to_load_agen (dep_insn
, insn
))
22430 if ((rs6000_cpu
== PROCESSOR_POWER6
)
22431 && recog_memoized (dep_insn
)
22432 && (INSN_CODE (dep_insn
) >= 0)
22433 && (get_attr_type (dep_insn
) == TYPE_MFFGPR
))
22440 /* Fall out to return default cost. */
22444 case REG_DEP_OUTPUT
:
22445 /* Output dependency; DEP_INSN writes a register that INSN writes some
22447 if ((rs6000_cpu
== PROCESSOR_POWER6
)
22448 && recog_memoized (dep_insn
)
22449 && (INSN_CODE (dep_insn
) >= 0))
22451 attr_type
= get_attr_type (insn
);
22456 if (get_attr_type (dep_insn
) == TYPE_FP
)
22460 if (get_attr_type (dep_insn
) == TYPE_MFFGPR
)
22468 /* Anti dependency; DEP_INSN reads a register that INSN writes some
22473 gcc_unreachable ();
22479 /* Debug version of rs6000_adjust_cost. */
22482 rs6000_debug_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
22484 int ret
= rs6000_adjust_cost (insn
, link
, dep_insn
, cost
);
22490 switch (REG_NOTE_KIND (link
))
22492 default: dep
= "unknown depencency"; break;
22493 case REG_DEP_TRUE
: dep
= "data dependency"; break;
22494 case REG_DEP_OUTPUT
: dep
= "output dependency"; break;
22495 case REG_DEP_ANTI
: dep
= "anti depencency"; break;
22499 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
22500 "%s, insn:\n", ret
, cost
, dep
);
22508 /* The function returns a true if INSN is microcoded.
22509 Return false otherwise. */
22512 is_microcoded_insn (rtx insn
)
22514 if (!insn
|| !NONDEBUG_INSN_P (insn
)
22515 || GET_CODE (PATTERN (insn
)) == USE
22516 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
22519 if (rs6000_cpu_attr
== CPU_CELL
)
22520 return get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
;
22522 if (rs6000_sched_groups
)
22524 enum attr_type type
= get_attr_type (insn
);
22525 if (type
== TYPE_LOAD_EXT_U
22526 || type
== TYPE_LOAD_EXT_UX
22527 || type
== TYPE_LOAD_UX
22528 || type
== TYPE_STORE_UX
22529 || type
== TYPE_MFCR
)
22536 /* The function returns true if INSN is cracked into 2 instructions
22537 by the processor (and therefore occupies 2 issue slots). */
22540 is_cracked_insn (rtx insn
)
22542 if (!insn
|| !NONDEBUG_INSN_P (insn
)
22543 || GET_CODE (PATTERN (insn
)) == USE
22544 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
22547 if (rs6000_sched_groups
)
22549 enum attr_type type
= get_attr_type (insn
);
22550 if (type
== TYPE_LOAD_U
|| type
== TYPE_STORE_U
22551 || type
== TYPE_FPLOAD_U
|| type
== TYPE_FPSTORE_U
22552 || type
== TYPE_FPLOAD_UX
|| type
== TYPE_FPSTORE_UX
22553 || type
== TYPE_LOAD_EXT
|| type
== TYPE_DELAYED_CR
22554 || type
== TYPE_COMPARE
|| type
== TYPE_DELAYED_COMPARE
22555 || type
== TYPE_IMUL_COMPARE
|| type
== TYPE_LMUL_COMPARE
22556 || type
== TYPE_IDIV
|| type
== TYPE_LDIV
22557 || type
== TYPE_INSERT_WORD
)
22564 /* The function returns true if INSN can be issued only from
22565 the branch slot. */
22568 is_branch_slot_insn (rtx insn
)
22570 if (!insn
|| !NONDEBUG_INSN_P (insn
)
22571 || GET_CODE (PATTERN (insn
)) == USE
22572 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
22575 if (rs6000_sched_groups
)
22577 enum attr_type type
= get_attr_type (insn
);
22578 if (type
== TYPE_BRANCH
|| type
== TYPE_JMPREG
)
22586 /* The function returns true if out_inst sets a value that is
22587 used in the address generation computation of in_insn */
22589 set_to_load_agen (rtx out_insn
, rtx in_insn
)
22591 rtx out_set
, in_set
;
22593 /* For performance reasons, only handle the simple case where
22594 both loads are a single_set. */
22595 out_set
= single_set (out_insn
);
22598 in_set
= single_set (in_insn
);
22600 return reg_mentioned_p (SET_DEST (out_set
), SET_SRC (in_set
));
22606 /* The function returns true if the target storage location of
22607 out_insn is adjacent to the target storage location of in_insn */
22608 /* Return 1 if memory locations are adjacent. */
22611 adjacent_mem_locations (rtx insn1
, rtx insn2
)
22614 rtx a
= get_store_dest (PATTERN (insn1
));
22615 rtx b
= get_store_dest (PATTERN (insn2
));
22617 if ((GET_CODE (XEXP (a
, 0)) == REG
22618 || (GET_CODE (XEXP (a
, 0)) == PLUS
22619 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
22620 && (GET_CODE (XEXP (b
, 0)) == REG
22621 || (GET_CODE (XEXP (b
, 0)) == PLUS
22622 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
22624 HOST_WIDE_INT val0
= 0, val1
= 0, val_diff
;
22627 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
22629 reg0
= XEXP (XEXP (a
, 0), 0);
22630 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
22633 reg0
= XEXP (a
, 0);
22635 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
22637 reg1
= XEXP (XEXP (b
, 0), 0);
22638 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
22641 reg1
= XEXP (b
, 0);
22643 val_diff
= val1
- val0
;
22645 return ((REGNO (reg0
) == REGNO (reg1
))
22646 && ((MEM_SIZE_KNOWN_P (a
) && val_diff
== MEM_SIZE (a
))
22647 || (MEM_SIZE_KNOWN_P (b
) && val_diff
== -MEM_SIZE (b
))));
22653 /* A C statement (sans semicolon) to update the integer scheduling
22654 priority INSN_PRIORITY (INSN). Increase the priority to execute the
22655 INSN earlier, reduce the priority to execute INSN later. Do not
22656 define this macro if you do not need to adjust the scheduling
22657 priorities of insns. */
22660 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
22662 /* On machines (like the 750) which have asymmetric integer units,
22663 where one integer unit can do multiply and divides and the other
22664 can't, reduce the priority of multiply/divide so it is scheduled
22665 before other integer operations. */
22668 if (! INSN_P (insn
))
22671 if (GET_CODE (PATTERN (insn
)) == USE
)
22674 switch (rs6000_cpu_attr
) {
22676 switch (get_attr_type (insn
))
22683 fprintf (stderr
, "priority was %#x (%d) before adjustment\n",
22684 priority
, priority
);
22685 if (priority
>= 0 && priority
< 0x01000000)
22692 if (insn_must_be_first_in_group (insn
)
22693 && reload_completed
22694 && current_sched_info
->sched_max_insns_priority
22695 && rs6000_sched_restricted_insns_priority
)
22698 /* Prioritize insns that can be dispatched only in the first
22700 if (rs6000_sched_restricted_insns_priority
== 1)
22701 /* Attach highest priority to insn. This means that in
22702 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
22703 precede 'priority' (critical path) considerations. */
22704 return current_sched_info
->sched_max_insns_priority
;
22705 else if (rs6000_sched_restricted_insns_priority
== 2)
22706 /* Increase priority of insn by a minimal amount. This means that in
22707 haifa-sched.c:ready_sort(), only 'priority' (critical path)
22708 considerations precede dispatch-slot restriction considerations. */
22709 return (priority
+ 1);
22712 if (rs6000_cpu
== PROCESSOR_POWER6
22713 && ((load_store_pendulum
== -2 && is_load_insn (insn
))
22714 || (load_store_pendulum
== 2 && is_store_insn (insn
))))
22715 /* Attach highest priority to insn if the scheduler has just issued two
22716 stores and this instruction is a load, or two loads and this instruction
22717 is a store. Power6 wants loads and stores scheduled alternately
22719 return current_sched_info
->sched_max_insns_priority
;
22724 /* Return true if the instruction is nonpipelined on the Cell. */
22726 is_nonpipeline_insn (rtx insn
)
22728 enum attr_type type
;
22729 if (!insn
|| !NONDEBUG_INSN_P (insn
)
22730 || GET_CODE (PATTERN (insn
)) == USE
22731 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
22734 type
= get_attr_type (insn
);
22735 if (type
== TYPE_IMUL
22736 || type
== TYPE_IMUL2
22737 || type
== TYPE_IMUL3
22738 || type
== TYPE_LMUL
22739 || type
== TYPE_IDIV
22740 || type
== TYPE_LDIV
22741 || type
== TYPE_SDIV
22742 || type
== TYPE_DDIV
22743 || type
== TYPE_SSQRT
22744 || type
== TYPE_DSQRT
22745 || type
== TYPE_MFCR
22746 || type
== TYPE_MFCRF
22747 || type
== TYPE_MFJMPR
)
22755 /* Return how many instructions the machine can issue per cycle. */
22758 rs6000_issue_rate (void)
22760 /* Unless scheduling for register pressure, use issue rate of 1 for
22761 first scheduling pass to decrease degradation. */
22762 if (!reload_completed
&& !flag_sched_pressure
)
22765 switch (rs6000_cpu_attr
) {
22766 case CPU_RIOS1
: /* ? */
22768 case CPU_PPC601
: /* ? */
22777 case CPU_PPCE300C2
:
22778 case CPU_PPCE300C3
:
22779 case CPU_PPCE500MC
:
22780 case CPU_PPCE500MC64
:
22800 /* Return how many instructions to look ahead for better insn
22804 rs6000_use_sched_lookahead (void)
22806 if (rs6000_cpu_attr
== CPU_PPC8540
)
22808 if (rs6000_cpu_attr
== CPU_CELL
)
22809 return (reload_completed
? 8 : 0);
22813 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
22815 rs6000_use_sched_lookahead_guard (rtx insn
)
22817 if (rs6000_cpu_attr
!= CPU_CELL
)
22820 if (insn
== NULL_RTX
|| !INSN_P (insn
))
22823 if (!reload_completed
22824 || is_nonpipeline_insn (insn
)
22825 || is_microcoded_insn (insn
))
22831 /* Determine is PAT refers to memory. */
22834 is_mem_ref (rtx pat
)
22840 /* stack_tie does not produce any real memory traffic. */
22841 if (GET_CODE (pat
) == UNSPEC
22842 && XINT (pat
, 1) == UNSPEC_TIE
)
22845 if (GET_CODE (pat
) == MEM
)
22848 /* Recursively process the pattern. */
22849 fmt
= GET_RTX_FORMAT (GET_CODE (pat
));
22851 for (i
= GET_RTX_LENGTH (GET_CODE (pat
)) - 1; i
>= 0 && !ret
; i
--)
22854 ret
|= is_mem_ref (XEXP (pat
, i
));
22855 else if (fmt
[i
] == 'E')
22856 for (j
= XVECLEN (pat
, i
) - 1; j
>= 0; j
--)
22857 ret
|= is_mem_ref (XVECEXP (pat
, i
, j
));
22863 /* Determine if PAT is a PATTERN of a load insn. */
22866 is_load_insn1 (rtx pat
)
22868 if (!pat
|| pat
== NULL_RTX
)
22871 if (GET_CODE (pat
) == SET
)
22872 return is_mem_ref (SET_SRC (pat
));
22874 if (GET_CODE (pat
) == PARALLEL
)
22878 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
22879 if (is_load_insn1 (XVECEXP (pat
, 0, i
)))
22886 /* Determine if INSN loads from memory. */
22889 is_load_insn (rtx insn
)
22891 if (!insn
|| !INSN_P (insn
))
22894 if (GET_CODE (insn
) == CALL_INSN
)
22897 return is_load_insn1 (PATTERN (insn
));
22900 /* Determine if PAT is a PATTERN of a store insn. */
22903 is_store_insn1 (rtx pat
)
22905 if (!pat
|| pat
== NULL_RTX
)
22908 if (GET_CODE (pat
) == SET
)
22909 return is_mem_ref (SET_DEST (pat
));
22911 if (GET_CODE (pat
) == PARALLEL
)
22915 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
22916 if (is_store_insn1 (XVECEXP (pat
, 0, i
)))
22923 /* Determine if INSN stores to memory. */
22926 is_store_insn (rtx insn
)
22928 if (!insn
|| !INSN_P (insn
))
22931 return is_store_insn1 (PATTERN (insn
));
22934 /* Return the dest of a store insn. */
22937 get_store_dest (rtx pat
)
22939 gcc_assert (is_store_insn1 (pat
));
22941 if (GET_CODE (pat
) == SET
)
22942 return SET_DEST (pat
);
22943 else if (GET_CODE (pat
) == PARALLEL
)
22947 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
22949 rtx inner_pat
= XVECEXP (pat
, 0, i
);
22950 if (GET_CODE (inner_pat
) == SET
22951 && is_mem_ref (SET_DEST (inner_pat
)))
22955 /* We shouldn't get here, because we should have either a simple
22956 store insn or a store with update which are covered above. */
22960 /* Returns whether the dependence between INSN and NEXT is considered
22961 costly by the given target. */
22964 rs6000_is_costly_dependence (dep_t dep
, int cost
, int distance
)
22969 /* If the flag is not enabled - no dependence is considered costly;
22970 allow all dependent insns in the same group.
22971 This is the most aggressive option. */
22972 if (rs6000_sched_costly_dep
== no_dep_costly
)
22975 /* If the flag is set to 1 - a dependence is always considered costly;
22976 do not allow dependent instructions in the same group.
22977 This is the most conservative option. */
22978 if (rs6000_sched_costly_dep
== all_deps_costly
)
22981 insn
= DEP_PRO (dep
);
22982 next
= DEP_CON (dep
);
22984 if (rs6000_sched_costly_dep
== store_to_load_dep_costly
22985 && is_load_insn (next
)
22986 && is_store_insn (insn
))
22987 /* Prevent load after store in the same group. */
22990 if (rs6000_sched_costly_dep
== true_store_to_load_dep_costly
22991 && is_load_insn (next
)
22992 && is_store_insn (insn
)
22993 && DEP_TYPE (dep
) == REG_DEP_TRUE
)
22994 /* Prevent load after store in the same group if it is a true
22998 /* The flag is set to X; dependences with latency >= X are considered costly,
22999 and will not be scheduled in the same group. */
23000 if (rs6000_sched_costly_dep
<= max_dep_latency
23001 && ((cost
- distance
) >= (int)rs6000_sched_costly_dep
))
23007 /* Return the next insn after INSN that is found before TAIL is reached,
23008 skipping any "non-active" insns - insns that will not actually occupy
23009 an issue slot. Return NULL_RTX if such an insn is not found. */
23012 get_next_active_insn (rtx insn
, rtx tail
)
23014 if (insn
== NULL_RTX
|| insn
== tail
)
23019 insn
= NEXT_INSN (insn
);
23020 if (insn
== NULL_RTX
|| insn
== tail
)
23025 || (NONJUMP_INSN_P (insn
)
23026 && GET_CODE (PATTERN (insn
)) != USE
23027 && GET_CODE (PATTERN (insn
)) != CLOBBER
23028 && INSN_CODE (insn
) != CODE_FOR_stack_tie
))
23034 /* We are about to begin issuing insns for this clock cycle. */
23037 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED
, int sched_verbose
,
23038 rtx
*ready ATTRIBUTE_UNUSED
,
23039 int *pn_ready ATTRIBUTE_UNUSED
,
23040 int clock_var ATTRIBUTE_UNUSED
)
23042 int n_ready
= *pn_ready
;
23045 fprintf (dump
, "// rs6000_sched_reorder :\n");
23047 /* Reorder the ready list, if the second to last ready insn
23048 is a nonepipeline insn. */
23049 if (rs6000_cpu_attr
== CPU_CELL
&& n_ready
> 1)
23051 if (is_nonpipeline_insn (ready
[n_ready
- 1])
23052 && (recog_memoized (ready
[n_ready
- 2]) > 0))
23053 /* Simply swap first two insns. */
23055 rtx tmp
= ready
[n_ready
- 1];
23056 ready
[n_ready
- 1] = ready
[n_ready
- 2];
23057 ready
[n_ready
- 2] = tmp
;
23061 if (rs6000_cpu
== PROCESSOR_POWER6
)
23062 load_store_pendulum
= 0;
23064 return rs6000_issue_rate ();
23067 /* Like rs6000_sched_reorder, but called after issuing each insn. */
23070 rs6000_sched_reorder2 (FILE *dump
, int sched_verbose
, rtx
*ready
,
23071 int *pn_ready
, int clock_var ATTRIBUTE_UNUSED
)
23074 fprintf (dump
, "// rs6000_sched_reorder2 :\n");
23076 /* For Power6, we need to handle some special cases to try and keep the
23077 store queue from overflowing and triggering expensive flushes.
23079 This code monitors how load and store instructions are being issued
23080 and skews the ready list one way or the other to increase the likelihood
23081 that a desired instruction is issued at the proper time.
23083 A couple of things are done. First, we maintain a "load_store_pendulum"
23084 to track the current state of load/store issue.
23086 - If the pendulum is at zero, then no loads or stores have been
23087 issued in the current cycle so we do nothing.
23089 - If the pendulum is 1, then a single load has been issued in this
23090 cycle and we attempt to locate another load in the ready list to
23093 - If the pendulum is -2, then two stores have already been
23094 issued in this cycle, so we increase the priority of the first load
23095 in the ready list to increase it's likelihood of being chosen first
23098 - If the pendulum is -1, then a single store has been issued in this
23099 cycle and we attempt to locate another store in the ready list to
23100 issue with it, preferring a store to an adjacent memory location to
23101 facilitate store pairing in the store queue.
23103 - If the pendulum is 2, then two loads have already been
23104 issued in this cycle, so we increase the priority of the first store
23105 in the ready list to increase it's likelihood of being chosen first
23108 - If the pendulum < -2 or > 2, then do nothing.
23110 Note: This code covers the most common scenarios. There exist non
23111 load/store instructions which make use of the LSU and which
23112 would need to be accounted for to strictly model the behavior
23113 of the machine. Those instructions are currently unaccounted
23114 for to help minimize compile time overhead of this code.
23116 if (rs6000_cpu
== PROCESSOR_POWER6
&& last_scheduled_insn
)
23122 if (is_store_insn (last_scheduled_insn
))
23123 /* Issuing a store, swing the load_store_pendulum to the left */
23124 load_store_pendulum
--;
23125 else if (is_load_insn (last_scheduled_insn
))
23126 /* Issuing a load, swing the load_store_pendulum to the right */
23127 load_store_pendulum
++;
23129 return cached_can_issue_more
;
23131 /* If the pendulum is balanced, or there is only one instruction on
23132 the ready list, then all is well, so return. */
23133 if ((load_store_pendulum
== 0) || (*pn_ready
<= 1))
23134 return cached_can_issue_more
;
23136 if (load_store_pendulum
== 1)
23138 /* A load has been issued in this cycle. Scan the ready list
23139 for another load to issue with it */
23144 if (is_load_insn (ready
[pos
]))
23146 /* Found a load. Move it to the head of the ready list,
23147 and adjust it's priority so that it is more likely to
23150 for (i
=pos
; i
<*pn_ready
-1; i
++)
23151 ready
[i
] = ready
[i
+ 1];
23152 ready
[*pn_ready
-1] = tmp
;
23154 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
23155 INSN_PRIORITY (tmp
)++;
23161 else if (load_store_pendulum
== -2)
23163 /* Two stores have been issued in this cycle. Increase the
23164 priority of the first load in the ready list to favor it for
23165 issuing in the next cycle. */
23170 if (is_load_insn (ready
[pos
])
23172 && INSN_PRIORITY_KNOWN (ready
[pos
]))
23174 INSN_PRIORITY (ready
[pos
])++;
23176 /* Adjust the pendulum to account for the fact that a load
23177 was found and increased in priority. This is to prevent
23178 increasing the priority of multiple loads */
23179 load_store_pendulum
--;
23186 else if (load_store_pendulum
== -1)
23188 /* A store has been issued in this cycle. Scan the ready list for
23189 another store to issue with it, preferring a store to an adjacent
23191 int first_store_pos
= -1;
23197 if (is_store_insn (ready
[pos
]))
23199 /* Maintain the index of the first store found on the
23201 if (first_store_pos
== -1)
23202 first_store_pos
= pos
;
23204 if (is_store_insn (last_scheduled_insn
)
23205 && adjacent_mem_locations (last_scheduled_insn
,ready
[pos
]))
23207 /* Found an adjacent store. Move it to the head of the
23208 ready list, and adjust it's priority so that it is
23209 more likely to stay there */
23211 for (i
=pos
; i
<*pn_ready
-1; i
++)
23212 ready
[i
] = ready
[i
+ 1];
23213 ready
[*pn_ready
-1] = tmp
;
23215 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
23216 INSN_PRIORITY (tmp
)++;
23218 first_store_pos
= -1;
23226 if (first_store_pos
>= 0)
23228 /* An adjacent store wasn't found, but a non-adjacent store was,
23229 so move the non-adjacent store to the front of the ready
23230 list, and adjust its priority so that it is more likely to
23232 tmp
= ready
[first_store_pos
];
23233 for (i
=first_store_pos
; i
<*pn_ready
-1; i
++)
23234 ready
[i
] = ready
[i
+ 1];
23235 ready
[*pn_ready
-1] = tmp
;
23236 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
23237 INSN_PRIORITY (tmp
)++;
23240 else if (load_store_pendulum
== 2)
23242 /* Two loads have been issued in this cycle. Increase the priority
23243 of the first store in the ready list to favor it for issuing in
23249 if (is_store_insn (ready
[pos
])
23251 && INSN_PRIORITY_KNOWN (ready
[pos
]))
23253 INSN_PRIORITY (ready
[pos
])++;
23255 /* Adjust the pendulum to account for the fact that a store
23256 was found and increased in priority. This is to prevent
23257 increasing the priority of multiple stores */
23258 load_store_pendulum
++;
23267 return cached_can_issue_more
;
23270 /* Return whether the presence of INSN causes a dispatch group termination
23271 of group WHICH_GROUP.
23273 If WHICH_GROUP == current_group, this function will return true if INSN
23274 causes the termination of the current group (i.e, the dispatch group to
23275 which INSN belongs). This means that INSN will be the last insn in the
23276 group it belongs to.
23278 If WHICH_GROUP == previous_group, this function will return true if INSN
23279 causes the termination of the previous group (i.e, the dispatch group that
23280 precedes the group to which INSN belongs). This means that INSN will be
23281 the first insn in the group it belongs to). */
23284 insn_terminates_group_p (rtx insn
, enum group_termination which_group
)
23291 first
= insn_must_be_first_in_group (insn
);
23292 last
= insn_must_be_last_in_group (insn
);
23297 if (which_group
== current_group
)
23299 else if (which_group
== previous_group
)
23307 insn_must_be_first_in_group (rtx insn
)
23309 enum attr_type type
;
23312 || GET_CODE (insn
) == NOTE
23313 || DEBUG_INSN_P (insn
)
23314 || GET_CODE (PATTERN (insn
)) == USE
23315 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
23318 switch (rs6000_cpu
)
23320 case PROCESSOR_POWER5
:
23321 if (is_cracked_insn (insn
))
23323 case PROCESSOR_POWER4
:
23324 if (is_microcoded_insn (insn
))
23327 if (!rs6000_sched_groups
)
23330 type
= get_attr_type (insn
);
23337 case TYPE_DELAYED_CR
:
23338 case TYPE_CR_LOGICAL
:
23352 case PROCESSOR_POWER6
:
23353 type
= get_attr_type (insn
);
23357 case TYPE_INSERT_DWORD
:
23361 case TYPE_VAR_SHIFT_ROTATE
:
23368 case TYPE_INSERT_WORD
:
23369 case TYPE_DELAYED_COMPARE
:
23370 case TYPE_IMUL_COMPARE
:
23371 case TYPE_LMUL_COMPARE
:
23372 case TYPE_FPCOMPARE
:
23383 case TYPE_LOAD_EXT_UX
:
23385 case TYPE_STORE_UX
:
23386 case TYPE_FPLOAD_U
:
23387 case TYPE_FPLOAD_UX
:
23388 case TYPE_FPSTORE_U
:
23389 case TYPE_FPSTORE_UX
:
23395 case PROCESSOR_POWER7
:
23396 type
= get_attr_type (insn
);
23400 case TYPE_CR_LOGICAL
:
23407 case TYPE_DELAYED_COMPARE
:
23408 case TYPE_VAR_DELAYED_COMPARE
:
23414 case TYPE_LOAD_EXT
:
23415 case TYPE_LOAD_EXT_U
:
23416 case TYPE_LOAD_EXT_UX
:
23418 case TYPE_STORE_UX
:
23419 case TYPE_FPLOAD_U
:
23420 case TYPE_FPLOAD_UX
:
23421 case TYPE_FPSTORE_U
:
23422 case TYPE_FPSTORE_UX
:
23438 insn_must_be_last_in_group (rtx insn
)
23440 enum attr_type type
;
23443 || GET_CODE (insn
) == NOTE
23444 || DEBUG_INSN_P (insn
)
23445 || GET_CODE (PATTERN (insn
)) == USE
23446 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
23449 switch (rs6000_cpu
) {
23450 case PROCESSOR_POWER4
:
23451 case PROCESSOR_POWER5
:
23452 if (is_microcoded_insn (insn
))
23455 if (is_branch_slot_insn (insn
))
23459 case PROCESSOR_POWER6
:
23460 type
= get_attr_type (insn
);
23467 case TYPE_VAR_SHIFT_ROTATE
:
23474 case TYPE_DELAYED_COMPARE
:
23475 case TYPE_IMUL_COMPARE
:
23476 case TYPE_LMUL_COMPARE
:
23477 case TYPE_FPCOMPARE
:
23491 case PROCESSOR_POWER7
:
23492 type
= get_attr_type (insn
);
23500 case TYPE_LOAD_EXT_U
:
23501 case TYPE_LOAD_EXT_UX
:
23502 case TYPE_STORE_UX
:
23515 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
23516 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
23519 is_costly_group (rtx
*group_insns
, rtx next_insn
)
23522 int issue_rate
= rs6000_issue_rate ();
23524 for (i
= 0; i
< issue_rate
; i
++)
23526 sd_iterator_def sd_it
;
23528 rtx insn
= group_insns
[i
];
23533 FOR_EACH_DEP (insn
, SD_LIST_FORW
, sd_it
, dep
)
23535 rtx next
= DEP_CON (dep
);
23537 if (next
== next_insn
23538 && rs6000_is_costly_dependence (dep
, dep_cost (dep
), 0))
23546 /* Utility of the function redefine_groups.
23547 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
23548 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
23549 to keep it "far" (in a separate group) from GROUP_INSNS, following
23550 one of the following schemes, depending on the value of the flag
23551 -minsert_sched_nops = X:
23552 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
23553 in order to force NEXT_INSN into a separate group.
23554 (2) X < sched_finish_regroup_exact: insert exactly X nops.
23555 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
23556 insertion (has a group just ended, how many vacant issue slots remain in the
23557 last group, and how many dispatch groups were encountered so far). */
23560 force_new_group (int sched_verbose
, FILE *dump
, rtx
*group_insns
,
23561 rtx next_insn
, bool *group_end
, int can_issue_more
,
23566 int issue_rate
= rs6000_issue_rate ();
23567 bool end
= *group_end
;
23570 if (next_insn
== NULL_RTX
|| DEBUG_INSN_P (next_insn
))
23571 return can_issue_more
;
23573 if (rs6000_sched_insert_nops
> sched_finish_regroup_exact
)
23574 return can_issue_more
;
23576 force
= is_costly_group (group_insns
, next_insn
);
23578 return can_issue_more
;
23580 if (sched_verbose
> 6)
23581 fprintf (dump
,"force: group count = %d, can_issue_more = %d\n",
23582 *group_count
,can_issue_more
);
23584 if (rs6000_sched_insert_nops
== sched_finish_regroup_exact
)
23587 can_issue_more
= 0;
23589 /* Since only a branch can be issued in the last issue_slot, it is
23590 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
23591 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
23592 in this case the last nop will start a new group and the branch
23593 will be forced to the new group. */
23594 if (can_issue_more
&& !is_branch_slot_insn (next_insn
))
23597 while (can_issue_more
> 0)
23600 emit_insn_before (nop
, next_insn
);
23608 if (rs6000_sched_insert_nops
< sched_finish_regroup_exact
)
23610 int n_nops
= rs6000_sched_insert_nops
;
23612 /* Nops can't be issued from the branch slot, so the effective
23613 issue_rate for nops is 'issue_rate - 1'. */
23614 if (can_issue_more
== 0)
23615 can_issue_more
= issue_rate
;
23617 if (can_issue_more
== 0)
23619 can_issue_more
= issue_rate
- 1;
23622 for (i
= 0; i
< issue_rate
; i
++)
23624 group_insns
[i
] = 0;
23631 emit_insn_before (nop
, next_insn
);
23632 if (can_issue_more
== issue_rate
- 1) /* new group begins */
23635 if (can_issue_more
== 0)
23637 can_issue_more
= issue_rate
- 1;
23640 for (i
= 0; i
< issue_rate
; i
++)
23642 group_insns
[i
] = 0;
23648 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
23651 /* Is next_insn going to start a new group? */
23654 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
23655 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
23656 || (can_issue_more
< issue_rate
&&
23657 insn_terminates_group_p (next_insn
, previous_group
)));
23658 if (*group_end
&& end
)
23661 if (sched_verbose
> 6)
23662 fprintf (dump
, "done force: group count = %d, can_issue_more = %d\n",
23663 *group_count
, can_issue_more
);
23664 return can_issue_more
;
23667 return can_issue_more
;
23670 /* This function tries to synch the dispatch groups that the compiler "sees"
23671 with the dispatch groups that the processor dispatcher is expected to
23672 form in practice. It tries to achieve this synchronization by forcing the
23673 estimated processor grouping on the compiler (as opposed to the function
23674 'pad_goups' which tries to force the scheduler's grouping on the processor).
23676 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
23677 examines the (estimated) dispatch groups that will be formed by the processor
23678 dispatcher. It marks these group boundaries to reflect the estimated
23679 processor grouping, overriding the grouping that the scheduler had marked.
23680 Depending on the value of the flag '-minsert-sched-nops' this function can
23681 force certain insns into separate groups or force a certain distance between
23682 them by inserting nops, for example, if there exists a "costly dependence"
23685 The function estimates the group boundaries that the processor will form as
23686 follows: It keeps track of how many vacant issue slots are available after
23687 each insn. A subsequent insn will start a new group if one of the following
23689 - no more vacant issue slots remain in the current dispatch group.
23690 - only the last issue slot, which is the branch slot, is vacant, but the next
23691 insn is not a branch.
23692 - only the last 2 or less issue slots, including the branch slot, are vacant,
23693 which means that a cracked insn (which occupies two issue slots) can't be
23694 issued in this group.
23695 - less than 'issue_rate' slots are vacant, and the next insn always needs to
23696 start a new group. */
23699 redefine_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
23701 rtx insn
, next_insn
;
23703 int can_issue_more
;
23706 int group_count
= 0;
23710 issue_rate
= rs6000_issue_rate ();
23711 group_insns
= XALLOCAVEC (rtx
, issue_rate
);
23712 for (i
= 0; i
< issue_rate
; i
++)
23714 group_insns
[i
] = 0;
23716 can_issue_more
= issue_rate
;
23718 insn
= get_next_active_insn (prev_head_insn
, tail
);
23721 while (insn
!= NULL_RTX
)
23723 slot
= (issue_rate
- can_issue_more
);
23724 group_insns
[slot
] = insn
;
23726 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
23727 if (insn_terminates_group_p (insn
, current_group
))
23728 can_issue_more
= 0;
23730 next_insn
= get_next_active_insn (insn
, tail
);
23731 if (next_insn
== NULL_RTX
)
23732 return group_count
+ 1;
23734 /* Is next_insn going to start a new group? */
23736 = (can_issue_more
== 0
23737 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
23738 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
23739 || (can_issue_more
< issue_rate
&&
23740 insn_terminates_group_p (next_insn
, previous_group
)));
23742 can_issue_more
= force_new_group (sched_verbose
, dump
, group_insns
,
23743 next_insn
, &group_end
, can_issue_more
,
23749 can_issue_more
= 0;
23750 for (i
= 0; i
< issue_rate
; i
++)
23752 group_insns
[i
] = 0;
23756 if (GET_MODE (next_insn
) == TImode
&& can_issue_more
)
23757 PUT_MODE (next_insn
, VOIDmode
);
23758 else if (!can_issue_more
&& GET_MODE (next_insn
) != TImode
)
23759 PUT_MODE (next_insn
, TImode
);
23762 if (can_issue_more
== 0)
23763 can_issue_more
= issue_rate
;
23766 return group_count
;
23769 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
23770 dispatch group boundaries that the scheduler had marked. Pad with nops
23771 any dispatch groups which have vacant issue slots, in order to force the
23772 scheduler's grouping on the processor dispatcher. The function
23773 returns the number of dispatch groups found. */
23776 pad_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
23778 rtx insn
, next_insn
;
23781 int can_issue_more
;
23783 int group_count
= 0;
23785 /* Initialize issue_rate. */
23786 issue_rate
= rs6000_issue_rate ();
23787 can_issue_more
= issue_rate
;
23789 insn
= get_next_active_insn (prev_head_insn
, tail
);
23790 next_insn
= get_next_active_insn (insn
, tail
);
23792 while (insn
!= NULL_RTX
)
23795 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
23797 group_end
= (next_insn
== NULL_RTX
|| GET_MODE (next_insn
) == TImode
);
23799 if (next_insn
== NULL_RTX
)
23804 /* If the scheduler had marked group termination at this location
23805 (between insn and next_insn), and neither insn nor next_insn will
23806 force group termination, pad the group with nops to force group
23809 && (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
23810 && !insn_terminates_group_p (insn
, current_group
)
23811 && !insn_terminates_group_p (next_insn
, previous_group
))
23813 if (!is_branch_slot_insn (next_insn
))
23816 while (can_issue_more
)
23819 emit_insn_before (nop
, next_insn
);
23824 can_issue_more
= issue_rate
;
23829 next_insn
= get_next_active_insn (insn
, tail
);
23832 return group_count
;
23835 /* We're beginning a new block. Initialize data structures as necessary. */
23838 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
23839 int sched_verbose ATTRIBUTE_UNUSED
,
23840 int max_ready ATTRIBUTE_UNUSED
)
23842 last_scheduled_insn
= NULL_RTX
;
23843 load_store_pendulum
= 0;
23846 /* The following function is called at the end of scheduling BB.
23847 After reload, it inserts nops at insn group bundling. */
23850 rs6000_sched_finish (FILE *dump
, int sched_verbose
)
23855 fprintf (dump
, "=== Finishing schedule.\n");
23857 if (reload_completed
&& rs6000_sched_groups
)
23859 /* Do not run sched_finish hook when selective scheduling enabled. */
23860 if (sel_sched_p ())
23863 if (rs6000_sched_insert_nops
== sched_finish_none
)
23866 if (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
23867 n_groups
= pad_groups (dump
, sched_verbose
,
23868 current_sched_info
->prev_head
,
23869 current_sched_info
->next_tail
);
23871 n_groups
= redefine_groups (dump
, sched_verbose
,
23872 current_sched_info
->prev_head
,
23873 current_sched_info
->next_tail
);
23875 if (sched_verbose
>= 6)
23877 fprintf (dump
, "ngroups = %d\n", n_groups
);
23878 print_rtl (dump
, current_sched_info
->prev_head
);
23879 fprintf (dump
, "Done finish_sched\n");
23884 struct _rs6000_sched_context
23886 short cached_can_issue_more
;
23887 rtx last_scheduled_insn
;
23888 int load_store_pendulum
;
23891 typedef struct _rs6000_sched_context rs6000_sched_context_def
;
23892 typedef rs6000_sched_context_def
*rs6000_sched_context_t
;
23894 /* Allocate store for new scheduling context. */
23896 rs6000_alloc_sched_context (void)
23898 return xmalloc (sizeof (rs6000_sched_context_def
));
23901 /* If CLEAN_P is true then initializes _SC with clean data,
23902 and from the global context otherwise. */
23904 rs6000_init_sched_context (void *_sc
, bool clean_p
)
23906 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
23910 sc
->cached_can_issue_more
= 0;
23911 sc
->last_scheduled_insn
= NULL_RTX
;
23912 sc
->load_store_pendulum
= 0;
23916 sc
->cached_can_issue_more
= cached_can_issue_more
;
23917 sc
->last_scheduled_insn
= last_scheduled_insn
;
23918 sc
->load_store_pendulum
= load_store_pendulum
;
23922 /* Sets the global scheduling context to the one pointed to by _SC. */
23924 rs6000_set_sched_context (void *_sc
)
23926 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
23928 gcc_assert (sc
!= NULL
);
23930 cached_can_issue_more
= sc
->cached_can_issue_more
;
23931 last_scheduled_insn
= sc
->last_scheduled_insn
;
23932 load_store_pendulum
= sc
->load_store_pendulum
;
23937 rs6000_free_sched_context (void *_sc
)
23939 gcc_assert (_sc
!= NULL
);
23945 /* Length in units of the trampoline for entering a nested function. */
23948 rs6000_trampoline_size (void)
23952 switch (DEFAULT_ABI
)
23955 gcc_unreachable ();
23958 ret
= (TARGET_32BIT
) ? 12 : 24;
23963 ret
= (TARGET_32BIT
) ? 40 : 48;
23970 /* Emit RTL insns to initialize the variable parts of a trampoline.
23971 FNADDR is an RTX for the address of the function's pure code.
23972 CXT is an RTX for the static chain value for the function. */
23975 rs6000_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
23977 int regsize
= (TARGET_32BIT
) ? 4 : 8;
23978 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
23979 rtx ctx_reg
= force_reg (Pmode
, cxt
);
23980 rtx addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
23982 switch (DEFAULT_ABI
)
23985 gcc_unreachable ();
23987 /* Under AIX, just build the 3 word function descriptor */
23990 rtx fnmem
, fn_reg
, toc_reg
;
23992 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
23993 error ("You cannot take the address of a nested function if you use "
23994 "the -mno-pointers-to-nested-functions option.");
23996 fnmem
= gen_const_mem (Pmode
, force_reg (Pmode
, fnaddr
));
23997 fn_reg
= gen_reg_rtx (Pmode
);
23998 toc_reg
= gen_reg_rtx (Pmode
);
24000 /* Macro to shorten the code expansions below. */
24001 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
24003 m_tramp
= replace_equiv_address (m_tramp
, addr
);
24005 emit_move_insn (fn_reg
, MEM_PLUS (fnmem
, 0));
24006 emit_move_insn (toc_reg
, MEM_PLUS (fnmem
, regsize
));
24007 emit_move_insn (MEM_PLUS (m_tramp
, 0), fn_reg
);
24008 emit_move_insn (MEM_PLUS (m_tramp
, regsize
), toc_reg
);
24009 emit_move_insn (MEM_PLUS (m_tramp
, 2*regsize
), ctx_reg
);
24015 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
24018 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__trampoline_setup"),
24019 LCT_NORMAL
, VOIDmode
, 4,
24021 GEN_INT (rs6000_trampoline_size ()), SImode
,
24029 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
24030 identifier as an argument, so the front end shouldn't look it up. */
24033 rs6000_attribute_takes_identifier_p (const_tree attr_id
)
24035 return is_attribute_p ("altivec", attr_id
);
24038 /* Handle the "altivec" attribute. The attribute may have
24039 arguments as follows:
24041 __attribute__((altivec(vector__)))
24042 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
24043 __attribute__((altivec(bool__))) (always followed by 'unsigned')
24045 and may appear more than once (e.g., 'vector bool char') in a
24046 given declaration. */
24049 rs6000_handle_altivec_attribute (tree
*node
,
24050 tree name ATTRIBUTE_UNUSED
,
24052 int flags ATTRIBUTE_UNUSED
,
24053 bool *no_add_attrs
)
24055 tree type
= *node
, result
= NULL_TREE
;
24056 enum machine_mode mode
;
24059 = ((args
&& TREE_CODE (args
) == TREE_LIST
&& TREE_VALUE (args
)
24060 && TREE_CODE (TREE_VALUE (args
)) == IDENTIFIER_NODE
)
24061 ? *IDENTIFIER_POINTER (TREE_VALUE (args
))
24064 while (POINTER_TYPE_P (type
)
24065 || TREE_CODE (type
) == FUNCTION_TYPE
24066 || TREE_CODE (type
) == METHOD_TYPE
24067 || TREE_CODE (type
) == ARRAY_TYPE
)
24068 type
= TREE_TYPE (type
);
24070 mode
= TYPE_MODE (type
);
24072 /* Check for invalid AltiVec type qualifiers. */
24073 if (type
== long_double_type_node
)
24074 error ("use of %<long double%> in AltiVec types is invalid");
24075 else if (type
== boolean_type_node
)
24076 error ("use of boolean types in AltiVec types is invalid");
24077 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
24078 error ("use of %<complex%> in AltiVec types is invalid");
24079 else if (DECIMAL_FLOAT_MODE_P (mode
))
24080 error ("use of decimal floating point types in AltiVec types is invalid");
24081 else if (!TARGET_VSX
)
24083 if (type
== long_unsigned_type_node
|| type
== long_integer_type_node
)
24086 error ("use of %<long%> in AltiVec types is invalid for "
24087 "64-bit code without -mvsx");
24088 else if (rs6000_warn_altivec_long
)
24089 warning (0, "use of %<long%> in AltiVec types is deprecated; "
24092 else if (type
== long_long_unsigned_type_node
24093 || type
== long_long_integer_type_node
)
24094 error ("use of %<long long%> in AltiVec types is invalid without "
24096 else if (type
== double_type_node
)
24097 error ("use of %<double%> in AltiVec types is invalid without -mvsx");
24100 switch (altivec_type
)
24103 unsigned_p
= TYPE_UNSIGNED (type
);
24107 result
= (unsigned_p
? unsigned_V2DI_type_node
: V2DI_type_node
);
24110 result
= (unsigned_p
? unsigned_V4SI_type_node
: V4SI_type_node
);
24113 result
= (unsigned_p
? unsigned_V8HI_type_node
: V8HI_type_node
);
24116 result
= (unsigned_p
? unsigned_V16QI_type_node
: V16QI_type_node
);
24118 case SFmode
: result
= V4SF_type_node
; break;
24119 case DFmode
: result
= V2DF_type_node
; break;
24120 /* If the user says 'vector int bool', we may be handed the 'bool'
24121 attribute _before_ the 'vector' attribute, and so select the
24122 proper type in the 'b' case below. */
24123 case V4SImode
: case V8HImode
: case V16QImode
: case V4SFmode
:
24124 case V2DImode
: case V2DFmode
:
24132 case DImode
: case V2DImode
: result
= bool_V2DI_type_node
; break;
24133 case SImode
: case V4SImode
: result
= bool_V4SI_type_node
; break;
24134 case HImode
: case V8HImode
: result
= bool_V8HI_type_node
; break;
24135 case QImode
: case V16QImode
: result
= bool_V16QI_type_node
;
24142 case V8HImode
: result
= pixel_V8HI_type_node
;
24148 /* Propagate qualifiers attached to the element type
24149 onto the vector type. */
24150 if (result
&& result
!= type
&& TYPE_QUALS (type
))
24151 result
= build_qualified_type (result
, TYPE_QUALS (type
));
24153 *no_add_attrs
= true; /* No need to hang on to the attribute. */
24156 *node
= lang_hooks
.types
.reconstruct_complex_type (*node
, result
);
24161 /* AltiVec defines four built-in scalar types that serve as vector
24162 elements; we must teach the compiler how to mangle them. */
24164 static const char *
24165 rs6000_mangle_type (const_tree type
)
24167 type
= TYPE_MAIN_VARIANT (type
);
24169 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
24170 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
24173 if (type
== bool_char_type_node
) return "U6__boolc";
24174 if (type
== bool_short_type_node
) return "U6__bools";
24175 if (type
== pixel_type_node
) return "u7__pixel";
24176 if (type
== bool_int_type_node
) return "U6__booli";
24177 if (type
== bool_long_type_node
) return "U6__booll";
24179 /* Mangle IBM extended float long double as `g' (__float128) on
24180 powerpc*-linux where long-double-64 previously was the default. */
24181 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
24183 && TARGET_LONG_DOUBLE_128
24184 && !TARGET_IEEEQUAD
)
24187 /* For all other types, use normal C++ mangling. */
24191 /* Handle a "longcall" or "shortcall" attribute; arguments as in
24192 struct attribute_spec.handler. */
24195 rs6000_handle_longcall_attribute (tree
*node
, tree name
,
24196 tree args ATTRIBUTE_UNUSED
,
24197 int flags ATTRIBUTE_UNUSED
,
24198 bool *no_add_attrs
)
24200 if (TREE_CODE (*node
) != FUNCTION_TYPE
24201 && TREE_CODE (*node
) != FIELD_DECL
24202 && TREE_CODE (*node
) != TYPE_DECL
)
24204 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
24206 *no_add_attrs
= true;
24212 /* Set longcall attributes on all functions declared when
24213 rs6000_default_long_calls is true. */
24215 rs6000_set_default_type_attributes (tree type
)
24217 if (rs6000_default_long_calls
24218 && (TREE_CODE (type
) == FUNCTION_TYPE
24219 || TREE_CODE (type
) == METHOD_TYPE
))
24220 TYPE_ATTRIBUTES (type
) = tree_cons (get_identifier ("longcall"),
24222 TYPE_ATTRIBUTES (type
));
24225 darwin_set_default_type_attributes (type
);
24229 /* Return a reference suitable for calling a function with the
24230 longcall attribute. */
24233 rs6000_longcall_ref (rtx call_ref
)
24235 const char *call_name
;
24238 if (GET_CODE (call_ref
) != SYMBOL_REF
)
24241 /* System V adds '.' to the internal name, so skip them. */
24242 call_name
= XSTR (call_ref
, 0);
24243 if (*call_name
== '.')
24245 while (*call_name
== '.')
24248 node
= get_identifier (call_name
);
24249 call_ref
= gen_rtx_SYMBOL_REF (VOIDmode
, IDENTIFIER_POINTER (node
));
24252 return force_reg (Pmode
, call_ref
);
24255 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
24256 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
24259 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
24260 struct attribute_spec.handler. */
24262 rs6000_handle_struct_attribute (tree
*node
, tree name
,
24263 tree args ATTRIBUTE_UNUSED
,
24264 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
24267 if (DECL_P (*node
))
24269 if (TREE_CODE (*node
) == TYPE_DECL
)
24270 type
= &TREE_TYPE (*node
);
24275 if (!(type
&& (TREE_CODE (*type
) == RECORD_TYPE
24276 || TREE_CODE (*type
) == UNION_TYPE
)))
24278 warning (OPT_Wattributes
, "%qE attribute ignored", name
);
24279 *no_add_attrs
= true;
24282 else if ((is_attribute_p ("ms_struct", name
)
24283 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type
)))
24284 || ((is_attribute_p ("gcc_struct", name
)
24285 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type
)))))
24287 warning (OPT_Wattributes
, "%qE incompatible attribute ignored",
24289 *no_add_attrs
= true;
24296 rs6000_ms_bitfield_layout_p (const_tree record_type
)
24298 return (TARGET_USE_MS_BITFIELD_LAYOUT
&&
24299 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type
)))
24300 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type
));
24303 #ifdef USING_ELFOS_H
24305 /* A get_unnamed_section callback, used for switching to toc_section. */
24308 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
24310 if (DEFAULT_ABI
== ABI_AIX
24311 && TARGET_MINIMAL_TOC
24312 && !TARGET_RELOCATABLE
)
24314 if (!toc_initialized
)
24316 toc_initialized
= 1;
24317 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
24318 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LCTOC", 0);
24319 fprintf (asm_out_file
, "\t.tc ");
24320 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1[TC],");
24321 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
24322 fprintf (asm_out_file
, "\n");
24324 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
24325 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
24326 fprintf (asm_out_file
, " = .+32768\n");
24329 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
24331 else if (DEFAULT_ABI
== ABI_AIX
&& !TARGET_RELOCATABLE
)
24332 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
24335 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
24336 if (!toc_initialized
)
24338 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
24339 fprintf (asm_out_file
, " = .+32768\n");
24340 toc_initialized
= 1;
24345 /* Implement TARGET_ASM_INIT_SECTIONS. */
24348 rs6000_elf_asm_init_sections (void)
24351 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op
, NULL
);
24354 = get_unnamed_section (SECTION_WRITE
, output_section_asm_op
,
24355 SDATA2_SECTION_ASM_OP
);
24358 /* Implement TARGET_SELECT_RTX_SECTION. */
24361 rs6000_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
24362 unsigned HOST_WIDE_INT align
)
24364 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
24365 return toc_section
;
24367 return default_elf_select_rtx_section (mode
, x
, align
);
24370 /* For a SYMBOL_REF, set generic flags and then perform some
24371 target-specific processing.
24373 When the AIX ABI is requested on a non-AIX system, replace the
24374 function name with the real name (with a leading .) rather than the
24375 function descriptor name. This saves a lot of overriding code to
24376 read the prefixes. */
24379 rs6000_elf_encode_section_info (tree decl
, rtx rtl
, int first
)
24381 default_encode_section_info (decl
, rtl
, first
);
24384 && TREE_CODE (decl
) == FUNCTION_DECL
24386 && DEFAULT_ABI
== ABI_AIX
)
24388 rtx sym_ref
= XEXP (rtl
, 0);
24389 size_t len
= strlen (XSTR (sym_ref
, 0));
24390 char *str
= XALLOCAVEC (char, len
+ 2);
24392 memcpy (str
+ 1, XSTR (sym_ref
, 0), len
+ 1);
24393 XSTR (sym_ref
, 0) = ggc_alloc_string (str
, len
+ 1);
24398 compare_section_name (const char *section
, const char *templ
)
24402 len
= strlen (templ
);
24403 return (strncmp (section
, templ
, len
) == 0
24404 && (section
[len
] == 0 || section
[len
] == '.'));
24408 rs6000_elf_in_small_data_p (const_tree decl
)
24410 if (rs6000_sdata
== SDATA_NONE
)
24413 /* We want to merge strings, so we never consider them small data. */
24414 if (TREE_CODE (decl
) == STRING_CST
)
24417 /* Functions are never in the small data area. */
24418 if (TREE_CODE (decl
) == FUNCTION_DECL
)
24421 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
))
24423 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
24424 if (compare_section_name (section
, ".sdata")
24425 || compare_section_name (section
, ".sdata2")
24426 || compare_section_name (section
, ".gnu.linkonce.s")
24427 || compare_section_name (section
, ".sbss")
24428 || compare_section_name (section
, ".sbss2")
24429 || compare_section_name (section
, ".gnu.linkonce.sb")
24430 || strcmp (section
, ".PPC.EMB.sdata0") == 0
24431 || strcmp (section
, ".PPC.EMB.sbss0") == 0)
24436 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
24439 && size
<= g_switch_value
24440 /* If it's not public, and we're not going to reference it there,
24441 there's no need to put it in the small data section. */
24442 && (rs6000_sdata
!= SDATA_DATA
|| TREE_PUBLIC (decl
)))
24449 #endif /* USING_ELFOS_H */
24451 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
24454 rs6000_use_blocks_for_constant_p (enum machine_mode mode
, const_rtx x
)
24456 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
);
24459 /* Return a REG that occurs in ADDR with coefficient 1.
24460 ADDR can be effectively incremented by incrementing REG.
24462 r0 is special and we must not select it as an address
24463 register by this routine since our caller will try to
24464 increment the returned register via an "la" instruction. */
24467 find_addr_reg (rtx addr
)
24469 while (GET_CODE (addr
) == PLUS
)
24471 if (GET_CODE (XEXP (addr
, 0)) == REG
24472 && REGNO (XEXP (addr
, 0)) != 0)
24473 addr
= XEXP (addr
, 0);
24474 else if (GET_CODE (XEXP (addr
, 1)) == REG
24475 && REGNO (XEXP (addr
, 1)) != 0)
24476 addr
= XEXP (addr
, 1);
24477 else if (CONSTANT_P (XEXP (addr
, 0)))
24478 addr
= XEXP (addr
, 1);
24479 else if (CONSTANT_P (XEXP (addr
, 1)))
24480 addr
= XEXP (addr
, 0);
24482 gcc_unreachable ();
24484 gcc_assert (GET_CODE (addr
) == REG
&& REGNO (addr
) != 0);
24489 rs6000_fatal_bad_address (rtx op
)
24491 fatal_insn ("bad address", op
);
24496 typedef struct branch_island_d
{
24497 tree function_name
;
24502 DEF_VEC_O(branch_island
);
24503 DEF_VEC_ALLOC_O(branch_island
,gc
);
24505 static VEC(branch_island
,gc
) *branch_islands
;
24507 /* Remember to generate a branch island for far calls to the given
24511 add_compiler_branch_island (tree label_name
, tree function_name
,
24514 branch_island
*bi
= VEC_safe_push (branch_island
, gc
, branch_islands
, NULL
);
24516 bi
->function_name
= function_name
;
24517 bi
->label_name
= label_name
;
24518 bi
->line_number
= line_number
;
24521 /* Generate far-jump branch islands for everything recorded in
24522 branch_islands. Invoked immediately after the last instruction of
24523 the epilogue has been emitted; the branch islands must be appended
24524 to, and contiguous with, the function body. Mach-O stubs are
24525 generated in machopic_output_stub(). */
24528 macho_branch_islands (void)
24532 while (!VEC_empty (branch_island
, branch_islands
))
24534 branch_island
*bi
= VEC_last (branch_island
, branch_islands
);
24535 const char *label
= IDENTIFIER_POINTER (bi
->label_name
);
24536 const char *name
= IDENTIFIER_POINTER (bi
->function_name
);
24537 char name_buf
[512];
24538 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
24539 if (name
[0] == '*' || name
[0] == '&')
24540 strcpy (name_buf
, name
+1);
24544 strcpy (name_buf
+1, name
);
24546 strcpy (tmp_buf
, "\n");
24547 strcat (tmp_buf
, label
);
24548 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
24549 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
24550 dbxout_stabd (N_SLINE
, bi
->line_number
);
24551 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
24554 if (TARGET_LINK_STACK
)
24557 get_ppc476_thunk_name (name
);
24558 strcat (tmp_buf
, ":\n\tmflr r0\n\tbl ");
24559 strcat (tmp_buf
, name
);
24560 strcat (tmp_buf
, "\n");
24561 strcat (tmp_buf
, label
);
24562 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
24566 strcat (tmp_buf
, ":\n\tmflr r0\n\tbcl 20,31,");
24567 strcat (tmp_buf
, label
);
24568 strcat (tmp_buf
, "_pic\n");
24569 strcat (tmp_buf
, label
);
24570 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
24573 strcat (tmp_buf
, "\taddis r11,r11,ha16(");
24574 strcat (tmp_buf
, name_buf
);
24575 strcat (tmp_buf
, " - ");
24576 strcat (tmp_buf
, label
);
24577 strcat (tmp_buf
, "_pic)\n");
24579 strcat (tmp_buf
, "\tmtlr r0\n");
24581 strcat (tmp_buf
, "\taddi r12,r11,lo16(");
24582 strcat (tmp_buf
, name_buf
);
24583 strcat (tmp_buf
, " - ");
24584 strcat (tmp_buf
, label
);
24585 strcat (tmp_buf
, "_pic)\n");
24587 strcat (tmp_buf
, "\tmtctr r12\n\tbctr\n");
24591 strcat (tmp_buf
, ":\nlis r12,hi16(");
24592 strcat (tmp_buf
, name_buf
);
24593 strcat (tmp_buf
, ")\n\tori r12,r12,lo16(");
24594 strcat (tmp_buf
, name_buf
);
24595 strcat (tmp_buf
, ")\n\tmtctr r12\n\tbctr");
24597 output_asm_insn (tmp_buf
, 0);
24598 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
24599 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
24600 dbxout_stabd (N_SLINE
, bi
->line_number
);
24601 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
24602 VEC_pop (branch_island
, branch_islands
);
24606 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
24607 already there or not. */
24610 no_previous_def (tree function_name
)
24615 FOR_EACH_VEC_ELT (branch_island
, branch_islands
, ix
, bi
)
24616 if (function_name
== bi
->function_name
)
24621 /* GET_PREV_LABEL gets the label name from the previous definition of
24625 get_prev_label (tree function_name
)
24630 FOR_EACH_VEC_ELT (branch_island
, branch_islands
, ix
, bi
)
24631 if (function_name
== bi
->function_name
)
24632 return bi
->label_name
;
24636 /* INSN is either a function call or a millicode call. It may have an
24637 unconditional jump in its delay slot.
24639 CALL_DEST is the routine we are calling. */
24642 output_call (rtx insn
, rtx
*operands
, int dest_operand_number
,
24643 int cookie_operand_number
)
24645 static char buf
[256];
24646 if (darwin_emit_branch_islands
24647 && GET_CODE (operands
[dest_operand_number
]) == SYMBOL_REF
24648 && (INTVAL (operands
[cookie_operand_number
]) & CALL_LONG
))
24651 tree funname
= get_identifier (XSTR (operands
[dest_operand_number
], 0));
24653 if (no_previous_def (funname
))
24655 rtx label_rtx
= gen_label_rtx ();
24656 char *label_buf
, temp_buf
[256];
24657 ASM_GENERATE_INTERNAL_LABEL (temp_buf
, "L",
24658 CODE_LABEL_NUMBER (label_rtx
));
24659 label_buf
= temp_buf
[0] == '*' ? temp_buf
+ 1 : temp_buf
;
24660 labelname
= get_identifier (label_buf
);
24661 add_compiler_branch_island (labelname
, funname
, insn_line (insn
));
24664 labelname
= get_prev_label (funname
);
24666 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
24667 instruction will reach 'foo', otherwise link as 'bl L42'".
24668 "L42" should be a 'branch island', that will do a far jump to
24669 'foo'. Branch islands are generated in
24670 macho_branch_islands(). */
24671 sprintf (buf
, "jbsr %%z%d,%.246s",
24672 dest_operand_number
, IDENTIFIER_POINTER (labelname
));
24675 sprintf (buf
, "bl %%z%d", dest_operand_number
);
24679 /* Generate PIC and indirect symbol stubs. */
24682 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
24684 unsigned int length
;
24685 char *symbol_name
, *lazy_ptr_name
;
24686 char *local_label_0
;
24687 static int label
= 0;
24689 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
24690 symb
= (*targetm
.strip_name_encoding
) (symb
);
24693 length
= strlen (symb
);
24694 symbol_name
= XALLOCAVEC (char, length
+ 32);
24695 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
24697 lazy_ptr_name
= XALLOCAVEC (char, length
+ 32);
24698 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name
, symb
, length
);
24701 switch_to_section (darwin_sections
[machopic_picsymbol_stub1_section
]);
24703 switch_to_section (darwin_sections
[machopic_symbol_stub1_section
]);
24707 fprintf (file
, "\t.align 5\n");
24709 fprintf (file
, "%s:\n", stub
);
24710 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
24713 local_label_0
= XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
24714 sprintf (local_label_0
, "\"L%011d$spb\"", label
);
24716 fprintf (file
, "\tmflr r0\n");
24717 if (TARGET_LINK_STACK
)
24720 get_ppc476_thunk_name (name
);
24721 fprintf (file
, "\tbl %s\n", name
);
24722 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
24726 fprintf (file
, "\tbcl 20,31,%s\n", local_label_0
);
24727 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
24729 fprintf (file
, "\taddis r11,r11,ha16(%s-%s)\n",
24730 lazy_ptr_name
, local_label_0
);
24731 fprintf (file
, "\tmtlr r0\n");
24732 fprintf (file
, "\t%s r12,lo16(%s-%s)(r11)\n",
24733 (TARGET_64BIT
? "ldu" : "lwzu"),
24734 lazy_ptr_name
, local_label_0
);
24735 fprintf (file
, "\tmtctr r12\n");
24736 fprintf (file
, "\tbctr\n");
24740 fprintf (file
, "\t.align 4\n");
24742 fprintf (file
, "%s:\n", stub
);
24743 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
24745 fprintf (file
, "\tlis r11,ha16(%s)\n", lazy_ptr_name
);
24746 fprintf (file
, "\t%s r12,lo16(%s)(r11)\n",
24747 (TARGET_64BIT
? "ldu" : "lwzu"),
24749 fprintf (file
, "\tmtctr r12\n");
24750 fprintf (file
, "\tbctr\n");
24753 switch_to_section (darwin_sections
[machopic_lazy_symbol_ptr_section
]);
24754 fprintf (file
, "%s:\n", lazy_ptr_name
);
24755 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
24756 fprintf (file
, "%sdyld_stub_binding_helper\n",
24757 (TARGET_64BIT
? DOUBLE_INT_ASM_OP
: "\t.long\t"));
24760 /* Legitimize PIC addresses. If the address is already
24761 position-independent, we return ORIG. Newly generated
24762 position-independent addresses go into a reg. This is REG if non
24763 zero, otherwise we allocate register(s) as necessary. */
24765 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
24768 rs6000_machopic_legitimize_pic_address (rtx orig
, enum machine_mode mode
,
24773 if (reg
== NULL
&& ! reload_in_progress
&& ! reload_completed
)
24774 reg
= gen_reg_rtx (Pmode
);
24776 if (GET_CODE (orig
) == CONST
)
24780 if (GET_CODE (XEXP (orig
, 0)) == PLUS
24781 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
24784 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
24786 /* Use a different reg for the intermediate value, as
24787 it will be marked UNCHANGING. */
24788 reg_temp
= !can_create_pseudo_p () ? reg
: gen_reg_rtx (Pmode
);
24789 base
= rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0),
24792 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
24795 if (GET_CODE (offset
) == CONST_INT
)
24797 if (SMALL_INT (offset
))
24798 return plus_constant (base
, INTVAL (offset
));
24799 else if (! reload_in_progress
&& ! reload_completed
)
24800 offset
= force_reg (Pmode
, offset
);
24803 rtx mem
= force_const_mem (Pmode
, orig
);
24804 return machopic_legitimize_pic_address (mem
, Pmode
, reg
);
24807 return gen_rtx_PLUS (Pmode
, base
, offset
);
24810 /* Fall back on generic machopic code. */
24811 return machopic_legitimize_pic_address (orig
, mode
, reg
);
24814 /* Output a .machine directive for the Darwin assembler, and call
24815 the generic start_file routine. */
24818 rs6000_darwin_file_start (void)
24820 static const struct
24826 { "ppc64", "ppc64", MASK_64BIT
},
24827 { "970", "ppc970", MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
24828 { "power4", "ppc970", 0 },
24829 { "G5", "ppc970", 0 },
24830 { "7450", "ppc7450", 0 },
24831 { "7400", "ppc7400", MASK_ALTIVEC
},
24832 { "G4", "ppc7400", 0 },
24833 { "750", "ppc750", 0 },
24834 { "740", "ppc750", 0 },
24835 { "G3", "ppc750", 0 },
24836 { "604e", "ppc604e", 0 },
24837 { "604", "ppc604", 0 },
24838 { "603e", "ppc603", 0 },
24839 { "603", "ppc603", 0 },
24840 { "601", "ppc601", 0 },
24841 { NULL
, "ppc", 0 } };
24842 const char *cpu_id
= "";
24845 rs6000_file_start ();
24846 darwin_file_start ();
24848 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
24850 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
24851 cpu_id
= rs6000_default_cpu
;
24853 if (global_options_set
.x_rs6000_cpu_index
)
24854 cpu_id
= processor_target_table
[rs6000_cpu_index
].name
;
24856 /* Look through the mapping array. Pick the first name that either
24857 matches the argument, has a bit set in IF_SET that is also set
24858 in the target flags, or has a NULL name. */
24861 while (mapping
[i
].arg
!= NULL
24862 && strcmp (mapping
[i
].arg
, cpu_id
) != 0
24863 && (mapping
[i
].if_set
& target_flags
) == 0)
24866 fprintf (asm_out_file
, "\t.machine %s\n", mapping
[i
].name
);
24869 #endif /* TARGET_MACHO */
24873 rs6000_elf_reloc_rw_mask (void)
24877 else if (DEFAULT_ABI
== ABI_AIX
)
24883 /* Record an element in the table of global constructors. SYMBOL is
24884 a SYMBOL_REF of the function to be called; PRIORITY is a number
24885 between 0 and MAX_INIT_PRIORITY.
24887 This differs from default_named_section_asm_out_constructor in
24888 that we have special handling for -mrelocatable. */
24891 rs6000_elf_asm_out_constructor (rtx symbol
, int priority
)
24893 const char *section
= ".ctors";
24896 if (priority
!= DEFAULT_INIT_PRIORITY
)
24898 sprintf (buf
, ".ctors.%.5u",
24899 /* Invert the numbering so the linker puts us in the proper
24900 order; constructors are run from right to left, and the
24901 linker sorts in increasing order. */
24902 MAX_INIT_PRIORITY
- priority
);
24906 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
24907 assemble_align (POINTER_SIZE
);
24909 if (TARGET_RELOCATABLE
)
24911 fputs ("\t.long (", asm_out_file
);
24912 output_addr_const (asm_out_file
, symbol
);
24913 fputs (")@fixup\n", asm_out_file
);
24916 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
24920 rs6000_elf_asm_out_destructor (rtx symbol
, int priority
)
24922 const char *section
= ".dtors";
24925 if (priority
!= DEFAULT_INIT_PRIORITY
)
24927 sprintf (buf
, ".dtors.%.5u",
24928 /* Invert the numbering so the linker puts us in the proper
24929 order; constructors are run from right to left, and the
24930 linker sorts in increasing order. */
24931 MAX_INIT_PRIORITY
- priority
);
24935 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
24936 assemble_align (POINTER_SIZE
);
24938 if (TARGET_RELOCATABLE
)
24940 fputs ("\t.long (", asm_out_file
);
24941 output_addr_const (asm_out_file
, symbol
);
24942 fputs (")@fixup\n", asm_out_file
);
24945 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
24949 rs6000_elf_declare_function_name (FILE *file
, const char *name
, tree decl
)
24953 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file
);
24954 ASM_OUTPUT_LABEL (file
, name
);
24955 fputs (DOUBLE_INT_ASM_OP
, file
);
24956 rs6000_output_function_entry (file
, name
);
24957 fputs (",.TOC.@tocbase,0\n\t.previous\n", file
);
24960 fputs ("\t.size\t", file
);
24961 assemble_name (file
, name
);
24962 fputs (",24\n\t.type\t.", file
);
24963 assemble_name (file
, name
);
24964 fputs (",@function\n", file
);
24965 if (TREE_PUBLIC (decl
) && ! DECL_WEAK (decl
))
24967 fputs ("\t.globl\t.", file
);
24968 assemble_name (file
, name
);
24973 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
24974 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
24975 rs6000_output_function_entry (file
, name
);
24976 fputs (":\n", file
);
24980 if (TARGET_RELOCATABLE
24981 && !TARGET_SECURE_PLT
24982 && (get_pool_size () != 0 || crtl
->profile
)
24987 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
24989 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
24990 fprintf (file
, "\t.long ");
24991 assemble_name (file
, buf
);
24993 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
24994 assemble_name (file
, buf
);
24998 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
24999 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
25001 if (DEFAULT_ABI
== ABI_AIX
)
25003 const char *desc_name
, *orig_name
;
25005 orig_name
= (*targetm
.strip_name_encoding
) (name
);
25006 desc_name
= orig_name
;
25007 while (*desc_name
== '.')
25010 if (TREE_PUBLIC (decl
))
25011 fprintf (file
, "\t.globl %s\n", desc_name
);
25013 fprintf (file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
25014 fprintf (file
, "%s:\n", desc_name
);
25015 fprintf (file
, "\t.long %s\n", orig_name
);
25016 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file
);
25017 if (DEFAULT_ABI
== ABI_AIX
)
25018 fputs ("\t.long 0\n", file
);
25019 fprintf (file
, "\t.previous\n");
25021 ASM_OUTPUT_LABEL (file
, name
);
25025 rs6000_elf_file_end (void)
25027 #ifdef HAVE_AS_GNU_ATTRIBUTE
25028 if (TARGET_32BIT
&& DEFAULT_ABI
== ABI_V4
)
25030 if (rs6000_passes_float
)
25031 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n",
25032 ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
) ? 1
25033 : (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_SINGLE_FLOAT
) ? 3
25035 if (rs6000_passes_vector
)
25036 fprintf (asm_out_file
, "\t.gnu_attribute 8, %d\n",
25037 (TARGET_ALTIVEC_ABI
? 2
25038 : TARGET_SPE_ABI
? 3
25040 if (rs6000_returns_struct
)
25041 fprintf (asm_out_file
, "\t.gnu_attribute 12, %d\n",
25042 aix_struct_return
? 2 : 1);
25045 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
25047 file_end_indicate_exec_stack ();
25054 rs6000_xcoff_asm_output_anchor (rtx symbol
)
25058 sprintf (buffer
, "$ + " HOST_WIDE_INT_PRINT_DEC
,
25059 SYMBOL_REF_BLOCK_OFFSET (symbol
));
25060 ASM_OUTPUT_DEF (asm_out_file
, XSTR (symbol
, 0), buffer
);
25064 rs6000_xcoff_asm_globalize_label (FILE *stream
, const char *name
)
25066 fputs (GLOBAL_ASM_OP
, stream
);
25067 RS6000_OUTPUT_BASENAME (stream
, name
);
25068 putc ('\n', stream
);
25071 /* A get_unnamed_decl callback, used for read-only sections. PTR
25072 points to the section string variable. */
25075 rs6000_xcoff_output_readonly_section_asm_op (const void *directive
)
25077 fprintf (asm_out_file
, "\t.csect %s[RO],%s\n",
25078 *(const char *const *) directive
,
25079 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
25082 /* Likewise for read-write sections. */
25085 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive
)
25087 fprintf (asm_out_file
, "\t.csect %s[RW],%s\n",
25088 *(const char *const *) directive
,
25089 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
25092 /* A get_unnamed_section callback, used for switching to toc_section. */
25095 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
25097 if (TARGET_MINIMAL_TOC
)
25099 /* toc_section is always selected at least once from
25100 rs6000_xcoff_file_start, so this is guaranteed to
25101 always be defined once and only once in each file. */
25102 if (!toc_initialized
)
25104 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file
);
25105 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file
);
25106 toc_initialized
= 1;
25108 fprintf (asm_out_file
, "\t.csect toc_table[RW]%s\n",
25109 (TARGET_32BIT
? "" : ",3"));
25112 fputs ("\t.toc\n", asm_out_file
);
25115 /* Implement TARGET_ASM_INIT_SECTIONS. */
25118 rs6000_xcoff_asm_init_sections (void)
25120 read_only_data_section
25121 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
25122 &xcoff_read_only_section_name
);
25124 private_data_section
25125 = get_unnamed_section (SECTION_WRITE
,
25126 rs6000_xcoff_output_readwrite_section_asm_op
,
25127 &xcoff_private_data_section_name
);
25129 read_only_private_data_section
25130 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
25131 &xcoff_private_data_section_name
);
25134 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op
, NULL
);
25136 readonly_data_section
= read_only_data_section
;
25137 exception_section
= data_section
;
25141 rs6000_xcoff_reloc_rw_mask (void)
25147 rs6000_xcoff_asm_named_section (const char *name
, unsigned int flags
,
25148 tree decl ATTRIBUTE_UNUSED
)
25151 static const char * const suffix
[3] = { "PR", "RO", "RW" };
25153 if (flags
& SECTION_CODE
)
25155 else if (flags
& SECTION_WRITE
)
25160 fprintf (asm_out_file
, "\t.csect %s%s[%s],%u\n",
25161 (flags
& SECTION_CODE
) ? "." : "",
25162 name
, suffix
[smclass
], flags
& SECTION_ENTSIZE
);
25166 rs6000_xcoff_select_section (tree decl
, int reloc
,
25167 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
25169 if (decl_readonly_section (decl
, reloc
))
25171 if (TREE_PUBLIC (decl
))
25172 return read_only_data_section
;
25174 return read_only_private_data_section
;
25178 if (TREE_PUBLIC (decl
))
25179 return data_section
;
25181 return private_data_section
;
25186 rs6000_xcoff_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
25190 /* Use select_section for private and uninitialized data. */
25191 if (!TREE_PUBLIC (decl
)
25192 || DECL_COMMON (decl
)
25193 || DECL_INITIAL (decl
) == NULL_TREE
25194 || DECL_INITIAL (decl
) == error_mark_node
25195 || (flag_zero_initialized_in_bss
25196 && initializer_zerop (DECL_INITIAL (decl
))))
25199 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
25200 name
= (*targetm
.strip_name_encoding
) (name
);
25201 DECL_SECTION_NAME (decl
) = build_string (strlen (name
), name
);
25204 /* Select section for constant in constant pool.
25206 On RS/6000, all constants are in the private read-only data area.
25207 However, if this is being placed in the TOC it must be output as a
25211 rs6000_xcoff_select_rtx_section (enum machine_mode mode
, rtx x
,
25212 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
25214 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
25215 return toc_section
;
25217 return read_only_private_data_section
;
25220 /* Remove any trailing [DS] or the like from the symbol name. */
25222 static const char *
25223 rs6000_xcoff_strip_name_encoding (const char *name
)
25228 len
= strlen (name
);
25229 if (name
[len
- 1] == ']')
25230 return ggc_alloc_string (name
, len
- 4);
25235 /* Section attributes. AIX is always PIC. */
25237 static unsigned int
25238 rs6000_xcoff_section_type_flags (tree decl
, const char *name
, int reloc
)
25240 unsigned int align
;
25241 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
25243 /* Align to at least UNIT size. */
25244 if (flags
& SECTION_CODE
|| !decl
)
25245 align
= MIN_UNITS_PER_WORD
;
25247 /* Increase alignment of large objects if not already stricter. */
25248 align
= MAX ((DECL_ALIGN (decl
) / BITS_PER_UNIT
),
25249 int_size_in_bytes (TREE_TYPE (decl
)) > MIN_UNITS_PER_WORD
25250 ? UNITS_PER_FP_WORD
: MIN_UNITS_PER_WORD
);
25252 return flags
| (exact_log2 (align
) & SECTION_ENTSIZE
);
25255 /* Output at beginning of assembler file.
25257 Initialize the section names for the RS/6000 at this point.
25259 Specify filename, including full path, to assembler.
25261 We want to go into the TOC section so at least one .toc will be emitted.
25262 Also, in order to output proper .bs/.es pairs, we need at least one static
25263 [RW] section emitted.
25265 Finally, declare mcount when profiling to make the assembler happy. */
25268 rs6000_xcoff_file_start (void)
25270 rs6000_gen_section_name (&xcoff_bss_section_name
,
25271 main_input_filename
, ".bss_");
25272 rs6000_gen_section_name (&xcoff_private_data_section_name
,
25273 main_input_filename
, ".rw_");
25274 rs6000_gen_section_name (&xcoff_read_only_section_name
,
25275 main_input_filename
, ".ro_");
25277 fputs ("\t.file\t", asm_out_file
);
25278 output_quoted_string (asm_out_file
, main_input_filename
);
25279 fputc ('\n', asm_out_file
);
25280 if (write_symbols
!= NO_DEBUG
)
25281 switch_to_section (private_data_section
);
25282 switch_to_section (text_section
);
25284 fprintf (asm_out_file
, "\t.extern %s\n", RS6000_MCOUNT
);
25285 rs6000_file_start ();
25288 /* Output at end of assembler file.
25289 On the RS/6000, referencing data should automatically pull in text. */
25292 rs6000_xcoff_file_end (void)
25294 switch_to_section (text_section
);
25295 fputs ("_section_.text:\n", asm_out_file
);
25296 switch_to_section (data_section
);
25297 fputs (TARGET_32BIT
25298 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
25301 #endif /* TARGET_XCOFF */
25303 /* Compute a (partial) cost for rtx X. Return true if the complete
25304 cost has been computed, and false if subexpressions should be
25305 scanned. In either case, *TOTAL contains the cost result. */
25308 rs6000_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
25309 int *total
, bool speed
)
25311 enum machine_mode mode
= GET_MODE (x
);
25315 /* On the RS/6000, if it is valid in the insn, it is free. */
25317 if (((outer_code
== SET
25318 || outer_code
== PLUS
25319 || outer_code
== MINUS
)
25320 && (satisfies_constraint_I (x
)
25321 || satisfies_constraint_L (x
)))
25322 || (outer_code
== AND
25323 && (satisfies_constraint_K (x
)
25325 ? satisfies_constraint_L (x
)
25326 : satisfies_constraint_J (x
))
25327 || mask_operand (x
, mode
)
25329 && mask64_operand (x
, DImode
))))
25330 || ((outer_code
== IOR
|| outer_code
== XOR
)
25331 && (satisfies_constraint_K (x
)
25333 ? satisfies_constraint_L (x
)
25334 : satisfies_constraint_J (x
))))
25335 || outer_code
== ASHIFT
25336 || outer_code
== ASHIFTRT
25337 || outer_code
== LSHIFTRT
25338 || outer_code
== ROTATE
25339 || outer_code
== ROTATERT
25340 || outer_code
== ZERO_EXTRACT
25341 || (outer_code
== MULT
25342 && satisfies_constraint_I (x
))
25343 || ((outer_code
== DIV
|| outer_code
== UDIV
25344 || outer_code
== MOD
|| outer_code
== UMOD
)
25345 && exact_log2 (INTVAL (x
)) >= 0)
25346 || (outer_code
== COMPARE
25347 && (satisfies_constraint_I (x
)
25348 || satisfies_constraint_K (x
)))
25349 || ((outer_code
== EQ
|| outer_code
== NE
)
25350 && (satisfies_constraint_I (x
)
25351 || satisfies_constraint_K (x
)
25353 ? satisfies_constraint_L (x
)
25354 : satisfies_constraint_J (x
))))
25355 || (outer_code
== GTU
25356 && satisfies_constraint_I (x
))
25357 || (outer_code
== LTU
25358 && satisfies_constraint_P (x
)))
25363 else if ((outer_code
== PLUS
25364 && reg_or_add_cint_operand (x
, VOIDmode
))
25365 || (outer_code
== MINUS
25366 && reg_or_sub_cint_operand (x
, VOIDmode
))
25367 || ((outer_code
== SET
25368 || outer_code
== IOR
25369 || outer_code
== XOR
)
25371 & ~ (unsigned HOST_WIDE_INT
) 0xffffffff) == 0))
25373 *total
= COSTS_N_INSNS (1);
25379 if (mode
== DImode
&& code
== CONST_DOUBLE
)
25381 if ((outer_code
== IOR
|| outer_code
== XOR
)
25382 && CONST_DOUBLE_HIGH (x
) == 0
25383 && (CONST_DOUBLE_LOW (x
)
25384 & ~ (unsigned HOST_WIDE_INT
) 0xffff) == 0)
25389 else if ((outer_code
== AND
&& and64_2_operand (x
, DImode
))
25390 || ((outer_code
== SET
25391 || outer_code
== IOR
25392 || outer_code
== XOR
)
25393 && CONST_DOUBLE_HIGH (x
) == 0))
25395 *total
= COSTS_N_INSNS (1);
25405 /* When optimizing for size, MEM should be slightly more expensive
25406 than generating address, e.g., (plus (reg) (const)).
25407 L1 cache latency is about two instructions. */
25408 *total
= !speed
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
25417 if (FLOAT_MODE_P (mode
))
25418 *total
= rs6000_cost
->fp
;
25420 *total
= COSTS_N_INSNS (1);
25424 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
25425 && satisfies_constraint_I (XEXP (x
, 1)))
25427 if (INTVAL (XEXP (x
, 1)) >= -256
25428 && INTVAL (XEXP (x
, 1)) <= 255)
25429 *total
= rs6000_cost
->mulsi_const9
;
25431 *total
= rs6000_cost
->mulsi_const
;
25433 else if (mode
== SFmode
)
25434 *total
= rs6000_cost
->fp
;
25435 else if (FLOAT_MODE_P (mode
))
25436 *total
= rs6000_cost
->dmul
;
25437 else if (mode
== DImode
)
25438 *total
= rs6000_cost
->muldi
;
25440 *total
= rs6000_cost
->mulsi
;
25444 if (mode
== SFmode
)
25445 *total
= rs6000_cost
->fp
;
25447 *total
= rs6000_cost
->dmul
;
25452 if (FLOAT_MODE_P (mode
))
25454 *total
= mode
== DFmode
? rs6000_cost
->ddiv
25455 : rs6000_cost
->sdiv
;
25462 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
25463 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
25465 if (code
== DIV
|| code
== MOD
)
25467 *total
= COSTS_N_INSNS (2);
25470 *total
= COSTS_N_INSNS (1);
25474 if (GET_MODE (XEXP (x
, 1)) == DImode
)
25475 *total
= rs6000_cost
->divdi
;
25477 *total
= rs6000_cost
->divsi
;
25479 /* Add in shift and subtract for MOD. */
25480 if (code
== MOD
|| code
== UMOD
)
25481 *total
+= COSTS_N_INSNS (2);
25486 *total
= COSTS_N_INSNS (4);
25490 *total
= COSTS_N_INSNS (TARGET_POPCNTD
? 1 : 6);
25494 *total
= COSTS_N_INSNS (TARGET_CMPB
? 2 : 6);
25498 if (outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
25510 *total
= COSTS_N_INSNS (1);
25518 /* Handle mul_highpart. */
25519 if (outer_code
== TRUNCATE
25520 && GET_CODE (XEXP (x
, 0)) == MULT
)
25522 if (mode
== DImode
)
25523 *total
= rs6000_cost
->muldi
;
25525 *total
= rs6000_cost
->mulsi
;
25528 else if (outer_code
== AND
)
25531 *total
= COSTS_N_INSNS (1);
25536 if (GET_CODE (XEXP (x
, 0)) == MEM
)
25539 *total
= COSTS_N_INSNS (1);
25545 if (!FLOAT_MODE_P (mode
))
25547 *total
= COSTS_N_INSNS (1);
25553 case UNSIGNED_FLOAT
:
25556 case FLOAT_TRUNCATE
:
25557 *total
= rs6000_cost
->fp
;
25561 if (mode
== DFmode
)
25564 *total
= rs6000_cost
->fp
;
25568 switch (XINT (x
, 1))
25571 *total
= rs6000_cost
->fp
;
25583 *total
= COSTS_N_INSNS (1);
25586 else if (FLOAT_MODE_P (mode
)
25587 && TARGET_PPC_GFXOPT
&& TARGET_HARD_FLOAT
&& TARGET_FPRS
)
25589 *total
= rs6000_cost
->fp
;
25597 /* Carry bit requires mode == Pmode.
25598 NEG or PLUS already counted so only add one. */
25600 && (outer_code
== NEG
|| outer_code
== PLUS
))
25602 *total
= COSTS_N_INSNS (1);
25605 if (outer_code
== SET
)
25607 if (XEXP (x
, 1) == const0_rtx
)
25609 if (TARGET_ISEL
&& !TARGET_MFCRF
)
25610 *total
= COSTS_N_INSNS (8);
25612 *total
= COSTS_N_INSNS (2);
25615 else if (mode
== Pmode
)
25617 *total
= COSTS_N_INSNS (3);
25626 if (outer_code
== SET
&& (XEXP (x
, 1) == const0_rtx
))
25628 if (TARGET_ISEL
&& !TARGET_MFCRF
)
25629 *total
= COSTS_N_INSNS (8);
25631 *total
= COSTS_N_INSNS (2);
25635 if (outer_code
== COMPARE
)
25649 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
25652 rs6000_debug_rtx_costs (rtx x
, int code
, int outer_code
, int opno
, int *total
,
25655 bool ret
= rs6000_rtx_costs (x
, code
, outer_code
, opno
, total
, speed
);
25658 "\nrs6000_rtx_costs, return = %s, code = %s, outer_code = %s, "
25659 "opno = %d, total = %d, speed = %s, x:\n",
25660 ret
? "complete" : "scan inner",
25661 GET_RTX_NAME (code
),
25662 GET_RTX_NAME (outer_code
),
25665 speed
? "true" : "false");
25672 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
25675 rs6000_debug_address_cost (rtx x
, bool speed
)
25677 int ret
= TARGET_ADDRESS_COST (x
, speed
);
25679 fprintf (stderr
, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
25680 ret
, speed
? "true" : "false");
25687 /* A C expression returning the cost of moving data from a register of class
25688 CLASS1 to one of CLASS2. */
25691 rs6000_register_move_cost (enum machine_mode mode
,
25692 reg_class_t from
, reg_class_t to
)
25696 if (TARGET_DEBUG_COST
)
25699 /* Moves from/to GENERAL_REGS. */
25700 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
25701 || reg_classes_intersect_p (from
, GENERAL_REGS
))
25703 reg_class_t rclass
= from
;
25705 if (! reg_classes_intersect_p (to
, GENERAL_REGS
))
25708 if (rclass
== FLOAT_REGS
|| rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
25709 ret
= (rs6000_memory_move_cost (mode
, rclass
, false)
25710 + rs6000_memory_move_cost (mode
, GENERAL_REGS
, false));
25712 /* It's more expensive to move CR_REGS than CR0_REGS because of the
25714 else if (rclass
== CR_REGS
)
25717 /* For those processors that have slow LR/CTR moves, make them more
25718 expensive than memory in order to bias spills to memory .*/
25719 else if ((rs6000_cpu
== PROCESSOR_POWER6
25720 || rs6000_cpu
== PROCESSOR_POWER7
)
25721 && reg_classes_intersect_p (rclass
, LINK_OR_CTR_REGS
))
25722 ret
= 6 * hard_regno_nregs
[0][mode
];
25725 /* A move will cost one instruction per GPR moved. */
25726 ret
= 2 * hard_regno_nregs
[0][mode
];
25729 /* If we have VSX, we can easily move between FPR or Altivec registers. */
25730 else if (VECTOR_UNIT_VSX_P (mode
)
25731 && reg_classes_intersect_p (to
, VSX_REGS
)
25732 && reg_classes_intersect_p (from
, VSX_REGS
))
25733 ret
= 2 * hard_regno_nregs
[32][mode
];
25735 /* Moving between two similar registers is just one instruction. */
25736 else if (reg_classes_intersect_p (to
, from
))
25737 ret
= (mode
== TFmode
|| mode
== TDmode
) ? 4 : 2;
25739 /* Everything else has to go through GENERAL_REGS. */
25741 ret
= (rs6000_register_move_cost (mode
, GENERAL_REGS
, to
)
25742 + rs6000_register_move_cost (mode
, from
, GENERAL_REGS
));
25744 if (TARGET_DEBUG_COST
)
25746 if (dbg_cost_ctrl
== 1)
25748 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
25749 ret
, GET_MODE_NAME (mode
), reg_class_names
[from
],
25750 reg_class_names
[to
]);
25757 /* A C expressions returning the cost of moving data of MODE from a register to
25761 rs6000_memory_move_cost (enum machine_mode mode
, reg_class_t rclass
,
25762 bool in ATTRIBUTE_UNUSED
)
25766 if (TARGET_DEBUG_COST
)
25769 if (reg_classes_intersect_p (rclass
, GENERAL_REGS
))
25770 ret
= 4 * hard_regno_nregs
[0][mode
];
25771 else if (reg_classes_intersect_p (rclass
, FLOAT_REGS
))
25772 ret
= 4 * hard_regno_nregs
[32][mode
];
25773 else if (reg_classes_intersect_p (rclass
, ALTIVEC_REGS
))
25774 ret
= 4 * hard_regno_nregs
[FIRST_ALTIVEC_REGNO
][mode
];
25776 ret
= 4 + rs6000_register_move_cost (mode
, rclass
, GENERAL_REGS
);
25778 if (TARGET_DEBUG_COST
)
25780 if (dbg_cost_ctrl
== 1)
25782 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
25783 ret
, GET_MODE_NAME (mode
), reg_class_names
[rclass
], in
);
25790 /* Returns a code for a target-specific builtin that implements
25791 reciprocal of the function, or NULL_TREE if not available. */
25794 rs6000_builtin_reciprocal (unsigned int fn
, bool md_fn
,
25795 bool sqrt ATTRIBUTE_UNUSED
)
25797 if (optimize_insn_for_size_p ())
25803 case VSX_BUILTIN_XVSQRTDP
:
25804 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode
))
25807 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
25809 case VSX_BUILTIN_XVSQRTSP
:
25810 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode
))
25813 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_4SF
];
25822 case BUILT_IN_SQRT
:
25823 if (!RS6000_RECIP_AUTO_RSQRTE_P (DFmode
))
25826 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRT
];
25828 case BUILT_IN_SQRTF
:
25829 if (!RS6000_RECIP_AUTO_RSQRTE_P (SFmode
))
25832 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRTF
];
25839 /* Load up a constant. If the mode is a vector mode, splat the value across
25840 all of the vector elements. */
25843 rs6000_load_constant_and_splat (enum machine_mode mode
, REAL_VALUE_TYPE dconst
)
25847 if (mode
== SFmode
|| mode
== DFmode
)
25849 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, mode
);
25850 reg
= force_reg (mode
, d
);
25852 else if (mode
== V4SFmode
)
25854 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, SFmode
);
25855 rtvec v
= gen_rtvec (4, d
, d
, d
, d
);
25856 reg
= gen_reg_rtx (mode
);
25857 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
25859 else if (mode
== V2DFmode
)
25861 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, DFmode
);
25862 rtvec v
= gen_rtvec (2, d
, d
);
25863 reg
= gen_reg_rtx (mode
);
25864 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
25867 gcc_unreachable ();
25872 /* Generate an FMA instruction. */
25875 rs6000_emit_madd (rtx target
, rtx m1
, rtx m2
, rtx a
)
25877 enum machine_mode mode
= GET_MODE (target
);
25880 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
25881 gcc_assert (dst
!= NULL
);
25884 emit_move_insn (target
, dst
);
25887 /* Generate a FMSUB instruction: dst = fma(m1, m2, -a). */
25890 rs6000_emit_msub (rtx target
, rtx m1
, rtx m2
, rtx a
)
25892 enum machine_mode mode
= GET_MODE (target
);
25895 /* Altivec does not support fms directly;
25896 generate in terms of fma in that case. */
25897 if (optab_handler (fms_optab
, mode
) != CODE_FOR_nothing
)
25898 dst
= expand_ternary_op (mode
, fms_optab
, m1
, m2
, a
, target
, 0);
25901 a
= expand_unop (mode
, neg_optab
, a
, NULL_RTX
, 0);
25902 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
25904 gcc_assert (dst
!= NULL
);
25907 emit_move_insn (target
, dst
);
25910 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
25913 rs6000_emit_nmsub (rtx dst
, rtx m1
, rtx m2
, rtx a
)
25915 enum machine_mode mode
= GET_MODE (dst
);
25918 /* This is a tad more complicated, since the fnma_optab is for
25919 a different expression: fma(-m1, m2, a), which is the same
25920 thing except in the case of signed zeros.
25922 Fortunately we know that if FMA is supported that FNMSUB is
25923 also supported in the ISA. Just expand it directly. */
25925 gcc_assert (optab_handler (fma_optab
, mode
) != CODE_FOR_nothing
);
25927 r
= gen_rtx_NEG (mode
, a
);
25928 r
= gen_rtx_FMA (mode
, m1
, m2
, r
);
25929 r
= gen_rtx_NEG (mode
, r
);
25930 emit_insn (gen_rtx_SET (VOIDmode
, dst
, r
));
25933 /* Newton-Raphson approximation of floating point divide with just 2 passes
25934 (either single precision floating point, or newer machines with higher
25935 accuracy estimates). Support both scalar and vector divide. Assumes no
25936 trapping math and finite arguments. */
25939 rs6000_emit_swdiv_high_precision (rtx dst
, rtx n
, rtx d
)
25941 enum machine_mode mode
= GET_MODE (dst
);
25942 rtx x0
, e0
, e1
, y1
, u0
, v0
;
25943 enum insn_code code
= optab_handler (smul_optab
, mode
);
25944 gen_2arg_fn_t gen_mul
= (gen_2arg_fn_t
) GEN_FCN (code
);
25945 rtx one
= rs6000_load_constant_and_splat (mode
, dconst1
);
25947 gcc_assert (code
!= CODE_FOR_nothing
);
25949 /* x0 = 1./d estimate */
25950 x0
= gen_reg_rtx (mode
);
25951 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
25952 gen_rtx_UNSPEC (mode
, gen_rtvec (1, d
),
25955 e0
= gen_reg_rtx (mode
);
25956 rs6000_emit_nmsub (e0
, d
, x0
, one
); /* e0 = 1. - (d * x0) */
25958 e1
= gen_reg_rtx (mode
);
25959 rs6000_emit_madd (e1
, e0
, e0
, e0
); /* e1 = (e0 * e0) + e0 */
25961 y1
= gen_reg_rtx (mode
);
25962 rs6000_emit_madd (y1
, e1
, x0
, x0
); /* y1 = (e1 * x0) + x0 */
25964 u0
= gen_reg_rtx (mode
);
25965 emit_insn (gen_mul (u0
, n
, y1
)); /* u0 = n * y1 */
25967 v0
= gen_reg_rtx (mode
);
25968 rs6000_emit_nmsub (v0
, d
, u0
, n
); /* v0 = n - (d * u0) */
25970 rs6000_emit_madd (dst
, v0
, y1
, u0
); /* dst = (v0 * y1) + u0 */
25973 /* Newton-Raphson approximation of floating point divide that has a low
25974 precision estimate. Assumes no trapping math and finite arguments. */
25977 rs6000_emit_swdiv_low_precision (rtx dst
, rtx n
, rtx d
)
25979 enum machine_mode mode
= GET_MODE (dst
);
25980 rtx x0
, e0
, e1
, e2
, y1
, y2
, y3
, u0
, v0
, one
;
25981 enum insn_code code
= optab_handler (smul_optab
, mode
);
25982 gen_2arg_fn_t gen_mul
= (gen_2arg_fn_t
) GEN_FCN (code
);
25984 gcc_assert (code
!= CODE_FOR_nothing
);
25986 one
= rs6000_load_constant_and_splat (mode
, dconst1
);
25988 /* x0 = 1./d estimate */
25989 x0
= gen_reg_rtx (mode
);
25990 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
25991 gen_rtx_UNSPEC (mode
, gen_rtvec (1, d
),
25994 e0
= gen_reg_rtx (mode
);
25995 rs6000_emit_nmsub (e0
, d
, x0
, one
); /* e0 = 1. - d * x0 */
25997 y1
= gen_reg_rtx (mode
);
25998 rs6000_emit_madd (y1
, e0
, x0
, x0
); /* y1 = x0 + e0 * x0 */
26000 e1
= gen_reg_rtx (mode
);
26001 emit_insn (gen_mul (e1
, e0
, e0
)); /* e1 = e0 * e0 */
26003 y2
= gen_reg_rtx (mode
);
26004 rs6000_emit_madd (y2
, e1
, y1
, y1
); /* y2 = y1 + e1 * y1 */
26006 e2
= gen_reg_rtx (mode
);
26007 emit_insn (gen_mul (e2
, e1
, e1
)); /* e2 = e1 * e1 */
26009 y3
= gen_reg_rtx (mode
);
26010 rs6000_emit_madd (y3
, e2
, y2
, y2
); /* y3 = y2 + e2 * y2 */
26012 u0
= gen_reg_rtx (mode
);
26013 emit_insn (gen_mul (u0
, n
, y3
)); /* u0 = n * y3 */
26015 v0
= gen_reg_rtx (mode
);
26016 rs6000_emit_nmsub (v0
, d
, u0
, n
); /* v0 = n - d * u0 */
26018 rs6000_emit_madd (dst
, v0
, y3
, u0
); /* dst = u0 + v0 * y3 */
26021 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
26022 add a reg_note saying that this was a division. Support both scalar and
26023 vector divide. Assumes no trapping math and finite arguments. */
26026 rs6000_emit_swdiv (rtx dst
, rtx n
, rtx d
, bool note_p
)
26028 enum machine_mode mode
= GET_MODE (dst
);
26030 if (RS6000_RECIP_HIGH_PRECISION_P (mode
))
26031 rs6000_emit_swdiv_high_precision (dst
, n
, d
);
26033 rs6000_emit_swdiv_low_precision (dst
, n
, d
);
26036 add_reg_note (get_last_insn (), REG_EQUAL
, gen_rtx_DIV (mode
, n
, d
));
26039 /* Newton-Raphson approximation of single/double-precision floating point
26040 rsqrt. Assumes no trapping math and finite arguments. */
26043 rs6000_emit_swrsqrt (rtx dst
, rtx src
)
26045 enum machine_mode mode
= GET_MODE (src
);
26046 rtx x0
= gen_reg_rtx (mode
);
26047 rtx y
= gen_reg_rtx (mode
);
26048 int passes
= (TARGET_RECIP_PRECISION
) ? 2 : 3;
26049 REAL_VALUE_TYPE dconst3_2
;
26052 enum insn_code code
= optab_handler (smul_optab
, mode
);
26053 gen_2arg_fn_t gen_mul
= (gen_2arg_fn_t
) GEN_FCN (code
);
26055 gcc_assert (code
!= CODE_FOR_nothing
);
26057 /* Load up the constant 1.5 either as a scalar, or as a vector. */
26058 real_from_integer (&dconst3_2
, VOIDmode
, 3, 0, 0);
26059 SET_REAL_EXP (&dconst3_2
, REAL_EXP (&dconst3_2
) - 1);
26061 halfthree
= rs6000_load_constant_and_splat (mode
, dconst3_2
);
26063 /* x0 = rsqrt estimate */
26064 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
26065 gen_rtx_UNSPEC (mode
, gen_rtvec (1, src
),
26068 /* y = 0.5 * src = 1.5 * src - src -> fewer constants */
26069 rs6000_emit_msub (y
, src
, halfthree
, src
);
26071 for (i
= 0; i
< passes
; i
++)
26073 rtx x1
= gen_reg_rtx (mode
);
26074 rtx u
= gen_reg_rtx (mode
);
26075 rtx v
= gen_reg_rtx (mode
);
26077 /* x1 = x0 * (1.5 - y * (x0 * x0)) */
26078 emit_insn (gen_mul (u
, x0
, x0
));
26079 rs6000_emit_nmsub (v
, y
, u
, halfthree
);
26080 emit_insn (gen_mul (x1
, x0
, v
));
26084 emit_move_insn (dst
, x0
);
26088 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
26089 (Power7) targets. DST is the target, and SRC is the argument operand. */
26092 rs6000_emit_popcount (rtx dst
, rtx src
)
26094 enum machine_mode mode
= GET_MODE (dst
);
26097 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
26098 if (TARGET_POPCNTD
)
26100 if (mode
== SImode
)
26101 emit_insn (gen_popcntdsi2 (dst
, src
));
26103 emit_insn (gen_popcntddi2 (dst
, src
));
26107 tmp1
= gen_reg_rtx (mode
);
26109 if (mode
== SImode
)
26111 emit_insn (gen_popcntbsi2 (tmp1
, src
));
26112 tmp2
= expand_mult (SImode
, tmp1
, GEN_INT (0x01010101),
26114 tmp2
= force_reg (SImode
, tmp2
);
26115 emit_insn (gen_lshrsi3 (dst
, tmp2
, GEN_INT (24)));
26119 emit_insn (gen_popcntbdi2 (tmp1
, src
));
26120 tmp2
= expand_mult (DImode
, tmp1
,
26121 GEN_INT ((HOST_WIDE_INT
)
26122 0x01010101 << 32 | 0x01010101),
26124 tmp2
= force_reg (DImode
, tmp2
);
26125 emit_insn (gen_lshrdi3 (dst
, tmp2
, GEN_INT (56)));
26130 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
26131 target, and SRC is the argument operand. */
26134 rs6000_emit_parity (rtx dst
, rtx src
)
26136 enum machine_mode mode
= GET_MODE (dst
);
26139 tmp
= gen_reg_rtx (mode
);
26141 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
26144 if (mode
== SImode
)
26146 emit_insn (gen_popcntbsi2 (tmp
, src
));
26147 emit_insn (gen_paritysi2_cmpb (dst
, tmp
));
26151 emit_insn (gen_popcntbdi2 (tmp
, src
));
26152 emit_insn (gen_paritydi2_cmpb (dst
, tmp
));
26157 if (mode
== SImode
)
26159 /* Is mult+shift >= shift+xor+shift+xor? */
26160 if (rs6000_cost
->mulsi_const
>= COSTS_N_INSNS (3))
26162 rtx tmp1
, tmp2
, tmp3
, tmp4
;
26164 tmp1
= gen_reg_rtx (SImode
);
26165 emit_insn (gen_popcntbsi2 (tmp1
, src
));
26167 tmp2
= gen_reg_rtx (SImode
);
26168 emit_insn (gen_lshrsi3 (tmp2
, tmp1
, GEN_INT (16)));
26169 tmp3
= gen_reg_rtx (SImode
);
26170 emit_insn (gen_xorsi3 (tmp3
, tmp1
, tmp2
));
26172 tmp4
= gen_reg_rtx (SImode
);
26173 emit_insn (gen_lshrsi3 (tmp4
, tmp3
, GEN_INT (8)));
26174 emit_insn (gen_xorsi3 (tmp
, tmp3
, tmp4
));
26177 rs6000_emit_popcount (tmp
, src
);
26178 emit_insn (gen_andsi3 (dst
, tmp
, const1_rtx
));
26182 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
26183 if (rs6000_cost
->muldi
>= COSTS_N_INSNS (5))
26185 rtx tmp1
, tmp2
, tmp3
, tmp4
, tmp5
, tmp6
;
26187 tmp1
= gen_reg_rtx (DImode
);
26188 emit_insn (gen_popcntbdi2 (tmp1
, src
));
26190 tmp2
= gen_reg_rtx (DImode
);
26191 emit_insn (gen_lshrdi3 (tmp2
, tmp1
, GEN_INT (32)));
26192 tmp3
= gen_reg_rtx (DImode
);
26193 emit_insn (gen_xordi3 (tmp3
, tmp1
, tmp2
));
26195 tmp4
= gen_reg_rtx (DImode
);
26196 emit_insn (gen_lshrdi3 (tmp4
, tmp3
, GEN_INT (16)));
26197 tmp5
= gen_reg_rtx (DImode
);
26198 emit_insn (gen_xordi3 (tmp5
, tmp3
, tmp4
));
26200 tmp6
= gen_reg_rtx (DImode
);
26201 emit_insn (gen_lshrdi3 (tmp6
, tmp5
, GEN_INT (8)));
26202 emit_insn (gen_xordi3 (tmp
, tmp5
, tmp6
));
26205 rs6000_emit_popcount (tmp
, src
);
26206 emit_insn (gen_anddi3 (dst
, tmp
, const1_rtx
));
26210 /* Expand an Altivec constant permutation. Return true if we match
26211 an efficient implementation; false to fall back to VPERM. */
26214 altivec_expand_vec_perm_const (rtx operands
[4])
26216 struct altivec_perm_insn
{
26217 enum insn_code impl
;
26218 unsigned char perm
[16];
26220 static const struct altivec_perm_insn patterns
[] = {
26221 { CODE_FOR_altivec_vpkuhum
,
26222 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
26223 { CODE_FOR_altivec_vpkuwum
,
26224 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
26225 { CODE_FOR_altivec_vmrghb
,
26226 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
26227 { CODE_FOR_altivec_vmrghh
,
26228 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
26229 { CODE_FOR_altivec_vmrghw
,
26230 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
26231 { CODE_FOR_altivec_vmrglb
,
26232 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
26233 { CODE_FOR_altivec_vmrglh
,
26234 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
26235 { CODE_FOR_altivec_vmrglw
,
26236 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } }
26239 unsigned int i
, j
, elt
, which
;
26240 unsigned char perm
[16];
26241 rtx target
, op0
, op1
, sel
, x
;
26244 target
= operands
[0];
26249 /* Unpack the constant selector. */
26250 for (i
= which
= 0; i
< 16; ++i
)
26252 rtx e
= XVECEXP (sel
, 0, i
);
26253 elt
= INTVAL (e
) & 31;
26254 which
|= (elt
< 16 ? 1 : 2);
26258 /* Simplify the constant selector based on operands. */
26262 gcc_unreachable ();
26266 if (!rtx_equal_p (op0
, op1
))
26271 for (i
= 0; i
< 16; ++i
)
26283 /* Look for splat patterns. */
26288 for (i
= 0; i
< 16; ++i
)
26289 if (perm
[i
] != elt
)
26293 emit_insn (gen_altivec_vspltb (target
, op0
, GEN_INT (elt
)));
26299 for (i
= 0; i
< 16; i
+= 2)
26300 if (perm
[i
] != elt
|| perm
[i
+ 1] != elt
+ 1)
26304 x
= gen_reg_rtx (V8HImode
);
26305 emit_insn (gen_altivec_vsplth (x
, gen_lowpart (V8HImode
, op0
),
26306 GEN_INT (elt
/ 2)));
26307 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
26314 for (i
= 0; i
< 16; i
+= 4)
26316 || perm
[i
+ 1] != elt
+ 1
26317 || perm
[i
+ 2] != elt
+ 2
26318 || perm
[i
+ 3] != elt
+ 3)
26322 x
= gen_reg_rtx (V4SImode
);
26323 emit_insn (gen_altivec_vspltw (x
, gen_lowpart (V4SImode
, op0
),
26324 GEN_INT (elt
/ 4)));
26325 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
26331 /* Look for merge and pack patterns. */
26332 for (j
= 0; j
< ARRAY_SIZE (patterns
); ++j
)
26336 elt
= patterns
[j
].perm
[0];
26337 if (perm
[0] == elt
)
26339 else if (perm
[0] == elt
+ 16)
26343 for (i
= 1; i
< 16; ++i
)
26345 elt
= patterns
[j
].perm
[i
];
26347 elt
= (elt
>= 16 ? elt
- 16 : elt
+ 16);
26348 else if (one_vec
&& elt
>= 16)
26350 if (perm
[i
] != elt
)
26355 enum insn_code icode
= patterns
[j
].impl
;
26356 enum machine_mode omode
= insn_data
[icode
].operand
[0].mode
;
26357 enum machine_mode imode
= insn_data
[icode
].operand
[1].mode
;
26360 x
= op0
, op0
= op1
, op1
= x
;
26361 if (imode
!= V16QImode
)
26363 op0
= gen_lowpart (imode
, op0
);
26364 op1
= gen_lowpart (imode
, op1
);
26366 if (omode
== V16QImode
)
26369 x
= gen_reg_rtx (omode
);
26370 emit_insn (GEN_FCN (icode
) (x
, op0
, op1
));
26371 if (omode
!= V16QImode
)
26372 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
26380 /* Expand a Paired Single, VSX Permute Doubleword, or SPE constant permutation.
26381 Return true if we match an efficient implementation. */
26384 rs6000_expand_vec_perm_const_1 (rtx target
, rtx op0
, rtx op1
,
26385 unsigned char perm0
, unsigned char perm1
)
26389 /* If both selectors come from the same operand, fold to single op. */
26390 if ((perm0
& 2) == (perm1
& 2))
26397 /* If both operands are equal, fold to simpler permutation. */
26398 if (rtx_equal_p (op0
, op1
))
26401 perm1
= (perm1
& 1) + 2;
26403 /* If the first selector comes from the second operand, swap. */
26404 else if (perm0
& 2)
26410 x
= op0
, op0
= op1
, op1
= x
;
26412 /* If the second selector does not come from the second operand, fail. */
26413 else if ((perm1
& 2) == 0)
26417 if (target
!= NULL
)
26419 enum machine_mode vmode
, dmode
;
26422 vmode
= GET_MODE (target
);
26423 gcc_assert (GET_MODE_NUNITS (vmode
) == 2);
26424 dmode
= mode_for_vector (GET_MODE_INNER (vmode
), 4);
26426 x
= gen_rtx_VEC_CONCAT (dmode
, op0
, op1
);
26427 v
= gen_rtvec (2, GEN_INT (perm0
), GEN_INT (perm1
));
26428 x
= gen_rtx_VEC_SELECT (vmode
, x
, gen_rtx_PARALLEL (VOIDmode
, v
));
26429 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
26435 rs6000_expand_vec_perm_const (rtx operands
[4])
26437 rtx target
, op0
, op1
, sel
;
26438 unsigned char perm0
, perm1
;
26440 target
= operands
[0];
26445 /* Unpack the constant selector. */
26446 perm0
= INTVAL (XVECEXP (sel
, 0, 0)) & 3;
26447 perm1
= INTVAL (XVECEXP (sel
, 0, 1)) & 3;
26449 return rs6000_expand_vec_perm_const_1 (target
, op0
, op1
, perm0
, perm1
);
26452 /* Test whether a constant permutation is supported. */
26455 rs6000_vectorize_vec_perm_const_ok (enum machine_mode vmode
,
26456 const unsigned char *sel
)
26458 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
26459 if (TARGET_ALTIVEC
)
26462 /* Check for ps_merge* or evmerge* insns. */
26463 if ((TARGET_PAIRED_FLOAT
&& vmode
== V2SFmode
)
26464 || (TARGET_SPE
&& vmode
== V2SImode
))
26466 rtx op0
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 1);
26467 rtx op1
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 2);
26468 return rs6000_expand_vec_perm_const_1 (NULL
, op0
, op1
, sel
[0], sel
[1]);
26474 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave. */
26477 rs6000_do_expand_vec_perm (rtx target
, rtx op0
, rtx op1
,
26478 enum machine_mode vmode
, unsigned nelt
, rtx perm
[])
26480 enum machine_mode imode
;
26484 if (GET_MODE_CLASS (vmode
) != MODE_VECTOR_INT
)
26486 imode
= GET_MODE_INNER (vmode
);
26487 imode
= mode_for_size (GET_MODE_BITSIZE (imode
), MODE_INT
, 0);
26488 imode
= mode_for_vector (imode
, nelt
);
26491 x
= gen_rtx_CONST_VECTOR (imode
, gen_rtvec_v (nelt
, perm
));
26492 x
= expand_vec_perm (vmode
, op0
, op1
, x
, target
);
26494 emit_move_insn (target
, x
);
26497 /* Expand an extract even operation. */
26500 rs6000_expand_extract_even (rtx target
, rtx op0
, rtx op1
)
26502 enum machine_mode vmode
= GET_MODE (target
);
26503 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
26506 for (i
= 0; i
< nelt
; i
++)
26507 perm
[i
] = GEN_INT (i
* 2);
26509 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
26512 /* Expand a vector interleave operation. */
26515 rs6000_expand_interleave (rtx target
, rtx op0
, rtx op1
, bool highp
)
26517 enum machine_mode vmode
= GET_MODE (target
);
26518 unsigned i
, high
, nelt
= GET_MODE_NUNITS (vmode
);
26521 high
= (highp
== BYTES_BIG_ENDIAN
? 0 : nelt
/ 2);
26522 for (i
= 0; i
< nelt
/ 2; i
++)
26524 perm
[i
* 2] = GEN_INT (i
+ high
);
26525 perm
[i
* 2 + 1] = GEN_INT (i
+ nelt
+ high
);
26528 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
26531 /* Return an RTX representing where to find the function value of a
26532 function returning MODE. */
26534 rs6000_complex_function_value (enum machine_mode mode
)
26536 unsigned int regno
;
26538 enum machine_mode inner
= GET_MODE_INNER (mode
);
26539 unsigned int inner_bytes
= GET_MODE_SIZE (inner
);
26541 if (FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
26542 regno
= FP_ARG_RETURN
;
26545 regno
= GP_ARG_RETURN
;
26547 /* 32-bit is OK since it'll go in r3/r4. */
26548 if (TARGET_32BIT
&& inner_bytes
>= 4)
26549 return gen_rtx_REG (mode
, regno
);
26552 if (inner_bytes
>= 8)
26553 return gen_rtx_REG (mode
, regno
);
26555 r1
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
),
26557 r2
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
+ 1),
26558 GEN_INT (inner_bytes
));
26559 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
26562 /* Target hook for TARGET_FUNCTION_VALUE.
26564 On the SPE, both FPs and vectors are returned in r3.
26566 On RS/6000 an integer value is in r3 and a floating-point value is in
26567 fp1, unless -msoft-float. */
26570 rs6000_function_value (const_tree valtype
,
26571 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
26572 bool outgoing ATTRIBUTE_UNUSED
)
26574 enum machine_mode mode
;
26575 unsigned int regno
;
26577 /* Special handling for structs in darwin64. */
26579 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype
), valtype
))
26581 CUMULATIVE_ARGS valcum
;
26585 valcum
.fregno
= FP_ARG_MIN_REG
;
26586 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
26587 /* Do a trial code generation as if this were going to be passed as
26588 an argument; if any part goes in memory, we return NULL. */
26589 valret
= rs6000_darwin64_record_arg (&valcum
, valtype
, true, /* retval= */ true);
26592 /* Otherwise fall through to standard ABI rules. */
26595 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DImode
)
26597 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
26598 return gen_rtx_PARALLEL (DImode
,
26600 gen_rtx_EXPR_LIST (VOIDmode
,
26601 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
26603 gen_rtx_EXPR_LIST (VOIDmode
,
26604 gen_rtx_REG (SImode
,
26605 GP_ARG_RETURN
+ 1),
26608 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DCmode
)
26610 return gen_rtx_PARALLEL (DCmode
,
26612 gen_rtx_EXPR_LIST (VOIDmode
,
26613 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
26615 gen_rtx_EXPR_LIST (VOIDmode
,
26616 gen_rtx_REG (SImode
,
26617 GP_ARG_RETURN
+ 1),
26619 gen_rtx_EXPR_LIST (VOIDmode
,
26620 gen_rtx_REG (SImode
,
26621 GP_ARG_RETURN
+ 2),
26623 gen_rtx_EXPR_LIST (VOIDmode
,
26624 gen_rtx_REG (SImode
,
26625 GP_ARG_RETURN
+ 3),
26629 mode
= TYPE_MODE (valtype
);
26630 if ((INTEGRAL_TYPE_P (valtype
) && GET_MODE_BITSIZE (mode
) < BITS_PER_WORD
)
26631 || POINTER_TYPE_P (valtype
))
26632 mode
= TARGET_32BIT
? SImode
: DImode
;
26634 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
26635 /* _Decimal128 must use an even/odd register pair. */
26636 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
26637 else if (SCALAR_FLOAT_TYPE_P (valtype
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
26638 && ((TARGET_SINGLE_FLOAT
&& (mode
== SFmode
)) || TARGET_DOUBLE_FLOAT
))
26639 regno
= FP_ARG_RETURN
;
26640 else if (TREE_CODE (valtype
) == COMPLEX_TYPE
26641 && targetm
.calls
.split_complex_arg
)
26642 return rs6000_complex_function_value (mode
);
26643 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
26644 return register is used in both cases, and we won't see V2DImode/V2DFmode
26645 for pure altivec, combine the two cases. */
26646 else if (TREE_CODE (valtype
) == VECTOR_TYPE
26647 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
26648 && ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
26649 regno
= ALTIVEC_ARG_RETURN
;
26650 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
26651 && (mode
== DFmode
|| mode
== DCmode
26652 || mode
== TFmode
|| mode
== TCmode
))
26653 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
26655 regno
= GP_ARG_RETURN
;
26657 return gen_rtx_REG (mode
, regno
);
26660 /* Define how to find the value returned by a library function
26661 assuming the value has mode MODE. */
26663 rs6000_libcall_value (enum machine_mode mode
)
26665 unsigned int regno
;
26667 if (TARGET_32BIT
&& TARGET_POWERPC64
&& mode
== DImode
)
26669 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
26670 return gen_rtx_PARALLEL (DImode
,
26672 gen_rtx_EXPR_LIST (VOIDmode
,
26673 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
26675 gen_rtx_EXPR_LIST (VOIDmode
,
26676 gen_rtx_REG (SImode
,
26677 GP_ARG_RETURN
+ 1),
26681 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
26682 /* _Decimal128 must use an even/odd register pair. */
26683 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
26684 else if (SCALAR_FLOAT_MODE_P (mode
)
26685 && TARGET_HARD_FLOAT
&& TARGET_FPRS
26686 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
) || TARGET_DOUBLE_FLOAT
))
26687 regno
= FP_ARG_RETURN
;
26688 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
26689 return register is used in both cases, and we won't see V2DImode/V2DFmode
26690 for pure altivec, combine the two cases. */
26691 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
26692 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
)
26693 regno
= ALTIVEC_ARG_RETURN
;
26694 else if (COMPLEX_MODE_P (mode
) && targetm
.calls
.split_complex_arg
)
26695 return rs6000_complex_function_value (mode
);
26696 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
26697 && (mode
== DFmode
|| mode
== DCmode
26698 || mode
== TFmode
|| mode
== TCmode
))
26699 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
26701 regno
= GP_ARG_RETURN
;
26703 return gen_rtx_REG (mode
, regno
);
26707 /* Given FROM and TO register numbers, say whether this elimination is allowed.
26708 Frame pointer elimination is automatically handled.
26710 For the RS/6000, if frame pointer elimination is being done, we would like
26711 to convert ap into fp, not sp.
26713 We need r30 if -mminimal-toc was specified, and there are constant pool
26717 rs6000_can_eliminate (const int from
, const int to
)
26719 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
26720 ? ! frame_pointer_needed
26721 : from
== RS6000_PIC_OFFSET_TABLE_REGNUM
26722 ? ! TARGET_MINIMAL_TOC
|| TARGET_NO_TOC
|| get_pool_size () == 0
26726 /* Define the offset between two registers, FROM to be eliminated and its
26727 replacement TO, at the start of a routine. */
26729 rs6000_initial_elimination_offset (int from
, int to
)
26731 rs6000_stack_t
*info
= rs6000_stack_info ();
26732 HOST_WIDE_INT offset
;
26734 if (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
26735 offset
= info
->push_p
? 0 : -info
->total_size
;
26736 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
26738 offset
= info
->push_p
? 0 : -info
->total_size
;
26739 if (FRAME_GROWS_DOWNWARD
)
26740 offset
+= info
->fixed_size
+ info
->vars_size
+ info
->parm_size
;
26742 else if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
26743 offset
= FRAME_GROWS_DOWNWARD
26744 ? info
->fixed_size
+ info
->vars_size
+ info
->parm_size
26746 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
26747 offset
= info
->total_size
;
26748 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
26749 offset
= info
->push_p
? info
->total_size
: 0;
26750 else if (from
== RS6000_PIC_OFFSET_TABLE_REGNUM
)
26753 gcc_unreachable ();
26759 rs6000_dwarf_register_span (rtx reg
)
26763 unsigned regno
= REGNO (reg
);
26764 enum machine_mode mode
= GET_MODE (reg
);
26768 && (SPE_VECTOR_MODE (GET_MODE (reg
))
26769 || (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
)
26770 && mode
!= SFmode
&& mode
!= SDmode
&& mode
!= SCmode
)))
26775 regno
= REGNO (reg
);
26777 /* The duality of the SPE register size wreaks all kinds of havoc.
26778 This is a way of distinguishing r0 in 32-bits from r0 in
26780 words
= (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
26781 gcc_assert (words
<= 4);
26782 for (i
= 0; i
< words
; i
++, regno
++)
26784 if (BYTES_BIG_ENDIAN
)
26786 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
+ 1200);
26787 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
);
26791 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
);
26792 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
+ 1200);
26796 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (words
* 2, parts
));
26799 /* Fill in sizes for SPE register high parts in table used by unwinder. */
26802 rs6000_init_dwarf_reg_sizes_extra (tree address
)
26807 enum machine_mode mode
= TYPE_MODE (char_type_node
);
26808 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
26809 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
26810 rtx value
= gen_int_mode (4, mode
);
26812 for (i
= 1201; i
< 1232; i
++)
26814 int column
= DWARF_REG_TO_UNWIND_COLUMN (i
);
26815 HOST_WIDE_INT offset
26816 = DWARF_FRAME_REGNUM (column
) * GET_MODE_SIZE (mode
);
26818 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
26823 /* Map internal gcc register numbers to DWARF2 register numbers. */
26826 rs6000_dbx_register_number (unsigned int regno
)
26828 if (regno
<= 63 || write_symbols
!= DWARF2_DEBUG
)
26830 if (regno
== MQ_REGNO
)
26832 if (regno
== LR_REGNO
)
26834 if (regno
== CTR_REGNO
)
26836 if (CR_REGNO_P (regno
))
26837 return regno
- CR0_REGNO
+ 86;
26838 if (regno
== CA_REGNO
)
26839 return 101; /* XER */
26840 if (ALTIVEC_REGNO_P (regno
))
26841 return regno
- FIRST_ALTIVEC_REGNO
+ 1124;
26842 if (regno
== VRSAVE_REGNO
)
26844 if (regno
== VSCR_REGNO
)
26846 if (regno
== SPE_ACC_REGNO
)
26848 if (regno
== SPEFSCR_REGNO
)
26850 /* SPE high reg number. We get these values of regno from
26851 rs6000_dwarf_register_span. */
26852 gcc_assert (regno
>= 1200 && regno
< 1232);
26856 /* target hook eh_return_filter_mode */
26857 static enum machine_mode
26858 rs6000_eh_return_filter_mode (void)
26860 return TARGET_32BIT
? SImode
: word_mode
;
26863 /* Target hook for scalar_mode_supported_p. */
26865 rs6000_scalar_mode_supported_p (enum machine_mode mode
)
26867 if (DECIMAL_FLOAT_MODE_P (mode
))
26868 return default_decimal_float_supported_p ();
26870 return default_scalar_mode_supported_p (mode
);
26873 /* Target hook for vector_mode_supported_p. */
26875 rs6000_vector_mode_supported_p (enum machine_mode mode
)
26878 if (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (mode
))
26881 if (TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
26884 else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
26891 /* Target hook for invalid_arg_for_unprototyped_fn. */
26892 static const char *
26893 invalid_arg_for_unprototyped_fn (const_tree typelist
, const_tree funcdecl
, const_tree val
)
26895 return (!rs6000_darwin64_abi
26897 && TREE_CODE (TREE_TYPE (val
)) == VECTOR_TYPE
26898 && (funcdecl
== NULL_TREE
26899 || (TREE_CODE (funcdecl
) == FUNCTION_DECL
26900 && DECL_BUILT_IN_CLASS (funcdecl
) != BUILT_IN_MD
)))
26901 ? N_("AltiVec argument passed to unprototyped function")
26905 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
26906 setup by using __stack_chk_fail_local hidden function instead of
26907 calling __stack_chk_fail directly. Otherwise it is better to call
26908 __stack_chk_fail directly. */
26910 static tree ATTRIBUTE_UNUSED
26911 rs6000_stack_protect_fail (void)
26913 return (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
26914 ? default_hidden_stack_protect_fail ()
26915 : default_external_stack_protect_fail ();
26919 rs6000_final_prescan_insn (rtx insn
, rtx
*operand ATTRIBUTE_UNUSED
,
26920 int num_operands ATTRIBUTE_UNUSED
)
26922 if (rs6000_warn_cell_microcode
)
26925 int insn_code_number
= recog_memoized (insn
);
26926 location_t location
= locator_location (INSN_LOCATOR (insn
));
26928 /* Punt on insns we cannot recognize. */
26929 if (insn_code_number
< 0)
26932 temp
= get_insn_template (insn_code_number
, insn
);
26934 if (get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
)
26935 warning_at (location
, OPT_mwarn_cell_microcode
,
26936 "emitting microcode insn %s\t[%s] #%d",
26937 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
26938 else if (get_attr_cell_micro (insn
) == CELL_MICRO_CONDITIONAL
)
26939 warning_at (location
, OPT_mwarn_cell_microcode
,
26940 "emitting conditional microcode insn %s\t[%s] #%d",
26941 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
26946 /* Mask options that we want to support inside of attribute((target)) and
26947 #pragma GCC target operations. Note, we do not include things like
26948 64/32-bit, endianess, hard/soft floating point, etc. that would have
26949 different calling sequences. */
26951 struct rs6000_opt_mask
{
26952 const char *name
; /* option name */
26953 int mask
; /* mask to set */
26954 bool invert
; /* invert sense of mask */
26955 bool valid_target
; /* option is a target option */
26958 static struct rs6000_opt_mask
const rs6000_opt_masks
[] =
26960 { "altivec", MASK_ALTIVEC
, false, true },
26961 { "cmpb", MASK_CMPB
, false, true },
26962 { "dlmzb", MASK_DLMZB
, false, true },
26963 { "fprnd", MASK_FPRND
, false, true },
26964 { "hard-dfp", MASK_DFP
, false, true },
26965 { "isel", MASK_ISEL
, false, true },
26966 { "mfcrf", MASK_MFCRF
, false, true },
26967 { "mfpgpr", MASK_MFPGPR
, false, true },
26968 { "mulhw", MASK_MULHW
, false, true },
26969 { "multiple", MASK_MULTIPLE
, false, true },
26970 { "update", MASK_NO_UPDATE
, true , true },
26971 { "popcntb", MASK_POPCNTB
, false, true },
26972 { "popcntd", MASK_POPCNTD
, false, true },
26973 { "powerpc-gfxopt", MASK_PPC_GFXOPT
, false, true },
26974 { "powerpc-gpopt", MASK_PPC_GPOPT
, false, true },
26975 { "recip-precision", MASK_RECIP_PRECISION
, false, true },
26976 { "string", MASK_STRING
, false, true },
26977 { "vsx", MASK_VSX
, false, true },
26980 { "aix64", MASK_64BIT
, false, false },
26981 { "aix32", MASK_64BIT
, true, false },
26983 { "64", MASK_64BIT
, false, false },
26984 { "32", MASK_64BIT
, true, false },
26988 { "eabi", MASK_EABI
, false, false },
26990 #ifdef MASK_LITTLE_ENDIAN
26991 { "little", MASK_LITTLE_ENDIAN
, false, false },
26992 { "big", MASK_LITTLE_ENDIAN
, true, false },
26994 #ifdef MASK_RELOCATABLE
26995 { "relocatable", MASK_RELOCATABLE
, false, false },
26997 #ifdef MASK_STRICT_ALIGN
26998 { "strict-align", MASK_STRICT_ALIGN
, false, false },
27000 { "power", MASK_POWER
, false, false },
27001 { "power2", MASK_POWER2
, false, false },
27002 { "powerpc", MASK_POWERPC
, false, false },
27003 { "soft-float", MASK_SOFT_FLOAT
, false, false },
27004 { "string", MASK_STRING
, false, false },
27007 /* Builtin mask mapping for printing the flags. */
27008 static struct rs6000_opt_mask
const rs6000_builtin_mask_names
[] =
27010 { "altivec", RS6000_BTM_ALTIVEC
, false, false },
27011 { "vsx", RS6000_BTM_VSX
, false, false },
27012 { "spe", RS6000_BTM_SPE
, false, false },
27013 { "paired", RS6000_BTM_PAIRED
, false, false },
27014 { "fre", RS6000_BTM_FRE
, false, false },
27015 { "fres", RS6000_BTM_FRES
, false, false },
27016 { "frsqrte", RS6000_BTM_FRSQRTE
, false, false },
27017 { "frsqrtes", RS6000_BTM_FRSQRTES
, false, false },
27018 { "popcntd", RS6000_BTM_POPCNTD
, false, false },
27019 { "powerpc", RS6000_BTM_POWERPC
, false, false },
27020 { "cell", RS6000_BTM_CELL
, false, false },
27023 /* Option variables that we want to support inside attribute((target)) and
27024 #pragma GCC target operations. */
27026 struct rs6000_opt_var
{
27027 const char *name
; /* option name */
27028 size_t global_offset
; /* offset of the option in global_options. */
27029 size_t target_offset
; /* offset of the option in target optiosn. */
27032 static struct rs6000_opt_var
const rs6000_opt_vars
[] =
27035 offsetof (struct gcc_options
, x_TARGET_FRIZ
),
27036 offsetof (struct cl_target_option
, x_TARGET_FRIZ
), },
27037 { "avoid-indexed-addresses",
27038 offsetof (struct gcc_options
, x_TARGET_AVOID_XFORM
),
27039 offsetof (struct cl_target_option
, x_TARGET_AVOID_XFORM
) },
27041 offsetof (struct gcc_options
, x_rs6000_paired_float
),
27042 offsetof (struct cl_target_option
, x_rs6000_paired_float
), },
27044 offsetof (struct gcc_options
, x_rs6000_default_long_calls
),
27045 offsetof (struct cl_target_option
, x_rs6000_default_long_calls
), },
27048 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
27049 parsing. Return true if there were no errors. */
27052 rs6000_inner_target_options (tree args
, bool attr_p
)
27056 if (args
== NULL_TREE
)
27059 else if (TREE_CODE (args
) == STRING_CST
)
27061 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
27064 while ((q
= strtok (p
, ",")) != NULL
)
27066 bool error_p
= false;
27067 bool not_valid_p
= false;
27068 const char *cpu_opt
= NULL
;
27071 if (strncmp (q
, "cpu=", 4) == 0)
27073 int cpu_index
= rs6000_cpu_name_lookup (q
+4);
27074 if (cpu_index
>= 0)
27075 rs6000_cpu_index
= cpu_index
;
27082 else if (strncmp (q
, "tune=", 5) == 0)
27084 int tune_index
= rs6000_cpu_name_lookup (q
+5);
27085 if (tune_index
>= 0)
27086 rs6000_tune_index
= tune_index
;
27096 bool invert
= false;
27100 if (strncmp (r
, "no-", 3) == 0)
27106 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_masks
); i
++)
27107 if (strcmp (r
, rs6000_opt_masks
[i
].name
) == 0)
27109 int mask
= rs6000_opt_masks
[i
].mask
;
27111 if (!rs6000_opt_masks
[i
].valid_target
)
27112 not_valid_p
= true;
27116 target_flags_explicit
|= mask
;
27118 /* VSX needs altivec, so -mvsx automagically sets
27120 if (mask
== MASK_VSX
&& !invert
)
27121 mask
|= MASK_ALTIVEC
;
27123 if (rs6000_opt_masks
[i
].invert
)
27127 target_flags
&= ~mask
;
27129 target_flags
|= mask
;
27134 if (error_p
&& !not_valid_p
)
27136 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_vars
); i
++)
27137 if (strcmp (r
, rs6000_opt_vars
[i
].name
) == 0)
27139 size_t j
= rs6000_opt_vars
[i
].global_offset
;
27140 *((int *) ((char *)&global_options
+ j
)) = !invert
;
27149 const char *eprefix
, *esuffix
;
27154 eprefix
= "__attribute__((__target__(";
27159 eprefix
= "#pragma GCC target ";
27164 error ("invalid cpu \"%s\" for %s\"%s\"%s", cpu_opt
, eprefix
,
27166 else if (not_valid_p
)
27167 error ("%s\"%s\"%s is not allowed", eprefix
, q
, esuffix
);
27169 error ("%s\"%s\"%s is invalid", eprefix
, q
, esuffix
);
27174 else if (TREE_CODE (args
) == TREE_LIST
)
27178 tree value
= TREE_VALUE (args
);
27181 bool ret2
= rs6000_inner_target_options (value
, attr_p
);
27185 args
= TREE_CHAIN (args
);
27187 while (args
!= NULL_TREE
);
27191 gcc_unreachable ();
27196 /* Print out the target options as a list for -mdebug=target. */
27199 rs6000_debug_target_options (tree args
, const char *prefix
)
27201 if (args
== NULL_TREE
)
27202 fprintf (stderr
, "%s<NULL>", prefix
);
27204 else if (TREE_CODE (args
) == STRING_CST
)
27206 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
27209 while ((q
= strtok (p
, ",")) != NULL
)
27212 fprintf (stderr
, "%s\"%s\"", prefix
, q
);
27217 else if (TREE_CODE (args
) == TREE_LIST
)
27221 tree value
= TREE_VALUE (args
);
27224 rs6000_debug_target_options (value
, prefix
);
27227 args
= TREE_CHAIN (args
);
27229 while (args
!= NULL_TREE
);
27233 gcc_unreachable ();
27239 /* Hook to validate attribute((target("..."))). */
27242 rs6000_valid_attribute_p (tree fndecl
,
27243 tree
ARG_UNUSED (name
),
27247 struct cl_target_option cur_target
;
27249 tree old_optimize
= build_optimization_node ();
27250 tree new_target
, new_optimize
;
27251 tree func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
27253 gcc_assert ((fndecl
!= NULL_TREE
) && (args
!= NULL_TREE
));
27255 if (TARGET_DEBUG_TARGET
)
27257 tree tname
= DECL_NAME (fndecl
);
27258 fprintf (stderr
, "\n==================== rs6000_valid_attribute_p:\n");
27260 fprintf (stderr
, "function: %.*s\n",
27261 (int) IDENTIFIER_LENGTH (tname
),
27262 IDENTIFIER_POINTER (tname
));
27264 fprintf (stderr
, "function: unknown\n");
27266 fprintf (stderr
, "args:");
27267 rs6000_debug_target_options (args
, " ");
27268 fprintf (stderr
, "\n");
27271 fprintf (stderr
, "flags: 0x%x\n", flags
);
27273 fprintf (stderr
, "--------------------\n");
27276 old_optimize
= build_optimization_node ();
27277 func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
27279 /* If the function changed the optimization levels as well as setting target
27280 options, start with the optimizations specified. */
27281 if (func_optimize
&& func_optimize
!= old_optimize
)
27282 cl_optimization_restore (&global_options
,
27283 TREE_OPTIMIZATION (func_optimize
));
27285 /* The target attributes may also change some optimization flags, so update
27286 the optimization options if necessary. */
27287 cl_target_option_save (&cur_target
, &global_options
);
27288 rs6000_cpu_index
= rs6000_tune_index
= -1;
27289 ret
= rs6000_inner_target_options (args
, true);
27291 /* Set up any additional state. */
27294 ret
= rs6000_option_override_internal (false);
27295 new_target
= build_target_option_node ();
27300 new_optimize
= build_optimization_node ();
27307 DECL_FUNCTION_SPECIFIC_TARGET (fndecl
) = new_target
;
27309 if (old_optimize
!= new_optimize
)
27310 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
) = new_optimize
;
27313 cl_target_option_restore (&global_options
, &cur_target
);
27315 if (old_optimize
!= new_optimize
)
27316 cl_optimization_restore (&global_options
,
27317 TREE_OPTIMIZATION (old_optimize
));
27323 /* Hook to validate the current #pragma GCC target and set the state, and
27324 update the macros based on what was changed. If ARGS is NULL, then
27325 POP_TARGET is used to reset the options. */
27328 rs6000_pragma_target_parse (tree args
, tree pop_target
)
27330 tree prev_tree
= build_target_option_node ();
27332 struct cl_target_option
*prev_opt
, *cur_opt
;
27333 unsigned prev_bumask
, cur_bumask
, diff_bumask
;
27334 int prev_flags
, cur_flags
, diff_flags
;
27336 if (TARGET_DEBUG_TARGET
)
27338 fprintf (stderr
, "\n==================== rs6000_pragma_target_parse\n");
27339 fprintf (stderr
, "args:");
27340 rs6000_debug_target_options (args
, " ");
27341 fprintf (stderr
, "\n");
27345 fprintf (stderr
, "pop_target:\n");
27346 debug_tree (pop_target
);
27349 fprintf (stderr
, "pop_target: <NULL>\n");
27351 fprintf (stderr
, "--------------------\n");
27356 cur_tree
= ((pop_target
)
27358 : target_option_default_node
);
27359 cl_target_option_restore (&global_options
,
27360 TREE_TARGET_OPTION (cur_tree
));
27364 rs6000_cpu_index
= rs6000_tune_index
= -1;
27365 if (!rs6000_inner_target_options (args
, false)
27366 || !rs6000_option_override_internal (false)
27367 || (cur_tree
= build_target_option_node ()) == NULL_TREE
)
27369 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
27370 fprintf (stderr
, "invalid pragma\n");
27376 target_option_current_node
= cur_tree
;
27378 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
27379 change the macros that are defined. */
27380 if (rs6000_target_modify_macros_ptr
)
27382 prev_opt
= TREE_TARGET_OPTION (prev_tree
);
27383 prev_bumask
= prev_opt
->x_rs6000_builtin_mask
;
27384 prev_flags
= prev_opt
->x_target_flags
;
27386 cur_opt
= TREE_TARGET_OPTION (cur_tree
);
27387 cur_flags
= cur_opt
->x_target_flags
;
27388 cur_bumask
= cur_opt
->x_rs6000_builtin_mask
;
27390 diff_bumask
= (prev_bumask
^ cur_bumask
);
27391 diff_flags
= (prev_flags
^ cur_flags
);
27393 if ((diff_flags
!= 0) || (diff_bumask
!= 0))
27395 /* Delete old macros. */
27396 rs6000_target_modify_macros_ptr (false,
27397 prev_flags
& diff_flags
,
27398 prev_bumask
& diff_bumask
);
27400 /* Define new macros. */
27401 rs6000_target_modify_macros_ptr (true,
27402 cur_flags
& diff_flags
,
27403 cur_bumask
& diff_bumask
);
27411 /* Remember the last target of rs6000_set_current_function. */
27412 static GTY(()) tree rs6000_previous_fndecl
;
27414 /* Establish appropriate back-end context for processing the function
27415 FNDECL. The argument might be NULL to indicate processing at top
27416 level, outside of any function scope. */
27418 rs6000_set_current_function (tree fndecl
)
27420 tree old_tree
= (rs6000_previous_fndecl
27421 ? DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl
)
27424 tree new_tree
= (fndecl
27425 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl
)
27428 if (TARGET_DEBUG_TARGET
)
27430 bool print_final
= false;
27431 fprintf (stderr
, "\n==================== rs6000_set_current_function");
27434 fprintf (stderr
, ", fndecl %s (%p)",
27435 (DECL_NAME (fndecl
)
27436 ? IDENTIFIER_POINTER (DECL_NAME (fndecl
))
27437 : "<unknown>"), (void *)fndecl
);
27439 if (rs6000_previous_fndecl
)
27440 fprintf (stderr
, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl
);
27442 fprintf (stderr
, "\n");
27445 fprintf (stderr
, "\nnew fndecl target specific options:\n");
27446 debug_tree (new_tree
);
27447 print_final
= true;
27452 fprintf (stderr
, "\nold fndecl target specific options:\n");
27453 debug_tree (old_tree
);
27454 print_final
= true;
27458 fprintf (stderr
, "--------------------\n");
27461 /* Only change the context if the function changes. This hook is called
27462 several times in the course of compiling a function, and we don't want to
27463 slow things down too much or call target_reinit when it isn't safe. */
27464 if (fndecl
&& fndecl
!= rs6000_previous_fndecl
)
27466 rs6000_previous_fndecl
= fndecl
;
27467 if (old_tree
== new_tree
)
27472 cl_target_option_restore (&global_options
,
27473 TREE_TARGET_OPTION (new_tree
));
27479 struct cl_target_option
*def
27480 = TREE_TARGET_OPTION (target_option_current_node
);
27482 cl_target_option_restore (&global_options
, def
);
27489 /* Save the current options */
27492 rs6000_function_specific_save (struct cl_target_option
*ptr
)
27494 ptr
->rs6000_target_flags_explicit
= target_flags_explicit
;
27497 /* Restore the current options */
27500 rs6000_function_specific_restore (struct cl_target_option
*ptr
)
27502 target_flags_explicit
= ptr
->rs6000_target_flags_explicit
;
27503 (void) rs6000_option_override_internal (false);
27506 /* Print the current options */
27509 rs6000_function_specific_print (FILE *file
, int indent
,
27510 struct cl_target_option
*ptr
)
27513 int flags
= ptr
->x_target_flags
;
27514 unsigned bu_mask
= ptr
->x_rs6000_builtin_mask
;
27516 /* Print the various mask options. */
27517 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_masks
); i
++)
27518 if ((flags
& rs6000_opt_masks
[i
].mask
) != 0)
27520 flags
&= ~ rs6000_opt_masks
[i
].mask
;
27521 fprintf (file
, "%*s-m%s%s\n", indent
, "",
27522 rs6000_opt_masks
[i
].invert
? "no-" : "",
27523 rs6000_opt_masks
[i
].name
);
27526 /* Print the various options that are variables. */
27527 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_vars
); i
++)
27529 size_t j
= rs6000_opt_vars
[i
].target_offset
;
27530 if (((signed char *) ptr
)[j
])
27531 fprintf (file
, "%*s-m%s\n", indent
, "",
27532 rs6000_opt_vars
[i
].name
);
27535 /* Print the various builtin flags. */
27536 fprintf (file
, "%*sbuiltin mask = 0x%x\n", indent
, "", bu_mask
);
27537 for (i
= 0; i
< ARRAY_SIZE (rs6000_builtin_mask_names
); i
++)
27538 if ((bu_mask
& rs6000_builtin_mask_names
[i
].mask
) != 0)
27540 fprintf (file
, "%*s%s builtins supported\n", indent
, "",
27541 rs6000_builtin_mask_names
[i
].name
);
27546 /* Hook to determine if one function can safely inline another. */
27549 rs6000_can_inline_p (tree caller
, tree callee
)
27552 tree caller_tree
= DECL_FUNCTION_SPECIFIC_TARGET (caller
);
27553 tree callee_tree
= DECL_FUNCTION_SPECIFIC_TARGET (callee
);
27555 /* If callee has no option attributes, then it is ok to inline. */
27559 /* If caller has no option attributes, but callee does then it is not ok to
27561 else if (!caller_tree
)
27566 struct cl_target_option
*caller_opts
= TREE_TARGET_OPTION (caller_tree
);
27567 struct cl_target_option
*callee_opts
= TREE_TARGET_OPTION (callee_tree
);
27569 /* Callee's options should a subset of the caller's, i.e. a vsx function
27570 can inline an altivec function but a non-vsx function can't inline a
27572 if ((caller_opts
->x_target_flags
& callee_opts
->x_target_flags
)
27573 == callee_opts
->x_target_flags
)
27577 if (TARGET_DEBUG_TARGET
)
27578 fprintf (stderr
, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
27579 (DECL_NAME (caller
)
27580 ? IDENTIFIER_POINTER (DECL_NAME (caller
))
27582 (DECL_NAME (callee
)
27583 ? IDENTIFIER_POINTER (DECL_NAME (callee
))
27585 (ret
? "can" : "cannot"));
27590 /* Allocate a stack temp and fixup the address so it meets the particular
27591 memory requirements (either offetable or REG+REG addressing). */
27594 rs6000_allocate_stack_temp (enum machine_mode mode
,
27595 bool offsettable_p
,
27598 rtx stack
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
), 0);
27599 rtx addr
= XEXP (stack
, 0);
27600 int strict_p
= (reload_in_progress
|| reload_completed
);
27602 if (!legitimate_indirect_address_p (addr
, strict_p
))
27605 && !rs6000_legitimate_offset_address_p (mode
, addr
, strict_p
))
27606 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
27608 else if (reg_reg_p
&& !legitimate_indexed_address_p (addr
, strict_p
))
27609 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
27615 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
27616 to such a form to deal with memory reference instructions like STFIWX that
27617 only take reg+reg addressing. */
27620 rs6000_address_for_fpconvert (rtx x
)
27622 int strict_p
= (reload_in_progress
|| reload_completed
);
27625 gcc_assert (MEM_P (x
));
27626 addr
= XEXP (x
, 0);
27627 if (! legitimate_indirect_address_p (addr
, strict_p
)
27628 && ! legitimate_indexed_address_p (addr
, strict_p
))
27630 if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
27632 rtx reg
= XEXP (addr
, 0);
27633 HOST_WIDE_INT size
= GET_MODE_SIZE (GET_MODE (x
));
27634 rtx size_rtx
= GEN_INT ((GET_CODE (addr
) == PRE_DEC
) ? -size
: size
);
27635 gcc_assert (REG_P (reg
));
27636 emit_insn (gen_add3_insn (reg
, reg
, size_rtx
));
27639 else if (GET_CODE (addr
) == PRE_MODIFY
)
27641 rtx reg
= XEXP (addr
, 0);
27642 rtx expr
= XEXP (addr
, 1);
27643 gcc_assert (REG_P (reg
));
27644 gcc_assert (GET_CODE (expr
) == PLUS
);
27645 emit_insn (gen_add3_insn (reg
, XEXP (expr
, 0), XEXP (expr
, 1)));
27649 x
= replace_equiv_address (x
, copy_addr_to_reg (addr
));
27655 /* Given a memory reference, if it is not in the form for altivec memory
27656 reference instructions (i.e. reg or reg+reg addressing with AND of -16),
27657 convert to the altivec format. */
27660 rs6000_address_for_altivec (rtx x
)
27662 gcc_assert (MEM_P (x
));
27663 if (!altivec_indexed_or_indirect_operand (x
, GET_MODE (x
)))
27665 rtx addr
= XEXP (x
, 0);
27666 int strict_p
= (reload_in_progress
|| reload_completed
);
27668 if (!legitimate_indexed_address_p (addr
, strict_p
)
27669 && !legitimate_indirect_address_p (addr
, strict_p
))
27670 addr
= copy_to_mode_reg (Pmode
, addr
);
27672 addr
= gen_rtx_AND (Pmode
, addr
, GEN_INT (-16));
27673 x
= change_address (x
, GET_MODE (x
), addr
);
27679 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
27681 On the RS/6000, all integer constants are acceptable, most won't be valid
27682 for particular insns, though. Only easy FP constants are acceptable. */
27685 rs6000_legitimate_constant_p (enum machine_mode mode
, rtx x
)
27687 if (rs6000_tls_referenced_p (x
))
27690 return ((GET_CODE (x
) != CONST_DOUBLE
&& GET_CODE (x
) != CONST_VECTOR
)
27691 || GET_MODE (x
) == VOIDmode
27692 || (TARGET_POWERPC64
&& mode
== DImode
)
27693 || easy_fp_constant (x
, mode
)
27694 || easy_vector_constant (x
, mode
));
27698 /* A function pointer under AIX is a pointer to a data area whose first word
27699 contains the actual address of the function, whose second word contains a
27700 pointer to its TOC, and whose third word contains a value to place in the
27701 static chain register (r11). Note that if we load the static chain, our
27702 "trampoline" need not have any executable code. */
27705 rs6000_call_indirect_aix (rtx value
, rtx func_desc
, rtx flag
)
27711 rtx stack_toc_offset
;
27713 rtx func_toc_offset
;
27715 rtx func_sc_offset
;
27718 rtx (*call_func
) (rtx
, rtx
, rtx
, rtx
);
27719 rtx (*call_value_func
) (rtx
, rtx
, rtx
, rtx
, rtx
);
27721 stack_ptr
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
27722 toc_reg
= gen_rtx_REG (Pmode
, TOC_REGNUM
);
27724 /* Load up address of the actual function. */
27725 func_desc
= force_reg (Pmode
, func_desc
);
27726 func_addr
= gen_reg_rtx (Pmode
);
27727 emit_move_insn (func_addr
, gen_rtx_MEM (Pmode
, func_desc
));
27732 stack_toc_offset
= GEN_INT (TOC_SAVE_OFFSET_32BIT
);
27733 func_toc_offset
= GEN_INT (AIX_FUNC_DESC_TOC_32BIT
);
27734 func_sc_offset
= GEN_INT (AIX_FUNC_DESC_SC_32BIT
);
27735 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
27737 call_func
= gen_call_indirect_aix32bit
;
27738 call_value_func
= gen_call_value_indirect_aix32bit
;
27742 call_func
= gen_call_indirect_aix32bit_nor11
;
27743 call_value_func
= gen_call_value_indirect_aix32bit_nor11
;
27748 stack_toc_offset
= GEN_INT (TOC_SAVE_OFFSET_64BIT
);
27749 func_toc_offset
= GEN_INT (AIX_FUNC_DESC_TOC_64BIT
);
27750 func_sc_offset
= GEN_INT (AIX_FUNC_DESC_SC_64BIT
);
27751 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
27753 call_func
= gen_call_indirect_aix64bit
;
27754 call_value_func
= gen_call_value_indirect_aix64bit
;
27758 call_func
= gen_call_indirect_aix64bit_nor11
;
27759 call_value_func
= gen_call_value_indirect_aix64bit_nor11
;
27763 /* Reserved spot to store the TOC. */
27764 stack_toc_mem
= gen_frame_mem (Pmode
,
27765 gen_rtx_PLUS (Pmode
,
27767 stack_toc_offset
));
27770 gcc_assert (cfun
->machine
);
27772 /* Can we optimize saving the TOC in the prologue or do we need to do it at
27774 if (TARGET_SAVE_TOC_INDIRECT
&& !cfun
->calls_alloca
)
27775 cfun
->machine
->save_toc_in_prologue
= true;
27779 MEM_VOLATILE_P (stack_toc_mem
) = 1;
27780 emit_move_insn (stack_toc_mem
, toc_reg
);
27783 /* Calculate the address to load the TOC of the called function. We don't
27784 actually load this until the split after reload. */
27785 func_toc_mem
= gen_rtx_MEM (Pmode
,
27786 gen_rtx_PLUS (Pmode
,
27790 /* If we have a static chain, load it up. */
27791 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
27793 func_sc_mem
= gen_rtx_MEM (Pmode
,
27794 gen_rtx_PLUS (Pmode
,
27798 sc_reg
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
27799 emit_move_insn (sc_reg
, func_sc_mem
);
27802 /* Create the call. */
27804 insn
= call_value_func (value
, func_addr
, flag
, func_toc_mem
,
27807 insn
= call_func (func_addr
, flag
, func_toc_mem
, stack_toc_mem
);
27809 emit_call_insn (insn
);
27812 /* Return whether we need to always update the saved TOC pointer when we update
27813 the stack pointer. */
27816 rs6000_save_toc_in_prologue_p (void)
27818 return (cfun
&& cfun
->machine
&& cfun
->machine
->save_toc_in_prologue
);
27821 #ifdef HAVE_GAS_HIDDEN
27822 # define USE_HIDDEN_LINKONCE 1
27824 # define USE_HIDDEN_LINKONCE 0
27827 /* Fills in the label name that should be used for a 476 link stack thunk. */
27830 get_ppc476_thunk_name (char name
[32])
27832 gcc_assert (TARGET_LINK_STACK
);
27834 if (USE_HIDDEN_LINKONCE
)
27835 sprintf (name
, "__ppc476.get_thunk");
27837 ASM_GENERATE_INTERNAL_LABEL (name
, "LPPC476_", 0);
27840 /* This function emits the simple thunk routine that is used to preserve
27841 the link stack on the 476 cpu. */
27844 rs6000_code_end (void)
27849 if (!TARGET_LINK_STACK
)
27852 get_ppc476_thunk_name (name
);
27854 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
, get_identifier (name
),
27855 build_function_type_list (void_type_node
, NULL_TREE
));
27856 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
27857 NULL_TREE
, void_type_node
);
27858 TREE_PUBLIC (decl
) = 1;
27859 TREE_STATIC (decl
) = 1;
27861 if (USE_HIDDEN_LINKONCE
)
27863 DECL_COMDAT_GROUP (decl
) = DECL_ASSEMBLER_NAME (decl
);
27864 targetm
.asm_out
.unique_section (decl
, 0);
27865 switch_to_section (get_named_section (decl
, NULL
, 0));
27866 DECL_WEAK (decl
) = 1;
27867 ASM_WEAKEN_DECL (asm_out_file
, decl
, name
, 0);
27868 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
27869 targetm
.asm_out
.assemble_visibility (decl
, VISIBILITY_HIDDEN
);
27870 ASM_DECLARE_FUNCTION_NAME (asm_out_file
, name
, decl
);
27874 switch_to_section (text_section
);
27875 ASM_OUTPUT_LABEL (asm_out_file
, name
);
27878 DECL_INITIAL (decl
) = make_node (BLOCK
);
27879 current_function_decl
= decl
;
27880 init_function_start (decl
);
27881 first_function_block_is_cold
= false;
27882 /* Make sure unwind info is emitted for the thunk if needed. */
27883 final_start_function (emit_barrier (), asm_out_file
, 1);
27885 fputs ("\tblr\n", asm_out_file
);
27887 final_end_function ();
27888 init_insn_lengths ();
27889 free_after_compilation (cfun
);
27891 current_function_decl
= NULL
;
27894 /* Add r30 to hard reg set if the prologue sets it up and it is not
27895 pic_offset_table_rtx. */
27898 rs6000_set_up_by_prologue (struct hard_reg_set_container
*set
)
27900 if (!TARGET_SINGLE_PIC_BASE
27902 && TARGET_MINIMAL_TOC
27903 && get_pool_size () != 0)
27904 add_to_hard_reg_set (&set
->set
, Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
27907 struct gcc_target targetm
= TARGET_INITIALIZER
;
27909 #include "gt-rs6000.h"