1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 3, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
56 #include "tree-flow.h"
59 #include "tm-constrs.h"
61 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
64 #include "gstab.h" /* for N_SLINE */
67 #ifndef TARGET_NO_PROTOTYPE
68 #define TARGET_NO_PROTOTYPE 0
71 #define min(A,B) ((A) < (B) ? (A) : (B))
72 #define max(A,B) ((A) > (B) ? (A) : (B))
74 /* Structure used to define the rs6000 stack */
75 typedef struct rs6000_stack
{
76 int first_gp_reg_save
; /* first callee saved GP register used */
77 int first_fp_reg_save
; /* first callee saved FP register used */
78 int first_altivec_reg_save
; /* first callee saved AltiVec register used */
79 int lr_save_p
; /* true if the link reg needs to be saved */
80 int cr_save_p
; /* true if the CR reg needs to be saved */
81 unsigned int vrsave_mask
; /* mask of vec registers to save */
82 int push_p
; /* true if we need to allocate stack space */
83 int calls_p
; /* true if the function makes any calls */
84 int world_save_p
; /* true if we're saving *everything*:
85 r13-r31, cr, f14-f31, vrsave, v20-v31 */
86 enum rs6000_abi abi
; /* which ABI to use */
87 int gp_save_offset
; /* offset to save GP regs from initial SP */
88 int fp_save_offset
; /* offset to save FP regs from initial SP */
89 int altivec_save_offset
; /* offset to save AltiVec regs from initial SP */
90 int lr_save_offset
; /* offset to save LR from initial SP */
91 int cr_save_offset
; /* offset to save CR from initial SP */
92 int vrsave_save_offset
; /* offset to save VRSAVE from initial SP */
93 int spe_gp_save_offset
; /* offset to save spe 64-bit gprs */
94 int varargs_save_offset
; /* offset to save the varargs registers */
95 int ehrd_offset
; /* offset to EH return data */
96 int reg_size
; /* register size (4 or 8) */
97 HOST_WIDE_INT vars_size
; /* variable save area size */
98 int parm_size
; /* outgoing parameter size */
99 int save_size
; /* save area size */
100 int fixed_size
; /* fixed size of stack frame */
101 int gp_size
; /* size of saved GP registers */
102 int fp_size
; /* size of saved FP registers */
103 int altivec_size
; /* size of saved AltiVec registers */
104 int cr_size
; /* size to hold CR if not in save_size */
105 int vrsave_size
; /* size to hold VRSAVE if not in save_size */
106 int altivec_padding_size
; /* size of altivec alignment padding if
108 int spe_gp_size
; /* size of 64-bit GPR save size for SPE */
109 int spe_padding_size
;
110 HOST_WIDE_INT total_size
; /* total bytes allocated for stack */
111 int spe_64bit_regs_used
;
114 /* A C structure for machine-specific, per-function data.
115 This is added to the cfun structure. */
116 typedef struct machine_function
GTY(())
118 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
119 int ra_needs_full_frame
;
120 /* Some local-dynamic symbol. */
121 const char *some_ld_name
;
122 /* Whether the instruction chain has been scanned already. */
123 int insn_chain_scanned_p
;
124 /* Flags if __builtin_return_address (0) was used. */
126 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
127 varargs save area. */
128 HOST_WIDE_INT varargs_save_offset
;
129 /* Temporary stack slot to use for SDmode copies. This slot is
130 64-bits wide and is allocated early enough so that the offset
131 does not overflow the 16-bit load/store offset field. */
132 rtx sdmode_stack_slot
;
135 /* Target cpu type */
137 enum processor_type rs6000_cpu
;
138 struct rs6000_cpu_select rs6000_select
[3] =
140 /* switch name, tune arch */
141 { (const char *)0, "--with-cpu=", 1, 1 },
142 { (const char *)0, "-mcpu=", 1, 1 },
143 { (const char *)0, "-mtune=", 1, 0 },
146 static GTY(()) bool rs6000_cell_dont_microcode
;
148 /* Always emit branch hint bits. */
149 static GTY(()) bool rs6000_always_hint
;
151 /* Schedule instructions for group formation. */
152 static GTY(()) bool rs6000_sched_groups
;
154 /* Align branch targets. */
155 static GTY(()) bool rs6000_align_branch_targets
;
157 /* Support for -msched-costly-dep option. */
158 const char *rs6000_sched_costly_dep_str
;
159 enum rs6000_dependence_cost rs6000_sched_costly_dep
;
161 /* Support for -minsert-sched-nops option. */
162 const char *rs6000_sched_insert_nops_str
;
163 enum rs6000_nop_insertion rs6000_sched_insert_nops
;
165 /* Support targetm.vectorize.builtin_mask_for_load. */
166 static GTY(()) tree altivec_builtin_mask_for_load
;
168 /* Size of long double. */
169 int rs6000_long_double_type_size
;
171 /* IEEE quad extended precision long double. */
174 /* Nonzero to use AltiVec ABI. */
175 int rs6000_altivec_abi
;
177 /* Nonzero if we want SPE SIMD instructions. */
180 /* Nonzero if we want SPE ABI extensions. */
183 /* Nonzero to use isel instructions. */
186 /* Nonzero if floating point operations are done in the GPRs. */
187 int rs6000_float_gprs
= 0;
189 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
190 int rs6000_darwin64_abi
;
192 /* Set to nonzero once AIX common-mode calls have been defined. */
193 static GTY(()) int common_mode_defined
;
195 /* Save information from a "cmpxx" operation until the branch or scc is
197 rtx rs6000_compare_op0
, rs6000_compare_op1
;
198 int rs6000_compare_fp_p
;
200 /* Label number of label created for -mrelocatable, to call to so we can
201 get the address of the GOT section */
202 int rs6000_pic_labelno
;
205 /* Which abi to adhere to */
206 const char *rs6000_abi_name
;
208 /* Semantics of the small data area */
209 enum rs6000_sdata_type rs6000_sdata
= SDATA_DATA
;
211 /* Which small data model to use */
212 const char *rs6000_sdata_name
= (char *)0;
214 /* Counter for labels which are to be placed in .fixup. */
215 int fixuplabelno
= 0;
218 /* Bit size of immediate TLS offsets and string from which it is decoded. */
219 int rs6000_tls_size
= 32;
220 const char *rs6000_tls_size_string
;
222 /* ABI enumeration available for subtarget to use. */
223 enum rs6000_abi rs6000_current_abi
;
225 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
229 const char *rs6000_debug_name
;
230 int rs6000_debug_stack
; /* debug stack applications */
231 int rs6000_debug_arg
; /* debug argument handling */
233 /* Value is TRUE if register/mode pair is acceptable. */
234 bool rs6000_hard_regno_mode_ok_p
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
236 /* Built in types. */
238 tree rs6000_builtin_types
[RS6000_BTI_MAX
];
239 tree rs6000_builtin_decls
[RS6000_BUILTIN_COUNT
];
241 const char *rs6000_traceback_name
;
243 traceback_default
= 0,
249 /* Flag to say the TOC is initialized */
251 char toc_label_name
[10];
253 /* Cached value of rs6000_variable_issue. This is cached in
254 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
255 static short cached_can_issue_more
;
257 static GTY(()) section
*read_only_data_section
;
258 static GTY(()) section
*private_data_section
;
259 static GTY(()) section
*read_only_private_data_section
;
260 static GTY(()) section
*sdata2_section
;
261 static GTY(()) section
*toc_section
;
263 /* Control alignment for fields within structures. */
264 /* String from -malign-XXXXX. */
265 int rs6000_alignment_flags
;
267 /* True for any options that were explicitly set. */
269 bool aix_struct_ret
; /* True if -maix-struct-ret was used. */
270 bool alignment
; /* True if -malign- was used. */
271 bool spe_abi
; /* True if -mabi=spe/no-spe was used. */
272 bool altivec_abi
; /* True if -mabi=altivec/no-altivec used. */
273 bool spe
; /* True if -mspe= was used. */
274 bool float_gprs
; /* True if -mfloat-gprs= was used. */
275 bool isel
; /* True if -misel was used. */
276 bool long_double
; /* True if -mlong-double- was used. */
277 bool ieee
; /* True if -mabi=ieee/ibmlongdouble used. */
278 bool vrsave
; /* True if -mvrsave was used. */
279 } rs6000_explicit_options
;
281 struct builtin_description
283 /* mask is not const because we're going to alter it below. This
284 nonsense will go away when we rewrite the -march infrastructure
285 to give us more target flag bits. */
287 const enum insn_code icode
;
288 const char *const name
;
289 const enum rs6000_builtins code
;
292 /* Target cpu costs. */
294 struct processor_costs
{
295 const int mulsi
; /* cost of SImode multiplication. */
296 const int mulsi_const
; /* cost of SImode multiplication by constant. */
297 const int mulsi_const9
; /* cost of SImode mult by short constant. */
298 const int muldi
; /* cost of DImode multiplication. */
299 const int divsi
; /* cost of SImode division. */
300 const int divdi
; /* cost of DImode division. */
301 const int fp
; /* cost of simple SFmode and DFmode insns. */
302 const int dmul
; /* cost of DFmode multiplication (and fmadd). */
303 const int sdiv
; /* cost of SFmode division (fdivs). */
304 const int ddiv
; /* cost of DFmode division (fdiv). */
305 const int cache_line_size
; /* cache line size in bytes. */
306 const int l1_cache_size
; /* size of l1 cache, in kilobytes. */
307 const int l2_cache_size
; /* size of l2 cache, in kilobytes. */
308 const int simultaneous_prefetches
; /* number of parallel prefetch
312 const struct processor_costs
*rs6000_cost
;
314 /* Processor costs (relative to an add) */
316 /* Instruction size costs on 32bit processors. */
318 struct processor_costs size32_cost
= {
319 COSTS_N_INSNS (1), /* mulsi */
320 COSTS_N_INSNS (1), /* mulsi_const */
321 COSTS_N_INSNS (1), /* mulsi_const9 */
322 COSTS_N_INSNS (1), /* muldi */
323 COSTS_N_INSNS (1), /* divsi */
324 COSTS_N_INSNS (1), /* divdi */
325 COSTS_N_INSNS (1), /* fp */
326 COSTS_N_INSNS (1), /* dmul */
327 COSTS_N_INSNS (1), /* sdiv */
328 COSTS_N_INSNS (1), /* ddiv */
335 /* Instruction size costs on 64bit processors. */
337 struct processor_costs size64_cost
= {
338 COSTS_N_INSNS (1), /* mulsi */
339 COSTS_N_INSNS (1), /* mulsi_const */
340 COSTS_N_INSNS (1), /* mulsi_const9 */
341 COSTS_N_INSNS (1), /* muldi */
342 COSTS_N_INSNS (1), /* divsi */
343 COSTS_N_INSNS (1), /* divdi */
344 COSTS_N_INSNS (1), /* fp */
345 COSTS_N_INSNS (1), /* dmul */
346 COSTS_N_INSNS (1), /* sdiv */
347 COSTS_N_INSNS (1), /* ddiv */
354 /* Instruction costs on RIOS1 processors. */
356 struct processor_costs rios1_cost
= {
357 COSTS_N_INSNS (5), /* mulsi */
358 COSTS_N_INSNS (4), /* mulsi_const */
359 COSTS_N_INSNS (3), /* mulsi_const9 */
360 COSTS_N_INSNS (5), /* muldi */
361 COSTS_N_INSNS (19), /* divsi */
362 COSTS_N_INSNS (19), /* divdi */
363 COSTS_N_INSNS (2), /* fp */
364 COSTS_N_INSNS (2), /* dmul */
365 COSTS_N_INSNS (19), /* sdiv */
366 COSTS_N_INSNS (19), /* ddiv */
367 128, /* cache line size */
373 /* Instruction costs on RIOS2 processors. */
375 struct processor_costs rios2_cost
= {
376 COSTS_N_INSNS (2), /* mulsi */
377 COSTS_N_INSNS (2), /* mulsi_const */
378 COSTS_N_INSNS (2), /* mulsi_const9 */
379 COSTS_N_INSNS (2), /* muldi */
380 COSTS_N_INSNS (13), /* divsi */
381 COSTS_N_INSNS (13), /* divdi */
382 COSTS_N_INSNS (2), /* fp */
383 COSTS_N_INSNS (2), /* dmul */
384 COSTS_N_INSNS (17), /* sdiv */
385 COSTS_N_INSNS (17), /* ddiv */
386 256, /* cache line size */
392 /* Instruction costs on RS64A processors. */
394 struct processor_costs rs64a_cost
= {
395 COSTS_N_INSNS (20), /* mulsi */
396 COSTS_N_INSNS (12), /* mulsi_const */
397 COSTS_N_INSNS (8), /* mulsi_const9 */
398 COSTS_N_INSNS (34), /* muldi */
399 COSTS_N_INSNS (65), /* divsi */
400 COSTS_N_INSNS (67), /* divdi */
401 COSTS_N_INSNS (4), /* fp */
402 COSTS_N_INSNS (4), /* dmul */
403 COSTS_N_INSNS (31), /* sdiv */
404 COSTS_N_INSNS (31), /* ddiv */
405 128, /* cache line size */
411 /* Instruction costs on MPCCORE processors. */
413 struct processor_costs mpccore_cost
= {
414 COSTS_N_INSNS (2), /* mulsi */
415 COSTS_N_INSNS (2), /* mulsi_const */
416 COSTS_N_INSNS (2), /* mulsi_const9 */
417 COSTS_N_INSNS (2), /* muldi */
418 COSTS_N_INSNS (6), /* divsi */
419 COSTS_N_INSNS (6), /* divdi */
420 COSTS_N_INSNS (4), /* fp */
421 COSTS_N_INSNS (5), /* dmul */
422 COSTS_N_INSNS (10), /* sdiv */
423 COSTS_N_INSNS (17), /* ddiv */
424 32, /* cache line size */
430 /* Instruction costs on PPC403 processors. */
432 struct processor_costs ppc403_cost
= {
433 COSTS_N_INSNS (4), /* mulsi */
434 COSTS_N_INSNS (4), /* mulsi_const */
435 COSTS_N_INSNS (4), /* mulsi_const9 */
436 COSTS_N_INSNS (4), /* muldi */
437 COSTS_N_INSNS (33), /* divsi */
438 COSTS_N_INSNS (33), /* divdi */
439 COSTS_N_INSNS (11), /* fp */
440 COSTS_N_INSNS (11), /* dmul */
441 COSTS_N_INSNS (11), /* sdiv */
442 COSTS_N_INSNS (11), /* ddiv */
443 32, /* cache line size */
449 /* Instruction costs on PPC405 processors. */
451 struct processor_costs ppc405_cost
= {
452 COSTS_N_INSNS (5), /* mulsi */
453 COSTS_N_INSNS (4), /* mulsi_const */
454 COSTS_N_INSNS (3), /* mulsi_const9 */
455 COSTS_N_INSNS (5), /* muldi */
456 COSTS_N_INSNS (35), /* divsi */
457 COSTS_N_INSNS (35), /* divdi */
458 COSTS_N_INSNS (11), /* fp */
459 COSTS_N_INSNS (11), /* dmul */
460 COSTS_N_INSNS (11), /* sdiv */
461 COSTS_N_INSNS (11), /* ddiv */
462 32, /* cache line size */
468 /* Instruction costs on PPC440 processors. */
470 struct processor_costs ppc440_cost
= {
471 COSTS_N_INSNS (3), /* mulsi */
472 COSTS_N_INSNS (2), /* mulsi_const */
473 COSTS_N_INSNS (2), /* mulsi_const9 */
474 COSTS_N_INSNS (3), /* muldi */
475 COSTS_N_INSNS (34), /* divsi */
476 COSTS_N_INSNS (34), /* divdi */
477 COSTS_N_INSNS (5), /* fp */
478 COSTS_N_INSNS (5), /* dmul */
479 COSTS_N_INSNS (19), /* sdiv */
480 COSTS_N_INSNS (33), /* ddiv */
481 32, /* cache line size */
487 /* Instruction costs on PPC601 processors. */
489 struct processor_costs ppc601_cost
= {
490 COSTS_N_INSNS (5), /* mulsi */
491 COSTS_N_INSNS (5), /* mulsi_const */
492 COSTS_N_INSNS (5), /* mulsi_const9 */
493 COSTS_N_INSNS (5), /* muldi */
494 COSTS_N_INSNS (36), /* divsi */
495 COSTS_N_INSNS (36), /* divdi */
496 COSTS_N_INSNS (4), /* fp */
497 COSTS_N_INSNS (5), /* dmul */
498 COSTS_N_INSNS (17), /* sdiv */
499 COSTS_N_INSNS (31), /* ddiv */
500 32, /* cache line size */
506 /* Instruction costs on PPC603 processors. */
508 struct processor_costs ppc603_cost
= {
509 COSTS_N_INSNS (5), /* mulsi */
510 COSTS_N_INSNS (3), /* mulsi_const */
511 COSTS_N_INSNS (2), /* mulsi_const9 */
512 COSTS_N_INSNS (5), /* muldi */
513 COSTS_N_INSNS (37), /* divsi */
514 COSTS_N_INSNS (37), /* divdi */
515 COSTS_N_INSNS (3), /* fp */
516 COSTS_N_INSNS (4), /* dmul */
517 COSTS_N_INSNS (18), /* sdiv */
518 COSTS_N_INSNS (33), /* ddiv */
519 32, /* cache line size */
525 /* Instruction costs on PPC604 processors. */
527 struct processor_costs ppc604_cost
= {
528 COSTS_N_INSNS (4), /* mulsi */
529 COSTS_N_INSNS (4), /* mulsi_const */
530 COSTS_N_INSNS (4), /* mulsi_const9 */
531 COSTS_N_INSNS (4), /* muldi */
532 COSTS_N_INSNS (20), /* divsi */
533 COSTS_N_INSNS (20), /* divdi */
534 COSTS_N_INSNS (3), /* fp */
535 COSTS_N_INSNS (3), /* dmul */
536 COSTS_N_INSNS (18), /* sdiv */
537 COSTS_N_INSNS (32), /* ddiv */
538 32, /* cache line size */
544 /* Instruction costs on PPC604e processors. */
546 struct processor_costs ppc604e_cost
= {
547 COSTS_N_INSNS (2), /* mulsi */
548 COSTS_N_INSNS (2), /* mulsi_const */
549 COSTS_N_INSNS (2), /* mulsi_const9 */
550 COSTS_N_INSNS (2), /* muldi */
551 COSTS_N_INSNS (20), /* divsi */
552 COSTS_N_INSNS (20), /* divdi */
553 COSTS_N_INSNS (3), /* fp */
554 COSTS_N_INSNS (3), /* dmul */
555 COSTS_N_INSNS (18), /* sdiv */
556 COSTS_N_INSNS (32), /* ddiv */
557 32, /* cache line size */
563 /* Instruction costs on PPC620 processors. */
565 struct processor_costs ppc620_cost
= {
566 COSTS_N_INSNS (5), /* mulsi */
567 COSTS_N_INSNS (4), /* mulsi_const */
568 COSTS_N_INSNS (3), /* mulsi_const9 */
569 COSTS_N_INSNS (7), /* muldi */
570 COSTS_N_INSNS (21), /* divsi */
571 COSTS_N_INSNS (37), /* divdi */
572 COSTS_N_INSNS (3), /* fp */
573 COSTS_N_INSNS (3), /* dmul */
574 COSTS_N_INSNS (18), /* sdiv */
575 COSTS_N_INSNS (32), /* ddiv */
576 128, /* cache line size */
582 /* Instruction costs on PPC630 processors. */
584 struct processor_costs ppc630_cost
= {
585 COSTS_N_INSNS (5), /* mulsi */
586 COSTS_N_INSNS (4), /* mulsi_const */
587 COSTS_N_INSNS (3), /* mulsi_const9 */
588 COSTS_N_INSNS (7), /* muldi */
589 COSTS_N_INSNS (21), /* divsi */
590 COSTS_N_INSNS (37), /* divdi */
591 COSTS_N_INSNS (3), /* fp */
592 COSTS_N_INSNS (3), /* dmul */
593 COSTS_N_INSNS (17), /* sdiv */
594 COSTS_N_INSNS (21), /* ddiv */
595 128, /* cache line size */
601 /* Instruction costs on Cell processor. */
602 /* COSTS_N_INSNS (1) ~ one add. */
604 struct processor_costs ppccell_cost
= {
605 COSTS_N_INSNS (9/2)+2, /* mulsi */
606 COSTS_N_INSNS (6/2), /* mulsi_const */
607 COSTS_N_INSNS (6/2), /* mulsi_const9 */
608 COSTS_N_INSNS (15/2)+2, /* muldi */
609 COSTS_N_INSNS (38/2), /* divsi */
610 COSTS_N_INSNS (70/2), /* divdi */
611 COSTS_N_INSNS (10/2), /* fp */
612 COSTS_N_INSNS (10/2), /* dmul */
613 COSTS_N_INSNS (74/2), /* sdiv */
614 COSTS_N_INSNS (74/2), /* ddiv */
615 128, /* cache line size */
621 /* Instruction costs on PPC750 and PPC7400 processors. */
623 struct processor_costs ppc750_cost
= {
624 COSTS_N_INSNS (5), /* mulsi */
625 COSTS_N_INSNS (3), /* mulsi_const */
626 COSTS_N_INSNS (2), /* mulsi_const9 */
627 COSTS_N_INSNS (5), /* muldi */
628 COSTS_N_INSNS (17), /* divsi */
629 COSTS_N_INSNS (17), /* divdi */
630 COSTS_N_INSNS (3), /* fp */
631 COSTS_N_INSNS (3), /* dmul */
632 COSTS_N_INSNS (17), /* sdiv */
633 COSTS_N_INSNS (31), /* ddiv */
634 32, /* cache line size */
640 /* Instruction costs on PPC7450 processors. */
642 struct processor_costs ppc7450_cost
= {
643 COSTS_N_INSNS (4), /* mulsi */
644 COSTS_N_INSNS (3), /* mulsi_const */
645 COSTS_N_INSNS (3), /* mulsi_const9 */
646 COSTS_N_INSNS (4), /* muldi */
647 COSTS_N_INSNS (23), /* divsi */
648 COSTS_N_INSNS (23), /* divdi */
649 COSTS_N_INSNS (5), /* fp */
650 COSTS_N_INSNS (5), /* dmul */
651 COSTS_N_INSNS (21), /* sdiv */
652 COSTS_N_INSNS (35), /* ddiv */
653 32, /* cache line size */
659 /* Instruction costs on PPC8540 processors. */
661 struct processor_costs ppc8540_cost
= {
662 COSTS_N_INSNS (4), /* mulsi */
663 COSTS_N_INSNS (4), /* mulsi_const */
664 COSTS_N_INSNS (4), /* mulsi_const9 */
665 COSTS_N_INSNS (4), /* muldi */
666 COSTS_N_INSNS (19), /* divsi */
667 COSTS_N_INSNS (19), /* divdi */
668 COSTS_N_INSNS (4), /* fp */
669 COSTS_N_INSNS (4), /* dmul */
670 COSTS_N_INSNS (29), /* sdiv */
671 COSTS_N_INSNS (29), /* ddiv */
672 32, /* cache line size */
675 1, /* prefetch streams /*/
678 /* Instruction costs on E300C2 and E300C3 cores. */
680 struct processor_costs ppce300c2c3_cost
= {
681 COSTS_N_INSNS (4), /* mulsi */
682 COSTS_N_INSNS (4), /* mulsi_const */
683 COSTS_N_INSNS (4), /* mulsi_const9 */
684 COSTS_N_INSNS (4), /* muldi */
685 COSTS_N_INSNS (19), /* divsi */
686 COSTS_N_INSNS (19), /* divdi */
687 COSTS_N_INSNS (3), /* fp */
688 COSTS_N_INSNS (4), /* dmul */
689 COSTS_N_INSNS (18), /* sdiv */
690 COSTS_N_INSNS (33), /* ddiv */
694 1, /* prefetch streams /*/
697 /* Instruction costs on PPCE500MC processors. */
699 struct processor_costs ppce500mc_cost
= {
700 COSTS_N_INSNS (4), /* mulsi */
701 COSTS_N_INSNS (4), /* mulsi_const */
702 COSTS_N_INSNS (4), /* mulsi_const9 */
703 COSTS_N_INSNS (4), /* muldi */
704 COSTS_N_INSNS (14), /* divsi */
705 COSTS_N_INSNS (14), /* divdi */
706 COSTS_N_INSNS (8), /* fp */
707 COSTS_N_INSNS (10), /* dmul */
708 COSTS_N_INSNS (36), /* sdiv */
709 COSTS_N_INSNS (66), /* ddiv */
710 64, /* cache line size */
713 1, /* prefetch streams /*/
716 /* Instruction costs on POWER4 and POWER5 processors. */
718 struct processor_costs power4_cost
= {
719 COSTS_N_INSNS (3), /* mulsi */
720 COSTS_N_INSNS (2), /* mulsi_const */
721 COSTS_N_INSNS (2), /* mulsi_const9 */
722 COSTS_N_INSNS (4), /* muldi */
723 COSTS_N_INSNS (18), /* divsi */
724 COSTS_N_INSNS (34), /* divdi */
725 COSTS_N_INSNS (3), /* fp */
726 COSTS_N_INSNS (3), /* dmul */
727 COSTS_N_INSNS (17), /* sdiv */
728 COSTS_N_INSNS (17), /* ddiv */
729 128, /* cache line size */
732 8, /* prefetch streams /*/
735 /* Instruction costs on POWER6 processors. */
737 struct processor_costs power6_cost
= {
738 COSTS_N_INSNS (8), /* mulsi */
739 COSTS_N_INSNS (8), /* mulsi_const */
740 COSTS_N_INSNS (8), /* mulsi_const9 */
741 COSTS_N_INSNS (8), /* muldi */
742 COSTS_N_INSNS (22), /* divsi */
743 COSTS_N_INSNS (28), /* divdi */
744 COSTS_N_INSNS (3), /* fp */
745 COSTS_N_INSNS (3), /* dmul */
746 COSTS_N_INSNS (13), /* sdiv */
747 COSTS_N_INSNS (16), /* ddiv */
748 128, /* cache line size */
751 16, /* prefetch streams */
755 static bool rs6000_function_ok_for_sibcall (tree
, tree
);
756 static const char *rs6000_invalid_within_doloop (const_rtx
);
757 static rtx
rs6000_generate_compare (enum rtx_code
);
758 static void rs6000_emit_stack_tie (void);
759 static void rs6000_frame_related (rtx
, rtx
, HOST_WIDE_INT
, rtx
, rtx
);
760 static bool spe_func_has_64bit_regs_p (void);
761 static void emit_frame_save (rtx
, rtx
, enum machine_mode
, unsigned int,
763 static rtx
gen_frame_mem_offset (enum machine_mode
, rtx
, int);
764 static void rs6000_emit_allocate_stack (HOST_WIDE_INT
, int, int);
765 static unsigned rs6000_hash_constant (rtx
);
766 static unsigned toc_hash_function (const void *);
767 static int toc_hash_eq (const void *, const void *);
768 static int constant_pool_expr_1 (rtx
, int *, int *);
769 static bool constant_pool_expr_p (rtx
);
770 static bool legitimate_small_data_p (enum machine_mode
, rtx
);
771 static bool legitimate_lo_sum_address_p (enum machine_mode
, rtx
, int);
772 static struct machine_function
* rs6000_init_machine_status (void);
773 static bool rs6000_assemble_integer (rtx
, unsigned int, int);
774 static bool no_global_regs_above (int, bool);
775 #ifdef HAVE_GAS_HIDDEN
776 static void rs6000_assemble_visibility (tree
, int);
778 static int rs6000_ra_ever_killed (void);
779 static tree
rs6000_handle_longcall_attribute (tree
*, tree
, tree
, int, bool *);
780 static tree
rs6000_handle_altivec_attribute (tree
*, tree
, tree
, int, bool *);
781 static bool rs6000_ms_bitfield_layout_p (const_tree
);
782 static tree
rs6000_handle_struct_attribute (tree
*, tree
, tree
, int, bool *);
783 static void rs6000_eliminate_indexed_memrefs (rtx operands
[2]);
784 static const char *rs6000_mangle_type (const_tree
);
785 extern const struct attribute_spec rs6000_attribute_table
[];
786 static void rs6000_set_default_type_attributes (tree
);
787 static rtx
rs6000_savres_routine_sym (rs6000_stack_t
*, bool, bool, bool);
788 static void rs6000_emit_stack_reset (rs6000_stack_t
*, rtx
, rtx
, int, bool);
789 static rtx
rs6000_make_savres_rtx (rs6000_stack_t
*, rtx
, int,
790 enum machine_mode
, bool, bool, bool);
791 static bool rs6000_reg_live_or_pic_offset_p (int);
792 static int rs6000_savres_strategy (rs6000_stack_t
*, bool, int, int);
793 static void rs6000_restore_saved_cr (rtx
, int);
794 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT
);
795 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT
);
796 static void rs6000_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
798 static rtx
rs6000_emit_set_long_const (rtx
, HOST_WIDE_INT
, HOST_WIDE_INT
);
799 static bool rs6000_return_in_memory (const_tree
, const_tree
);
800 static void rs6000_file_start (void);
802 static int rs6000_elf_reloc_rw_mask (void);
803 static void rs6000_elf_asm_out_constructor (rtx
, int);
804 static void rs6000_elf_asm_out_destructor (rtx
, int);
805 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED
;
806 static void rs6000_elf_asm_init_sections (void);
807 static section
*rs6000_elf_select_rtx_section (enum machine_mode
, rtx
,
808 unsigned HOST_WIDE_INT
);
809 static void rs6000_elf_encode_section_info (tree
, rtx
, int)
812 static bool rs6000_use_blocks_for_constant_p (enum machine_mode
, const_rtx
);
813 static void rs6000_alloc_sdmode_stack_slot (void);
814 static void rs6000_instantiate_decls (void);
816 static void rs6000_xcoff_asm_output_anchor (rtx
);
817 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
818 static void rs6000_xcoff_asm_init_sections (void);
819 static int rs6000_xcoff_reloc_rw_mask (void);
820 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree
);
821 static section
*rs6000_xcoff_select_section (tree
, int,
822 unsigned HOST_WIDE_INT
);
823 static void rs6000_xcoff_unique_section (tree
, int);
824 static section
*rs6000_xcoff_select_rtx_section
825 (enum machine_mode
, rtx
, unsigned HOST_WIDE_INT
);
826 static const char * rs6000_xcoff_strip_name_encoding (const char *);
827 static unsigned int rs6000_xcoff_section_type_flags (tree
, const char *, int);
828 static void rs6000_xcoff_file_start (void);
829 static void rs6000_xcoff_file_end (void);
831 static int rs6000_variable_issue (FILE *, int, rtx
, int);
832 static bool rs6000_rtx_costs (rtx
, int, int, int *);
833 static int rs6000_adjust_cost (rtx
, rtx
, rtx
, int);
834 static void rs6000_sched_init (FILE *, int, int);
835 static bool is_microcoded_insn (rtx
);
836 static bool is_nonpipeline_insn (rtx
);
837 static bool is_cracked_insn (rtx
);
838 static bool is_branch_slot_insn (rtx
);
839 static bool is_load_insn (rtx
);
840 static rtx
get_store_dest (rtx pat
);
841 static bool is_store_insn (rtx
);
842 static bool set_to_load_agen (rtx
,rtx
);
843 static bool adjacent_mem_locations (rtx
,rtx
);
844 static int rs6000_adjust_priority (rtx
, int);
845 static int rs6000_issue_rate (void);
846 static bool rs6000_is_costly_dependence (dep_t
, int, int);
847 static rtx
get_next_active_insn (rtx
, rtx
);
848 static bool insn_terminates_group_p (rtx
, enum group_termination
);
849 static bool insn_must_be_first_in_group (rtx
);
850 static bool insn_must_be_last_in_group (rtx
);
851 static bool is_costly_group (rtx
*, rtx
);
852 static int force_new_group (int, FILE *, rtx
*, rtx
, bool *, int, int *);
853 static int redefine_groups (FILE *, int, rtx
, rtx
);
854 static int pad_groups (FILE *, int, rtx
, rtx
);
855 static void rs6000_sched_finish (FILE *, int);
856 static int rs6000_sched_reorder (FILE *, int, rtx
*, int *, int);
857 static int rs6000_sched_reorder2 (FILE *, int, rtx
*, int *, int);
858 static int rs6000_use_sched_lookahead (void);
859 static int rs6000_use_sched_lookahead_guard (rtx
);
860 static tree
rs6000_builtin_reciprocal (unsigned int, bool, bool);
861 static tree
rs6000_builtin_mask_for_load (void);
862 static tree
rs6000_builtin_mul_widen_even (tree
);
863 static tree
rs6000_builtin_mul_widen_odd (tree
);
864 static tree
rs6000_builtin_conversion (enum tree_code
, tree
);
866 static void def_builtin (int, const char *, tree
, int);
867 static bool rs6000_vector_alignment_reachable (const_tree
, bool);
868 static void rs6000_init_builtins (void);
869 static rtx
rs6000_expand_unop_builtin (enum insn_code
, tree
, rtx
);
870 static rtx
rs6000_expand_binop_builtin (enum insn_code
, tree
, rtx
);
871 static rtx
rs6000_expand_ternop_builtin (enum insn_code
, tree
, rtx
);
872 static rtx
rs6000_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
873 static void altivec_init_builtins (void);
874 static void rs6000_common_init_builtins (void);
875 static void rs6000_init_libfuncs (void);
877 static void paired_init_builtins (void);
878 static rtx
paired_expand_builtin (tree
, rtx
, bool *);
879 static rtx
paired_expand_lv_builtin (enum insn_code
, tree
, rtx
);
880 static rtx
paired_expand_stv_builtin (enum insn_code
, tree
);
881 static rtx
paired_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
883 static void enable_mask_for_builtins (struct builtin_description
*, int,
884 enum rs6000_builtins
,
885 enum rs6000_builtins
);
886 static tree
build_opaque_vector_type (tree
, int);
887 static void spe_init_builtins (void);
888 static rtx
spe_expand_builtin (tree
, rtx
, bool *);
889 static rtx
spe_expand_stv_builtin (enum insn_code
, tree
);
890 static rtx
spe_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
891 static rtx
spe_expand_evsel_builtin (enum insn_code
, tree
, rtx
);
892 static int rs6000_emit_int_cmove (rtx
, rtx
, rtx
, rtx
);
893 static rs6000_stack_t
*rs6000_stack_info (void);
894 static void debug_stack_info (rs6000_stack_t
*);
896 static rtx
altivec_expand_builtin (tree
, rtx
, bool *);
897 static rtx
altivec_expand_ld_builtin (tree
, rtx
, bool *);
898 static rtx
altivec_expand_st_builtin (tree
, rtx
, bool *);
899 static rtx
altivec_expand_dst_builtin (tree
, rtx
, bool *);
900 static rtx
altivec_expand_abs_builtin (enum insn_code
, tree
, rtx
);
901 static rtx
altivec_expand_predicate_builtin (enum insn_code
,
902 const char *, tree
, rtx
);
903 static rtx
altivec_expand_lv_builtin (enum insn_code
, tree
, rtx
);
904 static rtx
altivec_expand_stv_builtin (enum insn_code
, tree
);
905 static rtx
altivec_expand_vec_init_builtin (tree
, tree
, rtx
);
906 static rtx
altivec_expand_vec_set_builtin (tree
);
907 static rtx
altivec_expand_vec_ext_builtin (tree
, rtx
);
908 static int get_element_number (tree
, tree
);
909 static bool rs6000_handle_option (size_t, const char *, int);
910 static void rs6000_parse_tls_size_option (void);
911 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
912 static int first_altivec_reg_to_save (void);
913 static unsigned int compute_vrsave_mask (void);
914 static void compute_save_world_info (rs6000_stack_t
*info_ptr
);
915 static void is_altivec_return_reg (rtx
, void *);
916 static rtx
generate_set_vrsave (rtx
, rs6000_stack_t
*, int);
917 int easy_vector_constant (rtx
, enum machine_mode
);
918 static bool rs6000_is_opaque_type (const_tree
);
919 static rtx
rs6000_dwarf_register_span (rtx
);
920 static void rs6000_init_dwarf_reg_sizes_extra (tree
);
921 static rtx
rs6000_legitimize_tls_address (rtx
, enum tls_model
);
922 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
923 static rtx
rs6000_tls_get_addr (void);
924 static rtx
rs6000_got_sym (void);
925 static int rs6000_tls_symbol_ref_1 (rtx
*, void *);
926 static const char *rs6000_get_some_local_dynamic_name (void);
927 static int rs6000_get_some_local_dynamic_name_1 (rtx
*, void *);
928 static rtx
rs6000_complex_function_value (enum machine_mode
);
929 static rtx
rs6000_spe_function_arg (CUMULATIVE_ARGS
*,
930 enum machine_mode
, tree
);
931 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*,
933 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*,
934 tree
, HOST_WIDE_INT
);
935 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*,
938 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*,
939 const_tree
, HOST_WIDE_INT
,
941 static rtx
rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*, const_tree
, int, bool);
942 static rtx
rs6000_mixed_function_arg (enum machine_mode
, tree
, int);
943 static void rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
);
944 static void setup_incoming_varargs (CUMULATIVE_ARGS
*,
945 enum machine_mode
, tree
,
947 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS
*, enum machine_mode
,
949 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
951 static const char *invalid_arg_for_unprototyped_fn (const_tree
, const_tree
, const_tree
);
953 static void macho_branch_islands (void);
954 static int no_previous_def (tree function_name
);
955 static tree
get_prev_label (tree function_name
);
956 static void rs6000_darwin_file_start (void);
959 static tree
rs6000_build_builtin_va_list (void);
960 static void rs6000_va_start (tree
, rtx
);
961 static tree
rs6000_gimplify_va_arg (tree
, tree
, gimple_seq
*, gimple_seq
*);
962 static bool rs6000_must_pass_in_stack (enum machine_mode
, const_tree
);
963 static bool rs6000_scalar_mode_supported_p (enum machine_mode
);
964 static bool rs6000_vector_mode_supported_p (enum machine_mode
);
965 static int get_vec_cmp_insn (enum rtx_code
, enum machine_mode
,
967 static rtx
rs6000_emit_vector_compare (enum rtx_code
, rtx
, rtx
,
969 static int get_vsel_insn (enum machine_mode
);
970 static void rs6000_emit_vector_select (rtx
, rtx
, rtx
, rtx
);
971 static tree
rs6000_stack_protect_fail (void);
973 const int INSN_NOT_AVAILABLE
= -1;
974 static enum machine_mode
rs6000_eh_return_filter_mode (void);
976 /* Hash table stuff for keeping track of TOC entries. */
978 struct toc_hash_struct
GTY(())
980 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
981 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
983 enum machine_mode key_mode
;
987 static GTY ((param_is (struct toc_hash_struct
))) htab_t toc_hash_table
;
989 /* Default register names. */
990 char rs6000_reg_names
[][8] =
992 "0", "1", "2", "3", "4", "5", "6", "7",
993 "8", "9", "10", "11", "12", "13", "14", "15",
994 "16", "17", "18", "19", "20", "21", "22", "23",
995 "24", "25", "26", "27", "28", "29", "30", "31",
996 "0", "1", "2", "3", "4", "5", "6", "7",
997 "8", "9", "10", "11", "12", "13", "14", "15",
998 "16", "17", "18", "19", "20", "21", "22", "23",
999 "24", "25", "26", "27", "28", "29", "30", "31",
1000 "mq", "lr", "ctr","ap",
1001 "0", "1", "2", "3", "4", "5", "6", "7",
1003 /* AltiVec registers. */
1004 "0", "1", "2", "3", "4", "5", "6", "7",
1005 "8", "9", "10", "11", "12", "13", "14", "15",
1006 "16", "17", "18", "19", "20", "21", "22", "23",
1007 "24", "25", "26", "27", "28", "29", "30", "31",
1009 /* SPE registers. */
1010 "spe_acc", "spefscr",
1011 /* Soft frame pointer. */
1015 #ifdef TARGET_REGNAMES
1016 static const char alt_reg_names
[][8] =
1018 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1019 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1020 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1021 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1022 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1023 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1024 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1025 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1026 "mq", "lr", "ctr", "ap",
1027 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1029 /* AltiVec registers. */
1030 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1031 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1032 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1033 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1035 /* SPE registers. */
1036 "spe_acc", "spefscr",
1037 /* Soft frame pointer. */
1042 #ifndef MASK_STRICT_ALIGN
1043 #define MASK_STRICT_ALIGN 0
1045 #ifndef TARGET_PROFILE_KERNEL
1046 #define TARGET_PROFILE_KERNEL 0
1049 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1050 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1052 /* Initialize the GCC target structure. */
1053 #undef TARGET_ATTRIBUTE_TABLE
1054 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1055 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1056 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1058 #undef TARGET_ASM_ALIGNED_DI_OP
1059 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1061 /* Default unaligned ops are only provided for ELF. Find the ops needed
1062 for non-ELF systems. */
1063 #ifndef OBJECT_FORMAT_ELF
1065 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1067 #undef TARGET_ASM_UNALIGNED_HI_OP
1068 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1069 #undef TARGET_ASM_UNALIGNED_SI_OP
1070 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1071 #undef TARGET_ASM_UNALIGNED_DI_OP
1072 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1075 #undef TARGET_ASM_UNALIGNED_HI_OP
1076 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1077 #undef TARGET_ASM_UNALIGNED_SI_OP
1078 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1079 #undef TARGET_ASM_UNALIGNED_DI_OP
1080 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1081 #undef TARGET_ASM_ALIGNED_DI_OP
1082 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1086 /* This hook deals with fixups for relocatable code and DI-mode objects
1088 #undef TARGET_ASM_INTEGER
1089 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1091 #ifdef HAVE_GAS_HIDDEN
1092 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1093 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1096 #undef TARGET_HAVE_TLS
1097 #define TARGET_HAVE_TLS HAVE_AS_TLS
1099 #undef TARGET_CANNOT_FORCE_CONST_MEM
1100 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
1102 #undef TARGET_ASM_FUNCTION_PROLOGUE
1103 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1104 #undef TARGET_ASM_FUNCTION_EPILOGUE
1105 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1107 #undef TARGET_SCHED_VARIABLE_ISSUE
1108 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1110 #undef TARGET_SCHED_ISSUE_RATE
1111 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1112 #undef TARGET_SCHED_ADJUST_COST
1113 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1114 #undef TARGET_SCHED_ADJUST_PRIORITY
1115 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1116 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1117 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1118 #undef TARGET_SCHED_INIT
1119 #define TARGET_SCHED_INIT rs6000_sched_init
1120 #undef TARGET_SCHED_FINISH
1121 #define TARGET_SCHED_FINISH rs6000_sched_finish
1122 #undef TARGET_SCHED_REORDER
1123 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1124 #undef TARGET_SCHED_REORDER2
1125 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1127 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1128 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1130 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1131 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1133 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1134 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1135 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN
1136 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN rs6000_builtin_mul_widen_even
1137 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD
1138 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD rs6000_builtin_mul_widen_odd
1139 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
1140 #define TARGET_VECTORIZE_BUILTIN_CONVERSION rs6000_builtin_conversion
1142 #undef TARGET_VECTOR_ALIGNMENT_REACHABLE
1143 #define TARGET_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1145 #undef TARGET_INIT_BUILTINS
1146 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1148 #undef TARGET_EXPAND_BUILTIN
1149 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1151 #undef TARGET_MANGLE_TYPE
1152 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1154 #undef TARGET_INIT_LIBFUNCS
1155 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1158 #undef TARGET_BINDS_LOCAL_P
1159 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1162 #undef TARGET_MS_BITFIELD_LAYOUT_P
1163 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1165 #undef TARGET_ASM_OUTPUT_MI_THUNK
1166 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1168 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1169 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1171 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1172 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1174 #undef TARGET_INVALID_WITHIN_DOLOOP
1175 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
1177 #undef TARGET_RTX_COSTS
1178 #define TARGET_RTX_COSTS rs6000_rtx_costs
1179 #undef TARGET_ADDRESS_COST
1180 #define TARGET_ADDRESS_COST hook_int_rtx_0
1182 #undef TARGET_VECTOR_OPAQUE_P
1183 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
1185 #undef TARGET_DWARF_REGISTER_SPAN
1186 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1188 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1189 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1191 /* On rs6000, function arguments are promoted, as are function return
1193 #undef TARGET_PROMOTE_FUNCTION_ARGS
1194 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
1195 #undef TARGET_PROMOTE_FUNCTION_RETURN
1196 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
1198 #undef TARGET_RETURN_IN_MEMORY
1199 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1201 #undef TARGET_SETUP_INCOMING_VARARGS
1202 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1204 /* Always strict argument naming on rs6000. */
1205 #undef TARGET_STRICT_ARGUMENT_NAMING
1206 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1207 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1208 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1209 #undef TARGET_SPLIT_COMPLEX_ARG
1210 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1211 #undef TARGET_MUST_PASS_IN_STACK
1212 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1213 #undef TARGET_PASS_BY_REFERENCE
1214 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1215 #undef TARGET_ARG_PARTIAL_BYTES
1216 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1218 #undef TARGET_BUILD_BUILTIN_VA_LIST
1219 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1221 #undef TARGET_EXPAND_BUILTIN_VA_START
1222 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1224 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1225 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1227 #undef TARGET_EH_RETURN_FILTER_MODE
1228 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1230 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1231 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1233 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1234 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1236 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1237 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1239 #undef TARGET_HANDLE_OPTION
1240 #define TARGET_HANDLE_OPTION rs6000_handle_option
1242 #undef TARGET_DEFAULT_TARGET_FLAGS
1243 #define TARGET_DEFAULT_TARGET_FLAGS \
1246 #undef TARGET_STACK_PROTECT_FAIL
1247 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1249 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1250 The PowerPC architecture requires only weak consistency among
1251 processors--that is, memory accesses between processors need not be
1252 sequentially consistent and memory accesses among processors can occur
1253 in any order. The ability to order memory accesses weakly provides
1254 opportunities for more efficient use of the system bus. Unless a
1255 dependency exists, the 604e allows read operations to precede store
1257 #undef TARGET_RELAXED_ORDERING
1258 #define TARGET_RELAXED_ORDERING true
1261 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1262 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1265 /* Use a 32-bit anchor range. This leads to sequences like:
1267 addis tmp,anchor,high
1270 where tmp itself acts as an anchor, and can be shared between
1271 accesses to the same 64k page. */
1272 #undef TARGET_MIN_ANCHOR_OFFSET
1273 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1274 #undef TARGET_MAX_ANCHOR_OFFSET
1275 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1276 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1277 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1279 #undef TARGET_BUILTIN_RECIPROCAL
1280 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1282 #undef TARGET_EXPAND_TO_RTL_HOOK
1283 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1285 #undef TARGET_INSTANTIATE_DECLS
1286 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1288 struct gcc_target targetm
= TARGET_INITIALIZER
;
1291 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1294 rs6000_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
1296 /* The GPRs can hold any mode, but values bigger than one register
1297 cannot go past R31. */
1298 if (INT_REGNO_P (regno
))
1299 return INT_REGNO_P (regno
+ HARD_REGNO_NREGS (regno
, mode
) - 1);
1301 /* The float registers can only hold floating modes and DImode.
1302 This excludes the 32-bit decimal float mode for now. */
1303 if (FP_REGNO_P (regno
))
1305 ((SCALAR_FLOAT_MODE_P (mode
)
1306 && (mode
!= TDmode
|| (regno
% 2) == 0)
1307 && FP_REGNO_P (regno
+ HARD_REGNO_NREGS (regno
, mode
) - 1))
1308 || (GET_MODE_CLASS (mode
) == MODE_INT
1309 && GET_MODE_SIZE (mode
) == UNITS_PER_FP_WORD
)
1310 || (PAIRED_SIMD_REGNO_P (regno
) && TARGET_PAIRED_FLOAT
1311 && PAIRED_VECTOR_MODE (mode
)));
1313 /* The CR register can only hold CC modes. */
1314 if (CR_REGNO_P (regno
))
1315 return GET_MODE_CLASS (mode
) == MODE_CC
;
1317 if (XER_REGNO_P (regno
))
1318 return mode
== PSImode
;
1320 /* AltiVec only in AldyVec registers. */
1321 if (ALTIVEC_REGNO_P (regno
))
1322 return ALTIVEC_VECTOR_MODE (mode
);
1324 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1325 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1328 /* We cannot put TImode anywhere except general register and it must be
1329 able to fit within the register set. */
1331 return GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
;
1334 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1336 rs6000_init_hard_regno_mode_ok (void)
1340 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
1341 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1342 if (rs6000_hard_regno_mode_ok (r
, m
))
1343 rs6000_hard_regno_mode_ok_p
[m
][r
] = true;
1347 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
1350 darwin_rs6000_override_options (void)
1352 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
1354 rs6000_altivec_abi
= 1;
1355 TARGET_ALTIVEC_VRSAVE
= 1;
1356 if (DEFAULT_ABI
== ABI_DARWIN
)
1358 if (MACHO_DYNAMIC_NO_PIC_P
)
1361 warning (0, "-mdynamic-no-pic overrides -fpic or -fPIC");
1364 else if (flag_pic
== 1)
1369 if (TARGET_64BIT
&& ! TARGET_POWERPC64
)
1371 target_flags
|= MASK_POWERPC64
;
1372 warning (0, "-m64 requires PowerPC64 architecture, enabling");
1376 rs6000_default_long_calls
= 1;
1377 target_flags
|= MASK_SOFT_FLOAT
;
1380 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
1382 if (!flag_mkernel
&& !flag_apple_kext
1384 && ! (target_flags_explicit
& MASK_ALTIVEC
))
1385 target_flags
|= MASK_ALTIVEC
;
1387 /* Unless the user (not the configurer) has explicitly overridden
1388 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
1389 G4 unless targetting the kernel. */
1392 && strverscmp (darwin_macosx_version_min
, "10.5") >= 0
1393 && ! (target_flags_explicit
& MASK_ALTIVEC
)
1394 && ! rs6000_select
[1].string
)
1396 target_flags
|= MASK_ALTIVEC
;
1401 /* If not otherwise specified by a target, make 'long double' equivalent to
1404 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1405 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1408 /* Override command line options. Mostly we process the processor
1409 type and sometimes adjust other TARGET_ options. */
1412 rs6000_override_options (const char *default_cpu
)
1415 struct rs6000_cpu_select
*ptr
;
1418 /* Simplifications for entries below. */
1421 POWERPC_BASE_MASK
= MASK_POWERPC
| MASK_NEW_MNEMONICS
,
1422 POWERPC_7400_MASK
= POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_ALTIVEC
1425 /* This table occasionally claims that a processor does not support
1426 a particular feature even though it does, but the feature is slower
1427 than the alternative. Thus, it shouldn't be relied on as a
1428 complete description of the processor's support.
1430 Please keep this list in order, and don't forget to update the
1431 documentation in invoke.texi when adding a new processor or
1435 const char *const name
; /* Canonical processor name. */
1436 const enum processor_type processor
; /* Processor type enum value. */
1437 const int target_enable
; /* Target flags to enable. */
1438 } const processor_target_table
[]
1439 = {{"401", PROCESSOR_PPC403
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1440 {"403", PROCESSOR_PPC403
,
1441 POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
| MASK_STRICT_ALIGN
},
1442 {"405", PROCESSOR_PPC405
,
1443 POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
| MASK_MULHW
| MASK_DLMZB
},
1444 {"405fp", PROCESSOR_PPC405
,
1445 POWERPC_BASE_MASK
| MASK_MULHW
| MASK_DLMZB
},
1446 {"440", PROCESSOR_PPC440
,
1447 POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
| MASK_MULHW
| MASK_DLMZB
},
1448 {"440fp", PROCESSOR_PPC440
,
1449 POWERPC_BASE_MASK
| MASK_MULHW
| MASK_DLMZB
},
1450 {"464", PROCESSOR_PPC440
,
1451 POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
| MASK_MULHW
| MASK_DLMZB
},
1452 {"464fp", PROCESSOR_PPC440
,
1453 POWERPC_BASE_MASK
| MASK_MULHW
| MASK_DLMZB
},
1454 {"505", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
},
1455 {"601", PROCESSOR_PPC601
,
1456 MASK_POWER
| POWERPC_BASE_MASK
| MASK_MULTIPLE
| MASK_STRING
},
1457 {"602", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1458 {"603", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1459 {"603e", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1460 {"604", PROCESSOR_PPC604
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1461 {"604e", PROCESSOR_PPC604e
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1462 {"620", PROCESSOR_PPC620
,
1463 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1464 {"630", PROCESSOR_PPC630
,
1465 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1466 {"740", PROCESSOR_PPC750
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1467 {"7400", PROCESSOR_PPC7400
, POWERPC_7400_MASK
},
1468 {"7450", PROCESSOR_PPC7450
, POWERPC_7400_MASK
},
1469 {"750", PROCESSOR_PPC750
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1470 {"801", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1471 {"821", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1472 {"823", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1473 {"8540", PROCESSOR_PPC8540
, POWERPC_BASE_MASK
| MASK_STRICT_ALIGN
},
1474 /* 8548 has a dummy entry for now. */
1475 {"8548", PROCESSOR_PPC8540
, POWERPC_BASE_MASK
| MASK_STRICT_ALIGN
},
1476 {"e300c2", PROCESSOR_PPCE300C2
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1477 {"e300c3", PROCESSOR_PPCE300C3
, POWERPC_BASE_MASK
},
1478 {"e500mc", PROCESSOR_PPCE500MC
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1479 {"860", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1480 {"970", PROCESSOR_POWER4
,
1481 POWERPC_7400_MASK
| MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1482 {"cell", PROCESSOR_CELL
,
1483 POWERPC_7400_MASK
| MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1484 {"common", PROCESSOR_COMMON
, MASK_NEW_MNEMONICS
},
1485 {"ec603e", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1486 {"G3", PROCESSOR_PPC750
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1487 {"G4", PROCESSOR_PPC7450
, POWERPC_7400_MASK
},
1488 {"G5", PROCESSOR_POWER4
,
1489 POWERPC_7400_MASK
| MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1490 {"power", PROCESSOR_POWER
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1491 {"power2", PROCESSOR_POWER
,
1492 MASK_POWER
| MASK_POWER2
| MASK_MULTIPLE
| MASK_STRING
},
1493 {"power3", PROCESSOR_PPC630
,
1494 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1495 {"power4", PROCESSOR_POWER4
,
1496 POWERPC_BASE_MASK
| MASK_POWERPC64
| MASK_PPC_GPOPT
| MASK_PPC_GFXOPT
1498 {"power5", PROCESSOR_POWER5
,
1499 POWERPC_BASE_MASK
| MASK_POWERPC64
| MASK_PPC_GPOPT
| MASK_PPC_GFXOPT
1500 | MASK_MFCRF
| MASK_POPCNTB
},
1501 {"power5+", PROCESSOR_POWER5
,
1502 POWERPC_BASE_MASK
| MASK_POWERPC64
| MASK_PPC_GPOPT
| MASK_PPC_GFXOPT
1503 | MASK_MFCRF
| MASK_POPCNTB
| MASK_FPRND
},
1504 {"power6", PROCESSOR_POWER6
,
1505 POWERPC_7400_MASK
| MASK_POWERPC64
| MASK_PPC_GPOPT
| MASK_MFCRF
1506 | MASK_POPCNTB
| MASK_FPRND
| MASK_CMPB
| MASK_DFP
},
1507 {"power6x", PROCESSOR_POWER6
,
1508 POWERPC_7400_MASK
| MASK_POWERPC64
| MASK_PPC_GPOPT
| MASK_MFCRF
1509 | MASK_POPCNTB
| MASK_FPRND
| MASK_CMPB
| MASK_DFP
| MASK_MFPGPR
},
1510 {"power7", PROCESSOR_POWER5
,
1511 POWERPC_7400_MASK
| MASK_POWERPC64
| MASK_PPC_GPOPT
| MASK_MFCRF
1512 | MASK_POPCNTB
| MASK_FPRND
| MASK_CMPB
| MASK_DFP
},
1513 {"powerpc", PROCESSOR_POWERPC
, POWERPC_BASE_MASK
},
1514 {"powerpc64", PROCESSOR_POWERPC64
,
1515 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1516 {"rios", PROCESSOR_RIOS1
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1517 {"rios1", PROCESSOR_RIOS1
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1518 {"rios2", PROCESSOR_RIOS2
,
1519 MASK_POWER
| MASK_POWER2
| MASK_MULTIPLE
| MASK_STRING
},
1520 {"rsc", PROCESSOR_PPC601
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1521 {"rsc1", PROCESSOR_PPC601
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1522 {"rs64", PROCESSOR_RS64A
,
1523 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
}
1526 const size_t ptt_size
= ARRAY_SIZE (processor_target_table
);
1528 /* Some OSs don't support saving the high part of 64-bit registers on
1529 context switch. Other OSs don't support saving Altivec registers.
1530 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1531 settings; if the user wants either, the user must explicitly specify
1532 them and we won't interfere with the user's specification. */
1535 POWER_MASKS
= MASK_POWER
| MASK_POWER2
| MASK_MULTIPLE
| MASK_STRING
,
1536 POWERPC_MASKS
= (POWERPC_BASE_MASK
| MASK_PPC_GPOPT
| MASK_STRICT_ALIGN
1537 | MASK_PPC_GFXOPT
| MASK_POWERPC64
| MASK_ALTIVEC
1538 | MASK_MFCRF
| MASK_POPCNTB
| MASK_FPRND
| MASK_MULHW
1539 | MASK_DLMZB
| MASK_CMPB
| MASK_MFPGPR
| MASK_DFP
)
1542 rs6000_init_hard_regno_mode_ok ();
1544 set_masks
= POWER_MASKS
| POWERPC_MASKS
| MASK_SOFT_FLOAT
;
1545 #ifdef OS_MISSING_POWERPC64
1546 if (OS_MISSING_POWERPC64
)
1547 set_masks
&= ~MASK_POWERPC64
;
1549 #ifdef OS_MISSING_ALTIVEC
1550 if (OS_MISSING_ALTIVEC
)
1551 set_masks
&= ~MASK_ALTIVEC
;
1554 /* Don't override by the processor default if given explicitly. */
1555 set_masks
&= ~target_flags_explicit
;
1557 /* Identify the processor type. */
1558 rs6000_select
[0].string
= default_cpu
;
1559 rs6000_cpu
= TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
;
1561 for (i
= 0; i
< ARRAY_SIZE (rs6000_select
); i
++)
1563 ptr
= &rs6000_select
[i
];
1564 if (ptr
->string
!= (char *)0 && ptr
->string
[0] != '\0')
1566 for (j
= 0; j
< ptt_size
; j
++)
1567 if (! strcmp (ptr
->string
, processor_target_table
[j
].name
))
1569 if (ptr
->set_tune_p
)
1570 rs6000_cpu
= processor_target_table
[j
].processor
;
1572 if (ptr
->set_arch_p
)
1574 target_flags
&= ~set_masks
;
1575 target_flags
|= (processor_target_table
[j
].target_enable
1582 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
1586 if ((TARGET_E500
|| rs6000_cpu
== PROCESSOR_PPCE500MC
)
1587 && !rs6000_explicit_options
.isel
)
1590 if (rs6000_cpu
== PROCESSOR_PPCE300C2
|| rs6000_cpu
== PROCESSOR_PPCE300C3
1591 || rs6000_cpu
== PROCESSOR_PPCE500MC
)
1594 error ("AltiVec not supported in this target");
1596 error ("Spe not supported in this target");
1599 /* If we are optimizing big endian systems for space, use the load/store
1600 multiple and string instructions. */
1601 if (BYTES_BIG_ENDIAN
&& optimize_size
)
1602 target_flags
|= ~target_flags_explicit
& (MASK_MULTIPLE
| MASK_STRING
);
1604 /* Don't allow -mmultiple or -mstring on little endian systems
1605 unless the cpu is a 750, because the hardware doesn't support the
1606 instructions used in little endian mode, and causes an alignment
1607 trap. The 750 does not cause an alignment trap (except when the
1608 target is unaligned). */
1610 if (!BYTES_BIG_ENDIAN
&& rs6000_cpu
!= PROCESSOR_PPC750
)
1612 if (TARGET_MULTIPLE
)
1614 target_flags
&= ~MASK_MULTIPLE
;
1615 if ((target_flags_explicit
& MASK_MULTIPLE
) != 0)
1616 warning (0, "-mmultiple is not supported on little endian systems");
1621 target_flags
&= ~MASK_STRING
;
1622 if ((target_flags_explicit
& MASK_STRING
) != 0)
1623 warning (0, "-mstring is not supported on little endian systems");
1627 /* Set debug flags */
1628 if (rs6000_debug_name
)
1630 if (! strcmp (rs6000_debug_name
, "all"))
1631 rs6000_debug_stack
= rs6000_debug_arg
= 1;
1632 else if (! strcmp (rs6000_debug_name
, "stack"))
1633 rs6000_debug_stack
= 1;
1634 else if (! strcmp (rs6000_debug_name
, "arg"))
1635 rs6000_debug_arg
= 1;
1637 error ("unknown -mdebug-%s switch", rs6000_debug_name
);
1640 if (rs6000_traceback_name
)
1642 if (! strncmp (rs6000_traceback_name
, "full", 4))
1643 rs6000_traceback
= traceback_full
;
1644 else if (! strncmp (rs6000_traceback_name
, "part", 4))
1645 rs6000_traceback
= traceback_part
;
1646 else if (! strncmp (rs6000_traceback_name
, "no", 2))
1647 rs6000_traceback
= traceback_none
;
1649 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1650 rs6000_traceback_name
);
1653 if (!rs6000_explicit_options
.long_double
)
1654 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
1656 #ifndef POWERPC_LINUX
1657 if (!rs6000_explicit_options
.ieee
)
1658 rs6000_ieeequad
= 1;
1661 /* Enable Altivec ABI for AIX -maltivec. */
1662 if (TARGET_XCOFF
&& TARGET_ALTIVEC
)
1663 rs6000_altivec_abi
= 1;
1665 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
1666 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
1667 be explicitly overridden in either case. */
1670 if (!rs6000_explicit_options
.altivec_abi
1671 && (TARGET_64BIT
|| TARGET_ALTIVEC
))
1672 rs6000_altivec_abi
= 1;
1674 /* Enable VRSAVE for AltiVec ABI, unless explicitly overridden. */
1675 if (!rs6000_explicit_options
.vrsave
)
1676 TARGET_ALTIVEC_VRSAVE
= rs6000_altivec_abi
;
1679 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1680 if (DEFAULT_ABI
== ABI_DARWIN
&& TARGET_64BIT
)
1682 rs6000_darwin64_abi
= 1;
1684 darwin_one_byte_bool
= 1;
1686 /* Default to natural alignment, for better performance. */
1687 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
1690 /* Place FP constants in the constant pool instead of TOC
1691 if section anchors enabled. */
1692 if (flag_section_anchors
)
1693 TARGET_NO_FP_IN_TOC
= 1;
1695 /* Handle -mtls-size option. */
1696 rs6000_parse_tls_size_option ();
1698 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1699 SUBTARGET_OVERRIDE_OPTIONS
;
1701 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1702 SUBSUBTARGET_OVERRIDE_OPTIONS
;
1704 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1705 SUB3TARGET_OVERRIDE_OPTIONS
;
1708 if (TARGET_E500
|| rs6000_cpu
== PROCESSOR_PPCE500MC
)
1710 /* The e500 and e500mc do not have string instructions, and we set
1711 MASK_STRING above when optimizing for size. */
1712 if ((target_flags
& MASK_STRING
) != 0)
1713 target_flags
= target_flags
& ~MASK_STRING
;
1715 else if (rs6000_select
[1].string
!= NULL
)
1717 /* For the powerpc-eabispe configuration, we set all these by
1718 default, so let's unset them if we manually set another
1719 CPU that is not the E500. */
1720 if (!rs6000_explicit_options
.spe_abi
)
1722 if (!rs6000_explicit_options
.spe
)
1724 if (!rs6000_explicit_options
.float_gprs
)
1725 rs6000_float_gprs
= 0;
1726 if (!rs6000_explicit_options
.isel
)
1730 /* Detect invalid option combinations with E500. */
1733 rs6000_always_hint
= (rs6000_cpu
!= PROCESSOR_POWER4
1734 && rs6000_cpu
!= PROCESSOR_POWER5
1735 && rs6000_cpu
!= PROCESSOR_POWER6
1736 && rs6000_cpu
!= PROCESSOR_CELL
);
1737 rs6000_sched_groups
= (rs6000_cpu
== PROCESSOR_POWER4
1738 || rs6000_cpu
== PROCESSOR_POWER5
);
1739 rs6000_align_branch_targets
= (rs6000_cpu
== PROCESSOR_POWER4
1740 || rs6000_cpu
== PROCESSOR_POWER5
1741 || rs6000_cpu
== PROCESSOR_POWER6
);
1743 rs6000_sched_restricted_insns_priority
1744 = (rs6000_sched_groups
? 1 : 0);
1746 /* Handle -msched-costly-dep option. */
1747 rs6000_sched_costly_dep
1748 = (rs6000_sched_groups
? store_to_load_dep_costly
: no_dep_costly
);
1750 if (rs6000_sched_costly_dep_str
)
1752 if (! strcmp (rs6000_sched_costly_dep_str
, "no"))
1753 rs6000_sched_costly_dep
= no_dep_costly
;
1754 else if (! strcmp (rs6000_sched_costly_dep_str
, "all"))
1755 rs6000_sched_costly_dep
= all_deps_costly
;
1756 else if (! strcmp (rs6000_sched_costly_dep_str
, "true_store_to_load"))
1757 rs6000_sched_costly_dep
= true_store_to_load_dep_costly
;
1758 else if (! strcmp (rs6000_sched_costly_dep_str
, "store_to_load"))
1759 rs6000_sched_costly_dep
= store_to_load_dep_costly
;
1761 rs6000_sched_costly_dep
= atoi (rs6000_sched_costly_dep_str
);
1764 /* Handle -minsert-sched-nops option. */
1765 rs6000_sched_insert_nops
1766 = (rs6000_sched_groups
? sched_finish_regroup_exact
: sched_finish_none
);
1768 if (rs6000_sched_insert_nops_str
)
1770 if (! strcmp (rs6000_sched_insert_nops_str
, "no"))
1771 rs6000_sched_insert_nops
= sched_finish_none
;
1772 else if (! strcmp (rs6000_sched_insert_nops_str
, "pad"))
1773 rs6000_sched_insert_nops
= sched_finish_pad_groups
;
1774 else if (! strcmp (rs6000_sched_insert_nops_str
, "regroup_exact"))
1775 rs6000_sched_insert_nops
= sched_finish_regroup_exact
;
1777 rs6000_sched_insert_nops
= atoi (rs6000_sched_insert_nops_str
);
1780 #ifdef TARGET_REGNAMES
1781 /* If the user desires alternate register names, copy in the
1782 alternate names now. */
1783 if (TARGET_REGNAMES
)
1784 memcpy (rs6000_reg_names
, alt_reg_names
, sizeof (rs6000_reg_names
));
1787 /* Set aix_struct_return last, after the ABI is determined.
1788 If -maix-struct-return or -msvr4-struct-return was explicitly
1789 used, don't override with the ABI default. */
1790 if (!rs6000_explicit_options
.aix_struct_ret
)
1791 aix_struct_return
= (DEFAULT_ABI
!= ABI_V4
|| DRAFT_V4_STRUCT_RET
);
1793 if (TARGET_LONG_DOUBLE_128
&& !TARGET_IEEEQUAD
)
1794 REAL_MODE_FORMAT (TFmode
) = &ibm_extended_format
;
1797 ASM_GENERATE_INTERNAL_LABEL (toc_label_name
, "LCTOC", 1);
1799 /* We can only guarantee the availability of DI pseudo-ops when
1800 assembling for 64-bit targets. */
1803 targetm
.asm_out
.aligned_op
.di
= NULL
;
1804 targetm
.asm_out
.unaligned_op
.di
= NULL
;
1807 /* Set branch target alignment, if not optimizing for size. */
1810 /* Cell wants to be aligned 8byte for dual issue. */
1811 if (rs6000_cpu
== PROCESSOR_CELL
)
1813 if (align_functions
<= 0)
1814 align_functions
= 8;
1815 if (align_jumps
<= 0)
1817 if (align_loops
<= 0)
1820 if (rs6000_align_branch_targets
)
1822 if (align_functions
<= 0)
1823 align_functions
= 16;
1824 if (align_jumps
<= 0)
1826 if (align_loops
<= 0)
1829 if (align_jumps_max_skip
<= 0)
1830 align_jumps_max_skip
= 15;
1831 if (align_loops_max_skip
<= 0)
1832 align_loops_max_skip
= 15;
1835 /* Arrange to save and restore machine status around nested functions. */
1836 init_machine_status
= rs6000_init_machine_status
;
1838 /* We should always be splitting complex arguments, but we can't break
1839 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1840 if (DEFAULT_ABI
!= ABI_AIX
)
1841 targetm
.calls
.split_complex_arg
= NULL
;
1843 /* Initialize rs6000_cost with the appropriate target costs. */
1845 rs6000_cost
= TARGET_POWERPC64
? &size64_cost
: &size32_cost
;
1849 case PROCESSOR_RIOS1
:
1850 rs6000_cost
= &rios1_cost
;
1853 case PROCESSOR_RIOS2
:
1854 rs6000_cost
= &rios2_cost
;
1857 case PROCESSOR_RS64A
:
1858 rs6000_cost
= &rs64a_cost
;
1861 case PROCESSOR_MPCCORE
:
1862 rs6000_cost
= &mpccore_cost
;
1865 case PROCESSOR_PPC403
:
1866 rs6000_cost
= &ppc403_cost
;
1869 case PROCESSOR_PPC405
:
1870 rs6000_cost
= &ppc405_cost
;
1873 case PROCESSOR_PPC440
:
1874 rs6000_cost
= &ppc440_cost
;
1877 case PROCESSOR_PPC601
:
1878 rs6000_cost
= &ppc601_cost
;
1881 case PROCESSOR_PPC603
:
1882 rs6000_cost
= &ppc603_cost
;
1885 case PROCESSOR_PPC604
:
1886 rs6000_cost
= &ppc604_cost
;
1889 case PROCESSOR_PPC604e
:
1890 rs6000_cost
= &ppc604e_cost
;
1893 case PROCESSOR_PPC620
:
1894 rs6000_cost
= &ppc620_cost
;
1897 case PROCESSOR_PPC630
:
1898 rs6000_cost
= &ppc630_cost
;
1901 case PROCESSOR_CELL
:
1902 rs6000_cost
= &ppccell_cost
;
1905 case PROCESSOR_PPC750
:
1906 case PROCESSOR_PPC7400
:
1907 rs6000_cost
= &ppc750_cost
;
1910 case PROCESSOR_PPC7450
:
1911 rs6000_cost
= &ppc7450_cost
;
1914 case PROCESSOR_PPC8540
:
1915 rs6000_cost
= &ppc8540_cost
;
1918 case PROCESSOR_PPCE300C2
:
1919 case PROCESSOR_PPCE300C3
:
1920 rs6000_cost
= &ppce300c2c3_cost
;
1923 case PROCESSOR_PPCE500MC
:
1924 rs6000_cost
= &ppce500mc_cost
;
1927 case PROCESSOR_POWER4
:
1928 case PROCESSOR_POWER5
:
1929 rs6000_cost
= &power4_cost
;
1932 case PROCESSOR_POWER6
:
1933 rs6000_cost
= &power6_cost
;
1940 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES
))
1941 set_param_value ("simultaneous-prefetches",
1942 rs6000_cost
->simultaneous_prefetches
);
1943 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE
))
1944 set_param_value ("l1-cache-size", rs6000_cost
->l1_cache_size
);
1945 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE
))
1946 set_param_value ("l1-cache-line-size", rs6000_cost
->cache_line_size
);
1947 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE
))
1948 set_param_value ("l2-cache-size", rs6000_cost
->l2_cache_size
);
1950 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
1951 can be optimized to ap = __builtin_next_arg (0). */
1952 if (DEFAULT_ABI
!= ABI_V4
)
1953 targetm
.expand_builtin_va_start
= NULL
;
1956 /* Implement targetm.vectorize.builtin_mask_for_load. */
1958 rs6000_builtin_mask_for_load (void)
1961 return altivec_builtin_mask_for_load
;
1966 /* Implement targetm.vectorize.builtin_conversion.
1967 Returns a decl of a function that implements conversion of an integer vector
1968 into a floating-point vector, or vice-versa. TYPE is the type of the integer
1969 side of the conversion.
1970 Return NULL_TREE if it is not available. */
1972 rs6000_builtin_conversion (enum tree_code code
, tree type
)
1974 if (!TARGET_ALTIVEC
)
1979 case FIX_TRUNC_EXPR
:
1980 switch (TYPE_MODE (type
))
1983 return TYPE_UNSIGNED (type
)
1984 ? rs6000_builtin_decls
[ALTIVEC_BUILTIN_VCTUXS
]
1985 : rs6000_builtin_decls
[ALTIVEC_BUILTIN_VCTSXS
];
1991 switch (TYPE_MODE (type
))
1994 return TYPE_UNSIGNED (type
)
1995 ? rs6000_builtin_decls
[ALTIVEC_BUILTIN_VCFUX
]
1996 : rs6000_builtin_decls
[ALTIVEC_BUILTIN_VCFSX
];
2006 /* Implement targetm.vectorize.builtin_mul_widen_even. */
2008 rs6000_builtin_mul_widen_even (tree type
)
2010 if (!TARGET_ALTIVEC
)
2013 switch (TYPE_MODE (type
))
2016 return TYPE_UNSIGNED (type
)
2017 ? rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULEUH
]
2018 : rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULESH
];
2021 return TYPE_UNSIGNED (type
)
2022 ? rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULEUB
]
2023 : rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULESB
];
2029 /* Implement targetm.vectorize.builtin_mul_widen_odd. */
2031 rs6000_builtin_mul_widen_odd (tree type
)
2033 if (!TARGET_ALTIVEC
)
2036 switch (TYPE_MODE (type
))
2039 return TYPE_UNSIGNED (type
)
2040 ? rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULOUH
]
2041 : rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULOSH
];
2044 return TYPE_UNSIGNED (type
)
2045 ? rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULOUB
]
2046 : rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULOSB
];
2053 /* Return true iff, data reference of TYPE can reach vector alignment (16)
2054 after applying N number of iterations. This routine does not determine
2055 how may iterations are required to reach desired alignment. */
2058 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED
, bool is_packed
)
2065 if (rs6000_alignment_flags
== MASK_ALIGN_NATURAL
)
2068 if (rs6000_alignment_flags
== MASK_ALIGN_POWER
)
2078 /* Assuming that all other types are naturally aligned. CHECKME! */
2083 /* Handle generic options of the form -mfoo=yes/no.
2084 NAME is the option name.
2085 VALUE is the option value.
2086 FLAG is the pointer to the flag where to store a 1 or 0, depending on
2087 whether the option value is 'yes' or 'no' respectively. */
2089 rs6000_parse_yes_no_option (const char *name
, const char *value
, int *flag
)
2093 else if (!strcmp (value
, "yes"))
2095 else if (!strcmp (value
, "no"))
2098 error ("unknown -m%s= option specified: '%s'", name
, value
);
2101 /* Validate and record the size specified with the -mtls-size option. */
2104 rs6000_parse_tls_size_option (void)
2106 if (rs6000_tls_size_string
== 0)
2108 else if (strcmp (rs6000_tls_size_string
, "16") == 0)
2109 rs6000_tls_size
= 16;
2110 else if (strcmp (rs6000_tls_size_string
, "32") == 0)
2111 rs6000_tls_size
= 32;
2112 else if (strcmp (rs6000_tls_size_string
, "64") == 0)
2113 rs6000_tls_size
= 64;
2115 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string
);
2119 optimization_options (int level ATTRIBUTE_UNUSED
, int size ATTRIBUTE_UNUSED
)
2121 if (DEFAULT_ABI
== ABI_DARWIN
)
2122 /* The Darwin libraries never set errno, so we might as well
2123 avoid calling them when that's the only reason we would. */
2124 flag_errno_math
= 0;
2126 /* Double growth factor to counter reduced min jump length. */
2127 set_param_value ("max-grow-copy-bb-insns", 16);
2129 /* Enable section anchors by default.
2130 Skip section anchors for Objective C and Objective C++
2131 until front-ends fixed. */
2132 if (!TARGET_MACHO
&& lang_hooks
.name
[4] != 'O')
2133 flag_section_anchors
= 2;
2136 /* Implement TARGET_HANDLE_OPTION. */
2139 rs6000_handle_option (size_t code
, const char *arg
, int value
)
2144 target_flags
&= ~(MASK_POWER
| MASK_POWER2
2145 | MASK_MULTIPLE
| MASK_STRING
);
2146 target_flags_explicit
|= (MASK_POWER
| MASK_POWER2
2147 | MASK_MULTIPLE
| MASK_STRING
);
2149 case OPT_mno_powerpc
:
2150 target_flags
&= ~(MASK_POWERPC
| MASK_PPC_GPOPT
2151 | MASK_PPC_GFXOPT
| MASK_POWERPC64
);
2152 target_flags_explicit
|= (MASK_POWERPC
| MASK_PPC_GPOPT
2153 | MASK_PPC_GFXOPT
| MASK_POWERPC64
);
2156 target_flags
&= ~MASK_MINIMAL_TOC
;
2157 TARGET_NO_FP_IN_TOC
= 0;
2158 TARGET_NO_SUM_IN_TOC
= 0;
2159 target_flags_explicit
|= MASK_MINIMAL_TOC
;
2160 #ifdef TARGET_USES_SYSV4_OPT
2161 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
2162 just the same as -mminimal-toc. */
2163 target_flags
|= MASK_MINIMAL_TOC
;
2164 target_flags_explicit
|= MASK_MINIMAL_TOC
;
2168 #ifdef TARGET_USES_SYSV4_OPT
2170 /* Make -mtoc behave like -mminimal-toc. */
2171 target_flags
|= MASK_MINIMAL_TOC
;
2172 target_flags_explicit
|= MASK_MINIMAL_TOC
;
2176 #ifdef TARGET_USES_AIX64_OPT
2181 target_flags
|= MASK_POWERPC64
| MASK_POWERPC
;
2182 target_flags
|= ~target_flags_explicit
& MASK_PPC_GFXOPT
;
2183 target_flags_explicit
|= MASK_POWERPC64
| MASK_POWERPC
;
2186 #ifdef TARGET_USES_AIX64_OPT
2191 target_flags
&= ~MASK_POWERPC64
;
2192 target_flags_explicit
|= MASK_POWERPC64
;
2195 case OPT_minsert_sched_nops_
:
2196 rs6000_sched_insert_nops_str
= arg
;
2199 case OPT_mminimal_toc
:
2202 TARGET_NO_FP_IN_TOC
= 0;
2203 TARGET_NO_SUM_IN_TOC
= 0;
2210 target_flags
|= (MASK_MULTIPLE
| MASK_STRING
);
2211 target_flags_explicit
|= (MASK_MULTIPLE
| MASK_STRING
);
2218 target_flags
|= (MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
);
2219 target_flags_explicit
|= (MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
);
2223 case OPT_mpowerpc_gpopt
:
2224 case OPT_mpowerpc_gfxopt
:
2227 target_flags
|= MASK_POWERPC
;
2228 target_flags_explicit
|= MASK_POWERPC
;
2232 case OPT_maix_struct_return
:
2233 case OPT_msvr4_struct_return
:
2234 rs6000_explicit_options
.aix_struct_ret
= true;
2238 rs6000_explicit_options
.vrsave
= true;
2239 rs6000_parse_yes_no_option ("vrsave", arg
, &(TARGET_ALTIVEC_VRSAVE
));
2243 rs6000_explicit_options
.isel
= true;
2244 rs6000_isel
= value
;
2248 rs6000_explicit_options
.isel
= true;
2249 rs6000_parse_yes_no_option ("isel", arg
, &(rs6000_isel
));
2253 rs6000_explicit_options
.spe
= true;
2258 rs6000_explicit_options
.spe
= true;
2259 rs6000_parse_yes_no_option ("spe", arg
, &(rs6000_spe
));
2263 rs6000_debug_name
= arg
;
2266 #ifdef TARGET_USES_SYSV4_OPT
2268 rs6000_abi_name
= arg
;
2272 rs6000_sdata_name
= arg
;
2275 case OPT_mtls_size_
:
2276 rs6000_tls_size_string
= arg
;
2279 case OPT_mrelocatable
:
2282 target_flags
|= MASK_MINIMAL_TOC
;
2283 target_flags_explicit
|= MASK_MINIMAL_TOC
;
2284 TARGET_NO_FP_IN_TOC
= 1;
2288 case OPT_mrelocatable_lib
:
2291 target_flags
|= MASK_RELOCATABLE
| MASK_MINIMAL_TOC
;
2292 target_flags_explicit
|= MASK_RELOCATABLE
| MASK_MINIMAL_TOC
;
2293 TARGET_NO_FP_IN_TOC
= 1;
2297 target_flags
&= ~MASK_RELOCATABLE
;
2298 target_flags_explicit
|= MASK_RELOCATABLE
;
2304 if (!strcmp (arg
, "altivec"))
2306 rs6000_explicit_options
.altivec_abi
= true;
2307 rs6000_altivec_abi
= 1;
2309 /* Enabling the AltiVec ABI turns off the SPE ABI. */
2312 else if (! strcmp (arg
, "no-altivec"))
2314 rs6000_explicit_options
.altivec_abi
= true;
2315 rs6000_altivec_abi
= 0;
2317 else if (! strcmp (arg
, "spe"))
2319 rs6000_explicit_options
.spe_abi
= true;
2321 rs6000_altivec_abi
= 0;
2322 if (!TARGET_SPE_ABI
)
2323 error ("not configured for ABI: '%s'", arg
);
2325 else if (! strcmp (arg
, "no-spe"))
2327 rs6000_explicit_options
.spe_abi
= true;
2331 /* These are here for testing during development only, do not
2332 document in the manual please. */
2333 else if (! strcmp (arg
, "d64"))
2335 rs6000_darwin64_abi
= 1;
2336 warning (0, "Using darwin64 ABI");
2338 else if (! strcmp (arg
, "d32"))
2340 rs6000_darwin64_abi
= 0;
2341 warning (0, "Using old darwin ABI");
2344 else if (! strcmp (arg
, "ibmlongdouble"))
2346 rs6000_explicit_options
.ieee
= true;
2347 rs6000_ieeequad
= 0;
2348 warning (0, "Using IBM extended precision long double");
2350 else if (! strcmp (arg
, "ieeelongdouble"))
2352 rs6000_explicit_options
.ieee
= true;
2353 rs6000_ieeequad
= 1;
2354 warning (0, "Using IEEE extended precision long double");
2359 error ("unknown ABI specified: '%s'", arg
);
2365 rs6000_select
[1].string
= arg
;
2369 rs6000_select
[2].string
= arg
;
2372 case OPT_mtraceback_
:
2373 rs6000_traceback_name
= arg
;
2376 case OPT_mfloat_gprs_
:
2377 rs6000_explicit_options
.float_gprs
= true;
2378 if (! strcmp (arg
, "yes") || ! strcmp (arg
, "single"))
2379 rs6000_float_gprs
= 1;
2380 else if (! strcmp (arg
, "double"))
2381 rs6000_float_gprs
= 2;
2382 else if (! strcmp (arg
, "no"))
2383 rs6000_float_gprs
= 0;
2386 error ("invalid option for -mfloat-gprs: '%s'", arg
);
2391 case OPT_mlong_double_
:
2392 rs6000_explicit_options
.long_double
= true;
2393 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
2394 if (value
!= 64 && value
!= 128)
2396 error ("Unknown switch -mlong-double-%s", arg
);
2397 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
2401 rs6000_long_double_type_size
= value
;
2404 case OPT_msched_costly_dep_
:
2405 rs6000_sched_costly_dep_str
= arg
;
2409 rs6000_explicit_options
.alignment
= true;
2410 if (! strcmp (arg
, "power"))
2412 /* On 64-bit Darwin, power alignment is ABI-incompatible with
2413 some C library functions, so warn about it. The flag may be
2414 useful for performance studies from time to time though, so
2415 don't disable it entirely. */
2416 if (DEFAULT_ABI
== ABI_DARWIN
&& TARGET_64BIT
)
2417 warning (0, "-malign-power is not supported for 64-bit Darwin;"
2418 " it is incompatible with the installed C and C++ libraries");
2419 rs6000_alignment_flags
= MASK_ALIGN_POWER
;
2421 else if (! strcmp (arg
, "natural"))
2422 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
2425 error ("unknown -malign-XXXXX option specified: '%s'", arg
);
2433 /* Do anything needed at the start of the asm file. */
2436 rs6000_file_start (void)
2440 const char *start
= buffer
;
2441 struct rs6000_cpu_select
*ptr
;
2442 const char *default_cpu
= TARGET_CPU_DEFAULT
;
2443 FILE *file
= asm_out_file
;
2445 default_file_start ();
2447 #ifdef TARGET_BI_ARCH
2448 if ((TARGET_DEFAULT
^ target_flags
) & MASK_64BIT
)
2452 if (flag_verbose_asm
)
2454 sprintf (buffer
, "\n%s rs6000/powerpc options:", ASM_COMMENT_START
);
2455 rs6000_select
[0].string
= default_cpu
;
2457 for (i
= 0; i
< ARRAY_SIZE (rs6000_select
); i
++)
2459 ptr
= &rs6000_select
[i
];
2460 if (ptr
->string
!= (char *)0 && ptr
->string
[0] != '\0')
2462 fprintf (file
, "%s %s%s", start
, ptr
->name
, ptr
->string
);
2467 if (PPC405_ERRATUM77
)
2469 fprintf (file
, "%s PPC405CR_ERRATUM77", start
);
2473 #ifdef USING_ELFOS_H
2474 switch (rs6000_sdata
)
2476 case SDATA_NONE
: fprintf (file
, "%s -msdata=none", start
); start
= ""; break;
2477 case SDATA_DATA
: fprintf (file
, "%s -msdata=data", start
); start
= ""; break;
2478 case SDATA_SYSV
: fprintf (file
, "%s -msdata=sysv", start
); start
= ""; break;
2479 case SDATA_EABI
: fprintf (file
, "%s -msdata=eabi", start
); start
= ""; break;
2482 if (rs6000_sdata
&& g_switch_value
)
2484 fprintf (file
, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED
, start
,
2494 #ifdef HAVE_AS_GNU_ATTRIBUTE
2495 if (TARGET_32BIT
&& DEFAULT_ABI
== ABI_V4
)
2497 fprintf (file
, "\t.gnu_attribute 4, %d\n",
2498 (TARGET_HARD_FLOAT
&& TARGET_FPRS
) ? 1 : 2);
2499 fprintf (file
, "\t.gnu_attribute 8, %d\n",
2500 (TARGET_ALTIVEC_ABI
? 2
2501 : TARGET_SPE_ABI
? 3
2506 if (DEFAULT_ABI
== ABI_AIX
|| (TARGET_ELF
&& flag_pic
== 2))
2508 switch_to_section (toc_section
);
2509 switch_to_section (text_section
);
2514 /* Return nonzero if this function is known to have a null epilogue. */
2517 direct_return (void)
2519 if (reload_completed
)
2521 rs6000_stack_t
*info
= rs6000_stack_info ();
2523 if (info
->first_gp_reg_save
== 32
2524 && info
->first_fp_reg_save
== 64
2525 && info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
2526 && ! info
->lr_save_p
2527 && ! info
->cr_save_p
2528 && info
->vrsave_mask
== 0
2536 /* Return the number of instructions it takes to form a constant in an
2537 integer register. */
2540 num_insns_constant_wide (HOST_WIDE_INT value
)
2542 /* signed constant loadable with {cal|addi} */
2543 if ((unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000)
2546 /* constant loadable with {cau|addis} */
2547 else if ((value
& 0xffff) == 0
2548 && (value
>> 31 == -1 || value
>> 31 == 0))
2551 #if HOST_BITS_PER_WIDE_INT == 64
2552 else if (TARGET_POWERPC64
)
2554 HOST_WIDE_INT low
= ((value
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2555 HOST_WIDE_INT high
= value
>> 31;
2557 if (high
== 0 || high
== -1)
2563 return num_insns_constant_wide (high
) + 1;
2565 return (num_insns_constant_wide (high
)
2566 + num_insns_constant_wide (low
) + 1);
2575 num_insns_constant (rtx op
, enum machine_mode mode
)
2577 HOST_WIDE_INT low
, high
;
2579 switch (GET_CODE (op
))
2582 #if HOST_BITS_PER_WIDE_INT == 64
2583 if ((INTVAL (op
) >> 31) != 0 && (INTVAL (op
) >> 31) != -1
2584 && mask64_operand (op
, mode
))
2588 return num_insns_constant_wide (INTVAL (op
));
2591 if (mode
== SFmode
|| mode
== SDmode
)
2596 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
2597 if (DECIMAL_FLOAT_MODE_P (mode
))
2598 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
2600 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
2601 return num_insns_constant_wide ((HOST_WIDE_INT
) l
);
2604 if (mode
== VOIDmode
|| mode
== DImode
)
2606 high
= CONST_DOUBLE_HIGH (op
);
2607 low
= CONST_DOUBLE_LOW (op
);
2614 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
2615 if (DECIMAL_FLOAT_MODE_P (mode
))
2616 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, l
);
2618 REAL_VALUE_TO_TARGET_DOUBLE (rv
, l
);
2619 high
= l
[WORDS_BIG_ENDIAN
== 0];
2620 low
= l
[WORDS_BIG_ENDIAN
!= 0];
2624 return (num_insns_constant_wide (low
)
2625 + num_insns_constant_wide (high
));
2628 if ((high
== 0 && low
>= 0)
2629 || (high
== -1 && low
< 0))
2630 return num_insns_constant_wide (low
);
2632 else if (mask64_operand (op
, mode
))
2636 return num_insns_constant_wide (high
) + 1;
2639 return (num_insns_constant_wide (high
)
2640 + num_insns_constant_wide (low
) + 1);
2648 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
2649 If the mode of OP is MODE_VECTOR_INT, this simply returns the
2650 corresponding element of the vector, but for V4SFmode and V2SFmode,
2651 the corresponding "float" is interpreted as an SImode integer. */
2653 static HOST_WIDE_INT
2654 const_vector_elt_as_int (rtx op
, unsigned int elt
)
2656 rtx tmp
= CONST_VECTOR_ELT (op
, elt
);
2657 if (GET_MODE (op
) == V4SFmode
2658 || GET_MODE (op
) == V2SFmode
)
2659 tmp
= gen_lowpart (SImode
, tmp
);
2660 return INTVAL (tmp
);
2663 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
2664 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
2665 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
2666 all items are set to the same value and contain COPIES replicas of the
2667 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
2668 operand and the others are set to the value of the operand's msb. */
2671 vspltis_constant (rtx op
, unsigned step
, unsigned copies
)
2673 enum machine_mode mode
= GET_MODE (op
);
2674 enum machine_mode inner
= GET_MODE_INNER (mode
);
2677 unsigned nunits
= GET_MODE_NUNITS (mode
);
2678 unsigned bitsize
= GET_MODE_BITSIZE (inner
);
2679 unsigned mask
= GET_MODE_MASK (inner
);
2681 HOST_WIDE_INT val
= const_vector_elt_as_int (op
, nunits
- 1);
2682 HOST_WIDE_INT splat_val
= val
;
2683 HOST_WIDE_INT msb_val
= val
> 0 ? 0 : -1;
2685 /* Construct the value to be splatted, if possible. If not, return 0. */
2686 for (i
= 2; i
<= copies
; i
*= 2)
2688 HOST_WIDE_INT small_val
;
2690 small_val
= splat_val
>> bitsize
;
2692 if (splat_val
!= ((small_val
<< bitsize
) | (small_val
& mask
)))
2694 splat_val
= small_val
;
2697 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
2698 if (EASY_VECTOR_15 (splat_val
))
2701 /* Also check if we can splat, and then add the result to itself. Do so if
2702 the value is positive, of if the splat instruction is using OP's mode;
2703 for splat_val < 0, the splat and the add should use the same mode. */
2704 else if (EASY_VECTOR_15_ADD_SELF (splat_val
)
2705 && (splat_val
>= 0 || (step
== 1 && copies
== 1)))
2711 /* Check if VAL is present in every STEP-th element, and the
2712 other elements are filled with its most significant bit. */
2713 for (i
= 0; i
< nunits
- 1; ++i
)
2715 HOST_WIDE_INT desired_val
;
2716 if (((i
+ 1) & (step
- 1)) == 0)
2719 desired_val
= msb_val
;
2721 if (desired_val
!= const_vector_elt_as_int (op
, i
))
2729 /* Return true if OP is of the given MODE and can be synthesized
2730 with a vspltisb, vspltish or vspltisw. */
2733 easy_altivec_constant (rtx op
, enum machine_mode mode
)
2735 unsigned step
, copies
;
2737 if (mode
== VOIDmode
)
2738 mode
= GET_MODE (op
);
2739 else if (mode
!= GET_MODE (op
))
2742 /* Start with a vspltisw. */
2743 step
= GET_MODE_NUNITS (mode
) / 4;
2746 if (vspltis_constant (op
, step
, copies
))
2749 /* Then try with a vspltish. */
2755 if (vspltis_constant (op
, step
, copies
))
2758 /* And finally a vspltisb. */
2764 if (vspltis_constant (op
, step
, copies
))
2770 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
2771 result is OP. Abort if it is not possible. */
2774 gen_easy_altivec_constant (rtx op
)
2776 enum machine_mode mode
= GET_MODE (op
);
2777 int nunits
= GET_MODE_NUNITS (mode
);
2778 rtx last
= CONST_VECTOR_ELT (op
, nunits
- 1);
2779 unsigned step
= nunits
/ 4;
2780 unsigned copies
= 1;
2782 /* Start with a vspltisw. */
2783 if (vspltis_constant (op
, step
, copies
))
2784 return gen_rtx_VEC_DUPLICATE (V4SImode
, gen_lowpart (SImode
, last
));
2786 /* Then try with a vspltish. */
2792 if (vspltis_constant (op
, step
, copies
))
2793 return gen_rtx_VEC_DUPLICATE (V8HImode
, gen_lowpart (HImode
, last
));
2795 /* And finally a vspltisb. */
2801 if (vspltis_constant (op
, step
, copies
))
2802 return gen_rtx_VEC_DUPLICATE (V16QImode
, gen_lowpart (QImode
, last
));
2808 output_vec_const_move (rtx
*operands
)
2811 enum machine_mode mode
;
2816 mode
= GET_MODE (dest
);
2821 if (zero_constant (vec
, mode
))
2822 return "vxor %0,%0,%0";
2824 splat_vec
= gen_easy_altivec_constant (vec
);
2825 gcc_assert (GET_CODE (splat_vec
) == VEC_DUPLICATE
);
2826 operands
[1] = XEXP (splat_vec
, 0);
2827 if (!EASY_VECTOR_15 (INTVAL (operands
[1])))
2830 switch (GET_MODE (splat_vec
))
2833 return "vspltisw %0,%1";
2836 return "vspltish %0,%1";
2839 return "vspltisb %0,%1";
2846 gcc_assert (TARGET_SPE
);
2848 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2849 pattern of V1DI, V4HI, and V2SF.
2851 FIXME: We should probably return # and add post reload
2852 splitters for these, but this way is so easy ;-). */
2853 cst
= INTVAL (CONST_VECTOR_ELT (vec
, 0));
2854 cst2
= INTVAL (CONST_VECTOR_ELT (vec
, 1));
2855 operands
[1] = CONST_VECTOR_ELT (vec
, 0);
2856 operands
[2] = CONST_VECTOR_ELT (vec
, 1);
2858 return "li %0,%1\n\tevmergelo %0,%0,%0";
2860 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2863 /* Initialize TARGET of vector PAIRED to VALS. */
2866 paired_expand_vector_init (rtx target
, rtx vals
)
2868 enum machine_mode mode
= GET_MODE (target
);
2869 int n_elts
= GET_MODE_NUNITS (mode
);
2871 rtx x
, new_rtx
, tmp
, constant_op
, op1
, op2
;
2874 for (i
= 0; i
< n_elts
; ++i
)
2876 x
= XVECEXP (vals
, 0, i
);
2877 if (!CONSTANT_P (x
))
2882 /* Load from constant pool. */
2883 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
2889 /* The vector is initialized only with non-constants. */
2890 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, XVECEXP (vals
, 0, 0),
2891 XVECEXP (vals
, 0, 1));
2893 emit_move_insn (target
, new_rtx
);
2897 /* One field is non-constant and the other one is a constant. Load the
2898 constant from the constant pool and use ps_merge instruction to
2899 construct the whole vector. */
2900 op1
= XVECEXP (vals
, 0, 0);
2901 op2
= XVECEXP (vals
, 0, 1);
2903 constant_op
= (CONSTANT_P (op1
)) ? op1
: op2
;
2905 tmp
= gen_reg_rtx (GET_MODE (constant_op
));
2906 emit_move_insn (tmp
, constant_op
);
2908 if (CONSTANT_P (op1
))
2909 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, tmp
, op2
);
2911 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, op1
, tmp
);
2913 emit_move_insn (target
, new_rtx
);
2917 paired_expand_vector_move (rtx operands
[])
2919 rtx op0
= operands
[0], op1
= operands
[1];
2921 emit_move_insn (op0
, op1
);
2924 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
2925 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
2926 operands for the relation operation COND. This is a recursive
2930 paired_emit_vector_compare (enum rtx_code rcode
,
2931 rtx dest
, rtx op0
, rtx op1
,
2932 rtx cc_op0
, rtx cc_op1
)
2934 rtx tmp
= gen_reg_rtx (V2SFmode
);
2935 rtx tmp1
, max
, min
, equal_zero
;
2937 gcc_assert (TARGET_PAIRED_FLOAT
);
2938 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
2944 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
2948 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
2949 emit_insn (gen_selv2sf4 (dest
, tmp
, op0
, op1
, CONST0_RTX (SFmode
)));
2953 paired_emit_vector_compare (GE
, dest
, op0
, op1
, cc_op1
, cc_op0
);
2956 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
2959 tmp1
= gen_reg_rtx (V2SFmode
);
2960 max
= gen_reg_rtx (V2SFmode
);
2961 min
= gen_reg_rtx (V2SFmode
);
2962 equal_zero
= gen_reg_rtx (V2SFmode
);
2964 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
2965 emit_insn (gen_selv2sf4
2966 (max
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
2967 emit_insn (gen_subv2sf3 (tmp
, cc_op1
, cc_op0
));
2968 emit_insn (gen_selv2sf4
2969 (min
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
2970 emit_insn (gen_subv2sf3 (tmp1
, min
, max
));
2971 emit_insn (gen_selv2sf4 (dest
, tmp1
, op0
, op1
, CONST0_RTX (SFmode
)));
2974 paired_emit_vector_compare (EQ
, dest
, op1
, op0
, cc_op0
, cc_op1
);
2977 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
2980 paired_emit_vector_compare (LT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
2983 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
2986 paired_emit_vector_compare (GT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
2995 /* Emit vector conditional expression.
2996 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
2997 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
3000 paired_emit_vector_cond_expr (rtx dest
, rtx op1
, rtx op2
,
3001 rtx cond
, rtx cc_op0
, rtx cc_op1
)
3003 enum rtx_code rcode
= GET_CODE (cond
);
3005 if (!TARGET_PAIRED_FLOAT
)
3008 paired_emit_vector_compare (rcode
, dest
, op1
, op2
, cc_op0
, cc_op1
);
3013 /* Initialize vector TARGET to VALS. */
3016 rs6000_expand_vector_init (rtx target
, rtx vals
)
3018 enum machine_mode mode
= GET_MODE (target
);
3019 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
3020 int n_elts
= GET_MODE_NUNITS (mode
);
3021 int n_var
= 0, one_var
= -1;
3022 bool all_same
= true, all_const_zero
= true;
3026 for (i
= 0; i
< n_elts
; ++i
)
3028 x
= XVECEXP (vals
, 0, i
);
3029 if (!CONSTANT_P (x
))
3030 ++n_var
, one_var
= i
;
3031 else if (x
!= CONST0_RTX (inner_mode
))
3032 all_const_zero
= false;
3034 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
3040 rtx const_vec
= gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0));
3041 if (mode
!= V4SFmode
&& all_const_zero
)
3043 /* Zero register. */
3044 emit_insn (gen_rtx_SET (VOIDmode
, target
,
3045 gen_rtx_XOR (mode
, target
, target
)));
3048 else if (mode
!= V4SFmode
&& easy_vector_constant (const_vec
, mode
))
3050 /* Splat immediate. */
3051 emit_insn (gen_rtx_SET (VOIDmode
, target
, const_vec
));
3055 ; /* Splat vector element. */
3058 /* Load from constant pool. */
3059 emit_move_insn (target
, const_vec
);
3064 /* Store value to stack temp. Load vector element. Splat. */
3067 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
), 0);
3068 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0),
3069 XVECEXP (vals
, 0, 0));
3070 x
= gen_rtx_UNSPEC (VOIDmode
,
3071 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
3072 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
3074 gen_rtx_SET (VOIDmode
,
3077 x
= gen_rtx_VEC_SELECT (inner_mode
, target
,
3078 gen_rtx_PARALLEL (VOIDmode
,
3079 gen_rtvec (1, const0_rtx
)));
3080 emit_insn (gen_rtx_SET (VOIDmode
, target
,
3081 gen_rtx_VEC_DUPLICATE (mode
, x
)));
3085 /* One field is non-constant. Load constant then overwrite
3089 rtx copy
= copy_rtx (vals
);
3091 /* Load constant part of vector, substitute neighboring value for
3093 XVECEXP (copy
, 0, one_var
) = XVECEXP (vals
, 0, (one_var
+ 1) % n_elts
);
3094 rs6000_expand_vector_init (target
, copy
);
3096 /* Insert variable. */
3097 rs6000_expand_vector_set (target
, XVECEXP (vals
, 0, one_var
), one_var
);
3101 /* Construct the vector in memory one field at a time
3102 and load the whole vector. */
3103 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
), 0);
3104 for (i
= 0; i
< n_elts
; i
++)
3105 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
3106 i
* GET_MODE_SIZE (inner_mode
)),
3107 XVECEXP (vals
, 0, i
));
3108 emit_move_insn (target
, mem
);
3111 /* Set field ELT of TARGET to VAL. */
3114 rs6000_expand_vector_set (rtx target
, rtx val
, int elt
)
3116 enum machine_mode mode
= GET_MODE (target
);
3117 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
3118 rtx reg
= gen_reg_rtx (mode
);
3120 int width
= GET_MODE_SIZE (inner_mode
);
3123 /* Load single variable value. */
3124 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
), 0);
3125 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0), val
);
3126 x
= gen_rtx_UNSPEC (VOIDmode
,
3127 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
3128 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
3130 gen_rtx_SET (VOIDmode
,
3134 /* Linear sequence. */
3135 mask
= gen_rtx_PARALLEL (V16QImode
, rtvec_alloc (16));
3136 for (i
= 0; i
< 16; ++i
)
3137 XVECEXP (mask
, 0, i
) = GEN_INT (i
);
3139 /* Set permute mask to insert element into target. */
3140 for (i
= 0; i
< width
; ++i
)
3141 XVECEXP (mask
, 0, elt
*width
+ i
)
3142 = GEN_INT (i
+ 0x10);
3143 x
= gen_rtx_CONST_VECTOR (V16QImode
, XVEC (mask
, 0));
3144 x
= gen_rtx_UNSPEC (mode
,
3145 gen_rtvec (3, target
, reg
,
3146 force_reg (V16QImode
, x
)),
3148 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
3151 /* Extract field ELT from VEC into TARGET. */
3154 rs6000_expand_vector_extract (rtx target
, rtx vec
, int elt
)
3156 enum machine_mode mode
= GET_MODE (vec
);
3157 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
3160 /* Allocate mode-sized buffer. */
3161 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
), 0);
3163 /* Add offset to field within buffer matching vector element. */
3164 mem
= adjust_address_nv (mem
, mode
, elt
* GET_MODE_SIZE (inner_mode
));
3166 /* Store single field into mode-sized buffer. */
3167 x
= gen_rtx_UNSPEC (VOIDmode
,
3168 gen_rtvec (1, const0_rtx
), UNSPEC_STVE
);
3169 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
3171 gen_rtx_SET (VOIDmode
,
3174 emit_move_insn (target
, adjust_address_nv (mem
, inner_mode
, 0));
3177 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
3178 implement ANDing by the mask IN. */
3180 build_mask64_2_operands (rtx in
, rtx
*out
)
3182 #if HOST_BITS_PER_WIDE_INT >= 64
3183 unsigned HOST_WIDE_INT c
, lsb
, m1
, m2
;
3186 gcc_assert (GET_CODE (in
) == CONST_INT
);
3191 /* Assume c initially something like 0x00fff000000fffff. The idea
3192 is to rotate the word so that the middle ^^^^^^ group of zeros
3193 is at the MS end and can be cleared with an rldicl mask. We then
3194 rotate back and clear off the MS ^^ group of zeros with a
3196 c
= ~c
; /* c == 0xff000ffffff00000 */
3197 lsb
= c
& -c
; /* lsb == 0x0000000000100000 */
3198 m1
= -lsb
; /* m1 == 0xfffffffffff00000 */
3199 c
= ~c
; /* c == 0x00fff000000fffff */
3200 c
&= -lsb
; /* c == 0x00fff00000000000 */
3201 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
3202 c
= ~c
; /* c == 0xff000fffffffffff */
3203 c
&= -lsb
; /* c == 0xff00000000000000 */
3205 while ((lsb
>>= 1) != 0)
3206 shift
++; /* shift == 44 on exit from loop */
3207 m1
<<= 64 - shift
; /* m1 == 0xffffff0000000000 */
3208 m1
= ~m1
; /* m1 == 0x000000ffffffffff */
3209 m2
= ~c
; /* m2 == 0x00ffffffffffffff */
3213 /* Assume c initially something like 0xff000f0000000000. The idea
3214 is to rotate the word so that the ^^^ middle group of zeros
3215 is at the LS end and can be cleared with an rldicr mask. We then
3216 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
3218 lsb
= c
& -c
; /* lsb == 0x0000010000000000 */
3219 m2
= -lsb
; /* m2 == 0xffffff0000000000 */
3220 c
= ~c
; /* c == 0x00fff0ffffffffff */
3221 c
&= -lsb
; /* c == 0x00fff00000000000 */
3222 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
3223 c
= ~c
; /* c == 0xff000fffffffffff */
3224 c
&= -lsb
; /* c == 0xff00000000000000 */
3226 while ((lsb
>>= 1) != 0)
3227 shift
++; /* shift == 44 on exit from loop */
3228 m1
= ~c
; /* m1 == 0x00ffffffffffffff */
3229 m1
>>= shift
; /* m1 == 0x0000000000000fff */
3230 m1
= ~m1
; /* m1 == 0xfffffffffffff000 */
3233 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
3234 masks will be all 1's. We are guaranteed more than one transition. */
3235 out
[0] = GEN_INT (64 - shift
);
3236 out
[1] = GEN_INT (m1
);
3237 out
[2] = GEN_INT (shift
);
3238 out
[3] = GEN_INT (m2
);
3246 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
3249 invalid_e500_subreg (rtx op
, enum machine_mode mode
)
3251 if (TARGET_E500_DOUBLE
)
3253 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
3254 subreg:TI and reg:TF. Decimal float modes are like integer
3255 modes (only low part of each register used) for this
3257 if (GET_CODE (op
) == SUBREG
3258 && (mode
== SImode
|| mode
== DImode
|| mode
== TImode
3259 || mode
== DDmode
|| mode
== TDmode
)
3260 && REG_P (SUBREG_REG (op
))
3261 && (GET_MODE (SUBREG_REG (op
)) == DFmode
3262 || GET_MODE (SUBREG_REG (op
)) == TFmode
))
3265 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
3267 if (GET_CODE (op
) == SUBREG
3268 && (mode
== DFmode
|| mode
== TFmode
)
3269 && REG_P (SUBREG_REG (op
))
3270 && (GET_MODE (SUBREG_REG (op
)) == DImode
3271 || GET_MODE (SUBREG_REG (op
)) == TImode
3272 || GET_MODE (SUBREG_REG (op
)) == DDmode
3273 || GET_MODE (SUBREG_REG (op
)) == TDmode
))
3278 && GET_CODE (op
) == SUBREG
3280 && REG_P (SUBREG_REG (op
))
3281 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op
))))
3287 /* AIX increases natural record alignment to doubleword if the first
3288 field is an FP double while the FP fields remain word aligned. */
3291 rs6000_special_round_type_align (tree type
, unsigned int computed
,
3292 unsigned int specified
)
3294 unsigned int align
= MAX (computed
, specified
);
3295 tree field
= TYPE_FIELDS (type
);
3297 /* Skip all non field decls */
3298 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
3299 field
= TREE_CHAIN (field
);
3301 if (field
!= NULL
&& field
!= type
)
3303 type
= TREE_TYPE (field
);
3304 while (TREE_CODE (type
) == ARRAY_TYPE
)
3305 type
= TREE_TYPE (type
);
3307 if (type
!= error_mark_node
&& TYPE_MODE (type
) == DFmode
)
3308 align
= MAX (align
, 64);
3314 /* Darwin increases record alignment to the natural alignment of
3318 darwin_rs6000_special_round_type_align (tree type
, unsigned int computed
,
3319 unsigned int specified
)
3321 unsigned int align
= MAX (computed
, specified
);
3323 if (TYPE_PACKED (type
))
3326 /* Find the first field, looking down into aggregates. */
3328 tree field
= TYPE_FIELDS (type
);
3329 /* Skip all non field decls */
3330 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
3331 field
= TREE_CHAIN (field
);
3334 type
= TREE_TYPE (field
);
3335 while (TREE_CODE (type
) == ARRAY_TYPE
)
3336 type
= TREE_TYPE (type
);
3337 } while (AGGREGATE_TYPE_P (type
));
3339 if (! AGGREGATE_TYPE_P (type
) && type
!= error_mark_node
)
3340 align
= MAX (align
, TYPE_ALIGN (type
));
3345 /* Return 1 for an operand in small memory on V.4/eabi. */
3348 small_data_operand (rtx op ATTRIBUTE_UNUSED
,
3349 enum machine_mode mode ATTRIBUTE_UNUSED
)
3354 if (rs6000_sdata
== SDATA_NONE
|| rs6000_sdata
== SDATA_DATA
)
3357 if (DEFAULT_ABI
!= ABI_V4
)
3360 /* Vector and float memory instructions have a limited offset on the
3361 SPE, so using a vector or float variable directly as an operand is
3364 && (SPE_VECTOR_MODE (mode
) || FLOAT_MODE_P (mode
)))
3367 if (GET_CODE (op
) == SYMBOL_REF
)
3370 else if (GET_CODE (op
) != CONST
3371 || GET_CODE (XEXP (op
, 0)) != PLUS
3372 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
3373 || GET_CODE (XEXP (XEXP (op
, 0), 1)) != CONST_INT
)
3378 rtx sum
= XEXP (op
, 0);
3379 HOST_WIDE_INT summand
;
3381 /* We have to be careful here, because it is the referenced address
3382 that must be 32k from _SDA_BASE_, not just the symbol. */
3383 summand
= INTVAL (XEXP (sum
, 1));
3384 if (summand
< 0 || (unsigned HOST_WIDE_INT
) summand
> g_switch_value
)
3387 sym_ref
= XEXP (sum
, 0);
3390 return SYMBOL_REF_SMALL_P (sym_ref
);
3396 /* Return true if either operand is a general purpose register. */
3399 gpr_or_gpr_p (rtx op0
, rtx op1
)
3401 return ((REG_P (op0
) && INT_REGNO_P (REGNO (op0
)))
3402 || (REG_P (op1
) && INT_REGNO_P (REGNO (op1
))));
3406 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
3409 constant_pool_expr_1 (rtx op
, int *have_sym
, int *have_toc
)
3411 switch (GET_CODE (op
))
3414 if (RS6000_SYMBOL_REF_TLS_P (op
))
3416 else if (CONSTANT_POOL_ADDRESS_P (op
))
3418 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op
), Pmode
))
3426 else if (! strcmp (XSTR (op
, 0), toc_label_name
))
3435 return (constant_pool_expr_1 (XEXP (op
, 0), have_sym
, have_toc
)
3436 && constant_pool_expr_1 (XEXP (op
, 1), have_sym
, have_toc
));
3438 return constant_pool_expr_1 (XEXP (op
, 0), have_sym
, have_toc
);
3447 constant_pool_expr_p (rtx op
)
3451 return constant_pool_expr_1 (op
, &have_sym
, &have_toc
) && have_sym
;
3455 toc_relative_expr_p (rtx op
)
3459 return constant_pool_expr_1 (op
, &have_sym
, &have_toc
) && have_toc
;
3463 legitimate_constant_pool_address_p (rtx x
)
3466 && GET_CODE (x
) == PLUS
3467 && GET_CODE (XEXP (x
, 0)) == REG
3468 && (TARGET_MINIMAL_TOC
|| REGNO (XEXP (x
, 0)) == TOC_REGISTER
)
3469 && constant_pool_expr_p (XEXP (x
, 1)));
3473 legitimate_small_data_p (enum machine_mode mode
, rtx x
)
3475 return (DEFAULT_ABI
== ABI_V4
3476 && !flag_pic
&& !TARGET_TOC
3477 && (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
)
3478 && small_data_operand (x
, mode
));
3481 /* SPE offset addressing is limited to 5-bits worth of double words. */
3482 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
3485 rs6000_legitimate_offset_address_p (enum machine_mode mode
, rtx x
, int strict
)
3487 unsigned HOST_WIDE_INT offset
, extra
;
3489 if (GET_CODE (x
) != PLUS
)
3491 if (GET_CODE (XEXP (x
, 0)) != REG
)
3493 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
3495 if (legitimate_constant_pool_address_p (x
))
3497 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
3500 offset
= INTVAL (XEXP (x
, 1));
3508 /* AltiVec vector modes. Only reg+reg addressing is valid and
3509 constant offset zero should not occur due to canonicalization. */
3516 /* Paired vector modes. Only reg+reg addressing is valid and
3517 constant offset zero should not occur due to canonicalization. */
3518 if (TARGET_PAIRED_FLOAT
)
3520 /* SPE vector modes. */
3521 return SPE_CONST_OFFSET_OK (offset
);
3524 if (TARGET_E500_DOUBLE
)
3525 return SPE_CONST_OFFSET_OK (offset
);
3529 /* On e500v2, we may have:
3531 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
3533 Which gets addressed with evldd instructions. */
3534 if (TARGET_E500_DOUBLE
)
3535 return SPE_CONST_OFFSET_OK (offset
);
3537 if (mode
== DFmode
|| mode
== DDmode
|| !TARGET_POWERPC64
)
3539 else if (offset
& 3)
3544 if (TARGET_E500_DOUBLE
)
3545 return (SPE_CONST_OFFSET_OK (offset
)
3546 && SPE_CONST_OFFSET_OK (offset
+ 8));
3550 if (mode
== TFmode
|| mode
== TDmode
|| !TARGET_POWERPC64
)
3552 else if (offset
& 3)
3563 return (offset
< 0x10000) && (offset
+ extra
< 0x10000);
3567 legitimate_indexed_address_p (rtx x
, int strict
)
3571 if (GET_CODE (x
) != PLUS
)
3577 /* Recognize the rtl generated by reload which we know will later be
3578 replaced with proper base and index regs. */
3580 && reload_in_progress
3581 && (REG_P (op0
) || GET_CODE (op0
) == PLUS
)
3585 return (REG_P (op0
) && REG_P (op1
)
3586 && ((INT_REG_OK_FOR_BASE_P (op0
, strict
)
3587 && INT_REG_OK_FOR_INDEX_P (op1
, strict
))
3588 || (INT_REG_OK_FOR_BASE_P (op1
, strict
)
3589 && INT_REG_OK_FOR_INDEX_P (op0
, strict
))));
3593 legitimate_indirect_address_p (rtx x
, int strict
)
3595 return GET_CODE (x
) == REG
&& INT_REG_OK_FOR_BASE_P (x
, strict
);
3599 macho_lo_sum_memory_operand (rtx x
, enum machine_mode mode
)
3601 if (!TARGET_MACHO
|| !flag_pic
3602 || mode
!= SImode
|| GET_CODE (x
) != MEM
)
3606 if (GET_CODE (x
) != LO_SUM
)
3608 if (GET_CODE (XEXP (x
, 0)) != REG
)
3610 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 0))
3614 return CONSTANT_P (x
);
3618 legitimate_lo_sum_address_p (enum machine_mode mode
, rtx x
, int strict
)
3620 if (GET_CODE (x
) != LO_SUM
)
3622 if (GET_CODE (XEXP (x
, 0)) != REG
)
3624 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
3626 /* Restrict addressing for DI because of our SUBREG hackery. */
3627 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
3628 || mode
== DDmode
|| mode
== TDmode
3633 if (TARGET_ELF
|| TARGET_MACHO
)
3635 if (DEFAULT_ABI
!= ABI_AIX
&& DEFAULT_ABI
!= ABI_DARWIN
&& flag_pic
)
3639 if (GET_MODE_NUNITS (mode
) != 1)
3641 if (GET_MODE_BITSIZE (mode
) > 64
3642 || (GET_MODE_BITSIZE (mode
) > 32 && !TARGET_POWERPC64
3643 && !(TARGET_HARD_FLOAT
&& TARGET_FPRS
3644 && (mode
== DFmode
|| mode
== DDmode
))))
3647 return CONSTANT_P (x
);
3654 /* Try machine-dependent ways of modifying an illegitimate address
3655 to be legitimate. If we find one, return the new, valid address.
3656 This is used from only one place: `memory_address' in explow.c.
3658 OLDX is the address as it was before break_out_memory_refs was
3659 called. In some cases it is useful to look at this to decide what
3662 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
3664 It is always safe for this function to do nothing. It exists to
3665 recognize opportunities to optimize the output.
3667 On RS/6000, first check for the sum of a register with a constant
3668 integer that is out of range. If so, generate code to add the
3669 constant with the low-order 16 bits masked to the register and force
3670 this result into another register (this can be done with `cau').
3671 Then generate an address of REG+(CONST&0xffff), allowing for the
3672 possibility of bit 16 being a one.
3674 Then check for the sum of a register and something not constant, try to
3675 load the other things into a register and return the sum. */
3678 rs6000_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3679 enum machine_mode mode
)
3681 if (GET_CODE (x
) == SYMBOL_REF
)
3683 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
3685 return rs6000_legitimize_tls_address (x
, model
);
3688 if (GET_CODE (x
) == PLUS
3689 && GET_CODE (XEXP (x
, 0)) == REG
3690 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3691 && (unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 1)) + 0x8000) >= 0x10000
3692 && !(SPE_VECTOR_MODE (mode
)
3693 || ALTIVEC_VECTOR_MODE (mode
)
3694 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
3695 || mode
== DImode
|| mode
== DDmode
3696 || mode
== TDmode
))))
3698 HOST_WIDE_INT high_int
, low_int
;
3700 low_int
= ((INTVAL (XEXP (x
, 1)) & 0xffff) ^ 0x8000) - 0x8000;
3701 high_int
= INTVAL (XEXP (x
, 1)) - low_int
;
3702 sum
= force_operand (gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3703 GEN_INT (high_int
)), 0);
3704 return gen_rtx_PLUS (Pmode
, sum
, GEN_INT (low_int
));
3706 else if (GET_CODE (x
) == PLUS
3707 && GET_CODE (XEXP (x
, 0)) == REG
3708 && GET_CODE (XEXP (x
, 1)) != CONST_INT
3709 && GET_MODE_NUNITS (mode
) == 1
3710 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
)
3712 || ((mode
!= DImode
&& mode
!= DFmode
&& mode
!= DDmode
)
3713 || (TARGET_E500_DOUBLE
&& mode
!= DDmode
)))
3714 && (TARGET_POWERPC64
|| mode
!= DImode
)
3719 return gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3720 force_reg (Pmode
, force_operand (XEXP (x
, 1), 0)));
3722 else if (ALTIVEC_VECTOR_MODE (mode
))
3726 /* Make sure both operands are registers. */
3727 if (GET_CODE (x
) == PLUS
)
3728 return gen_rtx_PLUS (Pmode
, force_reg (Pmode
, XEXP (x
, 0)),
3729 force_reg (Pmode
, XEXP (x
, 1)));
3731 reg
= force_reg (Pmode
, x
);
3734 else if (SPE_VECTOR_MODE (mode
)
3735 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
3736 || mode
== DDmode
|| mode
== TDmode
3737 || mode
== DImode
)))
3741 /* We accept [reg + reg] and [reg + OFFSET]. */
3743 if (GET_CODE (x
) == PLUS
)
3745 rtx op1
= XEXP (x
, 0);
3746 rtx op2
= XEXP (x
, 1);
3749 op1
= force_reg (Pmode
, op1
);
3751 if (GET_CODE (op2
) != REG
3752 && (GET_CODE (op2
) != CONST_INT
3753 || !SPE_CONST_OFFSET_OK (INTVAL (op2
))
3754 || (GET_MODE_SIZE (mode
) > 8
3755 && !SPE_CONST_OFFSET_OK (INTVAL (op2
) + 8))))
3756 op2
= force_reg (Pmode
, op2
);
3758 /* We can't always do [reg + reg] for these, because [reg +
3759 reg + offset] is not a legitimate addressing mode. */
3760 y
= gen_rtx_PLUS (Pmode
, op1
, op2
);
3762 if ((GET_MODE_SIZE (mode
) > 8 || mode
== DDmode
) && REG_P (op2
))
3763 return force_reg (Pmode
, y
);
3768 return force_reg (Pmode
, x
);
3774 && GET_CODE (x
) != CONST_INT
3775 && GET_CODE (x
) != CONST_DOUBLE
3777 && GET_MODE_NUNITS (mode
) == 1
3778 && (GET_MODE_BITSIZE (mode
) <= 32
3779 || ((TARGET_HARD_FLOAT
&& TARGET_FPRS
)
3780 && (mode
== DFmode
|| mode
== DDmode
))))
3782 rtx reg
= gen_reg_rtx (Pmode
);
3783 emit_insn (gen_elf_high (reg
, x
));
3784 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
3786 else if (TARGET_MACHO
&& TARGET_32BIT
&& TARGET_NO_TOC
3789 && ! MACHO_DYNAMIC_NO_PIC_P
3791 && GET_CODE (x
) != CONST_INT
3792 && GET_CODE (x
) != CONST_DOUBLE
3794 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
)
3795 || (mode
!= DFmode
&& mode
!= DDmode
))
3799 rtx reg
= gen_reg_rtx (Pmode
);
3800 emit_insn (gen_macho_high (reg
, x
));
3801 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
3804 && GET_CODE (x
) == SYMBOL_REF
3805 && constant_pool_expr_p (x
)
3806 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), Pmode
))
3808 return create_TOC_reference (x
);
3814 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
3815 We need to emit DTP-relative relocations. */
3818 rs6000_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
3823 fputs ("\t.long\t", file
);
3826 fputs (DOUBLE_INT_ASM_OP
, file
);
3831 output_addr_const (file
, x
);
3832 fputs ("@dtprel+0x8000", file
);
3835 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3837 static GTY(()) rtx rs6000_tls_symbol
;
3839 rs6000_tls_get_addr (void)
3841 if (!rs6000_tls_symbol
)
3842 rs6000_tls_symbol
= init_one_libfunc ("__tls_get_addr");
3844 return rs6000_tls_symbol
;
3847 /* Construct the SYMBOL_REF for TLS GOT references. */
3849 static GTY(()) rtx rs6000_got_symbol
;
3851 rs6000_got_sym (void)
3853 if (!rs6000_got_symbol
)
3855 rs6000_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3856 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_LOCAL
;
3857 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_EXTERNAL
;
3860 return rs6000_got_symbol
;
3863 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3864 this (thread-local) address. */
3867 rs6000_legitimize_tls_address (rtx addr
, enum tls_model model
)
3871 dest
= gen_reg_rtx (Pmode
);
3872 if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 16)
3878 tlsreg
= gen_rtx_REG (Pmode
, 13);
3879 insn
= gen_tls_tprel_64 (dest
, tlsreg
, addr
);
3883 tlsreg
= gen_rtx_REG (Pmode
, 2);
3884 insn
= gen_tls_tprel_32 (dest
, tlsreg
, addr
);
3888 else if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 32)
3892 tmp
= gen_reg_rtx (Pmode
);
3895 tlsreg
= gen_rtx_REG (Pmode
, 13);
3896 insn
= gen_tls_tprel_ha_64 (tmp
, tlsreg
, addr
);
3900 tlsreg
= gen_rtx_REG (Pmode
, 2);
3901 insn
= gen_tls_tprel_ha_32 (tmp
, tlsreg
, addr
);
3905 insn
= gen_tls_tprel_lo_64 (dest
, tmp
, addr
);
3907 insn
= gen_tls_tprel_lo_32 (dest
, tmp
, addr
);
3912 rtx r3
, got
, tga
, tmp1
, tmp2
, eqv
;
3914 /* We currently use relocations like @got@tlsgd for tls, which
3915 means the linker will handle allocation of tls entries, placing
3916 them in the .got section. So use a pointer to the .got section,
3917 not one to secondary TOC sections used by 64-bit -mminimal-toc,
3918 or to secondary GOT sections used by 32-bit -fPIC. */
3920 got
= gen_rtx_REG (Pmode
, 2);
3924 got
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
3927 rtx gsym
= rs6000_got_sym ();
3928 got
= gen_reg_rtx (Pmode
);
3930 rs6000_emit_move (got
, gsym
, Pmode
);
3936 tmp1
= gen_reg_rtx (Pmode
);
3937 tmp2
= gen_reg_rtx (Pmode
);
3938 tmp3
= gen_reg_rtx (Pmode
);
3939 mem
= gen_const_mem (Pmode
, tmp1
);
3941 first
= emit_insn (gen_load_toc_v4_PIC_1b (gsym
));
3942 emit_move_insn (tmp1
,
3943 gen_rtx_REG (Pmode
, LR_REGNO
));
3944 emit_move_insn (tmp2
, mem
);
3945 emit_insn (gen_addsi3 (tmp3
, tmp1
, tmp2
));
3946 last
= emit_move_insn (got
, tmp3
);
3947 set_unique_reg_note (last
, REG_EQUAL
, gsym
);
3952 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
)
3954 r3
= gen_rtx_REG (Pmode
, 3);
3955 tga
= rs6000_tls_get_addr ();
3957 if (DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
3958 insn
= gen_tls_gd_aix64 (r3
, got
, addr
, tga
, const0_rtx
);
3959 else if (DEFAULT_ABI
== ABI_AIX
&& !TARGET_64BIT
)
3960 insn
= gen_tls_gd_aix32 (r3
, got
, addr
, tga
, const0_rtx
);
3961 else if (DEFAULT_ABI
== ABI_V4
)
3962 insn
= gen_tls_gd_sysvsi (r3
, got
, addr
, tga
, const0_rtx
);
3967 insn
= emit_call_insn (insn
);
3968 RTL_CONST_CALL_P (insn
) = 1;
3969 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r3
);
3970 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
3971 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
3972 insn
= get_insns ();
3974 emit_libcall_block (insn
, dest
, r3
, addr
);
3976 else if (model
== TLS_MODEL_LOCAL_DYNAMIC
)
3978 r3
= gen_rtx_REG (Pmode
, 3);
3979 tga
= rs6000_tls_get_addr ();
3981 if (DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
3982 insn
= gen_tls_ld_aix64 (r3
, got
, tga
, const0_rtx
);
3983 else if (DEFAULT_ABI
== ABI_AIX
&& !TARGET_64BIT
)
3984 insn
= gen_tls_ld_aix32 (r3
, got
, tga
, const0_rtx
);
3985 else if (DEFAULT_ABI
== ABI_V4
)
3986 insn
= gen_tls_ld_sysvsi (r3
, got
, tga
, const0_rtx
);
3991 insn
= emit_call_insn (insn
);
3992 RTL_CONST_CALL_P (insn
) = 1;
3993 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r3
);
3994 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
3995 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
3996 insn
= get_insns ();
3998 tmp1
= gen_reg_rtx (Pmode
);
3999 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
4001 emit_libcall_block (insn
, tmp1
, r3
, eqv
);
4002 if (rs6000_tls_size
== 16)
4005 insn
= gen_tls_dtprel_64 (dest
, tmp1
, addr
);
4007 insn
= gen_tls_dtprel_32 (dest
, tmp1
, addr
);
4009 else if (rs6000_tls_size
== 32)
4011 tmp2
= gen_reg_rtx (Pmode
);
4013 insn
= gen_tls_dtprel_ha_64 (tmp2
, tmp1
, addr
);
4015 insn
= gen_tls_dtprel_ha_32 (tmp2
, tmp1
, addr
);
4018 insn
= gen_tls_dtprel_lo_64 (dest
, tmp2
, addr
);
4020 insn
= gen_tls_dtprel_lo_32 (dest
, tmp2
, addr
);
4024 tmp2
= gen_reg_rtx (Pmode
);
4026 insn
= gen_tls_got_dtprel_64 (tmp2
, got
, addr
);
4028 insn
= gen_tls_got_dtprel_32 (tmp2
, got
, addr
);
4030 insn
= gen_rtx_SET (Pmode
, dest
,
4031 gen_rtx_PLUS (Pmode
, tmp2
, tmp1
));
4037 /* IE, or 64-bit offset LE. */
4038 tmp2
= gen_reg_rtx (Pmode
);
4040 insn
= gen_tls_got_tprel_64 (tmp2
, got
, addr
);
4042 insn
= gen_tls_got_tprel_32 (tmp2
, got
, addr
);
4045 insn
= gen_tls_tls_64 (dest
, tmp2
, addr
);
4047 insn
= gen_tls_tls_32 (dest
, tmp2
, addr
);
4055 /* Return 1 if X contains a thread-local symbol. */
4058 rs6000_tls_referenced_p (rtx x
)
4060 if (! TARGET_HAVE_TLS
)
4063 return for_each_rtx (&x
, &rs6000_tls_symbol_ref_1
, 0);
4066 /* Return 1 if *X is a thread-local symbol. This is the same as
4067 rs6000_tls_symbol_ref except for the type of the unused argument. */
4070 rs6000_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
4072 return RS6000_SYMBOL_REF_TLS_P (*x
);
4075 /* The convention appears to be to define this wherever it is used.
4076 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
4077 is now used here. */
4078 #ifndef REG_MODE_OK_FOR_BASE_P
4079 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
4082 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
4083 replace the input X, or the original X if no replacement is called for.
4084 The output parameter *WIN is 1 if the calling macro should goto WIN,
4087 For RS/6000, we wish to handle large displacements off a base
4088 register by splitting the addend across an addiu/addis and the mem insn.
4089 This cuts number of extra insns needed from 3 to 1.
4091 On Darwin, we use this to generate code for floating point constants.
4092 A movsf_low is generated so we wind up with 2 instructions rather than 3.
4093 The Darwin code is inside #if TARGET_MACHO because only then is
4094 machopic_function_base_name() defined. */
4096 rs6000_legitimize_reload_address (rtx x
, enum machine_mode mode
,
4097 int opnum
, int type
,
4098 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
4100 /* We must recognize output that we have already generated ourselves. */
4101 if (GET_CODE (x
) == PLUS
4102 && GET_CODE (XEXP (x
, 0)) == PLUS
4103 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
4104 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4105 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4107 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4108 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
4109 opnum
, (enum reload_type
)type
);
4115 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
4116 && GET_CODE (x
) == LO_SUM
4117 && GET_CODE (XEXP (x
, 0)) == PLUS
4118 && XEXP (XEXP (x
, 0), 0) == pic_offset_table_rtx
4119 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == HIGH
4120 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 0)) == CONST
4121 && XEXP (XEXP (XEXP (x
, 0), 1), 0) == XEXP (x
, 1)
4122 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == MINUS
4123 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 0)) == SYMBOL_REF
4124 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 1)) == SYMBOL_REF
)
4126 /* Result of previous invocation of this function on Darwin
4127 floating point constant. */
4128 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4129 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
4130 opnum
, (enum reload_type
)type
);
4136 /* Force ld/std non-word aligned offset into base register by wrapping
4138 if (GET_CODE (x
) == PLUS
4139 && GET_CODE (XEXP (x
, 0)) == REG
4140 && REGNO (XEXP (x
, 0)) < 32
4141 && REG_MODE_OK_FOR_BASE_P (XEXP (x
, 0), mode
)
4142 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4143 && (INTVAL (XEXP (x
, 1)) & 3) != 0
4144 && !ALTIVEC_VECTOR_MODE (mode
)
4145 && GET_MODE_SIZE (mode
) >= UNITS_PER_WORD
4146 && TARGET_POWERPC64
)
4148 x
= gen_rtx_PLUS (GET_MODE (x
), x
, GEN_INT (0));
4149 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4150 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
4151 opnum
, (enum reload_type
) type
);
4156 if (GET_CODE (x
) == PLUS
4157 && GET_CODE (XEXP (x
, 0)) == REG
4158 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
4159 && REG_MODE_OK_FOR_BASE_P (XEXP (x
, 0), mode
)
4160 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4161 && !SPE_VECTOR_MODE (mode
)
4162 && !(TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
4163 || mode
== DDmode
|| mode
== TDmode
4165 && !ALTIVEC_VECTOR_MODE (mode
))
4167 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
4168 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
4170 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
4172 /* Check for 32-bit overflow. */
4173 if (high
+ low
!= val
)
4179 /* Reload the high part into a base reg; leave the low part
4180 in the mem directly. */
4182 x
= gen_rtx_PLUS (GET_MODE (x
),
4183 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
4187 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4188 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
4189 opnum
, (enum reload_type
)type
);
4194 if (GET_CODE (x
) == SYMBOL_REF
4195 && !ALTIVEC_VECTOR_MODE (mode
)
4196 && !SPE_VECTOR_MODE (mode
)
4198 && DEFAULT_ABI
== ABI_DARWIN
4199 && (flag_pic
|| MACHO_DYNAMIC_NO_PIC_P
)
4201 && DEFAULT_ABI
== ABI_V4
4204 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
4205 The same goes for DImode without 64-bit gprs and DFmode and DDmode
4209 && (mode
!= DImode
|| TARGET_POWERPC64
)
4210 && ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_POWERPC64
4211 || (TARGET_FPRS
&& TARGET_HARD_FLOAT
)))
4216 rtx offset
= gen_rtx_CONST (Pmode
,
4217 gen_rtx_MINUS (Pmode
, x
,
4218 machopic_function_base_sym ()));
4219 x
= gen_rtx_LO_SUM (GET_MODE (x
),
4220 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
4221 gen_rtx_HIGH (Pmode
, offset
)), offset
);
4225 x
= gen_rtx_LO_SUM (GET_MODE (x
),
4226 gen_rtx_HIGH (Pmode
, x
), x
);
4228 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4229 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
4230 opnum
, (enum reload_type
)type
);
4235 /* Reload an offset address wrapped by an AND that represents the
4236 masking of the lower bits. Strip the outer AND and let reload
4237 convert the offset address into an indirect address. */
4239 && ALTIVEC_VECTOR_MODE (mode
)
4240 && GET_CODE (x
) == AND
4241 && GET_CODE (XEXP (x
, 0)) == PLUS
4242 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
4243 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4244 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4245 && INTVAL (XEXP (x
, 1)) == -16)
4253 && GET_CODE (x
) == SYMBOL_REF
4254 && constant_pool_expr_p (x
)
4255 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), mode
))
4257 x
= create_TOC_reference (x
);
4265 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
4266 that is a valid memory address for an instruction.
4267 The MODE argument is the machine mode for the MEM expression
4268 that wants to use this address.
4270 On the RS/6000, there are four valid address: a SYMBOL_REF that
4271 refers to a constant pool entry of an address (or the sum of it
4272 plus a constant), a short (16-bit signed) constant plus a register,
4273 the sum of two registers, or a register indirect, possibly with an
4274 auto-increment. For DFmode, DDmode and DImode with a constant plus
4275 register, we must ensure that both words are addressable or PowerPC64
4276 with offset word aligned.
4278 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
4279 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
4280 because adjacent memory cells are accessed by adding word-sized offsets
4281 during assembly output. */
4283 rs6000_legitimate_address (enum machine_mode mode
, rtx x
, int reg_ok_strict
)
4285 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
4287 && ALTIVEC_VECTOR_MODE (mode
)
4288 && GET_CODE (x
) == AND
4289 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4290 && INTVAL (XEXP (x
, 1)) == -16)
4293 if (RS6000_SYMBOL_REF_TLS_P (x
))
4295 if (legitimate_indirect_address_p (x
, reg_ok_strict
))
4297 if ((GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
4298 && !ALTIVEC_VECTOR_MODE (mode
)
4299 && !SPE_VECTOR_MODE (mode
)
4302 /* Restrict addressing for DI because of our SUBREG hackery. */
4303 && !(TARGET_E500_DOUBLE
4304 && (mode
== DFmode
|| mode
== DDmode
|| mode
== DImode
))
4306 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
))
4308 if (legitimate_small_data_p (mode
, x
))
4310 if (legitimate_constant_pool_address_p (x
))
4312 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
4314 && GET_CODE (x
) == PLUS
4315 && GET_CODE (XEXP (x
, 0)) == REG
4316 && (XEXP (x
, 0) == virtual_stack_vars_rtx
4317 || XEXP (x
, 0) == arg_pointer_rtx
)
4318 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4320 if (rs6000_legitimate_offset_address_p (mode
, x
, reg_ok_strict
))
4325 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
)
4327 || (mode
!= DFmode
&& mode
!= DDmode
)
4328 || (TARGET_E500_DOUBLE
&& mode
!= DDmode
))
4329 && (TARGET_POWERPC64
|| mode
!= DImode
)
4330 && legitimate_indexed_address_p (x
, reg_ok_strict
))
4332 if (GET_CODE (x
) == PRE_MODIFY
4336 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
)
4338 || ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_E500_DOUBLE
))
4339 && (TARGET_POWERPC64
|| mode
!= DImode
)
4340 && !ALTIVEC_VECTOR_MODE (mode
)
4341 && !SPE_VECTOR_MODE (mode
)
4342 /* Restrict addressing for DI because of our SUBREG hackery. */
4343 && !(TARGET_E500_DOUBLE
4344 && (mode
== DFmode
|| mode
== DDmode
|| mode
== DImode
))
4346 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
)
4347 && (rs6000_legitimate_offset_address_p (mode
, XEXP (x
, 1), reg_ok_strict
)
4348 || legitimate_indexed_address_p (XEXP (x
, 1), reg_ok_strict
))
4349 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4351 if (legitimate_lo_sum_address_p (mode
, x
, reg_ok_strict
))
4356 /* Go to LABEL if ADDR (a legitimate address expression)
4357 has an effect that depends on the machine mode it is used for.
4359 On the RS/6000 this is true of all integral offsets (since AltiVec
4360 modes don't allow them) or is a pre-increment or decrement.
4362 ??? Except that due to conceptual problems in offsettable_address_p
4363 we can't really report the problems of integral offsets. So leave
4364 this assuming that the adjustable offset must be valid for the
4365 sub-words of a TFmode operand, which is what we had before. */
4368 rs6000_mode_dependent_address (rtx addr
)
4370 switch (GET_CODE (addr
))
4373 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
4375 unsigned HOST_WIDE_INT val
= INTVAL (XEXP (addr
, 1));
4376 return val
+ 12 + 0x8000 >= 0x10000;
4383 /* Auto-increment cases are now treated generically in recog.c. */
4385 return TARGET_UPDATE
;
4394 /* More elaborate version of recog's offsettable_memref_p predicate
4395 that works around the ??? note of rs6000_mode_dependent_address.
4396 In particular it accepts
4398 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
4400 in 32-bit mode, that the recog predicate rejects. */
4403 rs6000_offsettable_memref_p (rtx op
)
4408 /* First mimic offsettable_memref_p. */
4409 if (offsettable_address_p (1, GET_MODE (op
), XEXP (op
, 0)))
4412 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
4413 the latter predicate knows nothing about the mode of the memory
4414 reference and, therefore, assumes that it is the largest supported
4415 mode (TFmode). As a consequence, legitimate offsettable memory
4416 references are rejected. rs6000_legitimate_offset_address_p contains
4417 the correct logic for the PLUS case of rs6000_mode_dependent_address. */
4418 return rs6000_legitimate_offset_address_p (GET_MODE (op
), XEXP (op
, 0), 1);
4421 /* Return number of consecutive hard regs needed starting at reg REGNO
4422 to hold something of mode MODE.
4423 This is ordinarily the length in words of a value of mode MODE
4424 but can be less for certain modes in special long registers.
4426 For the SPE, GPRs are 64 bits but only 32 bits are visible in
4427 scalar instructions. The upper 32 bits are only available to the
4430 POWER and PowerPC GPRs hold 32 bits worth;
4431 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
4434 rs6000_hard_regno_nregs (int regno
, enum machine_mode mode
)
4436 if (FP_REGNO_P (regno
))
4437 return (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
4439 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
4440 return (GET_MODE_SIZE (mode
) + UNITS_PER_SPE_WORD
- 1) / UNITS_PER_SPE_WORD
;
4442 if (ALTIVEC_REGNO_P (regno
))
4444 (GET_MODE_SIZE (mode
) + UNITS_PER_ALTIVEC_WORD
- 1) / UNITS_PER_ALTIVEC_WORD
;
4446 /* The value returned for SCmode in the E500 double case is 2 for
4447 ABI compatibility; storing an SCmode value in a single register
4448 would require function_arg and rs6000_spe_function_arg to handle
4449 SCmode so as to pass the value correctly in a pair of
4451 if (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
) && mode
!= SCmode
4452 && !DECIMAL_FLOAT_MODE_P (mode
))
4453 return (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
4455 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4458 /* Change register usage conditional on target flags. */
4460 rs6000_conditional_register_usage (void)
4464 /* Set MQ register fixed (already call_used) if not POWER
4465 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
4470 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
4472 fixed_regs
[13] = call_used_regs
[13]
4473 = call_really_used_regs
[13] = 1;
4475 /* Conditionally disable FPRs. */
4476 if (TARGET_SOFT_FLOAT
|| !TARGET_FPRS
)
4477 for (i
= 32; i
< 64; i
++)
4478 fixed_regs
[i
] = call_used_regs
[i
]
4479 = call_really_used_regs
[i
] = 1;
4481 /* The TOC register is not killed across calls in a way that is
4482 visible to the compiler. */
4483 if (DEFAULT_ABI
== ABI_AIX
)
4484 call_really_used_regs
[2] = 0;
4486 if (DEFAULT_ABI
== ABI_V4
4487 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
4489 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
4491 if (DEFAULT_ABI
== ABI_V4
4492 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
4494 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4495 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4496 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
4498 if (DEFAULT_ABI
== ABI_DARWIN
4499 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
4500 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4501 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4502 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
4504 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
)
4505 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4506 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
4510 global_regs
[SPEFSCR_REGNO
] = 1;
4511 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
4512 registers in prologues and epilogues. We no longer use r14
4513 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
4514 pool for link-compatibility with older versions of GCC. Once
4515 "old" code has died out, we can return r14 to the allocation
4518 = call_used_regs
[14]
4519 = call_really_used_regs
[14] = 1;
4522 if (!TARGET_ALTIVEC
)
4524 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
4525 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
4526 call_really_used_regs
[VRSAVE_REGNO
] = 1;
4530 global_regs
[VSCR_REGNO
] = 1;
4532 if (TARGET_ALTIVEC_ABI
)
4534 for (i
= FIRST_ALTIVEC_REGNO
; i
< FIRST_ALTIVEC_REGNO
+ 20; ++i
)
4535 call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
4537 /* AIX reserves VR20:31 in non-extended ABI mode. */
4539 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
< FIRST_ALTIVEC_REGNO
+ 32; ++i
)
4540 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
4544 /* Try to output insns to set TARGET equal to the constant C if it can
4545 be done in less than N insns. Do all computations in MODE.
4546 Returns the place where the output has been placed if it can be
4547 done and the insns have been emitted. If it would take more than N
4548 insns, zero is returned and no insns and emitted. */
4551 rs6000_emit_set_const (rtx dest
, enum machine_mode mode
,
4552 rtx source
, int n ATTRIBUTE_UNUSED
)
4554 rtx result
, insn
, set
;
4555 HOST_WIDE_INT c0
, c1
;
4562 dest
= gen_reg_rtx (mode
);
4563 emit_insn (gen_rtx_SET (VOIDmode
, dest
, source
));
4567 result
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (SImode
);
4569 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (result
),
4570 GEN_INT (INTVAL (source
)
4571 & (~ (HOST_WIDE_INT
) 0xffff))));
4572 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
4573 gen_rtx_IOR (SImode
, copy_rtx (result
),
4574 GEN_INT (INTVAL (source
) & 0xffff))));
4579 switch (GET_CODE (source
))
4582 c0
= INTVAL (source
);
4587 #if HOST_BITS_PER_WIDE_INT >= 64
4588 c0
= CONST_DOUBLE_LOW (source
);
4591 c0
= CONST_DOUBLE_LOW (source
);
4592 c1
= CONST_DOUBLE_HIGH (source
);
4600 result
= rs6000_emit_set_long_const (dest
, c0
, c1
);
4607 insn
= get_last_insn ();
4608 set
= single_set (insn
);
4609 if (! CONSTANT_P (SET_SRC (set
)))
4610 set_unique_reg_note (insn
, REG_EQUAL
, source
);
4615 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
4616 fall back to a straight forward decomposition. We do this to avoid
4617 exponential run times encountered when looking for longer sequences
4618 with rs6000_emit_set_const. */
4620 rs6000_emit_set_long_const (rtx dest
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
4622 if (!TARGET_POWERPC64
)
4624 rtx operand1
, operand2
;
4626 operand1
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
== 0,
4628 operand2
= operand_subword_force (copy_rtx (dest
), WORDS_BIG_ENDIAN
!= 0,
4630 emit_move_insn (operand1
, GEN_INT (c1
));
4631 emit_move_insn (operand2
, GEN_INT (c2
));
4635 HOST_WIDE_INT ud1
, ud2
, ud3
, ud4
;
4638 ud2
= (c1
& 0xffff0000) >> 16;
4639 #if HOST_BITS_PER_WIDE_INT >= 64
4643 ud4
= (c2
& 0xffff0000) >> 16;
4645 if ((ud4
== 0xffff && ud3
== 0xffff && ud2
== 0xffff && (ud1
& 0x8000))
4646 || (ud4
== 0 && ud3
== 0 && ud2
== 0 && ! (ud1
& 0x8000)))
4649 emit_move_insn (dest
, GEN_INT (((ud1
^ 0x8000) - 0x8000)));
4651 emit_move_insn (dest
, GEN_INT (ud1
));
4654 else if ((ud4
== 0xffff && ud3
== 0xffff && (ud2
& 0x8000))
4655 || (ud4
== 0 && ud3
== 0 && ! (ud2
& 0x8000)))
4658 emit_move_insn (dest
, GEN_INT (((ud2
<< 16) ^ 0x80000000)
4661 emit_move_insn (dest
, GEN_INT (ud2
<< 16));
4663 emit_move_insn (copy_rtx (dest
),
4664 gen_rtx_IOR (DImode
, copy_rtx (dest
),
4667 else if ((ud4
== 0xffff && (ud3
& 0x8000))
4668 || (ud4
== 0 && ! (ud3
& 0x8000)))
4671 emit_move_insn (dest
, GEN_INT (((ud3
<< 16) ^ 0x80000000)
4674 emit_move_insn (dest
, GEN_INT (ud3
<< 16));
4677 emit_move_insn (copy_rtx (dest
),
4678 gen_rtx_IOR (DImode
, copy_rtx (dest
),
4680 emit_move_insn (copy_rtx (dest
),
4681 gen_rtx_ASHIFT (DImode
, copy_rtx (dest
),
4684 emit_move_insn (copy_rtx (dest
),
4685 gen_rtx_IOR (DImode
, copy_rtx (dest
),
4691 emit_move_insn (dest
, GEN_INT (((ud4
<< 16) ^ 0x80000000)
4694 emit_move_insn (dest
, GEN_INT (ud4
<< 16));
4697 emit_move_insn (copy_rtx (dest
),
4698 gen_rtx_IOR (DImode
, copy_rtx (dest
),
4701 emit_move_insn (copy_rtx (dest
),
4702 gen_rtx_ASHIFT (DImode
, copy_rtx (dest
),
4705 emit_move_insn (copy_rtx (dest
),
4706 gen_rtx_IOR (DImode
, copy_rtx (dest
),
4707 GEN_INT (ud2
<< 16)));
4709 emit_move_insn (copy_rtx (dest
),
4710 gen_rtx_IOR (DImode
, copy_rtx (dest
), GEN_INT (ud1
)));
4716 /* Helper for the following. Get rid of [r+r] memory refs
4717 in cases where it won't work (TImode, TFmode, TDmode). */
4720 rs6000_eliminate_indexed_memrefs (rtx operands
[2])
4722 if (GET_CODE (operands
[0]) == MEM
4723 && GET_CODE (XEXP (operands
[0], 0)) != REG
4724 && ! legitimate_constant_pool_address_p (XEXP (operands
[0], 0))
4725 && ! reload_in_progress
)
4727 = replace_equiv_address (operands
[0],
4728 copy_addr_to_reg (XEXP (operands
[0], 0)));
4730 if (GET_CODE (operands
[1]) == MEM
4731 && GET_CODE (XEXP (operands
[1], 0)) != REG
4732 && ! legitimate_constant_pool_address_p (XEXP (operands
[1], 0))
4733 && ! reload_in_progress
)
4735 = replace_equiv_address (operands
[1],
4736 copy_addr_to_reg (XEXP (operands
[1], 0)));
4739 /* Emit a move from SOURCE to DEST in mode MODE. */
4741 rs6000_emit_move (rtx dest
, rtx source
, enum machine_mode mode
)
4745 operands
[1] = source
;
4747 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
4748 if (GET_CODE (operands
[1]) == CONST_DOUBLE
4749 && ! FLOAT_MODE_P (mode
)
4750 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
4752 /* FIXME. This should never happen. */
4753 /* Since it seems that it does, do the safe thing and convert
4755 operands
[1] = gen_int_mode (CONST_DOUBLE_LOW (operands
[1]), mode
);
4757 gcc_assert (GET_CODE (operands
[1]) != CONST_DOUBLE
4758 || FLOAT_MODE_P (mode
)
4759 || ((CONST_DOUBLE_HIGH (operands
[1]) != 0
4760 || CONST_DOUBLE_LOW (operands
[1]) < 0)
4761 && (CONST_DOUBLE_HIGH (operands
[1]) != -1
4762 || CONST_DOUBLE_LOW (operands
[1]) >= 0)));
4764 /* Check if GCC is setting up a block move that will end up using FP
4765 registers as temporaries. We must make sure this is acceptable. */
4766 if (GET_CODE (operands
[0]) == MEM
4767 && GET_CODE (operands
[1]) == MEM
4769 && (SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[0]))
4770 || SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[1])))
4771 && ! (SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[0]) > 32
4772 ? 32 : MEM_ALIGN (operands
[0])))
4773 || SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[1]) > 32
4775 : MEM_ALIGN (operands
[1]))))
4776 && ! MEM_VOLATILE_P (operands
[0])
4777 && ! MEM_VOLATILE_P (operands
[1]))
4779 emit_move_insn (adjust_address (operands
[0], SImode
, 0),
4780 adjust_address (operands
[1], SImode
, 0));
4781 emit_move_insn (adjust_address (copy_rtx (operands
[0]), SImode
, 4),
4782 adjust_address (copy_rtx (operands
[1]), SImode
, 4));
4786 if (can_create_pseudo_p () && GET_CODE (operands
[0]) == MEM
4787 && !gpc_reg_operand (operands
[1], mode
))
4788 operands
[1] = force_reg (mode
, operands
[1]);
4790 if (mode
== SFmode
&& ! TARGET_POWERPC
4791 && TARGET_HARD_FLOAT
&& TARGET_FPRS
4792 && GET_CODE (operands
[0]) == MEM
)
4796 if (reload_in_progress
|| reload_completed
)
4797 regnum
= true_regnum (operands
[1]);
4798 else if (GET_CODE (operands
[1]) == REG
)
4799 regnum
= REGNO (operands
[1]);
4803 /* If operands[1] is a register, on POWER it may have
4804 double-precision data in it, so truncate it to single
4806 if (FP_REGNO_P (regnum
) || regnum
>= FIRST_PSEUDO_REGISTER
)
4809 newreg
= (!can_create_pseudo_p () ? copy_rtx (operands
[1])
4810 : gen_reg_rtx (mode
));
4811 emit_insn (gen_aux_truncdfsf2 (newreg
, operands
[1]));
4812 operands
[1] = newreg
;
4816 /* Recognize the case where operand[1] is a reference to thread-local
4817 data and load its address to a register. */
4818 if (rs6000_tls_referenced_p (operands
[1]))
4820 enum tls_model model
;
4821 rtx tmp
= operands
[1];
4824 if (GET_CODE (tmp
) == CONST
&& GET_CODE (XEXP (tmp
, 0)) == PLUS
)
4826 addend
= XEXP (XEXP (tmp
, 0), 1);
4827 tmp
= XEXP (XEXP (tmp
, 0), 0);
4830 gcc_assert (GET_CODE (tmp
) == SYMBOL_REF
);
4831 model
= SYMBOL_REF_TLS_MODEL (tmp
);
4832 gcc_assert (model
!= 0);
4834 tmp
= rs6000_legitimize_tls_address (tmp
, model
);
4837 tmp
= gen_rtx_PLUS (mode
, tmp
, addend
);
4838 tmp
= force_operand (tmp
, operands
[0]);
4843 /* Handle the case where reload calls us with an invalid address. */
4844 if (reload_in_progress
&& mode
== Pmode
4845 && (! general_operand (operands
[1], mode
)
4846 || ! nonimmediate_operand (operands
[0], mode
)))
4849 /* 128-bit constant floating-point values on Darwin should really be
4850 loaded as two parts. */
4851 if (!TARGET_IEEEQUAD
&& TARGET_LONG_DOUBLE_128
4852 && mode
== TFmode
&& GET_CODE (operands
[1]) == CONST_DOUBLE
)
4854 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
4855 know how to get a DFmode SUBREG of a TFmode. */
4856 enum machine_mode imode
= (TARGET_E500_DOUBLE
? DFmode
: DImode
);
4857 rs6000_emit_move (simplify_gen_subreg (imode
, operands
[0], mode
, 0),
4858 simplify_gen_subreg (imode
, operands
[1], mode
, 0),
4860 rs6000_emit_move (simplify_gen_subreg (imode
, operands
[0], mode
,
4861 GET_MODE_SIZE (imode
)),
4862 simplify_gen_subreg (imode
, operands
[1], mode
,
4863 GET_MODE_SIZE (imode
)),
4868 if (reload_in_progress
&& cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
4869 cfun
->machine
->sdmode_stack_slot
=
4870 eliminate_regs (cfun
->machine
->sdmode_stack_slot
, VOIDmode
, NULL_RTX
);
4872 if (reload_in_progress
4874 && MEM_P (operands
[0])
4875 && rtx_equal_p (operands
[0], cfun
->machine
->sdmode_stack_slot
)
4876 && REG_P (operands
[1]))
4878 if (FP_REGNO_P (REGNO (operands
[1])))
4880 rtx mem
= adjust_address_nv (operands
[0], DDmode
, 0);
4881 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
4882 emit_insn (gen_movsd_store (mem
, operands
[1]));
4884 else if (INT_REGNO_P (REGNO (operands
[1])))
4886 rtx mem
= adjust_address_nv (operands
[0], mode
, 4);
4887 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
4888 emit_insn (gen_movsd_hardfloat (mem
, operands
[1]));
4894 if (reload_in_progress
4896 && REG_P (operands
[0])
4897 && MEM_P (operands
[1])
4898 && rtx_equal_p (operands
[1], cfun
->machine
->sdmode_stack_slot
))
4900 if (FP_REGNO_P (REGNO (operands
[0])))
4902 rtx mem
= adjust_address_nv (operands
[1], DDmode
, 0);
4903 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
4904 emit_insn (gen_movsd_load (operands
[0], mem
));
4906 else if (INT_REGNO_P (REGNO (operands
[0])))
4908 rtx mem
= adjust_address_nv (operands
[1], mode
, 4);
4909 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
4910 emit_insn (gen_movsd_hardfloat (operands
[0], mem
));
4917 /* FIXME: In the long term, this switch statement should go away
4918 and be replaced by a sequence of tests based on things like
4924 if (CONSTANT_P (operands
[1])
4925 && GET_CODE (operands
[1]) != CONST_INT
)
4926 operands
[1] = force_const_mem (mode
, operands
[1]);
4931 rs6000_eliminate_indexed_memrefs (operands
);
4938 if (CONSTANT_P (operands
[1])
4939 && ! easy_fp_constant (operands
[1], mode
))
4940 operands
[1] = force_const_mem (mode
, operands
[1]);
4951 if (CONSTANT_P (operands
[1])
4952 && !easy_vector_constant (operands
[1], mode
))
4953 operands
[1] = force_const_mem (mode
, operands
[1]);
4958 /* Use default pattern for address of ELF small data */
4961 && DEFAULT_ABI
== ABI_V4
4962 && (GET_CODE (operands
[1]) == SYMBOL_REF
4963 || GET_CODE (operands
[1]) == CONST
)
4964 && small_data_operand (operands
[1], mode
))
4966 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
4970 if (DEFAULT_ABI
== ABI_V4
4971 && mode
== Pmode
&& mode
== SImode
4972 && flag_pic
== 1 && got_operand (operands
[1], mode
))
4974 emit_insn (gen_movsi_got (operands
[0], operands
[1]));
4978 if ((TARGET_ELF
|| DEFAULT_ABI
== ABI_DARWIN
)
4982 && CONSTANT_P (operands
[1])
4983 && GET_CODE (operands
[1]) != HIGH
4984 && GET_CODE (operands
[1]) != CONST_INT
)
4986 rtx target
= (!can_create_pseudo_p ()
4988 : gen_reg_rtx (mode
));
4990 /* If this is a function address on -mcall-aixdesc,
4991 convert it to the address of the descriptor. */
4992 if (DEFAULT_ABI
== ABI_AIX
4993 && GET_CODE (operands
[1]) == SYMBOL_REF
4994 && XSTR (operands
[1], 0)[0] == '.')
4996 const char *name
= XSTR (operands
[1], 0);
4998 while (*name
== '.')
5000 new_ref
= gen_rtx_SYMBOL_REF (Pmode
, name
);
5001 CONSTANT_POOL_ADDRESS_P (new_ref
)
5002 = CONSTANT_POOL_ADDRESS_P (operands
[1]);
5003 SYMBOL_REF_FLAGS (new_ref
) = SYMBOL_REF_FLAGS (operands
[1]);
5004 SYMBOL_REF_USED (new_ref
) = SYMBOL_REF_USED (operands
[1]);
5005 SYMBOL_REF_DATA (new_ref
) = SYMBOL_REF_DATA (operands
[1]);
5006 operands
[1] = new_ref
;
5009 if (DEFAULT_ABI
== ABI_DARWIN
)
5012 if (MACHO_DYNAMIC_NO_PIC_P
)
5014 /* Take care of any required data indirection. */
5015 operands
[1] = rs6000_machopic_legitimize_pic_address (
5016 operands
[1], mode
, operands
[0]);
5017 if (operands
[0] != operands
[1])
5018 emit_insn (gen_rtx_SET (VOIDmode
,
5019 operands
[0], operands
[1]));
5023 emit_insn (gen_macho_high (target
, operands
[1]));
5024 emit_insn (gen_macho_low (operands
[0], target
, operands
[1]));
5028 emit_insn (gen_elf_high (target
, operands
[1]));
5029 emit_insn (gen_elf_low (operands
[0], target
, operands
[1]));
5033 /* If this is a SYMBOL_REF that refers to a constant pool entry,
5034 and we have put it in the TOC, we just need to make a TOC-relative
5037 && GET_CODE (operands
[1]) == SYMBOL_REF
5038 && constant_pool_expr_p (operands
[1])
5039 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands
[1]),
5040 get_pool_mode (operands
[1])))
5042 operands
[1] = create_TOC_reference (operands
[1]);
5044 else if (mode
== Pmode
5045 && CONSTANT_P (operands
[1])
5046 && ((GET_CODE (operands
[1]) != CONST_INT
5047 && ! easy_fp_constant (operands
[1], mode
))
5048 || (GET_CODE (operands
[1]) == CONST_INT
5049 && num_insns_constant (operands
[1], mode
) > 2)
5050 || (GET_CODE (operands
[0]) == REG
5051 && FP_REGNO_P (REGNO (operands
[0]))))
5052 && GET_CODE (operands
[1]) != HIGH
5053 && ! legitimate_constant_pool_address_p (operands
[1])
5054 && ! toc_relative_expr_p (operands
[1]))
5056 /* Emit a USE operation so that the constant isn't deleted if
5057 expensive optimizations are turned on because nobody
5058 references it. This should only be done for operands that
5059 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
5060 This should not be done for operands that contain LABEL_REFs.
5061 For now, we just handle the obvious case. */
5062 if (GET_CODE (operands
[1]) != LABEL_REF
)
5063 emit_use (operands
[1]);
5066 /* Darwin uses a special PIC legitimizer. */
5067 if (DEFAULT_ABI
== ABI_DARWIN
&& MACHOPIC_INDIRECT
)
5070 rs6000_machopic_legitimize_pic_address (operands
[1], mode
,
5072 if (operands
[0] != operands
[1])
5073 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
5078 /* If we are to limit the number of things we put in the TOC and
5079 this is a symbol plus a constant we can add in one insn,
5080 just put the symbol in the TOC and add the constant. Don't do
5081 this if reload is in progress. */
5082 if (GET_CODE (operands
[1]) == CONST
5083 && TARGET_NO_SUM_IN_TOC
&& ! reload_in_progress
5084 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
5085 && add_operand (XEXP (XEXP (operands
[1], 0), 1), mode
)
5086 && (GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
5087 || GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == SYMBOL_REF
)
5088 && ! side_effects_p (operands
[0]))
5091 force_const_mem (mode
, XEXP (XEXP (operands
[1], 0), 0));
5092 rtx other
= XEXP (XEXP (operands
[1], 0), 1);
5094 sym
= force_reg (mode
, sym
);
5096 emit_insn (gen_addsi3 (operands
[0], sym
, other
));
5098 emit_insn (gen_adddi3 (operands
[0], sym
, other
));
5102 operands
[1] = force_const_mem (mode
, operands
[1]);
5105 && GET_CODE (XEXP (operands
[1], 0)) == SYMBOL_REF
5106 && constant_pool_expr_p (XEXP (operands
[1], 0))
5107 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
5108 get_pool_constant (XEXP (operands
[1], 0)),
5109 get_pool_mode (XEXP (operands
[1], 0))))
5112 = gen_const_mem (mode
,
5113 create_TOC_reference (XEXP (operands
[1], 0)));
5114 set_mem_alias_set (operands
[1], get_TOC_alias_set ());
5120 rs6000_eliminate_indexed_memrefs (operands
);
5124 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
5126 gen_rtx_SET (VOIDmode
,
5127 operands
[0], operands
[1]),
5128 gen_rtx_CLOBBER (VOIDmode
,
5129 gen_rtx_SCRATCH (SImode
)))));
5138 /* Above, we may have called force_const_mem which may have returned
5139 an invalid address. If we can, fix this up; otherwise, reload will
5140 have to deal with it. */
5141 if (GET_CODE (operands
[1]) == MEM
&& ! reload_in_progress
)
5142 operands
[1] = validize_mem (operands
[1]);
5145 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
5148 /* Nonzero if we can use a floating-point register to pass this arg. */
5149 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
5150 (SCALAR_FLOAT_MODE_P (MODE) \
5151 && (CUM)->fregno <= FP_ARG_MAX_REG \
5152 && TARGET_HARD_FLOAT && TARGET_FPRS)
5154 /* Nonzero if we can use an AltiVec register to pass this arg. */
5155 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
5156 (ALTIVEC_VECTOR_MODE (MODE) \
5157 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
5158 && TARGET_ALTIVEC_ABI \
5161 /* Return a nonzero value to say to return the function value in
5162 memory, just as large structures are always returned. TYPE will be
5163 the data type of the value, and FNTYPE will be the type of the
5164 function doing the returning, or @code{NULL} for libcalls.
5166 The AIX ABI for the RS/6000 specifies that all structures are
5167 returned in memory. The Darwin ABI does the same. The SVR4 ABI
5168 specifies that structures <= 8 bytes are returned in r3/r4, but a
5169 draft put them in memory, and GCC used to implement the draft
5170 instead of the final standard. Therefore, aix_struct_return
5171 controls this instead of DEFAULT_ABI; V.4 targets needing backward
5172 compatibility can change DRAFT_V4_STRUCT_RET to override the
5173 default, and -m switches get the final word. See
5174 rs6000_override_options for more details.
5176 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
5177 long double support is enabled. These values are returned in memory.
5179 int_size_in_bytes returns -1 for variable size objects, which go in
5180 memory always. The cast to unsigned makes -1 > 8. */
5183 rs6000_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5185 /* In the darwin64 abi, try to use registers for larger structs
5187 if (rs6000_darwin64_abi
5188 && TREE_CODE (type
) == RECORD_TYPE
5189 && int_size_in_bytes (type
) > 0)
5191 CUMULATIVE_ARGS valcum
;
5195 valcum
.fregno
= FP_ARG_MIN_REG
;
5196 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
5197 /* Do a trial code generation as if this were going to be passed
5198 as an argument; if any part goes in memory, we return NULL. */
5199 valret
= rs6000_darwin64_record_arg (&valcum
, type
, 1, true);
5202 /* Otherwise fall through to more conventional ABI rules. */
5205 if (AGGREGATE_TYPE_P (type
)
5206 && (aix_struct_return
5207 || (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8))
5210 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5211 modes only exist for GCC vector types if -maltivec. */
5212 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
5213 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
5216 /* Return synthetic vectors in memory. */
5217 if (TREE_CODE (type
) == VECTOR_TYPE
5218 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
5220 static bool warned_for_return_big_vectors
= false;
5221 if (!warned_for_return_big_vectors
)
5223 warning (0, "GCC vector returned by reference: "
5224 "non-standard ABI extension with no compatibility guarantee");
5225 warned_for_return_big_vectors
= true;
5230 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& TYPE_MODE (type
) == TFmode
)
5236 /* Initialize a variable CUM of type CUMULATIVE_ARGS
5237 for a call to a function whose data type is FNTYPE.
5238 For a library call, FNTYPE is 0.
5240 For incoming args we set the number of arguments in the prototype large
5241 so we never return a PARALLEL. */
5244 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
5245 rtx libname ATTRIBUTE_UNUSED
, int incoming
,
5246 int libcall
, int n_named_args
)
5248 static CUMULATIVE_ARGS zero_cumulative
;
5250 *cum
= zero_cumulative
;
5252 cum
->fregno
= FP_ARG_MIN_REG
;
5253 cum
->vregno
= ALTIVEC_ARG_MIN_REG
;
5254 cum
->prototype
= (fntype
&& TYPE_ARG_TYPES (fntype
));
5255 cum
->call_cookie
= ((DEFAULT_ABI
== ABI_V4
&& libcall
)
5256 ? CALL_LIBCALL
: CALL_NORMAL
);
5257 cum
->sysv_gregno
= GP_ARG_MIN_REG
;
5258 cum
->stdarg
= fntype
5259 && (TYPE_ARG_TYPES (fntype
) != 0
5260 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
5261 != void_type_node
));
5263 cum
->nargs_prototype
= 0;
5264 if (incoming
|| cum
->prototype
)
5265 cum
->nargs_prototype
= n_named_args
;
5267 /* Check for a longcall attribute. */
5268 if ((!fntype
&& rs6000_default_long_calls
)
5270 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
))
5271 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
))))
5272 cum
->call_cookie
|= CALL_LONG
;
5274 if (TARGET_DEBUG_ARG
)
5276 fprintf (stderr
, "\ninit_cumulative_args:");
5279 tree ret_type
= TREE_TYPE (fntype
);
5280 fprintf (stderr
, " ret code = %s,",
5281 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
5284 if (cum
->call_cookie
& CALL_LONG
)
5285 fprintf (stderr
, " longcall,");
5287 fprintf (stderr
, " proto = %d, nargs = %d\n",
5288 cum
->prototype
, cum
->nargs_prototype
);
5293 && TARGET_ALTIVEC_ABI
5294 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype
))))
5296 error ("cannot return value in vector register because"
5297 " altivec instructions are disabled, use -maltivec"
5302 /* Return true if TYPE must be passed on the stack and not in registers. */
5305 rs6000_must_pass_in_stack (enum machine_mode mode
, const_tree type
)
5307 if (DEFAULT_ABI
== ABI_AIX
|| TARGET_64BIT
)
5308 return must_pass_in_stack_var_size (mode
, type
);
5310 return must_pass_in_stack_var_size_or_pad (mode
, type
);
5313 /* If defined, a C expression which determines whether, and in which
5314 direction, to pad out an argument with extra space. The value
5315 should be of type `enum direction': either `upward' to pad above
5316 the argument, `downward' to pad below, or `none' to inhibit
5319 For the AIX ABI structs are always stored left shifted in their
5323 function_arg_padding (enum machine_mode mode
, const_tree type
)
5325 #ifndef AGGREGATE_PADDING_FIXED
5326 #define AGGREGATE_PADDING_FIXED 0
5328 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
5329 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
5332 if (!AGGREGATE_PADDING_FIXED
)
5334 /* GCC used to pass structures of the same size as integer types as
5335 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
5336 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
5337 passed padded downward, except that -mstrict-align further
5338 muddied the water in that multi-component structures of 2 and 4
5339 bytes in size were passed padded upward.
5341 The following arranges for best compatibility with previous
5342 versions of gcc, but removes the -mstrict-align dependency. */
5343 if (BYTES_BIG_ENDIAN
)
5345 HOST_WIDE_INT size
= 0;
5347 if (mode
== BLKmode
)
5349 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
5350 size
= int_size_in_bytes (type
);
5353 size
= GET_MODE_SIZE (mode
);
5355 if (size
== 1 || size
== 2 || size
== 4)
5361 if (AGGREGATES_PAD_UPWARD_ALWAYS
)
5363 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
5367 /* Fall back to the default. */
5368 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
5371 /* If defined, a C expression that gives the alignment boundary, in bits,
5372 of an argument with the specified mode and type. If it is not defined,
5373 PARM_BOUNDARY is used for all arguments.
5375 V.4 wants long longs and doubles to be double word aligned. Just
5376 testing the mode size is a boneheaded way to do this as it means
5377 that other types such as complex int are also double word aligned.
5378 However, we're stuck with this because changing the ABI might break
5379 existing library interfaces.
5381 Doubleword align SPE vectors.
5382 Quadword align Altivec vectors.
5383 Quadword align large synthetic vector types. */
5386 function_arg_boundary (enum machine_mode mode
, tree type
)
5388 if (DEFAULT_ABI
== ABI_V4
5389 && (GET_MODE_SIZE (mode
) == 8
5390 || (TARGET_HARD_FLOAT
5392 && (mode
== TFmode
|| mode
== TDmode
))))
5394 else if (SPE_VECTOR_MODE (mode
)
5395 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
5396 && int_size_in_bytes (type
) >= 8
5397 && int_size_in_bytes (type
) < 16))
5399 else if (ALTIVEC_VECTOR_MODE (mode
)
5400 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
5401 && int_size_in_bytes (type
) >= 16))
5403 else if (rs6000_darwin64_abi
&& mode
== BLKmode
5404 && type
&& TYPE_ALIGN (type
) > 64)
5407 return PARM_BOUNDARY
;
5410 /* For a function parm of MODE and TYPE, return the starting word in
5411 the parameter area. NWORDS of the parameter area are already used. */
5414 rs6000_parm_start (enum machine_mode mode
, tree type
, unsigned int nwords
)
5417 unsigned int parm_offset
;
5419 align
= function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
5420 parm_offset
= DEFAULT_ABI
== ABI_V4
? 2 : 6;
5421 return nwords
+ (-(parm_offset
+ nwords
) & align
);
5424 /* Compute the size (in words) of a function argument. */
5426 static unsigned long
5427 rs6000_arg_size (enum machine_mode mode
, tree type
)
5431 if (mode
!= BLKmode
)
5432 size
= GET_MODE_SIZE (mode
);
5434 size
= int_size_in_bytes (type
);
5437 return (size
+ 3) >> 2;
5439 return (size
+ 7) >> 3;
5442 /* Use this to flush pending int fields. */
5445 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*cum
,
5446 HOST_WIDE_INT bitpos
)
5448 unsigned int startbit
, endbit
;
5449 int intregs
, intoffset
;
5450 enum machine_mode mode
;
5452 if (cum
->intoffset
== -1)
5455 intoffset
= cum
->intoffset
;
5456 cum
->intoffset
= -1;
5458 if (intoffset
% BITS_PER_WORD
!= 0)
5460 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
5462 if (mode
== BLKmode
)
5464 /* We couldn't find an appropriate mode, which happens,
5465 e.g., in packed structs when there are 3 bytes to load.
5466 Back intoffset back to the beginning of the word in this
5468 intoffset
= intoffset
& -BITS_PER_WORD
;
5472 startbit
= intoffset
& -BITS_PER_WORD
;
5473 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5474 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
5475 cum
->words
+= intregs
;
5478 /* The darwin64 ABI calls for us to recurse down through structs,
5479 looking for elements passed in registers. Unfortunately, we have
5480 to track int register count here also because of misalignments
5481 in powerpc alignment mode. */
5484 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*cum
,
5486 HOST_WIDE_INT startbitpos
)
5490 for (f
= TYPE_FIELDS (type
); f
; f
= TREE_CHAIN (f
))
5491 if (TREE_CODE (f
) == FIELD_DECL
)
5493 HOST_WIDE_INT bitpos
= startbitpos
;
5494 tree ftype
= TREE_TYPE (f
);
5495 enum machine_mode mode
;
5496 if (ftype
== error_mark_node
)
5498 mode
= TYPE_MODE (ftype
);
5500 if (DECL_SIZE (f
) != 0
5501 && host_integerp (bit_position (f
), 1))
5502 bitpos
+= int_bit_position (f
);
5504 /* ??? FIXME: else assume zero offset. */
5506 if (TREE_CODE (ftype
) == RECORD_TYPE
)
5507 rs6000_darwin64_record_arg_advance_recurse (cum
, ftype
, bitpos
);
5508 else if (USE_FP_FOR_ARG_P (cum
, mode
, ftype
))
5510 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
);
5511 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
5512 cum
->words
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
5514 else if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, 1))
5516 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
);
5520 else if (cum
->intoffset
== -1)
5521 cum
->intoffset
= bitpos
;
5525 /* Update the data in CUM to advance over an argument
5526 of mode MODE and data type TYPE.
5527 (TYPE is null for libcalls where that information may not be available.)
5529 Note that for args passed by reference, function_arg will be called
5530 with MODE and TYPE set to that of the pointer to the arg, not the arg
5534 function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5535 tree type
, int named
, int depth
)
5539 /* Only tick off an argument if we're not recursing. */
5541 cum
->nargs_prototype
--;
5543 if (TARGET_ALTIVEC_ABI
5544 && (ALTIVEC_VECTOR_MODE (mode
)
5545 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
5546 && int_size_in_bytes (type
) == 16)))
5550 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
))
5553 if (!TARGET_ALTIVEC
)
5554 error ("cannot pass argument in vector register because"
5555 " altivec instructions are disabled, use -maltivec"
5558 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
5559 even if it is going to be passed in a vector register.
5560 Darwin does the same for variable-argument functions. */
5561 if ((DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
5562 || (cum
->stdarg
&& DEFAULT_ABI
!= ABI_V4
))
5572 /* Vector parameters must be 16-byte aligned. This places
5573 them at 2 mod 4 in terms of words in 32-bit mode, since
5574 the parameter save area starts at offset 24 from the
5575 stack. In 64-bit mode, they just have to start on an
5576 even word, since the parameter save area is 16-byte
5577 aligned. Space for GPRs is reserved even if the argument
5578 will be passed in memory. */
5580 align
= (2 - cum
->words
) & 3;
5582 align
= cum
->words
& 1;
5583 cum
->words
+= align
+ rs6000_arg_size (mode
, type
);
5585 if (TARGET_DEBUG_ARG
)
5587 fprintf (stderr
, "function_adv: words = %2d, align=%d, ",
5589 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s\n",
5590 cum
->nargs_prototype
, cum
->prototype
,
5591 GET_MODE_NAME (mode
));
5595 else if (TARGET_SPE_ABI
&& TARGET_SPE
&& SPE_VECTOR_MODE (mode
)
5597 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
5600 else if (rs6000_darwin64_abi
5602 && TREE_CODE (type
) == RECORD_TYPE
5603 && (size
= int_size_in_bytes (type
)) > 0)
5605 /* Variable sized types have size == -1 and are
5606 treated as if consisting entirely of ints.
5607 Pad to 16 byte boundary if needed. */
5608 if (TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
5609 && (cum
->words
% 2) != 0)
5611 /* For varargs, we can just go up by the size of the struct. */
5613 cum
->words
+= (size
+ 7) / 8;
5616 /* It is tempting to say int register count just goes up by
5617 sizeof(type)/8, but this is wrong in a case such as
5618 { int; double; int; } [powerpc alignment]. We have to
5619 grovel through the fields for these too. */
5621 rs6000_darwin64_record_arg_advance_recurse (cum
, type
, 0);
5622 rs6000_darwin64_record_arg_advance_flush (cum
,
5623 size
* BITS_PER_UNIT
);
5626 else if (DEFAULT_ABI
== ABI_V4
)
5628 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
5629 && (mode
== SFmode
|| mode
== DFmode
5630 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
5631 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)))
5633 /* _Decimal128 must use an even/odd register pair. This assumes
5634 that the register number is odd when fregno is odd. */
5635 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
5638 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
5639 <= FP_ARG_V4_MAX_REG
)
5640 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
5643 cum
->fregno
= FP_ARG_V4_MAX_REG
+ 1;
5644 if (mode
== DFmode
|| mode
== TFmode
5645 || mode
== DDmode
|| mode
== TDmode
)
5646 cum
->words
+= cum
->words
& 1;
5647 cum
->words
+= rs6000_arg_size (mode
, type
);
5652 int n_words
= rs6000_arg_size (mode
, type
);
5653 int gregno
= cum
->sysv_gregno
;
5655 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5656 (r7,r8) or (r9,r10). As does any other 2 word item such
5657 as complex int due to a historical mistake. */
5659 gregno
+= (1 - gregno
) & 1;
5661 /* Multi-reg args are not split between registers and stack. */
5662 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
5664 /* Long long and SPE vectors are aligned on the stack.
5665 So are other 2 word items such as complex int due to
5666 a historical mistake. */
5668 cum
->words
+= cum
->words
& 1;
5669 cum
->words
+= n_words
;
5672 /* Note: continuing to accumulate gregno past when we've started
5673 spilling to the stack indicates the fact that we've started
5674 spilling to the stack to expand_builtin_saveregs. */
5675 cum
->sysv_gregno
= gregno
+ n_words
;
5678 if (TARGET_DEBUG_ARG
)
5680 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
5681 cum
->words
, cum
->fregno
);
5682 fprintf (stderr
, "gregno = %2d, nargs = %4d, proto = %d, ",
5683 cum
->sysv_gregno
, cum
->nargs_prototype
, cum
->prototype
);
5684 fprintf (stderr
, "mode = %4s, named = %d\n",
5685 GET_MODE_NAME (mode
), named
);
5690 int n_words
= rs6000_arg_size (mode
, type
);
5691 int start_words
= cum
->words
;
5692 int align_words
= rs6000_parm_start (mode
, type
, start_words
);
5694 cum
->words
= align_words
+ n_words
;
5696 if (SCALAR_FLOAT_MODE_P (mode
)
5697 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
5699 /* _Decimal128 must be passed in an even/odd float register pair.
5700 This assumes that the register number is odd when fregno is
5702 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
5704 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
5707 if (TARGET_DEBUG_ARG
)
5709 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
5710 cum
->words
, cum
->fregno
);
5711 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s, ",
5712 cum
->nargs_prototype
, cum
->prototype
, GET_MODE_NAME (mode
));
5713 fprintf (stderr
, "named = %d, align = %d, depth = %d\n",
5714 named
, align_words
- start_words
, depth
);
5720 spe_build_register_parallel (enum machine_mode mode
, int gregno
)
5727 r1
= gen_rtx_REG (DImode
, gregno
);
5728 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
5729 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, r1
));
5733 r1
= gen_rtx_REG (DImode
, gregno
);
5734 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
5735 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
5736 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
5737 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r3
));
5740 r1
= gen_rtx_REG (DImode
, gregno
);
5741 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
5742 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
5743 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
5744 r5
= gen_rtx_REG (DImode
, gregno
+ 4);
5745 r5
= gen_rtx_EXPR_LIST (VOIDmode
, r5
, GEN_INT (16));
5746 r7
= gen_rtx_REG (DImode
, gregno
+ 6);
5747 r7
= gen_rtx_EXPR_LIST (VOIDmode
, r7
, GEN_INT (24));
5748 return gen_rtx_PARALLEL (mode
, gen_rtvec (4, r1
, r3
, r5
, r7
));
5755 /* Determine where to put a SIMD argument on the SPE. */
5757 rs6000_spe_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5760 int gregno
= cum
->sysv_gregno
;
5762 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
5763 are passed and returned in a pair of GPRs for ABI compatibility. */
5764 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
5765 || mode
== DCmode
|| mode
== TCmode
))
5767 int n_words
= rs6000_arg_size (mode
, type
);
5769 /* Doubles go in an odd/even register pair (r5/r6, etc). */
5771 gregno
+= (1 - gregno
) & 1;
5773 /* Multi-reg args are not split between registers and stack. */
5774 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
5777 return spe_build_register_parallel (mode
, gregno
);
5781 int n_words
= rs6000_arg_size (mode
, type
);
5783 /* SPE vectors are put in odd registers. */
5784 if (n_words
== 2 && (gregno
& 1) == 0)
5787 if (gregno
+ n_words
- 1 <= GP_ARG_MAX_REG
)
5790 enum machine_mode m
= SImode
;
5792 r1
= gen_rtx_REG (m
, gregno
);
5793 r1
= gen_rtx_EXPR_LIST (m
, r1
, const0_rtx
);
5794 r2
= gen_rtx_REG (m
, gregno
+ 1);
5795 r2
= gen_rtx_EXPR_LIST (m
, r2
, GEN_INT (4));
5796 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
5803 if (gregno
<= GP_ARG_MAX_REG
)
5804 return gen_rtx_REG (mode
, gregno
);
5810 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
5811 structure between cum->intoffset and bitpos to integer registers. */
5814 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*cum
,
5815 HOST_WIDE_INT bitpos
, rtx rvec
[], int *k
)
5817 enum machine_mode mode
;
5819 unsigned int startbit
, endbit
;
5820 int this_regno
, intregs
, intoffset
;
5823 if (cum
->intoffset
== -1)
5826 intoffset
= cum
->intoffset
;
5827 cum
->intoffset
= -1;
5829 /* If this is the trailing part of a word, try to only load that
5830 much into the register. Otherwise load the whole register. Note
5831 that in the latter case we may pick up unwanted bits. It's not a
5832 problem at the moment but may wish to revisit. */
5834 if (intoffset
% BITS_PER_WORD
!= 0)
5836 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
5838 if (mode
== BLKmode
)
5840 /* We couldn't find an appropriate mode, which happens,
5841 e.g., in packed structs when there are 3 bytes to load.
5842 Back intoffset back to the beginning of the word in this
5844 intoffset
= intoffset
& -BITS_PER_WORD
;
5851 startbit
= intoffset
& -BITS_PER_WORD
;
5852 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5853 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
5854 this_regno
= cum
->words
+ intoffset
/ BITS_PER_WORD
;
5856 if (intregs
> 0 && intregs
> GP_ARG_NUM_REG
- this_regno
)
5859 intregs
= MIN (intregs
, GP_ARG_NUM_REG
- this_regno
);
5863 intoffset
/= BITS_PER_UNIT
;
5866 regno
= GP_ARG_MIN_REG
+ this_regno
;
5867 reg
= gen_rtx_REG (mode
, regno
);
5869 gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
5872 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
5876 while (intregs
> 0);
5879 /* Recursive workhorse for the following. */
5882 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*cum
, const_tree type
,
5883 HOST_WIDE_INT startbitpos
, rtx rvec
[],
5888 for (f
= TYPE_FIELDS (type
); f
; f
= TREE_CHAIN (f
))
5889 if (TREE_CODE (f
) == FIELD_DECL
)
5891 HOST_WIDE_INT bitpos
= startbitpos
;
5892 tree ftype
= TREE_TYPE (f
);
5893 enum machine_mode mode
;
5894 if (ftype
== error_mark_node
)
5896 mode
= TYPE_MODE (ftype
);
5898 if (DECL_SIZE (f
) != 0
5899 && host_integerp (bit_position (f
), 1))
5900 bitpos
+= int_bit_position (f
);
5902 /* ??? FIXME: else assume zero offset. */
5904 if (TREE_CODE (ftype
) == RECORD_TYPE
)
5905 rs6000_darwin64_record_arg_recurse (cum
, ftype
, bitpos
, rvec
, k
);
5906 else if (cum
->named
&& USE_FP_FOR_ARG_P (cum
, mode
, ftype
))
5911 case SCmode
: mode
= SFmode
; break;
5912 case DCmode
: mode
= DFmode
; break;
5913 case TCmode
: mode
= TFmode
; break;
5917 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
5919 = gen_rtx_EXPR_LIST (VOIDmode
,
5920 gen_rtx_REG (mode
, cum
->fregno
++),
5921 GEN_INT (bitpos
/ BITS_PER_UNIT
));
5922 if (mode
== TFmode
|| mode
== TDmode
)
5925 else if (cum
->named
&& USE_ALTIVEC_FOR_ARG_P (cum
, mode
, ftype
, 1))
5927 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
5929 = gen_rtx_EXPR_LIST (VOIDmode
,
5930 gen_rtx_REG (mode
, cum
->vregno
++),
5931 GEN_INT (bitpos
/ BITS_PER_UNIT
));
5933 else if (cum
->intoffset
== -1)
5934 cum
->intoffset
= bitpos
;
5938 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
5939 the register(s) to be used for each field and subfield of a struct
5940 being passed by value, along with the offset of where the
5941 register's value may be found in the block. FP fields go in FP
5942 register, vector fields go in vector registers, and everything
5943 else goes in int registers, packed as in memory.
5945 This code is also used for function return values. RETVAL indicates
5946 whether this is the case.
5948 Much of this is taken from the SPARC V9 port, which has a similar
5949 calling convention. */
5952 rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*orig_cum
, const_tree type
,
5953 int named
, bool retval
)
5955 rtx rvec
[FIRST_PSEUDO_REGISTER
];
5956 int k
= 1, kbase
= 1;
5957 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
5958 /* This is a copy; modifications are not visible to our caller. */
5959 CUMULATIVE_ARGS copy_cum
= *orig_cum
;
5960 CUMULATIVE_ARGS
*cum
= ©_cum
;
5962 /* Pad to 16 byte boundary if needed. */
5963 if (!retval
&& TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
5964 && (cum
->words
% 2) != 0)
5971 /* Put entries into rvec[] for individual FP and vector fields, and
5972 for the chunks of memory that go in int regs. Note we start at
5973 element 1; 0 is reserved for an indication of using memory, and
5974 may or may not be filled in below. */
5975 rs6000_darwin64_record_arg_recurse (cum
, type
, 0, rvec
, &k
);
5976 rs6000_darwin64_record_arg_flush (cum
, typesize
* BITS_PER_UNIT
, rvec
, &k
);
5978 /* If any part of the struct went on the stack put all of it there.
5979 This hack is because the generic code for
5980 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
5981 parts of the struct are not at the beginning. */
5985 return NULL_RTX
; /* doesn't go in registers at all */
5987 rvec
[0] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
5989 if (k
> 1 || cum
->use_stack
)
5990 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (k
- kbase
, &rvec
[kbase
]));
5995 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5998 rs6000_mixed_function_arg (enum machine_mode mode
, tree type
, int align_words
)
6002 rtx rvec
[GP_ARG_NUM_REG
+ 1];
6004 if (align_words
>= GP_ARG_NUM_REG
)
6007 n_units
= rs6000_arg_size (mode
, type
);
6009 /* Optimize the simple case where the arg fits in one gpr, except in
6010 the case of BLKmode due to assign_parms assuming that registers are
6011 BITS_PER_WORD wide. */
6013 || (n_units
== 1 && mode
!= BLKmode
))
6014 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
6017 if (align_words
+ n_units
> GP_ARG_NUM_REG
)
6018 /* Not all of the arg fits in gprs. Say that it goes in memory too,
6019 using a magic NULL_RTX component.
6020 This is not strictly correct. Only some of the arg belongs in
6021 memory, not all of it. However, the normal scheme using
6022 function_arg_partial_nregs can result in unusual subregs, eg.
6023 (subreg:SI (reg:DF) 4), which are not handled well. The code to
6024 store the whole arg to memory is often more efficient than code
6025 to store pieces, and we know that space is available in the right
6026 place for the whole arg. */
6027 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6032 rtx r
= gen_rtx_REG (SImode
, GP_ARG_MIN_REG
+ align_words
);
6033 rtx off
= GEN_INT (i
++ * 4);
6034 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
6036 while (++align_words
< GP_ARG_NUM_REG
&& --n_units
!= 0);
6038 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
6041 /* Determine where to put an argument to a function.
6042 Value is zero to push the argument on the stack,
6043 or a hard register in which to store the argument.
6045 MODE is the argument's machine mode.
6046 TYPE is the data type of the argument (as a tree).
6047 This is null for libcalls where that information may
6049 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6050 the preceding args and about the function being called. It is
6051 not modified in this routine.
6052 NAMED is nonzero if this argument is a named parameter
6053 (otherwise it is an extra parameter matching an ellipsis).
6055 On RS/6000 the first eight words of non-FP are normally in registers
6056 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
6057 Under V.4, the first 8 FP args are in registers.
6059 If this is floating-point and no prototype is specified, we use
6060 both an FP and integer register (or possibly FP reg and stack). Library
6061 functions (when CALL_LIBCALL is set) always have the proper types for args,
6062 so we can pass the FP value just in one register. emit_library_function
6063 doesn't support PARALLEL anyway.
6065 Note that for args passed by reference, function_arg will be called
6066 with MODE and TYPE set to that of the pointer to the arg, not the arg
6070 function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
6071 tree type
, int named
)
6073 enum rs6000_abi abi
= DEFAULT_ABI
;
6075 /* Return a marker to indicate whether CR1 needs to set or clear the
6076 bit that V.4 uses to say fp args were passed in registers.
6077 Assume that we don't need the marker for software floating point,
6078 or compiler generated library calls. */
6079 if (mode
== VOIDmode
)
6082 && (cum
->call_cookie
& CALL_LIBCALL
) == 0
6084 || (cum
->nargs_prototype
< 0
6085 && (cum
->prototype
|| TARGET_NO_PROTOTYPE
))))
6087 /* For the SPE, we need to crxor CR6 always. */
6089 return GEN_INT (cum
->call_cookie
| CALL_V4_SET_FP_ARGS
);
6090 else if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
6091 return GEN_INT (cum
->call_cookie
6092 | ((cum
->fregno
== FP_ARG_MIN_REG
)
6093 ? CALL_V4_SET_FP_ARGS
6094 : CALL_V4_CLEAR_FP_ARGS
));
6097 return GEN_INT (cum
->call_cookie
);
6100 if (rs6000_darwin64_abi
&& mode
== BLKmode
6101 && TREE_CODE (type
) == RECORD_TYPE
)
6103 rtx rslt
= rs6000_darwin64_record_arg (cum
, type
, named
, false);
6104 if (rslt
!= NULL_RTX
)
6106 /* Else fall through to usual handling. */
6109 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
))
6110 if (TARGET_64BIT
&& ! cum
->prototype
)
6112 /* Vector parameters get passed in vector register
6113 and also in GPRs or memory, in absence of prototype. */
6116 align_words
= (cum
->words
+ 1) & ~1;
6118 if (align_words
>= GP_ARG_NUM_REG
)
6124 slot
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
6126 return gen_rtx_PARALLEL (mode
,
6128 gen_rtx_EXPR_LIST (VOIDmode
,
6130 gen_rtx_EXPR_LIST (VOIDmode
,
6131 gen_rtx_REG (mode
, cum
->vregno
),
6135 return gen_rtx_REG (mode
, cum
->vregno
);
6136 else if (TARGET_ALTIVEC_ABI
6137 && (ALTIVEC_VECTOR_MODE (mode
)
6138 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
6139 && int_size_in_bytes (type
) == 16)))
6141 if (named
|| abi
== ABI_V4
)
6145 /* Vector parameters to varargs functions under AIX or Darwin
6146 get passed in memory and possibly also in GPRs. */
6147 int align
, align_words
, n_words
;
6148 enum machine_mode part_mode
;
6150 /* Vector parameters must be 16-byte aligned. This places them at
6151 2 mod 4 in terms of words in 32-bit mode, since the parameter
6152 save area starts at offset 24 from the stack. In 64-bit mode,
6153 they just have to start on an even word, since the parameter
6154 save area is 16-byte aligned. */
6156 align
= (2 - cum
->words
) & 3;
6158 align
= cum
->words
& 1;
6159 align_words
= cum
->words
+ align
;
6161 /* Out of registers? Memory, then. */
6162 if (align_words
>= GP_ARG_NUM_REG
)
6165 if (TARGET_32BIT
&& TARGET_POWERPC64
)
6166 return rs6000_mixed_function_arg (mode
, type
, align_words
);
6168 /* The vector value goes in GPRs. Only the part of the
6169 value in GPRs is reported here. */
6171 n_words
= rs6000_arg_size (mode
, type
);
6172 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
6173 /* Fortunately, there are only two possibilities, the value
6174 is either wholly in GPRs or half in GPRs and half not. */
6177 return gen_rtx_REG (part_mode
, GP_ARG_MIN_REG
+ align_words
);
6180 else if (TARGET_SPE_ABI
&& TARGET_SPE
6181 && (SPE_VECTOR_MODE (mode
)
6182 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
6185 || mode
== TCmode
))))
6186 return rs6000_spe_function_arg (cum
, mode
, type
);
6188 else if (abi
== ABI_V4
)
6190 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
6191 && (mode
== SFmode
|| mode
== DFmode
6192 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
6193 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
6195 /* _Decimal128 must use an even/odd register pair. This assumes
6196 that the register number is odd when fregno is odd. */
6197 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
6200 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
6201 <= FP_ARG_V4_MAX_REG
)
6202 return gen_rtx_REG (mode
, cum
->fregno
);
6208 int n_words
= rs6000_arg_size (mode
, type
);
6209 int gregno
= cum
->sysv_gregno
;
6211 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
6212 (r7,r8) or (r9,r10). As does any other 2 word item such
6213 as complex int due to a historical mistake. */
6215 gregno
+= (1 - gregno
) & 1;
6217 /* Multi-reg args are not split between registers and stack. */
6218 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
6221 if (TARGET_32BIT
&& TARGET_POWERPC64
)
6222 return rs6000_mixed_function_arg (mode
, type
,
6223 gregno
- GP_ARG_MIN_REG
);
6224 return gen_rtx_REG (mode
, gregno
);
6229 int align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
6231 /* _Decimal128 must be passed in an even/odd float register pair.
6232 This assumes that the register number is odd when fregno is odd. */
6233 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
6236 if (USE_FP_FOR_ARG_P (cum
, mode
, type
))
6238 rtx rvec
[GP_ARG_NUM_REG
+ 1];
6242 enum machine_mode fmode
= mode
;
6243 unsigned long n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
6245 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
6247 /* Currently, we only ever need one reg here because complex
6248 doubles are split. */
6249 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
6250 && (fmode
== TFmode
|| fmode
== TDmode
));
6252 /* Long double or _Decimal128 split over regs and memory. */
6253 fmode
= DECIMAL_FLOAT_MODE_P (fmode
) ? DDmode
: DFmode
;
6256 /* Do we also need to pass this arg in the parameter save
6259 && (cum
->nargs_prototype
<= 0
6260 || (DEFAULT_ABI
== ABI_AIX
6262 && align_words
>= GP_ARG_NUM_REG
)));
6264 if (!needs_psave
&& mode
== fmode
)
6265 return gen_rtx_REG (fmode
, cum
->fregno
);
6270 /* Describe the part that goes in gprs or the stack.
6271 This piece must come first, before the fprs. */
6272 if (align_words
< GP_ARG_NUM_REG
)
6274 unsigned long n_words
= rs6000_arg_size (mode
, type
);
6276 if (align_words
+ n_words
> GP_ARG_NUM_REG
6277 || (TARGET_32BIT
&& TARGET_POWERPC64
))
6279 /* If this is partially on the stack, then we only
6280 include the portion actually in registers here. */
6281 enum machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
6284 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
6285 /* Not all of the arg fits in gprs. Say that it
6286 goes in memory too, using a magic NULL_RTX
6287 component. Also see comment in
6288 rs6000_mixed_function_arg for why the normal
6289 function_arg_partial_nregs scheme doesn't work
6291 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
,
6295 r
= gen_rtx_REG (rmode
,
6296 GP_ARG_MIN_REG
+ align_words
);
6297 off
= GEN_INT (i
++ * GET_MODE_SIZE (rmode
));
6298 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
6300 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
6304 /* The whole arg fits in gprs. */
6305 r
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
6306 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
6310 /* It's entirely in memory. */
6311 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6314 /* Describe where this piece goes in the fprs. */
6315 r
= gen_rtx_REG (fmode
, cum
->fregno
);
6316 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
6318 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
6320 else if (align_words
< GP_ARG_NUM_REG
)
6322 if (TARGET_32BIT
&& TARGET_POWERPC64
)
6323 return rs6000_mixed_function_arg (mode
, type
, align_words
);
6325 if (mode
== BLKmode
)
6328 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
6335 /* For an arg passed partly in registers and partly in memory, this is
6336 the number of bytes passed in registers. For args passed entirely in
6337 registers or entirely in memory, zero. When an arg is described by a
6338 PARALLEL, perhaps using more than one register type, this function
6339 returns the number of bytes used by the first element of the PARALLEL. */
6342 rs6000_arg_partial_bytes (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
6343 tree type
, bool named
)
6348 if (DEFAULT_ABI
== ABI_V4
)
6351 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
)
6352 && cum
->nargs_prototype
>= 0)
6355 /* In this complicated case we just disable the partial_nregs code. */
6356 if (rs6000_darwin64_abi
&& mode
== BLKmode
6357 && TREE_CODE (type
) == RECORD_TYPE
6358 && int_size_in_bytes (type
) > 0)
6361 align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
6363 if (USE_FP_FOR_ARG_P (cum
, mode
, type
))
6365 /* If we are passing this arg in the fixed parameter save area
6366 (gprs or memory) as well as fprs, then this function should
6367 return the number of partial bytes passed in the parameter
6368 save area rather than partial bytes passed in fprs. */
6370 && (cum
->nargs_prototype
<= 0
6371 || (DEFAULT_ABI
== ABI_AIX
6373 && align_words
>= GP_ARG_NUM_REG
)))
6375 else if (cum
->fregno
+ ((GET_MODE_SIZE (mode
) + 7) >> 3)
6376 > FP_ARG_MAX_REG
+ 1)
6377 ret
= (FP_ARG_MAX_REG
+ 1 - cum
->fregno
) * 8;
6378 else if (cum
->nargs_prototype
>= 0)
6382 if (align_words
< GP_ARG_NUM_REG
6383 && GP_ARG_NUM_REG
< align_words
+ rs6000_arg_size (mode
, type
))
6384 ret
= (GP_ARG_NUM_REG
- align_words
) * (TARGET_32BIT
? 4 : 8);
6386 if (ret
!= 0 && TARGET_DEBUG_ARG
)
6387 fprintf (stderr
, "rs6000_arg_partial_bytes: %d\n", ret
);
6392 /* A C expression that indicates when an argument must be passed by
6393 reference. If nonzero for an argument, a copy of that argument is
6394 made in memory and a pointer to the argument is passed instead of
6395 the argument itself. The pointer is passed in whatever way is
6396 appropriate for passing a pointer to that type.
6398 Under V.4, aggregates and long double are passed by reference.
6400 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
6401 reference unless the AltiVec vector extension ABI is in force.
6403 As an extension to all ABIs, variable sized types are passed by
6407 rs6000_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
6408 enum machine_mode mode
, const_tree type
,
6409 bool named ATTRIBUTE_UNUSED
)
6411 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& mode
== TFmode
)
6413 if (TARGET_DEBUG_ARG
)
6414 fprintf (stderr
, "function_arg_pass_by_reference: V4 long double\n");
6421 if (DEFAULT_ABI
== ABI_V4
&& AGGREGATE_TYPE_P (type
))
6423 if (TARGET_DEBUG_ARG
)
6424 fprintf (stderr
, "function_arg_pass_by_reference: V4 aggregate\n");
6428 if (int_size_in_bytes (type
) < 0)
6430 if (TARGET_DEBUG_ARG
)
6431 fprintf (stderr
, "function_arg_pass_by_reference: variable size\n");
6435 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
6436 modes only exist for GCC vector types if -maltivec. */
6437 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
6439 if (TARGET_DEBUG_ARG
)
6440 fprintf (stderr
, "function_arg_pass_by_reference: AltiVec\n");
6444 /* Pass synthetic vectors in memory. */
6445 if (TREE_CODE (type
) == VECTOR_TYPE
6446 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
6448 static bool warned_for_pass_big_vectors
= false;
6449 if (TARGET_DEBUG_ARG
)
6450 fprintf (stderr
, "function_arg_pass_by_reference: synthetic vector\n");
6451 if (!warned_for_pass_big_vectors
)
6453 warning (0, "GCC vector passed by reference: "
6454 "non-standard ABI extension with no compatibility guarantee");
6455 warned_for_pass_big_vectors
= true;
6464 rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
)
6467 enum machine_mode reg_mode
= TARGET_32BIT
? SImode
: DImode
;
6472 for (i
= 0; i
< nregs
; i
++)
6474 rtx tem
= adjust_address_nv (x
, reg_mode
, i
* GET_MODE_SIZE (reg_mode
));
6475 if (reload_completed
)
6477 if (! strict_memory_address_p (reg_mode
, XEXP (tem
, 0)))
6480 tem
= simplify_gen_subreg (reg_mode
, x
, BLKmode
,
6481 i
* GET_MODE_SIZE (reg_mode
));
6484 tem
= replace_equiv_address (tem
, XEXP (tem
, 0));
6488 emit_move_insn (tem
, gen_rtx_REG (reg_mode
, regno
+ i
));
6492 /* Perform any needed actions needed for a function that is receiving a
6493 variable number of arguments.
6497 MODE and TYPE are the mode and type of the current parameter.
6499 PRETEND_SIZE is a variable that should be set to the amount of stack
6500 that must be pushed by the prolog to pretend that our caller pushed
6503 Normally, this macro will push all remaining incoming registers on the
6504 stack and set PRETEND_SIZE to the length of the registers pushed. */
6507 setup_incoming_varargs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
6508 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
6511 CUMULATIVE_ARGS next_cum
;
6512 int reg_size
= TARGET_32BIT
? 4 : 8;
6513 rtx save_area
= NULL_RTX
, mem
;
6514 int first_reg_offset
;
6517 /* Skip the last named argument. */
6519 function_arg_advance (&next_cum
, mode
, type
, 1, 0);
6521 if (DEFAULT_ABI
== ABI_V4
)
6523 first_reg_offset
= next_cum
.sysv_gregno
- GP_ARG_MIN_REG
;
6527 int gpr_reg_num
= 0, gpr_size
= 0, fpr_size
= 0;
6528 HOST_WIDE_INT offset
= 0;
6530 /* Try to optimize the size of the varargs save area.
6531 The ABI requires that ap.reg_save_area is doubleword
6532 aligned, but we don't need to allocate space for all
6533 the bytes, only those to which we actually will save
6535 if (cfun
->va_list_gpr_size
&& first_reg_offset
< GP_ARG_NUM_REG
)
6536 gpr_reg_num
= GP_ARG_NUM_REG
- first_reg_offset
;
6537 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
6538 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
6539 && cfun
->va_list_fpr_size
)
6542 fpr_size
= (next_cum
.fregno
- FP_ARG_MIN_REG
)
6543 * UNITS_PER_FP_WORD
;
6544 if (cfun
->va_list_fpr_size
6545 < FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
6546 fpr_size
+= cfun
->va_list_fpr_size
* UNITS_PER_FP_WORD
;
6548 fpr_size
+= (FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
6549 * UNITS_PER_FP_WORD
;
6553 offset
= -((first_reg_offset
* reg_size
) & ~7);
6554 if (!fpr_size
&& gpr_reg_num
> cfun
->va_list_gpr_size
)
6556 gpr_reg_num
= cfun
->va_list_gpr_size
;
6557 if (reg_size
== 4 && (first_reg_offset
& 1))
6560 gpr_size
= (gpr_reg_num
* reg_size
+ 7) & ~7;
6563 offset
= - (int) (next_cum
.fregno
- FP_ARG_MIN_REG
)
6565 - (int) (GP_ARG_NUM_REG
* reg_size
);
6567 if (gpr_size
+ fpr_size
)
6570 = assign_stack_local (BLKmode
, gpr_size
+ fpr_size
, 64);
6571 gcc_assert (GET_CODE (reg_save_area
) == MEM
);
6572 reg_save_area
= XEXP (reg_save_area
, 0);
6573 if (GET_CODE (reg_save_area
) == PLUS
)
6575 gcc_assert (XEXP (reg_save_area
, 0)
6576 == virtual_stack_vars_rtx
);
6577 gcc_assert (GET_CODE (XEXP (reg_save_area
, 1)) == CONST_INT
);
6578 offset
+= INTVAL (XEXP (reg_save_area
, 1));
6581 gcc_assert (reg_save_area
== virtual_stack_vars_rtx
);
6584 cfun
->machine
->varargs_save_offset
= offset
;
6585 save_area
= plus_constant (virtual_stack_vars_rtx
, offset
);
6590 first_reg_offset
= next_cum
.words
;
6591 save_area
= virtual_incoming_args_rtx
;
6593 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
6594 first_reg_offset
+= rs6000_arg_size (TYPE_MODE (type
), type
);
6597 set
= get_varargs_alias_set ();
6598 if (! no_rtl
&& first_reg_offset
< GP_ARG_NUM_REG
6599 && cfun
->va_list_gpr_size
)
6601 int nregs
= GP_ARG_NUM_REG
- first_reg_offset
;
6603 if (va_list_gpr_counter_field
)
6605 /* V4 va_list_gpr_size counts number of registers needed. */
6606 if (nregs
> cfun
->va_list_gpr_size
)
6607 nregs
= cfun
->va_list_gpr_size
;
6611 /* char * va_list instead counts number of bytes needed. */
6612 if (nregs
> cfun
->va_list_gpr_size
/ reg_size
)
6613 nregs
= cfun
->va_list_gpr_size
/ reg_size
;
6616 mem
= gen_rtx_MEM (BLKmode
,
6617 plus_constant (save_area
,
6618 first_reg_offset
* reg_size
));
6619 MEM_NOTRAP_P (mem
) = 1;
6620 set_mem_alias_set (mem
, set
);
6621 set_mem_align (mem
, BITS_PER_WORD
);
6623 rs6000_move_block_from_reg (GP_ARG_MIN_REG
+ first_reg_offset
, mem
,
6627 /* Save FP registers if needed. */
6628 if (DEFAULT_ABI
== ABI_V4
6629 && TARGET_HARD_FLOAT
&& TARGET_FPRS
6631 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
6632 && cfun
->va_list_fpr_size
)
6634 int fregno
= next_cum
.fregno
, nregs
;
6635 rtx cr1
= gen_rtx_REG (CCmode
, CR1_REGNO
);
6636 rtx lab
= gen_label_rtx ();
6637 int off
= (GP_ARG_NUM_REG
* reg_size
) + ((fregno
- FP_ARG_MIN_REG
)
6638 * UNITS_PER_FP_WORD
);
6641 (gen_rtx_SET (VOIDmode
,
6643 gen_rtx_IF_THEN_ELSE (VOIDmode
,
6644 gen_rtx_NE (VOIDmode
, cr1
,
6646 gen_rtx_LABEL_REF (VOIDmode
, lab
),
6650 fregno
<= FP_ARG_V4_MAX_REG
&& nregs
< cfun
->va_list_fpr_size
;
6651 fregno
++, off
+= UNITS_PER_FP_WORD
, nregs
++)
6653 mem
= gen_rtx_MEM (DFmode
, plus_constant (save_area
, off
));
6654 MEM_NOTRAP_P (mem
) = 1;
6655 set_mem_alias_set (mem
, set
);
6656 set_mem_align (mem
, GET_MODE_ALIGNMENT (DFmode
));
6657 emit_move_insn (mem
, gen_rtx_REG (DFmode
, fregno
));
6664 /* Create the va_list data type. */
6667 rs6000_build_builtin_va_list (void)
6669 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
, record
, type_decl
;
6671 /* For AIX, prefer 'char *' because that's what the system
6672 header files like. */
6673 if (DEFAULT_ABI
!= ABI_V4
)
6674 return build_pointer_type (char_type_node
);
6676 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
6677 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
6679 f_gpr
= build_decl (FIELD_DECL
, get_identifier ("gpr"),
6680 unsigned_char_type_node
);
6681 f_fpr
= build_decl (FIELD_DECL
, get_identifier ("fpr"),
6682 unsigned_char_type_node
);
6683 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
6685 f_res
= build_decl (FIELD_DECL
, get_identifier ("reserved"),
6686 short_unsigned_type_node
);
6687 f_ovf
= build_decl (FIELD_DECL
, get_identifier ("overflow_arg_area"),
6689 f_sav
= build_decl (FIELD_DECL
, get_identifier ("reg_save_area"),
6692 va_list_gpr_counter_field
= f_gpr
;
6693 va_list_fpr_counter_field
= f_fpr
;
6695 DECL_FIELD_CONTEXT (f_gpr
) = record
;
6696 DECL_FIELD_CONTEXT (f_fpr
) = record
;
6697 DECL_FIELD_CONTEXT (f_res
) = record
;
6698 DECL_FIELD_CONTEXT (f_ovf
) = record
;
6699 DECL_FIELD_CONTEXT (f_sav
) = record
;
6701 TREE_CHAIN (record
) = type_decl
;
6702 TYPE_NAME (record
) = type_decl
;
6703 TYPE_FIELDS (record
) = f_gpr
;
6704 TREE_CHAIN (f_gpr
) = f_fpr
;
6705 TREE_CHAIN (f_fpr
) = f_res
;
6706 TREE_CHAIN (f_res
) = f_ovf
;
6707 TREE_CHAIN (f_ovf
) = f_sav
;
6709 layout_type (record
);
6711 /* The correct type is an array type of one element. */
6712 return build_array_type (record
, build_index_type (size_zero_node
));
6715 /* Implement va_start. */
6718 rs6000_va_start (tree valist
, rtx nextarg
)
6720 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
6721 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
6722 tree gpr
, fpr
, ovf
, sav
, t
;
6724 /* Only SVR4 needs something special. */
6725 if (DEFAULT_ABI
!= ABI_V4
)
6727 std_expand_builtin_va_start (valist
, nextarg
);
6731 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
6732 f_fpr
= TREE_CHAIN (f_gpr
);
6733 f_res
= TREE_CHAIN (f_fpr
);
6734 f_ovf
= TREE_CHAIN (f_res
);
6735 f_sav
= TREE_CHAIN (f_ovf
);
6737 valist
= build_va_arg_indirect_ref (valist
);
6738 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
6739 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
6741 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
6743 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
6746 /* Count number of gp and fp argument registers used. */
6747 words
= crtl
->args
.info
.words
;
6748 n_gpr
= MIN (crtl
->args
.info
.sysv_gregno
- GP_ARG_MIN_REG
,
6750 n_fpr
= MIN (crtl
->args
.info
.fregno
- FP_ARG_MIN_REG
,
6753 if (TARGET_DEBUG_ARG
)
6754 fprintf (stderr
, "va_start: words = "HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
6755 HOST_WIDE_INT_PRINT_DEC
", n_fpr = "HOST_WIDE_INT_PRINT_DEC
"\n",
6756 words
, n_gpr
, n_fpr
);
6758 if (cfun
->va_list_gpr_size
)
6760 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
6761 build_int_cst (NULL_TREE
, n_gpr
));
6762 TREE_SIDE_EFFECTS (t
) = 1;
6763 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6766 if (cfun
->va_list_fpr_size
)
6768 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
6769 build_int_cst (NULL_TREE
, n_fpr
));
6770 TREE_SIDE_EFFECTS (t
) = 1;
6771 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6774 /* Find the overflow area. */
6775 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
6777 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (ovf
), t
,
6778 size_int (words
* UNITS_PER_WORD
));
6779 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
6780 TREE_SIDE_EFFECTS (t
) = 1;
6781 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6783 /* If there were no va_arg invocations, don't set up the register
6785 if (!cfun
->va_list_gpr_size
6786 && !cfun
->va_list_fpr_size
6787 && n_gpr
< GP_ARG_NUM_REG
6788 && n_fpr
< FP_ARG_V4_MAX_REG
)
6791 /* Find the register save area. */
6792 t
= make_tree (TREE_TYPE (sav
), virtual_stack_vars_rtx
);
6793 if (cfun
->machine
->varargs_save_offset
)
6794 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (sav
), t
,
6795 size_int (cfun
->machine
->varargs_save_offset
));
6796 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
6797 TREE_SIDE_EFFECTS (t
) = 1;
6798 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6801 /* Implement va_arg. */
6804 rs6000_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
6807 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
6808 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
6809 int size
, rsize
, n_reg
, sav_ofs
, sav_scale
;
6810 tree lab_false
, lab_over
, addr
;
6812 tree ptrtype
= build_pointer_type (type
);
6816 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
6818 t
= rs6000_gimplify_va_arg (valist
, ptrtype
, pre_p
, post_p
);
6819 return build_va_arg_indirect_ref (t
);
6822 if (DEFAULT_ABI
!= ABI_V4
)
6824 if (targetm
.calls
.split_complex_arg
&& TREE_CODE (type
) == COMPLEX_TYPE
)
6826 tree elem_type
= TREE_TYPE (type
);
6827 enum machine_mode elem_mode
= TYPE_MODE (elem_type
);
6828 int elem_size
= GET_MODE_SIZE (elem_mode
);
6830 if (elem_size
< UNITS_PER_WORD
)
6832 tree real_part
, imag_part
;
6833 gimple_seq post
= NULL
;
6835 real_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
6837 /* Copy the value into a temporary, lest the formal temporary
6838 be reused out from under us. */
6839 real_part
= get_initialized_tmp_var (real_part
, pre_p
, &post
);
6840 gimple_seq_add_seq (pre_p
, post
);
6842 imag_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
6845 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
6849 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
6852 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
6853 f_fpr
= TREE_CHAIN (f_gpr
);
6854 f_res
= TREE_CHAIN (f_fpr
);
6855 f_ovf
= TREE_CHAIN (f_res
);
6856 f_sav
= TREE_CHAIN (f_ovf
);
6858 valist
= build_va_arg_indirect_ref (valist
);
6859 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
6860 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
6862 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
6864 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
6867 size
= int_size_in_bytes (type
);
6868 rsize
= (size
+ 3) / 4;
6871 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
6872 && (TYPE_MODE (type
) == SFmode
6873 || TYPE_MODE (type
) == DFmode
6874 || TYPE_MODE (type
) == TFmode
6875 || TYPE_MODE (type
) == SDmode
6876 || TYPE_MODE (type
) == DDmode
6877 || TYPE_MODE (type
) == TDmode
))
6879 /* FP args go in FP registers, if present. */
6881 n_reg
= (size
+ 7) / 8;
6884 if (TYPE_MODE (type
) != SFmode
&& TYPE_MODE (type
) != SDmode
)
6889 /* Otherwise into GP registers. */
6898 /* Pull the value out of the saved registers.... */
6901 addr
= create_tmp_var (ptr_type_node
, "addr");
6902 DECL_POINTER_ALIAS_SET (addr
) = get_varargs_alias_set ();
6904 /* AltiVec vectors never go in registers when -mabi=altivec. */
6905 if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
6909 lab_false
= create_artificial_label ();
6910 lab_over
= create_artificial_label ();
6912 /* Long long and SPE vectors are aligned in the registers.
6913 As are any other 2 gpr item such as complex int due to a
6914 historical mistake. */
6916 if (n_reg
== 2 && reg
== gpr
)
6919 u
= build2 (BIT_AND_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
6920 build_int_cst (TREE_TYPE (reg
), n_reg
- 1));
6921 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
),
6922 unshare_expr (reg
), u
);
6924 /* _Decimal128 is passed in even/odd fpr pairs; the stored
6925 reg number is 0 for f1, so we want to make it odd. */
6926 else if (reg
== fpr
&& TYPE_MODE (type
) == TDmode
)
6929 t
= build2 (BIT_IOR_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
6930 build_int_cst (TREE_TYPE (reg
), 1));
6931 u
= build2 (MODIFY_EXPR
, void_type_node
, unshare_expr (reg
), t
);
6934 t
= fold_convert (TREE_TYPE (reg
), size_int (8 - n_reg
+ 1));
6935 t
= build2 (GE_EXPR
, boolean_type_node
, u
, t
);
6936 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
6937 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
6938 gimplify_and_add (t
, pre_p
);
6942 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, sav
, size_int (sav_ofs
));
6944 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
6945 build_int_cst (TREE_TYPE (reg
), n_reg
));
6946 u
= fold_convert (sizetype
, u
);
6947 u
= build2 (MULT_EXPR
, sizetype
, u
, size_int (sav_scale
));
6948 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, t
, u
);
6950 /* _Decimal32 varargs are located in the second word of the 64-bit
6951 FP register for 32-bit binaries. */
6952 if (!TARGET_POWERPC64
6953 && TARGET_HARD_FLOAT
&& TARGET_FPRS
6954 && TYPE_MODE (type
) == SDmode
)
6955 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (t
), t
, size_int (size
));
6957 gimplify_assign (addr
, t
, pre_p
);
6959 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
6961 stmt
= gimple_build_label (lab_false
);
6962 gimple_seq_add_stmt (pre_p
, stmt
);
6964 if ((n_reg
== 2 && !regalign
) || n_reg
> 2)
6966 /* Ensure that we don't find any more args in regs.
6967 Alignment has taken care of for special cases. */
6968 gimplify_assign (reg
, build_int_cst (TREE_TYPE (reg
), 8), pre_p
);
6972 /* ... otherwise out of the overflow area. */
6974 /* Care for on-stack alignment if needed. */
6978 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (t
), t
, size_int (align
- 1));
6979 t
= fold_convert (sizetype
, t
);
6980 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
6982 t
= fold_convert (TREE_TYPE (ovf
), t
);
6984 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
6986 gimplify_assign (unshare_expr (addr
), t
, pre_p
);
6988 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (t
), t
, size_int (size
));
6989 gimplify_assign (unshare_expr (ovf
), t
, pre_p
);
6993 stmt
= gimple_build_label (lab_over
);
6994 gimple_seq_add_stmt (pre_p
, stmt
);
6997 if (STRICT_ALIGNMENT
6998 && (TYPE_ALIGN (type
)
6999 > (unsigned) BITS_PER_UNIT
* (align
< 4 ? 4 : align
)))
7001 /* The value (of type complex double, for example) may not be
7002 aligned in memory in the saved registers, so copy via a
7003 temporary. (This is the same code as used for SPARC.) */
7004 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
7005 tree dest_addr
= build_fold_addr_expr (tmp
);
7007 tree copy
= build_call_expr (implicit_built_in_decls
[BUILT_IN_MEMCPY
],
7008 3, dest_addr
, addr
, size_int (rsize
* 4));
7010 gimplify_and_add (copy
, pre_p
);
7014 addr
= fold_convert (ptrtype
, addr
);
7015 return build_va_arg_indirect_ref (addr
);
7021 def_builtin (int mask
, const char *name
, tree type
, int code
)
7023 if ((mask
& target_flags
) || TARGET_PAIRED_FLOAT
)
7025 if (rs6000_builtin_decls
[code
])
7028 rs6000_builtin_decls
[code
] =
7029 add_builtin_function (name
, type
, code
, BUILT_IN_MD
,
7034 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
7036 static const struct builtin_description bdesc_3arg
[] =
7038 { MASK_ALTIVEC
, CODE_FOR_altivec_vmaddfp
, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP
},
7039 { MASK_ALTIVEC
, CODE_FOR_altivec_vmhaddshs
, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS
},
7040 { MASK_ALTIVEC
, CODE_FOR_altivec_vmhraddshs
, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS
},
7041 { MASK_ALTIVEC
, CODE_FOR_altivec_vmladduhm
, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM
},
7042 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumubm
, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM
},
7043 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsummbm
, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM
},
7044 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumuhm
, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM
},
7045 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumshm
, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM
},
7046 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumuhs
, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS
},
7047 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumshs
, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS
},
7048 { MASK_ALTIVEC
, CODE_FOR_altivec_vnmsubfp
, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP
},
7049 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v4sf
, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF
},
7050 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v4si
, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI
},
7051 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v8hi
, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI
},
7052 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v16qi
, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI
},
7053 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v4sf
, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF
},
7054 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v4si
, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI
},
7055 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v8hi
, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI
},
7056 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v16qi
, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI
},
7057 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v16qi
, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI
},
7058 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v8hi
, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI
},
7059 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v4si
, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI
},
7060 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v4sf
, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF
},
7062 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD
},
7063 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS
},
7064 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD
},
7065 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS
},
7066 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM
},
7067 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM
},
7068 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM
},
7069 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM
},
7070 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM
},
7071 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS
},
7072 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS
},
7073 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS
},
7074 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB
},
7075 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM
},
7076 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL
},
7078 { 0, CODE_FOR_paired_msub
, "__builtin_paired_msub", PAIRED_BUILTIN_MSUB
},
7079 { 0, CODE_FOR_paired_madd
, "__builtin_paired_madd", PAIRED_BUILTIN_MADD
},
7080 { 0, CODE_FOR_paired_madds0
, "__builtin_paired_madds0", PAIRED_BUILTIN_MADDS0
},
7081 { 0, CODE_FOR_paired_madds1
, "__builtin_paired_madds1", PAIRED_BUILTIN_MADDS1
},
7082 { 0, CODE_FOR_paired_nmsub
, "__builtin_paired_nmsub", PAIRED_BUILTIN_NMSUB
},
7083 { 0, CODE_FOR_paired_nmadd
, "__builtin_paired_nmadd", PAIRED_BUILTIN_NMADD
},
7084 { 0, CODE_FOR_paired_sum0
, "__builtin_paired_sum0", PAIRED_BUILTIN_SUM0
},
7085 { 0, CODE_FOR_paired_sum1
, "__builtin_paired_sum1", PAIRED_BUILTIN_SUM1
},
7086 { 0, CODE_FOR_selv2sf4
, "__builtin_paired_selv2sf4", PAIRED_BUILTIN_SELV2SF4
},
7089 /* DST operations: void foo (void *, const int, const char). */
7091 static const struct builtin_description bdesc_dst
[] =
7093 { MASK_ALTIVEC
, CODE_FOR_altivec_dst
, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST
},
7094 { MASK_ALTIVEC
, CODE_FOR_altivec_dstt
, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT
},
7095 { MASK_ALTIVEC
, CODE_FOR_altivec_dstst
, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST
},
7096 { MASK_ALTIVEC
, CODE_FOR_altivec_dststt
, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT
},
7098 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST
},
7099 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT
},
7100 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST
},
7101 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT
}
7104 /* Simple binary operations: VECc = foo (VECa, VECb). */
7106 static struct builtin_description bdesc_2arg
[] =
7108 { MASK_ALTIVEC
, CODE_FOR_addv16qi3
, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM
},
7109 { MASK_ALTIVEC
, CODE_FOR_addv8hi3
, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM
},
7110 { MASK_ALTIVEC
, CODE_FOR_addv4si3
, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM
},
7111 { MASK_ALTIVEC
, CODE_FOR_addv4sf3
, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP
},
7112 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddcuw
, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW
},
7113 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddubs
, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS
},
7114 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddsbs
, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS
},
7115 { MASK_ALTIVEC
, CODE_FOR_altivec_vadduhs
, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS
},
7116 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddshs
, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS
},
7117 { MASK_ALTIVEC
, CODE_FOR_altivec_vadduws
, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS
},
7118 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddsws
, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS
},
7119 { MASK_ALTIVEC
, CODE_FOR_andv4si3
, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND
},
7120 { MASK_ALTIVEC
, CODE_FOR_andcv4si3
, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC
},
7121 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgub
, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB
},
7122 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgsb
, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB
},
7123 { MASK_ALTIVEC
, CODE_FOR_altivec_vavguh
, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH
},
7124 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgsh
, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH
},
7125 { MASK_ALTIVEC
, CODE_FOR_altivec_vavguw
, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW
},
7126 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgsw
, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW
},
7127 { MASK_ALTIVEC
, CODE_FOR_altivec_vcfux
, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX
},
7128 { MASK_ALTIVEC
, CODE_FOR_altivec_vcfsx
, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX
},
7129 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpbfp
, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP
},
7130 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpequb
, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB
},
7131 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpequh
, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH
},
7132 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpequw
, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW
},
7133 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpeqfp
, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP
},
7134 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgefp
, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP
},
7135 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtub
, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB
},
7136 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtsb
, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB
},
7137 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtuh
, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH
},
7138 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtsh
, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH
},
7139 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtuw
, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW
},
7140 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtsw
, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW
},
7141 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtfp
, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP
},
7142 { MASK_ALTIVEC
, CODE_FOR_altivec_vctsxs
, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS
},
7143 { MASK_ALTIVEC
, CODE_FOR_altivec_vctuxs
, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS
},
7144 { MASK_ALTIVEC
, CODE_FOR_umaxv16qi3
, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB
},
7145 { MASK_ALTIVEC
, CODE_FOR_smaxv16qi3
, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB
},
7146 { MASK_ALTIVEC
, CODE_FOR_umaxv8hi3
, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH
},
7147 { MASK_ALTIVEC
, CODE_FOR_smaxv8hi3
, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH
},
7148 { MASK_ALTIVEC
, CODE_FOR_umaxv4si3
, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW
},
7149 { MASK_ALTIVEC
, CODE_FOR_smaxv4si3
, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW
},
7150 { MASK_ALTIVEC
, CODE_FOR_smaxv4sf3
, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP
},
7151 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrghb
, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB
},
7152 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrghh
, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH
},
7153 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrghw
, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW
},
7154 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrglb
, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB
},
7155 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrglh
, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH
},
7156 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrglw
, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW
},
7157 { MASK_ALTIVEC
, CODE_FOR_uminv16qi3
, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB
},
7158 { MASK_ALTIVEC
, CODE_FOR_sminv16qi3
, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB
},
7159 { MASK_ALTIVEC
, CODE_FOR_uminv8hi3
, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH
},
7160 { MASK_ALTIVEC
, CODE_FOR_sminv8hi3
, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH
},
7161 { MASK_ALTIVEC
, CODE_FOR_uminv4si3
, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW
},
7162 { MASK_ALTIVEC
, CODE_FOR_sminv4si3
, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW
},
7163 { MASK_ALTIVEC
, CODE_FOR_sminv4sf3
, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP
},
7164 { MASK_ALTIVEC
, CODE_FOR_altivec_vmuleub
, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB
},
7165 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulesb
, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB
},
7166 { MASK_ALTIVEC
, CODE_FOR_altivec_vmuleuh
, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH
},
7167 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulesh
, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH
},
7168 { MASK_ALTIVEC
, CODE_FOR_altivec_vmuloub
, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB
},
7169 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulosb
, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB
},
7170 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulouh
, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH
},
7171 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulosh
, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH
},
7172 { MASK_ALTIVEC
, CODE_FOR_altivec_norv4si3
, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR
},
7173 { MASK_ALTIVEC
, CODE_FOR_iorv4si3
, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR
},
7174 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhum
, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM
},
7175 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwum
, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM
},
7176 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkpx
, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX
},
7177 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkshss
, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS
},
7178 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkswss
, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS
},
7179 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhus
, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS
},
7180 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkshus
, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS
},
7181 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwus
, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS
},
7182 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkswus
, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS
},
7183 { MASK_ALTIVEC
, CODE_FOR_altivec_vrlb
, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB
},
7184 { MASK_ALTIVEC
, CODE_FOR_altivec_vrlh
, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH
},
7185 { MASK_ALTIVEC
, CODE_FOR_altivec_vrlw
, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW
},
7186 { MASK_ALTIVEC
, CODE_FOR_vashlv16qi3
, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB
},
7187 { MASK_ALTIVEC
, CODE_FOR_vashlv8hi3
, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH
},
7188 { MASK_ALTIVEC
, CODE_FOR_vashlv4si3
, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW
},
7189 { MASK_ALTIVEC
, CODE_FOR_altivec_vsl
, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL
},
7190 { MASK_ALTIVEC
, CODE_FOR_altivec_vslo
, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO
},
7191 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltb
, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB
},
7192 { MASK_ALTIVEC
, CODE_FOR_altivec_vsplth
, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH
},
7193 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltw
, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW
},
7194 { MASK_ALTIVEC
, CODE_FOR_vlshrv16qi3
, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB
},
7195 { MASK_ALTIVEC
, CODE_FOR_vlshrv8hi3
, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH
},
7196 { MASK_ALTIVEC
, CODE_FOR_vlshrv4si3
, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW
},
7197 { MASK_ALTIVEC
, CODE_FOR_vashrv16qi3
, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB
},
7198 { MASK_ALTIVEC
, CODE_FOR_vashrv8hi3
, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH
},
7199 { MASK_ALTIVEC
, CODE_FOR_vashrv4si3
, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW
},
7200 { MASK_ALTIVEC
, CODE_FOR_altivec_vsr
, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR
},
7201 { MASK_ALTIVEC
, CODE_FOR_altivec_vsro
, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO
},
7202 { MASK_ALTIVEC
, CODE_FOR_subv16qi3
, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM
},
7203 { MASK_ALTIVEC
, CODE_FOR_subv8hi3
, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM
},
7204 { MASK_ALTIVEC
, CODE_FOR_subv4si3
, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM
},
7205 { MASK_ALTIVEC
, CODE_FOR_subv4sf3
, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP
},
7206 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubcuw
, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW
},
7207 { MASK_ALTIVEC
, CODE_FOR_altivec_vsububs
, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS
},
7208 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubsbs
, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS
},
7209 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubuhs
, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS
},
7210 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubshs
, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS
},
7211 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubuws
, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS
},
7212 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubsws
, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS
},
7213 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum4ubs
, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS
},
7214 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum4sbs
, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS
},
7215 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum4shs
, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS
},
7216 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum2sws
, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS
},
7217 { MASK_ALTIVEC
, CODE_FOR_altivec_vsumsws
, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS
},
7218 { MASK_ALTIVEC
, CODE_FOR_xorv4si3
, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR
},
7220 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD
},
7221 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP
},
7222 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM
},
7223 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM
},
7224 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM
},
7225 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC
},
7226 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS
},
7227 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS
},
7228 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS
},
7229 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS
},
7230 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS
},
7231 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS
},
7232 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS
},
7233 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND
},
7234 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC
},
7235 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG
},
7236 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW
},
7237 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW
},
7238 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH
},
7239 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH
},
7240 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB
},
7241 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB
},
7242 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB
},
7243 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ
},
7244 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP
},
7245 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW
},
7246 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH
},
7247 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB
},
7248 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE
},
7249 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT
},
7250 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP
},
7251 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW
},
7252 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW
},
7253 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH
},
7254 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH
},
7255 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB
},
7256 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB
},
7257 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE
},
7258 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT
},
7259 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX
},
7260 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP
},
7261 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW
},
7262 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW
},
7263 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH
},
7264 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH
},
7265 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB
},
7266 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB
},
7267 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH
},
7268 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW
},
7269 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH
},
7270 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB
},
7271 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL
},
7272 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW
},
7273 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH
},
7274 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB
},
7275 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN
},
7276 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP
},
7277 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW
},
7278 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW
},
7279 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH
},
7280 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH
},
7281 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB
},
7282 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB
},
7283 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE
},
7284 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB
},
7285 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB
},
7286 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH
},
7287 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH
},
7288 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO
},
7289 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH
},
7290 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH
},
7291 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB
},
7292 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB
},
7293 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR
},
7294 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR
},
7295 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK
},
7296 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM
},
7297 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM
},
7298 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX
},
7299 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS
},
7300 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS
},
7301 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS
},
7302 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS
},
7303 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS
},
7304 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU
},
7305 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS
},
7306 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS
},
7307 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL
},
7308 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW
},
7309 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH
},
7310 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB
},
7311 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL
},
7312 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW
},
7313 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH
},
7314 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB
},
7315 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL
},
7316 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO
},
7317 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR
},
7318 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW
},
7319 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH
},
7320 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB
},
7321 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA
},
7322 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW
},
7323 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH
},
7324 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB
},
7325 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL
},
7326 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO
},
7327 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB
},
7328 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP
},
7329 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM
},
7330 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM
},
7331 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM
},
7332 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC
},
7333 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS
},
7334 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS
},
7335 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS
},
7336 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS
},
7337 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS
},
7338 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS
},
7339 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS
},
7340 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S
},
7341 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS
},
7342 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS
},
7343 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS
},
7344 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S
},
7345 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS
},
7346 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR
},
7348 { 0, CODE_FOR_divv2sf3
, "__builtin_paired_divv2sf3", PAIRED_BUILTIN_DIVV2SF3
},
7349 { 0, CODE_FOR_addv2sf3
, "__builtin_paired_addv2sf3", PAIRED_BUILTIN_ADDV2SF3
},
7350 { 0, CODE_FOR_subv2sf3
, "__builtin_paired_subv2sf3", PAIRED_BUILTIN_SUBV2SF3
},
7351 { 0, CODE_FOR_mulv2sf3
, "__builtin_paired_mulv2sf3", PAIRED_BUILTIN_MULV2SF3
},
7352 { 0, CODE_FOR_paired_muls0
, "__builtin_paired_muls0", PAIRED_BUILTIN_MULS0
},
7353 { 0, CODE_FOR_paired_muls1
, "__builtin_paired_muls1", PAIRED_BUILTIN_MULS1
},
7354 { 0, CODE_FOR_paired_merge00
, "__builtin_paired_merge00", PAIRED_BUILTIN_MERGE00
},
7355 { 0, CODE_FOR_paired_merge01
, "__builtin_paired_merge01", PAIRED_BUILTIN_MERGE01
},
7356 { 0, CODE_FOR_paired_merge10
, "__builtin_paired_merge10", PAIRED_BUILTIN_MERGE10
},
7357 { 0, CODE_FOR_paired_merge11
, "__builtin_paired_merge11", PAIRED_BUILTIN_MERGE11
},
7359 /* Place holder, leave as first spe builtin. */
7360 { 0, CODE_FOR_spe_evaddw
, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW
},
7361 { 0, CODE_FOR_spe_evand
, "__builtin_spe_evand", SPE_BUILTIN_EVAND
},
7362 { 0, CODE_FOR_spe_evandc
, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC
},
7363 { 0, CODE_FOR_spe_evdivws
, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS
},
7364 { 0, CODE_FOR_spe_evdivwu
, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU
},
7365 { 0, CODE_FOR_spe_eveqv
, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV
},
7366 { 0, CODE_FOR_spe_evfsadd
, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD
},
7367 { 0, CODE_FOR_spe_evfsdiv
, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV
},
7368 { 0, CODE_FOR_spe_evfsmul
, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL
},
7369 { 0, CODE_FOR_spe_evfssub
, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB
},
7370 { 0, CODE_FOR_spe_evmergehi
, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI
},
7371 { 0, CODE_FOR_spe_evmergehilo
, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO
},
7372 { 0, CODE_FOR_spe_evmergelo
, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO
},
7373 { 0, CODE_FOR_spe_evmergelohi
, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI
},
7374 { 0, CODE_FOR_spe_evmhegsmfaa
, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA
},
7375 { 0, CODE_FOR_spe_evmhegsmfan
, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN
},
7376 { 0, CODE_FOR_spe_evmhegsmiaa
, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA
},
7377 { 0, CODE_FOR_spe_evmhegsmian
, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN
},
7378 { 0, CODE_FOR_spe_evmhegumiaa
, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA
},
7379 { 0, CODE_FOR_spe_evmhegumian
, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN
},
7380 { 0, CODE_FOR_spe_evmhesmf
, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF
},
7381 { 0, CODE_FOR_spe_evmhesmfa
, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA
},
7382 { 0, CODE_FOR_spe_evmhesmfaaw
, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW
},
7383 { 0, CODE_FOR_spe_evmhesmfanw
, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW
},
7384 { 0, CODE_FOR_spe_evmhesmi
, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI
},
7385 { 0, CODE_FOR_spe_evmhesmia
, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA
},
7386 { 0, CODE_FOR_spe_evmhesmiaaw
, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW
},
7387 { 0, CODE_FOR_spe_evmhesmianw
, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW
},
7388 { 0, CODE_FOR_spe_evmhessf
, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF
},
7389 { 0, CODE_FOR_spe_evmhessfa
, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA
},
7390 { 0, CODE_FOR_spe_evmhessfaaw
, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW
},
7391 { 0, CODE_FOR_spe_evmhessfanw
, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW
},
7392 { 0, CODE_FOR_spe_evmhessiaaw
, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW
},
7393 { 0, CODE_FOR_spe_evmhessianw
, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW
},
7394 { 0, CODE_FOR_spe_evmheumi
, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI
},
7395 { 0, CODE_FOR_spe_evmheumia
, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA
},
7396 { 0, CODE_FOR_spe_evmheumiaaw
, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW
},
7397 { 0, CODE_FOR_spe_evmheumianw
, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW
},
7398 { 0, CODE_FOR_spe_evmheusiaaw
, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW
},
7399 { 0, CODE_FOR_spe_evmheusianw
, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW
},
7400 { 0, CODE_FOR_spe_evmhogsmfaa
, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA
},
7401 { 0, CODE_FOR_spe_evmhogsmfan
, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN
},
7402 { 0, CODE_FOR_spe_evmhogsmiaa
, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA
},
7403 { 0, CODE_FOR_spe_evmhogsmian
, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN
},
7404 { 0, CODE_FOR_spe_evmhogumiaa
, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA
},
7405 { 0, CODE_FOR_spe_evmhogumian
, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN
},
7406 { 0, CODE_FOR_spe_evmhosmf
, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF
},
7407 { 0, CODE_FOR_spe_evmhosmfa
, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA
},
7408 { 0, CODE_FOR_spe_evmhosmfaaw
, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW
},
7409 { 0, CODE_FOR_spe_evmhosmfanw
, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW
},
7410 { 0, CODE_FOR_spe_evmhosmi
, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI
},
7411 { 0, CODE_FOR_spe_evmhosmia
, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA
},
7412 { 0, CODE_FOR_spe_evmhosmiaaw
, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW
},
7413 { 0, CODE_FOR_spe_evmhosmianw
, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW
},
7414 { 0, CODE_FOR_spe_evmhossf
, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF
},
7415 { 0, CODE_FOR_spe_evmhossfa
, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA
},
7416 { 0, CODE_FOR_spe_evmhossfaaw
, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW
},
7417 { 0, CODE_FOR_spe_evmhossfanw
, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW
},
7418 { 0, CODE_FOR_spe_evmhossiaaw
, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW
},
7419 { 0, CODE_FOR_spe_evmhossianw
, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW
},
7420 { 0, CODE_FOR_spe_evmhoumi
, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI
},
7421 { 0, CODE_FOR_spe_evmhoumia
, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA
},
7422 { 0, CODE_FOR_spe_evmhoumiaaw
, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW
},
7423 { 0, CODE_FOR_spe_evmhoumianw
, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW
},
7424 { 0, CODE_FOR_spe_evmhousiaaw
, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW
},
7425 { 0, CODE_FOR_spe_evmhousianw
, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW
},
7426 { 0, CODE_FOR_spe_evmwhsmf
, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF
},
7427 { 0, CODE_FOR_spe_evmwhsmfa
, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA
},
7428 { 0, CODE_FOR_spe_evmwhsmi
, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI
},
7429 { 0, CODE_FOR_spe_evmwhsmia
, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA
},
7430 { 0, CODE_FOR_spe_evmwhssf
, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF
},
7431 { 0, CODE_FOR_spe_evmwhssfa
, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA
},
7432 { 0, CODE_FOR_spe_evmwhumi
, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI
},
7433 { 0, CODE_FOR_spe_evmwhumia
, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA
},
7434 { 0, CODE_FOR_spe_evmwlsmiaaw
, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW
},
7435 { 0, CODE_FOR_spe_evmwlsmianw
, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW
},
7436 { 0, CODE_FOR_spe_evmwlssiaaw
, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW
},
7437 { 0, CODE_FOR_spe_evmwlssianw
, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW
},
7438 { 0, CODE_FOR_spe_evmwlumi
, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI
},
7439 { 0, CODE_FOR_spe_evmwlumia
, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA
},
7440 { 0, CODE_FOR_spe_evmwlumiaaw
, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW
},
7441 { 0, CODE_FOR_spe_evmwlumianw
, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW
},
7442 { 0, CODE_FOR_spe_evmwlusiaaw
, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW
},
7443 { 0, CODE_FOR_spe_evmwlusianw
, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW
},
7444 { 0, CODE_FOR_spe_evmwsmf
, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF
},
7445 { 0, CODE_FOR_spe_evmwsmfa
, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA
},
7446 { 0, CODE_FOR_spe_evmwsmfaa
, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA
},
7447 { 0, CODE_FOR_spe_evmwsmfan
, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN
},
7448 { 0, CODE_FOR_spe_evmwsmi
, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI
},
7449 { 0, CODE_FOR_spe_evmwsmia
, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA
},
7450 { 0, CODE_FOR_spe_evmwsmiaa
, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA
},
7451 { 0, CODE_FOR_spe_evmwsmian
, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN
},
7452 { 0, CODE_FOR_spe_evmwssf
, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF
},
7453 { 0, CODE_FOR_spe_evmwssfa
, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA
},
7454 { 0, CODE_FOR_spe_evmwssfaa
, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA
},
7455 { 0, CODE_FOR_spe_evmwssfan
, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN
},
7456 { 0, CODE_FOR_spe_evmwumi
, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI
},
7457 { 0, CODE_FOR_spe_evmwumia
, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA
},
7458 { 0, CODE_FOR_spe_evmwumiaa
, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA
},
7459 { 0, CODE_FOR_spe_evmwumian
, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN
},
7460 { 0, CODE_FOR_spe_evnand
, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND
},
7461 { 0, CODE_FOR_spe_evnor
, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR
},
7462 { 0, CODE_FOR_spe_evor
, "__builtin_spe_evor", SPE_BUILTIN_EVOR
},
7463 { 0, CODE_FOR_spe_evorc
, "__builtin_spe_evorc", SPE_BUILTIN_EVORC
},
7464 { 0, CODE_FOR_spe_evrlw
, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW
},
7465 { 0, CODE_FOR_spe_evslw
, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW
},
7466 { 0, CODE_FOR_spe_evsrws
, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS
},
7467 { 0, CODE_FOR_spe_evsrwu
, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU
},
7468 { 0, CODE_FOR_spe_evsubfw
, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW
},
7470 /* SPE binary operations expecting a 5-bit unsigned literal. */
7471 { 0, CODE_FOR_spe_evaddiw
, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW
},
7473 { 0, CODE_FOR_spe_evrlwi
, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI
},
7474 { 0, CODE_FOR_spe_evslwi
, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI
},
7475 { 0, CODE_FOR_spe_evsrwis
, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS
},
7476 { 0, CODE_FOR_spe_evsrwiu
, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU
},
7477 { 0, CODE_FOR_spe_evsubifw
, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW
},
7478 { 0, CODE_FOR_spe_evmwhssfaa
, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA
},
7479 { 0, CODE_FOR_spe_evmwhssmaa
, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA
},
7480 { 0, CODE_FOR_spe_evmwhsmfaa
, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA
},
7481 { 0, CODE_FOR_spe_evmwhsmiaa
, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA
},
7482 { 0, CODE_FOR_spe_evmwhusiaa
, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA
},
7483 { 0, CODE_FOR_spe_evmwhumiaa
, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA
},
7484 { 0, CODE_FOR_spe_evmwhssfan
, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN
},
7485 { 0, CODE_FOR_spe_evmwhssian
, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN
},
7486 { 0, CODE_FOR_spe_evmwhsmfan
, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN
},
7487 { 0, CODE_FOR_spe_evmwhsmian
, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN
},
7488 { 0, CODE_FOR_spe_evmwhusian
, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN
},
7489 { 0, CODE_FOR_spe_evmwhumian
, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN
},
7490 { 0, CODE_FOR_spe_evmwhgssfaa
, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA
},
7491 { 0, CODE_FOR_spe_evmwhgsmfaa
, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA
},
7492 { 0, CODE_FOR_spe_evmwhgsmiaa
, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA
},
7493 { 0, CODE_FOR_spe_evmwhgumiaa
, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA
},
7494 { 0, CODE_FOR_spe_evmwhgssfan
, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN
},
7495 { 0, CODE_FOR_spe_evmwhgsmfan
, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN
},
7496 { 0, CODE_FOR_spe_evmwhgsmian
, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN
},
7497 { 0, CODE_FOR_spe_evmwhgumian
, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN
},
7498 { 0, CODE_FOR_spe_brinc
, "__builtin_spe_brinc", SPE_BUILTIN_BRINC
},
7500 /* Place-holder. Leave as last binary SPE builtin. */
7501 { 0, CODE_FOR_xorv2si3
, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR
}
7504 /* AltiVec predicates. */
7506 struct builtin_description_predicates
7508 const unsigned int mask
;
7509 const enum insn_code icode
;
7511 const char *const name
;
7512 const enum rs6000_builtins code
;
7515 static const struct builtin_description_predicates bdesc_altivec_preds
[] =
7517 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P
},
7518 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P
},
7519 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P
},
7520 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P
},
7521 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4si
, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P
},
7522 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4si
, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P
},
7523 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4si
, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P
},
7524 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v8hi
, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P
},
7525 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v8hi
, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P
},
7526 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v8hi
, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P
},
7527 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v16qi
, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P
},
7528 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v16qi
, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P
},
7529 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v16qi
, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P
},
7531 { MASK_ALTIVEC
, 0, NULL
, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P
},
7532 { MASK_ALTIVEC
, 0, NULL
, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P
},
7533 { MASK_ALTIVEC
, 0, NULL
, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P
}
7536 /* SPE predicates. */
7537 static struct builtin_description bdesc_spe_predicates
[] =
7539 /* Place-holder. Leave as first. */
7540 { 0, CODE_FOR_spe_evcmpeq
, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ
},
7541 { 0, CODE_FOR_spe_evcmpgts
, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS
},
7542 { 0, CODE_FOR_spe_evcmpgtu
, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU
},
7543 { 0, CODE_FOR_spe_evcmplts
, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS
},
7544 { 0, CODE_FOR_spe_evcmpltu
, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU
},
7545 { 0, CODE_FOR_spe_evfscmpeq
, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ
},
7546 { 0, CODE_FOR_spe_evfscmpgt
, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT
},
7547 { 0, CODE_FOR_spe_evfscmplt
, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT
},
7548 { 0, CODE_FOR_spe_evfststeq
, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ
},
7549 { 0, CODE_FOR_spe_evfststgt
, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT
},
7550 /* Place-holder. Leave as last. */
7551 { 0, CODE_FOR_spe_evfststlt
, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT
},
7554 /* SPE evsel predicates. */
7555 static struct builtin_description bdesc_spe_evsel
[] =
7557 /* Place-holder. Leave as first. */
7558 { 0, CODE_FOR_spe_evcmpgts
, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS
},
7559 { 0, CODE_FOR_spe_evcmpgtu
, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU
},
7560 { 0, CODE_FOR_spe_evcmplts
, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS
},
7561 { 0, CODE_FOR_spe_evcmpltu
, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU
},
7562 { 0, CODE_FOR_spe_evcmpeq
, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ
},
7563 { 0, CODE_FOR_spe_evfscmpgt
, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT
},
7564 { 0, CODE_FOR_spe_evfscmplt
, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT
},
7565 { 0, CODE_FOR_spe_evfscmpeq
, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ
},
7566 { 0, CODE_FOR_spe_evfststgt
, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT
},
7567 { 0, CODE_FOR_spe_evfststlt
, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT
},
7568 /* Place-holder. Leave as last. */
7569 { 0, CODE_FOR_spe_evfststeq
, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ
},
7572 /* PAIRED predicates. */
7573 static const struct builtin_description bdesc_paired_preds
[] =
7575 /* Place-holder. Leave as first. */
7576 { 0, CODE_FOR_paired_cmpu0
, "__builtin_paired_cmpu0", PAIRED_BUILTIN_CMPU0
},
7577 /* Place-holder. Leave as last. */
7578 { 0, CODE_FOR_paired_cmpu1
, "__builtin_paired_cmpu1", PAIRED_BUILTIN_CMPU1
},
7581 /* ABS* operations. */
7583 static const struct builtin_description bdesc_abs
[] =
7585 { MASK_ALTIVEC
, CODE_FOR_absv4si2
, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI
},
7586 { MASK_ALTIVEC
, CODE_FOR_absv8hi2
, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI
},
7587 { MASK_ALTIVEC
, CODE_FOR_absv4sf2
, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF
},
7588 { MASK_ALTIVEC
, CODE_FOR_absv16qi2
, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI
},
7589 { MASK_ALTIVEC
, CODE_FOR_altivec_abss_v4si
, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI
},
7590 { MASK_ALTIVEC
, CODE_FOR_altivec_abss_v8hi
, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI
},
7591 { MASK_ALTIVEC
, CODE_FOR_altivec_abss_v16qi
, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI
}
7594 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
7597 static struct builtin_description bdesc_1arg
[] =
7599 { MASK_ALTIVEC
, CODE_FOR_altivec_vexptefp
, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP
},
7600 { MASK_ALTIVEC
, CODE_FOR_altivec_vlogefp
, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP
},
7601 { MASK_ALTIVEC
, CODE_FOR_altivec_vrefp
, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP
},
7602 { MASK_ALTIVEC
, CODE_FOR_altivec_vrfim
, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM
},
7603 { MASK_ALTIVEC
, CODE_FOR_altivec_vrfin
, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN
},
7604 { MASK_ALTIVEC
, CODE_FOR_altivec_vrfip
, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP
},
7605 { MASK_ALTIVEC
, CODE_FOR_ftruncv4sf2
, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ
},
7606 { MASK_ALTIVEC
, CODE_FOR_altivec_vrsqrtefp
, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP
},
7607 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltisb
, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB
},
7608 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltish
, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH
},
7609 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltisw
, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW
},
7610 { MASK_ALTIVEC
, CODE_FOR_altivec_vupkhsb
, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB
},
7611 { MASK_ALTIVEC
, CODE_FOR_altivec_vupkhpx
, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX
},
7612 { MASK_ALTIVEC
, CODE_FOR_altivec_vupkhsh
, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH
},
7613 { MASK_ALTIVEC
, CODE_FOR_altivec_vupklsb
, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB
},
7614 { MASK_ALTIVEC
, CODE_FOR_altivec_vupklpx
, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX
},
7615 { MASK_ALTIVEC
, CODE_FOR_altivec_vupklsh
, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH
},
7617 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS
},
7618 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS
},
7619 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL
},
7620 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE
},
7621 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR
},
7622 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE
},
7623 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR
},
7624 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE
},
7625 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND
},
7626 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE
},
7627 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC
},
7628 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH
},
7629 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH
},
7630 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX
},
7631 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB
},
7632 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL
},
7633 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX
},
7634 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH
},
7635 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB
},
7637 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
7638 end with SPE_BUILTIN_EVSUBFUSIAAW. */
7639 { 0, CODE_FOR_spe_evabs
, "__builtin_spe_evabs", SPE_BUILTIN_EVABS
},
7640 { 0, CODE_FOR_spe_evaddsmiaaw
, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW
},
7641 { 0, CODE_FOR_spe_evaddssiaaw
, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW
},
7642 { 0, CODE_FOR_spe_evaddumiaaw
, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW
},
7643 { 0, CODE_FOR_spe_evaddusiaaw
, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW
},
7644 { 0, CODE_FOR_spe_evcntlsw
, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW
},
7645 { 0, CODE_FOR_spe_evcntlzw
, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW
},
7646 { 0, CODE_FOR_spe_evextsb
, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB
},
7647 { 0, CODE_FOR_spe_evextsh
, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH
},
7648 { 0, CODE_FOR_spe_evfsabs
, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS
},
7649 { 0, CODE_FOR_spe_evfscfsf
, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF
},
7650 { 0, CODE_FOR_spe_evfscfsi
, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI
},
7651 { 0, CODE_FOR_spe_evfscfuf
, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF
},
7652 { 0, CODE_FOR_spe_evfscfui
, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI
},
7653 { 0, CODE_FOR_spe_evfsctsf
, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF
},
7654 { 0, CODE_FOR_spe_evfsctsi
, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI
},
7655 { 0, CODE_FOR_spe_evfsctsiz
, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ
},
7656 { 0, CODE_FOR_spe_evfsctuf
, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF
},
7657 { 0, CODE_FOR_spe_evfsctui
, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI
},
7658 { 0, CODE_FOR_spe_evfsctuiz
, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ
},
7659 { 0, CODE_FOR_spe_evfsnabs
, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS
},
7660 { 0, CODE_FOR_spe_evfsneg
, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG
},
7661 { 0, CODE_FOR_spe_evmra
, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA
},
7662 { 0, CODE_FOR_negv2si2
, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG
},
7663 { 0, CODE_FOR_spe_evrndw
, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW
},
7664 { 0, CODE_FOR_spe_evsubfsmiaaw
, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW
},
7665 { 0, CODE_FOR_spe_evsubfssiaaw
, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW
},
7666 { 0, CODE_FOR_spe_evsubfumiaaw
, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW
},
7668 /* Place-holder. Leave as last unary SPE builtin. */
7669 { 0, CODE_FOR_spe_evsubfusiaaw
, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW
},
7671 { 0, CODE_FOR_absv2sf2
, "__builtin_paired_absv2sf2", PAIRED_BUILTIN_ABSV2SF2
},
7672 { 0, CODE_FOR_nabsv2sf2
, "__builtin_paired_nabsv2sf2", PAIRED_BUILTIN_NABSV2SF2
},
7673 { 0, CODE_FOR_negv2sf2
, "__builtin_paired_negv2sf2", PAIRED_BUILTIN_NEGV2SF2
},
7674 { 0, CODE_FOR_sqrtv2sf2
, "__builtin_paired_sqrtv2sf2", PAIRED_BUILTIN_SQRTV2SF2
},
7675 { 0, CODE_FOR_resv2sf2
, "__builtin_paired_resv2sf2", PAIRED_BUILTIN_RESV2SF2
}
7679 rs6000_expand_unop_builtin (enum insn_code icode
, tree exp
, rtx target
)
7682 tree arg0
= CALL_EXPR_ARG (exp
, 0);
7683 rtx op0
= expand_normal (arg0
);
7684 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7685 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
7687 if (icode
== CODE_FOR_nothing
)
7688 /* Builtin not supported on this processor. */
7691 /* If we got invalid arguments bail out before generating bad rtl. */
7692 if (arg0
== error_mark_node
)
7695 if (icode
== CODE_FOR_altivec_vspltisb
7696 || icode
== CODE_FOR_altivec_vspltish
7697 || icode
== CODE_FOR_altivec_vspltisw
7698 || icode
== CODE_FOR_spe_evsplatfi
7699 || icode
== CODE_FOR_spe_evsplati
)
7701 /* Only allow 5-bit *signed* literals. */
7702 if (GET_CODE (op0
) != CONST_INT
7703 || INTVAL (op0
) > 15
7704 || INTVAL (op0
) < -16)
7706 error ("argument 1 must be a 5-bit signed literal");
7712 || GET_MODE (target
) != tmode
7713 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7714 target
= gen_reg_rtx (tmode
);
7716 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7717 op0
= copy_to_mode_reg (mode0
, op0
);
7719 pat
= GEN_FCN (icode
) (target
, op0
);
7728 altivec_expand_abs_builtin (enum insn_code icode
, tree exp
, rtx target
)
7730 rtx pat
, scratch1
, scratch2
;
7731 tree arg0
= CALL_EXPR_ARG (exp
, 0);
7732 rtx op0
= expand_normal (arg0
);
7733 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7734 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
7736 /* If we have invalid arguments, bail out before generating bad rtl. */
7737 if (arg0
== error_mark_node
)
7741 || GET_MODE (target
) != tmode
7742 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7743 target
= gen_reg_rtx (tmode
);
7745 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7746 op0
= copy_to_mode_reg (mode0
, op0
);
7748 scratch1
= gen_reg_rtx (mode0
);
7749 scratch2
= gen_reg_rtx (mode0
);
7751 pat
= GEN_FCN (icode
) (target
, op0
, scratch1
, scratch2
);
7760 rs6000_expand_binop_builtin (enum insn_code icode
, tree exp
, rtx target
)
7763 tree arg0
= CALL_EXPR_ARG (exp
, 0);
7764 tree arg1
= CALL_EXPR_ARG (exp
, 1);
7765 rtx op0
= expand_normal (arg0
);
7766 rtx op1
= expand_normal (arg1
);
7767 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7768 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
7769 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
7771 if (icode
== CODE_FOR_nothing
)
7772 /* Builtin not supported on this processor. */
7775 /* If we got invalid arguments bail out before generating bad rtl. */
7776 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
7779 if (icode
== CODE_FOR_altivec_vcfux
7780 || icode
== CODE_FOR_altivec_vcfsx
7781 || icode
== CODE_FOR_altivec_vctsxs
7782 || icode
== CODE_FOR_altivec_vctuxs
7783 || icode
== CODE_FOR_altivec_vspltb
7784 || icode
== CODE_FOR_altivec_vsplth
7785 || icode
== CODE_FOR_altivec_vspltw
7786 || icode
== CODE_FOR_spe_evaddiw
7787 || icode
== CODE_FOR_spe_evldd
7788 || icode
== CODE_FOR_spe_evldh
7789 || icode
== CODE_FOR_spe_evldw
7790 || icode
== CODE_FOR_spe_evlhhesplat
7791 || icode
== CODE_FOR_spe_evlhhossplat
7792 || icode
== CODE_FOR_spe_evlhhousplat
7793 || icode
== CODE_FOR_spe_evlwhe
7794 || icode
== CODE_FOR_spe_evlwhos
7795 || icode
== CODE_FOR_spe_evlwhou
7796 || icode
== CODE_FOR_spe_evlwhsplat
7797 || icode
== CODE_FOR_spe_evlwwsplat
7798 || icode
== CODE_FOR_spe_evrlwi
7799 || icode
== CODE_FOR_spe_evslwi
7800 || icode
== CODE_FOR_spe_evsrwis
7801 || icode
== CODE_FOR_spe_evsubifw
7802 || icode
== CODE_FOR_spe_evsrwiu
)
7804 /* Only allow 5-bit unsigned literals. */
7806 if (TREE_CODE (arg1
) != INTEGER_CST
7807 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
7809 error ("argument 2 must be a 5-bit unsigned literal");
7815 || GET_MODE (target
) != tmode
7816 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7817 target
= gen_reg_rtx (tmode
);
7819 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7820 op0
= copy_to_mode_reg (mode0
, op0
);
7821 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
7822 op1
= copy_to_mode_reg (mode1
, op1
);
7824 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
7833 altivec_expand_predicate_builtin (enum insn_code icode
, const char *opcode
,
7834 tree exp
, rtx target
)
7837 tree cr6_form
= CALL_EXPR_ARG (exp
, 0);
7838 tree arg0
= CALL_EXPR_ARG (exp
, 1);
7839 tree arg1
= CALL_EXPR_ARG (exp
, 2);
7840 rtx op0
= expand_normal (arg0
);
7841 rtx op1
= expand_normal (arg1
);
7842 enum machine_mode tmode
= SImode
;
7843 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
7844 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
7847 if (TREE_CODE (cr6_form
) != INTEGER_CST
)
7849 error ("argument 1 of __builtin_altivec_predicate must be a constant");
7853 cr6_form_int
= TREE_INT_CST_LOW (cr6_form
);
7855 gcc_assert (mode0
== mode1
);
7857 /* If we have invalid arguments, bail out before generating bad rtl. */
7858 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
7862 || GET_MODE (target
) != tmode
7863 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7864 target
= gen_reg_rtx (tmode
);
7866 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7867 op0
= copy_to_mode_reg (mode0
, op0
);
7868 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
7869 op1
= copy_to_mode_reg (mode1
, op1
);
7871 scratch
= gen_reg_rtx (mode0
);
7873 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
,
7874 gen_rtx_SYMBOL_REF (Pmode
, opcode
));
7879 /* The vec_any* and vec_all* predicates use the same opcodes for two
7880 different operations, but the bits in CR6 will be different
7881 depending on what information we want. So we have to play tricks
7882 with CR6 to get the right bits out.
7884 If you think this is disgusting, look at the specs for the
7885 AltiVec predicates. */
7887 switch (cr6_form_int
)
7890 emit_insn (gen_cr6_test_for_zero (target
));
7893 emit_insn (gen_cr6_test_for_zero_reverse (target
));
7896 emit_insn (gen_cr6_test_for_lt (target
));
7899 emit_insn (gen_cr6_test_for_lt_reverse (target
));
7902 error ("argument 1 of __builtin_altivec_predicate is out of range");
7910 paired_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
)
7913 tree arg0
= CALL_EXPR_ARG (exp
, 0);
7914 tree arg1
= CALL_EXPR_ARG (exp
, 1);
7915 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7916 enum machine_mode mode0
= Pmode
;
7917 enum machine_mode mode1
= Pmode
;
7918 rtx op0
= expand_normal (arg0
);
7919 rtx op1
= expand_normal (arg1
);
7921 if (icode
== CODE_FOR_nothing
)
7922 /* Builtin not supported on this processor. */
7925 /* If we got invalid arguments bail out before generating bad rtl. */
7926 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
7930 || GET_MODE (target
) != tmode
7931 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7932 target
= gen_reg_rtx (tmode
);
7934 op1
= copy_to_mode_reg (mode1
, op1
);
7936 if (op0
== const0_rtx
)
7938 addr
= gen_rtx_MEM (tmode
, op1
);
7942 op0
= copy_to_mode_reg (mode0
, op0
);
7943 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
7946 pat
= GEN_FCN (icode
) (target
, addr
);
7956 altivec_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
)
7959 tree arg0
= CALL_EXPR_ARG (exp
, 0);
7960 tree arg1
= CALL_EXPR_ARG (exp
, 1);
7961 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7962 enum machine_mode mode0
= Pmode
;
7963 enum machine_mode mode1
= Pmode
;
7964 rtx op0
= expand_normal (arg0
);
7965 rtx op1
= expand_normal (arg1
);
7967 if (icode
== CODE_FOR_nothing
)
7968 /* Builtin not supported on this processor. */
7971 /* If we got invalid arguments bail out before generating bad rtl. */
7972 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
7976 || GET_MODE (target
) != tmode
7977 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7978 target
= gen_reg_rtx (tmode
);
7980 op1
= copy_to_mode_reg (mode1
, op1
);
7982 if (op0
== const0_rtx
)
7984 addr
= gen_rtx_MEM (tmode
, op1
);
7988 op0
= copy_to_mode_reg (mode0
, op0
);
7989 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
7992 pat
= GEN_FCN (icode
) (target
, addr
);
8002 spe_expand_stv_builtin (enum insn_code icode
, tree exp
)
8004 tree arg0
= CALL_EXPR_ARG (exp
, 0);
8005 tree arg1
= CALL_EXPR_ARG (exp
, 1);
8006 tree arg2
= CALL_EXPR_ARG (exp
, 2);
8007 rtx op0
= expand_normal (arg0
);
8008 rtx op1
= expand_normal (arg1
);
8009 rtx op2
= expand_normal (arg2
);
8011 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
8012 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
8013 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
8015 /* Invalid arguments. Bail before doing anything stoopid! */
8016 if (arg0
== error_mark_node
8017 || arg1
== error_mark_node
8018 || arg2
== error_mark_node
)
8021 if (! (*insn_data
[icode
].operand
[2].predicate
) (op0
, mode2
))
8022 op0
= copy_to_mode_reg (mode2
, op0
);
8023 if (! (*insn_data
[icode
].operand
[0].predicate
) (op1
, mode0
))
8024 op1
= copy_to_mode_reg (mode0
, op1
);
8025 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
8026 op2
= copy_to_mode_reg (mode1
, op2
);
8028 pat
= GEN_FCN (icode
) (op1
, op2
, op0
);
8035 paired_expand_stv_builtin (enum insn_code icode
, tree exp
)
8037 tree arg0
= CALL_EXPR_ARG (exp
, 0);
8038 tree arg1
= CALL_EXPR_ARG (exp
, 1);
8039 tree arg2
= CALL_EXPR_ARG (exp
, 2);
8040 rtx op0
= expand_normal (arg0
);
8041 rtx op1
= expand_normal (arg1
);
8042 rtx op2
= expand_normal (arg2
);
8044 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
8045 enum machine_mode mode1
= Pmode
;
8046 enum machine_mode mode2
= Pmode
;
8048 /* Invalid arguments. Bail before doing anything stoopid! */
8049 if (arg0
== error_mark_node
8050 || arg1
== error_mark_node
8051 || arg2
== error_mark_node
)
8054 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
8055 op0
= copy_to_mode_reg (tmode
, op0
);
8057 op2
= copy_to_mode_reg (mode2
, op2
);
8059 if (op1
== const0_rtx
)
8061 addr
= gen_rtx_MEM (tmode
, op2
);
8065 op1
= copy_to_mode_reg (mode1
, op1
);
8066 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
8069 pat
= GEN_FCN (icode
) (addr
, op0
);
8076 altivec_expand_stv_builtin (enum insn_code icode
, tree exp
)
8078 tree arg0
= CALL_EXPR_ARG (exp
, 0);
8079 tree arg1
= CALL_EXPR_ARG (exp
, 1);
8080 tree arg2
= CALL_EXPR_ARG (exp
, 2);
8081 rtx op0
= expand_normal (arg0
);
8082 rtx op1
= expand_normal (arg1
);
8083 rtx op2
= expand_normal (arg2
);
8085 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
8086 enum machine_mode mode1
= Pmode
;
8087 enum machine_mode mode2
= Pmode
;
8089 /* Invalid arguments. Bail before doing anything stoopid! */
8090 if (arg0
== error_mark_node
8091 || arg1
== error_mark_node
8092 || arg2
== error_mark_node
)
8095 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
8096 op0
= copy_to_mode_reg (tmode
, op0
);
8098 op2
= copy_to_mode_reg (mode2
, op2
);
8100 if (op1
== const0_rtx
)
8102 addr
= gen_rtx_MEM (tmode
, op2
);
8106 op1
= copy_to_mode_reg (mode1
, op1
);
8107 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
8110 pat
= GEN_FCN (icode
) (addr
, op0
);
8117 rs6000_expand_ternop_builtin (enum insn_code icode
, tree exp
, rtx target
)
8120 tree arg0
= CALL_EXPR_ARG (exp
, 0);
8121 tree arg1
= CALL_EXPR_ARG (exp
, 1);
8122 tree arg2
= CALL_EXPR_ARG (exp
, 2);
8123 rtx op0
= expand_normal (arg0
);
8124 rtx op1
= expand_normal (arg1
);
8125 rtx op2
= expand_normal (arg2
);
8126 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
8127 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
8128 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
8129 enum machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
8131 if (icode
== CODE_FOR_nothing
)
8132 /* Builtin not supported on this processor. */
8135 /* If we got invalid arguments bail out before generating bad rtl. */
8136 if (arg0
== error_mark_node
8137 || arg1
== error_mark_node
8138 || arg2
== error_mark_node
)
8141 if (icode
== CODE_FOR_altivec_vsldoi_v4sf
8142 || icode
== CODE_FOR_altivec_vsldoi_v4si
8143 || icode
== CODE_FOR_altivec_vsldoi_v8hi
8144 || icode
== CODE_FOR_altivec_vsldoi_v16qi
)
8146 /* Only allow 4-bit unsigned literals. */
8148 if (TREE_CODE (arg2
) != INTEGER_CST
8149 || TREE_INT_CST_LOW (arg2
) & ~0xf)
8151 error ("argument 3 must be a 4-bit unsigned literal");
8157 || GET_MODE (target
) != tmode
8158 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8159 target
= gen_reg_rtx (tmode
);
8161 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
8162 op0
= copy_to_mode_reg (mode0
, op0
);
8163 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
8164 op1
= copy_to_mode_reg (mode1
, op1
);
8165 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
8166 op2
= copy_to_mode_reg (mode2
, op2
);
8168 if (TARGET_PAIRED_FLOAT
&& icode
== CODE_FOR_selv2sf4
)
8169 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
, CONST0_RTX (SFmode
));
8171 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
8179 /* Expand the lvx builtins. */
8181 altivec_expand_ld_builtin (tree exp
, rtx target
, bool *expandedp
)
8183 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8184 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8186 enum machine_mode tmode
, mode0
;
8188 enum insn_code icode
;
8192 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi
:
8193 icode
= CODE_FOR_altivec_lvx_v16qi
;
8195 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi
:
8196 icode
= CODE_FOR_altivec_lvx_v8hi
;
8198 case ALTIVEC_BUILTIN_LD_INTERNAL_4si
:
8199 icode
= CODE_FOR_altivec_lvx_v4si
;
8201 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf
:
8202 icode
= CODE_FOR_altivec_lvx_v4sf
;
8211 arg0
= CALL_EXPR_ARG (exp
, 0);
8212 op0
= expand_normal (arg0
);
8213 tmode
= insn_data
[icode
].operand
[0].mode
;
8214 mode0
= insn_data
[icode
].operand
[1].mode
;
8217 || GET_MODE (target
) != tmode
8218 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8219 target
= gen_reg_rtx (tmode
);
8221 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
8222 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
8224 pat
= GEN_FCN (icode
) (target
, op0
);
8231 /* Expand the stvx builtins. */
8233 altivec_expand_st_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
8236 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8237 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8239 enum machine_mode mode0
, mode1
;
8241 enum insn_code icode
;
8245 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi
:
8246 icode
= CODE_FOR_altivec_stvx_v16qi
;
8248 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi
:
8249 icode
= CODE_FOR_altivec_stvx_v8hi
;
8251 case ALTIVEC_BUILTIN_ST_INTERNAL_4si
:
8252 icode
= CODE_FOR_altivec_stvx_v4si
;
8254 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf
:
8255 icode
= CODE_FOR_altivec_stvx_v4sf
;
8262 arg0
= CALL_EXPR_ARG (exp
, 0);
8263 arg1
= CALL_EXPR_ARG (exp
, 1);
8264 op0
= expand_normal (arg0
);
8265 op1
= expand_normal (arg1
);
8266 mode0
= insn_data
[icode
].operand
[0].mode
;
8267 mode1
= insn_data
[icode
].operand
[1].mode
;
8269 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
8270 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
8271 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
8272 op1
= copy_to_mode_reg (mode1
, op1
);
8274 pat
= GEN_FCN (icode
) (op0
, op1
);
8282 /* Expand the dst builtins. */
8284 altivec_expand_dst_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
8287 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8288 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8289 tree arg0
, arg1
, arg2
;
8290 enum machine_mode mode0
, mode1
, mode2
;
8291 rtx pat
, op0
, op1
, op2
;
8292 const struct builtin_description
*d
;
8297 /* Handle DST variants. */
8299 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
8300 if (d
->code
== fcode
)
8302 arg0
= CALL_EXPR_ARG (exp
, 0);
8303 arg1
= CALL_EXPR_ARG (exp
, 1);
8304 arg2
= CALL_EXPR_ARG (exp
, 2);
8305 op0
= expand_normal (arg0
);
8306 op1
= expand_normal (arg1
);
8307 op2
= expand_normal (arg2
);
8308 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
8309 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
8310 mode2
= insn_data
[d
->icode
].operand
[2].mode
;
8312 /* Invalid arguments, bail out before generating bad rtl. */
8313 if (arg0
== error_mark_node
8314 || arg1
== error_mark_node
8315 || arg2
== error_mark_node
)
8320 if (TREE_CODE (arg2
) != INTEGER_CST
8321 || TREE_INT_CST_LOW (arg2
) & ~0x3)
8323 error ("argument to %qs must be a 2-bit unsigned literal", d
->name
);
8327 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
8328 op0
= copy_to_mode_reg (Pmode
, op0
);
8329 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
8330 op1
= copy_to_mode_reg (mode1
, op1
);
8332 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
8342 /* Expand vec_init builtin. */
8344 altivec_expand_vec_init_builtin (tree type
, tree exp
, rtx target
)
8346 enum machine_mode tmode
= TYPE_MODE (type
);
8347 enum machine_mode inner_mode
= GET_MODE_INNER (tmode
);
8348 int i
, n_elt
= GET_MODE_NUNITS (tmode
);
8349 rtvec v
= rtvec_alloc (n_elt
);
8351 gcc_assert (VECTOR_MODE_P (tmode
));
8352 gcc_assert (n_elt
== call_expr_nargs (exp
));
8354 for (i
= 0; i
< n_elt
; ++i
)
8356 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, i
));
8357 RTVEC_ELT (v
, i
) = gen_lowpart (inner_mode
, x
);
8360 if (!target
|| !register_operand (target
, tmode
))
8361 target
= gen_reg_rtx (tmode
);
8363 rs6000_expand_vector_init (target
, gen_rtx_PARALLEL (tmode
, v
));
8367 /* Return the integer constant in ARG. Constrain it to be in the range
8368 of the subparts of VEC_TYPE; issue an error if not. */
8371 get_element_number (tree vec_type
, tree arg
)
8373 unsigned HOST_WIDE_INT elt
, max
= TYPE_VECTOR_SUBPARTS (vec_type
) - 1;
8375 if (!host_integerp (arg
, 1)
8376 || (elt
= tree_low_cst (arg
, 1), elt
> max
))
8378 error ("selector must be an integer constant in the range 0..%wi", max
);
8385 /* Expand vec_set builtin. */
8387 altivec_expand_vec_set_builtin (tree exp
)
8389 enum machine_mode tmode
, mode1
;
8390 tree arg0
, arg1
, arg2
;
8394 arg0
= CALL_EXPR_ARG (exp
, 0);
8395 arg1
= CALL_EXPR_ARG (exp
, 1);
8396 arg2
= CALL_EXPR_ARG (exp
, 2);
8398 tmode
= TYPE_MODE (TREE_TYPE (arg0
));
8399 mode1
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
8400 gcc_assert (VECTOR_MODE_P (tmode
));
8402 op0
= expand_expr (arg0
, NULL_RTX
, tmode
, 0);
8403 op1
= expand_expr (arg1
, NULL_RTX
, mode1
, 0);
8404 elt
= get_element_number (TREE_TYPE (arg0
), arg2
);
8406 if (GET_MODE (op1
) != mode1
&& GET_MODE (op1
) != VOIDmode
)
8407 op1
= convert_modes (mode1
, GET_MODE (op1
), op1
, true);
8409 op0
= force_reg (tmode
, op0
);
8410 op1
= force_reg (mode1
, op1
);
8412 rs6000_expand_vector_set (op0
, op1
, elt
);
8417 /* Expand vec_ext builtin. */
8419 altivec_expand_vec_ext_builtin (tree exp
, rtx target
)
8421 enum machine_mode tmode
, mode0
;
8426 arg0
= CALL_EXPR_ARG (exp
, 0);
8427 arg1
= CALL_EXPR_ARG (exp
, 1);
8429 op0
= expand_normal (arg0
);
8430 elt
= get_element_number (TREE_TYPE (arg0
), arg1
);
8432 tmode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
8433 mode0
= TYPE_MODE (TREE_TYPE (arg0
));
8434 gcc_assert (VECTOR_MODE_P (mode0
));
8436 op0
= force_reg (mode0
, op0
);
8438 if (optimize
|| !target
|| !register_operand (target
, tmode
))
8439 target
= gen_reg_rtx (tmode
);
8441 rs6000_expand_vector_extract (target
, op0
, elt
);
8446 /* Expand the builtin in EXP and store the result in TARGET. Store
8447 true in *EXPANDEDP if we found a builtin to expand. */
8449 altivec_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
8451 const struct builtin_description
*d
;
8452 const struct builtin_description_predicates
*dp
;
8454 enum insn_code icode
;
8455 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8458 enum machine_mode tmode
, mode0
;
8459 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8461 if (fcode
>= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8462 && fcode
<= ALTIVEC_BUILTIN_OVERLOADED_LAST
)
8465 error ("unresolved overload for Altivec builtin %qF", fndecl
);
8469 target
= altivec_expand_ld_builtin (exp
, target
, expandedp
);
8473 target
= altivec_expand_st_builtin (exp
, target
, expandedp
);
8477 target
= altivec_expand_dst_builtin (exp
, target
, expandedp
);
8485 case ALTIVEC_BUILTIN_STVX
:
8486 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx
, exp
);
8487 case ALTIVEC_BUILTIN_STVEBX
:
8488 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx
, exp
);
8489 case ALTIVEC_BUILTIN_STVEHX
:
8490 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx
, exp
);
8491 case ALTIVEC_BUILTIN_STVEWX
:
8492 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx
, exp
);
8493 case ALTIVEC_BUILTIN_STVXL
:
8494 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl
, exp
);
8496 case ALTIVEC_BUILTIN_MFVSCR
:
8497 icode
= CODE_FOR_altivec_mfvscr
;
8498 tmode
= insn_data
[icode
].operand
[0].mode
;
8501 || GET_MODE (target
) != tmode
8502 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8503 target
= gen_reg_rtx (tmode
);
8505 pat
= GEN_FCN (icode
) (target
);
8511 case ALTIVEC_BUILTIN_MTVSCR
:
8512 icode
= CODE_FOR_altivec_mtvscr
;
8513 arg0
= CALL_EXPR_ARG (exp
, 0);
8514 op0
= expand_normal (arg0
);
8515 mode0
= insn_data
[icode
].operand
[0].mode
;
8517 /* If we got invalid arguments bail out before generating bad rtl. */
8518 if (arg0
== error_mark_node
)
8521 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
8522 op0
= copy_to_mode_reg (mode0
, op0
);
8524 pat
= GEN_FCN (icode
) (op0
);
8529 case ALTIVEC_BUILTIN_DSSALL
:
8530 emit_insn (gen_altivec_dssall ());
8533 case ALTIVEC_BUILTIN_DSS
:
8534 icode
= CODE_FOR_altivec_dss
;
8535 arg0
= CALL_EXPR_ARG (exp
, 0);
8537 op0
= expand_normal (arg0
);
8538 mode0
= insn_data
[icode
].operand
[0].mode
;
8540 /* If we got invalid arguments bail out before generating bad rtl. */
8541 if (arg0
== error_mark_node
)
8544 if (TREE_CODE (arg0
) != INTEGER_CST
8545 || TREE_INT_CST_LOW (arg0
) & ~0x3)
8547 error ("argument to dss must be a 2-bit unsigned literal");
8551 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
8552 op0
= copy_to_mode_reg (mode0
, op0
);
8554 emit_insn (gen_altivec_dss (op0
));
8557 case ALTIVEC_BUILTIN_VEC_INIT_V4SI
:
8558 case ALTIVEC_BUILTIN_VEC_INIT_V8HI
:
8559 case ALTIVEC_BUILTIN_VEC_INIT_V16QI
:
8560 case ALTIVEC_BUILTIN_VEC_INIT_V4SF
:
8561 return altivec_expand_vec_init_builtin (TREE_TYPE (exp
), exp
, target
);
8563 case ALTIVEC_BUILTIN_VEC_SET_V4SI
:
8564 case ALTIVEC_BUILTIN_VEC_SET_V8HI
:
8565 case ALTIVEC_BUILTIN_VEC_SET_V16QI
:
8566 case ALTIVEC_BUILTIN_VEC_SET_V4SF
:
8567 return altivec_expand_vec_set_builtin (exp
);
8569 case ALTIVEC_BUILTIN_VEC_EXT_V4SI
:
8570 case ALTIVEC_BUILTIN_VEC_EXT_V8HI
:
8571 case ALTIVEC_BUILTIN_VEC_EXT_V16QI
:
8572 case ALTIVEC_BUILTIN_VEC_EXT_V4SF
:
8573 return altivec_expand_vec_ext_builtin (exp
, target
);
8580 /* Expand abs* operations. */
8582 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
8583 if (d
->code
== fcode
)
8584 return altivec_expand_abs_builtin (d
->icode
, exp
, target
);
8586 /* Expand the AltiVec predicates. */
8587 dp
= bdesc_altivec_preds
;
8588 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, dp
++)
8589 if (dp
->code
== fcode
)
8590 return altivec_expand_predicate_builtin (dp
->icode
, dp
->opcode
,
8593 /* LV* are funky. We initialized them differently. */
8596 case ALTIVEC_BUILTIN_LVSL
:
8597 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl
,
8599 case ALTIVEC_BUILTIN_LVSR
:
8600 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr
,
8602 case ALTIVEC_BUILTIN_LVEBX
:
8603 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx
,
8605 case ALTIVEC_BUILTIN_LVEHX
:
8606 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx
,
8608 case ALTIVEC_BUILTIN_LVEWX
:
8609 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx
,
8611 case ALTIVEC_BUILTIN_LVXL
:
8612 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl
,
8614 case ALTIVEC_BUILTIN_LVX
:
8615 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx
,
8626 /* Expand the builtin in EXP and store the result in TARGET. Store
8627 true in *EXPANDEDP if we found a builtin to expand. */
8629 paired_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
8631 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8632 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8633 const struct builtin_description
*d
;
8640 case PAIRED_BUILTIN_STX
:
8641 return paired_expand_stv_builtin (CODE_FOR_paired_stx
, exp
);
8642 case PAIRED_BUILTIN_LX
:
8643 return paired_expand_lv_builtin (CODE_FOR_paired_lx
, exp
, target
);
8649 /* Expand the paired predicates. */
8650 d
= bdesc_paired_preds
;
8651 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); i
++, d
++)
8652 if (d
->code
== fcode
)
8653 return paired_expand_predicate_builtin (d
->icode
, exp
, target
);
8659 /* Binops that need to be initialized manually, but can be expanded
8660 automagically by rs6000_expand_binop_builtin. */
8661 static struct builtin_description bdesc_2arg_spe
[] =
8663 { 0, CODE_FOR_spe_evlddx
, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX
},
8664 { 0, CODE_FOR_spe_evldwx
, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX
},
8665 { 0, CODE_FOR_spe_evldhx
, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX
},
8666 { 0, CODE_FOR_spe_evlwhex
, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX
},
8667 { 0, CODE_FOR_spe_evlwhoux
, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX
},
8668 { 0, CODE_FOR_spe_evlwhosx
, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX
},
8669 { 0, CODE_FOR_spe_evlwwsplatx
, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX
},
8670 { 0, CODE_FOR_spe_evlwhsplatx
, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX
},
8671 { 0, CODE_FOR_spe_evlhhesplatx
, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX
},
8672 { 0, CODE_FOR_spe_evlhhousplatx
, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX
},
8673 { 0, CODE_FOR_spe_evlhhossplatx
, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX
},
8674 { 0, CODE_FOR_spe_evldd
, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD
},
8675 { 0, CODE_FOR_spe_evldw
, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW
},
8676 { 0, CODE_FOR_spe_evldh
, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH
},
8677 { 0, CODE_FOR_spe_evlwhe
, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE
},
8678 { 0, CODE_FOR_spe_evlwhou
, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU
},
8679 { 0, CODE_FOR_spe_evlwhos
, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS
},
8680 { 0, CODE_FOR_spe_evlwwsplat
, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT
},
8681 { 0, CODE_FOR_spe_evlwhsplat
, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT
},
8682 { 0, CODE_FOR_spe_evlhhesplat
, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT
},
8683 { 0, CODE_FOR_spe_evlhhousplat
, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT
},
8684 { 0, CODE_FOR_spe_evlhhossplat
, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT
}
8687 /* Expand the builtin in EXP and store the result in TARGET. Store
8688 true in *EXPANDEDP if we found a builtin to expand.
8690 This expands the SPE builtins that are not simple unary and binary
8693 spe_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
8695 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8697 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8698 enum insn_code icode
;
8699 enum machine_mode tmode
, mode0
;
8701 struct builtin_description
*d
;
8706 /* Syntax check for a 5-bit unsigned immediate. */
8709 case SPE_BUILTIN_EVSTDD
:
8710 case SPE_BUILTIN_EVSTDH
:
8711 case SPE_BUILTIN_EVSTDW
:
8712 case SPE_BUILTIN_EVSTWHE
:
8713 case SPE_BUILTIN_EVSTWHO
:
8714 case SPE_BUILTIN_EVSTWWE
:
8715 case SPE_BUILTIN_EVSTWWO
:
8716 arg1
= CALL_EXPR_ARG (exp
, 2);
8717 if (TREE_CODE (arg1
) != INTEGER_CST
8718 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
8720 error ("argument 2 must be a 5-bit unsigned literal");
8728 /* The evsplat*i instructions are not quite generic. */
8731 case SPE_BUILTIN_EVSPLATFI
:
8732 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi
,
8734 case SPE_BUILTIN_EVSPLATI
:
8735 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati
,
8741 d
= (struct builtin_description
*) bdesc_2arg_spe
;
8742 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg_spe
); ++i
, ++d
)
8743 if (d
->code
== fcode
)
8744 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
8746 d
= (struct builtin_description
*) bdesc_spe_predicates
;
8747 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, ++d
)
8748 if (d
->code
== fcode
)
8749 return spe_expand_predicate_builtin (d
->icode
, exp
, target
);
8751 d
= (struct builtin_description
*) bdesc_spe_evsel
;
8752 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, ++d
)
8753 if (d
->code
== fcode
)
8754 return spe_expand_evsel_builtin (d
->icode
, exp
, target
);
8758 case SPE_BUILTIN_EVSTDDX
:
8759 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx
, exp
);
8760 case SPE_BUILTIN_EVSTDHX
:
8761 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx
, exp
);
8762 case SPE_BUILTIN_EVSTDWX
:
8763 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx
, exp
);
8764 case SPE_BUILTIN_EVSTWHEX
:
8765 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex
, exp
);
8766 case SPE_BUILTIN_EVSTWHOX
:
8767 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox
, exp
);
8768 case SPE_BUILTIN_EVSTWWEX
:
8769 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex
, exp
);
8770 case SPE_BUILTIN_EVSTWWOX
:
8771 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox
, exp
);
8772 case SPE_BUILTIN_EVSTDD
:
8773 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd
, exp
);
8774 case SPE_BUILTIN_EVSTDH
:
8775 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh
, exp
);
8776 case SPE_BUILTIN_EVSTDW
:
8777 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw
, exp
);
8778 case SPE_BUILTIN_EVSTWHE
:
8779 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe
, exp
);
8780 case SPE_BUILTIN_EVSTWHO
:
8781 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho
, exp
);
8782 case SPE_BUILTIN_EVSTWWE
:
8783 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe
, exp
);
8784 case SPE_BUILTIN_EVSTWWO
:
8785 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo
, exp
);
8786 case SPE_BUILTIN_MFSPEFSCR
:
8787 icode
= CODE_FOR_spe_mfspefscr
;
8788 tmode
= insn_data
[icode
].operand
[0].mode
;
8791 || GET_MODE (target
) != tmode
8792 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8793 target
= gen_reg_rtx (tmode
);
8795 pat
= GEN_FCN (icode
) (target
);
8800 case SPE_BUILTIN_MTSPEFSCR
:
8801 icode
= CODE_FOR_spe_mtspefscr
;
8802 arg0
= CALL_EXPR_ARG (exp
, 0);
8803 op0
= expand_normal (arg0
);
8804 mode0
= insn_data
[icode
].operand
[0].mode
;
8806 if (arg0
== error_mark_node
)
8809 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
8810 op0
= copy_to_mode_reg (mode0
, op0
);
8812 pat
= GEN_FCN (icode
) (op0
);
8825 paired_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
8827 rtx pat
, scratch
, tmp
;
8828 tree form
= CALL_EXPR_ARG (exp
, 0);
8829 tree arg0
= CALL_EXPR_ARG (exp
, 1);
8830 tree arg1
= CALL_EXPR_ARG (exp
, 2);
8831 rtx op0
= expand_normal (arg0
);
8832 rtx op1
= expand_normal (arg1
);
8833 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
8834 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
8838 if (TREE_CODE (form
) != INTEGER_CST
)
8840 error ("argument 1 of __builtin_paired_predicate must be a constant");
8844 form_int
= TREE_INT_CST_LOW (form
);
8846 gcc_assert (mode0
== mode1
);
8848 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
8852 || GET_MODE (target
) != SImode
8853 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
8854 target
= gen_reg_rtx (SImode
);
8855 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
8856 op0
= copy_to_mode_reg (mode0
, op0
);
8857 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
8858 op1
= copy_to_mode_reg (mode1
, op1
);
8860 scratch
= gen_reg_rtx (CCFPmode
);
8862 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
8884 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
8887 error ("argument 1 of __builtin_paired_predicate is out of range");
8891 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
8892 emit_move_insn (target
, tmp
);
8897 spe_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
8899 rtx pat
, scratch
, tmp
;
8900 tree form
= CALL_EXPR_ARG (exp
, 0);
8901 tree arg0
= CALL_EXPR_ARG (exp
, 1);
8902 tree arg1
= CALL_EXPR_ARG (exp
, 2);
8903 rtx op0
= expand_normal (arg0
);
8904 rtx op1
= expand_normal (arg1
);
8905 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
8906 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
8910 if (TREE_CODE (form
) != INTEGER_CST
)
8912 error ("argument 1 of __builtin_spe_predicate must be a constant");
8916 form_int
= TREE_INT_CST_LOW (form
);
8918 gcc_assert (mode0
== mode1
);
8920 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
8924 || GET_MODE (target
) != SImode
8925 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
8926 target
= gen_reg_rtx (SImode
);
8928 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
8929 op0
= copy_to_mode_reg (mode0
, op0
);
8930 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
8931 op1
= copy_to_mode_reg (mode1
, op1
);
8933 scratch
= gen_reg_rtx (CCmode
);
8935 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
8940 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
8941 _lower_. We use one compare, but look in different bits of the
8942 CR for each variant.
8944 There are 2 elements in each SPE simd type (upper/lower). The CR
8945 bits are set as follows:
8947 BIT0 | BIT 1 | BIT 2 | BIT 3
8948 U | L | (U | L) | (U & L)
8950 So, for an "all" relationship, BIT 3 would be set.
8951 For an "any" relationship, BIT 2 would be set. Etc.
8953 Following traditional nomenclature, these bits map to:
8955 BIT0 | BIT 1 | BIT 2 | BIT 3
8958 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
8963 /* All variant. OV bit. */
8965 /* We need to get to the OV bit, which is the ORDERED bit. We
8966 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
8967 that's ugly and will make validate_condition_mode die.
8968 So let's just use another pattern. */
8969 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
8971 /* Any variant. EQ bit. */
8975 /* Upper variant. LT bit. */
8979 /* Lower variant. GT bit. */
8984 error ("argument 1 of __builtin_spe_predicate is out of range");
8988 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
8989 emit_move_insn (target
, tmp
);
8994 /* The evsel builtins look like this:
8996 e = __builtin_spe_evsel_OP (a, b, c, d);
9000 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
9001 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
9005 spe_expand_evsel_builtin (enum insn_code icode
, tree exp
, rtx target
)
9008 tree arg0
= CALL_EXPR_ARG (exp
, 0);
9009 tree arg1
= CALL_EXPR_ARG (exp
, 1);
9010 tree arg2
= CALL_EXPR_ARG (exp
, 2);
9011 tree arg3
= CALL_EXPR_ARG (exp
, 3);
9012 rtx op0
= expand_normal (arg0
);
9013 rtx op1
= expand_normal (arg1
);
9014 rtx op2
= expand_normal (arg2
);
9015 rtx op3
= expand_normal (arg3
);
9016 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
9017 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
9019 gcc_assert (mode0
== mode1
);
9021 if (arg0
== error_mark_node
|| arg1
== error_mark_node
9022 || arg2
== error_mark_node
|| arg3
== error_mark_node
)
9026 || GET_MODE (target
) != mode0
9027 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode0
))
9028 target
= gen_reg_rtx (mode0
);
9030 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
9031 op0
= copy_to_mode_reg (mode0
, op0
);
9032 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
9033 op1
= copy_to_mode_reg (mode0
, op1
);
9034 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
9035 op2
= copy_to_mode_reg (mode0
, op2
);
9036 if (! (*insn_data
[icode
].operand
[1].predicate
) (op3
, mode1
))
9037 op3
= copy_to_mode_reg (mode0
, op3
);
9039 /* Generate the compare. */
9040 scratch
= gen_reg_rtx (CCmode
);
9041 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
9046 if (mode0
== V2SImode
)
9047 emit_insn (gen_spe_evsel (target
, op2
, op3
, scratch
));
9049 emit_insn (gen_spe_evsel_fs (target
, op2
, op3
, scratch
));
9054 /* Expand an expression EXP that calls a built-in function,
9055 with result going to TARGET if that's convenient
9056 (and in mode MODE if that's convenient).
9057 SUBTARGET may be used as the target for computing one of EXP's operands.
9058 IGNORE is nonzero if the value is to be ignored. */
9061 rs6000_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
9062 enum machine_mode mode ATTRIBUTE_UNUSED
,
9063 int ignore ATTRIBUTE_UNUSED
)
9065 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
9066 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
9067 const struct builtin_description
*d
;
9072 if (fcode
== RS6000_BUILTIN_RECIP
)
9073 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3
, exp
, target
);
9075 if (fcode
== RS6000_BUILTIN_RECIPF
)
9076 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3
, exp
, target
);
9078 if (fcode
== RS6000_BUILTIN_RSQRTF
)
9079 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2
, exp
, target
);
9081 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_LOAD
9082 || fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
9084 int icode
= (int) CODE_FOR_altivec_lvsr
;
9085 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
9086 enum machine_mode mode
= insn_data
[icode
].operand
[1].mode
;
9090 gcc_assert (TARGET_ALTIVEC
);
9092 arg
= CALL_EXPR_ARG (exp
, 0);
9093 gcc_assert (TREE_CODE (TREE_TYPE (arg
)) == POINTER_TYPE
);
9094 op
= expand_expr (arg
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
9095 addr
= memory_address (mode
, op
);
9096 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
9100 /* For the load case need to negate the address. */
9101 op
= gen_reg_rtx (GET_MODE (addr
));
9102 emit_insn (gen_rtx_SET (VOIDmode
, op
,
9103 gen_rtx_NEG (GET_MODE (addr
), addr
)));
9105 op
= gen_rtx_MEM (mode
, op
);
9108 || GET_MODE (target
) != tmode
9109 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
9110 target
= gen_reg_rtx (tmode
);
9112 /*pat = gen_altivec_lvsr (target, op);*/
9113 pat
= GEN_FCN (icode
) (target
, op
);
9121 /* FIXME: There's got to be a nicer way to handle this case than
9122 constructing a new CALL_EXPR. */
9123 if (fcode
== ALTIVEC_BUILTIN_VCFUX
9124 || fcode
== ALTIVEC_BUILTIN_VCFSX
9125 || fcode
== ALTIVEC_BUILTIN_VCTUXS
9126 || fcode
== ALTIVEC_BUILTIN_VCTSXS
)
9128 if (call_expr_nargs (exp
) == 1)
9129 exp
= build_call_nary (TREE_TYPE (exp
), CALL_EXPR_FN (exp
),
9130 2, CALL_EXPR_ARG (exp
, 0), integer_zero_node
);
9135 ret
= altivec_expand_builtin (exp
, target
, &success
);
9142 ret
= spe_expand_builtin (exp
, target
, &success
);
9147 if (TARGET_PAIRED_FLOAT
)
9149 ret
= paired_expand_builtin (exp
, target
, &success
);
9155 gcc_assert (TARGET_ALTIVEC
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
);
9157 /* Handle simple unary operations. */
9158 d
= (struct builtin_description
*) bdesc_1arg
;
9159 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
9160 if (d
->code
== fcode
)
9161 return rs6000_expand_unop_builtin (d
->icode
, exp
, target
);
9163 /* Handle simple binary operations. */
9164 d
= (struct builtin_description
*) bdesc_2arg
;
9165 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
9166 if (d
->code
== fcode
)
9167 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
9169 /* Handle simple ternary operations. */
9171 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
9172 if (d
->code
== fcode
)
9173 return rs6000_expand_ternop_builtin (d
->icode
, exp
, target
);
9179 build_opaque_vector_type (tree node
, int nunits
)
9181 node
= copy_node (node
);
9182 TYPE_MAIN_VARIANT (node
) = node
;
9183 TYPE_CANONICAL (node
) = node
;
9184 return build_vector_type (node
, nunits
);
9188 rs6000_init_builtins (void)
9190 V2SI_type_node
= build_vector_type (intSI_type_node
, 2);
9191 V2SF_type_node
= build_vector_type (float_type_node
, 2);
9192 V4HI_type_node
= build_vector_type (intHI_type_node
, 4);
9193 V4SI_type_node
= build_vector_type (intSI_type_node
, 4);
9194 V4SF_type_node
= build_vector_type (float_type_node
, 4);
9195 V8HI_type_node
= build_vector_type (intHI_type_node
, 8);
9196 V16QI_type_node
= build_vector_type (intQI_type_node
, 16);
9198 unsigned_V16QI_type_node
= build_vector_type (unsigned_intQI_type_node
, 16);
9199 unsigned_V8HI_type_node
= build_vector_type (unsigned_intHI_type_node
, 8);
9200 unsigned_V4SI_type_node
= build_vector_type (unsigned_intSI_type_node
, 4);
9202 opaque_V2SF_type_node
= build_opaque_vector_type (float_type_node
, 2);
9203 opaque_V2SI_type_node
= build_opaque_vector_type (intSI_type_node
, 2);
9204 opaque_p_V2SI_type_node
= build_pointer_type (opaque_V2SI_type_node
);
9205 opaque_V4SI_type_node
= copy_node (V4SI_type_node
);
9207 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
9208 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
9209 'vector unsigned short'. */
9211 bool_char_type_node
= build_distinct_type_copy (unsigned_intQI_type_node
);
9212 bool_short_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
9213 bool_int_type_node
= build_distinct_type_copy (unsigned_intSI_type_node
);
9214 pixel_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
9216 long_integer_type_internal_node
= long_integer_type_node
;
9217 long_unsigned_type_internal_node
= long_unsigned_type_node
;
9218 intQI_type_internal_node
= intQI_type_node
;
9219 uintQI_type_internal_node
= unsigned_intQI_type_node
;
9220 intHI_type_internal_node
= intHI_type_node
;
9221 uintHI_type_internal_node
= unsigned_intHI_type_node
;
9222 intSI_type_internal_node
= intSI_type_node
;
9223 uintSI_type_internal_node
= unsigned_intSI_type_node
;
9224 float_type_internal_node
= float_type_node
;
9225 void_type_internal_node
= void_type_node
;
9227 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9228 get_identifier ("__bool char"),
9229 bool_char_type_node
));
9230 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9231 get_identifier ("__bool short"),
9232 bool_short_type_node
));
9233 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9234 get_identifier ("__bool int"),
9235 bool_int_type_node
));
9236 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9237 get_identifier ("__pixel"),
9240 bool_V16QI_type_node
= build_vector_type (bool_char_type_node
, 16);
9241 bool_V8HI_type_node
= build_vector_type (bool_short_type_node
, 8);
9242 bool_V4SI_type_node
= build_vector_type (bool_int_type_node
, 4);
9243 pixel_V8HI_type_node
= build_vector_type (pixel_type_node
, 8);
9245 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9246 get_identifier ("__vector unsigned char"),
9247 unsigned_V16QI_type_node
));
9248 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9249 get_identifier ("__vector signed char"),
9251 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9252 get_identifier ("__vector __bool char"),
9253 bool_V16QI_type_node
));
9255 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9256 get_identifier ("__vector unsigned short"),
9257 unsigned_V8HI_type_node
));
9258 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9259 get_identifier ("__vector signed short"),
9261 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9262 get_identifier ("__vector __bool short"),
9263 bool_V8HI_type_node
));
9265 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9266 get_identifier ("__vector unsigned int"),
9267 unsigned_V4SI_type_node
));
9268 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9269 get_identifier ("__vector signed int"),
9271 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9272 get_identifier ("__vector __bool int"),
9273 bool_V4SI_type_node
));
9275 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9276 get_identifier ("__vector float"),
9278 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9279 get_identifier ("__vector __pixel"),
9280 pixel_V8HI_type_node
));
9282 if (TARGET_PAIRED_FLOAT
)
9283 paired_init_builtins ();
9285 spe_init_builtins ();
9287 altivec_init_builtins ();
9288 if (TARGET_ALTIVEC
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
)
9289 rs6000_common_init_builtins ();
9290 if (TARGET_PPC_GFXOPT
)
9292 tree ftype
= build_function_type_list (float_type_node
,
9296 def_builtin (MASK_PPC_GFXOPT
, "__builtin_recipdivf", ftype
,
9297 RS6000_BUILTIN_RECIPF
);
9299 ftype
= build_function_type_list (float_type_node
,
9302 def_builtin (MASK_PPC_GFXOPT
, "__builtin_rsqrtf", ftype
,
9303 RS6000_BUILTIN_RSQRTF
);
9307 tree ftype
= build_function_type_list (double_type_node
,
9311 def_builtin (MASK_POPCNTB
, "__builtin_recipdiv", ftype
,
9312 RS6000_BUILTIN_RECIP
);
9317 /* AIX libm provides clog as __clog. */
9318 if (built_in_decls
[BUILT_IN_CLOG
])
9319 set_user_assembler_name (built_in_decls
[BUILT_IN_CLOG
], "__clog");
9322 #ifdef SUBTARGET_INIT_BUILTINS
9323 SUBTARGET_INIT_BUILTINS
;
9327 /* Search through a set of builtins and enable the mask bits.
9328 DESC is an array of builtins.
9329 SIZE is the total number of builtins.
9330 START is the builtin enum at which to start.
9331 END is the builtin enum at which to end. */
9333 enable_mask_for_builtins (struct builtin_description
*desc
, int size
,
9334 enum rs6000_builtins start
,
9335 enum rs6000_builtins end
)
9339 for (i
= 0; i
< size
; ++i
)
9340 if (desc
[i
].code
== start
)
9346 for (; i
< size
; ++i
)
9348 /* Flip all the bits on. */
9349 desc
[i
].mask
= target_flags
;
9350 if (desc
[i
].code
== end
)
9356 spe_init_builtins (void)
9358 tree endlink
= void_list_node
;
9359 tree puint_type_node
= build_pointer_type (unsigned_type_node
);
9360 tree pushort_type_node
= build_pointer_type (short_unsigned_type_node
);
9361 struct builtin_description
*d
;
9364 tree v2si_ftype_4_v2si
9365 = build_function_type
9366 (opaque_V2SI_type_node
,
9367 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9368 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9369 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9370 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9373 tree v2sf_ftype_4_v2sf
9374 = build_function_type
9375 (opaque_V2SF_type_node
,
9376 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
9377 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
9378 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
9379 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
9382 tree int_ftype_int_v2si_v2si
9383 = build_function_type
9385 tree_cons (NULL_TREE
, integer_type_node
,
9386 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9387 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9390 tree int_ftype_int_v2sf_v2sf
9391 = build_function_type
9393 tree_cons (NULL_TREE
, integer_type_node
,
9394 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
9395 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
9398 tree void_ftype_v2si_puint_int
9399 = build_function_type (void_type_node
,
9400 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9401 tree_cons (NULL_TREE
, puint_type_node
,
9402 tree_cons (NULL_TREE
,
9406 tree void_ftype_v2si_puint_char
9407 = build_function_type (void_type_node
,
9408 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9409 tree_cons (NULL_TREE
, puint_type_node
,
9410 tree_cons (NULL_TREE
,
9414 tree void_ftype_v2si_pv2si_int
9415 = build_function_type (void_type_node
,
9416 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9417 tree_cons (NULL_TREE
, opaque_p_V2SI_type_node
,
9418 tree_cons (NULL_TREE
,
9422 tree void_ftype_v2si_pv2si_char
9423 = build_function_type (void_type_node
,
9424 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9425 tree_cons (NULL_TREE
, opaque_p_V2SI_type_node
,
9426 tree_cons (NULL_TREE
,
9431 = build_function_type (void_type_node
,
9432 tree_cons (NULL_TREE
, integer_type_node
, endlink
));
9435 = build_function_type (integer_type_node
, endlink
);
9437 tree v2si_ftype_pv2si_int
9438 = build_function_type (opaque_V2SI_type_node
,
9439 tree_cons (NULL_TREE
, opaque_p_V2SI_type_node
,
9440 tree_cons (NULL_TREE
, integer_type_node
,
9443 tree v2si_ftype_puint_int
9444 = build_function_type (opaque_V2SI_type_node
,
9445 tree_cons (NULL_TREE
, puint_type_node
,
9446 tree_cons (NULL_TREE
, integer_type_node
,
9449 tree v2si_ftype_pushort_int
9450 = build_function_type (opaque_V2SI_type_node
,
9451 tree_cons (NULL_TREE
, pushort_type_node
,
9452 tree_cons (NULL_TREE
, integer_type_node
,
9455 tree v2si_ftype_signed_char
9456 = build_function_type (opaque_V2SI_type_node
,
9457 tree_cons (NULL_TREE
, signed_char_type_node
,
9460 /* The initialization of the simple binary and unary builtins is
9461 done in rs6000_common_init_builtins, but we have to enable the
9462 mask bits here manually because we have run out of `target_flags'
9463 bits. We really need to redesign this mask business. */
9465 enable_mask_for_builtins ((struct builtin_description
*) bdesc_2arg
,
9466 ARRAY_SIZE (bdesc_2arg
),
9469 enable_mask_for_builtins ((struct builtin_description
*) bdesc_1arg
,
9470 ARRAY_SIZE (bdesc_1arg
),
9472 SPE_BUILTIN_EVSUBFUSIAAW
);
9473 enable_mask_for_builtins ((struct builtin_description
*) bdesc_spe_predicates
,
9474 ARRAY_SIZE (bdesc_spe_predicates
),
9475 SPE_BUILTIN_EVCMPEQ
,
9476 SPE_BUILTIN_EVFSTSTLT
);
9477 enable_mask_for_builtins ((struct builtin_description
*) bdesc_spe_evsel
,
9478 ARRAY_SIZE (bdesc_spe_evsel
),
9479 SPE_BUILTIN_EVSEL_CMPGTS
,
9480 SPE_BUILTIN_EVSEL_FSTSTEQ
);
9482 (*lang_hooks
.decls
.pushdecl
)
9483 (build_decl (TYPE_DECL
, get_identifier ("__ev64_opaque__"),
9484 opaque_V2SI_type_node
));
9486 /* Initialize irregular SPE builtins. */
9488 def_builtin (target_flags
, "__builtin_spe_mtspefscr", void_ftype_int
, SPE_BUILTIN_MTSPEFSCR
);
9489 def_builtin (target_flags
, "__builtin_spe_mfspefscr", int_ftype_void
, SPE_BUILTIN_MFSPEFSCR
);
9490 def_builtin (target_flags
, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDDX
);
9491 def_builtin (target_flags
, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDHX
);
9492 def_builtin (target_flags
, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDWX
);
9493 def_builtin (target_flags
, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHEX
);
9494 def_builtin (target_flags
, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHOX
);
9495 def_builtin (target_flags
, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWEX
);
9496 def_builtin (target_flags
, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWOX
);
9497 def_builtin (target_flags
, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDD
);
9498 def_builtin (target_flags
, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDH
);
9499 def_builtin (target_flags
, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDW
);
9500 def_builtin (target_flags
, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHE
);
9501 def_builtin (target_flags
, "__builtin_spe_evstwho", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHO
);
9502 def_builtin (target_flags
, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWE
);
9503 def_builtin (target_flags
, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWO
);
9504 def_builtin (target_flags
, "__builtin_spe_evsplatfi", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATFI
);
9505 def_builtin (target_flags
, "__builtin_spe_evsplati", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATI
);
9508 def_builtin (target_flags
, "__builtin_spe_evlddx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDDX
);
9509 def_builtin (target_flags
, "__builtin_spe_evldwx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDWX
);
9510 def_builtin (target_flags
, "__builtin_spe_evldhx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDHX
);
9511 def_builtin (target_flags
, "__builtin_spe_evlwhex", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHEX
);
9512 def_builtin (target_flags
, "__builtin_spe_evlwhoux", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOUX
);
9513 def_builtin (target_flags
, "__builtin_spe_evlwhosx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOSX
);
9514 def_builtin (target_flags
, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLATX
);
9515 def_builtin (target_flags
, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLATX
);
9516 def_builtin (target_flags
, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLATX
);
9517 def_builtin (target_flags
, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLATX
);
9518 def_builtin (target_flags
, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLATX
);
9519 def_builtin (target_flags
, "__builtin_spe_evldd", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDD
);
9520 def_builtin (target_flags
, "__builtin_spe_evldw", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDW
);
9521 def_builtin (target_flags
, "__builtin_spe_evldh", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDH
);
9522 def_builtin (target_flags
, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLAT
);
9523 def_builtin (target_flags
, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLAT
);
9524 def_builtin (target_flags
, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLAT
);
9525 def_builtin (target_flags
, "__builtin_spe_evlwhe", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHE
);
9526 def_builtin (target_flags
, "__builtin_spe_evlwhos", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOS
);
9527 def_builtin (target_flags
, "__builtin_spe_evlwhou", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOU
);
9528 def_builtin (target_flags
, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLAT
);
9529 def_builtin (target_flags
, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLAT
);
9532 d
= (struct builtin_description
*) bdesc_spe_predicates
;
9533 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, d
++)
9537 switch (insn_data
[d
->icode
].operand
[1].mode
)
9540 type
= int_ftype_int_v2si_v2si
;
9543 type
= int_ftype_int_v2sf_v2sf
;
9549 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
9552 /* Evsel predicates. */
9553 d
= (struct builtin_description
*) bdesc_spe_evsel
;
9554 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, d
++)
9558 switch (insn_data
[d
->icode
].operand
[1].mode
)
9561 type
= v2si_ftype_4_v2si
;
9564 type
= v2sf_ftype_4_v2sf
;
9570 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
9575 paired_init_builtins (void)
9577 const struct builtin_description
*d
;
9579 tree endlink
= void_list_node
;
9581 tree int_ftype_int_v2sf_v2sf
9582 = build_function_type
9584 tree_cons (NULL_TREE
, integer_type_node
,
9585 tree_cons (NULL_TREE
, V2SF_type_node
,
9586 tree_cons (NULL_TREE
, V2SF_type_node
,
9588 tree pcfloat_type_node
=
9589 build_pointer_type (build_qualified_type
9590 (float_type_node
, TYPE_QUAL_CONST
));
9592 tree v2sf_ftype_long_pcfloat
= build_function_type_list (V2SF_type_node
,
9593 long_integer_type_node
,
9596 tree void_ftype_v2sf_long_pcfloat
=
9597 build_function_type_list (void_type_node
,
9599 long_integer_type_node
,
9604 def_builtin (0, "__builtin_paired_lx", v2sf_ftype_long_pcfloat
,
9608 def_builtin (0, "__builtin_paired_stx", void_ftype_v2sf_long_pcfloat
,
9609 PAIRED_BUILTIN_STX
);
9612 d
= bdesc_paired_preds
;
9613 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); ++i
, d
++)
9617 switch (insn_data
[d
->icode
].operand
[1].mode
)
9620 type
= int_ftype_int_v2sf_v2sf
;
9626 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
9631 altivec_init_builtins (void)
9633 const struct builtin_description
*d
;
9634 const struct builtin_description_predicates
*dp
;
9638 tree pfloat_type_node
= build_pointer_type (float_type_node
);
9639 tree pint_type_node
= build_pointer_type (integer_type_node
);
9640 tree pshort_type_node
= build_pointer_type (short_integer_type_node
);
9641 tree pchar_type_node
= build_pointer_type (char_type_node
);
9643 tree pvoid_type_node
= build_pointer_type (void_type_node
);
9645 tree pcfloat_type_node
= build_pointer_type (build_qualified_type (float_type_node
, TYPE_QUAL_CONST
));
9646 tree pcint_type_node
= build_pointer_type (build_qualified_type (integer_type_node
, TYPE_QUAL_CONST
));
9647 tree pcshort_type_node
= build_pointer_type (build_qualified_type (short_integer_type_node
, TYPE_QUAL_CONST
));
9648 tree pcchar_type_node
= build_pointer_type (build_qualified_type (char_type_node
, TYPE_QUAL_CONST
));
9650 tree pcvoid_type_node
= build_pointer_type (build_qualified_type (void_type_node
, TYPE_QUAL_CONST
));
9652 tree int_ftype_opaque
9653 = build_function_type_list (integer_type_node
,
9654 opaque_V4SI_type_node
, NULL_TREE
);
9656 tree opaque_ftype_opaque_int
9657 = build_function_type_list (opaque_V4SI_type_node
,
9658 opaque_V4SI_type_node
, integer_type_node
, NULL_TREE
);
9659 tree opaque_ftype_opaque_opaque_int
9660 = build_function_type_list (opaque_V4SI_type_node
,
9661 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
9662 integer_type_node
, NULL_TREE
);
9663 tree int_ftype_int_opaque_opaque
9664 = build_function_type_list (integer_type_node
,
9665 integer_type_node
, opaque_V4SI_type_node
,
9666 opaque_V4SI_type_node
, NULL_TREE
);
9667 tree int_ftype_int_v4si_v4si
9668 = build_function_type_list (integer_type_node
,
9669 integer_type_node
, V4SI_type_node
,
9670 V4SI_type_node
, NULL_TREE
);
9671 tree v4sf_ftype_pcfloat
9672 = build_function_type_list (V4SF_type_node
, pcfloat_type_node
, NULL_TREE
);
9673 tree void_ftype_pfloat_v4sf
9674 = build_function_type_list (void_type_node
,
9675 pfloat_type_node
, V4SF_type_node
, NULL_TREE
);
9676 tree v4si_ftype_pcint
9677 = build_function_type_list (V4SI_type_node
, pcint_type_node
, NULL_TREE
);
9678 tree void_ftype_pint_v4si
9679 = build_function_type_list (void_type_node
,
9680 pint_type_node
, V4SI_type_node
, NULL_TREE
);
9681 tree v8hi_ftype_pcshort
9682 = build_function_type_list (V8HI_type_node
, pcshort_type_node
, NULL_TREE
);
9683 tree void_ftype_pshort_v8hi
9684 = build_function_type_list (void_type_node
,
9685 pshort_type_node
, V8HI_type_node
, NULL_TREE
);
9686 tree v16qi_ftype_pcchar
9687 = build_function_type_list (V16QI_type_node
, pcchar_type_node
, NULL_TREE
);
9688 tree void_ftype_pchar_v16qi
9689 = build_function_type_list (void_type_node
,
9690 pchar_type_node
, V16QI_type_node
, NULL_TREE
);
9691 tree void_ftype_v4si
9692 = build_function_type_list (void_type_node
, V4SI_type_node
, NULL_TREE
);
9693 tree v8hi_ftype_void
9694 = build_function_type (V8HI_type_node
, void_list_node
);
9695 tree void_ftype_void
9696 = build_function_type (void_type_node
, void_list_node
);
9698 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
9700 tree opaque_ftype_long_pcvoid
9701 = build_function_type_list (opaque_V4SI_type_node
,
9702 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
9703 tree v16qi_ftype_long_pcvoid
9704 = build_function_type_list (V16QI_type_node
,
9705 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
9706 tree v8hi_ftype_long_pcvoid
9707 = build_function_type_list (V8HI_type_node
,
9708 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
9709 tree v4si_ftype_long_pcvoid
9710 = build_function_type_list (V4SI_type_node
,
9711 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
9713 tree void_ftype_opaque_long_pvoid
9714 = build_function_type_list (void_type_node
,
9715 opaque_V4SI_type_node
, long_integer_type_node
,
9716 pvoid_type_node
, NULL_TREE
);
9717 tree void_ftype_v4si_long_pvoid
9718 = build_function_type_list (void_type_node
,
9719 V4SI_type_node
, long_integer_type_node
,
9720 pvoid_type_node
, NULL_TREE
);
9721 tree void_ftype_v16qi_long_pvoid
9722 = build_function_type_list (void_type_node
,
9723 V16QI_type_node
, long_integer_type_node
,
9724 pvoid_type_node
, NULL_TREE
);
9725 tree void_ftype_v8hi_long_pvoid
9726 = build_function_type_list (void_type_node
,
9727 V8HI_type_node
, long_integer_type_node
,
9728 pvoid_type_node
, NULL_TREE
);
9729 tree int_ftype_int_v8hi_v8hi
9730 = build_function_type_list (integer_type_node
,
9731 integer_type_node
, V8HI_type_node
,
9732 V8HI_type_node
, NULL_TREE
);
9733 tree int_ftype_int_v16qi_v16qi
9734 = build_function_type_list (integer_type_node
,
9735 integer_type_node
, V16QI_type_node
,
9736 V16QI_type_node
, NULL_TREE
);
9737 tree int_ftype_int_v4sf_v4sf
9738 = build_function_type_list (integer_type_node
,
9739 integer_type_node
, V4SF_type_node
,
9740 V4SF_type_node
, NULL_TREE
);
9741 tree v4si_ftype_v4si
9742 = build_function_type_list (V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
9743 tree v8hi_ftype_v8hi
9744 = build_function_type_list (V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
9745 tree v16qi_ftype_v16qi
9746 = build_function_type_list (V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
9747 tree v4sf_ftype_v4sf
9748 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
9749 tree void_ftype_pcvoid_int_int
9750 = build_function_type_list (void_type_node
,
9751 pcvoid_type_node
, integer_type_node
,
9752 integer_type_node
, NULL_TREE
);
9754 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat
,
9755 ALTIVEC_BUILTIN_LD_INTERNAL_4sf
);
9756 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf
,
9757 ALTIVEC_BUILTIN_ST_INTERNAL_4sf
);
9758 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint
,
9759 ALTIVEC_BUILTIN_LD_INTERNAL_4si
);
9760 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si
,
9761 ALTIVEC_BUILTIN_ST_INTERNAL_4si
);
9762 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort
,
9763 ALTIVEC_BUILTIN_LD_INTERNAL_8hi
);
9764 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi
,
9765 ALTIVEC_BUILTIN_ST_INTERNAL_8hi
);
9766 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar
,
9767 ALTIVEC_BUILTIN_LD_INTERNAL_16qi
);
9768 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi
,
9769 ALTIVEC_BUILTIN_ST_INTERNAL_16qi
);
9770 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_mtvscr", void_ftype_v4si
, ALTIVEC_BUILTIN_MTVSCR
);
9771 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_mfvscr", v8hi_ftype_void
, ALTIVEC_BUILTIN_MFVSCR
);
9772 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_dssall", void_ftype_void
, ALTIVEC_BUILTIN_DSSALL
);
9773 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_dss", void_ftype_int
, ALTIVEC_BUILTIN_DSS
);
9774 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSL
);
9775 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSR
);
9776 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEBX
);
9777 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEHX
);
9778 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEWX
);
9779 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVXL
);
9780 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVX
);
9781 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVX
);
9782 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVEWX
);
9783 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVXL
);
9784 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVEBX
);
9785 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid
, ALTIVEC_BUILTIN_STVEHX
);
9786 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ld", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LD
);
9787 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lde", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDE
);
9788 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ldl", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDL
);
9789 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSL
);
9790 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSR
);
9791 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEBX
);
9792 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEHX
);
9793 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEWX
);
9794 def_builtin (MASK_ALTIVEC
, "__builtin_vec_st", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_ST
);
9795 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ste", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STE
);
9796 def_builtin (MASK_ALTIVEC
, "__builtin_vec_stl", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STL
);
9797 def_builtin (MASK_ALTIVEC
, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEWX
);
9798 def_builtin (MASK_ALTIVEC
, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEBX
);
9799 def_builtin (MASK_ALTIVEC
, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEHX
);
9801 def_builtin (MASK_ALTIVEC
, "__builtin_vec_step", int_ftype_opaque
, ALTIVEC_BUILTIN_VEC_STEP
);
9803 def_builtin (MASK_ALTIVEC
, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_SLD
);
9804 def_builtin (MASK_ALTIVEC
, "__builtin_vec_splat", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_SPLAT
);
9805 def_builtin (MASK_ALTIVEC
, "__builtin_vec_vspltw", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTW
);
9806 def_builtin (MASK_ALTIVEC
, "__builtin_vec_vsplth", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTH
);
9807 def_builtin (MASK_ALTIVEC
, "__builtin_vec_vspltb", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTB
);
9808 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ctf", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTF
);
9809 def_builtin (MASK_ALTIVEC
, "__builtin_vec_vcfsx", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFSX
);
9810 def_builtin (MASK_ALTIVEC
, "__builtin_vec_vcfux", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFUX
);
9811 def_builtin (MASK_ALTIVEC
, "__builtin_vec_cts", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTS
);
9812 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ctu", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTU
);
9814 /* Add the DST variants. */
9816 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
9817 def_builtin (d
->mask
, d
->name
, void_ftype_pcvoid_int_int
, d
->code
);
9819 /* Initialize the predicates. */
9820 dp
= bdesc_altivec_preds
;
9821 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, dp
++)
9823 enum machine_mode mode1
;
9825 bool is_overloaded
= dp
->code
>= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9826 && dp
->code
<= ALTIVEC_BUILTIN_OVERLOADED_LAST
;
9831 mode1
= insn_data
[dp
->icode
].operand
[1].mode
;
9836 type
= int_ftype_int_opaque_opaque
;
9839 type
= int_ftype_int_v4si_v4si
;
9842 type
= int_ftype_int_v8hi_v8hi
;
9845 type
= int_ftype_int_v16qi_v16qi
;
9848 type
= int_ftype_int_v4sf_v4sf
;
9854 def_builtin (dp
->mask
, dp
->name
, type
, dp
->code
);
9857 /* Initialize the abs* operators. */
9859 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
9861 enum machine_mode mode0
;
9864 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
9869 type
= v4si_ftype_v4si
;
9872 type
= v8hi_ftype_v8hi
;
9875 type
= v16qi_ftype_v16qi
;
9878 type
= v4sf_ftype_v4sf
;
9884 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
9891 /* Initialize target builtin that implements
9892 targetm.vectorize.builtin_mask_for_load. */
9894 decl
= add_builtin_function ("__builtin_altivec_mask_for_load",
9895 v16qi_ftype_long_pcvoid
,
9896 ALTIVEC_BUILTIN_MASK_FOR_LOAD
,
9897 BUILT_IN_MD
, NULL
, NULL_TREE
);
9898 TREE_READONLY (decl
) = 1;
9899 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
9900 altivec_builtin_mask_for_load
= decl
;
9903 /* Access to the vec_init patterns. */
9904 ftype
= build_function_type_list (V4SI_type_node
, integer_type_node
,
9905 integer_type_node
, integer_type_node
,
9906 integer_type_node
, NULL_TREE
);
9907 def_builtin (MASK_ALTIVEC
, "__builtin_vec_init_v4si", ftype
,
9908 ALTIVEC_BUILTIN_VEC_INIT_V4SI
);
9910 ftype
= build_function_type_list (V8HI_type_node
, short_integer_type_node
,
9911 short_integer_type_node
,
9912 short_integer_type_node
,
9913 short_integer_type_node
,
9914 short_integer_type_node
,
9915 short_integer_type_node
,
9916 short_integer_type_node
,
9917 short_integer_type_node
, NULL_TREE
);
9918 def_builtin (MASK_ALTIVEC
, "__builtin_vec_init_v8hi", ftype
,
9919 ALTIVEC_BUILTIN_VEC_INIT_V8HI
);
9921 ftype
= build_function_type_list (V16QI_type_node
, char_type_node
,
9922 char_type_node
, char_type_node
,
9923 char_type_node
, char_type_node
,
9924 char_type_node
, char_type_node
,
9925 char_type_node
, char_type_node
,
9926 char_type_node
, char_type_node
,
9927 char_type_node
, char_type_node
,
9928 char_type_node
, char_type_node
,
9929 char_type_node
, NULL_TREE
);
9930 def_builtin (MASK_ALTIVEC
, "__builtin_vec_init_v16qi", ftype
,
9931 ALTIVEC_BUILTIN_VEC_INIT_V16QI
);
9933 ftype
= build_function_type_list (V4SF_type_node
, float_type_node
,
9934 float_type_node
, float_type_node
,
9935 float_type_node
, NULL_TREE
);
9936 def_builtin (MASK_ALTIVEC
, "__builtin_vec_init_v4sf", ftype
,
9937 ALTIVEC_BUILTIN_VEC_INIT_V4SF
);
9939 /* Access to the vec_set patterns. */
9940 ftype
= build_function_type_list (V4SI_type_node
, V4SI_type_node
,
9942 integer_type_node
, NULL_TREE
);
9943 def_builtin (MASK_ALTIVEC
, "__builtin_vec_set_v4si", ftype
,
9944 ALTIVEC_BUILTIN_VEC_SET_V4SI
);
9946 ftype
= build_function_type_list (V8HI_type_node
, V8HI_type_node
,
9948 integer_type_node
, NULL_TREE
);
9949 def_builtin (MASK_ALTIVEC
, "__builtin_vec_set_v8hi", ftype
,
9950 ALTIVEC_BUILTIN_VEC_SET_V8HI
);
9952 ftype
= build_function_type_list (V8HI_type_node
, V16QI_type_node
,
9954 integer_type_node
, NULL_TREE
);
9955 def_builtin (MASK_ALTIVEC
, "__builtin_vec_set_v16qi", ftype
,
9956 ALTIVEC_BUILTIN_VEC_SET_V16QI
);
9958 ftype
= build_function_type_list (V4SF_type_node
, V4SF_type_node
,
9960 integer_type_node
, NULL_TREE
);
9961 def_builtin (MASK_ALTIVEC
, "__builtin_vec_set_v4sf", ftype
,
9962 ALTIVEC_BUILTIN_VEC_SET_V4SF
);
9964 /* Access to the vec_extract patterns. */
9965 ftype
= build_function_type_list (intSI_type_node
, V4SI_type_node
,
9966 integer_type_node
, NULL_TREE
);
9967 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ext_v4si", ftype
,
9968 ALTIVEC_BUILTIN_VEC_EXT_V4SI
);
9970 ftype
= build_function_type_list (intHI_type_node
, V8HI_type_node
,
9971 integer_type_node
, NULL_TREE
);
9972 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ext_v8hi", ftype
,
9973 ALTIVEC_BUILTIN_VEC_EXT_V8HI
);
9975 ftype
= build_function_type_list (intQI_type_node
, V16QI_type_node
,
9976 integer_type_node
, NULL_TREE
);
9977 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ext_v16qi", ftype
,
9978 ALTIVEC_BUILTIN_VEC_EXT_V16QI
);
9980 ftype
= build_function_type_list (float_type_node
, V4SF_type_node
,
9981 integer_type_node
, NULL_TREE
);
9982 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ext_v4sf", ftype
,
9983 ALTIVEC_BUILTIN_VEC_EXT_V4SF
);
9987 rs6000_common_init_builtins (void)
9989 const struct builtin_description
*d
;
9992 tree v2sf_ftype_v2sf_v2sf_v2sf
9993 = build_function_type_list (V2SF_type_node
,
9994 V2SF_type_node
, V2SF_type_node
,
9995 V2SF_type_node
, NULL_TREE
);
9997 tree v4sf_ftype_v4sf_v4sf_v16qi
9998 = build_function_type_list (V4SF_type_node
,
9999 V4SF_type_node
, V4SF_type_node
,
10000 V16QI_type_node
, NULL_TREE
);
10001 tree v4si_ftype_v4si_v4si_v16qi
10002 = build_function_type_list (V4SI_type_node
,
10003 V4SI_type_node
, V4SI_type_node
,
10004 V16QI_type_node
, NULL_TREE
);
10005 tree v8hi_ftype_v8hi_v8hi_v16qi
10006 = build_function_type_list (V8HI_type_node
,
10007 V8HI_type_node
, V8HI_type_node
,
10008 V16QI_type_node
, NULL_TREE
);
10009 tree v16qi_ftype_v16qi_v16qi_v16qi
10010 = build_function_type_list (V16QI_type_node
,
10011 V16QI_type_node
, V16QI_type_node
,
10012 V16QI_type_node
, NULL_TREE
);
10013 tree v4si_ftype_int
10014 = build_function_type_list (V4SI_type_node
, integer_type_node
, NULL_TREE
);
10015 tree v8hi_ftype_int
10016 = build_function_type_list (V8HI_type_node
, integer_type_node
, NULL_TREE
);
10017 tree v16qi_ftype_int
10018 = build_function_type_list (V16QI_type_node
, integer_type_node
, NULL_TREE
);
10019 tree v8hi_ftype_v16qi
10020 = build_function_type_list (V8HI_type_node
, V16QI_type_node
, NULL_TREE
);
10021 tree v4sf_ftype_v4sf
10022 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
10024 tree v2si_ftype_v2si_v2si
10025 = build_function_type_list (opaque_V2SI_type_node
,
10026 opaque_V2SI_type_node
,
10027 opaque_V2SI_type_node
, NULL_TREE
);
10029 tree v2sf_ftype_v2sf_v2sf_spe
10030 = build_function_type_list (opaque_V2SF_type_node
,
10031 opaque_V2SF_type_node
,
10032 opaque_V2SF_type_node
, NULL_TREE
);
10034 tree v2sf_ftype_v2sf_v2sf
10035 = build_function_type_list (V2SF_type_node
,
10037 V2SF_type_node
, NULL_TREE
);
10040 tree v2si_ftype_int_int
10041 = build_function_type_list (opaque_V2SI_type_node
,
10042 integer_type_node
, integer_type_node
,
10045 tree opaque_ftype_opaque
10046 = build_function_type_list (opaque_V4SI_type_node
,
10047 opaque_V4SI_type_node
, NULL_TREE
);
10049 tree v2si_ftype_v2si
10050 = build_function_type_list (opaque_V2SI_type_node
,
10051 opaque_V2SI_type_node
, NULL_TREE
);
10053 tree v2sf_ftype_v2sf_spe
10054 = build_function_type_list (opaque_V2SF_type_node
,
10055 opaque_V2SF_type_node
, NULL_TREE
);
10057 tree v2sf_ftype_v2sf
10058 = build_function_type_list (V2SF_type_node
,
10059 V2SF_type_node
, NULL_TREE
);
10061 tree v2sf_ftype_v2si
10062 = build_function_type_list (opaque_V2SF_type_node
,
10063 opaque_V2SI_type_node
, NULL_TREE
);
10065 tree v2si_ftype_v2sf
10066 = build_function_type_list (opaque_V2SI_type_node
,
10067 opaque_V2SF_type_node
, NULL_TREE
);
10069 tree v2si_ftype_v2si_char
10070 = build_function_type_list (opaque_V2SI_type_node
,
10071 opaque_V2SI_type_node
,
10072 char_type_node
, NULL_TREE
);
10074 tree v2si_ftype_int_char
10075 = build_function_type_list (opaque_V2SI_type_node
,
10076 integer_type_node
, char_type_node
, NULL_TREE
);
10078 tree v2si_ftype_char
10079 = build_function_type_list (opaque_V2SI_type_node
,
10080 char_type_node
, NULL_TREE
);
10082 tree int_ftype_int_int
10083 = build_function_type_list (integer_type_node
,
10084 integer_type_node
, integer_type_node
,
10087 tree opaque_ftype_opaque_opaque
10088 = build_function_type_list (opaque_V4SI_type_node
,
10089 opaque_V4SI_type_node
, opaque_V4SI_type_node
, NULL_TREE
);
10090 tree v4si_ftype_v4si_v4si
10091 = build_function_type_list (V4SI_type_node
,
10092 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
10093 tree v4sf_ftype_v4si_int
10094 = build_function_type_list (V4SF_type_node
,
10095 V4SI_type_node
, integer_type_node
, NULL_TREE
);
10096 tree v4si_ftype_v4sf_int
10097 = build_function_type_list (V4SI_type_node
,
10098 V4SF_type_node
, integer_type_node
, NULL_TREE
);
10099 tree v4si_ftype_v4si_int
10100 = build_function_type_list (V4SI_type_node
,
10101 V4SI_type_node
, integer_type_node
, NULL_TREE
);
10102 tree v8hi_ftype_v8hi_int
10103 = build_function_type_list (V8HI_type_node
,
10104 V8HI_type_node
, integer_type_node
, NULL_TREE
);
10105 tree v16qi_ftype_v16qi_int
10106 = build_function_type_list (V16QI_type_node
,
10107 V16QI_type_node
, integer_type_node
, NULL_TREE
);
10108 tree v16qi_ftype_v16qi_v16qi_int
10109 = build_function_type_list (V16QI_type_node
,
10110 V16QI_type_node
, V16QI_type_node
,
10111 integer_type_node
, NULL_TREE
);
10112 tree v8hi_ftype_v8hi_v8hi_int
10113 = build_function_type_list (V8HI_type_node
,
10114 V8HI_type_node
, V8HI_type_node
,
10115 integer_type_node
, NULL_TREE
);
10116 tree v4si_ftype_v4si_v4si_int
10117 = build_function_type_list (V4SI_type_node
,
10118 V4SI_type_node
, V4SI_type_node
,
10119 integer_type_node
, NULL_TREE
);
10120 tree v4sf_ftype_v4sf_v4sf_int
10121 = build_function_type_list (V4SF_type_node
,
10122 V4SF_type_node
, V4SF_type_node
,
10123 integer_type_node
, NULL_TREE
);
10124 tree v4sf_ftype_v4sf_v4sf
10125 = build_function_type_list (V4SF_type_node
,
10126 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
10127 tree opaque_ftype_opaque_opaque_opaque
10128 = build_function_type_list (opaque_V4SI_type_node
,
10129 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
10130 opaque_V4SI_type_node
, NULL_TREE
);
10131 tree v4sf_ftype_v4sf_v4sf_v4si
10132 = build_function_type_list (V4SF_type_node
,
10133 V4SF_type_node
, V4SF_type_node
,
10134 V4SI_type_node
, NULL_TREE
);
10135 tree v4sf_ftype_v4sf_v4sf_v4sf
10136 = build_function_type_list (V4SF_type_node
,
10137 V4SF_type_node
, V4SF_type_node
,
10138 V4SF_type_node
, NULL_TREE
);
10139 tree v4si_ftype_v4si_v4si_v4si
10140 = build_function_type_list (V4SI_type_node
,
10141 V4SI_type_node
, V4SI_type_node
,
10142 V4SI_type_node
, NULL_TREE
);
10143 tree v8hi_ftype_v8hi_v8hi
10144 = build_function_type_list (V8HI_type_node
,
10145 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
10146 tree v8hi_ftype_v8hi_v8hi_v8hi
10147 = build_function_type_list (V8HI_type_node
,
10148 V8HI_type_node
, V8HI_type_node
,
10149 V8HI_type_node
, NULL_TREE
);
10150 tree v4si_ftype_v8hi_v8hi_v4si
10151 = build_function_type_list (V4SI_type_node
,
10152 V8HI_type_node
, V8HI_type_node
,
10153 V4SI_type_node
, NULL_TREE
);
10154 tree v4si_ftype_v16qi_v16qi_v4si
10155 = build_function_type_list (V4SI_type_node
,
10156 V16QI_type_node
, V16QI_type_node
,
10157 V4SI_type_node
, NULL_TREE
);
10158 tree v16qi_ftype_v16qi_v16qi
10159 = build_function_type_list (V16QI_type_node
,
10160 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
10161 tree v4si_ftype_v4sf_v4sf
10162 = build_function_type_list (V4SI_type_node
,
10163 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
10164 tree v8hi_ftype_v16qi_v16qi
10165 = build_function_type_list (V8HI_type_node
,
10166 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
10167 tree v4si_ftype_v8hi_v8hi
10168 = build_function_type_list (V4SI_type_node
,
10169 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
10170 tree v8hi_ftype_v4si_v4si
10171 = build_function_type_list (V8HI_type_node
,
10172 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
10173 tree v16qi_ftype_v8hi_v8hi
10174 = build_function_type_list (V16QI_type_node
,
10175 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
10176 tree v4si_ftype_v16qi_v4si
10177 = build_function_type_list (V4SI_type_node
,
10178 V16QI_type_node
, V4SI_type_node
, NULL_TREE
);
10179 tree v4si_ftype_v16qi_v16qi
10180 = build_function_type_list (V4SI_type_node
,
10181 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
10182 tree v4si_ftype_v8hi_v4si
10183 = build_function_type_list (V4SI_type_node
,
10184 V8HI_type_node
, V4SI_type_node
, NULL_TREE
);
10185 tree v4si_ftype_v8hi
10186 = build_function_type_list (V4SI_type_node
, V8HI_type_node
, NULL_TREE
);
10187 tree int_ftype_v4si_v4si
10188 = build_function_type_list (integer_type_node
,
10189 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
10190 tree int_ftype_v4sf_v4sf
10191 = build_function_type_list (integer_type_node
,
10192 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
10193 tree int_ftype_v16qi_v16qi
10194 = build_function_type_list (integer_type_node
,
10195 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
10196 tree int_ftype_v8hi_v8hi
10197 = build_function_type_list (integer_type_node
,
10198 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
10200 /* Add the simple ternary operators. */
10202 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
10204 enum machine_mode mode0
, mode1
, mode2
, mode3
;
10206 bool is_overloaded
= d
->code
>= ALTIVEC_BUILTIN_OVERLOADED_FIRST
10207 && d
->code
<= ALTIVEC_BUILTIN_OVERLOADED_LAST
;
10218 if (d
->name
== 0 || d
->icode
== CODE_FOR_nothing
)
10221 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
10222 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
10223 mode2
= insn_data
[d
->icode
].operand
[2].mode
;
10224 mode3
= insn_data
[d
->icode
].operand
[3].mode
;
10227 /* When all four are of the same mode. */
10228 if (mode0
== mode1
&& mode1
== mode2
&& mode2
== mode3
)
10233 type
= opaque_ftype_opaque_opaque_opaque
;
10236 type
= v4si_ftype_v4si_v4si_v4si
;
10239 type
= v4sf_ftype_v4sf_v4sf_v4sf
;
10242 type
= v8hi_ftype_v8hi_v8hi_v8hi
;
10245 type
= v16qi_ftype_v16qi_v16qi_v16qi
;
10248 type
= v2sf_ftype_v2sf_v2sf_v2sf
;
10251 gcc_unreachable ();
10254 else if (mode0
== mode1
&& mode1
== mode2
&& mode3
== V16QImode
)
10259 type
= v4si_ftype_v4si_v4si_v16qi
;
10262 type
= v4sf_ftype_v4sf_v4sf_v16qi
;
10265 type
= v8hi_ftype_v8hi_v8hi_v16qi
;
10268 type
= v16qi_ftype_v16qi_v16qi_v16qi
;
10271 gcc_unreachable ();
10274 else if (mode0
== V4SImode
&& mode1
== V16QImode
&& mode2
== V16QImode
10275 && mode3
== V4SImode
)
10276 type
= v4si_ftype_v16qi_v16qi_v4si
;
10277 else if (mode0
== V4SImode
&& mode1
== V8HImode
&& mode2
== V8HImode
10278 && mode3
== V4SImode
)
10279 type
= v4si_ftype_v8hi_v8hi_v4si
;
10280 else if (mode0
== V4SFmode
&& mode1
== V4SFmode
&& mode2
== V4SFmode
10281 && mode3
== V4SImode
)
10282 type
= v4sf_ftype_v4sf_v4sf_v4si
;
10284 /* vchar, vchar, vchar, 4-bit literal. */
10285 else if (mode0
== V16QImode
&& mode1
== mode0
&& mode2
== mode0
10286 && mode3
== QImode
)
10287 type
= v16qi_ftype_v16qi_v16qi_int
;
10289 /* vshort, vshort, vshort, 4-bit literal. */
10290 else if (mode0
== V8HImode
&& mode1
== mode0
&& mode2
== mode0
10291 && mode3
== QImode
)
10292 type
= v8hi_ftype_v8hi_v8hi_int
;
10294 /* vint, vint, vint, 4-bit literal. */
10295 else if (mode0
== V4SImode
&& mode1
== mode0
&& mode2
== mode0
10296 && mode3
== QImode
)
10297 type
= v4si_ftype_v4si_v4si_int
;
10299 /* vfloat, vfloat, vfloat, 4-bit literal. */
10300 else if (mode0
== V4SFmode
&& mode1
== mode0
&& mode2
== mode0
10301 && mode3
== QImode
)
10302 type
= v4sf_ftype_v4sf_v4sf_int
;
10305 gcc_unreachable ();
10307 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
10310 /* Add the simple binary operators. */
10311 d
= (struct builtin_description
*) bdesc_2arg
;
10312 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
10314 enum machine_mode mode0
, mode1
, mode2
;
10316 bool is_overloaded
= d
->code
>= ALTIVEC_BUILTIN_OVERLOADED_FIRST
10317 && d
->code
<= ALTIVEC_BUILTIN_OVERLOADED_LAST
;
10327 if (d
->name
== 0 || d
->icode
== CODE_FOR_nothing
)
10330 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
10331 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
10332 mode2
= insn_data
[d
->icode
].operand
[2].mode
;
10335 /* When all three operands are of the same mode. */
10336 if (mode0
== mode1
&& mode1
== mode2
)
10341 type
= opaque_ftype_opaque_opaque
;
10344 type
= v4sf_ftype_v4sf_v4sf
;
10347 type
= v4si_ftype_v4si_v4si
;
10350 type
= v16qi_ftype_v16qi_v16qi
;
10353 type
= v8hi_ftype_v8hi_v8hi
;
10356 type
= v2si_ftype_v2si_v2si
;
10359 if (TARGET_PAIRED_FLOAT
)
10360 type
= v2sf_ftype_v2sf_v2sf
;
10362 type
= v2sf_ftype_v2sf_v2sf_spe
;
10365 type
= int_ftype_int_int
;
10368 gcc_unreachable ();
10372 /* A few other combos we really don't want to do manually. */
10374 /* vint, vfloat, vfloat. */
10375 else if (mode0
== V4SImode
&& mode1
== V4SFmode
&& mode2
== V4SFmode
)
10376 type
= v4si_ftype_v4sf_v4sf
;
10378 /* vshort, vchar, vchar. */
10379 else if (mode0
== V8HImode
&& mode1
== V16QImode
&& mode2
== V16QImode
)
10380 type
= v8hi_ftype_v16qi_v16qi
;
10382 /* vint, vshort, vshort. */
10383 else if (mode0
== V4SImode
&& mode1
== V8HImode
&& mode2
== V8HImode
)
10384 type
= v4si_ftype_v8hi_v8hi
;
10386 /* vshort, vint, vint. */
10387 else if (mode0
== V8HImode
&& mode1
== V4SImode
&& mode2
== V4SImode
)
10388 type
= v8hi_ftype_v4si_v4si
;
10390 /* vchar, vshort, vshort. */
10391 else if (mode0
== V16QImode
&& mode1
== V8HImode
&& mode2
== V8HImode
)
10392 type
= v16qi_ftype_v8hi_v8hi
;
10394 /* vint, vchar, vint. */
10395 else if (mode0
== V4SImode
&& mode1
== V16QImode
&& mode2
== V4SImode
)
10396 type
= v4si_ftype_v16qi_v4si
;
10398 /* vint, vchar, vchar. */
10399 else if (mode0
== V4SImode
&& mode1
== V16QImode
&& mode2
== V16QImode
)
10400 type
= v4si_ftype_v16qi_v16qi
;
10402 /* vint, vshort, vint. */
10403 else if (mode0
== V4SImode
&& mode1
== V8HImode
&& mode2
== V4SImode
)
10404 type
= v4si_ftype_v8hi_v4si
;
10406 /* vint, vint, 5-bit literal. */
10407 else if (mode0
== V4SImode
&& mode1
== V4SImode
&& mode2
== QImode
)
10408 type
= v4si_ftype_v4si_int
;
10410 /* vshort, vshort, 5-bit literal. */
10411 else if (mode0
== V8HImode
&& mode1
== V8HImode
&& mode2
== QImode
)
10412 type
= v8hi_ftype_v8hi_int
;
10414 /* vchar, vchar, 5-bit literal. */
10415 else if (mode0
== V16QImode
&& mode1
== V16QImode
&& mode2
== QImode
)
10416 type
= v16qi_ftype_v16qi_int
;
10418 /* vfloat, vint, 5-bit literal. */
10419 else if (mode0
== V4SFmode
&& mode1
== V4SImode
&& mode2
== QImode
)
10420 type
= v4sf_ftype_v4si_int
;
10422 /* vint, vfloat, 5-bit literal. */
10423 else if (mode0
== V4SImode
&& mode1
== V4SFmode
&& mode2
== QImode
)
10424 type
= v4si_ftype_v4sf_int
;
10426 else if (mode0
== V2SImode
&& mode1
== SImode
&& mode2
== SImode
)
10427 type
= v2si_ftype_int_int
;
10429 else if (mode0
== V2SImode
&& mode1
== V2SImode
&& mode2
== QImode
)
10430 type
= v2si_ftype_v2si_char
;
10432 else if (mode0
== V2SImode
&& mode1
== SImode
&& mode2
== QImode
)
10433 type
= v2si_ftype_int_char
;
10438 gcc_assert (mode0
== SImode
);
10442 type
= int_ftype_v4si_v4si
;
10445 type
= int_ftype_v4sf_v4sf
;
10448 type
= int_ftype_v16qi_v16qi
;
10451 type
= int_ftype_v8hi_v8hi
;
10454 gcc_unreachable ();
10458 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
10461 /* Add the simple unary operators. */
10462 d
= (struct builtin_description
*) bdesc_1arg
;
10463 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
10465 enum machine_mode mode0
, mode1
;
10467 bool is_overloaded
= d
->code
>= ALTIVEC_BUILTIN_OVERLOADED_FIRST
10468 && d
->code
<= ALTIVEC_BUILTIN_OVERLOADED_LAST
;
10477 if (d
->name
== 0 || d
->icode
== CODE_FOR_nothing
)
10480 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
10481 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
10484 if (mode0
== V4SImode
&& mode1
== QImode
)
10485 type
= v4si_ftype_int
;
10486 else if (mode0
== V8HImode
&& mode1
== QImode
)
10487 type
= v8hi_ftype_int
;
10488 else if (mode0
== V16QImode
&& mode1
== QImode
)
10489 type
= v16qi_ftype_int
;
10490 else if (mode0
== VOIDmode
&& mode1
== VOIDmode
)
10491 type
= opaque_ftype_opaque
;
10492 else if (mode0
== V4SFmode
&& mode1
== V4SFmode
)
10493 type
= v4sf_ftype_v4sf
;
10494 else if (mode0
== V8HImode
&& mode1
== V16QImode
)
10495 type
= v8hi_ftype_v16qi
;
10496 else if (mode0
== V4SImode
&& mode1
== V8HImode
)
10497 type
= v4si_ftype_v8hi
;
10498 else if (mode0
== V2SImode
&& mode1
== V2SImode
)
10499 type
= v2si_ftype_v2si
;
10500 else if (mode0
== V2SFmode
&& mode1
== V2SFmode
)
10502 if (TARGET_PAIRED_FLOAT
)
10503 type
= v2sf_ftype_v2sf
;
10505 type
= v2sf_ftype_v2sf_spe
;
10507 else if (mode0
== V2SFmode
&& mode1
== V2SImode
)
10508 type
= v2sf_ftype_v2si
;
10509 else if (mode0
== V2SImode
&& mode1
== V2SFmode
)
10510 type
= v2si_ftype_v2sf
;
10511 else if (mode0
== V2SImode
&& mode1
== QImode
)
10512 type
= v2si_ftype_char
;
10514 gcc_unreachable ();
10516 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
10521 rs6000_init_libfuncs (void)
10523 if (DEFAULT_ABI
!= ABI_V4
&& TARGET_XCOFF
10524 && !TARGET_POWER2
&& !TARGET_POWERPC
)
10526 /* AIX library routines for float->int conversion. */
10527 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__itrunc");
10528 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__uitrunc");
10529 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_qitrunc");
10530 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_quitrunc");
10533 if (!TARGET_IEEEQUAD
)
10534 /* AIX/Darwin/64-bit Linux quad floating point routines. */
10535 if (!TARGET_XL_COMPAT
)
10537 set_optab_libfunc (add_optab
, TFmode
, "__gcc_qadd");
10538 set_optab_libfunc (sub_optab
, TFmode
, "__gcc_qsub");
10539 set_optab_libfunc (smul_optab
, TFmode
, "__gcc_qmul");
10540 set_optab_libfunc (sdiv_optab
, TFmode
, "__gcc_qdiv");
10542 if (!(TARGET_HARD_FLOAT
&& (TARGET_FPRS
|| TARGET_E500_DOUBLE
)))
10544 set_optab_libfunc (neg_optab
, TFmode
, "__gcc_qneg");
10545 set_optab_libfunc (eq_optab
, TFmode
, "__gcc_qeq");
10546 set_optab_libfunc (ne_optab
, TFmode
, "__gcc_qne");
10547 set_optab_libfunc (gt_optab
, TFmode
, "__gcc_qgt");
10548 set_optab_libfunc (ge_optab
, TFmode
, "__gcc_qge");
10549 set_optab_libfunc (lt_optab
, TFmode
, "__gcc_qlt");
10550 set_optab_libfunc (le_optab
, TFmode
, "__gcc_qle");
10552 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "__gcc_stoq");
10553 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "__gcc_dtoq");
10554 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "__gcc_qtos");
10555 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "__gcc_qtod");
10556 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "__gcc_qtoi");
10557 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "__gcc_qtou");
10558 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "__gcc_itoq");
10559 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "__gcc_utoq");
10562 if (!(TARGET_HARD_FLOAT
&& TARGET_FPRS
))
10563 set_optab_libfunc (unord_optab
, TFmode
, "__gcc_qunord");
10567 set_optab_libfunc (add_optab
, TFmode
, "_xlqadd");
10568 set_optab_libfunc (sub_optab
, TFmode
, "_xlqsub");
10569 set_optab_libfunc (smul_optab
, TFmode
, "_xlqmul");
10570 set_optab_libfunc (sdiv_optab
, TFmode
, "_xlqdiv");
10574 /* 32-bit SVR4 quad floating point routines. */
10576 set_optab_libfunc (add_optab
, TFmode
, "_q_add");
10577 set_optab_libfunc (sub_optab
, TFmode
, "_q_sub");
10578 set_optab_libfunc (neg_optab
, TFmode
, "_q_neg");
10579 set_optab_libfunc (smul_optab
, TFmode
, "_q_mul");
10580 set_optab_libfunc (sdiv_optab
, TFmode
, "_q_div");
10581 if (TARGET_PPC_GPOPT
|| TARGET_POWER2
)
10582 set_optab_libfunc (sqrt_optab
, TFmode
, "_q_sqrt");
10584 set_optab_libfunc (eq_optab
, TFmode
, "_q_feq");
10585 set_optab_libfunc (ne_optab
, TFmode
, "_q_fne");
10586 set_optab_libfunc (gt_optab
, TFmode
, "_q_fgt");
10587 set_optab_libfunc (ge_optab
, TFmode
, "_q_fge");
10588 set_optab_libfunc (lt_optab
, TFmode
, "_q_flt");
10589 set_optab_libfunc (le_optab
, TFmode
, "_q_fle");
10591 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_q_stoq");
10592 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_q_dtoq");
10593 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_q_qtos");
10594 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_q_qtod");
10595 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_q_qtoi");
10596 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_q_qtou");
10597 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_q_itoq");
10598 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_q_utoq");
10603 /* Expand a block clear operation, and return 1 if successful. Return 0
10604 if we should let the compiler generate normal code.
10606 operands[0] is the destination
10607 operands[1] is the length
10608 operands[3] is the alignment */
10611 expand_block_clear (rtx operands
[])
10613 rtx orig_dest
= operands
[0];
10614 rtx bytes_rtx
= operands
[1];
10615 rtx align_rtx
= operands
[3];
10616 bool constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
10617 HOST_WIDE_INT align
;
10618 HOST_WIDE_INT bytes
;
10623 /* If this is not a fixed size move, just call memcpy */
10627 /* This must be a fixed size alignment */
10628 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
10629 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
10631 /* Anything to clear? */
10632 bytes
= INTVAL (bytes_rtx
);
10636 /* Use the builtin memset after a point, to avoid huge code bloat.
10637 When optimize_size, avoid any significant code bloat; calling
10638 memset is about 4 instructions, so allow for one instruction to
10639 load zero and three to do clearing. */
10640 if (TARGET_ALTIVEC
&& align
>= 128)
10642 else if (TARGET_POWERPC64
&& align
>= 32)
10644 else if (TARGET_SPE
&& align
>= 64)
10649 if (optimize_size
&& bytes
> 3 * clear_step
)
10651 if (! optimize_size
&& bytes
> 8 * clear_step
)
10654 for (offset
= 0; bytes
> 0; offset
+= clear_bytes
, bytes
-= clear_bytes
)
10656 enum machine_mode mode
= BLKmode
;
10659 if (bytes
>= 16 && TARGET_ALTIVEC
&& align
>= 128)
10664 else if (bytes
>= 8 && TARGET_SPE
&& align
>= 64)
10669 else if (bytes
>= 8 && TARGET_POWERPC64
10670 /* 64-bit loads and stores require word-aligned
10672 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
10677 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
10678 { /* move 4 bytes */
10682 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
10683 { /* move 2 bytes */
10687 else /* move 1 byte at a time */
10693 dest
= adjust_address (orig_dest
, mode
, offset
);
10695 emit_move_insn (dest
, CONST0_RTX (mode
));
10702 /* Expand a block move operation, and return 1 if successful. Return 0
10703 if we should let the compiler generate normal code.
10705 operands[0] is the destination
10706 operands[1] is the source
10707 operands[2] is the length
10708 operands[3] is the alignment */
10710 #define MAX_MOVE_REG 4
10713 expand_block_move (rtx operands
[])
10715 rtx orig_dest
= operands
[0];
10716 rtx orig_src
= operands
[1];
10717 rtx bytes_rtx
= operands
[2];
10718 rtx align_rtx
= operands
[3];
10719 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
10724 rtx stores
[MAX_MOVE_REG
];
10727 /* If this is not a fixed size move, just call memcpy */
10731 /* This must be a fixed size alignment */
10732 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
10733 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
10735 /* Anything to move? */
10736 bytes
= INTVAL (bytes_rtx
);
10740 /* store_one_arg depends on expand_block_move to handle at least the size of
10741 reg_parm_stack_space. */
10742 if (bytes
> (TARGET_POWERPC64
? 64 : 32))
10745 for (offset
= 0; bytes
> 0; offset
+= move_bytes
, bytes
-= move_bytes
)
10748 rtx (*movmemsi
) (rtx
, rtx
, rtx
, rtx
);
10749 rtx (*mov
) (rtx
, rtx
);
10751 enum machine_mode mode
= BLKmode
;
10754 /* Altivec first, since it will be faster than a string move
10755 when it applies, and usually not significantly larger. */
10756 if (TARGET_ALTIVEC
&& bytes
>= 16 && align
>= 128)
10760 gen_func
.mov
= gen_movv4si
;
10762 else if (TARGET_SPE
&& bytes
>= 8 && align
>= 64)
10766 gen_func
.mov
= gen_movv2si
;
10768 else if (TARGET_STRING
10769 && bytes
> 24 /* move up to 32 bytes at a time */
10775 && ! fixed_regs
[10]
10776 && ! fixed_regs
[11]
10777 && ! fixed_regs
[12])
10779 move_bytes
= (bytes
> 32) ? 32 : bytes
;
10780 gen_func
.movmemsi
= gen_movmemsi_8reg
;
10782 else if (TARGET_STRING
10783 && bytes
> 16 /* move up to 24 bytes at a time */
10789 && ! fixed_regs
[10])
10791 move_bytes
= (bytes
> 24) ? 24 : bytes
;
10792 gen_func
.movmemsi
= gen_movmemsi_6reg
;
10794 else if (TARGET_STRING
10795 && bytes
> 8 /* move up to 16 bytes at a time */
10799 && ! fixed_regs
[8])
10801 move_bytes
= (bytes
> 16) ? 16 : bytes
;
10802 gen_func
.movmemsi
= gen_movmemsi_4reg
;
10804 else if (bytes
>= 8 && TARGET_POWERPC64
10805 /* 64-bit loads and stores require word-aligned
10807 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
10811 gen_func
.mov
= gen_movdi
;
10813 else if (TARGET_STRING
&& bytes
> 4 && !TARGET_POWERPC64
)
10814 { /* move up to 8 bytes at a time */
10815 move_bytes
= (bytes
> 8) ? 8 : bytes
;
10816 gen_func
.movmemsi
= gen_movmemsi_2reg
;
10818 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
10819 { /* move 4 bytes */
10822 gen_func
.mov
= gen_movsi
;
10824 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
10825 { /* move 2 bytes */
10828 gen_func
.mov
= gen_movhi
;
10830 else if (TARGET_STRING
&& bytes
> 1)
10831 { /* move up to 4 bytes at a time */
10832 move_bytes
= (bytes
> 4) ? 4 : bytes
;
10833 gen_func
.movmemsi
= gen_movmemsi_1reg
;
10835 else /* move 1 byte at a time */
10839 gen_func
.mov
= gen_movqi
;
10842 src
= adjust_address (orig_src
, mode
, offset
);
10843 dest
= adjust_address (orig_dest
, mode
, offset
);
10845 if (mode
!= BLKmode
)
10847 rtx tmp_reg
= gen_reg_rtx (mode
);
10849 emit_insn ((*gen_func
.mov
) (tmp_reg
, src
));
10850 stores
[num_reg
++] = (*gen_func
.mov
) (dest
, tmp_reg
);
10853 if (mode
== BLKmode
|| num_reg
>= MAX_MOVE_REG
|| bytes
== move_bytes
)
10856 for (i
= 0; i
< num_reg
; i
++)
10857 emit_insn (stores
[i
]);
10861 if (mode
== BLKmode
)
10863 /* Move the address into scratch registers. The movmemsi
10864 patterns require zero offset. */
10865 if (!REG_P (XEXP (src
, 0)))
10867 rtx src_reg
= copy_addr_to_reg (XEXP (src
, 0));
10868 src
= replace_equiv_address (src
, src_reg
);
10870 set_mem_size (src
, GEN_INT (move_bytes
));
10872 if (!REG_P (XEXP (dest
, 0)))
10874 rtx dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
10875 dest
= replace_equiv_address (dest
, dest_reg
);
10877 set_mem_size (dest
, GEN_INT (move_bytes
));
10879 emit_insn ((*gen_func
.movmemsi
) (dest
, src
,
10880 GEN_INT (move_bytes
& 31),
10889 /* Return a string to perform a load_multiple operation.
10890 operands[0] is the vector.
10891 operands[1] is the source address.
10892 operands[2] is the first destination register. */
10895 rs6000_output_load_multiple (rtx operands
[3])
10897 /* We have to handle the case where the pseudo used to contain the address
10898 is assigned to one of the output registers. */
10900 int words
= XVECLEN (operands
[0], 0);
10903 if (XVECLEN (operands
[0], 0) == 1)
10904 return "{l|lwz} %2,0(%1)";
10906 for (i
= 0; i
< words
; i
++)
10907 if (refers_to_regno_p (REGNO (operands
[2]) + i
,
10908 REGNO (operands
[2]) + i
+ 1, operands
[1], 0))
10912 xop
[0] = GEN_INT (4 * (words
-1));
10913 xop
[1] = operands
[1];
10914 xop
[2] = operands
[2];
10915 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop
);
10920 xop
[0] = GEN_INT (4 * (words
-1));
10921 xop
[1] = operands
[1];
10922 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
10923 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop
);
10928 for (j
= 0; j
< words
; j
++)
10931 xop
[0] = GEN_INT (j
* 4);
10932 xop
[1] = operands
[1];
10933 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + j
);
10934 output_asm_insn ("{l|lwz} %2,%0(%1)", xop
);
10936 xop
[0] = GEN_INT (i
* 4);
10937 xop
[1] = operands
[1];
10938 output_asm_insn ("{l|lwz} %1,%0(%1)", xop
);
10943 return "{lsi|lswi} %2,%1,%N0";
10947 /* A validation routine: say whether CODE, a condition code, and MODE
10948 match. The other alternatives either don't make sense or should
10949 never be generated. */
10952 validate_condition_mode (enum rtx_code code
, enum machine_mode mode
)
10954 gcc_assert ((GET_RTX_CLASS (code
) == RTX_COMPARE
10955 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
10956 && GET_MODE_CLASS (mode
) == MODE_CC
);
10958 /* These don't make sense. */
10959 gcc_assert ((code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
)
10960 || mode
!= CCUNSmode
);
10962 gcc_assert ((code
!= GTU
&& code
!= LTU
&& code
!= GEU
&& code
!= LEU
)
10963 || mode
== CCUNSmode
);
10965 gcc_assert (mode
== CCFPmode
10966 || (code
!= ORDERED
&& code
!= UNORDERED
10967 && code
!= UNEQ
&& code
!= LTGT
10968 && code
!= UNGT
&& code
!= UNLT
10969 && code
!= UNGE
&& code
!= UNLE
));
10971 /* These should never be generated except for
10972 flag_finite_math_only. */
10973 gcc_assert (mode
!= CCFPmode
10974 || flag_finite_math_only
10975 || (code
!= LE
&& code
!= GE
10976 && code
!= UNEQ
&& code
!= LTGT
10977 && code
!= UNGT
&& code
!= UNLT
));
10979 /* These are invalid; the information is not there. */
10980 gcc_assert (mode
!= CCEQmode
|| code
== EQ
|| code
== NE
);
10984 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
10985 mask required to convert the result of a rotate insn into a shift
10986 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
10989 includes_lshift_p (rtx shiftop
, rtx andop
)
10991 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
10993 shift_mask
<<= INTVAL (shiftop
);
10995 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
10998 /* Similar, but for right shift. */
11001 includes_rshift_p (rtx shiftop
, rtx andop
)
11003 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
11005 shift_mask
>>= INTVAL (shiftop
);
11007 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
11010 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
11011 to perform a left shift. It must have exactly SHIFTOP least
11012 significant 0's, then one or more 1's, then zero or more 0's. */
11015 includes_rldic_lshift_p (rtx shiftop
, rtx andop
)
11017 if (GET_CODE (andop
) == CONST_INT
)
11019 HOST_WIDE_INT c
, lsb
, shift_mask
;
11021 c
= INTVAL (andop
);
11022 if (c
== 0 || c
== ~0)
11026 shift_mask
<<= INTVAL (shiftop
);
11028 /* Find the least significant one bit. */
11031 /* It must coincide with the LSB of the shift mask. */
11032 if (-lsb
!= shift_mask
)
11035 /* Invert to look for the next transition (if any). */
11038 /* Remove the low group of ones (originally low group of zeros). */
11041 /* Again find the lsb, and check we have all 1's above. */
11045 else if (GET_CODE (andop
) == CONST_DOUBLE
11046 && (GET_MODE (andop
) == VOIDmode
|| GET_MODE (andop
) == DImode
))
11048 HOST_WIDE_INT low
, high
, lsb
;
11049 HOST_WIDE_INT shift_mask_low
, shift_mask_high
;
11051 low
= CONST_DOUBLE_LOW (andop
);
11052 if (HOST_BITS_PER_WIDE_INT
< 64)
11053 high
= CONST_DOUBLE_HIGH (andop
);
11055 if ((low
== 0 && (HOST_BITS_PER_WIDE_INT
>= 64 || high
== 0))
11056 || (low
== ~0 && (HOST_BITS_PER_WIDE_INT
>= 64 || high
== ~0)))
11059 if (HOST_BITS_PER_WIDE_INT
< 64 && low
== 0)
11061 shift_mask_high
= ~0;
11062 if (INTVAL (shiftop
) > 32)
11063 shift_mask_high
<<= INTVAL (shiftop
) - 32;
11065 lsb
= high
& -high
;
11067 if (-lsb
!= shift_mask_high
|| INTVAL (shiftop
) < 32)
11073 lsb
= high
& -high
;
11074 return high
== -lsb
;
11077 shift_mask_low
= ~0;
11078 shift_mask_low
<<= INTVAL (shiftop
);
11082 if (-lsb
!= shift_mask_low
)
11085 if (HOST_BITS_PER_WIDE_INT
< 64)
11090 if (HOST_BITS_PER_WIDE_INT
< 64 && low
== 0)
11092 lsb
= high
& -high
;
11093 return high
== -lsb
;
11097 return low
== -lsb
&& (HOST_BITS_PER_WIDE_INT
>= 64 || high
== ~0);
11103 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
11104 to perform a left shift. It must have SHIFTOP or more least
11105 significant 0's, with the remainder of the word 1's. */
11108 includes_rldicr_lshift_p (rtx shiftop
, rtx andop
)
11110 if (GET_CODE (andop
) == CONST_INT
)
11112 HOST_WIDE_INT c
, lsb
, shift_mask
;
11115 shift_mask
<<= INTVAL (shiftop
);
11116 c
= INTVAL (andop
);
11118 /* Find the least significant one bit. */
11121 /* It must be covered by the shift mask.
11122 This test also rejects c == 0. */
11123 if ((lsb
& shift_mask
) == 0)
11126 /* Check we have all 1's above the transition, and reject all 1's. */
11127 return c
== -lsb
&& lsb
!= 1;
11129 else if (GET_CODE (andop
) == CONST_DOUBLE
11130 && (GET_MODE (andop
) == VOIDmode
|| GET_MODE (andop
) == DImode
))
11132 HOST_WIDE_INT low
, lsb
, shift_mask_low
;
11134 low
= CONST_DOUBLE_LOW (andop
);
11136 if (HOST_BITS_PER_WIDE_INT
< 64)
11138 HOST_WIDE_INT high
, shift_mask_high
;
11140 high
= CONST_DOUBLE_HIGH (andop
);
11144 shift_mask_high
= ~0;
11145 if (INTVAL (shiftop
) > 32)
11146 shift_mask_high
<<= INTVAL (shiftop
) - 32;
11148 lsb
= high
& -high
;
11150 if ((lsb
& shift_mask_high
) == 0)
11153 return high
== -lsb
;
11159 shift_mask_low
= ~0;
11160 shift_mask_low
<<= INTVAL (shiftop
);
11164 if ((lsb
& shift_mask_low
) == 0)
11167 return low
== -lsb
&& lsb
!= 1;
11173 /* Return 1 if operands will generate a valid arguments to rlwimi
11174 instruction for insert with right shift in 64-bit mode. The mask may
11175 not start on the first bit or stop on the last bit because wrap-around
11176 effects of instruction do not correspond to semantics of RTL insn. */
11179 insvdi_rshift_rlwimi_p (rtx sizeop
, rtx startop
, rtx shiftop
)
11181 if (INTVAL (startop
) > 32
11182 && INTVAL (startop
) < 64
11183 && INTVAL (sizeop
) > 1
11184 && INTVAL (sizeop
) + INTVAL (startop
) < 64
11185 && INTVAL (shiftop
) > 0
11186 && INTVAL (sizeop
) + INTVAL (shiftop
) < 32
11187 && (64 - (INTVAL (shiftop
) & 63)) >= INTVAL (sizeop
))
11193 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
11194 for lfq and stfq insns iff the registers are hard registers. */
11197 registers_ok_for_quad_peep (rtx reg1
, rtx reg2
)
11199 /* We might have been passed a SUBREG. */
11200 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
11203 /* We might have been passed non floating point registers. */
11204 if (!FP_REGNO_P (REGNO (reg1
))
11205 || !FP_REGNO_P (REGNO (reg2
)))
11208 return (REGNO (reg1
) == REGNO (reg2
) - 1);
11211 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
11212 addr1 and addr2 must be in consecutive memory locations
11213 (addr2 == addr1 + 8). */
11216 mems_ok_for_quad_peep (rtx mem1
, rtx mem2
)
11219 unsigned int reg1
, reg2
;
11220 int offset1
, offset2
;
11222 /* The mems cannot be volatile. */
11223 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
11226 addr1
= XEXP (mem1
, 0);
11227 addr2
= XEXP (mem2
, 0);
11229 /* Extract an offset (if used) from the first addr. */
11230 if (GET_CODE (addr1
) == PLUS
)
11232 /* If not a REG, return zero. */
11233 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
11237 reg1
= REGNO (XEXP (addr1
, 0));
11238 /* The offset must be constant! */
11239 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
11241 offset1
= INTVAL (XEXP (addr1
, 1));
11244 else if (GET_CODE (addr1
) != REG
)
11248 reg1
= REGNO (addr1
);
11249 /* This was a simple (mem (reg)) expression. Offset is 0. */
11253 /* And now for the second addr. */
11254 if (GET_CODE (addr2
) == PLUS
)
11256 /* If not a REG, return zero. */
11257 if (GET_CODE (XEXP (addr2
, 0)) != REG
)
11261 reg2
= REGNO (XEXP (addr2
, 0));
11262 /* The offset must be constant. */
11263 if (GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
11265 offset2
= INTVAL (XEXP (addr2
, 1));
11268 else if (GET_CODE (addr2
) != REG
)
11272 reg2
= REGNO (addr2
);
11273 /* This was a simple (mem (reg)) expression. Offset is 0. */
11277 /* Both of these must have the same base register. */
11281 /* The offset for the second addr must be 8 more than the first addr. */
11282 if (offset2
!= offset1
+ 8)
11285 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
11292 rs6000_secondary_memory_needed_rtx (enum machine_mode mode
)
11294 static bool eliminated
= false;
11295 if (mode
!= SDmode
)
11296 return assign_stack_local (mode
, GET_MODE_SIZE (mode
), 0);
11299 rtx mem
= cfun
->machine
->sdmode_stack_slot
;
11300 gcc_assert (mem
!= NULL_RTX
);
11304 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
11305 cfun
->machine
->sdmode_stack_slot
= mem
;
11313 rs6000_check_sdmode (tree
*tp
, int *walk_subtrees
, void *data ATTRIBUTE_UNUSED
)
11315 /* Don't walk into types. */
11316 if (*tp
== NULL_TREE
|| *tp
== error_mark_node
|| TYPE_P (*tp
))
11318 *walk_subtrees
= 0;
11322 switch (TREE_CODE (*tp
))
11330 case ALIGN_INDIRECT_REF
:
11331 case MISALIGNED_INDIRECT_REF
:
11332 case VIEW_CONVERT_EXPR
:
11333 if (TYPE_MODE (TREE_TYPE (*tp
)) == SDmode
)
11344 /* Allocate a 64-bit stack slot to be used for copying SDmode
11345 values through if this function has any SDmode references. */
11348 rs6000_alloc_sdmode_stack_slot (void)
11352 gimple_stmt_iterator gsi
;
11354 gcc_assert (cfun
->machine
->sdmode_stack_slot
== NULL_RTX
);
11357 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
11359 tree ret
= walk_gimple_op (gsi_stmt (gsi
), rs6000_check_sdmode
, NULL
);
11362 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
11363 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
11369 /* Check for any SDmode parameters of the function. */
11370 for (t
= DECL_ARGUMENTS (cfun
->decl
); t
; t
= TREE_CHAIN (t
))
11372 if (TREE_TYPE (t
) == error_mark_node
)
11375 if (TYPE_MODE (TREE_TYPE (t
)) == SDmode
11376 || TYPE_MODE (DECL_ARG_TYPE (t
)) == SDmode
)
11378 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
11379 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
11387 rs6000_instantiate_decls (void)
11389 if (cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
11390 instantiate_decl_rtl (cfun
->machine
->sdmode_stack_slot
);
11393 /* Return the register class of a scratch register needed to copy IN into
11394 or out of a register in RCLASS in MODE. If it can be done directly,
11395 NO_REGS is returned. */
11398 rs6000_secondary_reload_class (enum reg_class rclass
,
11399 enum machine_mode mode ATTRIBUTE_UNUSED
,
11404 if (TARGET_ELF
|| (DEFAULT_ABI
== ABI_DARWIN
11406 && MACHOPIC_INDIRECT
11410 /* We cannot copy a symbolic operand directly into anything
11411 other than BASE_REGS for TARGET_ELF. So indicate that a
11412 register from BASE_REGS is needed as an intermediate
11415 On Darwin, pic addresses require a load from memory, which
11416 needs a base register. */
11417 if (rclass
!= BASE_REGS
11418 && (GET_CODE (in
) == SYMBOL_REF
11419 || GET_CODE (in
) == HIGH
11420 || GET_CODE (in
) == LABEL_REF
11421 || GET_CODE (in
) == CONST
))
11425 if (GET_CODE (in
) == REG
)
11427 regno
= REGNO (in
);
11428 if (regno
>= FIRST_PSEUDO_REGISTER
)
11430 regno
= true_regnum (in
);
11431 if (regno
>= FIRST_PSEUDO_REGISTER
)
11435 else if (GET_CODE (in
) == SUBREG
)
11437 regno
= true_regnum (in
);
11438 if (regno
>= FIRST_PSEUDO_REGISTER
)
11444 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
11446 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
11447 || (regno
>= 0 && INT_REGNO_P (regno
)))
11450 /* Constants, memory, and FP registers can go into FP registers. */
11451 if ((regno
== -1 || FP_REGNO_P (regno
))
11452 && (rclass
== FLOAT_REGS
|| rclass
== NON_SPECIAL_REGS
))
11453 return (mode
!= SDmode
) ? NO_REGS
: GENERAL_REGS
;
11455 /* Memory, and AltiVec registers can go into AltiVec registers. */
11456 if ((regno
== -1 || ALTIVEC_REGNO_P (regno
))
11457 && rclass
== ALTIVEC_REGS
)
11460 /* We can copy among the CR registers. */
11461 if ((rclass
== CR_REGS
|| rclass
== CR0_REGS
)
11462 && regno
>= 0 && CR_REGNO_P (regno
))
11465 /* Otherwise, we need GENERAL_REGS. */
11466 return GENERAL_REGS
;
11469 /* Given a comparison operation, return the bit number in CCR to test. We
11470 know this is a valid comparison.
11472 SCC_P is 1 if this is for an scc. That means that %D will have been
11473 used instead of %C, so the bits will be in different places.
11475 Return -1 if OP isn't a valid comparison for some reason. */
11478 ccr_bit (rtx op
, int scc_p
)
11480 enum rtx_code code
= GET_CODE (op
);
11481 enum machine_mode cc_mode
;
11486 if (!COMPARISON_P (op
))
11489 reg
= XEXP (op
, 0);
11491 gcc_assert (GET_CODE (reg
) == REG
&& CR_REGNO_P (REGNO (reg
)));
11493 cc_mode
= GET_MODE (reg
);
11494 cc_regnum
= REGNO (reg
);
11495 base_bit
= 4 * (cc_regnum
- CR0_REGNO
);
11497 validate_condition_mode (code
, cc_mode
);
11499 /* When generating a sCOND operation, only positive conditions are
11502 || code
== EQ
|| code
== GT
|| code
== LT
|| code
== UNORDERED
11503 || code
== GTU
|| code
== LTU
);
11508 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
11510 return base_bit
+ 2;
11511 case GT
: case GTU
: case UNLE
:
11512 return base_bit
+ 1;
11513 case LT
: case LTU
: case UNGE
:
11515 case ORDERED
: case UNORDERED
:
11516 return base_bit
+ 3;
11519 /* If scc, we will have done a cror to put the bit in the
11520 unordered position. So test that bit. For integer, this is ! LT
11521 unless this is an scc insn. */
11522 return scc_p
? base_bit
+ 3 : base_bit
;
11525 return scc_p
? base_bit
+ 3 : base_bit
+ 1;
11528 gcc_unreachable ();
11532 /* Return the GOT register. */
11535 rs6000_got_register (rtx value ATTRIBUTE_UNUSED
)
11537 /* The second flow pass currently (June 1999) can't update
11538 regs_ever_live without disturbing other parts of the compiler, so
11539 update it here to make the prolog/epilogue code happy. */
11540 if (!can_create_pseudo_p ()
11541 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
11542 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM
, true);
11544 crtl
->uses_pic_offset_table
= 1;
11546 return pic_offset_table_rtx
;
11549 /* Function to init struct machine_function.
11550 This will be called, via a pointer variable,
11551 from push_function_context. */
11553 static struct machine_function
*
11554 rs6000_init_machine_status (void)
11556 return GGC_CNEW (machine_function
);
11559 /* These macros test for integers and extract the low-order bits. */
11561 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
11562 && GET_MODE (X) == VOIDmode)
11564 #define INT_LOWPART(X) \
11565 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
11568 extract_MB (rtx op
)
11571 unsigned long val
= INT_LOWPART (op
);
11573 /* If the high bit is zero, the value is the first 1 bit we find
11575 if ((val
& 0x80000000) == 0)
11577 gcc_assert (val
& 0xffffffff);
11580 while (((val
<<= 1) & 0x80000000) == 0)
11585 /* If the high bit is set and the low bit is not, or the mask is all
11586 1's, the value is zero. */
11587 if ((val
& 1) == 0 || (val
& 0xffffffff) == 0xffffffff)
11590 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
11593 while (((val
>>= 1) & 1) != 0)
11600 extract_ME (rtx op
)
11603 unsigned long val
= INT_LOWPART (op
);
11605 /* If the low bit is zero, the value is the first 1 bit we find from
11607 if ((val
& 1) == 0)
11609 gcc_assert (val
& 0xffffffff);
11612 while (((val
>>= 1) & 1) == 0)
11618 /* If the low bit is set and the high bit is not, or the mask is all
11619 1's, the value is 31. */
11620 if ((val
& 0x80000000) == 0 || (val
& 0xffffffff) == 0xffffffff)
11623 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
11626 while (((val
<<= 1) & 0x80000000) != 0)
11632 /* Locate some local-dynamic symbol still in use by this function
11633 so that we can print its name in some tls_ld pattern. */
11635 static const char *
11636 rs6000_get_some_local_dynamic_name (void)
11640 if (cfun
->machine
->some_ld_name
)
11641 return cfun
->machine
->some_ld_name
;
11643 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
11645 && for_each_rtx (&PATTERN (insn
),
11646 rs6000_get_some_local_dynamic_name_1
, 0))
11647 return cfun
->machine
->some_ld_name
;
11649 gcc_unreachable ();
11652 /* Helper function for rs6000_get_some_local_dynamic_name. */
11655 rs6000_get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
11659 if (GET_CODE (x
) == SYMBOL_REF
)
11661 const char *str
= XSTR (x
, 0);
11662 if (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
11664 cfun
->machine
->some_ld_name
= str
;
11672 /* Write out a function code label. */
11675 rs6000_output_function_entry (FILE *file
, const char *fname
)
11677 if (fname
[0] != '.')
11679 switch (DEFAULT_ABI
)
11682 gcc_unreachable ();
11688 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "L.");
11697 RS6000_OUTPUT_BASENAME (file
, fname
);
11699 assemble_name (file
, fname
);
11702 /* Print an operand. Recognize special options, documented below. */
11705 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
11706 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
11708 #define SMALL_DATA_RELOC "sda21"
11709 #define SMALL_DATA_REG 0
11713 print_operand (FILE *file
, rtx x
, int code
)
11717 unsigned HOST_WIDE_INT uval
;
11722 /* Write out an instruction after the call which may be replaced
11723 with glue code by the loader. This depends on the AIX version. */
11724 asm_fprintf (file
, RS6000_CALL_GLUE
);
11727 /* %a is output_address. */
11730 /* If X is a constant integer whose low-order 5 bits are zero,
11731 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
11732 in the AIX assembler where "sri" with a zero shift count
11733 writes a trash instruction. */
11734 if (GET_CODE (x
) == CONST_INT
&& (INTVAL (x
) & 31) == 0)
11741 /* If constant, low-order 16 bits of constant, unsigned.
11742 Otherwise, write normally. */
11744 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 0xffff);
11746 print_operand (file
, x
, 0);
11750 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
11751 for 64-bit mask direction. */
11752 putc (((INT_LOWPART (x
) & 1) == 0 ? 'r' : 'l'), file
);
11755 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
11759 /* X is a CR register. Print the number of the GT bit of the CR. */
11760 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
11761 output_operand_lossage ("invalid %%E value");
11763 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 1);
11767 /* Like 'J' but get to the GT bit only. */
11768 gcc_assert (GET_CODE (x
) == REG
);
11770 /* Bit 1 is GT bit. */
11771 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 1;
11773 /* Add one for shift count in rlinm for scc. */
11774 fprintf (file
, "%d", i
+ 1);
11778 /* X is a CR register. Print the number of the EQ bit of the CR */
11779 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
11780 output_operand_lossage ("invalid %%E value");
11782 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 2);
11786 /* X is a CR register. Print the shift count needed to move it
11787 to the high-order four bits. */
11788 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
11789 output_operand_lossage ("invalid %%f value");
11791 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
));
11795 /* Similar, but print the count for the rotate in the opposite
11797 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
11798 output_operand_lossage ("invalid %%F value");
11800 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - CR0_REGNO
));
11804 /* X is a constant integer. If it is negative, print "m",
11805 otherwise print "z". This is to make an aze or ame insn. */
11806 if (GET_CODE (x
) != CONST_INT
)
11807 output_operand_lossage ("invalid %%G value");
11808 else if (INTVAL (x
) >= 0)
11815 /* If constant, output low-order five bits. Otherwise, write
11818 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 31);
11820 print_operand (file
, x
, 0);
11824 /* If constant, output low-order six bits. Otherwise, write
11827 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 63);
11829 print_operand (file
, x
, 0);
11833 /* Print `i' if this is a constant, else nothing. */
11839 /* Write the bit number in CCR for jump. */
11840 i
= ccr_bit (x
, 0);
11842 output_operand_lossage ("invalid %%j code");
11844 fprintf (file
, "%d", i
);
11848 /* Similar, but add one for shift count in rlinm for scc and pass
11849 scc flag to `ccr_bit'. */
11850 i
= ccr_bit (x
, 1);
11852 output_operand_lossage ("invalid %%J code");
11854 /* If we want bit 31, write a shift count of zero, not 32. */
11855 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
11859 /* X must be a constant. Write the 1's complement of the
11862 output_operand_lossage ("invalid %%k value");
11864 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INT_LOWPART (x
));
11868 /* X must be a symbolic constant on ELF. Write an
11869 expression suitable for an 'addi' that adds in the low 16
11870 bits of the MEM. */
11871 if (GET_CODE (x
) != CONST
)
11873 print_operand_address (file
, x
);
11874 fputs ("@l", file
);
11878 if (GET_CODE (XEXP (x
, 0)) != PLUS
11879 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
11880 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
11881 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
11882 output_operand_lossage ("invalid %%K value");
11883 print_operand_address (file
, XEXP (XEXP (x
, 0), 0));
11884 fputs ("@l", file
);
11885 /* For GNU as, there must be a non-alphanumeric character
11886 between 'l' and the number. The '-' is added by
11887 print_operand() already. */
11888 if (INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0)
11890 print_operand (file
, XEXP (XEXP (x
, 0), 1), 0);
11894 /* %l is output_asm_label. */
11897 /* Write second word of DImode or DFmode reference. Works on register
11898 or non-indexed memory only. */
11899 if (GET_CODE (x
) == REG
)
11900 fputs (reg_names
[REGNO (x
) + 1], file
);
11901 else if (GET_CODE (x
) == MEM
)
11903 /* Handle possible auto-increment. Since it is pre-increment and
11904 we have already done it, we can just use an offset of word. */
11905 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
11906 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
11907 output_address (plus_constant (XEXP (XEXP (x
, 0), 0),
11909 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
11910 output_address (plus_constant (XEXP (XEXP (x
, 0), 0),
11913 output_address (XEXP (adjust_address_nv (x
, SImode
,
11917 if (small_data_operand (x
, GET_MODE (x
)))
11918 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
11919 reg_names
[SMALL_DATA_REG
]);
11924 /* MB value for a mask operand. */
11925 if (! mask_operand (x
, SImode
))
11926 output_operand_lossage ("invalid %%m value");
11928 fprintf (file
, "%d", extract_MB (x
));
11932 /* ME value for a mask operand. */
11933 if (! mask_operand (x
, SImode
))
11934 output_operand_lossage ("invalid %%M value");
11936 fprintf (file
, "%d", extract_ME (x
));
11939 /* %n outputs the negative of its operand. */
11942 /* Write the number of elements in the vector times 4. */
11943 if (GET_CODE (x
) != PARALLEL
)
11944 output_operand_lossage ("invalid %%N value");
11946 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
11950 /* Similar, but subtract 1 first. */
11951 if (GET_CODE (x
) != PARALLEL
)
11952 output_operand_lossage ("invalid %%O value");
11954 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
11958 /* X is a CONST_INT that is a power of two. Output the logarithm. */
11960 || INT_LOWPART (x
) < 0
11961 || (i
= exact_log2 (INT_LOWPART (x
))) < 0)
11962 output_operand_lossage ("invalid %%p value");
11964 fprintf (file
, "%d", i
);
11968 /* The operand must be an indirect memory reference. The result
11969 is the register name. */
11970 if (GET_CODE (x
) != MEM
|| GET_CODE (XEXP (x
, 0)) != REG
11971 || REGNO (XEXP (x
, 0)) >= 32)
11972 output_operand_lossage ("invalid %%P value");
11974 fputs (reg_names
[REGNO (XEXP (x
, 0))], file
);
11978 /* This outputs the logical code corresponding to a boolean
11979 expression. The expression may have one or both operands
11980 negated (if one, only the first one). For condition register
11981 logical operations, it will also treat the negated
11982 CR codes as NOTs, but not handle NOTs of them. */
11984 const char *const *t
= 0;
11986 enum rtx_code code
= GET_CODE (x
);
11987 static const char * const tbl
[3][3] = {
11988 { "and", "andc", "nor" },
11989 { "or", "orc", "nand" },
11990 { "xor", "eqv", "xor" } };
11994 else if (code
== IOR
)
11996 else if (code
== XOR
)
11999 output_operand_lossage ("invalid %%q value");
12001 if (GET_CODE (XEXP (x
, 0)) != NOT
)
12005 if (GET_CODE (XEXP (x
, 1)) == NOT
)
12023 /* X is a CR register. Print the mask for `mtcrf'. */
12024 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
12025 output_operand_lossage ("invalid %%R value");
12027 fprintf (file
, "%d", 128 >> (REGNO (x
) - CR0_REGNO
));
12031 /* Low 5 bits of 32 - value */
12033 output_operand_lossage ("invalid %%s value");
12035 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (32 - INT_LOWPART (x
)) & 31);
12039 /* PowerPC64 mask position. All 0's is excluded.
12040 CONST_INT 32-bit mask is considered sign-extended so any
12041 transition must occur within the CONST_INT, not on the boundary. */
12042 if (! mask64_operand (x
, DImode
))
12043 output_operand_lossage ("invalid %%S value");
12045 uval
= INT_LOWPART (x
);
12047 if (uval
& 1) /* Clear Left */
12049 #if HOST_BITS_PER_WIDE_INT > 64
12050 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
12054 else /* Clear Right */
12057 #if HOST_BITS_PER_WIDE_INT > 64
12058 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
12064 gcc_assert (i
>= 0);
12065 fprintf (file
, "%d", i
);
12069 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
12070 gcc_assert (GET_CODE (x
) == REG
&& GET_MODE (x
) == CCmode
);
12072 /* Bit 3 is OV bit. */
12073 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 3;
12075 /* If we want bit 31, write a shift count of zero, not 32. */
12076 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
12080 /* Print the symbolic name of a branch target register. */
12081 if (GET_CODE (x
) != REG
|| (REGNO (x
) != LR_REGNO
12082 && REGNO (x
) != CTR_REGNO
))
12083 output_operand_lossage ("invalid %%T value");
12084 else if (REGNO (x
) == LR_REGNO
)
12085 fputs (TARGET_NEW_MNEMONICS
? "lr" : "r", file
);
12087 fputs ("ctr", file
);
12091 /* High-order 16 bits of constant for use in unsigned operand. */
12093 output_operand_lossage ("invalid %%u value");
12095 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
12096 (INT_LOWPART (x
) >> 16) & 0xffff);
12100 /* High-order 16 bits of constant for use in signed operand. */
12102 output_operand_lossage ("invalid %%v value");
12104 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
12105 (INT_LOWPART (x
) >> 16) & 0xffff);
12109 /* Print `u' if this has an auto-increment or auto-decrement. */
12110 if (GET_CODE (x
) == MEM
12111 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
12112 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
12113 || GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
))
12118 /* Print the trap code for this operand. */
12119 switch (GET_CODE (x
))
12122 fputs ("eq", file
); /* 4 */
12125 fputs ("ne", file
); /* 24 */
12128 fputs ("lt", file
); /* 16 */
12131 fputs ("le", file
); /* 20 */
12134 fputs ("gt", file
); /* 8 */
12137 fputs ("ge", file
); /* 12 */
12140 fputs ("llt", file
); /* 2 */
12143 fputs ("lle", file
); /* 6 */
12146 fputs ("lgt", file
); /* 1 */
12149 fputs ("lge", file
); /* 5 */
12152 gcc_unreachable ();
12157 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
12160 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
12161 ((INT_LOWPART (x
) & 0xffff) ^ 0x8000) - 0x8000);
12163 print_operand (file
, x
, 0);
12167 /* MB value for a PowerPC64 rldic operand. */
12168 val
= (GET_CODE (x
) == CONST_INT
12169 ? INTVAL (x
) : CONST_DOUBLE_HIGH (x
));
12174 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
; i
++)
12175 if ((val
<<= 1) < 0)
12178 #if HOST_BITS_PER_WIDE_INT == 32
12179 if (GET_CODE (x
) == CONST_INT
&& i
>= 0)
12180 i
+= 32; /* zero-extend high-part was all 0's */
12181 else if (GET_CODE (x
) == CONST_DOUBLE
&& i
== 32)
12183 val
= CONST_DOUBLE_LOW (x
);
12189 for ( ; i
< 64; i
++)
12190 if ((val
<<= 1) < 0)
12195 fprintf (file
, "%d", i
+ 1);
12199 if (GET_CODE (x
) == MEM
12200 && (legitimate_indexed_address_p (XEXP (x
, 0), 0)
12201 || (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
12202 && legitimate_indexed_address_p (XEXP (XEXP (x
, 0), 1), 0))))
12207 /* Like 'L', for third word of TImode */
12208 if (GET_CODE (x
) == REG
)
12209 fputs (reg_names
[REGNO (x
) + 2], file
);
12210 else if (GET_CODE (x
) == MEM
)
12212 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
12213 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
12214 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 8));
12215 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
12216 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 8));
12218 output_address (XEXP (adjust_address_nv (x
, SImode
, 8), 0));
12219 if (small_data_operand (x
, GET_MODE (x
)))
12220 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
12221 reg_names
[SMALL_DATA_REG
]);
12226 /* X is a SYMBOL_REF. Write out the name preceded by a
12227 period and without any trailing data in brackets. Used for function
12228 names. If we are configured for System V (or the embedded ABI) on
12229 the PowerPC, do not emit the period, since those systems do not use
12230 TOCs and the like. */
12231 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
12233 /* Mark the decl as referenced so that cgraph will output the
12235 if (SYMBOL_REF_DECL (x
))
12236 mark_decl_referenced (SYMBOL_REF_DECL (x
));
12238 /* For macho, check to see if we need a stub. */
12241 const char *name
= XSTR (x
, 0);
12243 if (MACHOPIC_INDIRECT
12244 && machopic_classify_symbol (x
) == MACHOPIC_UNDEFINED_FUNCTION
)
12245 name
= machopic_indirection_name (x
, /*stub_p=*/true);
12247 assemble_name (file
, name
);
12249 else if (!DOT_SYMBOLS
)
12250 assemble_name (file
, XSTR (x
, 0));
12252 rs6000_output_function_entry (file
, XSTR (x
, 0));
12256 /* Like 'L', for last word of TImode. */
12257 if (GET_CODE (x
) == REG
)
12258 fputs (reg_names
[REGNO (x
) + 3], file
);
12259 else if (GET_CODE (x
) == MEM
)
12261 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
12262 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
12263 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 12));
12264 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
12265 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 12));
12267 output_address (XEXP (adjust_address_nv (x
, SImode
, 12), 0));
12268 if (small_data_operand (x
, GET_MODE (x
)))
12269 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
12270 reg_names
[SMALL_DATA_REG
]);
12274 /* Print AltiVec or SPE memory operand. */
12279 gcc_assert (GET_CODE (x
) == MEM
);
12283 /* Ugly hack because %y is overloaded. */
12284 if ((TARGET_SPE
|| TARGET_E500_DOUBLE
)
12285 && (GET_MODE_SIZE (GET_MODE (x
)) == 8
12286 || GET_MODE (x
) == TFmode
12287 || GET_MODE (x
) == TImode
))
12289 /* Handle [reg]. */
12290 if (GET_CODE (tmp
) == REG
)
12292 fprintf (file
, "0(%s)", reg_names
[REGNO (tmp
)]);
12295 /* Handle [reg+UIMM]. */
12296 else if (GET_CODE (tmp
) == PLUS
&&
12297 GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
12301 gcc_assert (GET_CODE (XEXP (tmp
, 0)) == REG
);
12303 x
= INTVAL (XEXP (tmp
, 1));
12304 fprintf (file
, "%d(%s)", x
, reg_names
[REGNO (XEXP (tmp
, 0))]);
12308 /* Fall through. Must be [reg+reg]. */
12311 && GET_CODE (tmp
) == AND
12312 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
12313 && INTVAL (XEXP (tmp
, 1)) == -16)
12314 tmp
= XEXP (tmp
, 0);
12315 if (GET_CODE (tmp
) == REG
)
12316 fprintf (file
, "0,%s", reg_names
[REGNO (tmp
)]);
12319 if (!GET_CODE (tmp
) == PLUS
12320 || !REG_P (XEXP (tmp
, 0))
12321 || !REG_P (XEXP (tmp
, 1)))
12323 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
12327 if (REGNO (XEXP (tmp
, 0)) == 0)
12328 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 1)) ],
12329 reg_names
[ REGNO (XEXP (tmp
, 0)) ]);
12331 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 0)) ],
12332 reg_names
[ REGNO (XEXP (tmp
, 1)) ]);
12338 if (GET_CODE (x
) == REG
)
12339 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
12340 else if (GET_CODE (x
) == MEM
)
12342 /* We need to handle PRE_INC and PRE_DEC here, since we need to
12343 know the width from the mode. */
12344 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
12345 fprintf (file
, "%d(%s)", GET_MODE_SIZE (GET_MODE (x
)),
12346 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
12347 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
12348 fprintf (file
, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x
)),
12349 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
12350 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
12351 output_address (XEXP (XEXP (x
, 0), 1));
12353 output_address (XEXP (x
, 0));
12356 output_addr_const (file
, x
);
12360 assemble_name (file
, rs6000_get_some_local_dynamic_name ());
12364 output_operand_lossage ("invalid %%xn code");
12368 /* Print the address of an operand. */
12371 print_operand_address (FILE *file
, rtx x
)
12373 if (GET_CODE (x
) == REG
)
12374 fprintf (file
, "0(%s)", reg_names
[ REGNO (x
) ]);
12375 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
12376 || GET_CODE (x
) == LABEL_REF
)
12378 output_addr_const (file
, x
);
12379 if (small_data_operand (x
, GET_MODE (x
)))
12380 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
12381 reg_names
[SMALL_DATA_REG
]);
12383 gcc_assert (!TARGET_TOC
);
12385 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == REG
)
12387 gcc_assert (REG_P (XEXP (x
, 0)));
12388 if (REGNO (XEXP (x
, 0)) == 0)
12389 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 1)) ],
12390 reg_names
[ REGNO (XEXP (x
, 0)) ]);
12392 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 0)) ],
12393 reg_names
[ REGNO (XEXP (x
, 1)) ]);
12395 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
12396 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"(%s)",
12397 INTVAL (XEXP (x
, 1)), reg_names
[ REGNO (XEXP (x
, 0)) ]);
12399 else if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == REG
12400 && CONSTANT_P (XEXP (x
, 1)))
12402 output_addr_const (file
, XEXP (x
, 1));
12403 fprintf (file
, "@l(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
12407 else if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == REG
12408 && CONSTANT_P (XEXP (x
, 1)))
12410 fprintf (file
, "lo16(");
12411 output_addr_const (file
, XEXP (x
, 1));
12412 fprintf (file
, ")(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
12415 else if (legitimate_constant_pool_address_p (x
))
12417 if (TARGET_AIX
&& (!TARGET_ELF
|| !TARGET_MINIMAL_TOC
))
12419 rtx contains_minus
= XEXP (x
, 1);
12423 /* Find the (minus (sym) (toc)) buried in X, and temporarily
12424 turn it into (sym) for output_addr_const. */
12425 while (GET_CODE (XEXP (contains_minus
, 0)) != MINUS
)
12426 contains_minus
= XEXP (contains_minus
, 0);
12428 minus
= XEXP (contains_minus
, 0);
12429 symref
= XEXP (minus
, 0);
12430 gcc_assert (GET_CODE (XEXP (minus
, 1)) == SYMBOL_REF
);
12431 XEXP (contains_minus
, 0) = symref
;
12436 name
= XSTR (symref
, 0);
12437 newname
= XALLOCAVEC (char, strlen (name
) + sizeof ("@toc"));
12438 strcpy (newname
, name
);
12439 strcat (newname
, "@toc");
12440 XSTR (symref
, 0) = newname
;
12442 output_addr_const (file
, XEXP (x
, 1));
12444 XSTR (symref
, 0) = name
;
12445 XEXP (contains_minus
, 0) = minus
;
12448 output_addr_const (file
, XEXP (x
, 1));
12450 fprintf (file
, "(%s)", reg_names
[REGNO (XEXP (x
, 0))]);
12453 gcc_unreachable ();
12456 /* Target hook for assembling integer objects. The PowerPC version has
12457 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
12458 is defined. It also needs to handle DI-mode objects on 64-bit
12462 rs6000_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
12464 #ifdef RELOCATABLE_NEEDS_FIXUP
12465 /* Special handling for SI values. */
12466 if (RELOCATABLE_NEEDS_FIXUP
&& size
== 4 && aligned_p
)
12468 static int recurse
= 0;
12470 /* For -mrelocatable, we mark all addresses that need to be fixed up
12471 in the .fixup section. */
12472 if (TARGET_RELOCATABLE
12473 && in_section
!= toc_section
12474 && in_section
!= text_section
12475 && !unlikely_text_section_p (in_section
)
12477 && GET_CODE (x
) != CONST_INT
12478 && GET_CODE (x
) != CONST_DOUBLE
12484 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", fixuplabelno
);
12486 ASM_OUTPUT_LABEL (asm_out_file
, buf
);
12487 fprintf (asm_out_file
, "\t.long\t(");
12488 output_addr_const (asm_out_file
, x
);
12489 fprintf (asm_out_file
, ")@fixup\n");
12490 fprintf (asm_out_file
, "\t.section\t\".fixup\",\"aw\"\n");
12491 ASM_OUTPUT_ALIGN (asm_out_file
, 2);
12492 fprintf (asm_out_file
, "\t.long\t");
12493 assemble_name (asm_out_file
, buf
);
12494 fprintf (asm_out_file
, "\n\t.previous\n");
12498 /* Remove initial .'s to turn a -mcall-aixdesc function
12499 address into the address of the descriptor, not the function
12501 else if (GET_CODE (x
) == SYMBOL_REF
12502 && XSTR (x
, 0)[0] == '.'
12503 && DEFAULT_ABI
== ABI_AIX
)
12505 const char *name
= XSTR (x
, 0);
12506 while (*name
== '.')
12509 fprintf (asm_out_file
, "\t.long\t%s\n", name
);
12513 #endif /* RELOCATABLE_NEEDS_FIXUP */
12514 return default_assemble_integer (x
, size
, aligned_p
);
12517 #ifdef HAVE_GAS_HIDDEN
12518 /* Emit an assembler directive to set symbol visibility for DECL to
12519 VISIBILITY_TYPE. */
12522 rs6000_assemble_visibility (tree decl
, int vis
)
12524 /* Functions need to have their entry point symbol visibility set as
12525 well as their descriptor symbol visibility. */
12526 if (DEFAULT_ABI
== ABI_AIX
12528 && TREE_CODE (decl
) == FUNCTION_DECL
)
12530 static const char * const visibility_types
[] = {
12531 NULL
, "internal", "hidden", "protected"
12534 const char *name
, *type
;
12536 name
= ((* targetm
.strip_name_encoding
)
12537 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
))));
12538 type
= visibility_types
[vis
];
12540 fprintf (asm_out_file
, "\t.%s\t%s\n", type
, name
);
12541 fprintf (asm_out_file
, "\t.%s\t.%s\n", type
, name
);
12544 default_assemble_visibility (decl
, vis
);
12549 rs6000_reverse_condition (enum machine_mode mode
, enum rtx_code code
)
12551 /* Reversal of FP compares takes care -- an ordered compare
12552 becomes an unordered compare and vice versa. */
12553 if (mode
== CCFPmode
12554 && (!flag_finite_math_only
12555 || code
== UNLT
|| code
== UNLE
|| code
== UNGT
|| code
== UNGE
12556 || code
== UNEQ
|| code
== LTGT
))
12557 return reverse_condition_maybe_unordered (code
);
12559 return reverse_condition (code
);
12562 /* Generate a compare for CODE. Return a brand-new rtx that
12563 represents the result of the compare. */
12566 rs6000_generate_compare (enum rtx_code code
)
12568 enum machine_mode comp_mode
;
12569 rtx compare_result
;
12571 if (rs6000_compare_fp_p
)
12572 comp_mode
= CCFPmode
;
12573 else if (code
== GTU
|| code
== LTU
12574 || code
== GEU
|| code
== LEU
)
12575 comp_mode
= CCUNSmode
;
12576 else if ((code
== EQ
|| code
== NE
)
12577 && GET_CODE (rs6000_compare_op0
) == SUBREG
12578 && GET_CODE (rs6000_compare_op1
) == SUBREG
12579 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0
)
12580 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1
))
12581 /* These are unsigned values, perhaps there will be a later
12582 ordering compare that can be shared with this one.
12583 Unfortunately we cannot detect the signedness of the operands
12584 for non-subregs. */
12585 comp_mode
= CCUNSmode
;
12587 comp_mode
= CCmode
;
12589 /* First, the compare. */
12590 compare_result
= gen_reg_rtx (comp_mode
);
12592 /* E500 FP compare instructions on the GPRs. Yuck! */
12593 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
)
12594 && rs6000_compare_fp_p
)
12596 rtx cmp
, or_result
, compare_result2
;
12597 enum machine_mode op_mode
= GET_MODE (rs6000_compare_op0
);
12599 if (op_mode
== VOIDmode
)
12600 op_mode
= GET_MODE (rs6000_compare_op1
);
12602 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
12603 This explains the following mess. */
12607 case EQ
: case UNEQ
: case NE
: case LTGT
:
12611 cmp
= flag_unsafe_math_optimizations
12612 ? gen_tstsfeq_gpr (compare_result
, rs6000_compare_op0
,
12613 rs6000_compare_op1
)
12614 : gen_cmpsfeq_gpr (compare_result
, rs6000_compare_op0
,
12615 rs6000_compare_op1
);
12619 cmp
= flag_unsafe_math_optimizations
12620 ? gen_tstdfeq_gpr (compare_result
, rs6000_compare_op0
,
12621 rs6000_compare_op1
)
12622 : gen_cmpdfeq_gpr (compare_result
, rs6000_compare_op0
,
12623 rs6000_compare_op1
);
12627 cmp
= flag_unsafe_math_optimizations
12628 ? gen_tsttfeq_gpr (compare_result
, rs6000_compare_op0
,
12629 rs6000_compare_op1
)
12630 : gen_cmptfeq_gpr (compare_result
, rs6000_compare_op0
,
12631 rs6000_compare_op1
);
12635 gcc_unreachable ();
12639 case GT
: case GTU
: case UNGT
: case UNGE
: case GE
: case GEU
:
12643 cmp
= flag_unsafe_math_optimizations
12644 ? gen_tstsfgt_gpr (compare_result
, rs6000_compare_op0
,
12645 rs6000_compare_op1
)
12646 : gen_cmpsfgt_gpr (compare_result
, rs6000_compare_op0
,
12647 rs6000_compare_op1
);
12651 cmp
= flag_unsafe_math_optimizations
12652 ? gen_tstdfgt_gpr (compare_result
, rs6000_compare_op0
,
12653 rs6000_compare_op1
)
12654 : gen_cmpdfgt_gpr (compare_result
, rs6000_compare_op0
,
12655 rs6000_compare_op1
);
12659 cmp
= flag_unsafe_math_optimizations
12660 ? gen_tsttfgt_gpr (compare_result
, rs6000_compare_op0
,
12661 rs6000_compare_op1
)
12662 : gen_cmptfgt_gpr (compare_result
, rs6000_compare_op0
,
12663 rs6000_compare_op1
);
12667 gcc_unreachable ();
12671 case LT
: case LTU
: case UNLT
: case UNLE
: case LE
: case LEU
:
12675 cmp
= flag_unsafe_math_optimizations
12676 ? gen_tstsflt_gpr (compare_result
, rs6000_compare_op0
,
12677 rs6000_compare_op1
)
12678 : gen_cmpsflt_gpr (compare_result
, rs6000_compare_op0
,
12679 rs6000_compare_op1
);
12683 cmp
= flag_unsafe_math_optimizations
12684 ? gen_tstdflt_gpr (compare_result
, rs6000_compare_op0
,
12685 rs6000_compare_op1
)
12686 : gen_cmpdflt_gpr (compare_result
, rs6000_compare_op0
,
12687 rs6000_compare_op1
);
12691 cmp
= flag_unsafe_math_optimizations
12692 ? gen_tsttflt_gpr (compare_result
, rs6000_compare_op0
,
12693 rs6000_compare_op1
)
12694 : gen_cmptflt_gpr (compare_result
, rs6000_compare_op0
,
12695 rs6000_compare_op1
);
12699 gcc_unreachable ();
12703 gcc_unreachable ();
12706 /* Synthesize LE and GE from LT/GT || EQ. */
12707 if (code
== LE
|| code
== GE
|| code
== LEU
|| code
== GEU
)
12713 case LE
: code
= LT
; break;
12714 case GE
: code
= GT
; break;
12715 case LEU
: code
= LT
; break;
12716 case GEU
: code
= GT
; break;
12717 default: gcc_unreachable ();
12720 compare_result2
= gen_reg_rtx (CCFPmode
);
12726 cmp
= flag_unsafe_math_optimizations
12727 ? gen_tstsfeq_gpr (compare_result2
, rs6000_compare_op0
,
12728 rs6000_compare_op1
)
12729 : gen_cmpsfeq_gpr (compare_result2
, rs6000_compare_op0
,
12730 rs6000_compare_op1
);
12734 cmp
= flag_unsafe_math_optimizations
12735 ? gen_tstdfeq_gpr (compare_result2
, rs6000_compare_op0
,
12736 rs6000_compare_op1
)
12737 : gen_cmpdfeq_gpr (compare_result2
, rs6000_compare_op0
,
12738 rs6000_compare_op1
);
12742 cmp
= flag_unsafe_math_optimizations
12743 ? gen_tsttfeq_gpr (compare_result2
, rs6000_compare_op0
,
12744 rs6000_compare_op1
)
12745 : gen_cmptfeq_gpr (compare_result2
, rs6000_compare_op0
,
12746 rs6000_compare_op1
);
12750 gcc_unreachable ();
12754 /* OR them together. */
12755 or_result
= gen_reg_rtx (CCFPmode
);
12756 cmp
= gen_e500_cr_ior_compare (or_result
, compare_result
,
12758 compare_result
= or_result
;
12763 if (code
== NE
|| code
== LTGT
)
12773 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
12774 CLOBBERs to match cmptf_internal2 pattern. */
12775 if (comp_mode
== CCFPmode
&& TARGET_XL_COMPAT
12776 && GET_MODE (rs6000_compare_op0
) == TFmode
12777 && !TARGET_IEEEQUAD
12778 && TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_LONG_DOUBLE_128
)
12779 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
12781 gen_rtx_SET (VOIDmode
,
12783 gen_rtx_COMPARE (comp_mode
,
12784 rs6000_compare_op0
,
12785 rs6000_compare_op1
)),
12786 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12787 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12788 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12789 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12790 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12791 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12792 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12793 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)))));
12794 else if (GET_CODE (rs6000_compare_op1
) == UNSPEC
12795 && XINT (rs6000_compare_op1
, 1) == UNSPEC_SP_TEST
)
12797 rtx op1
= XVECEXP (rs6000_compare_op1
, 0, 0);
12798 comp_mode
= CCEQmode
;
12799 compare_result
= gen_reg_rtx (CCEQmode
);
12801 emit_insn (gen_stack_protect_testdi (compare_result
,
12802 rs6000_compare_op0
, op1
));
12804 emit_insn (gen_stack_protect_testsi (compare_result
,
12805 rs6000_compare_op0
, op1
));
12808 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
12809 gen_rtx_COMPARE (comp_mode
,
12810 rs6000_compare_op0
,
12811 rs6000_compare_op1
)));
12814 /* Some kinds of FP comparisons need an OR operation;
12815 under flag_finite_math_only we don't bother. */
12816 if (rs6000_compare_fp_p
12817 && !flag_finite_math_only
12818 && !(TARGET_HARD_FLOAT
&& !TARGET_FPRS
)
12819 && (code
== LE
|| code
== GE
12820 || code
== UNEQ
|| code
== LTGT
12821 || code
== UNGT
|| code
== UNLT
))
12823 enum rtx_code or1
, or2
;
12824 rtx or1_rtx
, or2_rtx
, compare2_rtx
;
12825 rtx or_result
= gen_reg_rtx (CCEQmode
);
12829 case LE
: or1
= LT
; or2
= EQ
; break;
12830 case GE
: or1
= GT
; or2
= EQ
; break;
12831 case UNEQ
: or1
= UNORDERED
; or2
= EQ
; break;
12832 case LTGT
: or1
= LT
; or2
= GT
; break;
12833 case UNGT
: or1
= UNORDERED
; or2
= GT
; break;
12834 case UNLT
: or1
= UNORDERED
; or2
= LT
; break;
12835 default: gcc_unreachable ();
12837 validate_condition_mode (or1
, comp_mode
);
12838 validate_condition_mode (or2
, comp_mode
);
12839 or1_rtx
= gen_rtx_fmt_ee (or1
, SImode
, compare_result
, const0_rtx
);
12840 or2_rtx
= gen_rtx_fmt_ee (or2
, SImode
, compare_result
, const0_rtx
);
12841 compare2_rtx
= gen_rtx_COMPARE (CCEQmode
,
12842 gen_rtx_IOR (SImode
, or1_rtx
, or2_rtx
),
12844 emit_insn (gen_rtx_SET (VOIDmode
, or_result
, compare2_rtx
));
12846 compare_result
= or_result
;
12850 validate_condition_mode (code
, GET_MODE (compare_result
));
12852 return gen_rtx_fmt_ee (code
, VOIDmode
, compare_result
, const0_rtx
);
12856 /* Emit the RTL for an sCOND pattern. */
12859 rs6000_emit_sCOND (enum rtx_code code
, rtx result
)
12862 enum machine_mode op_mode
;
12863 enum rtx_code cond_code
;
12865 condition_rtx
= rs6000_generate_compare (code
);
12866 cond_code
= GET_CODE (condition_rtx
);
12868 if (rs6000_compare_fp_p
12869 && !TARGET_FPRS
&& TARGET_HARD_FLOAT
)
12873 PUT_MODE (condition_rtx
, SImode
);
12874 t
= XEXP (condition_rtx
, 0);
12876 gcc_assert (cond_code
== NE
|| cond_code
== EQ
);
12878 if (cond_code
== NE
)
12879 emit_insn (gen_e500_flip_gt_bit (t
, t
));
12881 emit_insn (gen_move_from_CR_gt_bit (result
, t
));
12885 if (cond_code
== NE
12886 || cond_code
== GE
|| cond_code
== LE
12887 || cond_code
== GEU
|| cond_code
== LEU
12888 || cond_code
== ORDERED
|| cond_code
== UNGE
|| cond_code
== UNLE
)
12890 rtx not_result
= gen_reg_rtx (CCEQmode
);
12891 rtx not_op
, rev_cond_rtx
;
12892 enum machine_mode cc_mode
;
12894 cc_mode
= GET_MODE (XEXP (condition_rtx
, 0));
12896 rev_cond_rtx
= gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode
, cond_code
),
12897 SImode
, XEXP (condition_rtx
, 0), const0_rtx
);
12898 not_op
= gen_rtx_COMPARE (CCEQmode
, rev_cond_rtx
, const0_rtx
);
12899 emit_insn (gen_rtx_SET (VOIDmode
, not_result
, not_op
));
12900 condition_rtx
= gen_rtx_EQ (VOIDmode
, not_result
, const0_rtx
);
12903 op_mode
= GET_MODE (rs6000_compare_op0
);
12904 if (op_mode
== VOIDmode
)
12905 op_mode
= GET_MODE (rs6000_compare_op1
);
12907 if (TARGET_POWERPC64
&& (op_mode
== DImode
|| rs6000_compare_fp_p
))
12909 PUT_MODE (condition_rtx
, DImode
);
12910 convert_move (result
, condition_rtx
, 0);
12914 PUT_MODE (condition_rtx
, SImode
);
12915 emit_insn (gen_rtx_SET (VOIDmode
, result
, condition_rtx
));
12919 /* Emit a branch of kind CODE to location LOC. */
12922 rs6000_emit_cbranch (enum rtx_code code
, rtx loc
)
12924 rtx condition_rtx
, loc_ref
;
12926 condition_rtx
= rs6000_generate_compare (code
);
12927 loc_ref
= gen_rtx_LABEL_REF (VOIDmode
, loc
);
12928 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
12929 gen_rtx_IF_THEN_ELSE (VOIDmode
, condition_rtx
,
12930 loc_ref
, pc_rtx
)));
12933 /* Return the string to output a conditional branch to LABEL, which is
12934 the operand number of the label, or -1 if the branch is really a
12935 conditional return.
12937 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
12938 condition code register and its mode specifies what kind of
12939 comparison we made.
12941 REVERSED is nonzero if we should reverse the sense of the comparison.
12943 INSN is the insn. */
12946 output_cbranch (rtx op
, const char *label
, int reversed
, rtx insn
)
12948 static char string
[64];
12949 enum rtx_code code
= GET_CODE (op
);
12950 rtx cc_reg
= XEXP (op
, 0);
12951 enum machine_mode mode
= GET_MODE (cc_reg
);
12952 int cc_regno
= REGNO (cc_reg
) - CR0_REGNO
;
12953 int need_longbranch
= label
!= NULL
&& get_attr_length (insn
) == 8;
12954 int really_reversed
= reversed
^ need_longbranch
;
12960 validate_condition_mode (code
, mode
);
12962 /* Work out which way this really branches. We could use
12963 reverse_condition_maybe_unordered here always but this
12964 makes the resulting assembler clearer. */
12965 if (really_reversed
)
12967 /* Reversal of FP compares takes care -- an ordered compare
12968 becomes an unordered compare and vice versa. */
12969 if (mode
== CCFPmode
)
12970 code
= reverse_condition_maybe_unordered (code
);
12972 code
= reverse_condition (code
);
12975 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
) && mode
== CCFPmode
)
12977 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
12982 /* Opposite of GT. */
12991 gcc_unreachable ();
12997 /* Not all of these are actually distinct opcodes, but
12998 we distinguish them for clarity of the resulting assembler. */
12999 case NE
: case LTGT
:
13000 ccode
= "ne"; break;
13001 case EQ
: case UNEQ
:
13002 ccode
= "eq"; break;
13004 ccode
= "ge"; break;
13005 case GT
: case GTU
: case UNGT
:
13006 ccode
= "gt"; break;
13008 ccode
= "le"; break;
13009 case LT
: case LTU
: case UNLT
:
13010 ccode
= "lt"; break;
13011 case UNORDERED
: ccode
= "un"; break;
13012 case ORDERED
: ccode
= "nu"; break;
13013 case UNGE
: ccode
= "nl"; break;
13014 case UNLE
: ccode
= "ng"; break;
13016 gcc_unreachable ();
13019 /* Maybe we have a guess as to how likely the branch is.
13020 The old mnemonics don't have a way to specify this information. */
13022 note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
);
13023 if (note
!= NULL_RTX
)
13025 /* PROB is the difference from 50%. */
13026 int prob
= INTVAL (XEXP (note
, 0)) - REG_BR_PROB_BASE
/ 2;
13028 /* Only hint for highly probable/improbable branches on newer
13029 cpus as static prediction overrides processor dynamic
13030 prediction. For older cpus we may as well always hint, but
13031 assume not taken for branches that are very close to 50% as a
13032 mispredicted taken branch is more expensive than a
13033 mispredicted not-taken branch. */
13034 if (rs6000_always_hint
13035 || (abs (prob
) > REG_BR_PROB_BASE
/ 100 * 48
13036 && br_prob_note_reliable_p (note
)))
13038 if (abs (prob
) > REG_BR_PROB_BASE
/ 20
13039 && ((prob
> 0) ^ need_longbranch
))
13047 s
+= sprintf (s
, "{b%sr|b%slr%s} ", ccode
, ccode
, pred
);
13049 s
+= sprintf (s
, "{b%s|b%s%s} ", ccode
, ccode
, pred
);
13051 /* We need to escape any '%' characters in the reg_names string.
13052 Assume they'd only be the first character.... */
13053 if (reg_names
[cc_regno
+ CR0_REGNO
][0] == '%')
13055 s
+= sprintf (s
, "%s", reg_names
[cc_regno
+ CR0_REGNO
]);
13059 /* If the branch distance was too far, we may have to use an
13060 unconditional branch to go the distance. */
13061 if (need_longbranch
)
13062 s
+= sprintf (s
, ",$+8\n\tb %s", label
);
13064 s
+= sprintf (s
, ",%s", label
);
13070 /* Return the string to flip the GT bit on a CR. */
13072 output_e500_flip_gt_bit (rtx dst
, rtx src
)
13074 static char string
[64];
13077 gcc_assert (GET_CODE (dst
) == REG
&& CR_REGNO_P (REGNO (dst
))
13078 && GET_CODE (src
) == REG
&& CR_REGNO_P (REGNO (src
)));
13081 a
= 4 * (REGNO (dst
) - CR0_REGNO
) + 1;
13082 b
= 4 * (REGNO (src
) - CR0_REGNO
) + 1;
13084 sprintf (string
, "crnot %d,%d", a
, b
);
13088 /* Return insn index for the vector compare instruction for given CODE,
13089 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
13093 get_vec_cmp_insn (enum rtx_code code
,
13094 enum machine_mode dest_mode
,
13095 enum machine_mode op_mode
)
13097 if (!TARGET_ALTIVEC
)
13098 return INSN_NOT_AVAILABLE
;
13103 if (dest_mode
== V16QImode
&& op_mode
== V16QImode
)
13104 return UNSPEC_VCMPEQUB
;
13105 if (dest_mode
== V8HImode
&& op_mode
== V8HImode
)
13106 return UNSPEC_VCMPEQUH
;
13107 if (dest_mode
== V4SImode
&& op_mode
== V4SImode
)
13108 return UNSPEC_VCMPEQUW
;
13109 if (dest_mode
== V4SImode
&& op_mode
== V4SFmode
)
13110 return UNSPEC_VCMPEQFP
;
13113 if (dest_mode
== V4SImode
&& op_mode
== V4SFmode
)
13114 return UNSPEC_VCMPGEFP
;
13116 if (dest_mode
== V16QImode
&& op_mode
== V16QImode
)
13117 return UNSPEC_VCMPGTSB
;
13118 if (dest_mode
== V8HImode
&& op_mode
== V8HImode
)
13119 return UNSPEC_VCMPGTSH
;
13120 if (dest_mode
== V4SImode
&& op_mode
== V4SImode
)
13121 return UNSPEC_VCMPGTSW
;
13122 if (dest_mode
== V4SImode
&& op_mode
== V4SFmode
)
13123 return UNSPEC_VCMPGTFP
;
13126 if (dest_mode
== V16QImode
&& op_mode
== V16QImode
)
13127 return UNSPEC_VCMPGTUB
;
13128 if (dest_mode
== V8HImode
&& op_mode
== V8HImode
)
13129 return UNSPEC_VCMPGTUH
;
13130 if (dest_mode
== V4SImode
&& op_mode
== V4SImode
)
13131 return UNSPEC_VCMPGTUW
;
13136 return INSN_NOT_AVAILABLE
;
13139 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
13140 DMODE is expected destination mode. This is a recursive function. */
13143 rs6000_emit_vector_compare (enum rtx_code rcode
,
13145 enum machine_mode dmode
)
13149 enum machine_mode dest_mode
;
13150 enum machine_mode op_mode
= GET_MODE (op1
);
13152 gcc_assert (TARGET_ALTIVEC
);
13153 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
13155 /* Floating point vector compare instructions uses destination V4SImode.
13156 Move destination to appropriate mode later. */
13157 if (dmode
== V4SFmode
)
13158 dest_mode
= V4SImode
;
13162 mask
= gen_reg_rtx (dest_mode
);
13163 vec_cmp_insn
= get_vec_cmp_insn (rcode
, dest_mode
, op_mode
);
13165 if (vec_cmp_insn
== INSN_NOT_AVAILABLE
)
13167 bool swap_operands
= false;
13168 bool try_again
= false;
13173 swap_operands
= true;
13178 swap_operands
= true;
13186 /* Invert condition and try again.
13187 e.g., A != B becomes ~(A==B). */
13189 enum rtx_code rev_code
;
13190 enum insn_code nor_code
;
13193 rev_code
= reverse_condition_maybe_unordered (rcode
);
13194 eq_rtx
= rs6000_emit_vector_compare (rev_code
, op0
, op1
,
13197 nor_code
= optab_handler (one_cmpl_optab
, (int)dest_mode
)->insn_code
;
13198 gcc_assert (nor_code
!= CODE_FOR_nothing
);
13199 emit_insn (GEN_FCN (nor_code
) (mask
, eq_rtx
));
13201 if (dmode
!= dest_mode
)
13203 rtx temp
= gen_reg_rtx (dest_mode
);
13204 convert_move (temp
, mask
, 0);
13214 /* Try GT/GTU/LT/LTU OR EQ */
13217 enum insn_code ior_code
;
13218 enum rtx_code new_code
;
13239 gcc_unreachable ();
13242 c_rtx
= rs6000_emit_vector_compare (new_code
,
13243 op0
, op1
, dest_mode
);
13244 eq_rtx
= rs6000_emit_vector_compare (EQ
, op0
, op1
,
13247 ior_code
= optab_handler (ior_optab
, (int)dest_mode
)->insn_code
;
13248 gcc_assert (ior_code
!= CODE_FOR_nothing
);
13249 emit_insn (GEN_FCN (ior_code
) (mask
, c_rtx
, eq_rtx
));
13250 if (dmode
!= dest_mode
)
13252 rtx temp
= gen_reg_rtx (dest_mode
);
13253 convert_move (temp
, mask
, 0);
13260 gcc_unreachable ();
13265 vec_cmp_insn
= get_vec_cmp_insn (rcode
, dest_mode
, op_mode
);
13266 /* You only get two chances. */
13267 gcc_assert (vec_cmp_insn
!= INSN_NOT_AVAILABLE
);
13279 emit_insn (gen_rtx_SET (VOIDmode
, mask
,
13280 gen_rtx_UNSPEC (dest_mode
,
13281 gen_rtvec (2, op0
, op1
),
13283 if (dmode
!= dest_mode
)
13285 rtx temp
= gen_reg_rtx (dest_mode
);
13286 convert_move (temp
, mask
, 0);
13292 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
13293 valid insn doesn exist for given mode. */
13296 get_vsel_insn (enum machine_mode mode
)
13301 return UNSPEC_VSEL4SI
;
13304 return UNSPEC_VSEL4SF
;
13307 return UNSPEC_VSEL8HI
;
13310 return UNSPEC_VSEL16QI
;
13313 return INSN_NOT_AVAILABLE
;
13316 return INSN_NOT_AVAILABLE
;
13319 /* Emit vector select insn where DEST is destination using
13320 operands OP1, OP2 and MASK. */
13323 rs6000_emit_vector_select (rtx dest
, rtx op1
, rtx op2
, rtx mask
)
13326 enum machine_mode dest_mode
= GET_MODE (dest
);
13327 int vsel_insn_index
= get_vsel_insn (GET_MODE (dest
));
13329 temp
= gen_reg_rtx (dest_mode
);
13331 /* For each vector element, select op1 when mask is 1 otherwise
13333 t
= gen_rtx_SET (VOIDmode
, temp
,
13334 gen_rtx_UNSPEC (dest_mode
,
13335 gen_rtvec (3, op2
, op1
, mask
),
13338 emit_move_insn (dest
, temp
);
13342 /* Emit vector conditional expression.
13343 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
13344 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
13347 rs6000_emit_vector_cond_expr (rtx dest
, rtx op1
, rtx op2
,
13348 rtx cond
, rtx cc_op0
, rtx cc_op1
)
13350 enum machine_mode dest_mode
= GET_MODE (dest
);
13351 enum rtx_code rcode
= GET_CODE (cond
);
13354 if (!TARGET_ALTIVEC
)
13357 /* Get the vector mask for the given relational operations. */
13358 mask
= rs6000_emit_vector_compare (rcode
, cc_op0
, cc_op1
, dest_mode
);
13360 rs6000_emit_vector_select (dest
, op1
, op2
, mask
);
13365 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
13366 operands of the last comparison is nonzero/true, FALSE_COND if it
13367 is zero/false. Return 0 if the hardware has no such operation. */
13370 rs6000_emit_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
13372 enum rtx_code code
= GET_CODE (op
);
13373 rtx op0
= rs6000_compare_op0
;
13374 rtx op1
= rs6000_compare_op1
;
13375 REAL_VALUE_TYPE c1
;
13376 enum machine_mode compare_mode
= GET_MODE (op0
);
13377 enum machine_mode result_mode
= GET_MODE (dest
);
13379 bool is_against_zero
;
13381 /* These modes should always match. */
13382 if (GET_MODE (op1
) != compare_mode
13383 /* In the isel case however, we can use a compare immediate, so
13384 op1 may be a small constant. */
13385 && (!TARGET_ISEL
|| !short_cint_operand (op1
, VOIDmode
)))
13387 if (GET_MODE (true_cond
) != result_mode
)
13389 if (GET_MODE (false_cond
) != result_mode
)
13392 /* First, work out if the hardware can do this at all, or
13393 if it's too slow.... */
13394 if (! rs6000_compare_fp_p
)
13397 return rs6000_emit_int_cmove (dest
, op
, true_cond
, false_cond
);
13400 else if (TARGET_HARD_FLOAT
&& !TARGET_FPRS
13401 && SCALAR_FLOAT_MODE_P (compare_mode
))
13404 is_against_zero
= op1
== CONST0_RTX (compare_mode
);
13406 /* A floating-point subtract might overflow, underflow, or produce
13407 an inexact result, thus changing the floating-point flags, so it
13408 can't be generated if we care about that. It's safe if one side
13409 of the construct is zero, since then no subtract will be
13411 if (SCALAR_FLOAT_MODE_P (compare_mode
)
13412 && flag_trapping_math
&& ! is_against_zero
)
13415 /* Eliminate half of the comparisons by switching operands, this
13416 makes the remaining code simpler. */
13417 if (code
== UNLT
|| code
== UNGT
|| code
== UNORDERED
|| code
== NE
13418 || code
== LTGT
|| code
== LT
|| code
== UNLE
)
13420 code
= reverse_condition_maybe_unordered (code
);
13422 true_cond
= false_cond
;
13426 /* UNEQ and LTGT take four instructions for a comparison with zero,
13427 it'll probably be faster to use a branch here too. */
13428 if (code
== UNEQ
&& HONOR_NANS (compare_mode
))
13431 if (GET_CODE (op1
) == CONST_DOUBLE
)
13432 REAL_VALUE_FROM_CONST_DOUBLE (c1
, op1
);
13434 /* We're going to try to implement comparisons by performing
13435 a subtract, then comparing against zero. Unfortunately,
13436 Inf - Inf is NaN which is not zero, and so if we don't
13437 know that the operand is finite and the comparison
13438 would treat EQ different to UNORDERED, we can't do it. */
13439 if (HONOR_INFINITIES (compare_mode
)
13440 && code
!= GT
&& code
!= UNGE
13441 && (GET_CODE (op1
) != CONST_DOUBLE
|| real_isinf (&c1
))
13442 /* Constructs of the form (a OP b ? a : b) are safe. */
13443 && ((! rtx_equal_p (op0
, false_cond
) && ! rtx_equal_p (op1
, false_cond
))
13444 || (! rtx_equal_p (op0
, true_cond
)
13445 && ! rtx_equal_p (op1
, true_cond
))))
13448 /* At this point we know we can use fsel. */
13450 /* Reduce the comparison to a comparison against zero. */
13451 if (! is_against_zero
)
13453 temp
= gen_reg_rtx (compare_mode
);
13454 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
13455 gen_rtx_MINUS (compare_mode
, op0
, op1
)));
13457 op1
= CONST0_RTX (compare_mode
);
13460 /* If we don't care about NaNs we can reduce some of the comparisons
13461 down to faster ones. */
13462 if (! HONOR_NANS (compare_mode
))
13468 true_cond
= false_cond
;
13481 /* Now, reduce everything down to a GE. */
13488 temp
= gen_reg_rtx (compare_mode
);
13489 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
13494 temp
= gen_reg_rtx (compare_mode
);
13495 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_ABS (compare_mode
, op0
)));
13500 temp
= gen_reg_rtx (compare_mode
);
13501 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
13502 gen_rtx_NEG (compare_mode
,
13503 gen_rtx_ABS (compare_mode
, op0
))));
13508 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
13509 temp
= gen_reg_rtx (result_mode
);
13510 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
13511 gen_rtx_IF_THEN_ELSE (result_mode
,
13512 gen_rtx_GE (VOIDmode
,
13514 true_cond
, false_cond
)));
13515 false_cond
= true_cond
;
13518 temp
= gen_reg_rtx (compare_mode
);
13519 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
13524 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
13525 temp
= gen_reg_rtx (result_mode
);
13526 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
13527 gen_rtx_IF_THEN_ELSE (result_mode
,
13528 gen_rtx_GE (VOIDmode
,
13530 true_cond
, false_cond
)));
13531 true_cond
= false_cond
;
13534 temp
= gen_reg_rtx (compare_mode
);
13535 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
13540 gcc_unreachable ();
13543 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
13544 gen_rtx_IF_THEN_ELSE (result_mode
,
13545 gen_rtx_GE (VOIDmode
,
13547 true_cond
, false_cond
)));
13551 /* Same as above, but for ints (isel). */
13554 rs6000_emit_int_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
13556 rtx condition_rtx
, cr
;
13558 /* All isel implementations thus far are 32-bits. */
13559 if (GET_MODE (rs6000_compare_op0
) != SImode
)
13562 /* We still have to do the compare, because isel doesn't do a
13563 compare, it just looks at the CRx bits set by a previous compare
13565 condition_rtx
= rs6000_generate_compare (GET_CODE (op
));
13566 cr
= XEXP (condition_rtx
, 0);
13568 if (GET_MODE (cr
) == CCmode
)
13569 emit_insn (gen_isel_signed (dest
, condition_rtx
,
13570 true_cond
, false_cond
, cr
));
13572 emit_insn (gen_isel_unsigned (dest
, condition_rtx
,
13573 true_cond
, false_cond
, cr
));
13579 output_isel (rtx
*operands
)
13581 enum rtx_code code
;
13583 code
= GET_CODE (operands
[1]);
13584 if (code
== GE
|| code
== GEU
|| code
== LE
|| code
== LEU
|| code
== NE
)
13586 PUT_CODE (operands
[1], reverse_condition (code
));
13587 return "isel %0,%3,%2,%j1";
13590 return "isel %0,%2,%3,%j1";
13594 rs6000_emit_minmax (rtx dest
, enum rtx_code code
, rtx op0
, rtx op1
)
13596 enum machine_mode mode
= GET_MODE (op0
);
13600 if (code
== SMAX
|| code
== SMIN
)
13605 if (code
== SMAX
|| code
== UMAX
)
13606 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
13607 op0
, op1
, mode
, 0);
13609 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
13610 op1
, op0
, mode
, 0);
13611 gcc_assert (target
);
13612 if (target
!= dest
)
13613 emit_move_insn (dest
, target
);
13616 /* Emit instructions to perform a load-reserved/store-conditional operation.
13617 The operation performed is an atomic
13618 (set M (CODE:MODE M OP))
13619 If not NULL, BEFORE is atomically set to M before the operation, and
13620 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
13621 If SYNC_P then a memory barrier is emitted before the operation.
13622 Either OP or M may be wrapped in a NOT operation. */
13625 rs6000_emit_sync (enum rtx_code code
, enum machine_mode mode
,
13626 rtx m
, rtx op
, rtx before_param
, rtx after_param
,
13629 enum machine_mode used_mode
;
13630 rtx the_op
, set_before
, set_after
, set_atomic
, cc_scratch
, before
, after
;
13633 HOST_WIDE_INT imask
= GET_MODE_MASK (mode
);
13634 rtx shift
= NULL_RTX
;
13637 emit_insn (gen_memory_barrier ());
13639 if (GET_CODE (m
) == NOT
)
13640 used_m
= XEXP (m
, 0);
13644 /* If this is smaller than SImode, we'll have to use SImode with
13646 if (mode
== QImode
|| mode
== HImode
)
13650 if (MEM_ALIGN (used_m
) >= 32)
13653 if (BYTES_BIG_ENDIAN
)
13654 ishift
= GET_MODE_BITSIZE (SImode
) - GET_MODE_BITSIZE (mode
);
13656 shift
= GEN_INT (ishift
);
13657 used_m
= change_address (used_m
, SImode
, 0);
13661 rtx addrSI
, aligned_addr
;
13662 int shift_mask
= mode
== QImode
? 0x18 : 0x10;
13664 addrSI
= gen_lowpart_common (SImode
,
13665 force_reg (Pmode
, XEXP (used_m
, 0)));
13666 addrSI
= force_reg (SImode
, addrSI
);
13667 shift
= gen_reg_rtx (SImode
);
13669 emit_insn (gen_rlwinm (shift
, addrSI
, GEN_INT (3),
13670 GEN_INT (shift_mask
)));
13671 emit_insn (gen_xorsi3 (shift
, shift
, GEN_INT (shift_mask
)));
13673 aligned_addr
= expand_binop (Pmode
, and_optab
,
13675 GEN_INT (-4), NULL_RTX
,
13676 1, OPTAB_LIB_WIDEN
);
13677 used_m
= change_address (used_m
, SImode
, aligned_addr
);
13678 set_mem_align (used_m
, 32);
13680 /* It's safe to keep the old alias set of USED_M, because
13681 the operation is atomic and only affects the original
13683 if (GET_CODE (m
) == NOT
)
13684 m
= gen_rtx_NOT (SImode
, used_m
);
13688 if (GET_CODE (op
) == NOT
)
13690 oldop
= lowpart_subreg (SImode
, XEXP (op
, 0), mode
);
13691 oldop
= gen_rtx_NOT (SImode
, oldop
);
13694 oldop
= lowpart_subreg (SImode
, op
, mode
);
13700 newop
= expand_binop (SImode
, and_optab
,
13701 oldop
, GEN_INT (imask
), NULL_RTX
,
13702 1, OPTAB_LIB_WIDEN
);
13703 emit_insn (gen_ashlsi3 (newop
, newop
, shift
));
13707 newop
= expand_binop (SImode
, ior_optab
,
13708 oldop
, GEN_INT (~imask
), NULL_RTX
,
13709 1, OPTAB_LIB_WIDEN
);
13710 emit_insn (gen_rotlsi3 (newop
, newop
, shift
));
13718 newop
= expand_binop (SImode
, and_optab
,
13719 oldop
, GEN_INT (imask
), NULL_RTX
,
13720 1, OPTAB_LIB_WIDEN
);
13721 emit_insn (gen_ashlsi3 (newop
, newop
, shift
));
13723 mask
= gen_reg_rtx (SImode
);
13724 emit_move_insn (mask
, GEN_INT (imask
));
13725 emit_insn (gen_ashlsi3 (mask
, mask
, shift
));
13728 newop
= gen_rtx_PLUS (SImode
, m
, newop
);
13730 newop
= gen_rtx_MINUS (SImode
, m
, newop
);
13731 newop
= gen_rtx_AND (SImode
, newop
, mask
);
13732 newop
= gen_rtx_IOR (SImode
, newop
,
13733 gen_rtx_AND (SImode
,
13734 gen_rtx_NOT (SImode
, mask
),
13740 gcc_unreachable ();
13743 if (GET_CODE (m
) == NOT
)
13747 mask
= gen_reg_rtx (SImode
);
13748 emit_move_insn (mask
, GEN_INT (imask
));
13749 emit_insn (gen_ashlsi3 (mask
, mask
, shift
));
13751 xorm
= gen_rtx_XOR (SImode
, used_m
, mask
);
13752 /* Depending on the value of 'op', the XOR or the operation might
13753 be able to be simplified away. */
13754 newop
= simplify_gen_binary (code
, SImode
, xorm
, newop
);
13757 used_mode
= SImode
;
13758 before
= gen_reg_rtx (used_mode
);
13759 after
= gen_reg_rtx (used_mode
);
13764 before
= before_param
;
13765 after
= after_param
;
13767 if (before
== NULL_RTX
)
13768 before
= gen_reg_rtx (used_mode
);
13769 if (after
== NULL_RTX
)
13770 after
= gen_reg_rtx (used_mode
);
13773 if ((code
== PLUS
|| code
== MINUS
|| GET_CODE (m
) == NOT
)
13774 && used_mode
!= mode
)
13775 the_op
= op
; /* Computed above. */
13776 else if (GET_CODE (op
) == NOT
&& GET_CODE (m
) != NOT
)
13777 the_op
= gen_rtx_fmt_ee (code
, used_mode
, op
, m
);
13779 the_op
= gen_rtx_fmt_ee (code
, used_mode
, m
, op
);
13781 set_after
= gen_rtx_SET (VOIDmode
, after
, the_op
);
13782 set_before
= gen_rtx_SET (VOIDmode
, before
, used_m
);
13783 set_atomic
= gen_rtx_SET (VOIDmode
, used_m
,
13784 gen_rtx_UNSPEC (used_mode
,
13785 gen_rtvec (1, the_op
),
13787 cc_scratch
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (CCmode
));
13789 if ((code
== PLUS
|| code
== MINUS
) && used_mode
!= mode
)
13790 vec
= gen_rtvec (5, set_after
, set_before
, set_atomic
, cc_scratch
,
13791 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (SImode
)));
13793 vec
= gen_rtvec (4, set_after
, set_before
, set_atomic
, cc_scratch
);
13794 emit_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
13796 /* Shift and mask the return values properly. */
13797 if (used_mode
!= mode
&& before_param
)
13799 emit_insn (gen_lshrsi3 (before
, before
, shift
));
13800 convert_move (before_param
, before
, 1);
13803 if (used_mode
!= mode
&& after_param
)
13805 emit_insn (gen_lshrsi3 (after
, after
, shift
));
13806 convert_move (after_param
, after
, 1);
13809 /* The previous sequence will end with a branch that's dependent on
13810 the conditional store, so placing an isync will ensure that no
13811 other instructions (especially, no load or store instructions)
13812 can start before the atomic operation completes. */
13814 emit_insn (gen_isync ());
13817 /* A subroutine of the atomic operation splitters. Jump to LABEL if
13818 COND is true. Mark the jump as unlikely to be taken. */
13821 emit_unlikely_jump (rtx cond
, rtx label
)
13823 rtx very_unlikely
= GEN_INT (REG_BR_PROB_BASE
/ 100 - 1);
13826 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, label
, pc_rtx
);
13827 x
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, x
));
13828 REG_NOTES (x
) = gen_rtx_EXPR_LIST (REG_BR_PROB
, very_unlikely
, NULL_RTX
);
13831 /* A subroutine of the atomic operation splitters. Emit a load-locked
13832 instruction in MODE. */
13835 emit_load_locked (enum machine_mode mode
, rtx reg
, rtx mem
)
13837 rtx (*fn
) (rtx
, rtx
) = NULL
;
13838 if (mode
== SImode
)
13839 fn
= gen_load_locked_si
;
13840 else if (mode
== DImode
)
13841 fn
= gen_load_locked_di
;
13842 emit_insn (fn (reg
, mem
));
13845 /* A subroutine of the atomic operation splitters. Emit a store-conditional
13846 instruction in MODE. */
13849 emit_store_conditional (enum machine_mode mode
, rtx res
, rtx mem
, rtx val
)
13851 rtx (*fn
) (rtx
, rtx
, rtx
) = NULL
;
13852 if (mode
== SImode
)
13853 fn
= gen_store_conditional_si
;
13854 else if (mode
== DImode
)
13855 fn
= gen_store_conditional_di
;
13857 /* Emit sync before stwcx. to address PPC405 Erratum. */
13858 if (PPC405_ERRATUM77
)
13859 emit_insn (gen_memory_barrier ());
13861 emit_insn (fn (res
, mem
, val
));
13864 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
13865 to perform. MEM is the memory on which to operate. VAL is the second
13866 operand of the binary operator. BEFORE and AFTER are optional locations to
13867 return the value of MEM either before of after the operation. SCRATCH is
13868 a scratch register. */
13871 rs6000_split_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
13872 rtx before
, rtx after
, rtx scratch
)
13874 enum machine_mode mode
= GET_MODE (mem
);
13875 rtx label
, x
, cond
= gen_rtx_REG (CCmode
, CR0_REGNO
);
13877 emit_insn (gen_memory_barrier ());
13879 label
= gen_label_rtx ();
13880 emit_label (label
);
13881 label
= gen_rtx_LABEL_REF (VOIDmode
, label
);
13883 if (before
== NULL_RTX
)
13885 emit_load_locked (mode
, before
, mem
);
13888 x
= gen_rtx_AND (mode
, gen_rtx_NOT (mode
, before
), val
);
13889 else if (code
== AND
)
13890 x
= gen_rtx_UNSPEC (mode
, gen_rtvec (2, before
, val
), UNSPEC_AND
);
13892 x
= gen_rtx_fmt_ee (code
, mode
, before
, val
);
13894 if (after
!= NULL_RTX
)
13895 emit_insn (gen_rtx_SET (VOIDmode
, after
, copy_rtx (x
)));
13896 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, x
));
13898 emit_store_conditional (mode
, cond
, mem
, scratch
);
13900 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
13901 emit_unlikely_jump (x
, label
);
13903 emit_insn (gen_isync ());
13906 /* Expand an atomic compare and swap operation. MEM is the memory on which
13907 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
13908 value to be stored. SCRATCH is a scratch GPR. */
13911 rs6000_split_compare_and_swap (rtx retval
, rtx mem
, rtx oldval
, rtx newval
,
13914 enum machine_mode mode
= GET_MODE (mem
);
13915 rtx label1
, label2
, x
, cond
= gen_rtx_REG (CCmode
, CR0_REGNO
);
13917 emit_insn (gen_memory_barrier ());
13919 label1
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
13920 label2
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
13921 emit_label (XEXP (label1
, 0));
13923 emit_load_locked (mode
, retval
, mem
);
13925 x
= gen_rtx_COMPARE (CCmode
, retval
, oldval
);
13926 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
13928 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
13929 emit_unlikely_jump (x
, label2
);
13931 emit_move_insn (scratch
, newval
);
13932 emit_store_conditional (mode
, cond
, mem
, scratch
);
13934 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
13935 emit_unlikely_jump (x
, label1
);
13937 emit_insn (gen_isync ());
13938 emit_label (XEXP (label2
, 0));
13941 /* Expand an atomic test and set operation. MEM is the memory on which
13942 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
13945 rs6000_split_lock_test_and_set (rtx retval
, rtx mem
, rtx val
, rtx scratch
)
13947 enum machine_mode mode
= GET_MODE (mem
);
13948 rtx label
, x
, cond
= gen_rtx_REG (CCmode
, CR0_REGNO
);
13950 emit_insn (gen_memory_barrier ());
13952 label
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
13953 emit_label (XEXP (label
, 0));
13955 emit_load_locked (mode
, retval
, mem
);
13956 emit_move_insn (scratch
, val
);
13957 emit_store_conditional (mode
, cond
, mem
, scratch
);
13959 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
13960 emit_unlikely_jump (x
, label
);
13962 emit_insn (gen_isync ());
13966 rs6000_expand_compare_and_swapqhi (rtx dst
, rtx mem
, rtx oldval
, rtx newval
)
13968 enum machine_mode mode
= GET_MODE (mem
);
13969 rtx addrSI
, align
, wdst
, shift
, mask
;
13970 HOST_WIDE_INT shift_mask
= mode
== QImode
? 0x18 : 0x10;
13971 HOST_WIDE_INT imask
= GET_MODE_MASK (mode
);
13973 /* Shift amount for subword relative to aligned word. */
13974 addrSI
= force_reg (SImode
, gen_lowpart_common (SImode
, XEXP (mem
, 0)));
13975 shift
= gen_reg_rtx (SImode
);
13976 emit_insn (gen_rlwinm (shift
, addrSI
, GEN_INT (3),
13977 GEN_INT (shift_mask
)));
13978 emit_insn (gen_xorsi3 (shift
, shift
, GEN_INT (shift_mask
)));
13980 /* Shift and mask old value into position within word. */
13981 oldval
= convert_modes (SImode
, mode
, oldval
, 1);
13982 oldval
= expand_binop (SImode
, and_optab
,
13983 oldval
, GEN_INT (imask
), NULL_RTX
,
13984 1, OPTAB_LIB_WIDEN
);
13985 emit_insn (gen_ashlsi3 (oldval
, oldval
, shift
));
13987 /* Shift and mask new value into position within word. */
13988 newval
= convert_modes (SImode
, mode
, newval
, 1);
13989 newval
= expand_binop (SImode
, and_optab
,
13990 newval
, GEN_INT (imask
), NULL_RTX
,
13991 1, OPTAB_LIB_WIDEN
);
13992 emit_insn (gen_ashlsi3 (newval
, newval
, shift
));
13994 /* Mask for insertion. */
13995 mask
= gen_reg_rtx (SImode
);
13996 emit_move_insn (mask
, GEN_INT (imask
));
13997 emit_insn (gen_ashlsi3 (mask
, mask
, shift
));
13999 /* Address of aligned word containing subword. */
14000 align
= expand_binop (Pmode
, and_optab
, XEXP (mem
, 0), GEN_INT (-4),
14001 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
14002 mem
= change_address (mem
, SImode
, align
);
14003 set_mem_align (mem
, 32);
14004 MEM_VOLATILE_P (mem
) = 1;
14006 wdst
= gen_reg_rtx (SImode
);
14007 emit_insn (gen_sync_compare_and_swapqhi_internal (wdst
, mask
,
14008 oldval
, newval
, mem
));
14010 /* Shift the result back. */
14011 emit_insn (gen_lshrsi3 (wdst
, wdst
, shift
));
14013 emit_move_insn (dst
, gen_lowpart (mode
, wdst
));
14017 rs6000_split_compare_and_swapqhi (rtx dest
, rtx mask
,
14018 rtx oldval
, rtx newval
, rtx mem
,
14021 rtx label1
, label2
, x
, cond
= gen_rtx_REG (CCmode
, CR0_REGNO
);
14023 emit_insn (gen_memory_barrier ());
14024 label1
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
14025 label2
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
14026 emit_label (XEXP (label1
, 0));
14028 emit_load_locked (SImode
, scratch
, mem
);
14030 /* Mask subword within loaded value for comparison with oldval.
14031 Use UNSPEC_AND to avoid clobber.*/
14032 emit_insn (gen_rtx_SET (SImode
, dest
,
14033 gen_rtx_UNSPEC (SImode
,
14034 gen_rtvec (2, scratch
, mask
),
14037 x
= gen_rtx_COMPARE (CCmode
, dest
, oldval
);
14038 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
14040 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
14041 emit_unlikely_jump (x
, label2
);
14043 /* Clear subword within loaded value for insertion of new value. */
14044 emit_insn (gen_rtx_SET (SImode
, scratch
,
14045 gen_rtx_AND (SImode
,
14046 gen_rtx_NOT (SImode
, mask
), scratch
)));
14047 emit_insn (gen_iorsi3 (scratch
, scratch
, newval
));
14048 emit_store_conditional (SImode
, cond
, mem
, scratch
);
14050 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
14051 emit_unlikely_jump (x
, label1
);
14053 emit_insn (gen_isync ());
14054 emit_label (XEXP (label2
, 0));
14058 /* Emit instructions to move SRC to DST. Called by splitters for
14059 multi-register moves. It will emit at most one instruction for
14060 each register that is accessed; that is, it won't emit li/lis pairs
14061 (or equivalent for 64-bit code). One of SRC or DST must be a hard
14065 rs6000_split_multireg_move (rtx dst
, rtx src
)
14067 /* The register number of the first register being moved. */
14069 /* The mode that is to be moved. */
14070 enum machine_mode mode
;
14071 /* The mode that the move is being done in, and its size. */
14072 enum machine_mode reg_mode
;
14074 /* The number of registers that will be moved. */
14077 reg
= REG_P (dst
) ? REGNO (dst
) : REGNO (src
);
14078 mode
= GET_MODE (dst
);
14079 nregs
= hard_regno_nregs
[reg
][mode
];
14080 if (FP_REGNO_P (reg
))
14081 reg_mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
: DFmode
;
14082 else if (ALTIVEC_REGNO_P (reg
))
14083 reg_mode
= V16QImode
;
14084 else if (TARGET_E500_DOUBLE
&& mode
== TFmode
)
14087 reg_mode
= word_mode
;
14088 reg_mode_size
= GET_MODE_SIZE (reg_mode
);
14090 gcc_assert (reg_mode_size
* nregs
== GET_MODE_SIZE (mode
));
14092 if (REG_P (src
) && REG_P (dst
) && (REGNO (src
) < REGNO (dst
)))
14094 /* Move register range backwards, if we might have destructive
14097 for (i
= nregs
- 1; i
>= 0; i
--)
14098 emit_insn (gen_rtx_SET (VOIDmode
,
14099 simplify_gen_subreg (reg_mode
, dst
, mode
,
14100 i
* reg_mode_size
),
14101 simplify_gen_subreg (reg_mode
, src
, mode
,
14102 i
* reg_mode_size
)));
14108 bool used_update
= false;
14110 if (MEM_P (src
) && INT_REGNO_P (reg
))
14114 if (GET_CODE (XEXP (src
, 0)) == PRE_INC
14115 || GET_CODE (XEXP (src
, 0)) == PRE_DEC
)
14118 breg
= XEXP (XEXP (src
, 0), 0);
14119 delta_rtx
= (GET_CODE (XEXP (src
, 0)) == PRE_INC
14120 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src
)))
14121 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src
))));
14122 emit_insn (TARGET_32BIT
14123 ? gen_addsi3 (breg
, breg
, delta_rtx
)
14124 : gen_adddi3 (breg
, breg
, delta_rtx
));
14125 src
= replace_equiv_address (src
, breg
);
14127 else if (! rs6000_offsettable_memref_p (src
))
14130 basereg
= gen_rtx_REG (Pmode
, reg
);
14131 emit_insn (gen_rtx_SET (VOIDmode
, basereg
, XEXP (src
, 0)));
14132 src
= replace_equiv_address (src
, basereg
);
14135 breg
= XEXP (src
, 0);
14136 if (GET_CODE (breg
) == PLUS
|| GET_CODE (breg
) == LO_SUM
)
14137 breg
= XEXP (breg
, 0);
14139 /* If the base register we are using to address memory is
14140 also a destination reg, then change that register last. */
14142 && REGNO (breg
) >= REGNO (dst
)
14143 && REGNO (breg
) < REGNO (dst
) + nregs
)
14144 j
= REGNO (breg
) - REGNO (dst
);
14147 if (GET_CODE (dst
) == MEM
&& INT_REGNO_P (reg
))
14151 if (GET_CODE (XEXP (dst
, 0)) == PRE_INC
14152 || GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
14155 breg
= XEXP (XEXP (dst
, 0), 0);
14156 delta_rtx
= (GET_CODE (XEXP (dst
, 0)) == PRE_INC
14157 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst
)))
14158 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst
))));
14160 /* We have to update the breg before doing the store.
14161 Use store with update, if available. */
14165 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
14166 emit_insn (TARGET_32BIT
14167 ? (TARGET_POWERPC64
14168 ? gen_movdi_si_update (breg
, breg
, delta_rtx
, nsrc
)
14169 : gen_movsi_update (breg
, breg
, delta_rtx
, nsrc
))
14170 : gen_movdi_di_update (breg
, breg
, delta_rtx
, nsrc
));
14171 used_update
= true;
14174 emit_insn (TARGET_32BIT
14175 ? gen_addsi3 (breg
, breg
, delta_rtx
)
14176 : gen_adddi3 (breg
, breg
, delta_rtx
));
14177 dst
= replace_equiv_address (dst
, breg
);
14180 gcc_assert (rs6000_offsettable_memref_p (dst
));
14183 for (i
= 0; i
< nregs
; i
++)
14185 /* Calculate index to next subword. */
14190 /* If compiler already emitted move of first word by
14191 store with update, no need to do anything. */
14192 if (j
== 0 && used_update
)
14195 emit_insn (gen_rtx_SET (VOIDmode
,
14196 simplify_gen_subreg (reg_mode
, dst
, mode
,
14197 j
* reg_mode_size
),
14198 simplify_gen_subreg (reg_mode
, src
, mode
,
14199 j
* reg_mode_size
)));
14205 /* This page contains routines that are used to determine what the
14206 function prologue and epilogue code will do and write them out. */
14208 /* Return the first fixed-point register that is required to be
14209 saved. 32 if none. */
14212 first_reg_to_save (void)
14216 /* Find lowest numbered live register. */
14217 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
14218 if (df_regs_ever_live_p (first_reg
)
14219 && (! call_used_regs
[first_reg
]
14220 || (first_reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
14221 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
14222 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
14223 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
)))))
14228 && crtl
->uses_pic_offset_table
14229 && first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
14230 return RS6000_PIC_OFFSET_TABLE_REGNUM
;
14236 /* Similar, for FP regs. */
14239 first_fp_reg_to_save (void)
14243 /* Find lowest numbered live register. */
14244 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
14245 if (df_regs_ever_live_p (first_reg
))
14251 /* Similar, for AltiVec regs. */
14254 first_altivec_reg_to_save (void)
14258 /* Stack frame remains as is unless we are in AltiVec ABI. */
14259 if (! TARGET_ALTIVEC_ABI
)
14260 return LAST_ALTIVEC_REGNO
+ 1;
14262 /* On Darwin, the unwind routines are compiled without
14263 TARGET_ALTIVEC, and use save_world to save/restore the
14264 altivec registers when necessary. */
14265 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
14266 && ! TARGET_ALTIVEC
)
14267 return FIRST_ALTIVEC_REGNO
+ 20;
14269 /* Find lowest numbered live register. */
14270 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
<= LAST_ALTIVEC_REGNO
; ++i
)
14271 if (df_regs_ever_live_p (i
))
14277 /* Return a 32-bit mask of the AltiVec registers we need to set in
14278 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
14279 the 32-bit word is 0. */
14281 static unsigned int
14282 compute_vrsave_mask (void)
14284 unsigned int i
, mask
= 0;
14286 /* On Darwin, the unwind routines are compiled without
14287 TARGET_ALTIVEC, and use save_world to save/restore the
14288 call-saved altivec registers when necessary. */
14289 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
14290 && ! TARGET_ALTIVEC
)
14293 /* First, find out if we use _any_ altivec registers. */
14294 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
14295 if (df_regs_ever_live_p (i
))
14296 mask
|= ALTIVEC_REG_BIT (i
);
14301 /* Next, remove the argument registers from the set. These must
14302 be in the VRSAVE mask set by the caller, so we don't need to add
14303 them in again. More importantly, the mask we compute here is
14304 used to generate CLOBBERs in the set_vrsave insn, and we do not
14305 wish the argument registers to die. */
14306 for (i
= crtl
->args
.info
.vregno
- 1; i
>= ALTIVEC_ARG_MIN_REG
; --i
)
14307 mask
&= ~ALTIVEC_REG_BIT (i
);
14309 /* Similarly, remove the return value from the set. */
14312 diddle_return_value (is_altivec_return_reg
, &yes
);
14314 mask
&= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN
);
14320 /* For a very restricted set of circumstances, we can cut down the
14321 size of prologues/epilogues by calling our own save/restore-the-world
14325 compute_save_world_info (rs6000_stack_t
*info_ptr
)
14327 info_ptr
->world_save_p
= 1;
14328 info_ptr
->world_save_p
14329 = (WORLD_SAVE_P (info_ptr
)
14330 && DEFAULT_ABI
== ABI_DARWIN
14331 && ! (cfun
->calls_setjmp
&& flag_exceptions
)
14332 && info_ptr
->first_fp_reg_save
== FIRST_SAVED_FP_REGNO
14333 && info_ptr
->first_gp_reg_save
== FIRST_SAVED_GP_REGNO
14334 && info_ptr
->first_altivec_reg_save
== FIRST_SAVED_ALTIVEC_REGNO
14335 && info_ptr
->cr_save_p
);
14337 /* This will not work in conjunction with sibcalls. Make sure there
14338 are none. (This check is expensive, but seldom executed.) */
14339 if (WORLD_SAVE_P (info_ptr
))
14342 for ( insn
= get_last_insn_anywhere (); insn
; insn
= PREV_INSN (insn
))
14343 if ( GET_CODE (insn
) == CALL_INSN
14344 && SIBLING_CALL_P (insn
))
14346 info_ptr
->world_save_p
= 0;
14351 if (WORLD_SAVE_P (info_ptr
))
14353 /* Even if we're not touching VRsave, make sure there's room on the
14354 stack for it, if it looks like we're calling SAVE_WORLD, which
14355 will attempt to save it. */
14356 info_ptr
->vrsave_size
= 4;
14358 /* If we are going to save the world, we need to save the link register too. */
14359 info_ptr
->lr_save_p
= 1;
14361 /* "Save" the VRsave register too if we're saving the world. */
14362 if (info_ptr
->vrsave_mask
== 0)
14363 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
14365 /* Because the Darwin register save/restore routines only handle
14366 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
14368 gcc_assert (info_ptr
->first_fp_reg_save
>= FIRST_SAVED_FP_REGNO
14369 && (info_ptr
->first_altivec_reg_save
14370 >= FIRST_SAVED_ALTIVEC_REGNO
));
14377 is_altivec_return_reg (rtx reg
, void *xyes
)
14379 bool *yes
= (bool *) xyes
;
14380 if (REGNO (reg
) == ALTIVEC_ARG_RETURN
)
14385 /* Calculate the stack information for the current function. This is
14386 complicated by having two separate calling sequences, the AIX calling
14387 sequence and the V.4 calling sequence.
14389 AIX (and Darwin/Mac OS X) stack frames look like:
14391 SP----> +---------------------------------------+
14392 | back chain to caller | 0 0
14393 +---------------------------------------+
14394 | saved CR | 4 8 (8-11)
14395 +---------------------------------------+
14397 +---------------------------------------+
14398 | reserved for compilers | 12 24
14399 +---------------------------------------+
14400 | reserved for binders | 16 32
14401 +---------------------------------------+
14402 | saved TOC pointer | 20 40
14403 +---------------------------------------+
14404 | Parameter save area (P) | 24 48
14405 +---------------------------------------+
14406 | Alloca space (A) | 24+P etc.
14407 +---------------------------------------+
14408 | Local variable space (L) | 24+P+A
14409 +---------------------------------------+
14410 | Float/int conversion temporary (X) | 24+P+A+L
14411 +---------------------------------------+
14412 | Save area for AltiVec registers (W) | 24+P+A+L+X
14413 +---------------------------------------+
14414 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
14415 +---------------------------------------+
14416 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
14417 +---------------------------------------+
14418 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
14419 +---------------------------------------+
14420 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
14421 +---------------------------------------+
14422 old SP->| back chain to caller's caller |
14423 +---------------------------------------+
14425 The required alignment for AIX configurations is two words (i.e., 8
14429 V.4 stack frames look like:
14431 SP----> +---------------------------------------+
14432 | back chain to caller | 0
14433 +---------------------------------------+
14434 | caller's saved LR | 4
14435 +---------------------------------------+
14436 | Parameter save area (P) | 8
14437 +---------------------------------------+
14438 | Alloca space (A) | 8+P
14439 +---------------------------------------+
14440 | Varargs save area (V) | 8+P+A
14441 +---------------------------------------+
14442 | Local variable space (L) | 8+P+A+V
14443 +---------------------------------------+
14444 | Float/int conversion temporary (X) | 8+P+A+V+L
14445 +---------------------------------------+
14446 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
14447 +---------------------------------------+
14448 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
14449 +---------------------------------------+
14450 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
14451 +---------------------------------------+
14452 | SPE: area for 64-bit GP registers |
14453 +---------------------------------------+
14454 | SPE alignment padding |
14455 +---------------------------------------+
14456 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
14457 +---------------------------------------+
14458 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
14459 +---------------------------------------+
14460 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
14461 +---------------------------------------+
14462 old SP->| back chain to caller's caller |
14463 +---------------------------------------+
14465 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
14466 given. (But note below and in sysv4.h that we require only 8 and
14467 may round up the size of our stack frame anyways. The historical
14468 reason is early versions of powerpc-linux which didn't properly
14469 align the stack at program startup. A happy side-effect is that
14470 -mno-eabi libraries can be used with -meabi programs.)
14472 The EABI configuration defaults to the V.4 layout. However,
14473 the stack alignment requirements may differ. If -mno-eabi is not
14474 given, the required stack alignment is 8 bytes; if -mno-eabi is
14475 given, the required alignment is 16 bytes. (But see V.4 comment
14478 #ifndef ABI_STACK_BOUNDARY
14479 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
14482 static rs6000_stack_t
*
14483 rs6000_stack_info (void)
14485 static rs6000_stack_t info
;
14486 rs6000_stack_t
*info_ptr
= &info
;
14487 int reg_size
= TARGET_32BIT
? 4 : 8;
14491 HOST_WIDE_INT non_fixed_size
;
14493 memset (&info
, 0, sizeof (info
));
14497 /* Cache value so we don't rescan instruction chain over and over. */
14498 if (cfun
->machine
->insn_chain_scanned_p
== 0)
14499 cfun
->machine
->insn_chain_scanned_p
14500 = spe_func_has_64bit_regs_p () + 1;
14501 info_ptr
->spe_64bit_regs_used
= cfun
->machine
->insn_chain_scanned_p
- 1;
14504 /* Select which calling sequence. */
14505 info_ptr
->abi
= DEFAULT_ABI
;
14507 /* Calculate which registers need to be saved & save area size. */
14508 info_ptr
->first_gp_reg_save
= first_reg_to_save ();
14509 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
14510 even if it currently looks like we won't. Reload may need it to
14511 get at a constant; if so, it will have already created a constant
14512 pool entry for it. */
14513 if (((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
14514 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
14515 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
14516 && crtl
->uses_const_pool
14517 && info_ptr
->first_gp_reg_save
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
14518 first_gp
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
14520 first_gp
= info_ptr
->first_gp_reg_save
;
14522 info_ptr
->gp_size
= reg_size
* (32 - first_gp
);
14524 /* For the SPE, we have an additional upper 32-bits on each GPR.
14525 Ideally we should save the entire 64-bits only when the upper
14526 half is used in SIMD instructions. Since we only record
14527 registers live (not the size they are used in), this proves
14528 difficult because we'd have to traverse the instruction chain at
14529 the right time, taking reload into account. This is a real pain,
14530 so we opt to save the GPRs in 64-bits always if but one register
14531 gets used in 64-bits. Otherwise, all the registers in the frame
14532 get saved in 32-bits.
14534 So... since when we save all GPRs (except the SP) in 64-bits, the
14535 traditional GP save area will be empty. */
14536 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
14537 info_ptr
->gp_size
= 0;
14539 info_ptr
->first_fp_reg_save
= first_fp_reg_to_save ();
14540 info_ptr
->fp_size
= 8 * (64 - info_ptr
->first_fp_reg_save
);
14542 info_ptr
->first_altivec_reg_save
= first_altivec_reg_to_save ();
14543 info_ptr
->altivec_size
= 16 * (LAST_ALTIVEC_REGNO
+ 1
14544 - info_ptr
->first_altivec_reg_save
);
14546 /* Does this function call anything? */
14547 info_ptr
->calls_p
= (! current_function_is_leaf
14548 || cfun
->machine
->ra_needs_full_frame
);
14550 /* Determine if we need to save the link register. */
14551 if ((DEFAULT_ABI
== ABI_AIX
14553 && !TARGET_PROFILE_KERNEL
)
14554 #ifdef TARGET_RELOCATABLE
14555 || (TARGET_RELOCATABLE
&& (get_pool_size () != 0))
14557 || (info_ptr
->first_fp_reg_save
!= 64
14558 && !FP_SAVE_INLINE (info_ptr
->first_fp_reg_save
))
14559 || (DEFAULT_ABI
== ABI_V4
&& cfun
->calls_alloca
)
14560 || info_ptr
->calls_p
14561 || rs6000_ra_ever_killed ())
14563 info_ptr
->lr_save_p
= 1;
14564 df_set_regs_ever_live (LR_REGNO
, true);
14567 /* Determine if we need to save the condition code registers. */
14568 if (df_regs_ever_live_p (CR2_REGNO
)
14569 || df_regs_ever_live_p (CR3_REGNO
)
14570 || df_regs_ever_live_p (CR4_REGNO
))
14572 info_ptr
->cr_save_p
= 1;
14573 if (DEFAULT_ABI
== ABI_V4
)
14574 info_ptr
->cr_size
= reg_size
;
14577 /* If the current function calls __builtin_eh_return, then we need
14578 to allocate stack space for registers that will hold data for
14579 the exception handler. */
14580 if (crtl
->calls_eh_return
)
14583 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
14586 /* SPE saves EH registers in 64-bits. */
14587 ehrd_size
= i
* (TARGET_SPE_ABI
14588 && info_ptr
->spe_64bit_regs_used
!= 0
14589 ? UNITS_PER_SPE_WORD
: UNITS_PER_WORD
);
14594 /* Determine various sizes. */
14595 info_ptr
->reg_size
= reg_size
;
14596 info_ptr
->fixed_size
= RS6000_SAVE_AREA
;
14597 info_ptr
->vars_size
= RS6000_ALIGN (get_frame_size (), 8);
14598 info_ptr
->parm_size
= RS6000_ALIGN (crtl
->outgoing_args_size
,
14599 TARGET_ALTIVEC
? 16 : 8);
14600 if (FRAME_GROWS_DOWNWARD
)
14601 info_ptr
->vars_size
14602 += RS6000_ALIGN (info_ptr
->fixed_size
+ info_ptr
->vars_size
14603 + info_ptr
->parm_size
,
14604 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
)
14605 - (info_ptr
->fixed_size
+ info_ptr
->vars_size
14606 + info_ptr
->parm_size
);
14608 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
14609 info_ptr
->spe_gp_size
= 8 * (32 - first_gp
);
14611 info_ptr
->spe_gp_size
= 0;
14613 if (TARGET_ALTIVEC_ABI
)
14614 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
14616 info_ptr
->vrsave_mask
= 0;
14618 if (TARGET_ALTIVEC_VRSAVE
&& info_ptr
->vrsave_mask
)
14619 info_ptr
->vrsave_size
= 4;
14621 info_ptr
->vrsave_size
= 0;
14623 compute_save_world_info (info_ptr
);
14625 /* Calculate the offsets. */
14626 switch (DEFAULT_ABI
)
14630 gcc_unreachable ();
14634 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
14635 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
14637 if (TARGET_ALTIVEC_ABI
)
14639 info_ptr
->vrsave_save_offset
14640 = info_ptr
->gp_save_offset
- info_ptr
->vrsave_size
;
14642 /* Align stack so vector save area is on a quadword boundary.
14643 The padding goes above the vectors. */
14644 if (info_ptr
->altivec_size
!= 0)
14645 info_ptr
->altivec_padding_size
14646 = info_ptr
->vrsave_save_offset
& 0xF;
14648 info_ptr
->altivec_padding_size
= 0;
14650 info_ptr
->altivec_save_offset
14651 = info_ptr
->vrsave_save_offset
14652 - info_ptr
->altivec_padding_size
14653 - info_ptr
->altivec_size
;
14654 gcc_assert (info_ptr
->altivec_size
== 0
14655 || info_ptr
->altivec_save_offset
% 16 == 0);
14657 /* Adjust for AltiVec case. */
14658 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
- ehrd_size
;
14661 info_ptr
->ehrd_offset
= info_ptr
->gp_save_offset
- ehrd_size
;
14662 info_ptr
->cr_save_offset
= reg_size
; /* first word when 64-bit. */
14663 info_ptr
->lr_save_offset
= 2*reg_size
;
14667 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
14668 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
14669 info_ptr
->cr_save_offset
= info_ptr
->gp_save_offset
- info_ptr
->cr_size
;
14671 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
14673 /* Align stack so SPE GPR save area is aligned on a
14674 double-word boundary. */
14675 if (info_ptr
->spe_gp_size
!= 0 && info_ptr
->cr_save_offset
!= 0)
14676 info_ptr
->spe_padding_size
14677 = 8 - (-info_ptr
->cr_save_offset
% 8);
14679 info_ptr
->spe_padding_size
= 0;
14681 info_ptr
->spe_gp_save_offset
14682 = info_ptr
->cr_save_offset
14683 - info_ptr
->spe_padding_size
14684 - info_ptr
->spe_gp_size
;
14686 /* Adjust for SPE case. */
14687 info_ptr
->ehrd_offset
= info_ptr
->spe_gp_save_offset
;
14689 else if (TARGET_ALTIVEC_ABI
)
14691 info_ptr
->vrsave_save_offset
14692 = info_ptr
->cr_save_offset
- info_ptr
->vrsave_size
;
14694 /* Align stack so vector save area is on a quadword boundary. */
14695 if (info_ptr
->altivec_size
!= 0)
14696 info_ptr
->altivec_padding_size
14697 = 16 - (-info_ptr
->vrsave_save_offset
% 16);
14699 info_ptr
->altivec_padding_size
= 0;
14701 info_ptr
->altivec_save_offset
14702 = info_ptr
->vrsave_save_offset
14703 - info_ptr
->altivec_padding_size
14704 - info_ptr
->altivec_size
;
14706 /* Adjust for AltiVec case. */
14707 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
;
14710 info_ptr
->ehrd_offset
= info_ptr
->cr_save_offset
;
14711 info_ptr
->ehrd_offset
-= ehrd_size
;
14712 info_ptr
->lr_save_offset
= reg_size
;
14716 save_align
= (TARGET_ALTIVEC_ABI
|| DEFAULT_ABI
== ABI_DARWIN
) ? 16 : 8;
14717 info_ptr
->save_size
= RS6000_ALIGN (info_ptr
->fp_size
14718 + info_ptr
->gp_size
14719 + info_ptr
->altivec_size
14720 + info_ptr
->altivec_padding_size
14721 + info_ptr
->spe_gp_size
14722 + info_ptr
->spe_padding_size
14724 + info_ptr
->cr_size
14725 + info_ptr
->vrsave_size
,
14728 non_fixed_size
= (info_ptr
->vars_size
14729 + info_ptr
->parm_size
14730 + info_ptr
->save_size
);
14732 info_ptr
->total_size
= RS6000_ALIGN (non_fixed_size
+ info_ptr
->fixed_size
,
14733 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
);
14735 /* Determine if we need to allocate any stack frame:
14737 For AIX we need to push the stack if a frame pointer is needed
14738 (because the stack might be dynamically adjusted), if we are
14739 debugging, if we make calls, or if the sum of fp_save, gp_save,
14740 and local variables are more than the space needed to save all
14741 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
14742 + 18*8 = 288 (GPR13 reserved).
14744 For V.4 we don't have the stack cushion that AIX uses, but assume
14745 that the debugger can handle stackless frames. */
14747 if (info_ptr
->calls_p
)
14748 info_ptr
->push_p
= 1;
14750 else if (DEFAULT_ABI
== ABI_V4
)
14751 info_ptr
->push_p
= non_fixed_size
!= 0;
14753 else if (frame_pointer_needed
)
14754 info_ptr
->push_p
= 1;
14756 else if (TARGET_XCOFF
&& write_symbols
!= NO_DEBUG
)
14757 info_ptr
->push_p
= 1;
14760 info_ptr
->push_p
= non_fixed_size
> (TARGET_32BIT
? 220 : 288);
14762 /* Zero offsets if we're not saving those registers. */
14763 if (info_ptr
->fp_size
== 0)
14764 info_ptr
->fp_save_offset
= 0;
14766 if (info_ptr
->gp_size
== 0)
14767 info_ptr
->gp_save_offset
= 0;
14769 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->altivec_size
== 0)
14770 info_ptr
->altivec_save_offset
= 0;
14772 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->vrsave_mask
== 0)
14773 info_ptr
->vrsave_save_offset
= 0;
14775 if (! TARGET_SPE_ABI
14776 || info_ptr
->spe_64bit_regs_used
== 0
14777 || info_ptr
->spe_gp_size
== 0)
14778 info_ptr
->spe_gp_save_offset
= 0;
14780 if (! info_ptr
->lr_save_p
)
14781 info_ptr
->lr_save_offset
= 0;
14783 if (! info_ptr
->cr_save_p
)
14784 info_ptr
->cr_save_offset
= 0;
14789 /* Return true if the current function uses any GPRs in 64-bit SIMD
14793 spe_func_has_64bit_regs_p (void)
14797 /* Functions that save and restore all the call-saved registers will
14798 need to save/restore the registers in 64-bits. */
14799 if (crtl
->calls_eh_return
14800 || cfun
->calls_setjmp
14801 || crtl
->has_nonlocal_goto
)
14804 insns
= get_insns ();
14806 for (insn
= NEXT_INSN (insns
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
14812 /* FIXME: This should be implemented with attributes...
14814 (set_attr "spe64" "true")....then,
14815 if (get_spe64(insn)) return true;
14817 It's the only reliable way to do the stuff below. */
14819 i
= PATTERN (insn
);
14820 if (GET_CODE (i
) == SET
)
14822 enum machine_mode mode
= GET_MODE (SET_SRC (i
));
14824 if (SPE_VECTOR_MODE (mode
))
14826 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
))
14836 debug_stack_info (rs6000_stack_t
*info
)
14838 const char *abi_string
;
14841 info
= rs6000_stack_info ();
14843 fprintf (stderr
, "\nStack information for function %s:\n",
14844 ((current_function_decl
&& DECL_NAME (current_function_decl
))
14845 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
14850 default: abi_string
= "Unknown"; break;
14851 case ABI_NONE
: abi_string
= "NONE"; break;
14852 case ABI_AIX
: abi_string
= "AIX"; break;
14853 case ABI_DARWIN
: abi_string
= "Darwin"; break;
14854 case ABI_V4
: abi_string
= "V.4"; break;
14857 fprintf (stderr
, "\tABI = %5s\n", abi_string
);
14859 if (TARGET_ALTIVEC_ABI
)
14860 fprintf (stderr
, "\tALTIVEC ABI extensions enabled.\n");
14862 if (TARGET_SPE_ABI
)
14863 fprintf (stderr
, "\tSPE ABI extensions enabled.\n");
14865 if (info
->first_gp_reg_save
!= 32)
14866 fprintf (stderr
, "\tfirst_gp_reg_save = %5d\n", info
->first_gp_reg_save
);
14868 if (info
->first_fp_reg_save
!= 64)
14869 fprintf (stderr
, "\tfirst_fp_reg_save = %5d\n", info
->first_fp_reg_save
);
14871 if (info
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
)
14872 fprintf (stderr
, "\tfirst_altivec_reg_save = %5d\n",
14873 info
->first_altivec_reg_save
);
14875 if (info
->lr_save_p
)
14876 fprintf (stderr
, "\tlr_save_p = %5d\n", info
->lr_save_p
);
14878 if (info
->cr_save_p
)
14879 fprintf (stderr
, "\tcr_save_p = %5d\n", info
->cr_save_p
);
14881 if (info
->vrsave_mask
)
14882 fprintf (stderr
, "\tvrsave_mask = 0x%x\n", info
->vrsave_mask
);
14885 fprintf (stderr
, "\tpush_p = %5d\n", info
->push_p
);
14888 fprintf (stderr
, "\tcalls_p = %5d\n", info
->calls_p
);
14890 if (info
->gp_save_offset
)
14891 fprintf (stderr
, "\tgp_save_offset = %5d\n", info
->gp_save_offset
);
14893 if (info
->fp_save_offset
)
14894 fprintf (stderr
, "\tfp_save_offset = %5d\n", info
->fp_save_offset
);
14896 if (info
->altivec_save_offset
)
14897 fprintf (stderr
, "\taltivec_save_offset = %5d\n",
14898 info
->altivec_save_offset
);
14900 if (info
->spe_gp_save_offset
)
14901 fprintf (stderr
, "\tspe_gp_save_offset = %5d\n",
14902 info
->spe_gp_save_offset
);
14904 if (info
->vrsave_save_offset
)
14905 fprintf (stderr
, "\tvrsave_save_offset = %5d\n",
14906 info
->vrsave_save_offset
);
14908 if (info
->lr_save_offset
)
14909 fprintf (stderr
, "\tlr_save_offset = %5d\n", info
->lr_save_offset
);
14911 if (info
->cr_save_offset
)
14912 fprintf (stderr
, "\tcr_save_offset = %5d\n", info
->cr_save_offset
);
14914 if (info
->varargs_save_offset
)
14915 fprintf (stderr
, "\tvarargs_save_offset = %5d\n", info
->varargs_save_offset
);
14917 if (info
->total_size
)
14918 fprintf (stderr
, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
14921 if (info
->vars_size
)
14922 fprintf (stderr
, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
14925 if (info
->parm_size
)
14926 fprintf (stderr
, "\tparm_size = %5d\n", info
->parm_size
);
14928 if (info
->fixed_size
)
14929 fprintf (stderr
, "\tfixed_size = %5d\n", info
->fixed_size
);
14932 fprintf (stderr
, "\tgp_size = %5d\n", info
->gp_size
);
14934 if (info
->spe_gp_size
)
14935 fprintf (stderr
, "\tspe_gp_size = %5d\n", info
->spe_gp_size
);
14938 fprintf (stderr
, "\tfp_size = %5d\n", info
->fp_size
);
14940 if (info
->altivec_size
)
14941 fprintf (stderr
, "\taltivec_size = %5d\n", info
->altivec_size
);
14943 if (info
->vrsave_size
)
14944 fprintf (stderr
, "\tvrsave_size = %5d\n", info
->vrsave_size
);
14946 if (info
->altivec_padding_size
)
14947 fprintf (stderr
, "\taltivec_padding_size= %5d\n",
14948 info
->altivec_padding_size
);
14950 if (info
->spe_padding_size
)
14951 fprintf (stderr
, "\tspe_padding_size = %5d\n",
14952 info
->spe_padding_size
);
14955 fprintf (stderr
, "\tcr_size = %5d\n", info
->cr_size
);
14957 if (info
->save_size
)
14958 fprintf (stderr
, "\tsave_size = %5d\n", info
->save_size
);
14960 if (info
->reg_size
!= 4)
14961 fprintf (stderr
, "\treg_size = %5d\n", info
->reg_size
);
14963 fprintf (stderr
, "\n");
14967 rs6000_return_addr (int count
, rtx frame
)
14969 /* Currently we don't optimize very well between prolog and body
14970 code and for PIC code the code can be actually quite bad, so
14971 don't try to be too clever here. */
14972 if (count
!= 0 || (DEFAULT_ABI
!= ABI_AIX
&& flag_pic
))
14974 cfun
->machine
->ra_needs_full_frame
= 1;
14981 plus_constant (copy_to_reg
14982 (gen_rtx_MEM (Pmode
,
14983 memory_address (Pmode
, frame
))),
14984 RETURN_ADDRESS_OFFSET
)));
14987 cfun
->machine
->ra_need_lr
= 1;
14988 return get_hard_reg_initial_val (Pmode
, LR_REGNO
);
14991 /* Say whether a function is a candidate for sibcall handling or not.
14992 We do not allow indirect calls to be optimized into sibling calls.
14993 Also, we can't do it if there are any vector parameters; there's
14994 nowhere to put the VRsave code so it works; note that functions with
14995 vector parameters are required to have a prototype, so the argument
14996 type info must be available here. (The tail recursion case can work
14997 with vector parameters, but there's no way to distinguish here.) */
14999 rs6000_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
15004 if (TARGET_ALTIVEC_VRSAVE
)
15006 for (type
= TYPE_ARG_TYPES (TREE_TYPE (decl
));
15007 type
; type
= TREE_CHAIN (type
))
15009 if (TREE_CODE (TREE_VALUE (type
)) == VECTOR_TYPE
)
15013 if (DEFAULT_ABI
== ABI_DARWIN
15014 || ((*targetm
.binds_local_p
) (decl
)
15015 && (DEFAULT_ABI
!= ABI_AIX
|| !DECL_EXTERNAL (decl
))))
15017 tree attr_list
= TYPE_ATTRIBUTES (TREE_TYPE (decl
));
15019 if (!lookup_attribute ("longcall", attr_list
)
15020 || lookup_attribute ("shortcall", attr_list
))
15027 /* NULL if INSN insn is valid within a low-overhead loop.
15028 Otherwise return why doloop cannot be applied.
15029 PowerPC uses the COUNT register for branch on table instructions. */
15031 static const char *
15032 rs6000_invalid_within_doloop (const_rtx insn
)
15035 return "Function call in the loop.";
15038 && (GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
15039 || GET_CODE (PATTERN (insn
)) == ADDR_VEC
))
15040 return "Computed branch in the loop.";
15046 rs6000_ra_ever_killed (void)
15052 if (crtl
->is_thunk
)
15055 /* regs_ever_live has LR marked as used if any sibcalls are present,
15056 but this should not force saving and restoring in the
15057 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
15058 clobbers LR, so that is inappropriate. */
15060 /* Also, the prologue can generate a store into LR that
15061 doesn't really count, like this:
15064 bcl to set PIC register
15068 When we're called from the epilogue, we need to avoid counting
15069 this as a store. */
15071 push_topmost_sequence ();
15072 top
= get_insns ();
15073 pop_topmost_sequence ();
15074 reg
= gen_rtx_REG (Pmode
, LR_REGNO
);
15076 for (insn
= NEXT_INSN (top
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
15082 if (!SIBLING_CALL_P (insn
))
15085 else if (find_regno_note (insn
, REG_INC
, LR_REGNO
))
15087 else if (set_of (reg
, insn
) != NULL_RTX
15088 && !prologue_epilogue_contains (insn
))
15095 /* Emit instructions needed to load the TOC register.
15096 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
15097 a constant pool; or for SVR4 -fpic. */
15100 rs6000_emit_load_toc_table (int fromprolog
)
15103 dest
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
15105 if (TARGET_ELF
&& TARGET_SECURE_PLT
&& DEFAULT_ABI
!= ABI_AIX
&& flag_pic
)
15108 rtx lab
, tmp1
, tmp2
, got
;
15110 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
15111 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
15113 got
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
15115 got
= rs6000_got_sym ();
15116 tmp1
= tmp2
= dest
;
15119 tmp1
= gen_reg_rtx (Pmode
);
15120 tmp2
= gen_reg_rtx (Pmode
);
15122 emit_insn (gen_load_toc_v4_PIC_1 (lab
));
15123 emit_move_insn (tmp1
,
15124 gen_rtx_REG (Pmode
, LR_REGNO
));
15125 emit_insn (gen_load_toc_v4_PIC_3b (tmp2
, tmp1
, got
, lab
));
15126 emit_insn (gen_load_toc_v4_PIC_3c (dest
, tmp2
, got
, lab
));
15128 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
15130 emit_insn (gen_load_toc_v4_pic_si ());
15131 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
15133 else if (TARGET_ELF
&& DEFAULT_ABI
!= ABI_AIX
&& flag_pic
== 2)
15136 rtx temp0
= (fromprolog
15137 ? gen_rtx_REG (Pmode
, 0)
15138 : gen_reg_rtx (Pmode
));
15144 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
15145 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
15147 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
15148 symL
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
15150 emit_insn (gen_load_toc_v4_PIC_1 (symF
));
15151 emit_move_insn (dest
,
15152 gen_rtx_REG (Pmode
, LR_REGNO
));
15153 emit_insn (gen_load_toc_v4_PIC_2 (temp0
, dest
, symL
, symF
));
15159 tocsym
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
15160 emit_insn (gen_load_toc_v4_PIC_1b (tocsym
));
15161 emit_move_insn (dest
,
15162 gen_rtx_REG (Pmode
, LR_REGNO
));
15163 emit_move_insn (temp0
, gen_rtx_MEM (Pmode
, dest
));
15165 emit_insn (gen_addsi3 (dest
, temp0
, dest
));
15167 else if (TARGET_ELF
&& !TARGET_AIX
&& flag_pic
== 0 && TARGET_MINIMAL_TOC
)
15169 /* This is for AIX code running in non-PIC ELF32. */
15172 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
15173 realsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
15175 emit_insn (gen_elf_high (dest
, realsym
));
15176 emit_insn (gen_elf_low (dest
, dest
, realsym
));
15180 gcc_assert (DEFAULT_ABI
== ABI_AIX
);
15183 emit_insn (gen_load_toc_aix_si (dest
));
15185 emit_insn (gen_load_toc_aix_di (dest
));
15189 /* Emit instructions to restore the link register after determining where
15190 its value has been stored. */
15193 rs6000_emit_eh_reg_restore (rtx source
, rtx scratch
)
15195 rs6000_stack_t
*info
= rs6000_stack_info ();
15198 operands
[0] = source
;
15199 operands
[1] = scratch
;
15201 if (info
->lr_save_p
)
15203 rtx frame_rtx
= stack_pointer_rtx
;
15204 HOST_WIDE_INT sp_offset
= 0;
15207 if (frame_pointer_needed
15208 || cfun
->calls_alloca
15209 || info
->total_size
> 32767)
15211 tmp
= gen_frame_mem (Pmode
, frame_rtx
);
15212 emit_move_insn (operands
[1], tmp
);
15213 frame_rtx
= operands
[1];
15215 else if (info
->push_p
)
15216 sp_offset
= info
->total_size
;
15218 tmp
= plus_constant (frame_rtx
, info
->lr_save_offset
+ sp_offset
);
15219 tmp
= gen_frame_mem (Pmode
, tmp
);
15220 emit_move_insn (tmp
, operands
[0]);
15223 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
), operands
[0]);
15226 static GTY(()) alias_set_type set
= -1;
15229 get_TOC_alias_set (void)
15232 set
= new_alias_set ();
15236 /* This returns nonzero if the current function uses the TOC. This is
15237 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
15238 is generated by the ABI_V4 load_toc_* patterns. */
15245 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
15248 rtx pat
= PATTERN (insn
);
15251 if (GET_CODE (pat
) == PARALLEL
)
15252 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
15254 rtx sub
= XVECEXP (pat
, 0, i
);
15255 if (GET_CODE (sub
) == USE
)
15257 sub
= XEXP (sub
, 0);
15258 if (GET_CODE (sub
) == UNSPEC
15259 && XINT (sub
, 1) == UNSPEC_TOC
)
15269 create_TOC_reference (rtx symbol
)
15271 if (!can_create_pseudo_p ())
15272 df_set_regs_ever_live (TOC_REGISTER
, true);
15273 return gen_rtx_PLUS (Pmode
,
15274 gen_rtx_REG (Pmode
, TOC_REGISTER
),
15275 gen_rtx_CONST (Pmode
,
15276 gen_rtx_MINUS (Pmode
, symbol
,
15277 gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
))));
15280 /* If _Unwind_* has been called from within the same module,
15281 toc register is not guaranteed to be saved to 40(1) on function
15282 entry. Save it there in that case. */
15285 rs6000_aix_emit_builtin_unwind_init (void)
15288 rtx stack_top
= gen_reg_rtx (Pmode
);
15289 rtx opcode_addr
= gen_reg_rtx (Pmode
);
15290 rtx opcode
= gen_reg_rtx (SImode
);
15291 rtx tocompare
= gen_reg_rtx (SImode
);
15292 rtx no_toc_save_needed
= gen_label_rtx ();
15294 mem
= gen_frame_mem (Pmode
, hard_frame_pointer_rtx
);
15295 emit_move_insn (stack_top
, mem
);
15297 mem
= gen_frame_mem (Pmode
,
15298 gen_rtx_PLUS (Pmode
, stack_top
,
15299 GEN_INT (2 * GET_MODE_SIZE (Pmode
))));
15300 emit_move_insn (opcode_addr
, mem
);
15301 emit_move_insn (opcode
, gen_rtx_MEM (SImode
, opcode_addr
));
15302 emit_move_insn (tocompare
, gen_int_mode (TARGET_32BIT
? 0x80410014
15303 : 0xE8410028, SImode
));
15305 do_compare_rtx_and_jump (opcode
, tocompare
, EQ
, 1,
15306 SImode
, NULL_RTX
, NULL_RTX
,
15307 no_toc_save_needed
);
15309 mem
= gen_frame_mem (Pmode
,
15310 gen_rtx_PLUS (Pmode
, stack_top
,
15311 GEN_INT (5 * GET_MODE_SIZE (Pmode
))));
15312 emit_move_insn (mem
, gen_rtx_REG (Pmode
, 2));
15313 emit_label (no_toc_save_needed
);
15316 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
15317 and the change to the stack pointer. */
15320 rs6000_emit_stack_tie (void)
15322 rtx mem
= gen_frame_mem (BLKmode
,
15323 gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
));
15325 emit_insn (gen_stack_tie (mem
));
15328 /* Emit the correct code for allocating stack space, as insns.
15329 If COPY_R12, make sure a copy of the old frame is left in r12.
15330 If COPY_R11, make sure a copy of the old frame is left in r11,
15331 in preference to r12 if COPY_R12.
15332 The generated code may use hard register 0 as a temporary. */
15335 rs6000_emit_allocate_stack (HOST_WIDE_INT size
, int copy_r12
, int copy_r11
)
15338 rtx stack_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
15339 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
15340 rtx todec
= gen_int_mode (-size
, Pmode
);
15342 if (INTVAL (todec
) != -size
)
15344 warning (0, "stack frame too large");
15345 emit_insn (gen_trap ());
15349 if (crtl
->limit_stack
)
15351 if (REG_P (stack_limit_rtx
)
15352 && REGNO (stack_limit_rtx
) > 1
15353 && REGNO (stack_limit_rtx
) <= 31)
15355 emit_insn (TARGET_32BIT
15356 ? gen_addsi3 (tmp_reg
,
15359 : gen_adddi3 (tmp_reg
,
15363 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
15366 else if (GET_CODE (stack_limit_rtx
) == SYMBOL_REF
15368 && DEFAULT_ABI
== ABI_V4
)
15370 rtx toload
= gen_rtx_CONST (VOIDmode
,
15371 gen_rtx_PLUS (Pmode
,
15375 emit_insn (gen_elf_high (tmp_reg
, toload
));
15376 emit_insn (gen_elf_low (tmp_reg
, tmp_reg
, toload
));
15377 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
15381 warning (0, "stack limit expression is not supported");
15384 if (copy_r12
|| copy_r11
|| ! TARGET_UPDATE
)
15385 emit_move_insn (copy_r11
15386 ? gen_rtx_REG (Pmode
, 11)
15387 : gen_rtx_REG (Pmode
, 12),
15394 /* Need a note here so that try_split doesn't get confused. */
15395 if (get_last_insn () == NULL_RTX
)
15396 emit_note (NOTE_INSN_DELETED
);
15397 insn
= emit_move_insn (tmp_reg
, todec
);
15398 try_split (PATTERN (insn
), insn
, 0);
15402 insn
= emit_insn (TARGET_32BIT
15403 ? gen_movsi_update (stack_reg
, stack_reg
,
15405 : gen_movdi_di_update (stack_reg
, stack_reg
,
15406 todec
, stack_reg
));
15410 insn
= emit_insn (TARGET_32BIT
15411 ? gen_addsi3 (stack_reg
, stack_reg
, todec
)
15412 : gen_adddi3 (stack_reg
, stack_reg
, todec
));
15413 emit_move_insn (gen_rtx_MEM (Pmode
, stack_reg
),
15415 ? gen_rtx_REG (Pmode
, 11)
15416 : gen_rtx_REG (Pmode
, 12));
15419 RTX_FRAME_RELATED_P (insn
) = 1;
15421 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
15422 gen_rtx_SET (VOIDmode
, stack_reg
,
15423 gen_rtx_PLUS (Pmode
, stack_reg
,
15428 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
15429 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
15430 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
15431 deduce these equivalences by itself so it wasn't necessary to hold
15432 its hand so much. */
15435 rs6000_frame_related (rtx insn
, rtx reg
, HOST_WIDE_INT val
,
15436 rtx reg2
, rtx rreg
)
15440 /* copy_rtx will not make unique copies of registers, so we need to
15441 ensure we don't have unwanted sharing here. */
15443 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
15446 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
15448 real
= copy_rtx (PATTERN (insn
));
15450 if (reg2
!= NULL_RTX
)
15451 real
= replace_rtx (real
, reg2
, rreg
);
15453 real
= replace_rtx (real
, reg
,
15454 gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
,
15455 STACK_POINTER_REGNUM
),
15458 /* We expect that 'real' is either a SET or a PARALLEL containing
15459 SETs (and possibly other stuff). In a PARALLEL, all the SETs
15460 are important so they all have to be marked RTX_FRAME_RELATED_P. */
15462 if (GET_CODE (real
) == SET
)
15466 temp
= simplify_rtx (SET_SRC (set
));
15468 SET_SRC (set
) = temp
;
15469 temp
= simplify_rtx (SET_DEST (set
));
15471 SET_DEST (set
) = temp
;
15472 if (GET_CODE (SET_DEST (set
)) == MEM
)
15474 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
15476 XEXP (SET_DEST (set
), 0) = temp
;
15483 gcc_assert (GET_CODE (real
) == PARALLEL
);
15484 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
15485 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
15487 rtx set
= XVECEXP (real
, 0, i
);
15489 temp
= simplify_rtx (SET_SRC (set
));
15491 SET_SRC (set
) = temp
;
15492 temp
= simplify_rtx (SET_DEST (set
));
15494 SET_DEST (set
) = temp
;
15495 if (GET_CODE (SET_DEST (set
)) == MEM
)
15497 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
15499 XEXP (SET_DEST (set
), 0) = temp
;
15501 RTX_FRAME_RELATED_P (set
) = 1;
15505 RTX_FRAME_RELATED_P (insn
) = 1;
15506 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
15511 /* Returns an insn that has a vrsave set operation with the
15512 appropriate CLOBBERs. */
15515 generate_set_vrsave (rtx reg
, rs6000_stack_t
*info
, int epiloguep
)
15518 rtx insn
, clobs
[TOTAL_ALTIVEC_REGS
+ 1];
15519 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
15522 = gen_rtx_SET (VOIDmode
,
15524 gen_rtx_UNSPEC_VOLATILE (SImode
,
15525 gen_rtvec (2, reg
, vrsave
),
15526 UNSPECV_SET_VRSAVE
));
15530 /* We need to clobber the registers in the mask so the scheduler
15531 does not move sets to VRSAVE before sets of AltiVec registers.
15533 However, if the function receives nonlocal gotos, reload will set
15534 all call saved registers live. We will end up with:
15536 (set (reg 999) (mem))
15537 (parallel [ (set (reg vrsave) (unspec blah))
15538 (clobber (reg 999))])
15540 The clobber will cause the store into reg 999 to be dead, and
15541 flow will attempt to delete an epilogue insn. In this case, we
15542 need an unspec use/set of the register. */
15544 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
15545 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
15547 if (!epiloguep
|| call_used_regs
[i
])
15548 clobs
[nclobs
++] = gen_rtx_CLOBBER (VOIDmode
,
15549 gen_rtx_REG (V4SImode
, i
));
15552 rtx reg
= gen_rtx_REG (V4SImode
, i
);
15555 = gen_rtx_SET (VOIDmode
,
15557 gen_rtx_UNSPEC (V4SImode
,
15558 gen_rtvec (1, reg
), 27));
15562 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nclobs
));
15564 for (i
= 0; i
< nclobs
; ++i
)
15565 XVECEXP (insn
, 0, i
) = clobs
[i
];
15570 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
15571 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
15574 emit_frame_save (rtx frame_reg
, rtx frame_ptr
, enum machine_mode mode
,
15575 unsigned int regno
, int offset
, HOST_WIDE_INT total_size
)
15577 rtx reg
, offset_rtx
, insn
, mem
, addr
, int_rtx
;
15578 rtx replacea
, replaceb
;
15580 int_rtx
= GEN_INT (offset
);
15582 /* Some cases that need register indexed addressing. */
15583 if ((TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
15584 || (TARGET_E500_DOUBLE
&& mode
== DFmode
)
15586 && SPE_VECTOR_MODE (mode
)
15587 && !SPE_CONST_OFFSET_OK (offset
)))
15589 /* Whomever calls us must make sure r11 is available in the
15590 flow path of instructions in the prologue. */
15591 offset_rtx
= gen_rtx_REG (Pmode
, 11);
15592 emit_move_insn (offset_rtx
, int_rtx
);
15594 replacea
= offset_rtx
;
15595 replaceb
= int_rtx
;
15599 offset_rtx
= int_rtx
;
15600 replacea
= NULL_RTX
;
15601 replaceb
= NULL_RTX
;
15604 reg
= gen_rtx_REG (mode
, regno
);
15605 addr
= gen_rtx_PLUS (Pmode
, frame_reg
, offset_rtx
);
15606 mem
= gen_frame_mem (mode
, addr
);
15608 insn
= emit_move_insn (mem
, reg
);
15610 rs6000_frame_related (insn
, frame_ptr
, total_size
, replacea
, replaceb
);
15613 /* Emit an offset memory reference suitable for a frame store, while
15614 converting to a valid addressing mode. */
15617 gen_frame_mem_offset (enum machine_mode mode
, rtx reg
, int offset
)
15619 rtx int_rtx
, offset_rtx
;
15621 int_rtx
= GEN_INT (offset
);
15623 if ((TARGET_SPE_ABI
&& SPE_VECTOR_MODE (mode
))
15624 || (TARGET_E500_DOUBLE
&& mode
== DFmode
))
15626 offset_rtx
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
15627 emit_move_insn (offset_rtx
, int_rtx
);
15630 offset_rtx
= int_rtx
;
15632 return gen_frame_mem (mode
, gen_rtx_PLUS (Pmode
, reg
, offset_rtx
));
15635 /* Look for user-defined global regs. We should not save and restore these,
15636 and cannot use stmw/lmw if there are any in its range. */
15639 no_global_regs_above (int first
, bool gpr
)
15642 for (i
= first
; i
< gpr
? 32 : 64 ; i
++)
15643 if (global_regs
[i
])
15648 #ifndef TARGET_FIX_AND_CONTINUE
15649 #define TARGET_FIX_AND_CONTINUE 0
15652 /* It's really GPR 13 and FPR 14, but we need the smaller of the two. */
15653 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
15654 #define LAST_SAVRES_REGISTER 31
15655 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
15657 static GTY(()) rtx savres_routine_syms
[N_SAVRES_REGISTERS
][8];
15659 /* Return the symbol for an out-of-line register save/restore routine.
15660 We are saving/restoring GPRs if GPR is true. */
15663 rs6000_savres_routine_sym (rs6000_stack_t
*info
, bool savep
, bool gpr
, bool exitp
)
15665 int regno
= gpr
? info
->first_gp_reg_save
: (info
->first_fp_reg_save
- 32);
15667 int select
= ((savep
? 1 : 0) << 2
15669 /* On the SPE, we never have any FPRs, but we do have
15670 32/64-bit versions of the routines. */
15671 ? (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
? 1 : 0)
15675 /* Don't generate bogus routine names. */
15676 gcc_assert (FIRST_SAVRES_REGISTER
<= regno
&& regno
<= LAST_SAVRES_REGISTER
);
15678 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
];
15683 const char *action
;
15684 const char *regkind
;
15685 const char *exit_suffix
;
15687 action
= savep
? "save" : "rest";
15689 /* SPE has slightly different names for its routines depending on
15690 whether we are saving 32-bit or 64-bit registers. */
15691 if (TARGET_SPE_ABI
)
15693 /* No floating point saves on the SPE. */
15696 regkind
= info
->spe_64bit_regs_used
? "64gpr" : "32gpr";
15699 regkind
= gpr
? "gpr" : "fpr";
15701 exit_suffix
= exitp
? "_x" : "";
15703 sprintf (name
, "_%s%s_%d%s", action
, regkind
, regno
, exit_suffix
);
15705 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
]
15706 = gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
15712 /* Emit a sequence of insns, including a stack tie if needed, for
15713 resetting the stack pointer. If SAVRES is true, then don't reset the
15714 stack pointer, but move the base of the frame into r11 for use by
15715 out-of-line register restore routines. */
15718 rs6000_emit_stack_reset (rs6000_stack_t
*info
,
15719 rtx sp_reg_rtx
, rtx frame_reg_rtx
,
15720 int sp_offset
, bool savres
)
15722 /* This blockage is needed so that sched doesn't decide to move
15723 the sp change before the register restores. */
15724 if (frame_reg_rtx
!= sp_reg_rtx
15726 && info
->spe_64bit_regs_used
!= 0
15727 && info
->first_gp_reg_save
!= 32))
15728 rs6000_emit_stack_tie ();
15730 if (frame_reg_rtx
!= sp_reg_rtx
)
15732 rs6000_emit_stack_tie ();
15733 if (sp_offset
!= 0)
15734 emit_insn (gen_addsi3 (sp_reg_rtx
, frame_reg_rtx
,
15735 GEN_INT (sp_offset
)));
15737 emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
15739 else if (sp_offset
!= 0)
15741 /* If we are restoring registers out-of-line, we will be using the
15742 "exit" variants of the restore routines, which will reset the
15743 stack for us. But we do need to point r11 into the right place
15744 for those routines. */
15745 rtx dest_reg
= (savres
15746 ? gen_rtx_REG (Pmode
, 11)
15749 emit_insn (TARGET_32BIT
15750 ? gen_addsi3 (dest_reg
, sp_reg_rtx
,
15751 GEN_INT (sp_offset
))
15752 : gen_adddi3 (dest_reg
, sp_reg_rtx
,
15753 GEN_INT (sp_offset
)));
15757 /* Construct a parallel rtx describing the effect of a call to an
15758 out-of-line register save/restore routine. */
15761 rs6000_make_savres_rtx (rs6000_stack_t
*info
,
15762 rtx frame_reg_rtx
, int save_area_offset
,
15763 enum machine_mode reg_mode
,
15764 bool savep
, bool gpr
, bool exitp
)
15767 int offset
, start_reg
, end_reg
, n_regs
;
15768 int reg_size
= GET_MODE_SIZE (reg_mode
);
15774 ? info
->first_gp_reg_save
15775 : info
->first_fp_reg_save
);
15776 end_reg
= gpr
? 32 : 64;
15777 n_regs
= end_reg
- start_reg
;
15778 p
= rtvec_alloc ((exitp
? 4 : 3) + n_regs
);
15780 /* If we're saving registers, then we should never say we're exiting. */
15781 gcc_assert ((savep
&& !exitp
) || !savep
);
15784 RTVEC_ELT (p
, offset
++) = gen_rtx_RETURN (VOIDmode
);
15786 RTVEC_ELT (p
, offset
++)
15787 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 65));
15789 sym
= rs6000_savres_routine_sym (info
, savep
, gpr
, exitp
);
15790 RTVEC_ELT (p
, offset
++) = gen_rtx_USE (VOIDmode
, sym
);
15791 RTVEC_ELT (p
, offset
++) = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 11));
15793 for (i
= 0; i
< end_reg
- start_reg
; i
++)
15795 rtx addr
, reg
, mem
;
15796 reg
= gen_rtx_REG (reg_mode
, start_reg
+ i
);
15797 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
15798 GEN_INT (save_area_offset
+ reg_size
*i
));
15799 mem
= gen_frame_mem (reg_mode
, addr
);
15801 RTVEC_ELT (p
, i
+ offset
) = gen_rtx_SET (VOIDmode
,
15803 savep
? reg
: mem
);
15806 return gen_rtx_PARALLEL (VOIDmode
, p
);
15809 /* Determine whether the gp REG is really used. */
15812 rs6000_reg_live_or_pic_offset_p (int reg
)
15814 return ((df_regs_ever_live_p (reg
)
15815 && (!call_used_regs
[reg
]
15816 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
15817 && TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
15818 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
15819 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
15820 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
))));
15824 SAVRES_MULTIPLE
= 0x1,
15825 SAVRES_INLINE_FPRS
= 0x2,
15826 SAVRES_INLINE_GPRS
= 0x4
15829 /* Determine the strategy for savings/restoring registers. */
15832 rs6000_savres_strategy (rs6000_stack_t
*info
, bool savep
,
15833 int using_static_chain_p
, int sibcall
)
15835 bool using_multiple_p
;
15837 bool savres_fprs_inline
;
15838 bool savres_gprs_inline
;
15839 bool noclobber_global_gprs
15840 = no_global_regs_above (info
->first_gp_reg_save
, /*gpr=*/true);
15842 using_multiple_p
= (TARGET_MULTIPLE
&& ! TARGET_POWERPC64
15843 && (!TARGET_SPE_ABI
15844 || info
->spe_64bit_regs_used
== 0)
15845 && info
->first_gp_reg_save
< 31
15846 && noclobber_global_gprs
);
15847 /* Don't bother to try to save things out-of-line if r11 is occupied
15848 by the static chain. It would require too much fiddling and the
15849 static chain is rarely used anyway. */
15850 common
= (using_static_chain_p
15852 || crtl
->calls_eh_return
15853 || !info
->lr_save_p
15854 || cfun
->machine
->ra_need_lr
15855 || info
->total_size
> 32767);
15856 savres_fprs_inline
= (common
15857 || info
->first_fp_reg_save
== 64
15858 || !no_global_regs_above (info
->first_fp_reg_save
,
15860 || FP_SAVE_INLINE (info
->first_fp_reg_save
));
15861 savres_gprs_inline
= (common
15862 /* Saving CR interferes with the exit routines
15863 used on the SPE, so just punt here. */
15866 && info
->spe_64bit_regs_used
!= 0
15867 && info
->cr_save_p
!= 0)
15868 || info
->first_gp_reg_save
== 32
15869 || !noclobber_global_gprs
15870 || GP_SAVE_INLINE (info
->first_gp_reg_save
));
15873 /* If we are going to use store multiple, then don't even bother
15874 with the out-of-line routines, since the store-multiple instruction
15875 will always be smaller. */
15876 savres_gprs_inline
= savres_gprs_inline
|| using_multiple_p
;
15879 /* The situation is more complicated with load multiple. We'd
15880 prefer to use the out-of-line routines for restores, since the
15881 "exit" out-of-line routines can handle the restore of LR and
15882 the frame teardown. But we can only use the out-of-line
15883 routines if we know that we've used store multiple or
15884 out-of-line routines in the prologue, i.e. if we've saved all
15885 the registers from first_gp_reg_save. Otherwise, we risk
15886 loading garbage from the stack. Furthermore, we can only use
15887 the "exit" out-of-line gpr restore if we haven't saved any
15889 bool saved_all
= !savres_gprs_inline
|| using_multiple_p
;
15891 if (saved_all
&& info
->first_fp_reg_save
!= 64)
15892 /* We can't use the exit routine; use load multiple if it's
15894 savres_gprs_inline
= savres_gprs_inline
|| using_multiple_p
;
15897 return (using_multiple_p
15898 | (savres_fprs_inline
<< 1)
15899 | (savres_gprs_inline
<< 2));
15902 /* Emit function prologue as insns. */
15905 rs6000_emit_prologue (void)
15907 rs6000_stack_t
*info
= rs6000_stack_info ();
15908 enum machine_mode reg_mode
= Pmode
;
15909 int reg_size
= TARGET_32BIT
? 4 : 8;
15910 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
15911 rtx frame_ptr_rtx
= gen_rtx_REG (Pmode
, 12);
15912 rtx frame_reg_rtx
= sp_reg_rtx
;
15913 rtx cr_save_rtx
= NULL_RTX
;
15916 int saving_FPRs_inline
;
15917 int saving_GPRs_inline
;
15918 int using_store_multiple
;
15919 int using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
15920 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
15921 && !call_used_regs
[STATIC_CHAIN_REGNUM
]);
15922 HOST_WIDE_INT sp_offset
= 0;
15924 if (TARGET_FIX_AND_CONTINUE
)
15926 /* gdb on darwin arranges to forward a function from the old
15927 address by modifying the first 5 instructions of the function
15928 to branch to the overriding function. This is necessary to
15929 permit function pointers that point to the old function to
15930 actually forward to the new function. */
15931 emit_insn (gen_nop ());
15932 emit_insn (gen_nop ());
15933 emit_insn (gen_nop ());
15934 emit_insn (gen_nop ());
15935 emit_insn (gen_nop ());
15938 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
15940 reg_mode
= V2SImode
;
15944 strategy
= rs6000_savres_strategy (info
, /*savep=*/true,
15945 /*static_chain_p=*/using_static_chain_p
,
15947 using_store_multiple
= strategy
& SAVRES_MULTIPLE
;
15948 saving_FPRs_inline
= strategy
& SAVRES_INLINE_FPRS
;
15949 saving_GPRs_inline
= strategy
& SAVRES_INLINE_GPRS
;
15951 /* For V.4, update stack before we do any saving and set back pointer. */
15952 if (! WORLD_SAVE_P (info
)
15954 && (DEFAULT_ABI
== ABI_V4
15955 || crtl
->calls_eh_return
))
15957 bool need_r11
= (TARGET_SPE
15958 ? (!saving_GPRs_inline
15959 && info
->spe_64bit_regs_used
== 0)
15960 : (!saving_FPRs_inline
|| !saving_GPRs_inline
));
15961 if (info
->total_size
< 32767)
15962 sp_offset
= info
->total_size
;
15964 frame_reg_rtx
= (need_r11
15965 ? gen_rtx_REG (Pmode
, 11)
15967 rs6000_emit_allocate_stack (info
->total_size
,
15968 (frame_reg_rtx
!= sp_reg_rtx
15969 && (info
->cr_save_p
15971 || info
->first_fp_reg_save
< 64
15972 || info
->first_gp_reg_save
< 32
15975 if (frame_reg_rtx
!= sp_reg_rtx
)
15976 rs6000_emit_stack_tie ();
15979 /* Handle world saves specially here. */
15980 if (WORLD_SAVE_P (info
))
15987 /* save_world expects lr in r0. */
15988 reg0
= gen_rtx_REG (Pmode
, 0);
15989 if (info
->lr_save_p
)
15991 insn
= emit_move_insn (reg0
,
15992 gen_rtx_REG (Pmode
, LR_REGNO
));
15993 RTX_FRAME_RELATED_P (insn
) = 1;
15996 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
15997 assumptions about the offsets of various bits of the stack
15999 gcc_assert (info
->gp_save_offset
== -220
16000 && info
->fp_save_offset
== -144
16001 && info
->lr_save_offset
== 8
16002 && info
->cr_save_offset
== 4
16005 && (!crtl
->calls_eh_return
16006 || info
->ehrd_offset
== -432)
16007 && info
->vrsave_save_offset
== -224
16008 && info
->altivec_save_offset
== -416);
16010 treg
= gen_rtx_REG (SImode
, 11);
16011 emit_move_insn (treg
, GEN_INT (-info
->total_size
));
16013 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
16014 in R11. It also clobbers R12, so beware! */
16016 /* Preserve CR2 for save_world prologues */
16018 sz
+= 32 - info
->first_gp_reg_save
;
16019 sz
+= 64 - info
->first_fp_reg_save
;
16020 sz
+= LAST_ALTIVEC_REGNO
- info
->first_altivec_reg_save
+ 1;
16021 p
= rtvec_alloc (sz
);
16023 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
,
16024 gen_rtx_REG (SImode
,
16026 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
16027 gen_rtx_SYMBOL_REF (Pmode
,
16029 /* We do floats first so that the instruction pattern matches
16031 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
16033 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
16034 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16035 GEN_INT (info
->fp_save_offset
16036 + sp_offset
+ 8 * i
));
16037 rtx mem
= gen_frame_mem (DFmode
, addr
);
16039 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
16041 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
16043 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
16044 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16045 GEN_INT (info
->altivec_save_offset
16046 + sp_offset
+ 16 * i
));
16047 rtx mem
= gen_frame_mem (V4SImode
, addr
);
16049 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
16051 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
16053 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
16054 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16055 GEN_INT (info
->gp_save_offset
16056 + sp_offset
+ reg_size
* i
));
16057 rtx mem
= gen_frame_mem (reg_mode
, addr
);
16059 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
16063 /* CR register traditionally saved as CR2. */
16064 rtx reg
= gen_rtx_REG (reg_mode
, CR2_REGNO
);
16065 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16066 GEN_INT (info
->cr_save_offset
16068 rtx mem
= gen_frame_mem (reg_mode
, addr
);
16070 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
16072 /* Explain about use of R0. */
16073 if (info
->lr_save_p
)
16075 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16076 GEN_INT (info
->lr_save_offset
16078 rtx mem
= gen_frame_mem (reg_mode
, addr
);
16080 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg0
);
16082 /* Explain what happens to the stack pointer. */
16084 rtx newval
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
, treg
);
16085 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, sp_reg_rtx
, newval
);
16088 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
16089 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
16090 treg
, GEN_INT (-info
->total_size
));
16091 sp_offset
= info
->total_size
;
16094 /* If we use the link register, get it into r0. */
16095 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
)
16097 rtx addr
, reg
, mem
;
16099 insn
= emit_move_insn (gen_rtx_REG (Pmode
, 0),
16100 gen_rtx_REG (Pmode
, LR_REGNO
));
16101 RTX_FRAME_RELATED_P (insn
) = 1;
16103 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16104 GEN_INT (info
->lr_save_offset
+ sp_offset
));
16105 reg
= gen_rtx_REG (Pmode
, 0);
16106 mem
= gen_rtx_MEM (Pmode
, addr
);
16107 /* This should not be of rs6000_sr_alias_set, because of
16108 __builtin_return_address. */
16110 insn
= emit_move_insn (mem
, reg
);
16111 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
16112 NULL_RTX
, NULL_RTX
);
16115 /* If we need to save CR, put it into r12. */
16116 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
&& frame_reg_rtx
!= frame_ptr_rtx
)
16120 cr_save_rtx
= gen_rtx_REG (SImode
, 12);
16121 insn
= emit_insn (gen_movesi_from_cr (cr_save_rtx
));
16122 RTX_FRAME_RELATED_P (insn
) = 1;
16123 /* Now, there's no way that dwarf2out_frame_debug_expr is going
16124 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
16125 But that's OK. All we have to do is specify that _one_ condition
16126 code register is saved in this stack slot. The thrower's epilogue
16127 will then restore all the call-saved registers.
16128 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
16129 set
= gen_rtx_SET (VOIDmode
, cr_save_rtx
,
16130 gen_rtx_REG (SImode
, CR2_REGNO
));
16131 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
16136 /* Do any required saving of fpr's. If only one or two to save, do
16137 it ourselves. Otherwise, call function. */
16138 if (!WORLD_SAVE_P (info
) && saving_FPRs_inline
)
16141 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
16142 if ((df_regs_ever_live_p (info
->first_fp_reg_save
+i
)
16143 && ! call_used_regs
[info
->first_fp_reg_save
+i
]))
16144 emit_frame_save (frame_reg_rtx
, frame_ptr_rtx
, DFmode
,
16145 info
->first_fp_reg_save
+ i
,
16146 info
->fp_save_offset
+ sp_offset
+ 8 * i
,
16149 else if (!WORLD_SAVE_P (info
) && info
->first_fp_reg_save
!= 64)
16153 par
= rs6000_make_savres_rtx (info
, frame_reg_rtx
,
16154 info
->fp_save_offset
+ sp_offset
,
16156 /*savep=*/true, /*gpr=*/false,
16158 insn
= emit_insn (par
);
16159 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
16160 NULL_RTX
, NULL_RTX
);
16163 /* Save GPRs. This is done as a PARALLEL if we are using
16164 the store-multiple instructions. */
16165 if (!WORLD_SAVE_P (info
)
16167 && info
->spe_64bit_regs_used
!= 0
16168 && info
->first_gp_reg_save
!= 32)
16171 rtx spe_save_area_ptr
;
16173 /* Determine whether we can address all of the registers that need
16174 to be saved with an offset from the stack pointer that fits in
16175 the small const field for SPE memory instructions. */
16176 int spe_regs_addressable_via_sp
16177 = (SPE_CONST_OFFSET_OK(info
->spe_gp_save_offset
+ sp_offset
16178 + (32 - info
->first_gp_reg_save
- 1) * reg_size
)
16179 && saving_GPRs_inline
);
16182 if (spe_regs_addressable_via_sp
)
16184 spe_save_area_ptr
= frame_reg_rtx
;
16185 spe_offset
= info
->spe_gp_save_offset
+ sp_offset
;
16189 /* Make r11 point to the start of the SPE save area. We need
16190 to be careful here if r11 is holding the static chain. If
16191 it is, then temporarily save it in r0. We would use r0 as
16192 our base register here, but using r0 as a base register in
16193 loads and stores means something different from what we
16195 int ool_adjust
= (saving_GPRs_inline
16197 : (info
->first_gp_reg_save
16198 - (FIRST_SAVRES_REGISTER
+1))*8);
16199 HOST_WIDE_INT offset
= (info
->spe_gp_save_offset
16200 + sp_offset
- ool_adjust
);
16202 if (using_static_chain_p
)
16204 rtx r0
= gen_rtx_REG (Pmode
, 0);
16205 gcc_assert (info
->first_gp_reg_save
> 11);
16207 emit_move_insn (r0
, gen_rtx_REG (Pmode
, 11));
16210 spe_save_area_ptr
= gen_rtx_REG (Pmode
, 11);
16211 insn
= emit_insn (gen_addsi3 (spe_save_area_ptr
,
16213 GEN_INT (offset
)));
16214 /* We need to make sure the move to r11 gets noted for
16215 properly outputting unwind information. */
16216 if (!saving_GPRs_inline
)
16217 rs6000_frame_related (insn
, frame_reg_rtx
, offset
,
16218 NULL_RTX
, NULL_RTX
);
16222 if (saving_GPRs_inline
)
16224 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
16225 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
16227 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
16228 rtx offset
, addr
, mem
;
16230 /* We're doing all this to ensure that the offset fits into
16231 the immediate offset of 'evstdd'. */
16232 gcc_assert (SPE_CONST_OFFSET_OK (reg_size
* i
+ spe_offset
));
16234 offset
= GEN_INT (reg_size
* i
+ spe_offset
);
16235 addr
= gen_rtx_PLUS (Pmode
, spe_save_area_ptr
, offset
);
16236 mem
= gen_rtx_MEM (V2SImode
, addr
);
16238 insn
= emit_move_insn (mem
, reg
);
16240 rs6000_frame_related (insn
, spe_save_area_ptr
,
16241 info
->spe_gp_save_offset
16242 + sp_offset
+ reg_size
* i
,
16243 offset
, const0_rtx
);
16250 par
= rs6000_make_savres_rtx (info
, gen_rtx_REG (Pmode
, 11),
16252 /*savep=*/true, /*gpr=*/true,
16254 insn
= emit_insn (par
);
16255 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
16256 NULL_RTX
, NULL_RTX
);
16260 /* Move the static chain pointer back. */
16261 if (using_static_chain_p
&& !spe_regs_addressable_via_sp
)
16262 emit_move_insn (gen_rtx_REG (Pmode
, 11), gen_rtx_REG (Pmode
, 0));
16264 else if (!WORLD_SAVE_P (info
) && !saving_GPRs_inline
)
16268 /* Need to adjust r11 if we saved any FPRs. */
16269 if (info
->first_fp_reg_save
!= 64)
16271 rtx r11
= gen_rtx_REG (reg_mode
, 11);
16272 rtx offset
= GEN_INT (info
->total_size
16273 + (-8 * (64-info
->first_fp_reg_save
)));
16274 rtx ptr_reg
= (sp_reg_rtx
== frame_reg_rtx
16275 ? sp_reg_rtx
: r11
);
16277 emit_insn (TARGET_32BIT
16278 ? gen_addsi3 (r11
, ptr_reg
, offset
)
16279 : gen_adddi3 (r11
, ptr_reg
, offset
));
16282 par
= rs6000_make_savres_rtx (info
, frame_reg_rtx
,
16283 info
->gp_save_offset
+ sp_offset
,
16285 /*savep=*/true, /*gpr=*/true,
16287 insn
= emit_insn (par
);
16288 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
16289 NULL_RTX
, NULL_RTX
);
16291 else if (!WORLD_SAVE_P (info
) && using_store_multiple
)
16295 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
16296 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
16298 rtx addr
, reg
, mem
;
16299 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
16300 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16301 GEN_INT (info
->gp_save_offset
16304 mem
= gen_frame_mem (reg_mode
, addr
);
16306 RTVEC_ELT (p
, i
) = gen_rtx_SET (VOIDmode
, mem
, reg
);
16308 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
16309 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
16310 NULL_RTX
, NULL_RTX
);
16312 else if (!WORLD_SAVE_P (info
))
16315 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
16316 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
16318 rtx addr
, reg
, mem
;
16319 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
16321 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16322 GEN_INT (info
->gp_save_offset
16325 mem
= gen_frame_mem (reg_mode
, addr
);
16327 insn
= emit_move_insn (mem
, reg
);
16328 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
16329 NULL_RTX
, NULL_RTX
);
16333 /* ??? There's no need to emit actual instructions here, but it's the
16334 easiest way to get the frame unwind information emitted. */
16335 if (crtl
->calls_eh_return
)
16337 unsigned int i
, regno
;
16339 /* In AIX ABI we need to pretend we save r2 here. */
16342 rtx addr
, reg
, mem
;
16344 reg
= gen_rtx_REG (reg_mode
, 2);
16345 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16346 GEN_INT (sp_offset
+ 5 * reg_size
));
16347 mem
= gen_frame_mem (reg_mode
, addr
);
16349 insn
= emit_move_insn (mem
, reg
);
16350 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
16351 NULL_RTX
, NULL_RTX
);
16352 PATTERN (insn
) = gen_blockage ();
16357 regno
= EH_RETURN_DATA_REGNO (i
);
16358 if (regno
== INVALID_REGNUM
)
16361 emit_frame_save (frame_reg_rtx
, frame_ptr_rtx
, reg_mode
, regno
,
16362 info
->ehrd_offset
+ sp_offset
16363 + reg_size
* (int) i
,
16368 /* Save CR if we use any that must be preserved. */
16369 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
)
16371 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16372 GEN_INT (info
->cr_save_offset
+ sp_offset
));
16373 rtx mem
= gen_frame_mem (SImode
, addr
);
16374 /* See the large comment above about why CR2_REGNO is used. */
16375 rtx magic_eh_cr_reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
16377 /* If r12 was used to hold the original sp, copy cr into r0 now
16379 if (REGNO (frame_reg_rtx
) == 12)
16383 cr_save_rtx
= gen_rtx_REG (SImode
, 0);
16384 insn
= emit_insn (gen_movesi_from_cr (cr_save_rtx
));
16385 RTX_FRAME_RELATED_P (insn
) = 1;
16386 set
= gen_rtx_SET (VOIDmode
, cr_save_rtx
, magic_eh_cr_reg
);
16387 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
16392 insn
= emit_move_insn (mem
, cr_save_rtx
);
16394 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
16395 NULL_RTX
, NULL_RTX
);
16398 /* Update stack and set back pointer unless this is V.4,
16399 for which it was done previously. */
16400 if (!WORLD_SAVE_P (info
) && info
->push_p
16401 && !(DEFAULT_ABI
== ABI_V4
|| crtl
->calls_eh_return
))
16403 if (info
->total_size
< 32767)
16404 sp_offset
= info
->total_size
;
16406 frame_reg_rtx
= frame_ptr_rtx
;
16407 rs6000_emit_allocate_stack (info
->total_size
,
16408 (frame_reg_rtx
!= sp_reg_rtx
16409 && ((info
->altivec_size
!= 0)
16410 || (info
->vrsave_mask
!= 0)
16413 if (frame_reg_rtx
!= sp_reg_rtx
)
16414 rs6000_emit_stack_tie ();
16417 /* Set frame pointer, if needed. */
16418 if (frame_pointer_needed
)
16420 insn
= emit_move_insn (gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
16422 RTX_FRAME_RELATED_P (insn
) = 1;
16425 /* Save AltiVec registers if needed. Save here because the red zone does
16426 not include AltiVec registers. */
16427 if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
&& info
->altivec_size
!= 0)
16431 /* There should be a non inline version of this, for when we
16432 are saving lots of vector registers. */
16433 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
16434 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
16436 rtx areg
, savereg
, mem
;
16439 offset
= info
->altivec_save_offset
+ sp_offset
16440 + 16 * (i
- info
->first_altivec_reg_save
);
16442 savereg
= gen_rtx_REG (V4SImode
, i
);
16444 areg
= gen_rtx_REG (Pmode
, 0);
16445 emit_move_insn (areg
, GEN_INT (offset
));
16447 /* AltiVec addressing mode is [reg+reg]. */
16448 mem
= gen_frame_mem (V4SImode
,
16449 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
));
16451 insn
= emit_move_insn (mem
, savereg
);
16453 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
16454 areg
, GEN_INT (offset
));
16458 /* VRSAVE is a bit vector representing which AltiVec registers
16459 are used. The OS uses this to determine which vector
16460 registers to save on a context switch. We need to save
16461 VRSAVE on the stack frame, add whatever AltiVec registers we
16462 used in this function, and do the corresponding magic in the
16465 if (TARGET_ALTIVEC
&& TARGET_ALTIVEC_VRSAVE
16466 && info
->vrsave_mask
!= 0)
16468 rtx reg
, mem
, vrsave
;
16471 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
16472 as frame_reg_rtx and r11 as the static chain pointer for
16473 nested functions. */
16474 reg
= gen_rtx_REG (SImode
, 0);
16475 vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
16477 emit_insn (gen_get_vrsave_internal (reg
));
16479 emit_insn (gen_rtx_SET (VOIDmode
, reg
, vrsave
));
16481 if (!WORLD_SAVE_P (info
))
16484 offset
= info
->vrsave_save_offset
+ sp_offset
;
16485 mem
= gen_frame_mem (SImode
,
16486 gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16487 GEN_INT (offset
)));
16488 insn
= emit_move_insn (mem
, reg
);
16491 /* Include the registers in the mask. */
16492 emit_insn (gen_iorsi3 (reg
, reg
, GEN_INT ((int) info
->vrsave_mask
)));
16494 insn
= emit_insn (generate_set_vrsave (reg
, info
, 0));
16497 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
16498 if ((TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
16499 || (DEFAULT_ABI
== ABI_V4
16500 && (flag_pic
== 1 || (flag_pic
&& TARGET_SECURE_PLT
))
16501 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
)))
16503 /* If emit_load_toc_table will use the link register, we need to save
16504 it. We use R12 for this purpose because emit_load_toc_table
16505 can use register 0. This allows us to use a plain 'blr' to return
16506 from the procedure more often. */
16507 int save_LR_around_toc_setup
= (TARGET_ELF
16508 && DEFAULT_ABI
!= ABI_AIX
16510 && ! info
->lr_save_p
16511 && EDGE_COUNT (EXIT_BLOCK_PTR
->preds
) > 0);
16512 if (save_LR_around_toc_setup
)
16514 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
16516 insn
= emit_move_insn (frame_ptr_rtx
, lr
);
16517 RTX_FRAME_RELATED_P (insn
) = 1;
16519 rs6000_emit_load_toc_table (TRUE
);
16521 insn
= emit_move_insn (lr
, frame_ptr_rtx
);
16522 RTX_FRAME_RELATED_P (insn
) = 1;
16525 rs6000_emit_load_toc_table (TRUE
);
16529 if (DEFAULT_ABI
== ABI_DARWIN
16530 && flag_pic
&& crtl
->uses_pic_offset_table
)
16532 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
16533 rtx src
= machopic_function_base_sym ();
16535 /* Save and restore LR locally around this call (in R0). */
16536 if (!info
->lr_save_p
)
16537 emit_move_insn (gen_rtx_REG (Pmode
, 0), lr
);
16539 emit_insn (gen_load_macho_picbase (src
));
16541 emit_move_insn (gen_rtx_REG (Pmode
,
16542 RS6000_PIC_OFFSET_TABLE_REGNUM
),
16545 if (!info
->lr_save_p
)
16546 emit_move_insn (lr
, gen_rtx_REG (Pmode
, 0));
16551 /* Write function prologue. */
16554 rs6000_output_function_prologue (FILE *file
,
16555 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
16557 rs6000_stack_t
*info
= rs6000_stack_info ();
16559 if (TARGET_DEBUG_STACK
)
16560 debug_stack_info (info
);
16562 /* Write .extern for any function we will call to save and restore
16564 if (info
->first_fp_reg_save
< 64
16565 && !FP_SAVE_INLINE (info
->first_fp_reg_save
))
16566 fprintf (file
, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
16567 SAVE_FP_PREFIX
, info
->first_fp_reg_save
- 32, SAVE_FP_SUFFIX
,
16568 RESTORE_FP_PREFIX
, info
->first_fp_reg_save
- 32, RESTORE_FP_SUFFIX
);
16570 /* Write .extern for AIX common mode routines, if needed. */
16571 if (! TARGET_POWER
&& ! TARGET_POWERPC
&& ! common_mode_defined
)
16573 fputs ("\t.extern __mulh\n", file
);
16574 fputs ("\t.extern __mull\n", file
);
16575 fputs ("\t.extern __divss\n", file
);
16576 fputs ("\t.extern __divus\n", file
);
16577 fputs ("\t.extern __quoss\n", file
);
16578 fputs ("\t.extern __quous\n", file
);
16579 common_mode_defined
= 1;
16582 if (! HAVE_prologue
)
16586 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
16587 the "toplevel" insn chain. */
16588 emit_note (NOTE_INSN_DELETED
);
16589 rs6000_emit_prologue ();
16590 emit_note (NOTE_INSN_DELETED
);
16592 /* Expand INSN_ADDRESSES so final() doesn't crash. */
16596 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
16598 INSN_ADDRESSES_NEW (insn
, addr
);
16603 if (TARGET_DEBUG_STACK
)
16604 debug_rtx_list (get_insns (), 100);
16605 final (get_insns (), file
, FALSE
);
16609 rs6000_pic_labelno
++;
16612 /* Non-zero if vmx regs are restored before the frame pop, zero if
16613 we restore after the pop when possible. */
16614 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
16616 /* Reload CR from REG. */
16619 rs6000_restore_saved_cr (rtx reg
, int using_mfcr_multiple
)
16624 if (using_mfcr_multiple
)
16626 for (i
= 0; i
< 8; i
++)
16627 if (df_regs_ever_live_p (CR0_REGNO
+i
) && ! call_used_regs
[CR0_REGNO
+i
])
16629 gcc_assert (count
);
16632 if (using_mfcr_multiple
&& count
> 1)
16637 p
= rtvec_alloc (count
);
16640 for (i
= 0; i
< 8; i
++)
16641 if (df_regs_ever_live_p (CR0_REGNO
+i
) && ! call_used_regs
[CR0_REGNO
+i
])
16643 rtvec r
= rtvec_alloc (2);
16644 RTVEC_ELT (r
, 0) = reg
;
16645 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7-i
));
16646 RTVEC_ELT (p
, ndx
) =
16647 gen_rtx_SET (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+i
),
16648 gen_rtx_UNSPEC (CCmode
, r
, UNSPEC_MOVESI_TO_CR
));
16651 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
16652 gcc_assert (ndx
== count
);
16655 for (i
= 0; i
< 8; i
++)
16656 if (df_regs_ever_live_p (CR0_REGNO
+i
) && ! call_used_regs
[CR0_REGNO
+i
])
16658 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode
,
16664 /* Emit function epilogue as insns.
16666 At present, dwarf2out_frame_debug_expr doesn't understand
16667 register restores, so we don't bother setting RTX_FRAME_RELATED_P
16668 anywhere in the epilogue. Most of the insns below would in any case
16669 need special notes to explain where r11 is in relation to the stack. */
16672 rs6000_emit_epilogue (int sibcall
)
16674 rs6000_stack_t
*info
;
16675 int restoring_GPRs_inline
;
16676 int restoring_FPRs_inline
;
16677 int using_load_multiple
;
16678 int using_mtcr_multiple
;
16679 int use_backchain_to_restore_sp
;
16683 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, 1);
16684 rtx frame_reg_rtx
= sp_reg_rtx
;
16685 enum machine_mode reg_mode
= Pmode
;
16686 int reg_size
= TARGET_32BIT
? 4 : 8;
16689 info
= rs6000_stack_info ();
16691 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
16693 reg_mode
= V2SImode
;
16697 strategy
= rs6000_savres_strategy (info
, /*savep=*/false,
16698 /*static_chain_p=*/0, sibcall
);
16699 using_load_multiple
= strategy
& SAVRES_MULTIPLE
;
16700 restoring_FPRs_inline
= strategy
& SAVRES_INLINE_FPRS
;
16701 restoring_GPRs_inline
= strategy
& SAVRES_INLINE_GPRS
;
16702 using_mtcr_multiple
= (rs6000_cpu
== PROCESSOR_PPC601
16703 || rs6000_cpu
== PROCESSOR_PPC603
16704 || rs6000_cpu
== PROCESSOR_PPC750
16706 /* Restore via the backchain when we have a large frame, since this
16707 is more efficient than an addis, addi pair. The second condition
16708 here will not trigger at the moment; We don't actually need a
16709 frame pointer for alloca, but the generic parts of the compiler
16710 give us one anyway. */
16711 use_backchain_to_restore_sp
= (info
->total_size
> 32767
16712 || info
->total_size
16713 + (info
->lr_save_p
? info
->lr_save_offset
: 0)
16715 || (cfun
->calls_alloca
16716 && !frame_pointer_needed
));
16717 restore_lr
= (info
->lr_save_p
16718 && restoring_GPRs_inline
16719 && restoring_FPRs_inline
);
16721 if (WORLD_SAVE_P (info
))
16725 const char *alloc_rname
;
16728 /* eh_rest_world_r10 will return to the location saved in the LR
16729 stack slot (which is not likely to be our caller.)
16730 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
16731 rest_world is similar, except any R10 parameter is ignored.
16732 The exception-handling stuff that was here in 2.95 is no
16733 longer necessary. */
16737 + 32 - info
->first_gp_reg_save
16738 + LAST_ALTIVEC_REGNO
+ 1 - info
->first_altivec_reg_save
16739 + 63 + 1 - info
->first_fp_reg_save
);
16741 strcpy (rname
, ((crtl
->calls_eh_return
) ?
16742 "*eh_rest_world_r10" : "*rest_world"));
16743 alloc_rname
= ggc_strdup (rname
);
16746 RTVEC_ELT (p
, j
++) = gen_rtx_RETURN (VOIDmode
);
16747 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
16748 gen_rtx_REG (Pmode
,
16751 = gen_rtx_USE (VOIDmode
, gen_rtx_SYMBOL_REF (Pmode
, alloc_rname
));
16752 /* The instruction pattern requires a clobber here;
16753 it is shared with the restVEC helper. */
16755 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 11));
16758 /* CR register traditionally saved as CR2. */
16759 rtx reg
= gen_rtx_REG (reg_mode
, CR2_REGNO
);
16760 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16761 GEN_INT (info
->cr_save_offset
));
16762 rtx mem
= gen_frame_mem (reg_mode
, addr
);
16764 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
16767 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
16769 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
16770 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16771 GEN_INT (info
->gp_save_offset
16773 rtx mem
= gen_frame_mem (reg_mode
, addr
);
16775 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
16777 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
16779 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
16780 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16781 GEN_INT (info
->altivec_save_offset
16783 rtx mem
= gen_frame_mem (V4SImode
, addr
);
16785 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
16787 for (i
= 0; info
->first_fp_reg_save
+ i
<= 63; i
++)
16789 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
16790 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16791 GEN_INT (info
->fp_save_offset
16793 rtx mem
= gen_frame_mem (DFmode
, addr
);
16795 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
16798 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 0));
16800 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 12));
16802 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 7));
16804 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 8));
16806 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, 10));
16807 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
16812 /* frame_reg_rtx + sp_offset points to the top of this stack frame. */
16814 sp_offset
= info
->total_size
;
16816 /* Restore AltiVec registers if we must do so before adjusting the
16818 if (TARGET_ALTIVEC_ABI
16819 && info
->altivec_size
!= 0
16820 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
16821 || (DEFAULT_ABI
!= ABI_V4
16822 && info
->altivec_save_offset
< (TARGET_32BIT
? -220 : -288))))
16826 if (use_backchain_to_restore_sp
)
16828 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
16829 emit_move_insn (frame_reg_rtx
,
16830 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
16833 else if (frame_pointer_needed
)
16834 frame_reg_rtx
= hard_frame_pointer_rtx
;
16836 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
16837 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
16839 rtx addr
, areg
, mem
;
16841 areg
= gen_rtx_REG (Pmode
, 0);
16843 (areg
, GEN_INT (info
->altivec_save_offset
16845 + 16 * (i
- info
->first_altivec_reg_save
)));
16847 /* AltiVec addressing mode is [reg+reg]. */
16848 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
16849 mem
= gen_frame_mem (V4SImode
, addr
);
16851 emit_move_insn (gen_rtx_REG (V4SImode
, i
), mem
);
16855 /* Restore VRSAVE if we must do so before adjusting the stack. */
16857 && TARGET_ALTIVEC_VRSAVE
16858 && info
->vrsave_mask
!= 0
16859 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
16860 || (DEFAULT_ABI
!= ABI_V4
16861 && info
->vrsave_save_offset
< (TARGET_32BIT
? -220 : -288))))
16863 rtx addr
, mem
, reg
;
16865 if (frame_reg_rtx
== sp_reg_rtx
)
16867 if (use_backchain_to_restore_sp
)
16869 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
16870 emit_move_insn (frame_reg_rtx
,
16871 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
16874 else if (frame_pointer_needed
)
16875 frame_reg_rtx
= hard_frame_pointer_rtx
;
16878 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16879 GEN_INT (info
->vrsave_save_offset
+ sp_offset
));
16880 mem
= gen_frame_mem (SImode
, addr
);
16881 reg
= gen_rtx_REG (SImode
, 12);
16882 emit_move_insn (reg
, mem
);
16884 emit_insn (generate_set_vrsave (reg
, info
, 1));
16887 /* If we have a large stack frame, restore the old stack pointer
16888 using the backchain. */
16889 if (use_backchain_to_restore_sp
)
16891 if (frame_reg_rtx
== sp_reg_rtx
)
16893 /* Under V.4, don't reset the stack pointer until after we're done
16894 loading the saved registers. */
16895 if (DEFAULT_ABI
== ABI_V4
)
16896 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
16898 emit_move_insn (frame_reg_rtx
,
16899 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
16902 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
16903 && DEFAULT_ABI
== ABI_V4
)
16904 /* frame_reg_rtx has been set up by the altivec restore. */
16908 emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
16909 frame_reg_rtx
= sp_reg_rtx
;
16912 /* If we have a frame pointer, we can restore the old stack pointer
16914 else if (frame_pointer_needed
)
16916 frame_reg_rtx
= sp_reg_rtx
;
16917 if (DEFAULT_ABI
== ABI_V4
)
16918 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
16920 emit_insn (TARGET_32BIT
16921 ? gen_addsi3 (frame_reg_rtx
, hard_frame_pointer_rtx
,
16922 GEN_INT (info
->total_size
))
16923 : gen_adddi3 (frame_reg_rtx
, hard_frame_pointer_rtx
,
16924 GEN_INT (info
->total_size
)));
16927 else if (info
->push_p
16928 && DEFAULT_ABI
!= ABI_V4
16929 && !crtl
->calls_eh_return
)
16931 emit_insn (TARGET_32BIT
16932 ? gen_addsi3 (sp_reg_rtx
, sp_reg_rtx
,
16933 GEN_INT (info
->total_size
))
16934 : gen_adddi3 (sp_reg_rtx
, sp_reg_rtx
,
16935 GEN_INT (info
->total_size
)));
16939 /* Restore AltiVec registers if we have not done so already. */
16940 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
16941 && TARGET_ALTIVEC_ABI
16942 && info
->altivec_size
!= 0
16943 && (DEFAULT_ABI
== ABI_V4
16944 || info
->altivec_save_offset
>= (TARGET_32BIT
? -220 : -288)))
16948 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
16949 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
16951 rtx addr
, areg
, mem
;
16953 areg
= gen_rtx_REG (Pmode
, 0);
16955 (areg
, GEN_INT (info
->altivec_save_offset
16957 + 16 * (i
- info
->first_altivec_reg_save
)));
16959 /* AltiVec addressing mode is [reg+reg]. */
16960 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
16961 mem
= gen_frame_mem (V4SImode
, addr
);
16963 emit_move_insn (gen_rtx_REG (V4SImode
, i
), mem
);
16967 /* Restore VRSAVE if we have not done so already. */
16968 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
16970 && TARGET_ALTIVEC_VRSAVE
16971 && info
->vrsave_mask
!= 0
16972 && (DEFAULT_ABI
== ABI_V4
16973 || info
->vrsave_save_offset
>= (TARGET_32BIT
? -220 : -288)))
16975 rtx addr
, mem
, reg
;
16977 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16978 GEN_INT (info
->vrsave_save_offset
+ sp_offset
));
16979 mem
= gen_frame_mem (SImode
, addr
);
16980 reg
= gen_rtx_REG (SImode
, 12);
16981 emit_move_insn (reg
, mem
);
16983 emit_insn (generate_set_vrsave (reg
, info
, 1));
16986 /* Get the old lr if we saved it. If we are restoring registers
16987 out-of-line, then the out-of-line routines can do this for us. */
16990 rtx mem
= gen_frame_mem_offset (Pmode
, frame_reg_rtx
,
16991 info
->lr_save_offset
+ sp_offset
);
16993 emit_move_insn (gen_rtx_REG (Pmode
, 0), mem
);
16996 /* Get the old cr if we saved it. */
16997 if (info
->cr_save_p
)
16999 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
17000 GEN_INT (info
->cr_save_offset
+ sp_offset
));
17001 rtx mem
= gen_frame_mem (SImode
, addr
);
17003 emit_move_insn (gen_rtx_REG (SImode
, 12), mem
);
17006 /* Set LR here to try to overlap restores below. */
17008 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
),
17009 gen_rtx_REG (Pmode
, 0));
17011 /* Load exception handler data registers, if needed. */
17012 if (crtl
->calls_eh_return
)
17014 unsigned int i
, regno
;
17018 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
17019 GEN_INT (sp_offset
+ 5 * reg_size
));
17020 rtx mem
= gen_frame_mem (reg_mode
, addr
);
17022 emit_move_insn (gen_rtx_REG (reg_mode
, 2), mem
);
17029 regno
= EH_RETURN_DATA_REGNO (i
);
17030 if (regno
== INVALID_REGNUM
)
17033 mem
= gen_frame_mem_offset (reg_mode
, frame_reg_rtx
,
17034 info
->ehrd_offset
+ sp_offset
17035 + reg_size
* (int) i
);
17037 emit_move_insn (gen_rtx_REG (reg_mode
, regno
), mem
);
17041 /* Restore GPRs. This is done as a PARALLEL if we are using
17042 the load-multiple instructions. */
17044 && info
->spe_64bit_regs_used
!= 0
17045 && info
->first_gp_reg_save
!= 32)
17047 /* Determine whether we can address all of the registers that need
17048 to be saved with an offset from the stack pointer that fits in
17049 the small const field for SPE memory instructions. */
17050 int spe_regs_addressable_via_sp
17051 = (SPE_CONST_OFFSET_OK(info
->spe_gp_save_offset
+ sp_offset
17052 + (32 - info
->first_gp_reg_save
- 1) * reg_size
)
17053 && restoring_GPRs_inline
);
17056 if (spe_regs_addressable_via_sp
)
17057 spe_offset
= info
->spe_gp_save_offset
+ sp_offset
;
17060 rtx old_frame_reg_rtx
= frame_reg_rtx
;
17061 /* Make r11 point to the start of the SPE save area. We worried about
17062 not clobbering it when we were saving registers in the prologue.
17063 There's no need to worry here because the static chain is passed
17064 anew to every function. */
17065 int ool_adjust
= (restoring_GPRs_inline
17067 : (info
->first_gp_reg_save
17068 - (FIRST_SAVRES_REGISTER
+1))*8);
17070 if (frame_reg_rtx
== sp_reg_rtx
)
17071 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
17072 emit_insn (gen_addsi3 (frame_reg_rtx
, old_frame_reg_rtx
,
17073 GEN_INT (info
->spe_gp_save_offset
17076 /* Keep the invariant that frame_reg_rtx + sp_offset points
17077 at the top of the stack frame. */
17078 sp_offset
= -info
->spe_gp_save_offset
;
17083 if (restoring_GPRs_inline
)
17085 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
17086 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
17088 rtx offset
, addr
, mem
;
17090 /* We're doing all this to ensure that the immediate offset
17091 fits into the immediate field of 'evldd'. */
17092 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset
+ reg_size
* i
));
17094 offset
= GEN_INT (spe_offset
+ reg_size
* i
);
17095 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, offset
);
17096 mem
= gen_rtx_MEM (V2SImode
, addr
);
17098 emit_move_insn (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
17106 par
= rs6000_make_savres_rtx (info
, gen_rtx_REG (Pmode
, 11),
17108 /*savep=*/false, /*gpr=*/true,
17110 emit_jump_insn (par
);
17112 /* We don't want anybody else emitting things after we jumped
17117 else if (!restoring_GPRs_inline
)
17119 /* We are jumping to an out-of-line function. */
17120 bool can_use_exit
= info
->first_fp_reg_save
== 64;
17123 /* Emit stack reset code if we need it. */
17125 rs6000_emit_stack_reset (info
, sp_reg_rtx
, frame_reg_rtx
,
17126 sp_offset
, can_use_exit
);
17128 emit_insn (gen_addsi3 (gen_rtx_REG (Pmode
, 11),
17130 GEN_INT (sp_offset
- info
->fp_size
)));
17132 par
= rs6000_make_savres_rtx (info
, frame_reg_rtx
,
17133 info
->gp_save_offset
, reg_mode
,
17134 /*savep=*/false, /*gpr=*/true,
17135 /*exitp=*/can_use_exit
);
17139 if (info
->cr_save_p
)
17140 rs6000_restore_saved_cr (gen_rtx_REG (SImode
, 12),
17141 using_mtcr_multiple
);
17143 emit_jump_insn (par
);
17145 /* We don't want anybody else emitting things after we jumped
17152 else if (using_load_multiple
)
17155 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
17156 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
17158 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
17159 GEN_INT (info
->gp_save_offset
17162 rtx mem
= gen_frame_mem (reg_mode
, addr
);
17165 gen_rtx_SET (VOIDmode
,
17166 gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
17169 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
17173 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
17174 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
17176 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
17177 GEN_INT (info
->gp_save_offset
17180 rtx mem
= gen_frame_mem (reg_mode
, addr
);
17182 emit_move_insn (gen_rtx_REG (reg_mode
,
17183 info
->first_gp_reg_save
+ i
), mem
);
17187 /* Restore fpr's if we need to do it without calling a function. */
17188 if (restoring_FPRs_inline
)
17189 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
17190 if ((df_regs_ever_live_p (info
->first_fp_reg_save
+i
)
17191 && ! call_used_regs
[info
->first_fp_reg_save
+i
]))
17194 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
17195 GEN_INT (info
->fp_save_offset
17198 mem
= gen_frame_mem (DFmode
, addr
);
17200 emit_move_insn (gen_rtx_REG (DFmode
,
17201 info
->first_fp_reg_save
+ i
),
17205 /* If we saved cr, restore it here. Just those that were used. */
17206 if (info
->cr_save_p
)
17207 rs6000_restore_saved_cr (gen_rtx_REG (SImode
, 12), using_mtcr_multiple
);
17209 /* If this is V.4, unwind the stack pointer after all of the loads
17211 rs6000_emit_stack_reset (info
, sp_reg_rtx
, frame_reg_rtx
,
17212 sp_offset
, !restoring_FPRs_inline
);
17214 if (crtl
->calls_eh_return
)
17216 rtx sa
= EH_RETURN_STACKADJ_RTX
;
17217 emit_insn (TARGET_32BIT
17218 ? gen_addsi3 (sp_reg_rtx
, sp_reg_rtx
, sa
)
17219 : gen_adddi3 (sp_reg_rtx
, sp_reg_rtx
, sa
));
17225 if (! restoring_FPRs_inline
)
17226 p
= rtvec_alloc (4 + 64 - info
->first_fp_reg_save
);
17228 p
= rtvec_alloc (2);
17230 RTVEC_ELT (p
, 0) = gen_rtx_RETURN (VOIDmode
);
17231 RTVEC_ELT (p
, 1) = (restoring_FPRs_inline
17232 ? gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 65))
17233 : gen_rtx_CLOBBER (VOIDmode
,
17234 gen_rtx_REG (Pmode
, 65)));
17236 /* If we have to restore more than two FP registers, branch to the
17237 restore function. It will return to our caller. */
17238 if (! restoring_FPRs_inline
)
17243 sym
= rs6000_savres_routine_sym (info
,
17247 RTVEC_ELT (p
, 2) = gen_rtx_USE (VOIDmode
, sym
);
17248 RTVEC_ELT (p
, 3) = gen_rtx_USE (VOIDmode
,
17249 gen_rtx_REG (Pmode
, 11));
17250 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
17253 addr
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
,
17254 GEN_INT (info
->fp_save_offset
+ 8*i
));
17255 mem
= gen_frame_mem (DFmode
, addr
);
17257 RTVEC_ELT (p
, i
+4) =
17258 gen_rtx_SET (VOIDmode
,
17259 gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
),
17264 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
17268 /* Write function epilogue. */
17271 rs6000_output_function_epilogue (FILE *file
,
17272 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
17274 if (! HAVE_epilogue
)
17276 rtx insn
= get_last_insn ();
17277 /* If the last insn was a BARRIER, we don't have to write anything except
17278 the trace table. */
17279 if (GET_CODE (insn
) == NOTE
)
17280 insn
= prev_nonnote_insn (insn
);
17281 if (insn
== 0 || GET_CODE (insn
) != BARRIER
)
17283 /* This is slightly ugly, but at least we don't have two
17284 copies of the epilogue-emitting code. */
17287 /* A NOTE_INSN_DELETED is supposed to be at the start
17288 and end of the "toplevel" insn chain. */
17289 emit_note (NOTE_INSN_DELETED
);
17290 rs6000_emit_epilogue (FALSE
);
17291 emit_note (NOTE_INSN_DELETED
);
17293 /* Expand INSN_ADDRESSES so final() doesn't crash. */
17297 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
17299 INSN_ADDRESSES_NEW (insn
, addr
);
17304 if (TARGET_DEBUG_STACK
)
17305 debug_rtx_list (get_insns (), 100);
17306 final (get_insns (), file
, FALSE
);
17312 macho_branch_islands ();
17313 /* Mach-O doesn't support labels at the end of objects, so if
17314 it looks like we might want one, insert a NOP. */
17316 rtx insn
= get_last_insn ();
17319 && NOTE_KIND (insn
) != NOTE_INSN_DELETED_LABEL
)
17320 insn
= PREV_INSN (insn
);
17324 && NOTE_KIND (insn
) == NOTE_INSN_DELETED_LABEL
)))
17325 fputs ("\tnop\n", file
);
17329 /* Output a traceback table here. See /usr/include/sys/debug.h for info
17332 We don't output a traceback table if -finhibit-size-directive was
17333 used. The documentation for -finhibit-size-directive reads
17334 ``don't output a @code{.size} assembler directive, or anything
17335 else that would cause trouble if the function is split in the
17336 middle, and the two halves are placed at locations far apart in
17337 memory.'' The traceback table has this property, since it
17338 includes the offset from the start of the function to the
17339 traceback table itself.
17341 System V.4 Powerpc's (and the embedded ABI derived from it) use a
17342 different traceback table. */
17343 if (DEFAULT_ABI
== ABI_AIX
&& ! flag_inhibit_size_directive
17344 && rs6000_traceback
!= traceback_none
&& !crtl
->is_thunk
)
17346 const char *fname
= NULL
;
17347 const char *language_string
= lang_hooks
.name
;
17348 int fixed_parms
= 0, float_parms
= 0, parm_info
= 0;
17350 int optional_tbtab
;
17351 rs6000_stack_t
*info
= rs6000_stack_info ();
17353 if (rs6000_traceback
== traceback_full
)
17354 optional_tbtab
= 1;
17355 else if (rs6000_traceback
== traceback_part
)
17356 optional_tbtab
= 0;
17358 optional_tbtab
= !optimize_size
&& !TARGET_ELF
;
17360 if (optional_tbtab
)
17362 fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
17363 while (*fname
== '.') /* V.4 encodes . in the name */
17366 /* Need label immediately before tbtab, so we can compute
17367 its offset from the function start. */
17368 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
17369 ASM_OUTPUT_LABEL (file
, fname
);
17372 /* The .tbtab pseudo-op can only be used for the first eight
17373 expressions, since it can't handle the possibly variable
17374 length fields that follow. However, if you omit the optional
17375 fields, the assembler outputs zeros for all optional fields
17376 anyways, giving each variable length field is minimum length
17377 (as defined in sys/debug.h). Thus we can not use the .tbtab
17378 pseudo-op at all. */
17380 /* An all-zero word flags the start of the tbtab, for debuggers
17381 that have to find it by searching forward from the entry
17382 point or from the current pc. */
17383 fputs ("\t.long 0\n", file
);
17385 /* Tbtab format type. Use format type 0. */
17386 fputs ("\t.byte 0,", file
);
17388 /* Language type. Unfortunately, there does not seem to be any
17389 official way to discover the language being compiled, so we
17390 use language_string.
17391 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
17392 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
17393 a number, so for now use 9. */
17394 if (! strcmp (language_string
, "GNU C"))
17396 else if (! strcmp (language_string
, "GNU F77")
17397 || ! strcmp (language_string
, "GNU Fortran"))
17399 else if (! strcmp (language_string
, "GNU Pascal"))
17401 else if (! strcmp (language_string
, "GNU Ada"))
17403 else if (! strcmp (language_string
, "GNU C++")
17404 || ! strcmp (language_string
, "GNU Objective-C++"))
17406 else if (! strcmp (language_string
, "GNU Java"))
17408 else if (! strcmp (language_string
, "GNU Objective-C"))
17411 gcc_unreachable ();
17412 fprintf (file
, "%d,", i
);
17414 /* 8 single bit fields: global linkage (not set for C extern linkage,
17415 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
17416 from start of procedure stored in tbtab, internal function, function
17417 has controlled storage, function has no toc, function uses fp,
17418 function logs/aborts fp operations. */
17419 /* Assume that fp operations are used if any fp reg must be saved. */
17420 fprintf (file
, "%d,",
17421 (optional_tbtab
<< 5) | ((info
->first_fp_reg_save
!= 64) << 1));
17423 /* 6 bitfields: function is interrupt handler, name present in
17424 proc table, function calls alloca, on condition directives
17425 (controls stack walks, 3 bits), saves condition reg, saves
17427 /* The `function calls alloca' bit seems to be set whenever reg 31 is
17428 set up as a frame pointer, even when there is no alloca call. */
17429 fprintf (file
, "%d,",
17430 ((optional_tbtab
<< 6)
17431 | ((optional_tbtab
& frame_pointer_needed
) << 5)
17432 | (info
->cr_save_p
<< 1)
17433 | (info
->lr_save_p
)));
17435 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
17437 fprintf (file
, "%d,",
17438 (info
->push_p
<< 7) | (64 - info
->first_fp_reg_save
));
17440 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
17441 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
17443 if (optional_tbtab
)
17445 /* Compute the parameter info from the function decl argument
17448 int next_parm_info_bit
= 31;
17450 for (decl
= DECL_ARGUMENTS (current_function_decl
);
17451 decl
; decl
= TREE_CHAIN (decl
))
17453 rtx parameter
= DECL_INCOMING_RTL (decl
);
17454 enum machine_mode mode
= GET_MODE (parameter
);
17456 if (GET_CODE (parameter
) == REG
)
17458 if (SCALAR_FLOAT_MODE_P (mode
))
17479 gcc_unreachable ();
17482 /* If only one bit will fit, don't or in this entry. */
17483 if (next_parm_info_bit
> 0)
17484 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
17485 next_parm_info_bit
-= 2;
17489 fixed_parms
+= ((GET_MODE_SIZE (mode
)
17490 + (UNITS_PER_WORD
- 1))
17492 next_parm_info_bit
-= 1;
17498 /* Number of fixed point parameters. */
17499 /* This is actually the number of words of fixed point parameters; thus
17500 an 8 byte struct counts as 2; and thus the maximum value is 8. */
17501 fprintf (file
, "%d,", fixed_parms
);
17503 /* 2 bitfields: number of floating point parameters (7 bits), parameters
17505 /* This is actually the number of fp registers that hold parameters;
17506 and thus the maximum value is 13. */
17507 /* Set parameters on stack bit if parameters are not in their original
17508 registers, regardless of whether they are on the stack? Xlc
17509 seems to set the bit when not optimizing. */
17510 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
17512 if (! optional_tbtab
)
17515 /* Optional fields follow. Some are variable length. */
17517 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
17518 11 double float. */
17519 /* There is an entry for each parameter in a register, in the order that
17520 they occur in the parameter list. Any intervening arguments on the
17521 stack are ignored. If the list overflows a long (max possible length
17522 34 bits) then completely leave off all elements that don't fit. */
17523 /* Only emit this long if there was at least one parameter. */
17524 if (fixed_parms
|| float_parms
)
17525 fprintf (file
, "\t.long %d\n", parm_info
);
17527 /* Offset from start of code to tb table. */
17528 fputs ("\t.long ", file
);
17529 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
17531 RS6000_OUTPUT_BASENAME (file
, fname
);
17533 assemble_name (file
, fname
);
17535 rs6000_output_function_entry (file
, fname
);
17538 /* Interrupt handler mask. */
17539 /* Omit this long, since we never set the interrupt handler bit
17542 /* Number of CTL (controlled storage) anchors. */
17543 /* Omit this long, since the has_ctl bit is never set above. */
17545 /* Displacement into stack of each CTL anchor. */
17546 /* Omit this list of longs, because there are no CTL anchors. */
17548 /* Length of function name. */
17551 fprintf (file
, "\t.short %d\n", (int) strlen (fname
));
17553 /* Function name. */
17554 assemble_string (fname
, strlen (fname
));
17556 /* Register for alloca automatic storage; this is always reg 31.
17557 Only emit this if the alloca bit was set above. */
17558 if (frame_pointer_needed
)
17559 fputs ("\t.byte 31\n", file
);
17561 fputs ("\t.align 2\n", file
);
17565 /* A C compound statement that outputs the assembler code for a thunk
17566 function, used to implement C++ virtual function calls with
17567 multiple inheritance. The thunk acts as a wrapper around a virtual
17568 function, adjusting the implicit object parameter before handing
17569 control off to the real function.
17571 First, emit code to add the integer DELTA to the location that
17572 contains the incoming first argument. Assume that this argument
17573 contains a pointer, and is the one used to pass the `this' pointer
17574 in C++. This is the incoming argument *before* the function
17575 prologue, e.g. `%o0' on a sparc. The addition must preserve the
17576 values of all other incoming arguments.
17578 After the addition, emit code to jump to FUNCTION, which is a
17579 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
17580 not touch the return address. Hence returning from FUNCTION will
17581 return to whoever called the current `thunk'.
17583 The effect must be as if FUNCTION had been called directly with the
17584 adjusted first argument. This macro is responsible for emitting
17585 all of the code for a thunk function; output_function_prologue()
17586 and output_function_epilogue() are not invoked.
17588 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
17589 been extracted from it.) It might possibly be useful on some
17590 targets, but probably not.
17592 If you do not define this macro, the target-independent code in the
17593 C++ frontend will generate a less efficient heavyweight thunk that
17594 calls FUNCTION instead of jumping to it. The generic approach does
17595 not support varargs. */
17598 rs6000_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
17599 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
17602 rtx this_rtx
, insn
, funexp
;
17604 reload_completed
= 1;
17605 epilogue_completed
= 1;
17607 /* Mark the end of the (empty) prologue. */
17608 emit_note (NOTE_INSN_PROLOGUE_END
);
17610 /* Find the "this" pointer. If the function returns a structure,
17611 the structure return pointer is in r3. */
17612 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
17613 this_rtx
= gen_rtx_REG (Pmode
, 4);
17615 this_rtx
= gen_rtx_REG (Pmode
, 3);
17617 /* Apply the constant offset, if required. */
17620 rtx delta_rtx
= GEN_INT (delta
);
17621 emit_insn (TARGET_32BIT
17622 ? gen_addsi3 (this_rtx
, this_rtx
, delta_rtx
)
17623 : gen_adddi3 (this_rtx
, this_rtx
, delta_rtx
));
17626 /* Apply the offset from the vtable, if required. */
17629 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
17630 rtx tmp
= gen_rtx_REG (Pmode
, 12);
17632 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this_rtx
));
17633 if (((unsigned HOST_WIDE_INT
) vcall_offset
) + 0x8000 >= 0x10000)
17635 emit_insn (TARGET_32BIT
17636 ? gen_addsi3 (tmp
, tmp
, vcall_offset_rtx
)
17637 : gen_adddi3 (tmp
, tmp
, vcall_offset_rtx
));
17638 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
17642 rtx loc
= gen_rtx_PLUS (Pmode
, tmp
, vcall_offset_rtx
);
17644 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, loc
));
17646 emit_insn (TARGET_32BIT
17647 ? gen_addsi3 (this_rtx
, this_rtx
, tmp
)
17648 : gen_adddi3 (this_rtx
, this_rtx
, tmp
));
17651 /* Generate a tail call to the target function. */
17652 if (!TREE_USED (function
))
17654 assemble_external (function
);
17655 TREE_USED (function
) = 1;
17657 funexp
= XEXP (DECL_RTL (function
), 0);
17658 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
17661 if (MACHOPIC_INDIRECT
)
17662 funexp
= machopic_indirect_call_target (funexp
);
17665 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
17666 generate sibcall RTL explicitly. */
17667 insn
= emit_call_insn (
17668 gen_rtx_PARALLEL (VOIDmode
,
17670 gen_rtx_CALL (VOIDmode
,
17671 funexp
, const0_rtx
),
17672 gen_rtx_USE (VOIDmode
, const0_rtx
),
17673 gen_rtx_USE (VOIDmode
,
17674 gen_rtx_REG (SImode
,
17676 gen_rtx_RETURN (VOIDmode
))));
17677 SIBLING_CALL_P (insn
) = 1;
17680 /* Run just enough of rest_of_compilation to get the insns emitted.
17681 There's not really enough bulk here to make other passes such as
17682 instruction scheduling worth while. Note that use_thunk calls
17683 assemble_start_function and assemble_end_function. */
17684 insn
= get_insns ();
17685 insn_locators_alloc ();
17686 shorten_branches (insn
);
17687 final_start_function (insn
, file
, 1);
17688 final (insn
, file
, 1);
17689 final_end_function ();
17690 free_after_compilation (cfun
);
17692 reload_completed
= 0;
17693 epilogue_completed
= 0;
17696 /* A quick summary of the various types of 'constant-pool tables'
17699 Target Flags Name One table per
17700 AIX (none) AIX TOC object file
17701 AIX -mfull-toc AIX TOC object file
17702 AIX -mminimal-toc AIX minimal TOC translation unit
17703 SVR4/EABI (none) SVR4 SDATA object file
17704 SVR4/EABI -fpic SVR4 pic object file
17705 SVR4/EABI -fPIC SVR4 PIC translation unit
17706 SVR4/EABI -mrelocatable EABI TOC function
17707 SVR4/EABI -maix AIX TOC object file
17708 SVR4/EABI -maix -mminimal-toc
17709 AIX minimal TOC translation unit
17711 Name Reg. Set by entries contains:
17712 made by addrs? fp? sum?
17714 AIX TOC 2 crt0 as Y option option
17715 AIX minimal TOC 30 prolog gcc Y Y option
17716 SVR4 SDATA 13 crt0 gcc N Y N
17717 SVR4 pic 30 prolog ld Y not yet N
17718 SVR4 PIC 30 prolog gcc Y option option
17719 EABI TOC 30 prolog gcc Y option option
17723 /* Hash functions for the hash table. */
17726 rs6000_hash_constant (rtx k
)
17728 enum rtx_code code
= GET_CODE (k
);
17729 enum machine_mode mode
= GET_MODE (k
);
17730 unsigned result
= (code
<< 3) ^ mode
;
17731 const char *format
;
17734 format
= GET_RTX_FORMAT (code
);
17735 flen
= strlen (format
);
17741 return result
* 1231 + (unsigned) INSN_UID (XEXP (k
, 0));
17744 if (mode
!= VOIDmode
)
17745 return real_hash (CONST_DOUBLE_REAL_VALUE (k
)) * result
;
17757 for (; fidx
< flen
; fidx
++)
17758 switch (format
[fidx
])
17763 const char *str
= XSTR (k
, fidx
);
17764 len
= strlen (str
);
17765 result
= result
* 613 + len
;
17766 for (i
= 0; i
< len
; i
++)
17767 result
= result
* 613 + (unsigned) str
[i
];
17772 result
= result
* 1231 + rs6000_hash_constant (XEXP (k
, fidx
));
17776 result
= result
* 613 + (unsigned) XINT (k
, fidx
);
17779 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT
))
17780 result
= result
* 613 + (unsigned) XWINT (k
, fidx
);
17784 for (i
= 0; i
< sizeof (HOST_WIDE_INT
) / sizeof (unsigned); i
++)
17785 result
= result
* 613 + (unsigned) (XWINT (k
, fidx
)
17792 gcc_unreachable ();
17799 toc_hash_function (const void *hash_entry
)
17801 const struct toc_hash_struct
*thc
=
17802 (const struct toc_hash_struct
*) hash_entry
;
17803 return rs6000_hash_constant (thc
->key
) ^ thc
->key_mode
;
17806 /* Compare H1 and H2 for equivalence. */
17809 toc_hash_eq (const void *h1
, const void *h2
)
17811 rtx r1
= ((const struct toc_hash_struct
*) h1
)->key
;
17812 rtx r2
= ((const struct toc_hash_struct
*) h2
)->key
;
17814 if (((const struct toc_hash_struct
*) h1
)->key_mode
17815 != ((const struct toc_hash_struct
*) h2
)->key_mode
)
17818 return rtx_equal_p (r1
, r2
);
17821 /* These are the names given by the C++ front-end to vtables, and
17822 vtable-like objects. Ideally, this logic should not be here;
17823 instead, there should be some programmatic way of inquiring as
17824 to whether or not an object is a vtable. */
17826 #define VTABLE_NAME_P(NAME) \
17827 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
17828 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
17829 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
17830 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
17831 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
17834 rs6000_output_symbol_ref (FILE *file
, rtx x
)
17836 /* Currently C++ toc references to vtables can be emitted before it
17837 is decided whether the vtable is public or private. If this is
17838 the case, then the linker will eventually complain that there is
17839 a reference to an unknown section. Thus, for vtables only,
17840 we emit the TOC reference to reference the symbol and not the
17842 const char *name
= XSTR (x
, 0);
17844 if (VTABLE_NAME_P (name
))
17846 RS6000_OUTPUT_BASENAME (file
, name
);
17849 assemble_name (file
, name
);
17852 /* Output a TOC entry. We derive the entry name from what is being
17856 output_toc (FILE *file
, rtx x
, int labelno
, enum machine_mode mode
)
17859 const char *name
= buf
;
17860 const char *real_name
;
17862 HOST_WIDE_INT offset
= 0;
17864 gcc_assert (!TARGET_NO_TOC
);
17866 /* When the linker won't eliminate them, don't output duplicate
17867 TOC entries (this happens on AIX if there is any kind of TOC,
17868 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
17870 if (TARGET_TOC
&& GET_CODE (x
) != LABEL_REF
)
17872 struct toc_hash_struct
*h
;
17875 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
17876 time because GGC is not initialized at that point. */
17877 if (toc_hash_table
== NULL
)
17878 toc_hash_table
= htab_create_ggc (1021, toc_hash_function
,
17879 toc_hash_eq
, NULL
);
17881 h
= GGC_NEW (struct toc_hash_struct
);
17883 h
->key_mode
= mode
;
17884 h
->labelno
= labelno
;
17886 found
= htab_find_slot (toc_hash_table
, h
, 1);
17887 if (*found
== NULL
)
17889 else /* This is indeed a duplicate.
17890 Set this label equal to that label. */
17892 fputs ("\t.set ", file
);
17893 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
17894 fprintf (file
, "%d,", labelno
);
17895 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
17896 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
17902 /* If we're going to put a double constant in the TOC, make sure it's
17903 aligned properly when strict alignment is on. */
17904 if (GET_CODE (x
) == CONST_DOUBLE
17905 && STRICT_ALIGNMENT
17906 && GET_MODE_BITSIZE (mode
) >= 64
17907 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
)) {
17908 ASM_OUTPUT_ALIGN (file
, 3);
17911 (*targetm
.asm_out
.internal_label
) (file
, "LC", labelno
);
17913 /* Handle FP constants specially. Note that if we have a minimal
17914 TOC, things we put here aren't actually in the TOC, so we can allow
17916 if (GET_CODE (x
) == CONST_DOUBLE
&&
17917 (GET_MODE (x
) == TFmode
|| GET_MODE (x
) == TDmode
))
17919 REAL_VALUE_TYPE rv
;
17922 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
17923 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
17924 REAL_VALUE_TO_TARGET_DECIMAL128 (rv
, k
);
17926 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv
, k
);
17930 if (TARGET_MINIMAL_TOC
)
17931 fputs (DOUBLE_INT_ASM_OP
, file
);
17933 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
17934 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
17935 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
17936 fprintf (file
, "0x%lx%08lx,0x%lx%08lx\n",
17937 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
17938 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
17943 if (TARGET_MINIMAL_TOC
)
17944 fputs ("\t.long ", file
);
17946 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
17947 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
17948 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
17949 fprintf (file
, "0x%lx,0x%lx,0x%lx,0x%lx\n",
17950 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
17951 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
17955 else if (GET_CODE (x
) == CONST_DOUBLE
&&
17956 (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DDmode
))
17958 REAL_VALUE_TYPE rv
;
17961 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
17963 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
17964 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, k
);
17966 REAL_VALUE_TO_TARGET_DOUBLE (rv
, k
);
17970 if (TARGET_MINIMAL_TOC
)
17971 fputs (DOUBLE_INT_ASM_OP
, file
);
17973 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
17974 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
17975 fprintf (file
, "0x%lx%08lx\n",
17976 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
17981 if (TARGET_MINIMAL_TOC
)
17982 fputs ("\t.long ", file
);
17984 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
17985 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
17986 fprintf (file
, "0x%lx,0x%lx\n",
17987 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
17991 else if (GET_CODE (x
) == CONST_DOUBLE
&&
17992 (GET_MODE (x
) == SFmode
|| GET_MODE (x
) == SDmode
))
17994 REAL_VALUE_TYPE rv
;
17997 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
17998 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
17999 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
18001 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
18005 if (TARGET_MINIMAL_TOC
)
18006 fputs (DOUBLE_INT_ASM_OP
, file
);
18008 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
18009 fprintf (file
, "0x%lx00000000\n", l
& 0xffffffff);
18014 if (TARGET_MINIMAL_TOC
)
18015 fputs ("\t.long ", file
);
18017 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
18018 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
18022 else if (GET_MODE (x
) == VOIDmode
18023 && (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
))
18025 unsigned HOST_WIDE_INT low
;
18026 HOST_WIDE_INT high
;
18028 if (GET_CODE (x
) == CONST_DOUBLE
)
18030 low
= CONST_DOUBLE_LOW (x
);
18031 high
= CONST_DOUBLE_HIGH (x
);
18034 #if HOST_BITS_PER_WIDE_INT == 32
18037 high
= (low
& 0x80000000) ? ~0 : 0;
18041 low
= INTVAL (x
) & 0xffffffff;
18042 high
= (HOST_WIDE_INT
) INTVAL (x
) >> 32;
18046 /* TOC entries are always Pmode-sized, but since this
18047 is a bigendian machine then if we're putting smaller
18048 integer constants in the TOC we have to pad them.
18049 (This is still a win over putting the constants in
18050 a separate constant pool, because then we'd have
18051 to have both a TOC entry _and_ the actual constant.)
18053 For a 32-bit target, CONST_INT values are loaded and shifted
18054 entirely within `low' and can be stored in one TOC entry. */
18056 /* It would be easy to make this work, but it doesn't now. */
18057 gcc_assert (!TARGET_64BIT
|| POINTER_SIZE
>= GET_MODE_BITSIZE (mode
));
18059 if (POINTER_SIZE
> GET_MODE_BITSIZE (mode
))
18061 #if HOST_BITS_PER_WIDE_INT == 32
18062 lshift_double (low
, high
, POINTER_SIZE
- GET_MODE_BITSIZE (mode
),
18063 POINTER_SIZE
, &low
, &high
, 0);
18066 low
<<= POINTER_SIZE
- GET_MODE_BITSIZE (mode
);
18067 high
= (HOST_WIDE_INT
) low
>> 32;
18074 if (TARGET_MINIMAL_TOC
)
18075 fputs (DOUBLE_INT_ASM_OP
, file
);
18077 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
18078 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
18079 fprintf (file
, "0x%lx%08lx\n",
18080 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
18085 if (POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
18087 if (TARGET_MINIMAL_TOC
)
18088 fputs ("\t.long ", file
);
18090 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
18091 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
18092 fprintf (file
, "0x%lx,0x%lx\n",
18093 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
18097 if (TARGET_MINIMAL_TOC
)
18098 fputs ("\t.long ", file
);
18100 fprintf (file
, "\t.tc IS_%lx[TC],", (long) low
& 0xffffffff);
18101 fprintf (file
, "0x%lx\n", (long) low
& 0xffffffff);
18107 if (GET_CODE (x
) == CONST
)
18109 gcc_assert (GET_CODE (XEXP (x
, 0)) == PLUS
);
18111 base
= XEXP (XEXP (x
, 0), 0);
18112 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
18115 switch (GET_CODE (base
))
18118 name
= XSTR (base
, 0);
18122 ASM_GENERATE_INTERNAL_LABEL (buf
, "L",
18123 CODE_LABEL_NUMBER (XEXP (base
, 0)));
18127 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
18131 gcc_unreachable ();
18134 real_name
= (*targetm
.strip_name_encoding
) (name
);
18135 if (TARGET_MINIMAL_TOC
)
18136 fputs (TARGET_32BIT
? "\t.long " : DOUBLE_INT_ASM_OP
, file
);
18139 fprintf (file
, "\t.tc %s", real_name
);
18142 fprintf (file
, ".N" HOST_WIDE_INT_PRINT_UNSIGNED
, - offset
);
18144 fprintf (file
, ".P" HOST_WIDE_INT_PRINT_UNSIGNED
, offset
);
18146 fputs ("[TC],", file
);
18149 /* Currently C++ toc references to vtables can be emitted before it
18150 is decided whether the vtable is public or private. If this is
18151 the case, then the linker will eventually complain that there is
18152 a TOC reference to an unknown section. Thus, for vtables only,
18153 we emit the TOC reference to reference the symbol and not the
18155 if (VTABLE_NAME_P (name
))
18157 RS6000_OUTPUT_BASENAME (file
, name
);
18159 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
18160 else if (offset
> 0)
18161 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
18164 output_addr_const (file
, x
);
18168 /* Output an assembler pseudo-op to write an ASCII string of N characters
18169 starting at P to FILE.
18171 On the RS/6000, we have to do this using the .byte operation and
18172 write out special characters outside the quoted string.
18173 Also, the assembler is broken; very long strings are truncated,
18174 so we must artificially break them up early. */
18177 output_ascii (FILE *file
, const char *p
, int n
)
18180 int i
, count_string
;
18181 const char *for_string
= "\t.byte \"";
18182 const char *for_decimal
= "\t.byte ";
18183 const char *to_close
= NULL
;
18186 for (i
= 0; i
< n
; i
++)
18189 if (c
>= ' ' && c
< 0177)
18192 fputs (for_string
, file
);
18195 /* Write two quotes to get one. */
18203 for_decimal
= "\"\n\t.byte ";
18207 if (count_string
>= 512)
18209 fputs (to_close
, file
);
18211 for_string
= "\t.byte \"";
18212 for_decimal
= "\t.byte ";
18220 fputs (for_decimal
, file
);
18221 fprintf (file
, "%d", c
);
18223 for_string
= "\n\t.byte \"";
18224 for_decimal
= ", ";
18230 /* Now close the string if we have written one. Then end the line. */
18232 fputs (to_close
, file
);
18235 /* Generate a unique section name for FILENAME for a section type
18236 represented by SECTION_DESC. Output goes into BUF.
18238 SECTION_DESC can be any string, as long as it is different for each
18239 possible section type.
18241 We name the section in the same manner as xlc. The name begins with an
18242 underscore followed by the filename (after stripping any leading directory
18243 names) with the last period replaced by the string SECTION_DESC. If
18244 FILENAME does not contain a period, SECTION_DESC is appended to the end of
18248 rs6000_gen_section_name (char **buf
, const char *filename
,
18249 const char *section_desc
)
18251 const char *q
, *after_last_slash
, *last_period
= 0;
18255 after_last_slash
= filename
;
18256 for (q
= filename
; *q
; q
++)
18259 after_last_slash
= q
+ 1;
18260 else if (*q
== '.')
18264 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
18265 *buf
= (char *) xmalloc (len
);
18270 for (q
= after_last_slash
; *q
; q
++)
18272 if (q
== last_period
)
18274 strcpy (p
, section_desc
);
18275 p
+= strlen (section_desc
);
18279 else if (ISALNUM (*q
))
18283 if (last_period
== 0)
18284 strcpy (p
, section_desc
);
18289 /* Emit profile function. */
18292 output_profile_hook (int labelno ATTRIBUTE_UNUSED
)
18294 /* Non-standard profiling for kernels, which just saves LR then calls
18295 _mcount without worrying about arg saves. The idea is to change
18296 the function prologue as little as possible as it isn't easy to
18297 account for arg save/restore code added just for _mcount. */
18298 if (TARGET_PROFILE_KERNEL
)
18301 if (DEFAULT_ABI
== ABI_AIX
)
18303 #ifndef NO_PROFILE_COUNTERS
18304 # define NO_PROFILE_COUNTERS 0
18306 if (NO_PROFILE_COUNTERS
)
18307 emit_library_call (init_one_libfunc (RS6000_MCOUNT
), 0, VOIDmode
, 0);
18311 const char *label_name
;
18314 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
18315 label_name
= (*targetm
.strip_name_encoding
) (ggc_strdup (buf
));
18316 fun
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
18318 emit_library_call (init_one_libfunc (RS6000_MCOUNT
), 0, VOIDmode
, 1,
18322 else if (DEFAULT_ABI
== ABI_DARWIN
)
18324 const char *mcount_name
= RS6000_MCOUNT
;
18325 int caller_addr_regno
= LR_REGNO
;
18327 /* Be conservative and always set this, at least for now. */
18328 crtl
->uses_pic_offset_table
= 1;
18331 /* For PIC code, set up a stub and collect the caller's address
18332 from r0, which is where the prologue puts it. */
18333 if (MACHOPIC_INDIRECT
18334 && crtl
->uses_pic_offset_table
)
18335 caller_addr_regno
= 0;
18337 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, mcount_name
),
18339 gen_rtx_REG (Pmode
, caller_addr_regno
), Pmode
);
18343 /* Write function profiler code. */
18346 output_function_profiler (FILE *file
, int labelno
)
18350 switch (DEFAULT_ABI
)
18353 gcc_unreachable ();
18358 warning (0, "no profiling of 64-bit code for this ABI");
18361 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
18362 fprintf (file
, "\tmflr %s\n", reg_names
[0]);
18363 if (NO_PROFILE_COUNTERS
)
18365 asm_fprintf (file
, "\t{st|stw} %s,4(%s)\n",
18366 reg_names
[0], reg_names
[1]);
18368 else if (TARGET_SECURE_PLT
&& flag_pic
)
18370 asm_fprintf (file
, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
18371 reg_names
[0], reg_names
[1]);
18372 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
18373 asm_fprintf (file
, "\t{cau|addis} %s,%s,",
18374 reg_names
[12], reg_names
[12]);
18375 assemble_name (file
, buf
);
18376 asm_fprintf (file
, "-1b@ha\n\t{cal|la} %s,", reg_names
[0]);
18377 assemble_name (file
, buf
);
18378 asm_fprintf (file
, "-1b@l(%s)\n", reg_names
[12]);
18380 else if (flag_pic
== 1)
18382 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file
);
18383 asm_fprintf (file
, "\t{st|stw} %s,4(%s)\n",
18384 reg_names
[0], reg_names
[1]);
18385 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
18386 asm_fprintf (file
, "\t{l|lwz} %s,", reg_names
[0]);
18387 assemble_name (file
, buf
);
18388 asm_fprintf (file
, "@got(%s)\n", reg_names
[12]);
18390 else if (flag_pic
> 1)
18392 asm_fprintf (file
, "\t{st|stw} %s,4(%s)\n",
18393 reg_names
[0], reg_names
[1]);
18394 /* Now, we need to get the address of the label. */
18395 fputs ("\tbcl 20,31,1f\n\t.long ", file
);
18396 assemble_name (file
, buf
);
18397 fputs ("-.\n1:", file
);
18398 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
18399 asm_fprintf (file
, "\t{l|lwz} %s,0(%s)\n",
18400 reg_names
[0], reg_names
[11]);
18401 asm_fprintf (file
, "\t{cax|add} %s,%s,%s\n",
18402 reg_names
[0], reg_names
[0], reg_names
[11]);
18406 asm_fprintf (file
, "\t{liu|lis} %s,", reg_names
[12]);
18407 assemble_name (file
, buf
);
18408 fputs ("@ha\n", file
);
18409 asm_fprintf (file
, "\t{st|stw} %s,4(%s)\n",
18410 reg_names
[0], reg_names
[1]);
18411 asm_fprintf (file
, "\t{cal|la} %s,", reg_names
[0]);
18412 assemble_name (file
, buf
);
18413 asm_fprintf (file
, "@l(%s)\n", reg_names
[12]);
18416 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
18417 fprintf (file
, "\tbl %s%s\n",
18418 RS6000_MCOUNT
, flag_pic
? "@plt" : "");
18423 if (!TARGET_PROFILE_KERNEL
)
18425 /* Don't do anything, done in output_profile_hook (). */
18429 gcc_assert (!TARGET_32BIT
);
18431 asm_fprintf (file
, "\tmflr %s\n", reg_names
[0]);
18432 asm_fprintf (file
, "\tstd %s,16(%s)\n", reg_names
[0], reg_names
[1]);
18434 if (cfun
->static_chain_decl
!= NULL
)
18436 asm_fprintf (file
, "\tstd %s,24(%s)\n",
18437 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
18438 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
18439 asm_fprintf (file
, "\tld %s,24(%s)\n",
18440 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
18443 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
18451 /* The following variable value is the last issued insn. */
18453 static rtx last_scheduled_insn
;
18455 /* The following variable helps to balance issuing of load and
18456 store instructions */
18458 static int load_store_pendulum
;
18460 /* Power4 load update and store update instructions are cracked into a
18461 load or store and an integer insn which are executed in the same cycle.
18462 Branches have their own dispatch slot which does not count against the
18463 GCC issue rate, but it changes the program flow so there are no other
18464 instructions to issue in this cycle. */
18467 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED
,
18468 int verbose ATTRIBUTE_UNUSED
,
18469 rtx insn
, int more
)
18471 last_scheduled_insn
= insn
;
18472 if (GET_CODE (PATTERN (insn
)) == USE
18473 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
18475 cached_can_issue_more
= more
;
18476 return cached_can_issue_more
;
18479 if (insn_terminates_group_p (insn
, current_group
))
18481 cached_can_issue_more
= 0;
18482 return cached_can_issue_more
;
18485 /* If no reservation, but reach here */
18486 if (recog_memoized (insn
) < 0)
18489 if (rs6000_sched_groups
)
18491 if (is_microcoded_insn (insn
))
18492 cached_can_issue_more
= 0;
18493 else if (is_cracked_insn (insn
))
18494 cached_can_issue_more
= more
> 2 ? more
- 2 : 0;
18496 cached_can_issue_more
= more
- 1;
18498 return cached_can_issue_more
;
18501 if (rs6000_cpu_attr
== CPU_CELL
&& is_nonpipeline_insn (insn
))
18504 cached_can_issue_more
= more
- 1;
18505 return cached_can_issue_more
;
18508 /* Adjust the cost of a scheduling dependency. Return the new cost of
18509 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
18512 rs6000_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
18514 enum attr_type attr_type
;
18516 if (! recog_memoized (insn
))
18519 switch (REG_NOTE_KIND (link
))
18523 /* Data dependency; DEP_INSN writes a register that INSN reads
18524 some cycles later. */
18526 /* Separate a load from a narrower, dependent store. */
18527 if (rs6000_sched_groups
18528 && GET_CODE (PATTERN (insn
)) == SET
18529 && GET_CODE (PATTERN (dep_insn
)) == SET
18530 && GET_CODE (XEXP (PATTERN (insn
), 1)) == MEM
18531 && GET_CODE (XEXP (PATTERN (dep_insn
), 0)) == MEM
18532 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn
), 1)))
18533 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn
), 0)))))
18536 attr_type
= get_attr_type (insn
);
18541 /* Tell the first scheduling pass about the latency between
18542 a mtctr and bctr (and mtlr and br/blr). The first
18543 scheduling pass will not know about this latency since
18544 the mtctr instruction, which has the latency associated
18545 to it, will be generated by reload. */
18546 return TARGET_POWER
? 5 : 4;
18548 /* Leave some extra cycles between a compare and its
18549 dependent branch, to inhibit expensive mispredicts. */
18550 if ((rs6000_cpu_attr
== CPU_PPC603
18551 || rs6000_cpu_attr
== CPU_PPC604
18552 || rs6000_cpu_attr
== CPU_PPC604E
18553 || rs6000_cpu_attr
== CPU_PPC620
18554 || rs6000_cpu_attr
== CPU_PPC630
18555 || rs6000_cpu_attr
== CPU_PPC750
18556 || rs6000_cpu_attr
== CPU_PPC7400
18557 || rs6000_cpu_attr
== CPU_PPC7450
18558 || rs6000_cpu_attr
== CPU_POWER4
18559 || rs6000_cpu_attr
== CPU_POWER5
18560 || rs6000_cpu_attr
== CPU_CELL
)
18561 && recog_memoized (dep_insn
)
18562 && (INSN_CODE (dep_insn
) >= 0))
18564 switch (get_attr_type (dep_insn
))
18568 case TYPE_DELAYED_COMPARE
:
18569 case TYPE_IMUL_COMPARE
:
18570 case TYPE_LMUL_COMPARE
:
18571 case TYPE_FPCOMPARE
:
18572 case TYPE_CR_LOGICAL
:
18573 case TYPE_DELAYED_CR
:
18582 case TYPE_STORE_UX
:
18584 case TYPE_FPSTORE_U
:
18585 case TYPE_FPSTORE_UX
:
18586 if ((rs6000_cpu
== PROCESSOR_POWER6
)
18587 && recog_memoized (dep_insn
)
18588 && (INSN_CODE (dep_insn
) >= 0))
18591 if (GET_CODE (PATTERN (insn
)) != SET
)
18592 /* If this happens, we have to extend this to schedule
18593 optimally. Return default for now. */
18596 /* Adjust the cost for the case where the value written
18597 by a fixed point operation is used as the address
18598 gen value on a store. */
18599 switch (get_attr_type (dep_insn
))
18606 if (! store_data_bypass_p (dep_insn
, insn
))
18610 case TYPE_LOAD_EXT
:
18611 case TYPE_LOAD_EXT_U
:
18612 case TYPE_LOAD_EXT_UX
:
18613 case TYPE_VAR_SHIFT_ROTATE
:
18614 case TYPE_VAR_DELAYED_COMPARE
:
18616 if (! store_data_bypass_p (dep_insn
, insn
))
18622 case TYPE_FAST_COMPARE
:
18625 case TYPE_INSERT_WORD
:
18626 case TYPE_INSERT_DWORD
:
18627 case TYPE_FPLOAD_U
:
18628 case TYPE_FPLOAD_UX
:
18630 case TYPE_STORE_UX
:
18631 case TYPE_FPSTORE_U
:
18632 case TYPE_FPSTORE_UX
:
18634 if (! store_data_bypass_p (dep_insn
, insn
))
18642 case TYPE_IMUL_COMPARE
:
18643 case TYPE_LMUL_COMPARE
:
18645 if (! store_data_bypass_p (dep_insn
, insn
))
18651 if (! store_data_bypass_p (dep_insn
, insn
))
18657 if (! store_data_bypass_p (dep_insn
, insn
))
18670 case TYPE_LOAD_EXT
:
18671 case TYPE_LOAD_EXT_U
:
18672 case TYPE_LOAD_EXT_UX
:
18673 if ((rs6000_cpu
== PROCESSOR_POWER6
)
18674 && recog_memoized (dep_insn
)
18675 && (INSN_CODE (dep_insn
) >= 0))
18678 /* Adjust the cost for the case where the value written
18679 by a fixed point instruction is used within the address
18680 gen portion of a subsequent load(u)(x) */
18681 switch (get_attr_type (dep_insn
))
18688 if (set_to_load_agen (dep_insn
, insn
))
18692 case TYPE_LOAD_EXT
:
18693 case TYPE_LOAD_EXT_U
:
18694 case TYPE_LOAD_EXT_UX
:
18695 case TYPE_VAR_SHIFT_ROTATE
:
18696 case TYPE_VAR_DELAYED_COMPARE
:
18698 if (set_to_load_agen (dep_insn
, insn
))
18704 case TYPE_FAST_COMPARE
:
18707 case TYPE_INSERT_WORD
:
18708 case TYPE_INSERT_DWORD
:
18709 case TYPE_FPLOAD_U
:
18710 case TYPE_FPLOAD_UX
:
18712 case TYPE_STORE_UX
:
18713 case TYPE_FPSTORE_U
:
18714 case TYPE_FPSTORE_UX
:
18716 if (set_to_load_agen (dep_insn
, insn
))
18724 case TYPE_IMUL_COMPARE
:
18725 case TYPE_LMUL_COMPARE
:
18727 if (set_to_load_agen (dep_insn
, insn
))
18733 if (set_to_load_agen (dep_insn
, insn
))
18739 if (set_to_load_agen (dep_insn
, insn
))
18750 if ((rs6000_cpu
== PROCESSOR_POWER6
)
18751 && recog_memoized (dep_insn
)
18752 && (INSN_CODE (dep_insn
) >= 0)
18753 && (get_attr_type (dep_insn
) == TYPE_MFFGPR
))
18760 /* Fall out to return default cost. */
18764 case REG_DEP_OUTPUT
:
18765 /* Output dependency; DEP_INSN writes a register that INSN writes some
18767 if ((rs6000_cpu
== PROCESSOR_POWER6
)
18768 && recog_memoized (dep_insn
)
18769 && (INSN_CODE (dep_insn
) >= 0))
18771 attr_type
= get_attr_type (insn
);
18776 if (get_attr_type (dep_insn
) == TYPE_FP
)
18780 if (get_attr_type (dep_insn
) == TYPE_MFFGPR
)
18788 /* Anti dependency; DEP_INSN reads a register that INSN writes some
18793 gcc_unreachable ();
18799 /* The function returns a true if INSN is microcoded.
18800 Return false otherwise. */
18803 is_microcoded_insn (rtx insn
)
18805 if (!insn
|| !INSN_P (insn
)
18806 || GET_CODE (PATTERN (insn
)) == USE
18807 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
18810 if (rs6000_cpu_attr
== CPU_CELL
)
18811 return get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
;
18813 if (rs6000_sched_groups
)
18815 enum attr_type type
= get_attr_type (insn
);
18816 if (type
== TYPE_LOAD_EXT_U
18817 || type
== TYPE_LOAD_EXT_UX
18818 || type
== TYPE_LOAD_UX
18819 || type
== TYPE_STORE_UX
18820 || type
== TYPE_MFCR
)
18827 /* The function returns true if INSN is cracked into 2 instructions
18828 by the processor (and therefore occupies 2 issue slots). */
18831 is_cracked_insn (rtx insn
)
18833 if (!insn
|| !INSN_P (insn
)
18834 || GET_CODE (PATTERN (insn
)) == USE
18835 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
18838 if (rs6000_sched_groups
)
18840 enum attr_type type
= get_attr_type (insn
);
18841 if (type
== TYPE_LOAD_U
|| type
== TYPE_STORE_U
18842 || type
== TYPE_FPLOAD_U
|| type
== TYPE_FPSTORE_U
18843 || type
== TYPE_FPLOAD_UX
|| type
== TYPE_FPSTORE_UX
18844 || type
== TYPE_LOAD_EXT
|| type
== TYPE_DELAYED_CR
18845 || type
== TYPE_COMPARE
|| type
== TYPE_DELAYED_COMPARE
18846 || type
== TYPE_IMUL_COMPARE
|| type
== TYPE_LMUL_COMPARE
18847 || type
== TYPE_IDIV
|| type
== TYPE_LDIV
18848 || type
== TYPE_INSERT_WORD
)
18855 /* The function returns true if INSN can be issued only from
18856 the branch slot. */
18859 is_branch_slot_insn (rtx insn
)
18861 if (!insn
|| !INSN_P (insn
)
18862 || GET_CODE (PATTERN (insn
)) == USE
18863 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
18866 if (rs6000_sched_groups
)
18868 enum attr_type type
= get_attr_type (insn
);
18869 if (type
== TYPE_BRANCH
|| type
== TYPE_JMPREG
)
18877 /* The function returns true if out_inst sets a value that is
18878 used in the address generation computation of in_insn */
18880 set_to_load_agen (rtx out_insn
, rtx in_insn
)
18882 rtx out_set
, in_set
;
18884 /* For performance reasons, only handle the simple case where
18885 both loads are a single_set. */
18886 out_set
= single_set (out_insn
);
18889 in_set
= single_set (in_insn
);
18891 return reg_mentioned_p (SET_DEST (out_set
), SET_SRC (in_set
));
18897 /* The function returns true if the target storage location of
18898 out_insn is adjacent to the target storage location of in_insn */
18899 /* Return 1 if memory locations are adjacent. */
18902 adjacent_mem_locations (rtx insn1
, rtx insn2
)
18905 rtx a
= get_store_dest (PATTERN (insn1
));
18906 rtx b
= get_store_dest (PATTERN (insn2
));
18908 if ((GET_CODE (XEXP (a
, 0)) == REG
18909 || (GET_CODE (XEXP (a
, 0)) == PLUS
18910 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
18911 && (GET_CODE (XEXP (b
, 0)) == REG
18912 || (GET_CODE (XEXP (b
, 0)) == PLUS
18913 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
18915 HOST_WIDE_INT val0
= 0, val1
= 0, val_diff
;
18918 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
18920 reg0
= XEXP (XEXP (a
, 0), 0);
18921 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
18924 reg0
= XEXP (a
, 0);
18926 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
18928 reg1
= XEXP (XEXP (b
, 0), 0);
18929 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
18932 reg1
= XEXP (b
, 0);
18934 val_diff
= val1
- val0
;
18936 return ((REGNO (reg0
) == REGNO (reg1
))
18937 && ((MEM_SIZE (a
) && val_diff
== INTVAL (MEM_SIZE (a
)))
18938 || (MEM_SIZE (b
) && val_diff
== -INTVAL (MEM_SIZE (b
)))));
18944 /* A C statement (sans semicolon) to update the integer scheduling
18945 priority INSN_PRIORITY (INSN). Increase the priority to execute the
18946 INSN earlier, reduce the priority to execute INSN later. Do not
18947 define this macro if you do not need to adjust the scheduling
18948 priorities of insns. */
18951 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
18953 /* On machines (like the 750) which have asymmetric integer units,
18954 where one integer unit can do multiply and divides and the other
18955 can't, reduce the priority of multiply/divide so it is scheduled
18956 before other integer operations. */
18959 if (! INSN_P (insn
))
18962 if (GET_CODE (PATTERN (insn
)) == USE
)
18965 switch (rs6000_cpu_attr
) {
18967 switch (get_attr_type (insn
))
18974 fprintf (stderr
, "priority was %#x (%d) before adjustment\n",
18975 priority
, priority
);
18976 if (priority
>= 0 && priority
< 0x01000000)
18983 if (insn_must_be_first_in_group (insn
)
18984 && reload_completed
18985 && current_sched_info
->sched_max_insns_priority
18986 && rs6000_sched_restricted_insns_priority
)
18989 /* Prioritize insns that can be dispatched only in the first
18991 if (rs6000_sched_restricted_insns_priority
== 1)
18992 /* Attach highest priority to insn. This means that in
18993 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
18994 precede 'priority' (critical path) considerations. */
18995 return current_sched_info
->sched_max_insns_priority
;
18996 else if (rs6000_sched_restricted_insns_priority
== 2)
18997 /* Increase priority of insn by a minimal amount. This means that in
18998 haifa-sched.c:ready_sort(), only 'priority' (critical path)
18999 considerations precede dispatch-slot restriction considerations. */
19000 return (priority
+ 1);
19003 if (rs6000_cpu
== PROCESSOR_POWER6
19004 && ((load_store_pendulum
== -2 && is_load_insn (insn
))
19005 || (load_store_pendulum
== 2 && is_store_insn (insn
))))
19006 /* Attach highest priority to insn if the scheduler has just issued two
19007 stores and this instruction is a load, or two loads and this instruction
19008 is a store. Power6 wants loads and stores scheduled alternately
19010 return current_sched_info
->sched_max_insns_priority
;
19015 /* Return true if the instruction is nonpipelined on the Cell. */
19017 is_nonpipeline_insn (rtx insn
)
19019 enum attr_type type
;
19020 if (!insn
|| !INSN_P (insn
)
19021 || GET_CODE (PATTERN (insn
)) == USE
19022 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
19025 type
= get_attr_type (insn
);
19026 if (type
== TYPE_IMUL
19027 || type
== TYPE_IMUL2
19028 || type
== TYPE_IMUL3
19029 || type
== TYPE_LMUL
19030 || type
== TYPE_IDIV
19031 || type
== TYPE_LDIV
19032 || type
== TYPE_SDIV
19033 || type
== TYPE_DDIV
19034 || type
== TYPE_SSQRT
19035 || type
== TYPE_DSQRT
19036 || type
== TYPE_MFCR
19037 || type
== TYPE_MFCRF
19038 || type
== TYPE_MFJMPR
)
19046 /* Return how many instructions the machine can issue per cycle. */
19049 rs6000_issue_rate (void)
19051 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
19052 if (!reload_completed
)
19055 switch (rs6000_cpu_attr
) {
19056 case CPU_RIOS1
: /* ? */
19058 case CPU_PPC601
: /* ? */
19067 case CPU_PPCE300C2
:
19068 case CPU_PPCE300C3
:
19069 case CPU_PPCE500MC
:
19086 /* Return how many instructions to look ahead for better insn
19090 rs6000_use_sched_lookahead (void)
19092 if (rs6000_cpu_attr
== CPU_PPC8540
)
19094 if (rs6000_cpu_attr
== CPU_CELL
)
19095 return (reload_completed
? 8 : 0);
19099 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
19101 rs6000_use_sched_lookahead_guard (rtx insn
)
19103 if (rs6000_cpu_attr
!= CPU_CELL
)
19106 if (insn
== NULL_RTX
|| !INSN_P (insn
))
19109 if (!reload_completed
19110 || is_nonpipeline_insn (insn
)
19111 || is_microcoded_insn (insn
))
19117 /* Determine is PAT refers to memory. */
19120 is_mem_ref (rtx pat
)
19126 /* stack_tie does not produce any real memory traffic. */
19127 if (GET_CODE (pat
) == UNSPEC
19128 && XINT (pat
, 1) == UNSPEC_TIE
)
19131 if (GET_CODE (pat
) == MEM
)
19134 /* Recursively process the pattern. */
19135 fmt
= GET_RTX_FORMAT (GET_CODE (pat
));
19137 for (i
= GET_RTX_LENGTH (GET_CODE (pat
)) - 1; i
>= 0 && !ret
; i
--)
19140 ret
|= is_mem_ref (XEXP (pat
, i
));
19141 else if (fmt
[i
] == 'E')
19142 for (j
= XVECLEN (pat
, i
) - 1; j
>= 0; j
--)
19143 ret
|= is_mem_ref (XVECEXP (pat
, i
, j
));
19149 /* Determine if PAT is a PATTERN of a load insn. */
19152 is_load_insn1 (rtx pat
)
19154 if (!pat
|| pat
== NULL_RTX
)
19157 if (GET_CODE (pat
) == SET
)
19158 return is_mem_ref (SET_SRC (pat
));
19160 if (GET_CODE (pat
) == PARALLEL
)
19164 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
19165 if (is_load_insn1 (XVECEXP (pat
, 0, i
)))
19172 /* Determine if INSN loads from memory. */
19175 is_load_insn (rtx insn
)
19177 if (!insn
|| !INSN_P (insn
))
19180 if (GET_CODE (insn
) == CALL_INSN
)
19183 return is_load_insn1 (PATTERN (insn
));
19186 /* Determine if PAT is a PATTERN of a store insn. */
19189 is_store_insn1 (rtx pat
)
19191 if (!pat
|| pat
== NULL_RTX
)
19194 if (GET_CODE (pat
) == SET
)
19195 return is_mem_ref (SET_DEST (pat
));
19197 if (GET_CODE (pat
) == PARALLEL
)
19201 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
19202 if (is_store_insn1 (XVECEXP (pat
, 0, i
)))
19209 /* Determine if INSN stores to memory. */
19212 is_store_insn (rtx insn
)
19214 if (!insn
|| !INSN_P (insn
))
19217 return is_store_insn1 (PATTERN (insn
));
19220 /* Return the dest of a store insn. */
19223 get_store_dest (rtx pat
)
19225 gcc_assert (is_store_insn1 (pat
));
19227 if (GET_CODE (pat
) == SET
)
19228 return SET_DEST (pat
);
19229 else if (GET_CODE (pat
) == PARALLEL
)
19233 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
19235 rtx inner_pat
= XVECEXP (pat
, 0, i
);
19236 if (GET_CODE (inner_pat
) == SET
19237 && is_mem_ref (SET_DEST (inner_pat
)))
19241 /* We shouldn't get here, because we should have either a simple
19242 store insn or a store with update which are covered above. */
19246 /* Returns whether the dependence between INSN and NEXT is considered
19247 costly by the given target. */
19250 rs6000_is_costly_dependence (dep_t dep
, int cost
, int distance
)
19255 /* If the flag is not enabled - no dependence is considered costly;
19256 allow all dependent insns in the same group.
19257 This is the most aggressive option. */
19258 if (rs6000_sched_costly_dep
== no_dep_costly
)
19261 /* If the flag is set to 1 - a dependence is always considered costly;
19262 do not allow dependent instructions in the same group.
19263 This is the most conservative option. */
19264 if (rs6000_sched_costly_dep
== all_deps_costly
)
19267 insn
= DEP_PRO (dep
);
19268 next
= DEP_CON (dep
);
19270 if (rs6000_sched_costly_dep
== store_to_load_dep_costly
19271 && is_load_insn (next
)
19272 && is_store_insn (insn
))
19273 /* Prevent load after store in the same group. */
19276 if (rs6000_sched_costly_dep
== true_store_to_load_dep_costly
19277 && is_load_insn (next
)
19278 && is_store_insn (insn
)
19279 && DEP_TYPE (dep
) == REG_DEP_TRUE
)
19280 /* Prevent load after store in the same group if it is a true
19284 /* The flag is set to X; dependences with latency >= X are considered costly,
19285 and will not be scheduled in the same group. */
19286 if (rs6000_sched_costly_dep
<= max_dep_latency
19287 && ((cost
- distance
) >= (int)rs6000_sched_costly_dep
))
19293 /* Return the next insn after INSN that is found before TAIL is reached,
19294 skipping any "non-active" insns - insns that will not actually occupy
19295 an issue slot. Return NULL_RTX if such an insn is not found. */
19298 get_next_active_insn (rtx insn
, rtx tail
)
19300 if (insn
== NULL_RTX
|| insn
== tail
)
19305 insn
= NEXT_INSN (insn
);
19306 if (insn
== NULL_RTX
|| insn
== tail
)
19311 || (NONJUMP_INSN_P (insn
)
19312 && GET_CODE (PATTERN (insn
)) != USE
19313 && GET_CODE (PATTERN (insn
)) != CLOBBER
19314 && INSN_CODE (insn
) != CODE_FOR_stack_tie
))
19320 /* We are about to begin issuing insns for this clock cycle. */
19323 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED
, int sched_verbose
,
19324 rtx
*ready ATTRIBUTE_UNUSED
,
19325 int *pn_ready ATTRIBUTE_UNUSED
,
19326 int clock_var ATTRIBUTE_UNUSED
)
19328 int n_ready
= *pn_ready
;
19331 fprintf (dump
, "// rs6000_sched_reorder :\n");
19333 /* Reorder the ready list, if the second to last ready insn
19334 is a nonepipeline insn. */
19335 if (rs6000_cpu_attr
== CPU_CELL
&& n_ready
> 1)
19337 if (is_nonpipeline_insn (ready
[n_ready
- 1])
19338 && (recog_memoized (ready
[n_ready
- 2]) > 0))
19339 /* Simply swap first two insns. */
19341 rtx tmp
= ready
[n_ready
- 1];
19342 ready
[n_ready
- 1] = ready
[n_ready
- 2];
19343 ready
[n_ready
- 2] = tmp
;
19347 if (rs6000_cpu
== PROCESSOR_POWER6
)
19348 load_store_pendulum
= 0;
19350 return rs6000_issue_rate ();
19353 /* Like rs6000_sched_reorder, but called after issuing each insn. */
19356 rs6000_sched_reorder2 (FILE *dump
, int sched_verbose
, rtx
*ready
,
19357 int *pn_ready
, int clock_var ATTRIBUTE_UNUSED
)
19360 fprintf (dump
, "// rs6000_sched_reorder2 :\n");
19362 /* For Power6, we need to handle some special cases to try and keep the
19363 store queue from overflowing and triggering expensive flushes.
19365 This code monitors how load and store instructions are being issued
19366 and skews the ready list one way or the other to increase the likelihood
19367 that a desired instruction is issued at the proper time.
19369 A couple of things are done. First, we maintain a "load_store_pendulum"
19370 to track the current state of load/store issue.
19372 - If the pendulum is at zero, then no loads or stores have been
19373 issued in the current cycle so we do nothing.
19375 - If the pendulum is 1, then a single load has been issued in this
19376 cycle and we attempt to locate another load in the ready list to
19379 - If the pendulum is -2, then two stores have already been
19380 issued in this cycle, so we increase the priority of the first load
19381 in the ready list to increase it's likelihood of being chosen first
19384 - If the pendulum is -1, then a single store has been issued in this
19385 cycle and we attempt to locate another store in the ready list to
19386 issue with it, preferring a store to an adjacent memory location to
19387 facilitate store pairing in the store queue.
19389 - If the pendulum is 2, then two loads have already been
19390 issued in this cycle, so we increase the priority of the first store
19391 in the ready list to increase it's likelihood of being chosen first
19394 - If the pendulum < -2 or > 2, then do nothing.
19396 Note: This code covers the most common scenarios. There exist non
19397 load/store instructions which make use of the LSU and which
19398 would need to be accounted for to strictly model the behavior
19399 of the machine. Those instructions are currently unaccounted
19400 for to help minimize compile time overhead of this code.
19402 if (rs6000_cpu
== PROCESSOR_POWER6
&& last_scheduled_insn
)
19408 if (is_store_insn (last_scheduled_insn
))
19409 /* Issuing a store, swing the load_store_pendulum to the left */
19410 load_store_pendulum
--;
19411 else if (is_load_insn (last_scheduled_insn
))
19412 /* Issuing a load, swing the load_store_pendulum to the right */
19413 load_store_pendulum
++;
19415 return cached_can_issue_more
;
19417 /* If the pendulum is balanced, or there is only one instruction on
19418 the ready list, then all is well, so return. */
19419 if ((load_store_pendulum
== 0) || (*pn_ready
<= 1))
19420 return cached_can_issue_more
;
19422 if (load_store_pendulum
== 1)
19424 /* A load has been issued in this cycle. Scan the ready list
19425 for another load to issue with it */
19430 if (is_load_insn (ready
[pos
]))
19432 /* Found a load. Move it to the head of the ready list,
19433 and adjust it's priority so that it is more likely to
19436 for (i
=pos
; i
<*pn_ready
-1; i
++)
19437 ready
[i
] = ready
[i
+ 1];
19438 ready
[*pn_ready
-1] = tmp
;
19439 if INSN_PRIORITY_KNOWN (tmp
)
19440 INSN_PRIORITY (tmp
)++;
19446 else if (load_store_pendulum
== -2)
19448 /* Two stores have been issued in this cycle. Increase the
19449 priority of the first load in the ready list to favor it for
19450 issuing in the next cycle. */
19455 if (is_load_insn (ready
[pos
])
19456 && INSN_PRIORITY_KNOWN (ready
[pos
]))
19458 INSN_PRIORITY (ready
[pos
])++;
19460 /* Adjust the pendulum to account for the fact that a load
19461 was found and increased in priority. This is to prevent
19462 increasing the priority of multiple loads */
19463 load_store_pendulum
--;
19470 else if (load_store_pendulum
== -1)
19472 /* A store has been issued in this cycle. Scan the ready list for
19473 another store to issue with it, preferring a store to an adjacent
19475 int first_store_pos
= -1;
19481 if (is_store_insn (ready
[pos
]))
19483 /* Maintain the index of the first store found on the
19485 if (first_store_pos
== -1)
19486 first_store_pos
= pos
;
19488 if (is_store_insn (last_scheduled_insn
)
19489 && adjacent_mem_locations (last_scheduled_insn
,ready
[pos
]))
19491 /* Found an adjacent store. Move it to the head of the
19492 ready list, and adjust it's priority so that it is
19493 more likely to stay there */
19495 for (i
=pos
; i
<*pn_ready
-1; i
++)
19496 ready
[i
] = ready
[i
+ 1];
19497 ready
[*pn_ready
-1] = tmp
;
19498 if INSN_PRIORITY_KNOWN (tmp
)
19499 INSN_PRIORITY (tmp
)++;
19500 first_store_pos
= -1;
19508 if (first_store_pos
>= 0)
19510 /* An adjacent store wasn't found, but a non-adjacent store was,
19511 so move the non-adjacent store to the front of the ready
19512 list, and adjust its priority so that it is more likely to
19514 tmp
= ready
[first_store_pos
];
19515 for (i
=first_store_pos
; i
<*pn_ready
-1; i
++)
19516 ready
[i
] = ready
[i
+ 1];
19517 ready
[*pn_ready
-1] = tmp
;
19518 if INSN_PRIORITY_KNOWN (tmp
)
19519 INSN_PRIORITY (tmp
)++;
19522 else if (load_store_pendulum
== 2)
19524 /* Two loads have been issued in this cycle. Increase the priority
19525 of the first store in the ready list to favor it for issuing in
19531 if (is_store_insn (ready
[pos
])
19532 && INSN_PRIORITY_KNOWN (ready
[pos
]))
19534 INSN_PRIORITY (ready
[pos
])++;
19536 /* Adjust the pendulum to account for the fact that a store
19537 was found and increased in priority. This is to prevent
19538 increasing the priority of multiple stores */
19539 load_store_pendulum
++;
19548 return cached_can_issue_more
;
19551 /* Return whether the presence of INSN causes a dispatch group termination
19552 of group WHICH_GROUP.
19554 If WHICH_GROUP == current_group, this function will return true if INSN
19555 causes the termination of the current group (i.e, the dispatch group to
19556 which INSN belongs). This means that INSN will be the last insn in the
19557 group it belongs to.
19559 If WHICH_GROUP == previous_group, this function will return true if INSN
19560 causes the termination of the previous group (i.e, the dispatch group that
19561 precedes the group to which INSN belongs). This means that INSN will be
19562 the first insn in the group it belongs to). */
19565 insn_terminates_group_p (rtx insn
, enum group_termination which_group
)
19572 first
= insn_must_be_first_in_group (insn
);
19573 last
= insn_must_be_last_in_group (insn
);
19578 if (which_group
== current_group
)
19580 else if (which_group
== previous_group
)
19588 insn_must_be_first_in_group (rtx insn
)
19590 enum attr_type type
;
19593 || insn
== NULL_RTX
19594 || GET_CODE (insn
) == NOTE
19595 || GET_CODE (PATTERN (insn
)) == USE
19596 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
19599 switch (rs6000_cpu
)
19601 case PROCESSOR_POWER5
:
19602 if (is_cracked_insn (insn
))
19604 case PROCESSOR_POWER4
:
19605 if (is_microcoded_insn (insn
))
19608 if (!rs6000_sched_groups
)
19611 type
= get_attr_type (insn
);
19618 case TYPE_DELAYED_CR
:
19619 case TYPE_CR_LOGICAL
:
19633 case PROCESSOR_POWER6
:
19634 type
= get_attr_type (insn
);
19638 case TYPE_INSERT_DWORD
:
19642 case TYPE_VAR_SHIFT_ROTATE
:
19649 case TYPE_INSERT_WORD
:
19650 case TYPE_DELAYED_COMPARE
:
19651 case TYPE_IMUL_COMPARE
:
19652 case TYPE_LMUL_COMPARE
:
19653 case TYPE_FPCOMPARE
:
19664 case TYPE_LOAD_EXT_UX
:
19666 case TYPE_STORE_UX
:
19667 case TYPE_FPLOAD_U
:
19668 case TYPE_FPLOAD_UX
:
19669 case TYPE_FPSTORE_U
:
19670 case TYPE_FPSTORE_UX
:
19684 insn_must_be_last_in_group (rtx insn
)
19686 enum attr_type type
;
19689 || insn
== NULL_RTX
19690 || GET_CODE (insn
) == NOTE
19691 || GET_CODE (PATTERN (insn
)) == USE
19692 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
19695 switch (rs6000_cpu
) {
19696 case PROCESSOR_POWER4
:
19697 case PROCESSOR_POWER5
:
19698 if (is_microcoded_insn (insn
))
19701 if (is_branch_slot_insn (insn
))
19705 case PROCESSOR_POWER6
:
19706 type
= get_attr_type (insn
);
19713 case TYPE_VAR_SHIFT_ROTATE
:
19720 case TYPE_DELAYED_COMPARE
:
19721 case TYPE_IMUL_COMPARE
:
19722 case TYPE_LMUL_COMPARE
:
19723 case TYPE_FPCOMPARE
:
19744 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
19745 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
19748 is_costly_group (rtx
*group_insns
, rtx next_insn
)
19751 int issue_rate
= rs6000_issue_rate ();
19753 for (i
= 0; i
< issue_rate
; i
++)
19755 sd_iterator_def sd_it
;
19757 rtx insn
= group_insns
[i
];
19762 FOR_EACH_DEP (insn
, SD_LIST_FORW
, sd_it
, dep
)
19764 rtx next
= DEP_CON (dep
);
19766 if (next
== next_insn
19767 && rs6000_is_costly_dependence (dep
, dep_cost (dep
), 0))
19775 /* Utility of the function redefine_groups.
19776 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
19777 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
19778 to keep it "far" (in a separate group) from GROUP_INSNS, following
19779 one of the following schemes, depending on the value of the flag
19780 -minsert_sched_nops = X:
19781 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
19782 in order to force NEXT_INSN into a separate group.
19783 (2) X < sched_finish_regroup_exact: insert exactly X nops.
19784 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
19785 insertion (has a group just ended, how many vacant issue slots remain in the
19786 last group, and how many dispatch groups were encountered so far). */
19789 force_new_group (int sched_verbose
, FILE *dump
, rtx
*group_insns
,
19790 rtx next_insn
, bool *group_end
, int can_issue_more
,
19795 int issue_rate
= rs6000_issue_rate ();
19796 bool end
= *group_end
;
19799 if (next_insn
== NULL_RTX
)
19800 return can_issue_more
;
19802 if (rs6000_sched_insert_nops
> sched_finish_regroup_exact
)
19803 return can_issue_more
;
19805 force
= is_costly_group (group_insns
, next_insn
);
19807 return can_issue_more
;
19809 if (sched_verbose
> 6)
19810 fprintf (dump
,"force: group count = %d, can_issue_more = %d\n",
19811 *group_count
,can_issue_more
);
19813 if (rs6000_sched_insert_nops
== sched_finish_regroup_exact
)
19816 can_issue_more
= 0;
19818 /* Since only a branch can be issued in the last issue_slot, it is
19819 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
19820 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
19821 in this case the last nop will start a new group and the branch
19822 will be forced to the new group. */
19823 if (can_issue_more
&& !is_branch_slot_insn (next_insn
))
19826 while (can_issue_more
> 0)
19829 emit_insn_before (nop
, next_insn
);
19837 if (rs6000_sched_insert_nops
< sched_finish_regroup_exact
)
19839 int n_nops
= rs6000_sched_insert_nops
;
19841 /* Nops can't be issued from the branch slot, so the effective
19842 issue_rate for nops is 'issue_rate - 1'. */
19843 if (can_issue_more
== 0)
19844 can_issue_more
= issue_rate
;
19846 if (can_issue_more
== 0)
19848 can_issue_more
= issue_rate
- 1;
19851 for (i
= 0; i
< issue_rate
; i
++)
19853 group_insns
[i
] = 0;
19860 emit_insn_before (nop
, next_insn
);
19861 if (can_issue_more
== issue_rate
- 1) /* new group begins */
19864 if (can_issue_more
== 0)
19866 can_issue_more
= issue_rate
- 1;
19869 for (i
= 0; i
< issue_rate
; i
++)
19871 group_insns
[i
] = 0;
19877 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
19880 /* Is next_insn going to start a new group? */
19883 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
19884 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
19885 || (can_issue_more
< issue_rate
&&
19886 insn_terminates_group_p (next_insn
, previous_group
)));
19887 if (*group_end
&& end
)
19890 if (sched_verbose
> 6)
19891 fprintf (dump
, "done force: group count = %d, can_issue_more = %d\n",
19892 *group_count
, can_issue_more
);
19893 return can_issue_more
;
19896 return can_issue_more
;
19899 /* This function tries to synch the dispatch groups that the compiler "sees"
19900 with the dispatch groups that the processor dispatcher is expected to
19901 form in practice. It tries to achieve this synchronization by forcing the
19902 estimated processor grouping on the compiler (as opposed to the function
19903 'pad_goups' which tries to force the scheduler's grouping on the processor).
19905 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
19906 examines the (estimated) dispatch groups that will be formed by the processor
19907 dispatcher. It marks these group boundaries to reflect the estimated
19908 processor grouping, overriding the grouping that the scheduler had marked.
19909 Depending on the value of the flag '-minsert-sched-nops' this function can
19910 force certain insns into separate groups or force a certain distance between
19911 them by inserting nops, for example, if there exists a "costly dependence"
19914 The function estimates the group boundaries that the processor will form as
19915 follows: It keeps track of how many vacant issue slots are available after
19916 each insn. A subsequent insn will start a new group if one of the following
19918 - no more vacant issue slots remain in the current dispatch group.
19919 - only the last issue slot, which is the branch slot, is vacant, but the next
19920 insn is not a branch.
19921 - only the last 2 or less issue slots, including the branch slot, are vacant,
19922 which means that a cracked insn (which occupies two issue slots) can't be
19923 issued in this group.
19924 - less than 'issue_rate' slots are vacant, and the next insn always needs to
19925 start a new group. */
19928 redefine_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
19930 rtx insn
, next_insn
;
19932 int can_issue_more
;
19935 int group_count
= 0;
19939 issue_rate
= rs6000_issue_rate ();
19940 group_insns
= XALLOCAVEC (rtx
, issue_rate
);
19941 for (i
= 0; i
< issue_rate
; i
++)
19943 group_insns
[i
] = 0;
19945 can_issue_more
= issue_rate
;
19947 insn
= get_next_active_insn (prev_head_insn
, tail
);
19950 while (insn
!= NULL_RTX
)
19952 slot
= (issue_rate
- can_issue_more
);
19953 group_insns
[slot
] = insn
;
19955 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
19956 if (insn_terminates_group_p (insn
, current_group
))
19957 can_issue_more
= 0;
19959 next_insn
= get_next_active_insn (insn
, tail
);
19960 if (next_insn
== NULL_RTX
)
19961 return group_count
+ 1;
19963 /* Is next_insn going to start a new group? */
19965 = (can_issue_more
== 0
19966 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
19967 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
19968 || (can_issue_more
< issue_rate
&&
19969 insn_terminates_group_p (next_insn
, previous_group
)));
19971 can_issue_more
= force_new_group (sched_verbose
, dump
, group_insns
,
19972 next_insn
, &group_end
, can_issue_more
,
19978 can_issue_more
= 0;
19979 for (i
= 0; i
< issue_rate
; i
++)
19981 group_insns
[i
] = 0;
19985 if (GET_MODE (next_insn
) == TImode
&& can_issue_more
)
19986 PUT_MODE (next_insn
, VOIDmode
);
19987 else if (!can_issue_more
&& GET_MODE (next_insn
) != TImode
)
19988 PUT_MODE (next_insn
, TImode
);
19991 if (can_issue_more
== 0)
19992 can_issue_more
= issue_rate
;
19995 return group_count
;
19998 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
19999 dispatch group boundaries that the scheduler had marked. Pad with nops
20000 any dispatch groups which have vacant issue slots, in order to force the
20001 scheduler's grouping on the processor dispatcher. The function
20002 returns the number of dispatch groups found. */
20005 pad_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
20007 rtx insn
, next_insn
;
20010 int can_issue_more
;
20012 int group_count
= 0;
20014 /* Initialize issue_rate. */
20015 issue_rate
= rs6000_issue_rate ();
20016 can_issue_more
= issue_rate
;
20018 insn
= get_next_active_insn (prev_head_insn
, tail
);
20019 next_insn
= get_next_active_insn (insn
, tail
);
20021 while (insn
!= NULL_RTX
)
20024 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
20026 group_end
= (next_insn
== NULL_RTX
|| GET_MODE (next_insn
) == TImode
);
20028 if (next_insn
== NULL_RTX
)
20033 /* If the scheduler had marked group termination at this location
20034 (between insn and next_indn), and neither insn nor next_insn will
20035 force group termination, pad the group with nops to force group
20038 && (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
20039 && !insn_terminates_group_p (insn
, current_group
)
20040 && !insn_terminates_group_p (next_insn
, previous_group
))
20042 if (!is_branch_slot_insn (next_insn
))
20045 while (can_issue_more
)
20048 emit_insn_before (nop
, next_insn
);
20053 can_issue_more
= issue_rate
;
20058 next_insn
= get_next_active_insn (insn
, tail
);
20061 return group_count
;
20064 /* We're beginning a new block. Initialize data structures as necessary. */
20067 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
20068 int sched_verbose ATTRIBUTE_UNUSED
,
20069 int max_ready ATTRIBUTE_UNUSED
)
20071 last_scheduled_insn
= NULL_RTX
;
20072 load_store_pendulum
= 0;
20075 /* The following function is called at the end of scheduling BB.
20076 After reload, it inserts nops at insn group bundling. */
20079 rs6000_sched_finish (FILE *dump
, int sched_verbose
)
20084 fprintf (dump
, "=== Finishing schedule.\n");
20086 if (reload_completed
&& rs6000_sched_groups
)
20088 if (rs6000_sched_insert_nops
== sched_finish_none
)
20091 if (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
20092 n_groups
= pad_groups (dump
, sched_verbose
,
20093 current_sched_info
->prev_head
,
20094 current_sched_info
->next_tail
);
20096 n_groups
= redefine_groups (dump
, sched_verbose
,
20097 current_sched_info
->prev_head
,
20098 current_sched_info
->next_tail
);
20100 if (sched_verbose
>= 6)
20102 fprintf (dump
, "ngroups = %d\n", n_groups
);
20103 print_rtl (dump
, current_sched_info
->prev_head
);
20104 fprintf (dump
, "Done finish_sched\n");
20109 /* Length in units of the trampoline for entering a nested function. */
20112 rs6000_trampoline_size (void)
20116 switch (DEFAULT_ABI
)
20119 gcc_unreachable ();
20122 ret
= (TARGET_32BIT
) ? 12 : 24;
20127 ret
= (TARGET_32BIT
) ? 40 : 48;
20134 /* Emit RTL insns to initialize the variable parts of a trampoline.
20135 FNADDR is an RTX for the address of the function's pure code.
20136 CXT is an RTX for the static chain value for the function. */
20139 rs6000_initialize_trampoline (rtx addr
, rtx fnaddr
, rtx cxt
)
20141 int regsize
= (TARGET_32BIT
) ? 4 : 8;
20142 rtx ctx_reg
= force_reg (Pmode
, cxt
);
20144 switch (DEFAULT_ABI
)
20147 gcc_unreachable ();
20149 /* Macros to shorten the code expansions below. */
20150 #define MEM_DEREF(addr) gen_rtx_MEM (Pmode, memory_address (Pmode, addr))
20151 #define MEM_PLUS(addr,offset) \
20152 gen_rtx_MEM (Pmode, memory_address (Pmode, plus_constant (addr, offset)))
20154 /* Under AIX, just build the 3 word function descriptor */
20157 rtx fn_reg
= gen_reg_rtx (Pmode
);
20158 rtx toc_reg
= gen_reg_rtx (Pmode
);
20159 emit_move_insn (fn_reg
, MEM_DEREF (fnaddr
));
20160 emit_move_insn (toc_reg
, MEM_PLUS (fnaddr
, regsize
));
20161 emit_move_insn (MEM_DEREF (addr
), fn_reg
);
20162 emit_move_insn (MEM_PLUS (addr
, regsize
), toc_reg
);
20163 emit_move_insn (MEM_PLUS (addr
, 2*regsize
), ctx_reg
);
20167 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
20170 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__trampoline_setup"),
20171 FALSE
, VOIDmode
, 4,
20173 GEN_INT (rs6000_trampoline_size ()), SImode
,
20183 /* Table of valid machine attributes. */
20185 const struct attribute_spec rs6000_attribute_table
[] =
20187 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
20188 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute
},
20189 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
},
20190 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
},
20191 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
},
20192 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
},
20193 #ifdef SUBTARGET_ATTRIBUTE_TABLE
20194 SUBTARGET_ATTRIBUTE_TABLE
,
20196 { NULL
, 0, 0, false, false, false, NULL
}
20199 /* Handle the "altivec" attribute. The attribute may have
20200 arguments as follows:
20202 __attribute__((altivec(vector__)))
20203 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
20204 __attribute__((altivec(bool__))) (always followed by 'unsigned')
20206 and may appear more than once (e.g., 'vector bool char') in a
20207 given declaration. */
20210 rs6000_handle_altivec_attribute (tree
*node
,
20211 tree name ATTRIBUTE_UNUSED
,
20213 int flags ATTRIBUTE_UNUSED
,
20214 bool *no_add_attrs
)
20216 tree type
= *node
, result
= NULL_TREE
;
20217 enum machine_mode mode
;
20220 = ((args
&& TREE_CODE (args
) == TREE_LIST
&& TREE_VALUE (args
)
20221 && TREE_CODE (TREE_VALUE (args
)) == IDENTIFIER_NODE
)
20222 ? *IDENTIFIER_POINTER (TREE_VALUE (args
))
20225 while (POINTER_TYPE_P (type
)
20226 || TREE_CODE (type
) == FUNCTION_TYPE
20227 || TREE_CODE (type
) == METHOD_TYPE
20228 || TREE_CODE (type
) == ARRAY_TYPE
)
20229 type
= TREE_TYPE (type
);
20231 mode
= TYPE_MODE (type
);
20233 /* Check for invalid AltiVec type qualifiers. */
20234 if (type
== long_unsigned_type_node
|| type
== long_integer_type_node
)
20237 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
20238 else if (rs6000_warn_altivec_long
)
20239 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
20241 else if (type
== long_long_unsigned_type_node
20242 || type
== long_long_integer_type_node
)
20243 error ("use of %<long long%> in AltiVec types is invalid");
20244 else if (type
== double_type_node
)
20245 error ("use of %<double%> in AltiVec types is invalid");
20246 else if (type
== long_double_type_node
)
20247 error ("use of %<long double%> in AltiVec types is invalid");
20248 else if (type
== boolean_type_node
)
20249 error ("use of boolean types in AltiVec types is invalid");
20250 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
20251 error ("use of %<complex%> in AltiVec types is invalid");
20252 else if (DECIMAL_FLOAT_MODE_P (mode
))
20253 error ("use of decimal floating point types in AltiVec types is invalid");
20255 switch (altivec_type
)
20258 unsigned_p
= TYPE_UNSIGNED (type
);
20262 result
= (unsigned_p
? unsigned_V4SI_type_node
: V4SI_type_node
);
20265 result
= (unsigned_p
? unsigned_V8HI_type_node
: V8HI_type_node
);
20268 result
= (unsigned_p
? unsigned_V16QI_type_node
: V16QI_type_node
);
20270 case SFmode
: result
= V4SF_type_node
; break;
20271 /* If the user says 'vector int bool', we may be handed the 'bool'
20272 attribute _before_ the 'vector' attribute, and so select the
20273 proper type in the 'b' case below. */
20274 case V4SImode
: case V8HImode
: case V16QImode
: case V4SFmode
:
20282 case SImode
: case V4SImode
: result
= bool_V4SI_type_node
; break;
20283 case HImode
: case V8HImode
: result
= bool_V8HI_type_node
; break;
20284 case QImode
: case V16QImode
: result
= bool_V16QI_type_node
;
20291 case V8HImode
: result
= pixel_V8HI_type_node
;
20297 /* Propagate qualifiers attached to the element type
20298 onto the vector type. */
20299 if (result
&& result
!= type
&& TYPE_QUALS (type
))
20300 result
= build_qualified_type (result
, TYPE_QUALS (type
));
20302 *no_add_attrs
= true; /* No need to hang on to the attribute. */
20305 *node
= lang_hooks
.types
.reconstruct_complex_type (*node
, result
);
20310 /* AltiVec defines four built-in scalar types that serve as vector
20311 elements; we must teach the compiler how to mangle them. */
20313 static const char *
20314 rs6000_mangle_type (const_tree type
)
20316 type
= TYPE_MAIN_VARIANT (type
);
20318 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
20319 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
20322 if (type
== bool_char_type_node
) return "U6__boolc";
20323 if (type
== bool_short_type_node
) return "U6__bools";
20324 if (type
== pixel_type_node
) return "u7__pixel";
20325 if (type
== bool_int_type_node
) return "U6__booli";
20327 /* Mangle IBM extended float long double as `g' (__float128) on
20328 powerpc*-linux where long-double-64 previously was the default. */
20329 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
20331 && TARGET_LONG_DOUBLE_128
20332 && !TARGET_IEEEQUAD
)
20335 /* For all other types, use normal C++ mangling. */
20339 /* Handle a "longcall" or "shortcall" attribute; arguments as in
20340 struct attribute_spec.handler. */
20343 rs6000_handle_longcall_attribute (tree
*node
, tree name
,
20344 tree args ATTRIBUTE_UNUSED
,
20345 int flags ATTRIBUTE_UNUSED
,
20346 bool *no_add_attrs
)
20348 if (TREE_CODE (*node
) != FUNCTION_TYPE
20349 && TREE_CODE (*node
) != FIELD_DECL
20350 && TREE_CODE (*node
) != TYPE_DECL
)
20352 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
20353 IDENTIFIER_POINTER (name
));
20354 *no_add_attrs
= true;
20360 /* Set longcall attributes on all functions declared when
20361 rs6000_default_long_calls is true. */
20363 rs6000_set_default_type_attributes (tree type
)
20365 if (rs6000_default_long_calls
20366 && (TREE_CODE (type
) == FUNCTION_TYPE
20367 || TREE_CODE (type
) == METHOD_TYPE
))
20368 TYPE_ATTRIBUTES (type
) = tree_cons (get_identifier ("longcall"),
20370 TYPE_ATTRIBUTES (type
));
20373 darwin_set_default_type_attributes (type
);
20377 /* Return a reference suitable for calling a function with the
20378 longcall attribute. */
20381 rs6000_longcall_ref (rtx call_ref
)
20383 const char *call_name
;
20386 if (GET_CODE (call_ref
) != SYMBOL_REF
)
20389 /* System V adds '.' to the internal name, so skip them. */
20390 call_name
= XSTR (call_ref
, 0);
20391 if (*call_name
== '.')
20393 while (*call_name
== '.')
20396 node
= get_identifier (call_name
);
20397 call_ref
= gen_rtx_SYMBOL_REF (VOIDmode
, IDENTIFIER_POINTER (node
));
20400 return force_reg (Pmode
, call_ref
);
20403 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
20404 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
20407 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
20408 struct attribute_spec.handler. */
20410 rs6000_handle_struct_attribute (tree
*node
, tree name
,
20411 tree args ATTRIBUTE_UNUSED
,
20412 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
20415 if (DECL_P (*node
))
20417 if (TREE_CODE (*node
) == TYPE_DECL
)
20418 type
= &TREE_TYPE (*node
);
20423 if (!(type
&& (TREE_CODE (*type
) == RECORD_TYPE
20424 || TREE_CODE (*type
) == UNION_TYPE
)))
20426 warning (OPT_Wattributes
, "%qs attribute ignored", IDENTIFIER_POINTER (name
));
20427 *no_add_attrs
= true;
20430 else if ((is_attribute_p ("ms_struct", name
)
20431 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type
)))
20432 || ((is_attribute_p ("gcc_struct", name
)
20433 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type
)))))
20435 warning (OPT_Wattributes
, "%qs incompatible attribute ignored",
20436 IDENTIFIER_POINTER (name
));
20437 *no_add_attrs
= true;
20444 rs6000_ms_bitfield_layout_p (const_tree record_type
)
20446 return (TARGET_USE_MS_BITFIELD_LAYOUT
&&
20447 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type
)))
20448 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type
));
20451 #ifdef USING_ELFOS_H
20453 /* A get_unnamed_section callback, used for switching to toc_section. */
20456 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
20458 if (DEFAULT_ABI
== ABI_AIX
20459 && TARGET_MINIMAL_TOC
20460 && !TARGET_RELOCATABLE
)
20462 if (!toc_initialized
)
20464 toc_initialized
= 1;
20465 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
20466 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LCTOC", 0);
20467 fprintf (asm_out_file
, "\t.tc ");
20468 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1[TC],");
20469 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
20470 fprintf (asm_out_file
, "\n");
20472 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
20473 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
20474 fprintf (asm_out_file
, " = .+32768\n");
20477 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
20479 else if (DEFAULT_ABI
== ABI_AIX
&& !TARGET_RELOCATABLE
)
20480 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
20483 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
20484 if (!toc_initialized
)
20486 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
20487 fprintf (asm_out_file
, " = .+32768\n");
20488 toc_initialized
= 1;
20493 /* Implement TARGET_ASM_INIT_SECTIONS. */
20496 rs6000_elf_asm_init_sections (void)
20499 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op
, NULL
);
20502 = get_unnamed_section (SECTION_WRITE
, output_section_asm_op
,
20503 SDATA2_SECTION_ASM_OP
);
20506 /* Implement TARGET_SELECT_RTX_SECTION. */
20509 rs6000_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
20510 unsigned HOST_WIDE_INT align
)
20512 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
20513 return toc_section
;
20515 return default_elf_select_rtx_section (mode
, x
, align
);
20518 /* For a SYMBOL_REF, set generic flags and then perform some
20519 target-specific processing.
20521 When the AIX ABI is requested on a non-AIX system, replace the
20522 function name with the real name (with a leading .) rather than the
20523 function descriptor name. This saves a lot of overriding code to
20524 read the prefixes. */
20527 rs6000_elf_encode_section_info (tree decl
, rtx rtl
, int first
)
20529 default_encode_section_info (decl
, rtl
, first
);
20532 && TREE_CODE (decl
) == FUNCTION_DECL
20534 && DEFAULT_ABI
== ABI_AIX
)
20536 rtx sym_ref
= XEXP (rtl
, 0);
20537 size_t len
= strlen (XSTR (sym_ref
, 0));
20538 char *str
= XALLOCAVEC (char, len
+ 2);
20540 memcpy (str
+ 1, XSTR (sym_ref
, 0), len
+ 1);
20541 XSTR (sym_ref
, 0) = ggc_alloc_string (str
, len
+ 1);
20546 compare_section_name (const char *section
, const char *templ
)
20550 len
= strlen (templ
);
20551 return (strncmp (section
, templ
, len
) == 0
20552 && (section
[len
] == 0 || section
[len
] == '.'));
20556 rs6000_elf_in_small_data_p (const_tree decl
)
20558 if (rs6000_sdata
== SDATA_NONE
)
20561 /* We want to merge strings, so we never consider them small data. */
20562 if (TREE_CODE (decl
) == STRING_CST
)
20565 /* Functions are never in the small data area. */
20566 if (TREE_CODE (decl
) == FUNCTION_DECL
)
20569 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
))
20571 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
20572 if (compare_section_name (section
, ".sdata")
20573 || compare_section_name (section
, ".sdata2")
20574 || compare_section_name (section
, ".gnu.linkonce.s")
20575 || compare_section_name (section
, ".sbss")
20576 || compare_section_name (section
, ".sbss2")
20577 || compare_section_name (section
, ".gnu.linkonce.sb")
20578 || strcmp (section
, ".PPC.EMB.sdata0") == 0
20579 || strcmp (section
, ".PPC.EMB.sbss0") == 0)
20584 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
20587 && (unsigned HOST_WIDE_INT
) size
<= g_switch_value
20588 /* If it's not public, and we're not going to reference it there,
20589 there's no need to put it in the small data section. */
20590 && (rs6000_sdata
!= SDATA_DATA
|| TREE_PUBLIC (decl
)))
20597 #endif /* USING_ELFOS_H */
20599 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
20602 rs6000_use_blocks_for_constant_p (enum machine_mode mode
, const_rtx x
)
20604 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
);
20607 /* Return a REG that occurs in ADDR with coefficient 1.
20608 ADDR can be effectively incremented by incrementing REG.
20610 r0 is special and we must not select it as an address
20611 register by this routine since our caller will try to
20612 increment the returned register via an "la" instruction. */
20615 find_addr_reg (rtx addr
)
20617 while (GET_CODE (addr
) == PLUS
)
20619 if (GET_CODE (XEXP (addr
, 0)) == REG
20620 && REGNO (XEXP (addr
, 0)) != 0)
20621 addr
= XEXP (addr
, 0);
20622 else if (GET_CODE (XEXP (addr
, 1)) == REG
20623 && REGNO (XEXP (addr
, 1)) != 0)
20624 addr
= XEXP (addr
, 1);
20625 else if (CONSTANT_P (XEXP (addr
, 0)))
20626 addr
= XEXP (addr
, 1);
20627 else if (CONSTANT_P (XEXP (addr
, 1)))
20628 addr
= XEXP (addr
, 0);
20630 gcc_unreachable ();
20632 gcc_assert (GET_CODE (addr
) == REG
&& REGNO (addr
) != 0);
20637 rs6000_fatal_bad_address (rtx op
)
20639 fatal_insn ("bad address", op
);
20644 static tree branch_island_list
= 0;
20646 /* Remember to generate a branch island for far calls to the given
20650 add_compiler_branch_island (tree label_name
, tree function_name
,
20653 tree branch_island
= build_tree_list (function_name
, label_name
);
20654 TREE_TYPE (branch_island
) = build_int_cst (NULL_TREE
, line_number
);
20655 TREE_CHAIN (branch_island
) = branch_island_list
;
20656 branch_island_list
= branch_island
;
20659 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
20660 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
20661 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
20662 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
20664 /* Generate far-jump branch islands for everything on the
20665 branch_island_list. Invoked immediately after the last instruction
20666 of the epilogue has been emitted; the branch-islands must be
20667 appended to, and contiguous with, the function body. Mach-O stubs
20668 are generated in machopic_output_stub(). */
20671 macho_branch_islands (void)
20674 tree branch_island
;
20676 for (branch_island
= branch_island_list
;
20678 branch_island
= TREE_CHAIN (branch_island
))
20680 const char *label
=
20681 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island
));
20683 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island
));
20684 char name_buf
[512];
20685 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
20686 if (name
[0] == '*' || name
[0] == '&')
20687 strcpy (name_buf
, name
+1);
20691 strcpy (name_buf
+1, name
);
20693 strcpy (tmp_buf
, "\n");
20694 strcat (tmp_buf
, label
);
20695 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
20696 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
20697 dbxout_stabd (N_SLINE
, BRANCH_ISLAND_LINE_NUMBER (branch_island
));
20698 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
20701 strcat (tmp_buf
, ":\n\tmflr r0\n\tbcl 20,31,");
20702 strcat (tmp_buf
, label
);
20703 strcat (tmp_buf
, "_pic\n");
20704 strcat (tmp_buf
, label
);
20705 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
20707 strcat (tmp_buf
, "\taddis r11,r11,ha16(");
20708 strcat (tmp_buf
, name_buf
);
20709 strcat (tmp_buf
, " - ");
20710 strcat (tmp_buf
, label
);
20711 strcat (tmp_buf
, "_pic)\n");
20713 strcat (tmp_buf
, "\tmtlr r0\n");
20715 strcat (tmp_buf
, "\taddi r12,r11,lo16(");
20716 strcat (tmp_buf
, name_buf
);
20717 strcat (tmp_buf
, " - ");
20718 strcat (tmp_buf
, label
);
20719 strcat (tmp_buf
, "_pic)\n");
20721 strcat (tmp_buf
, "\tmtctr r12\n\tbctr\n");
20725 strcat (tmp_buf
, ":\nlis r12,hi16(");
20726 strcat (tmp_buf
, name_buf
);
20727 strcat (tmp_buf
, ")\n\tori r12,r12,lo16(");
20728 strcat (tmp_buf
, name_buf
);
20729 strcat (tmp_buf
, ")\n\tmtctr r12\n\tbctr");
20731 output_asm_insn (tmp_buf
, 0);
20732 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
20733 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
20734 dbxout_stabd (N_SLINE
, BRANCH_ISLAND_LINE_NUMBER (branch_island
));
20735 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
20738 branch_island_list
= 0;
20741 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
20742 already there or not. */
20745 no_previous_def (tree function_name
)
20747 tree branch_island
;
20748 for (branch_island
= branch_island_list
;
20750 branch_island
= TREE_CHAIN (branch_island
))
20751 if (function_name
== BRANCH_ISLAND_FUNCTION_NAME (branch_island
))
20756 /* GET_PREV_LABEL gets the label name from the previous definition of
20760 get_prev_label (tree function_name
)
20762 tree branch_island
;
20763 for (branch_island
= branch_island_list
;
20765 branch_island
= TREE_CHAIN (branch_island
))
20766 if (function_name
== BRANCH_ISLAND_FUNCTION_NAME (branch_island
))
20767 return BRANCH_ISLAND_LABEL_NAME (branch_island
);
20771 #ifndef DARWIN_LINKER_GENERATES_ISLANDS
20772 #define DARWIN_LINKER_GENERATES_ISLANDS 0
20775 /* KEXTs still need branch islands. */
20776 #define DARWIN_GENERATE_ISLANDS (!DARWIN_LINKER_GENERATES_ISLANDS \
20777 || flag_mkernel || flag_apple_kext)
20779 /* INSN is either a function call or a millicode call. It may have an
20780 unconditional jump in its delay slot.
20782 CALL_DEST is the routine we are calling. */
20785 output_call (rtx insn
, rtx
*operands
, int dest_operand_number
,
20786 int cookie_operand_number
)
20788 static char buf
[256];
20789 if (DARWIN_GENERATE_ISLANDS
20790 && GET_CODE (operands
[dest_operand_number
]) == SYMBOL_REF
20791 && (INTVAL (operands
[cookie_operand_number
]) & CALL_LONG
))
20794 tree funname
= get_identifier (XSTR (operands
[dest_operand_number
], 0));
20796 if (no_previous_def (funname
))
20798 rtx label_rtx
= gen_label_rtx ();
20799 char *label_buf
, temp_buf
[256];
20800 ASM_GENERATE_INTERNAL_LABEL (temp_buf
, "L",
20801 CODE_LABEL_NUMBER (label_rtx
));
20802 label_buf
= temp_buf
[0] == '*' ? temp_buf
+ 1 : temp_buf
;
20803 labelname
= get_identifier (label_buf
);
20804 add_compiler_branch_island (labelname
, funname
, insn_line (insn
));
20807 labelname
= get_prev_label (funname
);
20809 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
20810 instruction will reach 'foo', otherwise link as 'bl L42'".
20811 "L42" should be a 'branch island', that will do a far jump to
20812 'foo'. Branch islands are generated in
20813 macho_branch_islands(). */
20814 sprintf (buf
, "jbsr %%z%d,%.246s",
20815 dest_operand_number
, IDENTIFIER_POINTER (labelname
));
20818 sprintf (buf
, "bl %%z%d", dest_operand_number
);
20822 /* Generate PIC and indirect symbol stubs. */
20825 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
20827 unsigned int length
;
20828 char *symbol_name
, *lazy_ptr_name
;
20829 char *local_label_0
;
20830 static int label
= 0;
20832 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
20833 symb
= (*targetm
.strip_name_encoding
) (symb
);
20836 length
= strlen (symb
);
20837 symbol_name
= XALLOCAVEC (char, length
+ 32);
20838 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
20840 lazy_ptr_name
= XALLOCAVEC (char, length
+ 32);
20841 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name
, symb
, length
);
20844 switch_to_section (darwin_sections
[machopic_picsymbol_stub1_section
]);
20846 switch_to_section (darwin_sections
[machopic_symbol_stub1_section
]);
20850 fprintf (file
, "\t.align 5\n");
20852 fprintf (file
, "%s:\n", stub
);
20853 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
20856 local_label_0
= XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
20857 sprintf (local_label_0
, "\"L%011d$spb\"", label
);
20859 fprintf (file
, "\tmflr r0\n");
20860 fprintf (file
, "\tbcl 20,31,%s\n", local_label_0
);
20861 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
20862 fprintf (file
, "\taddis r11,r11,ha16(%s-%s)\n",
20863 lazy_ptr_name
, local_label_0
);
20864 fprintf (file
, "\tmtlr r0\n");
20865 fprintf (file
, "\t%s r12,lo16(%s-%s)(r11)\n",
20866 (TARGET_64BIT
? "ldu" : "lwzu"),
20867 lazy_ptr_name
, local_label_0
);
20868 fprintf (file
, "\tmtctr r12\n");
20869 fprintf (file
, "\tbctr\n");
20873 fprintf (file
, "\t.align 4\n");
20875 fprintf (file
, "%s:\n", stub
);
20876 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
20878 fprintf (file
, "\tlis r11,ha16(%s)\n", lazy_ptr_name
);
20879 fprintf (file
, "\t%s r12,lo16(%s)(r11)\n",
20880 (TARGET_64BIT
? "ldu" : "lwzu"),
20882 fprintf (file
, "\tmtctr r12\n");
20883 fprintf (file
, "\tbctr\n");
20886 switch_to_section (darwin_sections
[machopic_lazy_symbol_ptr_section
]);
20887 fprintf (file
, "%s:\n", lazy_ptr_name
);
20888 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
20889 fprintf (file
, "%sdyld_stub_binding_helper\n",
20890 (TARGET_64BIT
? DOUBLE_INT_ASM_OP
: "\t.long\t"));
20893 /* Legitimize PIC addresses. If the address is already
20894 position-independent, we return ORIG. Newly generated
20895 position-independent addresses go into a reg. This is REG if non
20896 zero, otherwise we allocate register(s) as necessary. */
20898 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
20901 rs6000_machopic_legitimize_pic_address (rtx orig
, enum machine_mode mode
,
20906 if (reg
== NULL
&& ! reload_in_progress
&& ! reload_completed
)
20907 reg
= gen_reg_rtx (Pmode
);
20909 if (GET_CODE (orig
) == CONST
)
20913 if (GET_CODE (XEXP (orig
, 0)) == PLUS
20914 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
20917 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
20919 /* Use a different reg for the intermediate value, as
20920 it will be marked UNCHANGING. */
20921 reg_temp
= !can_create_pseudo_p () ? reg
: gen_reg_rtx (Pmode
);
20922 base
= rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0),
20925 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
20928 if (GET_CODE (offset
) == CONST_INT
)
20930 if (SMALL_INT (offset
))
20931 return plus_constant (base
, INTVAL (offset
));
20932 else if (! reload_in_progress
&& ! reload_completed
)
20933 offset
= force_reg (Pmode
, offset
);
20936 rtx mem
= force_const_mem (Pmode
, orig
);
20937 return machopic_legitimize_pic_address (mem
, Pmode
, reg
);
20940 return gen_rtx_PLUS (Pmode
, base
, offset
);
20943 /* Fall back on generic machopic code. */
20944 return machopic_legitimize_pic_address (orig
, mode
, reg
);
20947 /* Output a .machine directive for the Darwin assembler, and call
20948 the generic start_file routine. */
20951 rs6000_darwin_file_start (void)
20953 static const struct
20959 { "ppc64", "ppc64", MASK_64BIT
},
20960 { "970", "ppc970", MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
20961 { "power4", "ppc970", 0 },
20962 { "G5", "ppc970", 0 },
20963 { "7450", "ppc7450", 0 },
20964 { "7400", "ppc7400", MASK_ALTIVEC
},
20965 { "G4", "ppc7400", 0 },
20966 { "750", "ppc750", 0 },
20967 { "740", "ppc750", 0 },
20968 { "G3", "ppc750", 0 },
20969 { "604e", "ppc604e", 0 },
20970 { "604", "ppc604", 0 },
20971 { "603e", "ppc603", 0 },
20972 { "603", "ppc603", 0 },
20973 { "601", "ppc601", 0 },
20974 { NULL
, "ppc", 0 } };
20975 const char *cpu_id
= "";
20978 rs6000_file_start ();
20979 darwin_file_start ();
20981 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
20982 for (i
= 0; i
< ARRAY_SIZE (rs6000_select
); i
++)
20983 if (rs6000_select
[i
].set_arch_p
&& rs6000_select
[i
].string
20984 && rs6000_select
[i
].string
[0] != '\0')
20985 cpu_id
= rs6000_select
[i
].string
;
20987 /* Look through the mapping array. Pick the first name that either
20988 matches the argument, has a bit set in IF_SET that is also set
20989 in the target flags, or has a NULL name. */
20992 while (mapping
[i
].arg
!= NULL
20993 && strcmp (mapping
[i
].arg
, cpu_id
) != 0
20994 && (mapping
[i
].if_set
& target_flags
) == 0)
20997 fprintf (asm_out_file
, "\t.machine %s\n", mapping
[i
].name
);
21000 #endif /* TARGET_MACHO */
21004 rs6000_elf_reloc_rw_mask (void)
21008 else if (DEFAULT_ABI
== ABI_AIX
)
21014 /* Record an element in the table of global constructors. SYMBOL is
21015 a SYMBOL_REF of the function to be called; PRIORITY is a number
21016 between 0 and MAX_INIT_PRIORITY.
21018 This differs from default_named_section_asm_out_constructor in
21019 that we have special handling for -mrelocatable. */
21022 rs6000_elf_asm_out_constructor (rtx symbol
, int priority
)
21024 const char *section
= ".ctors";
21027 if (priority
!= DEFAULT_INIT_PRIORITY
)
21029 sprintf (buf
, ".ctors.%.5u",
21030 /* Invert the numbering so the linker puts us in the proper
21031 order; constructors are run from right to left, and the
21032 linker sorts in increasing order. */
21033 MAX_INIT_PRIORITY
- priority
);
21037 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
21038 assemble_align (POINTER_SIZE
);
21040 if (TARGET_RELOCATABLE
)
21042 fputs ("\t.long (", asm_out_file
);
21043 output_addr_const (asm_out_file
, symbol
);
21044 fputs (")@fixup\n", asm_out_file
);
21047 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
21051 rs6000_elf_asm_out_destructor (rtx symbol
, int priority
)
21053 const char *section
= ".dtors";
21056 if (priority
!= DEFAULT_INIT_PRIORITY
)
21058 sprintf (buf
, ".dtors.%.5u",
21059 /* Invert the numbering so the linker puts us in the proper
21060 order; constructors are run from right to left, and the
21061 linker sorts in increasing order. */
21062 MAX_INIT_PRIORITY
- priority
);
21066 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
21067 assemble_align (POINTER_SIZE
);
21069 if (TARGET_RELOCATABLE
)
21071 fputs ("\t.long (", asm_out_file
);
21072 output_addr_const (asm_out_file
, symbol
);
21073 fputs (")@fixup\n", asm_out_file
);
21076 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
21080 rs6000_elf_declare_function_name (FILE *file
, const char *name
, tree decl
)
21084 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file
);
21085 ASM_OUTPUT_LABEL (file
, name
);
21086 fputs (DOUBLE_INT_ASM_OP
, file
);
21087 rs6000_output_function_entry (file
, name
);
21088 fputs (",.TOC.@tocbase,0\n\t.previous\n", file
);
21091 fputs ("\t.size\t", file
);
21092 assemble_name (file
, name
);
21093 fputs (",24\n\t.type\t.", file
);
21094 assemble_name (file
, name
);
21095 fputs (",@function\n", file
);
21096 if (TREE_PUBLIC (decl
) && ! DECL_WEAK (decl
))
21098 fputs ("\t.globl\t.", file
);
21099 assemble_name (file
, name
);
21104 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
21105 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
21106 rs6000_output_function_entry (file
, name
);
21107 fputs (":\n", file
);
21111 if (TARGET_RELOCATABLE
21112 && !TARGET_SECURE_PLT
21113 && (get_pool_size () != 0 || crtl
->profile
)
21118 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
21120 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
21121 fprintf (file
, "\t.long ");
21122 assemble_name (file
, buf
);
21124 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
21125 assemble_name (file
, buf
);
21129 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
21130 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
21132 if (DEFAULT_ABI
== ABI_AIX
)
21134 const char *desc_name
, *orig_name
;
21136 orig_name
= (*targetm
.strip_name_encoding
) (name
);
21137 desc_name
= orig_name
;
21138 while (*desc_name
== '.')
21141 if (TREE_PUBLIC (decl
))
21142 fprintf (file
, "\t.globl %s\n", desc_name
);
21144 fprintf (file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
21145 fprintf (file
, "%s:\n", desc_name
);
21146 fprintf (file
, "\t.long %s\n", orig_name
);
21147 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file
);
21148 if (DEFAULT_ABI
== ABI_AIX
)
21149 fputs ("\t.long 0\n", file
);
21150 fprintf (file
, "\t.previous\n");
21152 ASM_OUTPUT_LABEL (file
, name
);
21156 rs6000_elf_end_indicate_exec_stack (void)
21159 file_end_indicate_exec_stack ();
21165 rs6000_xcoff_asm_output_anchor (rtx symbol
)
21169 sprintf (buffer
, "$ + " HOST_WIDE_INT_PRINT_DEC
,
21170 SYMBOL_REF_BLOCK_OFFSET (symbol
));
21171 ASM_OUTPUT_DEF (asm_out_file
, XSTR (symbol
, 0), buffer
);
21175 rs6000_xcoff_asm_globalize_label (FILE *stream
, const char *name
)
21177 fputs (GLOBAL_ASM_OP
, stream
);
21178 RS6000_OUTPUT_BASENAME (stream
, name
);
21179 putc ('\n', stream
);
21182 /* A get_unnamed_decl callback, used for read-only sections. PTR
21183 points to the section string variable. */
21186 rs6000_xcoff_output_readonly_section_asm_op (const void *directive
)
21188 fprintf (asm_out_file
, "\t.csect %s[RO],%s\n",
21189 *(const char *const *) directive
,
21190 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
21193 /* Likewise for read-write sections. */
21196 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive
)
21198 fprintf (asm_out_file
, "\t.csect %s[RW],%s\n",
21199 *(const char *const *) directive
,
21200 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
21203 /* A get_unnamed_section callback, used for switching to toc_section. */
21206 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
21208 if (TARGET_MINIMAL_TOC
)
21210 /* toc_section is always selected at least once from
21211 rs6000_xcoff_file_start, so this is guaranteed to
21212 always be defined once and only once in each file. */
21213 if (!toc_initialized
)
21215 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file
);
21216 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file
);
21217 toc_initialized
= 1;
21219 fprintf (asm_out_file
, "\t.csect toc_table[RW]%s\n",
21220 (TARGET_32BIT
? "" : ",3"));
21223 fputs ("\t.toc\n", asm_out_file
);
21226 /* Implement TARGET_ASM_INIT_SECTIONS. */
21229 rs6000_xcoff_asm_init_sections (void)
21231 read_only_data_section
21232 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
21233 &xcoff_read_only_section_name
);
21235 private_data_section
21236 = get_unnamed_section (SECTION_WRITE
,
21237 rs6000_xcoff_output_readwrite_section_asm_op
,
21238 &xcoff_private_data_section_name
);
21240 read_only_private_data_section
21241 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
21242 &xcoff_private_data_section_name
);
21245 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op
, NULL
);
21247 readonly_data_section
= read_only_data_section
;
21248 exception_section
= data_section
;
21252 rs6000_xcoff_reloc_rw_mask (void)
21258 rs6000_xcoff_asm_named_section (const char *name
, unsigned int flags
,
21259 tree decl ATTRIBUTE_UNUSED
)
21262 static const char * const suffix
[3] = { "PR", "RO", "RW" };
21264 if (flags
& SECTION_CODE
)
21266 else if (flags
& SECTION_WRITE
)
21271 fprintf (asm_out_file
, "\t.csect %s%s[%s],%u\n",
21272 (flags
& SECTION_CODE
) ? "." : "",
21273 name
, suffix
[smclass
], flags
& SECTION_ENTSIZE
);
21277 rs6000_xcoff_select_section (tree decl
, int reloc
,
21278 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
21280 if (decl_readonly_section (decl
, reloc
))
21282 if (TREE_PUBLIC (decl
))
21283 return read_only_data_section
;
21285 return read_only_private_data_section
;
21289 if (TREE_PUBLIC (decl
))
21290 return data_section
;
21292 return private_data_section
;
21297 rs6000_xcoff_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
21301 /* Use select_section for private and uninitialized data. */
21302 if (!TREE_PUBLIC (decl
)
21303 || DECL_COMMON (decl
)
21304 || DECL_INITIAL (decl
) == NULL_TREE
21305 || DECL_INITIAL (decl
) == error_mark_node
21306 || (flag_zero_initialized_in_bss
21307 && initializer_zerop (DECL_INITIAL (decl
))))
21310 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
21311 name
= (*targetm
.strip_name_encoding
) (name
);
21312 DECL_SECTION_NAME (decl
) = build_string (strlen (name
), name
);
21315 /* Select section for constant in constant pool.
21317 On RS/6000, all constants are in the private read-only data area.
21318 However, if this is being placed in the TOC it must be output as a
21322 rs6000_xcoff_select_rtx_section (enum machine_mode mode
, rtx x
,
21323 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
21325 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
21326 return toc_section
;
21328 return read_only_private_data_section
;
21331 /* Remove any trailing [DS] or the like from the symbol name. */
21333 static const char *
21334 rs6000_xcoff_strip_name_encoding (const char *name
)
21339 len
= strlen (name
);
21340 if (name
[len
- 1] == ']')
21341 return ggc_alloc_string (name
, len
- 4);
21346 /* Section attributes. AIX is always PIC. */
21348 static unsigned int
21349 rs6000_xcoff_section_type_flags (tree decl
, const char *name
, int reloc
)
21351 unsigned int align
;
21352 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
21354 /* Align to at least UNIT size. */
21355 if (flags
& SECTION_CODE
)
21356 align
= MIN_UNITS_PER_WORD
;
21358 /* Increase alignment of large objects if not already stricter. */
21359 align
= MAX ((DECL_ALIGN (decl
) / BITS_PER_UNIT
),
21360 int_size_in_bytes (TREE_TYPE (decl
)) > MIN_UNITS_PER_WORD
21361 ? UNITS_PER_FP_WORD
: MIN_UNITS_PER_WORD
);
21363 return flags
| (exact_log2 (align
) & SECTION_ENTSIZE
);
21366 /* Output at beginning of assembler file.
21368 Initialize the section names for the RS/6000 at this point.
21370 Specify filename, including full path, to assembler.
21372 We want to go into the TOC section so at least one .toc will be emitted.
21373 Also, in order to output proper .bs/.es pairs, we need at least one static
21374 [RW] section emitted.
21376 Finally, declare mcount when profiling to make the assembler happy. */
21379 rs6000_xcoff_file_start (void)
21381 rs6000_gen_section_name (&xcoff_bss_section_name
,
21382 main_input_filename
, ".bss_");
21383 rs6000_gen_section_name (&xcoff_private_data_section_name
,
21384 main_input_filename
, ".rw_");
21385 rs6000_gen_section_name (&xcoff_read_only_section_name
,
21386 main_input_filename
, ".ro_");
21388 fputs ("\t.file\t", asm_out_file
);
21389 output_quoted_string (asm_out_file
, main_input_filename
);
21390 fputc ('\n', asm_out_file
);
21391 if (write_symbols
!= NO_DEBUG
)
21392 switch_to_section (private_data_section
);
21393 switch_to_section (text_section
);
21395 fprintf (asm_out_file
, "\t.extern %s\n", RS6000_MCOUNT
);
21396 rs6000_file_start ();
21399 /* Output at end of assembler file.
21400 On the RS/6000, referencing data should automatically pull in text. */
21403 rs6000_xcoff_file_end (void)
21405 switch_to_section (text_section
);
21406 fputs ("_section_.text:\n", asm_out_file
);
21407 switch_to_section (data_section
);
21408 fputs (TARGET_32BIT
21409 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
21412 #endif /* TARGET_XCOFF */
21414 /* Compute a (partial) cost for rtx X. Return true if the complete
21415 cost has been computed, and false if subexpressions should be
21416 scanned. In either case, *TOTAL contains the cost result. */
21419 rs6000_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
21421 enum machine_mode mode
= GET_MODE (x
);
21425 /* On the RS/6000, if it is valid in the insn, it is free. */
21427 if (((outer_code
== SET
21428 || outer_code
== PLUS
21429 || outer_code
== MINUS
)
21430 && (satisfies_constraint_I (x
)
21431 || satisfies_constraint_L (x
)))
21432 || (outer_code
== AND
21433 && (satisfies_constraint_K (x
)
21435 ? satisfies_constraint_L (x
)
21436 : satisfies_constraint_J (x
))
21437 || mask_operand (x
, mode
)
21439 && mask64_operand (x
, DImode
))))
21440 || ((outer_code
== IOR
|| outer_code
== XOR
)
21441 && (satisfies_constraint_K (x
)
21443 ? satisfies_constraint_L (x
)
21444 : satisfies_constraint_J (x
))))
21445 || outer_code
== ASHIFT
21446 || outer_code
== ASHIFTRT
21447 || outer_code
== LSHIFTRT
21448 || outer_code
== ROTATE
21449 || outer_code
== ROTATERT
21450 || outer_code
== ZERO_EXTRACT
21451 || (outer_code
== MULT
21452 && satisfies_constraint_I (x
))
21453 || ((outer_code
== DIV
|| outer_code
== UDIV
21454 || outer_code
== MOD
|| outer_code
== UMOD
)
21455 && exact_log2 (INTVAL (x
)) >= 0)
21456 || (outer_code
== COMPARE
21457 && (satisfies_constraint_I (x
)
21458 || satisfies_constraint_K (x
)))
21459 || (outer_code
== EQ
21460 && (satisfies_constraint_I (x
)
21461 || satisfies_constraint_K (x
)
21463 ? satisfies_constraint_L (x
)
21464 : satisfies_constraint_J (x
))))
21465 || (outer_code
== GTU
21466 && satisfies_constraint_I (x
))
21467 || (outer_code
== LTU
21468 && satisfies_constraint_P (x
)))
21473 else if ((outer_code
== PLUS
21474 && reg_or_add_cint_operand (x
, VOIDmode
))
21475 || (outer_code
== MINUS
21476 && reg_or_sub_cint_operand (x
, VOIDmode
))
21477 || ((outer_code
== SET
21478 || outer_code
== IOR
21479 || outer_code
== XOR
)
21481 & ~ (unsigned HOST_WIDE_INT
) 0xffffffff) == 0))
21483 *total
= COSTS_N_INSNS (1);
21489 if (mode
== DImode
&& code
== CONST_DOUBLE
)
21491 if ((outer_code
== IOR
|| outer_code
== XOR
)
21492 && CONST_DOUBLE_HIGH (x
) == 0
21493 && (CONST_DOUBLE_LOW (x
)
21494 & ~ (unsigned HOST_WIDE_INT
) 0xffff) == 0)
21499 else if ((outer_code
== AND
&& and64_2_operand (x
, DImode
))
21500 || ((outer_code
== SET
21501 || outer_code
== IOR
21502 || outer_code
== XOR
)
21503 && CONST_DOUBLE_HIGH (x
) == 0))
21505 *total
= COSTS_N_INSNS (1);
21515 /* When optimizing for size, MEM should be slightly more expensive
21516 than generating address, e.g., (plus (reg) (const)).
21517 L1 cache latency is about two instructions. */
21518 *total
= optimize_size
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
21526 if (mode
== DFmode
)
21528 if (GET_CODE (XEXP (x
, 0)) == MULT
)
21530 /* FNMA accounted in outer NEG. */
21531 if (outer_code
== NEG
)
21532 *total
= rs6000_cost
->dmul
- rs6000_cost
->fp
;
21534 *total
= rs6000_cost
->dmul
;
21537 *total
= rs6000_cost
->fp
;
21539 else if (mode
== SFmode
)
21541 /* FNMA accounted in outer NEG. */
21542 if (outer_code
== NEG
&& GET_CODE (XEXP (x
, 0)) == MULT
)
21545 *total
= rs6000_cost
->fp
;
21548 *total
= COSTS_N_INSNS (1);
21552 if (mode
== DFmode
)
21554 if (GET_CODE (XEXP (x
, 0)) == MULT
21555 || GET_CODE (XEXP (x
, 1)) == MULT
)
21557 /* FNMA accounted in outer NEG. */
21558 if (outer_code
== NEG
)
21559 *total
= rs6000_cost
->dmul
- rs6000_cost
->fp
;
21561 *total
= rs6000_cost
->dmul
;
21564 *total
= rs6000_cost
->fp
;
21566 else if (mode
== SFmode
)
21568 /* FNMA accounted in outer NEG. */
21569 if (outer_code
== NEG
&& GET_CODE (XEXP (x
, 0)) == MULT
)
21572 *total
= rs6000_cost
->fp
;
21575 *total
= COSTS_N_INSNS (1);
21579 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
21580 && satisfies_constraint_I (XEXP (x
, 1)))
21582 if (INTVAL (XEXP (x
, 1)) >= -256
21583 && INTVAL (XEXP (x
, 1)) <= 255)
21584 *total
= rs6000_cost
->mulsi_const9
;
21586 *total
= rs6000_cost
->mulsi_const
;
21588 /* FMA accounted in outer PLUS/MINUS. */
21589 else if ((mode
== DFmode
|| mode
== SFmode
)
21590 && (outer_code
== PLUS
|| outer_code
== MINUS
))
21592 else if (mode
== DFmode
)
21593 *total
= rs6000_cost
->dmul
;
21594 else if (mode
== SFmode
)
21595 *total
= rs6000_cost
->fp
;
21596 else if (mode
== DImode
)
21597 *total
= rs6000_cost
->muldi
;
21599 *total
= rs6000_cost
->mulsi
;
21604 if (FLOAT_MODE_P (mode
))
21606 *total
= mode
== DFmode
? rs6000_cost
->ddiv
21607 : rs6000_cost
->sdiv
;
21614 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
21615 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
21617 if (code
== DIV
|| code
== MOD
)
21619 *total
= COSTS_N_INSNS (2);
21622 *total
= COSTS_N_INSNS (1);
21626 if (GET_MODE (XEXP (x
, 1)) == DImode
)
21627 *total
= rs6000_cost
->divdi
;
21629 *total
= rs6000_cost
->divsi
;
21631 /* Add in shift and subtract for MOD. */
21632 if (code
== MOD
|| code
== UMOD
)
21633 *total
+= COSTS_N_INSNS (2);
21638 *total
= COSTS_N_INSNS (4);
21642 *total
= COSTS_N_INSNS (6);
21646 if (outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
21658 *total
= COSTS_N_INSNS (1);
21666 /* Handle mul_highpart. */
21667 if (outer_code
== TRUNCATE
21668 && GET_CODE (XEXP (x
, 0)) == MULT
)
21670 if (mode
== DImode
)
21671 *total
= rs6000_cost
->muldi
;
21673 *total
= rs6000_cost
->mulsi
;
21676 else if (outer_code
== AND
)
21679 *total
= COSTS_N_INSNS (1);
21684 if (GET_CODE (XEXP (x
, 0)) == MEM
)
21687 *total
= COSTS_N_INSNS (1);
21693 if (!FLOAT_MODE_P (mode
))
21695 *total
= COSTS_N_INSNS (1);
21701 case UNSIGNED_FLOAT
:
21704 case FLOAT_TRUNCATE
:
21705 *total
= rs6000_cost
->fp
;
21709 if (mode
== DFmode
)
21712 *total
= rs6000_cost
->fp
;
21716 switch (XINT (x
, 1))
21719 *total
= rs6000_cost
->fp
;
21731 *total
= COSTS_N_INSNS (1);
21734 else if (FLOAT_MODE_P (mode
)
21735 && TARGET_PPC_GFXOPT
&& TARGET_HARD_FLOAT
&& TARGET_FPRS
)
21737 *total
= rs6000_cost
->fp
;
21745 /* Carry bit requires mode == Pmode.
21746 NEG or PLUS already counted so only add one. */
21748 && (outer_code
== NEG
|| outer_code
== PLUS
))
21750 *total
= COSTS_N_INSNS (1);
21753 if (outer_code
== SET
)
21755 if (XEXP (x
, 1) == const0_rtx
)
21757 *total
= COSTS_N_INSNS (2);
21760 else if (mode
== Pmode
)
21762 *total
= COSTS_N_INSNS (3);
21771 if (outer_code
== SET
&& (XEXP (x
, 1) == const0_rtx
))
21773 *total
= COSTS_N_INSNS (2);
21777 if (outer_code
== COMPARE
)
21791 /* A C expression returning the cost of moving data from a register of class
21792 CLASS1 to one of CLASS2. */
21795 rs6000_register_move_cost (enum machine_mode mode
,
21796 enum reg_class from
, enum reg_class to
)
21798 /* Moves from/to GENERAL_REGS. */
21799 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
21800 || reg_classes_intersect_p (from
, GENERAL_REGS
))
21802 if (! reg_classes_intersect_p (to
, GENERAL_REGS
))
21805 if (from
== FLOAT_REGS
|| from
== ALTIVEC_REGS
)
21806 return (rs6000_memory_move_cost (mode
, from
, 0)
21807 + rs6000_memory_move_cost (mode
, GENERAL_REGS
, 0));
21809 /* It's more expensive to move CR_REGS than CR0_REGS because of the
21811 else if (from
== CR_REGS
)
21814 /* Power6 has slower LR/CTR moves so make them more expensive than
21815 memory in order to bias spills to memory .*/
21816 else if (rs6000_cpu
== PROCESSOR_POWER6
21817 && reg_classes_intersect_p (from
, LINK_OR_CTR_REGS
))
21818 return 6 * hard_regno_nregs
[0][mode
];
21821 /* A move will cost one instruction per GPR moved. */
21822 return 2 * hard_regno_nregs
[0][mode
];
21825 /* Moving between two similar registers is just one instruction. */
21826 else if (reg_classes_intersect_p (to
, from
))
21827 return (mode
== TFmode
|| mode
== TDmode
) ? 4 : 2;
21829 /* Everything else has to go through GENERAL_REGS. */
21831 return (rs6000_register_move_cost (mode
, GENERAL_REGS
, to
)
21832 + rs6000_register_move_cost (mode
, from
, GENERAL_REGS
));
21835 /* A C expressions returning the cost of moving data of MODE from a register to
21839 rs6000_memory_move_cost (enum machine_mode mode
, enum reg_class rclass
,
21840 int in ATTRIBUTE_UNUSED
)
21842 if (reg_classes_intersect_p (rclass
, GENERAL_REGS
))
21843 return 4 * hard_regno_nregs
[0][mode
];
21844 else if (reg_classes_intersect_p (rclass
, FLOAT_REGS
))
21845 return 4 * hard_regno_nregs
[32][mode
];
21846 else if (reg_classes_intersect_p (rclass
, ALTIVEC_REGS
))
21847 return 4 * hard_regno_nregs
[FIRST_ALTIVEC_REGNO
][mode
];
21849 return 4 + rs6000_register_move_cost (mode
, rclass
, GENERAL_REGS
);
21852 /* Returns a code for a target-specific builtin that implements
21853 reciprocal of the function, or NULL_TREE if not available. */
21856 rs6000_builtin_reciprocal (unsigned int fn
, bool md_fn
,
21857 bool sqrt ATTRIBUTE_UNUSED
)
21859 if (! (TARGET_RECIP
&& TARGET_PPC_GFXOPT
&& !optimize_size
21860 && flag_finite_math_only
&& !flag_trapping_math
21861 && flag_unsafe_math_optimizations
))
21869 case BUILT_IN_SQRTF
:
21870 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRTF
];
21877 /* Newton-Raphson approximation of single-precision floating point divide n/d.
21878 Assumes no trapping math and finite arguments. */
21881 rs6000_emit_swdivsf (rtx dst
, rtx n
, rtx d
)
21883 rtx x0
, e0
, e1
, y1
, u0
, v0
, one
;
21885 x0
= gen_reg_rtx (SFmode
);
21886 e0
= gen_reg_rtx (SFmode
);
21887 e1
= gen_reg_rtx (SFmode
);
21888 y1
= gen_reg_rtx (SFmode
);
21889 u0
= gen_reg_rtx (SFmode
);
21890 v0
= gen_reg_rtx (SFmode
);
21891 one
= force_reg (SFmode
, CONST_DOUBLE_FROM_REAL_VALUE (dconst1
, SFmode
));
21893 /* x0 = 1./d estimate */
21894 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
21895 gen_rtx_UNSPEC (SFmode
, gen_rtvec (1, d
),
21897 /* e0 = 1. - d * x0 */
21898 emit_insn (gen_rtx_SET (VOIDmode
, e0
,
21899 gen_rtx_MINUS (SFmode
, one
,
21900 gen_rtx_MULT (SFmode
, d
, x0
))));
21901 /* e1 = e0 + e0 * e0 */
21902 emit_insn (gen_rtx_SET (VOIDmode
, e1
,
21903 gen_rtx_PLUS (SFmode
,
21904 gen_rtx_MULT (SFmode
, e0
, e0
), e0
)));
21905 /* y1 = x0 + e1 * x0 */
21906 emit_insn (gen_rtx_SET (VOIDmode
, y1
,
21907 gen_rtx_PLUS (SFmode
,
21908 gen_rtx_MULT (SFmode
, e1
, x0
), x0
)));
21910 emit_insn (gen_rtx_SET (VOIDmode
, u0
,
21911 gen_rtx_MULT (SFmode
, n
, y1
)));
21912 /* v0 = n - d * u0 */
21913 emit_insn (gen_rtx_SET (VOIDmode
, v0
,
21914 gen_rtx_MINUS (SFmode
, n
,
21915 gen_rtx_MULT (SFmode
, d
, u0
))));
21916 /* dst = u0 + v0 * y1 */
21917 emit_insn (gen_rtx_SET (VOIDmode
, dst
,
21918 gen_rtx_PLUS (SFmode
,
21919 gen_rtx_MULT (SFmode
, v0
, y1
), u0
)));
21922 /* Newton-Raphson approximation of double-precision floating point divide n/d.
21923 Assumes no trapping math and finite arguments. */
21926 rs6000_emit_swdivdf (rtx dst
, rtx n
, rtx d
)
21928 rtx x0
, e0
, e1
, e2
, y1
, y2
, y3
, u0
, v0
, one
;
21930 x0
= gen_reg_rtx (DFmode
);
21931 e0
= gen_reg_rtx (DFmode
);
21932 e1
= gen_reg_rtx (DFmode
);
21933 e2
= gen_reg_rtx (DFmode
);
21934 y1
= gen_reg_rtx (DFmode
);
21935 y2
= gen_reg_rtx (DFmode
);
21936 y3
= gen_reg_rtx (DFmode
);
21937 u0
= gen_reg_rtx (DFmode
);
21938 v0
= gen_reg_rtx (DFmode
);
21939 one
= force_reg (DFmode
, CONST_DOUBLE_FROM_REAL_VALUE (dconst1
, DFmode
));
21941 /* x0 = 1./d estimate */
21942 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
21943 gen_rtx_UNSPEC (DFmode
, gen_rtvec (1, d
),
21945 /* e0 = 1. - d * x0 */
21946 emit_insn (gen_rtx_SET (VOIDmode
, e0
,
21947 gen_rtx_MINUS (DFmode
, one
,
21948 gen_rtx_MULT (SFmode
, d
, x0
))));
21949 /* y1 = x0 + e0 * x0 */
21950 emit_insn (gen_rtx_SET (VOIDmode
, y1
,
21951 gen_rtx_PLUS (DFmode
,
21952 gen_rtx_MULT (DFmode
, e0
, x0
), x0
)));
21954 emit_insn (gen_rtx_SET (VOIDmode
, e1
,
21955 gen_rtx_MULT (DFmode
, e0
, e0
)));
21956 /* y2 = y1 + e1 * y1 */
21957 emit_insn (gen_rtx_SET (VOIDmode
, y2
,
21958 gen_rtx_PLUS (DFmode
,
21959 gen_rtx_MULT (DFmode
, e1
, y1
), y1
)));
21961 emit_insn (gen_rtx_SET (VOIDmode
, e2
,
21962 gen_rtx_MULT (DFmode
, e1
, e1
)));
21963 /* y3 = y2 + e2 * y2 */
21964 emit_insn (gen_rtx_SET (VOIDmode
, y3
,
21965 gen_rtx_PLUS (DFmode
,
21966 gen_rtx_MULT (DFmode
, e2
, y2
), y2
)));
21968 emit_insn (gen_rtx_SET (VOIDmode
, u0
,
21969 gen_rtx_MULT (DFmode
, n
, y3
)));
21970 /* v0 = n - d * u0 */
21971 emit_insn (gen_rtx_SET (VOIDmode
, v0
,
21972 gen_rtx_MINUS (DFmode
, n
,
21973 gen_rtx_MULT (DFmode
, d
, u0
))));
21974 /* dst = u0 + v0 * y3 */
21975 emit_insn (gen_rtx_SET (VOIDmode
, dst
,
21976 gen_rtx_PLUS (DFmode
,
21977 gen_rtx_MULT (DFmode
, v0
, y3
), u0
)));
21981 /* Newton-Raphson approximation of single-precision floating point rsqrt.
21982 Assumes no trapping math and finite arguments. */
21985 rs6000_emit_swrsqrtsf (rtx dst
, rtx src
)
21987 rtx x0
, x1
, x2
, y1
, u0
, u1
, u2
, v0
, v1
, v2
, t0
,
21988 half
, one
, halfthree
, c1
, cond
, label
;
21990 x0
= gen_reg_rtx (SFmode
);
21991 x1
= gen_reg_rtx (SFmode
);
21992 x2
= gen_reg_rtx (SFmode
);
21993 y1
= gen_reg_rtx (SFmode
);
21994 u0
= gen_reg_rtx (SFmode
);
21995 u1
= gen_reg_rtx (SFmode
);
21996 u2
= gen_reg_rtx (SFmode
);
21997 v0
= gen_reg_rtx (SFmode
);
21998 v1
= gen_reg_rtx (SFmode
);
21999 v2
= gen_reg_rtx (SFmode
);
22000 t0
= gen_reg_rtx (SFmode
);
22001 halfthree
= gen_reg_rtx (SFmode
);
22002 cond
= gen_rtx_REG (CCFPmode
, CR1_REGNO
);
22003 label
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
22005 /* check 0.0, 1.0, NaN, Inf by testing src * src = src */
22006 emit_insn (gen_rtx_SET (VOIDmode
, t0
,
22007 gen_rtx_MULT (SFmode
, src
, src
)));
22009 emit_insn (gen_rtx_SET (VOIDmode
, cond
,
22010 gen_rtx_COMPARE (CCFPmode
, t0
, src
)));
22011 c1
= gen_rtx_EQ (VOIDmode
, cond
, const0_rtx
);
22012 emit_unlikely_jump (c1
, label
);
22014 half
= force_reg (SFmode
, CONST_DOUBLE_FROM_REAL_VALUE (dconsthalf
, SFmode
));
22015 one
= force_reg (SFmode
, CONST_DOUBLE_FROM_REAL_VALUE (dconst1
, SFmode
));
22017 /* halfthree = 1.5 = 1.0 + 0.5 */
22018 emit_insn (gen_rtx_SET (VOIDmode
, halfthree
,
22019 gen_rtx_PLUS (SFmode
, one
, half
)));
22021 /* x0 = rsqrt estimate */
22022 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
22023 gen_rtx_UNSPEC (SFmode
, gen_rtvec (1, src
),
22026 /* y1 = 0.5 * src = 1.5 * src - src -> fewer constants */
22027 emit_insn (gen_rtx_SET (VOIDmode
, y1
,
22028 gen_rtx_MINUS (SFmode
,
22029 gen_rtx_MULT (SFmode
, src
, halfthree
),
22032 /* x1 = x0 * (1.5 - y1 * (x0 * x0)) */
22033 emit_insn (gen_rtx_SET (VOIDmode
, u0
,
22034 gen_rtx_MULT (SFmode
, x0
, x0
)));
22035 emit_insn (gen_rtx_SET (VOIDmode
, v0
,
22036 gen_rtx_MINUS (SFmode
,
22038 gen_rtx_MULT (SFmode
, y1
, u0
))));
22039 emit_insn (gen_rtx_SET (VOIDmode
, x1
,
22040 gen_rtx_MULT (SFmode
, x0
, v0
)));
22042 /* x2 = x1 * (1.5 - y1 * (x1 * x1)) */
22043 emit_insn (gen_rtx_SET (VOIDmode
, u1
,
22044 gen_rtx_MULT (SFmode
, x1
, x1
)));
22045 emit_insn (gen_rtx_SET (VOIDmode
, v1
,
22046 gen_rtx_MINUS (SFmode
,
22048 gen_rtx_MULT (SFmode
, y1
, u1
))));
22049 emit_insn (gen_rtx_SET (VOIDmode
, x2
,
22050 gen_rtx_MULT (SFmode
, x1
, v1
)));
22052 /* dst = x2 * (1.5 - y1 * (x2 * x2)) */
22053 emit_insn (gen_rtx_SET (VOIDmode
, u2
,
22054 gen_rtx_MULT (SFmode
, x2
, x2
)));
22055 emit_insn (gen_rtx_SET (VOIDmode
, v2
,
22056 gen_rtx_MINUS (SFmode
,
22058 gen_rtx_MULT (SFmode
, y1
, u2
))));
22059 emit_insn (gen_rtx_SET (VOIDmode
, dst
,
22060 gen_rtx_MULT (SFmode
, x2
, v2
)));
22062 emit_label (XEXP (label
, 0));
22065 /* Emit popcount intrinsic on TARGET_POPCNTB targets. DST is the
22066 target, and SRC is the argument operand. */
22069 rs6000_emit_popcount (rtx dst
, rtx src
)
22071 enum machine_mode mode
= GET_MODE (dst
);
22074 tmp1
= gen_reg_rtx (mode
);
22076 if (mode
== SImode
)
22078 emit_insn (gen_popcntbsi2 (tmp1
, src
));
22079 tmp2
= expand_mult (SImode
, tmp1
, GEN_INT (0x01010101),
22081 tmp2
= force_reg (SImode
, tmp2
);
22082 emit_insn (gen_lshrsi3 (dst
, tmp2
, GEN_INT (24)));
22086 emit_insn (gen_popcntbdi2 (tmp1
, src
));
22087 tmp2
= expand_mult (DImode
, tmp1
,
22088 GEN_INT ((HOST_WIDE_INT
)
22089 0x01010101 << 32 | 0x01010101),
22091 tmp2
= force_reg (DImode
, tmp2
);
22092 emit_insn (gen_lshrdi3 (dst
, tmp2
, GEN_INT (56)));
22097 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
22098 target, and SRC is the argument operand. */
22101 rs6000_emit_parity (rtx dst
, rtx src
)
22103 enum machine_mode mode
= GET_MODE (dst
);
22106 tmp
= gen_reg_rtx (mode
);
22107 if (mode
== SImode
)
22109 /* Is mult+shift >= shift+xor+shift+xor? */
22110 if (rs6000_cost
->mulsi_const
>= COSTS_N_INSNS (3))
22112 rtx tmp1
, tmp2
, tmp3
, tmp4
;
22114 tmp1
= gen_reg_rtx (SImode
);
22115 emit_insn (gen_popcntbsi2 (tmp1
, src
));
22117 tmp2
= gen_reg_rtx (SImode
);
22118 emit_insn (gen_lshrsi3 (tmp2
, tmp1
, GEN_INT (16)));
22119 tmp3
= gen_reg_rtx (SImode
);
22120 emit_insn (gen_xorsi3 (tmp3
, tmp1
, tmp2
));
22122 tmp4
= gen_reg_rtx (SImode
);
22123 emit_insn (gen_lshrsi3 (tmp4
, tmp3
, GEN_INT (8)));
22124 emit_insn (gen_xorsi3 (tmp
, tmp3
, tmp4
));
22127 rs6000_emit_popcount (tmp
, src
);
22128 emit_insn (gen_andsi3 (dst
, tmp
, const1_rtx
));
22132 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
22133 if (rs6000_cost
->muldi
>= COSTS_N_INSNS (5))
22135 rtx tmp1
, tmp2
, tmp3
, tmp4
, tmp5
, tmp6
;
22137 tmp1
= gen_reg_rtx (DImode
);
22138 emit_insn (gen_popcntbdi2 (tmp1
, src
));
22140 tmp2
= gen_reg_rtx (DImode
);
22141 emit_insn (gen_lshrdi3 (tmp2
, tmp1
, GEN_INT (32)));
22142 tmp3
= gen_reg_rtx (DImode
);
22143 emit_insn (gen_xordi3 (tmp3
, tmp1
, tmp2
));
22145 tmp4
= gen_reg_rtx (DImode
);
22146 emit_insn (gen_lshrdi3 (tmp4
, tmp3
, GEN_INT (16)));
22147 tmp5
= gen_reg_rtx (DImode
);
22148 emit_insn (gen_xordi3 (tmp5
, tmp3
, tmp4
));
22150 tmp6
= gen_reg_rtx (DImode
);
22151 emit_insn (gen_lshrdi3 (tmp6
, tmp5
, GEN_INT (8)));
22152 emit_insn (gen_xordi3 (tmp
, tmp5
, tmp6
));
22155 rs6000_emit_popcount (tmp
, src
);
22156 emit_insn (gen_anddi3 (dst
, tmp
, const1_rtx
));
22160 /* Return an RTX representing where to find the function value of a
22161 function returning MODE. */
22163 rs6000_complex_function_value (enum machine_mode mode
)
22165 unsigned int regno
;
22167 enum machine_mode inner
= GET_MODE_INNER (mode
);
22168 unsigned int inner_bytes
= GET_MODE_SIZE (inner
);
22170 if (FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
22171 regno
= FP_ARG_RETURN
;
22174 regno
= GP_ARG_RETURN
;
22176 /* 32-bit is OK since it'll go in r3/r4. */
22177 if (TARGET_32BIT
&& inner_bytes
>= 4)
22178 return gen_rtx_REG (mode
, regno
);
22181 if (inner_bytes
>= 8)
22182 return gen_rtx_REG (mode
, regno
);
22184 r1
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
),
22186 r2
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
+ 1),
22187 GEN_INT (inner_bytes
));
22188 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
22191 /* Define how to find the value returned by a function.
22192 VALTYPE is the data type of the value (as a tree).
22193 If the precise function being called is known, FUNC is its FUNCTION_DECL;
22194 otherwise, FUNC is 0.
22196 On the SPE, both FPs and vectors are returned in r3.
22198 On RS/6000 an integer value is in r3 and a floating-point value is in
22199 fp1, unless -msoft-float. */
22202 rs6000_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
)
22204 enum machine_mode mode
;
22205 unsigned int regno
;
22207 /* Special handling for structs in darwin64. */
22208 if (rs6000_darwin64_abi
22209 && TYPE_MODE (valtype
) == BLKmode
22210 && TREE_CODE (valtype
) == RECORD_TYPE
22211 && int_size_in_bytes (valtype
) > 0)
22213 CUMULATIVE_ARGS valcum
;
22217 valcum
.fregno
= FP_ARG_MIN_REG
;
22218 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
22219 /* Do a trial code generation as if this were going to be passed as
22220 an argument; if any part goes in memory, we return NULL. */
22221 valret
= rs6000_darwin64_record_arg (&valcum
, valtype
, 1, true);
22224 /* Otherwise fall through to standard ABI rules. */
22227 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DImode
)
22229 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
22230 return gen_rtx_PARALLEL (DImode
,
22232 gen_rtx_EXPR_LIST (VOIDmode
,
22233 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
22235 gen_rtx_EXPR_LIST (VOIDmode
,
22236 gen_rtx_REG (SImode
,
22237 GP_ARG_RETURN
+ 1),
22240 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DCmode
)
22242 return gen_rtx_PARALLEL (DCmode
,
22244 gen_rtx_EXPR_LIST (VOIDmode
,
22245 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
22247 gen_rtx_EXPR_LIST (VOIDmode
,
22248 gen_rtx_REG (SImode
,
22249 GP_ARG_RETURN
+ 1),
22251 gen_rtx_EXPR_LIST (VOIDmode
,
22252 gen_rtx_REG (SImode
,
22253 GP_ARG_RETURN
+ 2),
22255 gen_rtx_EXPR_LIST (VOIDmode
,
22256 gen_rtx_REG (SImode
,
22257 GP_ARG_RETURN
+ 3),
22261 mode
= TYPE_MODE (valtype
);
22262 if ((INTEGRAL_TYPE_P (valtype
) && GET_MODE_BITSIZE (mode
) < BITS_PER_WORD
)
22263 || POINTER_TYPE_P (valtype
))
22264 mode
= TARGET_32BIT
? SImode
: DImode
;
22266 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
22267 /* _Decimal128 must use an even/odd register pair. */
22268 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
22269 else if (SCALAR_FLOAT_TYPE_P (valtype
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
22270 regno
= FP_ARG_RETURN
;
22271 else if (TREE_CODE (valtype
) == COMPLEX_TYPE
22272 && targetm
.calls
.split_complex_arg
)
22273 return rs6000_complex_function_value (mode
);
22274 else if (TREE_CODE (valtype
) == VECTOR_TYPE
22275 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
22276 && ALTIVEC_VECTOR_MODE (mode
))
22277 regno
= ALTIVEC_ARG_RETURN
;
22278 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
22279 && (mode
== DFmode
|| mode
== DCmode
22280 || mode
== TFmode
|| mode
== TCmode
))
22281 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
22283 regno
= GP_ARG_RETURN
;
22285 return gen_rtx_REG (mode
, regno
);
22288 /* Define how to find the value returned by a library function
22289 assuming the value has mode MODE. */
22291 rs6000_libcall_value (enum machine_mode mode
)
22293 unsigned int regno
;
22295 if (TARGET_32BIT
&& TARGET_POWERPC64
&& mode
== DImode
)
22297 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
22298 return gen_rtx_PARALLEL (DImode
,
22300 gen_rtx_EXPR_LIST (VOIDmode
,
22301 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
22303 gen_rtx_EXPR_LIST (VOIDmode
,
22304 gen_rtx_REG (SImode
,
22305 GP_ARG_RETURN
+ 1),
22309 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
22310 /* _Decimal128 must use an even/odd register pair. */
22311 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
22312 else if (SCALAR_FLOAT_MODE_P (mode
)
22313 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
22314 regno
= FP_ARG_RETURN
;
22315 else if (ALTIVEC_VECTOR_MODE (mode
)
22316 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
)
22317 regno
= ALTIVEC_ARG_RETURN
;
22318 else if (COMPLEX_MODE_P (mode
) && targetm
.calls
.split_complex_arg
)
22319 return rs6000_complex_function_value (mode
);
22320 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
22321 && (mode
== DFmode
|| mode
== DCmode
22322 || mode
== TFmode
|| mode
== TCmode
))
22323 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
22325 regno
= GP_ARG_RETURN
;
22327 return gen_rtx_REG (mode
, regno
);
22330 /* Define the offset between two registers, FROM to be eliminated and its
22331 replacement TO, at the start of a routine. */
22333 rs6000_initial_elimination_offset (int from
, int to
)
22335 rs6000_stack_t
*info
= rs6000_stack_info ();
22336 HOST_WIDE_INT offset
;
22338 if (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
22339 offset
= info
->push_p
? 0 : -info
->total_size
;
22340 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
22342 offset
= info
->push_p
? 0 : -info
->total_size
;
22343 if (FRAME_GROWS_DOWNWARD
)
22344 offset
+= info
->fixed_size
+ info
->vars_size
+ info
->parm_size
;
22346 else if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
22347 offset
= FRAME_GROWS_DOWNWARD
22348 ? info
->fixed_size
+ info
->vars_size
+ info
->parm_size
22350 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
22351 offset
= info
->total_size
;
22352 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
22353 offset
= info
->push_p
? info
->total_size
: 0;
22354 else if (from
== RS6000_PIC_OFFSET_TABLE_REGNUM
)
22357 gcc_unreachable ();
22362 /* Return true if TYPE is a SPE or AltiVec opaque type. */
22365 rs6000_is_opaque_type (const_tree type
)
22367 return (type
== opaque_V2SI_type_node
22368 || type
== opaque_V2SF_type_node
22369 || type
== opaque_V4SI_type_node
);
22373 rs6000_dwarf_register_span (rtx reg
)
22378 && (SPE_VECTOR_MODE (GET_MODE (reg
))
22379 || (TARGET_E500_DOUBLE
22380 && (GET_MODE (reg
) == DFmode
|| GET_MODE (reg
) == DDmode
))))
22385 regno
= REGNO (reg
);
22387 /* The duality of the SPE register size wreaks all kinds of havoc.
22388 This is a way of distinguishing r0 in 32-bits from r0 in
22391 gen_rtx_PARALLEL (VOIDmode
,
22394 gen_rtx_REG (SImode
, regno
+ 1200),
22395 gen_rtx_REG (SImode
, regno
))
22397 gen_rtx_REG (SImode
, regno
),
22398 gen_rtx_REG (SImode
, regno
+ 1200)));
22401 /* Fill in sizes for SPE register high parts in table used by unwinder. */
22404 rs6000_init_dwarf_reg_sizes_extra (tree address
)
22409 enum machine_mode mode
= TYPE_MODE (char_type_node
);
22410 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, 0);
22411 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
22412 rtx value
= gen_int_mode (4, mode
);
22414 for (i
= 1201; i
< 1232; i
++)
22416 int column
= DWARF_REG_TO_UNWIND_COLUMN (i
);
22417 HOST_WIDE_INT offset
22418 = DWARF_FRAME_REGNUM (column
) * GET_MODE_SIZE (mode
);
22420 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
22425 /* Map internal gcc register numbers to DWARF2 register numbers. */
22428 rs6000_dbx_register_number (unsigned int regno
)
22430 if (regno
<= 63 || write_symbols
!= DWARF2_DEBUG
)
22432 if (regno
== MQ_REGNO
)
22434 if (regno
== LR_REGNO
)
22436 if (regno
== CTR_REGNO
)
22438 if (CR_REGNO_P (regno
))
22439 return regno
- CR0_REGNO
+ 86;
22440 if (regno
== XER_REGNO
)
22442 if (ALTIVEC_REGNO_P (regno
))
22443 return regno
- FIRST_ALTIVEC_REGNO
+ 1124;
22444 if (regno
== VRSAVE_REGNO
)
22446 if (regno
== VSCR_REGNO
)
22448 if (regno
== SPE_ACC_REGNO
)
22450 if (regno
== SPEFSCR_REGNO
)
22452 /* SPE high reg number. We get these values of regno from
22453 rs6000_dwarf_register_span. */
22454 gcc_assert (regno
>= 1200 && regno
< 1232);
22458 /* target hook eh_return_filter_mode */
22459 static enum machine_mode
22460 rs6000_eh_return_filter_mode (void)
22462 return TARGET_32BIT
? SImode
: word_mode
;
22465 /* Target hook for scalar_mode_supported_p. */
22467 rs6000_scalar_mode_supported_p (enum machine_mode mode
)
22469 if (DECIMAL_FLOAT_MODE_P (mode
))
22472 return default_scalar_mode_supported_p (mode
);
22475 /* Target hook for vector_mode_supported_p. */
22477 rs6000_vector_mode_supported_p (enum machine_mode mode
)
22480 if (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (mode
))
22483 if (TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
22486 else if (TARGET_ALTIVEC
&& ALTIVEC_VECTOR_MODE (mode
))
22493 /* Target hook for invalid_arg_for_unprototyped_fn. */
22494 static const char *
22495 invalid_arg_for_unprototyped_fn (const_tree typelist
, const_tree funcdecl
, const_tree val
)
22497 return (!rs6000_darwin64_abi
22499 && TREE_CODE (TREE_TYPE (val
)) == VECTOR_TYPE
22500 && (funcdecl
== NULL_TREE
22501 || (TREE_CODE (funcdecl
) == FUNCTION_DECL
22502 && DECL_BUILT_IN_CLASS (funcdecl
) != BUILT_IN_MD
)))
22503 ? N_("AltiVec argument passed to unprototyped function")
22507 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
22508 setup by using __stack_chk_fail_local hidden function instead of
22509 calling __stack_chk_fail directly. Otherwise it is better to call
22510 __stack_chk_fail directly. */
22513 rs6000_stack_protect_fail (void)
22515 return (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
22516 ? default_hidden_stack_protect_fail ()
22517 : default_external_stack_protect_fail ();
22520 #include "gt-rs6000.h"