1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
21 MA 02110-1301, USA. */
23 /* Note that some other tm.h files include this one and then override
24 many of the definitions. */
26 /* Definitions for the object file format. These are set at
29 #define OBJECT_XCOFF 1
32 #define OBJECT_MACHO 4
34 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
35 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
36 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
37 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
43 /* Control whether function entry points use a "dot" symbol when
47 /* Default string to use for cpu if not specified. */
48 #ifndef TARGET_CPU_DEFAULT
49 #define TARGET_CPU_DEFAULT ((char *)0)
52 /* If configured for PPC405, support PPC405CR Erratum77. */
53 #ifdef CONFIG_PPC405CR
54 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405)
56 #define PPC405_ERRATUM77 0
59 /* Common ASM definitions used by ASM_SPEC among the various targets
60 for handling -mcpu=xxx switches. */
61 #define ASM_CPU_SPEC \
63 %{mpower: %{!mpower2: -mpwr}} \
65 %{mpowerpc64*: -mppc64} \
66 %{!mpowerpc64*: %{mpowerpc*: -mppc}} \
67 %{mno-power: %{!mpowerpc*: -mcom}} \
68 %{!mno-power: %{!mpower*: %(asm_default)}}} \
69 %{mcpu=common: -mcom} \
70 %{mcpu=power: -mpwr} \
71 %{mcpu=power2: -mpwrx} \
72 %{mcpu=power3: -mppc64} \
73 %{mcpu=power4: -mpower4} \
74 %{mcpu=power5: -mpower4} \
75 %{mcpu=powerpc: -mppc} \
77 %{mcpu=rios1: -mpwr} \
78 %{mcpu=rios2: -mpwrx} \
81 %{mcpu=rs64a: -mppc64} \
85 %{mcpu=405fp: -m405} \
87 %{mcpu=440fp: -m440} \
93 %{mcpu=ec603e: -mppc} \
96 %{mcpu=620: -mppc64} \
97 %{mcpu=630: -mppc64} \
101 %{mcpu=7400: -mppc -maltivec} \
102 %{mcpu=7450: -mppc -maltivec} \
103 %{mcpu=G4: -mppc -maltivec} \
108 %{mcpu=970: -mpower4 -maltivec} \
109 %{mcpu=G5: -mpower4 -maltivec} \
110 %{mcpu=8540: -me500} \
111 %{maltivec: -maltivec} \
114 #define CPP_DEFAULT_SPEC ""
116 #define ASM_DEFAULT_SPEC ""
118 /* This macro defines names of additional specifications to put in the specs
119 that can be used in various specifications like CC1_SPEC. Its definition
120 is an initializer with a subgrouping for each command option.
122 Each subgrouping contains a string constant, that defines the
123 specification name, and a string constant that used by the GCC driver
126 Do not define this macro if it does not need to do anything. */
128 #define SUBTARGET_EXTRA_SPECS
130 #define EXTRA_SPECS \
131 { "cpp_default", CPP_DEFAULT_SPEC }, \
132 { "asm_cpu", ASM_CPU_SPEC }, \
133 { "asm_default", ASM_DEFAULT_SPEC }, \
134 SUBTARGET_EXTRA_SPECS
136 /* Architecture type. */
138 /* Define TARGET_MFCRF if the target assembler does not support the
139 optional field operand for mfcr. */
141 #ifndef HAVE_AS_MFCRF
143 #define TARGET_MFCRF 0
146 /* Define TARGET_POPCNTB if the target assembler does not support the
147 popcount byte instruction. */
149 #ifndef HAVE_AS_POPCNTB
150 #undef TARGET_POPCNTB
151 #define TARGET_POPCNTB 0
154 #ifndef TARGET_SECURE_PLT
155 #define TARGET_SECURE_PLT 0
158 #define TARGET_32BIT (! TARGET_64BIT)
161 #define HAVE_AS_TLS 0
164 /* Return 1 for a symbol ref for a thread-local storage symbol. */
165 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
166 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
169 /* For libgcc2 we make sure this is a compile time constant */
170 #if defined (__64BIT__) || defined (__powerpc64__)
171 #undef TARGET_POWERPC64
172 #define TARGET_POWERPC64 1
174 #undef TARGET_POWERPC64
175 #define TARGET_POWERPC64 0
178 /* The option machinery will define this. */
181 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
183 /* Processor type. Order must match cpu attribute in MD file. */
207 extern enum processor_type rs6000_cpu
;
209 /* Recast the processor type to the cpu attribute. */
210 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
212 /* Define generic processor types based upon current deployment. */
213 #define PROCESSOR_COMMON PROCESSOR_PPC601
214 #define PROCESSOR_POWER PROCESSOR_RIOS1
215 #define PROCESSOR_POWERPC PROCESSOR_PPC604
216 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
218 /* Define the default processor. This is overridden by other tm.h files. */
219 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1
220 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
222 /* Specify the dialect of assembler to use. New mnemonics is dialect one
223 and the old mnemonics are dialect zero. */
224 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
226 /* Types of costly dependences. */
227 enum rs6000_dependence_cost
229 max_dep_latency
= 1000,
232 true_store_to_load_dep_costly
,
233 store_to_load_dep_costly
236 /* Types of nop insertion schemes in sched target hook sched_finish. */
237 enum rs6000_nop_insertion
239 sched_finish_regroup_exact
= 1000,
240 sched_finish_pad_groups
,
244 /* Dispatch group termination caused by an insn. */
245 enum group_termination
251 /* Support for a compile-time default CPU, et cetera. The rules are:
252 --with-cpu is ignored if -mcpu is specified.
253 --with-tune is ignored if -mtune is specified.
254 --with-float is ignored if -mhard-float or -msoft-float are
256 #define OPTION_DEFAULT_SPECS \
257 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
258 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
259 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
261 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
262 struct rs6000_cpu_select
270 extern struct rs6000_cpu_select rs6000_select
[];
273 extern const char *rs6000_debug_name
; /* Name for -mdebug-xxxx option */
274 extern int rs6000_debug_stack
; /* debug stack applications */
275 extern int rs6000_debug_arg
; /* debug argument handling */
277 #define TARGET_DEBUG_STACK rs6000_debug_stack
278 #define TARGET_DEBUG_ARG rs6000_debug_arg
280 extern const char *rs6000_traceback_name
; /* Type of traceback table. */
282 /* These are separate from target_flags because we've run out of bits
284 extern int rs6000_long_double_type_size
;
285 extern int rs6000_altivec_abi
;
286 extern int rs6000_spe_abi
;
287 extern int rs6000_float_gprs
;
288 extern int rs6000_alignment_flags
;
289 extern const char *rs6000_sched_insert_nops_str
;
290 extern enum rs6000_nop_insertion rs6000_sched_insert_nops
;
292 /* Alignment options for fields in structures for sub-targets following
294 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
295 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
297 Override the macro definitions when compiling libobjc to avoid undefined
298 reference to rs6000_alignment_flags due to library's use of GCC alignment
299 macros which use the macros below. */
301 #ifndef IN_TARGET_LIBS
302 #define MASK_ALIGN_POWER 0x00000000
303 #define MASK_ALIGN_NATURAL 0x00000001
304 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
306 #define TARGET_ALIGN_NATURAL 0
309 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
310 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
312 #define TARGET_SPE_ABI 0
314 #define TARGET_E500 0
315 #define TARGET_ISEL 0
316 #define TARGET_FPRS 1
317 #define TARGET_E500_SINGLE 0
318 #define TARGET_E500_DOUBLE 0
320 /* Sometimes certain combinations of command options do not make sense
321 on a particular target machine. You can define a macro
322 `OVERRIDE_OPTIONS' to take account of this. This macro, if
323 defined, is executed once just after all the command options have
326 Do not use this macro to turn on various extra optimizations for
327 `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
329 On the RS/6000 this is used to define the target cpu type. */
331 #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
333 /* Define this to change the optimizations performed by default. */
334 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
336 /* Show we can debug even without a frame pointer. */
337 #define CAN_DEBUG_WITHOUT_FP
340 #define REGISTER_TARGET_PRAGMAS() do { \
341 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
342 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
345 /* Target #defines. */
346 #define TARGET_CPU_CPP_BUILTINS() \
347 rs6000_cpu_cpp_builtins (pfile)
349 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
350 we're compiling for. Some configurations may need to override it. */
351 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
354 if (BYTES_BIG_ENDIAN) \
356 builtin_define ("__BIG_ENDIAN__"); \
357 builtin_define ("_BIG_ENDIAN"); \
358 builtin_assert ("machine=bigendian"); \
362 builtin_define ("__LITTLE_ENDIAN__"); \
363 builtin_define ("_LITTLE_ENDIAN"); \
364 builtin_assert ("machine=littleendian"); \
369 /* Target machine storage layout. */
371 /* Define this macro if it is advisable to hold scalars in registers
372 in a wider mode than that declared by the program. In such cases,
373 the value is constrained to be within the bounds of the declared
374 type, but kept valid in the wider mode. The signedness of the
375 extension may differ from that of the type. */
377 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
378 if (GET_MODE_CLASS (MODE) == MODE_INT \
379 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
380 (MODE) = TARGET_32BIT ? SImode : DImode;
382 /* Define this if most significant bit is lowest numbered
383 in instructions that operate on numbered bit-fields. */
384 /* That is true on RS/6000. */
385 #define BITS_BIG_ENDIAN 1
387 /* Define this if most significant byte of a word is the lowest numbered. */
388 /* That is true on RS/6000. */
389 #define BYTES_BIG_ENDIAN 1
391 /* Define this if most significant word of a multiword number is lowest
394 For RS/6000 we can decide arbitrarily since there are no machine
395 instructions for them. Might as well be consistent with bits and bytes. */
396 #define WORDS_BIG_ENDIAN 1
398 #define MAX_BITS_PER_WORD 64
400 /* Width of a word, in units (bytes). */
401 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
403 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
405 #define MIN_UNITS_PER_WORD 4
407 #define UNITS_PER_FP_WORD 8
408 #define UNITS_PER_ALTIVEC_WORD 16
409 #define UNITS_PER_SPE_WORD 8
411 /* Type used for ptrdiff_t, as a string used in a declaration. */
412 #define PTRDIFF_TYPE "int"
414 /* Type used for size_t, as a string used in a declaration. */
415 #define SIZE_TYPE "long unsigned int"
417 /* Type used for wchar_t, as a string used in a declaration. */
418 #define WCHAR_TYPE "short unsigned int"
420 /* Width of wchar_t in bits. */
421 #define WCHAR_TYPE_SIZE 16
423 /* A C expression for the size in bits of the type `short' on the
424 target machine. If you don't define this, the default is half a
425 word. (If this would be less than one storage unit, it is
426 rounded up to one unit.) */
427 #define SHORT_TYPE_SIZE 16
429 /* A C expression for the size in bits of the type `int' on the
430 target machine. If you don't define this, the default is one
432 #define INT_TYPE_SIZE 32
434 /* A C expression for the size in bits of the type `long' on the
435 target machine. If you don't define this, the default is one
437 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
439 /* A C expression for the size in bits of the type `long long' on the
440 target machine. If you don't define this, the default is two
442 #define LONG_LONG_TYPE_SIZE 64
444 /* A C expression for the size in bits of the type `float' on the
445 target machine. If you don't define this, the default is one
447 #define FLOAT_TYPE_SIZE 32
449 /* A C expression for the size in bits of the type `double' on the
450 target machine. If you don't define this, the default is two
452 #define DOUBLE_TYPE_SIZE 64
454 /* A C expression for the size in bits of the type `long double' on
455 the target machine. If you don't define this, the default is two
457 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
459 /* Define this to set long double type size to use in libgcc2.c, which can
460 not depend on target_flags. */
461 #ifdef __LONG_DOUBLE_128__
462 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
464 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
467 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
468 #define WIDEST_HARDWARE_FP_SIZE 64
470 /* Width in bits of a pointer.
471 See also the macro `Pmode' defined below. */
472 #define POINTER_SIZE (TARGET_32BIT ? 32 : 64)
474 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
475 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
477 /* Boundary (in *bits*) on which stack pointer should be aligned. */
478 #define STACK_BOUNDARY \
479 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI) ? 64 : 128)
481 /* Allocation boundary (in *bits*) for the code of a function. */
482 #define FUNCTION_BOUNDARY 32
484 /* No data type wants to be aligned rounder than this. */
485 #define BIGGEST_ALIGNMENT 128
487 /* A C expression to compute the alignment for a variables in the
488 local store. TYPE is the data type, and ALIGN is the alignment
489 that the object would ordinarily have. */
490 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
491 ((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : \
492 (TARGET_E500_DOUBLE && TYPE_MODE (TYPE) == DFmode) ? 64 : \
493 (TARGET_SPE && TREE_CODE (TYPE) == VECTOR_TYPE) ? 64 : ALIGN)
495 /* Alignment of field after `int : 0' in a structure. */
496 #define EMPTY_FIELD_BOUNDARY 32
498 /* Every structure's size must be a multiple of this. */
499 #define STRUCTURE_SIZE_BOUNDARY 8
501 /* Return 1 if a structure or array containing FIELD should be
502 accessed using `BLKMODE'.
504 For the SPE, simd types are V2SI, and gcc can be tempted to put the
505 entire thing in a DI and use subregs to access the internals.
506 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
507 back-end. Because a single GPR can hold a V2SI, but not a DI, the
508 best thing to do is set structs to BLKmode and avoid Severe Tire
511 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
512 fit into 1, whereas DI still needs two. */
513 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
514 ((TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \
515 || (TARGET_E500_DOUBLE && (MODE) == DFmode))
517 /* A bit-field declared as `int' forces `int' alignment for the struct. */
518 #define PCC_BITFIELD_TYPE_MATTERS 1
520 /* Make strings word-aligned so strcpy from constants will be faster.
521 Make vector constants quadword aligned. */
522 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
523 (TREE_CODE (EXP) == STRING_CST \
524 && (ALIGN) < BITS_PER_WORD \
528 /* Make arrays of chars word-aligned for the same reasons.
529 Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to
531 #define DATA_ALIGNMENT(TYPE, ALIGN) \
532 (TREE_CODE (TYPE) == VECTOR_TYPE ? (TARGET_SPE_ABI ? 64 : 128) \
533 : (TARGET_E500_DOUBLE && TYPE_MODE (TYPE) == DFmode) ? 64 \
534 : TREE_CODE (TYPE) == ARRAY_TYPE \
535 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
536 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
538 /* Nonzero if move instructions will actually fail to work
539 when given unaligned data. */
540 #define STRICT_ALIGNMENT 0
542 /* Define this macro to be the value 1 if unaligned accesses have a cost
543 many times greater than aligned accesses, for example if they are
544 emulated in a trap handler. */
545 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
547 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
548 || (MODE) == DImode) \
551 /* Standard register usage. */
553 /* Number of actual hardware registers.
554 The hardware registers are assigned numbers for the compiler
555 from 0 to just below FIRST_PSEUDO_REGISTER.
556 All registers that the compiler knows about must be given numbers,
557 even those that are not normally considered general registers.
559 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
560 an MQ register, a count register, a link register, and 8 condition
561 register fields, which we view here as separate registers. AltiVec
562 adds 32 vector registers and a VRsave register.
564 In addition, the difference between the frame and argument pointers is
565 a function of the number of registers saved, so we need to have a
566 register for AP that will later be eliminated in favor of SP or FP.
567 This is a normal register, but it is fixed.
569 We also create a pseudo register for float/int conversions, that will
570 really represent the memory location used. It is represented here as
571 a register, in order to work around problems in allocating stack storage
574 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
575 pointer, which is eventually eliminated in favor of SP or FP. */
577 #define FIRST_PSEUDO_REGISTER 114
579 /* This must be included for pre gcc 3.0 glibc compatibility. */
580 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
582 /* Add 32 dwarf columns for synthetic SPE registers. */
583 #define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 1) + 32)
585 /* The SPE has an additional 32 synthetic registers, with DWARF debug
586 info numbering for these registers starting at 1200. While eh_frame
587 register numbering need not be the same as the debug info numbering,
588 we choose to number these regs for eh_frame at 1200 too. This allows
589 future versions of the rs6000 backend to add hard registers and
590 continue to use the gcc hard register numbering for eh_frame. If the
591 extra SPE registers in eh_frame were numbered starting from the
592 current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER
593 changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to
594 avoid invalidating older SPE eh_frame info.
596 We must map them here to avoid huge unwinder tables mostly consisting
598 #define DWARF_REG_TO_UNWIND_COLUMN(r) \
599 ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r))
601 /* Use gcc hard register numbering for eh_frame. */
602 #define DWARF_FRAME_REGNUM(REGNO) (REGNO)
604 /* 1 for registers that have pervasive standard uses
605 and are not available for the register allocator.
607 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
608 as a local register; for all other OS's r2 is the TOC pointer.
610 cr5 is not supposed to be used.
612 On System V implementations, r13 is fixed and not available for use. */
614 #define FIXED_REGISTERS \
615 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
616 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
617 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
618 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
619 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
620 /* AltiVec registers. */ \
621 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
622 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
627 /* 1 for registers not available across function calls.
628 These must include the FIXED_REGISTERS and also any
629 registers that can be used without being saved.
630 The latter must include the registers where values are returned
631 and the register where structure-value addresses are passed.
632 Aside from that, you can include as many other registers as you like. */
634 #define CALL_USED_REGISTERS \
635 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
636 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
637 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
638 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
639 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
640 /* AltiVec registers. */ \
641 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
642 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
647 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
648 the entire set of `FIXED_REGISTERS' be included.
649 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
650 This macro is optional. If not specified, it defaults to the value
651 of `CALL_USED_REGISTERS'. */
653 #define CALL_REALLY_USED_REGISTERS \
654 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
655 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
656 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
657 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
658 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
659 /* AltiVec registers. */ \
660 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
661 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
672 #define MAX_CR_REGNO 75
674 #define FIRST_ALTIVEC_REGNO 77
675 #define LAST_ALTIVEC_REGNO 108
676 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
677 #define VRSAVE_REGNO 109
678 #define VSCR_REGNO 110
679 #define SPE_ACC_REGNO 111
680 #define SPEFSCR_REGNO 112
682 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
683 #define FIRST_SAVED_FP_REGNO (14+32)
684 #define FIRST_SAVED_GP_REGNO 13
686 /* List the order in which to allocate registers. Each register must be
687 listed once, even those in FIXED_REGISTERS.
689 We allocate in the following order:
690 fp0 (not saved or used for anything)
691 fp13 - fp2 (not saved; incoming fp arg registers)
692 fp1 (not saved; return value)
693 fp31 - fp14 (saved; order given to save least number)
694 cr7, cr6 (not saved or special)
695 cr1 (not saved, but used for FP operations)
696 cr0 (not saved, but used for arithmetic operations)
697 cr4, cr3, cr2 (saved)
698 r0 (not saved; cannot be base reg)
699 r9 (not saved; best for TImode)
700 r11, r10, r8-r4 (not saved; highest used first to make less conflict)
701 r3 (not saved; return value register)
702 r31 - r13 (saved; order given to save least number)
703 r12 (not saved; if used for DImode or DFmode would use r13)
704 mq (not saved; best to use it if we can)
705 ctr (not saved; when we have the choice ctr is better)
707 cr5, r1, r2, ap, xer (fixed)
708 v0 - v1 (not saved or used for anything)
709 v13 - v3 (not saved; incoming vector arg registers)
710 v2 (not saved; incoming vector arg reg; return value)
711 v19 - v14 (not saved or used for anything)
712 v31 - v20 (saved; order given to save least number)
714 spe_acc, spefscr (fixed)
719 #define MAYBE_R2_AVAILABLE
720 #define MAYBE_R2_FIXED 2,
722 #define MAYBE_R2_AVAILABLE 2,
723 #define MAYBE_R2_FIXED
726 #define REG_ALLOC_ORDER \
728 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
730 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
731 50, 49, 48, 47, 46, \
732 75, 74, 69, 68, 72, 71, 70, \
733 0, MAYBE_R2_AVAILABLE \
734 9, 11, 10, 8, 7, 6, 5, 4, \
736 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
737 18, 17, 16, 15, 14, 13, 12, \
739 73, 1, MAYBE_R2_FIXED 67, 76, \
740 /* AltiVec registers. */ \
742 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
744 96, 95, 94, 93, 92, 91, \
745 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
750 /* True if register is floating-point. */
751 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
753 /* True if register is a condition register. */
754 #define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75)
756 /* True if register is a condition register, but not cr0. */
757 #define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75)
759 /* True if register is an integer register. */
760 #define INT_REGNO_P(N) \
761 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
763 /* SPE SIMD registers are just the GPRs. */
764 #define SPE_SIMD_REGNO_P(N) ((N) <= 31)
766 /* True if register is the XER register. */
767 #define XER_REGNO_P(N) ((N) == XER_REGNO)
769 /* True if register is an AltiVec register. */
770 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
772 /* Return number of consecutive hard regs needed starting at reg REGNO
773 to hold something of mode MODE. */
775 #define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs ((REGNO), (MODE))
777 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
778 ((TARGET_32BIT && TARGET_POWERPC64 \
779 && (GET_MODE_SIZE (MODE) > 4) \
780 && INT_REGNO_P (REGNO)) ? 1 : 0)
782 #define ALTIVEC_VECTOR_MODE(MODE) \
783 ((MODE) == V16QImode \
784 || (MODE) == V8HImode \
785 || (MODE) == V4SFmode \
786 || (MODE) == V4SImode)
788 #define SPE_VECTOR_MODE(MODE) \
789 ((MODE) == V4HImode \
790 || (MODE) == V2SFmode \
791 || (MODE) == V1DImode \
792 || (MODE) == V2SImode)
794 #define UNITS_PER_SIMD_WORD \
795 (TARGET_ALTIVEC ? UNITS_PER_ALTIVEC_WORD \
796 : (TARGET_SPE ? UNITS_PER_SPE_WORD : UNITS_PER_WORD))
798 /* Value is TRUE if hard register REGNO can hold a value of
799 machine-mode MODE. */
800 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
801 rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO]
803 /* Value is 1 if it is a good idea to tie two pseudo registers
804 when one has mode MODE1 and one has mode MODE2.
805 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
806 for any hard reg, then this must be 0 for correct output. */
807 #define MODES_TIEABLE_P(MODE1, MODE2) \
808 (GET_MODE_CLASS (MODE1) == MODE_FLOAT \
809 ? GET_MODE_CLASS (MODE2) == MODE_FLOAT \
810 : GET_MODE_CLASS (MODE2) == MODE_FLOAT \
811 ? GET_MODE_CLASS (MODE1) == MODE_FLOAT \
812 : GET_MODE_CLASS (MODE1) == MODE_CC \
813 ? GET_MODE_CLASS (MODE2) == MODE_CC \
814 : GET_MODE_CLASS (MODE2) == MODE_CC \
815 ? GET_MODE_CLASS (MODE1) == MODE_CC \
816 : SPE_VECTOR_MODE (MODE1) \
817 ? SPE_VECTOR_MODE (MODE2) \
818 : SPE_VECTOR_MODE (MODE2) \
819 ? SPE_VECTOR_MODE (MODE1) \
820 : ALTIVEC_VECTOR_MODE (MODE1) \
821 ? ALTIVEC_VECTOR_MODE (MODE2) \
822 : ALTIVEC_VECTOR_MODE (MODE2) \
823 ? ALTIVEC_VECTOR_MODE (MODE1) \
826 /* Post-reload, we can't use any new AltiVec registers, as we already
827 emitted the vrsave mask. */
829 #define HARD_REGNO_RENAME_OK(SRC, DST) \
830 (! ALTIVEC_REGNO_P (DST) || regs_ever_live[DST])
832 /* A C expression returning the cost of moving data from a register of class
833 CLASS1 to one of CLASS2. */
835 #define REGISTER_MOVE_COST rs6000_register_move_cost
837 /* A C expressions returning the cost of moving data of MODE from a register to
840 #define MEMORY_MOVE_COST rs6000_memory_move_cost
842 /* Specify the cost of a branch insn; roughly the number of extra insns that
843 should be added to avoid a branch.
845 Set this to 3 on the RS/6000 since that is roughly the average cost of an
846 unscheduled conditional branch. */
848 #define BRANCH_COST 3
850 /* Override BRANCH_COST heuristic which empirically produces worse
851 performance for removing short circuiting from the logical ops. */
853 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
855 /* A fixed register used at prologue and epilogue generation to fix
856 addressing modes. The SPE needs heavy addressing fixes at the last
857 minute, and it's best to save a register for it.
859 AltiVec also needs fixes, but we've gotten around using r11, which
860 is actually wrong because when use_backchain_to_restore_sp is true,
861 we end up clobbering r11.
863 The AltiVec case needs to be fixed. Dunno if we should break ABI
864 compatibility and reserve a register for it as well.. */
866 #define FIXED_SCRATCH (TARGET_SPE ? 14 : 11)
868 /* Define this macro to change register usage conditional on target
871 #define CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage ()
873 /* Specify the registers used for certain standard purposes.
874 The values of these macros are register numbers. */
876 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
877 /* #define PC_REGNUM */
879 /* Register to use for pushing function arguments. */
880 #define STACK_POINTER_REGNUM 1
882 /* Base register for access to local variables of the function. */
883 #define HARD_FRAME_POINTER_REGNUM 31
885 /* Base register for access to local variables of the function. */
886 #define FRAME_POINTER_REGNUM 113
888 /* Value should be nonzero if functions must have frame pointers.
889 Zero means the frame pointer need not be set up (and parms
890 may be accessed via the stack pointer) in functions that seem suitable.
891 This is computed in `reload', in reload1.c. */
892 #define FRAME_POINTER_REQUIRED 0
894 /* Base register for access to arguments of the function. */
895 #define ARG_POINTER_REGNUM 67
897 /* Place to put static chain when calling a function that requires it. */
898 #define STATIC_CHAIN_REGNUM 11
900 /* Link register number. */
901 #define LINK_REGISTER_REGNUM 65
903 /* Count register number. */
904 #define COUNT_REGISTER_REGNUM 66
906 /* Define the classes of registers for register constraints in the
907 machine description. Also define ranges of constants.
909 One of the classes must always be named ALL_REGS and include all hard regs.
910 If there is more than one class, another class must be named NO_REGS
911 and contain no registers.
913 The name GENERAL_REGS must be the name of a class (or an alias for
914 another name such as ALL_REGS). This is the class of registers
915 that is allowed by "g" or "r" in a register constraint.
916 Also, registers outside this class are allocated only when
917 instructions express preferences for them.
919 The classes must be numbered in nondecreasing order; that is,
920 a larger-numbered class must never be contained completely
921 in a smaller-numbered class.
923 For any two classes, it is very desirable that there be another
924 class that represents their union. */
926 /* The RS/6000 has three types of registers, fixed-point, floating-point,
927 and condition registers, plus three special registers, MQ, CTR, and the
928 link register. AltiVec adds a vector register class.
930 However, r0 is special in that it cannot be used as a base register.
931 So make a class for registers valid as base registers.
933 Also, cr0 is the only condition code register that can be used in
934 arithmetic insns, so make a separate class for it. */
962 #define N_REG_CLASSES (int) LIM_REG_CLASSES
964 /* Give names of register classes as strings for dump file. */
966 #define REG_CLASS_NAMES \
977 "NON_SPECIAL_REGS", \
981 "LINK_OR_CTR_REGS", \
983 "SPEC_OR_GEN_REGS", \
991 /* Define which registers fit in which classes.
992 This is an initializer for a vector of HARD_REG_SET
993 of length N_REG_CLASSES. */
995 #define REG_CLASS_CONTENTS \
997 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
998 { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */ \
999 { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */ \
1000 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
1001 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
1002 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
1003 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
1004 { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \
1005 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \
1006 { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \
1007 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
1008 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
1009 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
1010 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
1011 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \
1012 { 0xffffffff, 0x00000000, 0x0000000f, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \
1013 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
1014 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
1015 { 0xffffffff, 0x00000000, 0x0000efff, 0x00000000 }, /* NON_FLOAT_REGS */ \
1016 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \
1017 { 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff } /* ALL_REGS */ \
1020 /* The same information, inverted:
1021 Return the class number of the smallest class containing
1022 reg number REGNO. This could be a conditional expression
1023 or could index an array. */
1025 #define REGNO_REG_CLASS(REGNO) \
1026 ((REGNO) == 0 ? GENERAL_REGS \
1027 : (REGNO) < 32 ? BASE_REGS \
1028 : FP_REGNO_P (REGNO) ? FLOAT_REGS \
1029 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS \
1030 : (REGNO) == CR0_REGNO ? CR0_REGS \
1031 : CR_REGNO_P (REGNO) ? CR_REGS \
1032 : (REGNO) == MQ_REGNO ? MQ_REGS \
1033 : (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS \
1034 : (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS \
1035 : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \
1036 : (REGNO) == XER_REGNO ? XER_REGS \
1037 : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \
1038 : (REGNO) == VSCR_REGNO ? VRSAVE_REGS \
1039 : (REGNO) == SPE_ACC_REGNO ? SPE_ACC_REGS \
1040 : (REGNO) == SPEFSCR_REGNO ? SPEFSCR_REGS \
1041 : (REGNO) == FRAME_POINTER_REGNUM ? BASE_REGS \
1044 /* The class value for index registers, and the one for base regs. */
1045 #define INDEX_REG_CLASS GENERAL_REGS
1046 #define BASE_REG_CLASS BASE_REGS
1048 /* Get reg_class from a letter such as appears in the machine description. */
1050 #define REG_CLASS_FROM_LETTER(C) \
1051 ((C) == 'f' ? ((TARGET_HARD_FLOAT && TARGET_FPRS) ? FLOAT_REGS : NO_REGS) \
1052 : (C) == 'b' ? BASE_REGS \
1053 : (C) == 'h' ? SPECIAL_REGS \
1054 : (C) == 'q' ? MQ_REGS \
1055 : (C) == 'c' ? CTR_REGS \
1056 : (C) == 'l' ? LINK_REGS \
1057 : (C) == 'v' ? ALTIVEC_REGS \
1058 : (C) == 'x' ? CR0_REGS \
1059 : (C) == 'y' ? CR_REGS \
1060 : (C) == 'z' ? XER_REGS \
1063 /* The letters I, J, K, L, M, N, and P in a register constraint string
1064 can be used to stand for particular ranges of immediate operands.
1065 This macro defines what the ranges are.
1066 C is the letter, and VALUE is a constant value.
1067 Return 1 if VALUE is in the range specified by C.
1069 `I' is a signed 16-bit constant
1070 `J' is a constant with only the high-order 16 bits nonzero
1071 `K' is a constant with only the low-order 16 bits nonzero
1072 `L' is a signed 16-bit constant shifted left 16 bits
1073 `M' is a constant that is greater than 31
1074 `N' is a positive constant that is an exact power of two
1075 `O' is the constant zero
1076 `P' is a constant whose negation is a signed 16-bit constant */
1078 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1079 ( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
1080 : (C) == 'J' ? ((VALUE) & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0 \
1081 : (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \
1082 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
1083 && ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \
1084 : (C) == 'M' ? (VALUE) > 31 \
1085 : (C) == 'N' ? (VALUE) > 0 && exact_log2 (VALUE) >= 0 \
1086 : (C) == 'O' ? (VALUE) == 0 \
1087 : (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x10000 \
1090 /* Similar, but for floating constants, and defining letters G and H.
1091 Here VALUE is the CONST_DOUBLE rtx itself.
1093 We flag for special constants when we can copy the constant into
1094 a general register in two insns for DF/DI and one insn for SF.
1096 'H' is used for DI/DF constants that take 3 insns. */
1098 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1099 ( (C) == 'G' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) \
1100 == ((GET_MODE (VALUE) == SFmode) ? 1 : 2)) \
1101 : (C) == 'H' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) == 3) \
1104 /* Optional extra constraints for this machine.
1106 'Q' means that is a memory operand that is just an offset from a reg.
1107 'R' is for AIX TOC entries.
1108 'S' is a constant that can be placed into a 64-bit mask operand.
1109 'T' is a constant that can be placed into a 32-bit mask operand.
1110 'U' is for V.4 small data references.
1111 'W' is a vector constant that can be easily generated (no mem refs).
1112 'Y' is an indexed or word-aligned displacement memory operand.
1113 'Z' is an indexed or indirect memory operand.
1114 'a' is an indexed or indirect address operand.
1115 't' is for AND masks that can be performed by two rldic{l,r} insns
1116 (but excluding those that could match other constraints of anddi3.) */
1118 #define EXTRA_CONSTRAINT(OP, C) \
1119 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
1120 : (C) == 'R' ? legitimate_constant_pool_address_p (OP) \
1121 : (C) == 'S' ? mask64_operand (OP, DImode) \
1122 : (C) == 'T' ? mask_operand (OP, GET_MODE (OP)) \
1123 : (C) == 'U' ? (DEFAULT_ABI == ABI_V4 \
1124 && small_data_operand (OP, GET_MODE (OP))) \
1125 : (C) == 't' ? (mask64_2_operand (OP, DImode) \
1126 && (fixed_regs[CR0_REGNO] \
1127 || !logical_operand (OP, DImode)) \
1128 && !mask_operand (OP, DImode) \
1129 && !mask64_operand (OP, DImode)) \
1130 : (C) == 'W' ? (easy_vector_constant (OP, GET_MODE (OP))) \
1131 : (C) == 'Y' ? (word_offset_memref_operand (OP, GET_MODE (OP))) \
1132 : (C) == 'Z' ? (indexed_or_indirect_operand (OP, GET_MODE (OP))) \
1133 : (C) == 'a' ? (indexed_or_indirect_address (OP, GET_MODE (OP))) \
1136 /* Define which constraints are memory constraints. Tell reload
1137 that any memory address can be reloaded by copying the
1138 memory address into a base register if required. */
1140 #define EXTRA_MEMORY_CONSTRAINT(C, STR) \
1141 ((C) == 'Q' || (C) == 'Y' || (C) == 'Z')
1143 /* Define which constraints should be treated like address constraints
1144 by the reload pass. */
1146 #define EXTRA_ADDRESS_CONSTRAINT(C, STR) \
1149 /* Given an rtx X being reloaded into a reg required to be
1150 in class CLASS, return the class of reg to actually use.
1151 In general this is just CLASS; but on some machines
1152 in some cases it is preferable to use a more restrictive class.
1154 On the RS/6000, we have to return NO_REGS when we want to reload a
1155 floating-point CONST_DOUBLE to force it to be copied to memory.
1157 We also don't want to reload integer values into floating-point
1158 registers if we can at all help it. In fact, this can
1159 cause reload to die, if it tries to generate a reload of CTR
1160 into a FP register and discovers it doesn't have the memory location
1163 ??? Would it be a good idea to have reload do the converse, that is
1164 try to reload floating modes into FP registers if possible?
1167 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1169 && reg_classes_intersect_p ((CLASS), FLOAT_REGS)) \
1171 : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1172 && (CLASS) == NON_SPECIAL_REGS) \
1176 /* Return the register class of a scratch register needed to copy IN into
1177 or out of a register in CLASS in MODE. If it can be done directly,
1178 NO_REGS is returned. */
1180 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1181 secondary_reload_class (CLASS, MODE, IN)
1183 /* If we are copying between FP or AltiVec registers and anything
1184 else, we need a memory location. */
1186 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1187 ((CLASS1) != (CLASS2) && ((CLASS1) == FLOAT_REGS \
1188 || (CLASS2) == FLOAT_REGS \
1189 || (CLASS1) == ALTIVEC_REGS \
1190 || (CLASS2) == ALTIVEC_REGS))
1192 /* Return the maximum number of consecutive registers
1193 needed to represent mode MODE in a register of class CLASS.
1195 On RS/6000, this is the size of MODE in words,
1196 except in the FP regs, where a single reg is enough for two words. */
1197 #define CLASS_MAX_NREGS(CLASS, MODE) \
1198 (((CLASS) == FLOAT_REGS) \
1199 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
1200 : (TARGET_E500_DOUBLE && (CLASS) == GENERAL_REGS && (MODE) == DFmode) \
1202 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1205 /* Return a class of registers that cannot change FROM mode to TO mode. */
1207 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1208 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) \
1209 && GET_MODE_SIZE (FROM) >= 8 && GET_MODE_SIZE (TO) >= 8) \
1211 : GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1212 ? reg_classes_intersect_p (FLOAT_REGS, CLASS) \
1213 : (TARGET_E500_DOUBLE && (((TO) == DFmode) + ((FROM) == DFmode)) == 1) \
1214 ? reg_classes_intersect_p (GENERAL_REGS, CLASS) \
1215 : (TARGET_E500_DOUBLE && (((TO) == DImode) + ((FROM) == DImode)) == 1) \
1216 ? reg_classes_intersect_p (GENERAL_REGS, CLASS) \
1217 : (TARGET_SPE && (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1) \
1218 ? reg_classes_intersect_p (GENERAL_REGS, CLASS) \
1221 /* Stack layout; function entry, exit and calling. */
1223 /* Enumeration to give which calling sequence to use. */
1226 ABI_AIX
, /* IBM's AIX */
1227 ABI_V4
, /* System V.4/eabi */
1228 ABI_DARWIN
/* Apple's Darwin (OS X kernel) */
1231 extern enum rs6000_abi rs6000_current_abi
; /* available for use by subtarget */
1233 /* Define this if pushing a word on the stack
1234 makes the stack pointer a smaller address. */
1235 #define STACK_GROWS_DOWNWARD
1237 /* Offsets recorded in opcodes are a multiple of this alignment factor. */
1238 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
1240 /* Define this to nonzero if the nominal address of the stack frame
1241 is at the high-address end of the local variables;
1242 that is, each additional local variable allocated
1243 goes at a more negative offset in the frame.
1245 On the RS/6000, we grow upwards, from the area after the outgoing
1247 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0)
1249 /* Size of the outgoing register save area */
1250 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
1251 || DEFAULT_ABI == ABI_DARWIN) \
1252 ? (TARGET_64BIT ? 64 : 32) \
1255 /* Size of the fixed area on the stack */
1256 #define RS6000_SAVE_AREA \
1257 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
1258 << (TARGET_64BIT ? 1 : 0))
1260 /* MEM representing address to save the TOC register */
1261 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1262 plus_constant (stack_pointer_rtx, \
1263 (TARGET_32BIT ? 20 : 40)))
1265 /* Align an address */
1266 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
1268 /* Offset within stack frame to start allocating local variables at.
1269 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1270 first local allocated. Otherwise, it is the offset to the BEGINNING
1271 of the first local allocated.
1273 On the RS/6000, the frame pointer is the same as the stack pointer,
1274 except for dynamic allocations. So we start after the fixed area and
1275 outgoing parameter area. */
1277 #define STARTING_FRAME_OFFSET \
1278 (FRAME_GROWS_DOWNWARD \
1280 : (RS6000_ALIGN (current_function_outgoing_args_size, \
1281 TARGET_ALTIVEC ? 16 : 8) \
1282 + RS6000_SAVE_AREA))
1284 /* Offset from the stack pointer register to an item dynamically
1285 allocated on the stack, e.g., by `alloca'.
1287 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1288 length of the outgoing arguments. The default is correct for most
1289 machines. See `function.c' for details. */
1290 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1291 (RS6000_ALIGN (current_function_outgoing_args_size, \
1292 TARGET_ALTIVEC ? 16 : 8) \
1293 + (STACK_POINTER_OFFSET))
1295 /* If we generate an insn to push BYTES bytes,
1296 this says how many the stack pointer really advances by.
1297 On RS/6000, don't define this because there are no push insns. */
1298 /* #define PUSH_ROUNDING(BYTES) */
1300 /* Offset of first parameter from the argument pointer register value.
1301 On the RS/6000, we define the argument pointer to the start of the fixed
1303 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1305 /* Offset from the argument pointer register value to the top of
1306 stack. This is different from FIRST_PARM_OFFSET because of the
1307 register save area. */
1308 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1310 /* Define this if stack space is still allocated for a parameter passed
1311 in a register. The value is the number of bytes allocated to this
1313 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
1315 /* Define this if the above stack space is to be considered part of the
1316 space allocated by the caller. */
1317 #define OUTGOING_REG_PARM_STACK_SPACE
1319 /* This is the difference between the logical top of stack and the actual sp.
1321 For the RS/6000, sp points past the fixed area. */
1322 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1324 /* Define this if the maximum size of all the outgoing args is to be
1325 accumulated and pushed during the prologue. The amount can be
1326 found in the variable current_function_outgoing_args_size. */
1327 #define ACCUMULATE_OUTGOING_ARGS 1
1329 /* Value is the number of bytes of arguments automatically
1330 popped when returning from a subroutine call.
1331 FUNDECL is the declaration node of the function (as a tree),
1332 FUNTYPE is the data type of the function (as a tree),
1333 or for a library call it is an identifier node for the subroutine name.
1334 SIZE is the number of bytes of arguments passed on the stack. */
1336 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1338 /* Define how to find the value returned by a function.
1339 VALTYPE is the data type of the value (as a tree).
1340 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1341 otherwise, FUNC is 0. */
1343 #define FUNCTION_VALUE(VALTYPE, FUNC) rs6000_function_value ((VALTYPE), (FUNC))
1345 /* Define how to find the value returned by a library function
1346 assuming the value has mode MODE. */
1348 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
1350 /* DRAFT_V4_STRUCT_RET defaults off. */
1351 #define DRAFT_V4_STRUCT_RET 0
1353 /* Let TARGET_RETURN_IN_MEMORY control what happens. */
1354 #define DEFAULT_PCC_STRUCT_RETURN 0
1356 /* Mode of stack savearea.
1357 FUNCTION is VOIDmode because calling convention maintains SP.
1358 BLOCK needs Pmode for SP.
1359 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1360 #define STACK_SAVEAREA_MODE(LEVEL) \
1361 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1362 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
1364 /* Minimum and maximum general purpose registers used to hold arguments. */
1365 #define GP_ARG_MIN_REG 3
1366 #define GP_ARG_MAX_REG 10
1367 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1369 /* Minimum and maximum floating point registers used to hold arguments. */
1370 #define FP_ARG_MIN_REG 33
1371 #define FP_ARG_AIX_MAX_REG 45
1372 #define FP_ARG_V4_MAX_REG 40
1373 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
1374 || DEFAULT_ABI == ABI_DARWIN) \
1375 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
1376 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1378 /* Minimum and maximum AltiVec registers used to hold arguments. */
1379 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1380 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1381 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1383 /* Return registers */
1384 #define GP_ARG_RETURN GP_ARG_MIN_REG
1385 #define FP_ARG_RETURN FP_ARG_MIN_REG
1386 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1388 /* Flags for the call/call_value rtl operations set up by function_arg */
1389 #define CALL_NORMAL 0x00000000 /* no special processing */
1390 /* Bits in 0x00000001 are unused. */
1391 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1392 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1393 #define CALL_LONG 0x00000008 /* always call indirect */
1394 #define CALL_LIBCALL 0x00000010 /* libcall */
1396 /* We don't have prologue and epilogue functions to save/restore
1397 everything for most ABIs. */
1398 #define WORLD_SAVE_P(INFO) 0
1400 /* 1 if N is a possible register number for a function value
1401 as seen by the caller.
1403 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1404 #define FUNCTION_VALUE_REGNO_P(N) \
1405 ((N) == GP_ARG_RETURN \
1406 || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT && TARGET_FPRS) \
1407 || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
1409 /* 1 if N is a possible register number for function argument passing.
1410 On RS/6000, these are r3-r10 and fp1-fp13.
1411 On AltiVec, v2 - v13 are used for passing vectors. */
1412 #define FUNCTION_ARG_REGNO_P(N) \
1413 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \
1414 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \
1415 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
1416 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \
1417 && TARGET_HARD_FLOAT && TARGET_FPRS))
1419 /* Define a data type for recording info about an argument list
1420 during the scan of that argument list. This data type should
1421 hold all necessary information about the function itself
1422 and about the args processed so far, enough to enable macros
1423 such as FUNCTION_ARG to determine where the next arg should go.
1425 On the RS/6000, this is a structure. The first element is the number of
1426 total argument words, the second is used to store the next
1427 floating-point register number, and the third says how many more args we
1428 have prototype types for.
1430 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1431 the next available GP register, `fregno' is the next available FP
1432 register, and `words' is the number of words used on the stack.
1434 The varargs/stdarg support requires that this structure's size
1435 be a multiple of sizeof(int). */
1437 typedef struct rs6000_args
1439 int words
; /* # words used for passing GP registers */
1440 int fregno
; /* next available FP register */
1441 int vregno
; /* next available AltiVec register */
1442 int nargs_prototype
; /* # args left in the current prototype */
1443 int prototype
; /* Whether a prototype was defined */
1444 int stdarg
; /* Whether function is a stdarg function. */
1445 int call_cookie
; /* Do special things for this call */
1446 int sysv_gregno
; /* next available GP register */
1447 int intoffset
; /* running offset in struct (darwin64) */
1448 int use_stack
; /* any part of struct on stack (darwin64) */
1449 int named
; /* false for varargs params */
1452 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1453 for a call to a function whose data type is FNTYPE.
1454 For a library call, FNTYPE is 0. */
1456 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1457 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, N_NAMED_ARGS)
1459 /* Similar, but when scanning the definition of a procedure. We always
1460 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1462 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1463 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, 1000)
1465 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1467 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1468 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, 0)
1470 /* Update the data in CUM to advance over an argument
1471 of mode MODE and data type TYPE.
1472 (TYPE is null for libcalls where that information may not be available.) */
1474 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1475 function_arg_advance (&CUM, MODE, TYPE, NAMED, 0)
1477 /* Determine where to put an argument to a function.
1478 Value is zero to push the argument on the stack,
1479 or a hard register in which to store the argument.
1481 MODE is the argument's machine mode.
1482 TYPE is the data type of the argument (as a tree).
1483 This is null for libcalls where that information may
1485 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1486 the preceding args and about the function being called.
1487 NAMED is nonzero if this argument is a named parameter
1488 (otherwise it is an extra parameter matching an ellipsis).
1490 On RS/6000 the first eight words of non-FP are normally in registers
1491 and the rest are pushed. The first 13 FP args are in registers.
1493 If this is floating-point and no prototype is specified, we use
1494 both an FP and integer register (or possibly FP reg and stack). Library
1495 functions (when TYPE is zero) always have the proper types for args,
1496 so we can pass the FP value just in one register. emit_library_function
1497 doesn't support EXPR_LIST anyway. */
1499 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1500 function_arg (&CUM, MODE, TYPE, NAMED)
1502 /* If defined, a C expression which determines whether, and in which
1503 direction, to pad out an argument with extra space. The value
1504 should be of type `enum direction': either `upward' to pad above
1505 the argument, `downward' to pad below, or `none' to inhibit
1508 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
1510 /* If defined, a C expression that gives the alignment boundary, in bits,
1511 of an argument with the specified mode and type. If it is not defined,
1512 PARM_BOUNDARY is used for all arguments. */
1514 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1515 function_arg_boundary (MODE, TYPE)
1517 /* Implement `va_start' for varargs and stdarg. */
1518 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1519 rs6000_va_start (valist, nextarg)
1521 #define PAD_VARARGS_DOWN \
1522 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1524 /* Output assembler code to FILE to increment profiler label # LABELNO
1525 for profiling a function entry. */
1527 #define FUNCTION_PROFILER(FILE, LABELNO) \
1528 output_function_profiler ((FILE), (LABELNO));
1530 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1531 the stack pointer does not matter. No definition is equivalent to
1534 On the RS/6000, this is nonzero because we can restore the stack from
1535 its backpointer, which we maintain. */
1536 #define EXIT_IGNORE_STACK 1
1538 /* Define this macro as a C expression that is nonzero for registers
1539 that are used by the epilogue or the return' pattern. The stack
1540 and frame pointer registers are already be assumed to be used as
1543 #define EPILOGUE_USES(REGNO) \
1544 ((reload_completed && (REGNO) == LINK_REGISTER_REGNUM) \
1545 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1546 || (current_function_calls_eh_return \
1551 /* TRAMPOLINE_TEMPLATE deleted */
1553 /* Length in units of the trampoline for entering a nested function. */
1555 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1557 /* Emit RTL insns to initialize the variable parts of a trampoline.
1558 FNADDR is an RTX for the address of the function's pure code.
1559 CXT is an RTX for the static chain value for the function. */
1561 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
1562 rs6000_initialize_trampoline (ADDR, FNADDR, CXT)
1564 /* Definitions for __builtin_return_address and __builtin_frame_address.
1565 __builtin_return_address (0) should give link register (65), enable
1567 /* This should be uncommented, so that the link register is used, but
1568 currently this would result in unmatched insns and spilling fixed
1569 registers so we'll leave it for another day. When these problems are
1570 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1572 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1574 /* Number of bytes into the frame return addresses can be found. See
1575 rs6000_stack_info in rs6000.c for more information on how the different
1576 abi's store the return address. */
1577 #define RETURN_ADDRESS_OFFSET \
1578 ((DEFAULT_ABI == ABI_AIX \
1579 || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \
1580 (DEFAULT_ABI == ABI_V4) ? 4 : \
1581 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
1583 /* The current return address is in link register (65). The return address
1584 of anything farther back is accessed normally at an offset of 8 from the
1586 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1587 (rs6000_return_addr (COUNT, FRAME))
1590 /* Definitions for register eliminations.
1592 We have two registers that can be eliminated on the RS/6000. First, the
1593 frame pointer register can often be eliminated in favor of the stack
1594 pointer register. Secondly, the argument pointer register can always be
1595 eliminated; it is replaced with either the stack or frame pointer.
1597 In addition, we use the elimination mechanism to see if r30 is needed
1598 Initially we assume that it isn't. If it is, we spill it. This is done
1599 by making it an eliminable register. We replace it with itself so that
1600 if it isn't needed, then existing uses won't be modified. */
1602 /* This is an array of structures. Each structure initializes one pair
1603 of eliminable registers. The "from" register number is given first,
1604 followed by "to". Eliminations of the same "from" register are listed
1605 in order of preference. */
1606 #define ELIMINABLE_REGS \
1607 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1608 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1609 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1610 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1611 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1612 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
1614 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1615 Frame pointer elimination is automatically handled.
1617 For the RS/6000, if frame pointer elimination is being done, we would like
1618 to convert ap into fp, not sp.
1620 We need r30 if -mminimal-toc was specified, and there are constant pool
1623 #define CAN_ELIMINATE(FROM, TO) \
1624 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
1625 ? ! frame_pointer_needed \
1626 : (FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM \
1627 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \
1630 /* Define the offset between two registers, one to be eliminated, and the other
1631 its replacement, at the start of a routine. */
1632 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1633 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
1635 /* Addressing modes, and classification of registers for them. */
1637 #define HAVE_PRE_DECREMENT 1
1638 #define HAVE_PRE_INCREMENT 1
1640 /* Macros to check register numbers against specific register classes. */
1642 /* These assume that REGNO is a hard or pseudo reg number.
1643 They give nonzero only if REGNO is a hard reg of the suitable class
1644 or a pseudo reg currently allocated to a suitable hard reg.
1645 Since they use reg_renumber, they are safe only once reg_renumber
1646 has been allocated, which happens in local-alloc.c. */
1648 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1649 ((REGNO) < FIRST_PSEUDO_REGISTER \
1650 ? (REGNO) <= 31 || (REGNO) == 67 \
1651 || (REGNO) == FRAME_POINTER_REGNUM \
1652 : (reg_renumber[REGNO] >= 0 \
1653 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1654 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1656 #define REGNO_OK_FOR_BASE_P(REGNO) \
1657 ((REGNO) < FIRST_PSEUDO_REGISTER \
1658 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1659 || (REGNO) == FRAME_POINTER_REGNUM \
1660 : (reg_renumber[REGNO] > 0 \
1661 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1662 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1664 /* Maximum number of registers that can appear in a valid memory address. */
1666 #define MAX_REGS_PER_ADDRESS 2
1668 /* Recognize any constant value that is a valid address. */
1670 #define CONSTANT_ADDRESS_P(X) \
1671 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1672 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1673 || GET_CODE (X) == HIGH)
1675 /* Nonzero if the constant value X is a legitimate general operand.
1676 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1678 On the RS/6000, all integer constants are acceptable, most won't be valid
1679 for particular insns, though. Only easy FP constants are
1682 #define LEGITIMATE_CONSTANT_P(X) \
1683 (((GET_CODE (X) != CONST_DOUBLE \
1684 && GET_CODE (X) != CONST_VECTOR) \
1685 || GET_MODE (X) == VOIDmode \
1686 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
1687 || easy_fp_constant (X, GET_MODE (X)) \
1688 || easy_vector_constant (X, GET_MODE (X))) \
1689 && !rs6000_tls_referenced_p (X))
1691 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
1692 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \
1693 && EASY_VECTOR_15((n) >> 1))
1695 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1696 and check its validity for a certain class.
1697 We have two alternate definitions for each of them.
1698 The usual definition accepts all pseudo regs; the other rejects
1699 them unless they have been allocated suitable hard regs.
1700 The symbol REG_OK_STRICT causes the latter definition to be used.
1702 Most source files want to accept pseudo regs in the hope that
1703 they will get allocated to the class that the insn wants them to be in.
1704 Source files for reload pass need to be strict.
1705 After reload, it makes no difference, since pseudo regs have
1706 been eliminated by then. */
1708 #ifdef REG_OK_STRICT
1709 # define REG_OK_STRICT_FLAG 1
1711 # define REG_OK_STRICT_FLAG 0
1714 /* Nonzero if X is a hard reg that can be used as an index
1715 or if it is a pseudo reg in the non-strict case. */
1716 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1718 && (REGNO (X) <= 31 \
1719 || REGNO (X) == ARG_POINTER_REGNUM \
1720 || REGNO (X) == FRAME_POINTER_REGNUM \
1721 || REGNO (X) >= FIRST_PSEUDO_REGISTER)) \
1722 || ((STRICT) && REGNO_OK_FOR_INDEX_P (REGNO (X))))
1724 /* Nonzero if X is a hard reg that can be used as a base reg
1725 or if it is a pseudo reg in the non-strict case. */
1726 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1727 (REGNO (X) > 0 && INT_REG_OK_FOR_INDEX_P (X, (STRICT)))
1729 #define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG)
1730 #define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG)
1732 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1733 that is a valid memory address for an instruction.
1734 The MODE argument is the machine mode for the MEM expression
1735 that wants to use this address.
1737 On the RS/6000, there are four valid address: a SYMBOL_REF that
1738 refers to a constant pool entry of an address (or the sum of it
1739 plus a constant), a short (16-bit signed) constant plus a register,
1740 the sum of two registers, or a register indirect, possibly with an
1741 auto-increment. For DFmode and DImode with a constant plus register,
1742 we must ensure that both words are addressable or PowerPC64 with offset
1745 For modes spanning multiple registers (DFmode in 32-bit GPRs,
1746 32-bit DImode, TImode), indexed addressing cannot be used because
1747 adjacent memory cells are accessed by adding word-sized offsets
1748 during assembly output. */
1750 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1751 { if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \
1755 /* Try machine-dependent ways of modifying an illegitimate address
1756 to be legitimate. If we find one, return the new, valid address.
1757 This macro is used in only one place: `memory_address' in explow.c.
1759 OLDX is the address as it was before break_out_memory_refs was called.
1760 In some cases it is useful to look at this to decide what needs to be done.
1762 MODE and WIN are passed so that this macro can use
1763 GO_IF_LEGITIMATE_ADDRESS.
1765 It is always safe for this macro to do nothing. It exists to recognize
1766 opportunities to optimize the output.
1768 On RS/6000, first check for the sum of a register with a constant
1769 integer that is out of range. If so, generate code to add the
1770 constant with the low-order 16 bits masked to the register and force
1771 this result into another register (this can be done with `cau').
1772 Then generate an address of REG+(CONST&0xffff), allowing for the
1773 possibility of bit 16 being a one.
1775 Then check for the sum of a register and something not constant, try to
1776 load the other things into a register and return the sum. */
1778 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1779 { rtx result = rs6000_legitimize_address (X, OLDX, MODE); \
1780 if (result != NULL_RTX) \
1787 /* Try a machine-dependent way of reloading an illegitimate address
1788 operand. If we find one, push the reload and jump to WIN. This
1789 macro is used in only one place: `find_reloads_address' in reload.c.
1791 Implemented on rs6000 by rs6000_legitimize_reload_address.
1792 Note that (X) is evaluated twice; this is safe in current usage. */
1794 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1797 (X) = rs6000_legitimize_reload_address ((X), (MODE), (OPNUM), \
1798 (int)(TYPE), (IND_LEVELS), &win); \
1803 /* Go to LABEL if ADDR (a legitimate address expression)
1804 has an effect that depends on the machine mode it is used for. */
1806 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1808 if (rs6000_mode_dependent_address (ADDR)) \
1812 /* The register number of the register used to address a table of
1813 static data addresses in memory. In some cases this register is
1814 defined by a processor's "application binary interface" (ABI).
1815 When this macro is defined, RTL is generated for this register
1816 once, as with the stack pointer and frame pointer registers. If
1817 this macro is not defined, it is up to the machine-dependent files
1818 to allocate such a register (if necessary). */
1820 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
1821 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
1823 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
1825 /* Define this macro if the register defined by
1826 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
1827 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
1829 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
1831 /* A C expression that is nonzero if X is a legitimate immediate
1832 operand on the target machine when generating position independent
1833 code. You can assume that X satisfies `CONSTANT_P', so you need
1834 not check this. You can also assume FLAG_PIC is true, so you need
1835 not check it either. You need not define this macro if all
1836 constants (including `SYMBOL_REF') can be immediate operands when
1837 generating position independent code. */
1839 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
1841 /* Define this if some processing needs to be done immediately before
1842 emitting code for an insn. */
1844 /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
1846 /* Specify the machine mode that this machine uses
1847 for the index in the tablejump instruction. */
1848 #define CASE_VECTOR_MODE SImode
1850 /* Define as C expression which evaluates to nonzero if the tablejump
1851 instruction expects the table to contain offsets from the address of the
1853 Do not define this if the table should contain absolute addresses. */
1854 #define CASE_VECTOR_PC_RELATIVE 1
1856 /* Define this as 1 if `char' should by default be signed; else as 0. */
1857 #define DEFAULT_SIGNED_CHAR 0
1859 /* This flag, if defined, says the same insns that convert to a signed fixnum
1860 also convert validly to an unsigned one. */
1862 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
1864 /* An integer expression for the size in bits of the largest integer machine
1865 mode that should actually be used. */
1867 /* Allow pairs of registers to be used, which is the intent of the default. */
1868 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
1870 /* Max number of bytes we can move from memory to memory
1871 in one reasonably fast instruction. */
1872 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
1873 #define MAX_MOVE_MAX 8
1875 /* Nonzero if access to memory by bytes is no faster than for words.
1876 Also nonzero if doing byte operations (specifically shifts) in registers
1878 #define SLOW_BYTE_ACCESS 1
1880 /* Define if operations between registers always perform the operation
1881 on the full register even if a narrower mode is specified. */
1882 #define WORD_REGISTER_OPERATIONS
1884 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1885 will either zero-extend or sign-extend. The value of this macro should
1886 be the code that says which one of the two operations is implicitly
1887 done, UNKNOWN if none. */
1888 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1890 /* Define if loading short immediate values into registers sign extends. */
1891 #define SHORT_IMMEDIATES_SIGN_EXTEND
1893 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1894 is done just by pretending it is already truncated. */
1895 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1897 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
1898 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1899 ((VALUE) = ((MODE) == SImode ? 32 : 64))
1901 /* The CTZ patterns return -1 for input of zero. */
1902 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1)
1904 /* Specify the machine mode that pointers have.
1905 After generation of rtl, the compiler makes no further distinction
1906 between pointers and any other objects of this machine mode. */
1907 #define Pmode (TARGET_32BIT ? SImode : DImode)
1909 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
1910 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
1912 /* Mode of a function address in a call instruction (for indexing purposes).
1913 Doesn't matter on RS/6000. */
1914 #define FUNCTION_MODE SImode
1916 /* Define this if addresses of constant functions
1917 shouldn't be put through pseudo regs where they can be cse'd.
1918 Desirable on machines where ordinary constants are expensive
1919 but a CALL with constant address is cheap. */
1920 #define NO_FUNCTION_CSE
1922 /* Define this to be nonzero if shift instructions ignore all but the low-order
1925 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
1926 have been dropped from the PowerPC architecture. */
1928 #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
1930 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
1931 should be adjusted to reflect any required changes. This macro is used when
1932 there is some systematic length adjustment required that would be difficult
1933 to express in the length attribute. */
1935 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
1937 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
1938 COMPARE, return the mode to be used for the comparison. For
1939 floating-point, CCFPmode should be used. CCUNSmode should be used
1940 for unsigned comparisons. CCEQmode should be used when we are
1941 doing an inequality comparison on the result of a
1942 comparison. CCmode should be used in all other cases. */
1944 #define SELECT_CC_MODE(OP,X,Y) \
1945 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode \
1946 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
1947 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
1948 ? CCEQmode : CCmode))
1950 /* Can the condition code MODE be safely reversed? This is safe in
1951 all cases on this port, because at present it doesn't use the
1952 trapping FP comparisons (fcmpo). */
1953 #define REVERSIBLE_CC_MODE(MODE) 1
1955 /* Given a condition code and a mode, return the inverse condition. */
1956 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
1958 /* Define the information needed to generate branch and scc insns. This is
1959 stored from the compare operation. */
1961 extern GTY(()) rtx rs6000_compare_op0
;
1962 extern GTY(()) rtx rs6000_compare_op1
;
1963 extern int rs6000_compare_fp_p
;
1965 /* Control the assembler format that we output. */
1967 /* A C string constant describing how to begin a comment in the target
1968 assembler language. The compiler assumes that the comment will end at
1969 the end of the line. */
1970 #define ASM_COMMENT_START " #"
1972 /* Flag to say the TOC is initialized */
1973 extern int toc_initialized
;
1975 /* Macro to output a special constant pool entry. Go to WIN if we output
1976 it. Otherwise, it is written the usual way.
1978 On the RS/6000, toc entries are handled this way. */
1980 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
1981 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
1983 output_toc (FILE, X, LABELNO, MODE); \
1988 #ifdef HAVE_GAS_WEAK
1989 #define RS6000_WEAK 1
1991 #define RS6000_WEAK 0
1995 /* Used in lieu of ASM_WEAKEN_LABEL. */
1996 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
1999 fputs ("\t.weak\t", (FILE)); \
2000 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2001 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2002 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2005 fputs ("[DS]", (FILE)); \
2006 fputs ("\n\t.weak\t.", (FILE)); \
2007 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2009 fputc ('\n', (FILE)); \
2012 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \
2013 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2014 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2016 fputs ("\t.set\t.", (FILE)); \
2017 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2018 fputs (",.", (FILE)); \
2019 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \
2020 fputc ('\n', (FILE)); \
2027 /* This implements the `alias' attribute. */
2028 #undef ASM_OUTPUT_DEF_FROM_DECLS
2029 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
2032 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
2033 const char *name = IDENTIFIER_POINTER (TARGET); \
2034 if (TREE_CODE (DECL) == FUNCTION_DECL \
2035 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2037 if (TREE_PUBLIC (DECL)) \
2039 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2041 fputs ("\t.globl\t.", FILE); \
2042 RS6000_OUTPUT_BASENAME (FILE, alias); \
2043 putc ('\n', FILE); \
2046 else if (TARGET_XCOFF) \
2048 fputs ("\t.lglobl\t.", FILE); \
2049 RS6000_OUTPUT_BASENAME (FILE, alias); \
2050 putc ('\n', FILE); \
2052 fputs ("\t.set\t.", FILE); \
2053 RS6000_OUTPUT_BASENAME (FILE, alias); \
2054 fputs (",.", FILE); \
2055 RS6000_OUTPUT_BASENAME (FILE, name); \
2056 fputc ('\n', FILE); \
2058 ASM_OUTPUT_DEF (FILE, alias, name); \
2062 #define TARGET_ASM_FILE_START rs6000_file_start
2064 /* Output to assembler file text saying following lines
2065 may contain character constants, extra white space, comments, etc. */
2067 #define ASM_APP_ON ""
2069 /* Output to assembler file text saying following lines
2070 no longer contain unusual constructs. */
2072 #define ASM_APP_OFF ""
2074 /* How to refer to registers in assembler output.
2075 This sequence is indexed by compiler's hard-register-number (see above). */
2077 extern char rs6000_reg_names
[][8]; /* register names (0 vs. %r0). */
2079 #define REGISTER_NAMES \
2081 &rs6000_reg_names[ 0][0], /* r0 */ \
2082 &rs6000_reg_names[ 1][0], /* r1 */ \
2083 &rs6000_reg_names[ 2][0], /* r2 */ \
2084 &rs6000_reg_names[ 3][0], /* r3 */ \
2085 &rs6000_reg_names[ 4][0], /* r4 */ \
2086 &rs6000_reg_names[ 5][0], /* r5 */ \
2087 &rs6000_reg_names[ 6][0], /* r6 */ \
2088 &rs6000_reg_names[ 7][0], /* r7 */ \
2089 &rs6000_reg_names[ 8][0], /* r8 */ \
2090 &rs6000_reg_names[ 9][0], /* r9 */ \
2091 &rs6000_reg_names[10][0], /* r10 */ \
2092 &rs6000_reg_names[11][0], /* r11 */ \
2093 &rs6000_reg_names[12][0], /* r12 */ \
2094 &rs6000_reg_names[13][0], /* r13 */ \
2095 &rs6000_reg_names[14][0], /* r14 */ \
2096 &rs6000_reg_names[15][0], /* r15 */ \
2097 &rs6000_reg_names[16][0], /* r16 */ \
2098 &rs6000_reg_names[17][0], /* r17 */ \
2099 &rs6000_reg_names[18][0], /* r18 */ \
2100 &rs6000_reg_names[19][0], /* r19 */ \
2101 &rs6000_reg_names[20][0], /* r20 */ \
2102 &rs6000_reg_names[21][0], /* r21 */ \
2103 &rs6000_reg_names[22][0], /* r22 */ \
2104 &rs6000_reg_names[23][0], /* r23 */ \
2105 &rs6000_reg_names[24][0], /* r24 */ \
2106 &rs6000_reg_names[25][0], /* r25 */ \
2107 &rs6000_reg_names[26][0], /* r26 */ \
2108 &rs6000_reg_names[27][0], /* r27 */ \
2109 &rs6000_reg_names[28][0], /* r28 */ \
2110 &rs6000_reg_names[29][0], /* r29 */ \
2111 &rs6000_reg_names[30][0], /* r30 */ \
2112 &rs6000_reg_names[31][0], /* r31 */ \
2114 &rs6000_reg_names[32][0], /* fr0 */ \
2115 &rs6000_reg_names[33][0], /* fr1 */ \
2116 &rs6000_reg_names[34][0], /* fr2 */ \
2117 &rs6000_reg_names[35][0], /* fr3 */ \
2118 &rs6000_reg_names[36][0], /* fr4 */ \
2119 &rs6000_reg_names[37][0], /* fr5 */ \
2120 &rs6000_reg_names[38][0], /* fr6 */ \
2121 &rs6000_reg_names[39][0], /* fr7 */ \
2122 &rs6000_reg_names[40][0], /* fr8 */ \
2123 &rs6000_reg_names[41][0], /* fr9 */ \
2124 &rs6000_reg_names[42][0], /* fr10 */ \
2125 &rs6000_reg_names[43][0], /* fr11 */ \
2126 &rs6000_reg_names[44][0], /* fr12 */ \
2127 &rs6000_reg_names[45][0], /* fr13 */ \
2128 &rs6000_reg_names[46][0], /* fr14 */ \
2129 &rs6000_reg_names[47][0], /* fr15 */ \
2130 &rs6000_reg_names[48][0], /* fr16 */ \
2131 &rs6000_reg_names[49][0], /* fr17 */ \
2132 &rs6000_reg_names[50][0], /* fr18 */ \
2133 &rs6000_reg_names[51][0], /* fr19 */ \
2134 &rs6000_reg_names[52][0], /* fr20 */ \
2135 &rs6000_reg_names[53][0], /* fr21 */ \
2136 &rs6000_reg_names[54][0], /* fr22 */ \
2137 &rs6000_reg_names[55][0], /* fr23 */ \
2138 &rs6000_reg_names[56][0], /* fr24 */ \
2139 &rs6000_reg_names[57][0], /* fr25 */ \
2140 &rs6000_reg_names[58][0], /* fr26 */ \
2141 &rs6000_reg_names[59][0], /* fr27 */ \
2142 &rs6000_reg_names[60][0], /* fr28 */ \
2143 &rs6000_reg_names[61][0], /* fr29 */ \
2144 &rs6000_reg_names[62][0], /* fr30 */ \
2145 &rs6000_reg_names[63][0], /* fr31 */ \
2147 &rs6000_reg_names[64][0], /* mq */ \
2148 &rs6000_reg_names[65][0], /* lr */ \
2149 &rs6000_reg_names[66][0], /* ctr */ \
2150 &rs6000_reg_names[67][0], /* ap */ \
2152 &rs6000_reg_names[68][0], /* cr0 */ \
2153 &rs6000_reg_names[69][0], /* cr1 */ \
2154 &rs6000_reg_names[70][0], /* cr2 */ \
2155 &rs6000_reg_names[71][0], /* cr3 */ \
2156 &rs6000_reg_names[72][0], /* cr4 */ \
2157 &rs6000_reg_names[73][0], /* cr5 */ \
2158 &rs6000_reg_names[74][0], /* cr6 */ \
2159 &rs6000_reg_names[75][0], /* cr7 */ \
2161 &rs6000_reg_names[76][0], /* xer */ \
2163 &rs6000_reg_names[77][0], /* v0 */ \
2164 &rs6000_reg_names[78][0], /* v1 */ \
2165 &rs6000_reg_names[79][0], /* v2 */ \
2166 &rs6000_reg_names[80][0], /* v3 */ \
2167 &rs6000_reg_names[81][0], /* v4 */ \
2168 &rs6000_reg_names[82][0], /* v5 */ \
2169 &rs6000_reg_names[83][0], /* v6 */ \
2170 &rs6000_reg_names[84][0], /* v7 */ \
2171 &rs6000_reg_names[85][0], /* v8 */ \
2172 &rs6000_reg_names[86][0], /* v9 */ \
2173 &rs6000_reg_names[87][0], /* v10 */ \
2174 &rs6000_reg_names[88][0], /* v11 */ \
2175 &rs6000_reg_names[89][0], /* v12 */ \
2176 &rs6000_reg_names[90][0], /* v13 */ \
2177 &rs6000_reg_names[91][0], /* v14 */ \
2178 &rs6000_reg_names[92][0], /* v15 */ \
2179 &rs6000_reg_names[93][0], /* v16 */ \
2180 &rs6000_reg_names[94][0], /* v17 */ \
2181 &rs6000_reg_names[95][0], /* v18 */ \
2182 &rs6000_reg_names[96][0], /* v19 */ \
2183 &rs6000_reg_names[97][0], /* v20 */ \
2184 &rs6000_reg_names[98][0], /* v21 */ \
2185 &rs6000_reg_names[99][0], /* v22 */ \
2186 &rs6000_reg_names[100][0], /* v23 */ \
2187 &rs6000_reg_names[101][0], /* v24 */ \
2188 &rs6000_reg_names[102][0], /* v25 */ \
2189 &rs6000_reg_names[103][0], /* v26 */ \
2190 &rs6000_reg_names[104][0], /* v27 */ \
2191 &rs6000_reg_names[105][0], /* v28 */ \
2192 &rs6000_reg_names[106][0], /* v29 */ \
2193 &rs6000_reg_names[107][0], /* v30 */ \
2194 &rs6000_reg_names[108][0], /* v31 */ \
2195 &rs6000_reg_names[109][0], /* vrsave */ \
2196 &rs6000_reg_names[110][0], /* vscr */ \
2197 &rs6000_reg_names[111][0], /* spe_acc */ \
2198 &rs6000_reg_names[112][0], /* spefscr */ \
2199 &rs6000_reg_names[113][0], /* sfp */ \
2202 /* Table of additional register names to use in user input. */
2204 #define ADDITIONAL_REGISTER_NAMES \
2205 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2206 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2207 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2208 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2209 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2210 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2211 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2212 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2213 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2214 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2215 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2216 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2217 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2218 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2219 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2220 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2221 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2222 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2223 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2224 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2225 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2226 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2227 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2228 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2229 {"vrsave", 109}, {"vscr", 110}, \
2230 {"spe_acc", 111}, {"spefscr", 112}, \
2231 /* no additional names for: mq, lr, ctr, ap */ \
2232 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2233 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2234 {"cc", 68}, {"sp", 1}, {"toc", 2} }
2236 /* Text to write out after a CALL that may be replaced by glue code by
2237 the loader. This depends on the AIX version. */
2238 #define RS6000_CALL_GLUE "cror 31,31,31"
2240 /* This is how to output an element of a case-vector that is relative. */
2242 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2243 do { char buf[100]; \
2244 fputs ("\t.long ", FILE); \
2245 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2246 assemble_name (FILE, buf); \
2248 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2249 assemble_name (FILE, buf); \
2250 putc ('\n', FILE); \
2253 /* This is how to output an assembler line
2254 that says to advance the location counter
2255 to a multiple of 2**LOG bytes. */
2257 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2259 fprintf (FILE, "\t.align %d\n", (LOG))
2261 /* Pick up the return address upon entry to a procedure. Used for
2262 dwarf2 unwind information. This also enables the table driven
2265 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
2266 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM)
2268 /* Describe how we implement __builtin_eh_return. */
2269 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2270 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2272 /* Print operand X (an rtx) in assembler syntax to file FILE.
2273 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2274 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2276 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2278 /* Define which CODE values are valid. */
2280 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2281 ((CODE) == '.' || (CODE) == '&')
2283 /* Print a memory address as an operand to reference that memory location. */
2285 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2287 /* uncomment for disabling the corresponding default options */
2288 /* #define MACHINE_no_sched_interblock */
2289 /* #define MACHINE_no_sched_speculative */
2290 /* #define MACHINE_no_sched_speculative_load */
2292 /* General flags. */
2293 extern int flag_pic
;
2294 extern int optimize
;
2295 extern int flag_expensive_optimizations
;
2296 extern int frame_pointer_needed
;
2298 enum rs6000_builtins
2300 /* AltiVec builtins. */
2301 ALTIVEC_BUILTIN_ST_INTERNAL_4si
,
2302 ALTIVEC_BUILTIN_LD_INTERNAL_4si
,
2303 ALTIVEC_BUILTIN_ST_INTERNAL_8hi
,
2304 ALTIVEC_BUILTIN_LD_INTERNAL_8hi
,
2305 ALTIVEC_BUILTIN_ST_INTERNAL_16qi
,
2306 ALTIVEC_BUILTIN_LD_INTERNAL_16qi
,
2307 ALTIVEC_BUILTIN_ST_INTERNAL_4sf
,
2308 ALTIVEC_BUILTIN_LD_INTERNAL_4sf
,
2309 ALTIVEC_BUILTIN_VADDUBM
,
2310 ALTIVEC_BUILTIN_VADDUHM
,
2311 ALTIVEC_BUILTIN_VADDUWM
,
2312 ALTIVEC_BUILTIN_VADDFP
,
2313 ALTIVEC_BUILTIN_VADDCUW
,
2314 ALTIVEC_BUILTIN_VADDUBS
,
2315 ALTIVEC_BUILTIN_VADDSBS
,
2316 ALTIVEC_BUILTIN_VADDUHS
,
2317 ALTIVEC_BUILTIN_VADDSHS
,
2318 ALTIVEC_BUILTIN_VADDUWS
,
2319 ALTIVEC_BUILTIN_VADDSWS
,
2320 ALTIVEC_BUILTIN_VAND
,
2321 ALTIVEC_BUILTIN_VANDC
,
2322 ALTIVEC_BUILTIN_VAVGUB
,
2323 ALTIVEC_BUILTIN_VAVGSB
,
2324 ALTIVEC_BUILTIN_VAVGUH
,
2325 ALTIVEC_BUILTIN_VAVGSH
,
2326 ALTIVEC_BUILTIN_VAVGUW
,
2327 ALTIVEC_BUILTIN_VAVGSW
,
2328 ALTIVEC_BUILTIN_VCFUX
,
2329 ALTIVEC_BUILTIN_VCFSX
,
2330 ALTIVEC_BUILTIN_VCTSXS
,
2331 ALTIVEC_BUILTIN_VCTUXS
,
2332 ALTIVEC_BUILTIN_VCMPBFP
,
2333 ALTIVEC_BUILTIN_VCMPEQUB
,
2334 ALTIVEC_BUILTIN_VCMPEQUH
,
2335 ALTIVEC_BUILTIN_VCMPEQUW
,
2336 ALTIVEC_BUILTIN_VCMPEQFP
,
2337 ALTIVEC_BUILTIN_VCMPGEFP
,
2338 ALTIVEC_BUILTIN_VCMPGTUB
,
2339 ALTIVEC_BUILTIN_VCMPGTSB
,
2340 ALTIVEC_BUILTIN_VCMPGTUH
,
2341 ALTIVEC_BUILTIN_VCMPGTSH
,
2342 ALTIVEC_BUILTIN_VCMPGTUW
,
2343 ALTIVEC_BUILTIN_VCMPGTSW
,
2344 ALTIVEC_BUILTIN_VCMPGTFP
,
2345 ALTIVEC_BUILTIN_VEXPTEFP
,
2346 ALTIVEC_BUILTIN_VLOGEFP
,
2347 ALTIVEC_BUILTIN_VMADDFP
,
2348 ALTIVEC_BUILTIN_VMAXUB
,
2349 ALTIVEC_BUILTIN_VMAXSB
,
2350 ALTIVEC_BUILTIN_VMAXUH
,
2351 ALTIVEC_BUILTIN_VMAXSH
,
2352 ALTIVEC_BUILTIN_VMAXUW
,
2353 ALTIVEC_BUILTIN_VMAXSW
,
2354 ALTIVEC_BUILTIN_VMAXFP
,
2355 ALTIVEC_BUILTIN_VMHADDSHS
,
2356 ALTIVEC_BUILTIN_VMHRADDSHS
,
2357 ALTIVEC_BUILTIN_VMLADDUHM
,
2358 ALTIVEC_BUILTIN_VMRGHB
,
2359 ALTIVEC_BUILTIN_VMRGHH
,
2360 ALTIVEC_BUILTIN_VMRGHW
,
2361 ALTIVEC_BUILTIN_VMRGLB
,
2362 ALTIVEC_BUILTIN_VMRGLH
,
2363 ALTIVEC_BUILTIN_VMRGLW
,
2364 ALTIVEC_BUILTIN_VMSUMUBM
,
2365 ALTIVEC_BUILTIN_VMSUMMBM
,
2366 ALTIVEC_BUILTIN_VMSUMUHM
,
2367 ALTIVEC_BUILTIN_VMSUMSHM
,
2368 ALTIVEC_BUILTIN_VMSUMUHS
,
2369 ALTIVEC_BUILTIN_VMSUMSHS
,
2370 ALTIVEC_BUILTIN_VMINUB
,
2371 ALTIVEC_BUILTIN_VMINSB
,
2372 ALTIVEC_BUILTIN_VMINUH
,
2373 ALTIVEC_BUILTIN_VMINSH
,
2374 ALTIVEC_BUILTIN_VMINUW
,
2375 ALTIVEC_BUILTIN_VMINSW
,
2376 ALTIVEC_BUILTIN_VMINFP
,
2377 ALTIVEC_BUILTIN_VMULEUB
,
2378 ALTIVEC_BUILTIN_VMULESB
,
2379 ALTIVEC_BUILTIN_VMULEUH
,
2380 ALTIVEC_BUILTIN_VMULESH
,
2381 ALTIVEC_BUILTIN_VMULOUB
,
2382 ALTIVEC_BUILTIN_VMULOSB
,
2383 ALTIVEC_BUILTIN_VMULOUH
,
2384 ALTIVEC_BUILTIN_VMULOSH
,
2385 ALTIVEC_BUILTIN_VNMSUBFP
,
2386 ALTIVEC_BUILTIN_VNOR
,
2387 ALTIVEC_BUILTIN_VOR
,
2388 ALTIVEC_BUILTIN_VSEL_4SI
,
2389 ALTIVEC_BUILTIN_VSEL_4SF
,
2390 ALTIVEC_BUILTIN_VSEL_8HI
,
2391 ALTIVEC_BUILTIN_VSEL_16QI
,
2392 ALTIVEC_BUILTIN_VPERM_4SI
,
2393 ALTIVEC_BUILTIN_VPERM_4SF
,
2394 ALTIVEC_BUILTIN_VPERM_8HI
,
2395 ALTIVEC_BUILTIN_VPERM_16QI
,
2396 ALTIVEC_BUILTIN_VPKUHUM
,
2397 ALTIVEC_BUILTIN_VPKUWUM
,
2398 ALTIVEC_BUILTIN_VPKPX
,
2399 ALTIVEC_BUILTIN_VPKUHSS
,
2400 ALTIVEC_BUILTIN_VPKSHSS
,
2401 ALTIVEC_BUILTIN_VPKUWSS
,
2402 ALTIVEC_BUILTIN_VPKSWSS
,
2403 ALTIVEC_BUILTIN_VPKUHUS
,
2404 ALTIVEC_BUILTIN_VPKSHUS
,
2405 ALTIVEC_BUILTIN_VPKUWUS
,
2406 ALTIVEC_BUILTIN_VPKSWUS
,
2407 ALTIVEC_BUILTIN_VREFP
,
2408 ALTIVEC_BUILTIN_VRFIM
,
2409 ALTIVEC_BUILTIN_VRFIN
,
2410 ALTIVEC_BUILTIN_VRFIP
,
2411 ALTIVEC_BUILTIN_VRFIZ
,
2412 ALTIVEC_BUILTIN_VRLB
,
2413 ALTIVEC_BUILTIN_VRLH
,
2414 ALTIVEC_BUILTIN_VRLW
,
2415 ALTIVEC_BUILTIN_VRSQRTEFP
,
2416 ALTIVEC_BUILTIN_VSLB
,
2417 ALTIVEC_BUILTIN_VSLH
,
2418 ALTIVEC_BUILTIN_VSLW
,
2419 ALTIVEC_BUILTIN_VSL
,
2420 ALTIVEC_BUILTIN_VSLO
,
2421 ALTIVEC_BUILTIN_VSPLTB
,
2422 ALTIVEC_BUILTIN_VSPLTH
,
2423 ALTIVEC_BUILTIN_VSPLTW
,
2424 ALTIVEC_BUILTIN_VSPLTISB
,
2425 ALTIVEC_BUILTIN_VSPLTISH
,
2426 ALTIVEC_BUILTIN_VSPLTISW
,
2427 ALTIVEC_BUILTIN_VSRB
,
2428 ALTIVEC_BUILTIN_VSRH
,
2429 ALTIVEC_BUILTIN_VSRW
,
2430 ALTIVEC_BUILTIN_VSRAB
,
2431 ALTIVEC_BUILTIN_VSRAH
,
2432 ALTIVEC_BUILTIN_VSRAW
,
2433 ALTIVEC_BUILTIN_VSR
,
2434 ALTIVEC_BUILTIN_VSRO
,
2435 ALTIVEC_BUILTIN_VSUBUBM
,
2436 ALTIVEC_BUILTIN_VSUBUHM
,
2437 ALTIVEC_BUILTIN_VSUBUWM
,
2438 ALTIVEC_BUILTIN_VSUBFP
,
2439 ALTIVEC_BUILTIN_VSUBCUW
,
2440 ALTIVEC_BUILTIN_VSUBUBS
,
2441 ALTIVEC_BUILTIN_VSUBSBS
,
2442 ALTIVEC_BUILTIN_VSUBUHS
,
2443 ALTIVEC_BUILTIN_VSUBSHS
,
2444 ALTIVEC_BUILTIN_VSUBUWS
,
2445 ALTIVEC_BUILTIN_VSUBSWS
,
2446 ALTIVEC_BUILTIN_VSUM4UBS
,
2447 ALTIVEC_BUILTIN_VSUM4SBS
,
2448 ALTIVEC_BUILTIN_VSUM4SHS
,
2449 ALTIVEC_BUILTIN_VSUM2SWS
,
2450 ALTIVEC_BUILTIN_VSUMSWS
,
2451 ALTIVEC_BUILTIN_VXOR
,
2452 ALTIVEC_BUILTIN_VSLDOI_16QI
,
2453 ALTIVEC_BUILTIN_VSLDOI_8HI
,
2454 ALTIVEC_BUILTIN_VSLDOI_4SI
,
2455 ALTIVEC_BUILTIN_VSLDOI_4SF
,
2456 ALTIVEC_BUILTIN_VUPKHSB
,
2457 ALTIVEC_BUILTIN_VUPKHPX
,
2458 ALTIVEC_BUILTIN_VUPKHSH
,
2459 ALTIVEC_BUILTIN_VUPKLSB
,
2460 ALTIVEC_BUILTIN_VUPKLPX
,
2461 ALTIVEC_BUILTIN_VUPKLSH
,
2462 ALTIVEC_BUILTIN_MTVSCR
,
2463 ALTIVEC_BUILTIN_MFVSCR
,
2464 ALTIVEC_BUILTIN_DSSALL
,
2465 ALTIVEC_BUILTIN_DSS
,
2466 ALTIVEC_BUILTIN_LVSL
,
2467 ALTIVEC_BUILTIN_LVSR
,
2468 ALTIVEC_BUILTIN_DSTT
,
2469 ALTIVEC_BUILTIN_DSTST
,
2470 ALTIVEC_BUILTIN_DSTSTT
,
2471 ALTIVEC_BUILTIN_DST
,
2472 ALTIVEC_BUILTIN_LVEBX
,
2473 ALTIVEC_BUILTIN_LVEHX
,
2474 ALTIVEC_BUILTIN_LVEWX
,
2475 ALTIVEC_BUILTIN_LVXL
,
2476 ALTIVEC_BUILTIN_LVX
,
2477 ALTIVEC_BUILTIN_STVX
,
2478 ALTIVEC_BUILTIN_STVEBX
,
2479 ALTIVEC_BUILTIN_STVEHX
,
2480 ALTIVEC_BUILTIN_STVEWX
,
2481 ALTIVEC_BUILTIN_STVXL
,
2482 ALTIVEC_BUILTIN_VCMPBFP_P
,
2483 ALTIVEC_BUILTIN_VCMPEQFP_P
,
2484 ALTIVEC_BUILTIN_VCMPEQUB_P
,
2485 ALTIVEC_BUILTIN_VCMPEQUH_P
,
2486 ALTIVEC_BUILTIN_VCMPEQUW_P
,
2487 ALTIVEC_BUILTIN_VCMPGEFP_P
,
2488 ALTIVEC_BUILTIN_VCMPGTFP_P
,
2489 ALTIVEC_BUILTIN_VCMPGTSB_P
,
2490 ALTIVEC_BUILTIN_VCMPGTSH_P
,
2491 ALTIVEC_BUILTIN_VCMPGTSW_P
,
2492 ALTIVEC_BUILTIN_VCMPGTUB_P
,
2493 ALTIVEC_BUILTIN_VCMPGTUH_P
,
2494 ALTIVEC_BUILTIN_VCMPGTUW_P
,
2495 ALTIVEC_BUILTIN_ABSS_V4SI
,
2496 ALTIVEC_BUILTIN_ABSS_V8HI
,
2497 ALTIVEC_BUILTIN_ABSS_V16QI
,
2498 ALTIVEC_BUILTIN_ABS_V4SI
,
2499 ALTIVEC_BUILTIN_ABS_V4SF
,
2500 ALTIVEC_BUILTIN_ABS_V8HI
,
2501 ALTIVEC_BUILTIN_ABS_V16QI
,
2502 ALTIVEC_BUILTIN_MASK_FOR_LOAD
,
2503 ALTIVEC_BUILTIN_MASK_FOR_STORE
,
2504 ALTIVEC_BUILTIN_VEC_INIT_V4SI
,
2505 ALTIVEC_BUILTIN_VEC_INIT_V8HI
,
2506 ALTIVEC_BUILTIN_VEC_INIT_V16QI
,
2507 ALTIVEC_BUILTIN_VEC_INIT_V4SF
,
2508 ALTIVEC_BUILTIN_VEC_SET_V4SI
,
2509 ALTIVEC_BUILTIN_VEC_SET_V8HI
,
2510 ALTIVEC_BUILTIN_VEC_SET_V16QI
,
2511 ALTIVEC_BUILTIN_VEC_SET_V4SF
,
2512 ALTIVEC_BUILTIN_VEC_EXT_V4SI
,
2513 ALTIVEC_BUILTIN_VEC_EXT_V8HI
,
2514 ALTIVEC_BUILTIN_VEC_EXT_V16QI
,
2515 ALTIVEC_BUILTIN_VEC_EXT_V4SF
,
2517 /* Altivec overloaded builtins. */
2518 ALTIVEC_BUILTIN_VCMPEQ_P
,
2519 ALTIVEC_BUILTIN_OVERLOADED_FIRST
= ALTIVEC_BUILTIN_VCMPEQ_P
,
2520 ALTIVEC_BUILTIN_VCMPGT_P
,
2521 ALTIVEC_BUILTIN_VCMPGE_P
,
2522 ALTIVEC_BUILTIN_VEC_ABS
,
2523 ALTIVEC_BUILTIN_VEC_ABSS
,
2524 ALTIVEC_BUILTIN_VEC_ADD
,
2525 ALTIVEC_BUILTIN_VEC_ADDC
,
2526 ALTIVEC_BUILTIN_VEC_ADDS
,
2527 ALTIVEC_BUILTIN_VEC_AND
,
2528 ALTIVEC_BUILTIN_VEC_ANDC
,
2529 ALTIVEC_BUILTIN_VEC_AVG
,
2530 ALTIVEC_BUILTIN_VEC_CEIL
,
2531 ALTIVEC_BUILTIN_VEC_CMPB
,
2532 ALTIVEC_BUILTIN_VEC_CMPEQ
,
2533 ALTIVEC_BUILTIN_VEC_CMPEQUB
,
2534 ALTIVEC_BUILTIN_VEC_CMPEQUH
,
2535 ALTIVEC_BUILTIN_VEC_CMPEQUW
,
2536 ALTIVEC_BUILTIN_VEC_CMPGE
,
2537 ALTIVEC_BUILTIN_VEC_CMPGT
,
2538 ALTIVEC_BUILTIN_VEC_CMPLE
,
2539 ALTIVEC_BUILTIN_VEC_CMPLT
,
2540 ALTIVEC_BUILTIN_VEC_CTF
,
2541 ALTIVEC_BUILTIN_VEC_CTS
,
2542 ALTIVEC_BUILTIN_VEC_CTU
,
2543 ALTIVEC_BUILTIN_VEC_DST
,
2544 ALTIVEC_BUILTIN_VEC_DSTST
,
2545 ALTIVEC_BUILTIN_VEC_DSTSTT
,
2546 ALTIVEC_BUILTIN_VEC_DSTT
,
2547 ALTIVEC_BUILTIN_VEC_EXPTE
,
2548 ALTIVEC_BUILTIN_VEC_FLOOR
,
2549 ALTIVEC_BUILTIN_VEC_LD
,
2550 ALTIVEC_BUILTIN_VEC_LDE
,
2551 ALTIVEC_BUILTIN_VEC_LDL
,
2552 ALTIVEC_BUILTIN_VEC_LOGE
,
2553 ALTIVEC_BUILTIN_VEC_LVEBX
,
2554 ALTIVEC_BUILTIN_VEC_LVEHX
,
2555 ALTIVEC_BUILTIN_VEC_LVEWX
,
2556 ALTIVEC_BUILTIN_VEC_LVSL
,
2557 ALTIVEC_BUILTIN_VEC_LVSR
,
2558 ALTIVEC_BUILTIN_VEC_MADD
,
2559 ALTIVEC_BUILTIN_VEC_MADDS
,
2560 ALTIVEC_BUILTIN_VEC_MAX
,
2561 ALTIVEC_BUILTIN_VEC_MERGEH
,
2562 ALTIVEC_BUILTIN_VEC_MERGEL
,
2563 ALTIVEC_BUILTIN_VEC_MIN
,
2564 ALTIVEC_BUILTIN_VEC_MLADD
,
2565 ALTIVEC_BUILTIN_VEC_MPERM
,
2566 ALTIVEC_BUILTIN_VEC_MRADDS
,
2567 ALTIVEC_BUILTIN_VEC_MRGHB
,
2568 ALTIVEC_BUILTIN_VEC_MRGHH
,
2569 ALTIVEC_BUILTIN_VEC_MRGHW
,
2570 ALTIVEC_BUILTIN_VEC_MRGLB
,
2571 ALTIVEC_BUILTIN_VEC_MRGLH
,
2572 ALTIVEC_BUILTIN_VEC_MRGLW
,
2573 ALTIVEC_BUILTIN_VEC_MSUM
,
2574 ALTIVEC_BUILTIN_VEC_MSUMS
,
2575 ALTIVEC_BUILTIN_VEC_MTVSCR
,
2576 ALTIVEC_BUILTIN_VEC_MULE
,
2577 ALTIVEC_BUILTIN_VEC_MULO
,
2578 ALTIVEC_BUILTIN_VEC_NMSUB
,
2579 ALTIVEC_BUILTIN_VEC_NOR
,
2580 ALTIVEC_BUILTIN_VEC_OR
,
2581 ALTIVEC_BUILTIN_VEC_PACK
,
2582 ALTIVEC_BUILTIN_VEC_PACKPX
,
2583 ALTIVEC_BUILTIN_VEC_PACKS
,
2584 ALTIVEC_BUILTIN_VEC_PACKSU
,
2585 ALTIVEC_BUILTIN_VEC_PERM
,
2586 ALTIVEC_BUILTIN_VEC_RE
,
2587 ALTIVEC_BUILTIN_VEC_RL
,
2588 ALTIVEC_BUILTIN_VEC_ROUND
,
2589 ALTIVEC_BUILTIN_VEC_RSQRTE
,
2590 ALTIVEC_BUILTIN_VEC_SEL
,
2591 ALTIVEC_BUILTIN_VEC_SL
,
2592 ALTIVEC_BUILTIN_VEC_SLD
,
2593 ALTIVEC_BUILTIN_VEC_SLL
,
2594 ALTIVEC_BUILTIN_VEC_SLO
,
2595 ALTIVEC_BUILTIN_VEC_SPLAT
,
2596 ALTIVEC_BUILTIN_VEC_SPLAT_S16
,
2597 ALTIVEC_BUILTIN_VEC_SPLAT_S32
,
2598 ALTIVEC_BUILTIN_VEC_SPLAT_S8
,
2599 ALTIVEC_BUILTIN_VEC_SPLAT_U16
,
2600 ALTIVEC_BUILTIN_VEC_SPLAT_U32
,
2601 ALTIVEC_BUILTIN_VEC_SPLAT_U8
,
2602 ALTIVEC_BUILTIN_VEC_SPLTB
,
2603 ALTIVEC_BUILTIN_VEC_SPLTH
,
2604 ALTIVEC_BUILTIN_VEC_SPLTW
,
2605 ALTIVEC_BUILTIN_VEC_SR
,
2606 ALTIVEC_BUILTIN_VEC_SRA
,
2607 ALTIVEC_BUILTIN_VEC_SRL
,
2608 ALTIVEC_BUILTIN_VEC_SRO
,
2609 ALTIVEC_BUILTIN_VEC_ST
,
2610 ALTIVEC_BUILTIN_VEC_STE
,
2611 ALTIVEC_BUILTIN_VEC_STL
,
2612 ALTIVEC_BUILTIN_VEC_STVEBX
,
2613 ALTIVEC_BUILTIN_VEC_STVEHX
,
2614 ALTIVEC_BUILTIN_VEC_STVEWX
,
2615 ALTIVEC_BUILTIN_VEC_SUB
,
2616 ALTIVEC_BUILTIN_VEC_SUBC
,
2617 ALTIVEC_BUILTIN_VEC_SUBS
,
2618 ALTIVEC_BUILTIN_VEC_SUM2S
,
2619 ALTIVEC_BUILTIN_VEC_SUM4S
,
2620 ALTIVEC_BUILTIN_VEC_SUMS
,
2621 ALTIVEC_BUILTIN_VEC_TRUNC
,
2622 ALTIVEC_BUILTIN_VEC_UNPACKH
,
2623 ALTIVEC_BUILTIN_VEC_UNPACKL
,
2624 ALTIVEC_BUILTIN_VEC_VADDFP
,
2625 ALTIVEC_BUILTIN_VEC_VADDSBS
,
2626 ALTIVEC_BUILTIN_VEC_VADDSHS
,
2627 ALTIVEC_BUILTIN_VEC_VADDSWS
,
2628 ALTIVEC_BUILTIN_VEC_VADDUBM
,
2629 ALTIVEC_BUILTIN_VEC_VADDUBS
,
2630 ALTIVEC_BUILTIN_VEC_VADDUHM
,
2631 ALTIVEC_BUILTIN_VEC_VADDUHS
,
2632 ALTIVEC_BUILTIN_VEC_VADDUWM
,
2633 ALTIVEC_BUILTIN_VEC_VADDUWS
,
2634 ALTIVEC_BUILTIN_VEC_VAVGSB
,
2635 ALTIVEC_BUILTIN_VEC_VAVGSH
,
2636 ALTIVEC_BUILTIN_VEC_VAVGSW
,
2637 ALTIVEC_BUILTIN_VEC_VAVGUB
,
2638 ALTIVEC_BUILTIN_VEC_VAVGUH
,
2639 ALTIVEC_BUILTIN_VEC_VAVGUW
,
2640 ALTIVEC_BUILTIN_VEC_VCFSX
,
2641 ALTIVEC_BUILTIN_VEC_VCFUX
,
2642 ALTIVEC_BUILTIN_VEC_VCMPEQFP
,
2643 ALTIVEC_BUILTIN_VEC_VCMPEQUB
,
2644 ALTIVEC_BUILTIN_VEC_VCMPEQUH
,
2645 ALTIVEC_BUILTIN_VEC_VCMPEQUW
,
2646 ALTIVEC_BUILTIN_VEC_VCMPGTFP
,
2647 ALTIVEC_BUILTIN_VEC_VCMPGTSB
,
2648 ALTIVEC_BUILTIN_VEC_VCMPGTSH
,
2649 ALTIVEC_BUILTIN_VEC_VCMPGTSW
,
2650 ALTIVEC_BUILTIN_VEC_VCMPGTUB
,
2651 ALTIVEC_BUILTIN_VEC_VCMPGTUH
,
2652 ALTIVEC_BUILTIN_VEC_VCMPGTUW
,
2653 ALTIVEC_BUILTIN_VEC_VMAXFP
,
2654 ALTIVEC_BUILTIN_VEC_VMAXSB
,
2655 ALTIVEC_BUILTIN_VEC_VMAXSH
,
2656 ALTIVEC_BUILTIN_VEC_VMAXSW
,
2657 ALTIVEC_BUILTIN_VEC_VMAXUB
,
2658 ALTIVEC_BUILTIN_VEC_VMAXUH
,
2659 ALTIVEC_BUILTIN_VEC_VMAXUW
,
2660 ALTIVEC_BUILTIN_VEC_VMINFP
,
2661 ALTIVEC_BUILTIN_VEC_VMINSB
,
2662 ALTIVEC_BUILTIN_VEC_VMINSH
,
2663 ALTIVEC_BUILTIN_VEC_VMINSW
,
2664 ALTIVEC_BUILTIN_VEC_VMINUB
,
2665 ALTIVEC_BUILTIN_VEC_VMINUH
,
2666 ALTIVEC_BUILTIN_VEC_VMINUW
,
2667 ALTIVEC_BUILTIN_VEC_VMRGHB
,
2668 ALTIVEC_BUILTIN_VEC_VMRGHH
,
2669 ALTIVEC_BUILTIN_VEC_VMRGHW
,
2670 ALTIVEC_BUILTIN_VEC_VMRGLB
,
2671 ALTIVEC_BUILTIN_VEC_VMRGLH
,
2672 ALTIVEC_BUILTIN_VEC_VMRGLW
,
2673 ALTIVEC_BUILTIN_VEC_VMSUMMBM
,
2674 ALTIVEC_BUILTIN_VEC_VMSUMSHM
,
2675 ALTIVEC_BUILTIN_VEC_VMSUMSHS
,
2676 ALTIVEC_BUILTIN_VEC_VMSUMUBM
,
2677 ALTIVEC_BUILTIN_VEC_VMSUMUHM
,
2678 ALTIVEC_BUILTIN_VEC_VMSUMUHS
,
2679 ALTIVEC_BUILTIN_VEC_VMULESB
,
2680 ALTIVEC_BUILTIN_VEC_VMULESH
,
2681 ALTIVEC_BUILTIN_VEC_VMULEUB
,
2682 ALTIVEC_BUILTIN_VEC_VMULEUH
,
2683 ALTIVEC_BUILTIN_VEC_VMULOSB
,
2684 ALTIVEC_BUILTIN_VEC_VMULOSH
,
2685 ALTIVEC_BUILTIN_VEC_VMULOUB
,
2686 ALTIVEC_BUILTIN_VEC_VMULOUH
,
2687 ALTIVEC_BUILTIN_VEC_VPKSHSS
,
2688 ALTIVEC_BUILTIN_VEC_VPKSHUS
,
2689 ALTIVEC_BUILTIN_VEC_VPKSWSS
,
2690 ALTIVEC_BUILTIN_VEC_VPKSWUS
,
2691 ALTIVEC_BUILTIN_VEC_VPKUHUM
,
2692 ALTIVEC_BUILTIN_VEC_VPKUHUS
,
2693 ALTIVEC_BUILTIN_VEC_VPKUWUM
,
2694 ALTIVEC_BUILTIN_VEC_VPKUWUS
,
2695 ALTIVEC_BUILTIN_VEC_VRLB
,
2696 ALTIVEC_BUILTIN_VEC_VRLH
,
2697 ALTIVEC_BUILTIN_VEC_VRLW
,
2698 ALTIVEC_BUILTIN_VEC_VSLB
,
2699 ALTIVEC_BUILTIN_VEC_VSLH
,
2700 ALTIVEC_BUILTIN_VEC_VSLW
,
2701 ALTIVEC_BUILTIN_VEC_VSPLTB
,
2702 ALTIVEC_BUILTIN_VEC_VSPLTH
,
2703 ALTIVEC_BUILTIN_VEC_VSPLTW
,
2704 ALTIVEC_BUILTIN_VEC_VSRAB
,
2705 ALTIVEC_BUILTIN_VEC_VSRAH
,
2706 ALTIVEC_BUILTIN_VEC_VSRAW
,
2707 ALTIVEC_BUILTIN_VEC_VSRB
,
2708 ALTIVEC_BUILTIN_VEC_VSRH
,
2709 ALTIVEC_BUILTIN_VEC_VSRW
,
2710 ALTIVEC_BUILTIN_VEC_VSUBFP
,
2711 ALTIVEC_BUILTIN_VEC_VSUBSBS
,
2712 ALTIVEC_BUILTIN_VEC_VSUBSHS
,
2713 ALTIVEC_BUILTIN_VEC_VSUBSWS
,
2714 ALTIVEC_BUILTIN_VEC_VSUBUBM
,
2715 ALTIVEC_BUILTIN_VEC_VSUBUBS
,
2716 ALTIVEC_BUILTIN_VEC_VSUBUHM
,
2717 ALTIVEC_BUILTIN_VEC_VSUBUHS
,
2718 ALTIVEC_BUILTIN_VEC_VSUBUWM
,
2719 ALTIVEC_BUILTIN_VEC_VSUBUWS
,
2720 ALTIVEC_BUILTIN_VEC_VSUM4SBS
,
2721 ALTIVEC_BUILTIN_VEC_VSUM4SHS
,
2722 ALTIVEC_BUILTIN_VEC_VSUM4UBS
,
2723 ALTIVEC_BUILTIN_VEC_VUPKHPX
,
2724 ALTIVEC_BUILTIN_VEC_VUPKHSB
,
2725 ALTIVEC_BUILTIN_VEC_VUPKHSH
,
2726 ALTIVEC_BUILTIN_VEC_VUPKLPX
,
2727 ALTIVEC_BUILTIN_VEC_VUPKLSB
,
2728 ALTIVEC_BUILTIN_VEC_VUPKLSH
,
2729 ALTIVEC_BUILTIN_VEC_XOR
,
2730 ALTIVEC_BUILTIN_VEC_STEP
,
2731 ALTIVEC_BUILTIN_OVERLOADED_LAST
= ALTIVEC_BUILTIN_VEC_STEP
,
2737 SPE_BUILTIN_EVDIVWS
,
2738 SPE_BUILTIN_EVDIVWU
,
2740 SPE_BUILTIN_EVFSADD
,
2741 SPE_BUILTIN_EVFSDIV
,
2742 SPE_BUILTIN_EVFSMUL
,
2743 SPE_BUILTIN_EVFSSUB
,
2747 SPE_BUILTIN_EVLHHESPLATX
,
2748 SPE_BUILTIN_EVLHHOSSPLATX
,
2749 SPE_BUILTIN_EVLHHOUSPLATX
,
2750 SPE_BUILTIN_EVLWHEX
,
2751 SPE_BUILTIN_EVLWHOSX
,
2752 SPE_BUILTIN_EVLWHOUX
,
2753 SPE_BUILTIN_EVLWHSPLATX
,
2754 SPE_BUILTIN_EVLWWSPLATX
,
2755 SPE_BUILTIN_EVMERGEHI
,
2756 SPE_BUILTIN_EVMERGEHILO
,
2757 SPE_BUILTIN_EVMERGELO
,
2758 SPE_BUILTIN_EVMERGELOHI
,
2759 SPE_BUILTIN_EVMHEGSMFAA
,
2760 SPE_BUILTIN_EVMHEGSMFAN
,
2761 SPE_BUILTIN_EVMHEGSMIAA
,
2762 SPE_BUILTIN_EVMHEGSMIAN
,
2763 SPE_BUILTIN_EVMHEGUMIAA
,
2764 SPE_BUILTIN_EVMHEGUMIAN
,
2765 SPE_BUILTIN_EVMHESMF
,
2766 SPE_BUILTIN_EVMHESMFA
,
2767 SPE_BUILTIN_EVMHESMFAAW
,
2768 SPE_BUILTIN_EVMHESMFANW
,
2769 SPE_BUILTIN_EVMHESMI
,
2770 SPE_BUILTIN_EVMHESMIA
,
2771 SPE_BUILTIN_EVMHESMIAAW
,
2772 SPE_BUILTIN_EVMHESMIANW
,
2773 SPE_BUILTIN_EVMHESSF
,
2774 SPE_BUILTIN_EVMHESSFA
,
2775 SPE_BUILTIN_EVMHESSFAAW
,
2776 SPE_BUILTIN_EVMHESSFANW
,
2777 SPE_BUILTIN_EVMHESSIAAW
,
2778 SPE_BUILTIN_EVMHESSIANW
,
2779 SPE_BUILTIN_EVMHEUMI
,
2780 SPE_BUILTIN_EVMHEUMIA
,
2781 SPE_BUILTIN_EVMHEUMIAAW
,
2782 SPE_BUILTIN_EVMHEUMIANW
,
2783 SPE_BUILTIN_EVMHEUSIAAW
,
2784 SPE_BUILTIN_EVMHEUSIANW
,
2785 SPE_BUILTIN_EVMHOGSMFAA
,
2786 SPE_BUILTIN_EVMHOGSMFAN
,
2787 SPE_BUILTIN_EVMHOGSMIAA
,
2788 SPE_BUILTIN_EVMHOGSMIAN
,
2789 SPE_BUILTIN_EVMHOGUMIAA
,
2790 SPE_BUILTIN_EVMHOGUMIAN
,
2791 SPE_BUILTIN_EVMHOSMF
,
2792 SPE_BUILTIN_EVMHOSMFA
,
2793 SPE_BUILTIN_EVMHOSMFAAW
,
2794 SPE_BUILTIN_EVMHOSMFANW
,
2795 SPE_BUILTIN_EVMHOSMI
,
2796 SPE_BUILTIN_EVMHOSMIA
,
2797 SPE_BUILTIN_EVMHOSMIAAW
,
2798 SPE_BUILTIN_EVMHOSMIANW
,
2799 SPE_BUILTIN_EVMHOSSF
,
2800 SPE_BUILTIN_EVMHOSSFA
,
2801 SPE_BUILTIN_EVMHOSSFAAW
,
2802 SPE_BUILTIN_EVMHOSSFANW
,
2803 SPE_BUILTIN_EVMHOSSIAAW
,
2804 SPE_BUILTIN_EVMHOSSIANW
,
2805 SPE_BUILTIN_EVMHOUMI
,
2806 SPE_BUILTIN_EVMHOUMIA
,
2807 SPE_BUILTIN_EVMHOUMIAAW
,
2808 SPE_BUILTIN_EVMHOUMIANW
,
2809 SPE_BUILTIN_EVMHOUSIAAW
,
2810 SPE_BUILTIN_EVMHOUSIANW
,
2811 SPE_BUILTIN_EVMWHSMF
,
2812 SPE_BUILTIN_EVMWHSMFA
,
2813 SPE_BUILTIN_EVMWHSMI
,
2814 SPE_BUILTIN_EVMWHSMIA
,
2815 SPE_BUILTIN_EVMWHSSF
,
2816 SPE_BUILTIN_EVMWHSSFA
,
2817 SPE_BUILTIN_EVMWHUMI
,
2818 SPE_BUILTIN_EVMWHUMIA
,
2819 SPE_BUILTIN_EVMWLSMIAAW
,
2820 SPE_BUILTIN_EVMWLSMIANW
,
2821 SPE_BUILTIN_EVMWLSSIAAW
,
2822 SPE_BUILTIN_EVMWLSSIANW
,
2823 SPE_BUILTIN_EVMWLUMI
,
2824 SPE_BUILTIN_EVMWLUMIA
,
2825 SPE_BUILTIN_EVMWLUMIAAW
,
2826 SPE_BUILTIN_EVMWLUMIANW
,
2827 SPE_BUILTIN_EVMWLUSIAAW
,
2828 SPE_BUILTIN_EVMWLUSIANW
,
2829 SPE_BUILTIN_EVMWSMF
,
2830 SPE_BUILTIN_EVMWSMFA
,
2831 SPE_BUILTIN_EVMWSMFAA
,
2832 SPE_BUILTIN_EVMWSMFAN
,
2833 SPE_BUILTIN_EVMWSMI
,
2834 SPE_BUILTIN_EVMWSMIA
,
2835 SPE_BUILTIN_EVMWSMIAA
,
2836 SPE_BUILTIN_EVMWSMIAN
,
2837 SPE_BUILTIN_EVMWHSSFAA
,
2838 SPE_BUILTIN_EVMWSSF
,
2839 SPE_BUILTIN_EVMWSSFA
,
2840 SPE_BUILTIN_EVMWSSFAA
,
2841 SPE_BUILTIN_EVMWSSFAN
,
2842 SPE_BUILTIN_EVMWUMI
,
2843 SPE_BUILTIN_EVMWUMIA
,
2844 SPE_BUILTIN_EVMWUMIAA
,
2845 SPE_BUILTIN_EVMWUMIAN
,
2854 SPE_BUILTIN_EVSTDDX
,
2855 SPE_BUILTIN_EVSTDHX
,
2856 SPE_BUILTIN_EVSTDWX
,
2857 SPE_BUILTIN_EVSTWHEX
,
2858 SPE_BUILTIN_EVSTWHOX
,
2859 SPE_BUILTIN_EVSTWWEX
,
2860 SPE_BUILTIN_EVSTWWOX
,
2861 SPE_BUILTIN_EVSUBFW
,
2864 SPE_BUILTIN_EVADDSMIAAW
,
2865 SPE_BUILTIN_EVADDSSIAAW
,
2866 SPE_BUILTIN_EVADDUMIAAW
,
2867 SPE_BUILTIN_EVADDUSIAAW
,
2868 SPE_BUILTIN_EVCNTLSW
,
2869 SPE_BUILTIN_EVCNTLZW
,
2870 SPE_BUILTIN_EVEXTSB
,
2871 SPE_BUILTIN_EVEXTSH
,
2872 SPE_BUILTIN_EVFSABS
,
2873 SPE_BUILTIN_EVFSCFSF
,
2874 SPE_BUILTIN_EVFSCFSI
,
2875 SPE_BUILTIN_EVFSCFUF
,
2876 SPE_BUILTIN_EVFSCFUI
,
2877 SPE_BUILTIN_EVFSCTSF
,
2878 SPE_BUILTIN_EVFSCTSI
,
2879 SPE_BUILTIN_EVFSCTSIZ
,
2880 SPE_BUILTIN_EVFSCTUF
,
2881 SPE_BUILTIN_EVFSCTUI
,
2882 SPE_BUILTIN_EVFSCTUIZ
,
2883 SPE_BUILTIN_EVFSNABS
,
2884 SPE_BUILTIN_EVFSNEG
,
2888 SPE_BUILTIN_EVSUBFSMIAAW
,
2889 SPE_BUILTIN_EVSUBFSSIAAW
,
2890 SPE_BUILTIN_EVSUBFUMIAAW
,
2891 SPE_BUILTIN_EVSUBFUSIAAW
,
2892 SPE_BUILTIN_EVADDIW
,
2896 SPE_BUILTIN_EVLHHESPLAT
,
2897 SPE_BUILTIN_EVLHHOSSPLAT
,
2898 SPE_BUILTIN_EVLHHOUSPLAT
,
2900 SPE_BUILTIN_EVLWHOS
,
2901 SPE_BUILTIN_EVLWHOU
,
2902 SPE_BUILTIN_EVLWHSPLAT
,
2903 SPE_BUILTIN_EVLWWSPLAT
,
2906 SPE_BUILTIN_EVSRWIS
,
2907 SPE_BUILTIN_EVSRWIU
,
2911 SPE_BUILTIN_EVSTWHE
,
2912 SPE_BUILTIN_EVSTWHO
,
2913 SPE_BUILTIN_EVSTWWE
,
2914 SPE_BUILTIN_EVSTWWO
,
2915 SPE_BUILTIN_EVSUBIFW
,
2918 SPE_BUILTIN_EVCMPEQ
,
2919 SPE_BUILTIN_EVCMPGTS
,
2920 SPE_BUILTIN_EVCMPGTU
,
2921 SPE_BUILTIN_EVCMPLTS
,
2922 SPE_BUILTIN_EVCMPLTU
,
2923 SPE_BUILTIN_EVFSCMPEQ
,
2924 SPE_BUILTIN_EVFSCMPGT
,
2925 SPE_BUILTIN_EVFSCMPLT
,
2926 SPE_BUILTIN_EVFSTSTEQ
,
2927 SPE_BUILTIN_EVFSTSTGT
,
2928 SPE_BUILTIN_EVFSTSTLT
,
2930 /* EVSEL compares. */
2931 SPE_BUILTIN_EVSEL_CMPEQ
,
2932 SPE_BUILTIN_EVSEL_CMPGTS
,
2933 SPE_BUILTIN_EVSEL_CMPGTU
,
2934 SPE_BUILTIN_EVSEL_CMPLTS
,
2935 SPE_BUILTIN_EVSEL_CMPLTU
,
2936 SPE_BUILTIN_EVSEL_FSCMPEQ
,
2937 SPE_BUILTIN_EVSEL_FSCMPGT
,
2938 SPE_BUILTIN_EVSEL_FSCMPLT
,
2939 SPE_BUILTIN_EVSEL_FSTSTEQ
,
2940 SPE_BUILTIN_EVSEL_FSTSTGT
,
2941 SPE_BUILTIN_EVSEL_FSTSTLT
,
2943 SPE_BUILTIN_EVSPLATFI
,
2944 SPE_BUILTIN_EVSPLATI
,
2945 SPE_BUILTIN_EVMWHSSMAA
,
2946 SPE_BUILTIN_EVMWHSMFAA
,
2947 SPE_BUILTIN_EVMWHSMIAA
,
2948 SPE_BUILTIN_EVMWHUSIAA
,
2949 SPE_BUILTIN_EVMWHUMIAA
,
2950 SPE_BUILTIN_EVMWHSSFAN
,
2951 SPE_BUILTIN_EVMWHSSIAN
,
2952 SPE_BUILTIN_EVMWHSMFAN
,
2953 SPE_BUILTIN_EVMWHSMIAN
,
2954 SPE_BUILTIN_EVMWHUSIAN
,
2955 SPE_BUILTIN_EVMWHUMIAN
,
2956 SPE_BUILTIN_EVMWHGSSFAA
,
2957 SPE_BUILTIN_EVMWHGSMFAA
,
2958 SPE_BUILTIN_EVMWHGSMIAA
,
2959 SPE_BUILTIN_EVMWHGUMIAA
,
2960 SPE_BUILTIN_EVMWHGSSFAN
,
2961 SPE_BUILTIN_EVMWHGSMFAN
,
2962 SPE_BUILTIN_EVMWHGSMIAN
,
2963 SPE_BUILTIN_EVMWHGUMIAN
,
2964 SPE_BUILTIN_MTSPEFSCR
,
2965 SPE_BUILTIN_MFSPEFSCR
,
2968 RS6000_BUILTIN_COUNT
2971 enum rs6000_builtin_type_index
2973 RS6000_BTI_NOT_OPAQUE
,
2974 RS6000_BTI_opaque_V2SI
,
2975 RS6000_BTI_opaque_V2SF
,
2976 RS6000_BTI_opaque_p_V2SI
,
2977 RS6000_BTI_opaque_V4SI
,
2985 RS6000_BTI_unsigned_V16QI
,
2986 RS6000_BTI_unsigned_V8HI
,
2987 RS6000_BTI_unsigned_V4SI
,
2988 RS6000_BTI_bool_char
, /* __bool char */
2989 RS6000_BTI_bool_short
, /* __bool short */
2990 RS6000_BTI_bool_int
, /* __bool int */
2991 RS6000_BTI_pixel
, /* __pixel */
2992 RS6000_BTI_bool_V16QI
, /* __vector __bool char */
2993 RS6000_BTI_bool_V8HI
, /* __vector __bool short */
2994 RS6000_BTI_bool_V4SI
, /* __vector __bool int */
2995 RS6000_BTI_pixel_V8HI
, /* __vector __pixel */
2996 RS6000_BTI_long
, /* long_integer_type_node */
2997 RS6000_BTI_unsigned_long
, /* long_unsigned_type_node */
2998 RS6000_BTI_INTQI
, /* intQI_type_node */
2999 RS6000_BTI_UINTQI
, /* unsigned_intQI_type_node */
3000 RS6000_BTI_INTHI
, /* intHI_type_node */
3001 RS6000_BTI_UINTHI
, /* unsigned_intHI_type_node */
3002 RS6000_BTI_INTSI
, /* intSI_type_node */
3003 RS6000_BTI_UINTSI
, /* unsigned_intSI_type_node */
3004 RS6000_BTI_float
, /* float_type_node */
3005 RS6000_BTI_void
, /* void_type_node */
3010 #define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI])
3011 #define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF])
3012 #define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI])
3013 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
3014 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])
3015 #define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI])
3016 #define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF])
3017 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI])
3018 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI])
3019 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])
3020 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI])
3021 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])
3022 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])
3023 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])
3024 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char])
3025 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short])
3026 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int])
3027 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel])
3028 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI])
3029 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
3030 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
3031 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
3033 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long])
3034 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long])
3035 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI])
3036 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI])
3037 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI])
3038 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI])
3039 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI])
3040 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI])
3041 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float])
3042 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])
3044 extern GTY(()) tree rs6000_builtin_types
[RS6000_BTI_MAX
];
3045 extern GTY(()) tree rs6000_builtin_decls
[RS6000_BUILTIN_COUNT
];