1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992-2018 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 Under Section 7 of GPL version 3, you are granted additional
18 permissions described in the GCC Runtime Library Exception, version
19 3.1, as published by the Free Software Foundation.
21 You should have received a copy of the GNU General Public License and
22 a copy of the GCC Runtime Library Exception along with this program;
23 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
24 <http://www.gnu.org/licenses/>. */
26 /* Note that some other tm.h files include this one and then override
27 many of the definitions. */
30 #include "config/rs6000/rs6000-opts.h"
33 /* 128-bit floating point precision values. */
34 #ifndef RS6000_MODES_H
35 #include "config/rs6000/rs6000-modes.h"
38 /* Definitions for the object file format. These are set at
41 #define OBJECT_XCOFF 1
44 #define OBJECT_MACHO 4
46 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
47 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
48 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
49 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
56 #define TARGET_AIX_OS 0
59 /* Control whether function entry points use a "dot" symbol when
63 /* Default string to use for cpu if not specified. */
64 #ifndef TARGET_CPU_DEFAULT
65 #define TARGET_CPU_DEFAULT ((char *)0)
68 /* If configured for PPC405, support PPC405CR Erratum77. */
69 #ifdef CONFIG_PPC405CR
70 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405)
72 #define PPC405_ERRATUM77 0
75 #define ASM_CPU_POWER5_SPEC "-mpower5"
76 #define ASM_CPU_POWER6_SPEC "-mpower6 -maltivec"
77 #define ASM_CPU_POWER7_SPEC "-mpower7"
78 #define ASM_CPU_POWER8_SPEC "-mpower8"
79 #define ASM_CPU_POWER9_SPEC "-mpower9"
82 #define ASM_CPU_476_SPEC "-m476"
84 #define ASM_CPU_476_SPEC "-mpower4"
87 /* Common ASM definitions used by ASM_SPEC among the various targets for
88 handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to
89 provide the default assembler options if the user uses -mcpu=native, so if
90 you make changes here, make them also there. PR63177: Do not pass -mpower8
91 to the assembler if -mpower9-vector was also used. */
92 #define ASM_CPU_SPEC \
94 %{mpowerpc64*: -mppc64} \
95 %{!mpowerpc64*: %(asm_default)}} \
96 %{mcpu=native: %(asm_cpu_native)} \
97 %{mcpu=cell: -mcell} \
98 %{mcpu=power3: -mppc64} \
99 %{mcpu=power4: -mpower4} \
100 %{mcpu=power5: %(asm_cpu_power5)} \
101 %{mcpu=power5+: %(asm_cpu_power5)} \
102 %{mcpu=power6: %(asm_cpu_power6) -maltivec} \
103 %{mcpu=power6x: %(asm_cpu_power6) -maltivec} \
104 %{mcpu=power7: %(asm_cpu_power7)} \
105 %{mcpu=power8: %{!mpower9-vector: %(asm_cpu_power8)}} \
106 %{mcpu=power9: %(asm_cpu_power9)} \
108 %{mcpu=powerpc: -mppc} \
109 %{mcpu=powerpc64le: %(asm_cpu_power8)} \
110 %{mcpu=rs64a: -mppc64} \
114 %{mcpu=405fp: -m405} \
116 %{mcpu=440fp: -m440} \
118 %{mcpu=464fp: -m440} \
119 %{mcpu=476: %(asm_cpu_476)} \
120 %{mcpu=476fp: %(asm_cpu_476)} \
125 %{mcpu=603e: -mppc} \
126 %{mcpu=ec603e: -mppc} \
128 %{mcpu=604e: -mppc} \
129 %{mcpu=620: -mppc64} \
130 %{mcpu=630: -mppc64} \
134 %{mcpu=7400: -mppc -maltivec} \
135 %{mcpu=7450: -mppc -maltivec} \
136 %{mcpu=G4: -mppc -maltivec} \
141 %{mcpu=970: -mpower4 -maltivec} \
142 %{mcpu=G5: -mpower4 -maltivec} \
143 %{mcpu=8540: -me500} \
144 %{mcpu=8548: -me500} \
145 %{mcpu=e300c2: -me300} \
146 %{mcpu=e300c3: -me300} \
147 %{mcpu=e500mc: -me500mc} \
148 %{mcpu=e500mc64: -me500mc64} \
149 %{mcpu=e5500: -me5500} \
150 %{mcpu=e6500: -me6500} \
151 %{maltivec: -maltivec} \
152 %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \
153 %{mpower8-vector|mcrypto|mdirect-move|mhtm: %{!mcpu*: %(asm_cpu_power8)}} \
154 %{mpower9-vector: %{!mcpu*|mcpu=power8: %(asm_cpu_power9)}} \
157 #define CPP_DEFAULT_SPEC ""
159 #define ASM_DEFAULT_SPEC ""
161 /* This macro defines names of additional specifications to put in the specs
162 that can be used in various specifications like CC1_SPEC. Its definition
163 is an initializer with a subgrouping for each command option.
165 Each subgrouping contains a string constant, that defines the
166 specification name, and a string constant that used by the GCC driver
169 Do not define this macro if it does not need to do anything. */
171 #define SUBTARGET_EXTRA_SPECS
173 #define EXTRA_SPECS \
174 { "cpp_default", CPP_DEFAULT_SPEC }, \
175 { "asm_cpu", ASM_CPU_SPEC }, \
176 { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \
177 { "asm_default", ASM_DEFAULT_SPEC }, \
178 { "cc1_cpu", CC1_CPU_SPEC }, \
179 { "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \
180 { "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \
181 { "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \
182 { "asm_cpu_power8", ASM_CPU_POWER8_SPEC }, \
183 { "asm_cpu_power9", ASM_CPU_POWER9_SPEC }, \
184 { "asm_cpu_476", ASM_CPU_476_SPEC }, \
185 SUBTARGET_EXTRA_SPECS
187 /* -mcpu=native handling only makes sense with compiler running on
188 an PowerPC chip. If changing this condition, also change
189 the condition in driver-rs6000.c. */
190 #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX)
191 /* In driver-rs6000.c. */
192 extern const char *host_detect_local_cpu (int argc
, const char **argv
);
193 #define EXTRA_SPEC_FUNCTIONS \
194 { "local_cpu_detect", host_detect_local_cpu },
195 #define HAVE_LOCAL_CPU_DETECT
196 #define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)"
199 #define ASM_CPU_NATIVE_SPEC "%(asm_default)"
203 #ifdef HAVE_LOCAL_CPU_DETECT
204 #define CC1_CPU_SPEC \
205 "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \
206 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
208 #define CC1_CPU_SPEC ""
212 /* Architecture type. */
214 /* Define TARGET_MFCRF if the target assembler does not support the
215 optional field operand for mfcr. */
217 #ifndef HAVE_AS_MFCRF
219 #define TARGET_MFCRF 0
222 /* Define TARGET_TLS_MARKERS if the target assembler does not support
223 arg markers for __tls_get_addr calls. */
224 #ifndef HAVE_AS_TLS_MARKERS
225 #undef TARGET_TLS_MARKERS
226 #define TARGET_TLS_MARKERS 0
228 #define TARGET_TLS_MARKERS tls_markers
231 #ifndef TARGET_SECURE_PLT
232 #define TARGET_SECURE_PLT 0
235 #ifndef TARGET_CMODEL
236 #define TARGET_CMODEL CMODEL_SMALL
239 #define TARGET_32BIT (! TARGET_64BIT)
242 #define HAVE_AS_TLS 0
245 #ifndef TARGET_LINK_STACK
246 #define TARGET_LINK_STACK 0
249 #ifndef SET_TARGET_LINK_STACK
250 #define SET_TARGET_LINK_STACK(X) do { } while (0)
253 #ifndef TARGET_FLOAT128_ENABLE_TYPE
254 #define TARGET_FLOAT128_ENABLE_TYPE 0
257 /* Return 1 for a symbol ref for a thread-local storage symbol. */
258 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
259 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
262 /* For libgcc2 we make sure this is a compile time constant */
263 #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__)
264 #undef TARGET_POWERPC64
265 #define TARGET_POWERPC64 1
267 #undef TARGET_POWERPC64
268 #define TARGET_POWERPC64 0
271 /* The option machinery will define this. */
274 #define TARGET_DEFAULT (MASK_MULTIPLE)
276 /* Define generic processor types based upon current deployment. */
277 #define PROCESSOR_COMMON PROCESSOR_PPC601
278 #define PROCESSOR_POWERPC PROCESSOR_PPC604
279 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
281 /* Define the default processor. This is overridden by other tm.h files. */
282 #define PROCESSOR_DEFAULT PROCESSOR_PPC603
283 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
285 /* Specify the dialect of assembler to use. Only new mnemonics are supported
286 starting with GCC 4.8, i.e. just one dialect, but for backwards
287 compatibility with older inline asm ASSEMBLER_DIALECT needs to be
289 #define ASSEMBLER_DIALECT 1
292 #define MASK_DEBUG_STACK 0x01 /* debug stack applications */
293 #define MASK_DEBUG_ARG 0x02 /* debug argument handling */
294 #define MASK_DEBUG_REG 0x04 /* debug register handling */
295 #define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */
296 #define MASK_DEBUG_COST 0x10 /* debug rtx codes */
297 #define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */
298 #define MASK_DEBUG_BUILTIN 0x40 /* debug builtins */
299 #define MASK_DEBUG_ALL (MASK_DEBUG_STACK \
304 | MASK_DEBUG_TARGET \
305 | MASK_DEBUG_BUILTIN)
307 #define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK)
308 #define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG)
309 #define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG)
310 #define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR)
311 #define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST)
312 #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET)
313 #define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN)
315 /* Helper macros for TFmode. Quad floating point (TFmode) can be either IBM
316 long double format that uses a pair of doubles, or IEEE 128-bit floating
317 point. KFmode was added as a way to represent IEEE 128-bit floating point,
318 even if the default for long double is the IBM long double format.
319 Similarly IFmode is the IBM long double format even if the default is IEEE
320 128-bit. Don't allow IFmode if -msoft-float. */
321 #define FLOAT128_IEEE_P(MODE) \
322 ((TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \
323 && ((MODE) == TFmode || (MODE) == TCmode)) \
324 || ((MODE) == KFmode) || ((MODE) == KCmode))
326 #define FLOAT128_IBM_P(MODE) \
327 ((!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \
328 && ((MODE) == TFmode || (MODE) == TCmode)) \
329 || (TARGET_HARD_FLOAT && ((MODE) == IFmode || (MODE) == ICmode)))
331 /* Helper macros to say whether a 128-bit floating point type can go in a
332 single vector register, or whether it needs paired scalar values. */
333 #define FLOAT128_VECTOR_P(MODE) (TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE))
335 #define FLOAT128_2REG_P(MODE) \
336 (FLOAT128_IBM_P (MODE) \
337 || ((MODE) == TDmode) \
338 || (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE)))
340 /* Return true for floating point that does not use a vector register. */
341 #define SCALAR_FLOAT_MODE_NOT_VECTOR_P(MODE) \
342 (SCALAR_FLOAT_MODE_P (MODE) && !FLOAT128_VECTOR_P (MODE))
344 /* Describe the vector unit used for arithmetic operations. */
345 extern enum rs6000_vector rs6000_vector_unit
[];
347 #define VECTOR_UNIT_NONE_P(MODE) \
348 (rs6000_vector_unit[(MODE)] == VECTOR_NONE)
350 #define VECTOR_UNIT_VSX_P(MODE) \
351 (rs6000_vector_unit[(MODE)] == VECTOR_VSX)
353 #define VECTOR_UNIT_P8_VECTOR_P(MODE) \
354 (rs6000_vector_unit[(MODE)] == VECTOR_P8_VECTOR)
356 #define VECTOR_UNIT_ALTIVEC_P(MODE) \
357 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC)
359 #define VECTOR_UNIT_VSX_OR_P8_VECTOR_P(MODE) \
360 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \
362 (int)VECTOR_P8_VECTOR))
364 /* VECTOR_UNIT_ALTIVEC_OR_VSX_P is used in places where we are using either
365 altivec (VMX) or VSX vector instructions. P8 vector support is upwards
366 compatible, so allow it as well, rather than changing all of the uses of the
368 #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \
369 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \
370 (int)VECTOR_ALTIVEC, \
371 (int)VECTOR_P8_VECTOR))
373 /* Describe whether to use VSX loads or Altivec loads. For now, just use the
374 same unit as the vector unit we are using, but we may want to migrate to
375 using VSX style loads even for types handled by altivec. */
376 extern enum rs6000_vector rs6000_vector_mem
[];
378 #define VECTOR_MEM_NONE_P(MODE) \
379 (rs6000_vector_mem[(MODE)] == VECTOR_NONE)
381 #define VECTOR_MEM_VSX_P(MODE) \
382 (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
384 #define VECTOR_MEM_P8_VECTOR_P(MODE) \
385 (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
387 #define VECTOR_MEM_ALTIVEC_P(MODE) \
388 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC)
390 #define VECTOR_MEM_VSX_OR_P8_VECTOR_P(MODE) \
391 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \
393 (int)VECTOR_P8_VECTOR))
395 #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \
396 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \
397 (int)VECTOR_ALTIVEC, \
398 (int)VECTOR_P8_VECTOR))
400 /* Return the alignment of a given vector type, which is set based on the
401 vector unit use. VSX for instance can load 32 or 64 bit aligned words
402 without problems, while Altivec requires 128-bit aligned vectors. */
403 extern int rs6000_vector_align
[];
405 #define VECTOR_ALIGN(MODE) \
406 ((rs6000_vector_align[(MODE)] != 0) \
407 ? rs6000_vector_align[(MODE)] \
408 : (int)GET_MODE_BITSIZE ((MODE)))
410 /* Element number of the 64-bit value in a 128-bit vector that can be accessed
411 with scalar instructions. */
412 #define VECTOR_ELEMENT_SCALAR_64BIT ((BYTES_BIG_ENDIAN) ? 0 : 1)
414 /* Element number of the 64-bit value in a 128-bit vector that can be accessed
415 with the ISA 3.0 MFVSRLD instructions. */
416 #define VECTOR_ELEMENT_MFVSRLD_64BIT ((BYTES_BIG_ENDIAN) ? 1 : 0)
418 /* Alignment options for fields in structures for sub-targets following
420 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
421 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
423 Override the macro definitions when compiling libobjc to avoid undefined
424 reference to rs6000_alignment_flags due to library's use of GCC alignment
425 macros which use the macros below. */
427 #ifndef IN_TARGET_LIBS
428 #define MASK_ALIGN_POWER 0x00000000
429 #define MASK_ALIGN_NATURAL 0x00000001
430 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
432 #define TARGET_ALIGN_NATURAL 0
435 /* We use values 126..128 to pick the appropriate long double type (IFmode,
437 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size > 64)
438 #define TARGET_IEEEQUAD rs6000_ieeequad
439 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
440 #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
442 /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
443 Enable 32-bit fcfid's on any of the switches for newer ISA machines. */
444 #define TARGET_FCFID (TARGET_POWERPC64 \
445 || TARGET_PPC_GPOPT /* 970/power4 */ \
446 || TARGET_POPCNTB /* ISA 2.02 */ \
447 || TARGET_CMPB /* ISA 2.05 */ \
448 || TARGET_POPCNTD) /* ISA 2.06 */
450 #define TARGET_FCTIDZ TARGET_FCFID
451 #define TARGET_STFIWX TARGET_PPC_GFXOPT
452 #define TARGET_LFIWAX TARGET_CMPB
453 #define TARGET_LFIWZX TARGET_POPCNTD
454 #define TARGET_FCFIDS TARGET_POPCNTD
455 #define TARGET_FCFIDU TARGET_POPCNTD
456 #define TARGET_FCFIDUS TARGET_POPCNTD
457 #define TARGET_FCTIDUZ TARGET_POPCNTD
458 #define TARGET_FCTIWUZ TARGET_POPCNTD
459 #define TARGET_CTZ TARGET_MODULO
460 #define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64)
461 #define TARGET_MADDLD (TARGET_MODULO && TARGET_POWERPC64)
463 #define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
464 #define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
465 #define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64)
466 #define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
468 #define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
471 /* Whether we should avoid (SUBREG:SI (REG:SF) and (SUBREG:SF (REG:SI). */
472 #define TARGET_NO_SF_SUBREG TARGET_DIRECT_MOVE_64BIT
473 #define TARGET_ALLOW_SF_SUBREG (!TARGET_DIRECT_MOVE_64BIT)
475 /* This wants to be set for p8 and newer. On p7, overlapping unaligned
477 #define TARGET_EFFICIENT_OVERLAPPING_UNALIGNED TARGET_EFFICIENT_UNALIGNED_VSX
479 /* Byte/char syncs were added as phased in for ISA 2.06B, but are not present
480 in power7, so conditionalize them on p8 features. TImode syncs need quad
482 #define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \
483 || TARGET_QUAD_MEMORY_ATOMIC \
484 || TARGET_DIRECT_MOVE)
486 #define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC
488 /* Power7 has both 32-bit load and store integer for the FPRs, so we don't need
489 to allocate the SDmode stack slot to get the value into the proper location
491 #define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP)
493 /* ISA 3.0 has new min/max functions that don't need fast math that are being
494 phased in. Min/max using FSEL or XSMAXDP/XSMINDP do not return the correct
495 answers if the arguments are not in the normal range. */
496 #define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
497 && (TARGET_P9_MINMAX || !flag_trapping_math))
499 /* In switching from using target_flags to using rs6000_isa_flags, the options
500 machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map
501 OPTION_MASK_<xxx> back into MASK_<xxx>. */
502 #define MASK_ALTIVEC OPTION_MASK_ALTIVEC
503 #define MASK_CMPB OPTION_MASK_CMPB
504 #define MASK_CRYPTO OPTION_MASK_CRYPTO
505 #define MASK_DFP OPTION_MASK_DFP
506 #define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE
507 #define MASK_DLMZB OPTION_MASK_DLMZB
508 #define MASK_EABI OPTION_MASK_EABI
509 #define MASK_FLOAT128_KEYWORD OPTION_MASK_FLOAT128_KEYWORD
510 #define MASK_FLOAT128_HW OPTION_MASK_FLOAT128_HW
511 #define MASK_FPRND OPTION_MASK_FPRND
512 #define MASK_P8_FUSION OPTION_MASK_P8_FUSION
513 #define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT
514 #define MASK_HTM OPTION_MASK_HTM
515 #define MASK_ISEL OPTION_MASK_ISEL
516 #define MASK_MFCRF OPTION_MASK_MFCRF
517 #define MASK_MFPGPR OPTION_MASK_MFPGPR
518 #define MASK_MULHW OPTION_MASK_MULHW
519 #define MASK_MULTIPLE OPTION_MASK_MULTIPLE
520 #define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE
521 #define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR
522 #define MASK_P9_VECTOR OPTION_MASK_P9_VECTOR
523 #define MASK_P9_MISC OPTION_MASK_P9_MISC
524 #define MASK_POPCNTB OPTION_MASK_POPCNTB
525 #define MASK_POPCNTD OPTION_MASK_POPCNTD
526 #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT
527 #define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT
528 #define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION
529 #define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT
530 #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN
531 #define MASK_UPDATE OPTION_MASK_UPDATE
532 #define MASK_VSX OPTION_MASK_VSX
535 #define MASK_POWERPC64 OPTION_MASK_POWERPC64
539 #define MASK_64BIT OPTION_MASK_64BIT
542 #ifdef TARGET_LITTLE_ENDIAN
543 #define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN
546 #ifdef TARGET_REGNAMES
547 #define MASK_REGNAMES OPTION_MASK_REGNAMES
550 #ifdef TARGET_PROTOTYPE
551 #define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE
555 #define RS6000_BTM_MODULO OPTION_MASK_MODULO
559 /* For power systems, we want to enable Altivec and VSX builtins even if the
560 user did not use -maltivec or -mvsx to allow the builtins to be used inside
561 of #pragma GCC target or the target attribute to change the code level for a
564 #define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64 \
565 || TARGET_PPC_GPOPT /* 970/power4 */ \
566 || TARGET_POPCNTB /* ISA 2.02 */ \
567 || TARGET_CMPB /* ISA 2.05 */ \
568 || TARGET_POPCNTD /* ISA 2.06 */ \
571 || TARGET_HARD_FLOAT)
573 /* E500 cores only support plain "sync", not lwsync. */
574 #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \
575 || rs6000_cpu == PROCESSOR_PPC8548)
578 /* Which machine supports the various reciprocal estimate instructions. */
579 #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT)
581 #define TARGET_FRE (TARGET_HARD_FLOAT \
582 && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
584 #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \
585 && TARGET_PPC_GFXOPT)
587 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT \
588 && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode)))
590 /* Macro to say whether we can do optimizations where we need to do parts of
591 the calculation in 64-bit GPRs and then is transfered to the vector
593 #define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \
594 && TARGET_P8_VECTOR \
597 /* Whether the various reciprocal divide/square root estimate instructions
598 exist, and whether we should automatically generate code for the instruction
600 #define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */
601 #define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */
602 #define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */
603 #define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */
605 extern unsigned char rs6000_recip_bits
[];
607 #define RS6000_RECIP_HAVE_RE_P(MODE) \
608 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE)
610 #define RS6000_RECIP_AUTO_RE_P(MODE) \
611 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE)
613 #define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \
614 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE)
616 #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \
617 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE)
619 /* The default CPU for TARGET_OPTION_OVERRIDE. */
620 #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT
623 #define REGISTER_TARGET_PRAGMAS() do { \
624 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
625 targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \
626 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
627 rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \
630 /* Target #defines. */
631 #define TARGET_CPU_CPP_BUILTINS() \
632 rs6000_cpu_cpp_builtins (pfile)
634 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
635 we're compiling for. Some configurations may need to override it. */
636 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
639 if (BYTES_BIG_ENDIAN) \
641 builtin_define ("__BIG_ENDIAN__"); \
642 builtin_define ("_BIG_ENDIAN"); \
643 builtin_assert ("machine=bigendian"); \
647 builtin_define ("__LITTLE_ENDIAN__"); \
648 builtin_define ("_LITTLE_ENDIAN"); \
649 builtin_assert ("machine=littleendian"); \
654 /* Target machine storage layout. */
656 /* Define this macro if it is advisable to hold scalars in registers
657 in a wider mode than that declared by the program. In such cases,
658 the value is constrained to be within the bounds of the declared
659 type, but kept valid in the wider mode. The signedness of the
660 extension may differ from that of the type. */
662 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
663 if (GET_MODE_CLASS (MODE) == MODE_INT \
664 && GET_MODE_SIZE (MODE) < (TARGET_32BIT ? 4 : 8)) \
665 (MODE) = TARGET_32BIT ? SImode : DImode;
667 /* Define this if most significant bit is lowest numbered
668 in instructions that operate on numbered bit-fields. */
669 /* That is true on RS/6000. */
670 #define BITS_BIG_ENDIAN 1
672 /* Define this if most significant byte of a word is the lowest numbered. */
673 /* That is true on RS/6000. */
674 #define BYTES_BIG_ENDIAN 1
676 /* Define this if most significant word of a multiword number is lowest
679 For RS/6000 we can decide arbitrarily since there are no machine
680 instructions for them. Might as well be consistent with bits and bytes. */
681 #define WORDS_BIG_ENDIAN 1
683 /* This says that for the IBM long double the larger magnitude double
684 comes first. It's really a two element double array, and arrays
685 don't index differently between little- and big-endian. */
686 #define LONG_DOUBLE_LARGE_FIRST 1
688 #define MAX_BITS_PER_WORD 64
690 /* Width of a word, in units (bytes). */
691 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
693 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
695 #define MIN_UNITS_PER_WORD 4
697 #define UNITS_PER_FP_WORD 8
698 #define UNITS_PER_ALTIVEC_WORD 16
699 #define UNITS_PER_VSX_WORD 16
701 /* Type used for ptrdiff_t, as a string used in a declaration. */
702 #define PTRDIFF_TYPE "int"
704 /* Type used for size_t, as a string used in a declaration. */
705 #define SIZE_TYPE "long unsigned int"
707 /* Type used for wchar_t, as a string used in a declaration. */
708 #define WCHAR_TYPE "short unsigned int"
710 /* Width of wchar_t in bits. */
711 #define WCHAR_TYPE_SIZE 16
713 /* A C expression for the size in bits of the type `short' on the
714 target machine. If you don't define this, the default is half a
715 word. (If this would be less than one storage unit, it is
716 rounded up to one unit.) */
717 #define SHORT_TYPE_SIZE 16
719 /* A C expression for the size in bits of the type `int' on the
720 target machine. If you don't define this, the default is one
722 #define INT_TYPE_SIZE 32
724 /* A C expression for the size in bits of the type `long' on the
725 target machine. If you don't define this, the default is one
727 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
729 /* A C expression for the size in bits of the type `long long' on the
730 target machine. If you don't define this, the default is two
732 #define LONG_LONG_TYPE_SIZE 64
734 /* A C expression for the size in bits of the type `float' on the
735 target machine. If you don't define this, the default is one
737 #define FLOAT_TYPE_SIZE 32
739 /* A C expression for the size in bits of the type `double' on the
740 target machine. If you don't define this, the default is two
742 #define DOUBLE_TYPE_SIZE 64
744 /* A C expression for the size in bits of the type `long double' on the target
745 machine. If you don't define this, the default is two words. */
746 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
748 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
749 #define WIDEST_HARDWARE_FP_SIZE 64
751 /* Width in bits of a pointer.
752 See also the macro `Pmode' defined below. */
753 extern unsigned rs6000_pointer_size
;
754 #define POINTER_SIZE rs6000_pointer_size
756 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
757 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
759 /* Boundary (in *bits*) on which stack pointer should be aligned. */
760 #define STACK_BOUNDARY \
761 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \
764 /* Allocation boundary (in *bits*) for the code of a function. */
765 #define FUNCTION_BOUNDARY 32
767 /* No data type wants to be aligned rounder than this. */
768 #define BIGGEST_ALIGNMENT 128
770 /* Alignment of field after `int : 0' in a structure. */
771 #define EMPTY_FIELD_BOUNDARY 32
773 /* Every structure's size must be a multiple of this. */
774 #define STRUCTURE_SIZE_BOUNDARY 8
776 /* A bit-field declared as `int' forces `int' alignment for the struct. */
777 #define PCC_BITFIELD_TYPE_MATTERS 1
779 enum data_align
{ align_abi
, align_opt
, align_both
};
781 /* A C expression to compute the alignment for a variables in the
782 local store. TYPE is the data type, and ALIGN is the alignment
783 that the object would ordinarily have. */
784 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
785 rs6000_data_alignment (TYPE, ALIGN, align_both)
787 /* Make arrays of chars word-aligned for the same reasons. */
788 #define DATA_ALIGNMENT(TYPE, ALIGN) \
789 rs6000_data_alignment (TYPE, ALIGN, align_opt)
791 /* Align vectors to 128 bits. */
792 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \
793 rs6000_data_alignment (TYPE, ALIGN, align_abi)
795 /* Nonzero if move instructions will actually fail to work
796 when given unaligned data. */
797 #define STRICT_ALIGNMENT 0
799 /* Standard register usage. */
801 /* Number of actual hardware registers.
802 The hardware registers are assigned numbers for the compiler
803 from 0 to just below FIRST_PSEUDO_REGISTER.
804 All registers that the compiler knows about must be given numbers,
805 even those that are not normally considered general registers.
807 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
808 a count register, a link register, and 8 condition register fields,
809 which we view here as separate registers. AltiVec adds 32 vector
810 registers and a VRsave register.
812 In addition, the difference between the frame and argument pointers is
813 a function of the number of registers saved, so we need to have a
814 register for AP that will later be eliminated in favor of SP or FP.
815 This is a normal register, but it is fixed.
817 We also create a pseudo register for float/int conversions, that will
818 really represent the memory location used. It is represented here as
819 a register, in order to work around problems in allocating stack storage
822 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
823 pointer, which is eventually eliminated in favor of SP or FP.
825 The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */
827 #define FIRST_PSEUDO_REGISTER 115
829 /* This must be included for pre gcc 3.0 glibc compatibility. */
830 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
832 /* The sfp register and 3 HTM registers
833 aren't included in DWARF_FRAME_REGISTERS. */
834 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4)
836 /* Use standard DWARF numbering for DWARF debugging information. */
837 #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number ((REGNO), 0)
839 /* Use gcc hard register numbering for eh_frame. */
840 #define DWARF_FRAME_REGNUM(REGNO) (REGNO)
842 /* Map register numbers held in the call frame info that gcc has
843 collected using DWARF_FRAME_REGNUM to those that should be output in
844 .debug_frame and .eh_frame. */
845 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \
846 rs6000_dbx_register_number ((REGNO), (FOR_EH)? 2 : 1)
848 /* 1 for registers that have pervasive standard uses
849 and are not available for the register allocator.
851 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
852 as a local register; for all other OS's r2 is the TOC pointer.
854 On System V implementations, r13 is fixed and not available for use. */
856 #define FIXED_REGISTERS \
857 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
858 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
859 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
860 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
861 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
862 /* AltiVec registers. */ \
863 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
864 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
869 /* 1 for registers not available across function calls.
870 These must include the FIXED_REGISTERS and also any
871 registers that can be used without being saved.
872 The latter must include the registers where values are returned
873 and the register where structure-value addresses are passed.
874 Aside from that, you can include as many other registers as you like. */
876 #define CALL_USED_REGISTERS \
877 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
878 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
879 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
880 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
881 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
882 /* AltiVec registers. */ \
883 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
884 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
889 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
890 the entire set of `FIXED_REGISTERS' be included.
891 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
892 This macro is optional. If not specified, it defaults to the value
893 of `CALL_USED_REGISTERS'. */
895 #define CALL_REALLY_USED_REGISTERS \
896 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
897 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
898 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
899 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
900 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
901 /* AltiVec registers. */ \
902 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
903 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
908 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
910 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
911 #define FIRST_SAVED_FP_REGNO (14+32)
912 #define FIRST_SAVED_GP_REGNO (FIXED_R13 ? 14 : 13)
914 /* List the order in which to allocate registers. Each register must be
915 listed once, even those in FIXED_REGISTERS.
917 We allocate in the following order:
918 fp0 (not saved or used for anything)
919 fp13 - fp2 (not saved; incoming fp arg registers)
920 fp1 (not saved; return value)
921 fp31 - fp14 (saved; order given to save least number)
922 cr7, cr5 (not saved or special)
923 cr6 (not saved, but used for vector operations)
924 cr1 (not saved, but used for FP operations)
925 cr0 (not saved, but used for arithmetic operations)
926 cr4, cr3, cr2 (saved)
927 r9 (not saved; best for TImode)
928 r10, r8-r4 (not saved; highest first for less conflict with params)
929 r3 (not saved; return value register)
930 r11 (not saved; later alloc to help shrink-wrap)
931 r0 (not saved; cannot be base reg)
932 r31 - r13 (saved; order given to save least number)
933 r12 (not saved; if used for DImode or DFmode would use r13)
934 ctr (not saved; when we have the choice ctr is better)
936 r1, r2, ap, ca (fixed)
937 v0 - v1 (not saved or used for anything)
938 v13 - v3 (not saved; incoming vector arg registers)
939 v2 (not saved; incoming vector arg reg; return value)
940 v19 - v14 (not saved or used for anything)
941 v31 - v20 (saved; order given to save least number)
950 #define MAYBE_R2_AVAILABLE
951 #define MAYBE_R2_FIXED 2,
953 #define MAYBE_R2_AVAILABLE 2,
954 #define MAYBE_R2_FIXED
958 #define EARLY_R12 12,
965 #define REG_ALLOC_ORDER \
967 /* move fr13 (ie 45) later, so if we need TFmode, it does */ \
968 /* not use fr14 which is a saved register. */ \
969 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \
971 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
972 50, 49, 48, 47, 46, \
973 75, 73, 74, 69, 68, 72, 71, 70, \
975 9, 10, 8, 7, 6, 5, 4, \
976 3, EARLY_R12 11, 0, \
977 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
978 18, 17, 16, 15, 14, 13, LATE_R12 \
980 1, MAYBE_R2_FIXED 67, 76, \
981 /* AltiVec registers. */ \
983 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
985 96, 95, 94, 93, 92, 91, \
986 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
991 /* True if register is floating-point. */
992 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
994 /* True if register is a condition register. */
995 #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO)
997 /* True if register is a condition register, but not cr0. */
998 #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO)
1000 /* True if register is an integer register. */
1001 #define INT_REGNO_P(N) \
1002 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
1004 /* True if register is the CA register. */
1005 #define CA_REGNO_P(N) ((N) == CA_REGNO)
1007 /* True if register is an AltiVec register. */
1008 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
1010 /* True if register is a VSX register. */
1011 #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N))
1013 /* Alternate name for any vector register supporting floating point, no matter
1014 which instruction set(s) are available. */
1015 #define VFLOAT_REGNO_P(N) \
1016 (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N)))
1018 /* Alternate name for any vector register supporting integer, no matter which
1019 instruction set(s) are available. */
1020 #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N)
1022 /* Alternate name for any vector register supporting logical operations, no
1023 matter which instruction set(s) are available. Allow GPRs as well as the
1024 vector registers. */
1025 #define VLOGICAL_REGNO_P(N) \
1026 (INT_REGNO_P (N) || ALTIVEC_REGNO_P (N) \
1027 || (TARGET_VSX && FP_REGNO_P (N))) \
1029 /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate
1030 enough space to account for vectors in FP regs. However, TFmode/TDmode
1031 should not use VSX instructions to do a caller save. */
1032 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1033 ((NREGS) <= rs6000_hard_regno_nregs[MODE][REGNO] \
1036 && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \
1037 && FP_REGNO_P (REGNO) \
1039 : FLOAT128_IBM_P (MODE) && FP_REGNO_P (REGNO) \
1041 : (MODE) == TDmode && FP_REGNO_P (REGNO) \
1043 : choose_hard_reg_mode ((REGNO), (NREGS), false))
1045 #define VSX_VECTOR_MODE(MODE) \
1046 ((MODE) == V4SFmode \
1047 || (MODE) == V2DFmode) \
1049 /* Note KFmode and possibly TFmode (i.e. IEEE 128-bit floating point) are not
1050 really a vector, but we want to treat it as a vector for moves, and
1053 #define ALTIVEC_VECTOR_MODE(MODE) \
1054 ((MODE) == V16QImode \
1055 || (MODE) == V8HImode \
1056 || (MODE) == V4SFmode \
1057 || (MODE) == V4SImode \
1058 || FLOAT128_VECTOR_P (MODE))
1060 #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \
1061 (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \
1062 || (MODE) == V2DImode || (MODE) == V1TImode)
1064 /* Post-reload, we can't use any new AltiVec registers, as we already
1065 emitted the vrsave mask. */
1067 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1068 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST))
1070 /* Specify the cost of a branch insn; roughly the number of extra insns that
1071 should be added to avoid a branch.
1073 Set this to 3 on the RS/6000 since that is roughly the average cost of an
1074 unscheduled conditional branch. */
1076 #define BRANCH_COST(speed_p, predictable_p) 3
1078 /* Override BRANCH_COST heuristic which empirically produces worse
1079 performance for removing short circuiting from the logical ops. */
1081 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
1083 /* Specify the registers used for certain standard purposes.
1084 The values of these macros are register numbers. */
1086 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
1087 /* #define PC_REGNUM */
1089 /* Register to use for pushing function arguments. */
1090 #define STACK_POINTER_REGNUM 1
1092 /* Base register for access to local variables of the function. */
1093 #define HARD_FRAME_POINTER_REGNUM 31
1095 /* Base register for access to local variables of the function. */
1096 #define FRAME_POINTER_REGNUM 111
1098 /* Base register for access to arguments of the function. */
1099 #define ARG_POINTER_REGNUM 67
1101 /* Place to put static chain when calling a function that requires it. */
1102 #define STATIC_CHAIN_REGNUM 11
1104 /* Base register for access to thread local storage variables. */
1105 #define TLS_REGNUM ((TARGET_64BIT) ? 13 : 2)
1108 /* Define the classes of registers for register constraints in the
1109 machine description. Also define ranges of constants.
1111 One of the classes must always be named ALL_REGS and include all hard regs.
1112 If there is more than one class, another class must be named NO_REGS
1113 and contain no registers.
1115 The name GENERAL_REGS must be the name of a class (or an alias for
1116 another name such as ALL_REGS). This is the class of registers
1117 that is allowed by "g" or "r" in a register constraint.
1118 Also, registers outside this class are allocated only when
1119 instructions express preferences for them.
1121 The classes must be numbered in nondecreasing order; that is,
1122 a larger-numbered class must never be contained completely
1123 in a smaller-numbered class.
1125 For any two classes, it is very desirable that there be another
1126 class that represents their union. */
1128 /* The RS/6000 has three types of registers, fixed-point, floating-point, and
1129 condition registers, plus three special registers, CTR, and the link
1130 register. AltiVec adds a vector register class. VSX registers overlap the
1131 FPR registers and the Altivec registers.
1133 However, r0 is special in that it cannot be used as a base register.
1134 So make a class for registers valid as base registers.
1136 Also, cr0 is the only condition code register that can be used in
1137 arithmetic insns, so make a separate class for it. */
1164 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1166 /* Give names of register classes as strings for dump file. */
1168 #define REG_CLASS_NAMES \
1179 "NON_SPECIAL_REGS", \
1182 "LINK_OR_CTR_REGS", \
1184 "SPEC_OR_GEN_REGS", \
1192 /* Define which registers fit in which classes.
1193 This is an initializer for a vector of HARD_REG_SET
1194 of length N_REG_CLASSES. */
1196 #define REG_CLASS_CONTENTS \
1199 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1201 { 0xfffffffe, 0x00000000, 0x00000008, 0x00008000 }, \
1202 /* GENERAL_REGS. */ \
1203 { 0xffffffff, 0x00000000, 0x00000008, 0x00008000 }, \
1205 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, \
1206 /* ALTIVEC_REGS. */ \
1207 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, \
1209 { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, \
1210 /* VRSAVE_REGS. */ \
1211 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, \
1213 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, \
1215 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, \
1216 /* NON_SPECIAL_REGS. */ \
1217 { 0xffffffff, 0xffffffff, 0x00000008, 0x00008000 }, \
1219 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, \
1221 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, \
1222 /* LINK_OR_CTR_REGS. */ \
1223 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, \
1224 /* SPECIAL_REGS. */ \
1225 { 0x00000000, 0x00000000, 0x00000006, 0x00002000 }, \
1226 /* SPEC_OR_GEN_REGS. */ \
1227 { 0xffffffff, 0x00000000, 0x0000000e, 0x0000a000 }, \
1229 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, \
1231 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, \
1232 /* NON_FLOAT_REGS. */ \
1233 { 0xffffffff, 0x00000000, 0x00000ffe, 0x00008000 }, \
1235 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, \
1237 { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0001ffff } \
1240 /* The same information, inverted:
1241 Return the class number of the smallest class containing
1242 reg number REGNO. This could be a conditional expression
1243 or could index an array. */
1245 extern enum reg_class rs6000_regno_regclass
[FIRST_PSEUDO_REGISTER
];
1247 #define REGNO_REG_CLASS(REGNO) \
1248 (gcc_checking_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)),\
1249 rs6000_regno_regclass[(REGNO)])
1251 /* Register classes for various constraints that are based on the target
1253 enum r6000_reg_class_enum
{
1254 RS6000_CONSTRAINT_d
, /* fpr registers for double values */
1255 RS6000_CONSTRAINT_f
, /* fpr registers for single values */
1256 RS6000_CONSTRAINT_v
, /* Altivec registers */
1257 RS6000_CONSTRAINT_wa
, /* Any VSX register */
1258 RS6000_CONSTRAINT_wb
, /* Altivec register if ISA 3.0 vector. */
1259 RS6000_CONSTRAINT_wd
, /* VSX register for V2DF */
1260 RS6000_CONSTRAINT_we
, /* VSX register if ISA 3.0 vector. */
1261 RS6000_CONSTRAINT_wf
, /* VSX register for V4SF */
1262 RS6000_CONSTRAINT_wg
, /* FPR register for -mmfpgpr */
1263 RS6000_CONSTRAINT_wh
, /* FPR register for direct moves. */
1264 RS6000_CONSTRAINT_wi
, /* FPR/VSX register to hold DImode */
1265 RS6000_CONSTRAINT_wj
, /* FPR/VSX register for DImode direct moves. */
1266 RS6000_CONSTRAINT_wk
, /* FPR/VSX register for DFmode direct moves. */
1267 RS6000_CONSTRAINT_wl
, /* FPR register for LFIWAX */
1268 RS6000_CONSTRAINT_wm
, /* VSX register for direct move */
1269 RS6000_CONSTRAINT_wo
, /* VSX register for power9 vector. */
1270 RS6000_CONSTRAINT_wp
, /* VSX reg for IEEE 128-bit fp TFmode. */
1271 RS6000_CONSTRAINT_wq
, /* VSX reg for IEEE 128-bit fp KFmode. */
1272 RS6000_CONSTRAINT_wr
, /* GPR register if 64-bit */
1273 RS6000_CONSTRAINT_ws
, /* VSX register for DF */
1274 RS6000_CONSTRAINT_wt
, /* VSX register for TImode */
1275 RS6000_CONSTRAINT_wu
, /* Altivec register for float load/stores. */
1276 RS6000_CONSTRAINT_wv
, /* Altivec register for double load/stores. */
1277 RS6000_CONSTRAINT_ww
, /* FP or VSX register for vsx float ops. */
1278 RS6000_CONSTRAINT_wx
, /* FPR register for STFIWX */
1279 RS6000_CONSTRAINT_wy
, /* VSX register for SF */
1280 RS6000_CONSTRAINT_wz
, /* FPR register for LFIWZX */
1281 RS6000_CONSTRAINT_wA
, /* BASE_REGS if 64-bit. */
1282 RS6000_CONSTRAINT_wH
, /* Altivec register for 32-bit integers. */
1283 RS6000_CONSTRAINT_wI
, /* VSX register for 32-bit integers. */
1284 RS6000_CONSTRAINT_wJ
, /* VSX register for 8/16-bit integers. */
1285 RS6000_CONSTRAINT_wK
, /* Altivec register for 16/32-bit integers. */
1286 RS6000_CONSTRAINT_MAX
1289 extern enum reg_class rs6000_constraints
[RS6000_CONSTRAINT_MAX
];
1291 /* The class value for index registers, and the one for base regs. */
1292 #define INDEX_REG_CLASS GENERAL_REGS
1293 #define BASE_REG_CLASS BASE_REGS
1295 /* Return whether a given register class can hold VSX objects. */
1296 #define VSX_REG_CLASS_P(CLASS) \
1297 ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS)
1299 /* Return whether a given register class targets general purpose registers. */
1300 #define GPR_REG_CLASS_P(CLASS) ((CLASS) == GENERAL_REGS || (CLASS) == BASE_REGS)
1302 /* Given an rtx X being reloaded into a reg required to be
1303 in class CLASS, return the class of reg to actually use.
1304 In general this is just CLASS; but on some machines
1305 in some cases it is preferable to use a more restrictive class.
1307 On the RS/6000, we have to return NO_REGS when we want to reload a
1308 floating-point CONST_DOUBLE to force it to be copied to memory.
1310 We also don't want to reload integer values into floating-point
1311 registers if we can at all help it. In fact, this can
1312 cause reload to die, if it tries to generate a reload of CTR
1313 into a FP register and discovers it doesn't have the memory location
1316 ??? Would it be a good idea to have reload do the converse, that is
1317 try to reload floating modes into FP registers if possible?
1320 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1321 rs6000_preferred_reload_class_ptr (X, CLASS)
1323 /* Return the register class of a scratch register needed to copy IN into
1324 or out of a register in CLASS in MODE. If it can be done directly,
1325 NO_REGS is returned. */
1327 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1328 rs6000_secondary_reload_class_ptr (CLASS, MODE, IN)
1330 /* Return the maximum number of consecutive registers
1331 needed to represent mode MODE in a register of class CLASS.
1333 On RS/6000, this is the size of MODE in words, except in the FP regs, where
1334 a single reg is enough for two words, unless we have VSX, where the FP
1335 registers can hold 128 bits. */
1336 #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)]
1338 /* Stack layout; function entry, exit and calling. */
1340 /* Define this if pushing a word on the stack
1341 makes the stack pointer a smaller address. */
1342 #define STACK_GROWS_DOWNWARD 1
1344 /* Offsets recorded in opcodes are a multiple of this alignment factor. */
1345 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
1347 /* Define this to nonzero if the nominal address of the stack frame
1348 is at the high-address end of the local variables;
1349 that is, each additional local variable allocated
1350 goes at a more negative offset in the frame.
1352 On the RS/6000, we grow upwards, from the area after the outgoing
1354 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \
1355 || (flag_sanitize & SANITIZE_ADDRESS) != 0)
1357 /* Size of the fixed area on the stack */
1358 #define RS6000_SAVE_AREA \
1359 ((DEFAULT_ABI == ABI_V4 ? 8 : DEFAULT_ABI == ABI_ELFv2 ? 16 : 24) \
1360 << (TARGET_64BIT ? 1 : 0))
1362 /* Stack offset for toc save slot. */
1363 #define RS6000_TOC_SAVE_SLOT \
1364 ((DEFAULT_ABI == ABI_ELFv2 ? 12 : 20) << (TARGET_64BIT ? 1 : 0))
1366 /* Align an address */
1367 #define RS6000_ALIGN(n,a) ROUND_UP ((n), (a))
1369 /* Offset within stack frame to start allocating local variables at.
1370 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1371 first local allocated. Otherwise, it is the offset to the BEGINNING
1372 of the first local allocated.
1374 On the RS/6000, the frame pointer is the same as the stack pointer,
1375 except for dynamic allocations. So we start after the fixed area and
1376 outgoing parameter area.
1378 If the function uses dynamic stack space (CALLS_ALLOCA is set), that
1379 space needs to be aligned to STACK_BOUNDARY, i.e. the sum of the
1380 sizes of the fixed area and the parameter area must be a multiple of
1383 #define RS6000_STARTING_FRAME_OFFSET \
1384 (cfun->calls_alloca \
1385 ? (RS6000_ALIGN (crtl->outgoing_args_size + RS6000_SAVE_AREA, \
1386 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8 )) \
1387 : (RS6000_ALIGN (crtl->outgoing_args_size, \
1388 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \
1389 + RS6000_SAVE_AREA))
1391 /* Offset from the stack pointer register to an item dynamically
1392 allocated on the stack, e.g., by `alloca'.
1394 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1395 length of the outgoing arguments. The default is correct for most
1396 machines. See `function.c' for details.
1398 This value must be a multiple of STACK_BOUNDARY (hard coded in
1400 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1401 RS6000_ALIGN (crtl->outgoing_args_size.to_constant () \
1402 + STACK_POINTER_OFFSET, \
1403 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8)
1405 /* If we generate an insn to push BYTES bytes,
1406 this says how many the stack pointer really advances by.
1407 On RS/6000, don't define this because there are no push insns. */
1408 /* #define PUSH_ROUNDING(BYTES) */
1410 /* Offset of first parameter from the argument pointer register value.
1411 On the RS/6000, we define the argument pointer to the start of the fixed
1413 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1415 /* Offset from the argument pointer register value to the top of
1416 stack. This is different from FIRST_PARM_OFFSET because of the
1417 register save area. */
1418 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1420 /* Define this if stack space is still allocated for a parameter passed
1421 in a register. The value is the number of bytes allocated to this
1423 #define REG_PARM_STACK_SPACE(FNDECL) \
1424 rs6000_reg_parm_stack_space ((FNDECL), false)
1426 /* Define this macro if space guaranteed when compiling a function body
1427 is different to space required when making a call, a situation that
1428 can arise with K&R style function definitions. */
1429 #define INCOMING_REG_PARM_STACK_SPACE(FNDECL) \
1430 rs6000_reg_parm_stack_space ((FNDECL), true)
1432 /* Define this if the above stack space is to be considered part of the
1433 space allocated by the caller. */
1434 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
1436 /* This is the difference between the logical top of stack and the actual sp.
1438 For the RS/6000, sp points past the fixed area. */
1439 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1441 /* Define this if the maximum size of all the outgoing args is to be
1442 accumulated and pushed during the prologue. The amount can be
1443 found in the variable crtl->outgoing_args_size. */
1444 #define ACCUMULATE_OUTGOING_ARGS 1
1446 /* Define how to find the value returned by a library function
1447 assuming the value has mode MODE. */
1449 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
1451 /* DRAFT_V4_STRUCT_RET defaults off. */
1452 #define DRAFT_V4_STRUCT_RET 0
1454 /* Let TARGET_RETURN_IN_MEMORY control what happens. */
1455 #define DEFAULT_PCC_STRUCT_RETURN 0
1457 /* Mode of stack savearea.
1458 FUNCTION is VOIDmode because calling convention maintains SP.
1459 BLOCK needs Pmode for SP.
1460 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1461 #define STACK_SAVEAREA_MODE(LEVEL) \
1462 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1463 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode)
1465 /* Minimum and maximum general purpose registers used to hold arguments. */
1466 #define GP_ARG_MIN_REG 3
1467 #define GP_ARG_MAX_REG 10
1468 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1470 /* Minimum and maximum floating point registers used to hold arguments. */
1471 #define FP_ARG_MIN_REG 33
1472 #define FP_ARG_AIX_MAX_REG 45
1473 #define FP_ARG_V4_MAX_REG 40
1474 #define FP_ARG_MAX_REG (DEFAULT_ABI == ABI_V4 \
1475 ? FP_ARG_V4_MAX_REG : FP_ARG_AIX_MAX_REG)
1476 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1478 /* Minimum and maximum AltiVec registers used to hold arguments. */
1479 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1480 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1481 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1483 /* Maximum number of registers per ELFv2 homogeneous aggregate argument. */
1484 #define AGGR_ARG_NUM_REG 8
1486 /* Return registers */
1487 #define GP_ARG_RETURN GP_ARG_MIN_REG
1488 #define FP_ARG_RETURN FP_ARG_MIN_REG
1489 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1490 #define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \
1491 : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1))
1492 #define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 \
1493 ? (ALTIVEC_ARG_RETURN \
1494 + (TARGET_FLOAT128_TYPE ? 1 : 0)) \
1495 : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1))
1497 /* Flags for the call/call_value rtl operations set up by function_arg */
1498 #define CALL_NORMAL 0x00000000 /* no special processing */
1499 /* Bits in 0x00000001 are unused. */
1500 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1501 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1502 #define CALL_LONG 0x00000008 /* always call indirect */
1503 #define CALL_LIBCALL 0x00000010 /* libcall */
1505 /* We don't have prologue and epilogue functions to save/restore
1506 everything for most ABIs. */
1507 #define WORLD_SAVE_P(INFO) 0
1509 /* 1 if N is a possible register number for a function value
1510 as seen by the caller.
1512 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1513 #define FUNCTION_VALUE_REGNO_P(N) \
1514 ((N) == GP_ARG_RETURN \
1515 || (IN_RANGE ((N), FP_ARG_RETURN, FP_ARG_MAX_RETURN) \
1516 && TARGET_HARD_FLOAT) \
1517 || (IN_RANGE ((N), ALTIVEC_ARG_RETURN, ALTIVEC_ARG_MAX_RETURN) \
1518 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
1520 /* 1 if N is a possible register number for function argument passing.
1521 On RS/6000, these are r3-r10 and fp1-fp13.
1522 On AltiVec, v2 - v13 are used for passing vectors. */
1523 #define FUNCTION_ARG_REGNO_P(N) \
1524 (IN_RANGE ((N), GP_ARG_MIN_REG, GP_ARG_MAX_REG) \
1525 || (IN_RANGE ((N), ALTIVEC_ARG_MIN_REG, ALTIVEC_ARG_MAX_REG) \
1526 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
1527 || (IN_RANGE ((N), FP_ARG_MIN_REG, FP_ARG_MAX_REG) \
1528 && TARGET_HARD_FLOAT))
1530 /* Define a data type for recording info about an argument list
1531 during the scan of that argument list. This data type should
1532 hold all necessary information about the function itself
1533 and about the args processed so far, enough to enable macros
1534 such as FUNCTION_ARG to determine where the next arg should go.
1536 On the RS/6000, this is a structure. The first element is the number of
1537 total argument words, the second is used to store the next
1538 floating-point register number, and the third says how many more args we
1539 have prototype types for.
1541 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1542 the next available GP register, `fregno' is the next available FP
1543 register, and `words' is the number of words used on the stack.
1545 The varargs/stdarg support requires that this structure's size
1546 be a multiple of sizeof(int). */
1548 typedef struct rs6000_args
1550 int words
; /* # words used for passing GP registers */
1551 int fregno
; /* next available FP register */
1552 int vregno
; /* next available AltiVec register */
1553 int nargs_prototype
; /* # args left in the current prototype */
1554 int prototype
; /* Whether a prototype was defined */
1555 int stdarg
; /* Whether function is a stdarg function. */
1556 int call_cookie
; /* Do special things for this call */
1557 int sysv_gregno
; /* next available GP register */
1558 int intoffset
; /* running offset in struct (darwin64) */
1559 int use_stack
; /* any part of struct on stack (darwin64) */
1560 int floats_in_gpr
; /* count of SFmode floats taking up
1561 GPR space (darwin64) */
1562 int named
; /* false for varargs params */
1563 int escapes
; /* if function visible outside tu */
1564 int libcall
; /* If this is a compiler generated call. */
1567 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1568 for a call to a function whose data type is FNTYPE.
1569 For a library call, FNTYPE is 0. */
1571 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1572 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \
1573 N_NAMED_ARGS, FNDECL, VOIDmode)
1575 /* Similar, but when scanning the definition of a procedure. We always
1576 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1578 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1579 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \
1580 1000, current_function_decl, VOIDmode)
1582 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1584 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1585 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \
1588 #define PAD_VARARGS_DOWN \
1589 (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD)
1591 /* Output assembler code to FILE to increment profiler label # LABELNO
1592 for profiling a function entry. */
1594 #define FUNCTION_PROFILER(FILE, LABELNO) \
1595 output_function_profiler ((FILE), (LABELNO));
1597 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1598 the stack pointer does not matter. No definition is equivalent to
1601 On the RS/6000, this is nonzero because we can restore the stack from
1602 its backpointer, which we maintain. */
1603 #define EXIT_IGNORE_STACK 1
1605 /* Define this macro as a C expression that is nonzero for registers
1606 that are used by the epilogue or the return' pattern. The stack
1607 and frame pointer registers are already be assumed to be used as
1610 #define EPILOGUE_USES(REGNO) \
1611 ((reload_completed && (REGNO) == LR_REGNO) \
1612 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1613 || (crtl->calls_eh_return \
1618 /* Length in units of the trampoline for entering a nested function. */
1620 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1622 /* Definitions for __builtin_return_address and __builtin_frame_address.
1623 __builtin_return_address (0) should give link register (LR_REGNO), enable
1625 /* This should be uncommented, so that the link register is used, but
1626 currently this would result in unmatched insns and spilling fixed
1627 registers so we'll leave it for another day. When these problems are
1628 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1630 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1632 /* Number of bytes into the frame return addresses can be found. See
1633 rs6000_stack_info in rs6000.c for more information on how the different
1634 abi's store the return address. */
1635 #define RETURN_ADDRESS_OFFSET \
1636 ((DEFAULT_ABI == ABI_V4 ? 4 : 8) << (TARGET_64BIT ? 1 : 0))
1638 /* The current return address is in link register (65). The return address
1639 of anything farther back is accessed normally at an offset of 8 from the
1641 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1642 (rs6000_return_addr (COUNT, FRAME))
1645 /* Definitions for register eliminations.
1647 We have two registers that can be eliminated on the RS/6000. First, the
1648 frame pointer register can often be eliminated in favor of the stack
1649 pointer register. Secondly, the argument pointer register can always be
1650 eliminated; it is replaced with either the stack or frame pointer.
1652 In addition, we use the elimination mechanism to see if r30 is needed
1653 Initially we assume that it isn't. If it is, we spill it. This is done
1654 by making it an eliminable register. We replace it with itself so that
1655 if it isn't needed, then existing uses won't be modified. */
1657 /* This is an array of structures. Each structure initializes one pair
1658 of eliminable registers. The "from" register number is given first,
1659 followed by "to". Eliminations of the same "from" register are listed
1660 in order of preference. */
1661 #define ELIMINABLE_REGS \
1662 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1663 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1664 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1665 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1666 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1667 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
1669 /* Define the offset between two registers, one to be eliminated, and the other
1670 its replacement, at the start of a routine. */
1671 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1672 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
1674 /* Addressing modes, and classification of registers for them. */
1676 #define HAVE_PRE_DECREMENT 1
1677 #define HAVE_PRE_INCREMENT 1
1678 #define HAVE_PRE_MODIFY_DISP 1
1679 #define HAVE_PRE_MODIFY_REG 1
1681 /* Macros to check register numbers against specific register classes. */
1683 /* These assume that REGNO is a hard or pseudo reg number.
1684 They give nonzero only if REGNO is a hard reg of the suitable class
1685 or a pseudo reg currently allocated to a suitable hard reg.
1686 Since they use reg_renumber, they are safe only once reg_renumber
1687 has been allocated, which happens in reginfo.c during register
1690 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1691 ((REGNO) < FIRST_PSEUDO_REGISTER \
1692 ? (REGNO) <= 31 || (REGNO) == 67 \
1693 || (REGNO) == FRAME_POINTER_REGNUM \
1694 : (reg_renumber[REGNO] >= 0 \
1695 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1696 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1698 #define REGNO_OK_FOR_BASE_P(REGNO) \
1699 ((REGNO) < FIRST_PSEUDO_REGISTER \
1700 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1701 || (REGNO) == FRAME_POINTER_REGNUM \
1702 : (reg_renumber[REGNO] > 0 \
1703 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1704 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1706 /* Nonzero if X is a hard reg that can be used as an index
1707 or if it is a pseudo reg in the non-strict case. */
1708 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1709 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1710 || REGNO_OK_FOR_INDEX_P (REGNO (X)))
1712 /* Nonzero if X is a hard reg that can be used as a base reg
1713 or if it is a pseudo reg in the non-strict case. */
1714 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1715 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1716 || REGNO_OK_FOR_BASE_P (REGNO (X)))
1719 /* Maximum number of registers that can appear in a valid memory address. */
1721 #define MAX_REGS_PER_ADDRESS 2
1723 /* Recognize any constant value that is a valid address. */
1725 #define CONSTANT_ADDRESS_P(X) \
1726 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1727 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1728 || GET_CODE (X) == HIGH)
1730 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
1731 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \
1732 && EASY_VECTOR_15((n) >> 1) \
1735 #define EASY_VECTOR_MSB(n,mode) \
1736 ((((unsigned HOST_WIDE_INT) (n)) & GET_MODE_MASK (mode)) == \
1737 ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1))
1740 /* Try a machine-dependent way of reloading an illegitimate address
1741 operand. If we find one, push the reload and jump to WIN. This
1742 macro is used in only one place: `find_reloads_address' in reload.c.
1744 Implemented on rs6000 by rs6000_legitimize_reload_address.
1745 Note that (X) is evaluated twice; this is safe in current usage. */
1747 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1750 (X) = rs6000_legitimize_reload_address_ptr ((X), (MODE), (OPNUM), \
1751 (int)(TYPE), (IND_LEVELS), &win); \
1756 #define FIND_BASE_TERM rs6000_find_base_term
1758 /* The register number of the register used to address a table of
1759 static data addresses in memory. In some cases this register is
1760 defined by a processor's "application binary interface" (ABI).
1761 When this macro is defined, RTL is generated for this register
1762 once, as with the stack pointer and frame pointer registers. If
1763 this macro is not defined, it is up to the machine-dependent files
1764 to allocate such a register (if necessary). */
1766 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
1767 #define PIC_OFFSET_TABLE_REGNUM \
1768 (TARGET_TOC ? TOC_REGISTER \
1769 : flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM \
1772 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
1774 /* Define this macro if the register defined by
1775 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
1776 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
1778 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
1780 /* A C expression that is nonzero if X is a legitimate immediate
1781 operand on the target machine when generating position independent
1782 code. You can assume that X satisfies `CONSTANT_P', so you need
1783 not check this. You can also assume FLAG_PIC is true, so you need
1784 not check it either. You need not define this macro if all
1785 constants (including `SYMBOL_REF') can be immediate operands when
1786 generating position independent code. */
1788 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
1790 /* Specify the machine mode that this machine uses
1791 for the index in the tablejump instruction. */
1792 #define CASE_VECTOR_MODE SImode
1794 /* Define as C expression which evaluates to nonzero if the tablejump
1795 instruction expects the table to contain offsets from the address of the
1797 Do not define this if the table should contain absolute addresses. */
1798 #define CASE_VECTOR_PC_RELATIVE 1
1800 /* Define this as 1 if `char' should by default be signed; else as 0. */
1801 #define DEFAULT_SIGNED_CHAR 0
1803 /* An integer expression for the size in bits of the largest integer machine
1804 mode that should actually be used. */
1806 /* Allow pairs of registers to be used, which is the intent of the default. */
1807 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
1809 /* Max number of bytes we can move from memory to memory
1810 in one reasonably fast instruction. */
1811 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
1812 #define MAX_MOVE_MAX 8
1814 /* Nonzero if access to memory by bytes is no faster than for words.
1815 Also nonzero if doing byte operations (specifically shifts) in registers
1817 #define SLOW_BYTE_ACCESS 1
1819 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1820 will either zero-extend or sign-extend. The value of this macro should
1821 be the code that says which one of the two operations is implicitly
1822 done, UNKNOWN if none. */
1823 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1825 /* Define if loading short immediate values into registers sign extends. */
1826 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
1828 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
1829 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1830 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1832 /* The CTZ patterns that are implemented in terms of CLZ return -1 for input of
1833 zero. The hardware instructions added in Power9 and the sequences using
1834 popcount return 32 or 64. */
1835 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1836 (TARGET_CTZ || TARGET_POPCNTD \
1837 ? ((VALUE) = GET_MODE_BITSIZE (MODE), 2) \
1838 : ((VALUE) = -1, 2))
1840 /* Specify the machine mode that pointers have.
1841 After generation of rtl, the compiler makes no further distinction
1842 between pointers and any other objects of this machine mode. */
1843 extern scalar_int_mode rs6000_pmode
;
1844 #define Pmode rs6000_pmode
1846 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
1847 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
1849 /* Mode of a function address in a call instruction (for indexing purposes).
1850 Doesn't matter on RS/6000. */
1851 #define FUNCTION_MODE SImode
1853 /* Define this if addresses of constant functions
1854 shouldn't be put through pseudo regs where they can be cse'd.
1855 Desirable on machines where ordinary constants are expensive
1856 but a CALL with constant address is cheap. */
1857 #define NO_FUNCTION_CSE 1
1859 /* Define this to be nonzero if shift instructions ignore all but the low-order
1862 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
1863 have been dropped from the PowerPC architecture. */
1864 #define SHIFT_COUNT_TRUNCATED 0
1866 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
1867 should be adjusted to reflect any required changes. This macro is used when
1868 there is some systematic length adjustment required that would be difficult
1869 to express in the length attribute. */
1871 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
1873 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
1874 COMPARE, return the mode to be used for the comparison. For
1875 floating-point, CCFPmode should be used. CCUNSmode should be used
1876 for unsigned comparisons. CCEQmode should be used when we are
1877 doing an inequality comparison on the result of a
1878 comparison. CCmode should be used in all other cases. */
1880 #define SELECT_CC_MODE(OP,X,Y) \
1881 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \
1882 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
1883 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
1884 ? CCEQmode : CCmode))
1886 /* Can the condition code MODE be safely reversed? This is safe in
1887 all cases on this port, because at present it doesn't use the
1888 trapping FP comparisons (fcmpo). */
1889 #define REVERSIBLE_CC_MODE(MODE) 1
1891 /* Given a condition code and a mode, return the inverse condition. */
1892 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
1895 /* Target cpu costs. */
1897 struct processor_costs
{
1898 const int mulsi
; /* cost of SImode multiplication. */
1899 const int mulsi_const
; /* cost of SImode multiplication by constant. */
1900 const int mulsi_const9
; /* cost of SImode mult by short constant. */
1901 const int muldi
; /* cost of DImode multiplication. */
1902 const int divsi
; /* cost of SImode division. */
1903 const int divdi
; /* cost of DImode division. */
1904 const int fp
; /* cost of simple SFmode and DFmode insns. */
1905 const int dmul
; /* cost of DFmode multiplication (and fmadd). */
1906 const int sdiv
; /* cost of SFmode division (fdivs). */
1907 const int ddiv
; /* cost of DFmode division (fdiv). */
1908 const int cache_line_size
; /* cache line size in bytes. */
1909 const int l1_cache_size
; /* size of l1 cache, in kilobytes. */
1910 const int l2_cache_size
; /* size of l2 cache, in kilobytes. */
1911 const int simultaneous_prefetches
; /* number of parallel prefetch
1913 const int sfdf_convert
; /* cost of SF->DF conversion. */
1916 extern const struct processor_costs
*rs6000_cost
;
1918 /* Control the assembler format that we output. */
1920 /* A C string constant describing how to begin a comment in the target
1921 assembler language. The compiler assumes that the comment will end at
1922 the end of the line. */
1923 #define ASM_COMMENT_START " #"
1925 /* Flag to say the TOC is initialized */
1926 extern int toc_initialized
;
1928 /* Macro to output a special constant pool entry. Go to WIN if we output
1929 it. Otherwise, it is written the usual way.
1931 On the RS/6000, toc entries are handled this way. */
1933 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
1934 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
1936 output_toc (FILE, X, LABELNO, MODE); \
1941 #ifdef HAVE_GAS_WEAK
1942 #define RS6000_WEAK 1
1944 #define RS6000_WEAK 0
1948 /* Used in lieu of ASM_WEAKEN_LABEL. */
1949 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
1950 rs6000_asm_weaken_decl ((FILE), (DECL), (NAME), (VAL))
1953 #if HAVE_GAS_WEAKREF
1954 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \
1957 fputs ("\t.weakref\t", (FILE)); \
1958 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1959 fputs (", ", (FILE)); \
1960 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
1961 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
1962 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
1964 fputs ("\n\t.weakref\t.", (FILE)); \
1965 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1966 fputs (", .", (FILE)); \
1967 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
1969 fputc ('\n', (FILE)); \
1973 /* This implements the `alias' attribute. */
1974 #undef ASM_OUTPUT_DEF_FROM_DECLS
1975 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
1978 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
1979 const char *name = IDENTIFIER_POINTER (TARGET); \
1980 if (TREE_CODE (DECL) == FUNCTION_DECL \
1981 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
1983 if (TREE_PUBLIC (DECL)) \
1985 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
1987 fputs ("\t.globl\t.", FILE); \
1988 RS6000_OUTPUT_BASENAME (FILE, alias); \
1989 putc ('\n', FILE); \
1992 else if (TARGET_XCOFF) \
1994 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
1996 fputs ("\t.lglobl\t.", FILE); \
1997 RS6000_OUTPUT_BASENAME (FILE, alias); \
1998 putc ('\n', FILE); \
1999 fputs ("\t.lglobl\t", FILE); \
2000 RS6000_OUTPUT_BASENAME (FILE, alias); \
2001 putc ('\n', FILE); \
2004 fputs ("\t.set\t.", FILE); \
2005 RS6000_OUTPUT_BASENAME (FILE, alias); \
2006 fputs (",.", FILE); \
2007 RS6000_OUTPUT_BASENAME (FILE, name); \
2008 fputc ('\n', FILE); \
2010 ASM_OUTPUT_DEF (FILE, alias, name); \
2014 #define TARGET_ASM_FILE_START rs6000_file_start
2016 /* Output to assembler file text saying following lines
2017 may contain character constants, extra white space, comments, etc. */
2019 #define ASM_APP_ON ""
2021 /* Output to assembler file text saying following lines
2022 no longer contain unusual constructs. */
2024 #define ASM_APP_OFF ""
2026 /* How to refer to registers in assembler output.
2027 This sequence is indexed by compiler's hard-register-number (see above). */
2029 extern char rs6000_reg_names
[][8]; /* register names (0 vs. %r0). */
2031 #define REGISTER_NAMES \
2033 &rs6000_reg_names[ 0][0], /* r0 */ \
2034 &rs6000_reg_names[ 1][0], /* r1 */ \
2035 &rs6000_reg_names[ 2][0], /* r2 */ \
2036 &rs6000_reg_names[ 3][0], /* r3 */ \
2037 &rs6000_reg_names[ 4][0], /* r4 */ \
2038 &rs6000_reg_names[ 5][0], /* r5 */ \
2039 &rs6000_reg_names[ 6][0], /* r6 */ \
2040 &rs6000_reg_names[ 7][0], /* r7 */ \
2041 &rs6000_reg_names[ 8][0], /* r8 */ \
2042 &rs6000_reg_names[ 9][0], /* r9 */ \
2043 &rs6000_reg_names[10][0], /* r10 */ \
2044 &rs6000_reg_names[11][0], /* r11 */ \
2045 &rs6000_reg_names[12][0], /* r12 */ \
2046 &rs6000_reg_names[13][0], /* r13 */ \
2047 &rs6000_reg_names[14][0], /* r14 */ \
2048 &rs6000_reg_names[15][0], /* r15 */ \
2049 &rs6000_reg_names[16][0], /* r16 */ \
2050 &rs6000_reg_names[17][0], /* r17 */ \
2051 &rs6000_reg_names[18][0], /* r18 */ \
2052 &rs6000_reg_names[19][0], /* r19 */ \
2053 &rs6000_reg_names[20][0], /* r20 */ \
2054 &rs6000_reg_names[21][0], /* r21 */ \
2055 &rs6000_reg_names[22][0], /* r22 */ \
2056 &rs6000_reg_names[23][0], /* r23 */ \
2057 &rs6000_reg_names[24][0], /* r24 */ \
2058 &rs6000_reg_names[25][0], /* r25 */ \
2059 &rs6000_reg_names[26][0], /* r26 */ \
2060 &rs6000_reg_names[27][0], /* r27 */ \
2061 &rs6000_reg_names[28][0], /* r28 */ \
2062 &rs6000_reg_names[29][0], /* r29 */ \
2063 &rs6000_reg_names[30][0], /* r30 */ \
2064 &rs6000_reg_names[31][0], /* r31 */ \
2066 &rs6000_reg_names[32][0], /* fr0 */ \
2067 &rs6000_reg_names[33][0], /* fr1 */ \
2068 &rs6000_reg_names[34][0], /* fr2 */ \
2069 &rs6000_reg_names[35][0], /* fr3 */ \
2070 &rs6000_reg_names[36][0], /* fr4 */ \
2071 &rs6000_reg_names[37][0], /* fr5 */ \
2072 &rs6000_reg_names[38][0], /* fr6 */ \
2073 &rs6000_reg_names[39][0], /* fr7 */ \
2074 &rs6000_reg_names[40][0], /* fr8 */ \
2075 &rs6000_reg_names[41][0], /* fr9 */ \
2076 &rs6000_reg_names[42][0], /* fr10 */ \
2077 &rs6000_reg_names[43][0], /* fr11 */ \
2078 &rs6000_reg_names[44][0], /* fr12 */ \
2079 &rs6000_reg_names[45][0], /* fr13 */ \
2080 &rs6000_reg_names[46][0], /* fr14 */ \
2081 &rs6000_reg_names[47][0], /* fr15 */ \
2082 &rs6000_reg_names[48][0], /* fr16 */ \
2083 &rs6000_reg_names[49][0], /* fr17 */ \
2084 &rs6000_reg_names[50][0], /* fr18 */ \
2085 &rs6000_reg_names[51][0], /* fr19 */ \
2086 &rs6000_reg_names[52][0], /* fr20 */ \
2087 &rs6000_reg_names[53][0], /* fr21 */ \
2088 &rs6000_reg_names[54][0], /* fr22 */ \
2089 &rs6000_reg_names[55][0], /* fr23 */ \
2090 &rs6000_reg_names[56][0], /* fr24 */ \
2091 &rs6000_reg_names[57][0], /* fr25 */ \
2092 &rs6000_reg_names[58][0], /* fr26 */ \
2093 &rs6000_reg_names[59][0], /* fr27 */ \
2094 &rs6000_reg_names[60][0], /* fr28 */ \
2095 &rs6000_reg_names[61][0], /* fr29 */ \
2096 &rs6000_reg_names[62][0], /* fr30 */ \
2097 &rs6000_reg_names[63][0], /* fr31 */ \
2099 &rs6000_reg_names[64][0], /* was mq */ \
2100 &rs6000_reg_names[65][0], /* lr */ \
2101 &rs6000_reg_names[66][0], /* ctr */ \
2102 &rs6000_reg_names[67][0], /* ap */ \
2104 &rs6000_reg_names[68][0], /* cr0 */ \
2105 &rs6000_reg_names[69][0], /* cr1 */ \
2106 &rs6000_reg_names[70][0], /* cr2 */ \
2107 &rs6000_reg_names[71][0], /* cr3 */ \
2108 &rs6000_reg_names[72][0], /* cr4 */ \
2109 &rs6000_reg_names[73][0], /* cr5 */ \
2110 &rs6000_reg_names[74][0], /* cr6 */ \
2111 &rs6000_reg_names[75][0], /* cr7 */ \
2113 &rs6000_reg_names[76][0], /* ca */ \
2115 &rs6000_reg_names[77][0], /* v0 */ \
2116 &rs6000_reg_names[78][0], /* v1 */ \
2117 &rs6000_reg_names[79][0], /* v2 */ \
2118 &rs6000_reg_names[80][0], /* v3 */ \
2119 &rs6000_reg_names[81][0], /* v4 */ \
2120 &rs6000_reg_names[82][0], /* v5 */ \
2121 &rs6000_reg_names[83][0], /* v6 */ \
2122 &rs6000_reg_names[84][0], /* v7 */ \
2123 &rs6000_reg_names[85][0], /* v8 */ \
2124 &rs6000_reg_names[86][0], /* v9 */ \
2125 &rs6000_reg_names[87][0], /* v10 */ \
2126 &rs6000_reg_names[88][0], /* v11 */ \
2127 &rs6000_reg_names[89][0], /* v12 */ \
2128 &rs6000_reg_names[90][0], /* v13 */ \
2129 &rs6000_reg_names[91][0], /* v14 */ \
2130 &rs6000_reg_names[92][0], /* v15 */ \
2131 &rs6000_reg_names[93][0], /* v16 */ \
2132 &rs6000_reg_names[94][0], /* v17 */ \
2133 &rs6000_reg_names[95][0], /* v18 */ \
2134 &rs6000_reg_names[96][0], /* v19 */ \
2135 &rs6000_reg_names[97][0], /* v20 */ \
2136 &rs6000_reg_names[98][0], /* v21 */ \
2137 &rs6000_reg_names[99][0], /* v22 */ \
2138 &rs6000_reg_names[100][0], /* v23 */ \
2139 &rs6000_reg_names[101][0], /* v24 */ \
2140 &rs6000_reg_names[102][0], /* v25 */ \
2141 &rs6000_reg_names[103][0], /* v26 */ \
2142 &rs6000_reg_names[104][0], /* v27 */ \
2143 &rs6000_reg_names[105][0], /* v28 */ \
2144 &rs6000_reg_names[106][0], /* v29 */ \
2145 &rs6000_reg_names[107][0], /* v30 */ \
2146 &rs6000_reg_names[108][0], /* v31 */ \
2147 &rs6000_reg_names[109][0], /* vrsave */ \
2148 &rs6000_reg_names[110][0], /* vscr */ \
2149 &rs6000_reg_names[111][0], /* sfp */ \
2150 &rs6000_reg_names[112][0], /* tfhar */ \
2151 &rs6000_reg_names[113][0], /* tfiar */ \
2152 &rs6000_reg_names[114][0], /* texasr */ \
2155 /* Table of additional register names to use in user input. */
2157 #define ADDITIONAL_REGISTER_NAMES \
2158 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2159 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2160 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2161 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2162 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2163 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2164 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2165 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2166 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2167 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2168 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2169 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2170 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2171 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2172 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2173 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2174 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2175 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2176 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2177 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2178 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2179 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2180 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2181 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2182 {"vrsave", 109}, {"vscr", 110}, \
2183 /* no additional names for: lr, ctr, ap */ \
2184 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2185 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2186 {"cc", 68}, {"sp", 1}, {"toc", 2}, \
2187 /* CA is only part of XER, but we do not model the other parts (yet). */ \
2189 /* VSX registers overlaid on top of FR, Altivec registers */ \
2190 {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \
2191 {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \
2192 {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \
2193 {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \
2194 {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \
2195 {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \
2196 {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \
2197 {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \
2198 {"vs32", 77}, {"vs33", 78}, {"vs34", 79}, {"vs35", 80}, \
2199 {"vs36", 81}, {"vs37", 82}, {"vs38", 83}, {"vs39", 84}, \
2200 {"vs40", 85}, {"vs41", 86}, {"vs42", 87}, {"vs43", 88}, \
2201 {"vs44", 89}, {"vs45", 90}, {"vs46", 91}, {"vs47", 92}, \
2202 {"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \
2203 {"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \
2204 {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \
2205 {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108}, \
2206 /* Transactional Memory Facility (HTM) Registers. */ \
2207 {"tfhar", 112}, {"tfiar", 113}, {"texasr", 114}, \
2210 /* This is how to output an element of a case-vector that is relative. */
2212 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2213 do { char buf[100]; \
2214 fputs ("\t.long ", FILE); \
2215 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2216 assemble_name (FILE, buf); \
2218 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2219 assemble_name (FILE, buf); \
2220 putc ('\n', FILE); \
2223 /* This is how to output an assembler line
2224 that says to advance the location counter
2225 to a multiple of 2**LOG bytes. */
2227 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2229 fprintf (FILE, "\t.align %d\n", (LOG))
2231 /* How to align the given loop. */
2232 #define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL)
2234 /* Alignment guaranteed by __builtin_malloc. */
2235 /* FIXME: 128-bit alignment is guaranteed by glibc for TARGET_64BIT.
2236 However, specifying the stronger guarantee currently leads to
2237 a regression in SPEC CPU2006 437.leslie3d. The stronger
2238 guarantee should be implemented here once that's fixed. */
2239 #define MALLOC_ABI_ALIGNMENT (64)
2241 /* Pick up the return address upon entry to a procedure. Used for
2242 dwarf2 unwind information. This also enables the table driven
2245 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO)
2246 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO)
2248 /* Describe how we implement __builtin_eh_return. */
2249 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2250 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2252 /* Print operand X (an rtx) in assembler syntax to file FILE.
2253 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2254 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2256 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2258 /* Define which CODE values are valid. */
2260 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '&')
2262 /* Print a memory address as an operand to reference that memory location. */
2264 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2266 /* For switching between functions with different target attributes. */
2267 #define SWITCHABLE_TARGET 1
2269 /* uncomment for disabling the corresponding default options */
2270 /* #define MACHINE_no_sched_interblock */
2271 /* #define MACHINE_no_sched_speculative */
2272 /* #define MACHINE_no_sched_speculative_load */
2274 /* General flags. */
2275 extern int frame_pointer_needed
;
2277 /* Classification of the builtin functions as to which switches enable the
2278 builtin, and what attributes it should have. We used to use the target
2279 flags macros, but we've run out of bits, so we now map the options into new
2280 settings used here. */
2282 /* Builtin attributes. */
2283 #define RS6000_BTC_SPECIAL 0x00000000 /* Special function. */
2284 #define RS6000_BTC_UNARY 0x00000001 /* normal unary function. */
2285 #define RS6000_BTC_BINARY 0x00000002 /* normal binary function. */
2286 #define RS6000_BTC_TERNARY 0x00000003 /* normal ternary function. */
2287 #define RS6000_BTC_PREDICATE 0x00000004 /* predicate function. */
2288 #define RS6000_BTC_ABS 0x00000005 /* Altivec/VSX ABS function. */
2289 #define RS6000_BTC_DST 0x00000007 /* Altivec DST function. */
2290 #define RS6000_BTC_TYPE_MASK 0x0000000f /* Mask to isolate types */
2292 #define RS6000_BTC_MISC 0x00000000 /* No special attributes. */
2293 #define RS6000_BTC_CONST 0x00000100 /* Neither uses, nor
2294 modifies global state. */
2295 #define RS6000_BTC_PURE 0x00000200 /* reads global
2297 not modify global state. */
2298 #define RS6000_BTC_FP 0x00000400 /* depends on rounding mode. */
2299 #define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */
2301 /* Miscellaneous information. */
2302 #define RS6000_BTC_SPR 0x01000000 /* function references SPRs. */
2303 #define RS6000_BTC_VOID 0x02000000 /* function has no return value. */
2304 #define RS6000_BTC_CR 0x04000000 /* function references a CR. */
2305 #define RS6000_BTC_OVERLOADED 0x08000000 /* function is overloaded. */
2306 #define RS6000_BTC_MISC_MASK 0x1f000000 /* Mask of the misc info. */
2308 /* Convenience macros to document the instruction type. */
2309 #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */
2310 #define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */
2312 /* Builtin targets. For now, we reuse the masks for those options that are in
2313 target flags, and pick a random bit for ldbl128, which isn't in
2315 #define RS6000_BTM_ALWAYS 0 /* Always enabled. */
2316 #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */
2317 #define RS6000_BTM_CMPB MASK_CMPB /* ISA 2.05: compare bytes. */
2318 #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */
2319 #define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */
2320 #define RS6000_BTM_P9_VECTOR MASK_P9_VECTOR /* ISA 3.0 vector. */
2321 #define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */
2322 #define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */
2323 #define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */
2324 #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */
2325 #define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */
2326 #define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */
2327 #define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */
2328 #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */
2329 #define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */
2330 #define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */
2331 #define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */
2332 #define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */
2333 #define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */
2334 #define RS6000_BTM_POWERPC64 MASK_POWERPC64 /* 64-bit registers. */
2335 #define RS6000_BTM_FLOAT128 MASK_FLOAT128_KEYWORD /* IEEE 128-bit float. */
2336 #define RS6000_BTM_FLOAT128_HW MASK_FLOAT128_HW /* IEEE 128-bit float h/w. */
2338 #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \
2340 | RS6000_BTM_P8_VECTOR \
2341 | RS6000_BTM_P9_VECTOR \
2342 | RS6000_BTM_P9_MISC \
2343 | RS6000_BTM_MODULO \
2344 | RS6000_BTM_CRYPTO \
2347 | RS6000_BTM_FRSQRTE \
2348 | RS6000_BTM_FRSQRTES \
2350 | RS6000_BTM_POPCNTD \
2353 | RS6000_BTM_HARD_FLOAT \
2354 | RS6000_BTM_LDBL128 \
2355 | RS6000_BTM_POWERPC64 \
2356 | RS6000_BTM_FLOAT128 \
2357 | RS6000_BTM_FLOAT128_HW)
2359 /* Define builtin enum index. */
2361 #undef RS6000_BUILTIN_0
2362 #undef RS6000_BUILTIN_1
2363 #undef RS6000_BUILTIN_2
2364 #undef RS6000_BUILTIN_3
2365 #undef RS6000_BUILTIN_A
2366 #undef RS6000_BUILTIN_D
2367 #undef RS6000_BUILTIN_H
2368 #undef RS6000_BUILTIN_P
2369 #undef RS6000_BUILTIN_X
2371 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2372 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2373 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2374 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2375 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2376 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2377 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2378 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2379 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2381 enum rs6000_builtins
2383 #include "rs6000-builtin.def"
2385 RS6000_BUILTIN_COUNT
2388 #undef RS6000_BUILTIN_0
2389 #undef RS6000_BUILTIN_1
2390 #undef RS6000_BUILTIN_2
2391 #undef RS6000_BUILTIN_3
2392 #undef RS6000_BUILTIN_A
2393 #undef RS6000_BUILTIN_D
2394 #undef RS6000_BUILTIN_H
2395 #undef RS6000_BUILTIN_P
2396 #undef RS6000_BUILTIN_X
2398 enum rs6000_builtin_type_index
2400 RS6000_BTI_NOT_OPAQUE
,
2401 RS6000_BTI_opaque_V4SI
,
2402 RS6000_BTI_V16QI
, /* __vector signed char */
2410 RS6000_BTI_unsigned_V16QI
, /* __vector unsigned char */
2411 RS6000_BTI_unsigned_V1TI
,
2412 RS6000_BTI_unsigned_V8HI
,
2413 RS6000_BTI_unsigned_V4SI
,
2414 RS6000_BTI_unsigned_V2DI
,
2415 RS6000_BTI_bool_char
, /* __bool char */
2416 RS6000_BTI_bool_short
, /* __bool short */
2417 RS6000_BTI_bool_int
, /* __bool int */
2418 RS6000_BTI_bool_long_long
, /* __bool long long */
2419 RS6000_BTI_pixel
, /* __pixel (16 bits arranged as 4
2420 channels of 1, 5, 5, and 5 bits
2421 respectively as packed with the
2422 vpkpx insn. __pixel is only
2423 meaningful as a vector type.
2424 There is no corresponding scalar
2425 __pixel data type.) */
2426 RS6000_BTI_bool_V16QI
, /* __vector __bool char */
2427 RS6000_BTI_bool_V8HI
, /* __vector __bool short */
2428 RS6000_BTI_bool_V4SI
, /* __vector __bool int */
2429 RS6000_BTI_bool_V2DI
, /* __vector __bool long */
2430 RS6000_BTI_pixel_V8HI
, /* __vector __pixel */
2431 RS6000_BTI_long
, /* long_integer_type_node */
2432 RS6000_BTI_unsigned_long
, /* long_unsigned_type_node */
2433 RS6000_BTI_long_long
, /* long_long_integer_type_node */
2434 RS6000_BTI_unsigned_long_long
, /* long_long_unsigned_type_node */
2435 RS6000_BTI_INTQI
, /* (signed) intQI_type_node */
2436 RS6000_BTI_UINTQI
, /* unsigned_intQI_type_node */
2437 RS6000_BTI_INTHI
, /* intHI_type_node */
2438 RS6000_BTI_UINTHI
, /* unsigned_intHI_type_node */
2439 RS6000_BTI_INTSI
, /* intSI_type_node (signed) */
2440 RS6000_BTI_UINTSI
, /* unsigned_intSI_type_node */
2441 RS6000_BTI_INTDI
, /* intDI_type_node */
2442 RS6000_BTI_UINTDI
, /* unsigned_intDI_type_node */
2443 RS6000_BTI_INTTI
, /* intTI_type_node */
2444 RS6000_BTI_UINTTI
, /* unsigned_intTI_type_node */
2445 RS6000_BTI_float
, /* float_type_node */
2446 RS6000_BTI_double
, /* double_type_node */
2447 RS6000_BTI_long_double
, /* long_double_type_node */
2448 RS6000_BTI_dfloat64
, /* dfloat64_type_node */
2449 RS6000_BTI_dfloat128
, /* dfloat128_type_node */
2450 RS6000_BTI_void
, /* void_type_node */
2451 RS6000_BTI_ieee128_float
, /* ieee 128-bit floating point */
2452 RS6000_BTI_ibm128_float
, /* IBM 128-bit floating point */
2453 RS6000_BTI_const_str
, /* pointer to const char * */
2458 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
2459 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])
2460 #define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI])
2461 #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI])
2462 #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF])
2463 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI])
2464 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI])
2465 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])
2466 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI])
2467 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])
2468 #define unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V1TI])
2469 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])
2470 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])
2471 #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI])
2472 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char])
2473 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short])
2474 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int])
2475 #define bool_long_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long_long])
2476 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel])
2477 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI])
2478 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
2479 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
2480 #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI])
2481 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
2483 #define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long])
2484 #define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long])
2485 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long])
2486 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long])
2487 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI])
2488 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI])
2489 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI])
2490 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI])
2491 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI])
2492 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI])
2493 #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI])
2494 #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI])
2495 #define intTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTTI])
2496 #define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI])
2497 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float])
2498 #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double])
2499 #define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double])
2500 #define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64])
2501 #define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128])
2502 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])
2503 #define ieee128_float_type_node (rs6000_builtin_types[RS6000_BTI_ieee128_float])
2504 #define ibm128_float_type_node (rs6000_builtin_types[RS6000_BTI_ibm128_float])
2505 #define const_str_type_node (rs6000_builtin_types[RS6000_BTI_const_str])
2507 extern GTY(()) tree rs6000_builtin_types
[RS6000_BTI_MAX
];
2508 extern GTY(()) tree rs6000_builtin_decls
[RS6000_BUILTIN_COUNT
];
2510 #define TARGET_SUPPORTS_WIDE_INT 1
2512 #if (GCC_VERSION >= 3000)
2513 #pragma GCC poison TARGET_FLOAT128 OPTION_MASK_FLOAT128 MASK_FLOAT128