1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 3, or (at your
12 ;; option) any later version.
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
43 (FIRST_ALTIVEC_REGNO 77)
44 (LAST_ALTIVEC_REGNO 108)
57 [(UNSPEC_FRSP 0) ; frsp for POWER machines
58 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
59 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
60 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
62 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
68 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
69 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
72 (UNSPEC_MOVESI_FROM_CR 19)
73 (UNSPEC_MOVESI_TO_CR 20)
75 (UNSPEC_TLSDTPRELHA 22)
76 (UNSPEC_TLSDTPRELLO 23)
77 (UNSPEC_TLSGOTDTPREL 24)
79 (UNSPEC_TLSTPRELHA 26)
80 (UNSPEC_TLSTPRELLO 27)
81 (UNSPEC_TLSGOTTPREL 28)
83 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
84 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
100 (UNSPEC_DLMZB_STRLEN 47)
103 (UNSPEC_MACHOPIC_OFFSET 50)
107 ;; UNSPEC_VOLATILE usage
112 (UNSPECV_LL 1) ; load-locked
113 (UNSPECV_SC 2) ; store-conditional
114 (UNSPECV_EH_RR 9) ; eh_reg_restore
117 ;; Define an insn type attribute. This is used in function unit delay
119 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr"
120 (const_string "integer"))
122 ;; Define floating point instruction sub-types for use with Xfpu.md
123 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
125 ;; Length (in bytes).
126 ; '(pc)' in the following doesn't include the instruction itself; it is
127 ; calculated as if the instruction had zero size.
128 (define_attr "length" ""
129 (if_then_else (eq_attr "type" "branch")
130 (if_then_else (and (ge (minus (match_dup 0) (pc))
132 (lt (minus (match_dup 0) (pc))
138 ;; Processor type -- this attribute must exactly match the processor_type
139 ;; enumeration in rs6000.h.
141 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,power4,power5,power6,power7,cell"
142 (const (symbol_ref "rs6000_cpu_attr")))
145 ;; If this instruction is microcoded on the CELL processor
146 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
147 (define_attr "cell_micro" "not,conditional,always"
148 (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
149 (const_string "always")
150 (const_string "not")))
152 (automata_option "ndfa")
165 (include "e300c2c3.md")
166 (include "e500mc.md")
167 (include "power4.md")
168 (include "power5.md")
169 (include "power6.md")
173 (include "predicates.md")
174 (include "constraints.md")
176 (include "darwin.md")
181 ; This mode iterator allows :GPR to be used to indicate the allowable size
182 ; of whole values in GPRs.
183 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
185 ; Any supported integer mode.
186 (define_mode_iterator INT [QI HI SI DI TI])
188 ; Any supported integer mode that fits in one register.
189 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
191 ; extend modes for DImode
192 (define_mode_iterator QHSI [QI HI SI])
194 ; SImode or DImode, even if DImode doesn't fit in GPRs.
195 (define_mode_iterator SDI [SI DI])
197 ; The size of a pointer. Also, the size of the value that a record-condition
198 ; (one with a '.') will compare.
199 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
201 ; Any hardware-supported floating-point mode
202 (define_mode_iterator FP [
203 (SF "TARGET_HARD_FLOAT
204 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
205 (DF "TARGET_HARD_FLOAT
206 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
207 (TF "!TARGET_IEEEQUAD
209 && (TARGET_FPRS || TARGET_E500_DOUBLE)
210 && TARGET_LONG_DOUBLE_128")
214 ; Various instructions that come in SI and DI forms.
215 ; A generic w/d attribute, for things like cmpw/cmpd.
216 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
219 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
221 ;; ISEL/ISEL64 target selection
222 (define_mode_attr sel [(SI "") (DI "64")])
224 ;; Suffix for reload patterns
225 (define_mode_attr ptrsize [(SI "32bit")
228 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
229 (DI "TARGET_64BIT")])
231 (define_mode_attr mptrsize [(SI "si")
235 ;; Start with fixed-point load and store insns. Here we put only the more
236 ;; complex forms. Basic data transfer is done later.
238 (define_expand "zero_extend<mode>di2"
239 [(set (match_operand:DI 0 "gpc_reg_operand" "")
240 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
244 (define_insn "*zero_extend<mode>di2_internal1"
245 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
246 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
250 rldicl %0,%1,0,<dbits>"
251 [(set_attr "type" "load,*")])
253 (define_insn "*zero_extend<mode>di2_internal2"
254 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
255 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
257 (clobber (match_scratch:DI 2 "=r,r"))]
260 rldicl. %2,%1,0,<dbits>
262 [(set_attr "type" "compare")
263 (set_attr "length" "4,8")])
266 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
267 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
269 (clobber (match_scratch:DI 2 ""))]
270 "TARGET_POWERPC64 && reload_completed"
272 (zero_extend:DI (match_dup 1)))
274 (compare:CC (match_dup 2)
278 (define_insn "*zero_extend<mode>di2_internal3"
279 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
280 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
282 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
283 (zero_extend:DI (match_dup 1)))]
286 rldicl. %0,%1,0,<dbits>
288 [(set_attr "type" "compare")
289 (set_attr "length" "4,8")])
292 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
293 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
295 (set (match_operand:DI 0 "gpc_reg_operand" "")
296 (zero_extend:DI (match_dup 1)))]
297 "TARGET_POWERPC64 && reload_completed"
299 (zero_extend:DI (match_dup 1)))
301 (compare:CC (match_dup 0)
305 (define_insn "extendqidi2"
306 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
307 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
310 [(set_attr "type" "exts")])
313 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
314 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
316 (clobber (match_scratch:DI 2 "=r,r"))]
321 [(set_attr "type" "compare")
322 (set_attr "length" "4,8")])
325 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
326 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
328 (clobber (match_scratch:DI 2 ""))]
329 "TARGET_POWERPC64 && reload_completed"
331 (sign_extend:DI (match_dup 1)))
333 (compare:CC (match_dup 2)
338 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
339 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
341 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
342 (sign_extend:DI (match_dup 1)))]
347 [(set_attr "type" "compare")
348 (set_attr "length" "4,8")])
351 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
352 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
354 (set (match_operand:DI 0 "gpc_reg_operand" "")
355 (sign_extend:DI (match_dup 1)))]
356 "TARGET_POWERPC64 && reload_completed"
358 (sign_extend:DI (match_dup 1)))
360 (compare:CC (match_dup 0)
364 (define_expand "extendhidi2"
365 [(set (match_operand:DI 0 "gpc_reg_operand" "")
366 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
371 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
372 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
373 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
377 [(set_attr "type" "load_ext,exts")])
380 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
381 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
382 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
384 [(set_attr "type" "exts")])
387 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
388 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
390 (clobber (match_scratch:DI 2 "=r,r"))]
395 [(set_attr "type" "compare")
396 (set_attr "length" "4,8")])
399 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
400 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
402 (clobber (match_scratch:DI 2 ""))]
403 "TARGET_POWERPC64 && reload_completed"
405 (sign_extend:DI (match_dup 1)))
407 (compare:CC (match_dup 2)
412 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
413 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
415 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
416 (sign_extend:DI (match_dup 1)))]
421 [(set_attr "type" "compare")
422 (set_attr "length" "4,8")])
425 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
426 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
428 (set (match_operand:DI 0 "gpc_reg_operand" "")
429 (sign_extend:DI (match_dup 1)))]
430 "TARGET_POWERPC64 && reload_completed"
432 (sign_extend:DI (match_dup 1)))
434 (compare:CC (match_dup 0)
438 (define_expand "extendsidi2"
439 [(set (match_operand:DI 0 "gpc_reg_operand" "")
440 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
445 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
446 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
447 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
451 [(set_attr "type" "load_ext,exts")])
454 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
455 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
456 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
458 [(set_attr "type" "exts")])
461 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
462 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
464 (clobber (match_scratch:DI 2 "=r,r"))]
469 [(set_attr "type" "compare")
470 (set_attr "length" "4,8")])
473 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
474 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
476 (clobber (match_scratch:DI 2 ""))]
477 "TARGET_POWERPC64 && reload_completed"
479 (sign_extend:DI (match_dup 1)))
481 (compare:CC (match_dup 2)
486 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
487 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
489 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
490 (sign_extend:DI (match_dup 1)))]
495 [(set_attr "type" "compare")
496 (set_attr "length" "4,8")])
499 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
500 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
502 (set (match_operand:DI 0 "gpc_reg_operand" "")
503 (sign_extend:DI (match_dup 1)))]
504 "TARGET_POWERPC64 && reload_completed"
506 (sign_extend:DI (match_dup 1)))
508 (compare:CC (match_dup 0)
512 (define_expand "zero_extendqisi2"
513 [(set (match_operand:SI 0 "gpc_reg_operand" "")
514 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
519 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
520 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
524 {rlinm|rlwinm} %0,%1,0,0xff"
525 [(set_attr "type" "load,*")])
528 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
529 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
531 (clobber (match_scratch:SI 2 "=r,r"))]
534 {andil.|andi.} %2,%1,0xff
536 [(set_attr "type" "fast_compare,compare")
537 (set_attr "length" "4,8")])
540 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
541 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
543 (clobber (match_scratch:SI 2 ""))]
546 (zero_extend:SI (match_dup 1)))
548 (compare:CC (match_dup 2)
553 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
554 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
556 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
557 (zero_extend:SI (match_dup 1)))]
560 {andil.|andi.} %0,%1,0xff
562 [(set_attr "type" "fast_compare,compare")
563 (set_attr "length" "4,8")])
566 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
567 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
569 (set (match_operand:SI 0 "gpc_reg_operand" "")
570 (zero_extend:SI (match_dup 1)))]
573 (zero_extend:SI (match_dup 1)))
575 (compare:CC (match_dup 0)
579 (define_expand "extendqisi2"
580 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
581 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
586 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
587 else if (TARGET_POWER)
588 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
590 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
594 (define_insn "extendqisi2_ppc"
595 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
596 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
599 [(set_attr "type" "exts")])
602 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
603 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
605 (clobber (match_scratch:SI 2 "=r,r"))]
610 [(set_attr "type" "compare")
611 (set_attr "length" "4,8")])
614 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
615 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
617 (clobber (match_scratch:SI 2 ""))]
618 "TARGET_POWERPC && reload_completed"
620 (sign_extend:SI (match_dup 1)))
622 (compare:CC (match_dup 2)
627 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
628 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
630 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
631 (sign_extend:SI (match_dup 1)))]
636 [(set_attr "type" "compare")
637 (set_attr "length" "4,8")])
640 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
641 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
643 (set (match_operand:SI 0 "gpc_reg_operand" "")
644 (sign_extend:SI (match_dup 1)))]
645 "TARGET_POWERPC && reload_completed"
647 (sign_extend:SI (match_dup 1)))
649 (compare:CC (match_dup 0)
653 (define_expand "extendqisi2_power"
654 [(parallel [(set (match_dup 2)
655 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
657 (clobber (scratch:SI))])
658 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
659 (ashiftrt:SI (match_dup 2)
661 (clobber (scratch:SI))])]
664 { operands[1] = gen_lowpart (SImode, operands[1]);
665 operands[2] = gen_reg_rtx (SImode); }")
667 (define_expand "extendqisi2_no_power"
669 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
671 (set (match_operand:SI 0 "gpc_reg_operand" "")
672 (ashiftrt:SI (match_dup 2)
674 "! TARGET_POWER && ! TARGET_POWERPC"
676 { operands[1] = gen_lowpart (SImode, operands[1]);
677 operands[2] = gen_reg_rtx (SImode); }")
679 (define_expand "zero_extendqihi2"
680 [(set (match_operand:HI 0 "gpc_reg_operand" "")
681 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
686 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
687 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
691 {rlinm|rlwinm} %0,%1,0,0xff"
692 [(set_attr "type" "load,*")])
695 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
696 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
698 (clobber (match_scratch:HI 2 "=r,r"))]
701 {andil.|andi.} %2,%1,0xff
703 [(set_attr "type" "fast_compare,compare")
704 (set_attr "length" "4,8")])
707 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
708 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
710 (clobber (match_scratch:HI 2 ""))]
713 (zero_extend:HI (match_dup 1)))
715 (compare:CC (match_dup 2)
720 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
721 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
723 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
724 (zero_extend:HI (match_dup 1)))]
727 {andil.|andi.} %0,%1,0xff
729 [(set_attr "type" "fast_compare,compare")
730 (set_attr "length" "4,8")])
733 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
734 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
736 (set (match_operand:HI 0 "gpc_reg_operand" "")
737 (zero_extend:HI (match_dup 1)))]
740 (zero_extend:HI (match_dup 1)))
742 (compare:CC (match_dup 0)
746 (define_expand "extendqihi2"
747 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
748 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
753 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
754 else if (TARGET_POWER)
755 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
757 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
761 (define_insn "extendqihi2_ppc"
762 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
763 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
766 [(set_attr "type" "exts")])
769 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
770 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
772 (clobber (match_scratch:HI 2 "=r,r"))]
777 [(set_attr "type" "compare")
778 (set_attr "length" "4,8")])
781 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
782 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
784 (clobber (match_scratch:HI 2 ""))]
785 "TARGET_POWERPC && reload_completed"
787 (sign_extend:HI (match_dup 1)))
789 (compare:CC (match_dup 2)
794 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
795 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
797 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
798 (sign_extend:HI (match_dup 1)))]
803 [(set_attr "type" "compare")
804 (set_attr "length" "4,8")])
807 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
808 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
810 (set (match_operand:HI 0 "gpc_reg_operand" "")
811 (sign_extend:HI (match_dup 1)))]
812 "TARGET_POWERPC && reload_completed"
814 (sign_extend:HI (match_dup 1)))
816 (compare:CC (match_dup 0)
820 (define_expand "extendqihi2_power"
821 [(parallel [(set (match_dup 2)
822 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
824 (clobber (scratch:SI))])
825 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
826 (ashiftrt:SI (match_dup 2)
828 (clobber (scratch:SI))])]
831 { operands[0] = gen_lowpart (SImode, operands[0]);
832 operands[1] = gen_lowpart (SImode, operands[1]);
833 operands[2] = gen_reg_rtx (SImode); }")
835 (define_expand "extendqihi2_no_power"
837 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
839 (set (match_operand:HI 0 "gpc_reg_operand" "")
840 (ashiftrt:SI (match_dup 2)
842 "! TARGET_POWER && ! TARGET_POWERPC"
844 { operands[0] = gen_lowpart (SImode, operands[0]);
845 operands[1] = gen_lowpart (SImode, operands[1]);
846 operands[2] = gen_reg_rtx (SImode); }")
848 (define_expand "zero_extendhisi2"
849 [(set (match_operand:SI 0 "gpc_reg_operand" "")
850 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
855 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
856 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
860 {rlinm|rlwinm} %0,%1,0,0xffff"
861 [(set_attr "type" "load,*")])
864 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
865 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
867 (clobber (match_scratch:SI 2 "=r,r"))]
870 {andil.|andi.} %2,%1,0xffff
872 [(set_attr "type" "fast_compare,compare")
873 (set_attr "length" "4,8")])
876 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
877 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
879 (clobber (match_scratch:SI 2 ""))]
882 (zero_extend:SI (match_dup 1)))
884 (compare:CC (match_dup 2)
889 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
890 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
892 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
893 (zero_extend:SI (match_dup 1)))]
896 {andil.|andi.} %0,%1,0xffff
898 [(set_attr "type" "fast_compare,compare")
899 (set_attr "length" "4,8")])
902 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
903 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
905 (set (match_operand:SI 0 "gpc_reg_operand" "")
906 (zero_extend:SI (match_dup 1)))]
909 (zero_extend:SI (match_dup 1)))
911 (compare:CC (match_dup 0)
915 (define_expand "extendhisi2"
916 [(set (match_operand:SI 0 "gpc_reg_operand" "")
917 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
922 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
923 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
924 "rs6000_gen_cell_microcode"
928 [(set_attr "type" "load_ext,exts")])
931 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
932 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
933 "!rs6000_gen_cell_microcode"
935 [(set_attr "type" "exts")])
938 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
939 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
941 (clobber (match_scratch:SI 2 "=r,r"))]
946 [(set_attr "type" "compare")
947 (set_attr "length" "4,8")])
950 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
951 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
953 (clobber (match_scratch:SI 2 ""))]
956 (sign_extend:SI (match_dup 1)))
958 (compare:CC (match_dup 2)
963 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
964 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
966 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
967 (sign_extend:SI (match_dup 1)))]
972 [(set_attr "type" "compare")
973 (set_attr "length" "4,8")])
975 ;; IBM 405, 440 and 464 half-word multiplication operations.
977 (define_insn "*macchwc"
978 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
979 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
980 (match_operand:SI 2 "gpc_reg_operand" "r")
983 (match_operand:HI 1 "gpc_reg_operand" "r")))
984 (match_operand:SI 4 "gpc_reg_operand" "0"))
986 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
987 (plus:SI (mult:SI (ashiftrt:SI
995 [(set_attr "type" "imul3")])
997 (define_insn "*macchw"
998 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
999 (plus:SI (mult:SI (ashiftrt:SI
1000 (match_operand:SI 2 "gpc_reg_operand" "r")
1003 (match_operand:HI 1 "gpc_reg_operand" "r")))
1004 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1007 [(set_attr "type" "imul3")])
1009 (define_insn "*macchwuc"
1010 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1011 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1012 (match_operand:SI 2 "gpc_reg_operand" "r")
1015 (match_operand:HI 1 "gpc_reg_operand" "r")))
1016 (match_operand:SI 4 "gpc_reg_operand" "0"))
1018 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1019 (plus:SI (mult:SI (lshiftrt:SI
1026 "macchwu. %0, %1, %2"
1027 [(set_attr "type" "imul3")])
1029 (define_insn "*macchwu"
1030 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1031 (plus:SI (mult:SI (lshiftrt:SI
1032 (match_operand:SI 2 "gpc_reg_operand" "r")
1035 (match_operand:HI 1 "gpc_reg_operand" "r")))
1036 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1038 "macchwu %0, %1, %2"
1039 [(set_attr "type" "imul3")])
1041 (define_insn "*machhwc"
1042 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1043 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1044 (match_operand:SI 1 "gpc_reg_operand" "%r")
1047 (match_operand:SI 2 "gpc_reg_operand" "r")
1049 (match_operand:SI 4 "gpc_reg_operand" "0"))
1051 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1052 (plus:SI (mult:SI (ashiftrt:SI
1060 "machhw. %0, %1, %2"
1061 [(set_attr "type" "imul3")])
1063 (define_insn "*machhw"
1064 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1065 (plus:SI (mult:SI (ashiftrt:SI
1066 (match_operand:SI 1 "gpc_reg_operand" "%r")
1069 (match_operand:SI 2 "gpc_reg_operand" "r")
1071 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1074 [(set_attr "type" "imul3")])
1076 (define_insn "*machhwuc"
1077 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1078 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1079 (match_operand:SI 1 "gpc_reg_operand" "%r")
1082 (match_operand:SI 2 "gpc_reg_operand" "r")
1084 (match_operand:SI 4 "gpc_reg_operand" "0"))
1086 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1087 (plus:SI (mult:SI (lshiftrt:SI
1095 "machhwu. %0, %1, %2"
1096 [(set_attr "type" "imul3")])
1098 (define_insn "*machhwu"
1099 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1100 (plus:SI (mult:SI (lshiftrt:SI
1101 (match_operand:SI 1 "gpc_reg_operand" "%r")
1104 (match_operand:SI 2 "gpc_reg_operand" "r")
1106 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1108 "machhwu %0, %1, %2"
1109 [(set_attr "type" "imul3")])
1111 (define_insn "*maclhwc"
1112 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1113 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1114 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1116 (match_operand:HI 2 "gpc_reg_operand" "r")))
1117 (match_operand:SI 4 "gpc_reg_operand" "0"))
1119 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1120 (plus:SI (mult:SI (sign_extend:SI
1126 "maclhw. %0, %1, %2"
1127 [(set_attr "type" "imul3")])
1129 (define_insn "*maclhw"
1130 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1131 (plus:SI (mult:SI (sign_extend:SI
1132 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1134 (match_operand:HI 2 "gpc_reg_operand" "r")))
1135 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1138 [(set_attr "type" "imul3")])
1140 (define_insn "*maclhwuc"
1141 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1142 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1143 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1145 (match_operand:HI 2 "gpc_reg_operand" "r")))
1146 (match_operand:SI 4 "gpc_reg_operand" "0"))
1148 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1149 (plus:SI (mult:SI (zero_extend:SI
1155 "maclhwu. %0, %1, %2"
1156 [(set_attr "type" "imul3")])
1158 (define_insn "*maclhwu"
1159 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1160 (plus:SI (mult:SI (zero_extend:SI
1161 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1163 (match_operand:HI 2 "gpc_reg_operand" "r")))
1164 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1166 "maclhwu %0, %1, %2"
1167 [(set_attr "type" "imul3")])
1169 (define_insn "*nmacchwc"
1170 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1171 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1172 (mult:SI (ashiftrt:SI
1173 (match_operand:SI 2 "gpc_reg_operand" "r")
1176 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1178 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1179 (minus:SI (match_dup 4)
1180 (mult:SI (ashiftrt:SI
1186 "nmacchw. %0, %1, %2"
1187 [(set_attr "type" "imul3")])
1189 (define_insn "*nmacchw"
1190 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1191 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1192 (mult:SI (ashiftrt:SI
1193 (match_operand:SI 2 "gpc_reg_operand" "r")
1196 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1198 "nmacchw %0, %1, %2"
1199 [(set_attr "type" "imul3")])
1201 (define_insn "*nmachhwc"
1202 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1203 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1204 (mult:SI (ashiftrt:SI
1205 (match_operand:SI 1 "gpc_reg_operand" "%r")
1208 (match_operand:SI 2 "gpc_reg_operand" "r")
1211 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1212 (minus:SI (match_dup 4)
1213 (mult:SI (ashiftrt:SI
1220 "nmachhw. %0, %1, %2"
1221 [(set_attr "type" "imul3")])
1223 (define_insn "*nmachhw"
1224 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1225 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1226 (mult:SI (ashiftrt:SI
1227 (match_operand:SI 1 "gpc_reg_operand" "%r")
1230 (match_operand:SI 2 "gpc_reg_operand" "r")
1233 "nmachhw %0, %1, %2"
1234 [(set_attr "type" "imul3")])
1236 (define_insn "*nmaclhwc"
1237 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1238 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1239 (mult:SI (sign_extend:SI
1240 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1242 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1244 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1245 (minus:SI (match_dup 4)
1246 (mult:SI (sign_extend:SI
1251 "nmaclhw. %0, %1, %2"
1252 [(set_attr "type" "imul3")])
1254 (define_insn "*nmaclhw"
1255 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1256 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1257 (mult:SI (sign_extend:SI
1258 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1260 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1262 "nmaclhw %0, %1, %2"
1263 [(set_attr "type" "imul3")])
1265 (define_insn "*mulchwc"
1266 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1267 (compare:CC (mult:SI (ashiftrt:SI
1268 (match_operand:SI 2 "gpc_reg_operand" "r")
1271 (match_operand:HI 1 "gpc_reg_operand" "r")))
1273 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1274 (mult:SI (ashiftrt:SI
1280 "mulchw. %0, %1, %2"
1281 [(set_attr "type" "imul3")])
1283 (define_insn "*mulchw"
1284 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1285 (mult:SI (ashiftrt:SI
1286 (match_operand:SI 2 "gpc_reg_operand" "r")
1289 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1292 [(set_attr "type" "imul3")])
1294 (define_insn "*mulchwuc"
1295 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1296 (compare:CC (mult:SI (lshiftrt:SI
1297 (match_operand:SI 2 "gpc_reg_operand" "r")
1300 (match_operand:HI 1 "gpc_reg_operand" "r")))
1302 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1303 (mult:SI (lshiftrt:SI
1309 "mulchwu. %0, %1, %2"
1310 [(set_attr "type" "imul3")])
1312 (define_insn "*mulchwu"
1313 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1314 (mult:SI (lshiftrt:SI
1315 (match_operand:SI 2 "gpc_reg_operand" "r")
1318 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1320 "mulchwu %0, %1, %2"
1321 [(set_attr "type" "imul3")])
1323 (define_insn "*mulhhwc"
1324 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1325 (compare:CC (mult:SI (ashiftrt:SI
1326 (match_operand:SI 1 "gpc_reg_operand" "%r")
1329 (match_operand:SI 2 "gpc_reg_operand" "r")
1332 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1333 (mult:SI (ashiftrt:SI
1340 "mulhhw. %0, %1, %2"
1341 [(set_attr "type" "imul3")])
1343 (define_insn "*mulhhw"
1344 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1345 (mult:SI (ashiftrt:SI
1346 (match_operand:SI 1 "gpc_reg_operand" "%r")
1349 (match_operand:SI 2 "gpc_reg_operand" "r")
1353 [(set_attr "type" "imul3")])
1355 (define_insn "*mulhhwuc"
1356 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1357 (compare:CC (mult:SI (lshiftrt:SI
1358 (match_operand:SI 1 "gpc_reg_operand" "%r")
1361 (match_operand:SI 2 "gpc_reg_operand" "r")
1364 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1365 (mult:SI (lshiftrt:SI
1372 "mulhhwu. %0, %1, %2"
1373 [(set_attr "type" "imul3")])
1375 (define_insn "*mulhhwu"
1376 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1377 (mult:SI (lshiftrt:SI
1378 (match_operand:SI 1 "gpc_reg_operand" "%r")
1381 (match_operand:SI 2 "gpc_reg_operand" "r")
1384 "mulhhwu %0, %1, %2"
1385 [(set_attr "type" "imul3")])
1387 (define_insn "*mullhwc"
1388 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1389 (compare:CC (mult:SI (sign_extend:SI
1390 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1392 (match_operand:HI 2 "gpc_reg_operand" "r")))
1394 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1395 (mult:SI (sign_extend:SI
1400 "mullhw. %0, %1, %2"
1401 [(set_attr "type" "imul3")])
1403 (define_insn "*mullhw"
1404 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1405 (mult:SI (sign_extend:SI
1406 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1408 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1411 [(set_attr "type" "imul3")])
1413 (define_insn "*mullhwuc"
1414 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1415 (compare:CC (mult:SI (zero_extend:SI
1416 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1418 (match_operand:HI 2 "gpc_reg_operand" "r")))
1420 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1421 (mult:SI (zero_extend:SI
1426 "mullhwu. %0, %1, %2"
1427 [(set_attr "type" "imul3")])
1429 (define_insn "*mullhwu"
1430 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1431 (mult:SI (zero_extend:SI
1432 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1434 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1436 "mullhwu %0, %1, %2"
1437 [(set_attr "type" "imul3")])
1439 ;; IBM 405, 440 and 464 string-search dlmzb instruction support.
1440 (define_insn "dlmzb"
1441 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1442 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1443 (match_operand:SI 2 "gpc_reg_operand" "r")]
1445 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1446 (unspec:SI [(match_dup 1)
1450 "dlmzb. %0, %1, %2")
1452 (define_expand "strlensi"
1453 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1454 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1455 (match_operand:QI 2 "const_int_operand" "")
1456 (match_operand 3 "const_int_operand" "")]
1457 UNSPEC_DLMZB_STRLEN))
1458 (clobber (match_scratch:CC 4 "=x"))]
1459 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1461 rtx result = operands[0];
1462 rtx src = operands[1];
1463 rtx search_char = operands[2];
1464 rtx align = operands[3];
1465 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1466 rtx loop_label, end_label, mem, cr0, cond;
1467 if (search_char != const0_rtx
1468 || GET_CODE (align) != CONST_INT
1469 || INTVAL (align) < 8)
1471 word1 = gen_reg_rtx (SImode);
1472 word2 = gen_reg_rtx (SImode);
1473 scratch_dlmzb = gen_reg_rtx (SImode);
1474 scratch_string = gen_reg_rtx (Pmode);
1475 loop_label = gen_label_rtx ();
1476 end_label = gen_label_rtx ();
1477 addr = force_reg (Pmode, XEXP (src, 0));
1478 emit_move_insn (scratch_string, addr);
1479 emit_label (loop_label);
1480 mem = change_address (src, SImode, scratch_string);
1481 emit_move_insn (word1, mem);
1482 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1483 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1484 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1485 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1486 emit_jump_insn (gen_rtx_SET (VOIDmode,
1488 gen_rtx_IF_THEN_ELSE (VOIDmode,
1494 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1495 emit_jump_insn (gen_rtx_SET (VOIDmode,
1497 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1499 emit_label (end_label);
1500 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1501 emit_insn (gen_subsi3 (result, scratch_string, addr));
1502 emit_insn (gen_subsi3 (result, result, const1_rtx));
1507 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1508 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1510 (set (match_operand:SI 0 "gpc_reg_operand" "")
1511 (sign_extend:SI (match_dup 1)))]
1514 (sign_extend:SI (match_dup 1)))
1516 (compare:CC (match_dup 0)
1520 ;; Fixed-point arithmetic insns.
1522 (define_expand "add<mode>3"
1523 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1524 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1525 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1528 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1530 if (non_short_cint_operand (operands[2], DImode))
1533 else if (GET_CODE (operands[2]) == CONST_INT
1534 && ! add_operand (operands[2], <MODE>mode))
1536 rtx tmp = ((!can_create_pseudo_p ()
1537 || rtx_equal_p (operands[0], operands[1]))
1538 ? operands[0] : gen_reg_rtx (<MODE>mode));
1540 HOST_WIDE_INT val = INTVAL (operands[2]);
1541 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1542 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1544 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1547 /* The ordering here is important for the prolog expander.
1548 When space is allocated from the stack, adding 'low' first may
1549 produce a temporary deallocation (which would be bad). */
1550 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1551 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1556 ;; Discourage ai/addic because of carry but provide it in an alternative
1557 ;; allowing register zero as source.
1558 (define_insn "*add<mode>3_internal1"
1559 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1560 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1561 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1562 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1565 {cal %0,%2(%1)|addi %0,%1,%2}
1567 {cau|addis} %0,%1,%v2"
1568 [(set_attr "length" "4,4,4,4")])
1570 (define_insn "addsi3_high"
1571 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1572 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1573 (high:SI (match_operand 2 "" ""))))]
1574 "TARGET_MACHO && !TARGET_64BIT"
1575 "{cau|addis} %0,%1,ha16(%2)"
1576 [(set_attr "length" "4")])
1578 (define_insn "*add<mode>3_internal2"
1579 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1580 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1581 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1583 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1586 {cax.|add.} %3,%1,%2
1587 {ai.|addic.} %3,%1,%2
1590 [(set_attr "type" "fast_compare,compare,compare,compare")
1591 (set_attr "length" "4,4,8,8")])
1594 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1595 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1596 (match_operand:GPR 2 "reg_or_short_operand" ""))
1598 (clobber (match_scratch:GPR 3 ""))]
1601 (plus:GPR (match_dup 1)
1604 (compare:CC (match_dup 3)
1608 (define_insn "*add<mode>3_internal3"
1609 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1610 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1611 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1613 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1614 (plus:P (match_dup 1)
1618 {cax.|add.} %0,%1,%2
1619 {ai.|addic.} %0,%1,%2
1622 [(set_attr "type" "fast_compare,compare,compare,compare")
1623 (set_attr "length" "4,4,8,8")])
1626 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1627 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1628 (match_operand:P 2 "reg_or_short_operand" ""))
1630 (set (match_operand:P 0 "gpc_reg_operand" "")
1631 (plus:P (match_dup 1) (match_dup 2)))]
1634 (plus:P (match_dup 1)
1637 (compare:CC (match_dup 0)
1641 ;; Split an add that we can't do in one insn into two insns, each of which
1642 ;; does one 16-bit part. This is used by combine. Note that the low-order
1643 ;; add should be last in case the result gets used in an address.
1646 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1647 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1648 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1650 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1651 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1653 HOST_WIDE_INT val = INTVAL (operands[2]);
1654 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1655 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1657 operands[4] = GEN_INT (low);
1658 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1659 operands[3] = GEN_INT (rest);
1660 else if (can_create_pseudo_p ())
1662 operands[3] = gen_reg_rtx (DImode);
1663 emit_move_insn (operands[3], operands[2]);
1664 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1671 (define_insn "one_cmpl<mode>2"
1672 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1673 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1678 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1679 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1681 (clobber (match_scratch:P 2 "=r,r"))]
1686 [(set_attr "type" "fast_compare,compare")
1687 (set_attr "length" "4,8")])
1690 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1691 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1693 (clobber (match_scratch:P 2 ""))]
1696 (not:P (match_dup 1)))
1698 (compare:CC (match_dup 2)
1703 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1704 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1706 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1707 (not:P (match_dup 1)))]
1712 [(set_attr "type" "fast_compare,compare")
1713 (set_attr "length" "4,8")])
1716 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1717 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1719 (set (match_operand:P 0 "gpc_reg_operand" "")
1720 (not:P (match_dup 1)))]
1723 (not:P (match_dup 1)))
1725 (compare:CC (match_dup 0)
1730 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1731 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1732 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1734 "{sf%I1|subf%I1c} %0,%2,%1")
1737 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1738 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1739 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1746 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1747 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1748 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1750 (clobber (match_scratch:SI 3 "=r,r"))]
1753 {sf.|subfc.} %3,%2,%1
1755 [(set_attr "type" "compare")
1756 (set_attr "length" "4,8")])
1759 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1760 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1761 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1763 (clobber (match_scratch:P 3 "=r,r"))]
1768 [(set_attr "type" "fast_compare")
1769 (set_attr "length" "4,8")])
1772 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1773 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1774 (match_operand:P 2 "gpc_reg_operand" ""))
1776 (clobber (match_scratch:P 3 ""))]
1779 (minus:P (match_dup 1)
1782 (compare:CC (match_dup 3)
1787 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1788 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1789 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1791 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1792 (minus:SI (match_dup 1) (match_dup 2)))]
1795 {sf.|subfc.} %0,%2,%1
1797 [(set_attr "type" "compare")
1798 (set_attr "length" "4,8")])
1801 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1802 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1803 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1805 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1806 (minus:P (match_dup 1)
1812 [(set_attr "type" "fast_compare")
1813 (set_attr "length" "4,8")])
1816 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1817 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1818 (match_operand:P 2 "gpc_reg_operand" ""))
1820 (set (match_operand:P 0 "gpc_reg_operand" "")
1821 (minus:P (match_dup 1)
1825 (minus:P (match_dup 1)
1828 (compare:CC (match_dup 0)
1832 (define_expand "sub<mode>3"
1833 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1834 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1835 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1839 if (GET_CODE (operands[2]) == CONST_INT)
1841 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1842 negate_rtx (<MODE>mode, operands[2])));
1847 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1848 ;; instruction and some auxiliary computations. Then we just have a single
1849 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1852 (define_expand "sminsi3"
1854 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1855 (match_operand:SI 2 "reg_or_short_operand" ""))
1857 (minus:SI (match_dup 2) (match_dup 1))))
1858 (set (match_operand:SI 0 "gpc_reg_operand" "")
1859 (minus:SI (match_dup 2) (match_dup 3)))]
1860 "TARGET_POWER || TARGET_ISEL"
1865 operands[2] = force_reg (SImode, operands[2]);
1866 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1870 operands[3] = gen_reg_rtx (SImode);
1874 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1875 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1876 (match_operand:SI 2 "reg_or_short_operand" "")))
1877 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1880 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1882 (minus:SI (match_dup 2) (match_dup 1))))
1883 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1886 (define_expand "smaxsi3"
1888 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1889 (match_operand:SI 2 "reg_or_short_operand" ""))
1891 (minus:SI (match_dup 2) (match_dup 1))))
1892 (set (match_operand:SI 0 "gpc_reg_operand" "")
1893 (plus:SI (match_dup 3) (match_dup 1)))]
1894 "TARGET_POWER || TARGET_ISEL"
1899 operands[2] = force_reg (SImode, operands[2]);
1900 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1903 operands[3] = gen_reg_rtx (SImode);
1907 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1908 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1909 (match_operand:SI 2 "reg_or_short_operand" "")))
1910 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1913 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1915 (minus:SI (match_dup 2) (match_dup 1))))
1916 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1919 (define_expand "uminsi3"
1920 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1922 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1924 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1926 (minus:SI (match_dup 4) (match_dup 3))))
1927 (set (match_operand:SI 0 "gpc_reg_operand" "")
1928 (minus:SI (match_dup 2) (match_dup 3)))]
1929 "TARGET_POWER || TARGET_ISEL"
1934 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1937 operands[3] = gen_reg_rtx (SImode);
1938 operands[4] = gen_reg_rtx (SImode);
1939 operands[5] = GEN_INT (-2147483647 - 1);
1942 (define_expand "umaxsi3"
1943 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1945 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1947 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1949 (minus:SI (match_dup 4) (match_dup 3))))
1950 (set (match_operand:SI 0 "gpc_reg_operand" "")
1951 (plus:SI (match_dup 3) (match_dup 1)))]
1952 "TARGET_POWER || TARGET_ISEL"
1957 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1960 operands[3] = gen_reg_rtx (SImode);
1961 operands[4] = gen_reg_rtx (SImode);
1962 operands[5] = GEN_INT (-2147483647 - 1);
1966 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1967 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1968 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1970 (minus:SI (match_dup 2) (match_dup 1))))]
1975 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1977 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1978 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1980 (minus:SI (match_dup 2) (match_dup 1)))
1982 (clobber (match_scratch:SI 3 "=r,r"))]
1987 [(set_attr "type" "delayed_compare")
1988 (set_attr "length" "4,8")])
1991 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1993 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1994 (match_operand:SI 2 "reg_or_short_operand" ""))
1996 (minus:SI (match_dup 2) (match_dup 1)))
1998 (clobber (match_scratch:SI 3 ""))]
1999 "TARGET_POWER && reload_completed"
2001 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2003 (minus:SI (match_dup 2) (match_dup 1))))
2005 (compare:CC (match_dup 3)
2010 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2012 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
2013 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
2015 (minus:SI (match_dup 2) (match_dup 1)))
2017 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2018 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2020 (minus:SI (match_dup 2) (match_dup 1))))]
2025 [(set_attr "type" "delayed_compare")
2026 (set_attr "length" "4,8")])
2029 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2031 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2032 (match_operand:SI 2 "reg_or_short_operand" ""))
2034 (minus:SI (match_dup 2) (match_dup 1)))
2036 (set (match_operand:SI 0 "gpc_reg_operand" "")
2037 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2039 (minus:SI (match_dup 2) (match_dup 1))))]
2040 "TARGET_POWER && reload_completed"
2042 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2044 (minus:SI (match_dup 2) (match_dup 1))))
2046 (compare:CC (match_dup 0)
2050 ;; We don't need abs with condition code because such comparisons should
2052 (define_expand "abssi2"
2053 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2054 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2060 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
2063 else if (! TARGET_POWER)
2065 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2070 (define_insn "*abssi2_power"
2071 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2072 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2076 (define_insn_and_split "abssi2_isel"
2077 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2078 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
2079 (clobber (match_scratch:SI 2 "=&b"))
2080 (clobber (match_scratch:CC 3 "=y"))]
2083 "&& reload_completed"
2084 [(set (match_dup 2) (neg:SI (match_dup 1)))
2086 (compare:CC (match_dup 1)
2089 (if_then_else:SI (ge (match_dup 3)
2095 (define_insn_and_split "abssi2_nopower"
2096 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2097 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2098 (clobber (match_scratch:SI 2 "=&r,&r"))]
2099 "! TARGET_POWER && ! TARGET_ISEL"
2101 "&& reload_completed"
2102 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2103 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2104 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2107 (define_insn "*nabs_power"
2108 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2109 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2113 (define_insn_and_split "*nabs_nopower"
2114 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2115 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2116 (clobber (match_scratch:SI 2 "=&r,&r"))]
2119 "&& reload_completed"
2120 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2121 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2122 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2125 (define_expand "neg<mode>2"
2126 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2127 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2131 (define_insn "*neg<mode>2_internal"
2132 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2133 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2138 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2139 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2141 (clobber (match_scratch:P 2 "=r,r"))]
2146 [(set_attr "type" "fast_compare")
2147 (set_attr "length" "4,8")])
2150 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2151 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2153 (clobber (match_scratch:P 2 ""))]
2156 (neg:P (match_dup 1)))
2158 (compare:CC (match_dup 2)
2163 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2164 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2166 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2167 (neg:P (match_dup 1)))]
2172 [(set_attr "type" "fast_compare")
2173 (set_attr "length" "4,8")])
2176 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2177 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2179 (set (match_operand:P 0 "gpc_reg_operand" "")
2180 (neg:P (match_dup 1)))]
2183 (neg:P (match_dup 1)))
2185 (compare:CC (match_dup 0)
2189 (define_insn "clz<mode>2"
2190 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2191 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2193 "{cntlz|cntlz<wd>} %0,%1"
2194 [(set_attr "type" "cntlz")])
2196 (define_expand "ctz<mode>2"
2198 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2199 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2201 (clobber (scratch:CC))])
2202 (set (match_dup 4) (clz:GPR (match_dup 3)))
2203 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2204 (minus:GPR (match_dup 5) (match_dup 4)))]
2207 operands[2] = gen_reg_rtx (<MODE>mode);
2208 operands[3] = gen_reg_rtx (<MODE>mode);
2209 operands[4] = gen_reg_rtx (<MODE>mode);
2210 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2213 (define_expand "ffs<mode>2"
2215 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2216 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2218 (clobber (scratch:CC))])
2219 (set (match_dup 4) (clz:GPR (match_dup 3)))
2220 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2221 (minus:GPR (match_dup 5) (match_dup 4)))]
2224 operands[2] = gen_reg_rtx (<MODE>mode);
2225 operands[3] = gen_reg_rtx (<MODE>mode);
2226 operands[4] = gen_reg_rtx (<MODE>mode);
2227 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2230 (define_insn "popcntb<mode>2"
2231 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2232 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2237 (define_insn "popcntwsi2"
2238 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2239 (popcount:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2243 (define_insn "popcntddi2"
2244 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2245 (popcount:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
2246 "TARGET_POPCNTD && TARGET_POWERPC64"
2249 (define_expand "popcount<mode>2"
2250 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2251 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2252 "TARGET_POPCNTB || TARGET_POPCNTD"
2254 rs6000_emit_popcount (operands[0], operands[1]);
2258 (define_expand "parity<mode>2"
2259 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2260 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2263 rs6000_emit_parity (operands[0], operands[1]);
2267 (define_insn "bswapsi2"
2268 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2269 (bswap:SI (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2273 {stbrx|stwbrx} %1,%y0
2275 [(set_attr "length" "4,4,12")])
2278 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2279 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2282 (rotate:SI (match_dup 1) (const_int 8)))
2283 (set (zero_extract:SI (match_dup 0)
2287 (set (zero_extract:SI (match_dup 0)
2290 (rotate:SI (match_dup 1)
2294 (define_expand "mulsi3"
2295 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2296 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2297 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2302 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2304 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2308 (define_insn "mulsi3_mq"
2309 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2310 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2311 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2312 (clobber (match_scratch:SI 3 "=q,q"))]
2315 {muls|mullw} %0,%1,%2
2316 {muli|mulli} %0,%1,%2"
2318 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2319 (const_string "imul3")
2320 (match_operand:SI 2 "short_cint_operand" "")
2321 (const_string "imul2")]
2322 (const_string "imul")))])
2324 (define_insn "mulsi3_no_mq"
2325 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2326 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2327 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2330 {muls|mullw} %0,%1,%2
2331 {muli|mulli} %0,%1,%2"
2333 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2334 (const_string "imul3")
2335 (match_operand:SI 2 "short_cint_operand" "")
2336 (const_string "imul2")]
2337 (const_string "imul")))])
2339 (define_insn "*mulsi3_mq_internal1"
2340 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2341 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2342 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2344 (clobber (match_scratch:SI 3 "=r,r"))
2345 (clobber (match_scratch:SI 4 "=q,q"))]
2348 {muls.|mullw.} %3,%1,%2
2350 [(set_attr "type" "imul_compare")
2351 (set_attr "length" "4,8")])
2354 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2355 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2356 (match_operand:SI 2 "gpc_reg_operand" ""))
2358 (clobber (match_scratch:SI 3 ""))
2359 (clobber (match_scratch:SI 4 ""))]
2360 "TARGET_POWER && reload_completed"
2361 [(parallel [(set (match_dup 3)
2362 (mult:SI (match_dup 1) (match_dup 2)))
2363 (clobber (match_dup 4))])
2365 (compare:CC (match_dup 3)
2369 (define_insn "*mulsi3_no_mq_internal1"
2370 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2371 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2372 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2374 (clobber (match_scratch:SI 3 "=r,r"))]
2377 {muls.|mullw.} %3,%1,%2
2379 [(set_attr "type" "imul_compare")
2380 (set_attr "length" "4,8")])
2383 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2384 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2385 (match_operand:SI 2 "gpc_reg_operand" ""))
2387 (clobber (match_scratch:SI 3 ""))]
2388 "! TARGET_POWER && reload_completed"
2390 (mult:SI (match_dup 1) (match_dup 2)))
2392 (compare:CC (match_dup 3)
2396 (define_insn "*mulsi3_mq_internal2"
2397 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2398 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2399 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2401 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2402 (mult:SI (match_dup 1) (match_dup 2)))
2403 (clobber (match_scratch:SI 4 "=q,q"))]
2406 {muls.|mullw.} %0,%1,%2
2408 [(set_attr "type" "imul_compare")
2409 (set_attr "length" "4,8")])
2412 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2413 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2414 (match_operand:SI 2 "gpc_reg_operand" ""))
2416 (set (match_operand:SI 0 "gpc_reg_operand" "")
2417 (mult:SI (match_dup 1) (match_dup 2)))
2418 (clobber (match_scratch:SI 4 ""))]
2419 "TARGET_POWER && reload_completed"
2420 [(parallel [(set (match_dup 0)
2421 (mult:SI (match_dup 1) (match_dup 2)))
2422 (clobber (match_dup 4))])
2424 (compare:CC (match_dup 0)
2428 (define_insn "*mulsi3_no_mq_internal2"
2429 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2430 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2431 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2433 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2434 (mult:SI (match_dup 1) (match_dup 2)))]
2437 {muls.|mullw.} %0,%1,%2
2439 [(set_attr "type" "imul_compare")
2440 (set_attr "length" "4,8")])
2443 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2444 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2445 (match_operand:SI 2 "gpc_reg_operand" ""))
2447 (set (match_operand:SI 0 "gpc_reg_operand" "")
2448 (mult:SI (match_dup 1) (match_dup 2)))]
2449 "! TARGET_POWER && reload_completed"
2451 (mult:SI (match_dup 1) (match_dup 2)))
2453 (compare:CC (match_dup 0)
2457 ;; Operand 1 is divided by operand 2; quotient goes to operand
2458 ;; 0 and remainder to operand 3.
2459 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2461 (define_expand "divmodsi4"
2462 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2463 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2464 (match_operand:SI 2 "gpc_reg_operand" "")))
2465 (set (match_operand:SI 3 "register_operand" "")
2466 (mod:SI (match_dup 1) (match_dup 2)))])]
2467 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2470 if (! TARGET_POWER && ! TARGET_POWERPC)
2472 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2473 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2474 emit_insn (gen_divss_call ());
2475 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2476 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2481 (define_insn "*divmodsi4_internal"
2482 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2483 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2484 (match_operand:SI 2 "gpc_reg_operand" "r")))
2485 (set (match_operand:SI 3 "register_operand" "=q")
2486 (mod:SI (match_dup 1) (match_dup 2)))]
2489 [(set_attr "type" "idiv")])
2491 (define_expand "udiv<mode>3"
2492 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2493 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2494 (match_operand:GPR 2 "gpc_reg_operand" "")))]
2495 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2498 if (! TARGET_POWER && ! TARGET_POWERPC)
2500 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2501 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2502 emit_insn (gen_quous_call ());
2503 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2506 else if (TARGET_POWER)
2508 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2513 (define_insn "udivsi3_mq"
2514 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2515 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2516 (match_operand:SI 2 "gpc_reg_operand" "r")))
2517 (clobber (match_scratch:SI 3 "=q"))]
2518 "TARGET_POWERPC && TARGET_POWER"
2520 [(set_attr "type" "idiv")])
2522 (define_insn "*udivsi3_no_mq"
2523 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2524 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2525 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2526 "TARGET_POWERPC && ! TARGET_POWER"
2529 (cond [(match_operand:SI 0 "" "")
2530 (const_string "idiv")]
2531 (const_string "ldiv")))])
2534 ;; For powers of two we can do srai/aze for divide and then adjust for
2535 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2536 ;; used; for PowerPC, force operands into register and do a normal divide;
2537 ;; for AIX common-mode, use quoss call on register operands.
2538 (define_expand "div<mode>3"
2539 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2540 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2541 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2545 if (GET_CODE (operands[2]) == CONST_INT
2546 && INTVAL (operands[2]) > 0
2547 && exact_log2 (INTVAL (operands[2])) >= 0)
2549 else if (TARGET_POWERPC)
2551 operands[2] = force_reg (<MODE>mode, operands[2]);
2554 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2558 else if (TARGET_POWER)
2562 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2563 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2564 emit_insn (gen_quoss_call ());
2565 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2570 (define_insn "divsi3_mq"
2571 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2572 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2573 (match_operand:SI 2 "gpc_reg_operand" "r")))
2574 (clobber (match_scratch:SI 3 "=q"))]
2575 "TARGET_POWERPC && TARGET_POWER"
2577 [(set_attr "type" "idiv")])
2579 (define_insn "*div<mode>3_no_mq"
2580 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2581 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2582 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2583 "TARGET_POWERPC && ! TARGET_POWER"
2586 (cond [(match_operand:SI 0 "" "")
2587 (const_string "idiv")]
2588 (const_string "ldiv")))])
2590 (define_expand "mod<mode>3"
2591 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2592 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2593 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2601 if (GET_CODE (operands[2]) != CONST_INT
2602 || INTVAL (operands[2]) <= 0
2603 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2606 temp1 = gen_reg_rtx (<MODE>mode);
2607 temp2 = gen_reg_rtx (<MODE>mode);
2609 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2610 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2611 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2616 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2617 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2618 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2620 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
2621 [(set_attr "type" "two")
2622 (set_attr "length" "8")])
2625 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2626 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2627 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2629 (clobber (match_scratch:P 3 "=r,r"))]
2632 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
2634 [(set_attr "type" "compare")
2635 (set_attr "length" "8,12")
2636 (set_attr "cell_micro" "not")])
2639 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2640 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2641 (match_operand:GPR 2 "exact_log2_cint_operand"
2644 (clobber (match_scratch:GPR 3 ""))]
2647 (div:<MODE> (match_dup 1) (match_dup 2)))
2649 (compare:CC (match_dup 3)
2654 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2655 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2656 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2658 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2659 (div:P (match_dup 1) (match_dup 2)))]
2662 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
2664 [(set_attr "type" "compare")
2665 (set_attr "length" "8,12")
2666 (set_attr "cell_micro" "not")])
2669 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2670 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2671 (match_operand:GPR 2 "exact_log2_cint_operand"
2674 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2675 (div:GPR (match_dup 1) (match_dup 2)))]
2678 (div:<MODE> (match_dup 1) (match_dup 2)))
2680 (compare:CC (match_dup 0)
2685 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2688 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2690 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2691 (match_operand:SI 3 "gpc_reg_operand" "r")))
2692 (set (match_operand:SI 2 "register_operand" "=*q")
2695 (zero_extend:DI (match_dup 1)) (const_int 32))
2696 (zero_extend:DI (match_dup 4)))
2700 [(set_attr "type" "idiv")])
2702 ;; To do unsigned divide we handle the cases of the divisor looking like a
2703 ;; negative number. If it is a constant that is less than 2**31, we don't
2704 ;; have to worry about the branches. So make a few subroutines here.
2706 ;; First comes the normal case.
2707 (define_expand "udivmodsi4_normal"
2708 [(set (match_dup 4) (const_int 0))
2709 (parallel [(set (match_operand:SI 0 "" "")
2710 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2712 (zero_extend:DI (match_operand:SI 1 "" "")))
2713 (match_operand:SI 2 "" "")))
2714 (set (match_operand:SI 3 "" "")
2715 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2717 (zero_extend:DI (match_dup 1)))
2721 { operands[4] = gen_reg_rtx (SImode); }")
2723 ;; This handles the branches.
2724 (define_expand "udivmodsi4_tests"
2725 [(set (match_operand:SI 0 "" "") (const_int 0))
2726 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2727 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2728 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2729 (label_ref (match_operand:SI 4 "" "")) (pc)))
2730 (set (match_dup 0) (const_int 1))
2731 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2732 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2733 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2734 (label_ref (match_dup 4)) (pc)))]
2737 { operands[5] = gen_reg_rtx (CCUNSmode);
2738 operands[6] = gen_reg_rtx (CCmode);
2741 (define_expand "udivmodsi4"
2742 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2743 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2744 (match_operand:SI 2 "reg_or_cint_operand" "")))
2745 (set (match_operand:SI 3 "gpc_reg_operand" "")
2746 (umod:SI (match_dup 1) (match_dup 2)))])]
2754 if (! TARGET_POWERPC)
2756 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2757 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2758 emit_insn (gen_divus_call ());
2759 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2760 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2767 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2769 operands[2] = force_reg (SImode, operands[2]);
2770 label = gen_label_rtx ();
2771 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2772 operands[3], label));
2775 operands[2] = force_reg (SImode, operands[2]);
2777 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2785 ;; AIX architecture-independent common-mode multiply (DImode),
2786 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2787 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2788 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2789 ;; assumed unused if generating common-mode, so ignore.
2790 (define_insn "mulh_call"
2793 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2794 (sign_extend:DI (reg:SI 4)))
2796 (clobber (reg:SI LR_REGNO))]
2797 "! TARGET_POWER && ! TARGET_POWERPC"
2799 [(set_attr "type" "imul")])
2801 (define_insn "mull_call"
2803 (mult:DI (sign_extend:DI (reg:SI 3))
2804 (sign_extend:DI (reg:SI 4))))
2805 (clobber (reg:SI LR_REGNO))
2806 (clobber (reg:SI 0))]
2807 "! TARGET_POWER && ! TARGET_POWERPC"
2809 [(set_attr "type" "imul")])
2811 (define_insn "divss_call"
2813 (div:SI (reg:SI 3) (reg:SI 4)))
2815 (mod:SI (reg:SI 3) (reg:SI 4)))
2816 (clobber (reg:SI LR_REGNO))
2817 (clobber (reg:SI 0))]
2818 "! TARGET_POWER && ! TARGET_POWERPC"
2820 [(set_attr "type" "idiv")])
2822 (define_insn "divus_call"
2824 (udiv:SI (reg:SI 3) (reg:SI 4)))
2826 (umod:SI (reg:SI 3) (reg:SI 4)))
2827 (clobber (reg:SI LR_REGNO))
2828 (clobber (reg:SI 0))
2829 (clobber (match_scratch:CC 0 "=x"))
2830 (clobber (reg:CC CR1_REGNO))]
2831 "! TARGET_POWER && ! TARGET_POWERPC"
2833 [(set_attr "type" "idiv")])
2835 (define_insn "quoss_call"
2837 (div:SI (reg:SI 3) (reg:SI 4)))
2838 (clobber (reg:SI LR_REGNO))]
2839 "! TARGET_POWER && ! TARGET_POWERPC"
2841 [(set_attr "type" "idiv")])
2843 (define_insn "quous_call"
2845 (udiv:SI (reg:SI 3) (reg:SI 4)))
2846 (clobber (reg:SI LR_REGNO))
2847 (clobber (reg:SI 0))
2848 (clobber (match_scratch:CC 0 "=x"))
2849 (clobber (reg:CC CR1_REGNO))]
2850 "! TARGET_POWER && ! TARGET_POWERPC"
2852 [(set_attr "type" "idiv")])
2854 ;; Logical instructions
2855 ;; The logical instructions are mostly combined by using match_operator,
2856 ;; but the plain AND insns are somewhat different because there is no
2857 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2858 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2860 (define_expand "andsi3"
2862 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2863 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2864 (match_operand:SI 2 "and_operand" "")))
2865 (clobber (match_scratch:CC 3 ""))])]
2869 (define_insn "andsi3_mc"
2870 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2871 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2872 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2873 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2874 "rs6000_gen_cell_microcode"
2877 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2878 {andil.|andi.} %0,%1,%b2
2879 {andiu.|andis.} %0,%1,%u2"
2880 [(set_attr "type" "*,*,fast_compare,fast_compare")])
2882 (define_insn "andsi3_nomc"
2883 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2884 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2885 (match_operand:SI 2 "and_operand" "?r,T")))
2886 (clobber (match_scratch:CC 3 "=X,X"))]
2887 "!rs6000_gen_cell_microcode"
2890 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
2892 (define_insn "andsi3_internal0_nomc"
2893 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2894 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2895 (match_operand:SI 2 "and_operand" "?r,T")))]
2896 "!rs6000_gen_cell_microcode"
2899 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
2902 ;; Note to set cr's other than cr0 we do the and immediate and then
2903 ;; the test again -- this avoids a mfcr which on the higher end
2904 ;; machines causes an execution serialization
2906 (define_insn "*andsi3_internal2_mc"
2907 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2908 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2909 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2911 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2912 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2913 "TARGET_32BIT && rs6000_gen_cell_microcode"
2916 {andil.|andi.} %3,%1,%b2
2917 {andiu.|andis.} %3,%1,%u2
2918 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2923 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
2924 compare,compare,compare,compare")
2925 (set_attr "length" "4,4,4,4,8,8,8,8")])
2927 (define_insn "*andsi3_internal3_mc"
2928 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2929 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2930 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2932 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2933 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2934 "TARGET_64BIT && rs6000_gen_cell_microcode"
2937 {andil.|andi.} %3,%1,%b2
2938 {andiu.|andis.} %3,%1,%u2
2939 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2944 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
2945 compare,compare,compare")
2946 (set_attr "length" "8,4,4,4,8,8,8,8")])
2949 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2950 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2951 (match_operand:GPR 2 "and_operand" ""))
2953 (clobber (match_scratch:GPR 3 ""))
2954 (clobber (match_scratch:CC 4 ""))]
2956 [(parallel [(set (match_dup 3)
2957 (and:<MODE> (match_dup 1)
2959 (clobber (match_dup 4))])
2961 (compare:CC (match_dup 3)
2965 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2966 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2969 [(set (match_operand:CC 0 "cc_reg_operand" "")
2970 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2971 (match_operand:SI 2 "gpc_reg_operand" ""))
2973 (clobber (match_scratch:SI 3 ""))
2974 (clobber (match_scratch:CC 4 ""))]
2975 "TARGET_POWERPC64 && reload_completed"
2976 [(parallel [(set (match_dup 3)
2977 (and:SI (match_dup 1)
2979 (clobber (match_dup 4))])
2981 (compare:CC (match_dup 3)
2985 (define_insn "*andsi3_internal4"
2986 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2987 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2988 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2990 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2991 (and:SI (match_dup 1)
2993 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2994 "TARGET_32BIT && rs6000_gen_cell_microcode"
2997 {andil.|andi.} %0,%1,%b2
2998 {andiu.|andis.} %0,%1,%u2
2999 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3004 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3005 compare,compare,compare,compare")
3006 (set_attr "length" "4,4,4,4,8,8,8,8")])
3008 (define_insn "*andsi3_internal5_mc"
3009 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3010 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3011 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3013 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3014 (and:SI (match_dup 1)
3016 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3017 "TARGET_64BIT && rs6000_gen_cell_microcode"
3020 {andil.|andi.} %0,%1,%b2
3021 {andiu.|andis.} %0,%1,%u2
3022 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3027 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3028 compare,compare,compare")
3029 (set_attr "length" "8,4,4,4,8,8,8,8")])
3032 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3033 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3034 (match_operand:SI 2 "and_operand" ""))
3036 (set (match_operand:SI 0 "gpc_reg_operand" "")
3037 (and:SI (match_dup 1)
3039 (clobber (match_scratch:CC 4 ""))]
3041 [(parallel [(set (match_dup 0)
3042 (and:SI (match_dup 1)
3044 (clobber (match_dup 4))])
3046 (compare:CC (match_dup 0)
3051 [(set (match_operand:CC 3 "cc_reg_operand" "")
3052 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3053 (match_operand:SI 2 "gpc_reg_operand" ""))
3055 (set (match_operand:SI 0 "gpc_reg_operand" "")
3056 (and:SI (match_dup 1)
3058 (clobber (match_scratch:CC 4 ""))]
3059 "TARGET_POWERPC64 && reload_completed"
3060 [(parallel [(set (match_dup 0)
3061 (and:SI (match_dup 1)
3063 (clobber (match_dup 4))])
3065 (compare:CC (match_dup 0)
3069 ;; Handle the PowerPC64 rlwinm corner case
3071 (define_insn_and_split "*andsi3_internal6"
3072 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3073 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3074 (match_operand:SI 2 "mask_operand_wrap" "i")))]
3079 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3082 (rotate:SI (match_dup 0) (match_dup 5)))]
3085 int mb = extract_MB (operands[2]);
3086 int me = extract_ME (operands[2]);
3087 operands[3] = GEN_INT (me + 1);
3088 operands[5] = GEN_INT (32 - (me + 1));
3089 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3091 [(set_attr "length" "8")])
3093 (define_expand "iorsi3"
3094 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3095 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
3096 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3100 if (GET_CODE (operands[2]) == CONST_INT
3101 && ! logical_operand (operands[2], SImode))
3103 HOST_WIDE_INT value = INTVAL (operands[2]);
3104 rtx tmp = ((!can_create_pseudo_p ()
3105 || rtx_equal_p (operands[0], operands[1]))
3106 ? operands[0] : gen_reg_rtx (SImode));
3108 emit_insn (gen_iorsi3 (tmp, operands[1],
3109 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3110 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3115 (define_expand "xorsi3"
3116 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3117 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3118 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3122 if (GET_CODE (operands[2]) == CONST_INT
3123 && ! logical_operand (operands[2], SImode))
3125 HOST_WIDE_INT value = INTVAL (operands[2]);
3126 rtx tmp = ((!can_create_pseudo_p ()
3127 || rtx_equal_p (operands[0], operands[1]))
3128 ? operands[0] : gen_reg_rtx (SImode));
3130 emit_insn (gen_xorsi3 (tmp, operands[1],
3131 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3132 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3137 (define_insn "*boolsi3_internal1"
3138 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3139 (match_operator:SI 3 "boolean_or_operator"
3140 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3141 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3145 {%q3il|%q3i} %0,%1,%b2
3146 {%q3iu|%q3is} %0,%1,%u2")
3148 (define_insn "*boolsi3_internal2"
3149 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3150 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3151 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3152 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3154 (clobber (match_scratch:SI 3 "=r,r"))]
3159 [(set_attr "type" "fast_compare,compare")
3160 (set_attr "length" "4,8")])
3163 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3164 (compare:CC (match_operator:SI 4 "boolean_operator"
3165 [(match_operand:SI 1 "gpc_reg_operand" "")
3166 (match_operand:SI 2 "gpc_reg_operand" "")])
3168 (clobber (match_scratch:SI 3 ""))]
3169 "TARGET_32BIT && reload_completed"
3170 [(set (match_dup 3) (match_dup 4))
3172 (compare:CC (match_dup 3)
3176 (define_insn "*boolsi3_internal3"
3177 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3178 (compare:CC (match_operator:SI 4 "boolean_operator"
3179 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3180 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3182 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3188 [(set_attr "type" "fast_compare,compare")
3189 (set_attr "length" "4,8")])
3192 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3193 (compare:CC (match_operator:SI 4 "boolean_operator"
3194 [(match_operand:SI 1 "gpc_reg_operand" "")
3195 (match_operand:SI 2 "gpc_reg_operand" "")])
3197 (set (match_operand:SI 0 "gpc_reg_operand" "")
3199 "TARGET_32BIT && reload_completed"
3200 [(set (match_dup 0) (match_dup 4))
3202 (compare:CC (match_dup 0)
3206 ;; Split a logical operation that we can't do in one insn into two insns,
3207 ;; each of which does one 16-bit part. This is used by combine.
3210 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3211 (match_operator:SI 3 "boolean_or_operator"
3212 [(match_operand:SI 1 "gpc_reg_operand" "")
3213 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3215 [(set (match_dup 0) (match_dup 4))
3216 (set (match_dup 0) (match_dup 5))]
3220 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3221 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3223 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3224 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3228 (define_insn "*boolcsi3_internal1"
3229 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3230 (match_operator:SI 3 "boolean_operator"
3231 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3232 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3236 (define_insn "*boolcsi3_internal2"
3237 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3238 (compare:CC (match_operator:SI 4 "boolean_operator"
3239 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3240 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3242 (clobber (match_scratch:SI 3 "=r,r"))]
3247 [(set_attr "type" "compare")
3248 (set_attr "length" "4,8")])
3251 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3252 (compare:CC (match_operator:SI 4 "boolean_operator"
3253 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3254 (match_operand:SI 2 "gpc_reg_operand" "")])
3256 (clobber (match_scratch:SI 3 ""))]
3257 "TARGET_32BIT && reload_completed"
3258 [(set (match_dup 3) (match_dup 4))
3260 (compare:CC (match_dup 3)
3264 (define_insn "*boolcsi3_internal3"
3265 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3266 (compare:CC (match_operator:SI 4 "boolean_operator"
3267 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3268 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3270 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3276 [(set_attr "type" "compare")
3277 (set_attr "length" "4,8")])
3280 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3281 (compare:CC (match_operator:SI 4 "boolean_operator"
3282 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3283 (match_operand:SI 2 "gpc_reg_operand" "")])
3285 (set (match_operand:SI 0 "gpc_reg_operand" "")
3287 "TARGET_32BIT && reload_completed"
3288 [(set (match_dup 0) (match_dup 4))
3290 (compare:CC (match_dup 0)
3294 (define_insn "*boolccsi3_internal1"
3295 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3296 (match_operator:SI 3 "boolean_operator"
3297 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3298 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3302 (define_insn "*boolccsi3_internal2"
3303 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3304 (compare:CC (match_operator:SI 4 "boolean_operator"
3305 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3306 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3308 (clobber (match_scratch:SI 3 "=r,r"))]
3313 [(set_attr "type" "fast_compare,compare")
3314 (set_attr "length" "4,8")])
3317 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3318 (compare:CC (match_operator:SI 4 "boolean_operator"
3319 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3320 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3322 (clobber (match_scratch:SI 3 ""))]
3323 "TARGET_32BIT && reload_completed"
3324 [(set (match_dup 3) (match_dup 4))
3326 (compare:CC (match_dup 3)
3330 (define_insn "*boolccsi3_internal3"
3331 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3332 (compare:CC (match_operator:SI 4 "boolean_operator"
3333 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3334 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3336 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3342 [(set_attr "type" "fast_compare,compare")
3343 (set_attr "length" "4,8")])
3346 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3347 (compare:CC (match_operator:SI 4 "boolean_operator"
3348 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3349 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3351 (set (match_operand:SI 0 "gpc_reg_operand" "")
3353 "TARGET_32BIT && reload_completed"
3354 [(set (match_dup 0) (match_dup 4))
3356 (compare:CC (match_dup 0)
3360 ;; maskir insn. We need four forms because things might be in arbitrary
3361 ;; orders. Don't define forms that only set CR fields because these
3362 ;; would modify an input register.
3364 (define_insn "*maskir_internal1"
3365 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3366 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3367 (match_operand:SI 1 "gpc_reg_operand" "0"))
3368 (and:SI (match_dup 2)
3369 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3373 (define_insn "*maskir_internal2"
3374 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3375 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3376 (match_operand:SI 1 "gpc_reg_operand" "0"))
3377 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3382 (define_insn "*maskir_internal3"
3383 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3384 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3385 (match_operand:SI 3 "gpc_reg_operand" "r"))
3386 (and:SI (not:SI (match_dup 2))
3387 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3391 (define_insn "*maskir_internal4"
3392 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3393 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3394 (match_operand:SI 2 "gpc_reg_operand" "r"))
3395 (and:SI (not:SI (match_dup 2))
3396 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3400 (define_insn "*maskir_internal5"
3401 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3403 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3404 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3405 (and:SI (match_dup 2)
3406 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3408 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3409 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3410 (and:SI (match_dup 2) (match_dup 3))))]
3415 [(set_attr "type" "compare")
3416 (set_attr "length" "4,8")])
3419 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3421 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3422 (match_operand:SI 1 "gpc_reg_operand" ""))
3423 (and:SI (match_dup 2)
3424 (match_operand:SI 3 "gpc_reg_operand" "")))
3426 (set (match_operand:SI 0 "gpc_reg_operand" "")
3427 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3428 (and:SI (match_dup 2) (match_dup 3))))]
3429 "TARGET_POWER && reload_completed"
3431 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3432 (and:SI (match_dup 2) (match_dup 3))))
3434 (compare:CC (match_dup 0)
3438 (define_insn "*maskir_internal6"
3439 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3441 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3442 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3443 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3446 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3447 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3448 (and:SI (match_dup 3) (match_dup 2))))]
3453 [(set_attr "type" "compare")
3454 (set_attr "length" "4,8")])
3457 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3459 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3460 (match_operand:SI 1 "gpc_reg_operand" ""))
3461 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3464 (set (match_operand:SI 0 "gpc_reg_operand" "")
3465 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3466 (and:SI (match_dup 3) (match_dup 2))))]
3467 "TARGET_POWER && reload_completed"
3469 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3470 (and:SI (match_dup 3) (match_dup 2))))
3472 (compare:CC (match_dup 0)
3476 (define_insn "*maskir_internal7"
3477 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3479 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3480 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3481 (and:SI (not:SI (match_dup 2))
3482 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3484 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3485 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3486 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3491 [(set_attr "type" "compare")
3492 (set_attr "length" "4,8")])
3495 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3497 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3498 (match_operand:SI 3 "gpc_reg_operand" ""))
3499 (and:SI (not:SI (match_dup 2))
3500 (match_operand:SI 1 "gpc_reg_operand" "")))
3502 (set (match_operand:SI 0 "gpc_reg_operand" "")
3503 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3504 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3505 "TARGET_POWER && reload_completed"
3507 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3508 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3510 (compare:CC (match_dup 0)
3514 (define_insn "*maskir_internal8"
3515 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3517 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3518 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3519 (and:SI (not:SI (match_dup 2))
3520 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3522 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3523 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3524 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3529 [(set_attr "type" "compare")
3530 (set_attr "length" "4,8")])
3533 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3535 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3536 (match_operand:SI 2 "gpc_reg_operand" ""))
3537 (and:SI (not:SI (match_dup 2))
3538 (match_operand:SI 1 "gpc_reg_operand" "")))
3540 (set (match_operand:SI 0 "gpc_reg_operand" "")
3541 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3542 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3543 "TARGET_POWER && reload_completed"
3545 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3546 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3548 (compare:CC (match_dup 0)
3552 ;; Rotate and shift insns, in all their variants. These support shifts,
3553 ;; field inserts and extracts, and various combinations thereof.
3554 (define_expand "insv"
3555 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3556 (match_operand:SI 1 "const_int_operand" "")
3557 (match_operand:SI 2 "const_int_operand" ""))
3558 (match_operand 3 "gpc_reg_operand" ""))]
3562 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3563 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3564 compiler if the address of the structure is taken later. Likewise, do
3565 not handle invalid E500 subregs. */
3566 if (GET_CODE (operands[0]) == SUBREG
3567 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3568 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3569 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3572 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3573 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3575 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3579 (define_insn "insvsi"
3580 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3581 (match_operand:SI 1 "const_int_operand" "i")
3582 (match_operand:SI 2 "const_int_operand" "i"))
3583 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3587 int start = INTVAL (operands[2]) & 31;
3588 int size = INTVAL (operands[1]) & 31;
3590 operands[4] = GEN_INT (32 - start - size);
3591 operands[1] = GEN_INT (start + size - 1);
3592 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3594 [(set_attr "type" "insert_word")])
3596 (define_insn "*insvsi_internal1"
3597 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3598 (match_operand:SI 1 "const_int_operand" "i")
3599 (match_operand:SI 2 "const_int_operand" "i"))
3600 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3601 (match_operand:SI 4 "const_int_operand" "i")))]
3602 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3605 int shift = INTVAL (operands[4]) & 31;
3606 int start = INTVAL (operands[2]) & 31;
3607 int size = INTVAL (operands[1]) & 31;
3609 operands[4] = GEN_INT (shift - start - size);
3610 operands[1] = GEN_INT (start + size - 1);
3611 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3613 [(set_attr "type" "insert_word")])
3615 (define_insn "*insvsi_internal2"
3616 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3617 (match_operand:SI 1 "const_int_operand" "i")
3618 (match_operand:SI 2 "const_int_operand" "i"))
3619 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3620 (match_operand:SI 4 "const_int_operand" "i")))]
3621 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3624 int shift = INTVAL (operands[4]) & 31;
3625 int start = INTVAL (operands[2]) & 31;
3626 int size = INTVAL (operands[1]) & 31;
3628 operands[4] = GEN_INT (32 - shift - start - size);
3629 operands[1] = GEN_INT (start + size - 1);
3630 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3632 [(set_attr "type" "insert_word")])
3634 (define_insn "*insvsi_internal3"
3635 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3636 (match_operand:SI 1 "const_int_operand" "i")
3637 (match_operand:SI 2 "const_int_operand" "i"))
3638 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3639 (match_operand:SI 4 "const_int_operand" "i")))]
3640 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3643 int shift = INTVAL (operands[4]) & 31;
3644 int start = INTVAL (operands[2]) & 31;
3645 int size = INTVAL (operands[1]) & 31;
3647 operands[4] = GEN_INT (32 - shift - start - size);
3648 operands[1] = GEN_INT (start + size - 1);
3649 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3651 [(set_attr "type" "insert_word")])
3653 (define_insn "*insvsi_internal4"
3654 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3655 (match_operand:SI 1 "const_int_operand" "i")
3656 (match_operand:SI 2 "const_int_operand" "i"))
3657 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3658 (match_operand:SI 4 "const_int_operand" "i")
3659 (match_operand:SI 5 "const_int_operand" "i")))]
3660 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3663 int extract_start = INTVAL (operands[5]) & 31;
3664 int extract_size = INTVAL (operands[4]) & 31;
3665 int insert_start = INTVAL (operands[2]) & 31;
3666 int insert_size = INTVAL (operands[1]) & 31;
3668 /* Align extract field with insert field */
3669 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3670 operands[1] = GEN_INT (insert_start + insert_size - 1);
3671 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3673 [(set_attr "type" "insert_word")])
3675 ;; combine patterns for rlwimi
3676 (define_insn "*insvsi_internal5"
3677 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3678 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3679 (match_operand:SI 1 "mask_operand" "i"))
3680 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3681 (match_operand:SI 2 "const_int_operand" "i"))
3682 (match_operand:SI 5 "mask_operand" "i"))))]
3683 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3686 int me = extract_ME(operands[5]);
3687 int mb = extract_MB(operands[5]);
3688 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3689 operands[2] = GEN_INT(mb);
3690 operands[1] = GEN_INT(me);
3691 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3693 [(set_attr "type" "insert_word")])
3695 (define_insn "*insvsi_internal6"
3696 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3697 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3698 (match_operand:SI 2 "const_int_operand" "i"))
3699 (match_operand:SI 5 "mask_operand" "i"))
3700 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3701 (match_operand:SI 1 "mask_operand" "i"))))]
3702 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3705 int me = extract_ME(operands[5]);
3706 int mb = extract_MB(operands[5]);
3707 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3708 operands[2] = GEN_INT(mb);
3709 operands[1] = GEN_INT(me);
3710 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3712 [(set_attr "type" "insert_word")])
3714 (define_insn "insvdi"
3715 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3716 (match_operand:SI 1 "const_int_operand" "i")
3717 (match_operand:SI 2 "const_int_operand" "i"))
3718 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3722 int start = INTVAL (operands[2]) & 63;
3723 int size = INTVAL (operands[1]) & 63;
3725 operands[1] = GEN_INT (64 - start - size);
3726 return \"rldimi %0,%3,%H1,%H2\";
3728 [(set_attr "type" "insert_dword")])
3730 (define_insn "*insvdi_internal2"
3731 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3732 (match_operand:SI 1 "const_int_operand" "i")
3733 (match_operand:SI 2 "const_int_operand" "i"))
3734 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3735 (match_operand:SI 4 "const_int_operand" "i")))]
3737 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3740 int shift = INTVAL (operands[4]) & 63;
3741 int start = (INTVAL (operands[2]) & 63) - 32;
3742 int size = INTVAL (operands[1]) & 63;
3744 operands[4] = GEN_INT (64 - shift - start - size);
3745 operands[2] = GEN_INT (start);
3746 operands[1] = GEN_INT (start + size - 1);
3747 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3750 (define_insn "*insvdi_internal3"
3751 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3752 (match_operand:SI 1 "const_int_operand" "i")
3753 (match_operand:SI 2 "const_int_operand" "i"))
3754 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3755 (match_operand:SI 4 "const_int_operand" "i")))]
3757 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3760 int shift = INTVAL (operands[4]) & 63;
3761 int start = (INTVAL (operands[2]) & 63) - 32;
3762 int size = INTVAL (operands[1]) & 63;
3764 operands[4] = GEN_INT (64 - shift - start - size);
3765 operands[2] = GEN_INT (start);
3766 operands[1] = GEN_INT (start + size - 1);
3767 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3770 (define_expand "extzv"
3771 [(set (match_operand 0 "gpc_reg_operand" "")
3772 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3773 (match_operand:SI 2 "const_int_operand" "")
3774 (match_operand:SI 3 "const_int_operand" "")))]
3778 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3779 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3780 compiler if the address of the structure is taken later. */
3781 if (GET_CODE (operands[0]) == SUBREG
3782 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3785 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3786 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3788 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3792 (define_insn "extzvsi"
3793 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3794 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3795 (match_operand:SI 2 "const_int_operand" "i")
3796 (match_operand:SI 3 "const_int_operand" "i")))]
3800 int start = INTVAL (operands[3]) & 31;
3801 int size = INTVAL (operands[2]) & 31;
3803 if (start + size >= 32)
3804 operands[3] = const0_rtx;
3806 operands[3] = GEN_INT (start + size);
3807 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3810 (define_insn "*extzvsi_internal1"
3811 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3812 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3813 (match_operand:SI 2 "const_int_operand" "i,i")
3814 (match_operand:SI 3 "const_int_operand" "i,i"))
3816 (clobber (match_scratch:SI 4 "=r,r"))]
3820 int start = INTVAL (operands[3]) & 31;
3821 int size = INTVAL (operands[2]) & 31;
3823 /* Force split for non-cc0 compare. */
3824 if (which_alternative == 1)
3827 /* If the bit-field being tested fits in the upper or lower half of a
3828 word, it is possible to use andiu. or andil. to test it. This is
3829 useful because the condition register set-use delay is smaller for
3830 andi[ul]. than for rlinm. This doesn't work when the starting bit
3831 position is 0 because the LT and GT bits may be set wrong. */
3833 if ((start > 0 && start + size <= 16) || start >= 16)
3835 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3836 - (1 << (16 - (start & 15) - size))));
3838 return \"{andiu.|andis.} %4,%1,%3\";
3840 return \"{andil.|andi.} %4,%1,%3\";
3843 if (start + size >= 32)
3844 operands[3] = const0_rtx;
3846 operands[3] = GEN_INT (start + size);
3847 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3849 [(set_attr "type" "delayed_compare")
3850 (set_attr "length" "4,8")])
3853 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3854 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3855 (match_operand:SI 2 "const_int_operand" "")
3856 (match_operand:SI 3 "const_int_operand" ""))
3858 (clobber (match_scratch:SI 4 ""))]
3861 (zero_extract:SI (match_dup 1) (match_dup 2)
3864 (compare:CC (match_dup 4)
3868 (define_insn "*extzvsi_internal2"
3869 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3870 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3871 (match_operand:SI 2 "const_int_operand" "i,i")
3872 (match_operand:SI 3 "const_int_operand" "i,i"))
3874 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3875 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3879 int start = INTVAL (operands[3]) & 31;
3880 int size = INTVAL (operands[2]) & 31;
3882 /* Force split for non-cc0 compare. */
3883 if (which_alternative == 1)
3886 /* Since we are using the output value, we can't ignore any need for
3887 a shift. The bit-field must end at the LSB. */
3888 if (start >= 16 && start + size == 32)
3890 operands[3] = GEN_INT ((1 << size) - 1);
3891 return \"{andil.|andi.} %0,%1,%3\";
3894 if (start + size >= 32)
3895 operands[3] = const0_rtx;
3897 operands[3] = GEN_INT (start + size);
3898 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3900 [(set_attr "type" "delayed_compare")
3901 (set_attr "length" "4,8")])
3904 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3905 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3906 (match_operand:SI 2 "const_int_operand" "")
3907 (match_operand:SI 3 "const_int_operand" ""))
3909 (set (match_operand:SI 0 "gpc_reg_operand" "")
3910 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3913 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3915 (compare:CC (match_dup 0)
3919 (define_insn "extzvdi"
3920 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3921 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3922 (match_operand:SI 2 "const_int_operand" "i")
3923 (match_operand:SI 3 "const_int_operand" "i")))]
3927 int start = INTVAL (operands[3]) & 63;
3928 int size = INTVAL (operands[2]) & 63;
3930 if (start + size >= 64)
3931 operands[3] = const0_rtx;
3933 operands[3] = GEN_INT (start + size);
3934 operands[2] = GEN_INT (64 - size);
3935 return \"rldicl %0,%1,%3,%2\";
3938 (define_insn "*extzvdi_internal1"
3939 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3940 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3941 (match_operand:SI 2 "const_int_operand" "i")
3942 (match_operand:SI 3 "const_int_operand" "i"))
3944 (clobber (match_scratch:DI 4 "=r"))]
3945 "TARGET_64BIT && rs6000_gen_cell_microcode"
3948 int start = INTVAL (operands[3]) & 63;
3949 int size = INTVAL (operands[2]) & 63;
3951 if (start + size >= 64)
3952 operands[3] = const0_rtx;
3954 operands[3] = GEN_INT (start + size);
3955 operands[2] = GEN_INT (64 - size);
3956 return \"rldicl. %4,%1,%3,%2\";
3958 [(set_attr "type" "compare")])
3960 (define_insn "*extzvdi_internal2"
3961 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3962 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3963 (match_operand:SI 2 "const_int_operand" "i")
3964 (match_operand:SI 3 "const_int_operand" "i"))
3966 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3967 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3968 "TARGET_64BIT && rs6000_gen_cell_microcode"
3971 int start = INTVAL (operands[3]) & 63;
3972 int size = INTVAL (operands[2]) & 63;
3974 if (start + size >= 64)
3975 operands[3] = const0_rtx;
3977 operands[3] = GEN_INT (start + size);
3978 operands[2] = GEN_INT (64 - size);
3979 return \"rldicl. %0,%1,%3,%2\";
3981 [(set_attr "type" "compare")])
3983 (define_insn "rotlsi3"
3984 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3985 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3986 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
3989 {rlnm|rlwnm} %0,%1,%2,0xffffffff
3990 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
3991 [(set_attr "type" "var_shift_rotate,integer")])
3993 (define_insn "*rotlsi3_internal2"
3994 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3995 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3996 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3998 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4001 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
4002 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
4005 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4006 (set_attr "length" "4,4,8,8")])
4009 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4010 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4011 (match_operand:SI 2 "reg_or_cint_operand" ""))
4013 (clobber (match_scratch:SI 3 ""))]
4016 (rotate:SI (match_dup 1) (match_dup 2)))
4018 (compare:CC (match_dup 3)
4022 (define_insn "*rotlsi3_internal3"
4023 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4024 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4025 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4027 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4028 (rotate:SI (match_dup 1) (match_dup 2)))]
4031 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
4032 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
4035 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4036 (set_attr "length" "4,4,8,8")])
4039 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4040 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4041 (match_operand:SI 2 "reg_or_cint_operand" ""))
4043 (set (match_operand:SI 0 "gpc_reg_operand" "")
4044 (rotate:SI (match_dup 1) (match_dup 2)))]
4047 (rotate:SI (match_dup 1) (match_dup 2)))
4049 (compare:CC (match_dup 0)
4053 (define_insn "*rotlsi3_internal4"
4054 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4055 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4056 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
4057 (match_operand:SI 3 "mask_operand" "n,n")))]
4060 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
4061 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
4062 [(set_attr "type" "var_shift_rotate,integer")])
4064 (define_insn "*rotlsi3_internal5"
4065 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4067 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4068 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4069 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4071 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
4074 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
4075 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4078 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4079 (set_attr "length" "4,4,8,8")])
4082 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4084 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4085 (match_operand:SI 2 "reg_or_cint_operand" ""))
4086 (match_operand:SI 3 "mask_operand" ""))
4088 (clobber (match_scratch:SI 4 ""))]
4091 (and:SI (rotate:SI (match_dup 1)
4095 (compare:CC (match_dup 4)
4099 (define_insn "*rotlsi3_internal6"
4100 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
4102 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4103 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4104 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4106 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4107 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4110 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
4111 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4114 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4115 (set_attr "length" "4,4,8,8")])
4118 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4120 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4121 (match_operand:SI 2 "reg_or_cint_operand" ""))
4122 (match_operand:SI 3 "mask_operand" ""))
4124 (set (match_operand:SI 0 "gpc_reg_operand" "")
4125 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4128 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4130 (compare:CC (match_dup 0)
4134 (define_insn "*rotlsi3_internal7"
4135 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4138 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4139 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4141 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff"
4142 [(set (attr "cell_micro")
4143 (if_then_else (match_operand:SI 2 "const_int_operand" "")
4144 (const_string "not")
4145 (const_string "always")))])
4147 (define_insn "*rotlsi3_internal8"
4148 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4149 (compare:CC (zero_extend:SI
4151 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4152 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4154 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4157 {rlnm.|rlwnm.} %3,%1,%2,0xff
4158 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4161 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4162 (set_attr "length" "4,4,8,8")])
4165 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4166 (compare:CC (zero_extend:SI
4168 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4169 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4171 (clobber (match_scratch:SI 3 ""))]
4174 (zero_extend:SI (subreg:QI
4175 (rotate:SI (match_dup 1)
4178 (compare:CC (match_dup 3)
4182 (define_insn "*rotlsi3_internal9"
4183 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4184 (compare:CC (zero_extend:SI
4186 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4187 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4189 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4190 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4193 {rlnm.|rlwnm.} %0,%1,%2,0xff
4194 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4197 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4198 (set_attr "length" "4,4,8,8")])
4201 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4202 (compare:CC (zero_extend:SI
4204 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4205 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4207 (set (match_operand:SI 0 "gpc_reg_operand" "")
4208 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4211 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4213 (compare:CC (match_dup 0)
4217 (define_insn "*rotlsi3_internal10"
4218 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4221 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4222 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4225 {rlnm|rlwnm} %0,%1,%2,0xffff
4226 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4227 [(set_attr "type" "var_shift_rotate,integer")])
4230 (define_insn "*rotlsi3_internal11"
4231 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4232 (compare:CC (zero_extend:SI
4234 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4235 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4237 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4240 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4241 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4244 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4245 (set_attr "length" "4,4,8,8")])
4248 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4249 (compare:CC (zero_extend:SI
4251 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4252 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4254 (clobber (match_scratch:SI 3 ""))]
4257 (zero_extend:SI (subreg:HI
4258 (rotate:SI (match_dup 1)
4261 (compare:CC (match_dup 3)
4265 (define_insn "*rotlsi3_internal12"
4266 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4267 (compare:CC (zero_extend:SI
4269 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4270 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4272 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4273 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4276 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4277 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4280 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4281 (set_attr "length" "4,4,8,8")])
4284 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4285 (compare:CC (zero_extend:SI
4287 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4288 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4290 (set (match_operand:SI 0 "gpc_reg_operand" "")
4291 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4294 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4296 (compare:CC (match_dup 0)
4300 ;; Note that we use "sle." instead of "sl." so that we can set
4301 ;; SHIFT_COUNT_TRUNCATED.
4303 (define_expand "ashlsi3"
4304 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4305 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4306 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4311 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4313 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4317 (define_insn "ashlsi3_power"
4318 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4319 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4320 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4321 (clobber (match_scratch:SI 3 "=q,X"))]
4325 {sli|slwi} %0,%1,%h2")
4327 (define_insn "ashlsi3_no_power"
4328 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4329 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4330 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4334 {sli|slwi} %0,%1,%h2"
4335 [(set_attr "type" "var_shift_rotate,shift")])
4338 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4339 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4340 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4342 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4343 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4347 {sli.|slwi.} %3,%1,%h2
4350 [(set_attr "type" "delayed_compare")
4351 (set_attr "length" "4,4,8,8")])
4354 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4355 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4356 (match_operand:SI 2 "reg_or_cint_operand" ""))
4358 (clobber (match_scratch:SI 3 ""))
4359 (clobber (match_scratch:SI 4 ""))]
4360 "TARGET_POWER && reload_completed"
4361 [(parallel [(set (match_dup 3)
4362 (ashift:SI (match_dup 1) (match_dup 2)))
4363 (clobber (match_dup 4))])
4365 (compare:CC (match_dup 3)
4370 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4371 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4372 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4374 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4375 "! TARGET_POWER && TARGET_32BIT"
4378 {sli.|slwi.} %3,%1,%h2
4381 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4382 (set_attr "length" "4,4,8,8")])
4385 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4386 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4387 (match_operand:SI 2 "reg_or_cint_operand" ""))
4389 (clobber (match_scratch:SI 3 ""))]
4390 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4392 (ashift:SI (match_dup 1) (match_dup 2)))
4394 (compare:CC (match_dup 3)
4399 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4400 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4401 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4403 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4404 (ashift:SI (match_dup 1) (match_dup 2)))
4405 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4409 {sli.|slwi.} %0,%1,%h2
4412 [(set_attr "type" "delayed_compare")
4413 (set_attr "length" "4,4,8,8")])
4416 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4417 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4418 (match_operand:SI 2 "reg_or_cint_operand" ""))
4420 (set (match_operand:SI 0 "gpc_reg_operand" "")
4421 (ashift:SI (match_dup 1) (match_dup 2)))
4422 (clobber (match_scratch:SI 4 ""))]
4423 "TARGET_POWER && reload_completed"
4424 [(parallel [(set (match_dup 0)
4425 (ashift:SI (match_dup 1) (match_dup 2)))
4426 (clobber (match_dup 4))])
4428 (compare:CC (match_dup 0)
4433 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4434 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4435 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4437 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4438 (ashift:SI (match_dup 1) (match_dup 2)))]
4439 "! TARGET_POWER && TARGET_32BIT"
4442 {sli.|slwi.} %0,%1,%h2
4445 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4446 (set_attr "length" "4,4,8,8")])
4449 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4450 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4451 (match_operand:SI 2 "reg_or_cint_operand" ""))
4453 (set (match_operand:SI 0 "gpc_reg_operand" "")
4454 (ashift:SI (match_dup 1) (match_dup 2)))]
4455 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4457 (ashift:SI (match_dup 1) (match_dup 2)))
4459 (compare:CC (match_dup 0)
4463 (define_insn "rlwinm"
4464 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4465 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4466 (match_operand:SI 2 "const_int_operand" "i"))
4467 (match_operand:SI 3 "mask_operand" "n")))]
4468 "includes_lshift_p (operands[2], operands[3])"
4469 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4472 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4474 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4475 (match_operand:SI 2 "const_int_operand" "i,i"))
4476 (match_operand:SI 3 "mask_operand" "n,n"))
4478 (clobber (match_scratch:SI 4 "=r,r"))]
4479 "includes_lshift_p (operands[2], operands[3])"
4481 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4483 [(set_attr "type" "delayed_compare")
4484 (set_attr "length" "4,8")])
4487 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4489 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4490 (match_operand:SI 2 "const_int_operand" ""))
4491 (match_operand:SI 3 "mask_operand" ""))
4493 (clobber (match_scratch:SI 4 ""))]
4494 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4496 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4499 (compare:CC (match_dup 4)
4504 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4506 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4507 (match_operand:SI 2 "const_int_operand" "i,i"))
4508 (match_operand:SI 3 "mask_operand" "n,n"))
4510 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4511 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4512 "includes_lshift_p (operands[2], operands[3])"
4514 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4516 [(set_attr "type" "delayed_compare")
4517 (set_attr "length" "4,8")])
4520 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4522 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4523 (match_operand:SI 2 "const_int_operand" ""))
4524 (match_operand:SI 3 "mask_operand" ""))
4526 (set (match_operand:SI 0 "gpc_reg_operand" "")
4527 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4528 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4530 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4532 (compare:CC (match_dup 0)
4536 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
4538 (define_expand "lshrsi3"
4539 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4540 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4541 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4546 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4548 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
4552 (define_insn "lshrsi3_power"
4553 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4554 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4555 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4556 (clobber (match_scratch:SI 3 "=q,X,X"))]
4561 {s%A2i|s%A2wi} %0,%1,%h2")
4563 (define_insn "lshrsi3_no_power"
4564 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4565 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4566 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
4571 {sri|srwi} %0,%1,%h2"
4572 [(set_attr "type" "integer,var_shift_rotate,shift")])
4575 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4576 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4577 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4579 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4580 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4585 {s%A2i.|s%A2wi.} %3,%1,%h2
4589 [(set_attr "type" "delayed_compare")
4590 (set_attr "length" "4,4,4,8,8,8")])
4593 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4594 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4595 (match_operand:SI 2 "reg_or_cint_operand" ""))
4597 (clobber (match_scratch:SI 3 ""))
4598 (clobber (match_scratch:SI 4 ""))]
4599 "TARGET_POWER && reload_completed"
4600 [(parallel [(set (match_dup 3)
4601 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4602 (clobber (match_dup 4))])
4604 (compare:CC (match_dup 3)
4609 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4610 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4611 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4613 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4614 "! TARGET_POWER && TARGET_32BIT"
4618 {sri.|srwi.} %3,%1,%h2
4622 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4623 (set_attr "length" "4,4,4,8,8,8")])
4626 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4627 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4628 (match_operand:SI 2 "reg_or_cint_operand" ""))
4630 (clobber (match_scratch:SI 3 ""))]
4631 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4633 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4635 (compare:CC (match_dup 3)
4640 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4641 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4642 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4644 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4645 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4646 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4651 {s%A2i.|s%A2wi.} %0,%1,%h2
4655 [(set_attr "type" "delayed_compare")
4656 (set_attr "length" "4,4,4,8,8,8")])
4659 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4660 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4661 (match_operand:SI 2 "reg_or_cint_operand" ""))
4663 (set (match_operand:SI 0 "gpc_reg_operand" "")
4664 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4665 (clobber (match_scratch:SI 4 ""))]
4666 "TARGET_POWER && reload_completed"
4667 [(parallel [(set (match_dup 0)
4668 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4669 (clobber (match_dup 4))])
4671 (compare:CC (match_dup 0)
4676 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4677 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4678 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4680 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4681 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4682 "! TARGET_POWER && TARGET_32BIT"
4686 {sri.|srwi.} %0,%1,%h2
4690 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4691 (set_attr "length" "4,4,4,8,8,8")])
4694 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4695 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4696 (match_operand:SI 2 "reg_or_cint_operand" ""))
4698 (set (match_operand:SI 0 "gpc_reg_operand" "")
4699 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4700 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4702 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4704 (compare:CC (match_dup 0)
4709 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4710 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4711 (match_operand:SI 2 "const_int_operand" "i"))
4712 (match_operand:SI 3 "mask_operand" "n")))]
4713 "includes_rshift_p (operands[2], operands[3])"
4714 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4717 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4719 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4720 (match_operand:SI 2 "const_int_operand" "i,i"))
4721 (match_operand:SI 3 "mask_operand" "n,n"))
4723 (clobber (match_scratch:SI 4 "=r,r"))]
4724 "includes_rshift_p (operands[2], operands[3])"
4726 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4728 [(set_attr "type" "delayed_compare")
4729 (set_attr "length" "4,8")])
4732 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4734 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4735 (match_operand:SI 2 "const_int_operand" ""))
4736 (match_operand:SI 3 "mask_operand" ""))
4738 (clobber (match_scratch:SI 4 ""))]
4739 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4741 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4744 (compare:CC (match_dup 4)
4749 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4751 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4752 (match_operand:SI 2 "const_int_operand" "i,i"))
4753 (match_operand:SI 3 "mask_operand" "n,n"))
4755 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4756 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4757 "includes_rshift_p (operands[2], operands[3])"
4759 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4761 [(set_attr "type" "delayed_compare")
4762 (set_attr "length" "4,8")])
4765 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4767 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4768 (match_operand:SI 2 "const_int_operand" ""))
4769 (match_operand:SI 3 "mask_operand" ""))
4771 (set (match_operand:SI 0 "gpc_reg_operand" "")
4772 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4773 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4775 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4777 (compare:CC (match_dup 0)
4782 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4785 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4786 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4787 "includes_rshift_p (operands[2], GEN_INT (255))"
4788 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4791 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4795 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4796 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4798 (clobber (match_scratch:SI 3 "=r,r"))]
4799 "includes_rshift_p (operands[2], GEN_INT (255))"
4801 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4803 [(set_attr "type" "delayed_compare")
4804 (set_attr "length" "4,8")])
4807 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4811 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4812 (match_operand:SI 2 "const_int_operand" "")) 0))
4814 (clobber (match_scratch:SI 3 ""))]
4815 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4817 (zero_extend:SI (subreg:QI
4818 (lshiftrt:SI (match_dup 1)
4821 (compare:CC (match_dup 3)
4826 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4830 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4831 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4833 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4834 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4835 "includes_rshift_p (operands[2], GEN_INT (255))"
4837 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4839 [(set_attr "type" "delayed_compare")
4840 (set_attr "length" "4,8")])
4843 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4847 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4848 (match_operand:SI 2 "const_int_operand" "")) 0))
4850 (set (match_operand:SI 0 "gpc_reg_operand" "")
4851 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4852 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4854 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4856 (compare:CC (match_dup 0)
4861 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4864 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4865 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4866 "includes_rshift_p (operands[2], GEN_INT (65535))"
4867 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4870 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4874 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4875 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4877 (clobber (match_scratch:SI 3 "=r,r"))]
4878 "includes_rshift_p (operands[2], GEN_INT (65535))"
4880 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4882 [(set_attr "type" "delayed_compare")
4883 (set_attr "length" "4,8")])
4886 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4890 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4891 (match_operand:SI 2 "const_int_operand" "")) 0))
4893 (clobber (match_scratch:SI 3 ""))]
4894 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4896 (zero_extend:SI (subreg:HI
4897 (lshiftrt:SI (match_dup 1)
4900 (compare:CC (match_dup 3)
4905 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4909 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4910 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4912 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4913 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4914 "includes_rshift_p (operands[2], GEN_INT (65535))"
4916 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4918 [(set_attr "type" "delayed_compare")
4919 (set_attr "length" "4,8")])
4922 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4926 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4927 (match_operand:SI 2 "const_int_operand" "")) 0))
4929 (set (match_operand:SI 0 "gpc_reg_operand" "")
4930 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4931 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4933 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4935 (compare:CC (match_dup 0)
4940 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4942 (match_operand:SI 1 "gpc_reg_operand" "r"))
4943 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4949 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4951 (match_operand:SI 1 "gpc_reg_operand" "r"))
4952 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4958 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4960 (match_operand:SI 1 "gpc_reg_operand" "r"))
4961 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4967 (define_expand "ashrsi3"
4968 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4969 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4970 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4975 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4977 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4981 (define_insn "ashrsi3_power"
4982 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4983 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4984 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4985 (clobber (match_scratch:SI 3 "=q,X"))]
4989 {srai|srawi} %0,%1,%h2"
4990 [(set_attr "type" "shift")])
4992 (define_insn "ashrsi3_no_power"
4993 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4994 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4995 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4999 {srai|srawi} %0,%1,%h2"
5000 [(set_attr "type" "var_shift_rotate,shift")])
5003 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5004 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5005 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5007 (clobber (match_scratch:SI 3 "=r,r,r,r"))
5008 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5012 {srai.|srawi.} %3,%1,%h2
5015 [(set_attr "type" "delayed_compare")
5016 (set_attr "length" "4,4,8,8")])
5019 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5020 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5021 (match_operand:SI 2 "reg_or_cint_operand" ""))
5023 (clobber (match_scratch:SI 3 ""))
5024 (clobber (match_scratch:SI 4 ""))]
5025 "TARGET_POWER && reload_completed"
5026 [(parallel [(set (match_dup 3)
5027 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5028 (clobber (match_dup 4))])
5030 (compare:CC (match_dup 3)
5035 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5036 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5037 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5039 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
5042 {sra.|sraw.} %3,%1,%2
5043 {srai.|srawi.} %3,%1,%h2
5046 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5047 (set_attr "length" "4,4,8,8")])
5050 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5051 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5052 (match_operand:SI 2 "reg_or_cint_operand" ""))
5054 (clobber (match_scratch:SI 3 ""))]
5055 "! TARGET_POWER && reload_completed"
5057 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5059 (compare:CC (match_dup 3)
5064 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5065 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5066 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5068 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5069 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5070 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5074 {srai.|srawi.} %0,%1,%h2
5077 [(set_attr "type" "delayed_compare")
5078 (set_attr "length" "4,4,8,8")])
5081 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5082 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5083 (match_operand:SI 2 "reg_or_cint_operand" ""))
5085 (set (match_operand:SI 0 "gpc_reg_operand" "")
5086 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5087 (clobber (match_scratch:SI 4 ""))]
5088 "TARGET_POWER && reload_completed"
5089 [(parallel [(set (match_dup 0)
5090 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5091 (clobber (match_dup 4))])
5093 (compare:CC (match_dup 0)
5098 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5099 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5100 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5102 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5103 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5106 {sra.|sraw.} %0,%1,%2
5107 {srai.|srawi.} %0,%1,%h2
5110 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5111 (set_attr "length" "4,4,8,8")])
5114 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5115 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5116 (match_operand:SI 2 "reg_or_cint_operand" ""))
5118 (set (match_operand:SI 0 "gpc_reg_operand" "")
5119 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5120 "! TARGET_POWER && reload_completed"
5122 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5124 (compare:CC (match_dup 0)
5128 ;; Floating-point insns, excluding normal data motion.
5130 ;; PowerPC has a full set of single-precision floating point instructions.
5132 ;; For the POWER architecture, we pretend that we have both SFmode and
5133 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
5134 ;; The only conversions we will do will be when storing to memory. In that
5135 ;; case, we will use the "frsp" instruction before storing.
5137 ;; Note that when we store into a single-precision memory location, we need to
5138 ;; use the frsp insn first. If the register being stored isn't dead, we
5139 ;; need a scratch register for the frsp. But this is difficult when the store
5140 ;; is done by reload. It is not incorrect to do the frsp on the register in
5141 ;; this case, we just lose precision that we would have otherwise gotten but
5142 ;; is not guaranteed. Perhaps this should be tightened up at some point.
5144 (define_expand "extendsfdf2"
5145 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5146 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5147 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5150 (define_insn_and_split "*extendsfdf2_fpr"
5151 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d")
5152 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
5153 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5158 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5161 emit_note (NOTE_INSN_DELETED);
5164 [(set_attr "type" "fp,fp,fpload")])
5166 (define_expand "truncdfsf2"
5167 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5168 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5169 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5172 (define_insn "*truncdfsf2_fpr"
5173 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5174 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5175 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5177 [(set_attr "type" "fp")])
5179 (define_insn "aux_truncdfsf2"
5180 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5181 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
5182 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5184 [(set_attr "type" "fp")])
5186 (define_expand "negsf2"
5187 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5188 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5189 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5192 (define_insn "*negsf2"
5193 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5194 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5195 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5197 [(set_attr "type" "fp")])
5199 (define_expand "abssf2"
5200 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5201 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5202 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5205 (define_insn "*abssf2"
5206 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5207 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5208 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5210 [(set_attr "type" "fp")])
5213 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5214 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
5215 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5217 [(set_attr "type" "fp")])
5219 (define_expand "addsf3"
5220 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5221 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5222 (match_operand:SF 2 "gpc_reg_operand" "")))]
5223 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5227 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5228 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5229 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5230 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5232 [(set_attr "type" "fp")
5233 (set_attr "fp_type" "fp_addsub_s")])
5236 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5237 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5238 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5239 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5240 "{fa|fadd} %0,%1,%2"
5241 [(set_attr "type" "fp")])
5243 (define_expand "subsf3"
5244 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5245 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5246 (match_operand:SF 2 "gpc_reg_operand" "")))]
5247 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5251 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5252 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5253 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5254 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5256 [(set_attr "type" "fp")
5257 (set_attr "fp_type" "fp_addsub_s")])
5260 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5261 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5262 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5263 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5264 "{fs|fsub} %0,%1,%2"
5265 [(set_attr "type" "fp")])
5267 (define_expand "mulsf3"
5268 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5269 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5270 (match_operand:SF 2 "gpc_reg_operand" "")))]
5271 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5275 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5276 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5277 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5278 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5280 [(set_attr "type" "fp")
5281 (set_attr "fp_type" "fp_mul_s")])
5284 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5285 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5286 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5287 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5288 "{fm|fmul} %0,%1,%2"
5289 [(set_attr "type" "dmul")])
5291 (define_expand "divsf3"
5292 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5293 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5294 (match_operand:SF 2 "gpc_reg_operand" "")))]
5295 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5299 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5300 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5301 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5302 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5303 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5305 [(set_attr "type" "sdiv")])
5308 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5309 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5310 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5311 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5312 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5313 "{fd|fdiv} %0,%1,%2"
5314 [(set_attr "type" "ddiv")])
5316 (define_expand "recipsf3"
5317 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5318 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")
5319 (match_operand:SF 2 "gpc_reg_operand" "f")]
5321 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5322 && flag_finite_math_only && !flag_trapping_math"
5324 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5329 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5330 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5331 "TARGET_PPC_GFXOPT && flag_finite_math_only"
5333 [(set_attr "type" "fp")])
5335 (define_insn "*fmaddsf4_powerpc"
5336 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5337 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5338 (match_operand:SF 2 "gpc_reg_operand" "f"))
5339 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5340 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5341 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5342 "fmadds %0,%1,%2,%3"
5343 [(set_attr "type" "fp")
5344 (set_attr "fp_type" "fp_maddsub_s")])
5346 (define_insn "*fmaddsf4_power"
5347 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5348 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5349 (match_operand:SF 2 "gpc_reg_operand" "f"))
5350 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5351 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5352 "{fma|fmadd} %0,%1,%2,%3"
5353 [(set_attr "type" "dmul")])
5355 (define_insn "*fmsubsf4_powerpc"
5356 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5357 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5358 (match_operand:SF 2 "gpc_reg_operand" "f"))
5359 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5360 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5361 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5362 "fmsubs %0,%1,%2,%3"
5363 [(set_attr "type" "fp")
5364 (set_attr "fp_type" "fp_maddsub_s")])
5366 (define_insn "*fmsubsf4_power"
5367 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5368 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5369 (match_operand:SF 2 "gpc_reg_operand" "f"))
5370 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5371 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5372 "{fms|fmsub} %0,%1,%2,%3"
5373 [(set_attr "type" "dmul")])
5375 (define_insn "*fnmaddsf4_powerpc_1"
5376 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5377 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5378 (match_operand:SF 2 "gpc_reg_operand" "f"))
5379 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5380 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5381 && TARGET_SINGLE_FLOAT && HONOR_SIGNED_ZEROS (SFmode)"
5382 "fnmadds %0,%1,%2,%3"
5383 [(set_attr "type" "fp")
5384 (set_attr "fp_type" "fp_maddsub_s")])
5386 (define_insn "*fnmaddsf4_powerpc_2"
5387 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5388 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5389 (match_operand:SF 2 "gpc_reg_operand" "f"))
5390 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5391 "TARGET_POWERPC && TARGET_SINGLE_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5392 && ! HONOR_SIGNED_ZEROS (SFmode)"
5393 "fnmadds %0,%1,%2,%3"
5394 [(set_attr "type" "fp")
5395 (set_attr "fp_type" "fp_maddsub_s")])
5397 (define_insn "*fnmaddsf4_power_1"
5398 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5399 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5400 (match_operand:SF 2 "gpc_reg_operand" "f"))
5401 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5402 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5403 "{fnma|fnmadd} %0,%1,%2,%3"
5404 [(set_attr "type" "dmul")])
5406 (define_insn "*fnmaddsf4_power_2"
5407 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5408 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5409 (match_operand:SF 2 "gpc_reg_operand" "f"))
5410 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5411 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5412 && ! HONOR_SIGNED_ZEROS (SFmode)"
5413 "{fnma|fnmadd} %0,%1,%2,%3"
5414 [(set_attr "type" "dmul")])
5416 (define_insn "*fnmsubsf4_powerpc_1"
5417 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5418 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5419 (match_operand:SF 2 "gpc_reg_operand" "f"))
5420 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5421 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5422 && TARGET_SINGLE_FLOAT && HONOR_SIGNED_ZEROS (SFmode)"
5423 "fnmsubs %0,%1,%2,%3"
5424 [(set_attr "type" "fp")
5425 (set_attr "fp_type" "fp_maddsub_s")])
5427 (define_insn "*fnmsubsf4_powerpc_2"
5428 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5429 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5430 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5431 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5432 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5433 && TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)"
5434 "fnmsubs %0,%1,%2,%3"
5435 [(set_attr "type" "fp")
5436 (set_attr "fp_type" "fp_maddsub_s")])
5438 (define_insn "*fnmsubsf4_power_1"
5439 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5440 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5441 (match_operand:SF 2 "gpc_reg_operand" "f"))
5442 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5443 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5444 "{fnms|fnmsub} %0,%1,%2,%3"
5445 [(set_attr "type" "dmul")])
5447 (define_insn "*fnmsubsf4_power_2"
5448 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5449 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5450 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5451 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5452 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5453 && ! HONOR_SIGNED_ZEROS (SFmode)"
5454 "{fnms|fnmsub} %0,%1,%2,%3"
5455 [(set_attr "type" "dmul")])
5457 (define_expand "sqrtsf2"
5458 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5459 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5460 "(TARGET_PPC_GPOPT || TARGET_POWER2 || TARGET_XILINX_FPU)
5461 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5462 && !TARGET_SIMPLE_FPU"
5466 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5467 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5468 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT
5469 && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5471 [(set_attr "type" "ssqrt")])
5474 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5475 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5476 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS
5477 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5479 [(set_attr "type" "dsqrt")])
5481 (define_expand "rsqrtsf2"
5482 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5483 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5485 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5486 && flag_finite_math_only && !flag_trapping_math"
5488 rs6000_emit_swrsqrtsf (operands[0], operands[1]);
5492 (define_insn "*rsqrt_internal1"
5493 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5494 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5496 "TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT"
5498 [(set_attr "type" "fp")])
5500 (define_expand "copysignsf3"
5502 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5504 (neg:SF (abs:SF (match_dup 1))))
5505 (set (match_operand:SF 0 "gpc_reg_operand" "")
5506 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5510 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5511 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
5513 operands[3] = gen_reg_rtx (SFmode);
5514 operands[4] = gen_reg_rtx (SFmode);
5515 operands[5] = CONST0_RTX (SFmode);
5518 (define_expand "copysigndf3"
5520 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5522 (neg:DF (abs:DF (match_dup 1))))
5523 (set (match_operand:DF 0 "gpc_reg_operand" "")
5524 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5528 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5529 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
5531 operands[3] = gen_reg_rtx (DFmode);
5532 operands[4] = gen_reg_rtx (DFmode);
5533 operands[5] = CONST0_RTX (DFmode);
5536 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5537 ;; fsel instruction and some auxiliary computations. Then we just have a
5538 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5540 (define_expand "smaxsf3"
5541 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5542 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5543 (match_operand:SF 2 "gpc_reg_operand" ""))
5546 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5547 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5548 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5550 (define_expand "sminsf3"
5551 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5552 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5553 (match_operand:SF 2 "gpc_reg_operand" ""))
5556 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5557 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5558 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5561 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5562 (match_operator:SF 3 "min_max_operator"
5563 [(match_operand:SF 1 "gpc_reg_operand" "")
5564 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5565 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5566 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5569 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5570 operands[1], operands[2]);
5574 (define_expand "mov<mode>cc"
5575 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
5576 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5577 (match_operand:GPR 2 "gpc_reg_operand" "")
5578 (match_operand:GPR 3 "gpc_reg_operand" "")))]
5582 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5588 ;; We use the BASE_REGS for the isel input operands because, if rA is
5589 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5590 ;; because we may switch the operands and rB may end up being rA.
5592 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5593 ;; leave out the mode in operand 4 and use one pattern, but reload can
5594 ;; change the mode underneath our feet and then gets confused trying
5595 ;; to reload the value.
5596 (define_insn "isel_signed_<mode>"
5597 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5599 (match_operator 1 "comparison_operator"
5600 [(match_operand:CC 4 "cc_reg_operand" "y")
5602 (match_operand:GPR 2 "gpc_reg_operand" "b")
5603 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5606 { return output_isel (operands); }"
5607 [(set_attr "length" "4")])
5609 (define_insn "isel_unsigned_<mode>"
5610 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5612 (match_operator 1 "comparison_operator"
5613 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5615 (match_operand:GPR 2 "gpc_reg_operand" "b")
5616 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5619 { return output_isel (operands); }"
5620 [(set_attr "length" "4")])
5622 (define_expand "movsfcc"
5623 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5624 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5625 (match_operand:SF 2 "gpc_reg_operand" "")
5626 (match_operand:SF 3 "gpc_reg_operand" "")))]
5627 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5630 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5636 (define_insn "*fselsfsf4"
5637 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5638 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5639 (match_operand:SF 4 "zero_fp_constant" "F"))
5640 (match_operand:SF 2 "gpc_reg_operand" "f")
5641 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5642 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5644 [(set_attr "type" "fp")])
5646 (define_insn "*fseldfsf4"
5647 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5648 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5649 (match_operand:DF 4 "zero_fp_constant" "F"))
5650 (match_operand:SF 2 "gpc_reg_operand" "f")
5651 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5652 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5654 [(set_attr "type" "fp")])
5656 (define_expand "negdf2"
5657 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5658 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5659 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5662 (define_insn "*negdf2_fpr"
5663 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5664 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5665 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5667 [(set_attr "type" "fp")])
5669 (define_expand "absdf2"
5670 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5671 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5672 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5675 (define_insn "*absdf2_fpr"
5676 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5677 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5678 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5680 [(set_attr "type" "fp")])
5682 (define_insn "*nabsdf2_fpr"
5683 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5684 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))]
5685 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5687 [(set_attr "type" "fp")])
5689 (define_expand "adddf3"
5690 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5691 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5692 (match_operand:DF 2 "gpc_reg_operand" "")))]
5693 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5696 (define_insn "*adddf3_fpr"
5697 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5698 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
5699 (match_operand:DF 2 "gpc_reg_operand" "d")))]
5700 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5701 "{fa|fadd} %0,%1,%2"
5702 [(set_attr "type" "fp")
5703 (set_attr "fp_type" "fp_addsub_d")])
5705 (define_expand "subdf3"
5706 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5707 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5708 (match_operand:DF 2 "gpc_reg_operand" "")))]
5709 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5712 (define_insn "*subdf3_fpr"
5713 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5714 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d")
5715 (match_operand:DF 2 "gpc_reg_operand" "d")))]
5716 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5717 "{fs|fsub} %0,%1,%2"
5718 [(set_attr "type" "fp")
5719 (set_attr "fp_type" "fp_addsub_d")])
5721 (define_expand "muldf3"
5722 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5723 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5724 (match_operand:DF 2 "gpc_reg_operand" "")))]
5725 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5728 (define_insn "*muldf3_fpr"
5729 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5730 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
5731 (match_operand:DF 2 "gpc_reg_operand" "d")))]
5732 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5733 "{fm|fmul} %0,%1,%2"
5734 [(set_attr "type" "dmul")
5735 (set_attr "fp_type" "fp_mul_d")])
5737 (define_expand "divdf3"
5738 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5739 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5740 (match_operand:DF 2 "gpc_reg_operand" "")))]
5742 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)
5743 && !TARGET_SIMPLE_FPU"
5746 (define_insn "*divdf3_fpr"
5747 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5748 (div:DF (match_operand:DF 1 "gpc_reg_operand" "d")
5749 (match_operand:DF 2 "gpc_reg_operand" "d")))]
5750 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU"
5751 "{fd|fdiv} %0,%1,%2"
5752 [(set_attr "type" "ddiv")])
5754 (define_expand "recipdf3"
5755 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5756 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")
5757 (match_operand:DF 2 "gpc_reg_operand" "d")]
5759 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_POPCNTB && !optimize_size
5760 && flag_finite_math_only && !flag_trapping_math"
5762 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5767 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5768 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRES))]
5769 "TARGET_POPCNTB && flag_finite_math_only"
5771 [(set_attr "type" "fp")])
5774 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5775 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
5776 (match_operand:DF 2 "gpc_reg_operand" "d"))
5777 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5778 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT"
5779 "{fma|fmadd} %0,%1,%2,%3"
5780 [(set_attr "type" "dmul")
5781 (set_attr "fp_type" "fp_maddsub_d")])
5784 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5785 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
5786 (match_operand:DF 2 "gpc_reg_operand" "d"))
5787 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5788 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT"
5789 "{fms|fmsub} %0,%1,%2,%3"
5790 [(set_attr "type" "dmul")
5791 (set_attr "fp_type" "fp_maddsub_d")])
5794 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5795 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
5796 (match_operand:DF 2 "gpc_reg_operand" "d"))
5797 (match_operand:DF 3 "gpc_reg_operand" "d"))))]
5798 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
5799 && HONOR_SIGNED_ZEROS (DFmode)"
5800 "{fnma|fnmadd} %0,%1,%2,%3"
5801 [(set_attr "type" "dmul")
5802 (set_attr "fp_type" "fp_maddsub_d")])
5805 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5806 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d"))
5807 (match_operand:DF 2 "gpc_reg_operand" "d"))
5808 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5809 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
5810 && ! HONOR_SIGNED_ZEROS (DFmode)"
5811 "{fnma|fnmadd} %0,%1,%2,%3"
5812 [(set_attr "type" "dmul")
5813 (set_attr "fp_type" "fp_maddsub_d")])
5816 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5817 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
5818 (match_operand:DF 2 "gpc_reg_operand" "d"))
5819 (match_operand:DF 3 "gpc_reg_operand" "d"))))]
5820 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
5821 && HONOR_SIGNED_ZEROS (DFmode)"
5822 "{fnms|fnmsub} %0,%1,%2,%3"
5823 [(set_attr "type" "dmul")
5824 (set_attr "fp_type" "fp_maddsub_d")])
5827 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5828 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "d")
5829 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
5830 (match_operand:DF 2 "gpc_reg_operand" "d"))))]
5831 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
5832 && ! HONOR_SIGNED_ZEROS (DFmode)"
5833 "{fnms|fnmsub} %0,%1,%2,%3"
5834 [(set_attr "type" "dmul")
5835 (set_attr "fp_type" "fp_maddsub_d")])
5837 (define_insn "sqrtdf2"
5838 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5839 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5840 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
5841 && TARGET_DOUBLE_FLOAT"
5843 [(set_attr "type" "dsqrt")])
5845 ;; The conditional move instructions allow us to perform max and min
5846 ;; operations even when
5848 (define_expand "smaxdf3"
5849 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5850 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5851 (match_operand:DF 2 "gpc_reg_operand" ""))
5854 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5855 && !flag_trapping_math"
5856 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5858 (define_expand "smindf3"
5859 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5860 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5861 (match_operand:DF 2 "gpc_reg_operand" ""))
5864 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5865 && !flag_trapping_math"
5866 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5869 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5870 (match_operator:DF 3 "min_max_operator"
5871 [(match_operand:DF 1 "gpc_reg_operand" "")
5872 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5873 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5874 && !flag_trapping_math"
5877 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5878 operands[1], operands[2]);
5882 (define_expand "movdfcc"
5883 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5884 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5885 (match_operand:DF 2 "gpc_reg_operand" "")
5886 (match_operand:DF 3 "gpc_reg_operand" "")))]
5887 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5890 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5896 (define_insn "*fseldfdf4"
5897 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5898 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5899 (match_operand:DF 4 "zero_fp_constant" "F"))
5900 (match_operand:DF 2 "gpc_reg_operand" "d")
5901 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5902 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5904 [(set_attr "type" "fp")])
5906 (define_insn "*fselsfdf4"
5907 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5908 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5909 (match_operand:SF 4 "zero_fp_constant" "F"))
5910 (match_operand:DF 2 "gpc_reg_operand" "d")
5911 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5912 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5914 [(set_attr "type" "fp")])
5916 ;; Conversions to and from floating-point.
5918 (define_expand "fixuns_truncsfsi2"
5919 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5920 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5921 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
5924 (define_expand "fix_truncsfsi2"
5925 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5926 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5927 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
5930 (define_expand "fixuns_truncdfsi2"
5931 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5932 (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))]
5933 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
5936 ; For each of these conversions, there is a define_expand, a define_insn
5937 ; with a '#' template, and a define_split (with C code). The idea is
5938 ; to allow constant folding with the template of the define_insn,
5939 ; then to have the insns split later (between sched1 and final).
5941 (define_expand "floatsidf2"
5942 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5943 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5946 (clobber (match_dup 4))
5947 (clobber (match_dup 5))
5948 (clobber (match_dup 6))])]
5950 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5953 if (TARGET_E500_DOUBLE)
5955 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5958 if (TARGET_POWERPC64)
5960 rtx x = convert_to_mode (DImode, operands[1], 0);
5961 emit_insn (gen_floatdidf2 (operands[0], x));
5965 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5966 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5967 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5968 operands[5] = gen_reg_rtx (DFmode);
5969 operands[6] = gen_reg_rtx (SImode);
5972 (define_insn_and_split "*floatsidf2_internal"
5973 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5974 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5975 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5976 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5977 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5978 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
5979 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5980 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5982 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
5986 rtx lowword, highword;
5987 gcc_assert (MEM_P (operands[4]));
5988 highword = adjust_address (operands[4], SImode, 0);
5989 lowword = adjust_address (operands[4], SImode, 4);
5990 if (! WORDS_BIG_ENDIAN)
5993 tmp = highword; highword = lowword; lowword = tmp;
5996 emit_insn (gen_xorsi3 (operands[6], operands[1],
5997 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5998 emit_move_insn (lowword, operands[6]);
5999 emit_move_insn (highword, operands[2]);
6000 emit_move_insn (operands[5], operands[4]);
6001 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6004 [(set_attr "length" "24")])
6006 (define_expand "floatunssisf2"
6007 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6008 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6009 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
6012 (define_expand "floatunssidf2"
6013 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
6014 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
6017 (clobber (match_dup 4))
6018 (clobber (match_dup 5))])]
6019 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6022 if (TARGET_E500_DOUBLE)
6024 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
6027 if (TARGET_POWERPC64)
6029 rtx x = convert_to_mode (DImode, operands[1], 1);
6030 emit_insn (gen_floatdidf2 (operands[0], x));
6034 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
6035 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
6036 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
6037 operands[5] = gen_reg_rtx (DFmode);
6040 (define_insn_and_split "*floatunssidf2_internal"
6041 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
6042 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6043 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6044 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
6045 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6046 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
6047 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6049 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
6053 rtx lowword, highword;
6054 gcc_assert (MEM_P (operands[4]));
6055 highword = adjust_address (operands[4], SImode, 0);
6056 lowword = adjust_address (operands[4], SImode, 4);
6057 if (! WORDS_BIG_ENDIAN)
6060 tmp = highword; highword = lowword; lowword = tmp;
6063 emit_move_insn (lowword, operands[1]);
6064 emit_move_insn (highword, operands[2]);
6065 emit_move_insn (operands[5], operands[4]);
6066 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6069 [(set_attr "length" "20")])
6071 (define_expand "fix_truncdfsi2"
6072 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
6073 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
6074 (clobber (match_dup 2))
6075 (clobber (match_dup 3))])]
6076 "(TARGET_POWER2 || TARGET_POWERPC)
6077 && TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6080 if (TARGET_E500_DOUBLE)
6082 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
6085 operands[2] = gen_reg_rtx (DImode);
6086 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
6087 && gpc_reg_operand(operands[0], GET_MODE (operands[0])))
6089 operands[3] = gen_reg_rtx (DImode);
6090 emit_insn (gen_fix_truncdfsi2_mfpgpr (operands[0], operands[1],
6091 operands[2], operands[3]));
6094 if (TARGET_PPC_GFXOPT)
6096 rtx orig_dest = operands[0];
6097 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
6098 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
6099 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
6101 if (operands[0] != orig_dest)
6102 emit_move_insn (orig_dest, operands[0]);
6105 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
6108 (define_insn_and_split "*fix_truncdfsi2_internal"
6109 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6110 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6111 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))
6112 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))]
6113 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6114 && TARGET_DOUBLE_FLOAT"
6116 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[3]))"
6121 gcc_assert (MEM_P (operands[3]));
6122 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
6124 emit_insn (gen_fctiwz (operands[2], operands[1]));
6125 emit_move_insn (operands[3], operands[2]);
6126 emit_move_insn (operands[0], lowword);
6129 [(set_attr "length" "16")])
6131 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
6132 [(set (match_operand:SI 0 "memory_operand" "=Z")
6133 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6134 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))]
6135 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6136 && TARGET_DOUBLE_FLOAT
6137 && TARGET_PPC_GFXOPT"
6143 emit_insn (gen_fctiwz (operands[2], operands[1]));
6144 emit_insn (gen_stfiwx (operands[0], operands[2]));
6147 [(set_attr "length" "16")])
6149 (define_insn_and_split "fix_truncdfsi2_mfpgpr"
6150 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6151 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6152 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))
6153 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
6154 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
6155 && TARGET_DOUBLE_FLOAT"
6158 [(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
6159 (set (match_dup 3) (match_dup 2))
6160 (set (match_dup 0) (subreg:SI (match_dup 3) 4))]
6162 [(set_attr "length" "12")])
6164 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6165 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6166 ; because the first makes it clear that operand 0 is not live
6167 ; before the instruction.
6168 (define_insn "fctiwz"
6169 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6170 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "d"))]
6172 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6173 && TARGET_DOUBLE_FLOAT"
6174 "{fcirz|fctiwz} %0,%1"
6175 [(set_attr "type" "fp")])
6177 (define_insn "btruncdf2"
6178 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6179 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIZ))]
6180 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6182 [(set_attr "type" "fp")])
6184 (define_insn "btruncsf2"
6185 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6186 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6187 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6189 [(set_attr "type" "fp")])
6191 (define_insn "ceildf2"
6192 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6193 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIP))]
6194 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6196 [(set_attr "type" "fp")])
6198 (define_insn "ceilsf2"
6199 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6200 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6201 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6203 [(set_attr "type" "fp")])
6205 (define_insn "floordf2"
6206 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6207 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIM))]
6208 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6210 [(set_attr "type" "fp")])
6212 (define_insn "floorsf2"
6213 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6214 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6215 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6217 [(set_attr "type" "fp")])
6219 (define_insn "rounddf2"
6220 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6221 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIN))]
6222 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6224 [(set_attr "type" "fp")])
6226 (define_insn "roundsf2"
6227 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6228 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6229 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6231 [(set_attr "type" "fp")])
6233 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6234 (define_insn "stfiwx"
6235 [(set (match_operand:SI 0 "memory_operand" "=Z")
6236 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
6240 [(set_attr "type" "fpstore")])
6242 (define_expand "floatsisf2"
6243 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6244 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6245 "TARGET_HARD_FLOAT && !TARGET_FPRS"
6248 (define_insn "floatdidf2"
6249 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6250 (float:DF (match_operand:DI 1 "gpc_reg_operand" "!d#r")))]
6251 "(TARGET_POWERPC64 || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6253 [(set_attr "type" "fp")])
6255 (define_insn "fix_truncdfdi2"
6256 [(set (match_operand:DI 0 "gpc_reg_operand" "=!d#r")
6257 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d")))]
6258 "(TARGET_POWERPC64 || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6260 [(set_attr "type" "fp")])
6262 (define_expand "floatdisf2"
6263 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6264 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6265 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6268 rtx val = operands[1];
6269 if (!flag_unsafe_math_optimizations)
6271 rtx label = gen_label_rtx ();
6272 val = gen_reg_rtx (DImode);
6273 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6276 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6280 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6281 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6282 ;; from double rounding.
6283 (define_insn_and_split "floatdisf2_internal1"
6284 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6285 (float:SF (match_operand:DI 1 "gpc_reg_operand" "!d#r")))
6286 (clobber (match_scratch:DF 2 "=d"))]
6287 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6289 "&& reload_completed"
6291 (float:DF (match_dup 1)))
6293 (float_truncate:SF (match_dup 2)))]
6296 ;; Twiddles bits to avoid double rounding.
6297 ;; Bits that might be truncated when converting to DFmode are replaced
6298 ;; by a bit that won't be lost at that stage, but is below the SFmode
6299 ;; rounding position.
6300 (define_expand "floatdisf2_internal2"
6301 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6303 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6305 (clobber (scratch:CC))])
6306 (set (match_dup 3) (plus:DI (match_dup 3)
6308 (set (match_dup 0) (plus:DI (match_dup 0)
6310 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6312 (set (match_dup 0) (ior:DI (match_dup 0)
6314 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6316 (clobber (scratch:CC))])
6317 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6318 (label_ref (match_operand:DI 2 "" ""))
6320 (set (match_dup 0) (match_dup 1))]
6321 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6324 operands[3] = gen_reg_rtx (DImode);
6325 operands[4] = gen_reg_rtx (CCUNSmode);
6328 ;; Define the DImode operations that can be done in a small number
6329 ;; of instructions. The & constraints are to prevent the register
6330 ;; allocator from allocating registers that overlap with the inputs
6331 ;; (for example, having an input in 7,8 and an output in 6,7). We
6332 ;; also allow for the output being the same as one of the inputs.
6334 (define_insn "*adddi3_noppc64"
6335 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6336 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6337 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6338 "! TARGET_POWERPC64"
6341 if (WORDS_BIG_ENDIAN)
6342 return (GET_CODE (operands[2])) != CONST_INT
6343 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6344 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6346 return (GET_CODE (operands[2])) != CONST_INT
6347 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6348 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6350 [(set_attr "type" "two")
6351 (set_attr "length" "8")])
6353 (define_insn "*subdi3_noppc64"
6354 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6355 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6356 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6357 "! TARGET_POWERPC64"
6360 if (WORDS_BIG_ENDIAN)
6361 return (GET_CODE (operands[1]) != CONST_INT)
6362 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6363 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6365 return (GET_CODE (operands[1]) != CONST_INT)
6366 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6367 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
6369 [(set_attr "type" "two")
6370 (set_attr "length" "8")])
6372 (define_insn "*negdi2_noppc64"
6373 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6374 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6375 "! TARGET_POWERPC64"
6378 return (WORDS_BIG_ENDIAN)
6379 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6380 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6382 [(set_attr "type" "two")
6383 (set_attr "length" "8")])
6385 (define_expand "mulsidi3"
6386 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6387 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6388 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6389 "! TARGET_POWERPC64"
6392 if (! TARGET_POWER && ! TARGET_POWERPC)
6394 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6395 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6396 emit_insn (gen_mull_call ());
6397 if (WORDS_BIG_ENDIAN)
6398 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
6401 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
6402 gen_rtx_REG (SImode, 3));
6403 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
6404 gen_rtx_REG (SImode, 4));
6408 else if (TARGET_POWER)
6410 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6415 (define_insn "mulsidi3_mq"
6416 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6417 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6418 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6419 (clobber (match_scratch:SI 3 "=q"))]
6421 "mul %0,%1,%2\;mfmq %L0"
6422 [(set_attr "type" "imul")
6423 (set_attr "length" "8")])
6425 (define_insn "*mulsidi3_no_mq"
6426 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6427 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6428 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6429 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6432 return (WORDS_BIG_ENDIAN)
6433 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6434 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6436 [(set_attr "type" "imul")
6437 (set_attr "length" "8")])
6440 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6441 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6442 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6443 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6446 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6447 (sign_extend:DI (match_dup 2)))
6450 (mult:SI (match_dup 1)
6454 int endian = (WORDS_BIG_ENDIAN == 0);
6455 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6456 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6459 (define_expand "umulsidi3"
6460 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6461 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6462 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6463 "TARGET_POWERPC && ! TARGET_POWERPC64"
6468 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6473 (define_insn "umulsidi3_mq"
6474 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6475 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6476 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6477 (clobber (match_scratch:SI 3 "=q"))]
6478 "TARGET_POWERPC && TARGET_POWER"
6481 return (WORDS_BIG_ENDIAN)
6482 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6483 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6485 [(set_attr "type" "imul")
6486 (set_attr "length" "8")])
6488 (define_insn "*umulsidi3_no_mq"
6489 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6490 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6491 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6492 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6495 return (WORDS_BIG_ENDIAN)
6496 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6497 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6499 [(set_attr "type" "imul")
6500 (set_attr "length" "8")])
6503 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6504 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6505 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6506 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6509 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6510 (zero_extend:DI (match_dup 2)))
6513 (mult:SI (match_dup 1)
6517 int endian = (WORDS_BIG_ENDIAN == 0);
6518 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6519 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6522 (define_expand "smulsi3_highpart"
6523 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6525 (lshiftrt:DI (mult:DI (sign_extend:DI
6526 (match_operand:SI 1 "gpc_reg_operand" ""))
6528 (match_operand:SI 2 "gpc_reg_operand" "")))
6533 if (! TARGET_POWER && ! TARGET_POWERPC)
6535 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6536 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6537 emit_insn (gen_mulh_call ());
6538 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
6541 else if (TARGET_POWER)
6543 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6548 (define_insn "smulsi3_highpart_mq"
6549 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6551 (lshiftrt:DI (mult:DI (sign_extend:DI
6552 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6554 (match_operand:SI 2 "gpc_reg_operand" "r")))
6556 (clobber (match_scratch:SI 3 "=q"))]
6559 [(set_attr "type" "imul")])
6561 (define_insn "*smulsi3_highpart_no_mq"
6562 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6564 (lshiftrt:DI (mult:DI (sign_extend:DI
6565 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6567 (match_operand:SI 2 "gpc_reg_operand" "r")))
6569 "TARGET_POWERPC && ! TARGET_POWER"
6571 [(set_attr "type" "imul")])
6573 (define_expand "umulsi3_highpart"
6574 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6576 (lshiftrt:DI (mult:DI (zero_extend:DI
6577 (match_operand:SI 1 "gpc_reg_operand" ""))
6579 (match_operand:SI 2 "gpc_reg_operand" "")))
6586 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6591 (define_insn "umulsi3_highpart_mq"
6592 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6594 (lshiftrt:DI (mult:DI (zero_extend:DI
6595 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6597 (match_operand:SI 2 "gpc_reg_operand" "r")))
6599 (clobber (match_scratch:SI 3 "=q"))]
6600 "TARGET_POWERPC && TARGET_POWER"
6602 [(set_attr "type" "imul")])
6604 (define_insn "*umulsi3_highpart_no_mq"
6605 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6607 (lshiftrt:DI (mult:DI (zero_extend:DI
6608 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6610 (match_operand:SI 2 "gpc_reg_operand" "r")))
6612 "TARGET_POWERPC && ! TARGET_POWER"
6614 [(set_attr "type" "imul")])
6616 ;; If operands 0 and 2 are in the same register, we have a problem. But
6617 ;; operands 0 and 1 (the usual case) can be in the same register. That's
6618 ;; why we have the strange constraints below.
6619 (define_insn "ashldi3_power"
6620 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6621 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6622 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6623 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6626 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
6627 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6628 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6629 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
6630 [(set_attr "length" "8")])
6632 (define_insn "lshrdi3_power"
6633 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6634 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6635 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6636 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6639 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
6640 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6641 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6642 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
6643 [(set_attr "length" "8")])
6645 ;; Shift by a variable amount is too complex to be worth open-coding. We
6646 ;; just handle shifts by constants.
6647 (define_insn "ashrdi3_power"
6648 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6649 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6650 (match_operand:SI 2 "const_int_operand" "M,i")))
6651 (clobber (match_scratch:SI 3 "=X,q"))]
6654 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6655 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
6656 [(set_attr "type" "shift")
6657 (set_attr "length" "8")])
6659 (define_insn "ashrdi3_no_power"
6660 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6661 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6662 (match_operand:SI 2 "const_int_operand" "M,i")))]
6663 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
6665 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6666 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
6667 [(set_attr "type" "two,three")
6668 (set_attr "length" "8,12")])
6670 (define_insn "*ashrdisi3_noppc64"
6671 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6672 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6673 (const_int 32)) 4))]
6674 "TARGET_32BIT && !TARGET_POWERPC64"
6677 if (REGNO (operands[0]) == REGNO (operands[1]))
6680 return \"mr %0,%1\";
6682 [(set_attr "length" "4")])
6685 ;; PowerPC64 DImode operations.
6687 (define_insn_and_split "absdi2"
6688 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6689 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6690 (clobber (match_scratch:DI 2 "=&r,&r"))]
6693 "&& reload_completed"
6694 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6695 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6696 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6699 (define_insn_and_split "*nabsdi2"
6700 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6701 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6702 (clobber (match_scratch:DI 2 "=&r,&r"))]
6705 "&& reload_completed"
6706 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6707 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6708 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
6711 (define_insn "muldi3"
6712 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6713 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6714 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6720 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6721 (const_string "imul3")
6722 (match_operand:SI 2 "short_cint_operand" "")
6723 (const_string "imul2")]
6724 (const_string "lmul")))])
6726 (define_insn "*muldi3_internal1"
6727 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6728 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6729 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6731 (clobber (match_scratch:DI 3 "=r,r"))]
6736 [(set_attr "type" "lmul_compare")
6737 (set_attr "length" "4,8")])
6740 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6741 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6742 (match_operand:DI 2 "gpc_reg_operand" ""))
6744 (clobber (match_scratch:DI 3 ""))]
6745 "TARGET_POWERPC64 && reload_completed"
6747 (mult:DI (match_dup 1) (match_dup 2)))
6749 (compare:CC (match_dup 3)
6753 (define_insn "*muldi3_internal2"
6754 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6755 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6756 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6758 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6759 (mult:DI (match_dup 1) (match_dup 2)))]
6764 [(set_attr "type" "lmul_compare")
6765 (set_attr "length" "4,8")])
6768 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6769 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6770 (match_operand:DI 2 "gpc_reg_operand" ""))
6772 (set (match_operand:DI 0 "gpc_reg_operand" "")
6773 (mult:DI (match_dup 1) (match_dup 2)))]
6774 "TARGET_POWERPC64 && reload_completed"
6776 (mult:DI (match_dup 1) (match_dup 2)))
6778 (compare:CC (match_dup 0)
6782 (define_insn "smuldi3_highpart"
6783 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6785 (lshiftrt:TI (mult:TI (sign_extend:TI
6786 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6788 (match_operand:DI 2 "gpc_reg_operand" "r")))
6792 [(set_attr "type" "lmul")])
6794 (define_insn "umuldi3_highpart"
6795 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6797 (lshiftrt:TI (mult:TI (zero_extend:TI
6798 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6800 (match_operand:DI 2 "gpc_reg_operand" "r")))
6804 [(set_attr "type" "lmul")])
6806 (define_insn "rotldi3"
6807 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6808 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6809 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
6814 [(set_attr "type" "var_shift_rotate,integer")])
6816 (define_insn "*rotldi3_internal2"
6817 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6818 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6819 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6821 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6828 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6829 (set_attr "length" "4,4,8,8")])
6832 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6833 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6834 (match_operand:DI 2 "reg_or_cint_operand" ""))
6836 (clobber (match_scratch:DI 3 ""))]
6837 "TARGET_POWERPC64 && reload_completed"
6839 (rotate:DI (match_dup 1) (match_dup 2)))
6841 (compare:CC (match_dup 3)
6845 (define_insn "*rotldi3_internal3"
6846 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6847 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6848 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6850 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6851 (rotate:DI (match_dup 1) (match_dup 2)))]
6858 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6859 (set_attr "length" "4,4,8,8")])
6862 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6863 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6864 (match_operand:DI 2 "reg_or_cint_operand" ""))
6866 (set (match_operand:DI 0 "gpc_reg_operand" "")
6867 (rotate:DI (match_dup 1) (match_dup 2)))]
6868 "TARGET_POWERPC64 && reload_completed"
6870 (rotate:DI (match_dup 1) (match_dup 2)))
6872 (compare:CC (match_dup 0)
6876 (define_insn "*rotldi3_internal4"
6877 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6878 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6879 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6880 (match_operand:DI 3 "mask64_operand" "n,n")))]
6883 rldc%B3 %0,%1,%2,%S3
6884 rldic%B3 %0,%1,%H2,%S3"
6885 [(set_attr "type" "var_shift_rotate,integer")])
6887 (define_insn "*rotldi3_internal5"
6888 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6890 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6891 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6892 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6894 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
6897 rldc%B3. %4,%1,%2,%S3
6898 rldic%B3. %4,%1,%H2,%S3
6901 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6902 (set_attr "length" "4,4,8,8")])
6905 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6907 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6908 (match_operand:DI 2 "reg_or_cint_operand" ""))
6909 (match_operand:DI 3 "mask64_operand" ""))
6911 (clobber (match_scratch:DI 4 ""))]
6912 "TARGET_POWERPC64 && reload_completed"
6914 (and:DI (rotate:DI (match_dup 1)
6918 (compare:CC (match_dup 4)
6922 (define_insn "*rotldi3_internal6"
6923 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
6925 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6926 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6927 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6929 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6930 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6933 rldc%B3. %0,%1,%2,%S3
6934 rldic%B3. %0,%1,%H2,%S3
6937 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6938 (set_attr "length" "4,4,8,8")])
6941 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
6943 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6944 (match_operand:DI 2 "reg_or_cint_operand" ""))
6945 (match_operand:DI 3 "mask64_operand" ""))
6947 (set (match_operand:DI 0 "gpc_reg_operand" "")
6948 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6949 "TARGET_POWERPC64 && reload_completed"
6951 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6953 (compare:CC (match_dup 0)
6957 (define_insn "*rotldi3_internal7"
6958 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6961 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6962 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6966 rldicl %0,%1,%H2,56"
6967 [(set_attr "type" "var_shift_rotate,integer")])
6969 (define_insn "*rotldi3_internal8"
6970 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6971 (compare:CC (zero_extend:DI
6973 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6974 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6976 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6980 rldicl. %3,%1,%H2,56
6983 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6984 (set_attr "length" "4,4,8,8")])
6987 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6988 (compare:CC (zero_extend:DI
6990 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6991 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6993 (clobber (match_scratch:DI 3 ""))]
6994 "TARGET_POWERPC64 && reload_completed"
6996 (zero_extend:DI (subreg:QI
6997 (rotate:DI (match_dup 1)
7000 (compare:CC (match_dup 3)
7004 (define_insn "*rotldi3_internal9"
7005 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7006 (compare:CC (zero_extend:DI
7008 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7009 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7011 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7012 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7016 rldicl. %0,%1,%H2,56
7019 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7020 (set_attr "length" "4,4,8,8")])
7023 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7024 (compare:CC (zero_extend:DI
7026 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7027 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7029 (set (match_operand:DI 0 "gpc_reg_operand" "")
7030 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7031 "TARGET_POWERPC64 && reload_completed"
7033 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7035 (compare:CC (match_dup 0)
7039 (define_insn "*rotldi3_internal10"
7040 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7043 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7044 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7048 rldicl %0,%1,%H2,48"
7049 [(set_attr "type" "var_shift_rotate,integer")])
7051 (define_insn "*rotldi3_internal11"
7052 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7053 (compare:CC (zero_extend:DI
7055 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7056 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7058 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7062 rldicl. %3,%1,%H2,48
7065 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7066 (set_attr "length" "4,4,8,8")])
7069 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7070 (compare:CC (zero_extend:DI
7072 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7073 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7075 (clobber (match_scratch:DI 3 ""))]
7076 "TARGET_POWERPC64 && reload_completed"
7078 (zero_extend:DI (subreg:HI
7079 (rotate:DI (match_dup 1)
7082 (compare:CC (match_dup 3)
7086 (define_insn "*rotldi3_internal12"
7087 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7088 (compare:CC (zero_extend:DI
7090 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7091 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7093 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7094 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7098 rldicl. %0,%1,%H2,48
7101 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7102 (set_attr "length" "4,4,8,8")])
7105 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7106 (compare:CC (zero_extend:DI
7108 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7109 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7111 (set (match_operand:DI 0 "gpc_reg_operand" "")
7112 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7113 "TARGET_POWERPC64 && reload_completed"
7115 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7117 (compare:CC (match_dup 0)
7121 (define_insn "*rotldi3_internal13"
7122 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7125 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7126 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7130 rldicl %0,%1,%H2,32"
7131 [(set_attr "type" "var_shift_rotate,integer")])
7133 (define_insn "*rotldi3_internal14"
7134 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7135 (compare:CC (zero_extend:DI
7137 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7138 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7140 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7144 rldicl. %3,%1,%H2,32
7147 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7148 (set_attr "length" "4,4,8,8")])
7151 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7152 (compare:CC (zero_extend:DI
7154 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7155 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7157 (clobber (match_scratch:DI 3 ""))]
7158 "TARGET_POWERPC64 && reload_completed"
7160 (zero_extend:DI (subreg:SI
7161 (rotate:DI (match_dup 1)
7164 (compare:CC (match_dup 3)
7168 (define_insn "*rotldi3_internal15"
7169 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7170 (compare:CC (zero_extend:DI
7172 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7173 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7175 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7176 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7180 rldicl. %0,%1,%H2,32
7183 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7184 (set_attr "length" "4,4,8,8")])
7187 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7188 (compare:CC (zero_extend:DI
7190 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7191 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7193 (set (match_operand:DI 0 "gpc_reg_operand" "")
7194 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7195 "TARGET_POWERPC64 && reload_completed"
7197 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7199 (compare:CC (match_dup 0)
7203 (define_expand "ashldi3"
7204 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7205 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7206 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7207 "TARGET_POWERPC64 || TARGET_POWER"
7210 if (TARGET_POWERPC64)
7212 else if (TARGET_POWER)
7214 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
7221 (define_insn "*ashldi3_internal1"
7222 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7223 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7224 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7229 [(set_attr "type" "var_shift_rotate,shift")])
7231 (define_insn "*ashldi3_internal2"
7232 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7233 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7234 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7236 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7243 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7244 (set_attr "length" "4,4,8,8")])
7247 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7248 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7249 (match_operand:SI 2 "reg_or_cint_operand" ""))
7251 (clobber (match_scratch:DI 3 ""))]
7252 "TARGET_POWERPC64 && reload_completed"
7254 (ashift:DI (match_dup 1) (match_dup 2)))
7256 (compare:CC (match_dup 3)
7260 (define_insn "*ashldi3_internal3"
7261 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7262 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7263 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7265 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7266 (ashift:DI (match_dup 1) (match_dup 2)))]
7273 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7274 (set_attr "length" "4,4,8,8")])
7277 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7278 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7279 (match_operand:SI 2 "reg_or_cint_operand" ""))
7281 (set (match_operand:DI 0 "gpc_reg_operand" "")
7282 (ashift:DI (match_dup 1) (match_dup 2)))]
7283 "TARGET_POWERPC64 && reload_completed"
7285 (ashift:DI (match_dup 1) (match_dup 2)))
7287 (compare:CC (match_dup 0)
7291 (define_insn "*ashldi3_internal4"
7292 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7293 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7294 (match_operand:SI 2 "const_int_operand" "i"))
7295 (match_operand:DI 3 "const_int_operand" "n")))]
7296 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7297 "rldic %0,%1,%H2,%W3")
7299 (define_insn "ashldi3_internal5"
7300 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7302 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7303 (match_operand:SI 2 "const_int_operand" "i,i"))
7304 (match_operand:DI 3 "const_int_operand" "n,n"))
7306 (clobber (match_scratch:DI 4 "=r,r"))]
7307 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7309 rldic. %4,%1,%H2,%W3
7311 [(set_attr "type" "compare")
7312 (set_attr "length" "4,8")])
7315 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7317 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7318 (match_operand:SI 2 "const_int_operand" ""))
7319 (match_operand:DI 3 "const_int_operand" ""))
7321 (clobber (match_scratch:DI 4 ""))]
7322 "TARGET_POWERPC64 && reload_completed
7323 && includes_rldic_lshift_p (operands[2], operands[3])"
7325 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7328 (compare:CC (match_dup 4)
7332 (define_insn "*ashldi3_internal6"
7333 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7335 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7336 (match_operand:SI 2 "const_int_operand" "i,i"))
7337 (match_operand:DI 3 "const_int_operand" "n,n"))
7339 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7340 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7341 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7343 rldic. %0,%1,%H2,%W3
7345 [(set_attr "type" "compare")
7346 (set_attr "length" "4,8")])
7349 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7351 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7352 (match_operand:SI 2 "const_int_operand" ""))
7353 (match_operand:DI 3 "const_int_operand" ""))
7355 (set (match_operand:DI 0 "gpc_reg_operand" "")
7356 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7357 "TARGET_POWERPC64 && reload_completed
7358 && includes_rldic_lshift_p (operands[2], operands[3])"
7360 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7363 (compare:CC (match_dup 0)
7367 (define_insn "*ashldi3_internal7"
7368 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7369 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7370 (match_operand:SI 2 "const_int_operand" "i"))
7371 (match_operand:DI 3 "mask64_operand" "n")))]
7372 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7373 "rldicr %0,%1,%H2,%S3")
7375 (define_insn "ashldi3_internal8"
7376 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7378 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7379 (match_operand:SI 2 "const_int_operand" "i,i"))
7380 (match_operand:DI 3 "mask64_operand" "n,n"))
7382 (clobber (match_scratch:DI 4 "=r,r"))]
7383 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7385 rldicr. %4,%1,%H2,%S3
7387 [(set_attr "type" "compare")
7388 (set_attr "length" "4,8")])
7391 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7393 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7394 (match_operand:SI 2 "const_int_operand" ""))
7395 (match_operand:DI 3 "mask64_operand" ""))
7397 (clobber (match_scratch:DI 4 ""))]
7398 "TARGET_POWERPC64 && reload_completed
7399 && includes_rldicr_lshift_p (operands[2], operands[3])"
7401 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7404 (compare:CC (match_dup 4)
7408 (define_insn "*ashldi3_internal9"
7409 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7411 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7412 (match_operand:SI 2 "const_int_operand" "i,i"))
7413 (match_operand:DI 3 "mask64_operand" "n,n"))
7415 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7416 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7417 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7419 rldicr. %0,%1,%H2,%S3
7421 [(set_attr "type" "compare")
7422 (set_attr "length" "4,8")])
7425 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7427 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7428 (match_operand:SI 2 "const_int_operand" ""))
7429 (match_operand:DI 3 "mask64_operand" ""))
7431 (set (match_operand:DI 0 "gpc_reg_operand" "")
7432 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7433 "TARGET_POWERPC64 && reload_completed
7434 && includes_rldicr_lshift_p (operands[2], operands[3])"
7436 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7439 (compare:CC (match_dup 0)
7443 (define_expand "lshrdi3"
7444 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7445 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7446 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7447 "TARGET_POWERPC64 || TARGET_POWER"
7450 if (TARGET_POWERPC64)
7452 else if (TARGET_POWER)
7454 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7461 (define_insn "*lshrdi3_internal1"
7462 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7463 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7464 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7469 [(set_attr "type" "var_shift_rotate,shift")])
7471 (define_insn "*lshrdi3_internal2"
7472 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7473 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7474 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7476 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7483 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7484 (set_attr "length" "4,4,8,8")])
7487 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7488 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7489 (match_operand:SI 2 "reg_or_cint_operand" ""))
7491 (clobber (match_scratch:DI 3 ""))]
7492 "TARGET_POWERPC64 && reload_completed"
7494 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7496 (compare:CC (match_dup 3)
7500 (define_insn "*lshrdi3_internal3"
7501 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7502 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7503 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7505 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7506 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7513 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7514 (set_attr "length" "4,4,8,8")])
7517 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7518 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7519 (match_operand:SI 2 "reg_or_cint_operand" ""))
7521 (set (match_operand:DI 0 "gpc_reg_operand" "")
7522 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7523 "TARGET_POWERPC64 && reload_completed"
7525 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7527 (compare:CC (match_dup 0)
7531 (define_expand "ashrdi3"
7532 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7533 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7534 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7538 if (TARGET_POWERPC64)
7540 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7542 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7545 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7546 && WORDS_BIG_ENDIAN)
7548 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7555 (define_insn "*ashrdi3_internal1"
7556 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7557 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7558 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7563 [(set_attr "type" "var_shift_rotate,shift")])
7565 (define_insn "*ashrdi3_internal2"
7566 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7567 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7568 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7570 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7577 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7578 (set_attr "length" "4,4,8,8")])
7581 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7582 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7583 (match_operand:SI 2 "reg_or_cint_operand" ""))
7585 (clobber (match_scratch:DI 3 ""))]
7586 "TARGET_POWERPC64 && reload_completed"
7588 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7590 (compare:CC (match_dup 3)
7594 (define_insn "*ashrdi3_internal3"
7595 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7596 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7597 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7599 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7600 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7607 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7608 (set_attr "length" "4,4,8,8")])
7611 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7612 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7613 (match_operand:SI 2 "reg_or_cint_operand" ""))
7615 (set (match_operand:DI 0 "gpc_reg_operand" "")
7616 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7617 "TARGET_POWERPC64 && reload_completed"
7619 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7621 (compare:CC (match_dup 0)
7625 (define_expand "anddi3"
7627 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7628 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7629 (match_operand:DI 2 "and64_2_operand" "")))
7630 (clobber (match_scratch:CC 3 ""))])]
7634 (define_insn "anddi3_mc"
7635 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7636 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7637 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7638 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7639 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
7642 rldic%B2 %0,%1,0,%S2
7643 rlwinm %0,%1,0,%m2,%M2
7647 [(set_attr "type" "*,*,*,fast_compare,fast_compare,*")
7648 (set_attr "length" "4,4,4,4,4,8")])
7650 (define_insn "anddi3_nomc"
7651 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7652 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
7653 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
7654 (clobber (match_scratch:CC 3 "=X,X,X,X"))]
7655 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
7658 rldic%B2 %0,%1,0,%S2
7659 rlwinm %0,%1,0,%m2,%M2
7661 [(set_attr "length" "4,4,4,8")])
7664 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7665 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7666 (match_operand:DI 2 "mask64_2_operand" "")))
7667 (clobber (match_scratch:CC 3 ""))]
7669 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7670 && !mask_operand (operands[2], DImode)
7671 && !mask64_operand (operands[2], DImode)"
7673 (and:DI (rotate:DI (match_dup 1)
7677 (and:DI (rotate:DI (match_dup 0)
7681 build_mask64_2_operands (operands[2], &operands[4]);
7684 (define_insn "*anddi3_internal2_mc"
7685 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7686 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7687 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7689 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7690 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7691 "TARGET_64BIT && rs6000_gen_cell_microcode"
7694 rldic%B2. %3,%1,0,%S2
7695 rlwinm. %3,%1,0,%m2,%M2
7705 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
7706 fast_compare,compare,compare,compare,compare,compare,\
7708 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7711 [(set (match_operand:CC 0 "cc_reg_operand" "")
7712 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7713 (match_operand:DI 2 "mask64_2_operand" ""))
7715 (clobber (match_scratch:DI 3 ""))
7716 (clobber (match_scratch:CC 4 ""))]
7717 "TARGET_64BIT && reload_completed
7718 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7719 && !mask_operand (operands[2], DImode)
7720 && !mask64_operand (operands[2], DImode)"
7722 (and:DI (rotate:DI (match_dup 1)
7725 (parallel [(set (match_dup 0)
7726 (compare:CC (and:DI (rotate:DI (match_dup 3)
7730 (clobber (match_dup 3))])]
7733 build_mask64_2_operands (operands[2], &operands[5]);
7736 (define_insn "*anddi3_internal3_mc"
7737 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7738 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7739 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7741 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
7742 (and:DI (match_dup 1) (match_dup 2)))
7743 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7744 "TARGET_64BIT && rs6000_gen_cell_microcode"
7747 rldic%B2. %0,%1,0,%S2
7748 rlwinm. %0,%1,0,%m2,%M2
7758 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
7759 fast_compare,compare,compare,compare,compare,compare,\
7761 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7764 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7765 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7766 (match_operand:DI 2 "and64_2_operand" ""))
7768 (set (match_operand:DI 0 "gpc_reg_operand" "")
7769 (and:DI (match_dup 1) (match_dup 2)))
7770 (clobber (match_scratch:CC 4 ""))]
7771 "TARGET_64BIT && reload_completed"
7772 [(parallel [(set (match_dup 0)
7773 (and:DI (match_dup 1) (match_dup 2)))
7774 (clobber (match_dup 4))])
7776 (compare:CC (match_dup 0)
7781 [(set (match_operand:CC 3 "cc_reg_operand" "")
7782 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7783 (match_operand:DI 2 "mask64_2_operand" ""))
7785 (set (match_operand:DI 0 "gpc_reg_operand" "")
7786 (and:DI (match_dup 1) (match_dup 2)))
7787 (clobber (match_scratch:CC 4 ""))]
7788 "TARGET_64BIT && reload_completed
7789 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7790 && !mask_operand (operands[2], DImode)
7791 && !mask64_operand (operands[2], DImode)"
7793 (and:DI (rotate:DI (match_dup 1)
7796 (parallel [(set (match_dup 3)
7797 (compare:CC (and:DI (rotate:DI (match_dup 0)
7802 (and:DI (rotate:DI (match_dup 0)
7807 build_mask64_2_operands (operands[2], &operands[5]);
7810 (define_expand "iordi3"
7811 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7812 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7813 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7817 if (non_logical_cint_operand (operands[2], DImode))
7819 HOST_WIDE_INT value;
7820 rtx tmp = ((!can_create_pseudo_p ()
7821 || rtx_equal_p (operands[0], operands[1]))
7822 ? operands[0] : gen_reg_rtx (DImode));
7824 if (GET_CODE (operands[2]) == CONST_INT)
7826 value = INTVAL (operands[2]);
7827 emit_insn (gen_iordi3 (tmp, operands[1],
7828 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7832 value = CONST_DOUBLE_LOW (operands[2]);
7833 emit_insn (gen_iordi3 (tmp, operands[1],
7834 immed_double_const (value
7835 & (~ (HOST_WIDE_INT) 0xffff),
7839 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7844 (define_expand "xordi3"
7845 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7846 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7847 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7851 if (non_logical_cint_operand (operands[2], DImode))
7853 HOST_WIDE_INT value;
7854 rtx tmp = ((!can_create_pseudo_p ()
7855 || rtx_equal_p (operands[0], operands[1]))
7856 ? operands[0] : gen_reg_rtx (DImode));
7858 if (GET_CODE (operands[2]) == CONST_INT)
7860 value = INTVAL (operands[2]);
7861 emit_insn (gen_xordi3 (tmp, operands[1],
7862 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7866 value = CONST_DOUBLE_LOW (operands[2]);
7867 emit_insn (gen_xordi3 (tmp, operands[1],
7868 immed_double_const (value
7869 & (~ (HOST_WIDE_INT) 0xffff),
7873 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7878 (define_insn "*booldi3_internal1"
7879 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7880 (match_operator:DI 3 "boolean_or_operator"
7881 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7882 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7889 (define_insn "*booldi3_internal2"
7890 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7891 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7892 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7893 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7895 (clobber (match_scratch:DI 3 "=r,r"))]
7900 [(set_attr "type" "fast_compare,compare")
7901 (set_attr "length" "4,8")])
7904 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7905 (compare:CC (match_operator:DI 4 "boolean_operator"
7906 [(match_operand:DI 1 "gpc_reg_operand" "")
7907 (match_operand:DI 2 "gpc_reg_operand" "")])
7909 (clobber (match_scratch:DI 3 ""))]
7910 "TARGET_POWERPC64 && reload_completed"
7911 [(set (match_dup 3) (match_dup 4))
7913 (compare:CC (match_dup 3)
7917 (define_insn "*booldi3_internal3"
7918 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7919 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7920 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7921 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7923 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7929 [(set_attr "type" "fast_compare,compare")
7930 (set_attr "length" "4,8")])
7933 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7934 (compare:CC (match_operator:DI 4 "boolean_operator"
7935 [(match_operand:DI 1 "gpc_reg_operand" "")
7936 (match_operand:DI 2 "gpc_reg_operand" "")])
7938 (set (match_operand:DI 0 "gpc_reg_operand" "")
7940 "TARGET_POWERPC64 && reload_completed"
7941 [(set (match_dup 0) (match_dup 4))
7943 (compare:CC (match_dup 0)
7947 ;; Split a logical operation that we can't do in one insn into two insns,
7948 ;; each of which does one 16-bit part. This is used by combine.
7951 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7952 (match_operator:DI 3 "boolean_or_operator"
7953 [(match_operand:DI 1 "gpc_reg_operand" "")
7954 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7956 [(set (match_dup 0) (match_dup 4))
7957 (set (match_dup 0) (match_dup 5))]
7962 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7964 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7965 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7967 i4 = GEN_INT (value & 0xffff);
7971 i3 = GEN_INT (INTVAL (operands[2])
7972 & (~ (HOST_WIDE_INT) 0xffff));
7973 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7975 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7977 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7981 (define_insn "*boolcdi3_internal1"
7982 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7983 (match_operator:DI 3 "boolean_operator"
7984 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7985 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7989 (define_insn "*boolcdi3_internal2"
7990 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7991 (compare:CC (match_operator:DI 4 "boolean_operator"
7992 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7993 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7995 (clobber (match_scratch:DI 3 "=r,r"))]
8000 [(set_attr "type" "fast_compare,compare")
8001 (set_attr "length" "4,8")])
8004 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8005 (compare:CC (match_operator:DI 4 "boolean_operator"
8006 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8007 (match_operand:DI 2 "gpc_reg_operand" "")])
8009 (clobber (match_scratch:DI 3 ""))]
8010 "TARGET_POWERPC64 && reload_completed"
8011 [(set (match_dup 3) (match_dup 4))
8013 (compare:CC (match_dup 3)
8017 (define_insn "*boolcdi3_internal3"
8018 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8019 (compare:CC (match_operator:DI 4 "boolean_operator"
8020 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8021 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8023 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8029 [(set_attr "type" "fast_compare,compare")
8030 (set_attr "length" "4,8")])
8033 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8034 (compare:CC (match_operator:DI 4 "boolean_operator"
8035 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8036 (match_operand:DI 2 "gpc_reg_operand" "")])
8038 (set (match_operand:DI 0 "gpc_reg_operand" "")
8040 "TARGET_POWERPC64 && reload_completed"
8041 [(set (match_dup 0) (match_dup 4))
8043 (compare:CC (match_dup 0)
8047 (define_insn "*boolccdi3_internal1"
8048 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8049 (match_operator:DI 3 "boolean_operator"
8050 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8051 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
8055 (define_insn "*boolccdi3_internal2"
8056 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8057 (compare:CC (match_operator:DI 4 "boolean_operator"
8058 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8059 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8061 (clobber (match_scratch:DI 3 "=r,r"))]
8066 [(set_attr "type" "fast_compare,compare")
8067 (set_attr "length" "4,8")])
8070 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8071 (compare:CC (match_operator:DI 4 "boolean_operator"
8072 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8073 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8075 (clobber (match_scratch:DI 3 ""))]
8076 "TARGET_POWERPC64 && reload_completed"
8077 [(set (match_dup 3) (match_dup 4))
8079 (compare:CC (match_dup 3)
8083 (define_insn "*boolccdi3_internal3"
8084 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8085 (compare:CC (match_operator:DI 4 "boolean_operator"
8086 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8087 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8089 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8095 [(set_attr "type" "fast_compare,compare")
8096 (set_attr "length" "4,8")])
8099 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8100 (compare:CC (match_operator:DI 4 "boolean_operator"
8101 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8102 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8104 (set (match_operand:DI 0 "gpc_reg_operand" "")
8106 "TARGET_POWERPC64 && reload_completed"
8107 [(set (match_dup 0) (match_dup 4))
8109 (compare:CC (match_dup 0)
8113 (define_expand "smindi3"
8114 [(match_operand:DI 0 "gpc_reg_operand" "")
8115 (match_operand:DI 1 "gpc_reg_operand" "")
8116 (match_operand:DI 2 "gpc_reg_operand" "")]
8120 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
8124 (define_expand "smaxdi3"
8125 [(match_operand:DI 0 "gpc_reg_operand" "")
8126 (match_operand:DI 1 "gpc_reg_operand" "")
8127 (match_operand:DI 2 "gpc_reg_operand" "")]
8131 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
8135 (define_expand "umindi3"
8136 [(match_operand:DI 0 "gpc_reg_operand" "")
8137 (match_operand:DI 1 "gpc_reg_operand" "")
8138 (match_operand:DI 2 "gpc_reg_operand" "")]
8142 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
8146 (define_expand "umaxdi3"
8147 [(match_operand:DI 0 "gpc_reg_operand" "")
8148 (match_operand:DI 1 "gpc_reg_operand" "")
8149 (match_operand:DI 2 "gpc_reg_operand" "")]
8153 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
8158 ;; Now define ways of moving data around.
8160 ;; Set up a register with a value from the GOT table
8162 (define_expand "movsi_got"
8163 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8164 (unspec:SI [(match_operand:SI 1 "got_operand" "")
8165 (match_dup 2)] UNSPEC_MOVSI_GOT))]
8166 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8169 if (GET_CODE (operands[1]) == CONST)
8171 rtx offset = const0_rtx;
8172 HOST_WIDE_INT value;
8174 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8175 value = INTVAL (offset);
8178 rtx tmp = (!can_create_pseudo_p ()
8180 : gen_reg_rtx (Pmode));
8181 emit_insn (gen_movsi_got (tmp, operands[1]));
8182 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8187 operands[2] = rs6000_got_register (operands[1]);
8190 (define_insn "*movsi_got_internal"
8191 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8192 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8193 (match_operand:SI 2 "gpc_reg_operand" "b")]
8195 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8196 "{l|lwz} %0,%a1@got(%2)"
8197 [(set_attr "type" "load")])
8199 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
8200 ;; didn't get allocated to a hard register.
8202 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8203 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8204 (match_operand:SI 2 "memory_operand" "")]
8206 "DEFAULT_ABI == ABI_V4
8208 && (reload_in_progress || reload_completed)"
8209 [(set (match_dup 0) (match_dup 2))
8210 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8214 ;; For SI, we special-case integers that can't be loaded in one insn. We
8215 ;; do the load 16-bits at a time. We could do this by loading from memory,
8216 ;; and this is even supposed to be faster, but it is simpler not to get
8217 ;; integers in the TOC.
8218 (define_insn "movsi_low"
8219 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8220 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
8221 (match_operand 2 "" ""))))]
8222 "TARGET_MACHO && ! TARGET_64BIT"
8223 "{l|lwz} %0,lo16(%2)(%1)"
8224 [(set_attr "type" "load")
8225 (set_attr "length" "4")])
8227 (define_insn "*movsi_internal1"
8228 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
8229 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
8230 "!TARGET_SINGLE_FPU &&
8231 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8235 {l%U1%X1|lwz%U1%X1} %0,%1
8236 {st%U0%X0|stw%U0%X0} %1,%0
8246 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
8247 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
8249 (define_insn "*movsi_internal1_single"
8250 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h,m,*f")
8251 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0,f,m"))]
8252 "TARGET_SINGLE_FPU &&
8253 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8257 {l%U1%X1|lwz%U1%X1} %0,%1
8258 {st%U0%X0|stw%U0%X0} %1,%0
8270 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*,*,*")
8271 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4,4,4")])
8273 ;; Split a load of a large constant into the appropriate two-insn
8277 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8278 (match_operand:SI 1 "const_int_operand" ""))]
8279 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
8280 && (INTVAL (operands[1]) & 0xffff) != 0"
8284 (ior:SI (match_dup 0)
8287 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8289 if (tem == operands[0])
8295 (define_insn "*mov<mode>_internal2"
8296 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8297 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
8299 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8302 {cmpi|cmp<wd>i} %2,%0,0
8305 [(set_attr "type" "cmp,compare,cmp")
8306 (set_attr "length" "4,4,8")])
8309 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
8310 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
8312 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8314 [(set (match_dup 0) (match_dup 1))
8316 (compare:CC (match_dup 0)
8320 (define_insn "*movhi_internal"
8321 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8322 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8323 "gpc_reg_operand (operands[0], HImode)
8324 || gpc_reg_operand (operands[1], HImode)"
8334 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8336 (define_expand "mov<mode>"
8337 [(set (match_operand:INT 0 "general_operand" "")
8338 (match_operand:INT 1 "any_operand" ""))]
8340 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8342 (define_insn "*movqi_internal"
8343 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8344 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8345 "gpc_reg_operand (operands[0], QImode)
8346 || gpc_reg_operand (operands[1], QImode)"
8356 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8358 ;; Here is how to move condition codes around. When we store CC data in
8359 ;; an integer register or memory, we store just the high-order 4 bits.
8360 ;; This lets us not shift in the most common case of CR0.
8361 (define_expand "movcc"
8362 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8363 (match_operand:CC 1 "nonimmediate_operand" ""))]
8367 (define_insn "*movcc_internal1"
8368 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
8369 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
8370 "register_operand (operands[0], CCmode)
8371 || register_operand (operands[1], CCmode)"
8375 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
8378 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
8384 {l%U1%X1|lwz%U1%X1} %0,%1
8385 {st%U0%U1|stw%U0%U1} %1,%0"
8387 (cond [(eq_attr "alternative" "0,3")
8388 (const_string "cr_logical")
8389 (eq_attr "alternative" "1,2")
8390 (const_string "mtcr")
8391 (eq_attr "alternative" "6,7,9")
8392 (const_string "integer")
8393 (eq_attr "alternative" "8")
8394 (const_string "mfjmpr")
8395 (eq_attr "alternative" "10")
8396 (const_string "mtjmpr")
8397 (eq_attr "alternative" "11")
8398 (const_string "load")
8399 (eq_attr "alternative" "12")
8400 (const_string "store")
8401 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
8402 (const_string "mfcrf")
8404 (const_string "mfcr")))
8405 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
8407 ;; For floating-point, we normally deal with the floating-point registers
8408 ;; unless -msoft-float is used. The sole exception is that parameter passing
8409 ;; can produce floating-point values in fixed-point registers. Unless the
8410 ;; value is a simple constant or already in memory, we deal with this by
8411 ;; allocating memory and copying the value explicitly via that memory location.
8412 (define_expand "movsf"
8413 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8414 (match_operand:SF 1 "any_operand" ""))]
8416 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
8419 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8420 (match_operand:SF 1 "const_double_operand" ""))]
8422 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8423 || (GET_CODE (operands[0]) == SUBREG
8424 && GET_CODE (SUBREG_REG (operands[0])) == REG
8425 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8426 [(set (match_dup 2) (match_dup 3))]
8432 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8433 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
8435 if (! TARGET_POWERPC64)
8436 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
8438 operands[2] = gen_lowpart (SImode, operands[0]);
8440 operands[3] = gen_int_mode (l, SImode);
8443 (define_insn "*movsf_hardfloat"
8444 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
8445 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
8446 "(gpc_reg_operand (operands[0], SFmode)
8447 || gpc_reg_operand (operands[1], SFmode))
8448 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
8451 {l%U1%X1|lwz%U1%X1} %0,%1
8452 {st%U0%X0|stw%U0%X0} %1,%0
8462 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
8463 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
8465 (define_insn "*movsf_softfloat"
8466 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
8467 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
8468 "(gpc_reg_operand (operands[0], SFmode)
8469 || gpc_reg_operand (operands[1], SFmode))
8470 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
8476 {l%U1%X1|lwz%U1%X1} %0,%1
8477 {st%U0%X0|stw%U0%X0} %1,%0
8484 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
8485 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
8488 (define_expand "movdf"
8489 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8490 (match_operand:DF 1 "any_operand" ""))]
8492 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
8495 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8496 (match_operand:DF 1 "const_int_operand" ""))]
8497 "! TARGET_POWERPC64 && reload_completed
8498 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8499 || (GET_CODE (operands[0]) == SUBREG
8500 && GET_CODE (SUBREG_REG (operands[0])) == REG
8501 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8502 [(set (match_dup 2) (match_dup 4))
8503 (set (match_dup 3) (match_dup 1))]
8506 int endian = (WORDS_BIG_ENDIAN == 0);
8507 HOST_WIDE_INT value = INTVAL (operands[1]);
8509 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8510 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8511 #if HOST_BITS_PER_WIDE_INT == 32
8512 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8514 operands[4] = GEN_INT (value >> 32);
8515 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8520 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8521 (match_operand:DF 1 "const_double_operand" ""))]
8522 "! TARGET_POWERPC64 && reload_completed
8523 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8524 || (GET_CODE (operands[0]) == SUBREG
8525 && GET_CODE (SUBREG_REG (operands[0])) == REG
8526 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8527 [(set (match_dup 2) (match_dup 4))
8528 (set (match_dup 3) (match_dup 5))]
8531 int endian = (WORDS_BIG_ENDIAN == 0);
8535 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8536 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8538 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8539 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8540 operands[4] = gen_int_mode (l[endian], SImode);
8541 operands[5] = gen_int_mode (l[1 - endian], SImode);
8545 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8546 (match_operand:DF 1 "const_double_operand" ""))]
8547 "TARGET_POWERPC64 && reload_completed
8548 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8549 || (GET_CODE (operands[0]) == SUBREG
8550 && GET_CODE (SUBREG_REG (operands[0])) == REG
8551 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8552 [(set (match_dup 2) (match_dup 3))]
8555 int endian = (WORDS_BIG_ENDIAN == 0);
8558 #if HOST_BITS_PER_WIDE_INT >= 64
8562 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8563 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8565 operands[2] = gen_lowpart (DImode, operands[0]);
8566 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8567 #if HOST_BITS_PER_WIDE_INT >= 64
8568 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8569 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8571 operands[3] = gen_int_mode (val, DImode);
8573 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8577 ;; Don't have reload use general registers to load a constant. First,
8578 ;; it might not work if the output operand is the equivalent of
8579 ;; a non-offsettable memref, but also it is less efficient than loading
8580 ;; the constant into an FP register, since it will probably be used there.
8581 ;; The "??" is a kludge until we can figure out a more reasonable way
8582 ;; of handling these non-offsettable values.
8583 (define_insn "*movdf_hardfloat32"
8584 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,d,d,m,!r,!r,!r")
8585 (match_operand:DF 1 "input_operand" "r,m,r,d,m,d,G,H,F"))]
8586 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8587 && (gpc_reg_operand (operands[0], DFmode)
8588 || gpc_reg_operand (operands[1], DFmode))"
8591 switch (which_alternative)
8596 /* We normally copy the low-numbered register first. However, if
8597 the first register operand 0 is the same as the second register
8598 of operand 1, we must copy in the opposite order. */
8599 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8600 return \"mr %L0,%L1\;mr %0,%1\";
8602 return \"mr %0,%1\;mr %L0,%L1\";
8604 if (rs6000_offsettable_memref_p (operands[1])
8605 || (GET_CODE (operands[1]) == MEM
8606 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8607 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8608 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC
8609 || GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)))
8611 /* If the low-address word is used in the address, we must load
8612 it last. Otherwise, load it first. Note that we cannot have
8613 auto-increment in that case since the address register is
8614 known to be dead. */
8615 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8617 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8619 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
8625 addreg = find_addr_reg (XEXP (operands[1], 0));
8626 if (refers_to_regno_p (REGNO (operands[0]),
8627 REGNO (operands[0]) + 1,
8630 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8631 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
8632 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8633 return \"{l%X1|lwz%X1} %0,%1\";
8637 output_asm_insn (\"{l%X1|lwz%X1} %0,%1\", operands);
8638 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8639 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
8640 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8645 if (rs6000_offsettable_memref_p (operands[0])
8646 || (GET_CODE (operands[0]) == MEM
8647 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8648 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8649 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
8650 || GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)))
8651 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
8656 addreg = find_addr_reg (XEXP (operands[0], 0));
8657 output_asm_insn (\"{st%X0|stw%X0} %1,%0\", operands);
8658 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8659 output_asm_insn (\"{st%X0|stw%X0} %L1,%0\", operands);
8660 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8664 return \"fmr %0,%1\";
8666 return \"lfd%U1%X1 %0,%1\";
8668 return \"stfd%U0%X0 %1,%0\";
8675 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
8676 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
8678 (define_insn "*movdf_softfloat32"
8679 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8680 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8682 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
8683 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8684 && (gpc_reg_operand (operands[0], DFmode)
8685 || gpc_reg_operand (operands[1], DFmode))"
8688 switch (which_alternative)
8693 /* We normally copy the low-numbered register first. However, if
8694 the first register operand 0 is the same as the second register of
8695 operand 1, we must copy in the opposite order. */
8696 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8697 return \"mr %L0,%L1\;mr %0,%1\";
8699 return \"mr %0,%1\;mr %L0,%L1\";
8701 /* If the low-address word is used in the address, we must load
8702 it last. Otherwise, load it first. Note that we cannot have
8703 auto-increment in that case since the address register is
8704 known to be dead. */
8705 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8707 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8709 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
8711 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
8718 [(set_attr "type" "two,load,store,*,*,*")
8719 (set_attr "length" "8,8,8,8,12,16")])
8721 ; ld/std require word-aligned displacements -> 'Y' constraint.
8722 ; List Y->r and r->Y before r->r for reload.
8723 (define_insn "*movdf_hardfloat64_mfpgpr"
8724 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r,r,d")
8725 (match_operand:DF 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F,d,r"))]
8726 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8727 && TARGET_DOUBLE_FLOAT
8728 && (gpc_reg_operand (operands[0], DFmode)
8729 || gpc_reg_operand (operands[1], DFmode))"
8745 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
8746 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
8748 ; ld/std require word-aligned displacements -> 'Y' constraint.
8749 ; List Y->r and r->Y before r->r for reload.
8750 (define_insn "*movdf_hardfloat64"
8751 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r")
8752 (match_operand:DF 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F"))]
8753 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8754 && TARGET_DOUBLE_FLOAT
8755 && (gpc_reg_operand (operands[0], DFmode)
8756 || gpc_reg_operand (operands[1], DFmode))"
8770 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
8771 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
8773 (define_insn "*movdf_softfloat64"
8774 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8775 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
8776 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8777 && (gpc_reg_operand (operands[0], DFmode)
8778 || gpc_reg_operand (operands[1], DFmode))"
8789 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
8790 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8792 (define_expand "movtf"
8793 [(set (match_operand:TF 0 "general_operand" "")
8794 (match_operand:TF 1 "any_operand" ""))]
8795 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
8796 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8798 ; It's important to list the o->f and f->o moves before f->f because
8799 ; otherwise reload, given m->f, will try to pick f->f and reload it,
8800 ; which doesn't make progress. Likewise r->Y must be before r->r.
8801 (define_insn_and_split "*movtf_internal"
8802 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,d,r,Y,r")
8803 (match_operand:TF 1 "input_operand" "d,o,d,YGHF,r,r"))]
8805 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8806 && (gpc_reg_operand (operands[0], TFmode)
8807 || gpc_reg_operand (operands[1], TFmode))"
8809 "&& reload_completed"
8811 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8812 [(set_attr "length" "8,8,8,20,20,16")])
8814 (define_insn_and_split "*movtf_softfloat"
8815 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
8816 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
8818 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
8819 && (gpc_reg_operand (operands[0], TFmode)
8820 || gpc_reg_operand (operands[1], TFmode))"
8822 "&& reload_completed"
8824 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8825 [(set_attr "length" "20,20,16")])
8827 (define_expand "extenddftf2"
8828 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8829 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8831 && TARGET_HARD_FLOAT
8832 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8833 && TARGET_LONG_DOUBLE_128"
8835 if (TARGET_E500_DOUBLE)
8836 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8838 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8842 (define_expand "extenddftf2_fprs"
8843 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8844 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8845 (use (match_dup 2))])]
8847 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8848 && TARGET_LONG_DOUBLE_128"
8850 operands[2] = CONST0_RTX (DFmode);
8851 /* Generate GOT reference early for SVR4 PIC. */
8852 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8853 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8856 (define_insn_and_split "*extenddftf2_internal"
8857 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,&d,r")
8858 (float_extend:TF (match_operand:DF 1 "input_operand" "dr,md,md,rmGHF")))
8859 (use (match_operand:DF 2 "zero_reg_mem_operand" "rd,m,d,n"))]
8861 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8862 && TARGET_LONG_DOUBLE_128"
8864 "&& reload_completed"
8867 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8868 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8869 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8871 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8876 (define_expand "extendsftf2"
8877 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8878 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8880 && TARGET_HARD_FLOAT
8881 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8882 && TARGET_LONG_DOUBLE_128"
8884 rtx tmp = gen_reg_rtx (DFmode);
8885 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8886 emit_insn (gen_extenddftf2 (operands[0], tmp));
8890 (define_expand "trunctfdf2"
8891 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8892 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8894 && TARGET_HARD_FLOAT
8895 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8896 && TARGET_LONG_DOUBLE_128"
8899 (define_insn_and_split "trunctfdf2_internal1"
8900 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
8901 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
8902 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8903 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8907 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8910 emit_note (NOTE_INSN_DELETED);
8913 [(set_attr "type" "fp")])
8915 (define_insn "trunctfdf2_internal2"
8916 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
8917 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
8918 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8919 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8920 && TARGET_LONG_DOUBLE_128"
8922 [(set_attr "type" "fp")
8923 (set_attr "fp_type" "fp_addsub_d")])
8925 (define_expand "trunctfsf2"
8926 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8927 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8929 && TARGET_HARD_FLOAT
8930 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8931 && TARGET_LONG_DOUBLE_128"
8933 if (TARGET_E500_DOUBLE)
8934 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8936 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8940 (define_insn_and_split "trunctfsf2_fprs"
8941 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8942 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
8943 (clobber (match_scratch:DF 2 "=d"))]
8945 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
8946 && TARGET_LONG_DOUBLE_128"
8948 "&& reload_completed"
8950 (float_truncate:DF (match_dup 1)))
8952 (float_truncate:SF (match_dup 2)))]
8955 (define_expand "floatsitf2"
8956 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8957 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
8959 && TARGET_HARD_FLOAT
8960 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8961 && TARGET_LONG_DOUBLE_128"
8963 rtx tmp = gen_reg_rtx (DFmode);
8964 expand_float (tmp, operands[1], false);
8965 emit_insn (gen_extenddftf2 (operands[0], tmp));
8969 ; fadd, but rounding towards zero.
8970 ; This is probably not the optimal code sequence.
8971 (define_insn "fix_trunc_helper"
8972 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
8973 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
8974 UNSPEC_FIX_TRUNC_TF))
8975 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
8976 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
8977 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8978 [(set_attr "type" "fp")
8979 (set_attr "length" "20")])
8981 (define_expand "fix_trunctfsi2"
8982 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8983 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8985 && (TARGET_POWER2 || TARGET_POWERPC)
8986 && TARGET_HARD_FLOAT
8987 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8988 && TARGET_LONG_DOUBLE_128"
8990 if (TARGET_E500_DOUBLE)
8991 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8993 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8997 (define_expand "fix_trunctfsi2_fprs"
8998 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8999 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
9000 (clobber (match_dup 2))
9001 (clobber (match_dup 3))
9002 (clobber (match_dup 4))
9003 (clobber (match_dup 5))])]
9005 && (TARGET_POWER2 || TARGET_POWERPC)
9006 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9008 operands[2] = gen_reg_rtx (DFmode);
9009 operands[3] = gen_reg_rtx (DFmode);
9010 operands[4] = gen_reg_rtx (DImode);
9011 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
9014 (define_insn_and_split "*fix_trunctfsi2_internal"
9015 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9016 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
9017 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
9018 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
9019 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
9020 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
9022 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9024 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[5]))"
9028 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
9030 gcc_assert (MEM_P (operands[5]));
9031 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
9033 emit_insn (gen_fctiwz (operands[4], operands[2]));
9034 emit_move_insn (operands[5], operands[4]);
9035 emit_move_insn (operands[0], lowword);
9039 (define_expand "negtf2"
9040 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9041 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9043 && TARGET_HARD_FLOAT
9044 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9045 && TARGET_LONG_DOUBLE_128"
9048 (define_insn "negtf2_internal"
9049 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
9050 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9052 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9055 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9056 return \"fneg %L0,%L1\;fneg %0,%1\";
9058 return \"fneg %0,%1\;fneg %L0,%L1\";
9060 [(set_attr "type" "fp")
9061 (set_attr "length" "8")])
9063 (define_expand "abstf2"
9064 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9065 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9067 && TARGET_HARD_FLOAT
9068 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9069 && TARGET_LONG_DOUBLE_128"
9072 rtx label = gen_label_rtx ();
9073 if (TARGET_E500_DOUBLE)
9075 if (flag_finite_math_only && !flag_trapping_math)
9076 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
9078 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
9081 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
9086 (define_expand "abstf2_internal"
9087 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9088 (match_operand:TF 1 "gpc_reg_operand" ""))
9089 (set (match_dup 3) (match_dup 5))
9090 (set (match_dup 5) (abs:DF (match_dup 5)))
9091 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
9092 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
9093 (label_ref (match_operand 2 "" ""))
9095 (set (match_dup 6) (neg:DF (match_dup 6)))]
9097 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9098 && TARGET_LONG_DOUBLE_128"
9101 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9102 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9103 operands[3] = gen_reg_rtx (DFmode);
9104 operands[4] = gen_reg_rtx (CCFPmode);
9105 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
9106 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
9109 ;; Next come the multi-word integer load and store and the load and store
9112 ; List r->r after r->"o<>", otherwise reload will try to reload a
9113 ; non-offsettable address by using r->r which won't make progress.
9114 (define_insn "*movdi_internal32"
9115 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*d,*d,m,r")
9116 (match_operand:DI 1 "input_operand" "r,r,m,d,m,d,IJKnGHF"))]
9118 && (gpc_reg_operand (operands[0], DImode)
9119 || gpc_reg_operand (operands[1], DImode))"
9128 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
9131 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9132 (match_operand:DI 1 "const_int_operand" ""))]
9133 "! TARGET_POWERPC64 && reload_completed"
9134 [(set (match_dup 2) (match_dup 4))
9135 (set (match_dup 3) (match_dup 1))]
9138 HOST_WIDE_INT value = INTVAL (operands[1]);
9139 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9141 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9143 #if HOST_BITS_PER_WIDE_INT == 32
9144 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
9146 operands[4] = GEN_INT (value >> 32);
9147 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9152 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "")
9153 (match_operand:DI 1 "input_operand" ""))]
9154 "reload_completed && !TARGET_POWERPC64
9155 && gpr_or_gpr_p (operands[0], operands[1])"
9157 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9159 (define_insn "*movdi_mfpgpr"
9160 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h,r,*d")
9161 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0,*d,r"))]
9162 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9163 && (gpc_reg_operand (operands[0], DImode)
9164 || gpc_reg_operand (operands[1], DImode))"
9181 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
9182 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
9184 (define_insn "*movdi_internal64"
9185 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h")
9186 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0"))]
9187 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
9188 && (gpc_reg_operand (operands[0], DImode)
9189 || gpc_reg_operand (operands[1], DImode))"
9204 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
9205 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
9207 ;; immediate value valid for a single instruction hiding in a const_double
9209 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9210 (match_operand:DI 1 "const_double_operand" "F"))]
9211 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
9212 && GET_CODE (operands[1]) == CONST_DOUBLE
9213 && num_insns_constant (operands[1], DImode) == 1"
9216 return ((unsigned HOST_WIDE_INT)
9217 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
9218 ? \"li %0,%1\" : \"lis %0,%v1\";
9221 ;; Generate all one-bits and clear left or right.
9222 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9224 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9225 (match_operand:DI 1 "mask64_operand" ""))]
9226 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9227 [(set (match_dup 0) (const_int -1))
9229 (and:DI (rotate:DI (match_dup 0)
9234 ;; Split a load of a large constant into the appropriate five-instruction
9235 ;; sequence. Handle anything in a constant number of insns.
9236 ;; When non-easy constants can go in the TOC, this should use
9237 ;; easy_fp_constant predicate.
9239 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9240 (match_operand:DI 1 "const_int_operand" ""))]
9241 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9242 [(set (match_dup 0) (match_dup 2))
9243 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9245 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9247 if (tem == operands[0])
9254 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9255 (match_operand:DI 1 "const_double_operand" ""))]
9256 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9257 [(set (match_dup 0) (match_dup 2))
9258 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9260 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9262 if (tem == operands[0])
9268 ;; TImode is similar, except that we usually want to compute the address into
9269 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
9270 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
9272 ;; We say that MQ is clobbered in the last alternative because the first
9273 ;; alternative would never get used otherwise since it would need a reload
9274 ;; while the 2nd alternative would not. We put memory cases first so they
9275 ;; are preferred. Otherwise, we'd try to reload the output instead of
9276 ;; giving the SCRATCH mq.
9278 (define_insn "*movti_power"
9279 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
9280 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
9281 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
9282 "TARGET_POWER && ! TARGET_POWERPC64
9283 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9286 switch (which_alternative)
9293 return \"{stsi|stswi} %1,%P0,16\";
9298 /* If the address is not used in the output, we can use lsi. Otherwise,
9299 fall through to generating four loads. */
9301 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9302 return \"{lsi|lswi} %0,%P1,16\";
9303 /* ... fall through ... */
9309 [(set_attr "type" "store,store,*,load,load,*")])
9311 (define_insn "*movti_string"
9312 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
9313 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
9314 "! TARGET_POWER && ! TARGET_POWERPC64
9315 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9318 switch (which_alternative)
9324 return \"{stsi|stswi} %1,%P0,16\";
9329 /* If the address is not used in the output, we can use lsi. Otherwise,
9330 fall through to generating four loads. */
9332 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9333 return \"{lsi|lswi} %0,%P1,16\";
9334 /* ... fall through ... */
9340 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")
9341 (set (attr "cell_micro") (if_then_else (eq (symbol_ref "TARGET_STRING") (const_int 1))
9342 (const_string "always")
9343 (const_string "conditional")))])
9345 (define_insn "*movti_ppc64"
9346 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
9347 (match_operand:TI 1 "input_operand" "r,r,m"))]
9348 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
9349 || gpc_reg_operand (operands[1], TImode))"
9351 [(set_attr "type" "*,store,load")])
9354 [(set (match_operand:TI 0 "gpc_reg_operand" "")
9355 (match_operand:TI 1 "const_double_operand" ""))]
9357 [(set (match_dup 2) (match_dup 4))
9358 (set (match_dup 3) (match_dup 5))]
9361 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9363 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9365 if (GET_CODE (operands[1]) == CONST_DOUBLE)
9367 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9368 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9370 else if (GET_CODE (operands[1]) == CONST_INT)
9372 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9373 operands[5] = operands[1];
9380 [(set (match_operand:TI 0 "nonimmediate_operand" "")
9381 (match_operand:TI 1 "input_operand" ""))]
9383 && gpr_or_gpr_p (operands[0], operands[1])"
9385 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9387 (define_expand "load_multiple"
9388 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9389 (match_operand:SI 1 "" ""))
9390 (use (match_operand:SI 2 "" ""))])]
9391 "TARGET_STRING && !TARGET_POWERPC64"
9399 /* Support only loading a constant number of fixed-point registers from
9400 memory and only bother with this if more than two; the machine
9401 doesn't support more than eight. */
9402 if (GET_CODE (operands[2]) != CONST_INT
9403 || INTVAL (operands[2]) <= 2
9404 || INTVAL (operands[2]) > 8
9405 || GET_CODE (operands[1]) != MEM
9406 || GET_CODE (operands[0]) != REG
9407 || REGNO (operands[0]) >= 32)
9410 count = INTVAL (operands[2]);
9411 regno = REGNO (operands[0]);
9413 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9414 op1 = replace_equiv_address (operands[1],
9415 force_reg (SImode, XEXP (operands[1], 0)));
9417 for (i = 0; i < count; i++)
9418 XVECEXP (operands[3], 0, i)
9419 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
9420 adjust_address_nv (op1, SImode, i * 4));
9423 (define_insn "*ldmsi8"
9424 [(match_parallel 0 "load_multiple_operation"
9425 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9426 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9427 (set (match_operand:SI 3 "gpc_reg_operand" "")
9428 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9429 (set (match_operand:SI 4 "gpc_reg_operand" "")
9430 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9431 (set (match_operand:SI 5 "gpc_reg_operand" "")
9432 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9433 (set (match_operand:SI 6 "gpc_reg_operand" "")
9434 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9435 (set (match_operand:SI 7 "gpc_reg_operand" "")
9436 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9437 (set (match_operand:SI 8 "gpc_reg_operand" "")
9438 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9439 (set (match_operand:SI 9 "gpc_reg_operand" "")
9440 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9441 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9443 { return rs6000_output_load_multiple (operands); }"
9444 [(set_attr "type" "load_ux")
9445 (set_attr "length" "32")])
9447 (define_insn "*ldmsi7"
9448 [(match_parallel 0 "load_multiple_operation"
9449 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9450 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9451 (set (match_operand:SI 3 "gpc_reg_operand" "")
9452 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9453 (set (match_operand:SI 4 "gpc_reg_operand" "")
9454 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9455 (set (match_operand:SI 5 "gpc_reg_operand" "")
9456 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9457 (set (match_operand:SI 6 "gpc_reg_operand" "")
9458 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9459 (set (match_operand:SI 7 "gpc_reg_operand" "")
9460 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9461 (set (match_operand:SI 8 "gpc_reg_operand" "")
9462 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9463 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9465 { return rs6000_output_load_multiple (operands); }"
9466 [(set_attr "type" "load_ux")
9467 (set_attr "length" "32")])
9469 (define_insn "*ldmsi6"
9470 [(match_parallel 0 "load_multiple_operation"
9471 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9472 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9473 (set (match_operand:SI 3 "gpc_reg_operand" "")
9474 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9475 (set (match_operand:SI 4 "gpc_reg_operand" "")
9476 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9477 (set (match_operand:SI 5 "gpc_reg_operand" "")
9478 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9479 (set (match_operand:SI 6 "gpc_reg_operand" "")
9480 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9481 (set (match_operand:SI 7 "gpc_reg_operand" "")
9482 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9483 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9485 { return rs6000_output_load_multiple (operands); }"
9486 [(set_attr "type" "load_ux")
9487 (set_attr "length" "32")])
9489 (define_insn "*ldmsi5"
9490 [(match_parallel 0 "load_multiple_operation"
9491 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9492 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9493 (set (match_operand:SI 3 "gpc_reg_operand" "")
9494 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9495 (set (match_operand:SI 4 "gpc_reg_operand" "")
9496 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9497 (set (match_operand:SI 5 "gpc_reg_operand" "")
9498 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9499 (set (match_operand:SI 6 "gpc_reg_operand" "")
9500 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9501 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9503 { return rs6000_output_load_multiple (operands); }"
9504 [(set_attr "type" "load_ux")
9505 (set_attr "length" "32")])
9507 (define_insn "*ldmsi4"
9508 [(match_parallel 0 "load_multiple_operation"
9509 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9510 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9511 (set (match_operand:SI 3 "gpc_reg_operand" "")
9512 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9513 (set (match_operand:SI 4 "gpc_reg_operand" "")
9514 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9515 (set (match_operand:SI 5 "gpc_reg_operand" "")
9516 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9517 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9519 { return rs6000_output_load_multiple (operands); }"
9520 [(set_attr "type" "load_ux")
9521 (set_attr "length" "32")])
9523 (define_insn "*ldmsi3"
9524 [(match_parallel 0 "load_multiple_operation"
9525 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9526 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9527 (set (match_operand:SI 3 "gpc_reg_operand" "")
9528 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9529 (set (match_operand:SI 4 "gpc_reg_operand" "")
9530 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9531 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9533 { return rs6000_output_load_multiple (operands); }"
9534 [(set_attr "type" "load_ux")
9535 (set_attr "length" "32")])
9537 (define_expand "store_multiple"
9538 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9539 (match_operand:SI 1 "" ""))
9540 (clobber (scratch:SI))
9541 (use (match_operand:SI 2 "" ""))])]
9542 "TARGET_STRING && !TARGET_POWERPC64"
9551 /* Support only storing a constant number of fixed-point registers to
9552 memory and only bother with this if more than two; the machine
9553 doesn't support more than eight. */
9554 if (GET_CODE (operands[2]) != CONST_INT
9555 || INTVAL (operands[2]) <= 2
9556 || INTVAL (operands[2]) > 8
9557 || GET_CODE (operands[0]) != MEM
9558 || GET_CODE (operands[1]) != REG
9559 || REGNO (operands[1]) >= 32)
9562 count = INTVAL (operands[2]);
9563 regno = REGNO (operands[1]);
9565 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
9566 to = force_reg (SImode, XEXP (operands[0], 0));
9567 op0 = replace_equiv_address (operands[0], to);
9569 XVECEXP (operands[3], 0, 0)
9570 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
9571 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
9572 gen_rtx_SCRATCH (SImode));
9574 for (i = 1; i < count; i++)
9575 XVECEXP (operands[3], 0, i + 1)
9576 = gen_rtx_SET (VOIDmode,
9577 adjust_address_nv (op0, SImode, i * 4),
9578 gen_rtx_REG (SImode, regno + i));
9581 (define_insn "*stmsi8"
9582 [(match_parallel 0 "store_multiple_operation"
9583 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9584 (match_operand:SI 2 "gpc_reg_operand" "r"))
9585 (clobber (match_scratch:SI 3 "=X"))
9586 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9587 (match_operand:SI 4 "gpc_reg_operand" "r"))
9588 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9589 (match_operand:SI 5 "gpc_reg_operand" "r"))
9590 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9591 (match_operand:SI 6 "gpc_reg_operand" "r"))
9592 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9593 (match_operand:SI 7 "gpc_reg_operand" "r"))
9594 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9595 (match_operand:SI 8 "gpc_reg_operand" "r"))
9596 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9597 (match_operand:SI 9 "gpc_reg_operand" "r"))
9598 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9599 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9600 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9601 "{stsi|stswi} %2,%1,%O0"
9602 [(set_attr "type" "store_ux")
9603 (set_attr "cell_micro" "always")])
9605 (define_insn "*stmsi7"
9606 [(match_parallel 0 "store_multiple_operation"
9607 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9608 (match_operand:SI 2 "gpc_reg_operand" "r"))
9609 (clobber (match_scratch:SI 3 "=X"))
9610 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9611 (match_operand:SI 4 "gpc_reg_operand" "r"))
9612 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9613 (match_operand:SI 5 "gpc_reg_operand" "r"))
9614 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9615 (match_operand:SI 6 "gpc_reg_operand" "r"))
9616 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9617 (match_operand:SI 7 "gpc_reg_operand" "r"))
9618 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9619 (match_operand:SI 8 "gpc_reg_operand" "r"))
9620 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9621 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9622 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9623 "{stsi|stswi} %2,%1,%O0"
9624 [(set_attr "type" "store_ux")
9625 (set_attr "cell_micro" "always")])
9627 (define_insn "*stmsi6"
9628 [(match_parallel 0 "store_multiple_operation"
9629 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9630 (match_operand:SI 2 "gpc_reg_operand" "r"))
9631 (clobber (match_scratch:SI 3 "=X"))
9632 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9633 (match_operand:SI 4 "gpc_reg_operand" "r"))
9634 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9635 (match_operand:SI 5 "gpc_reg_operand" "r"))
9636 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9637 (match_operand:SI 6 "gpc_reg_operand" "r"))
9638 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9639 (match_operand:SI 7 "gpc_reg_operand" "r"))
9640 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9641 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9642 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9643 "{stsi|stswi} %2,%1,%O0"
9644 [(set_attr "type" "store_ux")
9645 (set_attr "cell_micro" "always")])
9647 (define_insn "*stmsi5"
9648 [(match_parallel 0 "store_multiple_operation"
9649 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9650 (match_operand:SI 2 "gpc_reg_operand" "r"))
9651 (clobber (match_scratch:SI 3 "=X"))
9652 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9653 (match_operand:SI 4 "gpc_reg_operand" "r"))
9654 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9655 (match_operand:SI 5 "gpc_reg_operand" "r"))
9656 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9657 (match_operand:SI 6 "gpc_reg_operand" "r"))
9658 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9659 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9660 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9661 "{stsi|stswi} %2,%1,%O0"
9662 [(set_attr "type" "store_ux")
9663 (set_attr "cell_micro" "always")])
9665 (define_insn "*stmsi4"
9666 [(match_parallel 0 "store_multiple_operation"
9667 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9668 (match_operand:SI 2 "gpc_reg_operand" "r"))
9669 (clobber (match_scratch:SI 3 "=X"))
9670 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9671 (match_operand:SI 4 "gpc_reg_operand" "r"))
9672 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9673 (match_operand:SI 5 "gpc_reg_operand" "r"))
9674 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9675 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9676 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9677 "{stsi|stswi} %2,%1,%O0"
9678 [(set_attr "type" "store_ux")
9679 (set_attr "cell_micro" "always")])
9681 (define_insn "*stmsi3"
9682 [(match_parallel 0 "store_multiple_operation"
9683 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9684 (match_operand:SI 2 "gpc_reg_operand" "r"))
9685 (clobber (match_scratch:SI 3 "=X"))
9686 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9687 (match_operand:SI 4 "gpc_reg_operand" "r"))
9688 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9689 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9690 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9691 "{stsi|stswi} %2,%1,%O0"
9692 [(set_attr "type" "store_ux")
9693 (set_attr "cell_micro" "always")])
9695 (define_insn "*stmsi8_power"
9696 [(match_parallel 0 "store_multiple_operation"
9697 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9698 (match_operand:SI 2 "gpc_reg_operand" "r"))
9699 (clobber (match_scratch:SI 3 "=q"))
9700 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9701 (match_operand:SI 4 "gpc_reg_operand" "r"))
9702 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9703 (match_operand:SI 5 "gpc_reg_operand" "r"))
9704 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9705 (match_operand:SI 6 "gpc_reg_operand" "r"))
9706 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9707 (match_operand:SI 7 "gpc_reg_operand" "r"))
9708 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9709 (match_operand:SI 8 "gpc_reg_operand" "r"))
9710 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9711 (match_operand:SI 9 "gpc_reg_operand" "r"))
9712 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9713 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9714 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9715 "{stsi|stswi} %2,%1,%O0"
9716 [(set_attr "type" "store_ux")
9717 (set_attr "cell_micro" "always")])
9719 (define_insn "*stmsi7_power"
9720 [(match_parallel 0 "store_multiple_operation"
9721 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9722 (match_operand:SI 2 "gpc_reg_operand" "r"))
9723 (clobber (match_scratch:SI 3 "=q"))
9724 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9725 (match_operand:SI 4 "gpc_reg_operand" "r"))
9726 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9727 (match_operand:SI 5 "gpc_reg_operand" "r"))
9728 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9729 (match_operand:SI 6 "gpc_reg_operand" "r"))
9730 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9731 (match_operand:SI 7 "gpc_reg_operand" "r"))
9732 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9733 (match_operand:SI 8 "gpc_reg_operand" "r"))
9734 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9735 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9736 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9737 "{stsi|stswi} %2,%1,%O0"
9738 [(set_attr "type" "store_ux")
9739 (set_attr "cell_micro" "always")])
9741 (define_insn "*stmsi6_power"
9742 [(match_parallel 0 "store_multiple_operation"
9743 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9744 (match_operand:SI 2 "gpc_reg_operand" "r"))
9745 (clobber (match_scratch:SI 3 "=q"))
9746 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9747 (match_operand:SI 4 "gpc_reg_operand" "r"))
9748 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9749 (match_operand:SI 5 "gpc_reg_operand" "r"))
9750 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9751 (match_operand:SI 6 "gpc_reg_operand" "r"))
9752 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9753 (match_operand:SI 7 "gpc_reg_operand" "r"))
9754 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9755 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9756 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9757 "{stsi|stswi} %2,%1,%O0"
9758 [(set_attr "type" "store_ux")
9759 (set_attr "cell_micro" "always")])
9761 (define_insn "*stmsi5_power"
9762 [(match_parallel 0 "store_multiple_operation"
9763 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9764 (match_operand:SI 2 "gpc_reg_operand" "r"))
9765 (clobber (match_scratch:SI 3 "=q"))
9766 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9767 (match_operand:SI 4 "gpc_reg_operand" "r"))
9768 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9769 (match_operand:SI 5 "gpc_reg_operand" "r"))
9770 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9771 (match_operand:SI 6 "gpc_reg_operand" "r"))
9772 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9773 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9774 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9775 "{stsi|stswi} %2,%1,%O0"
9776 [(set_attr "type" "store_ux")
9777 (set_attr "cell_micro" "always")])
9779 (define_insn "*stmsi4_power"
9780 [(match_parallel 0 "store_multiple_operation"
9781 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9782 (match_operand:SI 2 "gpc_reg_operand" "r"))
9783 (clobber (match_scratch:SI 3 "=q"))
9784 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9785 (match_operand:SI 4 "gpc_reg_operand" "r"))
9786 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9787 (match_operand:SI 5 "gpc_reg_operand" "r"))
9788 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9789 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9790 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9791 "{stsi|stswi} %2,%1,%O0"
9792 [(set_attr "type" "store_ux")
9793 (set_attr "cell_micro" "always")])
9795 (define_insn "*stmsi3_power"
9796 [(match_parallel 0 "store_multiple_operation"
9797 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9798 (match_operand:SI 2 "gpc_reg_operand" "r"))
9799 (clobber (match_scratch:SI 3 "=q"))
9800 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9801 (match_operand:SI 4 "gpc_reg_operand" "r"))
9802 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9803 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9804 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9805 "{stsi|stswi} %2,%1,%O0"
9806 [(set_attr "type" "store_ux")
9807 (set_attr "cell_micro" "always")])
9809 (define_expand "setmemsi"
9810 [(parallel [(set (match_operand:BLK 0 "" "")
9811 (match_operand 2 "const_int_operand" ""))
9812 (use (match_operand:SI 1 "" ""))
9813 (use (match_operand:SI 3 "" ""))])]
9817 /* If value to set is not zero, use the library routine. */
9818 if (operands[2] != const0_rtx)
9821 if (expand_block_clear (operands))
9827 ;; String/block move insn.
9828 ;; Argument 0 is the destination
9829 ;; Argument 1 is the source
9830 ;; Argument 2 is the length
9831 ;; Argument 3 is the alignment
9833 (define_expand "movmemsi"
9834 [(parallel [(set (match_operand:BLK 0 "" "")
9835 (match_operand:BLK 1 "" ""))
9836 (use (match_operand:SI 2 "" ""))
9837 (use (match_operand:SI 3 "" ""))])]
9841 if (expand_block_move (operands))
9847 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9848 ;; register allocator doesn't have a clue about allocating 8 word registers.
9849 ;; rD/rS = r5 is preferred, efficient form.
9850 (define_expand "movmemsi_8reg"
9851 [(parallel [(set (match_operand 0 "" "")
9852 (match_operand 1 "" ""))
9853 (use (match_operand 2 "" ""))
9854 (use (match_operand 3 "" ""))
9855 (clobber (reg:SI 5))
9856 (clobber (reg:SI 6))
9857 (clobber (reg:SI 7))
9858 (clobber (reg:SI 8))
9859 (clobber (reg:SI 9))
9860 (clobber (reg:SI 10))
9861 (clobber (reg:SI 11))
9862 (clobber (reg:SI 12))
9863 (clobber (match_scratch:SI 4 ""))])]
9868 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9869 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9870 (use (match_operand:SI 2 "immediate_operand" "i"))
9871 (use (match_operand:SI 3 "immediate_operand" "i"))
9872 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9873 (clobber (reg:SI 6))
9874 (clobber (reg:SI 7))
9875 (clobber (reg:SI 8))
9876 (clobber (reg:SI 9))
9877 (clobber (reg:SI 10))
9878 (clobber (reg:SI 11))
9879 (clobber (reg:SI 12))
9880 (clobber (match_scratch:SI 5 "=q"))]
9881 "TARGET_STRING && TARGET_POWER
9882 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9883 || INTVAL (operands[2]) == 0)
9884 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9885 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9886 && REGNO (operands[4]) == 5"
9887 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9888 [(set_attr "type" "store_ux")
9889 (set_attr "cell_micro" "always")
9890 (set_attr "length" "8")])
9893 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9894 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9895 (use (match_operand:SI 2 "immediate_operand" "i"))
9896 (use (match_operand:SI 3 "immediate_operand" "i"))
9897 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9898 (clobber (reg:SI 6))
9899 (clobber (reg:SI 7))
9900 (clobber (reg:SI 8))
9901 (clobber (reg:SI 9))
9902 (clobber (reg:SI 10))
9903 (clobber (reg:SI 11))
9904 (clobber (reg:SI 12))
9905 (clobber (match_scratch:SI 5 "=X"))]
9906 "TARGET_STRING && ! TARGET_POWER
9907 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9908 || INTVAL (operands[2]) == 0)
9909 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9910 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9911 && REGNO (operands[4]) == 5"
9912 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9913 [(set_attr "type" "store_ux")
9914 (set_attr "cell_micro" "always")
9915 (set_attr "length" "8")])
9917 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9918 ;; register allocator doesn't have a clue about allocating 6 word registers.
9919 ;; rD/rS = r5 is preferred, efficient form.
9920 (define_expand "movmemsi_6reg"
9921 [(parallel [(set (match_operand 0 "" "")
9922 (match_operand 1 "" ""))
9923 (use (match_operand 2 "" ""))
9924 (use (match_operand 3 "" ""))
9925 (clobber (reg:SI 5))
9926 (clobber (reg:SI 6))
9927 (clobber (reg:SI 7))
9928 (clobber (reg:SI 8))
9929 (clobber (reg:SI 9))
9930 (clobber (reg:SI 10))
9931 (clobber (match_scratch:SI 4 ""))])]
9936 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9937 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9938 (use (match_operand:SI 2 "immediate_operand" "i"))
9939 (use (match_operand:SI 3 "immediate_operand" "i"))
9940 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9941 (clobber (reg:SI 6))
9942 (clobber (reg:SI 7))
9943 (clobber (reg:SI 8))
9944 (clobber (reg:SI 9))
9945 (clobber (reg:SI 10))
9946 (clobber (match_scratch:SI 5 "=q"))]
9947 "TARGET_STRING && TARGET_POWER
9948 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9949 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9950 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9951 && REGNO (operands[4]) == 5"
9952 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9953 [(set_attr "type" "store_ux")
9954 (set_attr "cell_micro" "always")
9955 (set_attr "length" "8")])
9958 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9959 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9960 (use (match_operand:SI 2 "immediate_operand" "i"))
9961 (use (match_operand:SI 3 "immediate_operand" "i"))
9962 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9963 (clobber (reg:SI 6))
9964 (clobber (reg:SI 7))
9965 (clobber (reg:SI 8))
9966 (clobber (reg:SI 9))
9967 (clobber (reg:SI 10))
9968 (clobber (match_scratch:SI 5 "=X"))]
9969 "TARGET_STRING && ! TARGET_POWER
9970 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9971 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9972 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9973 && REGNO (operands[4]) == 5"
9974 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9975 [(set_attr "type" "store_ux")
9976 (set_attr "cell_micro" "always")
9977 (set_attr "length" "8")])
9979 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9980 ;; problems with TImode.
9981 ;; rD/rS = r5 is preferred, efficient form.
9982 (define_expand "movmemsi_4reg"
9983 [(parallel [(set (match_operand 0 "" "")
9984 (match_operand 1 "" ""))
9985 (use (match_operand 2 "" ""))
9986 (use (match_operand 3 "" ""))
9987 (clobber (reg:SI 5))
9988 (clobber (reg:SI 6))
9989 (clobber (reg:SI 7))
9990 (clobber (reg:SI 8))
9991 (clobber (match_scratch:SI 4 ""))])]
9996 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9997 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9998 (use (match_operand:SI 2 "immediate_operand" "i"))
9999 (use (match_operand:SI 3 "immediate_operand" "i"))
10000 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10001 (clobber (reg:SI 6))
10002 (clobber (reg:SI 7))
10003 (clobber (reg:SI 8))
10004 (clobber (match_scratch:SI 5 "=q"))]
10005 "TARGET_STRING && TARGET_POWER
10006 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10007 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10008 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10009 && REGNO (operands[4]) == 5"
10010 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10011 [(set_attr "type" "store_ux")
10012 (set_attr "cell_micro" "always")
10013 (set_attr "length" "8")])
10016 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10017 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10018 (use (match_operand:SI 2 "immediate_operand" "i"))
10019 (use (match_operand:SI 3 "immediate_operand" "i"))
10020 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10021 (clobber (reg:SI 6))
10022 (clobber (reg:SI 7))
10023 (clobber (reg:SI 8))
10024 (clobber (match_scratch:SI 5 "=X"))]
10025 "TARGET_STRING && ! TARGET_POWER
10026 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10027 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10028 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10029 && REGNO (operands[4]) == 5"
10030 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10031 [(set_attr "type" "store_ux")
10032 (set_attr "cell_micro" "always")
10033 (set_attr "length" "8")])
10035 ;; Move up to 8 bytes at a time.
10036 (define_expand "movmemsi_2reg"
10037 [(parallel [(set (match_operand 0 "" "")
10038 (match_operand 1 "" ""))
10039 (use (match_operand 2 "" ""))
10040 (use (match_operand 3 "" ""))
10041 (clobber (match_scratch:DI 4 ""))
10042 (clobber (match_scratch:SI 5 ""))])]
10043 "TARGET_STRING && ! TARGET_POWERPC64"
10047 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10048 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10049 (use (match_operand:SI 2 "immediate_operand" "i"))
10050 (use (match_operand:SI 3 "immediate_operand" "i"))
10051 (clobber (match_scratch:DI 4 "=&r"))
10052 (clobber (match_scratch:SI 5 "=q"))]
10053 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
10054 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
10055 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10056 [(set_attr "type" "store_ux")
10057 (set_attr "cell_micro" "always")
10058 (set_attr "length" "8")])
10061 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10062 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10063 (use (match_operand:SI 2 "immediate_operand" "i"))
10064 (use (match_operand:SI 3 "immediate_operand" "i"))
10065 (clobber (match_scratch:DI 4 "=&r"))
10066 (clobber (match_scratch:SI 5 "=X"))]
10067 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
10068 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
10069 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10070 [(set_attr "type" "store_ux")
10071 (set_attr "cell_micro" "always")
10072 (set_attr "length" "8")])
10074 ;; Move up to 4 bytes at a time.
10075 (define_expand "movmemsi_1reg"
10076 [(parallel [(set (match_operand 0 "" "")
10077 (match_operand 1 "" ""))
10078 (use (match_operand 2 "" ""))
10079 (use (match_operand 3 "" ""))
10080 (clobber (match_scratch:SI 4 ""))
10081 (clobber (match_scratch:SI 5 ""))])]
10086 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10087 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10088 (use (match_operand:SI 2 "immediate_operand" "i"))
10089 (use (match_operand:SI 3 "immediate_operand" "i"))
10090 (clobber (match_scratch:SI 4 "=&r"))
10091 (clobber (match_scratch:SI 5 "=q"))]
10092 "TARGET_STRING && TARGET_POWER
10093 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
10094 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10095 [(set_attr "type" "store_ux")
10096 (set_attr "cell_micro" "always")
10097 (set_attr "length" "8")])
10100 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10101 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10102 (use (match_operand:SI 2 "immediate_operand" "i"))
10103 (use (match_operand:SI 3 "immediate_operand" "i"))
10104 (clobber (match_scratch:SI 4 "=&r"))
10105 (clobber (match_scratch:SI 5 "=X"))]
10106 "TARGET_STRING && ! TARGET_POWER
10107 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
10108 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10109 [(set_attr "type" "store_ux")
10110 (set_attr "cell_micro" "always")
10111 (set_attr "length" "8")])
10113 ;; Define insns that do load or store with update. Some of these we can
10114 ;; get by using pre-decrement or pre-increment, but the hardware can also
10115 ;; do cases where the increment is not the size of the object.
10117 ;; In all these cases, we use operands 0 and 1 for the register being
10118 ;; incremented because those are the operands that local-alloc will
10119 ;; tie and these are the pair most likely to be tieable (and the ones
10120 ;; that will benefit the most).
10122 (define_insn "*movdi_update1"
10123 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
10124 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
10125 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
10126 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
10127 (plus:DI (match_dup 1) (match_dup 2)))]
10128 "TARGET_POWERPC64 && TARGET_UPDATE
10129 && (!avoiding_indexed_address_p (DImode)
10130 || !gpc_reg_operand (operands[2], DImode))"
10134 [(set_attr "type" "load_ux,load_u")])
10136 (define_insn "movdi_<mode>_update"
10137 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10138 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10139 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10140 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10141 (plus:P (match_dup 1) (match_dup 2)))]
10142 "TARGET_POWERPC64 && TARGET_UPDATE
10143 && (!avoiding_indexed_address_p (Pmode)
10144 || !gpc_reg_operand (operands[2], Pmode)
10145 || (REG_P (operands[0])
10146 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10150 [(set_attr "type" "store_ux,store_u")])
10152 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
10153 ;; needed for stack allocation, even if the user passes -mno-update.
10154 (define_insn "movdi_<mode>_update_stack"
10155 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10156 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10157 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10158 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10159 (plus:P (match_dup 1) (match_dup 2)))]
10164 [(set_attr "type" "store_ux,store_u")])
10166 (define_insn "*movsi_update1"
10167 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10168 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10169 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10170 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10171 (plus:SI (match_dup 1) (match_dup 2)))]
10173 && (!avoiding_indexed_address_p (SImode)
10174 || !gpc_reg_operand (operands[2], SImode))"
10176 {lux|lwzux} %3,%0,%2
10177 {lu|lwzu} %3,%2(%0)"
10178 [(set_attr "type" "load_ux,load_u")])
10180 (define_insn "*movsi_update2"
10181 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
10183 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
10184 (match_operand:DI 2 "gpc_reg_operand" "r")))))
10185 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
10186 (plus:DI (match_dup 1) (match_dup 2)))]
10187 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
10188 && !avoiding_indexed_address_p (DImode)"
10190 [(set_attr "type" "load_ext_ux")])
10192 (define_insn "movsi_update"
10193 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10194 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10195 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10196 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10197 (plus:SI (match_dup 1) (match_dup 2)))]
10199 && (!avoiding_indexed_address_p (SImode)
10200 || !gpc_reg_operand (operands[2], SImode)
10201 || (REG_P (operands[0])
10202 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10204 {stux|stwux} %3,%0,%2
10205 {stu|stwu} %3,%2(%0)"
10206 [(set_attr "type" "store_ux,store_u")])
10208 ;; This is an unconditional pattern; needed for stack allocation, even
10209 ;; if the user passes -mno-update.
10210 (define_insn "movsi_update_stack"
10211 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10212 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10213 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10214 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10215 (plus:SI (match_dup 1) (match_dup 2)))]
10218 {stux|stwux} %3,%0,%2
10219 {stu|stwu} %3,%2(%0)"
10220 [(set_attr "type" "store_ux,store_u")])
10222 (define_insn "*movhi_update1"
10223 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
10224 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10225 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10226 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10227 (plus:SI (match_dup 1) (match_dup 2)))]
10229 && (!avoiding_indexed_address_p (SImode)
10230 || !gpc_reg_operand (operands[2], SImode))"
10234 [(set_attr "type" "load_ux,load_u")])
10236 (define_insn "*movhi_update2"
10237 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10239 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10240 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10241 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10242 (plus:SI (match_dup 1) (match_dup 2)))]
10244 && (!avoiding_indexed_address_p (SImode)
10245 || !gpc_reg_operand (operands[2], SImode))"
10249 [(set_attr "type" "load_ux,load_u")])
10251 (define_insn "*movhi_update3"
10252 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10254 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10255 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10256 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10257 (plus:SI (match_dup 1) (match_dup 2)))]
10258 "TARGET_UPDATE && rs6000_gen_cell_microcode
10259 && (!avoiding_indexed_address_p (SImode)
10260 || !gpc_reg_operand (operands[2], SImode))"
10264 [(set_attr "type" "load_ext_ux,load_ext_u")])
10266 (define_insn "*movhi_update4"
10267 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10268 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10269 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
10270 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10271 (plus:SI (match_dup 1) (match_dup 2)))]
10273 && (!avoiding_indexed_address_p (SImode)
10274 || !gpc_reg_operand (operands[2], SImode))"
10278 [(set_attr "type" "store_ux,store_u")])
10280 (define_insn "*movqi_update1"
10281 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
10282 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10283 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10284 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10285 (plus:SI (match_dup 1) (match_dup 2)))]
10287 && (!avoiding_indexed_address_p (SImode)
10288 || !gpc_reg_operand (operands[2], SImode))"
10292 [(set_attr "type" "load_ux,load_u")])
10294 (define_insn "*movqi_update2"
10295 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10297 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10298 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10299 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10300 (plus:SI (match_dup 1) (match_dup 2)))]
10302 && (!avoiding_indexed_address_p (SImode)
10303 || !gpc_reg_operand (operands[2], SImode))"
10307 [(set_attr "type" "load_ux,load_u")])
10309 (define_insn "*movqi_update3"
10310 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10311 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10312 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
10313 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10314 (plus:SI (match_dup 1) (match_dup 2)))]
10316 && (!avoiding_indexed_address_p (SImode)
10317 || !gpc_reg_operand (operands[2], SImode))"
10321 [(set_attr "type" "store_ux,store_u")])
10323 (define_insn "*movsf_update1"
10324 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
10325 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10326 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10327 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10328 (plus:SI (match_dup 1) (match_dup 2)))]
10329 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10330 && (!avoiding_indexed_address_p (SImode)
10331 || !gpc_reg_operand (operands[2], SImode))"
10335 [(set_attr "type" "fpload_ux,fpload_u")])
10337 (define_insn "*movsf_update2"
10338 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10339 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10340 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10341 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10342 (plus:SI (match_dup 1) (match_dup 2)))]
10343 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10344 && (!avoiding_indexed_address_p (SImode)
10345 || !gpc_reg_operand (operands[2], SImode))"
10349 [(set_attr "type" "fpstore_ux,fpstore_u")])
10351 (define_insn "*movsf_update3"
10352 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10353 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10354 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10355 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10356 (plus:SI (match_dup 1) (match_dup 2)))]
10357 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10358 && (!avoiding_indexed_address_p (SImode)
10359 || !gpc_reg_operand (operands[2], SImode))"
10361 {lux|lwzux} %3,%0,%2
10362 {lu|lwzu} %3,%2(%0)"
10363 [(set_attr "type" "load_ux,load_u")])
10365 (define_insn "*movsf_update4"
10366 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10367 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10368 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10369 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10370 (plus:SI (match_dup 1) (match_dup 2)))]
10371 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10372 && (!avoiding_indexed_address_p (SImode)
10373 || !gpc_reg_operand (operands[2], SImode))"
10375 {stux|stwux} %3,%0,%2
10376 {stu|stwu} %3,%2(%0)"
10377 [(set_attr "type" "store_ux,store_u")])
10379 (define_insn "*movdf_update1"
10380 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
10381 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10382 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10383 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10384 (plus:SI (match_dup 1) (match_dup 2)))]
10385 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10386 && (!avoiding_indexed_address_p (SImode)
10387 || !gpc_reg_operand (operands[2], SImode))"
10391 [(set_attr "type" "fpload_ux,fpload_u")])
10393 (define_insn "*movdf_update2"
10394 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10395 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10396 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
10397 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10398 (plus:SI (match_dup 1) (match_dup 2)))]
10399 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10400 && (!avoiding_indexed_address_p (SImode)
10401 || !gpc_reg_operand (operands[2], SImode))"
10405 [(set_attr "type" "fpstore_ux,fpstore_u")])
10407 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
10409 (define_insn "*lfq_power2"
10410 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
10411 (match_operand:V2DF 1 "memory_operand" ""))]
10413 && TARGET_HARD_FLOAT && TARGET_FPRS"
10417 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10418 (match_operand:DF 1 "memory_operand" ""))
10419 (set (match_operand:DF 2 "gpc_reg_operand" "")
10420 (match_operand:DF 3 "memory_operand" ""))]
10422 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
10423 && registers_ok_for_quad_peep (operands[0], operands[2])
10424 && mems_ok_for_quad_peep (operands[1], operands[3])"
10425 [(set (match_dup 0)
10427 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
10428 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
10430 (define_insn "*stfq_power2"
10431 [(set (match_operand:V2DF 0 "memory_operand" "")
10432 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
10434 && TARGET_HARD_FLOAT && TARGET_FPRS"
10435 "stfq%U0%X0 %1,%0")
10439 [(set (match_operand:DF 0 "memory_operand" "")
10440 (match_operand:DF 1 "gpc_reg_operand" ""))
10441 (set (match_operand:DF 2 "memory_operand" "")
10442 (match_operand:DF 3 "gpc_reg_operand" ""))]
10444 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
10445 && registers_ok_for_quad_peep (operands[1], operands[3])
10446 && mems_ok_for_quad_peep (operands[0], operands[2])"
10447 [(set (match_dup 0)
10449 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
10450 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
10452 ;; After inserting conditional returns we can sometimes have
10453 ;; unnecessary register moves. Unfortunately we cannot have a
10454 ;; modeless peephole here, because some single SImode sets have early
10455 ;; clobber outputs. Although those sets expand to multi-ppc-insn
10456 ;; sequences, using get_attr_length here will smash the operands
10457 ;; array. Neither is there an early_cobbler_p predicate.
10458 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
10460 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10461 (match_operand:DF 1 "any_operand" ""))
10462 (set (match_operand:DF 2 "gpc_reg_operand" "")
10464 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10465 && peep2_reg_dead_p (2, operands[0])"
10466 [(set (match_dup 2) (match_dup 1))])
10469 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10470 (match_operand:SF 1 "any_operand" ""))
10471 (set (match_operand:SF 2 "gpc_reg_operand" "")
10473 "peep2_reg_dead_p (2, operands[0])"
10474 [(set (match_dup 2) (match_dup 1))])
10479 ;; Mode attributes for different ABIs.
10480 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
10481 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
10482 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
10483 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
10485 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
10486 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10487 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10488 (match_operand 4 "" "g")))
10489 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10490 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10492 (clobber (reg:SI LR_REGNO))]
10493 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10494 "addi %0,%1,%2@got@tlsgd\;bl %z3\;%."
10495 "&& TARGET_TLS_MARKERS"
10496 [(set (match_dup 0)
10497 (unspec:TLSmode [(match_dup 1)
10500 (parallel [(set (match_dup 0)
10501 (call (mem:TLSmode (match_dup 3))
10503 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
10504 (clobber (reg:SI LR_REGNO))])]
10506 [(set_attr "type" "two")
10507 (set_attr "length" "12")])
10509 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
10510 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10511 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10512 (match_operand 4 "" "g")))
10513 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10514 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10516 (clobber (reg:SI LR_REGNO))]
10517 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10521 if (TARGET_SECURE_PLT && flag_pic == 2)
10522 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
10524 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
10527 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
10529 "&& TARGET_TLS_MARKERS"
10530 [(set (match_dup 0)
10531 (unspec:TLSmode [(match_dup 1)
10534 (parallel [(set (match_dup 0)
10535 (call (mem:TLSmode (match_dup 3))
10537 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
10538 (clobber (reg:SI LR_REGNO))])]
10540 [(set_attr "type" "two")
10541 (set_attr "length" "8")])
10543 (define_insn "*tls_gd<TLSmode:tls_abi_suffix>"
10544 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10545 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10546 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10548 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
10549 "addi %0,%1,%2@got@tlsgd"
10550 [(set_attr "length" "4")])
10552 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
10553 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10554 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10555 (match_operand 2 "" "g")))
10556 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
10558 (clobber (reg:SI LR_REGNO))]
10559 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
10560 "bl %z1(%3@tlsgd)\;%."
10561 [(set_attr "type" "branch")
10562 (set_attr "length" "8")])
10564 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
10565 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10566 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10567 (match_operand 2 "" "g")))
10568 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
10570 (clobber (reg:SI LR_REGNO))]
10571 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
10575 if (TARGET_SECURE_PLT && flag_pic == 2)
10576 return "bl %z1+32768(%3@tlsgd)@plt";
10577 return "bl %z1(%3@tlsgd)@plt";
10579 return "bl %z1(%3@tlsgd)";
10581 [(set_attr "type" "branch")
10582 (set_attr "length" "4")])
10584 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
10585 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10586 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10587 (match_operand 3 "" "g")))
10588 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10590 (clobber (reg:SI LR_REGNO))]
10591 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10592 "addi %0,%1,%&@got@tlsld\;bl %z2\;%."
10593 "&& TARGET_TLS_MARKERS"
10594 [(set (match_dup 0)
10595 (unspec:TLSmode [(match_dup 1)]
10597 (parallel [(set (match_dup 0)
10598 (call (mem:TLSmode (match_dup 2))
10600 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10601 (clobber (reg:SI LR_REGNO))])]
10603 [(set_attr "length" "12")])
10605 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
10606 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10607 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10608 (match_operand 3 "" "g")))
10609 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10611 (clobber (reg:SI LR_REGNO))]
10612 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10616 if (TARGET_SECURE_PLT && flag_pic == 2)
10617 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
10619 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
10622 return "addi %0,%1,%&@got@tlsld\;bl %z2";
10624 "&& TARGET_TLS_MARKERS"
10625 [(set (match_dup 0)
10626 (unspec:TLSmode [(match_dup 1)]
10628 (parallel [(set (match_dup 0)
10629 (call (mem:TLSmode (match_dup 2))
10631 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10632 (clobber (reg:SI LR_REGNO))])]
10634 [(set_attr "length" "8")])
10636 (define_insn "*tls_ld<TLSmode:tls_abi_suffix>"
10637 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10638 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10640 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
10641 "addi %0,%1,%&@got@tlsld"
10642 [(set_attr "length" "4")])
10644 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
10645 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10646 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10647 (match_operand 2 "" "g")))
10648 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10649 (clobber (reg:SI LR_REGNO))]
10650 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
10651 "bl %z1(%&@tlsld)\;%."
10652 [(set_attr "type" "branch")
10653 (set_attr "length" "8")])
10655 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
10656 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10657 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10658 (match_operand 2 "" "g")))
10659 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10660 (clobber (reg:SI LR_REGNO))]
10661 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
10665 if (TARGET_SECURE_PLT && flag_pic == 2)
10666 return "bl %z1+32768(%&@tlsld)@plt";
10667 return "bl %z1(%&@tlsld)@plt";
10669 return "bl %z1(%&@tlsld)";
10671 [(set_attr "type" "branch")
10672 (set_attr "length" "4")])
10674 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
10675 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10676 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10677 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10678 UNSPEC_TLSDTPREL))]
10680 "addi %0,%1,%2@dtprel")
10682 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
10683 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10684 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10685 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10686 UNSPEC_TLSDTPRELHA))]
10688 "addis %0,%1,%2@dtprel@ha")
10690 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
10691 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10692 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10693 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10694 UNSPEC_TLSDTPRELLO))]
10696 "addi %0,%1,%2@dtprel@l")
10698 (define_insn "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
10699 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10700 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10701 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10702 UNSPEC_TLSGOTDTPREL))]
10704 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)")
10706 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
10707 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10708 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10709 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10712 "addi %0,%1,%2@tprel")
10714 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
10715 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10716 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10717 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10718 UNSPEC_TLSTPRELHA))]
10720 "addis %0,%1,%2@tprel@ha")
10722 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
10723 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10724 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10725 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10726 UNSPEC_TLSTPRELLO))]
10728 "addi %0,%1,%2@tprel@l")
10730 ;; "b" output constraint here and on tls_tls input to support linker tls
10731 ;; optimization. The linker may edit the instructions emitted by a
10732 ;; tls_got_tprel/tls_tls pair to addis,addi.
10733 (define_insn "tls_got_tprel_<TLSmode:tls_abi_suffix>"
10734 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10735 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10736 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10737 UNSPEC_TLSGOTTPREL))]
10739 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)")
10741 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
10742 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10743 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10744 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10747 "add %0,%1,%2@tls")
10750 ;; Next come insns related to the calling sequence.
10752 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
10753 ;; We move the back-chain and decrement the stack pointer.
10755 (define_expand "allocate_stack"
10756 [(set (match_operand 0 "gpc_reg_operand" "")
10757 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10759 (minus (reg 1) (match_dup 1)))]
10762 { rtx chain = gen_reg_rtx (Pmode);
10763 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
10765 rtx insn, par, set, mem;
10767 emit_move_insn (chain, stack_bot);
10769 /* Check stack bounds if necessary. */
10770 if (crtl->limit_stack)
10773 available = expand_binop (Pmode, sub_optab,
10774 stack_pointer_rtx, stack_limit_rtx,
10775 NULL_RTX, 1, OPTAB_WIDEN);
10776 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10779 if (GET_CODE (operands[1]) != CONST_INT
10780 || INTVAL (operands[1]) < -32767
10781 || INTVAL (operands[1]) > 32768)
10783 neg_op0 = gen_reg_rtx (Pmode);
10785 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10787 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10790 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10792 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
10793 : gen_movdi_di_update_stack))
10794 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
10796 /* Since we didn't use gen_frame_mem to generate the MEM, grab
10797 it now and set the alias set/attributes. The above gen_*_update
10798 calls will generate a PARALLEL with the MEM set being the first
10800 par = PATTERN (insn);
10801 gcc_assert (GET_CODE (par) == PARALLEL);
10802 set = XVECEXP (par, 0, 0);
10803 gcc_assert (GET_CODE (set) == SET);
10804 mem = SET_DEST (set);
10805 gcc_assert (MEM_P (mem));
10806 MEM_NOTRAP_P (mem) = 1;
10807 set_mem_alias_set (mem, get_frame_alias_set ());
10809 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10813 ;; These patterns say how to save and restore the stack pointer. We need not
10814 ;; save the stack pointer at function level since we are careful to
10815 ;; preserve the backchain. At block level, we have to restore the backchain
10816 ;; when we restore the stack pointer.
10818 ;; For nonlocal gotos, we must save both the stack pointer and its
10819 ;; backchain and restore both. Note that in the nonlocal case, the
10820 ;; save area is a memory location.
10822 (define_expand "save_stack_function"
10823 [(match_operand 0 "any_operand" "")
10824 (match_operand 1 "any_operand" "")]
10828 (define_expand "restore_stack_function"
10829 [(match_operand 0 "any_operand" "")
10830 (match_operand 1 "any_operand" "")]
10834 ;; Adjust stack pointer (op0) to a new value (op1).
10835 ;; First copy old stack backchain to new location, and ensure that the
10836 ;; scheduler won't reorder the sp assignment before the backchain write.
10837 (define_expand "restore_stack_block"
10838 [(set (match_dup 2) (match_dup 3))
10839 (set (match_dup 4) (match_dup 2))
10840 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
10841 (set (match_operand 0 "register_operand" "")
10842 (match_operand 1 "register_operand" ""))]
10846 operands[1] = force_reg (Pmode, operands[1]);
10847 operands[2] = gen_reg_rtx (Pmode);
10848 operands[3] = gen_frame_mem (Pmode, operands[0]);
10849 operands[4] = gen_frame_mem (Pmode, operands[1]);
10850 operands[5] = gen_frame_mem (BLKmode, operands[0]);
10853 (define_expand "save_stack_nonlocal"
10854 [(set (match_dup 3) (match_dup 4))
10855 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10856 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
10860 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10862 /* Copy the backchain to the first word, sp to the second. */
10863 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10864 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10865 operands[3] = gen_reg_rtx (Pmode);
10866 operands[4] = gen_frame_mem (Pmode, operands[1]);
10869 (define_expand "restore_stack_nonlocal"
10870 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10871 (set (match_dup 3) (match_dup 4))
10872 (set (match_dup 5) (match_dup 2))
10873 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
10874 (set (match_operand 0 "register_operand" "") (match_dup 3))]
10878 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10880 /* Restore the backchain from the first word, sp from the second. */
10881 operands[2] = gen_reg_rtx (Pmode);
10882 operands[3] = gen_reg_rtx (Pmode);
10883 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10884 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10885 operands[5] = gen_frame_mem (Pmode, operands[3]);
10886 operands[6] = gen_frame_mem (BLKmode, operands[0]);
10889 ;; TOC register handling.
10891 ;; Code to initialize the TOC register...
10893 (define_insn "load_toc_aix_si"
10894 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10895 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10896 (use (reg:SI 2))])]
10897 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10901 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10902 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10903 operands[2] = gen_rtx_REG (Pmode, 2);
10904 return \"{l|lwz} %0,%1(%2)\";
10906 [(set_attr "type" "load")])
10908 (define_insn "load_toc_aix_di"
10909 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10910 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10911 (use (reg:DI 2))])]
10912 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10916 #ifdef TARGET_RELOCATABLE
10917 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10918 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10920 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10923 strcat (buf, \"@toc\");
10924 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10925 operands[2] = gen_rtx_REG (Pmode, 2);
10926 return \"ld %0,%1(%2)\";
10928 [(set_attr "type" "load")])
10930 (define_insn "load_toc_v4_pic_si"
10931 [(set (reg:SI LR_REGNO)
10932 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10933 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10934 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10935 [(set_attr "type" "branch")
10936 (set_attr "length" "4")])
10938 (define_insn "load_toc_v4_PIC_1"
10939 [(set (reg:SI LR_REGNO)
10940 (match_operand:SI 0 "immediate_operand" "s"))
10941 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10942 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
10943 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10944 "bcl 20,31,%0\\n%0:"
10945 [(set_attr "type" "branch")
10946 (set_attr "length" "4")])
10948 (define_insn "load_toc_v4_PIC_1b"
10949 [(set (reg:SI LR_REGNO)
10950 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")]
10952 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10953 "bcl 20,31,$+8\\n\\t.long %0-$"
10954 [(set_attr "type" "branch")
10955 (set_attr "length" "8")])
10957 (define_insn "load_toc_v4_PIC_2"
10958 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10959 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10960 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10961 (match_operand:SI 3 "immediate_operand" "s")))))]
10962 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10963 "{l|lwz} %0,%2-%3(%1)"
10964 [(set_attr "type" "load")])
10966 (define_insn "load_toc_v4_PIC_3b"
10967 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10968 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10970 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10971 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10972 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10973 "{cau|addis} %0,%1,%2-%3@ha")
10975 (define_insn "load_toc_v4_PIC_3c"
10976 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10977 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10978 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10979 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10980 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10981 "{cal|addi} %0,%1,%2-%3@l")
10983 ;; If the TOC is shared over a translation unit, as happens with all
10984 ;; the kinds of PIC that we support, we need to restore the TOC
10985 ;; pointer only when jumping over units of translation.
10986 ;; On Darwin, we need to reload the picbase.
10988 (define_expand "builtin_setjmp_receiver"
10989 [(use (label_ref (match_operand 0 "" "")))]
10990 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10991 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10992 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10996 if (DEFAULT_ABI == ABI_DARWIN)
10998 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
10999 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
11003 crtl->uses_pic_offset_table = 1;
11004 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
11005 CODE_LABEL_NUMBER (operands[0]));
11006 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
11008 emit_insn (gen_load_macho_picbase (tmplabrtx));
11009 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
11010 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
11014 rs6000_emit_load_toc_table (FALSE);
11018 ;; Elf specific ways of loading addresses for non-PIC code.
11019 ;; The output of this could be r0, but we make a very strong
11020 ;; preference for a base register because it will usually
11021 ;; be needed there.
11022 (define_insn "elf_high"
11023 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
11024 (high:SI (match_operand 1 "" "")))]
11025 "TARGET_ELF && ! TARGET_64BIT"
11026 "{liu|lis} %0,%1@ha")
11028 (define_insn "elf_low"
11029 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11030 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
11031 (match_operand 2 "" "")))]
11032 "TARGET_ELF && ! TARGET_64BIT"
11034 {cal|la} %0,%2@l(%1)
11035 {ai|addic} %0,%1,%K2")
11037 ;; A function pointer under AIX is a pointer to a data area whose first word
11038 ;; contains the actual address of the function, whose second word contains a
11039 ;; pointer to its TOC, and whose third word contains a value to place in the
11040 ;; static chain register (r11). Note that if we load the static chain, our
11041 ;; "trampoline" need not have any executable code.
11043 (define_expand "call_indirect_aix32"
11044 [(set (match_dup 2)
11045 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
11046 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
11049 (mem:SI (plus:SI (match_dup 0)
11051 (parallel [(call (mem:SI (match_dup 2))
11052 (match_operand 1 "" ""))
11053 (use (mem:SI (plus:SI (match_dup 0) (const_int 4))))
11055 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11056 (clobber (reg:SI LR_REGNO))])]
11059 { operands[2] = gen_reg_rtx (SImode); }")
11061 (define_expand "call_indirect_aix64"
11062 [(set (match_dup 2)
11063 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
11064 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
11067 (mem:DI (plus:DI (match_dup 0)
11069 (parallel [(call (mem:SI (match_dup 2))
11070 (match_operand 1 "" ""))
11071 (use (mem:DI (plus:DI (match_dup 0) (const_int 8))))
11073 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11074 (clobber (reg:SI LR_REGNO))])]
11077 { operands[2] = gen_reg_rtx (DImode); }")
11079 (define_expand "call_value_indirect_aix32"
11080 [(set (match_dup 3)
11081 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11082 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
11085 (mem:SI (plus:SI (match_dup 1)
11087 (parallel [(set (match_operand 0 "" "")
11088 (call (mem:SI (match_dup 3))
11089 (match_operand 2 "" "")))
11090 (use (mem:SI (plus:SI (match_dup 1) (const_int 4))))
11092 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11093 (clobber (reg:SI LR_REGNO))])]
11096 { operands[3] = gen_reg_rtx (SImode); }")
11098 (define_expand "call_value_indirect_aix64"
11099 [(set (match_dup 3)
11100 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11101 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
11104 (mem:DI (plus:DI (match_dup 1)
11106 (parallel [(set (match_operand 0 "" "")
11107 (call (mem:SI (match_dup 3))
11108 (match_operand 2 "" "")))
11109 (use (mem:DI (plus:DI (match_dup 1) (const_int 8))))
11111 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11112 (clobber (reg:SI LR_REGNO))])]
11115 { operands[3] = gen_reg_rtx (DImode); }")
11117 ;; Now the definitions for the call and call_value insns
11118 (define_expand "call"
11119 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11120 (match_operand 1 "" ""))
11121 (use (match_operand 2 "" ""))
11122 (clobber (reg:SI LR_REGNO))])]
11127 if (MACHOPIC_INDIRECT)
11128 operands[0] = machopic_indirect_call_target (operands[0]);
11131 gcc_assert (GET_CODE (operands[0]) == MEM);
11132 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11134 operands[0] = XEXP (operands[0], 0);
11136 if (GET_CODE (operands[0]) != SYMBOL_REF
11137 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
11138 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
11140 if (INTVAL (operands[2]) & CALL_LONG)
11141 operands[0] = rs6000_longcall_ref (operands[0]);
11143 switch (DEFAULT_ABI)
11147 operands[0] = force_reg (Pmode, operands[0]);
11151 /* AIX function pointers are really pointers to a three word
11153 emit_call_insn (TARGET_32BIT
11154 ? gen_call_indirect_aix32 (force_reg (SImode,
11157 : gen_call_indirect_aix64 (force_reg (DImode,
11163 gcc_unreachable ();
11168 (define_expand "call_value"
11169 [(parallel [(set (match_operand 0 "" "")
11170 (call (mem:SI (match_operand 1 "address_operand" ""))
11171 (match_operand 2 "" "")))
11172 (use (match_operand 3 "" ""))
11173 (clobber (reg:SI LR_REGNO))])]
11178 if (MACHOPIC_INDIRECT)
11179 operands[1] = machopic_indirect_call_target (operands[1]);
11182 gcc_assert (GET_CODE (operands[1]) == MEM);
11183 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11185 operands[1] = XEXP (operands[1], 0);
11187 if (GET_CODE (operands[1]) != SYMBOL_REF
11188 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
11189 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
11191 if (INTVAL (operands[3]) & CALL_LONG)
11192 operands[1] = rs6000_longcall_ref (operands[1]);
11194 switch (DEFAULT_ABI)
11198 operands[1] = force_reg (Pmode, operands[1]);
11202 /* AIX function pointers are really pointers to a three word
11204 emit_call_insn (TARGET_32BIT
11205 ? gen_call_value_indirect_aix32 (operands[0],
11209 : gen_call_value_indirect_aix64 (operands[0],
11216 gcc_unreachable ();
11221 ;; Call to function in current module. No TOC pointer reload needed.
11222 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
11223 ;; either the function was not prototyped, or it was prototyped as a
11224 ;; variable argument function. It is > 0 if FP registers were passed
11225 ;; and < 0 if they were not.
11227 (define_insn "*call_local32"
11228 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11229 (match_operand 1 "" "g,g"))
11230 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11231 (clobber (reg:SI LR_REGNO))]
11232 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11235 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11236 output_asm_insn (\"crxor 6,6,6\", operands);
11238 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11239 output_asm_insn (\"creqv 6,6,6\", operands);
11241 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11243 [(set_attr "type" "branch")
11244 (set_attr "length" "4,8")])
11246 (define_insn "*call_local64"
11247 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11248 (match_operand 1 "" "g,g"))
11249 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11250 (clobber (reg:SI LR_REGNO))]
11251 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11254 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11255 output_asm_insn (\"crxor 6,6,6\", operands);
11257 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11258 output_asm_insn (\"creqv 6,6,6\", operands);
11260 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11262 [(set_attr "type" "branch")
11263 (set_attr "length" "4,8")])
11265 (define_insn "*call_value_local32"
11266 [(set (match_operand 0 "" "")
11267 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11268 (match_operand 2 "" "g,g")))
11269 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11270 (clobber (reg:SI LR_REGNO))]
11271 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11274 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11275 output_asm_insn (\"crxor 6,6,6\", operands);
11277 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11278 output_asm_insn (\"creqv 6,6,6\", operands);
11280 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11282 [(set_attr "type" "branch")
11283 (set_attr "length" "4,8")])
11286 (define_insn "*call_value_local64"
11287 [(set (match_operand 0 "" "")
11288 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11289 (match_operand 2 "" "g,g")))
11290 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11291 (clobber (reg:SI LR_REGNO))]
11292 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11295 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11296 output_asm_insn (\"crxor 6,6,6\", operands);
11298 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11299 output_asm_insn (\"creqv 6,6,6\", operands);
11301 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11303 [(set_attr "type" "branch")
11304 (set_attr "length" "4,8")])
11306 ;; Call to function which may be in another module. Restore the TOC
11307 ;; pointer (r2) after the call unless this is System V.
11308 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
11309 ;; either the function was not prototyped, or it was prototyped as a
11310 ;; variable argument function. It is > 0 if FP registers were passed
11311 ;; and < 0 if they were not.
11313 (define_insn_and_split "*call_indirect_nonlocal_aix32_internal"
11314 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
11315 (match_operand 1 "" "g,g"))
11316 (use (mem:SI (plus:SI (match_operand:SI 2 "register_operand" "b,b") (const_int 4))))
11318 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11319 (clobber (reg:SI LR_REGNO))]
11320 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11322 "&& reload_completed"
11324 (mem:SI (plus:SI (match_dup 2) (const_int 4))))
11325 (parallel [(call (mem:SI (match_dup 0))
11330 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11331 (clobber (reg:SI LR_REGNO))])]
11333 [(set_attr "type" "jmpreg")
11334 (set_attr "length" "12")])
11336 (define_insn "*call_indirect_nonlocal_aix32"
11337 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
11338 (match_operand 1 "" "g,g"))
11342 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11343 (clobber (reg:SI LR_REGNO))]
11344 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11345 "b%T0l\;{l|lwz} 2,20(1)"
11346 [(set_attr "type" "jmpreg")
11347 (set_attr "length" "8")])
11349 (define_insn "*call_nonlocal_aix32"
11350 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11351 (match_operand 1 "" "g"))
11352 (use (match_operand:SI 2 "immediate_operand" "O"))
11353 (clobber (reg:SI LR_REGNO))]
11355 && DEFAULT_ABI == ABI_AIX
11356 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11358 [(set_attr "type" "branch")
11359 (set_attr "length" "8")])
11361 (define_insn_and_split "*call_indirect_nonlocal_aix64_internal"
11362 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
11363 (match_operand 1 "" "g,g"))
11364 (use (mem:DI (plus:DI (match_operand:DI 2 "register_operand" "b,b")
11367 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11368 (clobber (reg:SI LR_REGNO))]
11369 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11371 "&& reload_completed"
11373 (mem:DI (plus:DI (match_dup 2) (const_int 8))))
11374 (parallel [(call (mem:SI (match_dup 0))
11379 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11380 (clobber (reg:SI LR_REGNO))])]
11382 [(set_attr "type" "jmpreg")
11383 (set_attr "length" "12")])
11385 (define_insn "*call_indirect_nonlocal_aix64"
11386 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
11387 (match_operand 1 "" "g,g"))
11391 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11392 (clobber (reg:SI LR_REGNO))]
11393 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11394 "b%T0l\;ld 2,40(1)"
11395 [(set_attr "type" "jmpreg")
11396 (set_attr "length" "8")])
11398 (define_insn "*call_nonlocal_aix64"
11399 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11400 (match_operand 1 "" "g"))
11401 (use (match_operand:SI 2 "immediate_operand" "O"))
11402 (clobber (reg:SI LR_REGNO))]
11404 && DEFAULT_ABI == ABI_AIX
11405 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11407 [(set_attr "type" "branch")
11408 (set_attr "length" "8")])
11410 (define_insn_and_split "*call_value_indirect_nonlocal_aix32_internal"
11411 [(set (match_operand 0 "" "")
11412 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
11413 (match_operand 2 "" "g,g")))
11414 (use (mem:SI (plus:SI (match_operand:SI 3 "register_operand" "b,b")
11417 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11418 (clobber (reg:SI LR_REGNO))]
11419 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11421 "&& reload_completed"
11423 (mem:SI (plus:SI (match_dup 3) (const_int 4))))
11424 (parallel [(set (match_dup 0) (call (mem:SI (match_dup 1))
11429 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11430 (clobber (reg:SI LR_REGNO))])]
11432 [(set_attr "type" "jmpreg")
11433 (set_attr "length" "12")])
11435 (define_insn "*call_value_indirect_nonlocal_aix32"
11436 [(set (match_operand 0 "" "")
11437 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
11438 (match_operand 2 "" "g,g")))
11442 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11443 (clobber (reg:SI LR_REGNO))]
11444 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11445 "b%T1l\;{l|lwz} 2,20(1)"
11446 [(set_attr "type" "jmpreg")
11447 (set_attr "length" "8")])
11449 (define_insn "*call_value_nonlocal_aix32"
11450 [(set (match_operand 0 "" "")
11451 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11452 (match_operand 2 "" "g")))
11453 (use (match_operand:SI 3 "immediate_operand" "O"))
11454 (clobber (reg:SI LR_REGNO))]
11456 && DEFAULT_ABI == ABI_AIX
11457 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11459 [(set_attr "type" "branch")
11460 (set_attr "length" "8")])
11462 (define_insn_and_split "*call_value_indirect_nonlocal_aix64_internal"
11463 [(set (match_operand 0 "" "")
11464 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
11465 (match_operand 2 "" "g,g")))
11466 (use (mem:DI (plus:DI (match_operand:DI 3 "register_operand" "b,b")
11469 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11470 (clobber (reg:SI LR_REGNO))]
11471 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11473 "&& reload_completed"
11475 (mem:DI (plus:DI (match_dup 3) (const_int 8))))
11476 (parallel [(set (match_dup 0) (call (mem:SI (match_dup 1))
11481 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11482 (clobber (reg:SI LR_REGNO))])]
11484 [(set_attr "type" "jmpreg")
11485 (set_attr "length" "12")])
11487 (define_insn "*call_value_indirect_nonlocal_aix64"
11488 [(set (match_operand 0 "" "")
11489 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
11490 (match_operand 2 "" "g,g")))
11494 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11495 (clobber (reg:SI LR_REGNO))]
11496 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11497 "b%T1l\;ld 2,40(1)"
11498 [(set_attr "type" "jmpreg")
11499 (set_attr "length" "8")])
11501 (define_insn "*call_value_nonlocal_aix64"
11502 [(set (match_operand 0 "" "")
11503 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11504 (match_operand 2 "" "g")))
11505 (use (match_operand:SI 3 "immediate_operand" "O"))
11506 (clobber (reg:SI LR_REGNO))]
11508 && DEFAULT_ABI == ABI_AIX
11509 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11511 [(set_attr "type" "branch")
11512 (set_attr "length" "8")])
11514 ;; A function pointer under System V is just a normal pointer
11515 ;; operands[0] is the function pointer
11516 ;; operands[1] is the stack size to clean up
11517 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
11518 ;; which indicates how to set cr1
11520 (define_insn "*call_indirect_nonlocal_sysv<mode>"
11521 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
11522 (match_operand 1 "" "g,g,g,g"))
11523 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
11524 (clobber (reg:SI LR_REGNO))]
11525 "DEFAULT_ABI == ABI_V4
11526 || DEFAULT_ABI == ABI_DARWIN"
11528 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11529 output_asm_insn ("crxor 6,6,6", operands);
11531 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11532 output_asm_insn ("creqv 6,6,6", operands);
11536 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11537 (set_attr "length" "4,4,8,8")])
11539 (define_insn_and_split "*call_nonlocal_sysv<mode>"
11540 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11541 (match_operand 1 "" "g,g"))
11542 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11543 (clobber (reg:SI LR_REGNO))]
11544 "(DEFAULT_ABI == ABI_DARWIN
11545 || (DEFAULT_ABI == ABI_V4
11546 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
11548 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11549 output_asm_insn ("crxor 6,6,6", operands);
11551 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11552 output_asm_insn ("creqv 6,6,6", operands);
11555 return output_call(insn, operands, 0, 2);
11557 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11559 gcc_assert (!TARGET_SECURE_PLT);
11560 return "bl %z0@plt";
11566 "DEFAULT_ABI == ABI_V4
11567 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11568 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11569 [(parallel [(call (mem:SI (match_dup 0))
11571 (use (match_dup 2))
11572 (use (match_dup 3))
11573 (clobber (reg:SI LR_REGNO))])]
11575 operands[3] = pic_offset_table_rtx;
11577 [(set_attr "type" "branch,branch")
11578 (set_attr "length" "4,8")])
11580 (define_insn "*call_nonlocal_sysv_secure<mode>"
11581 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11582 (match_operand 1 "" "g,g"))
11583 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11584 (use (match_operand:SI 3 "register_operand" "r,r"))
11585 (clobber (reg:SI LR_REGNO))]
11586 "(DEFAULT_ABI == ABI_V4
11587 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11588 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
11590 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11591 output_asm_insn ("crxor 6,6,6", operands);
11593 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11594 output_asm_insn ("creqv 6,6,6", operands);
11597 /* The magic 32768 offset here and in the other sysv call insns
11598 corresponds to the offset of r30 in .got2, as given by LCTOC1.
11599 See sysv4.h:toc_section. */
11600 return "bl %z0+32768@plt";
11602 return "bl %z0@plt";
11604 [(set_attr "type" "branch,branch")
11605 (set_attr "length" "4,8")])
11607 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
11608 [(set (match_operand 0 "" "")
11609 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
11610 (match_operand 2 "" "g,g,g,g")))
11611 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
11612 (clobber (reg:SI LR_REGNO))]
11613 "DEFAULT_ABI == ABI_V4
11614 || DEFAULT_ABI == ABI_DARWIN"
11616 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11617 output_asm_insn ("crxor 6,6,6", operands);
11619 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11620 output_asm_insn ("creqv 6,6,6", operands);
11624 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11625 (set_attr "length" "4,4,8,8")])
11627 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
11628 [(set (match_operand 0 "" "")
11629 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11630 (match_operand 2 "" "g,g")))
11631 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11632 (clobber (reg:SI LR_REGNO))]
11633 "(DEFAULT_ABI == ABI_DARWIN
11634 || (DEFAULT_ABI == ABI_V4
11635 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
11637 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11638 output_asm_insn ("crxor 6,6,6", operands);
11640 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11641 output_asm_insn ("creqv 6,6,6", operands);
11644 return output_call(insn, operands, 1, 3);
11646 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11648 gcc_assert (!TARGET_SECURE_PLT);
11649 return "bl %z1@plt";
11655 "DEFAULT_ABI == ABI_V4
11656 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11657 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11658 [(parallel [(set (match_dup 0)
11659 (call (mem:SI (match_dup 1))
11661 (use (match_dup 3))
11662 (use (match_dup 4))
11663 (clobber (reg:SI LR_REGNO))])]
11665 operands[4] = pic_offset_table_rtx;
11667 [(set_attr "type" "branch,branch")
11668 (set_attr "length" "4,8")])
11670 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
11671 [(set (match_operand 0 "" "")
11672 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11673 (match_operand 2 "" "g,g")))
11674 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11675 (use (match_operand:SI 4 "register_operand" "r,r"))
11676 (clobber (reg:SI LR_REGNO))]
11677 "(DEFAULT_ABI == ABI_V4
11678 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11679 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
11681 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11682 output_asm_insn ("crxor 6,6,6", operands);
11684 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11685 output_asm_insn ("creqv 6,6,6", operands);
11688 return "bl %z1+32768@plt";
11690 return "bl %z1@plt";
11692 [(set_attr "type" "branch,branch")
11693 (set_attr "length" "4,8")])
11695 ;; Call subroutine returning any type.
11696 (define_expand "untyped_call"
11697 [(parallel [(call (match_operand 0 "" "")
11699 (match_operand 1 "" "")
11700 (match_operand 2 "" "")])]
11706 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
11708 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11710 rtx set = XVECEXP (operands[2], 0, i);
11711 emit_move_insn (SET_DEST (set), SET_SRC (set));
11714 /* The optimizer does not know that the call sets the function value
11715 registers we stored in the result block. We avoid problems by
11716 claiming that all hard registers are used and clobbered at this
11718 emit_insn (gen_blockage ());
11723 ;; sibling call patterns
11724 (define_expand "sibcall"
11725 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11726 (match_operand 1 "" ""))
11727 (use (match_operand 2 "" ""))
11728 (use (reg:SI LR_REGNO))
11734 if (MACHOPIC_INDIRECT)
11735 operands[0] = machopic_indirect_call_target (operands[0]);
11738 gcc_assert (GET_CODE (operands[0]) == MEM);
11739 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11741 operands[0] = XEXP (operands[0], 0);
11744 ;; this and similar patterns must be marked as using LR, otherwise
11745 ;; dataflow will try to delete the store into it. This is true
11746 ;; even when the actual reg to jump to is in CTR, when LR was
11747 ;; saved and restored around the PIC-setting BCL.
11748 (define_insn "*sibcall_local32"
11749 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11750 (match_operand 1 "" "g,g"))
11751 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11752 (use (reg:SI LR_REGNO))
11754 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11757 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11758 output_asm_insn (\"crxor 6,6,6\", operands);
11760 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11761 output_asm_insn (\"creqv 6,6,6\", operands);
11763 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11765 [(set_attr "type" "branch")
11766 (set_attr "length" "4,8")])
11768 (define_insn "*sibcall_local64"
11769 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11770 (match_operand 1 "" "g,g"))
11771 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11772 (use (reg:SI LR_REGNO))
11774 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11777 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11778 output_asm_insn (\"crxor 6,6,6\", operands);
11780 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11781 output_asm_insn (\"creqv 6,6,6\", operands);
11783 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11785 [(set_attr "type" "branch")
11786 (set_attr "length" "4,8")])
11788 (define_insn "*sibcall_value_local32"
11789 [(set (match_operand 0 "" "")
11790 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11791 (match_operand 2 "" "g,g")))
11792 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11793 (use (reg:SI LR_REGNO))
11795 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11798 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11799 output_asm_insn (\"crxor 6,6,6\", operands);
11801 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11802 output_asm_insn (\"creqv 6,6,6\", operands);
11804 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11806 [(set_attr "type" "branch")
11807 (set_attr "length" "4,8")])
11810 (define_insn "*sibcall_value_local64"
11811 [(set (match_operand 0 "" "")
11812 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11813 (match_operand 2 "" "g,g")))
11814 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11815 (use (reg:SI LR_REGNO))
11817 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11820 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11821 output_asm_insn (\"crxor 6,6,6\", operands);
11823 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11824 output_asm_insn (\"creqv 6,6,6\", operands);
11826 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11828 [(set_attr "type" "branch")
11829 (set_attr "length" "4,8")])
11831 (define_insn "*sibcall_nonlocal_aix32"
11832 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11833 (match_operand 1 "" "g"))
11834 (use (match_operand:SI 2 "immediate_operand" "O"))
11835 (use (reg:SI LR_REGNO))
11838 && DEFAULT_ABI == ABI_AIX
11839 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11841 [(set_attr "type" "branch")
11842 (set_attr "length" "4")])
11844 (define_insn "*sibcall_nonlocal_aix64"
11845 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11846 (match_operand 1 "" "g"))
11847 (use (match_operand:SI 2 "immediate_operand" "O"))
11848 (use (reg:SI LR_REGNO))
11851 && DEFAULT_ABI == ABI_AIX
11852 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11854 [(set_attr "type" "branch")
11855 (set_attr "length" "4")])
11857 (define_insn "*sibcall_value_nonlocal_aix32"
11858 [(set (match_operand 0 "" "")
11859 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11860 (match_operand 2 "" "g")))
11861 (use (match_operand:SI 3 "immediate_operand" "O"))
11862 (use (reg:SI LR_REGNO))
11865 && DEFAULT_ABI == ABI_AIX
11866 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11868 [(set_attr "type" "branch")
11869 (set_attr "length" "4")])
11871 (define_insn "*sibcall_value_nonlocal_aix64"
11872 [(set (match_operand 0 "" "")
11873 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11874 (match_operand 2 "" "g")))
11875 (use (match_operand:SI 3 "immediate_operand" "O"))
11876 (use (reg:SI LR_REGNO))
11879 && DEFAULT_ABI == ABI_AIX
11880 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11882 [(set_attr "type" "branch")
11883 (set_attr "length" "4")])
11885 (define_insn "*sibcall_nonlocal_sysv<mode>"
11886 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11887 (match_operand 1 "" ""))
11888 (use (match_operand 2 "immediate_operand" "O,n"))
11889 (use (reg:SI LR_REGNO))
11891 "(DEFAULT_ABI == ABI_DARWIN
11892 || DEFAULT_ABI == ABI_V4)
11893 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11896 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11897 output_asm_insn (\"crxor 6,6,6\", operands);
11899 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11900 output_asm_insn (\"creqv 6,6,6\", operands);
11902 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11904 gcc_assert (!TARGET_SECURE_PLT);
11905 return \"b %z0@plt\";
11910 [(set_attr "type" "branch,branch")
11911 (set_attr "length" "4,8")])
11913 (define_expand "sibcall_value"
11914 [(parallel [(set (match_operand 0 "register_operand" "")
11915 (call (mem:SI (match_operand 1 "address_operand" ""))
11916 (match_operand 2 "" "")))
11917 (use (match_operand 3 "" ""))
11918 (use (reg:SI LR_REGNO))
11924 if (MACHOPIC_INDIRECT)
11925 operands[1] = machopic_indirect_call_target (operands[1]);
11928 gcc_assert (GET_CODE (operands[1]) == MEM);
11929 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11931 operands[1] = XEXP (operands[1], 0);
11934 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
11935 [(set (match_operand 0 "" "")
11936 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11937 (match_operand 2 "" "")))
11938 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11939 (use (reg:SI LR_REGNO))
11941 "(DEFAULT_ABI == ABI_DARWIN
11942 || DEFAULT_ABI == ABI_V4)
11943 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11946 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11947 output_asm_insn (\"crxor 6,6,6\", operands);
11949 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11950 output_asm_insn (\"creqv 6,6,6\", operands);
11952 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11954 gcc_assert (!TARGET_SECURE_PLT);
11955 return \"b %z1@plt\";
11960 [(set_attr "type" "branch,branch")
11961 (set_attr "length" "4,8")])
11963 (define_expand "sibcall_epilogue"
11964 [(use (const_int 0))]
11965 "TARGET_SCHED_PROLOG"
11968 rs6000_emit_epilogue (TRUE);
11972 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11973 ;; all of memory. This blocks insns from being moved across this point.
11975 (define_insn "blockage"
11976 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
11980 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
11981 ;; signed & unsigned, and one type of branch.
11983 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11984 ;; insns, and branches.
11986 (define_expand "cbranch<mode>4"
11987 [(use (match_operator 0 "rs6000_cbranch_operator"
11988 [(match_operand:GPR 1 "gpc_reg_operand" "")
11989 (match_operand:GPR 2 "reg_or_short_operand" "")]))
11990 (use (match_operand 3 ""))]
11994 /* Take care of the possibility that operands[2] might be negative but
11995 this might be a logical operation. That insn doesn't exist. */
11996 if (GET_CODE (operands[2]) == CONST_INT
11997 && INTVAL (operands[2]) < 0)
11999 operands[2] = force_reg (<MODE>mode, operands[2]);
12000 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
12001 GET_MODE (operands[0]),
12002 operands[1], operands[2]);
12005 rs6000_emit_cbranch (<MODE>mode, operands);
12009 (define_expand "cbranch<mode>4"
12010 [(use (match_operator 0 "rs6000_cbranch_operator"
12011 [(match_operand:FP 1 "gpc_reg_operand" "")
12012 (match_operand:FP 2 "gpc_reg_operand" "")]))
12013 (use (match_operand 3 ""))]
12017 rs6000_emit_cbranch (<MODE>mode, operands);
12021 (define_expand "cstore<mode>4"
12022 [(use (match_operator 1 "rs6000_cbranch_operator"
12023 [(match_operand:GPR 2 "gpc_reg_operand" "")
12024 (match_operand:GPR 3 "reg_or_short_operand" "")]))
12025 (clobber (match_operand:SI 0 "register_operand"))]
12029 /* Take care of the possibility that operands[3] might be negative but
12030 this might be a logical operation. That insn doesn't exist. */
12031 if (GET_CODE (operands[3]) == CONST_INT
12032 && INTVAL (operands[3]) < 0)
12034 operands[3] = force_reg (<MODE>mode, operands[3]);
12035 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
12036 GET_MODE (operands[1]),
12037 operands[2], operands[3]);
12040 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
12041 For SEQ, likewise, except that comparisons with zero should be done
12042 with an scc insns. However, due to the order that combine see the
12043 resulting insns, we must, in fact, allow SEQ for integers. Fail in
12044 the cases we don't want to handle or are best handled by portable
12046 if (GET_CODE (operands[1]) == NE)
12048 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
12049 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
12050 && operands[3] == const0_rtx)
12052 rs6000_emit_sCOND (<MODE>mode, operands);
12056 (define_expand "cstore<mode>4"
12057 [(use (match_operator 1 "rs6000_cbranch_operator"
12058 [(match_operand:FP 2 "gpc_reg_operand" "")
12059 (match_operand:FP 3 "gpc_reg_operand" "")]))
12060 (clobber (match_operand:SI 0 "register_operand"))]
12064 rs6000_emit_sCOND (<MODE>mode, operands);
12069 (define_expand "stack_protect_set"
12070 [(match_operand 0 "memory_operand" "")
12071 (match_operand 1 "memory_operand" "")]
12074 #ifdef TARGET_THREAD_SSP_OFFSET
12075 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12076 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12077 operands[1] = gen_rtx_MEM (Pmode, addr);
12080 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
12082 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
12086 (define_insn "stack_protect_setsi"
12087 [(set (match_operand:SI 0 "memory_operand" "=m")
12088 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12089 (set (match_scratch:SI 2 "=&r") (const_int 0))]
12091 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
12092 [(set_attr "type" "three")
12093 (set_attr "length" "12")])
12095 (define_insn "stack_protect_setdi"
12096 [(set (match_operand:DI 0 "memory_operand" "=m")
12097 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12098 (set (match_scratch:DI 2 "=&r") (const_int 0))]
12100 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
12101 [(set_attr "type" "three")
12102 (set_attr "length" "12")])
12104 (define_expand "stack_protect_test"
12105 [(match_operand 0 "memory_operand" "")
12106 (match_operand 1 "memory_operand" "")
12107 (match_operand 2 "" "")]
12110 rtx test, op0, op1;
12111 #ifdef TARGET_THREAD_SSP_OFFSET
12112 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12113 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12114 operands[1] = gen_rtx_MEM (Pmode, addr);
12117 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
12118 test = gen_rtx_EQ (VOIDmode, op0, op1);
12119 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
12123 (define_insn "stack_protect_testsi"
12124 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12125 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
12126 (match_operand:SI 2 "memory_operand" "m,m")]
12128 (set (match_scratch:SI 4 "=r,r") (const_int 0))
12129 (clobber (match_scratch:SI 3 "=&r,&r"))]
12132 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
12133 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
12134 [(set_attr "length" "16,20")])
12136 (define_insn "stack_protect_testdi"
12137 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12138 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
12139 (match_operand:DI 2 "memory_operand" "m,m")]
12141 (set (match_scratch:DI 4 "=r,r") (const_int 0))
12142 (clobber (match_scratch:DI 3 "=&r,&r"))]
12145 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
12146 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
12147 [(set_attr "length" "16,20")])
12150 ;; Here are the actual compare insns.
12151 (define_insn "*cmp<mode>_internal1"
12152 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
12153 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
12154 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
12156 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
12157 [(set_attr "type" "cmp")])
12159 ;; If we are comparing a register for equality with a large constant,
12160 ;; we can do this with an XOR followed by a compare. But this is profitable
12161 ;; only if the large constant is only used for the comparison (and in this
12162 ;; case we already have a register to reuse as scratch).
12164 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
12165 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
12168 [(set (match_operand:SI 0 "register_operand")
12169 (match_operand:SI 1 "logical_const_operand" ""))
12170 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
12172 (match_operand:SI 2 "logical_const_operand" "")]))
12173 (set (match_operand:CC 4 "cc_reg_operand" "")
12174 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
12177 (if_then_else (match_operator 6 "equality_operator"
12178 [(match_dup 4) (const_int 0)])
12179 (match_operand 7 "" "")
12180 (match_operand 8 "" "")))]
12181 "peep2_reg_dead_p (3, operands[0])
12182 && peep2_reg_dead_p (4, operands[4])"
12183 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
12184 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
12185 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
12188 /* Get the constant we are comparing against, and see what it looks like
12189 when sign-extended from 16 to 32 bits. Then see what constant we could
12190 XOR with SEXTC to get the sign-extended value. */
12191 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
12193 operands[1], operands[2]);
12194 HOST_WIDE_INT c = INTVAL (cnst);
12195 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
12196 HOST_WIDE_INT xorv = c ^ sextc;
12198 operands[9] = GEN_INT (xorv);
12199 operands[10] = GEN_INT (sextc);
12202 (define_insn "*cmpsi_internal2"
12203 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12204 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12205 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
12207 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
12208 [(set_attr "type" "cmp")])
12210 (define_insn "*cmpdi_internal2"
12211 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12212 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
12213 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
12215 "cmpld%I2 %0,%1,%b2"
12216 [(set_attr "type" "cmp")])
12218 ;; The following two insns don't exist as single insns, but if we provide
12219 ;; them, we can swap an add and compare, which will enable us to overlap more
12220 ;; of the required delay between a compare and branch. We generate code for
12221 ;; them by splitting.
12224 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12225 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
12226 (match_operand:SI 2 "short_cint_operand" "i")))
12227 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12228 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12231 [(set_attr "length" "8")])
12234 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
12235 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12236 (match_operand:SI 2 "u_short_cint_operand" "i")))
12237 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12238 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12241 [(set_attr "length" "8")])
12244 [(set (match_operand:CC 3 "cc_reg_operand" "")
12245 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
12246 (match_operand:SI 2 "short_cint_operand" "")))
12247 (set (match_operand:SI 0 "gpc_reg_operand" "")
12248 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12250 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
12251 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12254 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
12255 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
12256 (match_operand:SI 2 "u_short_cint_operand" "")))
12257 (set (match_operand:SI 0 "gpc_reg_operand" "")
12258 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12260 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
12261 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12263 (define_insn "*cmpsf_internal1"
12264 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12265 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
12266 (match_operand:SF 2 "gpc_reg_operand" "f")))]
12267 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
12269 [(set_attr "type" "fpcompare")])
12271 (define_insn "*cmpdf_internal1"
12272 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12273 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "d")
12274 (match_operand:DF 2 "gpc_reg_operand" "d")))]
12275 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
12277 [(set_attr "type" "fpcompare")])
12279 ;; Only need to compare second words if first words equal
12280 (define_insn "*cmptf_internal1"
12281 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12282 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12283 (match_operand:TF 2 "gpc_reg_operand" "d")))]
12284 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
12285 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12286 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
12287 [(set_attr "type" "fpcompare")
12288 (set_attr "length" "12")])
12290 (define_insn_and_split "*cmptf_internal2"
12291 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12292 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12293 (match_operand:TF 2 "gpc_reg_operand" "d")))
12294 (clobber (match_scratch:DF 3 "=d"))
12295 (clobber (match_scratch:DF 4 "=d"))
12296 (clobber (match_scratch:DF 5 "=d"))
12297 (clobber (match_scratch:DF 6 "=d"))
12298 (clobber (match_scratch:DF 7 "=d"))
12299 (clobber (match_scratch:DF 8 "=d"))
12300 (clobber (match_scratch:DF 9 "=d"))
12301 (clobber (match_scratch:DF 10 "=d"))]
12302 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
12303 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12305 "&& reload_completed"
12306 [(set (match_dup 3) (match_dup 13))
12307 (set (match_dup 4) (match_dup 14))
12308 (set (match_dup 9) (abs:DF (match_dup 5)))
12309 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
12310 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
12311 (label_ref (match_dup 11))
12313 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
12314 (set (pc) (label_ref (match_dup 12)))
12316 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
12317 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
12318 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
12319 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
12322 REAL_VALUE_TYPE rv;
12323 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
12324 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
12326 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
12327 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
12328 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
12329 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
12330 operands[11] = gen_label_rtx ();
12331 operands[12] = gen_label_rtx ();
12333 operands[13] = force_const_mem (DFmode,
12334 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
12335 operands[14] = force_const_mem (DFmode,
12336 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
12340 operands[13] = gen_const_mem (DFmode,
12341 create_TOC_reference (XEXP (operands[13], 0)));
12342 operands[14] = gen_const_mem (DFmode,
12343 create_TOC_reference (XEXP (operands[14], 0)));
12344 set_mem_alias_set (operands[13], get_TOC_alias_set ());
12345 set_mem_alias_set (operands[14], get_TOC_alias_set ());
12349 ;; Now we have the scc insns. We can do some combinations because of the
12350 ;; way the machine works.
12352 ;; Note that this is probably faster if we can put an insn between the
12353 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
12354 ;; cases the insns below which don't use an intermediate CR field will
12355 ;; be used instead.
12357 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12358 (match_operator:SI 1 "scc_comparison_operator"
12359 [(match_operand 2 "cc_reg_operand" "y")
12362 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12363 [(set (attr "type")
12364 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12365 (const_string "mfcrf")
12367 (const_string "mfcr")))
12368 (set_attr "length" "8")])
12370 ;; Same as above, but get the GT bit.
12371 (define_insn "move_from_CR_gt_bit"
12372 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12373 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
12374 "TARGET_HARD_FLOAT && !TARGET_FPRS"
12375 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
12376 [(set_attr "type" "mfcr")
12377 (set_attr "length" "8")])
12379 ;; Same as above, but get the OV/ORDERED bit.
12380 (define_insn "move_from_CR_ov_bit"
12381 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12382 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
12384 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
12385 [(set_attr "type" "mfcr")
12386 (set_attr "length" "8")])
12389 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12390 (match_operator:DI 1 "scc_comparison_operator"
12391 [(match_operand 2 "cc_reg_operand" "y")
12394 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12395 [(set (attr "type")
12396 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12397 (const_string "mfcrf")
12399 (const_string "mfcr")))
12400 (set_attr "length" "8")])
12403 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12404 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12405 [(match_operand 2 "cc_reg_operand" "y,y")
12408 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
12409 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12412 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
12414 [(set_attr "type" "delayed_compare")
12415 (set_attr "length" "8,16")])
12418 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12419 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12420 [(match_operand 2 "cc_reg_operand" "")
12423 (set (match_operand:SI 3 "gpc_reg_operand" "")
12424 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12425 "TARGET_32BIT && reload_completed"
12426 [(set (match_dup 3)
12427 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12429 (compare:CC (match_dup 3)
12434 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12435 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12436 [(match_operand 2 "cc_reg_operand" "y")
12438 (match_operand:SI 3 "const_int_operand" "n")))]
12442 int is_bit = ccr_bit (operands[1], 1);
12443 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12446 if (is_bit >= put_bit)
12447 count = is_bit - put_bit;
12449 count = 32 - (put_bit - is_bit);
12451 operands[4] = GEN_INT (count);
12452 operands[5] = GEN_INT (put_bit);
12454 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
12456 [(set (attr "type")
12457 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12458 (const_string "mfcrf")
12460 (const_string "mfcr")))
12461 (set_attr "length" "8")])
12464 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12466 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12467 [(match_operand 2 "cc_reg_operand" "y,y")
12469 (match_operand:SI 3 "const_int_operand" "n,n"))
12471 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
12472 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12477 int is_bit = ccr_bit (operands[1], 1);
12478 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12481 /* Force split for non-cc0 compare. */
12482 if (which_alternative == 1)
12485 if (is_bit >= put_bit)
12486 count = is_bit - put_bit;
12488 count = 32 - (put_bit - is_bit);
12490 operands[5] = GEN_INT (count);
12491 operands[6] = GEN_INT (put_bit);
12493 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
12495 [(set_attr "type" "delayed_compare")
12496 (set_attr "length" "8,16")])
12499 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12501 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12502 [(match_operand 2 "cc_reg_operand" "")
12504 (match_operand:SI 3 "const_int_operand" ""))
12506 (set (match_operand:SI 4 "gpc_reg_operand" "")
12507 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12510 [(set (match_dup 4)
12511 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12514 (compare:CC (match_dup 4)
12518 ;; There is a 3 cycle delay between consecutive mfcr instructions
12519 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
12522 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12523 (match_operator:SI 1 "scc_comparison_operator"
12524 [(match_operand 2 "cc_reg_operand" "y")
12526 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
12527 (match_operator:SI 4 "scc_comparison_operator"
12528 [(match_operand 5 "cc_reg_operand" "y")
12530 "REGNO (operands[2]) != REGNO (operands[5])"
12531 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
12532 [(set_attr "type" "mfcr")
12533 (set_attr "length" "12")])
12536 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12537 (match_operator:DI 1 "scc_comparison_operator"
12538 [(match_operand 2 "cc_reg_operand" "y")
12540 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12541 (match_operator:DI 4 "scc_comparison_operator"
12542 [(match_operand 5 "cc_reg_operand" "y")
12544 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
12545 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
12546 [(set_attr "type" "mfcr")
12547 (set_attr "length" "12")])
12549 ;; There are some scc insns that can be done directly, without a compare.
12550 ;; These are faster because they don't involve the communications between
12551 ;; the FXU and branch units. In fact, we will be replacing all of the
12552 ;; integer scc insns here or in the portable methods in emit_store_flag.
12554 ;; Also support (neg (scc ..)) since that construct is used to replace
12555 ;; branches, (plus (scc ..) ..) since that construct is common and
12556 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12557 ;; cases where it is no more expensive than (neg (scc ..)).
12559 ;; Have reload force a constant into a register for the simple insns that
12560 ;; otherwise won't accept constants. We do this because it is faster than
12561 ;; the cmp/mfcr sequence we would otherwise generate.
12563 (define_mode_attr scc_eq_op2 [(SI "rKLI")
12566 (define_insn_and_split "*eq<mode>"
12567 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12568 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
12569 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
12573 [(set (match_dup 0)
12574 (clz:GPR (match_dup 3)))
12576 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
12578 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12580 /* Use output operand as intermediate. */
12581 operands[3] = operands[0];
12583 if (logical_operand (operands[2], <MODE>mode))
12584 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12585 gen_rtx_XOR (<MODE>mode,
12586 operands[1], operands[2])));
12588 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12589 gen_rtx_PLUS (<MODE>mode, operands[1],
12590 negate_rtx (<MODE>mode,
12594 operands[3] = operands[1];
12596 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12599 (define_insn_and_split "*eq<mode>_compare"
12600 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12602 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12603 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
12605 (set (match_operand:P 0 "gpc_reg_operand" "=r")
12606 (eq:P (match_dup 1) (match_dup 2)))]
12607 "!TARGET_POWER && optimize_size"
12609 "!TARGET_POWER && optimize_size"
12610 [(set (match_dup 0)
12611 (clz:P (match_dup 4)))
12612 (parallel [(set (match_dup 3)
12613 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
12616 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
12618 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12620 /* Use output operand as intermediate. */
12621 operands[4] = operands[0];
12623 if (logical_operand (operands[2], <MODE>mode))
12624 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12625 gen_rtx_XOR (<MODE>mode,
12626 operands[1], operands[2])));
12628 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12629 gen_rtx_PLUS (<MODE>mode, operands[1],
12630 negate_rtx (<MODE>mode,
12634 operands[4] = operands[1];
12636 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12639 (define_insn "*eqsi_power"
12640 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
12641 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12642 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
12643 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
12646 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12647 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
12648 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12649 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12650 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
12651 [(set_attr "type" "three,two,three,three,three")
12652 (set_attr "length" "12,8,12,12,12")])
12654 ;; We have insns of the form shown by the first define_insn below. If
12655 ;; there is something inside the comparison operation, we must split it.
12657 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12658 (plus:SI (match_operator 1 "comparison_operator"
12659 [(match_operand:SI 2 "" "")
12660 (match_operand:SI 3
12661 "reg_or_cint_operand" "")])
12662 (match_operand:SI 4 "gpc_reg_operand" "")))
12663 (clobber (match_operand:SI 5 "register_operand" ""))]
12664 "! gpc_reg_operand (operands[2], SImode)"
12665 [(set (match_dup 5) (match_dup 2))
12666 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
12669 (define_insn "*plus_eqsi"
12670 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
12671 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12672 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
12673 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
12676 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12677 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
12678 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12679 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12680 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12681 [(set_attr "type" "three,two,three,three,three")
12682 (set_attr "length" "12,8,12,12,12")])
12684 (define_insn "*compare_plus_eqsi"
12685 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12688 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12689 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12690 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12692 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
12693 "TARGET_32BIT && optimize_size"
12695 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12696 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
12697 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12698 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12699 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12705 [(set_attr "type" "compare")
12706 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12709 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12712 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12713 (match_operand:SI 2 "scc_eq_operand" ""))
12714 (match_operand:SI 3 "gpc_reg_operand" ""))
12716 (clobber (match_scratch:SI 4 ""))]
12717 "TARGET_32BIT && optimize_size && reload_completed"
12718 [(set (match_dup 4)
12719 (plus:SI (eq:SI (match_dup 1)
12723 (compare:CC (match_dup 4)
12727 (define_insn "*plus_eqsi_compare"
12728 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12731 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12732 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12733 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12735 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12736 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12737 "TARGET_32BIT && optimize_size"
12739 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12740 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
12741 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12742 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12743 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12749 [(set_attr "type" "compare")
12750 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12753 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12756 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12757 (match_operand:SI 2 "scc_eq_operand" ""))
12758 (match_operand:SI 3 "gpc_reg_operand" ""))
12760 (set (match_operand:SI 0 "gpc_reg_operand" "")
12761 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12762 "TARGET_32BIT && optimize_size && reload_completed"
12763 [(set (match_dup 0)
12764 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12766 (compare:CC (match_dup 0)
12770 (define_insn "*neg_eq0<mode>"
12771 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12772 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12775 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
12776 [(set_attr "type" "two")
12777 (set_attr "length" "8")])
12779 (define_insn_and_split "*neg_eq<mode>"
12780 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12781 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12782 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
12786 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12788 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12790 /* Use output operand as intermediate. */
12791 operands[3] = operands[0];
12793 if (logical_operand (operands[2], <MODE>mode))
12794 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12795 gen_rtx_XOR (<MODE>mode,
12796 operands[1], operands[2])));
12798 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12799 gen_rtx_PLUS (<MODE>mode, operands[1],
12800 negate_rtx (<MODE>mode,
12804 operands[3] = operands[1];
12807 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
12808 ;; since it nabs/sr is just as fast.
12809 (define_insn "*ne0si"
12810 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12811 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12813 (clobber (match_scratch:SI 2 "=&r"))]
12814 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
12815 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
12816 [(set_attr "type" "two")
12817 (set_attr "length" "8")])
12819 (define_insn "*ne0di"
12820 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12821 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12823 (clobber (match_scratch:DI 2 "=&r"))]
12825 "addic %2,%1,-1\;subfe %0,%2,%1"
12826 [(set_attr "type" "two")
12827 (set_attr "length" "8")])
12829 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
12830 (define_insn "*plus_ne0si"
12831 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12832 (plus:SI (lshiftrt:SI
12833 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12835 (match_operand:SI 2 "gpc_reg_operand" "r")))
12836 (clobber (match_scratch:SI 3 "=&r"))]
12838 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
12839 [(set_attr "type" "two")
12840 (set_attr "length" "8")])
12842 (define_insn "*plus_ne0di"
12843 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12844 (plus:DI (lshiftrt:DI
12845 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12847 (match_operand:DI 2 "gpc_reg_operand" "r")))
12848 (clobber (match_scratch:DI 3 "=&r"))]
12850 "addic %3,%1,-1\;addze %0,%2"
12851 [(set_attr "type" "two")
12852 (set_attr "length" "8")])
12854 (define_insn "*compare_plus_ne0si"
12855 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12857 (plus:SI (lshiftrt:SI
12858 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12860 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12862 (clobber (match_scratch:SI 3 "=&r,&r"))
12863 (clobber (match_scratch:SI 4 "=X,&r"))]
12866 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
12868 [(set_attr "type" "compare")
12869 (set_attr "length" "8,12")])
12872 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12874 (plus:SI (lshiftrt:SI
12875 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12877 (match_operand:SI 2 "gpc_reg_operand" ""))
12879 (clobber (match_scratch:SI 3 ""))
12880 (clobber (match_scratch:SI 4 ""))]
12881 "TARGET_32BIT && reload_completed"
12882 [(parallel [(set (match_dup 3)
12883 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
12886 (clobber (match_dup 4))])
12888 (compare:CC (match_dup 3)
12892 (define_insn "*compare_plus_ne0di"
12893 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12895 (plus:DI (lshiftrt:DI
12896 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12898 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12900 (clobber (match_scratch:DI 3 "=&r,&r"))]
12903 addic %3,%1,-1\;addze. %3,%2
12905 [(set_attr "type" "compare")
12906 (set_attr "length" "8,12")])
12909 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12911 (plus:DI (lshiftrt:DI
12912 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12914 (match_operand:DI 2 "gpc_reg_operand" ""))
12916 (clobber (match_scratch:DI 3 ""))]
12917 "TARGET_64BIT && reload_completed"
12918 [(set (match_dup 3)
12919 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12923 (compare:CC (match_dup 3)
12927 (define_insn "*plus_ne0si_compare"
12928 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12930 (plus:SI (lshiftrt:SI
12931 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12933 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12935 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12936 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12938 (clobber (match_scratch:SI 3 "=&r,&r"))]
12941 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
12943 [(set_attr "type" "compare")
12944 (set_attr "length" "8,12")])
12947 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12949 (plus:SI (lshiftrt:SI
12950 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12952 (match_operand:SI 2 "gpc_reg_operand" ""))
12954 (set (match_operand:SI 0 "gpc_reg_operand" "")
12955 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12957 (clobber (match_scratch:SI 3 ""))]
12958 "TARGET_32BIT && reload_completed"
12959 [(parallel [(set (match_dup 0)
12960 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12962 (clobber (match_dup 3))])
12964 (compare:CC (match_dup 0)
12968 (define_insn "*plus_ne0di_compare"
12969 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12971 (plus:DI (lshiftrt:DI
12972 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12974 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12976 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12977 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12979 (clobber (match_scratch:DI 3 "=&r,&r"))]
12982 addic %3,%1,-1\;addze. %0,%2
12984 [(set_attr "type" "compare")
12985 (set_attr "length" "8,12")])
12988 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
12990 (plus:DI (lshiftrt:DI
12991 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12993 (match_operand:DI 2 "gpc_reg_operand" ""))
12995 (set (match_operand:DI 0 "gpc_reg_operand" "")
12996 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12998 (clobber (match_scratch:DI 3 ""))]
12999 "TARGET_64BIT && reload_completed"
13000 [(parallel [(set (match_dup 0)
13001 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
13003 (clobber (match_dup 3))])
13005 (compare:CC (match_dup 0)
13010 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13011 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13012 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
13013 (clobber (match_scratch:SI 3 "=r,X"))]
13016 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
13017 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
13018 [(set_attr "length" "12")])
13021 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13023 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13024 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13026 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
13027 (le:SI (match_dup 1) (match_dup 2)))
13028 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
13031 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13032 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
13035 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
13036 (set_attr "length" "12,12,16,16")])
13039 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13041 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13042 (match_operand:SI 2 "reg_or_short_operand" ""))
13044 (set (match_operand:SI 0 "gpc_reg_operand" "")
13045 (le:SI (match_dup 1) (match_dup 2)))
13046 (clobber (match_scratch:SI 3 ""))]
13047 "TARGET_POWER && reload_completed"
13048 [(parallel [(set (match_dup 0)
13049 (le:SI (match_dup 1) (match_dup 2)))
13050 (clobber (match_dup 3))])
13052 (compare:CC (match_dup 0)
13057 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13058 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13059 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
13060 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
13063 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13064 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
13065 [(set_attr "length" "12")])
13068 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13070 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13071 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13072 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13074 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13077 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13078 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
13081 [(set_attr "type" "compare")
13082 (set_attr "length" "12,12,16,16")])
13085 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13087 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13088 (match_operand:SI 2 "reg_or_short_operand" ""))
13089 (match_operand:SI 3 "gpc_reg_operand" ""))
13091 (clobber (match_scratch:SI 4 ""))]
13092 "TARGET_POWER && reload_completed"
13093 [(set (match_dup 4)
13094 (plus:SI (le:SI (match_dup 1) (match_dup 2))
13097 (compare:CC (match_dup 4)
13102 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13104 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13105 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13106 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13108 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13109 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13112 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13113 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
13116 [(set_attr "type" "compare")
13117 (set_attr "length" "12,12,16,16")])
13120 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13122 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13123 (match_operand:SI 2 "reg_or_short_operand" ""))
13124 (match_operand:SI 3 "gpc_reg_operand" ""))
13126 (set (match_operand:SI 0 "gpc_reg_operand" "")
13127 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13128 "TARGET_POWER && reload_completed"
13129 [(set (match_dup 0)
13130 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13132 (compare:CC (match_dup 0)
13137 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13138 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13139 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
13142 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
13143 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
13144 [(set_attr "length" "12")])
13146 (define_insn "*leu<mode>"
13147 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13148 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13149 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13151 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
13152 [(set_attr "type" "three")
13153 (set_attr "length" "12")])
13155 (define_insn "*leu<mode>_compare"
13156 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13158 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13159 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13161 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13162 (leu:P (match_dup 1) (match_dup 2)))]
13165 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13167 [(set_attr "type" "compare")
13168 (set_attr "length" "12,16")])
13171 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13173 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
13174 (match_operand:P 2 "reg_or_short_operand" ""))
13176 (set (match_operand:P 0 "gpc_reg_operand" "")
13177 (leu:P (match_dup 1) (match_dup 2)))]
13179 [(set (match_dup 0)
13180 (leu:P (match_dup 1) (match_dup 2)))
13182 (compare:CC (match_dup 0)
13186 (define_insn "*plus_leu<mode>"
13187 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13188 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13189 (match_operand:P 2 "reg_or_short_operand" "rI"))
13190 (match_operand:P 3 "gpc_reg_operand" "r")))]
13192 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
13193 [(set_attr "type" "two")
13194 (set_attr "length" "8")])
13197 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13199 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13200 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13201 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13203 (clobber (match_scratch:SI 4 "=&r,&r"))]
13206 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
13208 [(set_attr "type" "compare")
13209 (set_attr "length" "8,12")])
13212 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13214 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13215 (match_operand:SI 2 "reg_or_short_operand" ""))
13216 (match_operand:SI 3 "gpc_reg_operand" ""))
13218 (clobber (match_scratch:SI 4 ""))]
13219 "TARGET_32BIT && reload_completed"
13220 [(set (match_dup 4)
13221 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
13224 (compare:CC (match_dup 4)
13229 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13231 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13232 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13233 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13235 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13236 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13239 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
13241 [(set_attr "type" "compare")
13242 (set_attr "length" "8,12")])
13245 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13247 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13248 (match_operand:SI 2 "reg_or_short_operand" ""))
13249 (match_operand:SI 3 "gpc_reg_operand" ""))
13251 (set (match_operand:SI 0 "gpc_reg_operand" "")
13252 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13253 "TARGET_32BIT && reload_completed"
13254 [(set (match_dup 0)
13255 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13257 (compare:CC (match_dup 0)
13261 (define_insn "*neg_leu<mode>"
13262 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13263 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13264 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13266 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
13267 [(set_attr "type" "three")
13268 (set_attr "length" "12")])
13270 (define_insn "*and_neg_leu<mode>"
13271 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13273 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13274 (match_operand:P 2 "reg_or_short_operand" "rI")))
13275 (match_operand:P 3 "gpc_reg_operand" "r")))]
13277 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13278 [(set_attr "type" "three")
13279 (set_attr "length" "12")])
13282 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13285 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13286 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13287 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13289 (clobber (match_scratch:SI 4 "=&r,&r"))]
13292 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13294 [(set_attr "type" "compare")
13295 (set_attr "length" "12,16")])
13298 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13301 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13302 (match_operand:SI 2 "reg_or_short_operand" "")))
13303 (match_operand:SI 3 "gpc_reg_operand" ""))
13305 (clobber (match_scratch:SI 4 ""))]
13306 "TARGET_32BIT && reload_completed"
13307 [(set (match_dup 4)
13308 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13311 (compare:CC (match_dup 4)
13316 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13319 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13320 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13321 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13323 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13324 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13327 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13329 [(set_attr "type" "compare")
13330 (set_attr "length" "12,16")])
13333 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13336 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13337 (match_operand:SI 2 "reg_or_short_operand" "")))
13338 (match_operand:SI 3 "gpc_reg_operand" ""))
13340 (set (match_operand:SI 0 "gpc_reg_operand" "")
13341 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13342 "TARGET_32BIT && reload_completed"
13343 [(set (match_dup 0)
13344 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13347 (compare:CC (match_dup 0)
13352 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13353 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13354 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13356 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13357 [(set_attr "length" "12")])
13360 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13362 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13363 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13365 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13366 (lt:SI (match_dup 1) (match_dup 2)))]
13369 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13371 [(set_attr "type" "delayed_compare")
13372 (set_attr "length" "12,16")])
13375 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13377 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13378 (match_operand:SI 2 "reg_or_short_operand" ""))
13380 (set (match_operand:SI 0 "gpc_reg_operand" "")
13381 (lt:SI (match_dup 1) (match_dup 2)))]
13382 "TARGET_POWER && reload_completed"
13383 [(set (match_dup 0)
13384 (lt:SI (match_dup 1) (match_dup 2)))
13386 (compare:CC (match_dup 0)
13391 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13392 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13393 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13394 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13396 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13397 [(set_attr "length" "12")])
13400 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13402 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13403 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13404 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13406 (clobber (match_scratch:SI 4 "=&r,&r"))]
13409 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13411 [(set_attr "type" "compare")
13412 (set_attr "length" "12,16")])
13415 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13417 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13418 (match_operand:SI 2 "reg_or_short_operand" ""))
13419 (match_operand:SI 3 "gpc_reg_operand" ""))
13421 (clobber (match_scratch:SI 4 ""))]
13422 "TARGET_POWER && reload_completed"
13423 [(set (match_dup 4)
13424 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
13427 (compare:CC (match_dup 4)
13432 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13434 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13435 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13436 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13438 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13439 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13442 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13444 [(set_attr "type" "compare")
13445 (set_attr "length" "12,16")])
13448 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13450 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13451 (match_operand:SI 2 "reg_or_short_operand" ""))
13452 (match_operand:SI 3 "gpc_reg_operand" ""))
13454 (set (match_operand:SI 0 "gpc_reg_operand" "")
13455 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13456 "TARGET_POWER && reload_completed"
13457 [(set (match_dup 0)
13458 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13460 (compare:CC (match_dup 0)
13465 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13466 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13467 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13469 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13470 [(set_attr "length" "12")])
13472 (define_insn_and_split "*ltu<mode>"
13473 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13474 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13475 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13479 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13480 (set (match_dup 0) (neg:P (match_dup 0)))]
13483 (define_insn_and_split "*ltu<mode>_compare"
13484 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13486 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13487 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13489 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13490 (ltu:P (match_dup 1) (match_dup 2)))]
13494 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13495 (parallel [(set (match_dup 3)
13496 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13497 (set (match_dup 0) (neg:P (match_dup 0)))])]
13500 (define_insn_and_split "*plus_ltu<mode>"
13501 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
13502 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13503 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13504 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
13507 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13508 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13509 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13512 (define_insn_and_split "*plus_ltu<mode>_compare"
13513 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13515 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13516 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13517 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13519 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13520 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13523 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13524 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13525 (parallel [(set (match_dup 4)
13526 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13528 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13531 (define_insn "*neg_ltu<mode>"
13532 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13533 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13534 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
13537 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
13538 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
13539 [(set_attr "type" "two")
13540 (set_attr "length" "8")])
13543 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13544 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13545 (match_operand:SI 2 "reg_or_short_operand" "rI")))
13546 (clobber (match_scratch:SI 3 "=r"))]
13548 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
13549 [(set_attr "length" "12")])
13552 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13554 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13555 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13557 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13558 (ge:SI (match_dup 1) (match_dup 2)))
13559 (clobber (match_scratch:SI 3 "=r,r"))]
13562 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13564 [(set_attr "type" "compare")
13565 (set_attr "length" "12,16")])
13568 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13570 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13571 (match_operand:SI 2 "reg_or_short_operand" ""))
13573 (set (match_operand:SI 0 "gpc_reg_operand" "")
13574 (ge:SI (match_dup 1) (match_dup 2)))
13575 (clobber (match_scratch:SI 3 ""))]
13576 "TARGET_POWER && reload_completed"
13577 [(parallel [(set (match_dup 0)
13578 (ge:SI (match_dup 1) (match_dup 2)))
13579 (clobber (match_dup 3))])
13581 (compare:CC (match_dup 0)
13586 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13587 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13588 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13589 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13591 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
13592 [(set_attr "length" "12")])
13595 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13597 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13598 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13599 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13601 (clobber (match_scratch:SI 4 "=&r,&r"))]
13604 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13606 [(set_attr "type" "compare")
13607 (set_attr "length" "12,16")])
13610 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13612 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13613 (match_operand:SI 2 "reg_or_short_operand" ""))
13614 (match_operand:SI 3 "gpc_reg_operand" ""))
13616 (clobber (match_scratch:SI 4 ""))]
13617 "TARGET_POWER && reload_completed"
13618 [(set (match_dup 4)
13619 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
13622 (compare:CC (match_dup 4)
13627 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13629 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13630 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13631 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13633 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13634 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13637 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13639 [(set_attr "type" "compare")
13640 (set_attr "length" "12,16")])
13643 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13645 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13646 (match_operand:SI 2 "reg_or_short_operand" ""))
13647 (match_operand:SI 3 "gpc_reg_operand" ""))
13649 (set (match_operand:SI 0 "gpc_reg_operand" "")
13650 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13651 "TARGET_POWER && reload_completed"
13652 [(set (match_dup 0)
13653 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13655 (compare:CC (match_dup 0)
13660 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13661 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13662 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13664 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
13665 [(set_attr "length" "12")])
13667 (define_insn "*geu<mode>"
13668 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13669 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13670 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13673 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
13674 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
13675 [(set_attr "type" "three")
13676 (set_attr "length" "12")])
13678 (define_insn "*geu<mode>_compare"
13679 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13681 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13682 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13684 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13685 (geu:P (match_dup 1) (match_dup 2)))]
13688 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13689 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13692 [(set_attr "type" "compare")
13693 (set_attr "length" "12,12,16,16")])
13696 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
13698 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
13699 (match_operand:P 2 "reg_or_neg_short_operand" ""))
13701 (set (match_operand:P 0 "gpc_reg_operand" "")
13702 (geu:P (match_dup 1) (match_dup 2)))]
13704 [(set (match_dup 0)
13705 (geu:P (match_dup 1) (match_dup 2)))
13707 (compare:CC (match_dup 0)
13711 (define_insn "*plus_geu<mode>"
13712 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13713 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13714 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13715 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13718 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
13719 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
13720 [(set_attr "type" "two")
13721 (set_attr "length" "8")])
13724 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13726 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13727 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13728 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13730 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13733 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
13734 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
13737 [(set_attr "type" "compare")
13738 (set_attr "length" "8,8,12,12")])
13741 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13743 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13744 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13745 (match_operand:SI 3 "gpc_reg_operand" ""))
13747 (clobber (match_scratch:SI 4 ""))]
13748 "TARGET_32BIT && reload_completed"
13749 [(set (match_dup 4)
13750 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13753 (compare:CC (match_dup 4)
13758 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13760 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13761 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13762 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13764 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13765 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13768 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
13769 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
13772 [(set_attr "type" "compare")
13773 (set_attr "length" "8,8,12,12")])
13776 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13778 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13779 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13780 (match_operand:SI 3 "gpc_reg_operand" ""))
13782 (set (match_operand:SI 0 "gpc_reg_operand" "")
13783 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13784 "TARGET_32BIT && reload_completed"
13785 [(set (match_dup 0)
13786 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13788 (compare:CC (match_dup 0)
13792 (define_insn "*neg_geu<mode>"
13793 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13794 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13795 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13798 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
13799 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
13800 [(set_attr "type" "three")
13801 (set_attr "length" "12")])
13803 (define_insn "*and_neg_geu<mode>"
13804 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13806 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13807 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13808 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13811 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
13812 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13813 [(set_attr "type" "three")
13814 (set_attr "length" "12")])
13817 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13820 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13821 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13822 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13824 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13827 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13828 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13831 [(set_attr "type" "compare")
13832 (set_attr "length" "12,12,16,16")])
13835 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13838 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13839 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13840 (match_operand:SI 3 "gpc_reg_operand" ""))
13842 (clobber (match_scratch:SI 4 ""))]
13843 "TARGET_32BIT && reload_completed"
13844 [(set (match_dup 4)
13845 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13848 (compare:CC (match_dup 4)
13853 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13856 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13857 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13858 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13860 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13861 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13864 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13865 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13868 [(set_attr "type" "compare")
13869 (set_attr "length" "12,12,16,16")])
13872 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13875 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13876 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13877 (match_operand:SI 3 "gpc_reg_operand" ""))
13879 (set (match_operand:SI 0 "gpc_reg_operand" "")
13880 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13881 "TARGET_32BIT && reload_completed"
13882 [(set (match_dup 0)
13883 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13885 (compare:CC (match_dup 0)
13890 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13891 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13892 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13894 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13895 [(set_attr "length" "12")])
13898 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13900 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13901 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13903 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13904 (gt:SI (match_dup 1) (match_dup 2)))]
13907 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13909 [(set_attr "type" "delayed_compare")
13910 (set_attr "length" "12,16")])
13913 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13915 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13916 (match_operand:SI 2 "reg_or_short_operand" ""))
13918 (set (match_operand:SI 0 "gpc_reg_operand" "")
13919 (gt:SI (match_dup 1) (match_dup 2)))]
13920 "TARGET_POWER && reload_completed"
13921 [(set (match_dup 0)
13922 (gt:SI (match_dup 1) (match_dup 2)))
13924 (compare:CC (match_dup 0)
13928 (define_insn "*plus_gt0<mode>"
13929 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13930 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13932 (match_operand:P 2 "gpc_reg_operand" "r")))]
13934 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13935 [(set_attr "type" "three")
13936 (set_attr "length" "12")])
13939 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13941 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13943 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13945 (clobber (match_scratch:SI 3 "=&r,&r"))]
13948 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13950 [(set_attr "type" "compare")
13951 (set_attr "length" "12,16")])
13954 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13956 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13958 (match_operand:SI 2 "gpc_reg_operand" ""))
13960 (clobber (match_scratch:SI 3 ""))]
13961 "TARGET_32BIT && reload_completed"
13962 [(set (match_dup 3)
13963 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13966 (compare:CC (match_dup 3)
13971 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13973 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13975 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13977 (clobber (match_scratch:DI 3 "=&r,&r"))]
13980 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13982 [(set_attr "type" "compare")
13983 (set_attr "length" "12,16")])
13986 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13988 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13990 (match_operand:DI 2 "gpc_reg_operand" ""))
13992 (clobber (match_scratch:DI 3 ""))]
13993 "TARGET_64BIT && reload_completed"
13994 [(set (match_dup 3)
13995 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13998 (compare:CC (match_dup 3)
14003 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14005 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14007 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14009 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14010 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
14013 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
14015 [(set_attr "type" "compare")
14016 (set_attr "length" "12,16")])
14019 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14021 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14023 (match_operand:SI 2 "gpc_reg_operand" ""))
14025 (set (match_operand:SI 0 "gpc_reg_operand" "")
14026 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
14027 "TARGET_32BIT && reload_completed"
14028 [(set (match_dup 0)
14029 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
14031 (compare:CC (match_dup 0)
14036 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14038 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
14040 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14042 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
14043 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
14046 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
14048 [(set_attr "type" "compare")
14049 (set_attr "length" "12,16")])
14052 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14054 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
14056 (match_operand:DI 2 "gpc_reg_operand" ""))
14058 (set (match_operand:DI 0 "gpc_reg_operand" "")
14059 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
14060 "TARGET_64BIT && reload_completed"
14061 [(set (match_dup 0)
14062 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
14064 (compare:CC (match_dup 0)
14069 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
14070 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14071 (match_operand:SI 2 "reg_or_short_operand" "r"))
14072 (match_operand:SI 3 "gpc_reg_operand" "r")))]
14074 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
14075 [(set_attr "length" "12")])
14078 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14080 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14081 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14082 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14084 (clobber (match_scratch:SI 4 "=&r,&r"))]
14087 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
14089 [(set_attr "type" "compare")
14090 (set_attr "length" "12,16")])
14093 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14095 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14096 (match_operand:SI 2 "reg_or_short_operand" ""))
14097 (match_operand:SI 3 "gpc_reg_operand" ""))
14099 (clobber (match_scratch:SI 4 ""))]
14100 "TARGET_POWER && reload_completed"
14101 [(set (match_dup 4)
14102 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14104 (compare:CC (match_dup 4)
14109 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14111 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14112 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14113 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14115 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14116 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14119 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
14121 [(set_attr "type" "compare")
14122 (set_attr "length" "12,16")])
14125 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14127 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14128 (match_operand:SI 2 "reg_or_short_operand" ""))
14129 (match_operand:SI 3 "gpc_reg_operand" ""))
14131 (set (match_operand:SI 0 "gpc_reg_operand" "")
14132 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14133 "TARGET_POWER && reload_completed"
14134 [(set (match_dup 0)
14135 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14137 (compare:CC (match_dup 0)
14142 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14143 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14144 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
14146 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
14147 [(set_attr "length" "12")])
14149 (define_insn_and_split "*gtu<mode>"
14150 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14151 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14152 (match_operand:P 2 "reg_or_short_operand" "rI")))]
14156 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14157 (set (match_dup 0) (neg:P (match_dup 0)))]
14160 (define_insn_and_split "*gtu<mode>_compare"
14161 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14163 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14164 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
14166 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14167 (gtu:P (match_dup 1) (match_dup 2)))]
14171 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14172 (parallel [(set (match_dup 3)
14173 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
14174 (set (match_dup 0) (neg:P (match_dup 0)))])]
14177 (define_insn_and_split "*plus_gtu<mode>"
14178 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14179 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14180 (match_operand:P 2 "reg_or_short_operand" "rI"))
14181 (match_operand:P 3 "reg_or_short_operand" "rI")))]
14184 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14185 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14186 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
14189 (define_insn_and_split "*plus_gtu<mode>_compare"
14190 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14192 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14193 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
14194 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14196 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14197 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14200 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14201 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14202 (parallel [(set (match_dup 4)
14203 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14205 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14208 (define_insn "*neg_gtu<mode>"
14209 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14210 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14211 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
14213 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
14214 [(set_attr "type" "two")
14215 (set_attr "length" "8")])
14218 ;; Define both directions of branch and return. If we need a reload
14219 ;; register, we'd rather use CR0 since it is much easier to copy a
14220 ;; register CC value to there.
14224 (if_then_else (match_operator 1 "branch_comparison_operator"
14226 "cc_reg_operand" "y")
14228 (label_ref (match_operand 0 "" ""))
14233 return output_cbranch (operands[1], \"%l0\", 0, insn);
14235 [(set_attr "type" "branch")])
14239 (if_then_else (match_operator 0 "branch_comparison_operator"
14241 "cc_reg_operand" "y")
14248 return output_cbranch (operands[0], NULL, 0, insn);
14250 [(set_attr "type" "jmpreg")
14251 (set_attr "length" "4")])
14255 (if_then_else (match_operator 1 "branch_comparison_operator"
14257 "cc_reg_operand" "y")
14260 (label_ref (match_operand 0 "" ""))))]
14264 return output_cbranch (operands[1], \"%l0\", 1, insn);
14266 [(set_attr "type" "branch")])
14270 (if_then_else (match_operator 0 "branch_comparison_operator"
14272 "cc_reg_operand" "y")
14279 return output_cbranch (operands[0], NULL, 1, insn);
14281 [(set_attr "type" "jmpreg")
14282 (set_attr "length" "4")])
14284 ;; Logic on condition register values.
14286 ; This pattern matches things like
14287 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
14288 ; (eq:SI (reg:CCFP 68) (const_int 0)))
14290 ; which are generated by the branch logic.
14291 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
14293 (define_insn "*cceq_ior_compare"
14294 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14295 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
14296 [(match_operator:SI 2
14297 "branch_positive_comparison_operator"
14299 "cc_reg_operand" "y,y")
14301 (match_operator:SI 4
14302 "branch_positive_comparison_operator"
14304 "cc_reg_operand" "0,y")
14308 "cr%q1 %E0,%j2,%j4"
14309 [(set_attr "type" "cr_logical,delayed_cr")])
14311 ; Why is the constant -1 here, but 1 in the previous pattern?
14312 ; Because ~1 has all but the low bit set.
14314 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14315 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
14316 [(not:SI (match_operator:SI 2
14317 "branch_positive_comparison_operator"
14319 "cc_reg_operand" "y,y")
14321 (match_operator:SI 4
14322 "branch_positive_comparison_operator"
14324 "cc_reg_operand" "0,y")
14328 "cr%q1 %E0,%j2,%j4"
14329 [(set_attr "type" "cr_logical,delayed_cr")])
14331 (define_insn "*cceq_rev_compare"
14332 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14333 (compare:CCEQ (match_operator:SI 1
14334 "branch_positive_comparison_operator"
14336 "cc_reg_operand" "0,y")
14340 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
14341 [(set_attr "type" "cr_logical,delayed_cr")])
14343 ;; If we are comparing the result of two comparisons, this can be done
14344 ;; using creqv or crxor.
14346 (define_insn_and_split ""
14347 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14348 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
14349 [(match_operand 2 "cc_reg_operand" "y")
14351 (match_operator 3 "branch_comparison_operator"
14352 [(match_operand 4 "cc_reg_operand" "y")
14357 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14361 int positive_1, positive_2;
14363 positive_1 = branch_positive_comparison_operator (operands[1],
14364 GET_MODE (operands[1]));
14365 positive_2 = branch_positive_comparison_operator (operands[3],
14366 GET_MODE (operands[3]));
14369 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
14370 GET_CODE (operands[1])),
14372 operands[2], const0_rtx);
14373 else if (GET_MODE (operands[1]) != SImode)
14374 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14375 operands[2], const0_rtx);
14378 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
14379 GET_CODE (operands[3])),
14381 operands[4], const0_rtx);
14382 else if (GET_MODE (operands[3]) != SImode)
14383 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14384 operands[4], const0_rtx);
14386 if (positive_1 == positive_2)
14388 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14389 operands[5] = constm1_rtx;
14393 operands[5] = const1_rtx;
14397 ;; Unconditional branch and return.
14399 (define_insn "jump"
14401 (label_ref (match_operand 0 "" "")))]
14404 [(set_attr "type" "branch")])
14406 (define_insn "return"
14410 [(set_attr "type" "jmpreg")])
14412 (define_expand "indirect_jump"
14413 [(set (pc) (match_operand 0 "register_operand" ""))])
14415 (define_insn "*indirect_jump<mode>"
14416 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14421 [(set_attr "type" "jmpreg")])
14423 ;; Table jump for switch statements:
14424 (define_expand "tablejump"
14425 [(use (match_operand 0 "" ""))
14426 (use (label_ref (match_operand 1 "" "")))]
14431 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14433 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14437 (define_expand "tablejumpsi"
14438 [(set (match_dup 3)
14439 (plus:SI (match_operand:SI 0 "" "")
14441 (parallel [(set (pc) (match_dup 3))
14442 (use (label_ref (match_operand 1 "" "")))])]
14445 { operands[0] = force_reg (SImode, operands[0]);
14446 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
14447 operands[3] = gen_reg_rtx (SImode);
14450 (define_expand "tablejumpdi"
14451 [(set (match_dup 4)
14452 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
14454 (plus:DI (match_dup 4)
14456 (parallel [(set (pc) (match_dup 3))
14457 (use (label_ref (match_operand 1 "" "")))])]
14460 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
14461 operands[3] = gen_reg_rtx (DImode);
14462 operands[4] = gen_reg_rtx (DImode);
14465 (define_insn "*tablejump<mode>_internal1"
14467 (match_operand:P 0 "register_operand" "c,*l"))
14468 (use (label_ref (match_operand 1 "" "")))]
14473 [(set_attr "type" "jmpreg")])
14478 "{cror 0,0,0|nop}")
14480 ;; Define the subtract-one-and-jump insns, starting with the template
14481 ;; so loop.c knows what to generate.
14483 (define_expand "doloop_end"
14484 [(use (match_operand 0 "" "")) ; loop pseudo
14485 (use (match_operand 1 "" "")) ; iterations; zero if unknown
14486 (use (match_operand 2 "" "")) ; max iterations
14487 (use (match_operand 3 "" "")) ; loop level
14488 (use (match_operand 4 "" ""))] ; label
14492 /* Only use this on innermost loops. */
14493 if (INTVAL (operands[3]) > 1)
14497 if (GET_MODE (operands[0]) != DImode)
14499 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
14503 if (GET_MODE (operands[0]) != SImode)
14505 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
14510 (define_expand "ctr<mode>"
14511 [(parallel [(set (pc)
14512 (if_then_else (ne (match_operand:P 0 "register_operand" "")
14514 (label_ref (match_operand 1 "" ""))
14517 (plus:P (match_dup 0)
14519 (clobber (match_scratch:CC 2 ""))
14520 (clobber (match_scratch:P 3 ""))])]
14524 ;; We need to be able to do this for any operand, including MEM, or we
14525 ;; will cause reload to blow up since we don't allow output reloads on
14527 ;; For the length attribute to be calculated correctly, the
14528 ;; label MUST be operand 0.
14530 (define_insn "*ctr<mode>_internal1"
14532 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14534 (label_ref (match_operand 0 "" ""))
14536 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14537 (plus:P (match_dup 1)
14539 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14540 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14544 if (which_alternative != 0)
14546 else if (get_attr_length (insn) == 4)
14547 return \"{bdn|bdnz} %l0\";
14549 return \"bdz $+8\;b %l0\";
14551 [(set_attr "type" "branch")
14552 (set_attr "length" "*,12,16,16")])
14554 (define_insn "*ctr<mode>_internal2"
14556 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14559 (label_ref (match_operand 0 "" ""))))
14560 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14561 (plus:P (match_dup 1)
14563 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14564 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14568 if (which_alternative != 0)
14570 else if (get_attr_length (insn) == 4)
14571 return \"bdz %l0\";
14573 return \"{bdn|bdnz} $+8\;b %l0\";
14575 [(set_attr "type" "branch")
14576 (set_attr "length" "*,12,16,16")])
14578 ;; Similar but use EQ
14580 (define_insn "*ctr<mode>_internal5"
14582 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14584 (label_ref (match_operand 0 "" ""))
14586 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14587 (plus:P (match_dup 1)
14589 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14590 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14594 if (which_alternative != 0)
14596 else if (get_attr_length (insn) == 4)
14597 return \"bdz %l0\";
14599 return \"{bdn|bdnz} $+8\;b %l0\";
14601 [(set_attr "type" "branch")
14602 (set_attr "length" "*,12,16,16")])
14604 (define_insn "*ctr<mode>_internal6"
14606 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14609 (label_ref (match_operand 0 "" ""))))
14610 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14611 (plus:P (match_dup 1)
14613 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14614 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14618 if (which_alternative != 0)
14620 else if (get_attr_length (insn) == 4)
14621 return \"{bdn|bdnz} %l0\";
14623 return \"bdz $+8\;b %l0\";
14625 [(set_attr "type" "branch")
14626 (set_attr "length" "*,12,16,16")])
14628 ;; Now the splitters if we could not allocate the CTR register
14632 (if_then_else (match_operator 2 "comparison_operator"
14633 [(match_operand:P 1 "gpc_reg_operand" "")
14635 (match_operand 5 "" "")
14636 (match_operand 6 "" "")))
14637 (set (match_operand:P 0 "gpc_reg_operand" "")
14638 (plus:P (match_dup 1) (const_int -1)))
14639 (clobber (match_scratch:CC 3 ""))
14640 (clobber (match_scratch:P 4 ""))]
14642 [(parallel [(set (match_dup 3)
14643 (compare:CC (plus:P (match_dup 1)
14647 (plus:P (match_dup 1)
14649 (set (pc) (if_then_else (match_dup 7)
14653 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14654 operands[3], const0_rtx); }")
14658 (if_then_else (match_operator 2 "comparison_operator"
14659 [(match_operand:P 1 "gpc_reg_operand" "")
14661 (match_operand 5 "" "")
14662 (match_operand 6 "" "")))
14663 (set (match_operand:P 0 "nonimmediate_operand" "")
14664 (plus:P (match_dup 1) (const_int -1)))
14665 (clobber (match_scratch:CC 3 ""))
14666 (clobber (match_scratch:P 4 ""))]
14667 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
14668 [(parallel [(set (match_dup 3)
14669 (compare:CC (plus:P (match_dup 1)
14673 (plus:P (match_dup 1)
14677 (set (pc) (if_then_else (match_dup 7)
14681 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14682 operands[3], const0_rtx); }")
14684 (define_insn "trap"
14685 [(trap_if (const_int 1) (const_int 0))]
14688 [(set_attr "type" "trap")])
14690 (define_expand "ctrap<mode>4"
14691 [(trap_if (match_operator 0 "ordered_comparison_operator"
14692 [(match_operand:GPR 1 "register_operand")
14693 (match_operand:GPR 2 "reg_or_short_operand")])
14694 (match_operand 3 "zero_constant" ""))]
14699 [(trap_if (match_operator 0 "ordered_comparison_operator"
14700 [(match_operand:GPR 1 "register_operand" "r")
14701 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
14704 "{t|t<wd>}%V0%I2 %1,%2"
14705 [(set_attr "type" "trap")])
14707 ;; Insns related to generating the function prologue and epilogue.
14709 (define_expand "prologue"
14710 [(use (const_int 0))]
14711 "TARGET_SCHED_PROLOG"
14714 rs6000_emit_prologue ();
14718 (define_insn "*movesi_from_cr_one"
14719 [(match_parallel 0 "mfcr_operation"
14720 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14721 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14722 (match_operand 3 "immediate_operand" "n")]
14723 UNSPEC_MOVESI_FROM_CR))])]
14729 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14731 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14732 operands[4] = GEN_INT (mask);
14733 output_asm_insn (\"mfcr %1,%4\", operands);
14737 [(set_attr "type" "mfcrf")])
14739 (define_insn "movesi_from_cr"
14740 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14741 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
14742 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
14743 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
14744 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
14745 UNSPEC_MOVESI_FROM_CR))]
14748 [(set_attr "type" "mfcr")])
14750 (define_insn "*stmw"
14751 [(match_parallel 0 "stmw_operation"
14752 [(set (match_operand:SI 1 "memory_operand" "=m")
14753 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14756 [(set_attr "type" "store_ux")])
14758 (define_insn "*save_gpregs_<mode>"
14759 [(match_parallel 0 "any_parallel_operand"
14760 [(clobber (reg:P 65))
14761 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14762 (use (match_operand:P 2 "gpc_reg_operand" "r"))
14763 (set (match_operand:P 3 "memory_operand" "=m")
14764 (match_operand:P 4 "gpc_reg_operand" "r"))])]
14767 [(set_attr "type" "branch")
14768 (set_attr "length" "4")])
14770 (define_insn "*save_fpregs_<mode>"
14771 [(match_parallel 0 "any_parallel_operand"
14772 [(clobber (reg:P 65))
14773 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14774 (use (match_operand:P 2 "gpc_reg_operand" "r"))
14775 (set (match_operand:DF 3 "memory_operand" "=m")
14776 (match_operand:DF 4 "gpc_reg_operand" "d"))])]
14779 [(set_attr "type" "branch")
14780 (set_attr "length" "4")])
14782 ; These are to explain that changes to the stack pointer should
14783 ; not be moved over stores to stack memory.
14784 (define_insn "stack_tie"
14785 [(set (match_operand:BLK 0 "memory_operand" "+m")
14786 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
14789 [(set_attr "length" "0")])
14792 (define_expand "epilogue"
14793 [(use (const_int 0))]
14794 "TARGET_SCHED_PROLOG"
14797 rs6000_emit_epilogue (FALSE);
14801 ; On some processors, doing the mtcrf one CC register at a time is
14802 ; faster (like on the 604e). On others, doing them all at once is
14803 ; faster; for instance, on the 601 and 750.
14805 (define_expand "movsi_to_cr_one"
14806 [(set (match_operand:CC 0 "cc_reg_operand" "")
14807 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
14808 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14810 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14812 (define_insn "*movsi_to_cr"
14813 [(match_parallel 0 "mtcrf_operation"
14814 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14815 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14816 (match_operand 3 "immediate_operand" "n")]
14817 UNSPEC_MOVESI_TO_CR))])]
14823 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14824 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14825 operands[4] = GEN_INT (mask);
14826 return \"mtcrf %4,%2\";
14828 [(set_attr "type" "mtcr")])
14830 (define_insn "*mtcrfsi"
14831 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14832 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14833 (match_operand 2 "immediate_operand" "n")]
14834 UNSPEC_MOVESI_TO_CR))]
14835 "GET_CODE (operands[0]) == REG
14836 && CR_REGNO_P (REGNO (operands[0]))
14837 && GET_CODE (operands[2]) == CONST_INT
14838 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14840 [(set_attr "type" "mtcr")])
14842 ; The load-multiple instructions have similar properties.
14843 ; Note that "load_multiple" is a name known to the machine-independent
14844 ; code that actually corresponds to the PowerPC load-string.
14846 (define_insn "*lmw"
14847 [(match_parallel 0 "lmw_operation"
14848 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14849 (match_operand:SI 2 "memory_operand" "m"))])]
14852 [(set_attr "type" "load_ux")
14853 (set_attr "cell_micro" "always")])
14855 (define_insn "*return_internal_<mode>"
14857 (use (match_operand:P 0 "register_operand" "lc"))]
14860 [(set_attr "type" "jmpreg")])
14862 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14863 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14865 (define_insn "*restore_gpregs_<mode>"
14866 [(match_parallel 0 "any_parallel_operand"
14867 [(clobber (match_operand:P 1 "register_operand" "=l"))
14868 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14869 (use (match_operand:P 3 "gpc_reg_operand" "r"))
14870 (set (match_operand:P 4 "gpc_reg_operand" "=r")
14871 (match_operand:P 5 "memory_operand" "m"))])]
14874 [(set_attr "type" "branch")
14875 (set_attr "length" "4")])
14877 (define_insn "*return_and_restore_gpregs_<mode>"
14878 [(match_parallel 0 "any_parallel_operand"
14880 (clobber (match_operand:P 1 "register_operand" "=l"))
14881 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14882 (use (match_operand:P 3 "gpc_reg_operand" "r"))
14883 (set (match_operand:P 4 "gpc_reg_operand" "=r")
14884 (match_operand:P 5 "memory_operand" "m"))])]
14887 [(set_attr "type" "branch")
14888 (set_attr "length" "4")])
14890 (define_insn "*return_and_restore_fpregs_<mode>"
14891 [(match_parallel 0 "any_parallel_operand"
14893 (clobber (match_operand:P 1 "register_operand" "=l"))
14894 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14895 (use (match_operand:P 3 "gpc_reg_operand" "r"))
14896 (set (match_operand:DF 4 "gpc_reg_operand" "=d")
14897 (match_operand:DF 5 "memory_operand" "m"))])]
14900 [(set_attr "type" "branch")
14901 (set_attr "length" "4")])
14903 ; This is used in compiling the unwind routines.
14904 (define_expand "eh_return"
14905 [(use (match_operand 0 "general_operand" ""))]
14910 emit_insn (gen_eh_set_lr_si (operands[0]));
14912 emit_insn (gen_eh_set_lr_di (operands[0]));
14916 ; We can't expand this before we know where the link register is stored.
14917 (define_insn "eh_set_lr_<mode>"
14918 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
14920 (clobber (match_scratch:P 1 "=&b"))]
14925 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14926 (clobber (match_scratch 1 ""))]
14931 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14935 (define_insn "prefetch"
14936 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
14937 (match_operand:SI 1 "const_int_operand" "n")
14938 (match_operand:SI 2 "const_int_operand" "n"))]
14942 if (GET_CODE (operands[0]) == REG)
14943 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14944 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14946 [(set_attr "type" "load")])
14949 (include "sync.md")
14950 (include "altivec.md")
14953 (include "paired.md")