1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 2, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to the
20 ;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
21 ;; MA 02110-1301, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
30 [(UNSPEC_FRSP 0) ; frsp for POWER machines
31 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
32 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
33 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
35 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
37 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
38 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
41 (UNSPEC_MOVESI_FROM_CR 19)
42 (UNSPEC_MOVESI_TO_CR 20)
44 (UNSPEC_TLSDTPRELHA 22)
45 (UNSPEC_TLSDTPRELLO 23)
46 (UNSPEC_TLSGOTDTPREL 24)
48 (UNSPEC_TLSTPRELHA 26)
49 (UNSPEC_TLSTPRELLO 27)
50 (UNSPEC_TLSGOTTPREL 28)
52 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
53 (UNSPEC_MV_CR_GT 31) ; move_from_CR_eq_bit
70 ;; UNSPEC_VOLATILE usage
75 (UNSPECV_LL 1) ; load-locked
76 (UNSPECV_SC 2) ; store-conditional
77 (UNSPECV_EH_RR 9) ; eh_reg_restore
80 ;; Define an insn type attribute. This is used in function unit delay
82 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c"
83 (const_string "integer"))
86 ; '(pc)' in the following doesn't include the instruction itself; it is
87 ; calculated as if the instruction had zero size.
88 (define_attr "length" ""
89 (if_then_else (eq_attr "type" "branch")
90 (if_then_else (and (ge (minus (match_dup 0) (pc))
92 (lt (minus (match_dup 0) (pc))
98 ;; Processor type -- this attribute must exactly match the processor_type
99 ;; enumeration in rs6000.h.
101 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5"
102 (const (symbol_ref "rs6000_cpu_attr")))
104 (automata_option "ndfa")
117 (include "power4.md")
118 (include "power5.md")
120 (include "predicates.md")
122 (include "darwin.md")
127 ; This mode macro allows :GPR to be used to indicate the allowable size
128 ; of whole values in GPRs.
129 (define_mode_macro GPR [SI (DI "TARGET_POWERPC64")])
131 ; Any supported integer mode.
132 (define_mode_macro INT [QI HI SI DI TI])
134 ; Any supported integer mode that fits in one register.
135 (define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")])
137 ; extend modes for DImode
138 (define_mode_macro QHSI [QI HI SI])
140 ; SImode or DImode, even if DImode doesn't fit in GPRs.
141 (define_mode_macro SDI [SI DI])
143 ; The size of a pointer. Also, the size of the value that a record-condition
144 ; (one with a '.') will compare.
145 (define_mode_macro P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
147 ; Any hardware-supported floating-point mode
148 (define_mode_macro FP [(SF "TARGET_HARD_FLOAT")
149 (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
150 (TF "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
151 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128")])
153 ; Various instructions that come in SI and DI forms.
154 ; A generic w/d attribute, for things like cmpw/cmpd.
155 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
158 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
161 ;; Start with fixed-point load and store insns. Here we put only the more
162 ;; complex forms. Basic data transfer is done later.
164 (define_expand "zero_extend<mode>di2"
165 [(set (match_operand:DI 0 "gpc_reg_operand" "")
166 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
170 (define_insn "*zero_extend<mode>di2_internal1"
171 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
172 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
176 rldicl %0,%1,0,<dbits>"
177 [(set_attr "type" "load,*")])
179 (define_insn "*zero_extend<mode>di2_internal2"
180 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
181 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
183 (clobber (match_scratch:DI 2 "=r,r"))]
186 rldicl. %2,%1,0,<dbits>
188 [(set_attr "type" "compare")
189 (set_attr "length" "4,8")])
192 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
193 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
195 (clobber (match_scratch:DI 2 ""))]
196 "TARGET_POWERPC64 && reload_completed"
198 (zero_extend:DI (match_dup 1)))
200 (compare:CC (match_dup 2)
204 (define_insn "*zero_extend<mode>di2_internal3"
205 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
206 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
208 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
209 (zero_extend:DI (match_dup 1)))]
212 rldicl. %0,%1,0,<dbits>
214 [(set_attr "type" "compare")
215 (set_attr "length" "4,8")])
218 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
219 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
221 (set (match_operand:DI 0 "gpc_reg_operand" "")
222 (zero_extend:DI (match_dup 1)))]
223 "TARGET_POWERPC64 && reload_completed"
225 (zero_extend:DI (match_dup 1)))
227 (compare:CC (match_dup 0)
231 (define_insn "extendqidi2"
232 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
233 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
238 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
239 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
241 (clobber (match_scratch:DI 2 "=r,r"))]
246 [(set_attr "type" "compare")
247 (set_attr "length" "4,8")])
250 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
251 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
253 (clobber (match_scratch:DI 2 ""))]
254 "TARGET_POWERPC64 && reload_completed"
256 (sign_extend:DI (match_dup 1)))
258 (compare:CC (match_dup 2)
263 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
264 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
266 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
267 (sign_extend:DI (match_dup 1)))]
272 [(set_attr "type" "compare")
273 (set_attr "length" "4,8")])
276 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
277 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
279 (set (match_operand:DI 0 "gpc_reg_operand" "")
280 (sign_extend:DI (match_dup 1)))]
281 "TARGET_POWERPC64 && reload_completed"
283 (sign_extend:DI (match_dup 1)))
285 (compare:CC (match_dup 0)
289 (define_expand "extendhidi2"
290 [(set (match_operand:DI 0 "gpc_reg_operand" "")
291 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
296 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
297 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
302 [(set_attr "type" "load_ext,*")])
305 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
306 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
308 (clobber (match_scratch:DI 2 "=r,r"))]
313 [(set_attr "type" "compare")
314 (set_attr "length" "4,8")])
317 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
318 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
320 (clobber (match_scratch:DI 2 ""))]
321 "TARGET_POWERPC64 && reload_completed"
323 (sign_extend:DI (match_dup 1)))
325 (compare:CC (match_dup 2)
330 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
331 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
333 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
334 (sign_extend:DI (match_dup 1)))]
339 [(set_attr "type" "compare")
340 (set_attr "length" "4,8")])
343 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
344 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
346 (set (match_operand:DI 0 "gpc_reg_operand" "")
347 (sign_extend:DI (match_dup 1)))]
348 "TARGET_POWERPC64 && reload_completed"
350 (sign_extend:DI (match_dup 1)))
352 (compare:CC (match_dup 0)
356 (define_expand "extendsidi2"
357 [(set (match_operand:DI 0 "gpc_reg_operand" "")
358 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
363 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
364 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
369 [(set_attr "type" "load_ext,*")])
372 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
373 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
375 (clobber (match_scratch:DI 2 "=r,r"))]
380 [(set_attr "type" "compare")
381 (set_attr "length" "4,8")])
384 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
385 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
387 (clobber (match_scratch:DI 2 ""))]
388 "TARGET_POWERPC64 && reload_completed"
390 (sign_extend:DI (match_dup 1)))
392 (compare:CC (match_dup 2)
397 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
398 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
400 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
401 (sign_extend:DI (match_dup 1)))]
406 [(set_attr "type" "compare")
407 (set_attr "length" "4,8")])
410 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
411 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
413 (set (match_operand:DI 0 "gpc_reg_operand" "")
414 (sign_extend:DI (match_dup 1)))]
415 "TARGET_POWERPC64 && reload_completed"
417 (sign_extend:DI (match_dup 1)))
419 (compare:CC (match_dup 0)
423 (define_expand "zero_extendqisi2"
424 [(set (match_operand:SI 0 "gpc_reg_operand" "")
425 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
430 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
431 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
435 {rlinm|rlwinm} %0,%1,0,0xff"
436 [(set_attr "type" "load,*")])
439 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
440 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
442 (clobber (match_scratch:SI 2 "=r,r"))]
445 {andil.|andi.} %2,%1,0xff
447 [(set_attr "type" "compare")
448 (set_attr "length" "4,8")])
451 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
452 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
454 (clobber (match_scratch:SI 2 ""))]
457 (zero_extend:SI (match_dup 1)))
459 (compare:CC (match_dup 2)
464 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
465 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
467 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
468 (zero_extend:SI (match_dup 1)))]
471 {andil.|andi.} %0,%1,0xff
473 [(set_attr "type" "compare")
474 (set_attr "length" "4,8")])
477 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
478 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
480 (set (match_operand:SI 0 "gpc_reg_operand" "")
481 (zero_extend:SI (match_dup 1)))]
484 (zero_extend:SI (match_dup 1)))
486 (compare:CC (match_dup 0)
490 (define_expand "extendqisi2"
491 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
492 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
497 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
498 else if (TARGET_POWER)
499 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
501 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
505 (define_insn "extendqisi2_ppc"
506 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
507 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
512 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
513 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
515 (clobber (match_scratch:SI 2 "=r,r"))]
520 [(set_attr "type" "compare")
521 (set_attr "length" "4,8")])
524 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
525 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
527 (clobber (match_scratch:SI 2 ""))]
528 "TARGET_POWERPC && reload_completed"
530 (sign_extend:SI (match_dup 1)))
532 (compare:CC (match_dup 2)
537 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
538 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
540 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
541 (sign_extend:SI (match_dup 1)))]
546 [(set_attr "type" "compare")
547 (set_attr "length" "4,8")])
550 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
551 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
553 (set (match_operand:SI 0 "gpc_reg_operand" "")
554 (sign_extend:SI (match_dup 1)))]
555 "TARGET_POWERPC && reload_completed"
557 (sign_extend:SI (match_dup 1)))
559 (compare:CC (match_dup 0)
563 (define_expand "extendqisi2_power"
564 [(parallel [(set (match_dup 2)
565 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
567 (clobber (scratch:SI))])
568 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
569 (ashiftrt:SI (match_dup 2)
571 (clobber (scratch:SI))])]
574 { operands[1] = gen_lowpart (SImode, operands[1]);
575 operands[2] = gen_reg_rtx (SImode); }")
577 (define_expand "extendqisi2_no_power"
579 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
581 (set (match_operand:SI 0 "gpc_reg_operand" "")
582 (ashiftrt:SI (match_dup 2)
584 "! TARGET_POWER && ! TARGET_POWERPC"
586 { operands[1] = gen_lowpart (SImode, operands[1]);
587 operands[2] = gen_reg_rtx (SImode); }")
589 (define_expand "zero_extendqihi2"
590 [(set (match_operand:HI 0 "gpc_reg_operand" "")
591 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
596 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
597 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
601 {rlinm|rlwinm} %0,%1,0,0xff"
602 [(set_attr "type" "load,*")])
605 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
606 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
608 (clobber (match_scratch:HI 2 "=r,r"))]
611 {andil.|andi.} %2,%1,0xff
613 [(set_attr "type" "compare")
614 (set_attr "length" "4,8")])
617 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
618 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
620 (clobber (match_scratch:HI 2 ""))]
623 (zero_extend:HI (match_dup 1)))
625 (compare:CC (match_dup 2)
630 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
631 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
633 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
634 (zero_extend:HI (match_dup 1)))]
637 {andil.|andi.} %0,%1,0xff
639 [(set_attr "type" "compare")
640 (set_attr "length" "4,8")])
643 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
644 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
646 (set (match_operand:HI 0 "gpc_reg_operand" "")
647 (zero_extend:HI (match_dup 1)))]
650 (zero_extend:HI (match_dup 1)))
652 (compare:CC (match_dup 0)
656 (define_expand "extendqihi2"
657 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
658 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
663 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
664 else if (TARGET_POWER)
665 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
667 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
671 (define_insn "extendqihi2_ppc"
672 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
673 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
678 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
679 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
681 (clobber (match_scratch:HI 2 "=r,r"))]
686 [(set_attr "type" "compare")
687 (set_attr "length" "4,8")])
690 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
691 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
693 (clobber (match_scratch:HI 2 ""))]
694 "TARGET_POWERPC && reload_completed"
696 (sign_extend:HI (match_dup 1)))
698 (compare:CC (match_dup 2)
703 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
704 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
706 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
707 (sign_extend:HI (match_dup 1)))]
712 [(set_attr "type" "compare")
713 (set_attr "length" "4,8")])
716 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
717 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
719 (set (match_operand:HI 0 "gpc_reg_operand" "")
720 (sign_extend:HI (match_dup 1)))]
721 "TARGET_POWERPC && reload_completed"
723 (sign_extend:HI (match_dup 1)))
725 (compare:CC (match_dup 0)
729 (define_expand "extendqihi2_power"
730 [(parallel [(set (match_dup 2)
731 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
733 (clobber (scratch:SI))])
734 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
735 (ashiftrt:SI (match_dup 2)
737 (clobber (scratch:SI))])]
740 { operands[0] = gen_lowpart (SImode, operands[0]);
741 operands[1] = gen_lowpart (SImode, operands[1]);
742 operands[2] = gen_reg_rtx (SImode); }")
744 (define_expand "extendqihi2_no_power"
746 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
748 (set (match_operand:HI 0 "gpc_reg_operand" "")
749 (ashiftrt:SI (match_dup 2)
751 "! TARGET_POWER && ! TARGET_POWERPC"
753 { operands[0] = gen_lowpart (SImode, operands[0]);
754 operands[1] = gen_lowpart (SImode, operands[1]);
755 operands[2] = gen_reg_rtx (SImode); }")
757 (define_expand "zero_extendhisi2"
758 [(set (match_operand:SI 0 "gpc_reg_operand" "")
759 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
764 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
765 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
769 {rlinm|rlwinm} %0,%1,0,0xffff"
770 [(set_attr "type" "load,*")])
773 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
774 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
776 (clobber (match_scratch:SI 2 "=r,r"))]
779 {andil.|andi.} %2,%1,0xffff
781 [(set_attr "type" "compare")
782 (set_attr "length" "4,8")])
785 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
786 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
788 (clobber (match_scratch:SI 2 ""))]
791 (zero_extend:SI (match_dup 1)))
793 (compare:CC (match_dup 2)
798 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
799 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
801 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
802 (zero_extend:SI (match_dup 1)))]
805 {andil.|andi.} %0,%1,0xffff
807 [(set_attr "type" "compare")
808 (set_attr "length" "4,8")])
811 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
812 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
814 (set (match_operand:SI 0 "gpc_reg_operand" "")
815 (zero_extend:SI (match_dup 1)))]
818 (zero_extend:SI (match_dup 1)))
820 (compare:CC (match_dup 0)
824 (define_expand "extendhisi2"
825 [(set (match_operand:SI 0 "gpc_reg_operand" "")
826 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
831 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
832 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
837 [(set_attr "type" "load_ext,*")])
840 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
841 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
843 (clobber (match_scratch:SI 2 "=r,r"))]
848 [(set_attr "type" "compare")
849 (set_attr "length" "4,8")])
852 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
853 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
855 (clobber (match_scratch:SI 2 ""))]
858 (sign_extend:SI (match_dup 1)))
860 (compare:CC (match_dup 2)
865 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
866 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
868 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
869 (sign_extend:SI (match_dup 1)))]
874 [(set_attr "type" "compare")
875 (set_attr "length" "4,8")])
878 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
879 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
881 (set (match_operand:SI 0 "gpc_reg_operand" "")
882 (sign_extend:SI (match_dup 1)))]
885 (sign_extend:SI (match_dup 1)))
887 (compare:CC (match_dup 0)
891 ;; Fixed-point arithmetic insns.
893 (define_expand "add<mode>3"
894 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
895 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
896 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
900 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
902 if (non_short_cint_operand (operands[2], DImode))
905 else if (GET_CODE (operands[2]) == CONST_INT
906 && ! add_operand (operands[2], <MODE>mode))
908 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
909 ? operands[0] : gen_reg_rtx (<MODE>mode));
911 HOST_WIDE_INT val = INTVAL (operands[2]);
912 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
913 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
915 if (<MODE>mode == DImode && !CONST_OK_FOR_LETTER_P (rest, 'L'))
918 /* The ordering here is important for the prolog expander.
919 When space is allocated from the stack, adding 'low' first may
920 produce a temporary deallocation (which would be bad). */
921 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
922 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
927 ;; Discourage ai/addic because of carry but provide it in an alternative
928 ;; allowing register zero as source.
929 (define_insn "*add<mode>3_internal1"
930 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
931 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
932 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
936 {cal %0,%2(%1)|addi %0,%1,%2}
938 {cau|addis} %0,%1,%v2"
939 [(set_attr "length" "4,4,4,4")])
941 (define_insn "addsi3_high"
942 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
943 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
944 (high:SI (match_operand 2 "" ""))))]
945 "TARGET_MACHO && !TARGET_64BIT"
946 "{cau|addis} %0,%1,ha16(%2)"
947 [(set_attr "length" "4")])
949 (define_insn "*add<mode>3_internal2"
950 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
951 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
952 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
954 (clobber (match_scratch:P 3 "=r,r,r,r"))]
958 {ai.|addic.} %3,%1,%2
961 [(set_attr "type" "fast_compare,compare,compare,compare")
962 (set_attr "length" "4,4,8,8")])
965 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
966 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
967 (match_operand:GPR 2 "reg_or_short_operand" ""))
969 (clobber (match_scratch:GPR 3 ""))]
972 (plus:GPR (match_dup 1)
975 (compare:CC (match_dup 3)
979 (define_insn "*add<mode>3_internal3"
980 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
981 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
982 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
984 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
985 (plus:P (match_dup 1)
990 {ai.|addic.} %0,%1,%2
993 [(set_attr "type" "fast_compare,compare,compare,compare")
994 (set_attr "length" "4,4,8,8")])
997 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
998 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
999 (match_operand:P 2 "reg_or_short_operand" ""))
1001 (set (match_operand:P 0 "gpc_reg_operand" "")
1002 (plus:P (match_dup 1) (match_dup 2)))]
1005 (plus:P (match_dup 1)
1008 (compare:CC (match_dup 0)
1012 ;; Split an add that we can't do in one insn into two insns, each of which
1013 ;; does one 16-bit part. This is used by combine. Note that the low-order
1014 ;; add should be last in case the result gets used in an address.
1017 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1018 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1019 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1021 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1022 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1025 HOST_WIDE_INT val = INTVAL (operands[2]);
1026 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1027 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1029 operands[4] = GEN_INT (low);
1030 if (<MODE>mode == SImode || CONST_OK_FOR_LETTER_P (rest, 'L'))
1031 operands[3] = GEN_INT (rest);
1032 else if (! no_new_pseudos)
1034 operands[3] = gen_reg_rtx (DImode);
1035 emit_move_insn (operands[3], operands[2]);
1036 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1043 (define_insn "one_cmpl<mode>2"
1044 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1045 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1050 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1051 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1053 (clobber (match_scratch:P 2 "=r,r"))]
1058 [(set_attr "type" "compare")
1059 (set_attr "length" "4,8")])
1062 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1063 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1065 (clobber (match_scratch:P 2 ""))]
1068 (not:P (match_dup 1)))
1070 (compare:CC (match_dup 2)
1075 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1076 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1078 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1079 (not:P (match_dup 1)))]
1084 [(set_attr "type" "compare")
1085 (set_attr "length" "4,8")])
1088 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1089 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1091 (set (match_operand:P 0 "gpc_reg_operand" "")
1092 (not:P (match_dup 1)))]
1095 (not:P (match_dup 1)))
1097 (compare:CC (match_dup 0)
1102 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1103 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1104 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1106 "{sf%I1|subf%I1c} %0,%2,%1")
1109 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1110 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1111 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1118 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1119 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1120 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1122 (clobber (match_scratch:SI 3 "=r,r"))]
1125 {sf.|subfc.} %3,%2,%1
1127 [(set_attr "type" "compare")
1128 (set_attr "length" "4,8")])
1131 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1132 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1133 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1135 (clobber (match_scratch:P 3 "=r,r"))]
1140 [(set_attr "type" "fast_compare")
1141 (set_attr "length" "4,8")])
1144 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1145 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1146 (match_operand:P 2 "gpc_reg_operand" ""))
1148 (clobber (match_scratch:P 3 ""))]
1151 (minus:P (match_dup 1)
1154 (compare:CC (match_dup 3)
1159 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1160 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1161 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1163 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1164 (minus:SI (match_dup 1) (match_dup 2)))]
1167 {sf.|subfc.} %0,%2,%1
1169 [(set_attr "type" "compare")
1170 (set_attr "length" "4,8")])
1173 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1174 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1175 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1177 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1178 (minus:P (match_dup 1)
1184 [(set_attr "type" "fast_compare")
1185 (set_attr "length" "4,8")])
1188 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1189 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1190 (match_operand:P 2 "gpc_reg_operand" ""))
1192 (set (match_operand:P 0 "gpc_reg_operand" "")
1193 (minus:P (match_dup 1)
1197 (minus:P (match_dup 1)
1200 (compare:CC (match_dup 0)
1204 (define_expand "sub<mode>3"
1205 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1206 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1207 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1211 if (GET_CODE (operands[2]) == CONST_INT)
1213 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1214 negate_rtx (<MODE>mode, operands[2])));
1219 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1220 ;; instruction and some auxiliary computations. Then we just have a single
1221 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1224 (define_expand "sminsi3"
1226 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1227 (match_operand:SI 2 "reg_or_short_operand" ""))
1229 (minus:SI (match_dup 2) (match_dup 1))))
1230 (set (match_operand:SI 0 "gpc_reg_operand" "")
1231 (minus:SI (match_dup 2) (match_dup 3)))]
1232 "TARGET_POWER || TARGET_ISEL"
1237 operands[2] = force_reg (SImode, operands[2]);
1238 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1242 operands[3] = gen_reg_rtx (SImode);
1246 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1247 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1248 (match_operand:SI 2 "reg_or_short_operand" "")))
1249 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1252 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1254 (minus:SI (match_dup 2) (match_dup 1))))
1255 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1258 (define_expand "smaxsi3"
1260 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1261 (match_operand:SI 2 "reg_or_short_operand" ""))
1263 (minus:SI (match_dup 2) (match_dup 1))))
1264 (set (match_operand:SI 0 "gpc_reg_operand" "")
1265 (plus:SI (match_dup 3) (match_dup 1)))]
1266 "TARGET_POWER || TARGET_ISEL"
1271 operands[2] = force_reg (SImode, operands[2]);
1272 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1275 operands[3] = gen_reg_rtx (SImode);
1279 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1280 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1281 (match_operand:SI 2 "reg_or_short_operand" "")))
1282 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1285 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1287 (minus:SI (match_dup 2) (match_dup 1))))
1288 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1291 (define_expand "uminsi3"
1292 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1294 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1296 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1298 (minus:SI (match_dup 4) (match_dup 3))))
1299 (set (match_operand:SI 0 "gpc_reg_operand" "")
1300 (minus:SI (match_dup 2) (match_dup 3)))]
1301 "TARGET_POWER || TARGET_ISEL"
1306 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1309 operands[3] = gen_reg_rtx (SImode);
1310 operands[4] = gen_reg_rtx (SImode);
1311 operands[5] = GEN_INT (-2147483647 - 1);
1314 (define_expand "umaxsi3"
1315 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1317 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1319 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1321 (minus:SI (match_dup 4) (match_dup 3))))
1322 (set (match_operand:SI 0 "gpc_reg_operand" "")
1323 (plus:SI (match_dup 3) (match_dup 1)))]
1324 "TARGET_POWER || TARGET_ISEL"
1329 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1332 operands[3] = gen_reg_rtx (SImode);
1333 operands[4] = gen_reg_rtx (SImode);
1334 operands[5] = GEN_INT (-2147483647 - 1);
1338 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1339 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1340 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1342 (minus:SI (match_dup 2) (match_dup 1))))]
1347 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1349 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1350 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1352 (minus:SI (match_dup 2) (match_dup 1)))
1354 (clobber (match_scratch:SI 3 "=r,r"))]
1359 [(set_attr "type" "delayed_compare")
1360 (set_attr "length" "4,8")])
1363 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1365 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1366 (match_operand:SI 2 "reg_or_short_operand" ""))
1368 (minus:SI (match_dup 2) (match_dup 1)))
1370 (clobber (match_scratch:SI 3 ""))]
1371 "TARGET_POWER && reload_completed"
1373 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1375 (minus:SI (match_dup 2) (match_dup 1))))
1377 (compare:CC (match_dup 3)
1382 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1384 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1385 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1387 (minus:SI (match_dup 2) (match_dup 1)))
1389 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1390 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1392 (minus:SI (match_dup 2) (match_dup 1))))]
1397 [(set_attr "type" "delayed_compare")
1398 (set_attr "length" "4,8")])
1401 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1403 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1404 (match_operand:SI 2 "reg_or_short_operand" ""))
1406 (minus:SI (match_dup 2) (match_dup 1)))
1408 (set (match_operand:SI 0 "gpc_reg_operand" "")
1409 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1411 (minus:SI (match_dup 2) (match_dup 1))))]
1412 "TARGET_POWER && reload_completed"
1414 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1416 (minus:SI (match_dup 2) (match_dup 1))))
1418 (compare:CC (match_dup 0)
1422 ;; We don't need abs with condition code because such comparisons should
1424 (define_expand "abssi2"
1425 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1426 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1432 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1435 else if (! TARGET_POWER)
1437 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1442 (define_insn "*abssi2_power"
1443 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1444 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1448 (define_insn_and_split "abssi2_isel"
1449 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1450 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
1451 (clobber (match_scratch:SI 2 "=&b"))
1452 (clobber (match_scratch:CC 3 "=y"))]
1455 "&& reload_completed"
1456 [(set (match_dup 2) (neg:SI (match_dup 1)))
1458 (compare:CC (match_dup 1)
1461 (if_then_else:SI (ge (match_dup 3)
1467 (define_insn_and_split "abssi2_nopower"
1468 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1469 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1470 (clobber (match_scratch:SI 2 "=&r,&r"))]
1471 "! TARGET_POWER && ! TARGET_ISEL"
1473 "&& reload_completed"
1474 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1475 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1476 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1479 (define_insn "*nabs_power"
1480 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1481 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1485 (define_insn_and_split "*nabs_nopower"
1486 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1487 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1488 (clobber (match_scratch:SI 2 "=&r,&r"))]
1491 "&& reload_completed"
1492 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1493 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1494 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1497 (define_expand "neg<mode>2"
1498 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1499 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1503 (define_insn "*neg<mode>2_internal"
1504 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1505 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1510 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1511 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1513 (clobber (match_scratch:P 2 "=r,r"))]
1518 [(set_attr "type" "fast_compare")
1519 (set_attr "length" "4,8")])
1522 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1523 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1525 (clobber (match_scratch:P 2 ""))]
1528 (neg:P (match_dup 1)))
1530 (compare:CC (match_dup 2)
1535 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1536 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1538 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1539 (neg:P (match_dup 1)))]
1544 [(set_attr "type" "fast_compare")
1545 (set_attr "length" "4,8")])
1548 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1549 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1551 (set (match_operand:P 0 "gpc_reg_operand" "")
1552 (neg:P (match_dup 1)))]
1555 (neg:P (match_dup 1)))
1557 (compare:CC (match_dup 0)
1561 (define_insn "clz<mode>2"
1562 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1563 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1565 "{cntlz|cntlz<wd>} %0,%1")
1567 (define_expand "ctz<mode>2"
1569 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
1570 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1572 (clobber (scratch:CC))])
1573 (set (match_dup 4) (clz:GPR (match_dup 3)))
1574 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1575 (minus:GPR (match_dup 5) (match_dup 4)))]
1578 operands[2] = gen_reg_rtx (<MODE>mode);
1579 operands[3] = gen_reg_rtx (<MODE>mode);
1580 operands[4] = gen_reg_rtx (<MODE>mode);
1581 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
1584 (define_expand "ffs<mode>2"
1586 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
1587 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1589 (clobber (scratch:CC))])
1590 (set (match_dup 4) (clz:GPR (match_dup 3)))
1591 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1592 (minus:GPR (match_dup 5) (match_dup 4)))]
1595 operands[2] = gen_reg_rtx (<MODE>mode);
1596 operands[3] = gen_reg_rtx (<MODE>mode);
1597 operands[4] = gen_reg_rtx (<MODE>mode);
1598 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
1601 (define_expand "popcount<mode>2"
1603 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1606 (mult:GPR (match_dup 2) (match_dup 4)))
1607 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1608 (lshiftrt:GPR (match_dup 3) (match_dup 5)))]
1611 operands[2] = gen_reg_rtx (<MODE>mode);
1612 operands[3] = gen_reg_rtx (<MODE>mode);
1613 operands[4] = force_reg (<MODE>mode,
1614 <MODE>mode == SImode
1615 ? GEN_INT (0x01010101)
1616 : GEN_INT ((HOST_WIDE_INT)
1617 0x01010101 << 32 | 0x01010101));
1618 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 8);
1621 (define_insn "popcntb<mode>2"
1622 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1623 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1628 (define_expand "mulsi3"
1629 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1630 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1631 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1636 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
1638 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
1642 (define_insn "mulsi3_mq"
1643 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1644 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1645 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1646 (clobber (match_scratch:SI 3 "=q,q"))]
1649 {muls|mullw} %0,%1,%2
1650 {muli|mulli} %0,%1,%2"
1652 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1653 (const_string "imul3")
1654 (match_operand:SI 2 "short_cint_operand" "")
1655 (const_string "imul2")]
1656 (const_string "imul")))])
1658 (define_insn "mulsi3_no_mq"
1659 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1660 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1661 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
1664 {muls|mullw} %0,%1,%2
1665 {muli|mulli} %0,%1,%2"
1667 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1668 (const_string "imul3")
1669 (match_operand:SI 2 "short_cint_operand" "")
1670 (const_string "imul2")]
1671 (const_string "imul")))])
1673 (define_insn "*mulsi3_mq_internal1"
1674 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1675 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1676 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1678 (clobber (match_scratch:SI 3 "=r,r"))
1679 (clobber (match_scratch:SI 4 "=q,q"))]
1682 {muls.|mullw.} %3,%1,%2
1684 [(set_attr "type" "imul_compare")
1685 (set_attr "length" "4,8")])
1688 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1689 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1690 (match_operand:SI 2 "gpc_reg_operand" ""))
1692 (clobber (match_scratch:SI 3 ""))
1693 (clobber (match_scratch:SI 4 ""))]
1694 "TARGET_POWER && reload_completed"
1695 [(parallel [(set (match_dup 3)
1696 (mult:SI (match_dup 1) (match_dup 2)))
1697 (clobber (match_dup 4))])
1699 (compare:CC (match_dup 3)
1703 (define_insn "*mulsi3_no_mq_internal1"
1704 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1705 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1706 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1708 (clobber (match_scratch:SI 3 "=r,r"))]
1711 {muls.|mullw.} %3,%1,%2
1713 [(set_attr "type" "imul_compare")
1714 (set_attr "length" "4,8")])
1717 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1718 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1719 (match_operand:SI 2 "gpc_reg_operand" ""))
1721 (clobber (match_scratch:SI 3 ""))]
1722 "! TARGET_POWER && reload_completed"
1724 (mult:SI (match_dup 1) (match_dup 2)))
1726 (compare:CC (match_dup 3)
1730 (define_insn "*mulsi3_mq_internal2"
1731 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1732 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1733 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1735 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1736 (mult:SI (match_dup 1) (match_dup 2)))
1737 (clobber (match_scratch:SI 4 "=q,q"))]
1740 {muls.|mullw.} %0,%1,%2
1742 [(set_attr "type" "imul_compare")
1743 (set_attr "length" "4,8")])
1746 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1747 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1748 (match_operand:SI 2 "gpc_reg_operand" ""))
1750 (set (match_operand:SI 0 "gpc_reg_operand" "")
1751 (mult:SI (match_dup 1) (match_dup 2)))
1752 (clobber (match_scratch:SI 4 ""))]
1753 "TARGET_POWER && reload_completed"
1754 [(parallel [(set (match_dup 0)
1755 (mult:SI (match_dup 1) (match_dup 2)))
1756 (clobber (match_dup 4))])
1758 (compare:CC (match_dup 0)
1762 (define_insn "*mulsi3_no_mq_internal2"
1763 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1764 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1765 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1767 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1768 (mult:SI (match_dup 1) (match_dup 2)))]
1771 {muls.|mullw.} %0,%1,%2
1773 [(set_attr "type" "imul_compare")
1774 (set_attr "length" "4,8")])
1777 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1778 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1779 (match_operand:SI 2 "gpc_reg_operand" ""))
1781 (set (match_operand:SI 0 "gpc_reg_operand" "")
1782 (mult:SI (match_dup 1) (match_dup 2)))]
1783 "! TARGET_POWER && reload_completed"
1785 (mult:SI (match_dup 1) (match_dup 2)))
1787 (compare:CC (match_dup 0)
1791 ;; Operand 1 is divided by operand 2; quotient goes to operand
1792 ;; 0 and remainder to operand 3.
1793 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1795 (define_expand "divmodsi4"
1796 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1797 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1798 (match_operand:SI 2 "gpc_reg_operand" "")))
1799 (set (match_operand:SI 3 "register_operand" "")
1800 (mod:SI (match_dup 1) (match_dup 2)))])]
1801 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1804 if (! TARGET_POWER && ! TARGET_POWERPC)
1806 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1807 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1808 emit_insn (gen_divss_call ());
1809 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1810 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
1815 (define_insn "*divmodsi4_internal"
1816 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1817 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1818 (match_operand:SI 2 "gpc_reg_operand" "r")))
1819 (set (match_operand:SI 3 "register_operand" "=q")
1820 (mod:SI (match_dup 1) (match_dup 2)))]
1823 [(set_attr "type" "idiv")])
1825 (define_expand "udiv<mode>3"
1826 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1827 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1828 (match_operand:GPR 2 "gpc_reg_operand" "")))]
1829 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1832 if (! TARGET_POWER && ! TARGET_POWERPC)
1834 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1835 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1836 emit_insn (gen_quous_call ());
1837 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1840 else if (TARGET_POWER)
1842 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
1847 (define_insn "udivsi3_mq"
1848 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1849 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1850 (match_operand:SI 2 "gpc_reg_operand" "r")))
1851 (clobber (match_scratch:SI 3 "=q"))]
1852 "TARGET_POWERPC && TARGET_POWER"
1854 [(set_attr "type" "idiv")])
1856 (define_insn "*udivsi3_no_mq"
1857 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1858 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
1859 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
1860 "TARGET_POWERPC && ! TARGET_POWER"
1862 [(set_attr "type" "idiv")])
1864 ;; For powers of two we can do srai/aze for divide and then adjust for
1865 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1866 ;; used; for PowerPC, force operands into register and do a normal divide;
1867 ;; for AIX common-mode, use quoss call on register operands.
1868 (define_expand "div<mode>3"
1869 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1870 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1871 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
1875 if (GET_CODE (operands[2]) == CONST_INT
1876 && INTVAL (operands[2]) > 0
1877 && exact_log2 (INTVAL (operands[2])) >= 0)
1879 else if (TARGET_POWERPC)
1881 operands[2] = force_reg (SImode, operands[2]);
1884 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
1888 else if (TARGET_POWER)
1892 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1893 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1894 emit_insn (gen_quoss_call ());
1895 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1900 (define_insn "divsi3_mq"
1901 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1902 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1903 (match_operand:SI 2 "gpc_reg_operand" "r")))
1904 (clobber (match_scratch:SI 3 "=q"))]
1905 "TARGET_POWERPC && TARGET_POWER"
1907 [(set_attr "type" "idiv")])
1909 (define_insn "*div<mode>3_no_mq"
1910 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1911 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
1912 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
1913 "TARGET_POWERPC && ! TARGET_POWER"
1915 [(set_attr "type" "idiv")])
1917 (define_expand "mod<mode>3"
1918 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
1919 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
1920 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
1928 if (GET_CODE (operands[2]) != CONST_INT
1929 || INTVAL (operands[2]) <= 0
1930 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
1933 temp1 = gen_reg_rtx (<MODE>mode);
1934 temp2 = gen_reg_rtx (<MODE>mode);
1936 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
1937 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
1938 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
1943 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1944 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
1945 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
1947 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
1948 [(set_attr "type" "two")
1949 (set_attr "length" "8")])
1952 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1953 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1954 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
1956 (clobber (match_scratch:P 3 "=r,r"))]
1959 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
1961 [(set_attr "type" "compare")
1962 (set_attr "length" "8,12")])
1965 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1966 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1967 (match_operand:GPR 2 "exact_log2_cint_operand"
1970 (clobber (match_scratch:GPR 3 ""))]
1973 (div:<MODE> (match_dup 1) (match_dup 2)))
1975 (compare:CC (match_dup 3)
1980 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1981 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1982 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
1984 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1985 (div:P (match_dup 1) (match_dup 2)))]
1988 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
1990 [(set_attr "type" "compare")
1991 (set_attr "length" "8,12")])
1994 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1995 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1996 (match_operand:GPR 2 "exact_log2_cint_operand"
1999 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2000 (div:GPR (match_dup 1) (match_dup 2)))]
2003 (div:<MODE> (match_dup 1) (match_dup 2)))
2005 (compare:CC (match_dup 0)
2010 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2013 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2015 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2016 (match_operand:SI 3 "gpc_reg_operand" "r")))
2017 (set (match_operand:SI 2 "register_operand" "=*q")
2020 (zero_extend:DI (match_dup 1)) (const_int 32))
2021 (zero_extend:DI (match_dup 4)))
2025 [(set_attr "type" "idiv")])
2027 ;; To do unsigned divide we handle the cases of the divisor looking like a
2028 ;; negative number. If it is a constant that is less than 2**31, we don't
2029 ;; have to worry about the branches. So make a few subroutines here.
2031 ;; First comes the normal case.
2032 (define_expand "udivmodsi4_normal"
2033 [(set (match_dup 4) (const_int 0))
2034 (parallel [(set (match_operand:SI 0 "" "")
2035 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2037 (zero_extend:DI (match_operand:SI 1 "" "")))
2038 (match_operand:SI 2 "" "")))
2039 (set (match_operand:SI 3 "" "")
2040 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2042 (zero_extend:DI (match_dup 1)))
2046 { operands[4] = gen_reg_rtx (SImode); }")
2048 ;; This handles the branches.
2049 (define_expand "udivmodsi4_tests"
2050 [(set (match_operand:SI 0 "" "") (const_int 0))
2051 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2052 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2053 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2054 (label_ref (match_operand:SI 4 "" "")) (pc)))
2055 (set (match_dup 0) (const_int 1))
2056 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2057 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2058 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2059 (label_ref (match_dup 4)) (pc)))]
2062 { operands[5] = gen_reg_rtx (CCUNSmode);
2063 operands[6] = gen_reg_rtx (CCmode);
2066 (define_expand "udivmodsi4"
2067 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2068 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2069 (match_operand:SI 2 "reg_or_cint_operand" "")))
2070 (set (match_operand:SI 3 "gpc_reg_operand" "")
2071 (umod:SI (match_dup 1) (match_dup 2)))])]
2079 if (! TARGET_POWERPC)
2081 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2082 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2083 emit_insn (gen_divus_call ());
2084 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2085 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2092 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2094 operands[2] = force_reg (SImode, operands[2]);
2095 label = gen_label_rtx ();
2096 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2097 operands[3], label));
2100 operands[2] = force_reg (SImode, operands[2]);
2102 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2110 ;; AIX architecture-independent common-mode multiply (DImode),
2111 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2112 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2113 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2114 ;; assumed unused if generating common-mode, so ignore.
2115 (define_insn "mulh_call"
2118 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2119 (sign_extend:DI (reg:SI 4)))
2121 (clobber (match_scratch:SI 0 "=l"))]
2122 "! TARGET_POWER && ! TARGET_POWERPC"
2124 [(set_attr "type" "imul")])
2126 (define_insn "mull_call"
2128 (mult:DI (sign_extend:DI (reg:SI 3))
2129 (sign_extend:DI (reg:SI 4))))
2130 (clobber (match_scratch:SI 0 "=l"))
2131 (clobber (reg:SI 0))]
2132 "! TARGET_POWER && ! TARGET_POWERPC"
2134 [(set_attr "type" "imul")])
2136 (define_insn "divss_call"
2138 (div:SI (reg:SI 3) (reg:SI 4)))
2140 (mod:SI (reg:SI 3) (reg:SI 4)))
2141 (clobber (match_scratch:SI 0 "=l"))
2142 (clobber (reg:SI 0))]
2143 "! TARGET_POWER && ! TARGET_POWERPC"
2145 [(set_attr "type" "idiv")])
2147 (define_insn "divus_call"
2149 (udiv:SI (reg:SI 3) (reg:SI 4)))
2151 (umod:SI (reg:SI 3) (reg:SI 4)))
2152 (clobber (match_scratch:SI 0 "=l"))
2153 (clobber (reg:SI 0))
2154 (clobber (match_scratch:CC 1 "=x"))
2155 (clobber (reg:CC 69))]
2156 "! TARGET_POWER && ! TARGET_POWERPC"
2158 [(set_attr "type" "idiv")])
2160 (define_insn "quoss_call"
2162 (div:SI (reg:SI 3) (reg:SI 4)))
2163 (clobber (match_scratch:SI 0 "=l"))]
2164 "! TARGET_POWER && ! TARGET_POWERPC"
2166 [(set_attr "type" "idiv")])
2168 (define_insn "quous_call"
2170 (udiv:SI (reg:SI 3) (reg:SI 4)))
2171 (clobber (match_scratch:SI 0 "=l"))
2172 (clobber (reg:SI 0))
2173 (clobber (match_scratch:CC 1 "=x"))
2174 (clobber (reg:CC 69))]
2175 "! TARGET_POWER && ! TARGET_POWERPC"
2177 [(set_attr "type" "idiv")])
2179 ;; Logical instructions
2180 ;; The logical instructions are mostly combined by using match_operator,
2181 ;; but the plain AND insns are somewhat different because there is no
2182 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2183 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2185 (define_insn "andsi3"
2186 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2187 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2188 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2189 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2193 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2194 {andil.|andi.} %0,%1,%b2
2195 {andiu.|andis.} %0,%1,%u2"
2196 [(set_attr "type" "*,*,compare,compare")])
2198 ;; Note to set cr's other than cr0 we do the and immediate and then
2199 ;; the test again -- this avoids a mfcr which on the higher end
2200 ;; machines causes an execution serialization
2202 (define_insn "*andsi3_internal2"
2203 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2204 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2205 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2207 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2208 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2212 {andil.|andi.} %3,%1,%b2
2213 {andiu.|andis.} %3,%1,%u2
2214 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2219 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2220 (set_attr "length" "4,4,4,4,8,8,8,8")])
2222 (define_insn "*andsi3_internal3"
2223 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2224 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2225 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2227 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2228 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2232 {andil.|andi.} %3,%1,%b2
2233 {andiu.|andis.} %3,%1,%u2
2234 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2239 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2240 (set_attr "length" "8,4,4,4,8,8,8,8")])
2243 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2244 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2245 (match_operand:GPR 2 "and_operand" ""))
2247 (clobber (match_scratch:GPR 3 ""))
2248 (clobber (match_scratch:CC 4 ""))]
2250 [(parallel [(set (match_dup 3)
2251 (and:<MODE> (match_dup 1)
2253 (clobber (match_dup 4))])
2255 (compare:CC (match_dup 3)
2259 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2260 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2263 [(set (match_operand:CC 0 "cc_reg_operand" "")
2264 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2265 (match_operand:SI 2 "gpc_reg_operand" ""))
2267 (clobber (match_scratch:SI 3 ""))
2268 (clobber (match_scratch:CC 4 ""))]
2269 "TARGET_POWERPC64 && reload_completed"
2270 [(parallel [(set (match_dup 3)
2271 (and:SI (match_dup 1)
2273 (clobber (match_dup 4))])
2275 (compare:CC (match_dup 3)
2279 (define_insn "*andsi3_internal4"
2280 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2281 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2282 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2284 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2285 (and:SI (match_dup 1)
2287 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2291 {andil.|andi.} %0,%1,%b2
2292 {andiu.|andis.} %0,%1,%u2
2293 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2298 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2299 (set_attr "length" "4,4,4,4,8,8,8,8")])
2301 (define_insn "*andsi3_internal5"
2302 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2303 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2304 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2306 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2307 (and:SI (match_dup 1)
2309 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2313 {andil.|andi.} %0,%1,%b2
2314 {andiu.|andis.} %0,%1,%u2
2315 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2320 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2321 (set_attr "length" "8,4,4,4,8,8,8,8")])
2324 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2325 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2326 (match_operand:SI 2 "and_operand" ""))
2328 (set (match_operand:SI 0 "gpc_reg_operand" "")
2329 (and:SI (match_dup 1)
2331 (clobber (match_scratch:CC 4 ""))]
2333 [(parallel [(set (match_dup 0)
2334 (and:SI (match_dup 1)
2336 (clobber (match_dup 4))])
2338 (compare:CC (match_dup 0)
2343 [(set (match_operand:CC 3 "cc_reg_operand" "")
2344 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2345 (match_operand:SI 2 "gpc_reg_operand" ""))
2347 (set (match_operand:SI 0 "gpc_reg_operand" "")
2348 (and:SI (match_dup 1)
2350 (clobber (match_scratch:CC 4 ""))]
2351 "TARGET_POWERPC64 && reload_completed"
2352 [(parallel [(set (match_dup 0)
2353 (and:SI (match_dup 1)
2355 (clobber (match_dup 4))])
2357 (compare:CC (match_dup 0)
2361 ;; Handle the PowerPC64 rlwinm corner case
2363 (define_insn_and_split "*andsi3_internal6"
2364 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2365 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2366 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2371 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2374 (rotate:SI (match_dup 0) (match_dup 5)))]
2377 int mb = extract_MB (operands[2]);
2378 int me = extract_ME (operands[2]);
2379 operands[3] = GEN_INT (me + 1);
2380 operands[5] = GEN_INT (32 - (me + 1));
2381 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2383 [(set_attr "length" "8")])
2385 (define_expand "iorsi3"
2386 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2387 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2388 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2392 if (GET_CODE (operands[2]) == CONST_INT
2393 && ! logical_operand (operands[2], SImode))
2395 HOST_WIDE_INT value = INTVAL (operands[2]);
2396 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2397 ? operands[0] : gen_reg_rtx (SImode));
2399 emit_insn (gen_iorsi3 (tmp, operands[1],
2400 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2401 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2406 (define_expand "xorsi3"
2407 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2408 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2409 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2413 if (GET_CODE (operands[2]) == CONST_INT
2414 && ! logical_operand (operands[2], SImode))
2416 HOST_WIDE_INT value = INTVAL (operands[2]);
2417 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2418 ? operands[0] : gen_reg_rtx (SImode));
2420 emit_insn (gen_xorsi3 (tmp, operands[1],
2421 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2422 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2427 (define_insn "*boolsi3_internal1"
2428 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2429 (match_operator:SI 3 "boolean_or_operator"
2430 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2431 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2435 {%q3il|%q3i} %0,%1,%b2
2436 {%q3iu|%q3is} %0,%1,%u2")
2438 (define_insn "*boolsi3_internal2"
2439 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2440 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2441 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2442 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2444 (clobber (match_scratch:SI 3 "=r,r"))]
2449 [(set_attr "type" "compare")
2450 (set_attr "length" "4,8")])
2453 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2454 (compare:CC (match_operator:SI 4 "boolean_operator"
2455 [(match_operand:SI 1 "gpc_reg_operand" "")
2456 (match_operand:SI 2 "gpc_reg_operand" "")])
2458 (clobber (match_scratch:SI 3 ""))]
2459 "TARGET_32BIT && reload_completed"
2460 [(set (match_dup 3) (match_dup 4))
2462 (compare:CC (match_dup 3)
2466 (define_insn "*boolsi3_internal3"
2467 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2468 (compare:CC (match_operator:SI 4 "boolean_operator"
2469 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2470 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2472 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2478 [(set_attr "type" "compare")
2479 (set_attr "length" "4,8")])
2482 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2483 (compare:CC (match_operator:SI 4 "boolean_operator"
2484 [(match_operand:SI 1 "gpc_reg_operand" "")
2485 (match_operand:SI 2 "gpc_reg_operand" "")])
2487 (set (match_operand:SI 0 "gpc_reg_operand" "")
2489 "TARGET_32BIT && reload_completed"
2490 [(set (match_dup 0) (match_dup 4))
2492 (compare:CC (match_dup 0)
2496 ;; Split a logical operation that we can't do in one insn into two insns,
2497 ;; each of which does one 16-bit part. This is used by combine.
2500 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2501 (match_operator:SI 3 "boolean_or_operator"
2502 [(match_operand:SI 1 "gpc_reg_operand" "")
2503 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
2505 [(set (match_dup 0) (match_dup 4))
2506 (set (match_dup 0) (match_dup 5))]
2510 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2511 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2513 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2514 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2518 (define_insn "*boolcsi3_internal1"
2519 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2520 (match_operator:SI 3 "boolean_operator"
2521 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2522 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
2526 (define_insn "*boolcsi3_internal2"
2527 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2528 (compare:CC (match_operator:SI 4 "boolean_operator"
2529 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2530 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2532 (clobber (match_scratch:SI 3 "=r,r"))]
2537 [(set_attr "type" "compare")
2538 (set_attr "length" "4,8")])
2541 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2542 (compare:CC (match_operator:SI 4 "boolean_operator"
2543 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2544 (match_operand:SI 2 "gpc_reg_operand" "")])
2546 (clobber (match_scratch:SI 3 ""))]
2547 "TARGET_32BIT && reload_completed"
2548 [(set (match_dup 3) (match_dup 4))
2550 (compare:CC (match_dup 3)
2554 (define_insn "*boolcsi3_internal3"
2555 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2556 (compare:CC (match_operator:SI 4 "boolean_operator"
2557 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2558 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2560 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2566 [(set_attr "type" "compare")
2567 (set_attr "length" "4,8")])
2570 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2571 (compare:CC (match_operator:SI 4 "boolean_operator"
2572 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2573 (match_operand:SI 2 "gpc_reg_operand" "")])
2575 (set (match_operand:SI 0 "gpc_reg_operand" "")
2577 "TARGET_32BIT && reload_completed"
2578 [(set (match_dup 0) (match_dup 4))
2580 (compare:CC (match_dup 0)
2584 (define_insn "*boolccsi3_internal1"
2585 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2586 (match_operator:SI 3 "boolean_operator"
2587 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2588 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
2592 (define_insn "*boolccsi3_internal2"
2593 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2594 (compare:CC (match_operator:SI 4 "boolean_operator"
2595 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2596 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2598 (clobber (match_scratch:SI 3 "=r,r"))]
2603 [(set_attr "type" "compare")
2604 (set_attr "length" "4,8")])
2607 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2608 (compare:CC (match_operator:SI 4 "boolean_operator"
2609 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2610 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2612 (clobber (match_scratch:SI 3 ""))]
2613 "TARGET_32BIT && reload_completed"
2614 [(set (match_dup 3) (match_dup 4))
2616 (compare:CC (match_dup 3)
2620 (define_insn "*boolccsi3_internal3"
2621 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2622 (compare:CC (match_operator:SI 4 "boolean_operator"
2623 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2624 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2626 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2632 [(set_attr "type" "compare")
2633 (set_attr "length" "4,8")])
2636 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2637 (compare:CC (match_operator:SI 4 "boolean_operator"
2638 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2639 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2641 (set (match_operand:SI 0 "gpc_reg_operand" "")
2643 "TARGET_32BIT && reload_completed"
2644 [(set (match_dup 0) (match_dup 4))
2646 (compare:CC (match_dup 0)
2650 ;; maskir insn. We need four forms because things might be in arbitrary
2651 ;; orders. Don't define forms that only set CR fields because these
2652 ;; would modify an input register.
2654 (define_insn "*maskir_internal1"
2655 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2656 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2657 (match_operand:SI 1 "gpc_reg_operand" "0"))
2658 (and:SI (match_dup 2)
2659 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
2663 (define_insn "*maskir_internal2"
2664 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2665 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2666 (match_operand:SI 1 "gpc_reg_operand" "0"))
2667 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2672 (define_insn "*maskir_internal3"
2673 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2674 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2675 (match_operand:SI 3 "gpc_reg_operand" "r"))
2676 (and:SI (not:SI (match_dup 2))
2677 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2681 (define_insn "*maskir_internal4"
2682 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2683 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2684 (match_operand:SI 2 "gpc_reg_operand" "r"))
2685 (and:SI (not:SI (match_dup 2))
2686 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2690 (define_insn "*maskir_internal5"
2691 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2693 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2694 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2695 (and:SI (match_dup 2)
2696 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
2698 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2699 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2700 (and:SI (match_dup 2) (match_dup 3))))]
2705 [(set_attr "type" "compare")
2706 (set_attr "length" "4,8")])
2709 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2711 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2712 (match_operand:SI 1 "gpc_reg_operand" ""))
2713 (and:SI (match_dup 2)
2714 (match_operand:SI 3 "gpc_reg_operand" "")))
2716 (set (match_operand:SI 0 "gpc_reg_operand" "")
2717 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2718 (and:SI (match_dup 2) (match_dup 3))))]
2719 "TARGET_POWER && reload_completed"
2721 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2722 (and:SI (match_dup 2) (match_dup 3))))
2724 (compare:CC (match_dup 0)
2728 (define_insn "*maskir_internal6"
2729 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2731 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2732 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2733 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2736 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2737 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2738 (and:SI (match_dup 3) (match_dup 2))))]
2743 [(set_attr "type" "compare")
2744 (set_attr "length" "4,8")])
2747 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2749 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2750 (match_operand:SI 1 "gpc_reg_operand" ""))
2751 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2754 (set (match_operand:SI 0 "gpc_reg_operand" "")
2755 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2756 (and:SI (match_dup 3) (match_dup 2))))]
2757 "TARGET_POWER && reload_completed"
2759 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2760 (and:SI (match_dup 3) (match_dup 2))))
2762 (compare:CC (match_dup 0)
2766 (define_insn "*maskir_internal7"
2767 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2769 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
2770 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
2771 (and:SI (not:SI (match_dup 2))
2772 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2774 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2775 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2776 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2781 [(set_attr "type" "compare")
2782 (set_attr "length" "4,8")])
2785 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2787 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
2788 (match_operand:SI 3 "gpc_reg_operand" ""))
2789 (and:SI (not:SI (match_dup 2))
2790 (match_operand:SI 1 "gpc_reg_operand" "")))
2792 (set (match_operand:SI 0 "gpc_reg_operand" "")
2793 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2794 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2795 "TARGET_POWER && reload_completed"
2797 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2798 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2800 (compare:CC (match_dup 0)
2804 (define_insn "*maskir_internal8"
2805 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2807 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2808 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2809 (and:SI (not:SI (match_dup 2))
2810 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2812 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2813 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2814 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2819 [(set_attr "type" "compare")
2820 (set_attr "length" "4,8")])
2823 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2825 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2826 (match_operand:SI 2 "gpc_reg_operand" ""))
2827 (and:SI (not:SI (match_dup 2))
2828 (match_operand:SI 1 "gpc_reg_operand" "")))
2830 (set (match_operand:SI 0 "gpc_reg_operand" "")
2831 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2832 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2833 "TARGET_POWER && reload_completed"
2835 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2836 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2838 (compare:CC (match_dup 0)
2842 ;; Rotate and shift insns, in all their variants. These support shifts,
2843 ;; field inserts and extracts, and various combinations thereof.
2844 (define_expand "insv"
2845 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
2846 (match_operand:SI 1 "const_int_operand" "")
2847 (match_operand:SI 2 "const_int_operand" ""))
2848 (match_operand 3 "gpc_reg_operand" ""))]
2852 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2853 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2854 compiler if the address of the structure is taken later. */
2855 if (GET_CODE (operands[0]) == SUBREG
2856 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2859 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
2860 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
2862 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
2866 (define_insn "insvsi"
2867 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2868 (match_operand:SI 1 "const_int_operand" "i")
2869 (match_operand:SI 2 "const_int_operand" "i"))
2870 (match_operand:SI 3 "gpc_reg_operand" "r"))]
2874 int start = INTVAL (operands[2]) & 31;
2875 int size = INTVAL (operands[1]) & 31;
2877 operands[4] = GEN_INT (32 - start - size);
2878 operands[1] = GEN_INT (start + size - 1);
2879 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2881 [(set_attr "type" "insert_word")])
2883 (define_insn "*insvsi_internal1"
2884 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2885 (match_operand:SI 1 "const_int_operand" "i")
2886 (match_operand:SI 2 "const_int_operand" "i"))
2887 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2888 (match_operand:SI 4 "const_int_operand" "i")))]
2889 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2892 int shift = INTVAL (operands[4]) & 31;
2893 int start = INTVAL (operands[2]) & 31;
2894 int size = INTVAL (operands[1]) & 31;
2896 operands[4] = GEN_INT (shift - start - size);
2897 operands[1] = GEN_INT (start + size - 1);
2898 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2900 [(set_attr "type" "insert_word")])
2902 (define_insn "*insvsi_internal2"
2903 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2904 (match_operand:SI 1 "const_int_operand" "i")
2905 (match_operand:SI 2 "const_int_operand" "i"))
2906 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2907 (match_operand:SI 4 "const_int_operand" "i")))]
2908 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2911 int shift = INTVAL (operands[4]) & 31;
2912 int start = INTVAL (operands[2]) & 31;
2913 int size = INTVAL (operands[1]) & 31;
2915 operands[4] = GEN_INT (32 - shift - start - size);
2916 operands[1] = GEN_INT (start + size - 1);
2917 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2919 [(set_attr "type" "insert_word")])
2921 (define_insn "*insvsi_internal3"
2922 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2923 (match_operand:SI 1 "const_int_operand" "i")
2924 (match_operand:SI 2 "const_int_operand" "i"))
2925 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2926 (match_operand:SI 4 "const_int_operand" "i")))]
2927 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2930 int shift = INTVAL (operands[4]) & 31;
2931 int start = INTVAL (operands[2]) & 31;
2932 int size = INTVAL (operands[1]) & 31;
2934 operands[4] = GEN_INT (32 - shift - start - size);
2935 operands[1] = GEN_INT (start + size - 1);
2936 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2938 [(set_attr "type" "insert_word")])
2940 (define_insn "*insvsi_internal4"
2941 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2942 (match_operand:SI 1 "const_int_operand" "i")
2943 (match_operand:SI 2 "const_int_operand" "i"))
2944 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2945 (match_operand:SI 4 "const_int_operand" "i")
2946 (match_operand:SI 5 "const_int_operand" "i")))]
2947 "INTVAL (operands[4]) >= INTVAL (operands[1])"
2950 int extract_start = INTVAL (operands[5]) & 31;
2951 int extract_size = INTVAL (operands[4]) & 31;
2952 int insert_start = INTVAL (operands[2]) & 31;
2953 int insert_size = INTVAL (operands[1]) & 31;
2955 /* Align extract field with insert field */
2956 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
2957 operands[1] = GEN_INT (insert_start + insert_size - 1);
2958 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
2960 [(set_attr "type" "insert_word")])
2962 ;; combine patterns for rlwimi
2963 (define_insn "*insvsi_internal5"
2964 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2965 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
2966 (match_operand:SI 1 "mask_operand" "i"))
2967 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2968 (match_operand:SI 2 "const_int_operand" "i"))
2969 (match_operand:SI 5 "mask_operand" "i"))))]
2970 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
2973 int me = extract_ME(operands[5]);
2974 int mb = extract_MB(operands[5]);
2975 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
2976 operands[2] = GEN_INT(mb);
2977 operands[1] = GEN_INT(me);
2978 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2980 [(set_attr "type" "insert_word")])
2982 (define_insn "*insvsi_internal6"
2983 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2984 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2985 (match_operand:SI 2 "const_int_operand" "i"))
2986 (match_operand:SI 5 "mask_operand" "i"))
2987 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
2988 (match_operand:SI 1 "mask_operand" "i"))))]
2989 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
2992 int me = extract_ME(operands[5]);
2993 int mb = extract_MB(operands[5]);
2994 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
2995 operands[2] = GEN_INT(mb);
2996 operands[1] = GEN_INT(me);
2997 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2999 [(set_attr "type" "insert_word")])
3001 (define_insn "insvdi"
3002 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3003 (match_operand:SI 1 "const_int_operand" "i")
3004 (match_operand:SI 2 "const_int_operand" "i"))
3005 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3009 int start = INTVAL (operands[2]) & 63;
3010 int size = INTVAL (operands[1]) & 63;
3012 operands[1] = GEN_INT (64 - start - size);
3013 return \"rldimi %0,%3,%H1,%H2\";
3016 (define_insn "*insvdi_internal2"
3017 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3018 (match_operand:SI 1 "const_int_operand" "i")
3019 (match_operand:SI 2 "const_int_operand" "i"))
3020 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3021 (match_operand:SI 4 "const_int_operand" "i")))]
3023 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3026 int shift = INTVAL (operands[4]) & 63;
3027 int start = (INTVAL (operands[2]) & 63) - 32;
3028 int size = INTVAL (operands[1]) & 63;
3030 operands[4] = GEN_INT (64 - shift - start - size);
3031 operands[2] = GEN_INT (start);
3032 operands[1] = GEN_INT (start + size - 1);
3033 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3036 (define_insn "*insvdi_internal3"
3037 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3038 (match_operand:SI 1 "const_int_operand" "i")
3039 (match_operand:SI 2 "const_int_operand" "i"))
3040 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3041 (match_operand:SI 4 "const_int_operand" "i")))]
3043 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3046 int shift = INTVAL (operands[4]) & 63;
3047 int start = (INTVAL (operands[2]) & 63) - 32;
3048 int size = INTVAL (operands[1]) & 63;
3050 operands[4] = GEN_INT (64 - shift - start - size);
3051 operands[2] = GEN_INT (start);
3052 operands[1] = GEN_INT (start + size - 1);
3053 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3056 (define_expand "extzv"
3057 [(set (match_operand 0 "gpc_reg_operand" "")
3058 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3059 (match_operand:SI 2 "const_int_operand" "")
3060 (match_operand:SI 3 "const_int_operand" "")))]
3064 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3065 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3066 compiler if the address of the structure is taken later. */
3067 if (GET_CODE (operands[0]) == SUBREG
3068 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3071 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3072 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3074 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3078 (define_insn "extzvsi"
3079 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3080 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3081 (match_operand:SI 2 "const_int_operand" "i")
3082 (match_operand:SI 3 "const_int_operand" "i")))]
3086 int start = INTVAL (operands[3]) & 31;
3087 int size = INTVAL (operands[2]) & 31;
3089 if (start + size >= 32)
3090 operands[3] = const0_rtx;
3092 operands[3] = GEN_INT (start + size);
3093 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3096 (define_insn "*extzvsi_internal1"
3097 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3098 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3099 (match_operand:SI 2 "const_int_operand" "i,i")
3100 (match_operand:SI 3 "const_int_operand" "i,i"))
3102 (clobber (match_scratch:SI 4 "=r,r"))]
3106 int start = INTVAL (operands[3]) & 31;
3107 int size = INTVAL (operands[2]) & 31;
3109 /* Force split for non-cc0 compare. */
3110 if (which_alternative == 1)
3113 /* If the bit-field being tested fits in the upper or lower half of a
3114 word, it is possible to use andiu. or andil. to test it. This is
3115 useful because the condition register set-use delay is smaller for
3116 andi[ul]. than for rlinm. This doesn't work when the starting bit
3117 position is 0 because the LT and GT bits may be set wrong. */
3119 if ((start > 0 && start + size <= 16) || start >= 16)
3121 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3122 - (1 << (16 - (start & 15) - size))));
3124 return \"{andiu.|andis.} %4,%1,%3\";
3126 return \"{andil.|andi.} %4,%1,%3\";
3129 if (start + size >= 32)
3130 operands[3] = const0_rtx;
3132 operands[3] = GEN_INT (start + size);
3133 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3135 [(set_attr "type" "compare")
3136 (set_attr "length" "4,8")])
3139 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3140 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3141 (match_operand:SI 2 "const_int_operand" "")
3142 (match_operand:SI 3 "const_int_operand" ""))
3144 (clobber (match_scratch:SI 4 ""))]
3147 (zero_extract:SI (match_dup 1) (match_dup 2)
3150 (compare:CC (match_dup 4)
3154 (define_insn "*extzvsi_internal2"
3155 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3156 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3157 (match_operand:SI 2 "const_int_operand" "i,i")
3158 (match_operand:SI 3 "const_int_operand" "i,i"))
3160 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3161 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3165 int start = INTVAL (operands[3]) & 31;
3166 int size = INTVAL (operands[2]) & 31;
3168 /* Force split for non-cc0 compare. */
3169 if (which_alternative == 1)
3172 /* Since we are using the output value, we can't ignore any need for
3173 a shift. The bit-field must end at the LSB. */
3174 if (start >= 16 && start + size == 32)
3176 operands[3] = GEN_INT ((1 << size) - 1);
3177 return \"{andil.|andi.} %0,%1,%3\";
3180 if (start + size >= 32)
3181 operands[3] = const0_rtx;
3183 operands[3] = GEN_INT (start + size);
3184 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3186 [(set_attr "type" "compare")
3187 (set_attr "length" "4,8")])
3190 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3191 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3192 (match_operand:SI 2 "const_int_operand" "")
3193 (match_operand:SI 3 "const_int_operand" ""))
3195 (set (match_operand:SI 0 "gpc_reg_operand" "")
3196 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3199 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3201 (compare:CC (match_dup 0)
3205 (define_insn "extzvdi"
3206 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3207 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3208 (match_operand:SI 2 "const_int_operand" "i")
3209 (match_operand:SI 3 "const_int_operand" "i")))]
3213 int start = INTVAL (operands[3]) & 63;
3214 int size = INTVAL (operands[2]) & 63;
3216 if (start + size >= 64)
3217 operands[3] = const0_rtx;
3219 operands[3] = GEN_INT (start + size);
3220 operands[2] = GEN_INT (64 - size);
3221 return \"rldicl %0,%1,%3,%2\";
3224 (define_insn "*extzvdi_internal1"
3225 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3226 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3227 (match_operand:SI 2 "const_int_operand" "i")
3228 (match_operand:SI 3 "const_int_operand" "i"))
3230 (clobber (match_scratch:DI 4 "=r"))]
3234 int start = INTVAL (operands[3]) & 63;
3235 int size = INTVAL (operands[2]) & 63;
3237 if (start + size >= 64)
3238 operands[3] = const0_rtx;
3240 operands[3] = GEN_INT (start + size);
3241 operands[2] = GEN_INT (64 - size);
3242 return \"rldicl. %4,%1,%3,%2\";
3244 [(set_attr "type" "compare")])
3246 (define_insn "*extzvdi_internal2"
3247 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3248 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3249 (match_operand:SI 2 "const_int_operand" "i")
3250 (match_operand:SI 3 "const_int_operand" "i"))
3252 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3253 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3257 int start = INTVAL (operands[3]) & 63;
3258 int size = INTVAL (operands[2]) & 63;
3260 if (start + size >= 64)
3261 operands[3] = const0_rtx;
3263 operands[3] = GEN_INT (start + size);
3264 operands[2] = GEN_INT (64 - size);
3265 return \"rldicl. %0,%1,%3,%2\";
3267 [(set_attr "type" "compare")])
3269 (define_insn "rotlsi3"
3270 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3271 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3272 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3274 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3276 (define_insn "*rotlsi3_internal2"
3277 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3278 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3279 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3281 (clobber (match_scratch:SI 3 "=r,r"))]
3284 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3286 [(set_attr "type" "delayed_compare")
3287 (set_attr "length" "4,8")])
3290 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3291 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3292 (match_operand:SI 2 "reg_or_cint_operand" ""))
3294 (clobber (match_scratch:SI 3 ""))]
3297 (rotate:SI (match_dup 1) (match_dup 2)))
3299 (compare:CC (match_dup 3)
3303 (define_insn "*rotlsi3_internal3"
3304 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3305 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3306 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3308 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3309 (rotate:SI (match_dup 1) (match_dup 2)))]
3312 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3314 [(set_attr "type" "delayed_compare")
3315 (set_attr "length" "4,8")])
3318 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3319 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3320 (match_operand:SI 2 "reg_or_cint_operand" ""))
3322 (set (match_operand:SI 0 "gpc_reg_operand" "")
3323 (rotate:SI (match_dup 1) (match_dup 2)))]
3326 (rotate:SI (match_dup 1) (match_dup 2)))
3328 (compare:CC (match_dup 0)
3332 (define_insn "*rotlsi3_internal4"
3333 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3334 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3335 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3336 (match_operand:SI 3 "mask_operand" "n")))]
3338 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3340 (define_insn "*rotlsi3_internal5"
3341 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3343 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3344 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3345 (match_operand:SI 3 "mask_operand" "n,n"))
3347 (clobber (match_scratch:SI 4 "=r,r"))]
3350 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3352 [(set_attr "type" "delayed_compare")
3353 (set_attr "length" "4,8")])
3356 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3358 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3359 (match_operand:SI 2 "reg_or_cint_operand" ""))
3360 (match_operand:SI 3 "mask_operand" ""))
3362 (clobber (match_scratch:SI 4 ""))]
3365 (and:SI (rotate:SI (match_dup 1)
3369 (compare:CC (match_dup 4)
3373 (define_insn "*rotlsi3_internal6"
3374 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3376 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3377 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3378 (match_operand:SI 3 "mask_operand" "n,n"))
3380 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3381 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3384 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3386 [(set_attr "type" "delayed_compare")
3387 (set_attr "length" "4,8")])
3390 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3392 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3393 (match_operand:SI 2 "reg_or_cint_operand" ""))
3394 (match_operand:SI 3 "mask_operand" ""))
3396 (set (match_operand:SI 0 "gpc_reg_operand" "")
3397 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3400 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3402 (compare:CC (match_dup 0)
3406 (define_insn "*rotlsi3_internal7"
3407 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3410 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3411 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3413 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3415 (define_insn "*rotlsi3_internal8"
3416 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3417 (compare:CC (zero_extend:SI
3419 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3420 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3422 (clobber (match_scratch:SI 3 "=r,r"))]
3425 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3427 [(set_attr "type" "delayed_compare")
3428 (set_attr "length" "4,8")])
3431 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3432 (compare:CC (zero_extend:SI
3434 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3435 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3437 (clobber (match_scratch:SI 3 ""))]
3440 (zero_extend:SI (subreg:QI
3441 (rotate:SI (match_dup 1)
3444 (compare:CC (match_dup 3)
3448 (define_insn "*rotlsi3_internal9"
3449 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3450 (compare:CC (zero_extend:SI
3452 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3453 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3455 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3456 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3459 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3461 [(set_attr "type" "delayed_compare")
3462 (set_attr "length" "4,8")])
3465 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3466 (compare:CC (zero_extend:SI
3468 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3469 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3471 (set (match_operand:SI 0 "gpc_reg_operand" "")
3472 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3475 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3477 (compare:CC (match_dup 0)
3481 (define_insn "*rotlsi3_internal10"
3482 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3485 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3486 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3488 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
3490 (define_insn "*rotlsi3_internal11"
3491 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3492 (compare:CC (zero_extend:SI
3494 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3495 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3497 (clobber (match_scratch:SI 3 "=r,r"))]
3500 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
3502 [(set_attr "type" "delayed_compare")
3503 (set_attr "length" "4,8")])
3506 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3507 (compare:CC (zero_extend:SI
3509 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3510 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3512 (clobber (match_scratch:SI 3 ""))]
3515 (zero_extend:SI (subreg:HI
3516 (rotate:SI (match_dup 1)
3519 (compare:CC (match_dup 3)
3523 (define_insn "*rotlsi3_internal12"
3524 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3525 (compare:CC (zero_extend:SI
3527 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3528 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3530 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3531 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3534 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
3536 [(set_attr "type" "delayed_compare")
3537 (set_attr "length" "4,8")])
3540 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3541 (compare:CC (zero_extend:SI
3543 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3544 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3546 (set (match_operand:SI 0 "gpc_reg_operand" "")
3547 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3550 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3552 (compare:CC (match_dup 0)
3556 ;; Note that we use "sle." instead of "sl." so that we can set
3557 ;; SHIFT_COUNT_TRUNCATED.
3559 (define_expand "ashlsi3"
3560 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3561 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3562 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3567 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
3569 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
3573 (define_insn "ashlsi3_power"
3574 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3575 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3576 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3577 (clobber (match_scratch:SI 3 "=q,X"))]
3581 {sli|slwi} %0,%1,%h2")
3583 (define_insn "ashlsi3_no_power"
3584 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3585 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3586 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3588 "{sl|slw}%I2 %0,%1,%h2")
3591 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3592 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3593 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3595 (clobber (match_scratch:SI 3 "=r,r,r,r"))
3596 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3600 {sli.|slwi.} %3,%1,%h2
3603 [(set_attr "type" "delayed_compare")
3604 (set_attr "length" "4,4,8,8")])
3607 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3608 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3609 (match_operand:SI 2 "reg_or_cint_operand" ""))
3611 (clobber (match_scratch:SI 3 ""))
3612 (clobber (match_scratch:SI 4 ""))]
3613 "TARGET_POWER && reload_completed"
3614 [(parallel [(set (match_dup 3)
3615 (ashift:SI (match_dup 1) (match_dup 2)))
3616 (clobber (match_dup 4))])
3618 (compare:CC (match_dup 3)
3623 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3624 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3625 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3627 (clobber (match_scratch:SI 3 "=r,r"))]
3628 "! TARGET_POWER && TARGET_32BIT"
3630 {sl|slw}%I2. %3,%1,%h2
3632 [(set_attr "type" "delayed_compare")
3633 (set_attr "length" "4,8")])
3636 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3637 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3638 (match_operand:SI 2 "reg_or_cint_operand" ""))
3640 (clobber (match_scratch:SI 3 ""))]
3641 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3643 (ashift:SI (match_dup 1) (match_dup 2)))
3645 (compare:CC (match_dup 3)
3650 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3651 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3652 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3654 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3655 (ashift:SI (match_dup 1) (match_dup 2)))
3656 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3660 {sli.|slwi.} %0,%1,%h2
3663 [(set_attr "type" "delayed_compare")
3664 (set_attr "length" "4,4,8,8")])
3667 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3668 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3669 (match_operand:SI 2 "reg_or_cint_operand" ""))
3671 (set (match_operand:SI 0 "gpc_reg_operand" "")
3672 (ashift:SI (match_dup 1) (match_dup 2)))
3673 (clobber (match_scratch:SI 4 ""))]
3674 "TARGET_POWER && reload_completed"
3675 [(parallel [(set (match_dup 0)
3676 (ashift:SI (match_dup 1) (match_dup 2)))
3677 (clobber (match_dup 4))])
3679 (compare:CC (match_dup 0)
3684 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3685 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3686 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3688 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3689 (ashift:SI (match_dup 1) (match_dup 2)))]
3690 "! TARGET_POWER && TARGET_32BIT"
3692 {sl|slw}%I2. %0,%1,%h2
3694 [(set_attr "type" "delayed_compare")
3695 (set_attr "length" "4,8")])
3698 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3699 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3700 (match_operand:SI 2 "reg_or_cint_operand" ""))
3702 (set (match_operand:SI 0 "gpc_reg_operand" "")
3703 (ashift:SI (match_dup 1) (match_dup 2)))]
3704 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3706 (ashift:SI (match_dup 1) (match_dup 2)))
3708 (compare:CC (match_dup 0)
3712 (define_insn "rlwinm"
3713 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3714 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3715 (match_operand:SI 2 "const_int_operand" "i"))
3716 (match_operand:SI 3 "mask_operand" "n")))]
3717 "includes_lshift_p (operands[2], operands[3])"
3718 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
3721 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3723 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3724 (match_operand:SI 2 "const_int_operand" "i,i"))
3725 (match_operand:SI 3 "mask_operand" "n,n"))
3727 (clobber (match_scratch:SI 4 "=r,r"))]
3728 "includes_lshift_p (operands[2], operands[3])"
3730 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3732 [(set_attr "type" "delayed_compare")
3733 (set_attr "length" "4,8")])
3736 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3738 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3739 (match_operand:SI 2 "const_int_operand" ""))
3740 (match_operand:SI 3 "mask_operand" ""))
3742 (clobber (match_scratch:SI 4 ""))]
3743 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3745 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3748 (compare:CC (match_dup 4)
3753 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3755 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3756 (match_operand:SI 2 "const_int_operand" "i,i"))
3757 (match_operand:SI 3 "mask_operand" "n,n"))
3759 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3760 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3761 "includes_lshift_p (operands[2], operands[3])"
3763 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3765 [(set_attr "type" "delayed_compare")
3766 (set_attr "length" "4,8")])
3769 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3771 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3772 (match_operand:SI 2 "const_int_operand" ""))
3773 (match_operand:SI 3 "mask_operand" ""))
3775 (set (match_operand:SI 0 "gpc_reg_operand" "")
3776 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3777 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3779 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3781 (compare:CC (match_dup 0)
3785 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
3787 (define_expand "lshrsi3"
3788 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3789 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3790 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3795 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
3797 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
3801 (define_insn "lshrsi3_power"
3802 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3803 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
3804 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
3805 (clobber (match_scratch:SI 3 "=q,X,X"))]
3810 {s%A2i|s%A2wi} %0,%1,%h2")
3812 (define_insn "lshrsi3_no_power"
3813 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3814 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3815 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
3819 {sr|srw}%I2 %0,%1,%h2")
3822 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3823 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3824 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3826 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
3827 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3832 {s%A2i.|s%A2wi.} %3,%1,%h2
3836 [(set_attr "type" "delayed_compare")
3837 (set_attr "length" "4,4,4,8,8,8")])
3840 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3841 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3842 (match_operand:SI 2 "reg_or_cint_operand" ""))
3844 (clobber (match_scratch:SI 3 ""))
3845 (clobber (match_scratch:SI 4 ""))]
3846 "TARGET_POWER && reload_completed"
3847 [(parallel [(set (match_dup 3)
3848 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3849 (clobber (match_dup 4))])
3851 (compare:CC (match_dup 3)
3856 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3857 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3858 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3860 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
3861 "! TARGET_POWER && TARGET_32BIT"
3864 {sr|srw}%I2. %3,%1,%h2
3867 [(set_attr "type" "delayed_compare")
3868 (set_attr "length" "4,4,8,8")])
3871 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3872 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3873 (match_operand:SI 2 "reg_or_cint_operand" ""))
3875 (clobber (match_scratch:SI 3 ""))]
3876 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3878 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3880 (compare:CC (match_dup 3)
3885 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3886 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3887 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3889 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
3890 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3891 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3896 {s%A2i.|s%A2wi.} %0,%1,%h2
3900 [(set_attr "type" "delayed_compare")
3901 (set_attr "length" "4,4,4,8,8,8")])
3904 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3905 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3906 (match_operand:SI 2 "reg_or_cint_operand" ""))
3908 (set (match_operand:SI 0 "gpc_reg_operand" "")
3909 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3910 (clobber (match_scratch:SI 4 ""))]
3911 "TARGET_POWER && reload_completed"
3912 [(parallel [(set (match_dup 0)
3913 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3914 (clobber (match_dup 4))])
3916 (compare:CC (match_dup 0)
3921 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3922 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3923 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3925 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3926 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3927 "! TARGET_POWER && TARGET_32BIT"
3930 {sr|srw}%I2. %0,%1,%h2
3933 [(set_attr "type" "delayed_compare")
3934 (set_attr "length" "4,4,8,8")])
3937 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3938 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3939 (match_operand:SI 2 "reg_or_cint_operand" ""))
3941 (set (match_operand:SI 0 "gpc_reg_operand" "")
3942 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3943 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3945 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3947 (compare:CC (match_dup 0)
3952 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3953 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3954 (match_operand:SI 2 "const_int_operand" "i"))
3955 (match_operand:SI 3 "mask_operand" "n")))]
3956 "includes_rshift_p (operands[2], operands[3])"
3957 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
3960 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3962 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3963 (match_operand:SI 2 "const_int_operand" "i,i"))
3964 (match_operand:SI 3 "mask_operand" "n,n"))
3966 (clobber (match_scratch:SI 4 "=r,r"))]
3967 "includes_rshift_p (operands[2], operands[3])"
3969 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
3971 [(set_attr "type" "delayed_compare")
3972 (set_attr "length" "4,8")])
3975 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3977 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3978 (match_operand:SI 2 "const_int_operand" ""))
3979 (match_operand:SI 3 "mask_operand" ""))
3981 (clobber (match_scratch:SI 4 ""))]
3982 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
3984 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
3987 (compare:CC (match_dup 4)
3992 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3994 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3995 (match_operand:SI 2 "const_int_operand" "i,i"))
3996 (match_operand:SI 3 "mask_operand" "n,n"))
3998 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3999 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4000 "includes_rshift_p (operands[2], operands[3])"
4002 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4004 [(set_attr "type" "delayed_compare")
4005 (set_attr "length" "4,8")])
4008 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4010 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4011 (match_operand:SI 2 "const_int_operand" ""))
4012 (match_operand:SI 3 "mask_operand" ""))
4014 (set (match_operand:SI 0 "gpc_reg_operand" "")
4015 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4016 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4018 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4020 (compare:CC (match_dup 0)
4025 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4028 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4029 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4030 "includes_rshift_p (operands[2], GEN_INT (255))"
4031 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4034 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4038 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4039 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4041 (clobber (match_scratch:SI 3 "=r,r"))]
4042 "includes_rshift_p (operands[2], GEN_INT (255))"
4044 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4046 [(set_attr "type" "delayed_compare")
4047 (set_attr "length" "4,8")])
4050 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4054 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4055 (match_operand:SI 2 "const_int_operand" "")) 0))
4057 (clobber (match_scratch:SI 3 ""))]
4058 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4060 (zero_extend:SI (subreg:QI
4061 (lshiftrt:SI (match_dup 1)
4064 (compare:CC (match_dup 3)
4069 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4073 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4074 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4076 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4077 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4078 "includes_rshift_p (operands[2], GEN_INT (255))"
4080 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4082 [(set_attr "type" "delayed_compare")
4083 (set_attr "length" "4,8")])
4086 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4090 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4091 (match_operand:SI 2 "const_int_operand" "")) 0))
4093 (set (match_operand:SI 0 "gpc_reg_operand" "")
4094 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4095 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4097 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4099 (compare:CC (match_dup 0)
4104 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4107 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4108 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4109 "includes_rshift_p (operands[2], GEN_INT (65535))"
4110 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4113 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4117 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4118 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4120 (clobber (match_scratch:SI 3 "=r,r"))]
4121 "includes_rshift_p (operands[2], GEN_INT (65535))"
4123 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4125 [(set_attr "type" "delayed_compare")
4126 (set_attr "length" "4,8")])
4129 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4133 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4134 (match_operand:SI 2 "const_int_operand" "")) 0))
4136 (clobber (match_scratch:SI 3 ""))]
4137 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4139 (zero_extend:SI (subreg:HI
4140 (lshiftrt:SI (match_dup 1)
4143 (compare:CC (match_dup 3)
4148 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4152 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4153 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4155 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4156 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4157 "includes_rshift_p (operands[2], GEN_INT (65535))"
4159 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4161 [(set_attr "type" "delayed_compare")
4162 (set_attr "length" "4,8")])
4165 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4169 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4170 (match_operand:SI 2 "const_int_operand" "")) 0))
4172 (set (match_operand:SI 0 "gpc_reg_operand" "")
4173 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4174 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4176 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4178 (compare:CC (match_dup 0)
4183 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4185 (match_operand:SI 1 "gpc_reg_operand" "r"))
4186 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4192 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4194 (match_operand:SI 1 "gpc_reg_operand" "r"))
4195 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4201 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4203 (match_operand:SI 1 "gpc_reg_operand" "r"))
4204 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4210 (define_expand "ashrsi3"
4211 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4212 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4213 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4218 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4220 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4224 (define_insn "ashrsi3_power"
4225 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4226 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4227 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4228 (clobber (match_scratch:SI 3 "=q,X"))]
4232 {srai|srawi} %0,%1,%h2")
4234 (define_insn "ashrsi3_no_power"
4235 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4236 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4237 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4239 "{sra|sraw}%I2 %0,%1,%h2")
4242 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4243 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4244 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4246 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4247 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4251 {srai.|srawi.} %3,%1,%h2
4254 [(set_attr "type" "delayed_compare")
4255 (set_attr "length" "4,4,8,8")])
4258 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4259 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4260 (match_operand:SI 2 "reg_or_cint_operand" ""))
4262 (clobber (match_scratch:SI 3 ""))
4263 (clobber (match_scratch:SI 4 ""))]
4264 "TARGET_POWER && reload_completed"
4265 [(parallel [(set (match_dup 3)
4266 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4267 (clobber (match_dup 4))])
4269 (compare:CC (match_dup 3)
4274 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4275 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4276 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4278 (clobber (match_scratch:SI 3 "=r,r"))]
4281 {sra|sraw}%I2. %3,%1,%h2
4283 [(set_attr "type" "delayed_compare")
4284 (set_attr "length" "4,8")])
4287 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4288 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4289 (match_operand:SI 2 "reg_or_cint_operand" ""))
4291 (clobber (match_scratch:SI 3 ""))]
4292 "! TARGET_POWER && reload_completed"
4294 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4296 (compare:CC (match_dup 3)
4301 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4302 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4303 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4305 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4306 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4307 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4311 {srai.|srawi.} %0,%1,%h2
4314 [(set_attr "type" "delayed_compare")
4315 (set_attr "length" "4,4,8,8")])
4318 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4319 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4320 (match_operand:SI 2 "reg_or_cint_operand" ""))
4322 (set (match_operand:SI 0 "gpc_reg_operand" "")
4323 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4324 (clobber (match_scratch:SI 4 ""))]
4325 "TARGET_POWER && reload_completed"
4326 [(parallel [(set (match_dup 0)
4327 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4328 (clobber (match_dup 4))])
4330 (compare:CC (match_dup 0)
4335 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4336 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4337 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4339 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4340 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4343 {sra|sraw}%I2. %0,%1,%h2
4345 [(set_attr "type" "delayed_compare")
4346 (set_attr "length" "4,8")])
4349 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4350 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4351 (match_operand:SI 2 "reg_or_cint_operand" ""))
4353 (set (match_operand:SI 0 "gpc_reg_operand" "")
4354 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4355 "! TARGET_POWER && reload_completed"
4357 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4359 (compare:CC (match_dup 0)
4363 ;; Floating-point insns, excluding normal data motion.
4365 ;; PowerPC has a full set of single-precision floating point instructions.
4367 ;; For the POWER architecture, we pretend that we have both SFmode and
4368 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4369 ;; The only conversions we will do will be when storing to memory. In that
4370 ;; case, we will use the "frsp" instruction before storing.
4372 ;; Note that when we store into a single-precision memory location, we need to
4373 ;; use the frsp insn first. If the register being stored isn't dead, we
4374 ;; need a scratch register for the frsp. But this is difficult when the store
4375 ;; is done by reload. It is not incorrect to do the frsp on the register in
4376 ;; this case, we just lose precision that we would have otherwise gotten but
4377 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4379 (define_expand "extendsfdf2"
4380 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4381 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4382 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4385 (define_insn_and_split "*extendsfdf2_fpr"
4386 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
4387 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
4388 "TARGET_HARD_FLOAT && TARGET_FPRS"
4393 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4396 emit_note (NOTE_INSN_DELETED);
4399 [(set_attr "type" "fp,fp,fpload")])
4401 (define_expand "truncdfsf2"
4402 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4403 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4404 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4407 (define_insn "*truncdfsf2_fpr"
4408 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4409 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4410 "TARGET_HARD_FLOAT && TARGET_FPRS"
4412 [(set_attr "type" "fp")])
4414 (define_insn "aux_truncdfsf2"
4415 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4416 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
4417 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4419 [(set_attr "type" "fp")])
4421 (define_expand "negsf2"
4422 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4423 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4427 (define_insn "*negsf2"
4428 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4429 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4430 "TARGET_HARD_FLOAT && TARGET_FPRS"
4432 [(set_attr "type" "fp")])
4434 (define_expand "abssf2"
4435 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4436 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4440 (define_insn "*abssf2"
4441 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4442 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4443 "TARGET_HARD_FLOAT && TARGET_FPRS"
4445 [(set_attr "type" "fp")])
4448 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4449 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4450 "TARGET_HARD_FLOAT && TARGET_FPRS"
4452 [(set_attr "type" "fp")])
4454 (define_expand "addsf3"
4455 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4456 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4457 (match_operand:SF 2 "gpc_reg_operand" "")))]
4462 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4463 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4464 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4465 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4467 [(set_attr "type" "fp")])
4470 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4471 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4472 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4473 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4474 "{fa|fadd} %0,%1,%2"
4475 [(set_attr "type" "fp")])
4477 (define_expand "subsf3"
4478 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4479 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4480 (match_operand:SF 2 "gpc_reg_operand" "")))]
4485 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4486 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4487 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4488 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4490 [(set_attr "type" "fp")])
4493 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4494 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4495 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4496 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4497 "{fs|fsub} %0,%1,%2"
4498 [(set_attr "type" "fp")])
4500 (define_expand "mulsf3"
4501 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4502 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4503 (match_operand:SF 2 "gpc_reg_operand" "")))]
4508 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4509 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4510 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4511 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4513 [(set_attr "type" "fp")])
4516 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4517 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4518 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4519 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4520 "{fm|fmul} %0,%1,%2"
4521 [(set_attr "type" "dmul")])
4524 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4525 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
4526 "TARGET_PPC_GFXOPT && flag_finite_math_only"
4528 [(set_attr "type" "fp")])
4530 (define_expand "divsf3"
4531 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4532 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4533 (match_operand:SF 2 "gpc_reg_operand" "")))]
4536 if (swdiv && !optimize_size && TARGET_PPC_GFXOPT
4537 && flag_finite_math_only && !flag_trapping_math)
4539 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
4545 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4546 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4547 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4548 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4550 [(set_attr "type" "sdiv")])
4553 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4554 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4555 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4556 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4557 "{fd|fdiv} %0,%1,%2"
4558 [(set_attr "type" "ddiv")])
4561 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4562 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4563 (match_operand:SF 2 "gpc_reg_operand" "f"))
4564 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4565 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4566 "fmadds %0,%1,%2,%3"
4567 [(set_attr "type" "fp")])
4570 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4571 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4572 (match_operand:SF 2 "gpc_reg_operand" "f"))
4573 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4574 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4575 "{fma|fmadd} %0,%1,%2,%3"
4576 [(set_attr "type" "dmul")])
4579 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4580 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4581 (match_operand:SF 2 "gpc_reg_operand" "f"))
4582 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4583 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4584 "fmsubs %0,%1,%2,%3"
4585 [(set_attr "type" "fp")])
4588 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4589 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4590 (match_operand:SF 2 "gpc_reg_operand" "f"))
4591 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4592 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4593 "{fms|fmsub} %0,%1,%2,%3"
4594 [(set_attr "type" "dmul")])
4597 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4598 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4599 (match_operand:SF 2 "gpc_reg_operand" "f"))
4600 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4601 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4602 && HONOR_SIGNED_ZEROS (SFmode)"
4603 "fnmadds %0,%1,%2,%3"
4604 [(set_attr "type" "fp")])
4607 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4608 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4609 (match_operand:SF 2 "gpc_reg_operand" "f"))
4610 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4611 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4612 && ! HONOR_SIGNED_ZEROS (SFmode)"
4613 "fnmadds %0,%1,%2,%3"
4614 [(set_attr "type" "fp")])
4617 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4618 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4619 (match_operand:SF 2 "gpc_reg_operand" "f"))
4620 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4621 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4622 "{fnma|fnmadd} %0,%1,%2,%3"
4623 [(set_attr "type" "dmul")])
4626 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4627 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4628 (match_operand:SF 2 "gpc_reg_operand" "f"))
4629 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4630 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4631 && ! HONOR_SIGNED_ZEROS (SFmode)"
4632 "{fnma|fnmadd} %0,%1,%2,%3"
4633 [(set_attr "type" "dmul")])
4636 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4637 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4638 (match_operand:SF 2 "gpc_reg_operand" "f"))
4639 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4640 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4641 && HONOR_SIGNED_ZEROS (SFmode)"
4642 "fnmsubs %0,%1,%2,%3"
4643 [(set_attr "type" "fp")])
4646 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4647 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4648 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4649 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4650 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4651 && ! HONOR_SIGNED_ZEROS (SFmode)"
4652 "fnmsubs %0,%1,%2,%3"
4653 [(set_attr "type" "fp")])
4656 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4657 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4658 (match_operand:SF 2 "gpc_reg_operand" "f"))
4659 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4660 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4661 "{fnms|fnmsub} %0,%1,%2,%3"
4662 [(set_attr "type" "dmul")])
4665 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4666 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4667 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4668 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4669 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4670 && ! HONOR_SIGNED_ZEROS (SFmode)"
4671 "{fnms|fnmsub} %0,%1,%2,%3"
4672 [(set_attr "type" "fp")])
4674 (define_expand "sqrtsf2"
4675 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4676 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4677 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4681 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4682 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4683 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4685 [(set_attr "type" "ssqrt")])
4688 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4689 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4690 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
4692 [(set_attr "type" "dsqrt")])
4694 (define_expand "copysignsf3"
4696 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
4698 (neg:SF (abs:SF (match_dup 1))))
4699 (set (match_operand:SF 0 "gpc_reg_operand" "")
4700 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
4704 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4705 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
4707 operands[3] = gen_reg_rtx (SFmode);
4708 operands[4] = gen_reg_rtx (SFmode);
4709 operands[5] = CONST0_RTX (SFmode);
4712 (define_expand "copysigndf3"
4714 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
4716 (neg:DF (abs:DF (match_dup 1))))
4717 (set (match_operand:DF 0 "gpc_reg_operand" "")
4718 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
4722 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4723 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
4725 operands[3] = gen_reg_rtx (DFmode);
4726 operands[4] = gen_reg_rtx (DFmode);
4727 operands[5] = CONST0_RTX (DFmode);
4730 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4731 ;; fsel instruction and some auxiliary computations. Then we just have a
4732 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
4734 (define_expand "smaxsf3"
4735 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4736 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4737 (match_operand:SF 2 "gpc_reg_operand" ""))
4740 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4741 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4743 (define_expand "sminsf3"
4744 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4745 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4746 (match_operand:SF 2 "gpc_reg_operand" ""))
4749 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4750 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4753 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4754 (match_operator:SF 3 "min_max_operator"
4755 [(match_operand:SF 1 "gpc_reg_operand" "")
4756 (match_operand:SF 2 "gpc_reg_operand" "")]))]
4757 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4760 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4761 operands[1], operands[2]);
4765 (define_expand "movsicc"
4766 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4767 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4768 (match_operand:SI 2 "gpc_reg_operand" "")
4769 (match_operand:SI 3 "gpc_reg_operand" "")))]
4773 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4779 ;; We use the BASE_REGS for the isel input operands because, if rA is
4780 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
4781 ;; because we may switch the operands and rB may end up being rA.
4783 ;; We need 2 patterns: an unsigned and a signed pattern. We could
4784 ;; leave out the mode in operand 4 and use one pattern, but reload can
4785 ;; change the mode underneath our feet and then gets confused trying
4786 ;; to reload the value.
4787 (define_insn "isel_signed"
4788 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4790 (match_operator 1 "comparison_operator"
4791 [(match_operand:CC 4 "cc_reg_operand" "y")
4793 (match_operand:SI 2 "gpc_reg_operand" "b")
4794 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4797 { return output_isel (operands); }"
4798 [(set_attr "length" "4")])
4800 (define_insn "isel_unsigned"
4801 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4803 (match_operator 1 "comparison_operator"
4804 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
4806 (match_operand:SI 2 "gpc_reg_operand" "b")
4807 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4810 { return output_isel (operands); }"
4811 [(set_attr "length" "4")])
4813 (define_expand "movsfcc"
4814 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4815 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4816 (match_operand:SF 2 "gpc_reg_operand" "")
4817 (match_operand:SF 3 "gpc_reg_operand" "")))]
4818 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4821 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4827 (define_insn "*fselsfsf4"
4828 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4829 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4830 (match_operand:SF 4 "zero_fp_constant" "F"))
4831 (match_operand:SF 2 "gpc_reg_operand" "f")
4832 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4833 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4835 [(set_attr "type" "fp")])
4837 (define_insn "*fseldfsf4"
4838 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4839 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4840 (match_operand:DF 4 "zero_fp_constant" "F"))
4841 (match_operand:SF 2 "gpc_reg_operand" "f")
4842 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4843 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4845 [(set_attr "type" "fp")])
4847 (define_expand "negdf2"
4848 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4849 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4850 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4853 (define_insn "*negdf2_fpr"
4854 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4855 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4856 "TARGET_HARD_FLOAT && TARGET_FPRS"
4858 [(set_attr "type" "fp")])
4860 (define_expand "absdf2"
4861 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4862 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4863 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4866 (define_insn "*absdf2_fpr"
4867 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4868 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4869 "TARGET_HARD_FLOAT && TARGET_FPRS"
4871 [(set_attr "type" "fp")])
4873 (define_insn "*nabsdf2_fpr"
4874 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4875 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
4876 "TARGET_HARD_FLOAT && TARGET_FPRS"
4878 [(set_attr "type" "fp")])
4880 (define_expand "adddf3"
4881 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4882 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
4883 (match_operand:DF 2 "gpc_reg_operand" "")))]
4884 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4887 (define_insn "*adddf3_fpr"
4888 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4889 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4890 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4891 "TARGET_HARD_FLOAT && TARGET_FPRS"
4892 "{fa|fadd} %0,%1,%2"
4893 [(set_attr "type" "fp")])
4895 (define_expand "subdf3"
4896 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4897 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
4898 (match_operand:DF 2 "gpc_reg_operand" "")))]
4899 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4902 (define_insn "*subdf3_fpr"
4903 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4904 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4905 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4906 "TARGET_HARD_FLOAT && TARGET_FPRS"
4907 "{fs|fsub} %0,%1,%2"
4908 [(set_attr "type" "fp")])
4910 (define_expand "muldf3"
4911 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4912 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
4913 (match_operand:DF 2 "gpc_reg_operand" "")))]
4914 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4917 (define_insn "*muldf3_fpr"
4918 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4919 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4920 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4921 "TARGET_HARD_FLOAT && TARGET_FPRS"
4922 "{fm|fmul} %0,%1,%2"
4923 [(set_attr "type" "dmul")])
4926 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4927 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
4928 "TARGET_POPCNTB && flag_finite_math_only"
4930 [(set_attr "type" "fp")])
4932 (define_expand "divdf3"
4933 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4934 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
4935 (match_operand:DF 2 "gpc_reg_operand" "")))]
4936 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4938 if (swdiv && !optimize_size && TARGET_POPCNTB
4939 && flag_finite_math_only && !flag_trapping_math)
4941 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
4946 (define_insn "*divdf3_fpr"
4947 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4948 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4949 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4950 "TARGET_HARD_FLOAT && TARGET_FPRS"
4951 "{fd|fdiv} %0,%1,%2"
4952 [(set_attr "type" "ddiv")])
4955 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4956 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4957 (match_operand:DF 2 "gpc_reg_operand" "f"))
4958 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4959 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4960 "{fma|fmadd} %0,%1,%2,%3"
4961 [(set_attr "type" "dmul")])
4964 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4965 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4966 (match_operand:DF 2 "gpc_reg_operand" "f"))
4967 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4968 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4969 "{fms|fmsub} %0,%1,%2,%3"
4970 [(set_attr "type" "dmul")])
4973 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4974 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4975 (match_operand:DF 2 "gpc_reg_operand" "f"))
4976 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4977 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4978 && HONOR_SIGNED_ZEROS (DFmode)"
4979 "{fnma|fnmadd} %0,%1,%2,%3"
4980 [(set_attr "type" "dmul")])
4983 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4984 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
4985 (match_operand:DF 2 "gpc_reg_operand" "f"))
4986 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4987 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4988 && ! HONOR_SIGNED_ZEROS (DFmode)"
4989 "{fnma|fnmadd} %0,%1,%2,%3"
4990 [(set_attr "type" "dmul")])
4993 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4994 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4995 (match_operand:DF 2 "gpc_reg_operand" "f"))
4996 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4997 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4998 && HONOR_SIGNED_ZEROS (DFmode)"
4999 "{fnms|fnmsub} %0,%1,%2,%3"
5000 [(set_attr "type" "dmul")])
5003 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5004 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5005 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5006 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5007 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5008 && ! HONOR_SIGNED_ZEROS (DFmode)"
5009 "{fnms|fnmsub} %0,%1,%2,%3"
5010 [(set_attr "type" "dmul")])
5012 (define_insn "sqrtdf2"
5013 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5014 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5015 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5017 [(set_attr "type" "dsqrt")])
5019 ;; The conditional move instructions allow us to perform max and min
5020 ;; operations even when
5022 (define_expand "smaxdf3"
5023 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5024 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5025 (match_operand:DF 2 "gpc_reg_operand" ""))
5028 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5029 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5031 (define_expand "smindf3"
5032 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5033 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5034 (match_operand:DF 2 "gpc_reg_operand" ""))
5037 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5038 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5041 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5042 (match_operator:DF 3 "min_max_operator"
5043 [(match_operand:DF 1 "gpc_reg_operand" "")
5044 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5045 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5048 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5049 operands[1], operands[2]);
5053 (define_expand "movdfcc"
5054 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5055 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5056 (match_operand:DF 2 "gpc_reg_operand" "")
5057 (match_operand:DF 3 "gpc_reg_operand" "")))]
5058 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5061 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5067 (define_insn "*fseldfdf4"
5068 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5069 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5070 (match_operand:DF 4 "zero_fp_constant" "F"))
5071 (match_operand:DF 2 "gpc_reg_operand" "f")
5072 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5073 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5075 [(set_attr "type" "fp")])
5077 (define_insn "*fselsfdf4"
5078 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5079 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5080 (match_operand:SF 4 "zero_fp_constant" "F"))
5081 (match_operand:DF 2 "gpc_reg_operand" "f")
5082 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5085 [(set_attr "type" "fp")])
5087 ;; Conversions to and from floating-point.
5089 (define_expand "fixuns_truncsfsi2"
5090 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5091 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5092 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5095 (define_expand "fix_truncsfsi2"
5096 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5097 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5098 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5101 ; For each of these conversions, there is a define_expand, a define_insn
5102 ; with a '#' template, and a define_split (with C code). The idea is
5103 ; to allow constant folding with the template of the define_insn,
5104 ; then to have the insns split later (between sched1 and final).
5106 (define_expand "floatsidf2"
5107 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5108 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5111 (clobber (match_dup 4))
5112 (clobber (match_dup 5))
5113 (clobber (match_dup 6))])]
5114 "TARGET_HARD_FLOAT && TARGET_FPRS"
5117 if (TARGET_E500_DOUBLE)
5119 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5122 if (TARGET_POWERPC64)
5124 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5125 rtx t1 = gen_reg_rtx (DImode);
5126 rtx t2 = gen_reg_rtx (DImode);
5127 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5131 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5132 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5133 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5134 operands[5] = gen_reg_rtx (DFmode);
5135 operands[6] = gen_reg_rtx (SImode);
5138 (define_insn_and_split "*floatsidf2_internal"
5139 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5140 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5141 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5142 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5143 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5144 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5145 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5146 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5148 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5152 rtx lowword, highword;
5153 gcc_assert (MEM_P (operands[4]));
5154 highword = adjust_address (operands[4], SImode, 0);
5155 lowword = adjust_address (operands[4], SImode, 4);
5156 if (! WORDS_BIG_ENDIAN)
5159 tmp = highword; highword = lowword; lowword = tmp;
5162 emit_insn (gen_xorsi3 (operands[6], operands[1],
5163 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5164 emit_move_insn (lowword, operands[6]);
5165 emit_move_insn (highword, operands[2]);
5166 emit_move_insn (operands[5], operands[4]);
5167 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5170 [(set_attr "length" "24")])
5172 (define_expand "floatunssisf2"
5173 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5174 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5175 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5178 (define_expand "floatunssidf2"
5179 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5180 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5183 (clobber (match_dup 4))
5184 (clobber (match_dup 5))])]
5185 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5188 if (TARGET_E500_DOUBLE)
5190 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5193 if (TARGET_POWERPC64)
5195 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5196 rtx t1 = gen_reg_rtx (DImode);
5197 rtx t2 = gen_reg_rtx (DImode);
5198 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5203 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5204 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5205 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5206 operands[5] = gen_reg_rtx (DFmode);
5209 (define_insn_and_split "*floatunssidf2_internal"
5210 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5211 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5212 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5213 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5214 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5215 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5216 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5218 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5222 rtx lowword, highword;
5223 gcc_assert (MEM_P (operands[4]));
5224 highword = adjust_address (operands[4], SImode, 0);
5225 lowword = adjust_address (operands[4], SImode, 4);
5226 if (! WORDS_BIG_ENDIAN)
5229 tmp = highword; highword = lowword; lowword = tmp;
5232 emit_move_insn (lowword, operands[1]);
5233 emit_move_insn (highword, operands[2]);
5234 emit_move_insn (operands[5], operands[4]);
5235 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5238 [(set_attr "length" "20")])
5240 (define_expand "fix_truncdfsi2"
5241 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
5242 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5243 (clobber (match_dup 2))
5244 (clobber (match_dup 3))])]
5245 "(TARGET_POWER2 || TARGET_POWERPC)
5246 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5249 if (TARGET_E500_DOUBLE)
5251 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5254 operands[2] = gen_reg_rtx (DImode);
5255 if (TARGET_PPC_GFXOPT)
5257 rtx orig_dest = operands[0];
5258 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
5259 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5260 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5262 if (operands[0] != orig_dest)
5263 emit_move_insn (orig_dest, operands[0]);
5266 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5269 (define_insn_and_split "*fix_truncdfsi2_internal"
5270 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5271 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5272 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5273 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5274 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5276 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[3]))"
5281 gcc_assert (MEM_P (operands[3]));
5282 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5284 emit_insn (gen_fctiwz (operands[2], operands[1]));
5285 emit_move_insn (operands[3], operands[2]);
5286 emit_move_insn (operands[0], lowword);
5289 [(set_attr "length" "16")])
5291 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
5292 [(set (match_operand:SI 0 "memory_operand" "=Z")
5293 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5294 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
5295 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
5296 && TARGET_PPC_GFXOPT"
5302 emit_insn (gen_fctiwz (operands[2], operands[1]));
5303 emit_insn (gen_stfiwx (operands[0], operands[2]));
5306 [(set_attr "length" "16")])
5308 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5309 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5310 ; because the first makes it clear that operand 0 is not live
5311 ; before the instruction.
5312 (define_insn "fctiwz"
5313 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
5314 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5316 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5317 "{fcirz|fctiwz} %0,%1"
5318 [(set_attr "type" "fp")])
5320 ; An UNSPEC is used so we don't have to support SImode in FP registers.
5321 (define_insn "stfiwx"
5322 [(set (match_operand:SI 0 "memory_operand" "=Z")
5323 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
5327 [(set_attr "type" "fpstore")])
5329 (define_expand "floatsisf2"
5330 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5331 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5332 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5335 (define_insn "floatdidf2"
5336 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5337 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
5338 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5340 [(set_attr "type" "fp")])
5342 (define_insn_and_split "floatsidf_ppc64"
5343 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5344 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5345 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5346 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5347 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5348 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5351 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5352 (set (match_dup 2) (match_dup 3))
5353 (set (match_dup 4) (match_dup 2))
5354 (set (match_dup 0) (float:DF (match_dup 4)))]
5357 (define_insn_and_split "floatunssidf_ppc64"
5358 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5359 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5360 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5361 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5362 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5363 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5366 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5367 (set (match_dup 2) (match_dup 3))
5368 (set (match_dup 4) (match_dup 2))
5369 (set (match_dup 0) (float:DF (match_dup 4)))]
5372 (define_insn "fix_truncdfdi2"
5373 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5374 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5375 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5377 [(set_attr "type" "fp")])
5379 (define_expand "floatdisf2"
5380 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5381 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5382 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5385 rtx val = operands[1];
5386 if (!flag_unsafe_math_optimizations)
5388 rtx label = gen_label_rtx ();
5389 val = gen_reg_rtx (DImode);
5390 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
5393 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
5397 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5398 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5399 ;; from double rounding.
5400 (define_insn_and_split "floatdisf2_internal1"
5401 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5402 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
5403 (clobber (match_scratch:DF 2 "=f"))]
5404 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5406 "&& reload_completed"
5408 (float:DF (match_dup 1)))
5410 (float_truncate:SF (match_dup 2)))]
5413 ;; Twiddles bits to avoid double rounding.
5414 ;; Bits that might be truncated when converting to DFmode are replaced
5415 ;; by a bit that won't be lost at that stage, but is below the SFmode
5416 ;; rounding position.
5417 (define_expand "floatdisf2_internal2"
5418 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
5420 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
5422 (clobber (scratch:CC))])
5423 (set (match_dup 3) (plus:DI (match_dup 3)
5425 (set (match_dup 0) (plus:DI (match_dup 0)
5427 (set (match_dup 4) (compare:CCUNS (match_dup 3)
5429 (set (match_dup 0) (ior:DI (match_dup 0)
5431 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
5433 (clobber (scratch:CC))])
5434 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
5435 (label_ref (match_operand:DI 2 "" ""))
5437 (set (match_dup 0) (match_dup 1))]
5438 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5441 operands[3] = gen_reg_rtx (DImode);
5442 operands[4] = gen_reg_rtx (CCUNSmode);
5445 ;; Define the DImode operations that can be done in a small number
5446 ;; of instructions. The & constraints are to prevent the register
5447 ;; allocator from allocating registers that overlap with the inputs
5448 ;; (for example, having an input in 7,8 and an output in 6,7). We
5449 ;; also allow for the output being the same as one of the inputs.
5451 (define_insn "*adddi3_noppc64"
5452 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5453 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5454 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
5455 "! TARGET_POWERPC64"
5458 if (WORDS_BIG_ENDIAN)
5459 return (GET_CODE (operands[2])) != CONST_INT
5460 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5461 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5463 return (GET_CODE (operands[2])) != CONST_INT
5464 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5465 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5467 [(set_attr "type" "two")
5468 (set_attr "length" "8")])
5470 (define_insn "*subdi3_noppc64"
5471 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5472 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5473 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
5474 "! TARGET_POWERPC64"
5477 if (WORDS_BIG_ENDIAN)
5478 return (GET_CODE (operands[1]) != CONST_INT)
5479 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
5480 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
5482 return (GET_CODE (operands[1]) != CONST_INT)
5483 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
5484 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5486 [(set_attr "type" "two")
5487 (set_attr "length" "8")])
5489 (define_insn "*negdi2_noppc64"
5490 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5491 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
5492 "! TARGET_POWERPC64"
5495 return (WORDS_BIG_ENDIAN)
5496 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
5497 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
5499 [(set_attr "type" "two")
5500 (set_attr "length" "8")])
5502 (define_expand "mulsidi3"
5503 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5504 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5505 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5506 "! TARGET_POWERPC64"
5509 if (! TARGET_POWER && ! TARGET_POWERPC)
5511 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5512 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5513 emit_insn (gen_mull_call ());
5514 if (WORDS_BIG_ENDIAN)
5515 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
5518 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
5519 gen_rtx_REG (SImode, 3));
5520 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
5521 gen_rtx_REG (SImode, 4));
5525 else if (TARGET_POWER)
5527 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
5532 (define_insn "mulsidi3_mq"
5533 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5534 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5535 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5536 (clobber (match_scratch:SI 3 "=q"))]
5538 "mul %0,%1,%2\;mfmq %L0"
5539 [(set_attr "type" "imul")
5540 (set_attr "length" "8")])
5542 (define_insn "*mulsidi3_no_mq"
5543 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5544 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5545 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5546 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5549 return (WORDS_BIG_ENDIAN)
5550 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
5551 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
5553 [(set_attr "type" "imul")
5554 (set_attr "length" "8")])
5557 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5558 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5559 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5560 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5563 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
5564 (sign_extend:DI (match_dup 2)))
5567 (mult:SI (match_dup 1)
5571 int endian = (WORDS_BIG_ENDIAN == 0);
5572 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5573 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5576 (define_expand "umulsidi3"
5577 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5578 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5579 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5580 "TARGET_POWERPC && ! TARGET_POWERPC64"
5585 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
5590 (define_insn "umulsidi3_mq"
5591 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5592 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5593 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5594 (clobber (match_scratch:SI 3 "=q"))]
5595 "TARGET_POWERPC && TARGET_POWER"
5598 return (WORDS_BIG_ENDIAN)
5599 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5600 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5602 [(set_attr "type" "imul")
5603 (set_attr "length" "8")])
5605 (define_insn "*umulsidi3_no_mq"
5606 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5607 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5608 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5609 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5612 return (WORDS_BIG_ENDIAN)
5613 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5614 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5616 [(set_attr "type" "imul")
5617 (set_attr "length" "8")])
5620 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5621 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5622 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5623 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5626 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
5627 (zero_extend:DI (match_dup 2)))
5630 (mult:SI (match_dup 1)
5634 int endian = (WORDS_BIG_ENDIAN == 0);
5635 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5636 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5639 (define_expand "smulsi3_highpart"
5640 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5642 (lshiftrt:DI (mult:DI (sign_extend:DI
5643 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5645 (match_operand:SI 2 "gpc_reg_operand" "r")))
5650 if (! TARGET_POWER && ! TARGET_POWERPC)
5652 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5653 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5654 emit_insn (gen_mulh_call ());
5655 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
5658 else if (TARGET_POWER)
5660 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5665 (define_insn "smulsi3_highpart_mq"
5666 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5668 (lshiftrt:DI (mult:DI (sign_extend:DI
5669 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5671 (match_operand:SI 2 "gpc_reg_operand" "r")))
5673 (clobber (match_scratch:SI 3 "=q"))]
5676 [(set_attr "type" "imul")])
5678 (define_insn "*smulsi3_highpart_no_mq"
5679 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5681 (lshiftrt:DI (mult:DI (sign_extend:DI
5682 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5684 (match_operand:SI 2 "gpc_reg_operand" "r")))
5686 "TARGET_POWERPC && ! TARGET_POWER"
5688 [(set_attr "type" "imul")])
5690 (define_expand "umulsi3_highpart"
5691 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5693 (lshiftrt:DI (mult:DI (zero_extend:DI
5694 (match_operand:SI 1 "gpc_reg_operand" ""))
5696 (match_operand:SI 2 "gpc_reg_operand" "")))
5703 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5708 (define_insn "umulsi3_highpart_mq"
5709 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5711 (lshiftrt:DI (mult:DI (zero_extend:DI
5712 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5714 (match_operand:SI 2 "gpc_reg_operand" "r")))
5716 (clobber (match_scratch:SI 3 "=q"))]
5717 "TARGET_POWERPC && TARGET_POWER"
5719 [(set_attr "type" "imul")])
5721 (define_insn "*umulsi3_highpart_no_mq"
5722 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5724 (lshiftrt:DI (mult:DI (zero_extend:DI
5725 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5727 (match_operand:SI 2 "gpc_reg_operand" "r")))
5729 "TARGET_POWERPC && ! TARGET_POWER"
5731 [(set_attr "type" "imul")])
5733 ;; If operands 0 and 2 are in the same register, we have a problem. But
5734 ;; operands 0 and 1 (the usual case) can be in the same register. That's
5735 ;; why we have the strange constraints below.
5736 (define_insn "ashldi3_power"
5737 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5738 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5739 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5740 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5743 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
5744 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5745 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5746 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
5747 [(set_attr "length" "8")])
5749 (define_insn "lshrdi3_power"
5750 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5751 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5752 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5753 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5756 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
5757 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5758 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5759 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
5760 [(set_attr "length" "8")])
5762 ;; Shift by a variable amount is too complex to be worth open-coding. We
5763 ;; just handle shifts by constants.
5764 (define_insn "ashrdi3_power"
5765 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5766 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5767 (match_operand:SI 2 "const_int_operand" "M,i")))
5768 (clobber (match_scratch:SI 3 "=X,q"))]
5771 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5772 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
5773 [(set_attr "length" "8")])
5775 (define_insn "ashrdi3_no_power"
5776 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
5777 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5778 (match_operand:SI 2 "const_int_operand" "M,i")))]
5779 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
5781 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5782 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
5783 [(set_attr "type" "two,three")
5784 (set_attr "length" "8,12")])
5786 (define_insn "*ashrdisi3_noppc64"
5787 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5788 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5789 (const_int 32)) 4))]
5790 "TARGET_32BIT && !TARGET_POWERPC64"
5793 if (REGNO (operands[0]) == REGNO (operands[1]))
5796 return \"mr %0,%1\";
5798 [(set_attr "length" "4")])
5801 ;; PowerPC64 DImode operations.
5803 (define_insn_and_split "absdi2"
5804 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5805 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
5806 (clobber (match_scratch:DI 2 "=&r,&r"))]
5809 "&& reload_completed"
5810 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5811 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5812 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
5815 (define_insn_and_split "*nabsdi2"
5816 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5817 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
5818 (clobber (match_scratch:DI 2 "=&r,&r"))]
5821 "&& reload_completed"
5822 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5823 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5824 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
5827 (define_insn "muldi3"
5828 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5829 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
5830 (match_operand:DI 2 "gpc_reg_operand" "r")))]
5833 [(set_attr "type" "lmul")])
5835 (define_insn "*muldi3_internal1"
5836 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5837 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
5838 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5840 (clobber (match_scratch:DI 3 "=r,r"))]
5845 [(set_attr "type" "lmul_compare")
5846 (set_attr "length" "4,8")])
5849 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5850 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
5851 (match_operand:DI 2 "gpc_reg_operand" ""))
5853 (clobber (match_scratch:DI 3 ""))]
5854 "TARGET_POWERPC64 && reload_completed"
5856 (mult:DI (match_dup 1) (match_dup 2)))
5858 (compare:CC (match_dup 3)
5862 (define_insn "*muldi3_internal2"
5863 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5864 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
5865 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5867 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5868 (mult:DI (match_dup 1) (match_dup 2)))]
5873 [(set_attr "type" "lmul_compare")
5874 (set_attr "length" "4,8")])
5877 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5878 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
5879 (match_operand:DI 2 "gpc_reg_operand" ""))
5881 (set (match_operand:DI 0 "gpc_reg_operand" "")
5882 (mult:DI (match_dup 1) (match_dup 2)))]
5883 "TARGET_POWERPC64 && reload_completed"
5885 (mult:DI (match_dup 1) (match_dup 2)))
5887 (compare:CC (match_dup 0)
5891 (define_insn "smuldi3_highpart"
5892 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5894 (lshiftrt:TI (mult:TI (sign_extend:TI
5895 (match_operand:DI 1 "gpc_reg_operand" "%r"))
5897 (match_operand:DI 2 "gpc_reg_operand" "r")))
5901 [(set_attr "type" "lmul")])
5903 (define_insn "umuldi3_highpart"
5904 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5906 (lshiftrt:TI (mult:TI (zero_extend:TI
5907 (match_operand:DI 1 "gpc_reg_operand" "%r"))
5909 (match_operand:DI 2 "gpc_reg_operand" "r")))
5913 [(set_attr "type" "lmul")])
5915 (define_insn "rotldi3"
5916 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5917 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5918 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
5920 "rld%I2cl %0,%1,%H2,0")
5922 (define_insn "*rotldi3_internal2"
5923 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5924 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5925 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
5927 (clobber (match_scratch:DI 3 "=r,r"))]
5930 rld%I2cl. %3,%1,%H2,0
5932 [(set_attr "type" "delayed_compare")
5933 (set_attr "length" "4,8")])
5936 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5937 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
5938 (match_operand:DI 2 "reg_or_cint_operand" ""))
5940 (clobber (match_scratch:DI 3 ""))]
5941 "TARGET_POWERPC64 && reload_completed"
5943 (rotate:DI (match_dup 1) (match_dup 2)))
5945 (compare:CC (match_dup 3)
5949 (define_insn "*rotldi3_internal3"
5950 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5951 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5952 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
5954 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5955 (rotate:DI (match_dup 1) (match_dup 2)))]
5958 rld%I2cl. %0,%1,%H2,0
5960 [(set_attr "type" "delayed_compare")
5961 (set_attr "length" "4,8")])
5964 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5965 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
5966 (match_operand:DI 2 "reg_or_cint_operand" ""))
5968 (set (match_operand:DI 0 "gpc_reg_operand" "")
5969 (rotate:DI (match_dup 1) (match_dup 2)))]
5970 "TARGET_POWERPC64 && reload_completed"
5972 (rotate:DI (match_dup 1) (match_dup 2)))
5974 (compare:CC (match_dup 0)
5978 (define_insn "*rotldi3_internal4"
5979 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5980 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5981 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
5982 (match_operand:DI 3 "mask_operand" "n")))]
5984 "rld%I2c%B3 %0,%1,%H2,%S3")
5986 (define_insn "*rotldi3_internal5"
5987 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5989 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5990 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
5991 (match_operand:DI 3 "mask_operand" "n,n"))
5993 (clobber (match_scratch:DI 4 "=r,r"))]
5996 rld%I2c%B3. %4,%1,%H2,%S3
5998 [(set_attr "type" "delayed_compare")
5999 (set_attr "length" "4,8")])
6002 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6004 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6005 (match_operand:DI 2 "reg_or_cint_operand" ""))
6006 (match_operand:DI 3 "mask_operand" ""))
6008 (clobber (match_scratch:DI 4 ""))]
6009 "TARGET_POWERPC64 && reload_completed"
6011 (and:DI (rotate:DI (match_dup 1)
6015 (compare:CC (match_dup 4)
6019 (define_insn "*rotldi3_internal6"
6020 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6022 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6023 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6024 (match_operand:DI 3 "mask_operand" "n,n"))
6026 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6027 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6030 rld%I2c%B3. %0,%1,%H2,%S3
6032 [(set_attr "type" "delayed_compare")
6033 (set_attr "length" "4,8")])
6036 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6038 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6039 (match_operand:DI 2 "reg_or_cint_operand" ""))
6040 (match_operand:DI 3 "mask_operand" ""))
6042 (set (match_operand:DI 0 "gpc_reg_operand" "")
6043 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6044 "TARGET_POWERPC64 && reload_completed"
6046 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6048 (compare:CC (match_dup 0)
6052 (define_insn "*rotldi3_internal7"
6053 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6056 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6057 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6059 "rld%I2cl %0,%1,%H2,56")
6061 (define_insn "*rotldi3_internal8"
6062 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6063 (compare:CC (zero_extend:DI
6065 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6066 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6068 (clobber (match_scratch:DI 3 "=r,r"))]
6071 rld%I2cl. %3,%1,%H2,56
6073 [(set_attr "type" "delayed_compare")
6074 (set_attr "length" "4,8")])
6077 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6078 (compare:CC (zero_extend:DI
6080 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6081 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6083 (clobber (match_scratch:DI 3 ""))]
6084 "TARGET_POWERPC64 && reload_completed"
6086 (zero_extend:DI (subreg:QI
6087 (rotate:DI (match_dup 1)
6090 (compare:CC (match_dup 3)
6094 (define_insn "*rotldi3_internal9"
6095 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6096 (compare:CC (zero_extend:DI
6098 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6099 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6101 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6102 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6105 rld%I2cl. %0,%1,%H2,56
6107 [(set_attr "type" "delayed_compare")
6108 (set_attr "length" "4,8")])
6111 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6112 (compare:CC (zero_extend:DI
6114 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6115 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6117 (set (match_operand:DI 0 "gpc_reg_operand" "")
6118 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6119 "TARGET_POWERPC64 && reload_completed"
6121 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6123 (compare:CC (match_dup 0)
6127 (define_insn "*rotldi3_internal10"
6128 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6131 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6132 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6134 "rld%I2cl %0,%1,%H2,48")
6136 (define_insn "*rotldi3_internal11"
6137 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6138 (compare:CC (zero_extend:DI
6140 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6141 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6143 (clobber (match_scratch:DI 3 "=r,r"))]
6146 rld%I2cl. %3,%1,%H2,48
6148 [(set_attr "type" "delayed_compare")
6149 (set_attr "length" "4,8")])
6152 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6153 (compare:CC (zero_extend:DI
6155 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6156 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6158 (clobber (match_scratch:DI 3 ""))]
6159 "TARGET_POWERPC64 && reload_completed"
6161 (zero_extend:DI (subreg:HI
6162 (rotate:DI (match_dup 1)
6165 (compare:CC (match_dup 3)
6169 (define_insn "*rotldi3_internal12"
6170 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6171 (compare:CC (zero_extend:DI
6173 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6174 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6176 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6177 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6180 rld%I2cl. %0,%1,%H2,48
6182 [(set_attr "type" "delayed_compare")
6183 (set_attr "length" "4,8")])
6186 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6187 (compare:CC (zero_extend:DI
6189 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6190 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6192 (set (match_operand:DI 0 "gpc_reg_operand" "")
6193 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6194 "TARGET_POWERPC64 && reload_completed"
6196 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6198 (compare:CC (match_dup 0)
6202 (define_insn "*rotldi3_internal13"
6203 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6206 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6207 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6209 "rld%I2cl %0,%1,%H2,32")
6211 (define_insn "*rotldi3_internal14"
6212 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6213 (compare:CC (zero_extend:DI
6215 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6216 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6218 (clobber (match_scratch:DI 3 "=r,r"))]
6221 rld%I2cl. %3,%1,%H2,32
6223 [(set_attr "type" "delayed_compare")
6224 (set_attr "length" "4,8")])
6227 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6228 (compare:CC (zero_extend:DI
6230 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6231 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6233 (clobber (match_scratch:DI 3 ""))]
6234 "TARGET_POWERPC64 && reload_completed"
6236 (zero_extend:DI (subreg:SI
6237 (rotate:DI (match_dup 1)
6240 (compare:CC (match_dup 3)
6244 (define_insn "*rotldi3_internal15"
6245 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6246 (compare:CC (zero_extend:DI
6248 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6249 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6251 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6252 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6255 rld%I2cl. %0,%1,%H2,32
6257 [(set_attr "type" "delayed_compare")
6258 (set_attr "length" "4,8")])
6261 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6262 (compare:CC (zero_extend:DI
6264 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6265 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6267 (set (match_operand:DI 0 "gpc_reg_operand" "")
6268 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6269 "TARGET_POWERPC64 && reload_completed"
6271 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6273 (compare:CC (match_dup 0)
6277 (define_expand "ashldi3"
6278 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6279 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6280 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6281 "TARGET_POWERPC64 || TARGET_POWER"
6284 if (TARGET_POWERPC64)
6286 else if (TARGET_POWER)
6288 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6295 (define_insn "*ashldi3_internal1"
6296 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6297 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6298 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6302 (define_insn "*ashldi3_internal2"
6303 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6304 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6305 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6307 (clobber (match_scratch:DI 3 "=r,r"))]
6312 [(set_attr "type" "delayed_compare")
6313 (set_attr "length" "4,8")])
6316 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6317 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6318 (match_operand:SI 2 "reg_or_cint_operand" ""))
6320 (clobber (match_scratch:DI 3 ""))]
6321 "TARGET_POWERPC64 && reload_completed"
6323 (ashift:DI (match_dup 1) (match_dup 2)))
6325 (compare:CC (match_dup 3)
6329 (define_insn "*ashldi3_internal3"
6330 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6331 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6332 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6334 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6335 (ashift:DI (match_dup 1) (match_dup 2)))]
6340 [(set_attr "type" "delayed_compare")
6341 (set_attr "length" "4,8")])
6344 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6345 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6346 (match_operand:SI 2 "reg_or_cint_operand" ""))
6348 (set (match_operand:DI 0 "gpc_reg_operand" "")
6349 (ashift:DI (match_dup 1) (match_dup 2)))]
6350 "TARGET_POWERPC64 && reload_completed"
6352 (ashift:DI (match_dup 1) (match_dup 2)))
6354 (compare:CC (match_dup 0)
6358 (define_insn "*ashldi3_internal4"
6359 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6360 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6361 (match_operand:SI 2 "const_int_operand" "i"))
6362 (match_operand:DI 3 "const_int_operand" "n")))]
6363 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6364 "rldic %0,%1,%H2,%W3")
6366 (define_insn "ashldi3_internal5"
6367 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6369 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6370 (match_operand:SI 2 "const_int_operand" "i,i"))
6371 (match_operand:DI 3 "const_int_operand" "n,n"))
6373 (clobber (match_scratch:DI 4 "=r,r"))]
6374 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6376 rldic. %4,%1,%H2,%W3
6378 [(set_attr "type" "delayed_compare")
6379 (set_attr "length" "4,8")])
6382 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6384 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6385 (match_operand:SI 2 "const_int_operand" ""))
6386 (match_operand:DI 3 "const_int_operand" ""))
6388 (clobber (match_scratch:DI 4 ""))]
6389 "TARGET_POWERPC64 && reload_completed
6390 && includes_rldic_lshift_p (operands[2], operands[3])"
6392 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6395 (compare:CC (match_dup 4)
6399 (define_insn "*ashldi3_internal6"
6400 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6402 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6403 (match_operand:SI 2 "const_int_operand" "i,i"))
6404 (match_operand:DI 3 "const_int_operand" "n,n"))
6406 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6407 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6408 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6410 rldic. %0,%1,%H2,%W3
6412 [(set_attr "type" "delayed_compare")
6413 (set_attr "length" "4,8")])
6416 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6418 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6419 (match_operand:SI 2 "const_int_operand" ""))
6420 (match_operand:DI 3 "const_int_operand" ""))
6422 (set (match_operand:DI 0 "gpc_reg_operand" "")
6423 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6424 "TARGET_POWERPC64 && reload_completed
6425 && includes_rldic_lshift_p (operands[2], operands[3])"
6427 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6430 (compare:CC (match_dup 0)
6434 (define_insn "*ashldi3_internal7"
6435 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6436 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6437 (match_operand:SI 2 "const_int_operand" "i"))
6438 (match_operand:DI 3 "mask_operand" "n")))]
6439 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6440 "rldicr %0,%1,%H2,%S3")
6442 (define_insn "ashldi3_internal8"
6443 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6445 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6446 (match_operand:SI 2 "const_int_operand" "i,i"))
6447 (match_operand:DI 3 "mask_operand" "n,n"))
6449 (clobber (match_scratch:DI 4 "=r,r"))]
6450 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6452 rldicr. %4,%1,%H2,%S3
6454 [(set_attr "type" "delayed_compare")
6455 (set_attr "length" "4,8")])
6458 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6460 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6461 (match_operand:SI 2 "const_int_operand" ""))
6462 (match_operand:DI 3 "mask_operand" ""))
6464 (clobber (match_scratch:DI 4 ""))]
6465 "TARGET_POWERPC64 && reload_completed
6466 && includes_rldicr_lshift_p (operands[2], operands[3])"
6468 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6471 (compare:CC (match_dup 4)
6475 (define_insn "*ashldi3_internal9"
6476 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6478 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6479 (match_operand:SI 2 "const_int_operand" "i,i"))
6480 (match_operand:DI 3 "mask_operand" "n,n"))
6482 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6483 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6484 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6486 rldicr. %0,%1,%H2,%S3
6488 [(set_attr "type" "delayed_compare")
6489 (set_attr "length" "4,8")])
6492 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6494 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6495 (match_operand:SI 2 "const_int_operand" ""))
6496 (match_operand:DI 3 "mask_operand" ""))
6498 (set (match_operand:DI 0 "gpc_reg_operand" "")
6499 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6500 "TARGET_POWERPC64 && reload_completed
6501 && includes_rldicr_lshift_p (operands[2], operands[3])"
6503 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6506 (compare:CC (match_dup 0)
6510 (define_expand "lshrdi3"
6511 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6512 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6513 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6514 "TARGET_POWERPC64 || TARGET_POWER"
6517 if (TARGET_POWERPC64)
6519 else if (TARGET_POWER)
6521 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
6528 (define_insn "*lshrdi3_internal1"
6529 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6530 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6531 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6535 (define_insn "*lshrdi3_internal2"
6536 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6537 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6538 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6540 (clobber (match_scratch:DI 3 "=r,r"))]
6545 [(set_attr "type" "delayed_compare")
6546 (set_attr "length" "4,8")])
6549 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6550 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6551 (match_operand:SI 2 "reg_or_cint_operand" ""))
6553 (clobber (match_scratch:DI 3 ""))]
6554 "TARGET_POWERPC64 && reload_completed"
6556 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6558 (compare:CC (match_dup 3)
6562 (define_insn "*lshrdi3_internal3"
6563 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6564 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6565 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6567 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6568 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6573 [(set_attr "type" "delayed_compare")
6574 (set_attr "length" "4,8")])
6577 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6578 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6579 (match_operand:SI 2 "reg_or_cint_operand" ""))
6581 (set (match_operand:DI 0 "gpc_reg_operand" "")
6582 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6583 "TARGET_POWERPC64 && reload_completed"
6585 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6587 (compare:CC (match_dup 0)
6591 (define_expand "ashrdi3"
6592 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6593 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6594 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6598 if (TARGET_POWERPC64)
6600 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
6602 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
6605 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
6606 && WORDS_BIG_ENDIAN)
6608 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
6615 (define_insn "*ashrdi3_internal1"
6616 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6617 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6618 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6620 "srad%I2 %0,%1,%H2")
6622 (define_insn "*ashrdi3_internal2"
6623 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6624 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6625 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6627 (clobber (match_scratch:DI 3 "=r,r"))]
6632 [(set_attr "type" "delayed_compare")
6633 (set_attr "length" "4,8")])
6636 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6637 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6638 (match_operand:SI 2 "reg_or_cint_operand" ""))
6640 (clobber (match_scratch:DI 3 ""))]
6641 "TARGET_POWERPC64 && reload_completed"
6643 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6645 (compare:CC (match_dup 3)
6649 (define_insn "*ashrdi3_internal3"
6650 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6651 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6652 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6654 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6655 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6660 [(set_attr "type" "delayed_compare")
6661 (set_attr "length" "4,8")])
6664 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6665 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6666 (match_operand:SI 2 "reg_or_cint_operand" ""))
6668 (set (match_operand:DI 0 "gpc_reg_operand" "")
6669 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6670 "TARGET_POWERPC64 && reload_completed"
6672 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6674 (compare:CC (match_dup 0)
6678 (define_insn "anddi3"
6679 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
6680 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
6681 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
6682 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
6686 rldic%B2 %0,%1,0,%S2
6687 rlwinm %0,%1,0,%m2,%M2
6691 [(set_attr "type" "*,*,*,compare,compare,*")
6692 (set_attr "length" "4,4,4,4,4,8")])
6695 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6696 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6697 (match_operand:DI 2 "mask64_2_operand" "")))
6698 (clobber (match_scratch:CC 3 ""))]
6700 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
6701 && !mask_operand (operands[2], DImode)"
6703 (and:DI (rotate:DI (match_dup 1)
6707 (and:DI (rotate:DI (match_dup 0)
6711 build_mask64_2_operands (operands[2], &operands[4]);
6714 (define_insn "*anddi3_internal2"
6715 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
6716 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
6717 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
6719 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r"))
6720 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
6724 rldic%B2. %3,%1,0,%S2
6733 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
6734 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
6737 [(set (match_operand:CC 0 "cc_reg_operand" "")
6738 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6739 (match_operand:DI 2 "mask64_2_operand" ""))
6741 (clobber (match_scratch:DI 3 ""))
6742 (clobber (match_scratch:CC 4 ""))]
6743 "TARGET_POWERPC64 && reload_completed
6744 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
6745 && !mask_operand (operands[2], DImode)"
6747 (and:DI (rotate:DI (match_dup 1)
6750 (parallel [(set (match_dup 0)
6751 (compare:CC (and:DI (rotate:DI (match_dup 3)
6755 (clobber (match_dup 3))])]
6758 build_mask64_2_operands (operands[2], &operands[5]);
6761 (define_insn "*anddi3_internal3"
6762 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
6763 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
6764 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
6766 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
6767 (and:DI (match_dup 1) (match_dup 2)))
6768 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
6772 rldic%B2. %0,%1,0,%S2
6781 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
6782 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
6785 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6786 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6787 (match_operand:DI 2 "and_operand" ""))
6789 (set (match_operand:DI 0 "gpc_reg_operand" "")
6790 (and:DI (match_dup 1) (match_dup 2)))
6791 (clobber (match_scratch:CC 4 ""))]
6792 "TARGET_POWERPC64 && reload_completed"
6793 [(parallel [(set (match_dup 0)
6794 (and:DI (match_dup 1) (match_dup 2)))
6795 (clobber (match_dup 4))])
6797 (compare:CC (match_dup 0)
6802 [(set (match_operand:CC 3 "cc_reg_operand" "")
6803 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6804 (match_operand:DI 2 "mask64_2_operand" ""))
6806 (set (match_operand:DI 0 "gpc_reg_operand" "")
6807 (and:DI (match_dup 1) (match_dup 2)))
6808 (clobber (match_scratch:CC 4 ""))]
6809 "TARGET_POWERPC64 && reload_completed
6810 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
6811 && !mask_operand (operands[2], DImode)"
6813 (and:DI (rotate:DI (match_dup 1)
6816 (parallel [(set (match_dup 3)
6817 (compare:CC (and:DI (rotate:DI (match_dup 0)
6822 (and:DI (rotate:DI (match_dup 0)
6827 build_mask64_2_operands (operands[2], &operands[5]);
6830 (define_expand "iordi3"
6831 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6832 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
6833 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
6837 if (non_logical_cint_operand (operands[2], DImode))
6839 HOST_WIDE_INT value;
6840 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
6841 ? operands[0] : gen_reg_rtx (DImode));
6843 if (GET_CODE (operands[2]) == CONST_INT)
6845 value = INTVAL (operands[2]);
6846 emit_insn (gen_iordi3 (tmp, operands[1],
6847 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
6851 value = CONST_DOUBLE_LOW (operands[2]);
6852 emit_insn (gen_iordi3 (tmp, operands[1],
6853 immed_double_const (value
6854 & (~ (HOST_WIDE_INT) 0xffff),
6858 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
6863 (define_expand "xordi3"
6864 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6865 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
6866 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
6870 if (non_logical_cint_operand (operands[2], DImode))
6872 HOST_WIDE_INT value;
6873 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
6874 ? operands[0] : gen_reg_rtx (DImode));
6876 if (GET_CODE (operands[2]) == CONST_INT)
6878 value = INTVAL (operands[2]);
6879 emit_insn (gen_xordi3 (tmp, operands[1],
6880 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
6884 value = CONST_DOUBLE_LOW (operands[2]);
6885 emit_insn (gen_xordi3 (tmp, operands[1],
6886 immed_double_const (value
6887 & (~ (HOST_WIDE_INT) 0xffff),
6891 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
6896 (define_insn "*booldi3_internal1"
6897 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
6898 (match_operator:DI 3 "boolean_or_operator"
6899 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
6900 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
6907 (define_insn "*booldi3_internal2"
6908 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6909 (compare:CC (match_operator:DI 4 "boolean_or_operator"
6910 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
6911 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
6913 (clobber (match_scratch:DI 3 "=r,r"))]
6918 [(set_attr "type" "compare")
6919 (set_attr "length" "4,8")])
6922 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6923 (compare:CC (match_operator:DI 4 "boolean_operator"
6924 [(match_operand:DI 1 "gpc_reg_operand" "")
6925 (match_operand:DI 2 "gpc_reg_operand" "")])
6927 (clobber (match_scratch:DI 3 ""))]
6928 "TARGET_POWERPC64 && reload_completed"
6929 [(set (match_dup 3) (match_dup 4))
6931 (compare:CC (match_dup 3)
6935 (define_insn "*booldi3_internal3"
6936 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6937 (compare:CC (match_operator:DI 4 "boolean_operator"
6938 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
6939 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
6941 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6947 [(set_attr "type" "compare")
6948 (set_attr "length" "4,8")])
6951 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6952 (compare:CC (match_operator:DI 4 "boolean_operator"
6953 [(match_operand:DI 1 "gpc_reg_operand" "")
6954 (match_operand:DI 2 "gpc_reg_operand" "")])
6956 (set (match_operand:DI 0 "gpc_reg_operand" "")
6958 "TARGET_POWERPC64 && reload_completed"
6959 [(set (match_dup 0) (match_dup 4))
6961 (compare:CC (match_dup 0)
6965 ;; Split a logical operation that we can't do in one insn into two insns,
6966 ;; each of which does one 16-bit part. This is used by combine.
6969 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6970 (match_operator:DI 3 "boolean_or_operator"
6971 [(match_operand:DI 1 "gpc_reg_operand" "")
6972 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
6974 [(set (match_dup 0) (match_dup 4))
6975 (set (match_dup 0) (match_dup 5))]
6980 if (GET_CODE (operands[2]) == CONST_DOUBLE)
6982 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
6983 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
6985 i4 = GEN_INT (value & 0xffff);
6989 i3 = GEN_INT (INTVAL (operands[2])
6990 & (~ (HOST_WIDE_INT) 0xffff));
6991 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
6993 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
6995 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
6999 (define_insn "*boolcdi3_internal1"
7000 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7001 (match_operator:DI 3 "boolean_operator"
7002 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7003 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7007 (define_insn "*boolcdi3_internal2"
7008 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7009 (compare:CC (match_operator:DI 4 "boolean_operator"
7010 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7011 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7013 (clobber (match_scratch:DI 3 "=r,r"))]
7018 [(set_attr "type" "compare")
7019 (set_attr "length" "4,8")])
7022 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7023 (compare:CC (match_operator:DI 4 "boolean_operator"
7024 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7025 (match_operand:DI 2 "gpc_reg_operand" "")])
7027 (clobber (match_scratch:DI 3 ""))]
7028 "TARGET_POWERPC64 && reload_completed"
7029 [(set (match_dup 3) (match_dup 4))
7031 (compare:CC (match_dup 3)
7035 (define_insn "*boolcdi3_internal3"
7036 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7037 (compare:CC (match_operator:DI 4 "boolean_operator"
7038 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7039 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7041 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7047 [(set_attr "type" "compare")
7048 (set_attr "length" "4,8")])
7051 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7052 (compare:CC (match_operator:DI 4 "boolean_operator"
7053 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7054 (match_operand:DI 2 "gpc_reg_operand" "")])
7056 (set (match_operand:DI 0 "gpc_reg_operand" "")
7058 "TARGET_POWERPC64 && reload_completed"
7059 [(set (match_dup 0) (match_dup 4))
7061 (compare:CC (match_dup 0)
7065 (define_insn "*boolccdi3_internal1"
7066 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7067 (match_operator:DI 3 "boolean_operator"
7068 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7069 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7073 (define_insn "*boolccdi3_internal2"
7074 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7075 (compare:CC (match_operator:DI 4 "boolean_operator"
7076 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7077 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7079 (clobber (match_scratch:DI 3 "=r,r"))]
7084 [(set_attr "type" "compare")
7085 (set_attr "length" "4,8")])
7088 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7089 (compare:CC (match_operator:DI 4 "boolean_operator"
7090 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7091 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7093 (clobber (match_scratch:DI 3 ""))]
7094 "TARGET_POWERPC64 && reload_completed"
7095 [(set (match_dup 3) (match_dup 4))
7097 (compare:CC (match_dup 3)
7101 (define_insn "*boolccdi3_internal3"
7102 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7103 (compare:CC (match_operator:DI 4 "boolean_operator"
7104 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7105 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7107 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7113 [(set_attr "type" "compare")
7114 (set_attr "length" "4,8")])
7117 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7118 (compare:CC (match_operator:DI 4 "boolean_operator"
7119 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7120 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7122 (set (match_operand:DI 0 "gpc_reg_operand" "")
7124 "TARGET_POWERPC64 && reload_completed"
7125 [(set (match_dup 0) (match_dup 4))
7127 (compare:CC (match_dup 0)
7131 ;; Now define ways of moving data around.
7133 ;; Set up a register with a value from the GOT table
7135 (define_expand "movsi_got"
7136 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7137 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7138 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7139 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7142 if (GET_CODE (operands[1]) == CONST)
7144 rtx offset = const0_rtx;
7145 HOST_WIDE_INT value;
7147 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7148 value = INTVAL (offset);
7151 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7152 emit_insn (gen_movsi_got (tmp, operands[1]));
7153 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7158 operands[2] = rs6000_got_register (operands[1]);
7161 (define_insn "*movsi_got_internal"
7162 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7163 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7164 (match_operand:SI 2 "gpc_reg_operand" "b")]
7166 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7167 "{l|lwz} %0,%a1@got(%2)"
7168 [(set_attr "type" "load")])
7170 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7171 ;; didn't get allocated to a hard register.
7173 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7174 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7175 (match_operand:SI 2 "memory_operand" "")]
7177 "DEFAULT_ABI == ABI_V4
7179 && (reload_in_progress || reload_completed)"
7180 [(set (match_dup 0) (match_dup 2))
7181 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7185 ;; For SI, we special-case integers that can't be loaded in one insn. We
7186 ;; do the load 16-bits at a time. We could do this by loading from memory,
7187 ;; and this is even supposed to be faster, but it is simpler not to get
7188 ;; integers in the TOC.
7189 (define_insn "movsi_low"
7190 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7191 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7192 (match_operand 2 "" ""))))]
7193 "TARGET_MACHO && ! TARGET_64BIT"
7194 "{l|lwz} %0,lo16(%2)(%1)"
7195 [(set_attr "type" "load")
7196 (set_attr "length" "4")])
7198 (define_insn "*movsi_internal1"
7199 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7200 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7201 "gpc_reg_operand (operands[0], SImode)
7202 || gpc_reg_operand (operands[1], SImode)"
7206 {l%U1%X1|lwz%U1%X1} %0,%1
7207 {st%U0%X0|stw%U0%X0} %1,%0
7217 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
7218 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7220 ;; Split a load of a large constant into the appropriate two-insn
7224 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7225 (match_operand:SI 1 "const_int_operand" ""))]
7226 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7227 && (INTVAL (operands[1]) & 0xffff) != 0"
7231 (ior:SI (match_dup 0)
7234 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7236 if (tem == operands[0])
7242 (define_insn "*mov<mode>_internal2"
7243 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7244 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
7246 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7249 {cmpi|cmp<wd>i} %2,%0,0
7252 [(set_attr "type" "cmp,compare,cmp")
7253 (set_attr "length" "4,4,8")])
7256 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7257 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
7259 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
7261 [(set (match_dup 0) (match_dup 1))
7263 (compare:CC (match_dup 0)
7267 (define_insn "*movhi_internal"
7268 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7269 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7270 "gpc_reg_operand (operands[0], HImode)
7271 || gpc_reg_operand (operands[1], HImode)"
7281 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7283 (define_expand "mov<mode>"
7284 [(set (match_operand:INT 0 "general_operand" "")
7285 (match_operand:INT 1 "any_operand" ""))]
7287 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7289 (define_insn "*movqi_internal"
7290 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7291 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7292 "gpc_reg_operand (operands[0], QImode)
7293 || gpc_reg_operand (operands[1], QImode)"
7303 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7305 ;; Here is how to move condition codes around. When we store CC data in
7306 ;; an integer register or memory, we store just the high-order 4 bits.
7307 ;; This lets us not shift in the most common case of CR0.
7308 (define_expand "movcc"
7309 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7310 (match_operand:CC 1 "nonimmediate_operand" ""))]
7314 (define_insn "*movcc_internal1"
7315 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m")
7316 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))]
7317 "register_operand (operands[0], CCmode)
7318 || register_operand (operands[1], CCmode)"
7322 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7324 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7329 {l%U1%X1|lwz%U1%X1} %0,%1
7330 {st%U0%U1|stw%U0%U1} %1,%0"
7332 (cond [(eq_attr "alternative" "0")
7333 (const_string "cr_logical")
7334 (eq_attr "alternative" "1,2")
7335 (const_string "mtcr")
7336 (eq_attr "alternative" "5,7")
7337 (const_string "integer")
7338 (eq_attr "alternative" "6")
7339 (const_string "mfjmpr")
7340 (eq_attr "alternative" "8")
7341 (const_string "mtjmpr")
7342 (eq_attr "alternative" "9")
7343 (const_string "load")
7344 (eq_attr "alternative" "10")
7345 (const_string "store")
7346 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
7347 (const_string "mfcrf")
7349 (const_string "mfcr")))
7350 (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
7352 ;; For floating-point, we normally deal with the floating-point registers
7353 ;; unless -msoft-float is used. The sole exception is that parameter passing
7354 ;; can produce floating-point values in fixed-point registers. Unless the
7355 ;; value is a simple constant or already in memory, we deal with this by
7356 ;; allocating memory and copying the value explicitly via that memory location.
7357 (define_expand "movsf"
7358 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7359 (match_operand:SF 1 "any_operand" ""))]
7361 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7364 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7365 (match_operand:SF 1 "const_double_operand" ""))]
7367 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7368 || (GET_CODE (operands[0]) == SUBREG
7369 && GET_CODE (SUBREG_REG (operands[0])) == REG
7370 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7371 [(set (match_dup 2) (match_dup 3))]
7377 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7378 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7380 if (! TARGET_POWERPC64)
7381 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7383 operands[2] = gen_lowpart (SImode, operands[0]);
7385 operands[3] = gen_int_mode (l, SImode);
7388 (define_insn "*movsf_hardfloat"
7389 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!h,!r,!r")
7390 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
7391 "(gpc_reg_operand (operands[0], SFmode)
7392 || gpc_reg_operand (operands[1], SFmode))
7393 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
7396 {l%U1%X1|lwz%U1%X1} %0,%1
7397 {st%U0%X0|stw%U0%X0} %1,%0
7407 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*")
7408 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
7410 (define_insn "*movsf_softfloat"
7411 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
7412 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
7413 "(gpc_reg_operand (operands[0], SFmode)
7414 || gpc_reg_operand (operands[1], SFmode))
7415 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7421 {l%U1%X1|lwz%U1%X1} %0,%1
7422 {st%U0%X0|stw%U0%X0} %1,%0
7429 [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*")
7430 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
7433 (define_expand "movdf"
7434 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7435 (match_operand:DF 1 "any_operand" ""))]
7437 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
7440 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7441 (match_operand:DF 1 "const_int_operand" ""))]
7442 "! TARGET_POWERPC64 && reload_completed
7443 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7444 || (GET_CODE (operands[0]) == SUBREG
7445 && GET_CODE (SUBREG_REG (operands[0])) == REG
7446 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7447 [(set (match_dup 2) (match_dup 4))
7448 (set (match_dup 3) (match_dup 1))]
7451 int endian = (WORDS_BIG_ENDIAN == 0);
7452 HOST_WIDE_INT value = INTVAL (operands[1]);
7454 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7455 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7456 #if HOST_BITS_PER_WIDE_INT == 32
7457 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7459 operands[4] = GEN_INT (value >> 32);
7460 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7465 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7466 (match_operand:DF 1 "const_double_operand" ""))]
7467 "! TARGET_POWERPC64 && reload_completed
7468 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7469 || (GET_CODE (operands[0]) == SUBREG
7470 && GET_CODE (SUBREG_REG (operands[0])) == REG
7471 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7472 [(set (match_dup 2) (match_dup 4))
7473 (set (match_dup 3) (match_dup 5))]
7476 int endian = (WORDS_BIG_ENDIAN == 0);
7480 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7481 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7483 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7484 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7485 operands[4] = gen_int_mode (l[endian], SImode);
7486 operands[5] = gen_int_mode (l[1 - endian], SImode);
7490 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7491 (match_operand:DF 1 "easy_fp_constant" ""))]
7492 "TARGET_POWERPC64 && reload_completed
7493 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7494 || (GET_CODE (operands[0]) == SUBREG
7495 && GET_CODE (SUBREG_REG (operands[0])) == REG
7496 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7497 [(set (match_dup 2) (match_dup 3))]
7500 int endian = (WORDS_BIG_ENDIAN == 0);
7503 #if HOST_BITS_PER_WIDE_INT >= 64
7507 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7508 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7510 operands[2] = gen_lowpart (DImode, operands[0]);
7511 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
7512 #if HOST_BITS_PER_WIDE_INT >= 64
7513 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
7514 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
7516 operands[3] = gen_int_mode (val, DImode);
7518 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
7522 ;; Don't have reload use general registers to load a constant. First,
7523 ;; it might not work if the output operand is the equivalent of
7524 ;; a non-offsettable memref, but also it is less efficient than loading
7525 ;; the constant into an FP register, since it will probably be used there.
7526 ;; The "??" is a kludge until we can figure out a more reasonable way
7527 ;; of handling these non-offsettable values.
7528 (define_insn "*movdf_hardfloat32"
7529 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
7530 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
7531 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
7532 && (gpc_reg_operand (operands[0], DFmode)
7533 || gpc_reg_operand (operands[1], DFmode))"
7536 switch (which_alternative)
7541 /* We normally copy the low-numbered register first. However, if
7542 the first register operand 0 is the same as the second register
7543 of operand 1, we must copy in the opposite order. */
7544 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7545 return \"mr %L0,%L1\;mr %0,%1\";
7547 return \"mr %0,%1\;mr %L0,%L1\";
7549 if (GET_CODE (operands[1]) == MEM
7550 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[1], 0),
7551 reload_completed || reload_in_progress)
7552 || rs6000_legitimate_small_data_p (DFmode, XEXP (operands[1], 0))
7553 || GET_CODE (XEXP (operands[1], 0)) == REG
7554 || GET_CODE (XEXP (operands[1], 0)) == LO_SUM
7555 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
7556 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))
7558 /* If the low-address word is used in the address, we must load
7559 it last. Otherwise, load it first. Note that we cannot have
7560 auto-increment in that case since the address register is
7561 known to be dead. */
7562 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7564 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7566 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7572 addreg = find_addr_reg (XEXP (operands[1], 0));
7573 if (refers_to_regno_p (REGNO (operands[0]),
7574 REGNO (operands[0]) + 1,
7577 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7578 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
7579 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7580 return \"{lx|lwzx} %0,%1\";
7584 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
7585 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7586 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
7587 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7592 if (GET_CODE (operands[0]) == MEM
7593 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[0], 0),
7594 reload_completed || reload_in_progress)
7595 || rs6000_legitimate_small_data_p (DFmode, XEXP (operands[0], 0))
7596 || GET_CODE (XEXP (operands[0], 0)) == REG
7597 || GET_CODE (XEXP (operands[0], 0)) == LO_SUM
7598 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
7599 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))
7600 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7605 addreg = find_addr_reg (XEXP (operands[0], 0));
7606 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
7607 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7608 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
7609 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7613 return \"fmr %0,%1\";
7615 return \"lfd%U1%X1 %0,%1\";
7617 return \"stfd%U0%X0 %1,%0\";
7624 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
7625 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
7627 (define_insn "*movdf_softfloat32"
7628 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
7629 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
7630 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
7631 && (gpc_reg_operand (operands[0], DFmode)
7632 || gpc_reg_operand (operands[1], DFmode))"
7635 switch (which_alternative)
7640 /* We normally copy the low-numbered register first. However, if
7641 the first register operand 0 is the same as the second register of
7642 operand 1, we must copy in the opposite order. */
7643 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7644 return \"mr %L0,%L1\;mr %0,%1\";
7646 return \"mr %0,%1\;mr %L0,%L1\";
7648 /* If the low-address word is used in the address, we must load
7649 it last. Otherwise, load it first. Note that we cannot have
7650 auto-increment in that case since the address register is
7651 known to be dead. */
7652 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7654 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7656 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7658 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7665 [(set_attr "type" "two,load,store,*,*,*")
7666 (set_attr "length" "8,8,8,8,12,16")])
7668 ; ld/std require word-aligned displacements -> 'Y' constraint.
7669 ; List Y->r and r->Y before r->r for reload.
7670 (define_insn "*movdf_hardfloat64"
7671 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,!cl,!r,!h,!r,!r,!r")
7672 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
7673 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
7674 && (gpc_reg_operand (operands[0], DFmode)
7675 || gpc_reg_operand (operands[1], DFmode))"
7689 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*,*")
7690 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
7692 (define_insn "*movdf_softfloat64"
7693 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
7694 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
7695 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
7696 && (gpc_reg_operand (operands[0], DFmode)
7697 || gpc_reg_operand (operands[1], DFmode))"
7708 [(set_attr "type" "load,store,*,*,*,*,*,*,*")
7709 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
7711 (define_expand "movtf"
7712 [(set (match_operand:TF 0 "general_operand" "")
7713 (match_operand:TF 1 "any_operand" ""))]
7714 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7715 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7716 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
7718 ; It's important to list the o->f and f->o moves before f->f because
7719 ; otherwise reload, given m->f, will try to pick f->f and reload it,
7720 ; which doesn't make progress. Likewise r->Y must be before r->r.
7721 (define_insn_and_split "*movtf_internal"
7722 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
7723 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
7724 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7725 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
7726 && (gpc_reg_operand (operands[0], TFmode)
7727 || gpc_reg_operand (operands[1], TFmode))"
7729 "&& reload_completed"
7731 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
7732 [(set_attr "length" "8,8,8,20,20,16")])
7734 (define_expand "extenddftf2"
7735 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
7736 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
7737 (use (match_dup 2))])]
7738 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7739 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7741 operands[2] = CONST0_RTX (DFmode);
7744 (define_insn_and_split "*extenddftf2_internal"
7745 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
7746 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
7747 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
7748 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7749 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7751 "&& reload_completed"
7754 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
7755 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
7756 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
7758 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
7763 (define_expand "extendsftf2"
7764 [(set (match_operand:TF 0 "nonimmediate_operand" "")
7765 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
7766 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7767 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7769 rtx tmp = gen_reg_rtx (DFmode);
7770 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
7771 emit_insn (gen_extenddftf2 (operands[0], tmp));
7775 (define_expand "trunctfdf2"
7776 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7777 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
7778 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7779 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7782 (define_insn_and_split "trunctfdf2_internal1"
7783 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
7784 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
7785 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
7786 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7790 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
7793 emit_note (NOTE_INSN_DELETED);
7796 [(set_attr "type" "fp")])
7798 (define_insn "trunctfdf2_internal2"
7799 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
7800 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
7801 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
7802 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7804 [(set_attr "type" "fp")])
7806 (define_insn_and_split "trunctfsf2"
7807 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7808 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
7809 (clobber (match_scratch:DF 2 "=f"))]
7810 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7811 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7813 "&& reload_completed"
7815 (float_truncate:DF (match_dup 1)))
7817 (float_truncate:SF (match_dup 2)))]
7820 (define_expand "floatsitf2"
7821 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
7822 (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))]
7823 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7824 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7826 rtx tmp = gen_reg_rtx (DFmode);
7827 expand_float (tmp, operands[1], false);
7828 emit_insn (gen_extenddftf2 (operands[0], tmp));
7832 ; fadd, but rounding towards zero.
7833 ; This is probably not the optimal code sequence.
7834 (define_insn "fix_trunc_helper"
7835 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
7836 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
7837 UNSPEC_FIX_TRUNC_TF))
7838 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
7839 "TARGET_HARD_FLOAT && TARGET_FPRS"
7840 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
7841 [(set_attr "type" "fp")
7842 (set_attr "length" "20")])
7844 (define_expand "fix_trunctfsi2"
7845 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
7846 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
7847 (clobber (match_dup 2))
7848 (clobber (match_dup 3))
7849 (clobber (match_dup 4))
7850 (clobber (match_dup 5))])]
7851 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7852 && (TARGET_POWER2 || TARGET_POWERPC)
7853 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7855 operands[2] = gen_reg_rtx (DFmode);
7856 operands[3] = gen_reg_rtx (DFmode);
7857 operands[4] = gen_reg_rtx (DImode);
7858 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
7861 (define_insn_and_split "*fix_trunctfsi2_internal"
7862 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7863 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
7864 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
7865 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
7866 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
7867 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
7868 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7869 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7871 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[5]))"
7875 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
7877 gcc_assert (MEM_P (operands[5]));
7878 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
7880 emit_insn (gen_fctiwz (operands[4], operands[2]));
7881 emit_move_insn (operands[5], operands[4]);
7882 emit_move_insn (operands[0], lowword);
7886 (define_insn "negtf2"
7887 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
7888 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
7889 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7890 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7893 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7894 return \"fneg %L0,%L1\;fneg %0,%1\";
7896 return \"fneg %0,%1\;fneg %L0,%L1\";
7898 [(set_attr "type" "fp")
7899 (set_attr "length" "8")])
7901 (define_expand "abstf2"
7902 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
7903 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
7904 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7905 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7908 rtx label = gen_label_rtx ();
7909 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
7914 (define_expand "abstf2_internal"
7915 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
7916 (match_operand:TF 1 "gpc_reg_operand" "f"))
7917 (set (match_dup 3) (match_dup 5))
7918 (set (match_dup 5) (abs:DF (match_dup 5)))
7919 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
7920 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
7921 (label_ref (match_operand 2 "" ""))
7923 (set (match_dup 6) (neg:DF (match_dup 6)))]
7924 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7925 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7928 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
7929 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
7930 operands[3] = gen_reg_rtx (DFmode);
7931 operands[4] = gen_reg_rtx (CCFPmode);
7932 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
7933 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
7936 ;; Next come the multi-word integer load and store and the load and store
7939 ; List r->r after r->"o<>", otherwise reload will try to reload a
7940 ; non-offsettable address by using r->r which won't make progress.
7941 (define_insn "*movdi_internal32"
7942 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
7943 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
7945 && (gpc_reg_operand (operands[0], DImode)
7946 || gpc_reg_operand (operands[1], DImode))"
7955 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
7958 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7959 (match_operand:DI 1 "const_int_operand" ""))]
7960 "! TARGET_POWERPC64 && reload_completed"
7961 [(set (match_dup 2) (match_dup 4))
7962 (set (match_dup 3) (match_dup 1))]
7965 HOST_WIDE_INT value = INTVAL (operands[1]);
7966 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
7968 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
7970 #if HOST_BITS_PER_WIDE_INT == 32
7971 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7973 operands[4] = GEN_INT (value >> 32);
7974 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7979 [(set (match_operand:DI 0 "nonimmediate_operand" "")
7980 (match_operand:DI 1 "input_operand" ""))]
7981 "reload_completed && !TARGET_POWERPC64
7982 && gpr_or_gpr_p (operands[0], operands[1])"
7984 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
7986 (define_insn "*movdi_internal64"
7987 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
7988 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
7990 && (gpc_reg_operand (operands[0], DImode)
7991 || gpc_reg_operand (operands[1], DImode))"
8006 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
8007 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8009 ;; immediate value valid for a single instruction hiding in a const_double
8011 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8012 (match_operand:DI 1 "const_double_operand" "F"))]
8013 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8014 && GET_CODE (operands[1]) == CONST_DOUBLE
8015 && num_insns_constant (operands[1], DImode) == 1"
8018 return ((unsigned HOST_WIDE_INT)
8019 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8020 ? \"li %0,%1\" : \"lis %0,%v1\";
8023 ;; Generate all one-bits and clear left or right.
8024 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8026 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8027 (match_operand:DI 1 "mask_operand" ""))]
8028 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8029 [(set (match_dup 0) (const_int -1))
8031 (and:DI (rotate:DI (match_dup 0)
8036 ;; Split a load of a large constant into the appropriate five-instruction
8037 ;; sequence. Handle anything in a constant number of insns.
8038 ;; When non-easy constants can go in the TOC, this should use
8039 ;; easy_fp_constant predicate.
8041 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8042 (match_operand:DI 1 "const_int_operand" ""))]
8043 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8044 [(set (match_dup 0) (match_dup 2))
8045 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8047 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8049 if (tem == operands[0])
8056 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8057 (match_operand:DI 1 "const_double_operand" ""))]
8058 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8059 [(set (match_dup 0) (match_dup 2))
8060 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8062 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8064 if (tem == operands[0])
8070 ;; TImode is similar, except that we usually want to compute the address into
8071 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8072 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8074 ;; We say that MQ is clobbered in the last alternative because the first
8075 ;; alternative would never get used otherwise since it would need a reload
8076 ;; while the 2nd alternative would not. We put memory cases first so they
8077 ;; are preferred. Otherwise, we'd try to reload the output instead of
8078 ;; giving the SCRATCH mq.
8080 (define_insn "*movti_power"
8081 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
8082 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
8083 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
8084 "TARGET_POWER && ! TARGET_POWERPC64
8085 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8088 switch (which_alternative)
8095 return \"{stsi|stswi} %1,%P0,16\";
8100 /* If the address is not used in the output, we can use lsi. Otherwise,
8101 fall through to generating four loads. */
8103 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8104 return \"{lsi|lswi} %0,%P1,16\";
8105 /* ... fall through ... */
8111 [(set_attr "type" "store,store,*,load,load,*")])
8113 (define_insn "*movti_string"
8114 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
8115 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
8116 "! TARGET_POWER && ! TARGET_POWERPC64
8117 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8120 switch (which_alternative)
8126 return \"{stsi|stswi} %1,%P0,16\";
8131 /* If the address is not used in the output, we can use lsi. Otherwise,
8132 fall through to generating four loads. */
8134 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8135 return \"{lsi|lswi} %0,%P1,16\";
8136 /* ... fall through ... */
8142 [(set_attr "type" "store,store,*,load,load,*")])
8144 (define_insn "*movti_ppc64"
8145 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
8146 (match_operand:TI 1 "input_operand" "r,r,m"))]
8147 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8148 || gpc_reg_operand (operands[1], TImode))"
8150 [(set_attr "type" "*,load,store")])
8153 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8154 (match_operand:TI 1 "const_double_operand" ""))]
8156 [(set (match_dup 2) (match_dup 4))
8157 (set (match_dup 3) (match_dup 5))]
8160 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8162 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8164 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8166 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8167 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8169 else if (GET_CODE (operands[1]) == CONST_INT)
8171 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8172 operands[5] = operands[1];
8179 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8180 (match_operand:TI 1 "input_operand" ""))]
8182 && gpr_or_gpr_p (operands[0], operands[1])"
8184 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8186 (define_expand "load_multiple"
8187 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8188 (match_operand:SI 1 "" ""))
8189 (use (match_operand:SI 2 "" ""))])]
8190 "TARGET_STRING && !TARGET_POWERPC64"
8198 /* Support only loading a constant number of fixed-point registers from
8199 memory and only bother with this if more than two; the machine
8200 doesn't support more than eight. */
8201 if (GET_CODE (operands[2]) != CONST_INT
8202 || INTVAL (operands[2]) <= 2
8203 || INTVAL (operands[2]) > 8
8204 || GET_CODE (operands[1]) != MEM
8205 || GET_CODE (operands[0]) != REG
8206 || REGNO (operands[0]) >= 32)
8209 count = INTVAL (operands[2]);
8210 regno = REGNO (operands[0]);
8212 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8213 op1 = replace_equiv_address (operands[1],
8214 force_reg (SImode, XEXP (operands[1], 0)));
8216 for (i = 0; i < count; i++)
8217 XVECEXP (operands[3], 0, i)
8218 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8219 adjust_address_nv (op1, SImode, i * 4));
8222 (define_insn "*ldmsi8"
8223 [(match_parallel 0 "load_multiple_operation"
8224 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8225 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8226 (set (match_operand:SI 3 "gpc_reg_operand" "")
8227 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8228 (set (match_operand:SI 4 "gpc_reg_operand" "")
8229 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8230 (set (match_operand:SI 5 "gpc_reg_operand" "")
8231 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8232 (set (match_operand:SI 6 "gpc_reg_operand" "")
8233 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8234 (set (match_operand:SI 7 "gpc_reg_operand" "")
8235 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8236 (set (match_operand:SI 8 "gpc_reg_operand" "")
8237 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8238 (set (match_operand:SI 9 "gpc_reg_operand" "")
8239 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8240 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8242 { return rs6000_output_load_multiple (operands); }"
8243 [(set_attr "type" "load")
8244 (set_attr "length" "32")])
8246 (define_insn "*ldmsi7"
8247 [(match_parallel 0 "load_multiple_operation"
8248 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8249 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8250 (set (match_operand:SI 3 "gpc_reg_operand" "")
8251 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8252 (set (match_operand:SI 4 "gpc_reg_operand" "")
8253 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8254 (set (match_operand:SI 5 "gpc_reg_operand" "")
8255 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8256 (set (match_operand:SI 6 "gpc_reg_operand" "")
8257 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8258 (set (match_operand:SI 7 "gpc_reg_operand" "")
8259 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8260 (set (match_operand:SI 8 "gpc_reg_operand" "")
8261 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8262 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8264 { return rs6000_output_load_multiple (operands); }"
8265 [(set_attr "type" "load")
8266 (set_attr "length" "32")])
8268 (define_insn "*ldmsi6"
8269 [(match_parallel 0 "load_multiple_operation"
8270 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8271 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8272 (set (match_operand:SI 3 "gpc_reg_operand" "")
8273 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8274 (set (match_operand:SI 4 "gpc_reg_operand" "")
8275 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8276 (set (match_operand:SI 5 "gpc_reg_operand" "")
8277 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8278 (set (match_operand:SI 6 "gpc_reg_operand" "")
8279 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8280 (set (match_operand:SI 7 "gpc_reg_operand" "")
8281 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8282 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8284 { return rs6000_output_load_multiple (operands); }"
8285 [(set_attr "type" "load")
8286 (set_attr "length" "32")])
8288 (define_insn "*ldmsi5"
8289 [(match_parallel 0 "load_multiple_operation"
8290 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8291 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8292 (set (match_operand:SI 3 "gpc_reg_operand" "")
8293 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8294 (set (match_operand:SI 4 "gpc_reg_operand" "")
8295 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8296 (set (match_operand:SI 5 "gpc_reg_operand" "")
8297 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8298 (set (match_operand:SI 6 "gpc_reg_operand" "")
8299 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8300 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8302 { return rs6000_output_load_multiple (operands); }"
8303 [(set_attr "type" "load")
8304 (set_attr "length" "32")])
8306 (define_insn "*ldmsi4"
8307 [(match_parallel 0 "load_multiple_operation"
8308 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8309 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8310 (set (match_operand:SI 3 "gpc_reg_operand" "")
8311 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8312 (set (match_operand:SI 4 "gpc_reg_operand" "")
8313 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8314 (set (match_operand:SI 5 "gpc_reg_operand" "")
8315 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8316 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8318 { return rs6000_output_load_multiple (operands); }"
8319 [(set_attr "type" "load")
8320 (set_attr "length" "32")])
8322 (define_insn "*ldmsi3"
8323 [(match_parallel 0 "load_multiple_operation"
8324 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8325 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8326 (set (match_operand:SI 3 "gpc_reg_operand" "")
8327 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8328 (set (match_operand:SI 4 "gpc_reg_operand" "")
8329 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8330 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8332 { return rs6000_output_load_multiple (operands); }"
8333 [(set_attr "type" "load")
8334 (set_attr "length" "32")])
8336 (define_expand "store_multiple"
8337 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8338 (match_operand:SI 1 "" ""))
8339 (clobber (scratch:SI))
8340 (use (match_operand:SI 2 "" ""))])]
8341 "TARGET_STRING && !TARGET_POWERPC64"
8350 /* Support only storing a constant number of fixed-point registers to
8351 memory and only bother with this if more than two; the machine
8352 doesn't support more than eight. */
8353 if (GET_CODE (operands[2]) != CONST_INT
8354 || INTVAL (operands[2]) <= 2
8355 || INTVAL (operands[2]) > 8
8356 || GET_CODE (operands[0]) != MEM
8357 || GET_CODE (operands[1]) != REG
8358 || REGNO (operands[1]) >= 32)
8361 count = INTVAL (operands[2]);
8362 regno = REGNO (operands[1]);
8364 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8365 to = force_reg (SImode, XEXP (operands[0], 0));
8366 op0 = replace_equiv_address (operands[0], to);
8368 XVECEXP (operands[3], 0, 0)
8369 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
8370 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8371 gen_rtx_SCRATCH (SImode));
8373 for (i = 1; i < count; i++)
8374 XVECEXP (operands[3], 0, i + 1)
8375 = gen_rtx_SET (VOIDmode,
8376 adjust_address_nv (op0, SImode, i * 4),
8377 gen_rtx_REG (SImode, regno + i));
8380 (define_insn "*store_multiple_power"
8381 [(match_parallel 0 "store_multiple_operation"
8382 [(set (match_operand:SI 1 "indirect_operand" "=Q")
8383 (match_operand:SI 2 "gpc_reg_operand" "r"))
8384 (clobber (match_scratch:SI 3 "=q"))])]
8385 "TARGET_STRING && TARGET_POWER"
8386 "{stsi|stswi} %2,%P1,%O0"
8387 [(set_attr "type" "store")])
8389 (define_insn "*stmsi8"
8390 [(match_parallel 0 "store_multiple_operation"
8391 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8392 (match_operand:SI 2 "gpc_reg_operand" "r"))
8393 (clobber (match_scratch:SI 3 "X"))
8394 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8395 (match_operand:SI 4 "gpc_reg_operand" "r"))
8396 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8397 (match_operand:SI 5 "gpc_reg_operand" "r"))
8398 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8399 (match_operand:SI 6 "gpc_reg_operand" "r"))
8400 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8401 (match_operand:SI 7 "gpc_reg_operand" "r"))
8402 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8403 (match_operand:SI 8 "gpc_reg_operand" "r"))
8404 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8405 (match_operand:SI 9 "gpc_reg_operand" "r"))
8406 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
8407 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
8408 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
8409 "{stsi|stswi} %2,%1,%O0"
8410 [(set_attr "type" "store")])
8412 (define_insn "*stmsi7"
8413 [(match_parallel 0 "store_multiple_operation"
8414 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8415 (match_operand:SI 2 "gpc_reg_operand" "r"))
8416 (clobber (match_scratch:SI 3 "X"))
8417 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8418 (match_operand:SI 4 "gpc_reg_operand" "r"))
8419 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8420 (match_operand:SI 5 "gpc_reg_operand" "r"))
8421 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8422 (match_operand:SI 6 "gpc_reg_operand" "r"))
8423 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8424 (match_operand:SI 7 "gpc_reg_operand" "r"))
8425 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8426 (match_operand:SI 8 "gpc_reg_operand" "r"))
8427 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8428 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
8429 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
8430 "{stsi|stswi} %2,%1,%O0"
8431 [(set_attr "type" "store")])
8433 (define_insn "*stmsi6"
8434 [(match_parallel 0 "store_multiple_operation"
8435 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8436 (match_operand:SI 2 "gpc_reg_operand" "r"))
8437 (clobber (match_scratch:SI 3 "X"))
8438 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8439 (match_operand:SI 4 "gpc_reg_operand" "r"))
8440 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8441 (match_operand:SI 5 "gpc_reg_operand" "r"))
8442 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8443 (match_operand:SI 6 "gpc_reg_operand" "r"))
8444 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8445 (match_operand:SI 7 "gpc_reg_operand" "r"))
8446 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8447 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
8448 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
8449 "{stsi|stswi} %2,%1,%O0"
8450 [(set_attr "type" "store")])
8452 (define_insn "*stmsi5"
8453 [(match_parallel 0 "store_multiple_operation"
8454 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8455 (match_operand:SI 2 "gpc_reg_operand" "r"))
8456 (clobber (match_scratch:SI 3 "X"))
8457 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8458 (match_operand:SI 4 "gpc_reg_operand" "r"))
8459 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8460 (match_operand:SI 5 "gpc_reg_operand" "r"))
8461 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8462 (match_operand:SI 6 "gpc_reg_operand" "r"))
8463 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8464 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
8465 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
8466 "{stsi|stswi} %2,%1,%O0"
8467 [(set_attr "type" "store")])
8469 (define_insn "*stmsi4"
8470 [(match_parallel 0 "store_multiple_operation"
8471 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8472 (match_operand:SI 2 "gpc_reg_operand" "r"))
8473 (clobber (match_scratch:SI 3 "X"))
8474 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8475 (match_operand:SI 4 "gpc_reg_operand" "r"))
8476 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8477 (match_operand:SI 5 "gpc_reg_operand" "r"))
8478 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8479 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
8480 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
8481 "{stsi|stswi} %2,%1,%O0"
8482 [(set_attr "type" "store")])
8484 (define_insn "*stmsi3"
8485 [(match_parallel 0 "store_multiple_operation"
8486 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8487 (match_operand:SI 2 "gpc_reg_operand" "r"))
8488 (clobber (match_scratch:SI 3 "X"))
8489 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8490 (match_operand:SI 4 "gpc_reg_operand" "r"))
8491 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8492 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
8493 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
8494 "{stsi|stswi} %2,%1,%O0"
8495 [(set_attr "type" "store")])
8497 (define_expand "setmemsi"
8498 [(parallel [(set (match_operand:BLK 0 "" "")
8499 (match_operand 2 "const_int_operand" ""))
8500 (use (match_operand:SI 1 "" ""))
8501 (use (match_operand:SI 3 "" ""))])]
8505 /* If value to set is not zero, use the library routine. */
8506 if (operands[2] != const0_rtx)
8509 if (expand_block_clear (operands))
8515 ;; String/block move insn.
8516 ;; Argument 0 is the destination
8517 ;; Argument 1 is the source
8518 ;; Argument 2 is the length
8519 ;; Argument 3 is the alignment
8521 (define_expand "movmemsi"
8522 [(parallel [(set (match_operand:BLK 0 "" "")
8523 (match_operand:BLK 1 "" ""))
8524 (use (match_operand:SI 2 "" ""))
8525 (use (match_operand:SI 3 "" ""))])]
8529 if (expand_block_move (operands))
8535 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
8536 ;; register allocator doesn't have a clue about allocating 8 word registers.
8537 ;; rD/rS = r5 is preferred, efficient form.
8538 (define_expand "movmemsi_8reg"
8539 [(parallel [(set (match_operand 0 "" "")
8540 (match_operand 1 "" ""))
8541 (use (match_operand 2 "" ""))
8542 (use (match_operand 3 "" ""))
8543 (clobber (reg:SI 5))
8544 (clobber (reg:SI 6))
8545 (clobber (reg:SI 7))
8546 (clobber (reg:SI 8))
8547 (clobber (reg:SI 9))
8548 (clobber (reg:SI 10))
8549 (clobber (reg:SI 11))
8550 (clobber (reg:SI 12))
8551 (clobber (match_scratch:SI 4 ""))])]
8556 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8557 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8558 (use (match_operand:SI 2 "immediate_operand" "i"))
8559 (use (match_operand:SI 3 "immediate_operand" "i"))
8560 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8561 (clobber (reg:SI 6))
8562 (clobber (reg:SI 7))
8563 (clobber (reg:SI 8))
8564 (clobber (reg:SI 9))
8565 (clobber (reg:SI 10))
8566 (clobber (reg:SI 11))
8567 (clobber (reg:SI 12))
8568 (clobber (match_scratch:SI 5 "=q"))]
8569 "TARGET_STRING && TARGET_POWER
8570 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8571 || INTVAL (operands[2]) == 0)
8572 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8573 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8574 && REGNO (operands[4]) == 5"
8575 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8576 [(set_attr "type" "load")
8577 (set_attr "length" "8")])
8580 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8581 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
8582 (use (match_operand:SI 2 "immediate_operand" "i"))
8583 (use (match_operand:SI 3 "immediate_operand" "i"))
8584 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8585 (clobber (reg:SI 6))
8586 (clobber (reg:SI 7))
8587 (clobber (reg:SI 8))
8588 (clobber (reg:SI 9))
8589 (clobber (reg:SI 10))
8590 (clobber (reg:SI 11))
8591 (clobber (reg:SI 12))
8592 (clobber (match_scratch:SI 5 "X"))]
8593 "TARGET_STRING && ! TARGET_POWER
8594 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8595 || INTVAL (operands[2]) == 0)
8596 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8597 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8598 && REGNO (operands[4]) == 5"
8599 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8600 [(set_attr "type" "load")
8601 (set_attr "length" "8")])
8603 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
8604 ;; register allocator doesn't have a clue about allocating 6 word registers.
8605 ;; rD/rS = r5 is preferred, efficient form.
8606 (define_expand "movmemsi_6reg"
8607 [(parallel [(set (match_operand 0 "" "")
8608 (match_operand 1 "" ""))
8609 (use (match_operand 2 "" ""))
8610 (use (match_operand 3 "" ""))
8611 (clobber (reg:SI 5))
8612 (clobber (reg:SI 6))
8613 (clobber (reg:SI 7))
8614 (clobber (reg:SI 8))
8615 (clobber (reg:SI 9))
8616 (clobber (reg:SI 10))
8617 (clobber (match_scratch:SI 4 ""))])]
8622 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8623 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8624 (use (match_operand:SI 2 "immediate_operand" "i"))
8625 (use (match_operand:SI 3 "immediate_operand" "i"))
8626 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8627 (clobber (reg:SI 6))
8628 (clobber (reg:SI 7))
8629 (clobber (reg:SI 8))
8630 (clobber (reg:SI 9))
8631 (clobber (reg:SI 10))
8632 (clobber (match_scratch:SI 5 "=q"))]
8633 "TARGET_STRING && TARGET_POWER
8634 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
8635 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8636 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8637 && REGNO (operands[4]) == 5"
8638 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8639 [(set_attr "type" "load")
8640 (set_attr "length" "8")])
8643 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8644 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
8645 (use (match_operand:SI 2 "immediate_operand" "i"))
8646 (use (match_operand:SI 3 "immediate_operand" "i"))
8647 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8648 (clobber (reg:SI 6))
8649 (clobber (reg:SI 7))
8650 (clobber (reg:SI 8))
8651 (clobber (reg:SI 9))
8652 (clobber (reg:SI 10))
8653 (clobber (match_scratch:SI 5 "X"))]
8654 "TARGET_STRING && ! TARGET_POWER
8655 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
8656 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8657 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8658 && REGNO (operands[4]) == 5"
8659 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8660 [(set_attr "type" "load")
8661 (set_attr "length" "8")])
8663 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
8664 ;; problems with TImode.
8665 ;; rD/rS = r5 is preferred, efficient form.
8666 (define_expand "movmemsi_4reg"
8667 [(parallel [(set (match_operand 0 "" "")
8668 (match_operand 1 "" ""))
8669 (use (match_operand 2 "" ""))
8670 (use (match_operand 3 "" ""))
8671 (clobber (reg:SI 5))
8672 (clobber (reg:SI 6))
8673 (clobber (reg:SI 7))
8674 (clobber (reg:SI 8))
8675 (clobber (match_scratch:SI 4 ""))])]
8680 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8681 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8682 (use (match_operand:SI 2 "immediate_operand" "i"))
8683 (use (match_operand:SI 3 "immediate_operand" "i"))
8684 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8685 (clobber (reg:SI 6))
8686 (clobber (reg:SI 7))
8687 (clobber (reg:SI 8))
8688 (clobber (match_scratch:SI 5 "=q"))]
8689 "TARGET_STRING && TARGET_POWER
8690 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
8691 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
8692 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
8693 && REGNO (operands[4]) == 5"
8694 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8695 [(set_attr "type" "load")
8696 (set_attr "length" "8")])
8699 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8700 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
8701 (use (match_operand:SI 2 "immediate_operand" "i"))
8702 (use (match_operand:SI 3 "immediate_operand" "i"))
8703 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8704 (clobber (reg:SI 6))
8705 (clobber (reg:SI 7))
8706 (clobber (reg:SI 8))
8707 (clobber (match_scratch:SI 5 "X"))]
8708 "TARGET_STRING && ! TARGET_POWER
8709 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
8710 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
8711 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
8712 && REGNO (operands[4]) == 5"
8713 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8714 [(set_attr "type" "load")
8715 (set_attr "length" "8")])
8717 ;; Move up to 8 bytes at a time.
8718 (define_expand "movmemsi_2reg"
8719 [(parallel [(set (match_operand 0 "" "")
8720 (match_operand 1 "" ""))
8721 (use (match_operand 2 "" ""))
8722 (use (match_operand 3 "" ""))
8723 (clobber (match_scratch:DI 4 ""))
8724 (clobber (match_scratch:SI 5 ""))])]
8725 "TARGET_STRING && ! TARGET_POWERPC64"
8729 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8730 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8731 (use (match_operand:SI 2 "immediate_operand" "i"))
8732 (use (match_operand:SI 3 "immediate_operand" "i"))
8733 (clobber (match_scratch:DI 4 "=&r"))
8734 (clobber (match_scratch:SI 5 "=q"))]
8735 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
8736 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
8737 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8738 [(set_attr "type" "load")
8739 (set_attr "length" "8")])
8742 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8743 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8744 (use (match_operand:SI 2 "immediate_operand" "i"))
8745 (use (match_operand:SI 3 "immediate_operand" "i"))
8746 (clobber (match_scratch:DI 4 "=&r"))
8747 (clobber (match_scratch:SI 5 "X"))]
8748 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
8749 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
8750 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8751 [(set_attr "type" "load")
8752 (set_attr "length" "8")])
8754 ;; Move up to 4 bytes at a time.
8755 (define_expand "movmemsi_1reg"
8756 [(parallel [(set (match_operand 0 "" "")
8757 (match_operand 1 "" ""))
8758 (use (match_operand 2 "" ""))
8759 (use (match_operand 3 "" ""))
8760 (clobber (match_scratch:SI 4 ""))
8761 (clobber (match_scratch:SI 5 ""))])]
8766 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8767 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8768 (use (match_operand:SI 2 "immediate_operand" "i"))
8769 (use (match_operand:SI 3 "immediate_operand" "i"))
8770 (clobber (match_scratch:SI 4 "=&r"))
8771 (clobber (match_scratch:SI 5 "=q"))]
8772 "TARGET_STRING && TARGET_POWER
8773 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
8774 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8775 [(set_attr "type" "load")
8776 (set_attr "length" "8")])
8779 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8780 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
8781 (use (match_operand:SI 2 "immediate_operand" "i"))
8782 (use (match_operand:SI 3 "immediate_operand" "i"))
8783 (clobber (match_scratch:SI 4 "=&r"))
8784 (clobber (match_scratch:SI 5 "X"))]
8785 "TARGET_STRING && ! TARGET_POWER
8786 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
8787 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8788 [(set_attr "type" "load")
8789 (set_attr "length" "8")])
8791 ;; Define insns that do load or store with update. Some of these we can
8792 ;; get by using pre-decrement or pre-increment, but the hardware can also
8793 ;; do cases where the increment is not the size of the object.
8795 ;; In all these cases, we use operands 0 and 1 for the register being
8796 ;; incremented because those are the operands that local-alloc will
8797 ;; tie and these are the pair most likely to be tieable (and the ones
8798 ;; that will benefit the most).
8800 (define_insn "*movdi_update1"
8801 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
8802 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
8803 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
8804 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
8805 (plus:DI (match_dup 1) (match_dup 2)))]
8806 "TARGET_POWERPC64 && TARGET_UPDATE"
8810 [(set_attr "type" "load_ux,load_u")])
8812 (define_insn "movdi_<mode>_update"
8813 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
8814 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
8815 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
8816 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
8817 (plus:P (match_dup 1) (match_dup 2)))]
8818 "TARGET_POWERPC64 && TARGET_UPDATE"
8822 [(set_attr "type" "store_ux,store_u")])
8824 (define_insn "*movsi_update1"
8825 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8826 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8827 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8828 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8829 (plus:SI (match_dup 1) (match_dup 2)))]
8832 {lux|lwzux} %3,%0,%2
8833 {lu|lwzu} %3,%2(%0)"
8834 [(set_attr "type" "load_ux,load_u")])
8836 (define_insn "*movsi_update2"
8837 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
8839 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
8840 (match_operand:DI 2 "gpc_reg_operand" "r")))))
8841 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
8842 (plus:DI (match_dup 1) (match_dup 2)))]
8845 [(set_attr "type" "load_ext_ux")])
8847 (define_insn "movsi_update"
8848 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8849 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8850 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8851 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8852 (plus:SI (match_dup 1) (match_dup 2)))]
8855 {stux|stwux} %3,%0,%2
8856 {stu|stwu} %3,%2(%0)"
8857 [(set_attr "type" "store_ux,store_u")])
8859 (define_insn "*movhi_update1"
8860 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
8861 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8862 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8863 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8864 (plus:SI (match_dup 1) (match_dup 2)))]
8869 [(set_attr "type" "load_ux,load_u")])
8871 (define_insn "*movhi_update2"
8872 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8874 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8875 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
8876 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8877 (plus:SI (match_dup 1) (match_dup 2)))]
8882 [(set_attr "type" "load_ux,load_u")])
8884 (define_insn "*movhi_update3"
8885 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8887 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8888 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
8889 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8890 (plus:SI (match_dup 1) (match_dup 2)))]
8895 [(set_attr "type" "load_ext_ux,load_ext_u")])
8897 (define_insn "*movhi_update4"
8898 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8899 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8900 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
8901 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8902 (plus:SI (match_dup 1) (match_dup 2)))]
8907 [(set_attr "type" "store_ux,store_u")])
8909 (define_insn "*movqi_update1"
8910 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
8911 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8912 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8913 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8914 (plus:SI (match_dup 1) (match_dup 2)))]
8919 [(set_attr "type" "load_ux,load_u")])
8921 (define_insn "*movqi_update2"
8922 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8924 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8925 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
8926 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8927 (plus:SI (match_dup 1) (match_dup 2)))]
8932 [(set_attr "type" "load_ux,load_u")])
8934 (define_insn "*movqi_update3"
8935 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8936 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8937 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
8938 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8939 (plus:SI (match_dup 1) (match_dup 2)))]
8944 [(set_attr "type" "store_ux,store_u")])
8946 (define_insn "*movsf_update1"
8947 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
8948 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8949 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8950 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8951 (plus:SI (match_dup 1) (match_dup 2)))]
8952 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
8956 [(set_attr "type" "fpload_ux,fpload_u")])
8958 (define_insn "*movsf_update2"
8959 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8960 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8961 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
8962 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8963 (plus:SI (match_dup 1) (match_dup 2)))]
8964 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
8968 [(set_attr "type" "fpstore_ux,fpstore_u")])
8970 (define_insn "*movsf_update3"
8971 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
8972 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8973 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8974 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8975 (plus:SI (match_dup 1) (match_dup 2)))]
8976 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
8978 {lux|lwzux} %3,%0,%2
8979 {lu|lwzu} %3,%2(%0)"
8980 [(set_attr "type" "load_ux,load_u")])
8982 (define_insn "*movsf_update4"
8983 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8984 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8985 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
8986 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8987 (plus:SI (match_dup 1) (match_dup 2)))]
8988 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
8990 {stux|stwux} %3,%0,%2
8991 {stu|stwu} %3,%2(%0)"
8992 [(set_attr "type" "store_ux,store_u")])
8994 (define_insn "*movdf_update1"
8995 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
8996 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8997 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8998 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8999 (plus:SI (match_dup 1) (match_dup 2)))]
9000 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9004 [(set_attr "type" "fpload_ux,fpload_u")])
9006 (define_insn "*movdf_update2"
9007 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9008 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9009 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9010 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9011 (plus:SI (match_dup 1) (match_dup 2)))]
9012 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9016 [(set_attr "type" "fpstore_ux,fpstore_u")])
9018 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9020 (define_insn "*lfq_power2"
9021 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
9022 (match_operand:V2DF 1 "memory_operand" ""))]
9024 && TARGET_HARD_FLOAT && TARGET_FPRS"
9028 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9029 (match_operand:DF 1 "memory_operand" ""))
9030 (set (match_operand:DF 2 "gpc_reg_operand" "")
9031 (match_operand:DF 3 "memory_operand" ""))]
9033 && TARGET_HARD_FLOAT && TARGET_FPRS
9034 && registers_ok_for_quad_peep (operands[0], operands[2])
9035 && mems_ok_for_quad_peep (operands[1], operands[3])"
9038 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
9039 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
9041 (define_insn "*stfq_power2"
9042 [(set (match_operand:V2DF 0 "memory_operand" "")
9043 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
9045 && TARGET_HARD_FLOAT && TARGET_FPRS"
9050 [(set (match_operand:DF 0 "memory_operand" "")
9051 (match_operand:DF 1 "gpc_reg_operand" ""))
9052 (set (match_operand:DF 2 "memory_operand" "")
9053 (match_operand:DF 3 "gpc_reg_operand" ""))]
9055 && TARGET_HARD_FLOAT && TARGET_FPRS
9056 && registers_ok_for_quad_peep (operands[1], operands[3])
9057 && mems_ok_for_quad_peep (operands[0], operands[2])"
9060 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
9061 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
9063 ;; after inserting conditional returns we can sometimes have
9064 ;; unnecessary register moves. Unfortunately we cannot have a
9065 ;; modeless peephole here, because some single SImode sets have early
9066 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9067 ;; sequences, using get_attr_length here will smash the operands
9068 ;; array. Neither is there an early_cobbler_p predicate.
9070 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9071 (match_operand:DF 1 "any_operand" ""))
9072 (set (match_operand:DF 2 "gpc_reg_operand" "")
9074 "peep2_reg_dead_p (2, operands[0])"
9075 [(set (match_dup 2) (match_dup 1))])
9078 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9079 (match_operand:SF 1 "any_operand" ""))
9080 (set (match_operand:SF 2 "gpc_reg_operand" "")
9082 "peep2_reg_dead_p (2, operands[0])"
9083 [(set (match_dup 2) (match_dup 1))])
9088 ;; "b" output constraint here and on tls_ld to support tls linker optimization.
9089 (define_insn "tls_gd_32"
9090 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9091 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9092 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9094 "HAVE_AS_TLS && !TARGET_64BIT"
9095 "addi %0,%1,%2@got@tlsgd")
9097 (define_insn "tls_gd_64"
9098 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9099 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9100 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9102 "HAVE_AS_TLS && TARGET_64BIT"
9103 "addi %0,%1,%2@got@tlsgd")
9105 (define_insn "tls_ld_32"
9106 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9107 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
9109 "HAVE_AS_TLS && !TARGET_64BIT"
9110 "addi %0,%1,%&@got@tlsld")
9112 (define_insn "tls_ld_64"
9113 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9114 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
9116 "HAVE_AS_TLS && TARGET_64BIT"
9117 "addi %0,%1,%&@got@tlsld")
9119 (define_insn "tls_dtprel_32"
9120 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9121 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9122 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9124 "HAVE_AS_TLS && !TARGET_64BIT"
9125 "addi %0,%1,%2@dtprel")
9127 (define_insn "tls_dtprel_64"
9128 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9129 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9130 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9132 "HAVE_AS_TLS && TARGET_64BIT"
9133 "addi %0,%1,%2@dtprel")
9135 (define_insn "tls_dtprel_ha_32"
9136 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9137 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9138 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9139 UNSPEC_TLSDTPRELHA))]
9140 "HAVE_AS_TLS && !TARGET_64BIT"
9141 "addis %0,%1,%2@dtprel@ha")
9143 (define_insn "tls_dtprel_ha_64"
9144 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9145 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9146 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9147 UNSPEC_TLSDTPRELHA))]
9148 "HAVE_AS_TLS && TARGET_64BIT"
9149 "addis %0,%1,%2@dtprel@ha")
9151 (define_insn "tls_dtprel_lo_32"
9152 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9153 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9154 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9155 UNSPEC_TLSDTPRELLO))]
9156 "HAVE_AS_TLS && !TARGET_64BIT"
9157 "addi %0,%1,%2@dtprel@l")
9159 (define_insn "tls_dtprel_lo_64"
9160 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9161 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9162 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9163 UNSPEC_TLSDTPRELLO))]
9164 "HAVE_AS_TLS && TARGET_64BIT"
9165 "addi %0,%1,%2@dtprel@l")
9167 (define_insn "tls_got_dtprel_32"
9168 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9169 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9170 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9171 UNSPEC_TLSGOTDTPREL))]
9172 "HAVE_AS_TLS && !TARGET_64BIT"
9173 "lwz %0,%2@got@dtprel(%1)")
9175 (define_insn "tls_got_dtprel_64"
9176 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9177 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9178 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9179 UNSPEC_TLSGOTDTPREL))]
9180 "HAVE_AS_TLS && TARGET_64BIT"
9181 "ld %0,%2@got@dtprel(%1)")
9183 (define_insn "tls_tprel_32"
9184 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9185 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9186 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9188 "HAVE_AS_TLS && !TARGET_64BIT"
9189 "addi %0,%1,%2@tprel")
9191 (define_insn "tls_tprel_64"
9192 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9193 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9194 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9196 "HAVE_AS_TLS && TARGET_64BIT"
9197 "addi %0,%1,%2@tprel")
9199 (define_insn "tls_tprel_ha_32"
9200 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9201 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9202 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9203 UNSPEC_TLSTPRELHA))]
9204 "HAVE_AS_TLS && !TARGET_64BIT"
9205 "addis %0,%1,%2@tprel@ha")
9207 (define_insn "tls_tprel_ha_64"
9208 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9209 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9210 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9211 UNSPEC_TLSTPRELHA))]
9212 "HAVE_AS_TLS && TARGET_64BIT"
9213 "addis %0,%1,%2@tprel@ha")
9215 (define_insn "tls_tprel_lo_32"
9216 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9217 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9218 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9219 UNSPEC_TLSTPRELLO))]
9220 "HAVE_AS_TLS && !TARGET_64BIT"
9221 "addi %0,%1,%2@tprel@l")
9223 (define_insn "tls_tprel_lo_64"
9224 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9225 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9226 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9227 UNSPEC_TLSTPRELLO))]
9228 "HAVE_AS_TLS && TARGET_64BIT"
9229 "addi %0,%1,%2@tprel@l")
9231 ;; "b" output constraint here and on tls_tls input to support linker tls
9232 ;; optimization. The linker may edit the instructions emitted by a
9233 ;; tls_got_tprel/tls_tls pair to addis,addi.
9234 (define_insn "tls_got_tprel_32"
9235 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9236 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9237 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9238 UNSPEC_TLSGOTTPREL))]
9239 "HAVE_AS_TLS && !TARGET_64BIT"
9240 "lwz %0,%2@got@tprel(%1)")
9242 (define_insn "tls_got_tprel_64"
9243 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9244 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9245 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9246 UNSPEC_TLSGOTTPREL))]
9247 "HAVE_AS_TLS && TARGET_64BIT"
9248 "ld %0,%2@got@tprel(%1)")
9250 (define_insn "tls_tls_32"
9251 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9252 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9253 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9255 "HAVE_AS_TLS && !TARGET_64BIT"
9258 (define_insn "tls_tls_64"
9259 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9260 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9261 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9263 "HAVE_AS_TLS && TARGET_64BIT"
9266 ;; Next come insns related to the calling sequence.
9268 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9269 ;; We move the back-chain and decrement the stack pointer.
9271 (define_expand "allocate_stack"
9272 [(set (match_operand 0 "gpc_reg_operand" "=r")
9273 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9275 (minus (reg 1) (match_dup 1)))]
9278 { rtx chain = gen_reg_rtx (Pmode);
9279 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
9282 emit_move_insn (chain, stack_bot);
9284 /* Check stack bounds if necessary. */
9285 if (current_function_limit_stack)
9288 available = expand_binop (Pmode, sub_optab,
9289 stack_pointer_rtx, stack_limit_rtx,
9290 NULL_RTX, 1, OPTAB_WIDEN);
9291 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
9294 if (GET_CODE (operands[1]) != CONST_INT
9295 || INTVAL (operands[1]) < -32767
9296 || INTVAL (operands[1]) > 32768)
9298 neg_op0 = gen_reg_rtx (Pmode);
9300 emit_insn (gen_negsi2 (neg_op0, operands[1]));
9302 emit_insn (gen_negdi2 (neg_op0, operands[1]));
9305 neg_op0 = GEN_INT (- INTVAL (operands[1]));
9308 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
9309 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
9313 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
9314 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
9315 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
9318 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9322 ;; These patterns say how to save and restore the stack pointer. We need not
9323 ;; save the stack pointer at function level since we are careful to
9324 ;; preserve the backchain. At block level, we have to restore the backchain
9325 ;; when we restore the stack pointer.
9327 ;; For nonlocal gotos, we must save both the stack pointer and its
9328 ;; backchain and restore both. Note that in the nonlocal case, the
9329 ;; save area is a memory location.
9331 (define_expand "save_stack_function"
9332 [(match_operand 0 "any_operand" "")
9333 (match_operand 1 "any_operand" "")]
9337 (define_expand "restore_stack_function"
9338 [(match_operand 0 "any_operand" "")
9339 (match_operand 1 "any_operand" "")]
9343 (define_expand "restore_stack_block"
9344 [(use (match_operand 0 "register_operand" ""))
9345 (set (match_dup 2) (match_dup 3))
9346 (set (match_dup 0) (match_operand 1 "register_operand" ""))
9347 (set (match_dup 3) (match_dup 2))]
9351 operands[2] = gen_reg_rtx (Pmode);
9352 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
9355 (define_expand "save_stack_nonlocal"
9356 [(match_operand 0 "memory_operand" "")
9357 (match_operand 1 "register_operand" "")]
9361 rtx temp = gen_reg_rtx (Pmode);
9362 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9364 /* Copy the backchain to the first word, sp to the second. */
9365 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
9366 emit_move_insn (adjust_address_nv (operands[0], Pmode, 0), temp);
9367 emit_move_insn (adjust_address_nv (operands[0], Pmode, units_per_word),
9372 (define_expand "restore_stack_nonlocal"
9373 [(match_operand 0 "register_operand" "")
9374 (match_operand 1 "memory_operand" "")]
9378 rtx temp = gen_reg_rtx (Pmode);
9379 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9381 /* Restore the backchain from the first word, sp from the second. */
9382 emit_move_insn (temp,
9383 adjust_address_nv (operands[1], Pmode, 0));
9384 emit_move_insn (operands[0],
9385 adjust_address_nv (operands[1], Pmode, units_per_word));
9386 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
9390 ;; TOC register handling.
9392 ;; Code to initialize the TOC register...
9394 (define_insn "load_toc_aix_si"
9395 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9396 (unspec:SI [(const_int 0)] UNSPEC_TOC))
9398 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
9402 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9403 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9404 operands[2] = gen_rtx_REG (Pmode, 2);
9405 return \"{l|lwz} %0,%1(%2)\";
9407 [(set_attr "type" "load")])
9409 (define_insn "load_toc_aix_di"
9410 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9411 (unspec:DI [(const_int 0)] UNSPEC_TOC))
9413 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
9417 #ifdef TARGET_RELOCATABLE
9418 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
9419 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
9421 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9424 strcat (buf, \"@toc\");
9425 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9426 operands[2] = gen_rtx_REG (Pmode, 2);
9427 return \"ld %0,%1(%2)\";
9429 [(set_attr "type" "load")])
9431 (define_insn "load_toc_v4_pic_si"
9432 [(set (match_operand:SI 0 "register_operand" "=l")
9433 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
9434 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
9435 "bl _GLOBAL_OFFSET_TABLE_@local-4"
9436 [(set_attr "type" "branch")
9437 (set_attr "length" "4")])
9439 (define_insn "load_toc_v4_PIC_1"
9440 [(set (match_operand:SI 0 "register_operand" "=l")
9441 (match_operand:SI 1 "immediate_operand" "s"))
9442 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
9443 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
9444 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
9445 "bcl 20,31,%1\\n%1:"
9446 [(set_attr "type" "branch")
9447 (set_attr "length" "4")])
9449 (define_insn "load_toc_v4_PIC_1b"
9450 [(set (match_operand:SI 0 "register_operand" "=l")
9451 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
9453 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9454 "bcl 20,31,$+8\\n\\t.long %1-$"
9455 [(set_attr "type" "branch")
9456 (set_attr "length" "8")])
9458 (define_insn "load_toc_v4_PIC_2"
9459 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9460 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9461 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
9462 (match_operand:SI 3 "immediate_operand" "s")))))]
9463 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9464 "{l|lwz} %0,%2-%3(%1)"
9465 [(set_attr "type" "load")])
9467 (define_insn "load_toc_v4_PIC_3b"
9468 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9469 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9471 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
9472 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
9473 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
9474 "{cau|addis} %0,%1,%2-%3@ha")
9476 (define_insn "load_toc_v4_PIC_3c"
9477 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9478 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9479 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
9480 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
9481 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
9482 "{cal|addi} %0,%1,%2-%3@l")
9484 ;; If the TOC is shared over a translation unit, as happens with all
9485 ;; the kinds of PIC that we support, we need to restore the TOC
9486 ;; pointer only when jumping over units of translation.
9487 ;; On Darwin, we need to reload the picbase.
9489 (define_expand "builtin_setjmp_receiver"
9490 [(use (label_ref (match_operand 0 "" "")))]
9491 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
9492 || (TARGET_TOC && TARGET_MINIMAL_TOC)
9493 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
9497 if (DEFAULT_ABI == ABI_DARWIN)
9499 const char *picbase = machopic_function_base_name ();
9500 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
9501 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
9505 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
9506 CODE_LABEL_NUMBER (operands[0]));
9507 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
9509 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
9510 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
9514 rs6000_emit_load_toc_table (FALSE);
9518 ;; Elf specific ways of loading addresses for non-PIC code.
9519 ;; The output of this could be r0, but we make a very strong
9520 ;; preference for a base register because it will usually
9522 (define_insn "elf_high"
9523 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
9524 (high:SI (match_operand 1 "" "")))]
9525 "TARGET_ELF && ! TARGET_64BIT"
9526 "{liu|lis} %0,%1@ha")
9528 (define_insn "elf_low"
9529 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9530 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
9531 (match_operand 2 "" "")))]
9532 "TARGET_ELF && ! TARGET_64BIT"
9534 {cal|la} %0,%2@l(%1)
9535 {ai|addic} %0,%1,%K2")
9537 ;; A function pointer under AIX is a pointer to a data area whose first word
9538 ;; contains the actual address of the function, whose second word contains a
9539 ;; pointer to its TOC, and whose third word contains a value to place in the
9540 ;; static chain register (r11). Note that if we load the static chain, our
9541 ;; "trampoline" need not have any executable code.
9543 (define_expand "call_indirect_aix32"
9545 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
9546 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9549 (mem:SI (plus:SI (match_dup 0)
9552 (mem:SI (plus:SI (match_dup 0)
9554 (parallel [(call (mem:SI (match_dup 2))
9555 (match_operand 1 "" ""))
9559 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9560 (clobber (scratch:SI))])]
9563 { operands[2] = gen_reg_rtx (SImode); }")
9565 (define_expand "call_indirect_aix64"
9567 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
9568 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9571 (mem:DI (plus:DI (match_dup 0)
9574 (mem:DI (plus:DI (match_dup 0)
9576 (parallel [(call (mem:SI (match_dup 2))
9577 (match_operand 1 "" ""))
9581 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9582 (clobber (scratch:SI))])]
9585 { operands[2] = gen_reg_rtx (DImode); }")
9587 (define_expand "call_value_indirect_aix32"
9589 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
9590 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9593 (mem:SI (plus:SI (match_dup 1)
9596 (mem:SI (plus:SI (match_dup 1)
9598 (parallel [(set (match_operand 0 "" "")
9599 (call (mem:SI (match_dup 3))
9600 (match_operand 2 "" "")))
9604 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9605 (clobber (scratch:SI))])]
9608 { operands[3] = gen_reg_rtx (SImode); }")
9610 (define_expand "call_value_indirect_aix64"
9612 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
9613 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9616 (mem:DI (plus:DI (match_dup 1)
9619 (mem:DI (plus:DI (match_dup 1)
9621 (parallel [(set (match_operand 0 "" "")
9622 (call (mem:SI (match_dup 3))
9623 (match_operand 2 "" "")))
9627 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9628 (clobber (scratch:SI))])]
9631 { operands[3] = gen_reg_rtx (DImode); }")
9633 ;; Now the definitions for the call and call_value insns
9634 (define_expand "call"
9635 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
9636 (match_operand 1 "" ""))
9637 (use (match_operand 2 "" ""))
9638 (clobber (scratch:SI))])]
9643 if (MACHOPIC_INDIRECT)
9644 operands[0] = machopic_indirect_call_target (operands[0]);
9647 gcc_assert (GET_CODE (operands[0]) == MEM);
9648 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
9650 operands[0] = XEXP (operands[0], 0);
9652 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
9654 && GET_CODE (operands[0]) == SYMBOL_REF
9655 && !SYMBOL_REF_LOCAL_P (operands[0]))
9661 gen_rtx_CALL (VOIDmode,
9662 gen_rtx_MEM (SImode, operands[0]),
9664 gen_rtx_USE (VOIDmode, operands[2]),
9665 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
9666 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
9667 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
9671 if (GET_CODE (operands[0]) != SYMBOL_REF
9672 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
9673 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
9675 if (INTVAL (operands[2]) & CALL_LONG)
9676 operands[0] = rs6000_longcall_ref (operands[0]);
9678 switch (DEFAULT_ABI)
9682 operands[0] = force_reg (Pmode, operands[0]);
9686 /* AIX function pointers are really pointers to a three word
9688 emit_call_insn (TARGET_32BIT
9689 ? gen_call_indirect_aix32 (force_reg (SImode,
9692 : gen_call_indirect_aix64 (force_reg (DImode,
9703 (define_expand "call_value"
9704 [(parallel [(set (match_operand 0 "" "")
9705 (call (mem:SI (match_operand 1 "address_operand" ""))
9706 (match_operand 2 "" "")))
9707 (use (match_operand 3 "" ""))
9708 (clobber (scratch:SI))])]
9713 if (MACHOPIC_INDIRECT)
9714 operands[1] = machopic_indirect_call_target (operands[1]);
9717 gcc_assert (GET_CODE (operands[1]) == MEM);
9718 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
9720 operands[1] = XEXP (operands[1], 0);
9722 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
9724 && GET_CODE (operands[1]) == SYMBOL_REF
9725 && !SYMBOL_REF_LOCAL_P (operands[1]))
9731 gen_rtx_SET (VOIDmode,
9733 gen_rtx_CALL (VOIDmode,
9734 gen_rtx_MEM (SImode,
9737 gen_rtx_USE (VOIDmode, operands[3]),
9738 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
9739 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
9740 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
9744 if (GET_CODE (operands[1]) != SYMBOL_REF
9745 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
9746 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
9748 if (INTVAL (operands[3]) & CALL_LONG)
9749 operands[1] = rs6000_longcall_ref (operands[1]);
9751 switch (DEFAULT_ABI)
9755 operands[1] = force_reg (Pmode, operands[1]);
9759 /* AIX function pointers are really pointers to a three word
9761 emit_call_insn (TARGET_32BIT
9762 ? gen_call_value_indirect_aix32 (operands[0],
9766 : gen_call_value_indirect_aix64 (operands[0],
9778 ;; Call to function in current module. No TOC pointer reload needed.
9779 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
9780 ;; either the function was not prototyped, or it was prototyped as a
9781 ;; variable argument function. It is > 0 if FP registers were passed
9782 ;; and < 0 if they were not.
9784 (define_insn "*call_local32"
9785 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
9786 (match_operand 1 "" "g,g"))
9787 (use (match_operand:SI 2 "immediate_operand" "O,n"))
9788 (clobber (match_scratch:SI 3 "=l,l"))]
9789 "(INTVAL (operands[2]) & CALL_LONG) == 0"
9792 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
9793 output_asm_insn (\"crxor 6,6,6\", operands);
9795 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
9796 output_asm_insn (\"creqv 6,6,6\", operands);
9798 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
9800 [(set_attr "type" "branch")
9801 (set_attr "length" "4,8")])
9803 (define_insn "*call_local64"
9804 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
9805 (match_operand 1 "" "g,g"))
9806 (use (match_operand:SI 2 "immediate_operand" "O,n"))
9807 (clobber (match_scratch:SI 3 "=l,l"))]
9808 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
9811 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
9812 output_asm_insn (\"crxor 6,6,6\", operands);
9814 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
9815 output_asm_insn (\"creqv 6,6,6\", operands);
9817 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
9819 [(set_attr "type" "branch")
9820 (set_attr "length" "4,8")])
9822 (define_insn "*call_value_local32"
9823 [(set (match_operand 0 "" "")
9824 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
9825 (match_operand 2 "" "g,g")))
9826 (use (match_operand:SI 3 "immediate_operand" "O,n"))
9827 (clobber (match_scratch:SI 4 "=l,l"))]
9828 "(INTVAL (operands[3]) & CALL_LONG) == 0"
9831 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
9832 output_asm_insn (\"crxor 6,6,6\", operands);
9834 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
9835 output_asm_insn (\"creqv 6,6,6\", operands);
9837 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
9839 [(set_attr "type" "branch")
9840 (set_attr "length" "4,8")])
9843 (define_insn "*call_value_local64"
9844 [(set (match_operand 0 "" "")
9845 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
9846 (match_operand 2 "" "g,g")))
9847 (use (match_operand:SI 3 "immediate_operand" "O,n"))
9848 (clobber (match_scratch:SI 4 "=l,l"))]
9849 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
9852 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
9853 output_asm_insn (\"crxor 6,6,6\", operands);
9855 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
9856 output_asm_insn (\"creqv 6,6,6\", operands);
9858 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
9860 [(set_attr "type" "branch")
9861 (set_attr "length" "4,8")])
9863 ;; Call to function which may be in another module. Restore the TOC
9864 ;; pointer (r2) after the call unless this is System V.
9865 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
9866 ;; either the function was not prototyped, or it was prototyped as a
9867 ;; variable argument function. It is > 0 if FP registers were passed
9868 ;; and < 0 if they were not.
9870 (define_insn "*call_indirect_nonlocal_aix32"
9871 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
9872 (match_operand 1 "" "g,g"))
9876 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9877 (clobber (match_scratch:SI 2 "=l,l"))]
9878 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
9879 "b%T0l\;{l|lwz} 2,20(1)"
9880 [(set_attr "type" "jmpreg")
9881 (set_attr "length" "8")])
9883 (define_insn "*call_nonlocal_aix32"
9884 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
9885 (match_operand 1 "" "g"))
9886 (use (match_operand:SI 2 "immediate_operand" "O"))
9887 (clobber (match_scratch:SI 3 "=l"))]
9889 && DEFAULT_ABI == ABI_AIX
9890 && (INTVAL (operands[2]) & CALL_LONG) == 0"
9892 [(set_attr "type" "branch")
9893 (set_attr "length" "8")])
9895 (define_insn "*call_indirect_nonlocal_aix64"
9896 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
9897 (match_operand 1 "" "g,g"))
9901 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9902 (clobber (match_scratch:SI 2 "=l,l"))]
9903 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
9905 [(set_attr "type" "jmpreg")
9906 (set_attr "length" "8")])
9908 (define_insn "*call_nonlocal_aix64"
9909 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
9910 (match_operand 1 "" "g"))
9911 (use (match_operand:SI 2 "immediate_operand" "O"))
9912 (clobber (match_scratch:SI 3 "=l"))]
9914 && DEFAULT_ABI == ABI_AIX
9915 && (INTVAL (operands[2]) & CALL_LONG) == 0"
9917 [(set_attr "type" "branch")
9918 (set_attr "length" "8")])
9920 (define_insn "*call_value_indirect_nonlocal_aix32"
9921 [(set (match_operand 0 "" "")
9922 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
9923 (match_operand 2 "" "g,g")))
9927 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9928 (clobber (match_scratch:SI 3 "=l,l"))]
9929 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
9930 "b%T1l\;{l|lwz} 2,20(1)"
9931 [(set_attr "type" "jmpreg")
9932 (set_attr "length" "8")])
9934 (define_insn "*call_value_nonlocal_aix32"
9935 [(set (match_operand 0 "" "")
9936 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
9937 (match_operand 2 "" "g")))
9938 (use (match_operand:SI 3 "immediate_operand" "O"))
9939 (clobber (match_scratch:SI 4 "=l"))]
9941 && DEFAULT_ABI == ABI_AIX
9942 && (INTVAL (operands[3]) & CALL_LONG) == 0"
9944 [(set_attr "type" "branch")
9945 (set_attr "length" "8")])
9947 (define_insn "*call_value_indirect_nonlocal_aix64"
9948 [(set (match_operand 0 "" "")
9949 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
9950 (match_operand 2 "" "g,g")))
9954 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9955 (clobber (match_scratch:SI 3 "=l,l"))]
9956 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
9958 [(set_attr "type" "jmpreg")
9959 (set_attr "length" "8")])
9961 (define_insn "*call_value_nonlocal_aix64"
9962 [(set (match_operand 0 "" "")
9963 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
9964 (match_operand 2 "" "g")))
9965 (use (match_operand:SI 3 "immediate_operand" "O"))
9966 (clobber (match_scratch:SI 4 "=l"))]
9968 && DEFAULT_ABI == ABI_AIX
9969 && (INTVAL (operands[3]) & CALL_LONG) == 0"
9971 [(set_attr "type" "branch")
9972 (set_attr "length" "8")])
9974 ;; A function pointer under System V is just a normal pointer
9975 ;; operands[0] is the function pointer
9976 ;; operands[1] is the stack size to clean up
9977 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
9978 ;; which indicates how to set cr1
9980 (define_insn "*call_indirect_nonlocal_sysv"
9981 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l,c,*l"))
9982 (match_operand 1 "" "g,g,g,g"))
9983 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
9984 (clobber (match_scratch:SI 3 "=l,l,l,l"))]
9985 "DEFAULT_ABI == ABI_V4
9986 || DEFAULT_ABI == ABI_DARWIN"
9988 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
9989 output_asm_insn ("crxor 6,6,6", operands);
9991 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
9992 output_asm_insn ("creqv 6,6,6", operands);
9996 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
9997 (set_attr "length" "4,4,8,8")])
9999 (define_insn "*call_nonlocal_sysv"
10000 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10001 (match_operand 1 "" "g,g"))
10002 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10003 (clobber (match_scratch:SI 3 "=l,l"))]
10004 "(DEFAULT_ABI == ABI_DARWIN
10005 || (DEFAULT_ABI == ABI_V4
10006 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10008 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10009 output_asm_insn ("crxor 6,6,6", operands);
10011 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10012 output_asm_insn ("creqv 6,6,6", operands);
10015 return output_call(insn, operands, 0, 2);
10017 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10019 if (TARGET_SECURE_PLT && flag_pic == 2)
10020 /* The magic 32768 offset here and in the other sysv call insns
10021 corresponds to the offset of r30 in .got2, as given by LCTOC1.
10022 See sysv4.h:toc_section. */
10023 return "bl %z0+32768@plt";
10025 return "bl %z0@plt";
10031 [(set_attr "type" "branch,branch")
10032 (set_attr "length" "4,8")])
10034 (define_insn "*call_value_indirect_nonlocal_sysv"
10035 [(set (match_operand 0 "" "")
10036 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l,c,*l"))
10037 (match_operand 2 "" "g,g,g,g")))
10038 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
10039 (clobber (match_scratch:SI 4 "=l,l,l,l"))]
10040 "DEFAULT_ABI == ABI_V4
10041 || DEFAULT_ABI == ABI_DARWIN"
10043 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10044 output_asm_insn ("crxor 6,6,6", operands);
10046 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10047 output_asm_insn ("creqv 6,6,6", operands);
10051 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10052 (set_attr "length" "4,4,8,8")])
10054 (define_insn "*call_value_nonlocal_sysv"
10055 [(set (match_operand 0 "" "")
10056 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10057 (match_operand 2 "" "g,g")))
10058 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10059 (clobber (match_scratch:SI 4 "=l,l"))]
10060 "(DEFAULT_ABI == ABI_DARWIN
10061 || (DEFAULT_ABI == ABI_V4
10062 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10064 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10065 output_asm_insn ("crxor 6,6,6", operands);
10067 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10068 output_asm_insn ("creqv 6,6,6", operands);
10071 return output_call(insn, operands, 1, 3);
10073 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10075 if (TARGET_SECURE_PLT && flag_pic == 2)
10076 return "bl %z1+32768@plt";
10078 return "bl %z1@plt";
10084 [(set_attr "type" "branch,branch")
10085 (set_attr "length" "4,8")])
10087 ;; Call subroutine returning any type.
10088 (define_expand "untyped_call"
10089 [(parallel [(call (match_operand 0 "" "")
10091 (match_operand 1 "" "")
10092 (match_operand 2 "" "")])]
10098 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10100 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10102 rtx set = XVECEXP (operands[2], 0, i);
10103 emit_move_insn (SET_DEST (set), SET_SRC (set));
10106 /* The optimizer does not know that the call sets the function value
10107 registers we stored in the result block. We avoid problems by
10108 claiming that all hard registers are used and clobbered at this
10110 emit_insn (gen_blockage ());
10115 ;; sibling call patterns
10116 (define_expand "sibcall"
10117 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10118 (match_operand 1 "" ""))
10119 (use (match_operand 2 "" ""))
10120 (use (match_operand 3 "" ""))
10126 if (MACHOPIC_INDIRECT)
10127 operands[0] = machopic_indirect_call_target (operands[0]);
10130 gcc_assert (GET_CODE (operands[0]) == MEM);
10131 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10133 operands[0] = XEXP (operands[0], 0);
10134 operands[3] = gen_reg_rtx (SImode);
10138 ;; this and similar patterns must be marked as using LR, otherwise
10139 ;; dataflow will try to delete the store into it. This is true
10140 ;; even when the actual reg to jump to is in CTR, when LR was
10141 ;; saved and restored around the PIC-setting BCL.
10142 (define_insn "*sibcall_local32"
10143 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10144 (match_operand 1 "" "g,g"))
10145 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10146 (use (match_operand:SI 3 "register_operand" "l,l"))
10148 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10151 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10152 output_asm_insn (\"crxor 6,6,6\", operands);
10154 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10155 output_asm_insn (\"creqv 6,6,6\", operands);
10157 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10159 [(set_attr "type" "branch")
10160 (set_attr "length" "4,8")])
10162 (define_insn "*sibcall_local64"
10163 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10164 (match_operand 1 "" "g,g"))
10165 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10166 (use (match_operand:SI 3 "register_operand" "l,l"))
10168 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10171 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10172 output_asm_insn (\"crxor 6,6,6\", operands);
10174 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10175 output_asm_insn (\"creqv 6,6,6\", operands);
10177 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10179 [(set_attr "type" "branch")
10180 (set_attr "length" "4,8")])
10182 (define_insn "*sibcall_value_local32"
10183 [(set (match_operand 0 "" "")
10184 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10185 (match_operand 2 "" "g,g")))
10186 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10187 (use (match_operand:SI 4 "register_operand" "l,l"))
10189 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10192 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10193 output_asm_insn (\"crxor 6,6,6\", operands);
10195 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10196 output_asm_insn (\"creqv 6,6,6\", operands);
10198 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10200 [(set_attr "type" "branch")
10201 (set_attr "length" "4,8")])
10204 (define_insn "*sibcall_value_local64"
10205 [(set (match_operand 0 "" "")
10206 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10207 (match_operand 2 "" "g,g")))
10208 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10209 (use (match_operand:SI 4 "register_operand" "l,l"))
10211 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10214 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10215 output_asm_insn (\"crxor 6,6,6\", operands);
10217 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10218 output_asm_insn (\"creqv 6,6,6\", operands);
10220 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10222 [(set_attr "type" "branch")
10223 (set_attr "length" "4,8")])
10225 (define_insn "*sibcall_nonlocal_aix32"
10226 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10227 (match_operand 1 "" "g"))
10228 (use (match_operand:SI 2 "immediate_operand" "O"))
10229 (use (match_operand:SI 3 "register_operand" "l"))
10232 && DEFAULT_ABI == ABI_AIX
10233 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10235 [(set_attr "type" "branch")
10236 (set_attr "length" "4")])
10238 (define_insn "*sibcall_nonlocal_aix64"
10239 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10240 (match_operand 1 "" "g"))
10241 (use (match_operand:SI 2 "immediate_operand" "O"))
10242 (use (match_operand:SI 3 "register_operand" "l"))
10245 && DEFAULT_ABI == ABI_AIX
10246 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10248 [(set_attr "type" "branch")
10249 (set_attr "length" "4")])
10251 (define_insn "*sibcall_value_nonlocal_aix32"
10252 [(set (match_operand 0 "" "")
10253 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10254 (match_operand 2 "" "g")))
10255 (use (match_operand:SI 3 "immediate_operand" "O"))
10256 (use (match_operand:SI 4 "register_operand" "l"))
10259 && DEFAULT_ABI == ABI_AIX
10260 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10262 [(set_attr "type" "branch")
10263 (set_attr "length" "4")])
10265 (define_insn "*sibcall_value_nonlocal_aix64"
10266 [(set (match_operand 0 "" "")
10267 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10268 (match_operand 2 "" "g")))
10269 (use (match_operand:SI 3 "immediate_operand" "O"))
10270 (use (match_operand:SI 4 "register_operand" "l"))
10273 && DEFAULT_ABI == ABI_AIX
10274 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10276 [(set_attr "type" "branch")
10277 (set_attr "length" "4")])
10279 (define_insn "*sibcall_nonlocal_sysv"
10280 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10281 (match_operand 1 "" ""))
10282 (use (match_operand 2 "immediate_operand" "O,n"))
10283 (use (match_operand:SI 3 "register_operand" "l,l"))
10285 "(DEFAULT_ABI == ABI_DARWIN
10286 || DEFAULT_ABI == ABI_V4)
10287 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10290 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10291 output_asm_insn (\"crxor 6,6,6\", operands);
10293 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10294 output_asm_insn (\"creqv 6,6,6\", operands);
10296 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10298 if (TARGET_SECURE_PLT && flag_pic == 2)
10299 return \"b %z0+32768@plt\";
10301 return \"b %z0@plt\";
10306 [(set_attr "type" "branch,branch")
10307 (set_attr "length" "4,8")])
10309 (define_expand "sibcall_value"
10310 [(parallel [(set (match_operand 0 "register_operand" "")
10311 (call (mem:SI (match_operand 1 "address_operand" ""))
10312 (match_operand 2 "" "")))
10313 (use (match_operand 3 "" ""))
10314 (use (match_operand 4 "" ""))
10320 if (MACHOPIC_INDIRECT)
10321 operands[1] = machopic_indirect_call_target (operands[1]);
10324 gcc_assert (GET_CODE (operands[1]) == MEM);
10325 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10327 operands[1] = XEXP (operands[1], 0);
10328 operands[4] = gen_reg_rtx (SImode);
10332 (define_insn "*sibcall_value_nonlocal_sysv"
10333 [(set (match_operand 0 "" "")
10334 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10335 (match_operand 2 "" "")))
10336 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10337 (use (match_operand:SI 4 "register_operand" "l,l"))
10339 "(DEFAULT_ABI == ABI_DARWIN
10340 || DEFAULT_ABI == ABI_V4)
10341 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10344 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10345 output_asm_insn (\"crxor 6,6,6\", operands);
10347 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10348 output_asm_insn (\"creqv 6,6,6\", operands);
10350 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10352 if (TARGET_SECURE_PLT && flag_pic == 2)
10353 return \"b %z1+32768@plt\";
10355 return \"b %z1@plt\";
10360 [(set_attr "type" "branch,branch")
10361 (set_attr "length" "4,8")])
10363 (define_expand "sibcall_epilogue"
10364 [(use (const_int 0))]
10365 "TARGET_SCHED_PROLOG"
10368 rs6000_emit_epilogue (TRUE);
10372 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10373 ;; all of memory. This blocks insns from being moved across this point.
10375 (define_insn "blockage"
10376 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
10380 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
10381 ;; signed & unsigned, and one type of branch.
10383 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
10384 ;; insns, and branches. We store the operands of compares until we see
10386 (define_expand "cmp<mode>"
10388 (compare (match_operand:GPR 0 "gpc_reg_operand" "")
10389 (match_operand:GPR 1 "reg_or_short_operand" "")))]
10393 /* Take care of the possibility that operands[1] might be negative but
10394 this might be a logical operation. That insn doesn't exist. */
10395 if (GET_CODE (operands[1]) == CONST_INT
10396 && INTVAL (operands[1]) < 0)
10397 operands[1] = force_reg (<MODE>mode, operands[1]);
10399 rs6000_compare_op0 = operands[0];
10400 rs6000_compare_op1 = operands[1];
10401 rs6000_compare_fp_p = 0;
10405 (define_expand "cmp<mode>"
10406 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
10407 (match_operand:FP 1 "gpc_reg_operand" "")))]
10411 rs6000_compare_op0 = operands[0];
10412 rs6000_compare_op1 = operands[1];
10413 rs6000_compare_fp_p = 1;
10417 (define_expand "beq"
10418 [(use (match_operand 0 "" ""))]
10420 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
10422 (define_expand "bne"
10423 [(use (match_operand 0 "" ""))]
10425 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
10427 (define_expand "bge"
10428 [(use (match_operand 0 "" ""))]
10430 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
10432 (define_expand "bgt"
10433 [(use (match_operand 0 "" ""))]
10435 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
10437 (define_expand "ble"
10438 [(use (match_operand 0 "" ""))]
10440 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
10442 (define_expand "blt"
10443 [(use (match_operand 0 "" ""))]
10445 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
10447 (define_expand "bgeu"
10448 [(use (match_operand 0 "" ""))]
10450 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
10452 (define_expand "bgtu"
10453 [(use (match_operand 0 "" ""))]
10455 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
10457 (define_expand "bleu"
10458 [(use (match_operand 0 "" ""))]
10460 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
10462 (define_expand "bltu"
10463 [(use (match_operand 0 "" ""))]
10465 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
10467 (define_expand "bunordered"
10468 [(use (match_operand 0 "" ""))]
10469 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10470 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
10472 (define_expand "bordered"
10473 [(use (match_operand 0 "" ""))]
10474 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10475 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
10477 (define_expand "buneq"
10478 [(use (match_operand 0 "" ""))]
10480 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
10482 (define_expand "bunge"
10483 [(use (match_operand 0 "" ""))]
10485 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
10487 (define_expand "bungt"
10488 [(use (match_operand 0 "" ""))]
10490 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
10492 (define_expand "bunle"
10493 [(use (match_operand 0 "" ""))]
10495 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
10497 (define_expand "bunlt"
10498 [(use (match_operand 0 "" ""))]
10500 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
10502 (define_expand "bltgt"
10503 [(use (match_operand 0 "" ""))]
10505 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
10507 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
10508 ;; For SEQ, likewise, except that comparisons with zero should be done
10509 ;; with an scc insns. However, due to the order that combine see the
10510 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
10511 ;; the cases we don't want to handle.
10512 (define_expand "seq"
10513 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10515 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
10517 (define_expand "sne"
10518 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10522 if (! rs6000_compare_fp_p)
10525 rs6000_emit_sCOND (NE, operands[0]);
10529 ;; A >= 0 is best done the portable way for A an integer.
10530 (define_expand "sge"
10531 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10535 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10538 rs6000_emit_sCOND (GE, operands[0]);
10542 ;; A > 0 is best done using the portable sequence, so fail in that case.
10543 (define_expand "sgt"
10544 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10548 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10551 rs6000_emit_sCOND (GT, operands[0]);
10555 ;; A <= 0 is best done the portable way for A an integer.
10556 (define_expand "sle"
10557 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10561 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10564 rs6000_emit_sCOND (LE, operands[0]);
10568 ;; A < 0 is best done in the portable way for A an integer.
10569 (define_expand "slt"
10570 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10574 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10577 rs6000_emit_sCOND (LT, operands[0]);
10581 (define_expand "sgeu"
10582 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10584 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
10586 (define_expand "sgtu"
10587 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10589 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
10591 (define_expand "sleu"
10592 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10594 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
10596 (define_expand "sltu"
10597 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10599 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
10601 (define_expand "sunordered"
10602 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10603 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10604 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
10606 (define_expand "sordered"
10607 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10608 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10609 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
10611 (define_expand "suneq"
10612 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10614 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
10616 (define_expand "sunge"
10617 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10619 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
10621 (define_expand "sungt"
10622 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10624 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
10626 (define_expand "sunle"
10627 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10629 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
10631 (define_expand "sunlt"
10632 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10634 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
10636 (define_expand "sltgt"
10637 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10639 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
10641 (define_expand "stack_protect_set"
10642 [(match_operand 0 "memory_operand" "")
10643 (match_operand 1 "memory_operand" "")]
10646 #ifdef TARGET_THREAD_SSP_OFFSET
10647 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
10648 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
10649 operands[1] = gen_rtx_MEM (Pmode, addr);
10652 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
10654 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
10658 (define_insn "stack_protect_setsi"
10659 [(set (match_operand:SI 0 "memory_operand" "=m")
10660 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
10661 (set (match_scratch:SI 2 "=&r") (const_int 0))]
10663 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
10664 [(set_attr "type" "three")
10665 (set_attr "length" "12")])
10667 (define_insn "stack_protect_setdi"
10668 [(set (match_operand:DI 0 "memory_operand" "=m")
10669 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
10670 (set (match_scratch:DI 2 "=&r") (const_int 0))]
10672 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
10673 [(set_attr "type" "three")
10674 (set_attr "length" "12")])
10676 (define_expand "stack_protect_test"
10677 [(match_operand 0 "memory_operand" "")
10678 (match_operand 1 "memory_operand" "")
10679 (match_operand 2 "" "")]
10682 #ifdef TARGET_THREAD_SSP_OFFSET
10683 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
10684 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
10685 operands[1] = gen_rtx_MEM (Pmode, addr);
10687 rs6000_compare_op0 = operands[0];
10688 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
10690 rs6000_compare_fp_p = 0;
10691 emit_jump_insn (gen_beq (operands[2]));
10695 (define_insn "stack_protect_testsi"
10696 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
10697 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
10698 (match_operand:SI 2 "memory_operand" "m,m")]
10700 (set (match_scratch:SI 4 "=r,r") (const_int 0))
10701 (clobber (match_scratch:SI 3 "=&r,&r"))]
10704 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
10705 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
10706 [(set_attr "length" "16,20")])
10708 (define_insn "stack_protect_testdi"
10709 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
10710 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
10711 (match_operand:DI 2 "memory_operand" "m,m")]
10713 (set (match_scratch:DI 4 "=r,r") (const_int 0))
10714 (clobber (match_scratch:DI 3 "=&r,&r"))]
10717 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
10718 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
10719 [(set_attr "length" "16,20")])
10722 ;; Here are the actual compare insns.
10723 (define_insn "*cmp<mode>_internal1"
10724 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
10725 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
10726 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
10728 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
10729 [(set_attr "type" "cmp")])
10731 ;; If we are comparing a register for equality with a large constant,
10732 ;; we can do this with an XOR followed by a compare. But we need a scratch
10733 ;; register for the result of the XOR.
10736 [(set (match_operand:CC 0 "cc_reg_operand" "")
10737 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
10738 (match_operand:SI 2 "non_short_cint_operand" "")))
10739 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
10740 "find_single_use (operands[0], insn, 0)
10741 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
10742 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
10743 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
10744 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
10747 /* Get the constant we are comparing against, C, and see what it looks like
10748 sign-extended to 16 bits. Then see what constant could be XOR'ed
10749 with C to get the sign-extended value. */
10751 HOST_WIDE_INT c = INTVAL (operands[2]);
10752 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
10753 HOST_WIDE_INT xorv = c ^ sextc;
10755 operands[4] = GEN_INT (xorv);
10756 operands[5] = GEN_INT (sextc);
10759 (define_insn "*cmpsi_internal2"
10760 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
10761 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
10762 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
10764 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
10765 [(set_attr "type" "cmp")])
10767 (define_insn "*cmpdi_internal2"
10768 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
10769 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
10770 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
10772 "cmpld%I2 %0,%1,%b2"
10773 [(set_attr "type" "cmp")])
10775 ;; The following two insns don't exist as single insns, but if we provide
10776 ;; them, we can swap an add and compare, which will enable us to overlap more
10777 ;; of the required delay between a compare and branch. We generate code for
10778 ;; them by splitting.
10781 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
10782 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
10783 (match_operand:SI 2 "short_cint_operand" "i")))
10784 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
10785 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
10788 [(set_attr "length" "8")])
10791 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
10792 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
10793 (match_operand:SI 2 "u_short_cint_operand" "i")))
10794 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
10795 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
10798 [(set_attr "length" "8")])
10801 [(set (match_operand:CC 3 "cc_reg_operand" "")
10802 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
10803 (match_operand:SI 2 "short_cint_operand" "")))
10804 (set (match_operand:SI 0 "gpc_reg_operand" "")
10805 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
10807 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
10808 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
10811 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
10812 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
10813 (match_operand:SI 2 "u_short_cint_operand" "")))
10814 (set (match_operand:SI 0 "gpc_reg_operand" "")
10815 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
10817 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
10818 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
10820 (define_insn "*cmpsf_internal1"
10821 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10822 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
10823 (match_operand:SF 2 "gpc_reg_operand" "f")))]
10824 "TARGET_HARD_FLOAT && TARGET_FPRS"
10826 [(set_attr "type" "fpcompare")])
10828 (define_insn "*cmpdf_internal1"
10829 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10830 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
10831 (match_operand:DF 2 "gpc_reg_operand" "f")))]
10832 "TARGET_HARD_FLOAT && TARGET_FPRS"
10834 [(set_attr "type" "fpcompare")])
10836 ;; Only need to compare second words if first words equal
10837 (define_insn "*cmptf_internal1"
10838 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10839 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
10840 (match_operand:TF 2 "gpc_reg_operand" "f")))]
10841 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
10842 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
10843 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
10844 [(set_attr "type" "fpcompare")
10845 (set_attr "length" "12")])
10847 (define_insn_and_split "*cmptf_internal2"
10848 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10849 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
10850 (match_operand:TF 2 "gpc_reg_operand" "f")))
10851 (clobber (match_scratch:DF 3 "=f"))
10852 (clobber (match_scratch:DF 4 "=f"))
10853 (clobber (match_scratch:DF 5 "=f"))
10854 (clobber (match_scratch:DF 6 "=f"))
10855 (clobber (match_scratch:DF 7 "=f"))
10856 (clobber (match_scratch:DF 8 "=f"))
10857 (clobber (match_scratch:DF 9 "=f"))
10858 (clobber (match_scratch:DF 10 "=f"))]
10859 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
10860 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
10862 "&& reload_completed"
10863 [(set (match_dup 3) (match_dup 13))
10864 (set (match_dup 4) (match_dup 14))
10865 (set (match_dup 9) (abs:DF (match_dup 5)))
10866 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
10867 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
10868 (label_ref (match_dup 11))
10870 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
10871 (set (pc) (label_ref (match_dup 12)))
10873 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
10874 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
10875 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
10876 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
10879 REAL_VALUE_TYPE rv;
10880 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
10881 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
10883 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
10884 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
10885 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
10886 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
10887 operands[11] = gen_label_rtx ();
10888 operands[12] = gen_label_rtx ();
10890 operands[13] = force_const_mem (DFmode,
10891 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
10892 operands[14] = force_const_mem (DFmode,
10893 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
10897 operands[13] = gen_const_mem (DFmode,
10898 create_TOC_reference (XEXP (operands[13], 0)));
10899 operands[14] = gen_const_mem (DFmode,
10900 create_TOC_reference (XEXP (operands[14], 0)));
10901 set_mem_alias_set (operands[13], get_TOC_alias_set ());
10902 set_mem_alias_set (operands[14], get_TOC_alias_set ());
10906 ;; Now we have the scc insns. We can do some combinations because of the
10907 ;; way the machine works.
10909 ;; Note that this is probably faster if we can put an insn between the
10910 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
10911 ;; cases the insns below which don't use an intermediate CR field will
10912 ;; be used instead.
10914 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10915 (match_operator:SI 1 "scc_comparison_operator"
10916 [(match_operand 2 "cc_reg_operand" "y")
10919 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
10920 [(set (attr "type")
10921 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
10922 (const_string "mfcrf")
10924 (const_string "mfcr")))
10925 (set_attr "length" "8")])
10927 ;; Same as above, but get the GT bit.
10928 (define_insn "move_from_CR_gt_bit"
10929 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10930 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
10932 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
10933 [(set_attr "type" "mfcr")
10934 (set_attr "length" "8")])
10936 ;; Same as above, but get the OV/ORDERED bit.
10937 (define_insn "move_from_CR_ov_bit"
10938 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10939 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
10941 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
10942 [(set_attr "type" "mfcr")
10943 (set_attr "length" "8")])
10946 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10947 (match_operator:DI 1 "scc_comparison_operator"
10948 [(match_operand 2 "cc_reg_operand" "y")
10951 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
10952 [(set (attr "type")
10953 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
10954 (const_string "mfcrf")
10956 (const_string "mfcr")))
10957 (set_attr "length" "8")])
10960 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
10961 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
10962 [(match_operand 2 "cc_reg_operand" "y,y")
10965 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10966 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
10969 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
10971 [(set_attr "type" "delayed_compare")
10972 (set_attr "length" "8,16")])
10975 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
10976 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
10977 [(match_operand 2 "cc_reg_operand" "")
10980 (set (match_operand:SI 3 "gpc_reg_operand" "")
10981 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
10982 "TARGET_32BIT && reload_completed"
10983 [(set (match_dup 3)
10984 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
10986 (compare:CC (match_dup 3)
10991 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10992 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
10993 [(match_operand 2 "cc_reg_operand" "y")
10995 (match_operand:SI 3 "const_int_operand" "n")))]
10999 int is_bit = ccr_bit (operands[1], 1);
11000 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11003 if (is_bit >= put_bit)
11004 count = is_bit - put_bit;
11006 count = 32 - (put_bit - is_bit);
11008 operands[4] = GEN_INT (count);
11009 operands[5] = GEN_INT (put_bit);
11011 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11013 [(set (attr "type")
11014 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11015 (const_string "mfcrf")
11017 (const_string "mfcr")))
11018 (set_attr "length" "8")])
11021 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11023 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11024 [(match_operand 2 "cc_reg_operand" "y,y")
11026 (match_operand:SI 3 "const_int_operand" "n,n"))
11028 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11029 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11034 int is_bit = ccr_bit (operands[1], 1);
11035 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11038 /* Force split for non-cc0 compare. */
11039 if (which_alternative == 1)
11042 if (is_bit >= put_bit)
11043 count = is_bit - put_bit;
11045 count = 32 - (put_bit - is_bit);
11047 operands[5] = GEN_INT (count);
11048 operands[6] = GEN_INT (put_bit);
11050 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
11052 [(set_attr "type" "delayed_compare")
11053 (set_attr "length" "8,16")])
11056 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11058 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11059 [(match_operand 2 "cc_reg_operand" "")
11061 (match_operand:SI 3 "const_int_operand" ""))
11063 (set (match_operand:SI 4 "gpc_reg_operand" "")
11064 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11067 [(set (match_dup 4)
11068 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11071 (compare:CC (match_dup 4)
11075 ;; There is a 3 cycle delay between consecutive mfcr instructions
11076 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11079 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11080 (match_operator:SI 1 "scc_comparison_operator"
11081 [(match_operand 2 "cc_reg_operand" "y")
11083 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11084 (match_operator:SI 4 "scc_comparison_operator"
11085 [(match_operand 5 "cc_reg_operand" "y")
11087 "REGNO (operands[2]) != REGNO (operands[5])"
11088 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11089 [(set_attr "type" "mfcr")
11090 (set_attr "length" "12")])
11093 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11094 (match_operator:DI 1 "scc_comparison_operator"
11095 [(match_operand 2 "cc_reg_operand" "y")
11097 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11098 (match_operator:DI 4 "scc_comparison_operator"
11099 [(match_operand 5 "cc_reg_operand" "y")
11101 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11102 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11103 [(set_attr "type" "mfcr")
11104 (set_attr "length" "12")])
11106 ;; There are some scc insns that can be done directly, without a compare.
11107 ;; These are faster because they don't involve the communications between
11108 ;; the FXU and branch units. In fact, we will be replacing all of the
11109 ;; integer scc insns here or in the portable methods in emit_store_flag.
11111 ;; Also support (neg (scc ..)) since that construct is used to replace
11112 ;; branches, (plus (scc ..) ..) since that construct is common and
11113 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11114 ;; cases where it is no more expensive than (neg (scc ..)).
11116 ;; Have reload force a constant into a register for the simple insns that
11117 ;; otherwise won't accept constants. We do this because it is faster than
11118 ;; the cmp/mfcr sequence we would otherwise generate.
11120 (define_mode_attr scc_eq_op2 [(SI "rKLI")
11123 (define_insn_and_split "*eq<mode>"
11124 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
11125 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
11126 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
11130 [(set (match_dup 0)
11131 (clz:GPR (match_dup 3)))
11133 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
11135 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11137 /* Use output operand as intermediate. */
11138 operands[3] = operands[0];
11140 if (logical_operand (operands[2], <MODE>mode))
11141 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11142 gen_rtx_XOR (<MODE>mode,
11143 operands[1], operands[2])));
11145 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11146 gen_rtx_PLUS (<MODE>mode, operands[1],
11147 negate_rtx (<MODE>mode,
11151 operands[3] = operands[1];
11153 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11156 (define_insn_and_split "*eq<mode>_compare"
11157 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11159 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
11160 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
11162 (set (match_operand:P 0 "gpc_reg_operand" "=r")
11163 (eq:P (match_dup 1) (match_dup 2)))]
11167 [(set (match_dup 0)
11168 (clz:P (match_dup 4)))
11169 (parallel [(set (match_dup 3)
11170 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
11173 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
11175 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11177 /* Use output operand as intermediate. */
11178 operands[4] = operands[0];
11180 if (logical_operand (operands[2], <MODE>mode))
11181 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11182 gen_rtx_XOR (<MODE>mode,
11183 operands[1], operands[2])));
11185 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11186 gen_rtx_PLUS (<MODE>mode, operands[1],
11187 negate_rtx (<MODE>mode,
11191 operands[4] = operands[1];
11193 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11196 ;; We have insns of the form shown by the first define_insn below. If
11197 ;; there is something inside the comparison operation, we must split it.
11199 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11200 (plus:SI (match_operator 1 "comparison_operator"
11201 [(match_operand:SI 2 "" "")
11202 (match_operand:SI 3
11203 "reg_or_cint_operand" "")])
11204 (match_operand:SI 4 "gpc_reg_operand" "")))
11205 (clobber (match_operand:SI 5 "register_operand" ""))]
11206 "! gpc_reg_operand (operands[2], SImode)"
11207 [(set (match_dup 5) (match_dup 2))
11208 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11212 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11213 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11214 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
11215 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11218 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11219 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11220 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11221 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11222 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
11223 [(set_attr "type" "three,two,three,three,three")
11224 (set_attr "length" "12,8,12,12,12")])
11227 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11230 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11231 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
11232 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11234 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11237 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11238 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
11239 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11240 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11241 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11247 [(set_attr "type" "compare")
11248 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11251 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11254 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11255 (match_operand:SI 2 "scc_eq_operand" ""))
11256 (match_operand:SI 3 "gpc_reg_operand" ""))
11258 (clobber (match_scratch:SI 4 ""))]
11259 "TARGET_32BIT && reload_completed"
11260 [(set (match_dup 4)
11261 (plus:SI (eq:SI (match_dup 1)
11265 (compare:CC (match_dup 4)
11270 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11273 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11274 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
11275 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11277 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11278 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11281 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11282 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
11283 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11284 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11285 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11291 [(set_attr "type" "compare")
11292 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11295 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11298 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11299 (match_operand:SI 2 "scc_eq_operand" ""))
11300 (match_operand:SI 3 "gpc_reg_operand" ""))
11302 (set (match_operand:SI 0 "gpc_reg_operand" "")
11303 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11304 "TARGET_32BIT && reload_completed"
11305 [(set (match_dup 0)
11306 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11308 (compare:CC (match_dup 0)
11312 (define_insn "*neg_eq0<mode>"
11313 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11314 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
11317 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
11318 [(set_attr "type" "two")
11319 (set_attr "length" "8")])
11321 (define_insn_and_split "*neg_eq<mode>"
11322 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11323 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
11324 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
11328 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
11330 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11332 /* Use output operand as intermediate. */
11333 operands[3] = operands[0];
11335 if (logical_operand (operands[2], <MODE>mode))
11336 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11337 gen_rtx_XOR (<MODE>mode,
11338 operands[1], operands[2])));
11340 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11341 gen_rtx_PLUS (<MODE>mode, operands[1],
11342 negate_rtx (<MODE>mode,
11346 operands[3] = operands[1];
11349 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
11350 ;; since it nabs/sr is just as fast.
11351 (define_insn "*ne0si"
11352 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11353 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11355 (clobber (match_scratch:SI 2 "=&r"))]
11356 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
11357 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
11358 [(set_attr "type" "two")
11359 (set_attr "length" "8")])
11361 (define_insn "*ne0di"
11362 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11363 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11365 (clobber (match_scratch:DI 2 "=&r"))]
11367 "addic %2,%1,-1\;subfe %0,%2,%1"
11368 [(set_attr "type" "two")
11369 (set_attr "length" "8")])
11371 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
11373 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11374 (plus:SI (lshiftrt:SI
11375 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11377 (match_operand:SI 2 "gpc_reg_operand" "r")))
11378 (clobber (match_scratch:SI 3 "=&r"))]
11380 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
11381 [(set_attr "type" "two")
11382 (set_attr "length" "8")])
11385 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11386 (plus:DI (lshiftrt:DI
11387 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11389 (match_operand:DI 2 "gpc_reg_operand" "r")))
11390 (clobber (match_scratch:DI 3 "=&r"))]
11392 "addic %3,%1,-1\;addze %0,%2"
11393 [(set_attr "type" "two")
11394 (set_attr "length" "8")])
11397 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11399 (plus:SI (lshiftrt:SI
11400 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11402 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11404 (clobber (match_scratch:SI 3 "=&r,&r"))
11405 (clobber (match_scratch:SI 4 "=X,&r"))]
11408 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
11410 [(set_attr "type" "compare")
11411 (set_attr "length" "8,12")])
11414 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11416 (plus:SI (lshiftrt:SI
11417 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11419 (match_operand:SI 2 "gpc_reg_operand" ""))
11421 (clobber (match_scratch:SI 3 ""))
11422 (clobber (match_scratch:SI 4 ""))]
11423 "TARGET_32BIT && reload_completed"
11424 [(parallel [(set (match_dup 3)
11425 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
11428 (clobber (match_dup 4))])
11430 (compare:CC (match_dup 3)
11435 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11437 (plus:DI (lshiftrt:DI
11438 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11440 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11442 (clobber (match_scratch:DI 3 "=&r,&r"))]
11445 addic %3,%1,-1\;addze. %3,%2
11447 [(set_attr "type" "compare")
11448 (set_attr "length" "8,12")])
11451 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11453 (plus:DI (lshiftrt:DI
11454 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11456 (match_operand:DI 2 "gpc_reg_operand" ""))
11458 (clobber (match_scratch:DI 3 ""))]
11459 "TARGET_64BIT && reload_completed"
11460 [(set (match_dup 3)
11461 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
11465 (compare:CC (match_dup 3)
11470 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11472 (plus:SI (lshiftrt:SI
11473 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11475 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11477 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11478 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11480 (clobber (match_scratch:SI 3 "=&r,&r"))]
11483 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
11485 [(set_attr "type" "compare")
11486 (set_attr "length" "8,12")])
11489 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11491 (plus:SI (lshiftrt:SI
11492 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11494 (match_operand:SI 2 "gpc_reg_operand" ""))
11496 (set (match_operand:SI 0 "gpc_reg_operand" "")
11497 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11499 (clobber (match_scratch:SI 3 ""))]
11500 "TARGET_32BIT && reload_completed"
11501 [(parallel [(set (match_dup 0)
11502 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11504 (clobber (match_dup 3))])
11506 (compare:CC (match_dup 0)
11511 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11513 (plus:DI (lshiftrt:DI
11514 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11516 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11518 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11519 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11521 (clobber (match_scratch:DI 3 "=&r,&r"))]
11524 addic %3,%1,-1\;addze. %0,%2
11526 [(set_attr "type" "compare")
11527 (set_attr "length" "8,12")])
11530 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11532 (plus:DI (lshiftrt:DI
11533 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11535 (match_operand:DI 2 "gpc_reg_operand" ""))
11537 (set (match_operand:DI 0 "gpc_reg_operand" "")
11538 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11540 (clobber (match_scratch:DI 3 ""))]
11541 "TARGET_64BIT && reload_completed"
11542 [(parallel [(set (match_dup 0)
11543 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11545 (clobber (match_dup 3))])
11547 (compare:CC (match_dup 0)
11552 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11553 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11554 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
11555 (clobber (match_scratch:SI 3 "=r,X"))]
11558 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
11559 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
11560 [(set_attr "length" "12")])
11563 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
11565 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11566 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11568 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11569 (le:SI (match_dup 1) (match_dup 2)))
11570 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
11573 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
11574 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
11577 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
11578 (set_attr "length" "12,12,16,16")])
11581 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11583 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11584 (match_operand:SI 2 "reg_or_short_operand" ""))
11586 (set (match_operand:SI 0 "gpc_reg_operand" "")
11587 (le:SI (match_dup 1) (match_dup 2)))
11588 (clobber (match_scratch:SI 3 ""))]
11589 "TARGET_POWER && reload_completed"
11590 [(parallel [(set (match_dup 0)
11591 (le:SI (match_dup 1) (match_dup 2)))
11592 (clobber (match_dup 3))])
11594 (compare:CC (match_dup 0)
11599 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
11600 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11601 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
11602 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
11605 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11606 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
11607 [(set_attr "length" "12")])
11610 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
11612 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11613 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11614 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11616 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11619 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11620 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
11623 [(set_attr "type" "compare")
11624 (set_attr "length" "12,12,16,16")])
11627 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11629 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11630 (match_operand:SI 2 "reg_or_short_operand" ""))
11631 (match_operand:SI 3 "gpc_reg_operand" ""))
11633 (clobber (match_scratch:SI 4 ""))]
11634 "TARGET_POWER && reload_completed"
11635 [(set (match_dup 4)
11636 (plus:SI (le:SI (match_dup 1) (match_dup 2))
11639 (compare:CC (match_dup 4)
11644 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
11646 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11647 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11648 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11650 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
11651 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11654 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11655 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
11658 [(set_attr "type" "compare")
11659 (set_attr "length" "12,12,16,16")])
11662 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11664 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11665 (match_operand:SI 2 "reg_or_short_operand" ""))
11666 (match_operand:SI 3 "gpc_reg_operand" ""))
11668 (set (match_operand:SI 0 "gpc_reg_operand" "")
11669 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11670 "TARGET_POWER && reload_completed"
11671 [(set (match_dup 0)
11672 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11674 (compare:CC (match_dup 0)
11679 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11680 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11681 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
11684 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11685 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
11686 [(set_attr "length" "12")])
11688 (define_insn "*leu<mode>"
11689 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11690 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
11691 (match_operand:P 2 "reg_or_short_operand" "rI")))]
11693 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
11694 [(set_attr "type" "three")
11695 (set_attr "length" "12")])
11697 (define_insn "*leu<mode>_compare"
11698 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11700 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
11701 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
11703 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
11704 (leu:P (match_dup 1) (match_dup 2)))]
11707 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
11709 [(set_attr "type" "compare")
11710 (set_attr "length" "12,16")])
11713 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11715 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
11716 (match_operand:P 2 "reg_or_short_operand" ""))
11718 (set (match_operand:P 0 "gpc_reg_operand" "")
11719 (leu:P (match_dup 1) (match_dup 2)))]
11721 [(set (match_dup 0)
11722 (leu:P (match_dup 1) (match_dup 2)))
11724 (compare:CC (match_dup 0)
11728 (define_insn "*plus_leu<mode>"
11729 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
11730 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
11731 (match_operand:P 2 "reg_or_short_operand" "rI"))
11732 (match_operand:P 3 "gpc_reg_operand" "r")))]
11734 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
11735 [(set_attr "type" "two")
11736 (set_attr "length" "8")])
11739 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11741 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11742 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11743 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11745 (clobber (match_scratch:SI 4 "=&r,&r"))]
11748 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
11750 [(set_attr "type" "compare")
11751 (set_attr "length" "8,12")])
11754 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11756 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11757 (match_operand:SI 2 "reg_or_short_operand" ""))
11758 (match_operand:SI 3 "gpc_reg_operand" ""))
11760 (clobber (match_scratch:SI 4 ""))]
11761 "TARGET_32BIT && reload_completed"
11762 [(set (match_dup 4)
11763 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
11766 (compare:CC (match_dup 4)
11771 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11773 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11774 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11775 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11777 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
11778 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11781 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
11783 [(set_attr "type" "compare")
11784 (set_attr "length" "8,12")])
11787 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11789 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11790 (match_operand:SI 2 "reg_or_short_operand" ""))
11791 (match_operand:SI 3 "gpc_reg_operand" ""))
11793 (set (match_operand:SI 0 "gpc_reg_operand" "")
11794 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11795 "TARGET_32BIT && reload_completed"
11796 [(set (match_dup 0)
11797 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11799 (compare:CC (match_dup 0)
11803 (define_insn "*neg_leu<mode>"
11804 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11805 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
11806 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
11808 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
11809 [(set_attr "type" "three")
11810 (set_attr "length" "12")])
11812 (define_insn "*and_neg_leu<mode>"
11813 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
11815 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
11816 (match_operand:P 2 "reg_or_short_operand" "rI")))
11817 (match_operand:P 3 "gpc_reg_operand" "r")))]
11819 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
11820 [(set_attr "type" "three")
11821 (set_attr "length" "12")])
11824 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11827 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11828 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
11829 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11831 (clobber (match_scratch:SI 4 "=&r,&r"))]
11834 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
11836 [(set_attr "type" "compare")
11837 (set_attr "length" "12,16")])
11840 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11843 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11844 (match_operand:SI 2 "reg_or_short_operand" "")))
11845 (match_operand:SI 3 "gpc_reg_operand" ""))
11847 (clobber (match_scratch:SI 4 ""))]
11848 "TARGET_32BIT && reload_completed"
11849 [(set (match_dup 4)
11850 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
11853 (compare:CC (match_dup 4)
11858 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11861 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11862 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
11863 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11865 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
11866 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
11869 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
11871 [(set_attr "type" "compare")
11872 (set_attr "length" "12,16")])
11875 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11878 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11879 (match_operand:SI 2 "reg_or_short_operand" "")))
11880 (match_operand:SI 3 "gpc_reg_operand" ""))
11882 (set (match_operand:SI 0 "gpc_reg_operand" "")
11883 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
11884 "TARGET_32BIT && reload_completed"
11885 [(set (match_dup 0)
11886 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
11889 (compare:CC (match_dup 0)
11894 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11895 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11896 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11898 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
11899 [(set_attr "length" "12")])
11902 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11904 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11905 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11907 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11908 (lt:SI (match_dup 1) (match_dup 2)))]
11911 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
11913 [(set_attr "type" "delayed_compare")
11914 (set_attr "length" "12,16")])
11917 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11919 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11920 (match_operand:SI 2 "reg_or_short_operand" ""))
11922 (set (match_operand:SI 0 "gpc_reg_operand" "")
11923 (lt:SI (match_dup 1) (match_dup 2)))]
11924 "TARGET_POWER && reload_completed"
11925 [(set (match_dup 0)
11926 (lt:SI (match_dup 1) (match_dup 2)))
11928 (compare:CC (match_dup 0)
11933 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11934 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11935 (match_operand:SI 2 "reg_or_short_operand" "rI"))
11936 (match_operand:SI 3 "gpc_reg_operand" "r")))]
11938 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
11939 [(set_attr "length" "12")])
11942 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11944 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11945 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11946 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11948 (clobber (match_scratch:SI 4 "=&r,&r"))]
11951 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
11953 [(set_attr "type" "compare")
11954 (set_attr "length" "12,16")])
11957 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11959 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11960 (match_operand:SI 2 "reg_or_short_operand" ""))
11961 (match_operand:SI 3 "gpc_reg_operand" ""))
11963 (clobber (match_scratch:SI 4 ""))]
11964 "TARGET_POWER && reload_completed"
11965 [(set (match_dup 4)
11966 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
11969 (compare:CC (match_dup 4)
11974 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11976 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11977 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11978 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11980 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
11981 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11984 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
11986 [(set_attr "type" "compare")
11987 (set_attr "length" "12,16")])
11990 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11992 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11993 (match_operand:SI 2 "reg_or_short_operand" ""))
11994 (match_operand:SI 3 "gpc_reg_operand" ""))
11996 (set (match_operand:SI 0 "gpc_reg_operand" "")
11997 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11998 "TARGET_POWER && reload_completed"
11999 [(set (match_dup 0)
12000 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12002 (compare:CC (match_dup 0)
12007 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12008 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12009 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12011 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12012 [(set_attr "length" "12")])
12014 (define_insn_and_split "*ltu<mode>"
12015 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12016 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12017 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12021 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12022 (set (match_dup 0) (neg:P (match_dup 0)))]
12025 (define_insn_and_split "*ltu<mode>_compare"
12026 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12028 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12029 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12031 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12032 (ltu:P (match_dup 1) (match_dup 2)))]
12036 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12037 (parallel [(set (match_dup 3)
12038 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12039 (set (match_dup 0) (neg:P (match_dup 0)))])]
12042 (define_insn_and_split "*plus_ltu<mode>"
12043 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
12044 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12045 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12046 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
12049 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12050 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12051 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
12054 (define_insn_and_split "*plus_ltu<mode>_compare"
12055 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12057 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12058 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12059 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
12061 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12062 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
12065 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12066 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12067 (parallel [(set (match_dup 4)
12068 (compare:CC (minus:P (match_dup 3) (match_dup 0))
12070 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
12073 (define_insn "*neg_ltu<mode>"
12074 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12075 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12076 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
12079 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12080 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12081 [(set_attr "type" "two")
12082 (set_attr "length" "8")])
12085 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12086 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12087 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12088 (clobber (match_scratch:SI 3 "=r"))]
12090 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
12091 [(set_attr "length" "12")])
12094 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12096 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12097 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12099 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12100 (ge:SI (match_dup 1) (match_dup 2)))
12101 (clobber (match_scratch:SI 3 "=r,r"))]
12104 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12106 [(set_attr "type" "compare")
12107 (set_attr "length" "12,16")])
12110 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12112 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12113 (match_operand:SI 2 "reg_or_short_operand" ""))
12115 (set (match_operand:SI 0 "gpc_reg_operand" "")
12116 (ge:SI (match_dup 1) (match_dup 2)))
12117 (clobber (match_scratch:SI 3 ""))]
12118 "TARGET_POWER && reload_completed"
12119 [(parallel [(set (match_dup 0)
12120 (ge:SI (match_dup 1) (match_dup 2)))
12121 (clobber (match_dup 3))])
12123 (compare:CC (match_dup 0)
12128 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12129 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12130 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12131 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12133 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12134 [(set_attr "length" "12")])
12137 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12139 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12140 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12141 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12143 (clobber (match_scratch:SI 4 "=&r,&r"))]
12146 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12148 [(set_attr "type" "compare")
12149 (set_attr "length" "12,16")])
12152 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12154 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12155 (match_operand:SI 2 "reg_or_short_operand" ""))
12156 (match_operand:SI 3 "gpc_reg_operand" ""))
12158 (clobber (match_scratch:SI 4 ""))]
12159 "TARGET_POWER && reload_completed"
12160 [(set (match_dup 4)
12161 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
12164 (compare:CC (match_dup 4)
12169 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12171 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12172 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12173 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12175 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12176 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12179 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12181 [(set_attr "type" "compare")
12182 (set_attr "length" "12,16")])
12185 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12187 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12188 (match_operand:SI 2 "reg_or_short_operand" ""))
12189 (match_operand:SI 3 "gpc_reg_operand" ""))
12191 (set (match_operand:SI 0 "gpc_reg_operand" "")
12192 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12193 "TARGET_POWER && reload_completed"
12194 [(set (match_dup 0)
12195 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12197 (compare:CC (match_dup 0)
12202 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12203 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12204 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12206 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
12207 [(set_attr "length" "12")])
12209 (define_insn "*geu<mode>"
12210 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12211 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12212 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12215 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12216 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12217 [(set_attr "type" "three")
12218 (set_attr "length" "12")])
12220 (define_insn "*geu<mode>_compare"
12221 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12223 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12224 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12226 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12227 (geu:P (match_dup 1) (match_dup 2)))]
12230 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12231 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12234 [(set_attr "type" "compare")
12235 (set_attr "length" "12,12,16,16")])
12238 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12240 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
12241 (match_operand:P 2 "reg_or_neg_short_operand" ""))
12243 (set (match_operand:P 0 "gpc_reg_operand" "")
12244 (geu:P (match_dup 1) (match_dup 2)))]
12246 [(set (match_dup 0)
12247 (geu:P (match_dup 1) (match_dup 2)))
12249 (compare:CC (match_dup 0)
12253 (define_insn "*plus_geu<mode>"
12254 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12255 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12256 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12257 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12260 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
12261 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
12262 [(set_attr "type" "two")
12263 (set_attr "length" "8")])
12266 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12268 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12269 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12270 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12272 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12275 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
12276 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
12279 [(set_attr "type" "compare")
12280 (set_attr "length" "8,8,12,12")])
12283 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12285 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12286 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12287 (match_operand:SI 3 "gpc_reg_operand" ""))
12289 (clobber (match_scratch:SI 4 ""))]
12290 "TARGET_32BIT && reload_completed"
12291 [(set (match_dup 4)
12292 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12295 (compare:CC (match_dup 4)
12300 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12302 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12303 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12304 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12306 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12307 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12310 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
12311 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
12314 [(set_attr "type" "compare")
12315 (set_attr "length" "8,8,12,12")])
12318 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12320 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12321 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12322 (match_operand:SI 3 "gpc_reg_operand" ""))
12324 (set (match_operand:SI 0 "gpc_reg_operand" "")
12325 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12326 "TARGET_32BIT && reload_completed"
12327 [(set (match_dup 0)
12328 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12330 (compare:CC (match_dup 0)
12334 (define_insn "*neg_geu<mode>"
12335 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12336 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12337 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
12340 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
12341 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
12342 [(set_attr "type" "three")
12343 (set_attr "length" "12")])
12345 (define_insn "*and_neg_geu<mode>"
12346 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12348 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12349 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
12350 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12353 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
12354 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12355 [(set_attr "type" "three")
12356 (set_attr "length" "12")])
12359 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12362 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12363 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12364 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12366 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12369 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12370 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12373 [(set_attr "type" "compare")
12374 (set_attr "length" "12,12,16,16")])
12377 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12380 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12381 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12382 (match_operand:SI 3 "gpc_reg_operand" ""))
12384 (clobber (match_scratch:SI 4 ""))]
12385 "TARGET_32BIT && reload_completed"
12386 [(set (match_dup 4)
12387 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12390 (compare:CC (match_dup 4)
12395 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12398 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12399 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12400 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12402 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12403 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12406 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12407 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12410 [(set_attr "type" "compare")
12411 (set_attr "length" "12,12,16,16")])
12414 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12417 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12418 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12419 (match_operand:SI 3 "gpc_reg_operand" ""))
12421 (set (match_operand:SI 0 "gpc_reg_operand" "")
12422 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12423 "TARGET_32BIT && reload_completed"
12424 [(set (match_dup 0)
12425 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
12427 (compare:CC (match_dup 0)
12432 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12433 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12434 (match_operand:SI 2 "reg_or_short_operand" "r")))]
12436 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12437 [(set_attr "length" "12")])
12440 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12442 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12443 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12445 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12446 (gt:SI (match_dup 1) (match_dup 2)))]
12449 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12451 [(set_attr "type" "delayed_compare")
12452 (set_attr "length" "12,16")])
12455 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12457 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12458 (match_operand:SI 2 "reg_or_short_operand" ""))
12460 (set (match_operand:SI 0 "gpc_reg_operand" "")
12461 (gt:SI (match_dup 1) (match_dup 2)))]
12462 "TARGET_POWER && reload_completed"
12463 [(set (match_dup 0)
12464 (gt:SI (match_dup 1) (match_dup 2)))
12466 (compare:CC (match_dup 0)
12470 (define_insn "*plus_gt0<mode>"
12471 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12472 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
12474 (match_operand:P 2 "gpc_reg_operand" "r")))]
12476 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
12477 [(set_attr "type" "three")
12478 (set_attr "length" "12")])
12481 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12483 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12485 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12487 (clobber (match_scratch:SI 3 "=&r,&r"))]
12490 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
12492 [(set_attr "type" "compare")
12493 (set_attr "length" "12,16")])
12496 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12498 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12500 (match_operand:SI 2 "gpc_reg_operand" ""))
12502 (clobber (match_scratch:SI 3 ""))]
12503 "TARGET_32BIT && reload_completed"
12504 [(set (match_dup 3)
12505 (plus:SI (gt:SI (match_dup 1) (const_int 0))
12508 (compare:CC (match_dup 3)
12513 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12515 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12517 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12519 (clobber (match_scratch:DI 3 "=&r,&r"))]
12522 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
12524 [(set_attr "type" "compare")
12525 (set_attr "length" "12,16")])
12528 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12530 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12532 (match_operand:DI 2 "gpc_reg_operand" ""))
12534 (clobber (match_scratch:DI 3 ""))]
12535 "TARGET_64BIT && reload_completed"
12536 [(set (match_dup 3)
12537 (plus:DI (gt:DI (match_dup 1) (const_int 0))
12540 (compare:CC (match_dup 3)
12545 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12547 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12549 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12551 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12552 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
12555 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
12557 [(set_attr "type" "compare")
12558 (set_attr "length" "12,16")])
12561 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12563 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12565 (match_operand:SI 2 "gpc_reg_operand" ""))
12567 (set (match_operand:SI 0 "gpc_reg_operand" "")
12568 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
12569 "TARGET_32BIT && reload_completed"
12570 [(set (match_dup 0)
12571 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
12573 (compare:CC (match_dup 0)
12578 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12580 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12582 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12584 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
12585 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
12588 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
12590 [(set_attr "type" "compare")
12591 (set_attr "length" "12,16")])
12594 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12596 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12598 (match_operand:DI 2 "gpc_reg_operand" ""))
12600 (set (match_operand:DI 0 "gpc_reg_operand" "")
12601 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
12602 "TARGET_64BIT && reload_completed"
12603 [(set (match_dup 0)
12604 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
12606 (compare:CC (match_dup 0)
12611 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12612 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12613 (match_operand:SI 2 "reg_or_short_operand" "r"))
12614 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12616 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12617 [(set_attr "length" "12")])
12620 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12622 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12623 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12624 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12626 (clobber (match_scratch:SI 4 "=&r,&r"))]
12629 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12631 [(set_attr "type" "compare")
12632 (set_attr "length" "12,16")])
12635 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12637 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12638 (match_operand:SI 2 "reg_or_short_operand" ""))
12639 (match_operand:SI 3 "gpc_reg_operand" ""))
12641 (clobber (match_scratch:SI 4 ""))]
12642 "TARGET_POWER && reload_completed"
12643 [(set (match_dup 4)
12644 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12646 (compare:CC (match_dup 4)
12651 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12653 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12654 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12655 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12657 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12658 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12661 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12663 [(set_attr "type" "compare")
12664 (set_attr "length" "12,16")])
12667 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12669 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12670 (match_operand:SI 2 "reg_or_short_operand" ""))
12671 (match_operand:SI 3 "gpc_reg_operand" ""))
12673 (set (match_operand:SI 0 "gpc_reg_operand" "")
12674 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12675 "TARGET_POWER && reload_completed"
12676 [(set (match_dup 0)
12677 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12679 (compare:CC (match_dup 0)
12684 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12685 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12686 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
12688 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12689 [(set_attr "length" "12")])
12691 (define_insn_and_split "*gtu<mode>"
12692 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12693 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
12694 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12698 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12699 (set (match_dup 0) (neg:P (match_dup 0)))]
12702 (define_insn_and_split "*gtu<mode>_compare"
12703 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12705 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12706 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12708 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12709 (gtu:P (match_dup 1) (match_dup 2)))]
12713 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12714 (parallel [(set (match_dup 3)
12715 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12716 (set (match_dup 0) (neg:P (match_dup 0)))])]
12719 (define_insn_and_split "*plus_gtu<mode>"
12720 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12721 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
12722 (match_operand:P 2 "reg_or_short_operand" "rI"))
12723 (match_operand:P 3 "reg_or_short_operand" "rI")))]
12726 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12727 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12728 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
12731 (define_insn_and_split "*plus_gtu<mode>_compare"
12732 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12734 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12735 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
12736 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
12738 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12739 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
12742 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12743 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12744 (parallel [(set (match_dup 4)
12745 (compare:CC (minus:P (match_dup 3) (match_dup 0))
12747 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
12750 (define_insn "*neg_gtu<mode>"
12751 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12752 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
12753 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12755 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
12756 [(set_attr "type" "two")
12757 (set_attr "length" "8")])
12760 ;; Define both directions of branch and return. If we need a reload
12761 ;; register, we'd rather use CR0 since it is much easier to copy a
12762 ;; register CC value to there.
12766 (if_then_else (match_operator 1 "branch_comparison_operator"
12768 "cc_reg_operand" "y")
12770 (label_ref (match_operand 0 "" ""))
12775 return output_cbranch (operands[1], \"%l0\", 0, insn);
12777 [(set_attr "type" "branch")])
12781 (if_then_else (match_operator 0 "branch_comparison_operator"
12783 "cc_reg_operand" "y")
12790 return output_cbranch (operands[0], NULL, 0, insn);
12792 [(set_attr "type" "branch")
12793 (set_attr "length" "4")])
12797 (if_then_else (match_operator 1 "branch_comparison_operator"
12799 "cc_reg_operand" "y")
12802 (label_ref (match_operand 0 "" ""))))]
12806 return output_cbranch (operands[1], \"%l0\", 1, insn);
12808 [(set_attr "type" "branch")])
12812 (if_then_else (match_operator 0 "branch_comparison_operator"
12814 "cc_reg_operand" "y")
12821 return output_cbranch (operands[0], NULL, 1, insn);
12823 [(set_attr "type" "branch")
12824 (set_attr "length" "4")])
12826 ;; Logic on condition register values.
12828 ; This pattern matches things like
12829 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
12830 ; (eq:SI (reg:CCFP 68) (const_int 0)))
12832 ; which are generated by the branch logic.
12833 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
12835 (define_insn "*cceq_ior_compare"
12836 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
12837 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
12838 [(match_operator:SI 2
12839 "branch_positive_comparison_operator"
12841 "cc_reg_operand" "y,y")
12843 (match_operator:SI 4
12844 "branch_positive_comparison_operator"
12846 "cc_reg_operand" "0,y")
12850 "cr%q1 %E0,%j2,%j4"
12851 [(set_attr "type" "cr_logical,delayed_cr")])
12853 ; Why is the constant -1 here, but 1 in the previous pattern?
12854 ; Because ~1 has all but the low bit set.
12856 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
12857 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
12858 [(not:SI (match_operator:SI 2
12859 "branch_positive_comparison_operator"
12861 "cc_reg_operand" "y,y")
12863 (match_operator:SI 4
12864 "branch_positive_comparison_operator"
12866 "cc_reg_operand" "0,y")
12870 "cr%q1 %E0,%j2,%j4"
12871 [(set_attr "type" "cr_logical,delayed_cr")])
12873 (define_insn "*cceq_rev_compare"
12874 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
12875 (compare:CCEQ (match_operator:SI 1
12876 "branch_positive_comparison_operator"
12878 "cc_reg_operand" "0,y")
12882 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
12883 [(set_attr "type" "cr_logical,delayed_cr")])
12885 ;; If we are comparing the result of two comparisons, this can be done
12886 ;; using creqv or crxor.
12888 (define_insn_and_split ""
12889 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
12890 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
12891 [(match_operand 2 "cc_reg_operand" "y")
12893 (match_operator 3 "branch_comparison_operator"
12894 [(match_operand 4 "cc_reg_operand" "y")
12899 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
12903 int positive_1, positive_2;
12905 positive_1 = branch_positive_comparison_operator (operands[1],
12906 GET_MODE (operands[1]));
12907 positive_2 = branch_positive_comparison_operator (operands[3],
12908 GET_MODE (operands[3]));
12911 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
12912 GET_CODE (operands[1])),
12914 operands[2], const0_rtx);
12915 else if (GET_MODE (operands[1]) != SImode)
12916 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
12917 operands[2], const0_rtx);
12920 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
12921 GET_CODE (operands[3])),
12923 operands[4], const0_rtx);
12924 else if (GET_MODE (operands[3]) != SImode)
12925 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
12926 operands[4], const0_rtx);
12928 if (positive_1 == positive_2)
12930 operands[1] = gen_rtx_NOT (SImode, operands[1]);
12931 operands[5] = constm1_rtx;
12935 operands[5] = const1_rtx;
12939 ;; Unconditional branch and return.
12941 (define_insn "jump"
12943 (label_ref (match_operand 0 "" "")))]
12946 [(set_attr "type" "branch")])
12948 (define_insn "return"
12952 [(set_attr "type" "jmpreg")])
12954 (define_expand "indirect_jump"
12955 [(set (pc) (match_operand 0 "register_operand" ""))])
12957 (define_insn "*indirect_jump<mode>"
12958 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
12963 [(set_attr "type" "jmpreg")])
12965 ;; Table jump for switch statements:
12966 (define_expand "tablejump"
12967 [(use (match_operand 0 "" ""))
12968 (use (label_ref (match_operand 1 "" "")))]
12973 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
12975 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
12979 (define_expand "tablejumpsi"
12980 [(set (match_dup 3)
12981 (plus:SI (match_operand:SI 0 "" "")
12983 (parallel [(set (pc) (match_dup 3))
12984 (use (label_ref (match_operand 1 "" "")))])]
12987 { operands[0] = force_reg (SImode, operands[0]);
12988 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
12989 operands[3] = gen_reg_rtx (SImode);
12992 (define_expand "tablejumpdi"
12993 [(set (match_dup 4)
12994 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
12996 (plus:DI (match_dup 4)
12998 (parallel [(set (pc) (match_dup 3))
12999 (use (label_ref (match_operand 1 "" "")))])]
13002 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13003 operands[3] = gen_reg_rtx (DImode);
13004 operands[4] = gen_reg_rtx (DImode);
13007 (define_insn "*tablejump<mode>_internal1"
13009 (match_operand:P 0 "register_operand" "c,*l"))
13010 (use (label_ref (match_operand 1 "" "")))]
13015 [(set_attr "type" "jmpreg")])
13020 "{cror 0,0,0|nop}")
13022 ;; Define the subtract-one-and-jump insns, starting with the template
13023 ;; so loop.c knows what to generate.
13025 (define_expand "doloop_end"
13026 [(use (match_operand 0 "" "")) ; loop pseudo
13027 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13028 (use (match_operand 2 "" "")) ; max iterations
13029 (use (match_operand 3 "" "")) ; loop level
13030 (use (match_operand 4 "" ""))] ; label
13034 /* Only use this on innermost loops. */
13035 if (INTVAL (operands[3]) > 1)
13039 if (GET_MODE (operands[0]) != DImode)
13041 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13045 if (GET_MODE (operands[0]) != SImode)
13047 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13052 (define_expand "ctr<mode>"
13053 [(parallel [(set (pc)
13054 (if_then_else (ne (match_operand:P 0 "register_operand" "")
13056 (label_ref (match_operand 1 "" ""))
13059 (plus:P (match_dup 0)
13061 (clobber (match_scratch:CC 2 ""))
13062 (clobber (match_scratch:P 3 ""))])]
13066 ;; We need to be able to do this for any operand, including MEM, or we
13067 ;; will cause reload to blow up since we don't allow output reloads on
13069 ;; For the length attribute to be calculated correctly, the
13070 ;; label MUST be operand 0.
13072 (define_insn "*ctr<mode>_internal1"
13074 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13076 (label_ref (match_operand 0 "" ""))
13078 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13079 (plus:P (match_dup 1)
13081 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13082 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13086 if (which_alternative != 0)
13088 else if (get_attr_length (insn) == 4)
13089 return \"{bdn|bdnz} %l0\";
13091 return \"bdz $+8\;b %l0\";
13093 [(set_attr "type" "branch")
13094 (set_attr "length" "*,12,16,16")])
13096 (define_insn "*ctr<mode>_internal2"
13098 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13101 (label_ref (match_operand 0 "" ""))))
13102 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13103 (plus:P (match_dup 1)
13105 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13106 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13110 if (which_alternative != 0)
13112 else if (get_attr_length (insn) == 4)
13113 return \"bdz %l0\";
13115 return \"{bdn|bdnz} $+8\;b %l0\";
13117 [(set_attr "type" "branch")
13118 (set_attr "length" "*,12,16,16")])
13120 ;; Similar but use EQ
13122 (define_insn "*ctr<mode>_internal5"
13124 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13126 (label_ref (match_operand 0 "" ""))
13128 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13129 (plus:P (match_dup 1)
13131 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13132 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13136 if (which_alternative != 0)
13138 else if (get_attr_length (insn) == 4)
13139 return \"bdz %l0\";
13141 return \"{bdn|bdnz} $+8\;b %l0\";
13143 [(set_attr "type" "branch")
13144 (set_attr "length" "*,12,16,16")])
13146 (define_insn "*ctr<mode>_internal6"
13148 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13151 (label_ref (match_operand 0 "" ""))))
13152 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13153 (plus:P (match_dup 1)
13155 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13156 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13160 if (which_alternative != 0)
13162 else if (get_attr_length (insn) == 4)
13163 return \"{bdn|bdnz} %l0\";
13165 return \"bdz $+8\;b %l0\";
13167 [(set_attr "type" "branch")
13168 (set_attr "length" "*,12,16,16")])
13170 ;; Now the splitters if we could not allocate the CTR register
13174 (if_then_else (match_operator 2 "comparison_operator"
13175 [(match_operand:P 1 "gpc_reg_operand" "")
13177 (match_operand 5 "" "")
13178 (match_operand 6 "" "")))
13179 (set (match_operand:P 0 "gpc_reg_operand" "")
13180 (plus:P (match_dup 1) (const_int -1)))
13181 (clobber (match_scratch:CC 3 ""))
13182 (clobber (match_scratch:P 4 ""))]
13184 [(parallel [(set (match_dup 3)
13185 (compare:CC (plus:P (match_dup 1)
13189 (plus:P (match_dup 1)
13191 (set (pc) (if_then_else (match_dup 7)
13195 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13196 operands[3], const0_rtx); }")
13200 (if_then_else (match_operator 2 "comparison_operator"
13201 [(match_operand:P 1 "gpc_reg_operand" "")
13203 (match_operand 5 "" "")
13204 (match_operand 6 "" "")))
13205 (set (match_operand:P 0 "nonimmediate_operand" "")
13206 (plus:P (match_dup 1) (const_int -1)))
13207 (clobber (match_scratch:CC 3 ""))
13208 (clobber (match_scratch:P 4 ""))]
13209 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
13210 [(parallel [(set (match_dup 3)
13211 (compare:CC (plus:P (match_dup 1)
13215 (plus:P (match_dup 1)
13219 (set (pc) (if_then_else (match_dup 7)
13223 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13224 operands[3], const0_rtx); }")
13226 (define_insn "trap"
13227 [(trap_if (const_int 1) (const_int 0))]
13231 (define_expand "conditional_trap"
13232 [(trap_if (match_operator 0 "trap_comparison_operator"
13233 [(match_dup 2) (match_dup 3)])
13234 (match_operand 1 "const_int_operand" ""))]
13236 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
13237 operands[2] = rs6000_compare_op0;
13238 operands[3] = rs6000_compare_op1;")
13241 [(trap_if (match_operator 0 "trap_comparison_operator"
13242 [(match_operand:GPR 1 "register_operand" "r")
13243 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
13246 "{t|t<wd>}%V0%I2 %1,%2")
13248 ;; Insns related to generating the function prologue and epilogue.
13250 (define_expand "prologue"
13251 [(use (const_int 0))]
13252 "TARGET_SCHED_PROLOG"
13255 rs6000_emit_prologue ();
13259 (define_insn "*movesi_from_cr_one"
13260 [(match_parallel 0 "mfcr_operation"
13261 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13262 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
13263 (match_operand 3 "immediate_operand" "n")]
13264 UNSPEC_MOVESI_FROM_CR))])]
13270 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13272 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13273 operands[4] = GEN_INT (mask);
13274 output_asm_insn (\"mfcr %1,%4\", operands);
13278 [(set_attr "type" "mfcrf")])
13280 (define_insn "movesi_from_cr"
13281 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13282 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
13283 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
13284 UNSPEC_MOVESI_FROM_CR))]
13287 [(set_attr "type" "mfcr")])
13289 (define_insn "*stmw"
13290 [(match_parallel 0 "stmw_operation"
13291 [(set (match_operand:SI 1 "memory_operand" "=m")
13292 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13294 "{stm|stmw} %2,%1")
13296 (define_insn "*save_fpregs_<mode>"
13297 [(match_parallel 0 "any_parallel_operand"
13298 [(clobber (match_operand:P 1 "register_operand" "=l"))
13299 (use (match_operand:P 2 "call_operand" "s"))
13300 (set (match_operand:DF 3 "memory_operand" "=m")
13301 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
13304 [(set_attr "type" "branch")
13305 (set_attr "length" "4")])
13307 ; These are to explain that changes to the stack pointer should
13308 ; not be moved over stores to stack memory.
13309 (define_insn "stack_tie"
13310 [(set (match_operand:BLK 0 "memory_operand" "+m")
13311 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
13314 [(set_attr "length" "0")])
13317 (define_expand "epilogue"
13318 [(use (const_int 0))]
13319 "TARGET_SCHED_PROLOG"
13322 rs6000_emit_epilogue (FALSE);
13326 ; On some processors, doing the mtcrf one CC register at a time is
13327 ; faster (like on the 604e). On others, doing them all at once is
13328 ; faster; for instance, on the 601 and 750.
13330 (define_expand "movsi_to_cr_one"
13331 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13332 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13333 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
13335 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
13337 (define_insn "*movsi_to_cr"
13338 [(match_parallel 0 "mtcrf_operation"
13339 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
13340 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
13341 (match_operand 3 "immediate_operand" "n")]
13342 UNSPEC_MOVESI_TO_CR))])]
13348 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13349 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13350 operands[4] = GEN_INT (mask);
13351 return \"mtcrf %4,%2\";
13353 [(set_attr "type" "mtcr")])
13355 (define_insn "*mtcrfsi"
13356 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13357 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13358 (match_operand 2 "immediate_operand" "n")]
13359 UNSPEC_MOVESI_TO_CR))]
13360 "GET_CODE (operands[0]) == REG
13361 && CR_REGNO_P (REGNO (operands[0]))
13362 && GET_CODE (operands[2]) == CONST_INT
13363 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
13365 [(set_attr "type" "mtcr")])
13367 ; The load-multiple instructions have similar properties.
13368 ; Note that "load_multiple" is a name known to the machine-independent
13369 ; code that actually corresponds to the powerpc load-string.
13371 (define_insn "*lmw"
13372 [(match_parallel 0 "lmw_operation"
13373 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13374 (match_operand:SI 2 "memory_operand" "m"))])]
13378 (define_insn "*return_internal_<mode>"
13380 (use (match_operand:P 0 "register_operand" "lc"))]
13383 [(set_attr "type" "jmpreg")])
13385 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
13386 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
13388 (define_insn "*return_and_restore_fpregs_<mode>"
13389 [(match_parallel 0 "any_parallel_operand"
13391 (use (match_operand:P 1 "register_operand" "l"))
13392 (use (match_operand:P 2 "call_operand" "s"))
13393 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
13394 (match_operand:DF 4 "memory_operand" "m"))])]
13398 ; This is used in compiling the unwind routines.
13399 (define_expand "eh_return"
13400 [(use (match_operand 0 "general_operand" ""))]
13405 emit_insn (gen_eh_set_lr_si (operands[0]));
13407 emit_insn (gen_eh_set_lr_di (operands[0]));
13411 ; We can't expand this before we know where the link register is stored.
13412 (define_insn "eh_set_lr_<mode>"
13413 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
13415 (clobber (match_scratch:P 1 "=&b"))]
13420 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
13421 (clobber (match_scratch 1 ""))]
13426 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
13430 (define_insn "prefetch"
13431 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
13432 (match_operand:SI 1 "const_int_operand" "n")
13433 (match_operand:SI 2 "const_int_operand" "n"))]
13437 if (GET_CODE (operands[0]) == REG)
13438 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
13439 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
13441 [(set_attr "type" "load")])
13444 (include "sync.md")
13445 (include "altivec.md")