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rs6000.opt (mmulhw): New option.
[thirdparty/gcc.git] / gcc / config / rs6000 / rs6000.md
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5
6 ;; This file is part of GCC.
7
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 2, or (at your
11 ;; option) any later version.
12
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
17
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to the
20 ;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
21 ;; MA 02110-1301, USA.
22
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
24
25 ;;
26 ;; UNSPEC usage
27 ;;
28
29 (define_constants
30 [(UNSPEC_FRSP 0) ; frsp for POWER machines
31 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
32 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
33 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
34 (UNSPEC_MOVSI_GOT 8)
35 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
36 (UNSPEC_FCTIWZ 10)
37 (UNSPEC_FRIM 11)
38 (UNSPEC_FRIN 12)
39 (UNSPEC_FRIP 13)
40 (UNSPEC_FRIZ 14)
41 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
42 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
43 (UNSPEC_TLSGD 17)
44 (UNSPEC_TLSLD 18)
45 (UNSPEC_MOVESI_FROM_CR 19)
46 (UNSPEC_MOVESI_TO_CR 20)
47 (UNSPEC_TLSDTPREL 21)
48 (UNSPEC_TLSDTPRELHA 22)
49 (UNSPEC_TLSDTPRELLO 23)
50 (UNSPEC_TLSGOTDTPREL 24)
51 (UNSPEC_TLSTPREL 25)
52 (UNSPEC_TLSTPRELHA 26)
53 (UNSPEC_TLSTPRELLO 27)
54 (UNSPEC_TLSGOTTPREL 28)
55 (UNSPEC_TLSTLS 29)
56 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
57 (UNSPEC_MV_CR_GT 31) ; move_from_CR_eq_bit
58 (UNSPEC_STFIWX 32)
59 (UNSPEC_POPCNTB 33)
60 (UNSPEC_FRES 34)
61 (UNSPEC_SP_SET 35)
62 (UNSPEC_SP_TEST 36)
63 (UNSPEC_SYNC 37)
64 (UNSPEC_LWSYNC 38)
65 (UNSPEC_ISYNC 39)
66 (UNSPEC_SYNC_OP 40)
67 (UNSPEC_ATOMIC 41)
68 (UNSPEC_CMPXCHG 42)
69 (UNSPEC_XCHG 43)
70 (UNSPEC_AND 44)
71 ])
72
73 ;;
74 ;; UNSPEC_VOLATILE usage
75 ;;
76
77 (define_constants
78 [(UNSPECV_BLOCK 0)
79 (UNSPECV_LL 1) ; load-locked
80 (UNSPECV_SC 2) ; store-conditional
81 (UNSPECV_EH_RR 9) ; eh_reg_restore
82 ])
83 \f
84 ;; Define an insn type attribute. This is used in function unit delay
85 ;; computations.
86 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c"
87 (const_string "integer"))
88
89 ;; Length (in bytes).
90 ; '(pc)' in the following doesn't include the instruction itself; it is
91 ; calculated as if the instruction had zero size.
92 (define_attr "length" ""
93 (if_then_else (eq_attr "type" "branch")
94 (if_then_else (and (ge (minus (match_dup 0) (pc))
95 (const_int -32768))
96 (lt (minus (match_dup 0) (pc))
97 (const_int 32764)))
98 (const_int 4)
99 (const_int 8))
100 (const_int 4)))
101
102 ;; Processor type -- this attribute must exactly match the processor_type
103 ;; enumeration in rs6000.h.
104
105 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5"
106 (const (symbol_ref "rs6000_cpu_attr")))
107
108 (automata_option "ndfa")
109
110 (include "rios1.md")
111 (include "rios2.md")
112 (include "rs64.md")
113 (include "mpc.md")
114 (include "40x.md")
115 (include "440.md")
116 (include "603.md")
117 (include "6xx.md")
118 (include "7xx.md")
119 (include "7450.md")
120 (include "8540.md")
121 (include "power4.md")
122 (include "power5.md")
123
124 (include "predicates.md")
125
126 (include "darwin.md")
127
128 \f
129 ;; Mode macros
130
131 ; This mode macro allows :GPR to be used to indicate the allowable size
132 ; of whole values in GPRs.
133 (define_mode_macro GPR [SI (DI "TARGET_POWERPC64")])
134
135 ; Any supported integer mode.
136 (define_mode_macro INT [QI HI SI DI TI])
137
138 ; Any supported integer mode that fits in one register.
139 (define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")])
140
141 ; extend modes for DImode
142 (define_mode_macro QHSI [QI HI SI])
143
144 ; SImode or DImode, even if DImode doesn't fit in GPRs.
145 (define_mode_macro SDI [SI DI])
146
147 ; The size of a pointer. Also, the size of the value that a record-condition
148 ; (one with a '.') will compare.
149 (define_mode_macro P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
150
151 ; Any hardware-supported floating-point mode
152 (define_mode_macro FP [(SF "TARGET_HARD_FLOAT")
153 (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
154 (TF "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
155 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128")])
156
157 ; Various instructions that come in SI and DI forms.
158 ; A generic w/d attribute, for things like cmpw/cmpd.
159 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
160
161 ; DImode bits
162 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
163
164 \f
165 ;; Start with fixed-point load and store insns. Here we put only the more
166 ;; complex forms. Basic data transfer is done later.
167
168 (define_expand "zero_extend<mode>di2"
169 [(set (match_operand:DI 0 "gpc_reg_operand" "")
170 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
171 "TARGET_POWERPC64"
172 "")
173
174 (define_insn "*zero_extend<mode>di2_internal1"
175 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
176 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
177 "TARGET_POWERPC64"
178 "@
179 l<wd>z%U1%X1 %0,%1
180 rldicl %0,%1,0,<dbits>"
181 [(set_attr "type" "load,*")])
182
183 (define_insn "*zero_extend<mode>di2_internal2"
184 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
185 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
186 (const_int 0)))
187 (clobber (match_scratch:DI 2 "=r,r"))]
188 "TARGET_64BIT"
189 "@
190 rldicl. %2,%1,0,<dbits>
191 #"
192 [(set_attr "type" "compare")
193 (set_attr "length" "4,8")])
194
195 (define_split
196 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
197 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
198 (const_int 0)))
199 (clobber (match_scratch:DI 2 ""))]
200 "TARGET_POWERPC64 && reload_completed"
201 [(set (match_dup 2)
202 (zero_extend:DI (match_dup 1)))
203 (set (match_dup 0)
204 (compare:CC (match_dup 2)
205 (const_int 0)))]
206 "")
207
208 (define_insn "*zero_extend<mode>di2_internal3"
209 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
210 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
211 (const_int 0)))
212 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
213 (zero_extend:DI (match_dup 1)))]
214 "TARGET_64BIT"
215 "@
216 rldicl. %0,%1,0,<dbits>
217 #"
218 [(set_attr "type" "compare")
219 (set_attr "length" "4,8")])
220
221 (define_split
222 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
223 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
224 (const_int 0)))
225 (set (match_operand:DI 0 "gpc_reg_operand" "")
226 (zero_extend:DI (match_dup 1)))]
227 "TARGET_POWERPC64 && reload_completed"
228 [(set (match_dup 0)
229 (zero_extend:DI (match_dup 1)))
230 (set (match_dup 2)
231 (compare:CC (match_dup 0)
232 (const_int 0)))]
233 "")
234
235 (define_insn "extendqidi2"
236 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
237 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
238 "TARGET_POWERPC64"
239 "extsb %0,%1")
240
241 (define_insn ""
242 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
243 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
244 (const_int 0)))
245 (clobber (match_scratch:DI 2 "=r,r"))]
246 "TARGET_64BIT"
247 "@
248 extsb. %2,%1
249 #"
250 [(set_attr "type" "compare")
251 (set_attr "length" "4,8")])
252
253 (define_split
254 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
255 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
256 (const_int 0)))
257 (clobber (match_scratch:DI 2 ""))]
258 "TARGET_POWERPC64 && reload_completed"
259 [(set (match_dup 2)
260 (sign_extend:DI (match_dup 1)))
261 (set (match_dup 0)
262 (compare:CC (match_dup 2)
263 (const_int 0)))]
264 "")
265
266 (define_insn ""
267 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
268 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
269 (const_int 0)))
270 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
271 (sign_extend:DI (match_dup 1)))]
272 "TARGET_64BIT"
273 "@
274 extsb. %0,%1
275 #"
276 [(set_attr "type" "compare")
277 (set_attr "length" "4,8")])
278
279 (define_split
280 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
281 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
282 (const_int 0)))
283 (set (match_operand:DI 0 "gpc_reg_operand" "")
284 (sign_extend:DI (match_dup 1)))]
285 "TARGET_POWERPC64 && reload_completed"
286 [(set (match_dup 0)
287 (sign_extend:DI (match_dup 1)))
288 (set (match_dup 2)
289 (compare:CC (match_dup 0)
290 (const_int 0)))]
291 "")
292
293 (define_expand "extendhidi2"
294 [(set (match_operand:DI 0 "gpc_reg_operand" "")
295 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
296 "TARGET_POWERPC64"
297 "")
298
299 (define_insn ""
300 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
301 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
302 "TARGET_POWERPC64"
303 "@
304 lha%U1%X1 %0,%1
305 extsh %0,%1"
306 [(set_attr "type" "load_ext,*")])
307
308 (define_insn ""
309 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
310 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
311 (const_int 0)))
312 (clobber (match_scratch:DI 2 "=r,r"))]
313 "TARGET_64BIT"
314 "@
315 extsh. %2,%1
316 #"
317 [(set_attr "type" "compare")
318 (set_attr "length" "4,8")])
319
320 (define_split
321 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
322 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
323 (const_int 0)))
324 (clobber (match_scratch:DI 2 ""))]
325 "TARGET_POWERPC64 && reload_completed"
326 [(set (match_dup 2)
327 (sign_extend:DI (match_dup 1)))
328 (set (match_dup 0)
329 (compare:CC (match_dup 2)
330 (const_int 0)))]
331 "")
332
333 (define_insn ""
334 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
335 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
336 (const_int 0)))
337 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
338 (sign_extend:DI (match_dup 1)))]
339 "TARGET_64BIT"
340 "@
341 extsh. %0,%1
342 #"
343 [(set_attr "type" "compare")
344 (set_attr "length" "4,8")])
345
346 (define_split
347 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
348 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
349 (const_int 0)))
350 (set (match_operand:DI 0 "gpc_reg_operand" "")
351 (sign_extend:DI (match_dup 1)))]
352 "TARGET_POWERPC64 && reload_completed"
353 [(set (match_dup 0)
354 (sign_extend:DI (match_dup 1)))
355 (set (match_dup 2)
356 (compare:CC (match_dup 0)
357 (const_int 0)))]
358 "")
359
360 (define_expand "extendsidi2"
361 [(set (match_operand:DI 0 "gpc_reg_operand" "")
362 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
363 "TARGET_POWERPC64"
364 "")
365
366 (define_insn ""
367 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
368 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
369 "TARGET_POWERPC64"
370 "@
371 lwa%U1%X1 %0,%1
372 extsw %0,%1"
373 [(set_attr "type" "load_ext,*")])
374
375 (define_insn ""
376 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
377 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
378 (const_int 0)))
379 (clobber (match_scratch:DI 2 "=r,r"))]
380 "TARGET_64BIT"
381 "@
382 extsw. %2,%1
383 #"
384 [(set_attr "type" "compare")
385 (set_attr "length" "4,8")])
386
387 (define_split
388 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
389 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
390 (const_int 0)))
391 (clobber (match_scratch:DI 2 ""))]
392 "TARGET_POWERPC64 && reload_completed"
393 [(set (match_dup 2)
394 (sign_extend:DI (match_dup 1)))
395 (set (match_dup 0)
396 (compare:CC (match_dup 2)
397 (const_int 0)))]
398 "")
399
400 (define_insn ""
401 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
402 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
403 (const_int 0)))
404 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
405 (sign_extend:DI (match_dup 1)))]
406 "TARGET_64BIT"
407 "@
408 extsw. %0,%1
409 #"
410 [(set_attr "type" "compare")
411 (set_attr "length" "4,8")])
412
413 (define_split
414 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
415 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
416 (const_int 0)))
417 (set (match_operand:DI 0 "gpc_reg_operand" "")
418 (sign_extend:DI (match_dup 1)))]
419 "TARGET_POWERPC64 && reload_completed"
420 [(set (match_dup 0)
421 (sign_extend:DI (match_dup 1)))
422 (set (match_dup 2)
423 (compare:CC (match_dup 0)
424 (const_int 0)))]
425 "")
426
427 (define_expand "zero_extendqisi2"
428 [(set (match_operand:SI 0 "gpc_reg_operand" "")
429 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
430 ""
431 "")
432
433 (define_insn ""
434 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
435 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
436 ""
437 "@
438 lbz%U1%X1 %0,%1
439 {rlinm|rlwinm} %0,%1,0,0xff"
440 [(set_attr "type" "load,*")])
441
442 (define_insn ""
443 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
444 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
445 (const_int 0)))
446 (clobber (match_scratch:SI 2 "=r,r"))]
447 ""
448 "@
449 {andil.|andi.} %2,%1,0xff
450 #"
451 [(set_attr "type" "compare")
452 (set_attr "length" "4,8")])
453
454 (define_split
455 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
456 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
457 (const_int 0)))
458 (clobber (match_scratch:SI 2 ""))]
459 "reload_completed"
460 [(set (match_dup 2)
461 (zero_extend:SI (match_dup 1)))
462 (set (match_dup 0)
463 (compare:CC (match_dup 2)
464 (const_int 0)))]
465 "")
466
467 (define_insn ""
468 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
469 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
470 (const_int 0)))
471 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
472 (zero_extend:SI (match_dup 1)))]
473 ""
474 "@
475 {andil.|andi.} %0,%1,0xff
476 #"
477 [(set_attr "type" "compare")
478 (set_attr "length" "4,8")])
479
480 (define_split
481 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
482 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
483 (const_int 0)))
484 (set (match_operand:SI 0 "gpc_reg_operand" "")
485 (zero_extend:SI (match_dup 1)))]
486 "reload_completed"
487 [(set (match_dup 0)
488 (zero_extend:SI (match_dup 1)))
489 (set (match_dup 2)
490 (compare:CC (match_dup 0)
491 (const_int 0)))]
492 "")
493
494 (define_expand "extendqisi2"
495 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
496 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
497 ""
498 "
499 {
500 if (TARGET_POWERPC)
501 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
502 else if (TARGET_POWER)
503 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
504 else
505 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
506 DONE;
507 }")
508
509 (define_insn "extendqisi2_ppc"
510 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
511 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
512 "TARGET_POWERPC"
513 "extsb %0,%1")
514
515 (define_insn ""
516 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
517 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
518 (const_int 0)))
519 (clobber (match_scratch:SI 2 "=r,r"))]
520 "TARGET_POWERPC"
521 "@
522 extsb. %2,%1
523 #"
524 [(set_attr "type" "compare")
525 (set_attr "length" "4,8")])
526
527 (define_split
528 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
529 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
530 (const_int 0)))
531 (clobber (match_scratch:SI 2 ""))]
532 "TARGET_POWERPC && reload_completed"
533 [(set (match_dup 2)
534 (sign_extend:SI (match_dup 1)))
535 (set (match_dup 0)
536 (compare:CC (match_dup 2)
537 (const_int 0)))]
538 "")
539
540 (define_insn ""
541 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
542 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
543 (const_int 0)))
544 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
545 (sign_extend:SI (match_dup 1)))]
546 "TARGET_POWERPC"
547 "@
548 extsb. %0,%1
549 #"
550 [(set_attr "type" "compare")
551 (set_attr "length" "4,8")])
552
553 (define_split
554 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
555 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
556 (const_int 0)))
557 (set (match_operand:SI 0 "gpc_reg_operand" "")
558 (sign_extend:SI (match_dup 1)))]
559 "TARGET_POWERPC && reload_completed"
560 [(set (match_dup 0)
561 (sign_extend:SI (match_dup 1)))
562 (set (match_dup 2)
563 (compare:CC (match_dup 0)
564 (const_int 0)))]
565 "")
566
567 (define_expand "extendqisi2_power"
568 [(parallel [(set (match_dup 2)
569 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
570 (const_int 24)))
571 (clobber (scratch:SI))])
572 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
573 (ashiftrt:SI (match_dup 2)
574 (const_int 24)))
575 (clobber (scratch:SI))])]
576 "TARGET_POWER"
577 "
578 { operands[1] = gen_lowpart (SImode, operands[1]);
579 operands[2] = gen_reg_rtx (SImode); }")
580
581 (define_expand "extendqisi2_no_power"
582 [(set (match_dup 2)
583 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
584 (const_int 24)))
585 (set (match_operand:SI 0 "gpc_reg_operand" "")
586 (ashiftrt:SI (match_dup 2)
587 (const_int 24)))]
588 "! TARGET_POWER && ! TARGET_POWERPC"
589 "
590 { operands[1] = gen_lowpart (SImode, operands[1]);
591 operands[2] = gen_reg_rtx (SImode); }")
592
593 (define_expand "zero_extendqihi2"
594 [(set (match_operand:HI 0 "gpc_reg_operand" "")
595 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
596 ""
597 "")
598
599 (define_insn ""
600 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
601 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
602 ""
603 "@
604 lbz%U1%X1 %0,%1
605 {rlinm|rlwinm} %0,%1,0,0xff"
606 [(set_attr "type" "load,*")])
607
608 (define_insn ""
609 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
610 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
611 (const_int 0)))
612 (clobber (match_scratch:HI 2 "=r,r"))]
613 ""
614 "@
615 {andil.|andi.} %2,%1,0xff
616 #"
617 [(set_attr "type" "compare")
618 (set_attr "length" "4,8")])
619
620 (define_split
621 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
622 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
623 (const_int 0)))
624 (clobber (match_scratch:HI 2 ""))]
625 "reload_completed"
626 [(set (match_dup 2)
627 (zero_extend:HI (match_dup 1)))
628 (set (match_dup 0)
629 (compare:CC (match_dup 2)
630 (const_int 0)))]
631 "")
632
633 (define_insn ""
634 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
635 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
636 (const_int 0)))
637 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
638 (zero_extend:HI (match_dup 1)))]
639 ""
640 "@
641 {andil.|andi.} %0,%1,0xff
642 #"
643 [(set_attr "type" "compare")
644 (set_attr "length" "4,8")])
645
646 (define_split
647 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
648 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
649 (const_int 0)))
650 (set (match_operand:HI 0 "gpc_reg_operand" "")
651 (zero_extend:HI (match_dup 1)))]
652 "reload_completed"
653 [(set (match_dup 0)
654 (zero_extend:HI (match_dup 1)))
655 (set (match_dup 2)
656 (compare:CC (match_dup 0)
657 (const_int 0)))]
658 "")
659
660 (define_expand "extendqihi2"
661 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
662 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
663 ""
664 "
665 {
666 if (TARGET_POWERPC)
667 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
668 else if (TARGET_POWER)
669 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
670 else
671 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
672 DONE;
673 }")
674
675 (define_insn "extendqihi2_ppc"
676 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
677 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
678 "TARGET_POWERPC"
679 "extsb %0,%1")
680
681 (define_insn ""
682 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
683 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
684 (const_int 0)))
685 (clobber (match_scratch:HI 2 "=r,r"))]
686 "TARGET_POWERPC"
687 "@
688 extsb. %2,%1
689 #"
690 [(set_attr "type" "compare")
691 (set_attr "length" "4,8")])
692
693 (define_split
694 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
695 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
696 (const_int 0)))
697 (clobber (match_scratch:HI 2 ""))]
698 "TARGET_POWERPC && reload_completed"
699 [(set (match_dup 2)
700 (sign_extend:HI (match_dup 1)))
701 (set (match_dup 0)
702 (compare:CC (match_dup 2)
703 (const_int 0)))]
704 "")
705
706 (define_insn ""
707 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
708 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
709 (const_int 0)))
710 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
711 (sign_extend:HI (match_dup 1)))]
712 "TARGET_POWERPC"
713 "@
714 extsb. %0,%1
715 #"
716 [(set_attr "type" "compare")
717 (set_attr "length" "4,8")])
718
719 (define_split
720 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
721 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
722 (const_int 0)))
723 (set (match_operand:HI 0 "gpc_reg_operand" "")
724 (sign_extend:HI (match_dup 1)))]
725 "TARGET_POWERPC && reload_completed"
726 [(set (match_dup 0)
727 (sign_extend:HI (match_dup 1)))
728 (set (match_dup 2)
729 (compare:CC (match_dup 0)
730 (const_int 0)))]
731 "")
732
733 (define_expand "extendqihi2_power"
734 [(parallel [(set (match_dup 2)
735 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
736 (const_int 24)))
737 (clobber (scratch:SI))])
738 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
739 (ashiftrt:SI (match_dup 2)
740 (const_int 24)))
741 (clobber (scratch:SI))])]
742 "TARGET_POWER"
743 "
744 { operands[0] = gen_lowpart (SImode, operands[0]);
745 operands[1] = gen_lowpart (SImode, operands[1]);
746 operands[2] = gen_reg_rtx (SImode); }")
747
748 (define_expand "extendqihi2_no_power"
749 [(set (match_dup 2)
750 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
751 (const_int 24)))
752 (set (match_operand:HI 0 "gpc_reg_operand" "")
753 (ashiftrt:SI (match_dup 2)
754 (const_int 24)))]
755 "! TARGET_POWER && ! TARGET_POWERPC"
756 "
757 { operands[0] = gen_lowpart (SImode, operands[0]);
758 operands[1] = gen_lowpart (SImode, operands[1]);
759 operands[2] = gen_reg_rtx (SImode); }")
760
761 (define_expand "zero_extendhisi2"
762 [(set (match_operand:SI 0 "gpc_reg_operand" "")
763 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
764 ""
765 "")
766
767 (define_insn ""
768 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
769 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
770 ""
771 "@
772 lhz%U1%X1 %0,%1
773 {rlinm|rlwinm} %0,%1,0,0xffff"
774 [(set_attr "type" "load,*")])
775
776 (define_insn ""
777 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
778 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
779 (const_int 0)))
780 (clobber (match_scratch:SI 2 "=r,r"))]
781 ""
782 "@
783 {andil.|andi.} %2,%1,0xffff
784 #"
785 [(set_attr "type" "compare")
786 (set_attr "length" "4,8")])
787
788 (define_split
789 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
790 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
791 (const_int 0)))
792 (clobber (match_scratch:SI 2 ""))]
793 "reload_completed"
794 [(set (match_dup 2)
795 (zero_extend:SI (match_dup 1)))
796 (set (match_dup 0)
797 (compare:CC (match_dup 2)
798 (const_int 0)))]
799 "")
800
801 (define_insn ""
802 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
803 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
804 (const_int 0)))
805 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
806 (zero_extend:SI (match_dup 1)))]
807 ""
808 "@
809 {andil.|andi.} %0,%1,0xffff
810 #"
811 [(set_attr "type" "compare")
812 (set_attr "length" "4,8")])
813
814 (define_split
815 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
816 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
817 (const_int 0)))
818 (set (match_operand:SI 0 "gpc_reg_operand" "")
819 (zero_extend:SI (match_dup 1)))]
820 "reload_completed"
821 [(set (match_dup 0)
822 (zero_extend:SI (match_dup 1)))
823 (set (match_dup 2)
824 (compare:CC (match_dup 0)
825 (const_int 0)))]
826 "")
827
828 (define_expand "extendhisi2"
829 [(set (match_operand:SI 0 "gpc_reg_operand" "")
830 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
831 ""
832 "")
833
834 (define_insn ""
835 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
836 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
837 ""
838 "@
839 lha%U1%X1 %0,%1
840 {exts|extsh} %0,%1"
841 [(set_attr "type" "load_ext,*")])
842
843 (define_insn ""
844 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
845 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
846 (const_int 0)))
847 (clobber (match_scratch:SI 2 "=r,r"))]
848 ""
849 "@
850 {exts.|extsh.} %2,%1
851 #"
852 [(set_attr "type" "compare")
853 (set_attr "length" "4,8")])
854
855 (define_split
856 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
857 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
858 (const_int 0)))
859 (clobber (match_scratch:SI 2 ""))]
860 "reload_completed"
861 [(set (match_dup 2)
862 (sign_extend:SI (match_dup 1)))
863 (set (match_dup 0)
864 (compare:CC (match_dup 2)
865 (const_int 0)))]
866 "")
867
868 (define_insn ""
869 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
870 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
871 (const_int 0)))
872 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
873 (sign_extend:SI (match_dup 1)))]
874 ""
875 "@
876 {exts.|extsh.} %0,%1
877 #"
878 [(set_attr "type" "compare")
879 (set_attr "length" "4,8")])
880 \f
881 ;; IBM 405 and 440 half-word multiplication operations.
882
883 (define_insn "*macchwc"
884 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
885 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
886 (match_operand:SI 2 "gpc_reg_operand" "r")
887 (const_int 16))
888 (sign_extend:SI
889 (match_operand:HI 1 "gpc_reg_operand" "r")))
890 (match_operand:SI 4 "gpc_reg_operand" "0"))
891 (const_int 0)))
892 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
893 (plus:SI (mult:SI (ashiftrt:SI
894 (match_dup 2)
895 (const_int 16))
896 (sign_extend:SI
897 (match_dup 1)))
898 (match_dup 4)))]
899 "TARGET_MULHW"
900 "macchw. %0, %1, %2"
901 [(set_attr "type" "imul3")])
902
903 (define_insn "*macchw"
904 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
905 (plus:SI (mult:SI (ashiftrt:SI
906 (match_operand:SI 2 "gpc_reg_operand" "r")
907 (const_int 16))
908 (sign_extend:SI
909 (match_operand:HI 1 "gpc_reg_operand" "r")))
910 (match_operand:SI 3 "gpc_reg_operand" "0")))]
911 "TARGET_MULHW"
912 "macchw %0, %1, %2"
913 [(set_attr "type" "imul3")])
914
915 (define_insn "*macchwuc"
916 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
917 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
918 (match_operand:SI 2 "gpc_reg_operand" "r")
919 (const_int 16))
920 (zero_extend:SI
921 (match_operand:HI 1 "gpc_reg_operand" "r")))
922 (match_operand:SI 4 "gpc_reg_operand" "0"))
923 (const_int 0)))
924 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
925 (plus:SI (mult:SI (lshiftrt:SI
926 (match_dup 2)
927 (const_int 16))
928 (zero_extend:SI
929 (match_dup 1)))
930 (match_dup 4)))]
931 "TARGET_MULHW"
932 "macchwu. %0, %1, %2"
933 [(set_attr "type" "imul3")])
934
935 (define_insn "*macchwu"
936 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
937 (plus:SI (mult:SI (lshiftrt:SI
938 (match_operand:SI 2 "gpc_reg_operand" "r")
939 (const_int 16))
940 (zero_extend:SI
941 (match_operand:HI 1 "gpc_reg_operand" "r")))
942 (match_operand:SI 3 "gpc_reg_operand" "0")))]
943 "TARGET_MULHW"
944 "macchwu %0, %1, %2"
945 [(set_attr "type" "imul3")])
946
947 (define_insn "*machhwc"
948 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
949 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
950 (match_operand:SI 1 "gpc_reg_operand" "%r")
951 (const_int 16))
952 (ashiftrt:SI
953 (match_operand:SI 2 "gpc_reg_operand" "r")
954 (const_int 16)))
955 (match_operand:SI 4 "gpc_reg_operand" "0"))
956 (const_int 0)))
957 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
958 (plus:SI (mult:SI (ashiftrt:SI
959 (match_dup 1)
960 (const_int 16))
961 (ashiftrt:SI
962 (match_dup 2)
963 (const_int 16)))
964 (match_dup 4)))]
965 "TARGET_MULHW"
966 "machhw. %0, %1, %2"
967 [(set_attr "type" "imul3")])
968
969 (define_insn "*machhw"
970 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
971 (plus:SI (mult:SI (ashiftrt:SI
972 (match_operand:SI 1 "gpc_reg_operand" "%r")
973 (const_int 16))
974 (ashiftrt:SI
975 (match_operand:SI 2 "gpc_reg_operand" "r")
976 (const_int 16)))
977 (match_operand:SI 3 "gpc_reg_operand" "0")))]
978 "TARGET_MULHW"
979 "machhw %0, %1, %2"
980 [(set_attr "type" "imul3")])
981
982 (define_insn "*machhwuc"
983 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
984 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
985 (match_operand:SI 1 "gpc_reg_operand" "%r")
986 (const_int 16))
987 (lshiftrt:SI
988 (match_operand:SI 2 "gpc_reg_operand" "r")
989 (const_int 16)))
990 (match_operand:SI 4 "gpc_reg_operand" "0"))
991 (const_int 0)))
992 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
993 (plus:SI (mult:SI (lshiftrt:SI
994 (match_dup 1)
995 (const_int 16))
996 (lshiftrt:SI
997 (match_dup 2)
998 (const_int 16)))
999 (match_dup 4)))]
1000 "TARGET_MULHW"
1001 "machhwu. %0, %1, %2"
1002 [(set_attr "type" "imul3")])
1003
1004 (define_insn "*machhwu"
1005 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1006 (plus:SI (mult:SI (lshiftrt:SI
1007 (match_operand:SI 1 "gpc_reg_operand" "%r")
1008 (const_int 16))
1009 (lshiftrt:SI
1010 (match_operand:SI 2 "gpc_reg_operand" "r")
1011 (const_int 16)))
1012 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1013 "TARGET_MULHW"
1014 "machhwu %0, %1, %2"
1015 [(set_attr "type" "imul3")])
1016
1017 (define_insn "*maclhwc"
1018 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1019 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1020 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1021 (sign_extend:SI
1022 (match_operand:HI 2 "gpc_reg_operand" "r")))
1023 (match_operand:SI 4 "gpc_reg_operand" "0"))
1024 (const_int 0)))
1025 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1026 (plus:SI (mult:SI (sign_extend:SI
1027 (match_dup 1))
1028 (sign_extend:SI
1029 (match_dup 2)))
1030 (match_dup 4)))]
1031 "TARGET_MULHW"
1032 "maclhw. %0, %1, %2"
1033 [(set_attr "type" "imul3")])
1034
1035 (define_insn "*maclhw"
1036 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1037 (plus:SI (mult:SI (sign_extend:SI
1038 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1039 (sign_extend:SI
1040 (match_operand:HI 2 "gpc_reg_operand" "r")))
1041 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1042 "TARGET_MULHW"
1043 "maclhw %0, %1, %2"
1044 [(set_attr "type" "imul3")])
1045
1046 (define_insn "*maclhwuc"
1047 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1048 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1049 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1050 (zero_extend:SI
1051 (match_operand:HI 2 "gpc_reg_operand" "r")))
1052 (match_operand:SI 4 "gpc_reg_operand" "0"))
1053 (const_int 0)))
1054 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1055 (plus:SI (mult:SI (zero_extend:SI
1056 (match_dup 1))
1057 (zero_extend:SI
1058 (match_dup 2)))
1059 (match_dup 4)))]
1060 "TARGET_MULHW"
1061 "maclhwu. %0, %1, %2"
1062 [(set_attr "type" "imul3")])
1063
1064 (define_insn "*maclhwu"
1065 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1066 (plus:SI (mult:SI (zero_extend:SI
1067 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1068 (zero_extend:SI
1069 (match_operand:HI 2 "gpc_reg_operand" "r")))
1070 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1071 "TARGET_MULHW"
1072 "maclhwu %0, %1, %2"
1073 [(set_attr "type" "imul3")])
1074
1075 (define_insn "*nmacchwc"
1076 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1077 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1078 (mult:SI (ashiftrt:SI
1079 (match_operand:SI 2 "gpc_reg_operand" "r")
1080 (const_int 16))
1081 (sign_extend:SI
1082 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1083 (const_int 0)))
1084 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1085 (minus:SI (match_dup 4)
1086 (mult:SI (ashiftrt:SI
1087 (match_dup 2)
1088 (const_int 16))
1089 (sign_extend:SI
1090 (match_dup 1)))))]
1091 "TARGET_MULHW"
1092 "nmacchw. %0, %1, %2"
1093 [(set_attr "type" "imul3")])
1094
1095 (define_insn "*nmacchw"
1096 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1097 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1098 (mult:SI (ashiftrt:SI
1099 (match_operand:SI 2 "gpc_reg_operand" "r")
1100 (const_int 16))
1101 (sign_extend:SI
1102 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1103 "TARGET_MULHW"
1104 "nmacchw %0, %1, %2"
1105 [(set_attr "type" "imul3")])
1106
1107 (define_insn "*nmachhwc"
1108 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1109 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1110 (mult:SI (ashiftrt:SI
1111 (match_operand:SI 1 "gpc_reg_operand" "%r")
1112 (const_int 16))
1113 (ashiftrt:SI
1114 (match_operand:SI 2 "gpc_reg_operand" "r")
1115 (const_int 16))))
1116 (const_int 0)))
1117 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1118 (minus:SI (match_dup 4)
1119 (mult:SI (ashiftrt:SI
1120 (match_dup 1)
1121 (const_int 16))
1122 (ashiftrt:SI
1123 (match_dup 2)
1124 (const_int 16)))))]
1125 "TARGET_MULHW"
1126 "nmachhw. %0, %1, %2"
1127 [(set_attr "type" "imul3")])
1128
1129 (define_insn "*nmachhw"
1130 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1131 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1132 (mult:SI (ashiftrt:SI
1133 (match_operand:SI 1 "gpc_reg_operand" "%r")
1134 (const_int 16))
1135 (ashiftrt:SI
1136 (match_operand:SI 2 "gpc_reg_operand" "r")
1137 (const_int 16)))))]
1138 "TARGET_MULHW"
1139 "nmachhw %0, %1, %2"
1140 [(set_attr "type" "imul3")])
1141
1142 (define_insn "*nmaclhwc"
1143 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1144 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1145 (mult:SI (sign_extend:SI
1146 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1147 (sign_extend:SI
1148 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1149 (const_int 0)))
1150 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1151 (minus:SI (match_dup 4)
1152 (mult:SI (sign_extend:SI
1153 (match_dup 1))
1154 (sign_extend:SI
1155 (match_dup 2)))))]
1156 "TARGET_MULHW"
1157 "nmaclhw. %0, %1, %2"
1158 [(set_attr "type" "imul3")])
1159
1160 (define_insn "*nmaclhw"
1161 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1162 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1163 (mult:SI (sign_extend:SI
1164 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1165 (sign_extend:SI
1166 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1167 "TARGET_MULHW"
1168 "nmaclhw %0, %1, %2"
1169 [(set_attr "type" "imul3")])
1170
1171 (define_insn "*mulchwc"
1172 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1173 (compare:CC (mult:SI (ashiftrt:SI
1174 (match_operand:SI 2 "gpc_reg_operand" "r")
1175 (const_int 16))
1176 (sign_extend:SI
1177 (match_operand:HI 1 "gpc_reg_operand" "r")))
1178 (const_int 0)))
1179 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1180 (mult:SI (ashiftrt:SI
1181 (match_dup 2)
1182 (const_int 16))
1183 (sign_extend:SI
1184 (match_dup 1))))]
1185 "TARGET_MULHW"
1186 "mulchw. %0, %1, %2"
1187 [(set_attr "type" "imul3")])
1188
1189 (define_insn "*mulchw"
1190 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1191 (mult:SI (ashiftrt:SI
1192 (match_operand:SI 2 "gpc_reg_operand" "r")
1193 (const_int 16))
1194 (sign_extend:SI
1195 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1196 "TARGET_MULHW"
1197 "mulchw %0, %1, %2"
1198 [(set_attr "type" "imul3")])
1199
1200 (define_insn "*mulchwuc"
1201 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1202 (compare:CC (mult:SI (lshiftrt:SI
1203 (match_operand:SI 2 "gpc_reg_operand" "r")
1204 (const_int 16))
1205 (zero_extend:SI
1206 (match_operand:HI 1 "gpc_reg_operand" "r")))
1207 (const_int 0)))
1208 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1209 (mult:SI (lshiftrt:SI
1210 (match_dup 2)
1211 (const_int 16))
1212 (zero_extend:SI
1213 (match_dup 1))))]
1214 "TARGET_MULHW"
1215 "mulchwu. %0, %1, %2"
1216 [(set_attr "type" "imul3")])
1217
1218 (define_insn "*mulchwu"
1219 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1220 (mult:SI (lshiftrt:SI
1221 (match_operand:SI 2 "gpc_reg_operand" "r")
1222 (const_int 16))
1223 (zero_extend:SI
1224 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1225 "TARGET_MULHW"
1226 "mulchwu %0, %1, %2"
1227 [(set_attr "type" "imul3")])
1228
1229 (define_insn "*mulhhwc"
1230 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1231 (compare:CC (mult:SI (ashiftrt:SI
1232 (match_operand:SI 1 "gpc_reg_operand" "%r")
1233 (const_int 16))
1234 (ashiftrt:SI
1235 (match_operand:SI 2 "gpc_reg_operand" "r")
1236 (const_int 16)))
1237 (const_int 0)))
1238 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1239 (mult:SI (ashiftrt:SI
1240 (match_dup 1)
1241 (const_int 16))
1242 (ashiftrt:SI
1243 (match_dup 2)
1244 (const_int 16))))]
1245 "TARGET_MULHW"
1246 "mulhhw. %0, %1, %2"
1247 [(set_attr "type" "imul3")])
1248
1249 (define_insn "*mulhhw"
1250 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1251 (mult:SI (ashiftrt:SI
1252 (match_operand:SI 1 "gpc_reg_operand" "%r")
1253 (const_int 16))
1254 (ashiftrt:SI
1255 (match_operand:SI 2 "gpc_reg_operand" "r")
1256 (const_int 16))))]
1257 "TARGET_MULHW"
1258 "mulhhw %0, %1, %2"
1259 [(set_attr "type" "imul3")])
1260
1261 (define_insn "*mulhhwuc"
1262 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1263 (compare:CC (mult:SI (lshiftrt:SI
1264 (match_operand:SI 1 "gpc_reg_operand" "%r")
1265 (const_int 16))
1266 (lshiftrt:SI
1267 (match_operand:SI 2 "gpc_reg_operand" "r")
1268 (const_int 16)))
1269 (const_int 0)))
1270 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1271 (mult:SI (lshiftrt:SI
1272 (match_dup 1)
1273 (const_int 16))
1274 (lshiftrt:SI
1275 (match_dup 2)
1276 (const_int 16))))]
1277 "TARGET_MULHW"
1278 "mulhhwu. %0, %1, %2"
1279 [(set_attr "type" "imul3")])
1280
1281 (define_insn "*mulhhwu"
1282 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1283 (mult:SI (lshiftrt:SI
1284 (match_operand:SI 1 "gpc_reg_operand" "%r")
1285 (const_int 16))
1286 (lshiftrt:SI
1287 (match_operand:SI 2 "gpc_reg_operand" "r")
1288 (const_int 16))))]
1289 "TARGET_MULHW"
1290 "mulhhwu %0, %1, %2"
1291 [(set_attr "type" "imul3")])
1292
1293 (define_insn "*mullhwc"
1294 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1295 (compare:CC (mult:SI (sign_extend:SI
1296 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1297 (sign_extend:SI
1298 (match_operand:HI 2 "gpc_reg_operand" "r")))
1299 (const_int 0)))
1300 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1301 (mult:SI (sign_extend:SI
1302 (match_dup 1))
1303 (sign_extend:SI
1304 (match_dup 2))))]
1305 "TARGET_MULHW"
1306 "mullhw. %0, %1, %2"
1307 [(set_attr "type" "imul3")])
1308
1309 (define_insn "*mullhw"
1310 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1311 (mult:SI (sign_extend:SI
1312 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1313 (sign_extend:SI
1314 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1315 "TARGET_MULHW"
1316 "mullhw %0, %1, %2"
1317 [(set_attr "type" "imul3")])
1318
1319 (define_insn "*mullhwuc"
1320 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1321 (compare:CC (mult:SI (zero_extend:SI
1322 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1323 (zero_extend:SI
1324 (match_operand:HI 2 "gpc_reg_operand" "r")))
1325 (const_int 0)))
1326 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1327 (mult:SI (zero_extend:SI
1328 (match_dup 1))
1329 (zero_extend:SI
1330 (match_dup 2))))]
1331 "TARGET_MULHW"
1332 "mullhwu. %0, %1, %2"
1333 [(set_attr "type" "imul3")])
1334
1335 (define_insn "*mullhwu"
1336 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1337 (mult:SI (zero_extend:SI
1338 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1339 (zero_extend:SI
1340 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1341 "TARGET_MULHW"
1342 "mullhwu %0, %1, %2"
1343 [(set_attr "type" "imul3")])
1344 \f
1345 (define_split
1346 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1347 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1348 (const_int 0)))
1349 (set (match_operand:SI 0 "gpc_reg_operand" "")
1350 (sign_extend:SI (match_dup 1)))]
1351 "reload_completed"
1352 [(set (match_dup 0)
1353 (sign_extend:SI (match_dup 1)))
1354 (set (match_dup 2)
1355 (compare:CC (match_dup 0)
1356 (const_int 0)))]
1357 "")
1358
1359 ;; Fixed-point arithmetic insns.
1360
1361 (define_expand "add<mode>3"
1362 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1363 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1364 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1365 ""
1366 "
1367 {
1368 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1369 {
1370 if (non_short_cint_operand (operands[2], DImode))
1371 FAIL;
1372 }
1373 else if (GET_CODE (operands[2]) == CONST_INT
1374 && ! add_operand (operands[2], <MODE>mode))
1375 {
1376 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
1377 ? operands[0] : gen_reg_rtx (<MODE>mode));
1378
1379 HOST_WIDE_INT val = INTVAL (operands[2]);
1380 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1381 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1382
1383 if (<MODE>mode == DImode && !CONST_OK_FOR_LETTER_P (rest, 'L'))
1384 FAIL;
1385
1386 /* The ordering here is important for the prolog expander.
1387 When space is allocated from the stack, adding 'low' first may
1388 produce a temporary deallocation (which would be bad). */
1389 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1390 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1391 DONE;
1392 }
1393 }")
1394
1395 ;; Discourage ai/addic because of carry but provide it in an alternative
1396 ;; allowing register zero as source.
1397 (define_insn "*add<mode>3_internal1"
1398 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1399 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1400 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1401 ""
1402 "@
1403 {cax|add} %0,%1,%2
1404 {cal %0,%2(%1)|addi %0,%1,%2}
1405 {ai|addic} %0,%1,%2
1406 {cau|addis} %0,%1,%v2"
1407 [(set_attr "length" "4,4,4,4")])
1408
1409 (define_insn "addsi3_high"
1410 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1411 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1412 (high:SI (match_operand 2 "" ""))))]
1413 "TARGET_MACHO && !TARGET_64BIT"
1414 "{cau|addis} %0,%1,ha16(%2)"
1415 [(set_attr "length" "4")])
1416
1417 (define_insn "*add<mode>3_internal2"
1418 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1419 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1420 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1421 (const_int 0)))
1422 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1423 ""
1424 "@
1425 {cax.|add.} %3,%1,%2
1426 {ai.|addic.} %3,%1,%2
1427 #
1428 #"
1429 [(set_attr "type" "fast_compare,compare,compare,compare")
1430 (set_attr "length" "4,4,8,8")])
1431
1432 (define_split
1433 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1434 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1435 (match_operand:GPR 2 "reg_or_short_operand" ""))
1436 (const_int 0)))
1437 (clobber (match_scratch:GPR 3 ""))]
1438 "reload_completed"
1439 [(set (match_dup 3)
1440 (plus:GPR (match_dup 1)
1441 (match_dup 2)))
1442 (set (match_dup 0)
1443 (compare:CC (match_dup 3)
1444 (const_int 0)))]
1445 "")
1446
1447 (define_insn "*add<mode>3_internal3"
1448 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1449 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1450 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1451 (const_int 0)))
1452 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1453 (plus:P (match_dup 1)
1454 (match_dup 2)))]
1455 ""
1456 "@
1457 {cax.|add.} %0,%1,%2
1458 {ai.|addic.} %0,%1,%2
1459 #
1460 #"
1461 [(set_attr "type" "fast_compare,compare,compare,compare")
1462 (set_attr "length" "4,4,8,8")])
1463
1464 (define_split
1465 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1466 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1467 (match_operand:P 2 "reg_or_short_operand" ""))
1468 (const_int 0)))
1469 (set (match_operand:P 0 "gpc_reg_operand" "")
1470 (plus:P (match_dup 1) (match_dup 2)))]
1471 "reload_completed"
1472 [(set (match_dup 0)
1473 (plus:P (match_dup 1)
1474 (match_dup 2)))
1475 (set (match_dup 3)
1476 (compare:CC (match_dup 0)
1477 (const_int 0)))]
1478 "")
1479
1480 ;; Split an add that we can't do in one insn into two insns, each of which
1481 ;; does one 16-bit part. This is used by combine. Note that the low-order
1482 ;; add should be last in case the result gets used in an address.
1483
1484 (define_split
1485 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1486 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1487 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1488 ""
1489 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1490 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1491 "
1492 {
1493 HOST_WIDE_INT val = INTVAL (operands[2]);
1494 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1495 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1496
1497 operands[4] = GEN_INT (low);
1498 if (<MODE>mode == SImode || CONST_OK_FOR_LETTER_P (rest, 'L'))
1499 operands[3] = GEN_INT (rest);
1500 else if (! no_new_pseudos)
1501 {
1502 operands[3] = gen_reg_rtx (DImode);
1503 emit_move_insn (operands[3], operands[2]);
1504 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1505 DONE;
1506 }
1507 else
1508 FAIL;
1509 }")
1510
1511 (define_insn "one_cmpl<mode>2"
1512 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1513 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1514 ""
1515 "nor %0,%1,%1")
1516
1517 (define_insn ""
1518 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1519 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1520 (const_int 0)))
1521 (clobber (match_scratch:P 2 "=r,r"))]
1522 ""
1523 "@
1524 nor. %2,%1,%1
1525 #"
1526 [(set_attr "type" "compare")
1527 (set_attr "length" "4,8")])
1528
1529 (define_split
1530 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1531 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1532 (const_int 0)))
1533 (clobber (match_scratch:P 2 ""))]
1534 "reload_completed"
1535 [(set (match_dup 2)
1536 (not:P (match_dup 1)))
1537 (set (match_dup 0)
1538 (compare:CC (match_dup 2)
1539 (const_int 0)))]
1540 "")
1541
1542 (define_insn ""
1543 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1544 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1545 (const_int 0)))
1546 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1547 (not:P (match_dup 1)))]
1548 ""
1549 "@
1550 nor. %0,%1,%1
1551 #"
1552 [(set_attr "type" "compare")
1553 (set_attr "length" "4,8")])
1554
1555 (define_split
1556 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1557 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1558 (const_int 0)))
1559 (set (match_operand:P 0 "gpc_reg_operand" "")
1560 (not:P (match_dup 1)))]
1561 "reload_completed"
1562 [(set (match_dup 0)
1563 (not:P (match_dup 1)))
1564 (set (match_dup 2)
1565 (compare:CC (match_dup 0)
1566 (const_int 0)))]
1567 "")
1568
1569 (define_insn ""
1570 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1571 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1572 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1573 "! TARGET_POWERPC"
1574 "{sf%I1|subf%I1c} %0,%2,%1")
1575
1576 (define_insn ""
1577 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1578 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1579 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1580 "TARGET_POWERPC"
1581 "@
1582 subf %0,%2,%1
1583 subfic %0,%2,%1")
1584
1585 (define_insn ""
1586 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1587 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1588 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1589 (const_int 0)))
1590 (clobber (match_scratch:SI 3 "=r,r"))]
1591 "! TARGET_POWERPC"
1592 "@
1593 {sf.|subfc.} %3,%2,%1
1594 #"
1595 [(set_attr "type" "compare")
1596 (set_attr "length" "4,8")])
1597
1598 (define_insn ""
1599 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1600 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1601 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1602 (const_int 0)))
1603 (clobber (match_scratch:P 3 "=r,r"))]
1604 "TARGET_POWERPC"
1605 "@
1606 subf. %3,%2,%1
1607 #"
1608 [(set_attr "type" "fast_compare")
1609 (set_attr "length" "4,8")])
1610
1611 (define_split
1612 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1613 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1614 (match_operand:P 2 "gpc_reg_operand" ""))
1615 (const_int 0)))
1616 (clobber (match_scratch:P 3 ""))]
1617 "reload_completed"
1618 [(set (match_dup 3)
1619 (minus:P (match_dup 1)
1620 (match_dup 2)))
1621 (set (match_dup 0)
1622 (compare:CC (match_dup 3)
1623 (const_int 0)))]
1624 "")
1625
1626 (define_insn ""
1627 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1628 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1629 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1630 (const_int 0)))
1631 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1632 (minus:SI (match_dup 1) (match_dup 2)))]
1633 "! TARGET_POWERPC"
1634 "@
1635 {sf.|subfc.} %0,%2,%1
1636 #"
1637 [(set_attr "type" "compare")
1638 (set_attr "length" "4,8")])
1639
1640 (define_insn ""
1641 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1642 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1643 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1644 (const_int 0)))
1645 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1646 (minus:P (match_dup 1)
1647 (match_dup 2)))]
1648 "TARGET_POWERPC"
1649 "@
1650 subf. %0,%2,%1
1651 #"
1652 [(set_attr "type" "fast_compare")
1653 (set_attr "length" "4,8")])
1654
1655 (define_split
1656 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1657 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1658 (match_operand:P 2 "gpc_reg_operand" ""))
1659 (const_int 0)))
1660 (set (match_operand:P 0 "gpc_reg_operand" "")
1661 (minus:P (match_dup 1)
1662 (match_dup 2)))]
1663 "reload_completed"
1664 [(set (match_dup 0)
1665 (minus:P (match_dup 1)
1666 (match_dup 2)))
1667 (set (match_dup 3)
1668 (compare:CC (match_dup 0)
1669 (const_int 0)))]
1670 "")
1671
1672 (define_expand "sub<mode>3"
1673 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1674 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1675 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1676 ""
1677 "
1678 {
1679 if (GET_CODE (operands[2]) == CONST_INT)
1680 {
1681 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1682 negate_rtx (<MODE>mode, operands[2])));
1683 DONE;
1684 }
1685 }")
1686
1687 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1688 ;; instruction and some auxiliary computations. Then we just have a single
1689 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1690 ;; combine.
1691
1692 (define_expand "sminsi3"
1693 [(set (match_dup 3)
1694 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1695 (match_operand:SI 2 "reg_or_short_operand" ""))
1696 (const_int 0)
1697 (minus:SI (match_dup 2) (match_dup 1))))
1698 (set (match_operand:SI 0 "gpc_reg_operand" "")
1699 (minus:SI (match_dup 2) (match_dup 3)))]
1700 "TARGET_POWER || TARGET_ISEL"
1701 "
1702 {
1703 if (TARGET_ISEL)
1704 {
1705 operands[2] = force_reg (SImode, operands[2]);
1706 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1707 DONE;
1708 }
1709
1710 operands[3] = gen_reg_rtx (SImode);
1711 }")
1712
1713 (define_split
1714 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1715 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1716 (match_operand:SI 2 "reg_or_short_operand" "")))
1717 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1718 "TARGET_POWER"
1719 [(set (match_dup 3)
1720 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1721 (const_int 0)
1722 (minus:SI (match_dup 2) (match_dup 1))))
1723 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1724 "")
1725
1726 (define_expand "smaxsi3"
1727 [(set (match_dup 3)
1728 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1729 (match_operand:SI 2 "reg_or_short_operand" ""))
1730 (const_int 0)
1731 (minus:SI (match_dup 2) (match_dup 1))))
1732 (set (match_operand:SI 0 "gpc_reg_operand" "")
1733 (plus:SI (match_dup 3) (match_dup 1)))]
1734 "TARGET_POWER || TARGET_ISEL"
1735 "
1736 {
1737 if (TARGET_ISEL)
1738 {
1739 operands[2] = force_reg (SImode, operands[2]);
1740 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1741 DONE;
1742 }
1743 operands[3] = gen_reg_rtx (SImode);
1744 }")
1745
1746 (define_split
1747 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1748 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1749 (match_operand:SI 2 "reg_or_short_operand" "")))
1750 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1751 "TARGET_POWER"
1752 [(set (match_dup 3)
1753 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1754 (const_int 0)
1755 (minus:SI (match_dup 2) (match_dup 1))))
1756 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1757 "")
1758
1759 (define_expand "uminsi3"
1760 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1761 (match_dup 5)))
1762 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1763 (match_dup 5)))
1764 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1765 (const_int 0)
1766 (minus:SI (match_dup 4) (match_dup 3))))
1767 (set (match_operand:SI 0 "gpc_reg_operand" "")
1768 (minus:SI (match_dup 2) (match_dup 3)))]
1769 "TARGET_POWER || TARGET_ISEL"
1770 "
1771 {
1772 if (TARGET_ISEL)
1773 {
1774 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1775 DONE;
1776 }
1777 operands[3] = gen_reg_rtx (SImode);
1778 operands[4] = gen_reg_rtx (SImode);
1779 operands[5] = GEN_INT (-2147483647 - 1);
1780 }")
1781
1782 (define_expand "umaxsi3"
1783 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1784 (match_dup 5)))
1785 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1786 (match_dup 5)))
1787 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1788 (const_int 0)
1789 (minus:SI (match_dup 4) (match_dup 3))))
1790 (set (match_operand:SI 0 "gpc_reg_operand" "")
1791 (plus:SI (match_dup 3) (match_dup 1)))]
1792 "TARGET_POWER || TARGET_ISEL"
1793 "
1794 {
1795 if (TARGET_ISEL)
1796 {
1797 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1798 DONE;
1799 }
1800 operands[3] = gen_reg_rtx (SImode);
1801 operands[4] = gen_reg_rtx (SImode);
1802 operands[5] = GEN_INT (-2147483647 - 1);
1803 }")
1804
1805 (define_insn ""
1806 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1807 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1808 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1809 (const_int 0)
1810 (minus:SI (match_dup 2) (match_dup 1))))]
1811 "TARGET_POWER"
1812 "doz%I2 %0,%1,%2")
1813
1814 (define_insn ""
1815 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1816 (compare:CC
1817 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1818 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1819 (const_int 0)
1820 (minus:SI (match_dup 2) (match_dup 1)))
1821 (const_int 0)))
1822 (clobber (match_scratch:SI 3 "=r,r"))]
1823 "TARGET_POWER"
1824 "@
1825 doz%I2. %3,%1,%2
1826 #"
1827 [(set_attr "type" "delayed_compare")
1828 (set_attr "length" "4,8")])
1829
1830 (define_split
1831 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1832 (compare:CC
1833 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1834 (match_operand:SI 2 "reg_or_short_operand" ""))
1835 (const_int 0)
1836 (minus:SI (match_dup 2) (match_dup 1)))
1837 (const_int 0)))
1838 (clobber (match_scratch:SI 3 ""))]
1839 "TARGET_POWER && reload_completed"
1840 [(set (match_dup 3)
1841 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1842 (const_int 0)
1843 (minus:SI (match_dup 2) (match_dup 1))))
1844 (set (match_dup 0)
1845 (compare:CC (match_dup 3)
1846 (const_int 0)))]
1847 "")
1848
1849 (define_insn ""
1850 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1851 (compare:CC
1852 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1853 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1854 (const_int 0)
1855 (minus:SI (match_dup 2) (match_dup 1)))
1856 (const_int 0)))
1857 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1858 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1859 (const_int 0)
1860 (minus:SI (match_dup 2) (match_dup 1))))]
1861 "TARGET_POWER"
1862 "@
1863 doz%I2. %0,%1,%2
1864 #"
1865 [(set_attr "type" "delayed_compare")
1866 (set_attr "length" "4,8")])
1867
1868 (define_split
1869 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1870 (compare:CC
1871 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1872 (match_operand:SI 2 "reg_or_short_operand" ""))
1873 (const_int 0)
1874 (minus:SI (match_dup 2) (match_dup 1)))
1875 (const_int 0)))
1876 (set (match_operand:SI 0 "gpc_reg_operand" "")
1877 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1878 (const_int 0)
1879 (minus:SI (match_dup 2) (match_dup 1))))]
1880 "TARGET_POWER && reload_completed"
1881 [(set (match_dup 0)
1882 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1883 (const_int 0)
1884 (minus:SI (match_dup 2) (match_dup 1))))
1885 (set (match_dup 3)
1886 (compare:CC (match_dup 0)
1887 (const_int 0)))]
1888 "")
1889
1890 ;; We don't need abs with condition code because such comparisons should
1891 ;; never be done.
1892 (define_expand "abssi2"
1893 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1894 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1895 ""
1896 "
1897 {
1898 if (TARGET_ISEL)
1899 {
1900 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1901 DONE;
1902 }
1903 else if (! TARGET_POWER)
1904 {
1905 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1906 DONE;
1907 }
1908 }")
1909
1910 (define_insn "*abssi2_power"
1911 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1912 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1913 "TARGET_POWER"
1914 "abs %0,%1")
1915
1916 (define_insn_and_split "abssi2_isel"
1917 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1918 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
1919 (clobber (match_scratch:SI 2 "=&b"))
1920 (clobber (match_scratch:CC 3 "=y"))]
1921 "TARGET_ISEL"
1922 "#"
1923 "&& reload_completed"
1924 [(set (match_dup 2) (neg:SI (match_dup 1)))
1925 (set (match_dup 3)
1926 (compare:CC (match_dup 1)
1927 (const_int 0)))
1928 (set (match_dup 0)
1929 (if_then_else:SI (ge (match_dup 3)
1930 (const_int 0))
1931 (match_dup 1)
1932 (match_dup 2)))]
1933 "")
1934
1935 (define_insn_and_split "abssi2_nopower"
1936 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1937 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1938 (clobber (match_scratch:SI 2 "=&r,&r"))]
1939 "! TARGET_POWER && ! TARGET_ISEL"
1940 "#"
1941 "&& reload_completed"
1942 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1943 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1944 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1945 "")
1946
1947 (define_insn "*nabs_power"
1948 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1949 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1950 "TARGET_POWER"
1951 "nabs %0,%1")
1952
1953 (define_insn_and_split "*nabs_nopower"
1954 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1955 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1956 (clobber (match_scratch:SI 2 "=&r,&r"))]
1957 "! TARGET_POWER"
1958 "#"
1959 "&& reload_completed"
1960 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1961 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1962 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1963 "")
1964
1965 (define_expand "neg<mode>2"
1966 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1967 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1968 ""
1969 "")
1970
1971 (define_insn "*neg<mode>2_internal"
1972 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1973 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1974 ""
1975 "neg %0,%1")
1976
1977 (define_insn ""
1978 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1979 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1980 (const_int 0)))
1981 (clobber (match_scratch:P 2 "=r,r"))]
1982 ""
1983 "@
1984 neg. %2,%1
1985 #"
1986 [(set_attr "type" "fast_compare")
1987 (set_attr "length" "4,8")])
1988
1989 (define_split
1990 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1991 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1992 (const_int 0)))
1993 (clobber (match_scratch:P 2 ""))]
1994 "reload_completed"
1995 [(set (match_dup 2)
1996 (neg:P (match_dup 1)))
1997 (set (match_dup 0)
1998 (compare:CC (match_dup 2)
1999 (const_int 0)))]
2000 "")
2001
2002 (define_insn ""
2003 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2004 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2005 (const_int 0)))
2006 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2007 (neg:P (match_dup 1)))]
2008 ""
2009 "@
2010 neg. %0,%1
2011 #"
2012 [(set_attr "type" "fast_compare")
2013 (set_attr "length" "4,8")])
2014
2015 (define_split
2016 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2017 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2018 (const_int 0)))
2019 (set (match_operand:P 0 "gpc_reg_operand" "")
2020 (neg:P (match_dup 1)))]
2021 "reload_completed"
2022 [(set (match_dup 0)
2023 (neg:P (match_dup 1)))
2024 (set (match_dup 2)
2025 (compare:CC (match_dup 0)
2026 (const_int 0)))]
2027 "")
2028
2029 (define_insn "clz<mode>2"
2030 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2031 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2032 ""
2033 "{cntlz|cntlz<wd>} %0,%1")
2034
2035 (define_expand "ctz<mode>2"
2036 [(set (match_dup 2)
2037 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
2038 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2039 (match_dup 2)))
2040 (clobber (scratch:CC))])
2041 (set (match_dup 4) (clz:GPR (match_dup 3)))
2042 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2043 (minus:GPR (match_dup 5) (match_dup 4)))]
2044 ""
2045 {
2046 operands[2] = gen_reg_rtx (<MODE>mode);
2047 operands[3] = gen_reg_rtx (<MODE>mode);
2048 operands[4] = gen_reg_rtx (<MODE>mode);
2049 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2050 })
2051
2052 (define_expand "ffs<mode>2"
2053 [(set (match_dup 2)
2054 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
2055 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2056 (match_dup 2)))
2057 (clobber (scratch:CC))])
2058 (set (match_dup 4) (clz:GPR (match_dup 3)))
2059 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2060 (minus:GPR (match_dup 5) (match_dup 4)))]
2061 ""
2062 {
2063 operands[2] = gen_reg_rtx (<MODE>mode);
2064 operands[3] = gen_reg_rtx (<MODE>mode);
2065 operands[4] = gen_reg_rtx (<MODE>mode);
2066 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2067 })
2068
2069 (define_expand "popcount<mode>2"
2070 [(set (match_dup 2)
2071 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2072 UNSPEC_POPCNTB))
2073 (set (match_dup 3)
2074 (mult:GPR (match_dup 2) (match_dup 4)))
2075 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2076 (lshiftrt:GPR (match_dup 3) (match_dup 5)))]
2077 "TARGET_POPCNTB"
2078 {
2079 operands[2] = gen_reg_rtx (<MODE>mode);
2080 operands[3] = gen_reg_rtx (<MODE>mode);
2081 operands[4] = force_reg (<MODE>mode,
2082 <MODE>mode == SImode
2083 ? GEN_INT (0x01010101)
2084 : GEN_INT ((HOST_WIDE_INT)
2085 0x01010101 << 32 | 0x01010101));
2086 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 8);
2087 })
2088
2089 (define_insn "popcntb<mode>2"
2090 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2091 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2092 UNSPEC_POPCNTB))]
2093 "TARGET_POPCNTB"
2094 "popcntb %0,%1")
2095
2096 (define_expand "mulsi3"
2097 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2098 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2099 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2100 ""
2101 "
2102 {
2103 if (TARGET_POWER)
2104 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2105 else
2106 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2107 DONE;
2108 }")
2109
2110 (define_insn "mulsi3_mq"
2111 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2112 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2113 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2114 (clobber (match_scratch:SI 3 "=q,q"))]
2115 "TARGET_POWER"
2116 "@
2117 {muls|mullw} %0,%1,%2
2118 {muli|mulli} %0,%1,%2"
2119 [(set (attr "type")
2120 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2121 (const_string "imul3")
2122 (match_operand:SI 2 "short_cint_operand" "")
2123 (const_string "imul2")]
2124 (const_string "imul")))])
2125
2126 (define_insn "mulsi3_no_mq"
2127 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2128 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2129 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2130 "! TARGET_POWER"
2131 "@
2132 {muls|mullw} %0,%1,%2
2133 {muli|mulli} %0,%1,%2"
2134 [(set (attr "type")
2135 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2136 (const_string "imul3")
2137 (match_operand:SI 2 "short_cint_operand" "")
2138 (const_string "imul2")]
2139 (const_string "imul")))])
2140
2141 (define_insn "*mulsi3_mq_internal1"
2142 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2143 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2144 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2145 (const_int 0)))
2146 (clobber (match_scratch:SI 3 "=r,r"))
2147 (clobber (match_scratch:SI 4 "=q,q"))]
2148 "TARGET_POWER"
2149 "@
2150 {muls.|mullw.} %3,%1,%2
2151 #"
2152 [(set_attr "type" "imul_compare")
2153 (set_attr "length" "4,8")])
2154
2155 (define_split
2156 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2157 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2158 (match_operand:SI 2 "gpc_reg_operand" ""))
2159 (const_int 0)))
2160 (clobber (match_scratch:SI 3 ""))
2161 (clobber (match_scratch:SI 4 ""))]
2162 "TARGET_POWER && reload_completed"
2163 [(parallel [(set (match_dup 3)
2164 (mult:SI (match_dup 1) (match_dup 2)))
2165 (clobber (match_dup 4))])
2166 (set (match_dup 0)
2167 (compare:CC (match_dup 3)
2168 (const_int 0)))]
2169 "")
2170
2171 (define_insn "*mulsi3_no_mq_internal1"
2172 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2173 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2174 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2175 (const_int 0)))
2176 (clobber (match_scratch:SI 3 "=r,r"))]
2177 "! TARGET_POWER"
2178 "@
2179 {muls.|mullw.} %3,%1,%2
2180 #"
2181 [(set_attr "type" "imul_compare")
2182 (set_attr "length" "4,8")])
2183
2184 (define_split
2185 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2186 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2187 (match_operand:SI 2 "gpc_reg_operand" ""))
2188 (const_int 0)))
2189 (clobber (match_scratch:SI 3 ""))]
2190 "! TARGET_POWER && reload_completed"
2191 [(set (match_dup 3)
2192 (mult:SI (match_dup 1) (match_dup 2)))
2193 (set (match_dup 0)
2194 (compare:CC (match_dup 3)
2195 (const_int 0)))]
2196 "")
2197
2198 (define_insn "*mulsi3_mq_internal2"
2199 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2200 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2201 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2202 (const_int 0)))
2203 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2204 (mult:SI (match_dup 1) (match_dup 2)))
2205 (clobber (match_scratch:SI 4 "=q,q"))]
2206 "TARGET_POWER"
2207 "@
2208 {muls.|mullw.} %0,%1,%2
2209 #"
2210 [(set_attr "type" "imul_compare")
2211 (set_attr "length" "4,8")])
2212
2213 (define_split
2214 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2215 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2216 (match_operand:SI 2 "gpc_reg_operand" ""))
2217 (const_int 0)))
2218 (set (match_operand:SI 0 "gpc_reg_operand" "")
2219 (mult:SI (match_dup 1) (match_dup 2)))
2220 (clobber (match_scratch:SI 4 ""))]
2221 "TARGET_POWER && reload_completed"
2222 [(parallel [(set (match_dup 0)
2223 (mult:SI (match_dup 1) (match_dup 2)))
2224 (clobber (match_dup 4))])
2225 (set (match_dup 3)
2226 (compare:CC (match_dup 0)
2227 (const_int 0)))]
2228 "")
2229
2230 (define_insn "*mulsi3_no_mq_internal2"
2231 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2232 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2233 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2234 (const_int 0)))
2235 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2236 (mult:SI (match_dup 1) (match_dup 2)))]
2237 "! TARGET_POWER"
2238 "@
2239 {muls.|mullw.} %0,%1,%2
2240 #"
2241 [(set_attr "type" "imul_compare")
2242 (set_attr "length" "4,8")])
2243
2244 (define_split
2245 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2246 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2247 (match_operand:SI 2 "gpc_reg_operand" ""))
2248 (const_int 0)))
2249 (set (match_operand:SI 0 "gpc_reg_operand" "")
2250 (mult:SI (match_dup 1) (match_dup 2)))]
2251 "! TARGET_POWER && reload_completed"
2252 [(set (match_dup 0)
2253 (mult:SI (match_dup 1) (match_dup 2)))
2254 (set (match_dup 3)
2255 (compare:CC (match_dup 0)
2256 (const_int 0)))]
2257 "")
2258
2259 ;; Operand 1 is divided by operand 2; quotient goes to operand
2260 ;; 0 and remainder to operand 3.
2261 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2262
2263 (define_expand "divmodsi4"
2264 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2265 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2266 (match_operand:SI 2 "gpc_reg_operand" "")))
2267 (set (match_operand:SI 3 "register_operand" "")
2268 (mod:SI (match_dup 1) (match_dup 2)))])]
2269 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2270 "
2271 {
2272 if (! TARGET_POWER && ! TARGET_POWERPC)
2273 {
2274 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2275 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2276 emit_insn (gen_divss_call ());
2277 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2278 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2279 DONE;
2280 }
2281 }")
2282
2283 (define_insn "*divmodsi4_internal"
2284 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2285 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2286 (match_operand:SI 2 "gpc_reg_operand" "r")))
2287 (set (match_operand:SI 3 "register_operand" "=q")
2288 (mod:SI (match_dup 1) (match_dup 2)))]
2289 "TARGET_POWER"
2290 "divs %0,%1,%2"
2291 [(set_attr "type" "idiv")])
2292
2293 (define_expand "udiv<mode>3"
2294 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2295 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2296 (match_operand:GPR 2 "gpc_reg_operand" "")))]
2297 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2298 "
2299 {
2300 if (! TARGET_POWER && ! TARGET_POWERPC)
2301 {
2302 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2303 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2304 emit_insn (gen_quous_call ());
2305 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2306 DONE;
2307 }
2308 else if (TARGET_POWER)
2309 {
2310 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2311 DONE;
2312 }
2313 }")
2314
2315 (define_insn "udivsi3_mq"
2316 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2317 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2318 (match_operand:SI 2 "gpc_reg_operand" "r")))
2319 (clobber (match_scratch:SI 3 "=q"))]
2320 "TARGET_POWERPC && TARGET_POWER"
2321 "divwu %0,%1,%2"
2322 [(set_attr "type" "idiv")])
2323
2324 (define_insn "*udivsi3_no_mq"
2325 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2326 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2327 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2328 "TARGET_POWERPC && ! TARGET_POWER"
2329 "div<wd>u %0,%1,%2"
2330 [(set_attr "type" "idiv")])
2331
2332 ;; For powers of two we can do srai/aze for divide and then adjust for
2333 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2334 ;; used; for PowerPC, force operands into register and do a normal divide;
2335 ;; for AIX common-mode, use quoss call on register operands.
2336 (define_expand "div<mode>3"
2337 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2338 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2339 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2340 ""
2341 "
2342 {
2343 if (GET_CODE (operands[2]) == CONST_INT
2344 && INTVAL (operands[2]) > 0
2345 && exact_log2 (INTVAL (operands[2])) >= 0)
2346 ;
2347 else if (TARGET_POWERPC)
2348 {
2349 operands[2] = force_reg (SImode, operands[2]);
2350 if (TARGET_POWER)
2351 {
2352 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2353 DONE;
2354 }
2355 }
2356 else if (TARGET_POWER)
2357 FAIL;
2358 else
2359 {
2360 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2361 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2362 emit_insn (gen_quoss_call ());
2363 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2364 DONE;
2365 }
2366 }")
2367
2368 (define_insn "divsi3_mq"
2369 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2370 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2371 (match_operand:SI 2 "gpc_reg_operand" "r")))
2372 (clobber (match_scratch:SI 3 "=q"))]
2373 "TARGET_POWERPC && TARGET_POWER"
2374 "divw %0,%1,%2"
2375 [(set_attr "type" "idiv")])
2376
2377 (define_insn "*div<mode>3_no_mq"
2378 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2379 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2380 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2381 "TARGET_POWERPC && ! TARGET_POWER"
2382 "div<wd> %0,%1,%2"
2383 [(set_attr "type" "idiv")])
2384
2385 (define_expand "mod<mode>3"
2386 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2387 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2388 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2389 ""
2390 "
2391 {
2392 int i;
2393 rtx temp1;
2394 rtx temp2;
2395
2396 if (GET_CODE (operands[2]) != CONST_INT
2397 || INTVAL (operands[2]) <= 0
2398 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2399 FAIL;
2400
2401 temp1 = gen_reg_rtx (<MODE>mode);
2402 temp2 = gen_reg_rtx (<MODE>mode);
2403
2404 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2405 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2406 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2407 DONE;
2408 }")
2409
2410 (define_insn ""
2411 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2412 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2413 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2414 ""
2415 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
2416 [(set_attr "type" "two")
2417 (set_attr "length" "8")])
2418
2419 (define_insn ""
2420 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2421 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2422 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2423 (const_int 0)))
2424 (clobber (match_scratch:P 3 "=r,r"))]
2425 ""
2426 "@
2427 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
2428 #"
2429 [(set_attr "type" "compare")
2430 (set_attr "length" "8,12")])
2431
2432 (define_split
2433 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2434 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2435 (match_operand:GPR 2 "exact_log2_cint_operand"
2436 ""))
2437 (const_int 0)))
2438 (clobber (match_scratch:GPR 3 ""))]
2439 "reload_completed"
2440 [(set (match_dup 3)
2441 (div:<MODE> (match_dup 1) (match_dup 2)))
2442 (set (match_dup 0)
2443 (compare:CC (match_dup 3)
2444 (const_int 0)))]
2445 "")
2446
2447 (define_insn ""
2448 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2449 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2450 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2451 (const_int 0)))
2452 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2453 (div:P (match_dup 1) (match_dup 2)))]
2454 ""
2455 "@
2456 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
2457 #"
2458 [(set_attr "type" "compare")
2459 (set_attr "length" "8,12")])
2460
2461 (define_split
2462 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2463 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2464 (match_operand:GPR 2 "exact_log2_cint_operand"
2465 ""))
2466 (const_int 0)))
2467 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2468 (div:GPR (match_dup 1) (match_dup 2)))]
2469 "reload_completed"
2470 [(set (match_dup 0)
2471 (div:<MODE> (match_dup 1) (match_dup 2)))
2472 (set (match_dup 3)
2473 (compare:CC (match_dup 0)
2474 (const_int 0)))]
2475 "")
2476
2477 (define_insn ""
2478 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2479 (udiv:SI
2480 (plus:DI (ashift:DI
2481 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2482 (const_int 32))
2483 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2484 (match_operand:SI 3 "gpc_reg_operand" "r")))
2485 (set (match_operand:SI 2 "register_operand" "=*q")
2486 (umod:SI
2487 (plus:DI (ashift:DI
2488 (zero_extend:DI (match_dup 1)) (const_int 32))
2489 (zero_extend:DI (match_dup 4)))
2490 (match_dup 3)))]
2491 "TARGET_POWER"
2492 "div %0,%1,%3"
2493 [(set_attr "type" "idiv")])
2494
2495 ;; To do unsigned divide we handle the cases of the divisor looking like a
2496 ;; negative number. If it is a constant that is less than 2**31, we don't
2497 ;; have to worry about the branches. So make a few subroutines here.
2498 ;;
2499 ;; First comes the normal case.
2500 (define_expand "udivmodsi4_normal"
2501 [(set (match_dup 4) (const_int 0))
2502 (parallel [(set (match_operand:SI 0 "" "")
2503 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2504 (const_int 32))
2505 (zero_extend:DI (match_operand:SI 1 "" "")))
2506 (match_operand:SI 2 "" "")))
2507 (set (match_operand:SI 3 "" "")
2508 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2509 (const_int 32))
2510 (zero_extend:DI (match_dup 1)))
2511 (match_dup 2)))])]
2512 "TARGET_POWER"
2513 "
2514 { operands[4] = gen_reg_rtx (SImode); }")
2515
2516 ;; This handles the branches.
2517 (define_expand "udivmodsi4_tests"
2518 [(set (match_operand:SI 0 "" "") (const_int 0))
2519 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2520 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2521 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2522 (label_ref (match_operand:SI 4 "" "")) (pc)))
2523 (set (match_dup 0) (const_int 1))
2524 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2525 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2526 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2527 (label_ref (match_dup 4)) (pc)))]
2528 "TARGET_POWER"
2529 "
2530 { operands[5] = gen_reg_rtx (CCUNSmode);
2531 operands[6] = gen_reg_rtx (CCmode);
2532 }")
2533
2534 (define_expand "udivmodsi4"
2535 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2536 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2537 (match_operand:SI 2 "reg_or_cint_operand" "")))
2538 (set (match_operand:SI 3 "gpc_reg_operand" "")
2539 (umod:SI (match_dup 1) (match_dup 2)))])]
2540 ""
2541 "
2542 {
2543 rtx label = 0;
2544
2545 if (! TARGET_POWER)
2546 {
2547 if (! TARGET_POWERPC)
2548 {
2549 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2550 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2551 emit_insn (gen_divus_call ());
2552 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2553 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2554 DONE;
2555 }
2556 else
2557 FAIL;
2558 }
2559
2560 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2561 {
2562 operands[2] = force_reg (SImode, operands[2]);
2563 label = gen_label_rtx ();
2564 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2565 operands[3], label));
2566 }
2567 else
2568 operands[2] = force_reg (SImode, operands[2]);
2569
2570 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2571 operands[3]));
2572 if (label)
2573 emit_label (label);
2574
2575 DONE;
2576 }")
2577
2578 ;; AIX architecture-independent common-mode multiply (DImode),
2579 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2580 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2581 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2582 ;; assumed unused if generating common-mode, so ignore.
2583 (define_insn "mulh_call"
2584 [(set (reg:SI 3)
2585 (truncate:SI
2586 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2587 (sign_extend:DI (reg:SI 4)))
2588 (const_int 32))))
2589 (clobber (match_scratch:SI 0 "=l"))]
2590 "! TARGET_POWER && ! TARGET_POWERPC"
2591 "bla __mulh"
2592 [(set_attr "type" "imul")])
2593
2594 (define_insn "mull_call"
2595 [(set (reg:DI 3)
2596 (mult:DI (sign_extend:DI (reg:SI 3))
2597 (sign_extend:DI (reg:SI 4))))
2598 (clobber (match_scratch:SI 0 "=l"))
2599 (clobber (reg:SI 0))]
2600 "! TARGET_POWER && ! TARGET_POWERPC"
2601 "bla __mull"
2602 [(set_attr "type" "imul")])
2603
2604 (define_insn "divss_call"
2605 [(set (reg:SI 3)
2606 (div:SI (reg:SI 3) (reg:SI 4)))
2607 (set (reg:SI 4)
2608 (mod:SI (reg:SI 3) (reg:SI 4)))
2609 (clobber (match_scratch:SI 0 "=l"))
2610 (clobber (reg:SI 0))]
2611 "! TARGET_POWER && ! TARGET_POWERPC"
2612 "bla __divss"
2613 [(set_attr "type" "idiv")])
2614
2615 (define_insn "divus_call"
2616 [(set (reg:SI 3)
2617 (udiv:SI (reg:SI 3) (reg:SI 4)))
2618 (set (reg:SI 4)
2619 (umod:SI (reg:SI 3) (reg:SI 4)))
2620 (clobber (match_scratch:SI 0 "=l"))
2621 (clobber (reg:SI 0))
2622 (clobber (match_scratch:CC 1 "=x"))
2623 (clobber (reg:CC 69))]
2624 "! TARGET_POWER && ! TARGET_POWERPC"
2625 "bla __divus"
2626 [(set_attr "type" "idiv")])
2627
2628 (define_insn "quoss_call"
2629 [(set (reg:SI 3)
2630 (div:SI (reg:SI 3) (reg:SI 4)))
2631 (clobber (match_scratch:SI 0 "=l"))]
2632 "! TARGET_POWER && ! TARGET_POWERPC"
2633 "bla __quoss"
2634 [(set_attr "type" "idiv")])
2635
2636 (define_insn "quous_call"
2637 [(set (reg:SI 3)
2638 (udiv:SI (reg:SI 3) (reg:SI 4)))
2639 (clobber (match_scratch:SI 0 "=l"))
2640 (clobber (reg:SI 0))
2641 (clobber (match_scratch:CC 1 "=x"))
2642 (clobber (reg:CC 69))]
2643 "! TARGET_POWER && ! TARGET_POWERPC"
2644 "bla __quous"
2645 [(set_attr "type" "idiv")])
2646 \f
2647 ;; Logical instructions
2648 ;; The logical instructions are mostly combined by using match_operator,
2649 ;; but the plain AND insns are somewhat different because there is no
2650 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2651 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2652
2653 (define_insn "andsi3"
2654 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2655 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2656 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2657 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2658 ""
2659 "@
2660 and %0,%1,%2
2661 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2662 {andil.|andi.} %0,%1,%b2
2663 {andiu.|andis.} %0,%1,%u2"
2664 [(set_attr "type" "*,*,compare,compare")])
2665
2666 ;; Note to set cr's other than cr0 we do the and immediate and then
2667 ;; the test again -- this avoids a mfcr which on the higher end
2668 ;; machines causes an execution serialization
2669
2670 (define_insn "*andsi3_internal2"
2671 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2672 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2673 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2674 (const_int 0)))
2675 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2676 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2677 "TARGET_32BIT"
2678 "@
2679 and. %3,%1,%2
2680 {andil.|andi.} %3,%1,%b2
2681 {andiu.|andis.} %3,%1,%u2
2682 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2683 #
2684 #
2685 #
2686 #"
2687 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2688 (set_attr "length" "4,4,4,4,8,8,8,8")])
2689
2690 (define_insn "*andsi3_internal3"
2691 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2692 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2693 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2694 (const_int 0)))
2695 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2696 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2697 "TARGET_64BIT"
2698 "@
2699 #
2700 {andil.|andi.} %3,%1,%b2
2701 {andiu.|andis.} %3,%1,%u2
2702 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2703 #
2704 #
2705 #
2706 #"
2707 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2708 (set_attr "length" "8,4,4,4,8,8,8,8")])
2709
2710 (define_split
2711 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2712 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2713 (match_operand:GPR 2 "and_operand" ""))
2714 (const_int 0)))
2715 (clobber (match_scratch:GPR 3 ""))
2716 (clobber (match_scratch:CC 4 ""))]
2717 "reload_completed"
2718 [(parallel [(set (match_dup 3)
2719 (and:<MODE> (match_dup 1)
2720 (match_dup 2)))
2721 (clobber (match_dup 4))])
2722 (set (match_dup 0)
2723 (compare:CC (match_dup 3)
2724 (const_int 0)))]
2725 "")
2726
2727 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2728 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2729
2730 (define_split
2731 [(set (match_operand:CC 0 "cc_reg_operand" "")
2732 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2733 (match_operand:SI 2 "gpc_reg_operand" ""))
2734 (const_int 0)))
2735 (clobber (match_scratch:SI 3 ""))
2736 (clobber (match_scratch:CC 4 ""))]
2737 "TARGET_POWERPC64 && reload_completed"
2738 [(parallel [(set (match_dup 3)
2739 (and:SI (match_dup 1)
2740 (match_dup 2)))
2741 (clobber (match_dup 4))])
2742 (set (match_dup 0)
2743 (compare:CC (match_dup 3)
2744 (const_int 0)))]
2745 "")
2746
2747 (define_insn "*andsi3_internal4"
2748 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2749 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2750 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2751 (const_int 0)))
2752 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2753 (and:SI (match_dup 1)
2754 (match_dup 2)))
2755 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2756 "TARGET_32BIT"
2757 "@
2758 and. %0,%1,%2
2759 {andil.|andi.} %0,%1,%b2
2760 {andiu.|andis.} %0,%1,%u2
2761 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2762 #
2763 #
2764 #
2765 #"
2766 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2767 (set_attr "length" "4,4,4,4,8,8,8,8")])
2768
2769 (define_insn "*andsi3_internal5"
2770 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2771 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2772 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2773 (const_int 0)))
2774 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2775 (and:SI (match_dup 1)
2776 (match_dup 2)))
2777 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2778 "TARGET_64BIT"
2779 "@
2780 #
2781 {andil.|andi.} %0,%1,%b2
2782 {andiu.|andis.} %0,%1,%u2
2783 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2784 #
2785 #
2786 #
2787 #"
2788 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2789 (set_attr "length" "8,4,4,4,8,8,8,8")])
2790
2791 (define_split
2792 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2793 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2794 (match_operand:SI 2 "and_operand" ""))
2795 (const_int 0)))
2796 (set (match_operand:SI 0 "gpc_reg_operand" "")
2797 (and:SI (match_dup 1)
2798 (match_dup 2)))
2799 (clobber (match_scratch:CC 4 ""))]
2800 "reload_completed"
2801 [(parallel [(set (match_dup 0)
2802 (and:SI (match_dup 1)
2803 (match_dup 2)))
2804 (clobber (match_dup 4))])
2805 (set (match_dup 3)
2806 (compare:CC (match_dup 0)
2807 (const_int 0)))]
2808 "")
2809
2810 (define_split
2811 [(set (match_operand:CC 3 "cc_reg_operand" "")
2812 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2813 (match_operand:SI 2 "gpc_reg_operand" ""))
2814 (const_int 0)))
2815 (set (match_operand:SI 0 "gpc_reg_operand" "")
2816 (and:SI (match_dup 1)
2817 (match_dup 2)))
2818 (clobber (match_scratch:CC 4 ""))]
2819 "TARGET_POWERPC64 && reload_completed"
2820 [(parallel [(set (match_dup 0)
2821 (and:SI (match_dup 1)
2822 (match_dup 2)))
2823 (clobber (match_dup 4))])
2824 (set (match_dup 3)
2825 (compare:CC (match_dup 0)
2826 (const_int 0)))]
2827 "")
2828
2829 ;; Handle the PowerPC64 rlwinm corner case
2830
2831 (define_insn_and_split "*andsi3_internal6"
2832 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2833 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2834 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2835 "TARGET_POWERPC64"
2836 "#"
2837 "TARGET_POWERPC64"
2838 [(set (match_dup 0)
2839 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2840 (match_dup 4)))
2841 (set (match_dup 0)
2842 (rotate:SI (match_dup 0) (match_dup 5)))]
2843 "
2844 {
2845 int mb = extract_MB (operands[2]);
2846 int me = extract_ME (operands[2]);
2847 operands[3] = GEN_INT (me + 1);
2848 operands[5] = GEN_INT (32 - (me + 1));
2849 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2850 }"
2851 [(set_attr "length" "8")])
2852
2853 (define_expand "iorsi3"
2854 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2855 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2856 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2857 ""
2858 "
2859 {
2860 if (GET_CODE (operands[2]) == CONST_INT
2861 && ! logical_operand (operands[2], SImode))
2862 {
2863 HOST_WIDE_INT value = INTVAL (operands[2]);
2864 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2865 ? operands[0] : gen_reg_rtx (SImode));
2866
2867 emit_insn (gen_iorsi3 (tmp, operands[1],
2868 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2869 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2870 DONE;
2871 }
2872 }")
2873
2874 (define_expand "xorsi3"
2875 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2876 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2877 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2878 ""
2879 "
2880 {
2881 if (GET_CODE (operands[2]) == CONST_INT
2882 && ! logical_operand (operands[2], SImode))
2883 {
2884 HOST_WIDE_INT value = INTVAL (operands[2]);
2885 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2886 ? operands[0] : gen_reg_rtx (SImode));
2887
2888 emit_insn (gen_xorsi3 (tmp, operands[1],
2889 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2890 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2891 DONE;
2892 }
2893 }")
2894
2895 (define_insn "*boolsi3_internal1"
2896 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2897 (match_operator:SI 3 "boolean_or_operator"
2898 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2899 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2900 ""
2901 "@
2902 %q3 %0,%1,%2
2903 {%q3il|%q3i} %0,%1,%b2
2904 {%q3iu|%q3is} %0,%1,%u2")
2905
2906 (define_insn "*boolsi3_internal2"
2907 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2908 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2909 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2910 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2911 (const_int 0)))
2912 (clobber (match_scratch:SI 3 "=r,r"))]
2913 "TARGET_32BIT"
2914 "@
2915 %q4. %3,%1,%2
2916 #"
2917 [(set_attr "type" "compare")
2918 (set_attr "length" "4,8")])
2919
2920 (define_split
2921 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2922 (compare:CC (match_operator:SI 4 "boolean_operator"
2923 [(match_operand:SI 1 "gpc_reg_operand" "")
2924 (match_operand:SI 2 "gpc_reg_operand" "")])
2925 (const_int 0)))
2926 (clobber (match_scratch:SI 3 ""))]
2927 "TARGET_32BIT && reload_completed"
2928 [(set (match_dup 3) (match_dup 4))
2929 (set (match_dup 0)
2930 (compare:CC (match_dup 3)
2931 (const_int 0)))]
2932 "")
2933
2934 (define_insn "*boolsi3_internal3"
2935 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2936 (compare:CC (match_operator:SI 4 "boolean_operator"
2937 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2938 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2939 (const_int 0)))
2940 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2941 (match_dup 4))]
2942 "TARGET_32BIT"
2943 "@
2944 %q4. %0,%1,%2
2945 #"
2946 [(set_attr "type" "compare")
2947 (set_attr "length" "4,8")])
2948
2949 (define_split
2950 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2951 (compare:CC (match_operator:SI 4 "boolean_operator"
2952 [(match_operand:SI 1 "gpc_reg_operand" "")
2953 (match_operand:SI 2 "gpc_reg_operand" "")])
2954 (const_int 0)))
2955 (set (match_operand:SI 0 "gpc_reg_operand" "")
2956 (match_dup 4))]
2957 "TARGET_32BIT && reload_completed"
2958 [(set (match_dup 0) (match_dup 4))
2959 (set (match_dup 3)
2960 (compare:CC (match_dup 0)
2961 (const_int 0)))]
2962 "")
2963
2964 ;; Split a logical operation that we can't do in one insn into two insns,
2965 ;; each of which does one 16-bit part. This is used by combine.
2966
2967 (define_split
2968 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2969 (match_operator:SI 3 "boolean_or_operator"
2970 [(match_operand:SI 1 "gpc_reg_operand" "")
2971 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
2972 ""
2973 [(set (match_dup 0) (match_dup 4))
2974 (set (match_dup 0) (match_dup 5))]
2975 "
2976 {
2977 rtx i;
2978 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2979 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2980 operands[1], i);
2981 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2982 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2983 operands[0], i);
2984 }")
2985
2986 (define_insn "*boolcsi3_internal1"
2987 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2988 (match_operator:SI 3 "boolean_operator"
2989 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2990 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
2991 ""
2992 "%q3 %0,%2,%1")
2993
2994 (define_insn "*boolcsi3_internal2"
2995 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2996 (compare:CC (match_operator:SI 4 "boolean_operator"
2997 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2998 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2999 (const_int 0)))
3000 (clobber (match_scratch:SI 3 "=r,r"))]
3001 "TARGET_32BIT"
3002 "@
3003 %q4. %3,%2,%1
3004 #"
3005 [(set_attr "type" "compare")
3006 (set_attr "length" "4,8")])
3007
3008 (define_split
3009 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3010 (compare:CC (match_operator:SI 4 "boolean_operator"
3011 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3012 (match_operand:SI 2 "gpc_reg_operand" "")])
3013 (const_int 0)))
3014 (clobber (match_scratch:SI 3 ""))]
3015 "TARGET_32BIT && reload_completed"
3016 [(set (match_dup 3) (match_dup 4))
3017 (set (match_dup 0)
3018 (compare:CC (match_dup 3)
3019 (const_int 0)))]
3020 "")
3021
3022 (define_insn "*boolcsi3_internal3"
3023 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3024 (compare:CC (match_operator:SI 4 "boolean_operator"
3025 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3026 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3027 (const_int 0)))
3028 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3029 (match_dup 4))]
3030 "TARGET_32BIT"
3031 "@
3032 %q4. %0,%2,%1
3033 #"
3034 [(set_attr "type" "compare")
3035 (set_attr "length" "4,8")])
3036
3037 (define_split
3038 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3039 (compare:CC (match_operator:SI 4 "boolean_operator"
3040 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3041 (match_operand:SI 2 "gpc_reg_operand" "")])
3042 (const_int 0)))
3043 (set (match_operand:SI 0 "gpc_reg_operand" "")
3044 (match_dup 4))]
3045 "TARGET_32BIT && reload_completed"
3046 [(set (match_dup 0) (match_dup 4))
3047 (set (match_dup 3)
3048 (compare:CC (match_dup 0)
3049 (const_int 0)))]
3050 "")
3051
3052 (define_insn "*boolccsi3_internal1"
3053 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3054 (match_operator:SI 3 "boolean_operator"
3055 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3056 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3057 ""
3058 "%q3 %0,%1,%2")
3059
3060 (define_insn "*boolccsi3_internal2"
3061 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3062 (compare:CC (match_operator:SI 4 "boolean_operator"
3063 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3064 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3065 (const_int 0)))
3066 (clobber (match_scratch:SI 3 "=r,r"))]
3067 "TARGET_32BIT"
3068 "@
3069 %q4. %3,%1,%2
3070 #"
3071 [(set_attr "type" "compare")
3072 (set_attr "length" "4,8")])
3073
3074 (define_split
3075 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3076 (compare:CC (match_operator:SI 4 "boolean_operator"
3077 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3078 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3079 (const_int 0)))
3080 (clobber (match_scratch:SI 3 ""))]
3081 "TARGET_32BIT && reload_completed"
3082 [(set (match_dup 3) (match_dup 4))
3083 (set (match_dup 0)
3084 (compare:CC (match_dup 3)
3085 (const_int 0)))]
3086 "")
3087
3088 (define_insn "*boolccsi3_internal3"
3089 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3090 (compare:CC (match_operator:SI 4 "boolean_operator"
3091 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3092 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3093 (const_int 0)))
3094 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3095 (match_dup 4))]
3096 "TARGET_32BIT"
3097 "@
3098 %q4. %0,%1,%2
3099 #"
3100 [(set_attr "type" "compare")
3101 (set_attr "length" "4,8")])
3102
3103 (define_split
3104 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3105 (compare:CC (match_operator:SI 4 "boolean_operator"
3106 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3107 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3108 (const_int 0)))
3109 (set (match_operand:SI 0 "gpc_reg_operand" "")
3110 (match_dup 4))]
3111 "TARGET_32BIT && reload_completed"
3112 [(set (match_dup 0) (match_dup 4))
3113 (set (match_dup 3)
3114 (compare:CC (match_dup 0)
3115 (const_int 0)))]
3116 "")
3117
3118 ;; maskir insn. We need four forms because things might be in arbitrary
3119 ;; orders. Don't define forms that only set CR fields because these
3120 ;; would modify an input register.
3121
3122 (define_insn "*maskir_internal1"
3123 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3124 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3125 (match_operand:SI 1 "gpc_reg_operand" "0"))
3126 (and:SI (match_dup 2)
3127 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3128 "TARGET_POWER"
3129 "maskir %0,%3,%2")
3130
3131 (define_insn "*maskir_internal2"
3132 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3133 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3134 (match_operand:SI 1 "gpc_reg_operand" "0"))
3135 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3136 (match_dup 2))))]
3137 "TARGET_POWER"
3138 "maskir %0,%3,%2")
3139
3140 (define_insn "*maskir_internal3"
3141 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3142 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3143 (match_operand:SI 3 "gpc_reg_operand" "r"))
3144 (and:SI (not:SI (match_dup 2))
3145 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3146 "TARGET_POWER"
3147 "maskir %0,%3,%2")
3148
3149 (define_insn "*maskir_internal4"
3150 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3151 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3152 (match_operand:SI 2 "gpc_reg_operand" "r"))
3153 (and:SI (not:SI (match_dup 2))
3154 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3155 "TARGET_POWER"
3156 "maskir %0,%3,%2")
3157
3158 (define_insn "*maskir_internal5"
3159 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3160 (compare:CC
3161 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3162 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3163 (and:SI (match_dup 2)
3164 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3165 (const_int 0)))
3166 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3167 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3168 (and:SI (match_dup 2) (match_dup 3))))]
3169 "TARGET_POWER"
3170 "@
3171 maskir. %0,%3,%2
3172 #"
3173 [(set_attr "type" "compare")
3174 (set_attr "length" "4,8")])
3175
3176 (define_split
3177 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3178 (compare:CC
3179 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3180 (match_operand:SI 1 "gpc_reg_operand" ""))
3181 (and:SI (match_dup 2)
3182 (match_operand:SI 3 "gpc_reg_operand" "")))
3183 (const_int 0)))
3184 (set (match_operand:SI 0 "gpc_reg_operand" "")
3185 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3186 (and:SI (match_dup 2) (match_dup 3))))]
3187 "TARGET_POWER && reload_completed"
3188 [(set (match_dup 0)
3189 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3190 (and:SI (match_dup 2) (match_dup 3))))
3191 (set (match_dup 4)
3192 (compare:CC (match_dup 0)
3193 (const_int 0)))]
3194 "")
3195
3196 (define_insn "*maskir_internal6"
3197 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3198 (compare:CC
3199 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3200 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3201 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3202 (match_dup 2)))
3203 (const_int 0)))
3204 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3205 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3206 (and:SI (match_dup 3) (match_dup 2))))]
3207 "TARGET_POWER"
3208 "@
3209 maskir. %0,%3,%2
3210 #"
3211 [(set_attr "type" "compare")
3212 (set_attr "length" "4,8")])
3213
3214 (define_split
3215 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3216 (compare:CC
3217 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3218 (match_operand:SI 1 "gpc_reg_operand" ""))
3219 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3220 (match_dup 2)))
3221 (const_int 0)))
3222 (set (match_operand:SI 0 "gpc_reg_operand" "")
3223 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3224 (and:SI (match_dup 3) (match_dup 2))))]
3225 "TARGET_POWER && reload_completed"
3226 [(set (match_dup 0)
3227 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3228 (and:SI (match_dup 3) (match_dup 2))))
3229 (set (match_dup 4)
3230 (compare:CC (match_dup 0)
3231 (const_int 0)))]
3232 "")
3233
3234 (define_insn "*maskir_internal7"
3235 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3236 (compare:CC
3237 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3238 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3239 (and:SI (not:SI (match_dup 2))
3240 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3241 (const_int 0)))
3242 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3243 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3244 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3245 "TARGET_POWER"
3246 "@
3247 maskir. %0,%3,%2
3248 #"
3249 [(set_attr "type" "compare")
3250 (set_attr "length" "4,8")])
3251
3252 (define_split
3253 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3254 (compare:CC
3255 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3256 (match_operand:SI 3 "gpc_reg_operand" ""))
3257 (and:SI (not:SI (match_dup 2))
3258 (match_operand:SI 1 "gpc_reg_operand" "")))
3259 (const_int 0)))
3260 (set (match_operand:SI 0 "gpc_reg_operand" "")
3261 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3262 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3263 "TARGET_POWER && reload_completed"
3264 [(set (match_dup 0)
3265 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3266 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3267 (set (match_dup 4)
3268 (compare:CC (match_dup 0)
3269 (const_int 0)))]
3270 "")
3271
3272 (define_insn "*maskir_internal8"
3273 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3274 (compare:CC
3275 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3276 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3277 (and:SI (not:SI (match_dup 2))
3278 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3279 (const_int 0)))
3280 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3281 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3282 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3283 "TARGET_POWER"
3284 "@
3285 maskir. %0,%3,%2
3286 #"
3287 [(set_attr "type" "compare")
3288 (set_attr "length" "4,8")])
3289
3290 (define_split
3291 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3292 (compare:CC
3293 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3294 (match_operand:SI 2 "gpc_reg_operand" ""))
3295 (and:SI (not:SI (match_dup 2))
3296 (match_operand:SI 1 "gpc_reg_operand" "")))
3297 (const_int 0)))
3298 (set (match_operand:SI 0 "gpc_reg_operand" "")
3299 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3300 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3301 "TARGET_POWER && reload_completed"
3302 [(set (match_dup 0)
3303 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3304 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3305 (set (match_dup 4)
3306 (compare:CC (match_dup 0)
3307 (const_int 0)))]
3308 "")
3309 \f
3310 ;; Rotate and shift insns, in all their variants. These support shifts,
3311 ;; field inserts and extracts, and various combinations thereof.
3312 (define_expand "insv"
3313 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3314 (match_operand:SI 1 "const_int_operand" "")
3315 (match_operand:SI 2 "const_int_operand" ""))
3316 (match_operand 3 "gpc_reg_operand" ""))]
3317 ""
3318 "
3319 {
3320 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3321 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3322 compiler if the address of the structure is taken later. */
3323 if (GET_CODE (operands[0]) == SUBREG
3324 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3325 FAIL;
3326
3327 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3328 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3329 else
3330 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3331 DONE;
3332 }")
3333
3334 (define_insn "insvsi"
3335 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3336 (match_operand:SI 1 "const_int_operand" "i")
3337 (match_operand:SI 2 "const_int_operand" "i"))
3338 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3339 ""
3340 "*
3341 {
3342 int start = INTVAL (operands[2]) & 31;
3343 int size = INTVAL (operands[1]) & 31;
3344
3345 operands[4] = GEN_INT (32 - start - size);
3346 operands[1] = GEN_INT (start + size - 1);
3347 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3348 }"
3349 [(set_attr "type" "insert_word")])
3350
3351 (define_insn "*insvsi_internal1"
3352 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3353 (match_operand:SI 1 "const_int_operand" "i")
3354 (match_operand:SI 2 "const_int_operand" "i"))
3355 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3356 (match_operand:SI 4 "const_int_operand" "i")))]
3357 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3358 "*
3359 {
3360 int shift = INTVAL (operands[4]) & 31;
3361 int start = INTVAL (operands[2]) & 31;
3362 int size = INTVAL (operands[1]) & 31;
3363
3364 operands[4] = GEN_INT (shift - start - size);
3365 operands[1] = GEN_INT (start + size - 1);
3366 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3367 }"
3368 [(set_attr "type" "insert_word")])
3369
3370 (define_insn "*insvsi_internal2"
3371 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3372 (match_operand:SI 1 "const_int_operand" "i")
3373 (match_operand:SI 2 "const_int_operand" "i"))
3374 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3375 (match_operand:SI 4 "const_int_operand" "i")))]
3376 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3377 "*
3378 {
3379 int shift = INTVAL (operands[4]) & 31;
3380 int start = INTVAL (operands[2]) & 31;
3381 int size = INTVAL (operands[1]) & 31;
3382
3383 operands[4] = GEN_INT (32 - shift - start - size);
3384 operands[1] = GEN_INT (start + size - 1);
3385 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3386 }"
3387 [(set_attr "type" "insert_word")])
3388
3389 (define_insn "*insvsi_internal3"
3390 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3391 (match_operand:SI 1 "const_int_operand" "i")
3392 (match_operand:SI 2 "const_int_operand" "i"))
3393 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3394 (match_operand:SI 4 "const_int_operand" "i")))]
3395 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3396 "*
3397 {
3398 int shift = INTVAL (operands[4]) & 31;
3399 int start = INTVAL (operands[2]) & 31;
3400 int size = INTVAL (operands[1]) & 31;
3401
3402 operands[4] = GEN_INT (32 - shift - start - size);
3403 operands[1] = GEN_INT (start + size - 1);
3404 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3405 }"
3406 [(set_attr "type" "insert_word")])
3407
3408 (define_insn "*insvsi_internal4"
3409 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3410 (match_operand:SI 1 "const_int_operand" "i")
3411 (match_operand:SI 2 "const_int_operand" "i"))
3412 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3413 (match_operand:SI 4 "const_int_operand" "i")
3414 (match_operand:SI 5 "const_int_operand" "i")))]
3415 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3416 "*
3417 {
3418 int extract_start = INTVAL (operands[5]) & 31;
3419 int extract_size = INTVAL (operands[4]) & 31;
3420 int insert_start = INTVAL (operands[2]) & 31;
3421 int insert_size = INTVAL (operands[1]) & 31;
3422
3423 /* Align extract field with insert field */
3424 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3425 operands[1] = GEN_INT (insert_start + insert_size - 1);
3426 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3427 }"
3428 [(set_attr "type" "insert_word")])
3429
3430 ;; combine patterns for rlwimi
3431 (define_insn "*insvsi_internal5"
3432 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3433 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3434 (match_operand:SI 1 "mask_operand" "i"))
3435 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3436 (match_operand:SI 2 "const_int_operand" "i"))
3437 (match_operand:SI 5 "mask_operand" "i"))))]
3438 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3439 "*
3440 {
3441 int me = extract_ME(operands[5]);
3442 int mb = extract_MB(operands[5]);
3443 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3444 operands[2] = GEN_INT(mb);
3445 operands[1] = GEN_INT(me);
3446 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3447 }"
3448 [(set_attr "type" "insert_word")])
3449
3450 (define_insn "*insvsi_internal6"
3451 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3452 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3453 (match_operand:SI 2 "const_int_operand" "i"))
3454 (match_operand:SI 5 "mask_operand" "i"))
3455 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3456 (match_operand:SI 1 "mask_operand" "i"))))]
3457 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3458 "*
3459 {
3460 int me = extract_ME(operands[5]);
3461 int mb = extract_MB(operands[5]);
3462 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3463 operands[2] = GEN_INT(mb);
3464 operands[1] = GEN_INT(me);
3465 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3466 }"
3467 [(set_attr "type" "insert_word")])
3468
3469 (define_insn "insvdi"
3470 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3471 (match_operand:SI 1 "const_int_operand" "i")
3472 (match_operand:SI 2 "const_int_operand" "i"))
3473 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3474 "TARGET_POWERPC64"
3475 "*
3476 {
3477 int start = INTVAL (operands[2]) & 63;
3478 int size = INTVAL (operands[1]) & 63;
3479
3480 operands[1] = GEN_INT (64 - start - size);
3481 return \"rldimi %0,%3,%H1,%H2\";
3482 }")
3483
3484 (define_insn "*insvdi_internal2"
3485 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3486 (match_operand:SI 1 "const_int_operand" "i")
3487 (match_operand:SI 2 "const_int_operand" "i"))
3488 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3489 (match_operand:SI 4 "const_int_operand" "i")))]
3490 "TARGET_POWERPC64
3491 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3492 "*
3493 {
3494 int shift = INTVAL (operands[4]) & 63;
3495 int start = (INTVAL (operands[2]) & 63) - 32;
3496 int size = INTVAL (operands[1]) & 63;
3497
3498 operands[4] = GEN_INT (64 - shift - start - size);
3499 operands[2] = GEN_INT (start);
3500 operands[1] = GEN_INT (start + size - 1);
3501 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3502 }")
3503
3504 (define_insn "*insvdi_internal3"
3505 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3506 (match_operand:SI 1 "const_int_operand" "i")
3507 (match_operand:SI 2 "const_int_operand" "i"))
3508 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3509 (match_operand:SI 4 "const_int_operand" "i")))]
3510 "TARGET_POWERPC64
3511 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3512 "*
3513 {
3514 int shift = INTVAL (operands[4]) & 63;
3515 int start = (INTVAL (operands[2]) & 63) - 32;
3516 int size = INTVAL (operands[1]) & 63;
3517
3518 operands[4] = GEN_INT (64 - shift - start - size);
3519 operands[2] = GEN_INT (start);
3520 operands[1] = GEN_INT (start + size - 1);
3521 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3522 }")
3523
3524 (define_expand "extzv"
3525 [(set (match_operand 0 "gpc_reg_operand" "")
3526 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3527 (match_operand:SI 2 "const_int_operand" "")
3528 (match_operand:SI 3 "const_int_operand" "")))]
3529 ""
3530 "
3531 {
3532 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3533 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3534 compiler if the address of the structure is taken later. */
3535 if (GET_CODE (operands[0]) == SUBREG
3536 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3537 FAIL;
3538
3539 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3540 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3541 else
3542 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3543 DONE;
3544 }")
3545
3546 (define_insn "extzvsi"
3547 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3548 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3549 (match_operand:SI 2 "const_int_operand" "i")
3550 (match_operand:SI 3 "const_int_operand" "i")))]
3551 ""
3552 "*
3553 {
3554 int start = INTVAL (operands[3]) & 31;
3555 int size = INTVAL (operands[2]) & 31;
3556
3557 if (start + size >= 32)
3558 operands[3] = const0_rtx;
3559 else
3560 operands[3] = GEN_INT (start + size);
3561 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3562 }")
3563
3564 (define_insn "*extzvsi_internal1"
3565 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3566 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3567 (match_operand:SI 2 "const_int_operand" "i,i")
3568 (match_operand:SI 3 "const_int_operand" "i,i"))
3569 (const_int 0)))
3570 (clobber (match_scratch:SI 4 "=r,r"))]
3571 ""
3572 "*
3573 {
3574 int start = INTVAL (operands[3]) & 31;
3575 int size = INTVAL (operands[2]) & 31;
3576
3577 /* Force split for non-cc0 compare. */
3578 if (which_alternative == 1)
3579 return \"#\";
3580
3581 /* If the bit-field being tested fits in the upper or lower half of a
3582 word, it is possible to use andiu. or andil. to test it. This is
3583 useful because the condition register set-use delay is smaller for
3584 andi[ul]. than for rlinm. This doesn't work when the starting bit
3585 position is 0 because the LT and GT bits may be set wrong. */
3586
3587 if ((start > 0 && start + size <= 16) || start >= 16)
3588 {
3589 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3590 - (1 << (16 - (start & 15) - size))));
3591 if (start < 16)
3592 return \"{andiu.|andis.} %4,%1,%3\";
3593 else
3594 return \"{andil.|andi.} %4,%1,%3\";
3595 }
3596
3597 if (start + size >= 32)
3598 operands[3] = const0_rtx;
3599 else
3600 operands[3] = GEN_INT (start + size);
3601 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3602 }"
3603 [(set_attr "type" "compare")
3604 (set_attr "length" "4,8")])
3605
3606 (define_split
3607 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3608 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3609 (match_operand:SI 2 "const_int_operand" "")
3610 (match_operand:SI 3 "const_int_operand" ""))
3611 (const_int 0)))
3612 (clobber (match_scratch:SI 4 ""))]
3613 "reload_completed"
3614 [(set (match_dup 4)
3615 (zero_extract:SI (match_dup 1) (match_dup 2)
3616 (match_dup 3)))
3617 (set (match_dup 0)
3618 (compare:CC (match_dup 4)
3619 (const_int 0)))]
3620 "")
3621
3622 (define_insn "*extzvsi_internal2"
3623 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3624 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3625 (match_operand:SI 2 "const_int_operand" "i,i")
3626 (match_operand:SI 3 "const_int_operand" "i,i"))
3627 (const_int 0)))
3628 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3629 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3630 ""
3631 "*
3632 {
3633 int start = INTVAL (operands[3]) & 31;
3634 int size = INTVAL (operands[2]) & 31;
3635
3636 /* Force split for non-cc0 compare. */
3637 if (which_alternative == 1)
3638 return \"#\";
3639
3640 /* Since we are using the output value, we can't ignore any need for
3641 a shift. The bit-field must end at the LSB. */
3642 if (start >= 16 && start + size == 32)
3643 {
3644 operands[3] = GEN_INT ((1 << size) - 1);
3645 return \"{andil.|andi.} %0,%1,%3\";
3646 }
3647
3648 if (start + size >= 32)
3649 operands[3] = const0_rtx;
3650 else
3651 operands[3] = GEN_INT (start + size);
3652 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3653 }"
3654 [(set_attr "type" "compare")
3655 (set_attr "length" "4,8")])
3656
3657 (define_split
3658 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3659 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3660 (match_operand:SI 2 "const_int_operand" "")
3661 (match_operand:SI 3 "const_int_operand" ""))
3662 (const_int 0)))
3663 (set (match_operand:SI 0 "gpc_reg_operand" "")
3664 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3665 "reload_completed"
3666 [(set (match_dup 0)
3667 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3668 (set (match_dup 4)
3669 (compare:CC (match_dup 0)
3670 (const_int 0)))]
3671 "")
3672
3673 (define_insn "extzvdi"
3674 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3675 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3676 (match_operand:SI 2 "const_int_operand" "i")
3677 (match_operand:SI 3 "const_int_operand" "i")))]
3678 "TARGET_POWERPC64"
3679 "*
3680 {
3681 int start = INTVAL (operands[3]) & 63;
3682 int size = INTVAL (operands[2]) & 63;
3683
3684 if (start + size >= 64)
3685 operands[3] = const0_rtx;
3686 else
3687 operands[3] = GEN_INT (start + size);
3688 operands[2] = GEN_INT (64 - size);
3689 return \"rldicl %0,%1,%3,%2\";
3690 }")
3691
3692 (define_insn "*extzvdi_internal1"
3693 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3694 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3695 (match_operand:SI 2 "const_int_operand" "i")
3696 (match_operand:SI 3 "const_int_operand" "i"))
3697 (const_int 0)))
3698 (clobber (match_scratch:DI 4 "=r"))]
3699 "TARGET_64BIT"
3700 "*
3701 {
3702 int start = INTVAL (operands[3]) & 63;
3703 int size = INTVAL (operands[2]) & 63;
3704
3705 if (start + size >= 64)
3706 operands[3] = const0_rtx;
3707 else
3708 operands[3] = GEN_INT (start + size);
3709 operands[2] = GEN_INT (64 - size);
3710 return \"rldicl. %4,%1,%3,%2\";
3711 }"
3712 [(set_attr "type" "compare")])
3713
3714 (define_insn "*extzvdi_internal2"
3715 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3716 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3717 (match_operand:SI 2 "const_int_operand" "i")
3718 (match_operand:SI 3 "const_int_operand" "i"))
3719 (const_int 0)))
3720 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3721 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3722 "TARGET_64BIT"
3723 "*
3724 {
3725 int start = INTVAL (operands[3]) & 63;
3726 int size = INTVAL (operands[2]) & 63;
3727
3728 if (start + size >= 64)
3729 operands[3] = const0_rtx;
3730 else
3731 operands[3] = GEN_INT (start + size);
3732 operands[2] = GEN_INT (64 - size);
3733 return \"rldicl. %0,%1,%3,%2\";
3734 }"
3735 [(set_attr "type" "compare")])
3736
3737 (define_insn "rotlsi3"
3738 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3739 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3740 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3741 ""
3742 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3743
3744 (define_insn "*rotlsi3_internal2"
3745 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3746 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3747 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3748 (const_int 0)))
3749 (clobber (match_scratch:SI 3 "=r,r"))]
3750 ""
3751 "@
3752 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3753 #"
3754 [(set_attr "type" "delayed_compare")
3755 (set_attr "length" "4,8")])
3756
3757 (define_split
3758 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3759 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3760 (match_operand:SI 2 "reg_or_cint_operand" ""))
3761 (const_int 0)))
3762 (clobber (match_scratch:SI 3 ""))]
3763 "reload_completed"
3764 [(set (match_dup 3)
3765 (rotate:SI (match_dup 1) (match_dup 2)))
3766 (set (match_dup 0)
3767 (compare:CC (match_dup 3)
3768 (const_int 0)))]
3769 "")
3770
3771 (define_insn "*rotlsi3_internal3"
3772 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3773 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3774 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3775 (const_int 0)))
3776 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3777 (rotate:SI (match_dup 1) (match_dup 2)))]
3778 ""
3779 "@
3780 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3781 #"
3782 [(set_attr "type" "delayed_compare")
3783 (set_attr "length" "4,8")])
3784
3785 (define_split
3786 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3787 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3788 (match_operand:SI 2 "reg_or_cint_operand" ""))
3789 (const_int 0)))
3790 (set (match_operand:SI 0 "gpc_reg_operand" "")
3791 (rotate:SI (match_dup 1) (match_dup 2)))]
3792 "reload_completed"
3793 [(set (match_dup 0)
3794 (rotate:SI (match_dup 1) (match_dup 2)))
3795 (set (match_dup 3)
3796 (compare:CC (match_dup 0)
3797 (const_int 0)))]
3798 "")
3799
3800 (define_insn "*rotlsi3_internal4"
3801 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3802 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3803 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3804 (match_operand:SI 3 "mask_operand" "n")))]
3805 ""
3806 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3807
3808 (define_insn "*rotlsi3_internal5"
3809 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3810 (compare:CC (and:SI
3811 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3812 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3813 (match_operand:SI 3 "mask_operand" "n,n"))
3814 (const_int 0)))
3815 (clobber (match_scratch:SI 4 "=r,r"))]
3816 ""
3817 "@
3818 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3819 #"
3820 [(set_attr "type" "delayed_compare")
3821 (set_attr "length" "4,8")])
3822
3823 (define_split
3824 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3825 (compare:CC (and:SI
3826 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3827 (match_operand:SI 2 "reg_or_cint_operand" ""))
3828 (match_operand:SI 3 "mask_operand" ""))
3829 (const_int 0)))
3830 (clobber (match_scratch:SI 4 ""))]
3831 "reload_completed"
3832 [(set (match_dup 4)
3833 (and:SI (rotate:SI (match_dup 1)
3834 (match_dup 2))
3835 (match_dup 3)))
3836 (set (match_dup 0)
3837 (compare:CC (match_dup 4)
3838 (const_int 0)))]
3839 "")
3840
3841 (define_insn "*rotlsi3_internal6"
3842 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3843 (compare:CC (and:SI
3844 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3845 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3846 (match_operand:SI 3 "mask_operand" "n,n"))
3847 (const_int 0)))
3848 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3849 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3850 ""
3851 "@
3852 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3853 #"
3854 [(set_attr "type" "delayed_compare")
3855 (set_attr "length" "4,8")])
3856
3857 (define_split
3858 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3859 (compare:CC (and:SI
3860 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3861 (match_operand:SI 2 "reg_or_cint_operand" ""))
3862 (match_operand:SI 3 "mask_operand" ""))
3863 (const_int 0)))
3864 (set (match_operand:SI 0 "gpc_reg_operand" "")
3865 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3866 "reload_completed"
3867 [(set (match_dup 0)
3868 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3869 (set (match_dup 4)
3870 (compare:CC (match_dup 0)
3871 (const_int 0)))]
3872 "")
3873
3874 (define_insn "*rotlsi3_internal7"
3875 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3876 (zero_extend:SI
3877 (subreg:QI
3878 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3879 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3880 ""
3881 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3882
3883 (define_insn "*rotlsi3_internal8"
3884 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3885 (compare:CC (zero_extend:SI
3886 (subreg:QI
3887 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3888 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3889 (const_int 0)))
3890 (clobber (match_scratch:SI 3 "=r,r"))]
3891 ""
3892 "@
3893 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3894 #"
3895 [(set_attr "type" "delayed_compare")
3896 (set_attr "length" "4,8")])
3897
3898 (define_split
3899 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3900 (compare:CC (zero_extend:SI
3901 (subreg:QI
3902 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3903 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3904 (const_int 0)))
3905 (clobber (match_scratch:SI 3 ""))]
3906 "reload_completed"
3907 [(set (match_dup 3)
3908 (zero_extend:SI (subreg:QI
3909 (rotate:SI (match_dup 1)
3910 (match_dup 2)) 0)))
3911 (set (match_dup 0)
3912 (compare:CC (match_dup 3)
3913 (const_int 0)))]
3914 "")
3915
3916 (define_insn "*rotlsi3_internal9"
3917 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3918 (compare:CC (zero_extend:SI
3919 (subreg:QI
3920 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3921 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3922 (const_int 0)))
3923 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3924 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3925 ""
3926 "@
3927 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3928 #"
3929 [(set_attr "type" "delayed_compare")
3930 (set_attr "length" "4,8")])
3931
3932 (define_split
3933 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3934 (compare:CC (zero_extend:SI
3935 (subreg:QI
3936 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3937 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3938 (const_int 0)))
3939 (set (match_operand:SI 0 "gpc_reg_operand" "")
3940 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3941 "reload_completed"
3942 [(set (match_dup 0)
3943 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3944 (set (match_dup 3)
3945 (compare:CC (match_dup 0)
3946 (const_int 0)))]
3947 "")
3948
3949 (define_insn "*rotlsi3_internal10"
3950 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3951 (zero_extend:SI
3952 (subreg:HI
3953 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3954 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3955 ""
3956 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
3957
3958 (define_insn "*rotlsi3_internal11"
3959 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3960 (compare:CC (zero_extend:SI
3961 (subreg:HI
3962 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3963 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3964 (const_int 0)))
3965 (clobber (match_scratch:SI 3 "=r,r"))]
3966 ""
3967 "@
3968 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
3969 #"
3970 [(set_attr "type" "delayed_compare")
3971 (set_attr "length" "4,8")])
3972
3973 (define_split
3974 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3975 (compare:CC (zero_extend:SI
3976 (subreg:HI
3977 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3978 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3979 (const_int 0)))
3980 (clobber (match_scratch:SI 3 ""))]
3981 "reload_completed"
3982 [(set (match_dup 3)
3983 (zero_extend:SI (subreg:HI
3984 (rotate:SI (match_dup 1)
3985 (match_dup 2)) 0)))
3986 (set (match_dup 0)
3987 (compare:CC (match_dup 3)
3988 (const_int 0)))]
3989 "")
3990
3991 (define_insn "*rotlsi3_internal12"
3992 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3993 (compare:CC (zero_extend:SI
3994 (subreg:HI
3995 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3996 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3997 (const_int 0)))
3998 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3999 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4000 ""
4001 "@
4002 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
4003 #"
4004 [(set_attr "type" "delayed_compare")
4005 (set_attr "length" "4,8")])
4006
4007 (define_split
4008 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4009 (compare:CC (zero_extend:SI
4010 (subreg:HI
4011 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4012 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4013 (const_int 0)))
4014 (set (match_operand:SI 0 "gpc_reg_operand" "")
4015 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4016 "reload_completed"
4017 [(set (match_dup 0)
4018 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4019 (set (match_dup 3)
4020 (compare:CC (match_dup 0)
4021 (const_int 0)))]
4022 "")
4023
4024 ;; Note that we use "sle." instead of "sl." so that we can set
4025 ;; SHIFT_COUNT_TRUNCATED.
4026
4027 (define_expand "ashlsi3"
4028 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4029 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4030 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4031 ""
4032 "
4033 {
4034 if (TARGET_POWER)
4035 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4036 else
4037 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4038 DONE;
4039 }")
4040
4041 (define_insn "ashlsi3_power"
4042 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4043 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4044 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4045 (clobber (match_scratch:SI 3 "=q,X"))]
4046 "TARGET_POWER"
4047 "@
4048 sle %0,%1,%2
4049 {sli|slwi} %0,%1,%h2")
4050
4051 (define_insn "ashlsi3_no_power"
4052 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4053 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4054 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4055 "! TARGET_POWER"
4056 "{sl|slw}%I2 %0,%1,%h2")
4057
4058 (define_insn ""
4059 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4060 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4061 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4062 (const_int 0)))
4063 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4064 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4065 "TARGET_POWER"
4066 "@
4067 sle. %3,%1,%2
4068 {sli.|slwi.} %3,%1,%h2
4069 #
4070 #"
4071 [(set_attr "type" "delayed_compare")
4072 (set_attr "length" "4,4,8,8")])
4073
4074 (define_split
4075 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4076 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4077 (match_operand:SI 2 "reg_or_cint_operand" ""))
4078 (const_int 0)))
4079 (clobber (match_scratch:SI 3 ""))
4080 (clobber (match_scratch:SI 4 ""))]
4081 "TARGET_POWER && reload_completed"
4082 [(parallel [(set (match_dup 3)
4083 (ashift:SI (match_dup 1) (match_dup 2)))
4084 (clobber (match_dup 4))])
4085 (set (match_dup 0)
4086 (compare:CC (match_dup 3)
4087 (const_int 0)))]
4088 "")
4089
4090 (define_insn ""
4091 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4092 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4093 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4094 (const_int 0)))
4095 (clobber (match_scratch:SI 3 "=r,r"))]
4096 "! TARGET_POWER && TARGET_32BIT"
4097 "@
4098 {sl|slw}%I2. %3,%1,%h2
4099 #"
4100 [(set_attr "type" "delayed_compare")
4101 (set_attr "length" "4,8")])
4102
4103 (define_split
4104 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4105 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4106 (match_operand:SI 2 "reg_or_cint_operand" ""))
4107 (const_int 0)))
4108 (clobber (match_scratch:SI 3 ""))]
4109 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4110 [(set (match_dup 3)
4111 (ashift:SI (match_dup 1) (match_dup 2)))
4112 (set (match_dup 0)
4113 (compare:CC (match_dup 3)
4114 (const_int 0)))]
4115 "")
4116
4117 (define_insn ""
4118 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4119 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4120 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4121 (const_int 0)))
4122 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4123 (ashift:SI (match_dup 1) (match_dup 2)))
4124 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4125 "TARGET_POWER"
4126 "@
4127 sle. %0,%1,%2
4128 {sli.|slwi.} %0,%1,%h2
4129 #
4130 #"
4131 [(set_attr "type" "delayed_compare")
4132 (set_attr "length" "4,4,8,8")])
4133
4134 (define_split
4135 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4136 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4137 (match_operand:SI 2 "reg_or_cint_operand" ""))
4138 (const_int 0)))
4139 (set (match_operand:SI 0 "gpc_reg_operand" "")
4140 (ashift:SI (match_dup 1) (match_dup 2)))
4141 (clobber (match_scratch:SI 4 ""))]
4142 "TARGET_POWER && reload_completed"
4143 [(parallel [(set (match_dup 0)
4144 (ashift:SI (match_dup 1) (match_dup 2)))
4145 (clobber (match_dup 4))])
4146 (set (match_dup 3)
4147 (compare:CC (match_dup 0)
4148 (const_int 0)))]
4149 "")
4150
4151 (define_insn ""
4152 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4153 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4154 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4155 (const_int 0)))
4156 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4157 (ashift:SI (match_dup 1) (match_dup 2)))]
4158 "! TARGET_POWER && TARGET_32BIT"
4159 "@
4160 {sl|slw}%I2. %0,%1,%h2
4161 #"
4162 [(set_attr "type" "delayed_compare")
4163 (set_attr "length" "4,8")])
4164
4165 (define_split
4166 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4167 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4168 (match_operand:SI 2 "reg_or_cint_operand" ""))
4169 (const_int 0)))
4170 (set (match_operand:SI 0 "gpc_reg_operand" "")
4171 (ashift:SI (match_dup 1) (match_dup 2)))]
4172 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4173 [(set (match_dup 0)
4174 (ashift:SI (match_dup 1) (match_dup 2)))
4175 (set (match_dup 3)
4176 (compare:CC (match_dup 0)
4177 (const_int 0)))]
4178 "")
4179
4180 (define_insn "rlwinm"
4181 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4182 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4183 (match_operand:SI 2 "const_int_operand" "i"))
4184 (match_operand:SI 3 "mask_operand" "n")))]
4185 "includes_lshift_p (operands[2], operands[3])"
4186 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4187
4188 (define_insn ""
4189 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4190 (compare:CC
4191 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4192 (match_operand:SI 2 "const_int_operand" "i,i"))
4193 (match_operand:SI 3 "mask_operand" "n,n"))
4194 (const_int 0)))
4195 (clobber (match_scratch:SI 4 "=r,r"))]
4196 "includes_lshift_p (operands[2], operands[3])"
4197 "@
4198 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4199 #"
4200 [(set_attr "type" "delayed_compare")
4201 (set_attr "length" "4,8")])
4202
4203 (define_split
4204 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4205 (compare:CC
4206 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4207 (match_operand:SI 2 "const_int_operand" ""))
4208 (match_operand:SI 3 "mask_operand" ""))
4209 (const_int 0)))
4210 (clobber (match_scratch:SI 4 ""))]
4211 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4212 [(set (match_dup 4)
4213 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4214 (match_dup 3)))
4215 (set (match_dup 0)
4216 (compare:CC (match_dup 4)
4217 (const_int 0)))]
4218 "")
4219
4220 (define_insn ""
4221 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4222 (compare:CC
4223 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4224 (match_operand:SI 2 "const_int_operand" "i,i"))
4225 (match_operand:SI 3 "mask_operand" "n,n"))
4226 (const_int 0)))
4227 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4228 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4229 "includes_lshift_p (operands[2], operands[3])"
4230 "@
4231 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4232 #"
4233 [(set_attr "type" "delayed_compare")
4234 (set_attr "length" "4,8")])
4235
4236 (define_split
4237 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4238 (compare:CC
4239 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4240 (match_operand:SI 2 "const_int_operand" ""))
4241 (match_operand:SI 3 "mask_operand" ""))
4242 (const_int 0)))
4243 (set (match_operand:SI 0 "gpc_reg_operand" "")
4244 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4245 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4246 [(set (match_dup 0)
4247 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4248 (set (match_dup 4)
4249 (compare:CC (match_dup 0)
4250 (const_int 0)))]
4251 "")
4252
4253 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
4254 ;; "sli x,x,0".
4255 (define_expand "lshrsi3"
4256 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4257 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4258 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4259 ""
4260 "
4261 {
4262 if (TARGET_POWER)
4263 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4264 else
4265 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
4266 DONE;
4267 }")
4268
4269 (define_insn "lshrsi3_power"
4270 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4271 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4272 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4273 (clobber (match_scratch:SI 3 "=q,X,X"))]
4274 "TARGET_POWER"
4275 "@
4276 sre %0,%1,%2
4277 mr %0,%1
4278 {s%A2i|s%A2wi} %0,%1,%h2")
4279
4280 (define_insn "lshrsi3_no_power"
4281 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4282 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4283 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
4284 "! TARGET_POWER"
4285 "@
4286 mr %0,%1
4287 {sr|srw}%I2 %0,%1,%h2")
4288
4289 (define_insn ""
4290 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4291 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4292 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4293 (const_int 0)))
4294 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4295 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4296 "TARGET_POWER"
4297 "@
4298 sre. %3,%1,%2
4299 mr. %1,%1
4300 {s%A2i.|s%A2wi.} %3,%1,%h2
4301 #
4302 #
4303 #"
4304 [(set_attr "type" "delayed_compare")
4305 (set_attr "length" "4,4,4,8,8,8")])
4306
4307 (define_split
4308 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4309 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4310 (match_operand:SI 2 "reg_or_cint_operand" ""))
4311 (const_int 0)))
4312 (clobber (match_scratch:SI 3 ""))
4313 (clobber (match_scratch:SI 4 ""))]
4314 "TARGET_POWER && reload_completed"
4315 [(parallel [(set (match_dup 3)
4316 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4317 (clobber (match_dup 4))])
4318 (set (match_dup 0)
4319 (compare:CC (match_dup 3)
4320 (const_int 0)))]
4321 "")
4322
4323 (define_insn ""
4324 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4325 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4326 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
4327 (const_int 0)))
4328 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
4329 "! TARGET_POWER && TARGET_32BIT"
4330 "@
4331 mr. %1,%1
4332 {sr|srw}%I2. %3,%1,%h2
4333 #
4334 #"
4335 [(set_attr "type" "delayed_compare")
4336 (set_attr "length" "4,4,8,8")])
4337
4338 (define_split
4339 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4340 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4341 (match_operand:SI 2 "reg_or_cint_operand" ""))
4342 (const_int 0)))
4343 (clobber (match_scratch:SI 3 ""))]
4344 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4345 [(set (match_dup 3)
4346 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4347 (set (match_dup 0)
4348 (compare:CC (match_dup 3)
4349 (const_int 0)))]
4350 "")
4351
4352 (define_insn ""
4353 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4354 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4355 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4356 (const_int 0)))
4357 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4358 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4359 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4360 "TARGET_POWER"
4361 "@
4362 sre. %0,%1,%2
4363 mr. %0,%1
4364 {s%A2i.|s%A2wi.} %0,%1,%h2
4365 #
4366 #
4367 #"
4368 [(set_attr "type" "delayed_compare")
4369 (set_attr "length" "4,4,4,8,8,8")])
4370
4371 (define_split
4372 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4373 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4374 (match_operand:SI 2 "reg_or_cint_operand" ""))
4375 (const_int 0)))
4376 (set (match_operand:SI 0 "gpc_reg_operand" "")
4377 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4378 (clobber (match_scratch:SI 4 ""))]
4379 "TARGET_POWER && reload_completed"
4380 [(parallel [(set (match_dup 0)
4381 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4382 (clobber (match_dup 4))])
4383 (set (match_dup 3)
4384 (compare:CC (match_dup 0)
4385 (const_int 0)))]
4386 "")
4387
4388 (define_insn ""
4389 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4390 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4391 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
4392 (const_int 0)))
4393 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4394 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4395 "! TARGET_POWER && TARGET_32BIT"
4396 "@
4397 mr. %0,%1
4398 {sr|srw}%I2. %0,%1,%h2
4399 #
4400 #"
4401 [(set_attr "type" "delayed_compare")
4402 (set_attr "length" "4,4,8,8")])
4403
4404 (define_split
4405 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4406 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4407 (match_operand:SI 2 "reg_or_cint_operand" ""))
4408 (const_int 0)))
4409 (set (match_operand:SI 0 "gpc_reg_operand" "")
4410 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4411 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4412 [(set (match_dup 0)
4413 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4414 (set (match_dup 3)
4415 (compare:CC (match_dup 0)
4416 (const_int 0)))]
4417 "")
4418
4419 (define_insn ""
4420 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4421 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4422 (match_operand:SI 2 "const_int_operand" "i"))
4423 (match_operand:SI 3 "mask_operand" "n")))]
4424 "includes_rshift_p (operands[2], operands[3])"
4425 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4426
4427 (define_insn ""
4428 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4429 (compare:CC
4430 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4431 (match_operand:SI 2 "const_int_operand" "i,i"))
4432 (match_operand:SI 3 "mask_operand" "n,n"))
4433 (const_int 0)))
4434 (clobber (match_scratch:SI 4 "=r,r"))]
4435 "includes_rshift_p (operands[2], operands[3])"
4436 "@
4437 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4438 #"
4439 [(set_attr "type" "delayed_compare")
4440 (set_attr "length" "4,8")])
4441
4442 (define_split
4443 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4444 (compare:CC
4445 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4446 (match_operand:SI 2 "const_int_operand" ""))
4447 (match_operand:SI 3 "mask_operand" ""))
4448 (const_int 0)))
4449 (clobber (match_scratch:SI 4 ""))]
4450 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4451 [(set (match_dup 4)
4452 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4453 (match_dup 3)))
4454 (set (match_dup 0)
4455 (compare:CC (match_dup 4)
4456 (const_int 0)))]
4457 "")
4458
4459 (define_insn ""
4460 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4461 (compare:CC
4462 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4463 (match_operand:SI 2 "const_int_operand" "i,i"))
4464 (match_operand:SI 3 "mask_operand" "n,n"))
4465 (const_int 0)))
4466 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4467 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4468 "includes_rshift_p (operands[2], operands[3])"
4469 "@
4470 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4471 #"
4472 [(set_attr "type" "delayed_compare")
4473 (set_attr "length" "4,8")])
4474
4475 (define_split
4476 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4477 (compare:CC
4478 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4479 (match_operand:SI 2 "const_int_operand" ""))
4480 (match_operand:SI 3 "mask_operand" ""))
4481 (const_int 0)))
4482 (set (match_operand:SI 0 "gpc_reg_operand" "")
4483 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4484 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4485 [(set (match_dup 0)
4486 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4487 (set (match_dup 4)
4488 (compare:CC (match_dup 0)
4489 (const_int 0)))]
4490 "")
4491
4492 (define_insn ""
4493 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4494 (zero_extend:SI
4495 (subreg:QI
4496 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4497 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4498 "includes_rshift_p (operands[2], GEN_INT (255))"
4499 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4500
4501 (define_insn ""
4502 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4503 (compare:CC
4504 (zero_extend:SI
4505 (subreg:QI
4506 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4507 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4508 (const_int 0)))
4509 (clobber (match_scratch:SI 3 "=r,r"))]
4510 "includes_rshift_p (operands[2], GEN_INT (255))"
4511 "@
4512 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4513 #"
4514 [(set_attr "type" "delayed_compare")
4515 (set_attr "length" "4,8")])
4516
4517 (define_split
4518 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4519 (compare:CC
4520 (zero_extend:SI
4521 (subreg:QI
4522 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4523 (match_operand:SI 2 "const_int_operand" "")) 0))
4524 (const_int 0)))
4525 (clobber (match_scratch:SI 3 ""))]
4526 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4527 [(set (match_dup 3)
4528 (zero_extend:SI (subreg:QI
4529 (lshiftrt:SI (match_dup 1)
4530 (match_dup 2)) 0)))
4531 (set (match_dup 0)
4532 (compare:CC (match_dup 3)
4533 (const_int 0)))]
4534 "")
4535
4536 (define_insn ""
4537 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4538 (compare:CC
4539 (zero_extend:SI
4540 (subreg:QI
4541 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4542 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4543 (const_int 0)))
4544 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4545 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4546 "includes_rshift_p (operands[2], GEN_INT (255))"
4547 "@
4548 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4549 #"
4550 [(set_attr "type" "delayed_compare")
4551 (set_attr "length" "4,8")])
4552
4553 (define_split
4554 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4555 (compare:CC
4556 (zero_extend:SI
4557 (subreg:QI
4558 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4559 (match_operand:SI 2 "const_int_operand" "")) 0))
4560 (const_int 0)))
4561 (set (match_operand:SI 0 "gpc_reg_operand" "")
4562 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4563 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4564 [(set (match_dup 0)
4565 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4566 (set (match_dup 3)
4567 (compare:CC (match_dup 0)
4568 (const_int 0)))]
4569 "")
4570
4571 (define_insn ""
4572 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4573 (zero_extend:SI
4574 (subreg:HI
4575 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4576 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4577 "includes_rshift_p (operands[2], GEN_INT (65535))"
4578 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4579
4580 (define_insn ""
4581 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4582 (compare:CC
4583 (zero_extend:SI
4584 (subreg:HI
4585 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4586 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4587 (const_int 0)))
4588 (clobber (match_scratch:SI 3 "=r,r"))]
4589 "includes_rshift_p (operands[2], GEN_INT (65535))"
4590 "@
4591 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4592 #"
4593 [(set_attr "type" "delayed_compare")
4594 (set_attr "length" "4,8")])
4595
4596 (define_split
4597 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4598 (compare:CC
4599 (zero_extend:SI
4600 (subreg:HI
4601 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4602 (match_operand:SI 2 "const_int_operand" "")) 0))
4603 (const_int 0)))
4604 (clobber (match_scratch:SI 3 ""))]
4605 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4606 [(set (match_dup 3)
4607 (zero_extend:SI (subreg:HI
4608 (lshiftrt:SI (match_dup 1)
4609 (match_dup 2)) 0)))
4610 (set (match_dup 0)
4611 (compare:CC (match_dup 3)
4612 (const_int 0)))]
4613 "")
4614
4615 (define_insn ""
4616 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4617 (compare:CC
4618 (zero_extend:SI
4619 (subreg:HI
4620 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4621 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4622 (const_int 0)))
4623 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4624 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4625 "includes_rshift_p (operands[2], GEN_INT (65535))"
4626 "@
4627 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4628 #"
4629 [(set_attr "type" "delayed_compare")
4630 (set_attr "length" "4,8")])
4631
4632 (define_split
4633 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4634 (compare:CC
4635 (zero_extend:SI
4636 (subreg:HI
4637 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4638 (match_operand:SI 2 "const_int_operand" "")) 0))
4639 (const_int 0)))
4640 (set (match_operand:SI 0 "gpc_reg_operand" "")
4641 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4642 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4643 [(set (match_dup 0)
4644 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4645 (set (match_dup 3)
4646 (compare:CC (match_dup 0)
4647 (const_int 0)))]
4648 "")
4649
4650 (define_insn ""
4651 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4652 (const_int 1)
4653 (match_operand:SI 1 "gpc_reg_operand" "r"))
4654 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4655 (const_int 31)))]
4656 "TARGET_POWER"
4657 "rrib %0,%1,%2")
4658
4659 (define_insn ""
4660 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4661 (const_int 1)
4662 (match_operand:SI 1 "gpc_reg_operand" "r"))
4663 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4664 (const_int 31)))]
4665 "TARGET_POWER"
4666 "rrib %0,%1,%2")
4667
4668 (define_insn ""
4669 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4670 (const_int 1)
4671 (match_operand:SI 1 "gpc_reg_operand" "r"))
4672 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4673 (const_int 1)
4674 (const_int 0)))]
4675 "TARGET_POWER"
4676 "rrib %0,%1,%2")
4677
4678 (define_expand "ashrsi3"
4679 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4680 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4681 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4682 ""
4683 "
4684 {
4685 if (TARGET_POWER)
4686 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4687 else
4688 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4689 DONE;
4690 }")
4691
4692 (define_insn "ashrsi3_power"
4693 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4694 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4695 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4696 (clobber (match_scratch:SI 3 "=q,X"))]
4697 "TARGET_POWER"
4698 "@
4699 srea %0,%1,%2
4700 {srai|srawi} %0,%1,%h2")
4701
4702 (define_insn "ashrsi3_no_power"
4703 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4704 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4705 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4706 "! TARGET_POWER"
4707 "{sra|sraw}%I2 %0,%1,%h2")
4708
4709 (define_insn ""
4710 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4711 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4712 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4713 (const_int 0)))
4714 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4715 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4716 "TARGET_POWER"
4717 "@
4718 srea. %3,%1,%2
4719 {srai.|srawi.} %3,%1,%h2
4720 #
4721 #"
4722 [(set_attr "type" "delayed_compare")
4723 (set_attr "length" "4,4,8,8")])
4724
4725 (define_split
4726 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4727 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4728 (match_operand:SI 2 "reg_or_cint_operand" ""))
4729 (const_int 0)))
4730 (clobber (match_scratch:SI 3 ""))
4731 (clobber (match_scratch:SI 4 ""))]
4732 "TARGET_POWER && reload_completed"
4733 [(parallel [(set (match_dup 3)
4734 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4735 (clobber (match_dup 4))])
4736 (set (match_dup 0)
4737 (compare:CC (match_dup 3)
4738 (const_int 0)))]
4739 "")
4740
4741 (define_insn ""
4742 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4743 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4744 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4745 (const_int 0)))
4746 (clobber (match_scratch:SI 3 "=r,r"))]
4747 "! TARGET_POWER"
4748 "@
4749 {sra|sraw}%I2. %3,%1,%h2
4750 #"
4751 [(set_attr "type" "delayed_compare")
4752 (set_attr "length" "4,8")])
4753
4754 (define_split
4755 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4756 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4757 (match_operand:SI 2 "reg_or_cint_operand" ""))
4758 (const_int 0)))
4759 (clobber (match_scratch:SI 3 ""))]
4760 "! TARGET_POWER && reload_completed"
4761 [(set (match_dup 3)
4762 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4763 (set (match_dup 0)
4764 (compare:CC (match_dup 3)
4765 (const_int 0)))]
4766 "")
4767
4768 (define_insn ""
4769 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4770 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4771 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4772 (const_int 0)))
4773 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4774 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4775 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4776 "TARGET_POWER"
4777 "@
4778 srea. %0,%1,%2
4779 {srai.|srawi.} %0,%1,%h2
4780 #
4781 #"
4782 [(set_attr "type" "delayed_compare")
4783 (set_attr "length" "4,4,8,8")])
4784
4785 (define_split
4786 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4787 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4788 (match_operand:SI 2 "reg_or_cint_operand" ""))
4789 (const_int 0)))
4790 (set (match_operand:SI 0 "gpc_reg_operand" "")
4791 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4792 (clobber (match_scratch:SI 4 ""))]
4793 "TARGET_POWER && reload_completed"
4794 [(parallel [(set (match_dup 0)
4795 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4796 (clobber (match_dup 4))])
4797 (set (match_dup 3)
4798 (compare:CC (match_dup 0)
4799 (const_int 0)))]
4800 "")
4801
4802 (define_insn ""
4803 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4804 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4805 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4806 (const_int 0)))
4807 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4808 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4809 "! TARGET_POWER"
4810 "@
4811 {sra|sraw}%I2. %0,%1,%h2
4812 #"
4813 [(set_attr "type" "delayed_compare")
4814 (set_attr "length" "4,8")])
4815 \f
4816 (define_split
4817 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4818 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4819 (match_operand:SI 2 "reg_or_cint_operand" ""))
4820 (const_int 0)))
4821 (set (match_operand:SI 0 "gpc_reg_operand" "")
4822 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4823 "! TARGET_POWER && reload_completed"
4824 [(set (match_dup 0)
4825 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4826 (set (match_dup 3)
4827 (compare:CC (match_dup 0)
4828 (const_int 0)))]
4829 "")
4830
4831 ;; Floating-point insns, excluding normal data motion.
4832 ;;
4833 ;; PowerPC has a full set of single-precision floating point instructions.
4834 ;;
4835 ;; For the POWER architecture, we pretend that we have both SFmode and
4836 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4837 ;; The only conversions we will do will be when storing to memory. In that
4838 ;; case, we will use the "frsp" instruction before storing.
4839 ;;
4840 ;; Note that when we store into a single-precision memory location, we need to
4841 ;; use the frsp insn first. If the register being stored isn't dead, we
4842 ;; need a scratch register for the frsp. But this is difficult when the store
4843 ;; is done by reload. It is not incorrect to do the frsp on the register in
4844 ;; this case, we just lose precision that we would have otherwise gotten but
4845 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4846
4847 (define_expand "extendsfdf2"
4848 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4849 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4850 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4851 "")
4852
4853 (define_insn_and_split "*extendsfdf2_fpr"
4854 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
4855 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
4856 "TARGET_HARD_FLOAT && TARGET_FPRS"
4857 "@
4858 #
4859 fmr %0,%1
4860 lfs%U1%X1 %0,%1"
4861 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4862 [(const_int 0)]
4863 {
4864 emit_note (NOTE_INSN_DELETED);
4865 DONE;
4866 }
4867 [(set_attr "type" "fp,fp,fpload")])
4868
4869 (define_expand "truncdfsf2"
4870 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4871 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4872 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4873 "")
4874
4875 (define_insn "*truncdfsf2_fpr"
4876 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4877 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4878 "TARGET_HARD_FLOAT && TARGET_FPRS"
4879 "frsp %0,%1"
4880 [(set_attr "type" "fp")])
4881
4882 (define_insn "aux_truncdfsf2"
4883 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4884 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
4885 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4886 "frsp %0,%1"
4887 [(set_attr "type" "fp")])
4888
4889 (define_expand "negsf2"
4890 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4891 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4892 "TARGET_HARD_FLOAT"
4893 "")
4894
4895 (define_insn "*negsf2"
4896 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4897 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4898 "TARGET_HARD_FLOAT && TARGET_FPRS"
4899 "fneg %0,%1"
4900 [(set_attr "type" "fp")])
4901
4902 (define_expand "abssf2"
4903 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4904 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4905 "TARGET_HARD_FLOAT"
4906 "")
4907
4908 (define_insn "*abssf2"
4909 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4910 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4911 "TARGET_HARD_FLOAT && TARGET_FPRS"
4912 "fabs %0,%1"
4913 [(set_attr "type" "fp")])
4914
4915 (define_insn ""
4916 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4917 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4918 "TARGET_HARD_FLOAT && TARGET_FPRS"
4919 "fnabs %0,%1"
4920 [(set_attr "type" "fp")])
4921
4922 (define_expand "addsf3"
4923 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4924 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4925 (match_operand:SF 2 "gpc_reg_operand" "")))]
4926 "TARGET_HARD_FLOAT"
4927 "")
4928
4929 (define_insn ""
4930 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4931 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4932 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4933 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4934 "fadds %0,%1,%2"
4935 [(set_attr "type" "fp")])
4936
4937 (define_insn ""
4938 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4939 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4940 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4941 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4942 "{fa|fadd} %0,%1,%2"
4943 [(set_attr "type" "fp")])
4944
4945 (define_expand "subsf3"
4946 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4947 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4948 (match_operand:SF 2 "gpc_reg_operand" "")))]
4949 "TARGET_HARD_FLOAT"
4950 "")
4951
4952 (define_insn ""
4953 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4954 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4955 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4956 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4957 "fsubs %0,%1,%2"
4958 [(set_attr "type" "fp")])
4959
4960 (define_insn ""
4961 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4962 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4963 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4964 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4965 "{fs|fsub} %0,%1,%2"
4966 [(set_attr "type" "fp")])
4967
4968 (define_expand "mulsf3"
4969 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4970 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4971 (match_operand:SF 2 "gpc_reg_operand" "")))]
4972 "TARGET_HARD_FLOAT"
4973 "")
4974
4975 (define_insn ""
4976 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4977 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4978 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4979 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4980 "fmuls %0,%1,%2"
4981 [(set_attr "type" "fp")])
4982
4983 (define_insn ""
4984 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4985 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4986 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4987 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4988 "{fm|fmul} %0,%1,%2"
4989 [(set_attr "type" "dmul")])
4990
4991 (define_insn "fres"
4992 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4993 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
4994 "TARGET_PPC_GFXOPT && flag_finite_math_only"
4995 "fres %0,%1"
4996 [(set_attr "type" "fp")])
4997
4998 (define_expand "divsf3"
4999 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5000 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5001 (match_operand:SF 2 "gpc_reg_operand" "")))]
5002 "TARGET_HARD_FLOAT"
5003 {
5004 if (swdiv && !optimize_size && TARGET_PPC_GFXOPT
5005 && flag_finite_math_only && !flag_trapping_math)
5006 {
5007 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5008 DONE;
5009 }
5010 })
5011
5012 (define_insn ""
5013 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5014 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5015 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5016 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5017 "fdivs %0,%1,%2"
5018 [(set_attr "type" "sdiv")])
5019
5020 (define_insn ""
5021 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5022 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5023 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5024 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5025 "{fd|fdiv} %0,%1,%2"
5026 [(set_attr "type" "ddiv")])
5027
5028 (define_insn ""
5029 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5030 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5031 (match_operand:SF 2 "gpc_reg_operand" "f"))
5032 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5033 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5034 "fmadds %0,%1,%2,%3"
5035 [(set_attr "type" "fp")])
5036
5037 (define_insn ""
5038 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5039 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5040 (match_operand:SF 2 "gpc_reg_operand" "f"))
5041 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5042 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5043 "{fma|fmadd} %0,%1,%2,%3"
5044 [(set_attr "type" "dmul")])
5045
5046 (define_insn ""
5047 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5048 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5049 (match_operand:SF 2 "gpc_reg_operand" "f"))
5050 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5051 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5052 "fmsubs %0,%1,%2,%3"
5053 [(set_attr "type" "fp")])
5054
5055 (define_insn ""
5056 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5057 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5058 (match_operand:SF 2 "gpc_reg_operand" "f"))
5059 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5060 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5061 "{fms|fmsub} %0,%1,%2,%3"
5062 [(set_attr "type" "dmul")])
5063
5064 (define_insn ""
5065 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5066 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5067 (match_operand:SF 2 "gpc_reg_operand" "f"))
5068 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5069 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5070 && HONOR_SIGNED_ZEROS (SFmode)"
5071 "fnmadds %0,%1,%2,%3"
5072 [(set_attr "type" "fp")])
5073
5074 (define_insn ""
5075 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5076 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5077 (match_operand:SF 2 "gpc_reg_operand" "f"))
5078 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5079 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5080 && ! HONOR_SIGNED_ZEROS (SFmode)"
5081 "fnmadds %0,%1,%2,%3"
5082 [(set_attr "type" "fp")])
5083
5084 (define_insn ""
5085 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5086 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5087 (match_operand:SF 2 "gpc_reg_operand" "f"))
5088 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5089 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5090 "{fnma|fnmadd} %0,%1,%2,%3"
5091 [(set_attr "type" "dmul")])
5092
5093 (define_insn ""
5094 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5095 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5096 (match_operand:SF 2 "gpc_reg_operand" "f"))
5097 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5098 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5099 && ! HONOR_SIGNED_ZEROS (SFmode)"
5100 "{fnma|fnmadd} %0,%1,%2,%3"
5101 [(set_attr "type" "dmul")])
5102
5103 (define_insn ""
5104 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5105 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5106 (match_operand:SF 2 "gpc_reg_operand" "f"))
5107 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5108 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5109 && HONOR_SIGNED_ZEROS (SFmode)"
5110 "fnmsubs %0,%1,%2,%3"
5111 [(set_attr "type" "fp")])
5112
5113 (define_insn ""
5114 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5115 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5116 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5117 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5118 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5119 && ! HONOR_SIGNED_ZEROS (SFmode)"
5120 "fnmsubs %0,%1,%2,%3"
5121 [(set_attr "type" "fp")])
5122
5123 (define_insn ""
5124 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5125 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5126 (match_operand:SF 2 "gpc_reg_operand" "f"))
5127 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5128 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5129 "{fnms|fnmsub} %0,%1,%2,%3"
5130 [(set_attr "type" "dmul")])
5131
5132 (define_insn ""
5133 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5134 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5135 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5136 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5137 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5138 && ! HONOR_SIGNED_ZEROS (SFmode)"
5139 "{fnms|fnmsub} %0,%1,%2,%3"
5140 [(set_attr "type" "dmul")])
5141
5142 (define_expand "sqrtsf2"
5143 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5144 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5145 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5146 "")
5147
5148 (define_insn ""
5149 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5150 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5151 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5152 "fsqrts %0,%1"
5153 [(set_attr "type" "ssqrt")])
5154
5155 (define_insn ""
5156 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5157 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5158 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
5159 "fsqrt %0,%1"
5160 [(set_attr "type" "dsqrt")])
5161
5162 (define_expand "copysignsf3"
5163 [(set (match_dup 3)
5164 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5165 (set (match_dup 4)
5166 (neg:SF (abs:SF (match_dup 1))))
5167 (set (match_operand:SF 0 "gpc_reg_operand" "")
5168 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5169 (match_dup 5))
5170 (match_dup 3)
5171 (match_dup 4)))]
5172 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5173 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
5174 {
5175 operands[3] = gen_reg_rtx (SFmode);
5176 operands[4] = gen_reg_rtx (SFmode);
5177 operands[5] = CONST0_RTX (SFmode);
5178 })
5179
5180 (define_expand "copysigndf3"
5181 [(set (match_dup 3)
5182 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5183 (set (match_dup 4)
5184 (neg:DF (abs:DF (match_dup 1))))
5185 (set (match_operand:DF 0 "gpc_reg_operand" "")
5186 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5187 (match_dup 5))
5188 (match_dup 3)
5189 (match_dup 4)))]
5190 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5191 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
5192 {
5193 operands[3] = gen_reg_rtx (DFmode);
5194 operands[4] = gen_reg_rtx (DFmode);
5195 operands[5] = CONST0_RTX (DFmode);
5196 })
5197
5198 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5199 ;; fsel instruction and some auxiliary computations. Then we just have a
5200 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5201 ;; combine.
5202 (define_expand "smaxsf3"
5203 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5204 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5205 (match_operand:SF 2 "gpc_reg_operand" ""))
5206 (match_dup 1)
5207 (match_dup 2)))]
5208 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5209 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5210
5211 (define_expand "sminsf3"
5212 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5213 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5214 (match_operand:SF 2 "gpc_reg_operand" ""))
5215 (match_dup 2)
5216 (match_dup 1)))]
5217 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5218 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5219
5220 (define_split
5221 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5222 (match_operator:SF 3 "min_max_operator"
5223 [(match_operand:SF 1 "gpc_reg_operand" "")
5224 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5225 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5226 [(const_int 0)]
5227 "
5228 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5229 operands[1], operands[2]);
5230 DONE;
5231 }")
5232
5233 (define_expand "movsicc"
5234 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5235 (if_then_else:SI (match_operand 1 "comparison_operator" "")
5236 (match_operand:SI 2 "gpc_reg_operand" "")
5237 (match_operand:SI 3 "gpc_reg_operand" "")))]
5238 "TARGET_ISEL"
5239 "
5240 {
5241 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5242 DONE;
5243 else
5244 FAIL;
5245 }")
5246
5247 ;; We use the BASE_REGS for the isel input operands because, if rA is
5248 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5249 ;; because we may switch the operands and rB may end up being rA.
5250 ;;
5251 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5252 ;; leave out the mode in operand 4 and use one pattern, but reload can
5253 ;; change the mode underneath our feet and then gets confused trying
5254 ;; to reload the value.
5255 (define_insn "isel_signed"
5256 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5257 (if_then_else:SI
5258 (match_operator 1 "comparison_operator"
5259 [(match_operand:CC 4 "cc_reg_operand" "y")
5260 (const_int 0)])
5261 (match_operand:SI 2 "gpc_reg_operand" "b")
5262 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5263 "TARGET_ISEL"
5264 "*
5265 { return output_isel (operands); }"
5266 [(set_attr "length" "4")])
5267
5268 (define_insn "isel_unsigned"
5269 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5270 (if_then_else:SI
5271 (match_operator 1 "comparison_operator"
5272 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5273 (const_int 0)])
5274 (match_operand:SI 2 "gpc_reg_operand" "b")
5275 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5276 "TARGET_ISEL"
5277 "*
5278 { return output_isel (operands); }"
5279 [(set_attr "length" "4")])
5280
5281 (define_expand "movsfcc"
5282 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5283 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5284 (match_operand:SF 2 "gpc_reg_operand" "")
5285 (match_operand:SF 3 "gpc_reg_operand" "")))]
5286 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5287 "
5288 {
5289 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5290 DONE;
5291 else
5292 FAIL;
5293 }")
5294
5295 (define_insn "*fselsfsf4"
5296 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5297 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5298 (match_operand:SF 4 "zero_fp_constant" "F"))
5299 (match_operand:SF 2 "gpc_reg_operand" "f")
5300 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5301 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5302 "fsel %0,%1,%2,%3"
5303 [(set_attr "type" "fp")])
5304
5305 (define_insn "*fseldfsf4"
5306 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5307 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5308 (match_operand:DF 4 "zero_fp_constant" "F"))
5309 (match_operand:SF 2 "gpc_reg_operand" "f")
5310 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5311 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5312 "fsel %0,%1,%2,%3"
5313 [(set_attr "type" "fp")])
5314
5315 (define_expand "negdf2"
5316 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5317 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5318 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5319 "")
5320
5321 (define_insn "*negdf2_fpr"
5322 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5323 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5324 "TARGET_HARD_FLOAT && TARGET_FPRS"
5325 "fneg %0,%1"
5326 [(set_attr "type" "fp")])
5327
5328 (define_expand "absdf2"
5329 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5330 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5331 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5332 "")
5333
5334 (define_insn "*absdf2_fpr"
5335 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5336 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5337 "TARGET_HARD_FLOAT && TARGET_FPRS"
5338 "fabs %0,%1"
5339 [(set_attr "type" "fp")])
5340
5341 (define_insn "*nabsdf2_fpr"
5342 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5343 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
5344 "TARGET_HARD_FLOAT && TARGET_FPRS"
5345 "fnabs %0,%1"
5346 [(set_attr "type" "fp")])
5347
5348 (define_expand "adddf3"
5349 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5350 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5351 (match_operand:DF 2 "gpc_reg_operand" "")))]
5352 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5353 "")
5354
5355 (define_insn "*adddf3_fpr"
5356 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5357 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5358 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5359 "TARGET_HARD_FLOAT && TARGET_FPRS"
5360 "{fa|fadd} %0,%1,%2"
5361 [(set_attr "type" "fp")])
5362
5363 (define_expand "subdf3"
5364 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5365 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5366 (match_operand:DF 2 "gpc_reg_operand" "")))]
5367 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5368 "")
5369
5370 (define_insn "*subdf3_fpr"
5371 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5372 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5373 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5374 "TARGET_HARD_FLOAT && TARGET_FPRS"
5375 "{fs|fsub} %0,%1,%2"
5376 [(set_attr "type" "fp")])
5377
5378 (define_expand "muldf3"
5379 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5380 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5381 (match_operand:DF 2 "gpc_reg_operand" "")))]
5382 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5383 "")
5384
5385 (define_insn "*muldf3_fpr"
5386 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5387 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5388 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5389 "TARGET_HARD_FLOAT && TARGET_FPRS"
5390 "{fm|fmul} %0,%1,%2"
5391 [(set_attr "type" "dmul")])
5392
5393 (define_insn "fred"
5394 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5395 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5396 "TARGET_POPCNTB && flag_finite_math_only"
5397 "fre %0,%1"
5398 [(set_attr "type" "fp")])
5399
5400 (define_expand "divdf3"
5401 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5402 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5403 (match_operand:DF 2 "gpc_reg_operand" "")))]
5404 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5405 {
5406 if (swdiv && !optimize_size && TARGET_POPCNTB
5407 && flag_finite_math_only && !flag_trapping_math)
5408 {
5409 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5410 DONE;
5411 }
5412 })
5413
5414 (define_insn "*divdf3_fpr"
5415 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5416 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5417 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5418 "TARGET_HARD_FLOAT && TARGET_FPRS"
5419 "{fd|fdiv} %0,%1,%2"
5420 [(set_attr "type" "ddiv")])
5421
5422 (define_insn ""
5423 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5424 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5425 (match_operand:DF 2 "gpc_reg_operand" "f"))
5426 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5427 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5428 "{fma|fmadd} %0,%1,%2,%3"
5429 [(set_attr "type" "dmul")])
5430
5431 (define_insn ""
5432 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5433 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5434 (match_operand:DF 2 "gpc_reg_operand" "f"))
5435 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5436 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5437 "{fms|fmsub} %0,%1,%2,%3"
5438 [(set_attr "type" "dmul")])
5439
5440 (define_insn ""
5441 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5442 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5443 (match_operand:DF 2 "gpc_reg_operand" "f"))
5444 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5445 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5446 && HONOR_SIGNED_ZEROS (DFmode)"
5447 "{fnma|fnmadd} %0,%1,%2,%3"
5448 [(set_attr "type" "dmul")])
5449
5450 (define_insn ""
5451 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5452 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5453 (match_operand:DF 2 "gpc_reg_operand" "f"))
5454 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5455 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5456 && ! HONOR_SIGNED_ZEROS (DFmode)"
5457 "{fnma|fnmadd} %0,%1,%2,%3"
5458 [(set_attr "type" "dmul")])
5459
5460 (define_insn ""
5461 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5462 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5463 (match_operand:DF 2 "gpc_reg_operand" "f"))
5464 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5465 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5466 && HONOR_SIGNED_ZEROS (DFmode)"
5467 "{fnms|fnmsub} %0,%1,%2,%3"
5468 [(set_attr "type" "dmul")])
5469
5470 (define_insn ""
5471 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5472 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5473 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5474 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5475 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5476 && ! HONOR_SIGNED_ZEROS (DFmode)"
5477 "{fnms|fnmsub} %0,%1,%2,%3"
5478 [(set_attr "type" "dmul")])
5479
5480 (define_insn "sqrtdf2"
5481 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5482 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5483 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5484 "fsqrt %0,%1"
5485 [(set_attr "type" "dsqrt")])
5486
5487 ;; The conditional move instructions allow us to perform max and min
5488 ;; operations even when
5489
5490 (define_expand "smaxdf3"
5491 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5492 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5493 (match_operand:DF 2 "gpc_reg_operand" ""))
5494 (match_dup 1)
5495 (match_dup 2)))]
5496 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5497 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5498
5499 (define_expand "smindf3"
5500 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5501 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5502 (match_operand:DF 2 "gpc_reg_operand" ""))
5503 (match_dup 2)
5504 (match_dup 1)))]
5505 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5506 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5507
5508 (define_split
5509 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5510 (match_operator:DF 3 "min_max_operator"
5511 [(match_operand:DF 1 "gpc_reg_operand" "")
5512 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5513 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5514 [(const_int 0)]
5515 "
5516 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5517 operands[1], operands[2]);
5518 DONE;
5519 }")
5520
5521 (define_expand "movdfcc"
5522 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5523 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5524 (match_operand:DF 2 "gpc_reg_operand" "")
5525 (match_operand:DF 3 "gpc_reg_operand" "")))]
5526 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5527 "
5528 {
5529 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5530 DONE;
5531 else
5532 FAIL;
5533 }")
5534
5535 (define_insn "*fseldfdf4"
5536 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5537 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5538 (match_operand:DF 4 "zero_fp_constant" "F"))
5539 (match_operand:DF 2 "gpc_reg_operand" "f")
5540 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5541 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5542 "fsel %0,%1,%2,%3"
5543 [(set_attr "type" "fp")])
5544
5545 (define_insn "*fselsfdf4"
5546 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5547 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5548 (match_operand:SF 4 "zero_fp_constant" "F"))
5549 (match_operand:DF 2 "gpc_reg_operand" "f")
5550 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5551 "TARGET_PPC_GFXOPT"
5552 "fsel %0,%1,%2,%3"
5553 [(set_attr "type" "fp")])
5554 \f
5555 ;; Conversions to and from floating-point.
5556
5557 (define_expand "fixuns_truncsfsi2"
5558 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5559 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5560 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5561 "")
5562
5563 (define_expand "fix_truncsfsi2"
5564 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5565 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5566 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5567 "")
5568
5569 ; For each of these conversions, there is a define_expand, a define_insn
5570 ; with a '#' template, and a define_split (with C code). The idea is
5571 ; to allow constant folding with the template of the define_insn,
5572 ; then to have the insns split later (between sched1 and final).
5573
5574 (define_expand "floatsidf2"
5575 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5576 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5577 (use (match_dup 2))
5578 (use (match_dup 3))
5579 (clobber (match_dup 4))
5580 (clobber (match_dup 5))
5581 (clobber (match_dup 6))])]
5582 "TARGET_HARD_FLOAT && TARGET_FPRS"
5583 "
5584 {
5585 if (TARGET_E500_DOUBLE)
5586 {
5587 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5588 DONE;
5589 }
5590 if (TARGET_POWERPC64)
5591 {
5592 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5593 rtx t1 = gen_reg_rtx (DImode);
5594 rtx t2 = gen_reg_rtx (DImode);
5595 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5596 DONE;
5597 }
5598
5599 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5600 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5601 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5602 operands[5] = gen_reg_rtx (DFmode);
5603 operands[6] = gen_reg_rtx (SImode);
5604 }")
5605
5606 (define_insn_and_split "*floatsidf2_internal"
5607 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5608 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5609 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5610 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5611 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5612 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5613 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5614 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5615 "#"
5616 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5617 [(pc)]
5618 "
5619 {
5620 rtx lowword, highword;
5621 gcc_assert (MEM_P (operands[4]));
5622 highword = adjust_address (operands[4], SImode, 0);
5623 lowword = adjust_address (operands[4], SImode, 4);
5624 if (! WORDS_BIG_ENDIAN)
5625 {
5626 rtx tmp;
5627 tmp = highword; highword = lowword; lowword = tmp;
5628 }
5629
5630 emit_insn (gen_xorsi3 (operands[6], operands[1],
5631 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5632 emit_move_insn (lowword, operands[6]);
5633 emit_move_insn (highword, operands[2]);
5634 emit_move_insn (operands[5], operands[4]);
5635 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5636 DONE;
5637 }"
5638 [(set_attr "length" "24")])
5639
5640 (define_expand "floatunssisf2"
5641 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5642 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5643 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5644 "")
5645
5646 (define_expand "floatunssidf2"
5647 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5648 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5649 (use (match_dup 2))
5650 (use (match_dup 3))
5651 (clobber (match_dup 4))
5652 (clobber (match_dup 5))])]
5653 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5654 "
5655 {
5656 if (TARGET_E500_DOUBLE)
5657 {
5658 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5659 DONE;
5660 }
5661 if (TARGET_POWERPC64)
5662 {
5663 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5664 rtx t1 = gen_reg_rtx (DImode);
5665 rtx t2 = gen_reg_rtx (DImode);
5666 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5667 t1, t2));
5668 DONE;
5669 }
5670
5671 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5672 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5673 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5674 operands[5] = gen_reg_rtx (DFmode);
5675 }")
5676
5677 (define_insn_and_split "*floatunssidf2_internal"
5678 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5679 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5680 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5681 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5682 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5683 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5684 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5685 "#"
5686 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5687 [(pc)]
5688 "
5689 {
5690 rtx lowword, highword;
5691 gcc_assert (MEM_P (operands[4]));
5692 highword = adjust_address (operands[4], SImode, 0);
5693 lowword = adjust_address (operands[4], SImode, 4);
5694 if (! WORDS_BIG_ENDIAN)
5695 {
5696 rtx tmp;
5697 tmp = highword; highword = lowword; lowword = tmp;
5698 }
5699
5700 emit_move_insn (lowword, operands[1]);
5701 emit_move_insn (highword, operands[2]);
5702 emit_move_insn (operands[5], operands[4]);
5703 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5704 DONE;
5705 }"
5706 [(set_attr "length" "20")])
5707
5708 (define_expand "fix_truncdfsi2"
5709 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
5710 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5711 (clobber (match_dup 2))
5712 (clobber (match_dup 3))])]
5713 "(TARGET_POWER2 || TARGET_POWERPC)
5714 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5715 "
5716 {
5717 if (TARGET_E500_DOUBLE)
5718 {
5719 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5720 DONE;
5721 }
5722 operands[2] = gen_reg_rtx (DImode);
5723 if (TARGET_PPC_GFXOPT)
5724 {
5725 rtx orig_dest = operands[0];
5726 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
5727 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5728 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5729 operands[2]));
5730 if (operands[0] != orig_dest)
5731 emit_move_insn (orig_dest, operands[0]);
5732 DONE;
5733 }
5734 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5735 }")
5736
5737 (define_insn_and_split "*fix_truncdfsi2_internal"
5738 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5739 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5740 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5741 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5742 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5743 "#"
5744 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[3]))"
5745 [(pc)]
5746 "
5747 {
5748 rtx lowword;
5749 gcc_assert (MEM_P (operands[3]));
5750 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5751
5752 emit_insn (gen_fctiwz (operands[2], operands[1]));
5753 emit_move_insn (operands[3], operands[2]);
5754 emit_move_insn (operands[0], lowword);
5755 DONE;
5756 }"
5757 [(set_attr "length" "16")])
5758
5759 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
5760 [(set (match_operand:SI 0 "memory_operand" "=Z")
5761 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5762 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
5763 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
5764 && TARGET_PPC_GFXOPT"
5765 "#"
5766 "&& 1"
5767 [(pc)]
5768 "
5769 {
5770 emit_insn (gen_fctiwz (operands[2], operands[1]));
5771 emit_insn (gen_stfiwx (operands[0], operands[2]));
5772 DONE;
5773 }"
5774 [(set_attr "length" "16")])
5775
5776 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5777 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5778 ; because the first makes it clear that operand 0 is not live
5779 ; before the instruction.
5780 (define_insn "fctiwz"
5781 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
5782 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5783 UNSPEC_FCTIWZ))]
5784 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5785 "{fcirz|fctiwz} %0,%1"
5786 [(set_attr "type" "fp")])
5787
5788 (define_insn "btruncdf2"
5789 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5790 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
5791 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5792 "friz %0,%1"
5793 [(set_attr "type" "fp")])
5794
5795 (define_insn "btruncsf2"
5796 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5797 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
5798 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5799 "friz %0,%1"
5800 [(set_attr "type" "fp")])
5801
5802 (define_insn "ceildf2"
5803 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5804 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
5805 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5806 "frip %0,%1"
5807 [(set_attr "type" "fp")])
5808
5809 (define_insn "ceilsf2"
5810 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5811 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
5812 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5813 "frip %0,%1"
5814 [(set_attr "type" "fp")])
5815
5816 (define_insn "floordf2"
5817 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5818 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
5819 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5820 "frim %0,%1"
5821 [(set_attr "type" "fp")])
5822
5823 (define_insn "floorsf2"
5824 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5825 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
5826 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5827 "frim %0,%1"
5828 [(set_attr "type" "fp")])
5829
5830 (define_insn "rounddf2"
5831 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5832 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
5833 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5834 "frin %0,%1"
5835 [(set_attr "type" "fp")])
5836
5837 (define_insn "roundsf2"
5838 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5839 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
5840 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5841 "frin %0,%1"
5842 [(set_attr "type" "fp")])
5843
5844 ; An UNSPEC is used so we don't have to support SImode in FP registers.
5845 (define_insn "stfiwx"
5846 [(set (match_operand:SI 0 "memory_operand" "=Z")
5847 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
5848 UNSPEC_STFIWX))]
5849 "TARGET_PPC_GFXOPT"
5850 "stfiwx %1,%y0"
5851 [(set_attr "type" "fpstore")])
5852
5853 (define_expand "floatsisf2"
5854 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5855 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5856 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5857 "")
5858
5859 (define_insn "floatdidf2"
5860 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5861 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
5862 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5863 "fcfid %0,%1"
5864 [(set_attr "type" "fp")])
5865
5866 (define_insn_and_split "floatsidf_ppc64"
5867 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5868 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5869 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5870 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5871 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5872 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5873 "#"
5874 "&& 1"
5875 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5876 (set (match_dup 2) (match_dup 3))
5877 (set (match_dup 4) (match_dup 2))
5878 (set (match_dup 0) (float:DF (match_dup 4)))]
5879 "")
5880
5881 (define_insn_and_split "floatunssidf_ppc64"
5882 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5883 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5884 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5885 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5886 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5887 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5888 "#"
5889 "&& 1"
5890 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5891 (set (match_dup 2) (match_dup 3))
5892 (set (match_dup 4) (match_dup 2))
5893 (set (match_dup 0) (float:DF (match_dup 4)))]
5894 "")
5895
5896 (define_insn "fix_truncdfdi2"
5897 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5898 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5899 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5900 "fctidz %0,%1"
5901 [(set_attr "type" "fp")])
5902
5903 (define_expand "floatdisf2"
5904 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5905 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5906 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5907 "
5908 {
5909 rtx val = operands[1];
5910 if (!flag_unsafe_math_optimizations)
5911 {
5912 rtx label = gen_label_rtx ();
5913 val = gen_reg_rtx (DImode);
5914 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
5915 emit_label (label);
5916 }
5917 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
5918 DONE;
5919 }")
5920
5921 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5922 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5923 ;; from double rounding.
5924 (define_insn_and_split "floatdisf2_internal1"
5925 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5926 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
5927 (clobber (match_scratch:DF 2 "=f"))]
5928 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5929 "#"
5930 "&& reload_completed"
5931 [(set (match_dup 2)
5932 (float:DF (match_dup 1)))
5933 (set (match_dup 0)
5934 (float_truncate:SF (match_dup 2)))]
5935 "")
5936
5937 ;; Twiddles bits to avoid double rounding.
5938 ;; Bits that might be truncated when converting to DFmode are replaced
5939 ;; by a bit that won't be lost at that stage, but is below the SFmode
5940 ;; rounding position.
5941 (define_expand "floatdisf2_internal2"
5942 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
5943 (const_int 53)))
5944 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
5945 (const_int 2047)))
5946 (clobber (scratch:CC))])
5947 (set (match_dup 3) (plus:DI (match_dup 3)
5948 (const_int 1)))
5949 (set (match_dup 0) (plus:DI (match_dup 0)
5950 (const_int 2047)))
5951 (set (match_dup 4) (compare:CCUNS (match_dup 3)
5952 (const_int 2)))
5953 (set (match_dup 0) (ior:DI (match_dup 0)
5954 (match_dup 1)))
5955 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
5956 (const_int -2048)))
5957 (clobber (scratch:CC))])
5958 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
5959 (label_ref (match_operand:DI 2 "" ""))
5960 (pc)))
5961 (set (match_dup 0) (match_dup 1))]
5962 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5963 "
5964 {
5965 operands[3] = gen_reg_rtx (DImode);
5966 operands[4] = gen_reg_rtx (CCUNSmode);
5967 }")
5968 \f
5969 ;; Define the DImode operations that can be done in a small number
5970 ;; of instructions. The & constraints are to prevent the register
5971 ;; allocator from allocating registers that overlap with the inputs
5972 ;; (for example, having an input in 7,8 and an output in 6,7). We
5973 ;; also allow for the output being the same as one of the inputs.
5974
5975 (define_insn "*adddi3_noppc64"
5976 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5977 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5978 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
5979 "! TARGET_POWERPC64"
5980 "*
5981 {
5982 if (WORDS_BIG_ENDIAN)
5983 return (GET_CODE (operands[2])) != CONST_INT
5984 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5985 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5986 else
5987 return (GET_CODE (operands[2])) != CONST_INT
5988 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5989 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5990 }"
5991 [(set_attr "type" "two")
5992 (set_attr "length" "8")])
5993
5994 (define_insn "*subdi3_noppc64"
5995 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5996 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5997 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
5998 "! TARGET_POWERPC64"
5999 "*
6000 {
6001 if (WORDS_BIG_ENDIAN)
6002 return (GET_CODE (operands[1]) != CONST_INT)
6003 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6004 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6005 else
6006 return (GET_CODE (operands[1]) != CONST_INT)
6007 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6008 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
6009 }"
6010 [(set_attr "type" "two")
6011 (set_attr "length" "8")])
6012
6013 (define_insn "*negdi2_noppc64"
6014 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6015 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6016 "! TARGET_POWERPC64"
6017 "*
6018 {
6019 return (WORDS_BIG_ENDIAN)
6020 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6021 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6022 }"
6023 [(set_attr "type" "two")
6024 (set_attr "length" "8")])
6025
6026 (define_expand "mulsidi3"
6027 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6028 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6029 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6030 "! TARGET_POWERPC64"
6031 "
6032 {
6033 if (! TARGET_POWER && ! TARGET_POWERPC)
6034 {
6035 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6036 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6037 emit_insn (gen_mull_call ());
6038 if (WORDS_BIG_ENDIAN)
6039 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
6040 else
6041 {
6042 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
6043 gen_rtx_REG (SImode, 3));
6044 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
6045 gen_rtx_REG (SImode, 4));
6046 }
6047 DONE;
6048 }
6049 else if (TARGET_POWER)
6050 {
6051 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6052 DONE;
6053 }
6054 }")
6055
6056 (define_insn "mulsidi3_mq"
6057 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6058 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6059 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6060 (clobber (match_scratch:SI 3 "=q"))]
6061 "TARGET_POWER"
6062 "mul %0,%1,%2\;mfmq %L0"
6063 [(set_attr "type" "imul")
6064 (set_attr "length" "8")])
6065
6066 (define_insn "*mulsidi3_no_mq"
6067 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6068 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6069 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6070 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6071 "*
6072 {
6073 return (WORDS_BIG_ENDIAN)
6074 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6075 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6076 }"
6077 [(set_attr "type" "imul")
6078 (set_attr "length" "8")])
6079
6080 (define_split
6081 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6082 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6083 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6084 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6085 [(set (match_dup 3)
6086 (truncate:SI
6087 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6088 (sign_extend:DI (match_dup 2)))
6089 (const_int 32))))
6090 (set (match_dup 4)
6091 (mult:SI (match_dup 1)
6092 (match_dup 2)))]
6093 "
6094 {
6095 int endian = (WORDS_BIG_ENDIAN == 0);
6096 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6097 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6098 }")
6099
6100 (define_expand "umulsidi3"
6101 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6102 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6103 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6104 "TARGET_POWERPC && ! TARGET_POWERPC64"
6105 "
6106 {
6107 if (TARGET_POWER)
6108 {
6109 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6110 DONE;
6111 }
6112 }")
6113
6114 (define_insn "umulsidi3_mq"
6115 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6116 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6117 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6118 (clobber (match_scratch:SI 3 "=q"))]
6119 "TARGET_POWERPC && TARGET_POWER"
6120 "*
6121 {
6122 return (WORDS_BIG_ENDIAN)
6123 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6124 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6125 }"
6126 [(set_attr "type" "imul")
6127 (set_attr "length" "8")])
6128
6129 (define_insn "*umulsidi3_no_mq"
6130 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6131 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6132 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6133 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6134 "*
6135 {
6136 return (WORDS_BIG_ENDIAN)
6137 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6138 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6139 }"
6140 [(set_attr "type" "imul")
6141 (set_attr "length" "8")])
6142
6143 (define_split
6144 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6145 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6146 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6147 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6148 [(set (match_dup 3)
6149 (truncate:SI
6150 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6151 (zero_extend:DI (match_dup 2)))
6152 (const_int 32))))
6153 (set (match_dup 4)
6154 (mult:SI (match_dup 1)
6155 (match_dup 2)))]
6156 "
6157 {
6158 int endian = (WORDS_BIG_ENDIAN == 0);
6159 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6160 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6161 }")
6162
6163 (define_expand "smulsi3_highpart"
6164 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6165 (truncate:SI
6166 (lshiftrt:DI (mult:DI (sign_extend:DI
6167 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6168 (sign_extend:DI
6169 (match_operand:SI 2 "gpc_reg_operand" "r")))
6170 (const_int 32))))]
6171 ""
6172 "
6173 {
6174 if (! TARGET_POWER && ! TARGET_POWERPC)
6175 {
6176 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6177 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6178 emit_insn (gen_mulh_call ());
6179 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
6180 DONE;
6181 }
6182 else if (TARGET_POWER)
6183 {
6184 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6185 DONE;
6186 }
6187 }")
6188
6189 (define_insn "smulsi3_highpart_mq"
6190 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6191 (truncate:SI
6192 (lshiftrt:DI (mult:DI (sign_extend:DI
6193 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6194 (sign_extend:DI
6195 (match_operand:SI 2 "gpc_reg_operand" "r")))
6196 (const_int 32))))
6197 (clobber (match_scratch:SI 3 "=q"))]
6198 "TARGET_POWER"
6199 "mul %0,%1,%2"
6200 [(set_attr "type" "imul")])
6201
6202 (define_insn "*smulsi3_highpart_no_mq"
6203 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6204 (truncate:SI
6205 (lshiftrt:DI (mult:DI (sign_extend:DI
6206 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6207 (sign_extend:DI
6208 (match_operand:SI 2 "gpc_reg_operand" "r")))
6209 (const_int 32))))]
6210 "TARGET_POWERPC && ! TARGET_POWER"
6211 "mulhw %0,%1,%2"
6212 [(set_attr "type" "imul")])
6213
6214 (define_expand "umulsi3_highpart"
6215 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6216 (truncate:SI
6217 (lshiftrt:DI (mult:DI (zero_extend:DI
6218 (match_operand:SI 1 "gpc_reg_operand" ""))
6219 (zero_extend:DI
6220 (match_operand:SI 2 "gpc_reg_operand" "")))
6221 (const_int 32))))]
6222 "TARGET_POWERPC"
6223 "
6224 {
6225 if (TARGET_POWER)
6226 {
6227 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6228 DONE;
6229 }
6230 }")
6231
6232 (define_insn "umulsi3_highpart_mq"
6233 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6234 (truncate:SI
6235 (lshiftrt:DI (mult:DI (zero_extend:DI
6236 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6237 (zero_extend:DI
6238 (match_operand:SI 2 "gpc_reg_operand" "r")))
6239 (const_int 32))))
6240 (clobber (match_scratch:SI 3 "=q"))]
6241 "TARGET_POWERPC && TARGET_POWER"
6242 "mulhwu %0,%1,%2"
6243 [(set_attr "type" "imul")])
6244
6245 (define_insn "*umulsi3_highpart_no_mq"
6246 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6247 (truncate:SI
6248 (lshiftrt:DI (mult:DI (zero_extend:DI
6249 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6250 (zero_extend:DI
6251 (match_operand:SI 2 "gpc_reg_operand" "r")))
6252 (const_int 32))))]
6253 "TARGET_POWERPC && ! TARGET_POWER"
6254 "mulhwu %0,%1,%2"
6255 [(set_attr "type" "imul")])
6256
6257 ;; If operands 0 and 2 are in the same register, we have a problem. But
6258 ;; operands 0 and 1 (the usual case) can be in the same register. That's
6259 ;; why we have the strange constraints below.
6260 (define_insn "ashldi3_power"
6261 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6262 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6263 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6264 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6265 "TARGET_POWER"
6266 "@
6267 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
6268 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6269 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6270 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
6271 [(set_attr "length" "8")])
6272
6273 (define_insn "lshrdi3_power"
6274 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6275 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6276 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6277 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6278 "TARGET_POWER"
6279 "@
6280 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
6281 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6282 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6283 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
6284 [(set_attr "length" "8")])
6285
6286 ;; Shift by a variable amount is too complex to be worth open-coding. We
6287 ;; just handle shifts by constants.
6288 (define_insn "ashrdi3_power"
6289 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6290 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6291 (match_operand:SI 2 "const_int_operand" "M,i")))
6292 (clobber (match_scratch:SI 3 "=X,q"))]
6293 "TARGET_POWER"
6294 "@
6295 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6296 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
6297 [(set_attr "length" "8")])
6298
6299 (define_insn "ashrdi3_no_power"
6300 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6301 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6302 (match_operand:SI 2 "const_int_operand" "M,i")))]
6303 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
6304 "@
6305 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6306 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
6307 [(set_attr "type" "two,three")
6308 (set_attr "length" "8,12")])
6309
6310 (define_insn "*ashrdisi3_noppc64"
6311 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6312 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6313 (const_int 32)) 4))]
6314 "TARGET_32BIT && !TARGET_POWERPC64"
6315 "*
6316 {
6317 if (REGNO (operands[0]) == REGNO (operands[1]))
6318 return \"\";
6319 else
6320 return \"mr %0,%1\";
6321 }"
6322 [(set_attr "length" "4")])
6323
6324 \f
6325 ;; PowerPC64 DImode operations.
6326
6327 (define_insn_and_split "absdi2"
6328 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6329 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6330 (clobber (match_scratch:DI 2 "=&r,&r"))]
6331 "TARGET_POWERPC64"
6332 "#"
6333 "&& reload_completed"
6334 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6335 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6336 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6337 "")
6338
6339 (define_insn_and_split "*nabsdi2"
6340 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6341 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6342 (clobber (match_scratch:DI 2 "=&r,&r"))]
6343 "TARGET_POWERPC64"
6344 "#"
6345 "&& reload_completed"
6346 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6347 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6348 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
6349 "")
6350
6351 (define_insn "muldi3"
6352 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6353 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6354 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6355 "TARGET_POWERPC64"
6356 "@
6357 mulld %0,%1,%2
6358 mulli %0,%1,%2"
6359 [(set (attr "type")
6360 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6361 (const_string "imul3")
6362 (match_operand:SI 2 "short_cint_operand" "")
6363 (const_string "imul2")]
6364 (const_string "lmul")))])
6365
6366 (define_insn "*muldi3_internal1"
6367 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6368 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6369 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6370 (const_int 0)))
6371 (clobber (match_scratch:DI 3 "=r,r"))]
6372 "TARGET_POWERPC64"
6373 "@
6374 mulld. %3,%1,%2
6375 #"
6376 [(set_attr "type" "lmul_compare")
6377 (set_attr "length" "4,8")])
6378
6379 (define_split
6380 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6381 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6382 (match_operand:DI 2 "gpc_reg_operand" ""))
6383 (const_int 0)))
6384 (clobber (match_scratch:DI 3 ""))]
6385 "TARGET_POWERPC64 && reload_completed"
6386 [(set (match_dup 3)
6387 (mult:DI (match_dup 1) (match_dup 2)))
6388 (set (match_dup 0)
6389 (compare:CC (match_dup 3)
6390 (const_int 0)))]
6391 "")
6392
6393 (define_insn "*muldi3_internal2"
6394 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6395 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6396 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6397 (const_int 0)))
6398 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6399 (mult:DI (match_dup 1) (match_dup 2)))]
6400 "TARGET_POWERPC64"
6401 "@
6402 mulld. %0,%1,%2
6403 #"
6404 [(set_attr "type" "lmul_compare")
6405 (set_attr "length" "4,8")])
6406
6407 (define_split
6408 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6409 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6410 (match_operand:DI 2 "gpc_reg_operand" ""))
6411 (const_int 0)))
6412 (set (match_operand:DI 0 "gpc_reg_operand" "")
6413 (mult:DI (match_dup 1) (match_dup 2)))]
6414 "TARGET_POWERPC64 && reload_completed"
6415 [(set (match_dup 0)
6416 (mult:DI (match_dup 1) (match_dup 2)))
6417 (set (match_dup 3)
6418 (compare:CC (match_dup 0)
6419 (const_int 0)))]
6420 "")
6421
6422 (define_insn "smuldi3_highpart"
6423 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6424 (truncate:DI
6425 (lshiftrt:TI (mult:TI (sign_extend:TI
6426 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6427 (sign_extend:TI
6428 (match_operand:DI 2 "gpc_reg_operand" "r")))
6429 (const_int 64))))]
6430 "TARGET_POWERPC64"
6431 "mulhd %0,%1,%2"
6432 [(set_attr "type" "lmul")])
6433
6434 (define_insn "umuldi3_highpart"
6435 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6436 (truncate:DI
6437 (lshiftrt:TI (mult:TI (zero_extend:TI
6438 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6439 (zero_extend:TI
6440 (match_operand:DI 2 "gpc_reg_operand" "r")))
6441 (const_int 64))))]
6442 "TARGET_POWERPC64"
6443 "mulhdu %0,%1,%2"
6444 [(set_attr "type" "lmul")])
6445
6446 (define_insn "rotldi3"
6447 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6448 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6449 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6450 "TARGET_POWERPC64"
6451 "rld%I2cl %0,%1,%H2,0")
6452
6453 (define_insn "*rotldi3_internal2"
6454 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6455 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6456 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6457 (const_int 0)))
6458 (clobber (match_scratch:DI 3 "=r,r"))]
6459 "TARGET_64BIT"
6460 "@
6461 rld%I2cl. %3,%1,%H2,0
6462 #"
6463 [(set_attr "type" "delayed_compare")
6464 (set_attr "length" "4,8")])
6465
6466 (define_split
6467 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6468 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6469 (match_operand:DI 2 "reg_or_cint_operand" ""))
6470 (const_int 0)))
6471 (clobber (match_scratch:DI 3 ""))]
6472 "TARGET_POWERPC64 && reload_completed"
6473 [(set (match_dup 3)
6474 (rotate:DI (match_dup 1) (match_dup 2)))
6475 (set (match_dup 0)
6476 (compare:CC (match_dup 3)
6477 (const_int 0)))]
6478 "")
6479
6480 (define_insn "*rotldi3_internal3"
6481 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6482 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6483 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6484 (const_int 0)))
6485 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6486 (rotate:DI (match_dup 1) (match_dup 2)))]
6487 "TARGET_64BIT"
6488 "@
6489 rld%I2cl. %0,%1,%H2,0
6490 #"
6491 [(set_attr "type" "delayed_compare")
6492 (set_attr "length" "4,8")])
6493
6494 (define_split
6495 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6496 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6497 (match_operand:DI 2 "reg_or_cint_operand" ""))
6498 (const_int 0)))
6499 (set (match_operand:DI 0 "gpc_reg_operand" "")
6500 (rotate:DI (match_dup 1) (match_dup 2)))]
6501 "TARGET_POWERPC64 && reload_completed"
6502 [(set (match_dup 0)
6503 (rotate:DI (match_dup 1) (match_dup 2)))
6504 (set (match_dup 3)
6505 (compare:CC (match_dup 0)
6506 (const_int 0)))]
6507 "")
6508
6509 (define_insn "*rotldi3_internal4"
6510 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6511 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6512 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
6513 (match_operand:DI 3 "mask64_operand" "n")))]
6514 "TARGET_POWERPC64"
6515 "rld%I2c%B3 %0,%1,%H2,%S3")
6516
6517 (define_insn "*rotldi3_internal5"
6518 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6519 (compare:CC (and:DI
6520 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6521 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6522 (match_operand:DI 3 "mask64_operand" "n,n"))
6523 (const_int 0)))
6524 (clobber (match_scratch:DI 4 "=r,r"))]
6525 "TARGET_64BIT"
6526 "@
6527 rld%I2c%B3. %4,%1,%H2,%S3
6528 #"
6529 [(set_attr "type" "delayed_compare")
6530 (set_attr "length" "4,8")])
6531
6532 (define_split
6533 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6534 (compare:CC (and:DI
6535 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6536 (match_operand:DI 2 "reg_or_cint_operand" ""))
6537 (match_operand:DI 3 "mask64_operand" ""))
6538 (const_int 0)))
6539 (clobber (match_scratch:DI 4 ""))]
6540 "TARGET_POWERPC64 && reload_completed"
6541 [(set (match_dup 4)
6542 (and:DI (rotate:DI (match_dup 1)
6543 (match_dup 2))
6544 (match_dup 3)))
6545 (set (match_dup 0)
6546 (compare:CC (match_dup 4)
6547 (const_int 0)))]
6548 "")
6549
6550 (define_insn "*rotldi3_internal6"
6551 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6552 (compare:CC (and:DI
6553 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6554 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6555 (match_operand:DI 3 "mask64_operand" "n,n"))
6556 (const_int 0)))
6557 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6558 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6559 "TARGET_64BIT"
6560 "@
6561 rld%I2c%B3. %0,%1,%H2,%S3
6562 #"
6563 [(set_attr "type" "delayed_compare")
6564 (set_attr "length" "4,8")])
6565
6566 (define_split
6567 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6568 (compare:CC (and:DI
6569 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6570 (match_operand:DI 2 "reg_or_cint_operand" ""))
6571 (match_operand:DI 3 "mask64_operand" ""))
6572 (const_int 0)))
6573 (set (match_operand:DI 0 "gpc_reg_operand" "")
6574 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6575 "TARGET_POWERPC64 && reload_completed"
6576 [(set (match_dup 0)
6577 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6578 (set (match_dup 4)
6579 (compare:CC (match_dup 0)
6580 (const_int 0)))]
6581 "")
6582
6583 (define_insn "*rotldi3_internal7"
6584 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6585 (zero_extend:DI
6586 (subreg:QI
6587 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6588 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6589 "TARGET_POWERPC64"
6590 "rld%I2cl %0,%1,%H2,56")
6591
6592 (define_insn "*rotldi3_internal8"
6593 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6594 (compare:CC (zero_extend:DI
6595 (subreg:QI
6596 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6597 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6598 (const_int 0)))
6599 (clobber (match_scratch:DI 3 "=r,r"))]
6600 "TARGET_64BIT"
6601 "@
6602 rld%I2cl. %3,%1,%H2,56
6603 #"
6604 [(set_attr "type" "delayed_compare")
6605 (set_attr "length" "4,8")])
6606
6607 (define_split
6608 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6609 (compare:CC (zero_extend:DI
6610 (subreg:QI
6611 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6612 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6613 (const_int 0)))
6614 (clobber (match_scratch:DI 3 ""))]
6615 "TARGET_POWERPC64 && reload_completed"
6616 [(set (match_dup 3)
6617 (zero_extend:DI (subreg:QI
6618 (rotate:DI (match_dup 1)
6619 (match_dup 2)) 0)))
6620 (set (match_dup 0)
6621 (compare:CC (match_dup 3)
6622 (const_int 0)))]
6623 "")
6624
6625 (define_insn "*rotldi3_internal9"
6626 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6627 (compare:CC (zero_extend:DI
6628 (subreg:QI
6629 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6630 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6631 (const_int 0)))
6632 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6633 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6634 "TARGET_64BIT"
6635 "@
6636 rld%I2cl. %0,%1,%H2,56
6637 #"
6638 [(set_attr "type" "delayed_compare")
6639 (set_attr "length" "4,8")])
6640
6641 (define_split
6642 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6643 (compare:CC (zero_extend:DI
6644 (subreg:QI
6645 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6646 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6647 (const_int 0)))
6648 (set (match_operand:DI 0 "gpc_reg_operand" "")
6649 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6650 "TARGET_POWERPC64 && reload_completed"
6651 [(set (match_dup 0)
6652 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6653 (set (match_dup 3)
6654 (compare:CC (match_dup 0)
6655 (const_int 0)))]
6656 "")
6657
6658 (define_insn "*rotldi3_internal10"
6659 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6660 (zero_extend:DI
6661 (subreg:HI
6662 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6663 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6664 "TARGET_POWERPC64"
6665 "rld%I2cl %0,%1,%H2,48")
6666
6667 (define_insn "*rotldi3_internal11"
6668 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6669 (compare:CC (zero_extend:DI
6670 (subreg:HI
6671 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6672 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6673 (const_int 0)))
6674 (clobber (match_scratch:DI 3 "=r,r"))]
6675 "TARGET_64BIT"
6676 "@
6677 rld%I2cl. %3,%1,%H2,48
6678 #"
6679 [(set_attr "type" "delayed_compare")
6680 (set_attr "length" "4,8")])
6681
6682 (define_split
6683 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6684 (compare:CC (zero_extend:DI
6685 (subreg:HI
6686 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6687 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6688 (const_int 0)))
6689 (clobber (match_scratch:DI 3 ""))]
6690 "TARGET_POWERPC64 && reload_completed"
6691 [(set (match_dup 3)
6692 (zero_extend:DI (subreg:HI
6693 (rotate:DI (match_dup 1)
6694 (match_dup 2)) 0)))
6695 (set (match_dup 0)
6696 (compare:CC (match_dup 3)
6697 (const_int 0)))]
6698 "")
6699
6700 (define_insn "*rotldi3_internal12"
6701 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6702 (compare:CC (zero_extend:DI
6703 (subreg:HI
6704 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6705 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6706 (const_int 0)))
6707 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6708 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6709 "TARGET_64BIT"
6710 "@
6711 rld%I2cl. %0,%1,%H2,48
6712 #"
6713 [(set_attr "type" "delayed_compare")
6714 (set_attr "length" "4,8")])
6715
6716 (define_split
6717 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6718 (compare:CC (zero_extend:DI
6719 (subreg:HI
6720 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6721 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6722 (const_int 0)))
6723 (set (match_operand:DI 0 "gpc_reg_operand" "")
6724 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6725 "TARGET_POWERPC64 && reload_completed"
6726 [(set (match_dup 0)
6727 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6728 (set (match_dup 3)
6729 (compare:CC (match_dup 0)
6730 (const_int 0)))]
6731 "")
6732
6733 (define_insn "*rotldi3_internal13"
6734 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6735 (zero_extend:DI
6736 (subreg:SI
6737 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6738 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6739 "TARGET_POWERPC64"
6740 "rld%I2cl %0,%1,%H2,32")
6741
6742 (define_insn "*rotldi3_internal14"
6743 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6744 (compare:CC (zero_extend:DI
6745 (subreg:SI
6746 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6747 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6748 (const_int 0)))
6749 (clobber (match_scratch:DI 3 "=r,r"))]
6750 "TARGET_64BIT"
6751 "@
6752 rld%I2cl. %3,%1,%H2,32
6753 #"
6754 [(set_attr "type" "delayed_compare")
6755 (set_attr "length" "4,8")])
6756
6757 (define_split
6758 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6759 (compare:CC (zero_extend:DI
6760 (subreg:SI
6761 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6762 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6763 (const_int 0)))
6764 (clobber (match_scratch:DI 3 ""))]
6765 "TARGET_POWERPC64 && reload_completed"
6766 [(set (match_dup 3)
6767 (zero_extend:DI (subreg:SI
6768 (rotate:DI (match_dup 1)
6769 (match_dup 2)) 0)))
6770 (set (match_dup 0)
6771 (compare:CC (match_dup 3)
6772 (const_int 0)))]
6773 "")
6774
6775 (define_insn "*rotldi3_internal15"
6776 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6777 (compare:CC (zero_extend:DI
6778 (subreg:SI
6779 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6780 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6781 (const_int 0)))
6782 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6783 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6784 "TARGET_64BIT"
6785 "@
6786 rld%I2cl. %0,%1,%H2,32
6787 #"
6788 [(set_attr "type" "delayed_compare")
6789 (set_attr "length" "4,8")])
6790
6791 (define_split
6792 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6793 (compare:CC (zero_extend:DI
6794 (subreg:SI
6795 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6796 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6797 (const_int 0)))
6798 (set (match_operand:DI 0 "gpc_reg_operand" "")
6799 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6800 "TARGET_POWERPC64 && reload_completed"
6801 [(set (match_dup 0)
6802 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6803 (set (match_dup 3)
6804 (compare:CC (match_dup 0)
6805 (const_int 0)))]
6806 "")
6807
6808 (define_expand "ashldi3"
6809 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6810 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6811 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6812 "TARGET_POWERPC64 || TARGET_POWER"
6813 "
6814 {
6815 if (TARGET_POWERPC64)
6816 ;
6817 else if (TARGET_POWER)
6818 {
6819 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6820 DONE;
6821 }
6822 else
6823 FAIL;
6824 }")
6825
6826 (define_insn "*ashldi3_internal1"
6827 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6828 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6829 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6830 "TARGET_POWERPC64"
6831 "sld%I2 %0,%1,%H2")
6832
6833 (define_insn "*ashldi3_internal2"
6834 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6835 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6836 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6837 (const_int 0)))
6838 (clobber (match_scratch:DI 3 "=r,r"))]
6839 "TARGET_64BIT"
6840 "@
6841 sld%I2. %3,%1,%H2
6842 #"
6843 [(set_attr "type" "delayed_compare")
6844 (set_attr "length" "4,8")])
6845
6846 (define_split
6847 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6848 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6849 (match_operand:SI 2 "reg_or_cint_operand" ""))
6850 (const_int 0)))
6851 (clobber (match_scratch:DI 3 ""))]
6852 "TARGET_POWERPC64 && reload_completed"
6853 [(set (match_dup 3)
6854 (ashift:DI (match_dup 1) (match_dup 2)))
6855 (set (match_dup 0)
6856 (compare:CC (match_dup 3)
6857 (const_int 0)))]
6858 "")
6859
6860 (define_insn "*ashldi3_internal3"
6861 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6862 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6863 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6864 (const_int 0)))
6865 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6866 (ashift:DI (match_dup 1) (match_dup 2)))]
6867 "TARGET_64BIT"
6868 "@
6869 sld%I2. %0,%1,%H2
6870 #"
6871 [(set_attr "type" "delayed_compare")
6872 (set_attr "length" "4,8")])
6873
6874 (define_split
6875 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6876 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6877 (match_operand:SI 2 "reg_or_cint_operand" ""))
6878 (const_int 0)))
6879 (set (match_operand:DI 0 "gpc_reg_operand" "")
6880 (ashift:DI (match_dup 1) (match_dup 2)))]
6881 "TARGET_POWERPC64 && reload_completed"
6882 [(set (match_dup 0)
6883 (ashift:DI (match_dup 1) (match_dup 2)))
6884 (set (match_dup 3)
6885 (compare:CC (match_dup 0)
6886 (const_int 0)))]
6887 "")
6888
6889 (define_insn "*ashldi3_internal4"
6890 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6891 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6892 (match_operand:SI 2 "const_int_operand" "i"))
6893 (match_operand:DI 3 "const_int_operand" "n")))]
6894 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6895 "rldic %0,%1,%H2,%W3")
6896
6897 (define_insn "ashldi3_internal5"
6898 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6899 (compare:CC
6900 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6901 (match_operand:SI 2 "const_int_operand" "i,i"))
6902 (match_operand:DI 3 "const_int_operand" "n,n"))
6903 (const_int 0)))
6904 (clobber (match_scratch:DI 4 "=r,r"))]
6905 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6906 "@
6907 rldic. %4,%1,%H2,%W3
6908 #"
6909 [(set_attr "type" "compare")
6910 (set_attr "length" "4,8")])
6911
6912 (define_split
6913 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6914 (compare:CC
6915 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6916 (match_operand:SI 2 "const_int_operand" ""))
6917 (match_operand:DI 3 "const_int_operand" ""))
6918 (const_int 0)))
6919 (clobber (match_scratch:DI 4 ""))]
6920 "TARGET_POWERPC64 && reload_completed
6921 && includes_rldic_lshift_p (operands[2], operands[3])"
6922 [(set (match_dup 4)
6923 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6924 (match_dup 3)))
6925 (set (match_dup 0)
6926 (compare:CC (match_dup 4)
6927 (const_int 0)))]
6928 "")
6929
6930 (define_insn "*ashldi3_internal6"
6931 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6932 (compare:CC
6933 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6934 (match_operand:SI 2 "const_int_operand" "i,i"))
6935 (match_operand:DI 3 "const_int_operand" "n,n"))
6936 (const_int 0)))
6937 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6938 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6939 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6940 "@
6941 rldic. %0,%1,%H2,%W3
6942 #"
6943 [(set_attr "type" "compare")
6944 (set_attr "length" "4,8")])
6945
6946 (define_split
6947 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6948 (compare:CC
6949 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6950 (match_operand:SI 2 "const_int_operand" ""))
6951 (match_operand:DI 3 "const_int_operand" ""))
6952 (const_int 0)))
6953 (set (match_operand:DI 0 "gpc_reg_operand" "")
6954 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6955 "TARGET_POWERPC64 && reload_completed
6956 && includes_rldic_lshift_p (operands[2], operands[3])"
6957 [(set (match_dup 0)
6958 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6959 (match_dup 3)))
6960 (set (match_dup 4)
6961 (compare:CC (match_dup 0)
6962 (const_int 0)))]
6963 "")
6964
6965 (define_insn "*ashldi3_internal7"
6966 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6967 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6968 (match_operand:SI 2 "const_int_operand" "i"))
6969 (match_operand:DI 3 "mask64_operand" "n")))]
6970 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6971 "rldicr %0,%1,%H2,%S3")
6972
6973 (define_insn "ashldi3_internal8"
6974 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6975 (compare:CC
6976 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6977 (match_operand:SI 2 "const_int_operand" "i,i"))
6978 (match_operand:DI 3 "mask64_operand" "n,n"))
6979 (const_int 0)))
6980 (clobber (match_scratch:DI 4 "=r,r"))]
6981 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6982 "@
6983 rldicr. %4,%1,%H2,%S3
6984 #"
6985 [(set_attr "type" "compare")
6986 (set_attr "length" "4,8")])
6987
6988 (define_split
6989 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6990 (compare:CC
6991 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6992 (match_operand:SI 2 "const_int_operand" ""))
6993 (match_operand:DI 3 "mask64_operand" ""))
6994 (const_int 0)))
6995 (clobber (match_scratch:DI 4 ""))]
6996 "TARGET_POWERPC64 && reload_completed
6997 && includes_rldicr_lshift_p (operands[2], operands[3])"
6998 [(set (match_dup 4)
6999 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7000 (match_dup 3)))
7001 (set (match_dup 0)
7002 (compare:CC (match_dup 4)
7003 (const_int 0)))]
7004 "")
7005
7006 (define_insn "*ashldi3_internal9"
7007 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7008 (compare:CC
7009 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7010 (match_operand:SI 2 "const_int_operand" "i,i"))
7011 (match_operand:DI 3 "mask64_operand" "n,n"))
7012 (const_int 0)))
7013 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7014 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7015 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7016 "@
7017 rldicr. %0,%1,%H2,%S3
7018 #"
7019 [(set_attr "type" "compare")
7020 (set_attr "length" "4,8")])
7021
7022 (define_split
7023 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7024 (compare:CC
7025 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7026 (match_operand:SI 2 "const_int_operand" ""))
7027 (match_operand:DI 3 "mask64_operand" ""))
7028 (const_int 0)))
7029 (set (match_operand:DI 0 "gpc_reg_operand" "")
7030 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7031 "TARGET_POWERPC64 && reload_completed
7032 && includes_rldicr_lshift_p (operands[2], operands[3])"
7033 [(set (match_dup 0)
7034 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7035 (match_dup 3)))
7036 (set (match_dup 4)
7037 (compare:CC (match_dup 0)
7038 (const_int 0)))]
7039 "")
7040
7041 (define_expand "lshrdi3"
7042 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7043 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7044 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7045 "TARGET_POWERPC64 || TARGET_POWER"
7046 "
7047 {
7048 if (TARGET_POWERPC64)
7049 ;
7050 else if (TARGET_POWER)
7051 {
7052 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7053 DONE;
7054 }
7055 else
7056 FAIL;
7057 }")
7058
7059 (define_insn "*lshrdi3_internal1"
7060 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7061 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7062 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
7063 "TARGET_POWERPC64"
7064 "srd%I2 %0,%1,%H2")
7065
7066 (define_insn "*lshrdi3_internal2"
7067 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7068 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7069 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7070 (const_int 0)))
7071 (clobber (match_scratch:DI 3 "=r,r"))]
7072 "TARGET_64BIT "
7073 "@
7074 srd%I2. %3,%1,%H2
7075 #"
7076 [(set_attr "type" "delayed_compare")
7077 (set_attr "length" "4,8")])
7078
7079 (define_split
7080 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7081 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7082 (match_operand:SI 2 "reg_or_cint_operand" ""))
7083 (const_int 0)))
7084 (clobber (match_scratch:DI 3 ""))]
7085 "TARGET_POWERPC64 && reload_completed"
7086 [(set (match_dup 3)
7087 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7088 (set (match_dup 0)
7089 (compare:CC (match_dup 3)
7090 (const_int 0)))]
7091 "")
7092
7093 (define_insn "*lshrdi3_internal3"
7094 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7095 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7096 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7097 (const_int 0)))
7098 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7099 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7100 "TARGET_64BIT"
7101 "@
7102 srd%I2. %0,%1,%H2
7103 #"
7104 [(set_attr "type" "delayed_compare")
7105 (set_attr "length" "4,8")])
7106
7107 (define_split
7108 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7109 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7110 (match_operand:SI 2 "reg_or_cint_operand" ""))
7111 (const_int 0)))
7112 (set (match_operand:DI 0 "gpc_reg_operand" "")
7113 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7114 "TARGET_POWERPC64 && reload_completed"
7115 [(set (match_dup 0)
7116 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7117 (set (match_dup 3)
7118 (compare:CC (match_dup 0)
7119 (const_int 0)))]
7120 "")
7121
7122 (define_expand "ashrdi3"
7123 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7124 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7125 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7126 "WORDS_BIG_ENDIAN"
7127 "
7128 {
7129 if (TARGET_POWERPC64)
7130 ;
7131 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7132 {
7133 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7134 DONE;
7135 }
7136 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7137 && WORDS_BIG_ENDIAN)
7138 {
7139 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7140 DONE;
7141 }
7142 else
7143 FAIL;
7144 }")
7145
7146 (define_insn "*ashrdi3_internal1"
7147 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7148 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7149 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
7150 "TARGET_POWERPC64"
7151 "srad%I2 %0,%1,%H2")
7152
7153 (define_insn "*ashrdi3_internal2"
7154 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7155 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7156 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7157 (const_int 0)))
7158 (clobber (match_scratch:DI 3 "=r,r"))]
7159 "TARGET_64BIT"
7160 "@
7161 srad%I2. %3,%1,%H2
7162 #"
7163 [(set_attr "type" "delayed_compare")
7164 (set_attr "length" "4,8")])
7165
7166 (define_split
7167 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7168 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7169 (match_operand:SI 2 "reg_or_cint_operand" ""))
7170 (const_int 0)))
7171 (clobber (match_scratch:DI 3 ""))]
7172 "TARGET_POWERPC64 && reload_completed"
7173 [(set (match_dup 3)
7174 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7175 (set (match_dup 0)
7176 (compare:CC (match_dup 3)
7177 (const_int 0)))]
7178 "")
7179
7180 (define_insn "*ashrdi3_internal3"
7181 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7182 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7183 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7184 (const_int 0)))
7185 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7186 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7187 "TARGET_64BIT"
7188 "@
7189 srad%I2. %0,%1,%H2
7190 #"
7191 [(set_attr "type" "delayed_compare")
7192 (set_attr "length" "4,8")])
7193
7194 (define_split
7195 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7196 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7197 (match_operand:SI 2 "reg_or_cint_operand" ""))
7198 (const_int 0)))
7199 (set (match_operand:DI 0 "gpc_reg_operand" "")
7200 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7201 "TARGET_POWERPC64 && reload_completed"
7202 [(set (match_dup 0)
7203 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7204 (set (match_dup 3)
7205 (compare:CC (match_dup 0)
7206 (const_int 0)))]
7207 "")
7208
7209 (define_insn "anddi3"
7210 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7211 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7212 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7213 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7214 "TARGET_POWERPC64"
7215 "@
7216 and %0,%1,%2
7217 rldic%B2 %0,%1,0,%S2
7218 rlwinm %0,%1,0,%m2,%M2
7219 andi. %0,%1,%b2
7220 andis. %0,%1,%u2
7221 #"
7222 [(set_attr "type" "*,*,*,compare,compare,*")
7223 (set_attr "length" "4,4,4,4,4,8")])
7224
7225 (define_split
7226 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7227 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7228 (match_operand:DI 2 "mask64_2_operand" "")))
7229 (clobber (match_scratch:CC 3 ""))]
7230 "TARGET_POWERPC64
7231 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7232 && !mask_operand (operands[2], DImode)
7233 && !mask64_operand (operands[2], DImode)"
7234 [(set (match_dup 0)
7235 (and:DI (rotate:DI (match_dup 1)
7236 (match_dup 4))
7237 (match_dup 5)))
7238 (set (match_dup 0)
7239 (and:DI (rotate:DI (match_dup 0)
7240 (match_dup 6))
7241 (match_dup 7)))]
7242 {
7243 build_mask64_2_operands (operands[2], &operands[4]);
7244 })
7245
7246 (define_insn "*anddi3_internal2"
7247 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7248 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7249 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7250 (const_int 0)))
7251 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7252 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7253 "TARGET_64BIT"
7254 "@
7255 and. %3,%1,%2
7256 rldic%B2. %3,%1,0,%S2
7257 rlwinm. %3,%1,0,%m2,%M2
7258 andi. %3,%1,%b2
7259 andis. %3,%1,%u2
7260 #
7261 #
7262 #
7263 #
7264 #
7265 #
7266 #"
7267 [(set_attr "type" "compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7268 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7269
7270 (define_split
7271 [(set (match_operand:CC 0 "cc_reg_operand" "")
7272 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7273 (match_operand:DI 2 "mask64_2_operand" ""))
7274 (const_int 0)))
7275 (clobber (match_scratch:DI 3 ""))
7276 (clobber (match_scratch:CC 4 ""))]
7277 "TARGET_64BIT && reload_completed
7278 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7279 && !mask_operand (operands[2], DImode)
7280 && !mask64_operand (operands[2], DImode)"
7281 [(set (match_dup 3)
7282 (and:DI (rotate:DI (match_dup 1)
7283 (match_dup 5))
7284 (match_dup 6)))
7285 (parallel [(set (match_dup 0)
7286 (compare:CC (and:DI (rotate:DI (match_dup 3)
7287 (match_dup 7))
7288 (match_dup 8))
7289 (const_int 0)))
7290 (clobber (match_dup 3))])]
7291 "
7292 {
7293 build_mask64_2_operands (operands[2], &operands[5]);
7294 }")
7295
7296 (define_insn "*anddi3_internal3"
7297 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7298 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7299 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7300 (const_int 0)))
7301 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
7302 (and:DI (match_dup 1) (match_dup 2)))
7303 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7304 "TARGET_64BIT"
7305 "@
7306 and. %0,%1,%2
7307 rldic%B2. %0,%1,0,%S2
7308 rlwinm. %0,%1,0,%m2,%M2
7309 andi. %0,%1,%b2
7310 andis. %0,%1,%u2
7311 #
7312 #
7313 #
7314 #
7315 #
7316 #
7317 #"
7318 [(set_attr "type" "compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7319 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7320
7321 (define_split
7322 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7323 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7324 (match_operand:DI 2 "and64_2_operand" ""))
7325 (const_int 0)))
7326 (set (match_operand:DI 0 "gpc_reg_operand" "")
7327 (and:DI (match_dup 1) (match_dup 2)))
7328 (clobber (match_scratch:CC 4 ""))]
7329 "TARGET_64BIT && reload_completed"
7330 [(parallel [(set (match_dup 0)
7331 (and:DI (match_dup 1) (match_dup 2)))
7332 (clobber (match_dup 4))])
7333 (set (match_dup 3)
7334 (compare:CC (match_dup 0)
7335 (const_int 0)))]
7336 "")
7337
7338 (define_split
7339 [(set (match_operand:CC 3 "cc_reg_operand" "")
7340 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7341 (match_operand:DI 2 "mask64_2_operand" ""))
7342 (const_int 0)))
7343 (set (match_operand:DI 0 "gpc_reg_operand" "")
7344 (and:DI (match_dup 1) (match_dup 2)))
7345 (clobber (match_scratch:CC 4 ""))]
7346 "TARGET_64BIT && reload_completed
7347 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7348 && !mask_operand (operands[2], DImode)
7349 && !mask64_operand (operands[2], DImode)"
7350 [(set (match_dup 0)
7351 (and:DI (rotate:DI (match_dup 1)
7352 (match_dup 5))
7353 (match_dup 6)))
7354 (parallel [(set (match_dup 3)
7355 (compare:CC (and:DI (rotate:DI (match_dup 0)
7356 (match_dup 7))
7357 (match_dup 8))
7358 (const_int 0)))
7359 (set (match_dup 0)
7360 (and:DI (rotate:DI (match_dup 0)
7361 (match_dup 7))
7362 (match_dup 8)))])]
7363 "
7364 {
7365 build_mask64_2_operands (operands[2], &operands[5]);
7366 }")
7367
7368 (define_expand "iordi3"
7369 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7370 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7371 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7372 "TARGET_POWERPC64"
7373 "
7374 {
7375 if (non_logical_cint_operand (operands[2], DImode))
7376 {
7377 HOST_WIDE_INT value;
7378 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7379 ? operands[0] : gen_reg_rtx (DImode));
7380
7381 if (GET_CODE (operands[2]) == CONST_INT)
7382 {
7383 value = INTVAL (operands[2]);
7384 emit_insn (gen_iordi3 (tmp, operands[1],
7385 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7386 }
7387 else
7388 {
7389 value = CONST_DOUBLE_LOW (operands[2]);
7390 emit_insn (gen_iordi3 (tmp, operands[1],
7391 immed_double_const (value
7392 & (~ (HOST_WIDE_INT) 0xffff),
7393 0, DImode)));
7394 }
7395
7396 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7397 DONE;
7398 }
7399 }")
7400
7401 (define_expand "xordi3"
7402 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7403 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7404 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7405 "TARGET_POWERPC64"
7406 "
7407 {
7408 if (non_logical_cint_operand (operands[2], DImode))
7409 {
7410 HOST_WIDE_INT value;
7411 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7412 ? operands[0] : gen_reg_rtx (DImode));
7413
7414 if (GET_CODE (operands[2]) == CONST_INT)
7415 {
7416 value = INTVAL (operands[2]);
7417 emit_insn (gen_xordi3 (tmp, operands[1],
7418 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7419 }
7420 else
7421 {
7422 value = CONST_DOUBLE_LOW (operands[2]);
7423 emit_insn (gen_xordi3 (tmp, operands[1],
7424 immed_double_const (value
7425 & (~ (HOST_WIDE_INT) 0xffff),
7426 0, DImode)));
7427 }
7428
7429 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7430 DONE;
7431 }
7432 }")
7433
7434 (define_insn "*booldi3_internal1"
7435 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7436 (match_operator:DI 3 "boolean_or_operator"
7437 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7438 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7439 "TARGET_POWERPC64"
7440 "@
7441 %q3 %0,%1,%2
7442 %q3i %0,%1,%b2
7443 %q3is %0,%1,%u2")
7444
7445 (define_insn "*booldi3_internal2"
7446 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7447 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7448 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7449 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7450 (const_int 0)))
7451 (clobber (match_scratch:DI 3 "=r,r"))]
7452 "TARGET_64BIT"
7453 "@
7454 %q4. %3,%1,%2
7455 #"
7456 [(set_attr "type" "compare")
7457 (set_attr "length" "4,8")])
7458
7459 (define_split
7460 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7461 (compare:CC (match_operator:DI 4 "boolean_operator"
7462 [(match_operand:DI 1 "gpc_reg_operand" "")
7463 (match_operand:DI 2 "gpc_reg_operand" "")])
7464 (const_int 0)))
7465 (clobber (match_scratch:DI 3 ""))]
7466 "TARGET_POWERPC64 && reload_completed"
7467 [(set (match_dup 3) (match_dup 4))
7468 (set (match_dup 0)
7469 (compare:CC (match_dup 3)
7470 (const_int 0)))]
7471 "")
7472
7473 (define_insn "*booldi3_internal3"
7474 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7475 (compare:CC (match_operator:DI 4 "boolean_operator"
7476 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7477 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7478 (const_int 0)))
7479 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7480 (match_dup 4))]
7481 "TARGET_64BIT"
7482 "@
7483 %q4. %0,%1,%2
7484 #"
7485 [(set_attr "type" "compare")
7486 (set_attr "length" "4,8")])
7487
7488 (define_split
7489 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7490 (compare:CC (match_operator:DI 4 "boolean_operator"
7491 [(match_operand:DI 1 "gpc_reg_operand" "")
7492 (match_operand:DI 2 "gpc_reg_operand" "")])
7493 (const_int 0)))
7494 (set (match_operand:DI 0 "gpc_reg_operand" "")
7495 (match_dup 4))]
7496 "TARGET_POWERPC64 && reload_completed"
7497 [(set (match_dup 0) (match_dup 4))
7498 (set (match_dup 3)
7499 (compare:CC (match_dup 0)
7500 (const_int 0)))]
7501 "")
7502
7503 ;; Split a logical operation that we can't do in one insn into two insns,
7504 ;; each of which does one 16-bit part. This is used by combine.
7505
7506 (define_split
7507 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7508 (match_operator:DI 3 "boolean_or_operator"
7509 [(match_operand:DI 1 "gpc_reg_operand" "")
7510 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7511 "TARGET_POWERPC64"
7512 [(set (match_dup 0) (match_dup 4))
7513 (set (match_dup 0) (match_dup 5))]
7514 "
7515 {
7516 rtx i3,i4;
7517
7518 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7519 {
7520 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7521 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7522 0, DImode);
7523 i4 = GEN_INT (value & 0xffff);
7524 }
7525 else
7526 {
7527 i3 = GEN_INT (INTVAL (operands[2])
7528 & (~ (HOST_WIDE_INT) 0xffff));
7529 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7530 }
7531 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7532 operands[1], i3);
7533 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7534 operands[0], i4);
7535 }")
7536
7537 (define_insn "*boolcdi3_internal1"
7538 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7539 (match_operator:DI 3 "boolean_operator"
7540 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7541 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7542 "TARGET_POWERPC64"
7543 "%q3 %0,%2,%1")
7544
7545 (define_insn "*boolcdi3_internal2"
7546 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7547 (compare:CC (match_operator:DI 4 "boolean_operator"
7548 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7549 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7550 (const_int 0)))
7551 (clobber (match_scratch:DI 3 "=r,r"))]
7552 "TARGET_64BIT"
7553 "@
7554 %q4. %3,%2,%1
7555 #"
7556 [(set_attr "type" "compare")
7557 (set_attr "length" "4,8")])
7558
7559 (define_split
7560 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7561 (compare:CC (match_operator:DI 4 "boolean_operator"
7562 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7563 (match_operand:DI 2 "gpc_reg_operand" "")])
7564 (const_int 0)))
7565 (clobber (match_scratch:DI 3 ""))]
7566 "TARGET_POWERPC64 && reload_completed"
7567 [(set (match_dup 3) (match_dup 4))
7568 (set (match_dup 0)
7569 (compare:CC (match_dup 3)
7570 (const_int 0)))]
7571 "")
7572
7573 (define_insn "*boolcdi3_internal3"
7574 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7575 (compare:CC (match_operator:DI 4 "boolean_operator"
7576 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7577 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7578 (const_int 0)))
7579 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7580 (match_dup 4))]
7581 "TARGET_64BIT"
7582 "@
7583 %q4. %0,%2,%1
7584 #"
7585 [(set_attr "type" "compare")
7586 (set_attr "length" "4,8")])
7587
7588 (define_split
7589 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7590 (compare:CC (match_operator:DI 4 "boolean_operator"
7591 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7592 (match_operand:DI 2 "gpc_reg_operand" "")])
7593 (const_int 0)))
7594 (set (match_operand:DI 0 "gpc_reg_operand" "")
7595 (match_dup 4))]
7596 "TARGET_POWERPC64 && reload_completed"
7597 [(set (match_dup 0) (match_dup 4))
7598 (set (match_dup 3)
7599 (compare:CC (match_dup 0)
7600 (const_int 0)))]
7601 "")
7602
7603 (define_insn "*boolccdi3_internal1"
7604 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7605 (match_operator:DI 3 "boolean_operator"
7606 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7607 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7608 "TARGET_POWERPC64"
7609 "%q3 %0,%1,%2")
7610
7611 (define_insn "*boolccdi3_internal2"
7612 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7613 (compare:CC (match_operator:DI 4 "boolean_operator"
7614 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7615 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7616 (const_int 0)))
7617 (clobber (match_scratch:DI 3 "=r,r"))]
7618 "TARGET_64BIT"
7619 "@
7620 %q4. %3,%1,%2
7621 #"
7622 [(set_attr "type" "compare")
7623 (set_attr "length" "4,8")])
7624
7625 (define_split
7626 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7627 (compare:CC (match_operator:DI 4 "boolean_operator"
7628 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7629 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7630 (const_int 0)))
7631 (clobber (match_scratch:DI 3 ""))]
7632 "TARGET_POWERPC64 && reload_completed"
7633 [(set (match_dup 3) (match_dup 4))
7634 (set (match_dup 0)
7635 (compare:CC (match_dup 3)
7636 (const_int 0)))]
7637 "")
7638
7639 (define_insn "*boolccdi3_internal3"
7640 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7641 (compare:CC (match_operator:DI 4 "boolean_operator"
7642 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7643 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7644 (const_int 0)))
7645 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7646 (match_dup 4))]
7647 "TARGET_64BIT"
7648 "@
7649 %q4. %0,%1,%2
7650 #"
7651 [(set_attr "type" "compare")
7652 (set_attr "length" "4,8")])
7653
7654 (define_split
7655 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7656 (compare:CC (match_operator:DI 4 "boolean_operator"
7657 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7658 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7659 (const_int 0)))
7660 (set (match_operand:DI 0 "gpc_reg_operand" "")
7661 (match_dup 4))]
7662 "TARGET_POWERPC64 && reload_completed"
7663 [(set (match_dup 0) (match_dup 4))
7664 (set (match_dup 3)
7665 (compare:CC (match_dup 0)
7666 (const_int 0)))]
7667 "")
7668 \f
7669 ;; Now define ways of moving data around.
7670
7671 ;; Set up a register with a value from the GOT table
7672
7673 (define_expand "movsi_got"
7674 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7675 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7676 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7677 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7678 "
7679 {
7680 if (GET_CODE (operands[1]) == CONST)
7681 {
7682 rtx offset = const0_rtx;
7683 HOST_WIDE_INT value;
7684
7685 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7686 value = INTVAL (offset);
7687 if (value != 0)
7688 {
7689 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7690 emit_insn (gen_movsi_got (tmp, operands[1]));
7691 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7692 DONE;
7693 }
7694 }
7695
7696 operands[2] = rs6000_got_register (operands[1]);
7697 }")
7698
7699 (define_insn "*movsi_got_internal"
7700 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7701 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7702 (match_operand:SI 2 "gpc_reg_operand" "b")]
7703 UNSPEC_MOVSI_GOT))]
7704 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7705 "{l|lwz} %0,%a1@got(%2)"
7706 [(set_attr "type" "load")])
7707
7708 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7709 ;; didn't get allocated to a hard register.
7710 (define_split
7711 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7712 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7713 (match_operand:SI 2 "memory_operand" "")]
7714 UNSPEC_MOVSI_GOT))]
7715 "DEFAULT_ABI == ABI_V4
7716 && flag_pic == 1
7717 && (reload_in_progress || reload_completed)"
7718 [(set (match_dup 0) (match_dup 2))
7719 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7720 UNSPEC_MOVSI_GOT))]
7721 "")
7722
7723 ;; For SI, we special-case integers that can't be loaded in one insn. We
7724 ;; do the load 16-bits at a time. We could do this by loading from memory,
7725 ;; and this is even supposed to be faster, but it is simpler not to get
7726 ;; integers in the TOC.
7727 (define_insn "movsi_low"
7728 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7729 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7730 (match_operand 2 "" ""))))]
7731 "TARGET_MACHO && ! TARGET_64BIT"
7732 "{l|lwz} %0,lo16(%2)(%1)"
7733 [(set_attr "type" "load")
7734 (set_attr "length" "4")])
7735
7736 (define_insn "*movsi_internal1"
7737 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7738 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7739 "gpc_reg_operand (operands[0], SImode)
7740 || gpc_reg_operand (operands[1], SImode)"
7741 "@
7742 mr %0,%1
7743 {cal|la} %0,%a1
7744 {l%U1%X1|lwz%U1%X1} %0,%1
7745 {st%U0%X0|stw%U0%X0} %1,%0
7746 {lil|li} %0,%1
7747 {liu|lis} %0,%v1
7748 #
7749 {cal|la} %0,%a1
7750 mf%1 %0
7751 mt%0 %1
7752 mt%0 %1
7753 mt%0 %1
7754 {cror 0,0,0|nop}"
7755 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
7756 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7757
7758 ;; Split a load of a large constant into the appropriate two-insn
7759 ;; sequence.
7760
7761 (define_split
7762 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7763 (match_operand:SI 1 "const_int_operand" ""))]
7764 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7765 && (INTVAL (operands[1]) & 0xffff) != 0"
7766 [(set (match_dup 0)
7767 (match_dup 2))
7768 (set (match_dup 0)
7769 (ior:SI (match_dup 0)
7770 (match_dup 3)))]
7771 "
7772 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7773
7774 if (tem == operands[0])
7775 DONE;
7776 else
7777 FAIL;
7778 }")
7779
7780 (define_insn "*mov<mode>_internal2"
7781 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7782 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
7783 (const_int 0)))
7784 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7785 ""
7786 "@
7787 {cmpi|cmp<wd>i} %2,%0,0
7788 mr. %0,%1
7789 #"
7790 [(set_attr "type" "cmp,compare,cmp")
7791 (set_attr "length" "4,4,8")])
7792
7793 (define_split
7794 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7795 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
7796 (const_int 0)))
7797 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
7798 "reload_completed"
7799 [(set (match_dup 0) (match_dup 1))
7800 (set (match_dup 2)
7801 (compare:CC (match_dup 0)
7802 (const_int 0)))]
7803 "")
7804 \f
7805 (define_insn "*movhi_internal"
7806 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7807 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7808 "gpc_reg_operand (operands[0], HImode)
7809 || gpc_reg_operand (operands[1], HImode)"
7810 "@
7811 mr %0,%1
7812 lhz%U1%X1 %0,%1
7813 sth%U0%X0 %1,%0
7814 {lil|li} %0,%w1
7815 mf%1 %0
7816 mt%0 %1
7817 mt%0 %1
7818 {cror 0,0,0|nop}"
7819 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7820
7821 (define_expand "mov<mode>"
7822 [(set (match_operand:INT 0 "general_operand" "")
7823 (match_operand:INT 1 "any_operand" ""))]
7824 ""
7825 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7826
7827 (define_insn "*movqi_internal"
7828 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7829 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7830 "gpc_reg_operand (operands[0], QImode)
7831 || gpc_reg_operand (operands[1], QImode)"
7832 "@
7833 mr %0,%1
7834 lbz%U1%X1 %0,%1
7835 stb%U0%X0 %1,%0
7836 {lil|li} %0,%1
7837 mf%1 %0
7838 mt%0 %1
7839 mt%0 %1
7840 {cror 0,0,0|nop}"
7841 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7842 \f
7843 ;; Here is how to move condition codes around. When we store CC data in
7844 ;; an integer register or memory, we store just the high-order 4 bits.
7845 ;; This lets us not shift in the most common case of CR0.
7846 (define_expand "movcc"
7847 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7848 (match_operand:CC 1 "nonimmediate_operand" ""))]
7849 ""
7850 "")
7851
7852 (define_insn "*movcc_internal1"
7853 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m")
7854 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))]
7855 "register_operand (operands[0], CCmode)
7856 || register_operand (operands[1], CCmode)"
7857 "@
7858 mcrf %0,%1
7859 mtcrf 128,%1
7860 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7861 mfcr %0%Q1
7862 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7863 mr %0,%1
7864 mf%1 %0
7865 mt%0 %1
7866 mt%0 %1
7867 {l%U1%X1|lwz%U1%X1} %0,%1
7868 {st%U0%U1|stw%U0%U1} %1,%0"
7869 [(set (attr "type")
7870 (cond [(eq_attr "alternative" "0")
7871 (const_string "cr_logical")
7872 (eq_attr "alternative" "1,2")
7873 (const_string "mtcr")
7874 (eq_attr "alternative" "5,7")
7875 (const_string "integer")
7876 (eq_attr "alternative" "6")
7877 (const_string "mfjmpr")
7878 (eq_attr "alternative" "8")
7879 (const_string "mtjmpr")
7880 (eq_attr "alternative" "9")
7881 (const_string "load")
7882 (eq_attr "alternative" "10")
7883 (const_string "store")
7884 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
7885 (const_string "mfcrf")
7886 ]
7887 (const_string "mfcr")))
7888 (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
7889 \f
7890 ;; For floating-point, we normally deal with the floating-point registers
7891 ;; unless -msoft-float is used. The sole exception is that parameter passing
7892 ;; can produce floating-point values in fixed-point registers. Unless the
7893 ;; value is a simple constant or already in memory, we deal with this by
7894 ;; allocating memory and copying the value explicitly via that memory location.
7895 (define_expand "movsf"
7896 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7897 (match_operand:SF 1 "any_operand" ""))]
7898 ""
7899 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7900
7901 (define_split
7902 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7903 (match_operand:SF 1 "const_double_operand" ""))]
7904 "reload_completed
7905 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7906 || (GET_CODE (operands[0]) == SUBREG
7907 && GET_CODE (SUBREG_REG (operands[0])) == REG
7908 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7909 [(set (match_dup 2) (match_dup 3))]
7910 "
7911 {
7912 long l;
7913 REAL_VALUE_TYPE rv;
7914
7915 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7916 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7917
7918 if (! TARGET_POWERPC64)
7919 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7920 else
7921 operands[2] = gen_lowpart (SImode, operands[0]);
7922
7923 operands[3] = gen_int_mode (l, SImode);
7924 }")
7925
7926 (define_insn "*movsf_hardfloat"
7927 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
7928 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
7929 "(gpc_reg_operand (operands[0], SFmode)
7930 || gpc_reg_operand (operands[1], SFmode))
7931 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
7932 "@
7933 mr %0,%1
7934 {l%U1%X1|lwz%U1%X1} %0,%1
7935 {st%U0%X0|stw%U0%X0} %1,%0
7936 fmr %0,%1
7937 lfs%U1%X1 %0,%1
7938 stfs%U0%X0 %1,%0
7939 mt%0 %1
7940 mt%0 %1
7941 mf%1 %0
7942 {cror 0,0,0|nop}
7943 #
7944 #"
7945 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
7946 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
7947
7948 (define_insn "*movsf_softfloat"
7949 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
7950 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
7951 "(gpc_reg_operand (operands[0], SFmode)
7952 || gpc_reg_operand (operands[1], SFmode))
7953 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7954 "@
7955 mr %0,%1
7956 mt%0 %1
7957 mt%0 %1
7958 mf%1 %0
7959 {l%U1%X1|lwz%U1%X1} %0,%1
7960 {st%U0%X0|stw%U0%X0} %1,%0
7961 {lil|li} %0,%1
7962 {liu|lis} %0,%v1
7963 {cal|la} %0,%a1
7964 #
7965 #
7966 {cror 0,0,0|nop}"
7967 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
7968 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
7969
7970 \f
7971 (define_expand "movdf"
7972 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7973 (match_operand:DF 1 "any_operand" ""))]
7974 ""
7975 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
7976
7977 (define_split
7978 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7979 (match_operand:DF 1 "const_int_operand" ""))]
7980 "! TARGET_POWERPC64 && reload_completed
7981 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7982 || (GET_CODE (operands[0]) == SUBREG
7983 && GET_CODE (SUBREG_REG (operands[0])) == REG
7984 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7985 [(set (match_dup 2) (match_dup 4))
7986 (set (match_dup 3) (match_dup 1))]
7987 "
7988 {
7989 int endian = (WORDS_BIG_ENDIAN == 0);
7990 HOST_WIDE_INT value = INTVAL (operands[1]);
7991
7992 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7993 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7994 #if HOST_BITS_PER_WIDE_INT == 32
7995 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7996 #else
7997 operands[4] = GEN_INT (value >> 32);
7998 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7999 #endif
8000 }")
8001
8002 (define_split
8003 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8004 (match_operand:DF 1 "const_double_operand" ""))]
8005 "! TARGET_POWERPC64 && reload_completed
8006 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8007 || (GET_CODE (operands[0]) == SUBREG
8008 && GET_CODE (SUBREG_REG (operands[0])) == REG
8009 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8010 [(set (match_dup 2) (match_dup 4))
8011 (set (match_dup 3) (match_dup 5))]
8012 "
8013 {
8014 int endian = (WORDS_BIG_ENDIAN == 0);
8015 long l[2];
8016 REAL_VALUE_TYPE rv;
8017
8018 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8019 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8020
8021 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8022 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8023 operands[4] = gen_int_mode (l[endian], SImode);
8024 operands[5] = gen_int_mode (l[1 - endian], SImode);
8025 }")
8026
8027 (define_split
8028 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8029 (match_operand:DF 1 "const_double_operand" ""))]
8030 "TARGET_POWERPC64 && reload_completed
8031 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8032 || (GET_CODE (operands[0]) == SUBREG
8033 && GET_CODE (SUBREG_REG (operands[0])) == REG
8034 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8035 [(set (match_dup 2) (match_dup 3))]
8036 "
8037 {
8038 int endian = (WORDS_BIG_ENDIAN == 0);
8039 long l[2];
8040 REAL_VALUE_TYPE rv;
8041 #if HOST_BITS_PER_WIDE_INT >= 64
8042 HOST_WIDE_INT val;
8043 #endif
8044
8045 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8046 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8047
8048 operands[2] = gen_lowpart (DImode, operands[0]);
8049 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8050 #if HOST_BITS_PER_WIDE_INT >= 64
8051 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8052 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8053
8054 operands[3] = gen_int_mode (val, DImode);
8055 #else
8056 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8057 #endif
8058 }")
8059
8060 ;; Don't have reload use general registers to load a constant. First,
8061 ;; it might not work if the output operand is the equivalent of
8062 ;; a non-offsettable memref, but also it is less efficient than loading
8063 ;; the constant into an FP register, since it will probably be used there.
8064 ;; The "??" is a kludge until we can figure out a more reasonable way
8065 ;; of handling these non-offsettable values.
8066 (define_insn "*movdf_hardfloat32"
8067 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8068 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
8069 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8070 && (gpc_reg_operand (operands[0], DFmode)
8071 || gpc_reg_operand (operands[1], DFmode))"
8072 "*
8073 {
8074 switch (which_alternative)
8075 {
8076 default:
8077 gcc_unreachable ();
8078 case 0:
8079 /* We normally copy the low-numbered register first. However, if
8080 the first register operand 0 is the same as the second register
8081 of operand 1, we must copy in the opposite order. */
8082 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8083 return \"mr %L0,%L1\;mr %0,%1\";
8084 else
8085 return \"mr %0,%1\;mr %L0,%L1\";
8086 case 1:
8087 if (GET_CODE (operands[1]) == MEM
8088 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[1], 0),
8089 reload_completed || reload_in_progress)
8090 || rs6000_legitimate_small_data_p (DFmode, XEXP (operands[1], 0))
8091 || GET_CODE (XEXP (operands[1], 0)) == REG
8092 || GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8093 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8094 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))
8095 {
8096 /* If the low-address word is used in the address, we must load
8097 it last. Otherwise, load it first. Note that we cannot have
8098 auto-increment in that case since the address register is
8099 known to be dead. */
8100 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8101 operands[1], 0))
8102 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8103 else
8104 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8105 }
8106 else
8107 {
8108 rtx addreg;
8109
8110 addreg = find_addr_reg (XEXP (operands[1], 0));
8111 if (refers_to_regno_p (REGNO (operands[0]),
8112 REGNO (operands[0]) + 1,
8113 operands[1], 0))
8114 {
8115 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8116 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8117 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8118 return \"{lx|lwzx} %0,%1\";
8119 }
8120 else
8121 {
8122 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
8123 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8124 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8125 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8126 return \"\";
8127 }
8128 }
8129 case 2:
8130 if (GET_CODE (operands[0]) == MEM
8131 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[0], 0),
8132 reload_completed || reload_in_progress)
8133 || rs6000_legitimate_small_data_p (DFmode, XEXP (operands[0], 0))
8134 || GET_CODE (XEXP (operands[0], 0)) == REG
8135 || GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8136 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8137 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))
8138 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8139 else
8140 {
8141 rtx addreg;
8142
8143 addreg = find_addr_reg (XEXP (operands[0], 0));
8144 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
8145 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8146 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
8147 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8148 return \"\";
8149 }
8150 case 3:
8151 return \"fmr %0,%1\";
8152 case 4:
8153 return \"lfd%U1%X1 %0,%1\";
8154 case 5:
8155 return \"stfd%U0%X0 %1,%0\";
8156 case 6:
8157 case 7:
8158 case 8:
8159 return \"#\";
8160 }
8161 }"
8162 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
8163 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
8164
8165 (define_insn "*movdf_softfloat32"
8166 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8167 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8168 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8169 && (gpc_reg_operand (operands[0], DFmode)
8170 || gpc_reg_operand (operands[1], DFmode))"
8171 "*
8172 {
8173 switch (which_alternative)
8174 {
8175 default:
8176 gcc_unreachable ();
8177 case 0:
8178 /* We normally copy the low-numbered register first. However, if
8179 the first register operand 0 is the same as the second register of
8180 operand 1, we must copy in the opposite order. */
8181 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8182 return \"mr %L0,%L1\;mr %0,%1\";
8183 else
8184 return \"mr %0,%1\;mr %L0,%L1\";
8185 case 1:
8186 /* If the low-address word is used in the address, we must load
8187 it last. Otherwise, load it first. Note that we cannot have
8188 auto-increment in that case since the address register is
8189 known to be dead. */
8190 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8191 operands[1], 0))
8192 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8193 else
8194 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8195 case 2:
8196 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8197 case 3:
8198 case 4:
8199 case 5:
8200 return \"#\";
8201 }
8202 }"
8203 [(set_attr "type" "two,load,store,*,*,*")
8204 (set_attr "length" "8,8,8,8,12,16")])
8205
8206 ; ld/std require word-aligned displacements -> 'Y' constraint.
8207 ; List Y->r and r->Y before r->r for reload.
8208 (define_insn "*movdf_hardfloat64"
8209 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
8210 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
8211 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8212 && (gpc_reg_operand (operands[0], DFmode)
8213 || gpc_reg_operand (operands[1], DFmode))"
8214 "@
8215 std%U0%X0 %1,%0
8216 ld%U1%X1 %0,%1
8217 mr %0,%1
8218 fmr %0,%1
8219 lfd%U1%X1 %0,%1
8220 stfd%U0%X0 %1,%0
8221 mt%0 %1
8222 mf%1 %0
8223 {cror 0,0,0|nop}
8224 #
8225 #
8226 #"
8227 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
8228 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
8229
8230 (define_insn "*movdf_softfloat64"
8231 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8232 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
8233 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8234 && (gpc_reg_operand (operands[0], DFmode)
8235 || gpc_reg_operand (operands[1], DFmode))"
8236 "@
8237 ld%U1%X1 %0,%1
8238 std%U0%X0 %1,%0
8239 mr %0,%1
8240 mt%0 %1
8241 mf%1 %0
8242 #
8243 #
8244 #
8245 {cror 0,0,0|nop}"
8246 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
8247 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8248 \f
8249 (define_expand "movtf"
8250 [(set (match_operand:TF 0 "general_operand" "")
8251 (match_operand:TF 1 "any_operand" ""))]
8252 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8253 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8254 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8255
8256 ; It's important to list the o->f and f->o moves before f->f because
8257 ; otherwise reload, given m->f, will try to pick f->f and reload it,
8258 ; which doesn't make progress. Likewise r->Y must be before r->r.
8259 (define_insn_and_split "*movtf_internal"
8260 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
8261 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
8262 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8263 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8264 && (gpc_reg_operand (operands[0], TFmode)
8265 || gpc_reg_operand (operands[1], TFmode))"
8266 "#"
8267 "&& reload_completed"
8268 [(pc)]
8269 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8270 [(set_attr "length" "8,8,8,20,20,16")])
8271
8272 (define_expand "extenddftf2"
8273 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8274 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8275 (use (match_dup 2))])]
8276 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8277 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8278 {
8279 operands[2] = CONST0_RTX (DFmode);
8280 })
8281
8282 (define_insn_and_split "*extenddftf2_internal"
8283 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8284 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8285 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
8286 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8287 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8288 "#"
8289 "&& reload_completed"
8290 [(pc)]
8291 {
8292 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8293 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8294 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8295 operands[1]);
8296 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8297 operands[2]);
8298 DONE;
8299 })
8300
8301 (define_expand "extendsftf2"
8302 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8303 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8304 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8305 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8306 {
8307 rtx tmp = gen_reg_rtx (DFmode);
8308 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8309 emit_insn (gen_extenddftf2 (operands[0], tmp));
8310 DONE;
8311 })
8312
8313 (define_expand "trunctfdf2"
8314 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8315 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8316 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8317 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8318 "")
8319
8320 (define_insn_and_split "trunctfdf2_internal1"
8321 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8322 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
8323 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
8324 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8325 "@
8326 #
8327 fmr %0,%1"
8328 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8329 [(const_int 0)]
8330 {
8331 emit_note (NOTE_INSN_DELETED);
8332 DONE;
8333 }
8334 [(set_attr "type" "fp")])
8335
8336 (define_insn "trunctfdf2_internal2"
8337 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8338 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8339 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
8340 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8341 "fadd %0,%1,%L1"
8342 [(set_attr "type" "fp")])
8343
8344 (define_insn_and_split "trunctfsf2"
8345 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8346 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8347 (clobber (match_scratch:DF 2 "=f"))]
8348 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8349 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8350 "#"
8351 "&& reload_completed"
8352 [(set (match_dup 2)
8353 (float_truncate:DF (match_dup 1)))
8354 (set (match_dup 0)
8355 (float_truncate:SF (match_dup 2)))]
8356 "")
8357
8358 (define_expand "floatsitf2"
8359 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8360 (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))]
8361 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8362 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8363 {
8364 rtx tmp = gen_reg_rtx (DFmode);
8365 expand_float (tmp, operands[1], false);
8366 emit_insn (gen_extenddftf2 (operands[0], tmp));
8367 DONE;
8368 })
8369
8370 ; fadd, but rounding towards zero.
8371 ; This is probably not the optimal code sequence.
8372 (define_insn "fix_trunc_helper"
8373 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8374 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8375 UNSPEC_FIX_TRUNC_TF))
8376 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8377 "TARGET_HARD_FLOAT && TARGET_FPRS"
8378 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8379 [(set_attr "type" "fp")
8380 (set_attr "length" "20")])
8381
8382 (define_expand "fix_trunctfsi2"
8383 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8384 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8385 (clobber (match_dup 2))
8386 (clobber (match_dup 3))
8387 (clobber (match_dup 4))
8388 (clobber (match_dup 5))])]
8389 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8390 && (TARGET_POWER2 || TARGET_POWERPC)
8391 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8392 {
8393 operands[2] = gen_reg_rtx (DFmode);
8394 operands[3] = gen_reg_rtx (DFmode);
8395 operands[4] = gen_reg_rtx (DImode);
8396 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8397 })
8398
8399 (define_insn_and_split "*fix_trunctfsi2_internal"
8400 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8401 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8402 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8403 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8404 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8405 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
8406 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8407 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8408 "#"
8409 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[5]))"
8410 [(pc)]
8411 {
8412 rtx lowword;
8413 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8414
8415 gcc_assert (MEM_P (operands[5]));
8416 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8417
8418 emit_insn (gen_fctiwz (operands[4], operands[2]));
8419 emit_move_insn (operands[5], operands[4]);
8420 emit_move_insn (operands[0], lowword);
8421 DONE;
8422 })
8423
8424 (define_insn "negtf2"
8425 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8426 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8427 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8428 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8429 "*
8430 {
8431 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8432 return \"fneg %L0,%L1\;fneg %0,%1\";
8433 else
8434 return \"fneg %0,%1\;fneg %L0,%L1\";
8435 }"
8436 [(set_attr "type" "fp")
8437 (set_attr "length" "8")])
8438
8439 (define_expand "abstf2"
8440 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8441 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8442 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8443 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8444 "
8445 {
8446 rtx label = gen_label_rtx ();
8447 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8448 emit_label (label);
8449 DONE;
8450 }")
8451
8452 (define_expand "abstf2_internal"
8453 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8454 (match_operand:TF 1 "gpc_reg_operand" "f"))
8455 (set (match_dup 3) (match_dup 5))
8456 (set (match_dup 5) (abs:DF (match_dup 5)))
8457 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8458 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8459 (label_ref (match_operand 2 "" ""))
8460 (pc)))
8461 (set (match_dup 6) (neg:DF (match_dup 6)))]
8462 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8463 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8464 "
8465 {
8466 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8467 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8468 operands[3] = gen_reg_rtx (DFmode);
8469 operands[4] = gen_reg_rtx (CCFPmode);
8470 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8471 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8472 }")
8473 \f
8474 ;; Next come the multi-word integer load and store and the load and store
8475 ;; multiple insns.
8476
8477 ; List r->r after r->"o<>", otherwise reload will try to reload a
8478 ; non-offsettable address by using r->r which won't make progress.
8479 (define_insn "*movdi_internal32"
8480 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
8481 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
8482 "! TARGET_POWERPC64
8483 && (gpc_reg_operand (operands[0], DImode)
8484 || gpc_reg_operand (operands[1], DImode))"
8485 "@
8486 #
8487 #
8488 #
8489 fmr %0,%1
8490 lfd%U1%X1 %0,%1
8491 stfd%U0%X0 %1,%0
8492 #"
8493 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
8494
8495 (define_split
8496 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8497 (match_operand:DI 1 "const_int_operand" ""))]
8498 "! TARGET_POWERPC64 && reload_completed"
8499 [(set (match_dup 2) (match_dup 4))
8500 (set (match_dup 3) (match_dup 1))]
8501 "
8502 {
8503 HOST_WIDE_INT value = INTVAL (operands[1]);
8504 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8505 DImode);
8506 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8507 DImode);
8508 #if HOST_BITS_PER_WIDE_INT == 32
8509 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8510 #else
8511 operands[4] = GEN_INT (value >> 32);
8512 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8513 #endif
8514 }")
8515
8516 (define_split
8517 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8518 (match_operand:DI 1 "input_operand" ""))]
8519 "reload_completed && !TARGET_POWERPC64
8520 && gpr_or_gpr_p (operands[0], operands[1])"
8521 [(pc)]
8522 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8523
8524 (define_insn "*movdi_internal64"
8525 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
8526 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8527 "TARGET_POWERPC64
8528 && (gpc_reg_operand (operands[0], DImode)
8529 || gpc_reg_operand (operands[1], DImode))"
8530 "@
8531 mr %0,%1
8532 ld%U1%X1 %0,%1
8533 std%U0%X0 %1,%0
8534 li %0,%1
8535 lis %0,%v1
8536 #
8537 {cal|la} %0,%a1
8538 fmr %0,%1
8539 lfd%U1%X1 %0,%1
8540 stfd%U0%X0 %1,%0
8541 mf%1 %0
8542 mt%0 %1
8543 {cror 0,0,0|nop}"
8544 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
8545 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8546
8547 ;; immediate value valid for a single instruction hiding in a const_double
8548 (define_insn ""
8549 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8550 (match_operand:DI 1 "const_double_operand" "F"))]
8551 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8552 && GET_CODE (operands[1]) == CONST_DOUBLE
8553 && num_insns_constant (operands[1], DImode) == 1"
8554 "*
8555 {
8556 return ((unsigned HOST_WIDE_INT)
8557 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8558 ? \"li %0,%1\" : \"lis %0,%v1\";
8559 }")
8560
8561 ;; Generate all one-bits and clear left or right.
8562 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8563 (define_split
8564 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8565 (match_operand:DI 1 "mask64_operand" ""))]
8566 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8567 [(set (match_dup 0) (const_int -1))
8568 (set (match_dup 0)
8569 (and:DI (rotate:DI (match_dup 0)
8570 (const_int 0))
8571 (match_dup 1)))]
8572 "")
8573
8574 ;; Split a load of a large constant into the appropriate five-instruction
8575 ;; sequence. Handle anything in a constant number of insns.
8576 ;; When non-easy constants can go in the TOC, this should use
8577 ;; easy_fp_constant predicate.
8578 (define_split
8579 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8580 (match_operand:DI 1 "const_int_operand" ""))]
8581 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8582 [(set (match_dup 0) (match_dup 2))
8583 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8584 "
8585 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8586
8587 if (tem == operands[0])
8588 DONE;
8589 else
8590 FAIL;
8591 }")
8592
8593 (define_split
8594 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8595 (match_operand:DI 1 "const_double_operand" ""))]
8596 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8597 [(set (match_dup 0) (match_dup 2))
8598 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8599 "
8600 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8601
8602 if (tem == operands[0])
8603 DONE;
8604 else
8605 FAIL;
8606 }")
8607 \f
8608 ;; TImode is similar, except that we usually want to compute the address into
8609 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8610 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8611
8612 ;; We say that MQ is clobbered in the last alternative because the first
8613 ;; alternative would never get used otherwise since it would need a reload
8614 ;; while the 2nd alternative would not. We put memory cases first so they
8615 ;; are preferred. Otherwise, we'd try to reload the output instead of
8616 ;; giving the SCRATCH mq.
8617
8618 (define_insn "*movti_power"
8619 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
8620 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
8621 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
8622 "TARGET_POWER && ! TARGET_POWERPC64
8623 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8624 "*
8625 {
8626 switch (which_alternative)
8627 {
8628 default:
8629 gcc_unreachable ();
8630
8631 case 0:
8632 if (TARGET_STRING)
8633 return \"{stsi|stswi} %1,%P0,16\";
8634 case 1:
8635 case 2:
8636 return \"#\";
8637 case 3:
8638 /* If the address is not used in the output, we can use lsi. Otherwise,
8639 fall through to generating four loads. */
8640 if (TARGET_STRING
8641 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8642 return \"{lsi|lswi} %0,%P1,16\";
8643 /* ... fall through ... */
8644 case 4:
8645 case 5:
8646 return \"#\";
8647 }
8648 }"
8649 [(set_attr "type" "store,store,*,load,load,*")])
8650
8651 (define_insn "*movti_string"
8652 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
8653 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
8654 "! TARGET_POWER && ! TARGET_POWERPC64
8655 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8656 "*
8657 {
8658 switch (which_alternative)
8659 {
8660 default:
8661 gcc_unreachable ();
8662 case 0:
8663 if (TARGET_STRING)
8664 return \"{stsi|stswi} %1,%P0,16\";
8665 case 1:
8666 case 2:
8667 return \"#\";
8668 case 3:
8669 /* If the address is not used in the output, we can use lsi. Otherwise,
8670 fall through to generating four loads. */
8671 if (TARGET_STRING
8672 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8673 return \"{lsi|lswi} %0,%P1,16\";
8674 /* ... fall through ... */
8675 case 4:
8676 case 5:
8677 return \"#\";
8678 }
8679 }"
8680 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")])
8681
8682 (define_insn "*movti_ppc64"
8683 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
8684 (match_operand:TI 1 "input_operand" "r,r,m"))]
8685 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8686 || gpc_reg_operand (operands[1], TImode))"
8687 "#"
8688 [(set_attr "type" "*,load,store")])
8689
8690 (define_split
8691 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8692 (match_operand:TI 1 "const_double_operand" ""))]
8693 "TARGET_POWERPC64"
8694 [(set (match_dup 2) (match_dup 4))
8695 (set (match_dup 3) (match_dup 5))]
8696 "
8697 {
8698 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8699 TImode);
8700 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8701 TImode);
8702 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8703 {
8704 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8705 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8706 }
8707 else if (GET_CODE (operands[1]) == CONST_INT)
8708 {
8709 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8710 operands[5] = operands[1];
8711 }
8712 else
8713 FAIL;
8714 }")
8715
8716 (define_split
8717 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8718 (match_operand:TI 1 "input_operand" ""))]
8719 "reload_completed
8720 && gpr_or_gpr_p (operands[0], operands[1])"
8721 [(pc)]
8722 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8723 \f
8724 (define_expand "load_multiple"
8725 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8726 (match_operand:SI 1 "" ""))
8727 (use (match_operand:SI 2 "" ""))])]
8728 "TARGET_STRING && !TARGET_POWERPC64"
8729 "
8730 {
8731 int regno;
8732 int count;
8733 rtx op1;
8734 int i;
8735
8736 /* Support only loading a constant number of fixed-point registers from
8737 memory and only bother with this if more than two; the machine
8738 doesn't support more than eight. */
8739 if (GET_CODE (operands[2]) != CONST_INT
8740 || INTVAL (operands[2]) <= 2
8741 || INTVAL (operands[2]) > 8
8742 || GET_CODE (operands[1]) != MEM
8743 || GET_CODE (operands[0]) != REG
8744 || REGNO (operands[0]) >= 32)
8745 FAIL;
8746
8747 count = INTVAL (operands[2]);
8748 regno = REGNO (operands[0]);
8749
8750 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8751 op1 = replace_equiv_address (operands[1],
8752 force_reg (SImode, XEXP (operands[1], 0)));
8753
8754 for (i = 0; i < count; i++)
8755 XVECEXP (operands[3], 0, i)
8756 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8757 adjust_address_nv (op1, SImode, i * 4));
8758 }")
8759
8760 (define_insn "*ldmsi8"
8761 [(match_parallel 0 "load_multiple_operation"
8762 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8763 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8764 (set (match_operand:SI 3 "gpc_reg_operand" "")
8765 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8766 (set (match_operand:SI 4 "gpc_reg_operand" "")
8767 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8768 (set (match_operand:SI 5 "gpc_reg_operand" "")
8769 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8770 (set (match_operand:SI 6 "gpc_reg_operand" "")
8771 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8772 (set (match_operand:SI 7 "gpc_reg_operand" "")
8773 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8774 (set (match_operand:SI 8 "gpc_reg_operand" "")
8775 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8776 (set (match_operand:SI 9 "gpc_reg_operand" "")
8777 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8778 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8779 "*
8780 { return rs6000_output_load_multiple (operands); }"
8781 [(set_attr "type" "load_ux")
8782 (set_attr "length" "32")])
8783
8784 (define_insn "*ldmsi7"
8785 [(match_parallel 0 "load_multiple_operation"
8786 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8787 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8788 (set (match_operand:SI 3 "gpc_reg_operand" "")
8789 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8790 (set (match_operand:SI 4 "gpc_reg_operand" "")
8791 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8792 (set (match_operand:SI 5 "gpc_reg_operand" "")
8793 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8794 (set (match_operand:SI 6 "gpc_reg_operand" "")
8795 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8796 (set (match_operand:SI 7 "gpc_reg_operand" "")
8797 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8798 (set (match_operand:SI 8 "gpc_reg_operand" "")
8799 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8800 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8801 "*
8802 { return rs6000_output_load_multiple (operands); }"
8803 [(set_attr "type" "load_ux")
8804 (set_attr "length" "32")])
8805
8806 (define_insn "*ldmsi6"
8807 [(match_parallel 0 "load_multiple_operation"
8808 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8809 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8810 (set (match_operand:SI 3 "gpc_reg_operand" "")
8811 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8812 (set (match_operand:SI 4 "gpc_reg_operand" "")
8813 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8814 (set (match_operand:SI 5 "gpc_reg_operand" "")
8815 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8816 (set (match_operand:SI 6 "gpc_reg_operand" "")
8817 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8818 (set (match_operand:SI 7 "gpc_reg_operand" "")
8819 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8820 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8821 "*
8822 { return rs6000_output_load_multiple (operands); }"
8823 [(set_attr "type" "load_ux")
8824 (set_attr "length" "32")])
8825
8826 (define_insn "*ldmsi5"
8827 [(match_parallel 0 "load_multiple_operation"
8828 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8829 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8830 (set (match_operand:SI 3 "gpc_reg_operand" "")
8831 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8832 (set (match_operand:SI 4 "gpc_reg_operand" "")
8833 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8834 (set (match_operand:SI 5 "gpc_reg_operand" "")
8835 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8836 (set (match_operand:SI 6 "gpc_reg_operand" "")
8837 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8838 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8839 "*
8840 { return rs6000_output_load_multiple (operands); }"
8841 [(set_attr "type" "load_ux")
8842 (set_attr "length" "32")])
8843
8844 (define_insn "*ldmsi4"
8845 [(match_parallel 0 "load_multiple_operation"
8846 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8847 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8848 (set (match_operand:SI 3 "gpc_reg_operand" "")
8849 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8850 (set (match_operand:SI 4 "gpc_reg_operand" "")
8851 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8852 (set (match_operand:SI 5 "gpc_reg_operand" "")
8853 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8854 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8855 "*
8856 { return rs6000_output_load_multiple (operands); }"
8857 [(set_attr "type" "load_ux")
8858 (set_attr "length" "32")])
8859
8860 (define_insn "*ldmsi3"
8861 [(match_parallel 0 "load_multiple_operation"
8862 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8863 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8864 (set (match_operand:SI 3 "gpc_reg_operand" "")
8865 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8866 (set (match_operand:SI 4 "gpc_reg_operand" "")
8867 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8868 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8869 "*
8870 { return rs6000_output_load_multiple (operands); }"
8871 [(set_attr "type" "load_ux")
8872 (set_attr "length" "32")])
8873
8874 (define_expand "store_multiple"
8875 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8876 (match_operand:SI 1 "" ""))
8877 (clobber (scratch:SI))
8878 (use (match_operand:SI 2 "" ""))])]
8879 "TARGET_STRING && !TARGET_POWERPC64"
8880 "
8881 {
8882 int regno;
8883 int count;
8884 rtx to;
8885 rtx op0;
8886 int i;
8887
8888 /* Support only storing a constant number of fixed-point registers to
8889 memory and only bother with this if more than two; the machine
8890 doesn't support more than eight. */
8891 if (GET_CODE (operands[2]) != CONST_INT
8892 || INTVAL (operands[2]) <= 2
8893 || INTVAL (operands[2]) > 8
8894 || GET_CODE (operands[0]) != MEM
8895 || GET_CODE (operands[1]) != REG
8896 || REGNO (operands[1]) >= 32)
8897 FAIL;
8898
8899 count = INTVAL (operands[2]);
8900 regno = REGNO (operands[1]);
8901
8902 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8903 to = force_reg (SImode, XEXP (operands[0], 0));
8904 op0 = replace_equiv_address (operands[0], to);
8905
8906 XVECEXP (operands[3], 0, 0)
8907 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
8908 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8909 gen_rtx_SCRATCH (SImode));
8910
8911 for (i = 1; i < count; i++)
8912 XVECEXP (operands[3], 0, i + 1)
8913 = gen_rtx_SET (VOIDmode,
8914 adjust_address_nv (op0, SImode, i * 4),
8915 gen_rtx_REG (SImode, regno + i));
8916 }")
8917
8918 (define_insn "*store_multiple_power"
8919 [(match_parallel 0 "store_multiple_operation"
8920 [(set (match_operand:SI 1 "indirect_operand" "=Q")
8921 (match_operand:SI 2 "gpc_reg_operand" "r"))
8922 (clobber (match_scratch:SI 3 "=q"))])]
8923 "TARGET_STRING && TARGET_POWER"
8924 "{stsi|stswi} %2,%P1,%O0"
8925 [(set_attr "type" "store")])
8926
8927 (define_insn "*stmsi8"
8928 [(match_parallel 0 "store_multiple_operation"
8929 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8930 (match_operand:SI 2 "gpc_reg_operand" "r"))
8931 (clobber (match_scratch:SI 3 "X"))
8932 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8933 (match_operand:SI 4 "gpc_reg_operand" "r"))
8934 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8935 (match_operand:SI 5 "gpc_reg_operand" "r"))
8936 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8937 (match_operand:SI 6 "gpc_reg_operand" "r"))
8938 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8939 (match_operand:SI 7 "gpc_reg_operand" "r"))
8940 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8941 (match_operand:SI 8 "gpc_reg_operand" "r"))
8942 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8943 (match_operand:SI 9 "gpc_reg_operand" "r"))
8944 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
8945 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
8946 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
8947 "{stsi|stswi} %2,%1,%O0"
8948 [(set_attr "type" "store_ux")])
8949
8950 (define_insn "*stmsi7"
8951 [(match_parallel 0 "store_multiple_operation"
8952 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8953 (match_operand:SI 2 "gpc_reg_operand" "r"))
8954 (clobber (match_scratch:SI 3 "X"))
8955 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8956 (match_operand:SI 4 "gpc_reg_operand" "r"))
8957 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8958 (match_operand:SI 5 "gpc_reg_operand" "r"))
8959 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8960 (match_operand:SI 6 "gpc_reg_operand" "r"))
8961 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8962 (match_operand:SI 7 "gpc_reg_operand" "r"))
8963 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8964 (match_operand:SI 8 "gpc_reg_operand" "r"))
8965 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8966 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
8967 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
8968 "{stsi|stswi} %2,%1,%O0"
8969 [(set_attr "type" "store_ux")])
8970
8971 (define_insn "*stmsi6"
8972 [(match_parallel 0 "store_multiple_operation"
8973 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8974 (match_operand:SI 2 "gpc_reg_operand" "r"))
8975 (clobber (match_scratch:SI 3 "X"))
8976 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8977 (match_operand:SI 4 "gpc_reg_operand" "r"))
8978 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8979 (match_operand:SI 5 "gpc_reg_operand" "r"))
8980 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8981 (match_operand:SI 6 "gpc_reg_operand" "r"))
8982 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8983 (match_operand:SI 7 "gpc_reg_operand" "r"))
8984 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8985 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
8986 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
8987 "{stsi|stswi} %2,%1,%O0"
8988 [(set_attr "type" "store_ux")])
8989
8990 (define_insn "*stmsi5"
8991 [(match_parallel 0 "store_multiple_operation"
8992 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8993 (match_operand:SI 2 "gpc_reg_operand" "r"))
8994 (clobber (match_scratch:SI 3 "X"))
8995 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8996 (match_operand:SI 4 "gpc_reg_operand" "r"))
8997 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8998 (match_operand:SI 5 "gpc_reg_operand" "r"))
8999 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9000 (match_operand:SI 6 "gpc_reg_operand" "r"))
9001 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9002 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9003 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9004 "{stsi|stswi} %2,%1,%O0"
9005 [(set_attr "type" "store_ux")])
9006
9007 (define_insn "*stmsi4"
9008 [(match_parallel 0 "store_multiple_operation"
9009 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9010 (match_operand:SI 2 "gpc_reg_operand" "r"))
9011 (clobber (match_scratch:SI 3 "X"))
9012 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9013 (match_operand:SI 4 "gpc_reg_operand" "r"))
9014 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9015 (match_operand:SI 5 "gpc_reg_operand" "r"))
9016 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9017 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9018 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9019 "{stsi|stswi} %2,%1,%O0"
9020 [(set_attr "type" "store_ux")])
9021
9022 (define_insn "*stmsi3"
9023 [(match_parallel 0 "store_multiple_operation"
9024 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9025 (match_operand:SI 2 "gpc_reg_operand" "r"))
9026 (clobber (match_scratch:SI 3 "X"))
9027 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9028 (match_operand:SI 4 "gpc_reg_operand" "r"))
9029 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9030 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9031 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9032 "{stsi|stswi} %2,%1,%O0"
9033 [(set_attr "type" "store_ux")])
9034 \f
9035 (define_expand "setmemsi"
9036 [(parallel [(set (match_operand:BLK 0 "" "")
9037 (match_operand 2 "const_int_operand" ""))
9038 (use (match_operand:SI 1 "" ""))
9039 (use (match_operand:SI 3 "" ""))])]
9040 ""
9041 "
9042 {
9043 /* If value to set is not zero, use the library routine. */
9044 if (operands[2] != const0_rtx)
9045 FAIL;
9046
9047 if (expand_block_clear (operands))
9048 DONE;
9049 else
9050 FAIL;
9051 }")
9052
9053 ;; String/block move insn.
9054 ;; Argument 0 is the destination
9055 ;; Argument 1 is the source
9056 ;; Argument 2 is the length
9057 ;; Argument 3 is the alignment
9058
9059 (define_expand "movmemsi"
9060 [(parallel [(set (match_operand:BLK 0 "" "")
9061 (match_operand:BLK 1 "" ""))
9062 (use (match_operand:SI 2 "" ""))
9063 (use (match_operand:SI 3 "" ""))])]
9064 ""
9065 "
9066 {
9067 if (expand_block_move (operands))
9068 DONE;
9069 else
9070 FAIL;
9071 }")
9072
9073 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9074 ;; register allocator doesn't have a clue about allocating 8 word registers.
9075 ;; rD/rS = r5 is preferred, efficient form.
9076 (define_expand "movmemsi_8reg"
9077 [(parallel [(set (match_operand 0 "" "")
9078 (match_operand 1 "" ""))
9079 (use (match_operand 2 "" ""))
9080 (use (match_operand 3 "" ""))
9081 (clobber (reg:SI 5))
9082 (clobber (reg:SI 6))
9083 (clobber (reg:SI 7))
9084 (clobber (reg:SI 8))
9085 (clobber (reg:SI 9))
9086 (clobber (reg:SI 10))
9087 (clobber (reg:SI 11))
9088 (clobber (reg:SI 12))
9089 (clobber (match_scratch:SI 4 ""))])]
9090 "TARGET_STRING"
9091 "")
9092
9093 (define_insn ""
9094 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9095 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9096 (use (match_operand:SI 2 "immediate_operand" "i"))
9097 (use (match_operand:SI 3 "immediate_operand" "i"))
9098 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9099 (clobber (reg:SI 6))
9100 (clobber (reg:SI 7))
9101 (clobber (reg:SI 8))
9102 (clobber (reg:SI 9))
9103 (clobber (reg:SI 10))
9104 (clobber (reg:SI 11))
9105 (clobber (reg:SI 12))
9106 (clobber (match_scratch:SI 5 "=q"))]
9107 "TARGET_STRING && TARGET_POWER
9108 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9109 || INTVAL (operands[2]) == 0)
9110 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9111 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9112 && REGNO (operands[4]) == 5"
9113 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9114 [(set_attr "type" "store_ux")
9115 (set_attr "length" "8")])
9116
9117 (define_insn ""
9118 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9119 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9120 (use (match_operand:SI 2 "immediate_operand" "i"))
9121 (use (match_operand:SI 3 "immediate_operand" "i"))
9122 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9123 (clobber (reg:SI 6))
9124 (clobber (reg:SI 7))
9125 (clobber (reg:SI 8))
9126 (clobber (reg:SI 9))
9127 (clobber (reg:SI 10))
9128 (clobber (reg:SI 11))
9129 (clobber (reg:SI 12))
9130 (clobber (match_scratch:SI 5 "X"))]
9131 "TARGET_STRING && ! TARGET_POWER
9132 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9133 || INTVAL (operands[2]) == 0)
9134 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9135 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9136 && REGNO (operands[4]) == 5"
9137 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9138 [(set_attr "type" "store_ux")
9139 (set_attr "length" "8")])
9140
9141 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9142 ;; register allocator doesn't have a clue about allocating 6 word registers.
9143 ;; rD/rS = r5 is preferred, efficient form.
9144 (define_expand "movmemsi_6reg"
9145 [(parallel [(set (match_operand 0 "" "")
9146 (match_operand 1 "" ""))
9147 (use (match_operand 2 "" ""))
9148 (use (match_operand 3 "" ""))
9149 (clobber (reg:SI 5))
9150 (clobber (reg:SI 6))
9151 (clobber (reg:SI 7))
9152 (clobber (reg:SI 8))
9153 (clobber (reg:SI 9))
9154 (clobber (reg:SI 10))
9155 (clobber (match_scratch:SI 4 ""))])]
9156 "TARGET_STRING"
9157 "")
9158
9159 (define_insn ""
9160 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9161 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9162 (use (match_operand:SI 2 "immediate_operand" "i"))
9163 (use (match_operand:SI 3 "immediate_operand" "i"))
9164 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9165 (clobber (reg:SI 6))
9166 (clobber (reg:SI 7))
9167 (clobber (reg:SI 8))
9168 (clobber (reg:SI 9))
9169 (clobber (reg:SI 10))
9170 (clobber (match_scratch:SI 5 "=q"))]
9171 "TARGET_STRING && TARGET_POWER
9172 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9173 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9174 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9175 && REGNO (operands[4]) == 5"
9176 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9177 [(set_attr "type" "store_ux")
9178 (set_attr "length" "8")])
9179
9180 (define_insn ""
9181 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9182 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9183 (use (match_operand:SI 2 "immediate_operand" "i"))
9184 (use (match_operand:SI 3 "immediate_operand" "i"))
9185 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9186 (clobber (reg:SI 6))
9187 (clobber (reg:SI 7))
9188 (clobber (reg:SI 8))
9189 (clobber (reg:SI 9))
9190 (clobber (reg:SI 10))
9191 (clobber (match_scratch:SI 5 "X"))]
9192 "TARGET_STRING && ! TARGET_POWER
9193 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9194 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9195 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9196 && REGNO (operands[4]) == 5"
9197 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9198 [(set_attr "type" "store_ux")
9199 (set_attr "length" "8")])
9200
9201 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9202 ;; problems with TImode.
9203 ;; rD/rS = r5 is preferred, efficient form.
9204 (define_expand "movmemsi_4reg"
9205 [(parallel [(set (match_operand 0 "" "")
9206 (match_operand 1 "" ""))
9207 (use (match_operand 2 "" ""))
9208 (use (match_operand 3 "" ""))
9209 (clobber (reg:SI 5))
9210 (clobber (reg:SI 6))
9211 (clobber (reg:SI 7))
9212 (clobber (reg:SI 8))
9213 (clobber (match_scratch:SI 4 ""))])]
9214 "TARGET_STRING"
9215 "")
9216
9217 (define_insn ""
9218 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9219 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9220 (use (match_operand:SI 2 "immediate_operand" "i"))
9221 (use (match_operand:SI 3 "immediate_operand" "i"))
9222 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9223 (clobber (reg:SI 6))
9224 (clobber (reg:SI 7))
9225 (clobber (reg:SI 8))
9226 (clobber (match_scratch:SI 5 "=q"))]
9227 "TARGET_STRING && TARGET_POWER
9228 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9229 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9230 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9231 && REGNO (operands[4]) == 5"
9232 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9233 [(set_attr "type" "store_ux")
9234 (set_attr "length" "8")])
9235
9236 (define_insn ""
9237 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9238 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9239 (use (match_operand:SI 2 "immediate_operand" "i"))
9240 (use (match_operand:SI 3 "immediate_operand" "i"))
9241 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9242 (clobber (reg:SI 6))
9243 (clobber (reg:SI 7))
9244 (clobber (reg:SI 8))
9245 (clobber (match_scratch:SI 5 "X"))]
9246 "TARGET_STRING && ! TARGET_POWER
9247 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9248 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9249 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9250 && REGNO (operands[4]) == 5"
9251 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9252 [(set_attr "type" "store_ux")
9253 (set_attr "length" "8")])
9254
9255 ;; Move up to 8 bytes at a time.
9256 (define_expand "movmemsi_2reg"
9257 [(parallel [(set (match_operand 0 "" "")
9258 (match_operand 1 "" ""))
9259 (use (match_operand 2 "" ""))
9260 (use (match_operand 3 "" ""))
9261 (clobber (match_scratch:DI 4 ""))
9262 (clobber (match_scratch:SI 5 ""))])]
9263 "TARGET_STRING && ! TARGET_POWERPC64"
9264 "")
9265
9266 (define_insn ""
9267 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9268 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9269 (use (match_operand:SI 2 "immediate_operand" "i"))
9270 (use (match_operand:SI 3 "immediate_operand" "i"))
9271 (clobber (match_scratch:DI 4 "=&r"))
9272 (clobber (match_scratch:SI 5 "=q"))]
9273 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9274 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9275 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9276 [(set_attr "type" "store_ux")
9277 (set_attr "length" "8")])
9278
9279 (define_insn ""
9280 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9281 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9282 (use (match_operand:SI 2 "immediate_operand" "i"))
9283 (use (match_operand:SI 3 "immediate_operand" "i"))
9284 (clobber (match_scratch:DI 4 "=&r"))
9285 (clobber (match_scratch:SI 5 "X"))]
9286 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9287 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9288 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9289 [(set_attr "type" "store_ux")
9290 (set_attr "length" "8")])
9291
9292 ;; Move up to 4 bytes at a time.
9293 (define_expand "movmemsi_1reg"
9294 [(parallel [(set (match_operand 0 "" "")
9295 (match_operand 1 "" ""))
9296 (use (match_operand 2 "" ""))
9297 (use (match_operand 3 "" ""))
9298 (clobber (match_scratch:SI 4 ""))
9299 (clobber (match_scratch:SI 5 ""))])]
9300 "TARGET_STRING"
9301 "")
9302
9303 (define_insn ""
9304 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9305 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9306 (use (match_operand:SI 2 "immediate_operand" "i"))
9307 (use (match_operand:SI 3 "immediate_operand" "i"))
9308 (clobber (match_scratch:SI 4 "=&r"))
9309 (clobber (match_scratch:SI 5 "=q"))]
9310 "TARGET_STRING && TARGET_POWER
9311 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9312 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9313 [(set_attr "type" "store_ux")
9314 (set_attr "length" "8")])
9315
9316 (define_insn ""
9317 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9318 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9319 (use (match_operand:SI 2 "immediate_operand" "i"))
9320 (use (match_operand:SI 3 "immediate_operand" "i"))
9321 (clobber (match_scratch:SI 4 "=&r"))
9322 (clobber (match_scratch:SI 5 "X"))]
9323 "TARGET_STRING && ! TARGET_POWER
9324 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9325 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9326 [(set_attr "type" "store_ux")
9327 (set_attr "length" "8")])
9328 \f
9329 ;; Define insns that do load or store with update. Some of these we can
9330 ;; get by using pre-decrement or pre-increment, but the hardware can also
9331 ;; do cases where the increment is not the size of the object.
9332 ;;
9333 ;; In all these cases, we use operands 0 and 1 for the register being
9334 ;; incremented because those are the operands that local-alloc will
9335 ;; tie and these are the pair most likely to be tieable (and the ones
9336 ;; that will benefit the most).
9337
9338 (define_insn "*movdi_update1"
9339 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9340 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9341 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9342 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9343 (plus:DI (match_dup 1) (match_dup 2)))]
9344 "TARGET_POWERPC64 && TARGET_UPDATE"
9345 "@
9346 ldux %3,%0,%2
9347 ldu %3,%2(%0)"
9348 [(set_attr "type" "load_ux,load_u")])
9349
9350 (define_insn "movdi_<mode>_update"
9351 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9352 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9353 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9354 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9355 (plus:P (match_dup 1) (match_dup 2)))]
9356 "TARGET_POWERPC64 && TARGET_UPDATE"
9357 "@
9358 stdux %3,%0,%2
9359 stdu %3,%2(%0)"
9360 [(set_attr "type" "store_ux,store_u")])
9361
9362 (define_insn "*movsi_update1"
9363 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9364 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9365 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9366 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9367 (plus:SI (match_dup 1) (match_dup 2)))]
9368 "TARGET_UPDATE"
9369 "@
9370 {lux|lwzux} %3,%0,%2
9371 {lu|lwzu} %3,%2(%0)"
9372 [(set_attr "type" "load_ux,load_u")])
9373
9374 (define_insn "*movsi_update2"
9375 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9376 (sign_extend:DI
9377 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9378 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9379 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9380 (plus:DI (match_dup 1) (match_dup 2)))]
9381 "TARGET_POWERPC64"
9382 "lwaux %3,%0,%2"
9383 [(set_attr "type" "load_ext_ux")])
9384
9385 (define_insn "movsi_update"
9386 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9387 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9388 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9389 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9390 (plus:SI (match_dup 1) (match_dup 2)))]
9391 "TARGET_UPDATE"
9392 "@
9393 {stux|stwux} %3,%0,%2
9394 {stu|stwu} %3,%2(%0)"
9395 [(set_attr "type" "store_ux,store_u")])
9396
9397 (define_insn "*movhi_update1"
9398 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9399 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9400 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9401 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9402 (plus:SI (match_dup 1) (match_dup 2)))]
9403 "TARGET_UPDATE"
9404 "@
9405 lhzux %3,%0,%2
9406 lhzu %3,%2(%0)"
9407 [(set_attr "type" "load_ux,load_u")])
9408
9409 (define_insn "*movhi_update2"
9410 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9411 (zero_extend:SI
9412 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9413 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9414 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9415 (plus:SI (match_dup 1) (match_dup 2)))]
9416 "TARGET_UPDATE"
9417 "@
9418 lhzux %3,%0,%2
9419 lhzu %3,%2(%0)"
9420 [(set_attr "type" "load_ux,load_u")])
9421
9422 (define_insn "*movhi_update3"
9423 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9424 (sign_extend:SI
9425 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9426 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9427 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9428 (plus:SI (match_dup 1) (match_dup 2)))]
9429 "TARGET_UPDATE"
9430 "@
9431 lhaux %3,%0,%2
9432 lhau %3,%2(%0)"
9433 [(set_attr "type" "load_ext_ux,load_ext_u")])
9434
9435 (define_insn "*movhi_update4"
9436 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9437 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9438 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9439 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9440 (plus:SI (match_dup 1) (match_dup 2)))]
9441 "TARGET_UPDATE"
9442 "@
9443 sthux %3,%0,%2
9444 sthu %3,%2(%0)"
9445 [(set_attr "type" "store_ux,store_u")])
9446
9447 (define_insn "*movqi_update1"
9448 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9449 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9450 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9451 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9452 (plus:SI (match_dup 1) (match_dup 2)))]
9453 "TARGET_UPDATE"
9454 "@
9455 lbzux %3,%0,%2
9456 lbzu %3,%2(%0)"
9457 [(set_attr "type" "load_ux,load_u")])
9458
9459 (define_insn "*movqi_update2"
9460 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9461 (zero_extend:SI
9462 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9463 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9464 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9465 (plus:SI (match_dup 1) (match_dup 2)))]
9466 "TARGET_UPDATE"
9467 "@
9468 lbzux %3,%0,%2
9469 lbzu %3,%2(%0)"
9470 [(set_attr "type" "load_ux,load_u")])
9471
9472 (define_insn "*movqi_update3"
9473 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9474 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9475 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9476 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9477 (plus:SI (match_dup 1) (match_dup 2)))]
9478 "TARGET_UPDATE"
9479 "@
9480 stbux %3,%0,%2
9481 stbu %3,%2(%0)"
9482 [(set_attr "type" "store_ux,store_u")])
9483
9484 (define_insn "*movsf_update1"
9485 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9486 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9487 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9488 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9489 (plus:SI (match_dup 1) (match_dup 2)))]
9490 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9491 "@
9492 lfsux %3,%0,%2
9493 lfsu %3,%2(%0)"
9494 [(set_attr "type" "fpload_ux,fpload_u")])
9495
9496 (define_insn "*movsf_update2"
9497 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9498 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9499 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9500 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9501 (plus:SI (match_dup 1) (match_dup 2)))]
9502 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9503 "@
9504 stfsux %3,%0,%2
9505 stfsu %3,%2(%0)"
9506 [(set_attr "type" "fpstore_ux,fpstore_u")])
9507
9508 (define_insn "*movsf_update3"
9509 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9510 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9511 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9512 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9513 (plus:SI (match_dup 1) (match_dup 2)))]
9514 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9515 "@
9516 {lux|lwzux} %3,%0,%2
9517 {lu|lwzu} %3,%2(%0)"
9518 [(set_attr "type" "load_ux,load_u")])
9519
9520 (define_insn "*movsf_update4"
9521 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9522 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9523 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9524 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9525 (plus:SI (match_dup 1) (match_dup 2)))]
9526 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9527 "@
9528 {stux|stwux} %3,%0,%2
9529 {stu|stwu} %3,%2(%0)"
9530 [(set_attr "type" "store_ux,store_u")])
9531
9532 (define_insn "*movdf_update1"
9533 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9534 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9535 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9536 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9537 (plus:SI (match_dup 1) (match_dup 2)))]
9538 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9539 "@
9540 lfdux %3,%0,%2
9541 lfdu %3,%2(%0)"
9542 [(set_attr "type" "fpload_ux,fpload_u")])
9543
9544 (define_insn "*movdf_update2"
9545 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9546 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9547 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9548 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9549 (plus:SI (match_dup 1) (match_dup 2)))]
9550 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9551 "@
9552 stfdux %3,%0,%2
9553 stfdu %3,%2(%0)"
9554 [(set_attr "type" "fpstore_ux,fpstore_u")])
9555
9556 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9557
9558 (define_insn "*lfq_power2"
9559 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
9560 (match_operand:V2DF 1 "memory_operand" ""))]
9561 "TARGET_POWER2
9562 && TARGET_HARD_FLOAT && TARGET_FPRS"
9563 "lfq%U1%X1 %0,%1")
9564
9565 (define_peephole2
9566 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9567 (match_operand:DF 1 "memory_operand" ""))
9568 (set (match_operand:DF 2 "gpc_reg_operand" "")
9569 (match_operand:DF 3 "memory_operand" ""))]
9570 "TARGET_POWER2
9571 && TARGET_HARD_FLOAT && TARGET_FPRS
9572 && registers_ok_for_quad_peep (operands[0], operands[2])
9573 && mems_ok_for_quad_peep (operands[1], operands[3])"
9574 [(set (match_dup 0)
9575 (match_dup 1))]
9576 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
9577 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
9578
9579 (define_insn "*stfq_power2"
9580 [(set (match_operand:V2DF 0 "memory_operand" "")
9581 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
9582 "TARGET_POWER2
9583 && TARGET_HARD_FLOAT && TARGET_FPRS"
9584 "stfq%U0%X0 %1,%0")
9585
9586
9587 (define_peephole2
9588 [(set (match_operand:DF 0 "memory_operand" "")
9589 (match_operand:DF 1 "gpc_reg_operand" ""))
9590 (set (match_operand:DF 2 "memory_operand" "")
9591 (match_operand:DF 3 "gpc_reg_operand" ""))]
9592 "TARGET_POWER2
9593 && TARGET_HARD_FLOAT && TARGET_FPRS
9594 && registers_ok_for_quad_peep (operands[1], operands[3])
9595 && mems_ok_for_quad_peep (operands[0], operands[2])"
9596 [(set (match_dup 0)
9597 (match_dup 1))]
9598 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
9599 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
9600
9601 ;; after inserting conditional returns we can sometimes have
9602 ;; unnecessary register moves. Unfortunately we cannot have a
9603 ;; modeless peephole here, because some single SImode sets have early
9604 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9605 ;; sequences, using get_attr_length here will smash the operands
9606 ;; array. Neither is there an early_cobbler_p predicate.
9607 (define_peephole2
9608 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9609 (match_operand:DF 1 "any_operand" ""))
9610 (set (match_operand:DF 2 "gpc_reg_operand" "")
9611 (match_dup 0))]
9612 "peep2_reg_dead_p (2, operands[0])"
9613 [(set (match_dup 2) (match_dup 1))])
9614
9615 (define_peephole2
9616 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9617 (match_operand:SF 1 "any_operand" ""))
9618 (set (match_operand:SF 2 "gpc_reg_operand" "")
9619 (match_dup 0))]
9620 "peep2_reg_dead_p (2, operands[0])"
9621 [(set (match_dup 2) (match_dup 1))])
9622
9623 \f
9624 ;; TLS support.
9625
9626 ;; "b" output constraint here and on tls_ld to support tls linker optimization.
9627 (define_insn "tls_gd_32"
9628 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9629 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9630 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9631 UNSPEC_TLSGD))]
9632 "HAVE_AS_TLS && !TARGET_64BIT"
9633 "addi %0,%1,%2@got@tlsgd")
9634
9635 (define_insn "tls_gd_64"
9636 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9637 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9638 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9639 UNSPEC_TLSGD))]
9640 "HAVE_AS_TLS && TARGET_64BIT"
9641 "addi %0,%1,%2@got@tlsgd")
9642
9643 (define_insn "tls_ld_32"
9644 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9645 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
9646 UNSPEC_TLSLD))]
9647 "HAVE_AS_TLS && !TARGET_64BIT"
9648 "addi %0,%1,%&@got@tlsld")
9649
9650 (define_insn "tls_ld_64"
9651 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9652 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
9653 UNSPEC_TLSLD))]
9654 "HAVE_AS_TLS && TARGET_64BIT"
9655 "addi %0,%1,%&@got@tlsld")
9656
9657 (define_insn "tls_dtprel_32"
9658 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9659 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9660 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9661 UNSPEC_TLSDTPREL))]
9662 "HAVE_AS_TLS && !TARGET_64BIT"
9663 "addi %0,%1,%2@dtprel")
9664
9665 (define_insn "tls_dtprel_64"
9666 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9667 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9668 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9669 UNSPEC_TLSDTPREL))]
9670 "HAVE_AS_TLS && TARGET_64BIT"
9671 "addi %0,%1,%2@dtprel")
9672
9673 (define_insn "tls_dtprel_ha_32"
9674 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9675 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9676 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9677 UNSPEC_TLSDTPRELHA))]
9678 "HAVE_AS_TLS && !TARGET_64BIT"
9679 "addis %0,%1,%2@dtprel@ha")
9680
9681 (define_insn "tls_dtprel_ha_64"
9682 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9683 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9684 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9685 UNSPEC_TLSDTPRELHA))]
9686 "HAVE_AS_TLS && TARGET_64BIT"
9687 "addis %0,%1,%2@dtprel@ha")
9688
9689 (define_insn "tls_dtprel_lo_32"
9690 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9691 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9692 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9693 UNSPEC_TLSDTPRELLO))]
9694 "HAVE_AS_TLS && !TARGET_64BIT"
9695 "addi %0,%1,%2@dtprel@l")
9696
9697 (define_insn "tls_dtprel_lo_64"
9698 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9699 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9700 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9701 UNSPEC_TLSDTPRELLO))]
9702 "HAVE_AS_TLS && TARGET_64BIT"
9703 "addi %0,%1,%2@dtprel@l")
9704
9705 (define_insn "tls_got_dtprel_32"
9706 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9707 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9708 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9709 UNSPEC_TLSGOTDTPREL))]
9710 "HAVE_AS_TLS && !TARGET_64BIT"
9711 "lwz %0,%2@got@dtprel(%1)")
9712
9713 (define_insn "tls_got_dtprel_64"
9714 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9715 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9716 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9717 UNSPEC_TLSGOTDTPREL))]
9718 "HAVE_AS_TLS && TARGET_64BIT"
9719 "ld %0,%2@got@dtprel(%1)")
9720
9721 (define_insn "tls_tprel_32"
9722 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9723 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9724 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9725 UNSPEC_TLSTPREL))]
9726 "HAVE_AS_TLS && !TARGET_64BIT"
9727 "addi %0,%1,%2@tprel")
9728
9729 (define_insn "tls_tprel_64"
9730 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9731 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9732 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9733 UNSPEC_TLSTPREL))]
9734 "HAVE_AS_TLS && TARGET_64BIT"
9735 "addi %0,%1,%2@tprel")
9736
9737 (define_insn "tls_tprel_ha_32"
9738 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9739 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9740 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9741 UNSPEC_TLSTPRELHA))]
9742 "HAVE_AS_TLS && !TARGET_64BIT"
9743 "addis %0,%1,%2@tprel@ha")
9744
9745 (define_insn "tls_tprel_ha_64"
9746 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9747 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9748 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9749 UNSPEC_TLSTPRELHA))]
9750 "HAVE_AS_TLS && TARGET_64BIT"
9751 "addis %0,%1,%2@tprel@ha")
9752
9753 (define_insn "tls_tprel_lo_32"
9754 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9755 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9756 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9757 UNSPEC_TLSTPRELLO))]
9758 "HAVE_AS_TLS && !TARGET_64BIT"
9759 "addi %0,%1,%2@tprel@l")
9760
9761 (define_insn "tls_tprel_lo_64"
9762 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9763 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9764 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9765 UNSPEC_TLSTPRELLO))]
9766 "HAVE_AS_TLS && TARGET_64BIT"
9767 "addi %0,%1,%2@tprel@l")
9768
9769 ;; "b" output constraint here and on tls_tls input to support linker tls
9770 ;; optimization. The linker may edit the instructions emitted by a
9771 ;; tls_got_tprel/tls_tls pair to addis,addi.
9772 (define_insn "tls_got_tprel_32"
9773 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9774 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9775 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9776 UNSPEC_TLSGOTTPREL))]
9777 "HAVE_AS_TLS && !TARGET_64BIT"
9778 "lwz %0,%2@got@tprel(%1)")
9779
9780 (define_insn "tls_got_tprel_64"
9781 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9782 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9783 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9784 UNSPEC_TLSGOTTPREL))]
9785 "HAVE_AS_TLS && TARGET_64BIT"
9786 "ld %0,%2@got@tprel(%1)")
9787
9788 (define_insn "tls_tls_32"
9789 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9790 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9791 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9792 UNSPEC_TLSTLS))]
9793 "HAVE_AS_TLS && !TARGET_64BIT"
9794 "add %0,%1,%2@tls")
9795
9796 (define_insn "tls_tls_64"
9797 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9798 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9799 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9800 UNSPEC_TLSTLS))]
9801 "HAVE_AS_TLS && TARGET_64BIT"
9802 "add %0,%1,%2@tls")
9803 \f
9804 ;; Next come insns related to the calling sequence.
9805 ;;
9806 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9807 ;; We move the back-chain and decrement the stack pointer.
9808
9809 (define_expand "allocate_stack"
9810 [(set (match_operand 0 "gpc_reg_operand" "=r")
9811 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9812 (set (reg 1)
9813 (minus (reg 1) (match_dup 1)))]
9814 ""
9815 "
9816 { rtx chain = gen_reg_rtx (Pmode);
9817 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
9818 rtx neg_op0;
9819
9820 emit_move_insn (chain, stack_bot);
9821
9822 /* Check stack bounds if necessary. */
9823 if (current_function_limit_stack)
9824 {
9825 rtx available;
9826 available = expand_binop (Pmode, sub_optab,
9827 stack_pointer_rtx, stack_limit_rtx,
9828 NULL_RTX, 1, OPTAB_WIDEN);
9829 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
9830 }
9831
9832 if (GET_CODE (operands[1]) != CONST_INT
9833 || INTVAL (operands[1]) < -32767
9834 || INTVAL (operands[1]) > 32768)
9835 {
9836 neg_op0 = gen_reg_rtx (Pmode);
9837 if (TARGET_32BIT)
9838 emit_insn (gen_negsi2 (neg_op0, operands[1]));
9839 else
9840 emit_insn (gen_negdi2 (neg_op0, operands[1]));
9841 }
9842 else
9843 neg_op0 = GEN_INT (- INTVAL (operands[1]));
9844
9845 if (TARGET_UPDATE)
9846 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
9847 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
9848
9849 else
9850 {
9851 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
9852 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
9853 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
9854 }
9855
9856 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9857 DONE;
9858 }")
9859
9860 ;; These patterns say how to save and restore the stack pointer. We need not
9861 ;; save the stack pointer at function level since we are careful to
9862 ;; preserve the backchain. At block level, we have to restore the backchain
9863 ;; when we restore the stack pointer.
9864 ;;
9865 ;; For nonlocal gotos, we must save both the stack pointer and its
9866 ;; backchain and restore both. Note that in the nonlocal case, the
9867 ;; save area is a memory location.
9868
9869 (define_expand "save_stack_function"
9870 [(match_operand 0 "any_operand" "")
9871 (match_operand 1 "any_operand" "")]
9872 ""
9873 "DONE;")
9874
9875 (define_expand "restore_stack_function"
9876 [(match_operand 0 "any_operand" "")
9877 (match_operand 1 "any_operand" "")]
9878 ""
9879 "DONE;")
9880
9881 ;; Adjust stack pointer (op0) to a new value (op1).
9882 ;; First copy old stack backchain to new location, and ensure that the
9883 ;; scheduler won't reorder the sp assignment before the backchain write.
9884 (define_expand "restore_stack_block"
9885 [(set (match_dup 2) (match_dup 3))
9886 (set (match_dup 4) (match_dup 2))
9887 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
9888 (set (match_operand 0 "register_operand" "")
9889 (match_operand 1 "register_operand" ""))]
9890 ""
9891 "
9892 {
9893 operands[2] = gen_reg_rtx (Pmode);
9894 operands[3] = gen_frame_mem (Pmode, operands[0]);
9895 operands[4] = gen_frame_mem (Pmode, operands[1]);
9896 operands[5] = gen_frame_mem (BLKmode, operands[0]);
9897 }")
9898
9899 (define_expand "save_stack_nonlocal"
9900 [(set (match_dup 3) (match_dup 4))
9901 (set (match_operand 0 "memory_operand" "") (match_dup 3))
9902 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
9903 ""
9904 "
9905 {
9906 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9907
9908 /* Copy the backchain to the first word, sp to the second. */
9909 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
9910 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
9911 operands[3] = gen_reg_rtx (Pmode);
9912 operands[4] = gen_frame_mem (Pmode, operands[1]);
9913 }")
9914
9915 (define_expand "restore_stack_nonlocal"
9916 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
9917 (set (match_dup 3) (match_dup 4))
9918 (set (match_dup 5) (match_dup 2))
9919 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
9920 (set (match_operand 0 "register_operand" "") (match_dup 3))]
9921 ""
9922 "
9923 {
9924 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9925
9926 /* Restore the backchain from the first word, sp from the second. */
9927 operands[2] = gen_reg_rtx (Pmode);
9928 operands[3] = gen_reg_rtx (Pmode);
9929 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
9930 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
9931 operands[5] = gen_frame_mem (Pmode, operands[3]);
9932 operands[6] = gen_frame_mem (BLKmode, operands[0]);
9933 }")
9934 \f
9935 ;; TOC register handling.
9936
9937 ;; Code to initialize the TOC register...
9938
9939 (define_insn "load_toc_aix_si"
9940 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9941 (unspec:SI [(const_int 0)] UNSPEC_TOC))
9942 (use (reg:SI 2))])]
9943 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
9944 "*
9945 {
9946 char buf[30];
9947 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9948 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9949 operands[2] = gen_rtx_REG (Pmode, 2);
9950 return \"{l|lwz} %0,%1(%2)\";
9951 }"
9952 [(set_attr "type" "load")])
9953
9954 (define_insn "load_toc_aix_di"
9955 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9956 (unspec:DI [(const_int 0)] UNSPEC_TOC))
9957 (use (reg:DI 2))])]
9958 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
9959 "*
9960 {
9961 char buf[30];
9962 #ifdef TARGET_RELOCATABLE
9963 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
9964 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
9965 #else
9966 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9967 #endif
9968 if (TARGET_ELF)
9969 strcat (buf, \"@toc\");
9970 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9971 operands[2] = gen_rtx_REG (Pmode, 2);
9972 return \"ld %0,%1(%2)\";
9973 }"
9974 [(set_attr "type" "load")])
9975
9976 (define_insn "load_toc_v4_pic_si"
9977 [(set (match_operand:SI 0 "register_operand" "=l")
9978 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
9979 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
9980 "bl _GLOBAL_OFFSET_TABLE_@local-4"
9981 [(set_attr "type" "branch")
9982 (set_attr "length" "4")])
9983
9984 (define_insn "load_toc_v4_PIC_1"
9985 [(set (match_operand:SI 0 "register_operand" "=l")
9986 (match_operand:SI 1 "immediate_operand" "s"))
9987 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
9988 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
9989 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
9990 "bcl 20,31,%1\\n%1:"
9991 [(set_attr "type" "branch")
9992 (set_attr "length" "4")])
9993
9994 (define_insn "load_toc_v4_PIC_1b"
9995 [(set (match_operand:SI 0 "register_operand" "=l")
9996 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
9997 UNSPEC_TOCPTR))]
9998 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9999 "bcl 20,31,$+8\\n\\t.long %1-$"
10000 [(set_attr "type" "branch")
10001 (set_attr "length" "8")])
10002
10003 (define_insn "load_toc_v4_PIC_2"
10004 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10005 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10006 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10007 (match_operand:SI 3 "immediate_operand" "s")))))]
10008 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10009 "{l|lwz} %0,%2-%3(%1)"
10010 [(set_attr "type" "load")])
10011
10012 (define_insn "load_toc_v4_PIC_3b"
10013 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10014 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10015 (high:SI
10016 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10017 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10018 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10019 "{cau|addis} %0,%1,%2-%3@ha")
10020
10021 (define_insn "load_toc_v4_PIC_3c"
10022 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10023 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10024 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10025 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10026 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10027 "{cal|addi} %0,%1,%2-%3@l")
10028
10029 ;; If the TOC is shared over a translation unit, as happens with all
10030 ;; the kinds of PIC that we support, we need to restore the TOC
10031 ;; pointer only when jumping over units of translation.
10032 ;; On Darwin, we need to reload the picbase.
10033
10034 (define_expand "builtin_setjmp_receiver"
10035 [(use (label_ref (match_operand 0 "" "")))]
10036 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10037 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10038 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10039 "
10040 {
10041 #if TARGET_MACHO
10042 if (DEFAULT_ABI == ABI_DARWIN)
10043 {
10044 const char *picbase = machopic_function_base_name ();
10045 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
10046 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10047 rtx tmplabrtx;
10048 char tmplab[20];
10049
10050 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10051 CODE_LABEL_NUMBER (operands[0]));
10052 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10053
10054 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
10055 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10056 }
10057 else
10058 #endif
10059 rs6000_emit_load_toc_table (FALSE);
10060 DONE;
10061 }")
10062
10063 ;; Elf specific ways of loading addresses for non-PIC code.
10064 ;; The output of this could be r0, but we make a very strong
10065 ;; preference for a base register because it will usually
10066 ;; be needed there.
10067 (define_insn "elf_high"
10068 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10069 (high:SI (match_operand 1 "" "")))]
10070 "TARGET_ELF && ! TARGET_64BIT"
10071 "{liu|lis} %0,%1@ha")
10072
10073 (define_insn "elf_low"
10074 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10075 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10076 (match_operand 2 "" "")))]
10077 "TARGET_ELF && ! TARGET_64BIT"
10078 "@
10079 {cal|la} %0,%2@l(%1)
10080 {ai|addic} %0,%1,%K2")
10081 \f
10082 ;; A function pointer under AIX is a pointer to a data area whose first word
10083 ;; contains the actual address of the function, whose second word contains a
10084 ;; pointer to its TOC, and whose third word contains a value to place in the
10085 ;; static chain register (r11). Note that if we load the static chain, our
10086 ;; "trampoline" need not have any executable code.
10087
10088 (define_expand "call_indirect_aix32"
10089 [(set (match_dup 2)
10090 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10091 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10092 (reg:SI 2))
10093 (set (reg:SI 2)
10094 (mem:SI (plus:SI (match_dup 0)
10095 (const_int 4))))
10096 (set (reg:SI 11)
10097 (mem:SI (plus:SI (match_dup 0)
10098 (const_int 8))))
10099 (parallel [(call (mem:SI (match_dup 2))
10100 (match_operand 1 "" ""))
10101 (use (reg:SI 2))
10102 (use (reg:SI 11))
10103 (set (reg:SI 2)
10104 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10105 (clobber (scratch:SI))])]
10106 "TARGET_32BIT"
10107 "
10108 { operands[2] = gen_reg_rtx (SImode); }")
10109
10110 (define_expand "call_indirect_aix64"
10111 [(set (match_dup 2)
10112 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10113 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10114 (reg:DI 2))
10115 (set (reg:DI 2)
10116 (mem:DI (plus:DI (match_dup 0)
10117 (const_int 8))))
10118 (set (reg:DI 11)
10119 (mem:DI (plus:DI (match_dup 0)
10120 (const_int 16))))
10121 (parallel [(call (mem:SI (match_dup 2))
10122 (match_operand 1 "" ""))
10123 (use (reg:DI 2))
10124 (use (reg:DI 11))
10125 (set (reg:DI 2)
10126 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10127 (clobber (scratch:SI))])]
10128 "TARGET_64BIT"
10129 "
10130 { operands[2] = gen_reg_rtx (DImode); }")
10131
10132 (define_expand "call_value_indirect_aix32"
10133 [(set (match_dup 3)
10134 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10135 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10136 (reg:SI 2))
10137 (set (reg:SI 2)
10138 (mem:SI (plus:SI (match_dup 1)
10139 (const_int 4))))
10140 (set (reg:SI 11)
10141 (mem:SI (plus:SI (match_dup 1)
10142 (const_int 8))))
10143 (parallel [(set (match_operand 0 "" "")
10144 (call (mem:SI (match_dup 3))
10145 (match_operand 2 "" "")))
10146 (use (reg:SI 2))
10147 (use (reg:SI 11))
10148 (set (reg:SI 2)
10149 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10150 (clobber (scratch:SI))])]
10151 "TARGET_32BIT"
10152 "
10153 { operands[3] = gen_reg_rtx (SImode); }")
10154
10155 (define_expand "call_value_indirect_aix64"
10156 [(set (match_dup 3)
10157 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10158 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10159 (reg:DI 2))
10160 (set (reg:DI 2)
10161 (mem:DI (plus:DI (match_dup 1)
10162 (const_int 8))))
10163 (set (reg:DI 11)
10164 (mem:DI (plus:DI (match_dup 1)
10165 (const_int 16))))
10166 (parallel [(set (match_operand 0 "" "")
10167 (call (mem:SI (match_dup 3))
10168 (match_operand 2 "" "")))
10169 (use (reg:DI 2))
10170 (use (reg:DI 11))
10171 (set (reg:DI 2)
10172 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10173 (clobber (scratch:SI))])]
10174 "TARGET_64BIT"
10175 "
10176 { operands[3] = gen_reg_rtx (DImode); }")
10177
10178 ;; Now the definitions for the call and call_value insns
10179 (define_expand "call"
10180 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10181 (match_operand 1 "" ""))
10182 (use (match_operand 2 "" ""))
10183 (clobber (scratch:SI))])]
10184 ""
10185 "
10186 {
10187 #if TARGET_MACHO
10188 if (MACHOPIC_INDIRECT)
10189 operands[0] = machopic_indirect_call_target (operands[0]);
10190 #endif
10191
10192 gcc_assert (GET_CODE (operands[0]) == MEM);
10193 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10194
10195 operands[0] = XEXP (operands[0], 0);
10196
10197 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10198 && flag_pic
10199 && GET_CODE (operands[0]) == SYMBOL_REF
10200 && !SYMBOL_REF_LOCAL_P (operands[0]))
10201 {
10202 rtx call;
10203 rtvec tmp;
10204
10205 tmp = gen_rtvec (3,
10206 gen_rtx_CALL (VOIDmode,
10207 gen_rtx_MEM (SImode, operands[0]),
10208 operands[1]),
10209 gen_rtx_USE (VOIDmode, operands[2]),
10210 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
10211 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10212 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10213 DONE;
10214 }
10215
10216 if (GET_CODE (operands[0]) != SYMBOL_REF
10217 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10218 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10219 {
10220 if (INTVAL (operands[2]) & CALL_LONG)
10221 operands[0] = rs6000_longcall_ref (operands[0]);
10222
10223 switch (DEFAULT_ABI)
10224 {
10225 case ABI_V4:
10226 case ABI_DARWIN:
10227 operands[0] = force_reg (Pmode, operands[0]);
10228 break;
10229
10230 case ABI_AIX:
10231 /* AIX function pointers are really pointers to a three word
10232 area. */
10233 emit_call_insn (TARGET_32BIT
10234 ? gen_call_indirect_aix32 (force_reg (SImode,
10235 operands[0]),
10236 operands[1])
10237 : gen_call_indirect_aix64 (force_reg (DImode,
10238 operands[0]),
10239 operands[1]));
10240 DONE;
10241
10242 default:
10243 gcc_unreachable ();
10244 }
10245 }
10246 }")
10247
10248 (define_expand "call_value"
10249 [(parallel [(set (match_operand 0 "" "")
10250 (call (mem:SI (match_operand 1 "address_operand" ""))
10251 (match_operand 2 "" "")))
10252 (use (match_operand 3 "" ""))
10253 (clobber (scratch:SI))])]
10254 ""
10255 "
10256 {
10257 #if TARGET_MACHO
10258 if (MACHOPIC_INDIRECT)
10259 operands[1] = machopic_indirect_call_target (operands[1]);
10260 #endif
10261
10262 gcc_assert (GET_CODE (operands[1]) == MEM);
10263 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10264
10265 operands[1] = XEXP (operands[1], 0);
10266
10267 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10268 && flag_pic
10269 && GET_CODE (operands[1]) == SYMBOL_REF
10270 && !SYMBOL_REF_LOCAL_P (operands[1]))
10271 {
10272 rtx call;
10273 rtvec tmp;
10274
10275 tmp = gen_rtvec (3,
10276 gen_rtx_SET (VOIDmode,
10277 operands[0],
10278 gen_rtx_CALL (VOIDmode,
10279 gen_rtx_MEM (SImode,
10280 operands[1]),
10281 operands[2])),
10282 gen_rtx_USE (VOIDmode, operands[3]),
10283 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
10284 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10285 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10286 DONE;
10287 }
10288
10289 if (GET_CODE (operands[1]) != SYMBOL_REF
10290 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10291 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10292 {
10293 if (INTVAL (operands[3]) & CALL_LONG)
10294 operands[1] = rs6000_longcall_ref (operands[1]);
10295
10296 switch (DEFAULT_ABI)
10297 {
10298 case ABI_V4:
10299 case ABI_DARWIN:
10300 operands[1] = force_reg (Pmode, operands[1]);
10301 break;
10302
10303 case ABI_AIX:
10304 /* AIX function pointers are really pointers to a three word
10305 area. */
10306 emit_call_insn (TARGET_32BIT
10307 ? gen_call_value_indirect_aix32 (operands[0],
10308 force_reg (SImode,
10309 operands[1]),
10310 operands[2])
10311 : gen_call_value_indirect_aix64 (operands[0],
10312 force_reg (DImode,
10313 operands[1]),
10314 operands[2]));
10315 DONE;
10316
10317 default:
10318 gcc_unreachable ();
10319 }
10320 }
10321 }")
10322
10323 ;; Call to function in current module. No TOC pointer reload needed.
10324 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10325 ;; either the function was not prototyped, or it was prototyped as a
10326 ;; variable argument function. It is > 0 if FP registers were passed
10327 ;; and < 0 if they were not.
10328
10329 (define_insn "*call_local32"
10330 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10331 (match_operand 1 "" "g,g"))
10332 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10333 (clobber (match_scratch:SI 3 "=l,l"))]
10334 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10335 "*
10336 {
10337 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10338 output_asm_insn (\"crxor 6,6,6\", operands);
10339
10340 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10341 output_asm_insn (\"creqv 6,6,6\", operands);
10342
10343 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10344 }"
10345 [(set_attr "type" "branch")
10346 (set_attr "length" "4,8")])
10347
10348 (define_insn "*call_local64"
10349 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10350 (match_operand 1 "" "g,g"))
10351 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10352 (clobber (match_scratch:SI 3 "=l,l"))]
10353 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10354 "*
10355 {
10356 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10357 output_asm_insn (\"crxor 6,6,6\", operands);
10358
10359 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10360 output_asm_insn (\"creqv 6,6,6\", operands);
10361
10362 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10363 }"
10364 [(set_attr "type" "branch")
10365 (set_attr "length" "4,8")])
10366
10367 (define_insn "*call_value_local32"
10368 [(set (match_operand 0 "" "")
10369 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10370 (match_operand 2 "" "g,g")))
10371 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10372 (clobber (match_scratch:SI 4 "=l,l"))]
10373 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10374 "*
10375 {
10376 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10377 output_asm_insn (\"crxor 6,6,6\", operands);
10378
10379 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10380 output_asm_insn (\"creqv 6,6,6\", operands);
10381
10382 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10383 }"
10384 [(set_attr "type" "branch")
10385 (set_attr "length" "4,8")])
10386
10387
10388 (define_insn "*call_value_local64"
10389 [(set (match_operand 0 "" "")
10390 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10391 (match_operand 2 "" "g,g")))
10392 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10393 (clobber (match_scratch:SI 4 "=l,l"))]
10394 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10395 "*
10396 {
10397 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10398 output_asm_insn (\"crxor 6,6,6\", operands);
10399
10400 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10401 output_asm_insn (\"creqv 6,6,6\", operands);
10402
10403 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10404 }"
10405 [(set_attr "type" "branch")
10406 (set_attr "length" "4,8")])
10407
10408 ;; Call to function which may be in another module. Restore the TOC
10409 ;; pointer (r2) after the call unless this is System V.
10410 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10411 ;; either the function was not prototyped, or it was prototyped as a
10412 ;; variable argument function. It is > 0 if FP registers were passed
10413 ;; and < 0 if they were not.
10414
10415 (define_insn "*call_indirect_nonlocal_aix32"
10416 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
10417 (match_operand 1 "" "g,g"))
10418 (use (reg:SI 2))
10419 (use (reg:SI 11))
10420 (set (reg:SI 2)
10421 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10422 (clobber (match_scratch:SI 2 "=l,l"))]
10423 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10424 "b%T0l\;{l|lwz} 2,20(1)"
10425 [(set_attr "type" "jmpreg")
10426 (set_attr "length" "8")])
10427
10428 (define_insn "*call_nonlocal_aix32"
10429 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10430 (match_operand 1 "" "g"))
10431 (use (match_operand:SI 2 "immediate_operand" "O"))
10432 (clobber (match_scratch:SI 3 "=l"))]
10433 "TARGET_32BIT
10434 && DEFAULT_ABI == ABI_AIX
10435 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10436 "bl %z0\;%."
10437 [(set_attr "type" "branch")
10438 (set_attr "length" "8")])
10439
10440 (define_insn "*call_indirect_nonlocal_aix64"
10441 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
10442 (match_operand 1 "" "g,g"))
10443 (use (reg:DI 2))
10444 (use (reg:DI 11))
10445 (set (reg:DI 2)
10446 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10447 (clobber (match_scratch:SI 2 "=l,l"))]
10448 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10449 "b%T0l\;ld 2,40(1)"
10450 [(set_attr "type" "jmpreg")
10451 (set_attr "length" "8")])
10452
10453 (define_insn "*call_nonlocal_aix64"
10454 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10455 (match_operand 1 "" "g"))
10456 (use (match_operand:SI 2 "immediate_operand" "O"))
10457 (clobber (match_scratch:SI 3 "=l"))]
10458 "TARGET_64BIT
10459 && DEFAULT_ABI == ABI_AIX
10460 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10461 "bl %z0\;%."
10462 [(set_attr "type" "branch")
10463 (set_attr "length" "8")])
10464
10465 (define_insn "*call_value_indirect_nonlocal_aix32"
10466 [(set (match_operand 0 "" "")
10467 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
10468 (match_operand 2 "" "g,g")))
10469 (use (reg:SI 2))
10470 (use (reg:SI 11))
10471 (set (reg:SI 2)
10472 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10473 (clobber (match_scratch:SI 3 "=l,l"))]
10474 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10475 "b%T1l\;{l|lwz} 2,20(1)"
10476 [(set_attr "type" "jmpreg")
10477 (set_attr "length" "8")])
10478
10479 (define_insn "*call_value_nonlocal_aix32"
10480 [(set (match_operand 0 "" "")
10481 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10482 (match_operand 2 "" "g")))
10483 (use (match_operand:SI 3 "immediate_operand" "O"))
10484 (clobber (match_scratch:SI 4 "=l"))]
10485 "TARGET_32BIT
10486 && DEFAULT_ABI == ABI_AIX
10487 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10488 "bl %z1\;%."
10489 [(set_attr "type" "branch")
10490 (set_attr "length" "8")])
10491
10492 (define_insn "*call_value_indirect_nonlocal_aix64"
10493 [(set (match_operand 0 "" "")
10494 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
10495 (match_operand 2 "" "g,g")))
10496 (use (reg:DI 2))
10497 (use (reg:DI 11))
10498 (set (reg:DI 2)
10499 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10500 (clobber (match_scratch:SI 3 "=l,l"))]
10501 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10502 "b%T1l\;ld 2,40(1)"
10503 [(set_attr "type" "jmpreg")
10504 (set_attr "length" "8")])
10505
10506 (define_insn "*call_value_nonlocal_aix64"
10507 [(set (match_operand 0 "" "")
10508 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10509 (match_operand 2 "" "g")))
10510 (use (match_operand:SI 3 "immediate_operand" "O"))
10511 (clobber (match_scratch:SI 4 "=l"))]
10512 "TARGET_64BIT
10513 && DEFAULT_ABI == ABI_AIX
10514 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10515 "bl %z1\;%."
10516 [(set_attr "type" "branch")
10517 (set_attr "length" "8")])
10518
10519 ;; A function pointer under System V is just a normal pointer
10520 ;; operands[0] is the function pointer
10521 ;; operands[1] is the stack size to clean up
10522 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10523 ;; which indicates how to set cr1
10524
10525 (define_insn "*call_indirect_nonlocal_sysv"
10526 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l,c,*l"))
10527 (match_operand 1 "" "g,g,g,g"))
10528 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
10529 (clobber (match_scratch:SI 3 "=l,l,l,l"))]
10530 "DEFAULT_ABI == ABI_V4
10531 || DEFAULT_ABI == ABI_DARWIN"
10532 {
10533 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10534 output_asm_insn ("crxor 6,6,6", operands);
10535
10536 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10537 output_asm_insn ("creqv 6,6,6", operands);
10538
10539 return "b%T0l";
10540 }
10541 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10542 (set_attr "length" "4,4,8,8")])
10543
10544 (define_insn "*call_nonlocal_sysv"
10545 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10546 (match_operand 1 "" "g,g"))
10547 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10548 (clobber (match_scratch:SI 3 "=l,l"))]
10549 "(DEFAULT_ABI == ABI_DARWIN
10550 || (DEFAULT_ABI == ABI_V4
10551 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10552 {
10553 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10554 output_asm_insn ("crxor 6,6,6", operands);
10555
10556 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10557 output_asm_insn ("creqv 6,6,6", operands);
10558
10559 #if TARGET_MACHO
10560 return output_call(insn, operands, 0, 2);
10561 #else
10562 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10563 {
10564 if (TARGET_SECURE_PLT && flag_pic == 2)
10565 /* The magic 32768 offset here and in the other sysv call insns
10566 corresponds to the offset of r30 in .got2, as given by LCTOC1.
10567 See sysv4.h:toc_section. */
10568 return "bl %z0+32768@plt";
10569 else
10570 return "bl %z0@plt";
10571 }
10572 else
10573 return "bl %z0";
10574 #endif
10575 }
10576 [(set_attr "type" "branch,branch")
10577 (set_attr "length" "4,8")])
10578
10579 (define_insn "*call_value_indirect_nonlocal_sysv"
10580 [(set (match_operand 0 "" "")
10581 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l,c,*l"))
10582 (match_operand 2 "" "g,g,g,g")))
10583 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
10584 (clobber (match_scratch:SI 4 "=l,l,l,l"))]
10585 "DEFAULT_ABI == ABI_V4
10586 || DEFAULT_ABI == ABI_DARWIN"
10587 {
10588 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10589 output_asm_insn ("crxor 6,6,6", operands);
10590
10591 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10592 output_asm_insn ("creqv 6,6,6", operands);
10593
10594 return "b%T1l";
10595 }
10596 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10597 (set_attr "length" "4,4,8,8")])
10598
10599 (define_insn "*call_value_nonlocal_sysv"
10600 [(set (match_operand 0 "" "")
10601 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10602 (match_operand 2 "" "g,g")))
10603 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10604 (clobber (match_scratch:SI 4 "=l,l"))]
10605 "(DEFAULT_ABI == ABI_DARWIN
10606 || (DEFAULT_ABI == ABI_V4
10607 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10608 {
10609 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10610 output_asm_insn ("crxor 6,6,6", operands);
10611
10612 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10613 output_asm_insn ("creqv 6,6,6", operands);
10614
10615 #if TARGET_MACHO
10616 return output_call(insn, operands, 1, 3);
10617 #else
10618 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10619 {
10620 if (TARGET_SECURE_PLT && flag_pic == 2)
10621 return "bl %z1+32768@plt";
10622 else
10623 return "bl %z1@plt";
10624 }
10625 else
10626 return "bl %z1";
10627 #endif
10628 }
10629 [(set_attr "type" "branch,branch")
10630 (set_attr "length" "4,8")])
10631
10632 ;; Call subroutine returning any type.
10633 (define_expand "untyped_call"
10634 [(parallel [(call (match_operand 0 "" "")
10635 (const_int 0))
10636 (match_operand 1 "" "")
10637 (match_operand 2 "" "")])]
10638 ""
10639 "
10640 {
10641 int i;
10642
10643 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10644
10645 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10646 {
10647 rtx set = XVECEXP (operands[2], 0, i);
10648 emit_move_insn (SET_DEST (set), SET_SRC (set));
10649 }
10650
10651 /* The optimizer does not know that the call sets the function value
10652 registers we stored in the result block. We avoid problems by
10653 claiming that all hard registers are used and clobbered at this
10654 point. */
10655 emit_insn (gen_blockage ());
10656
10657 DONE;
10658 }")
10659
10660 ;; sibling call patterns
10661 (define_expand "sibcall"
10662 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10663 (match_operand 1 "" ""))
10664 (use (match_operand 2 "" ""))
10665 (use (match_operand 3 "" ""))
10666 (return)])]
10667 ""
10668 "
10669 {
10670 #if TARGET_MACHO
10671 if (MACHOPIC_INDIRECT)
10672 operands[0] = machopic_indirect_call_target (operands[0]);
10673 #endif
10674
10675 gcc_assert (GET_CODE (operands[0]) == MEM);
10676 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10677
10678 operands[0] = XEXP (operands[0], 0);
10679 operands[3] = gen_reg_rtx (SImode);
10680
10681 }")
10682
10683 ;; this and similar patterns must be marked as using LR, otherwise
10684 ;; dataflow will try to delete the store into it. This is true
10685 ;; even when the actual reg to jump to is in CTR, when LR was
10686 ;; saved and restored around the PIC-setting BCL.
10687 (define_insn "*sibcall_local32"
10688 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10689 (match_operand 1 "" "g,g"))
10690 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10691 (use (match_operand:SI 3 "register_operand" "l,l"))
10692 (return)]
10693 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10694 "*
10695 {
10696 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10697 output_asm_insn (\"crxor 6,6,6\", operands);
10698
10699 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10700 output_asm_insn (\"creqv 6,6,6\", operands);
10701
10702 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10703 }"
10704 [(set_attr "type" "branch")
10705 (set_attr "length" "4,8")])
10706
10707 (define_insn "*sibcall_local64"
10708 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10709 (match_operand 1 "" "g,g"))
10710 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10711 (use (match_operand:SI 3 "register_operand" "l,l"))
10712 (return)]
10713 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10714 "*
10715 {
10716 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10717 output_asm_insn (\"crxor 6,6,6\", operands);
10718
10719 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10720 output_asm_insn (\"creqv 6,6,6\", operands);
10721
10722 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10723 }"
10724 [(set_attr "type" "branch")
10725 (set_attr "length" "4,8")])
10726
10727 (define_insn "*sibcall_value_local32"
10728 [(set (match_operand 0 "" "")
10729 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10730 (match_operand 2 "" "g,g")))
10731 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10732 (use (match_operand:SI 4 "register_operand" "l,l"))
10733 (return)]
10734 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10735 "*
10736 {
10737 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10738 output_asm_insn (\"crxor 6,6,6\", operands);
10739
10740 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10741 output_asm_insn (\"creqv 6,6,6\", operands);
10742
10743 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10744 }"
10745 [(set_attr "type" "branch")
10746 (set_attr "length" "4,8")])
10747
10748
10749 (define_insn "*sibcall_value_local64"
10750 [(set (match_operand 0 "" "")
10751 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10752 (match_operand 2 "" "g,g")))
10753 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10754 (use (match_operand:SI 4 "register_operand" "l,l"))
10755 (return)]
10756 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10757 "*
10758 {
10759 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10760 output_asm_insn (\"crxor 6,6,6\", operands);
10761
10762 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10763 output_asm_insn (\"creqv 6,6,6\", operands);
10764
10765 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10766 }"
10767 [(set_attr "type" "branch")
10768 (set_attr "length" "4,8")])
10769
10770 (define_insn "*sibcall_nonlocal_aix32"
10771 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10772 (match_operand 1 "" "g"))
10773 (use (match_operand:SI 2 "immediate_operand" "O"))
10774 (use (match_operand:SI 3 "register_operand" "l"))
10775 (return)]
10776 "TARGET_32BIT
10777 && DEFAULT_ABI == ABI_AIX
10778 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10779 "b %z0"
10780 [(set_attr "type" "branch")
10781 (set_attr "length" "4")])
10782
10783 (define_insn "*sibcall_nonlocal_aix64"
10784 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10785 (match_operand 1 "" "g"))
10786 (use (match_operand:SI 2 "immediate_operand" "O"))
10787 (use (match_operand:SI 3 "register_operand" "l"))
10788 (return)]
10789 "TARGET_64BIT
10790 && DEFAULT_ABI == ABI_AIX
10791 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10792 "b %z0"
10793 [(set_attr "type" "branch")
10794 (set_attr "length" "4")])
10795
10796 (define_insn "*sibcall_value_nonlocal_aix32"
10797 [(set (match_operand 0 "" "")
10798 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10799 (match_operand 2 "" "g")))
10800 (use (match_operand:SI 3 "immediate_operand" "O"))
10801 (use (match_operand:SI 4 "register_operand" "l"))
10802 (return)]
10803 "TARGET_32BIT
10804 && DEFAULT_ABI == ABI_AIX
10805 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10806 "b %z1"
10807 [(set_attr "type" "branch")
10808 (set_attr "length" "4")])
10809
10810 (define_insn "*sibcall_value_nonlocal_aix64"
10811 [(set (match_operand 0 "" "")
10812 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10813 (match_operand 2 "" "g")))
10814 (use (match_operand:SI 3 "immediate_operand" "O"))
10815 (use (match_operand:SI 4 "register_operand" "l"))
10816 (return)]
10817 "TARGET_64BIT
10818 && DEFAULT_ABI == ABI_AIX
10819 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10820 "b %z1"
10821 [(set_attr "type" "branch")
10822 (set_attr "length" "4")])
10823
10824 (define_insn "*sibcall_nonlocal_sysv"
10825 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10826 (match_operand 1 "" ""))
10827 (use (match_operand 2 "immediate_operand" "O,n"))
10828 (use (match_operand:SI 3 "register_operand" "l,l"))
10829 (return)]
10830 "(DEFAULT_ABI == ABI_DARWIN
10831 || DEFAULT_ABI == ABI_V4)
10832 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10833 "*
10834 {
10835 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10836 output_asm_insn (\"crxor 6,6,6\", operands);
10837
10838 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10839 output_asm_insn (\"creqv 6,6,6\", operands);
10840
10841 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10842 {
10843 if (TARGET_SECURE_PLT && flag_pic == 2)
10844 return \"b %z0+32768@plt\";
10845 else
10846 return \"b %z0@plt\";
10847 }
10848 else
10849 return \"b %z0\";
10850 }"
10851 [(set_attr "type" "branch,branch")
10852 (set_attr "length" "4,8")])
10853
10854 (define_expand "sibcall_value"
10855 [(parallel [(set (match_operand 0 "register_operand" "")
10856 (call (mem:SI (match_operand 1 "address_operand" ""))
10857 (match_operand 2 "" "")))
10858 (use (match_operand 3 "" ""))
10859 (use (match_operand 4 "" ""))
10860 (return)])]
10861 ""
10862 "
10863 {
10864 #if TARGET_MACHO
10865 if (MACHOPIC_INDIRECT)
10866 operands[1] = machopic_indirect_call_target (operands[1]);
10867 #endif
10868
10869 gcc_assert (GET_CODE (operands[1]) == MEM);
10870 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10871
10872 operands[1] = XEXP (operands[1], 0);
10873 operands[4] = gen_reg_rtx (SImode);
10874
10875 }")
10876
10877 (define_insn "*sibcall_value_nonlocal_sysv"
10878 [(set (match_operand 0 "" "")
10879 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10880 (match_operand 2 "" "")))
10881 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10882 (use (match_operand:SI 4 "register_operand" "l,l"))
10883 (return)]
10884 "(DEFAULT_ABI == ABI_DARWIN
10885 || DEFAULT_ABI == ABI_V4)
10886 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10887 "*
10888 {
10889 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10890 output_asm_insn (\"crxor 6,6,6\", operands);
10891
10892 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10893 output_asm_insn (\"creqv 6,6,6\", operands);
10894
10895 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10896 {
10897 if (TARGET_SECURE_PLT && flag_pic == 2)
10898 return \"b %z1+32768@plt\";
10899 else
10900 return \"b %z1@plt\";
10901 }
10902 else
10903 return \"b %z1\";
10904 }"
10905 [(set_attr "type" "branch,branch")
10906 (set_attr "length" "4,8")])
10907
10908 (define_expand "sibcall_epilogue"
10909 [(use (const_int 0))]
10910 "TARGET_SCHED_PROLOG"
10911 "
10912 {
10913 rs6000_emit_epilogue (TRUE);
10914 DONE;
10915 }")
10916
10917 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10918 ;; all of memory. This blocks insns from being moved across this point.
10919
10920 (define_insn "blockage"
10921 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
10922 ""
10923 "")
10924 \f
10925 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
10926 ;; signed & unsigned, and one type of branch.
10927 ;;
10928 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
10929 ;; insns, and branches. We store the operands of compares until we see
10930 ;; how it is used.
10931 (define_expand "cmp<mode>"
10932 [(set (cc0)
10933 (compare (match_operand:GPR 0 "gpc_reg_operand" "")
10934 (match_operand:GPR 1 "reg_or_short_operand" "")))]
10935 ""
10936 "
10937 {
10938 /* Take care of the possibility that operands[1] might be negative but
10939 this might be a logical operation. That insn doesn't exist. */
10940 if (GET_CODE (operands[1]) == CONST_INT
10941 && INTVAL (operands[1]) < 0)
10942 operands[1] = force_reg (<MODE>mode, operands[1]);
10943
10944 rs6000_compare_op0 = operands[0];
10945 rs6000_compare_op1 = operands[1];
10946 rs6000_compare_fp_p = 0;
10947 DONE;
10948 }")
10949
10950 (define_expand "cmp<mode>"
10951 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
10952 (match_operand:FP 1 "gpc_reg_operand" "")))]
10953 ""
10954 "
10955 {
10956 rs6000_compare_op0 = operands[0];
10957 rs6000_compare_op1 = operands[1];
10958 rs6000_compare_fp_p = 1;
10959 DONE;
10960 }")
10961
10962 (define_expand "beq"
10963 [(use (match_operand 0 "" ""))]
10964 ""
10965 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
10966
10967 (define_expand "bne"
10968 [(use (match_operand 0 "" ""))]
10969 ""
10970 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
10971
10972 (define_expand "bge"
10973 [(use (match_operand 0 "" ""))]
10974 ""
10975 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
10976
10977 (define_expand "bgt"
10978 [(use (match_operand 0 "" ""))]
10979 ""
10980 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
10981
10982 (define_expand "ble"
10983 [(use (match_operand 0 "" ""))]
10984 ""
10985 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
10986
10987 (define_expand "blt"
10988 [(use (match_operand 0 "" ""))]
10989 ""
10990 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
10991
10992 (define_expand "bgeu"
10993 [(use (match_operand 0 "" ""))]
10994 ""
10995 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
10996
10997 (define_expand "bgtu"
10998 [(use (match_operand 0 "" ""))]
10999 ""
11000 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
11001
11002 (define_expand "bleu"
11003 [(use (match_operand 0 "" ""))]
11004 ""
11005 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
11006
11007 (define_expand "bltu"
11008 [(use (match_operand 0 "" ""))]
11009 ""
11010 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
11011
11012 (define_expand "bunordered"
11013 [(use (match_operand 0 "" ""))]
11014 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11015 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
11016
11017 (define_expand "bordered"
11018 [(use (match_operand 0 "" ""))]
11019 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11020 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
11021
11022 (define_expand "buneq"
11023 [(use (match_operand 0 "" ""))]
11024 ""
11025 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
11026
11027 (define_expand "bunge"
11028 [(use (match_operand 0 "" ""))]
11029 ""
11030 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
11031
11032 (define_expand "bungt"
11033 [(use (match_operand 0 "" ""))]
11034 ""
11035 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
11036
11037 (define_expand "bunle"
11038 [(use (match_operand 0 "" ""))]
11039 ""
11040 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
11041
11042 (define_expand "bunlt"
11043 [(use (match_operand 0 "" ""))]
11044 ""
11045 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
11046
11047 (define_expand "bltgt"
11048 [(use (match_operand 0 "" ""))]
11049 ""
11050 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
11051
11052 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11053 ;; For SEQ, likewise, except that comparisons with zero should be done
11054 ;; with an scc insns. However, due to the order that combine see the
11055 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11056 ;; the cases we don't want to handle.
11057 (define_expand "seq"
11058 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11059 ""
11060 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
11061
11062 (define_expand "sne"
11063 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11064 ""
11065 "
11066 {
11067 if (! rs6000_compare_fp_p)
11068 FAIL;
11069
11070 rs6000_emit_sCOND (NE, operands[0]);
11071 DONE;
11072 }")
11073
11074 ;; A >= 0 is best done the portable way for A an integer.
11075 (define_expand "sge"
11076 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11077 ""
11078 "
11079 {
11080 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11081 FAIL;
11082
11083 rs6000_emit_sCOND (GE, operands[0]);
11084 DONE;
11085 }")
11086
11087 ;; A > 0 is best done using the portable sequence, so fail in that case.
11088 (define_expand "sgt"
11089 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11090 ""
11091 "
11092 {
11093 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11094 FAIL;
11095
11096 rs6000_emit_sCOND (GT, operands[0]);
11097 DONE;
11098 }")
11099
11100 ;; A <= 0 is best done the portable way for A an integer.
11101 (define_expand "sle"
11102 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11103 ""
11104 "
11105 {
11106 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11107 FAIL;
11108
11109 rs6000_emit_sCOND (LE, operands[0]);
11110 DONE;
11111 }")
11112
11113 ;; A < 0 is best done in the portable way for A an integer.
11114 (define_expand "slt"
11115 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11116 ""
11117 "
11118 {
11119 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11120 FAIL;
11121
11122 rs6000_emit_sCOND (LT, operands[0]);
11123 DONE;
11124 }")
11125
11126 (define_expand "sgeu"
11127 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11128 ""
11129 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11130
11131 (define_expand "sgtu"
11132 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11133 ""
11134 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
11135
11136 (define_expand "sleu"
11137 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11138 ""
11139 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11140
11141 (define_expand "sltu"
11142 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11143 ""
11144 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
11145
11146 (define_expand "sunordered"
11147 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11148 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11149 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
11150
11151 (define_expand "sordered"
11152 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11153 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11154 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11155
11156 (define_expand "suneq"
11157 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11158 ""
11159 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11160
11161 (define_expand "sunge"
11162 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11163 ""
11164 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11165
11166 (define_expand "sungt"
11167 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11168 ""
11169 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11170
11171 (define_expand "sunle"
11172 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11173 ""
11174 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11175
11176 (define_expand "sunlt"
11177 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11178 ""
11179 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11180
11181 (define_expand "sltgt"
11182 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11183 ""
11184 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11185
11186 (define_expand "stack_protect_set"
11187 [(match_operand 0 "memory_operand" "")
11188 (match_operand 1 "memory_operand" "")]
11189 ""
11190 {
11191 #ifdef TARGET_THREAD_SSP_OFFSET
11192 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11193 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11194 operands[1] = gen_rtx_MEM (Pmode, addr);
11195 #endif
11196 if (TARGET_64BIT)
11197 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11198 else
11199 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11200 DONE;
11201 })
11202
11203 (define_insn "stack_protect_setsi"
11204 [(set (match_operand:SI 0 "memory_operand" "=m")
11205 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11206 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11207 "TARGET_32BIT"
11208 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
11209 [(set_attr "type" "three")
11210 (set_attr "length" "12")])
11211
11212 (define_insn "stack_protect_setdi"
11213 [(set (match_operand:DI 0 "memory_operand" "=m")
11214 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11215 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11216 "TARGET_64BIT"
11217 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
11218 [(set_attr "type" "three")
11219 (set_attr "length" "12")])
11220
11221 (define_expand "stack_protect_test"
11222 [(match_operand 0 "memory_operand" "")
11223 (match_operand 1 "memory_operand" "")
11224 (match_operand 2 "" "")]
11225 ""
11226 {
11227 #ifdef TARGET_THREAD_SSP_OFFSET
11228 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11229 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11230 operands[1] = gen_rtx_MEM (Pmode, addr);
11231 #endif
11232 rs6000_compare_op0 = operands[0];
11233 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
11234 UNSPEC_SP_TEST);
11235 rs6000_compare_fp_p = 0;
11236 emit_jump_insn (gen_beq (operands[2]));
11237 DONE;
11238 })
11239
11240 (define_insn "stack_protect_testsi"
11241 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11242 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11243 (match_operand:SI 2 "memory_operand" "m,m")]
11244 UNSPEC_SP_TEST))
11245 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11246 (clobber (match_scratch:SI 3 "=&r,&r"))]
11247 "TARGET_32BIT"
11248 "@
11249 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11250 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11251 [(set_attr "length" "16,20")])
11252
11253 (define_insn "stack_protect_testdi"
11254 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11255 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
11256 (match_operand:DI 2 "memory_operand" "m,m")]
11257 UNSPEC_SP_TEST))
11258 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11259 (clobber (match_scratch:DI 3 "=&r,&r"))]
11260 "TARGET_64BIT"
11261 "@
11262 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11263 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11264 [(set_attr "length" "16,20")])
11265
11266 \f
11267 ;; Here are the actual compare insns.
11268 (define_insn "*cmp<mode>_internal1"
11269 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11270 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11271 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
11272 ""
11273 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
11274 [(set_attr "type" "cmp")])
11275
11276 ;; If we are comparing a register for equality with a large constant,
11277 ;; we can do this with an XOR followed by a compare. But this is profitable
11278 ;; only if the large constant is only used for the comparison (and in this
11279 ;; case we already have a register to reuse as scratch).
11280 ;;
11281 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11282 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
11283
11284 (define_peephole2
11285 [(set (match_operand:SI 0 "register_operand")
11286 (match_operand:SI 1 "logical_operand" ""))
11287 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
11288 [(match_dup 0)
11289 (match_operand:SI 2 "logical_operand" "")]))
11290 (set (match_operand:CC 4 "cc_reg_operand" "")
11291 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
11292 (match_dup 0)))
11293 (set (pc)
11294 (if_then_else (match_operator 6 "equality_operator"
11295 [(match_dup 4) (const_int 0)])
11296 (match_operand 7 "" "")
11297 (match_operand 8 "" "")))]
11298 "peep2_reg_dead_p (3, operands[0])
11299 && peep2_reg_dead_p (4, operands[4])"
11300 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
11301 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11302 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11303
11304 {
11305 /* Get the constant we are comparing against, and see what it looks like
11306 when sign-extended from 16 to 32 bits. Then see what constant we could
11307 XOR with SEXTC to get the sign-extended value. */
11308 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
11309 SImode,
11310 operands[1], operands[2]);
11311 HOST_WIDE_INT c = INTVAL (cnst);
11312 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11313 HOST_WIDE_INT xorv = c ^ sextc;
11314
11315 operands[9] = GEN_INT (xorv);
11316 operands[10] = GEN_INT (sextc);
11317 })
11318
11319 (define_insn "*cmpsi_internal2"
11320 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11321 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11322 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11323 ""
11324 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
11325 [(set_attr "type" "cmp")])
11326
11327 (define_insn "*cmpdi_internal2"
11328 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11329 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11330 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11331 ""
11332 "cmpld%I2 %0,%1,%b2"
11333 [(set_attr "type" "cmp")])
11334
11335 ;; The following two insns don't exist as single insns, but if we provide
11336 ;; them, we can swap an add and compare, which will enable us to overlap more
11337 ;; of the required delay between a compare and branch. We generate code for
11338 ;; them by splitting.
11339
11340 (define_insn ""
11341 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11342 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11343 (match_operand:SI 2 "short_cint_operand" "i")))
11344 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11345 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11346 ""
11347 "#"
11348 [(set_attr "length" "8")])
11349
11350 (define_insn ""
11351 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11352 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11353 (match_operand:SI 2 "u_short_cint_operand" "i")))
11354 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11355 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11356 ""
11357 "#"
11358 [(set_attr "length" "8")])
11359
11360 (define_split
11361 [(set (match_operand:CC 3 "cc_reg_operand" "")
11362 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11363 (match_operand:SI 2 "short_cint_operand" "")))
11364 (set (match_operand:SI 0 "gpc_reg_operand" "")
11365 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11366 ""
11367 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11368 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11369
11370 (define_split
11371 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11372 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11373 (match_operand:SI 2 "u_short_cint_operand" "")))
11374 (set (match_operand:SI 0 "gpc_reg_operand" "")
11375 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11376 ""
11377 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11378 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11379
11380 (define_insn "*cmpsf_internal1"
11381 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11382 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11383 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11384 "TARGET_HARD_FLOAT && TARGET_FPRS"
11385 "fcmpu %0,%1,%2"
11386 [(set_attr "type" "fpcompare")])
11387
11388 (define_insn "*cmpdf_internal1"
11389 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11390 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11391 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11392 "TARGET_HARD_FLOAT && TARGET_FPRS"
11393 "fcmpu %0,%1,%2"
11394 [(set_attr "type" "fpcompare")])
11395
11396 ;; Only need to compare second words if first words equal
11397 (define_insn "*cmptf_internal1"
11398 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11399 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11400 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11401 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
11402 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11403 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11404 [(set_attr "type" "fpcompare")
11405 (set_attr "length" "12")])
11406
11407 (define_insn_and_split "*cmptf_internal2"
11408 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11409 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11410 (match_operand:TF 2 "gpc_reg_operand" "f")))
11411 (clobber (match_scratch:DF 3 "=f"))
11412 (clobber (match_scratch:DF 4 "=f"))
11413 (clobber (match_scratch:DF 5 "=f"))
11414 (clobber (match_scratch:DF 6 "=f"))
11415 (clobber (match_scratch:DF 7 "=f"))
11416 (clobber (match_scratch:DF 8 "=f"))
11417 (clobber (match_scratch:DF 9 "=f"))
11418 (clobber (match_scratch:DF 10 "=f"))]
11419 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
11420 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11421 "#"
11422 "&& reload_completed"
11423 [(set (match_dup 3) (match_dup 13))
11424 (set (match_dup 4) (match_dup 14))
11425 (set (match_dup 9) (abs:DF (match_dup 5)))
11426 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11427 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11428 (label_ref (match_dup 11))
11429 (pc)))
11430 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11431 (set (pc) (label_ref (match_dup 12)))
11432 (match_dup 11)
11433 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11434 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11435 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11436 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
11437 (match_dup 12)]
11438 {
11439 REAL_VALUE_TYPE rv;
11440 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
11441 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
11442
11443 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11444 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11445 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11446 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11447 operands[11] = gen_label_rtx ();
11448 operands[12] = gen_label_rtx ();
11449 real_inf (&rv);
11450 operands[13] = force_const_mem (DFmode,
11451 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11452 operands[14] = force_const_mem (DFmode,
11453 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11454 DFmode));
11455 if (TARGET_TOC)
11456 {
11457 operands[13] = gen_const_mem (DFmode,
11458 create_TOC_reference (XEXP (operands[13], 0)));
11459 operands[14] = gen_const_mem (DFmode,
11460 create_TOC_reference (XEXP (operands[14], 0)));
11461 set_mem_alias_set (operands[13], get_TOC_alias_set ());
11462 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11463 }
11464 })
11465 \f
11466 ;; Now we have the scc insns. We can do some combinations because of the
11467 ;; way the machine works.
11468 ;;
11469 ;; Note that this is probably faster if we can put an insn between the
11470 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11471 ;; cases the insns below which don't use an intermediate CR field will
11472 ;; be used instead.
11473 (define_insn ""
11474 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11475 (match_operator:SI 1 "scc_comparison_operator"
11476 [(match_operand 2 "cc_reg_operand" "y")
11477 (const_int 0)]))]
11478 ""
11479 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11480 [(set (attr "type")
11481 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11482 (const_string "mfcrf")
11483 ]
11484 (const_string "mfcr")))
11485 (set_attr "length" "8")])
11486
11487 ;; Same as above, but get the GT bit.
11488 (define_insn "move_from_CR_gt_bit"
11489 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11490 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
11491 "TARGET_E500"
11492 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
11493 [(set_attr "type" "mfcr")
11494 (set_attr "length" "8")])
11495
11496 ;; Same as above, but get the OV/ORDERED bit.
11497 (define_insn "move_from_CR_ov_bit"
11498 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11499 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
11500 "TARGET_ISEL"
11501 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
11502 [(set_attr "type" "mfcr")
11503 (set_attr "length" "8")])
11504
11505 (define_insn ""
11506 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11507 (match_operator:DI 1 "scc_comparison_operator"
11508 [(match_operand 2 "cc_reg_operand" "y")
11509 (const_int 0)]))]
11510 "TARGET_POWERPC64"
11511 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11512 [(set (attr "type")
11513 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11514 (const_string "mfcrf")
11515 ]
11516 (const_string "mfcr")))
11517 (set_attr "length" "8")])
11518
11519 (define_insn ""
11520 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11521 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11522 [(match_operand 2 "cc_reg_operand" "y,y")
11523 (const_int 0)])
11524 (const_int 0)))
11525 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11526 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11527 "TARGET_32BIT"
11528 "@
11529 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
11530 #"
11531 [(set_attr "type" "delayed_compare")
11532 (set_attr "length" "8,16")])
11533
11534 (define_split
11535 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11536 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11537 [(match_operand 2 "cc_reg_operand" "")
11538 (const_int 0)])
11539 (const_int 0)))
11540 (set (match_operand:SI 3 "gpc_reg_operand" "")
11541 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11542 "TARGET_32BIT && reload_completed"
11543 [(set (match_dup 3)
11544 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11545 (set (match_dup 0)
11546 (compare:CC (match_dup 3)
11547 (const_int 0)))]
11548 "")
11549
11550 (define_insn ""
11551 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11552 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11553 [(match_operand 2 "cc_reg_operand" "y")
11554 (const_int 0)])
11555 (match_operand:SI 3 "const_int_operand" "n")))]
11556 ""
11557 "*
11558 {
11559 int is_bit = ccr_bit (operands[1], 1);
11560 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11561 int count;
11562
11563 if (is_bit >= put_bit)
11564 count = is_bit - put_bit;
11565 else
11566 count = 32 - (put_bit - is_bit);
11567
11568 operands[4] = GEN_INT (count);
11569 operands[5] = GEN_INT (put_bit);
11570
11571 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11572 }"
11573 [(set (attr "type")
11574 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11575 (const_string "mfcrf")
11576 ]
11577 (const_string "mfcr")))
11578 (set_attr "length" "8")])
11579
11580 (define_insn ""
11581 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11582 (compare:CC
11583 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11584 [(match_operand 2 "cc_reg_operand" "y,y")
11585 (const_int 0)])
11586 (match_operand:SI 3 "const_int_operand" "n,n"))
11587 (const_int 0)))
11588 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11589 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11590 (match_dup 3)))]
11591 ""
11592 "*
11593 {
11594 int is_bit = ccr_bit (operands[1], 1);
11595 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11596 int count;
11597
11598 /* Force split for non-cc0 compare. */
11599 if (which_alternative == 1)
11600 return \"#\";
11601
11602 if (is_bit >= put_bit)
11603 count = is_bit - put_bit;
11604 else
11605 count = 32 - (put_bit - is_bit);
11606
11607 operands[5] = GEN_INT (count);
11608 operands[6] = GEN_INT (put_bit);
11609
11610 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
11611 }"
11612 [(set_attr "type" "delayed_compare")
11613 (set_attr "length" "8,16")])
11614
11615 (define_split
11616 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11617 (compare:CC
11618 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11619 [(match_operand 2 "cc_reg_operand" "")
11620 (const_int 0)])
11621 (match_operand:SI 3 "const_int_operand" ""))
11622 (const_int 0)))
11623 (set (match_operand:SI 4 "gpc_reg_operand" "")
11624 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11625 (match_dup 3)))]
11626 "reload_completed"
11627 [(set (match_dup 4)
11628 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11629 (match_dup 3)))
11630 (set (match_dup 0)
11631 (compare:CC (match_dup 4)
11632 (const_int 0)))]
11633 "")
11634
11635 ;; There is a 3 cycle delay between consecutive mfcr instructions
11636 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11637
11638 (define_peephole
11639 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11640 (match_operator:SI 1 "scc_comparison_operator"
11641 [(match_operand 2 "cc_reg_operand" "y")
11642 (const_int 0)]))
11643 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11644 (match_operator:SI 4 "scc_comparison_operator"
11645 [(match_operand 5 "cc_reg_operand" "y")
11646 (const_int 0)]))]
11647 "REGNO (operands[2]) != REGNO (operands[5])"
11648 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11649 [(set_attr "type" "mfcr")
11650 (set_attr "length" "12")])
11651
11652 (define_peephole
11653 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11654 (match_operator:DI 1 "scc_comparison_operator"
11655 [(match_operand 2 "cc_reg_operand" "y")
11656 (const_int 0)]))
11657 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11658 (match_operator:DI 4 "scc_comparison_operator"
11659 [(match_operand 5 "cc_reg_operand" "y")
11660 (const_int 0)]))]
11661 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11662 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11663 [(set_attr "type" "mfcr")
11664 (set_attr "length" "12")])
11665
11666 ;; There are some scc insns that can be done directly, without a compare.
11667 ;; These are faster because they don't involve the communications between
11668 ;; the FXU and branch units. In fact, we will be replacing all of the
11669 ;; integer scc insns here or in the portable methods in emit_store_flag.
11670 ;;
11671 ;; Also support (neg (scc ..)) since that construct is used to replace
11672 ;; branches, (plus (scc ..) ..) since that construct is common and
11673 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11674 ;; cases where it is no more expensive than (neg (scc ..)).
11675
11676 ;; Have reload force a constant into a register for the simple insns that
11677 ;; otherwise won't accept constants. We do this because it is faster than
11678 ;; the cmp/mfcr sequence we would otherwise generate.
11679
11680 (define_mode_attr scc_eq_op2 [(SI "rKLI")
11681 (DI "rKJI")])
11682
11683 (define_insn_and_split "*eq<mode>"
11684 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
11685 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
11686 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
11687 "!TARGET_POWER"
11688 "#"
11689 "!TARGET_POWER"
11690 [(set (match_dup 0)
11691 (clz:GPR (match_dup 3)))
11692 (set (match_dup 0)
11693 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
11694 {
11695 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11696 {
11697 /* Use output operand as intermediate. */
11698 operands[3] = operands[0];
11699
11700 if (logical_operand (operands[2], <MODE>mode))
11701 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11702 gen_rtx_XOR (<MODE>mode,
11703 operands[1], operands[2])));
11704 else
11705 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11706 gen_rtx_PLUS (<MODE>mode, operands[1],
11707 negate_rtx (<MODE>mode,
11708 operands[2]))));
11709 }
11710 else
11711 operands[3] = operands[1];
11712
11713 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11714 })
11715
11716 (define_insn_and_split "*eq<mode>_compare"
11717 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11718 (compare:CC
11719 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
11720 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
11721 (const_int 0)))
11722 (set (match_operand:P 0 "gpc_reg_operand" "=r")
11723 (eq:P (match_dup 1) (match_dup 2)))]
11724 "!TARGET_POWER && optimize_size"
11725 "#"
11726 "!TARGET_POWER && optimize_size"
11727 [(set (match_dup 0)
11728 (clz:P (match_dup 4)))
11729 (parallel [(set (match_dup 3)
11730 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
11731 (const_int 0)))
11732 (set (match_dup 0)
11733 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
11734 {
11735 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11736 {
11737 /* Use output operand as intermediate. */
11738 operands[4] = operands[0];
11739
11740 if (logical_operand (operands[2], <MODE>mode))
11741 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11742 gen_rtx_XOR (<MODE>mode,
11743 operands[1], operands[2])));
11744 else
11745 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11746 gen_rtx_PLUS (<MODE>mode, operands[1],
11747 negate_rtx (<MODE>mode,
11748 operands[2]))));
11749 }
11750 else
11751 operands[4] = operands[1];
11752
11753 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11754 })
11755
11756 (define_insn "*eqsi_power"
11757 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11758 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11759 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
11760 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
11761 "TARGET_POWER"
11762 "@
11763 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11764 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
11765 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11766 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11767 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
11768 [(set_attr "type" "three,two,three,three,three")
11769 (set_attr "length" "12,8,12,12,12")])
11770
11771 ;; We have insns of the form shown by the first define_insn below. If
11772 ;; there is something inside the comparison operation, we must split it.
11773 (define_split
11774 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11775 (plus:SI (match_operator 1 "comparison_operator"
11776 [(match_operand:SI 2 "" "")
11777 (match_operand:SI 3
11778 "reg_or_cint_operand" "")])
11779 (match_operand:SI 4 "gpc_reg_operand" "")))
11780 (clobber (match_operand:SI 5 "register_operand" ""))]
11781 "! gpc_reg_operand (operands[2], SImode)"
11782 [(set (match_dup 5) (match_dup 2))
11783 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11784 (match_dup 4)))])
11785
11786 (define_insn "*plus_eqsi"
11787 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11788 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11789 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
11790 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11791 "TARGET_32BIT"
11792 "@
11793 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11794 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11795 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11796 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11797 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
11798 [(set_attr "type" "three,two,three,three,three")
11799 (set_attr "length" "12,8,12,12,12")])
11800
11801 (define_insn "*compare_plus_eqsi"
11802 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11803 (compare:CC
11804 (plus:SI
11805 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11806 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
11807 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11808 (const_int 0)))
11809 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11810 "TARGET_32BIT && optimize_size"
11811 "@
11812 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11813 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
11814 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11815 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11816 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11817 #
11818 #
11819 #
11820 #
11821 #"
11822 [(set_attr "type" "compare")
11823 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11824
11825 (define_split
11826 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11827 (compare:CC
11828 (plus:SI
11829 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11830 (match_operand:SI 2 "scc_eq_operand" ""))
11831 (match_operand:SI 3 "gpc_reg_operand" ""))
11832 (const_int 0)))
11833 (clobber (match_scratch:SI 4 ""))]
11834 "TARGET_32BIT && optimize_size && reload_completed"
11835 [(set (match_dup 4)
11836 (plus:SI (eq:SI (match_dup 1)
11837 (match_dup 2))
11838 (match_dup 3)))
11839 (set (match_dup 0)
11840 (compare:CC (match_dup 4)
11841 (const_int 0)))]
11842 "")
11843
11844 (define_insn "*plus_eqsi_compare"
11845 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11846 (compare:CC
11847 (plus:SI
11848 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11849 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
11850 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11851 (const_int 0)))
11852 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11853 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11854 "TARGET_32BIT && optimize_size"
11855 "@
11856 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11857 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
11858 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11859 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11860 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11861 #
11862 #
11863 #
11864 #
11865 #"
11866 [(set_attr "type" "compare")
11867 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11868
11869 (define_split
11870 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11871 (compare:CC
11872 (plus:SI
11873 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11874 (match_operand:SI 2 "scc_eq_operand" ""))
11875 (match_operand:SI 3 "gpc_reg_operand" ""))
11876 (const_int 0)))
11877 (set (match_operand:SI 0 "gpc_reg_operand" "")
11878 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11879 "TARGET_32BIT && optimize_size && reload_completed"
11880 [(set (match_dup 0)
11881 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11882 (set (match_dup 4)
11883 (compare:CC (match_dup 0)
11884 (const_int 0)))]
11885 "")
11886
11887 (define_insn "*neg_eq0<mode>"
11888 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11889 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
11890 (const_int 0))))]
11891 ""
11892 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
11893 [(set_attr "type" "two")
11894 (set_attr "length" "8")])
11895
11896 (define_insn_and_split "*neg_eq<mode>"
11897 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11898 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
11899 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
11900 ""
11901 "#"
11902 ""
11903 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
11904 {
11905 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11906 {
11907 /* Use output operand as intermediate. */
11908 operands[3] = operands[0];
11909
11910 if (logical_operand (operands[2], <MODE>mode))
11911 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11912 gen_rtx_XOR (<MODE>mode,
11913 operands[1], operands[2])));
11914 else
11915 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11916 gen_rtx_PLUS (<MODE>mode, operands[1],
11917 negate_rtx (<MODE>mode,
11918 operands[2]))));
11919 }
11920 else
11921 operands[3] = operands[1];
11922 })
11923
11924 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
11925 ;; since it nabs/sr is just as fast.
11926 (define_insn "*ne0si"
11927 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11928 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11929 (const_int 31)))
11930 (clobber (match_scratch:SI 2 "=&r"))]
11931 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
11932 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
11933 [(set_attr "type" "two")
11934 (set_attr "length" "8")])
11935
11936 (define_insn "*ne0di"
11937 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11938 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11939 (const_int 63)))
11940 (clobber (match_scratch:DI 2 "=&r"))]
11941 "TARGET_64BIT"
11942 "addic %2,%1,-1\;subfe %0,%2,%1"
11943 [(set_attr "type" "two")
11944 (set_attr "length" "8")])
11945
11946 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
11947 (define_insn "*plus_ne0si"
11948 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11949 (plus:SI (lshiftrt:SI
11950 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11951 (const_int 31))
11952 (match_operand:SI 2 "gpc_reg_operand" "r")))
11953 (clobber (match_scratch:SI 3 "=&r"))]
11954 "TARGET_32BIT"
11955 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
11956 [(set_attr "type" "two")
11957 (set_attr "length" "8")])
11958
11959 (define_insn "*plus_ne0di"
11960 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11961 (plus:DI (lshiftrt:DI
11962 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11963 (const_int 63))
11964 (match_operand:DI 2 "gpc_reg_operand" "r")))
11965 (clobber (match_scratch:DI 3 "=&r"))]
11966 "TARGET_64BIT"
11967 "addic %3,%1,-1\;addze %0,%2"
11968 [(set_attr "type" "two")
11969 (set_attr "length" "8")])
11970
11971 (define_insn "*compare_plus_ne0si"
11972 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11973 (compare:CC
11974 (plus:SI (lshiftrt:SI
11975 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11976 (const_int 31))
11977 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11978 (const_int 0)))
11979 (clobber (match_scratch:SI 3 "=&r,&r"))
11980 (clobber (match_scratch:SI 4 "=X,&r"))]
11981 "TARGET_32BIT"
11982 "@
11983 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
11984 #"
11985 [(set_attr "type" "compare")
11986 (set_attr "length" "8,12")])
11987
11988 (define_split
11989 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11990 (compare:CC
11991 (plus:SI (lshiftrt:SI
11992 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11993 (const_int 31))
11994 (match_operand:SI 2 "gpc_reg_operand" ""))
11995 (const_int 0)))
11996 (clobber (match_scratch:SI 3 ""))
11997 (clobber (match_scratch:SI 4 ""))]
11998 "TARGET_32BIT && reload_completed"
11999 [(parallel [(set (match_dup 3)
12000 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
12001 (const_int 31))
12002 (match_dup 2)))
12003 (clobber (match_dup 4))])
12004 (set (match_dup 0)
12005 (compare:CC (match_dup 3)
12006 (const_int 0)))]
12007 "")
12008
12009 (define_insn "*compare_plus_ne0di"
12010 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12011 (compare:CC
12012 (plus:DI (lshiftrt:DI
12013 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12014 (const_int 63))
12015 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12016 (const_int 0)))
12017 (clobber (match_scratch:DI 3 "=&r,&r"))]
12018 "TARGET_64BIT"
12019 "@
12020 addic %3,%1,-1\;addze. %3,%2
12021 #"
12022 [(set_attr "type" "compare")
12023 (set_attr "length" "8,12")])
12024
12025 (define_split
12026 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12027 (compare:CC
12028 (plus:DI (lshiftrt:DI
12029 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12030 (const_int 63))
12031 (match_operand:DI 2 "gpc_reg_operand" ""))
12032 (const_int 0)))
12033 (clobber (match_scratch:DI 3 ""))]
12034 "TARGET_64BIT && reload_completed"
12035 [(set (match_dup 3)
12036 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12037 (const_int 63))
12038 (match_dup 2)))
12039 (set (match_dup 0)
12040 (compare:CC (match_dup 3)
12041 (const_int 0)))]
12042 "")
12043
12044 (define_insn "*plus_ne0si_compare"
12045 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12046 (compare:CC
12047 (plus:SI (lshiftrt:SI
12048 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12049 (const_int 31))
12050 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12051 (const_int 0)))
12052 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12053 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12054 (match_dup 2)))
12055 (clobber (match_scratch:SI 3 "=&r,&r"))]
12056 "TARGET_32BIT"
12057 "@
12058 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
12059 #"
12060 [(set_attr "type" "compare")
12061 (set_attr "length" "8,12")])
12062
12063 (define_split
12064 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12065 (compare:CC
12066 (plus:SI (lshiftrt:SI
12067 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12068 (const_int 31))
12069 (match_operand:SI 2 "gpc_reg_operand" ""))
12070 (const_int 0)))
12071 (set (match_operand:SI 0 "gpc_reg_operand" "")
12072 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12073 (match_dup 2)))
12074 (clobber (match_scratch:SI 3 ""))]
12075 "TARGET_32BIT && reload_completed"
12076 [(parallel [(set (match_dup 0)
12077 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12078 (match_dup 2)))
12079 (clobber (match_dup 3))])
12080 (set (match_dup 4)
12081 (compare:CC (match_dup 0)
12082 (const_int 0)))]
12083 "")
12084
12085 (define_insn "*plus_ne0di_compare"
12086 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12087 (compare:CC
12088 (plus:DI (lshiftrt:DI
12089 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12090 (const_int 63))
12091 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12092 (const_int 0)))
12093 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12094 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12095 (match_dup 2)))
12096 (clobber (match_scratch:DI 3 "=&r,&r"))]
12097 "TARGET_64BIT"
12098 "@
12099 addic %3,%1,-1\;addze. %0,%2
12100 #"
12101 [(set_attr "type" "compare")
12102 (set_attr "length" "8,12")])
12103
12104 (define_split
12105 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12106 (compare:CC
12107 (plus:DI (lshiftrt:DI
12108 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12109 (const_int 63))
12110 (match_operand:DI 2 "gpc_reg_operand" ""))
12111 (const_int 0)))
12112 (set (match_operand:DI 0 "gpc_reg_operand" "")
12113 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12114 (match_dup 2)))
12115 (clobber (match_scratch:DI 3 ""))]
12116 "TARGET_64BIT && reload_completed"
12117 [(parallel [(set (match_dup 0)
12118 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12119 (match_dup 2)))
12120 (clobber (match_dup 3))])
12121 (set (match_dup 4)
12122 (compare:CC (match_dup 0)
12123 (const_int 0)))]
12124 "")
12125
12126 (define_insn ""
12127 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12128 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12129 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12130 (clobber (match_scratch:SI 3 "=r,X"))]
12131 "TARGET_POWER"
12132 "@
12133 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
12134 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
12135 [(set_attr "length" "12")])
12136
12137 (define_insn ""
12138 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12139 (compare:CC
12140 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12141 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12142 (const_int 0)))
12143 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12144 (le:SI (match_dup 1) (match_dup 2)))
12145 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
12146 "TARGET_POWER"
12147 "@
12148 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12149 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
12150 #
12151 #"
12152 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
12153 (set_attr "length" "12,12,16,16")])
12154
12155 (define_split
12156 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12157 (compare:CC
12158 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12159 (match_operand:SI 2 "reg_or_short_operand" ""))
12160 (const_int 0)))
12161 (set (match_operand:SI 0 "gpc_reg_operand" "")
12162 (le:SI (match_dup 1) (match_dup 2)))
12163 (clobber (match_scratch:SI 3 ""))]
12164 "TARGET_POWER && reload_completed"
12165 [(parallel [(set (match_dup 0)
12166 (le:SI (match_dup 1) (match_dup 2)))
12167 (clobber (match_dup 3))])
12168 (set (match_dup 4)
12169 (compare:CC (match_dup 0)
12170 (const_int 0)))]
12171 "")
12172
12173 (define_insn ""
12174 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12175 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12176 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
12177 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12178 "TARGET_POWER"
12179 "@
12180 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12181 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
12182 [(set_attr "length" "12")])
12183
12184 (define_insn ""
12185 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12186 (compare:CC
12187 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12188 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12189 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12190 (const_int 0)))
12191 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12192 "TARGET_POWER"
12193 "@
12194 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12195 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12196 #
12197 #"
12198 [(set_attr "type" "compare")
12199 (set_attr "length" "12,12,16,16")])
12200
12201 (define_split
12202 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12203 (compare:CC
12204 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12205 (match_operand:SI 2 "reg_or_short_operand" ""))
12206 (match_operand:SI 3 "gpc_reg_operand" ""))
12207 (const_int 0)))
12208 (clobber (match_scratch:SI 4 ""))]
12209 "TARGET_POWER && reload_completed"
12210 [(set (match_dup 4)
12211 (plus:SI (le:SI (match_dup 1) (match_dup 2))
12212 (match_dup 3)))
12213 (set (match_dup 0)
12214 (compare:CC (match_dup 4)
12215 (const_int 0)))]
12216 "")
12217
12218 (define_insn ""
12219 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12220 (compare:CC
12221 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12222 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12223 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12224 (const_int 0)))
12225 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12226 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12227 "TARGET_POWER"
12228 "@
12229 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12230 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
12231 #
12232 #"
12233 [(set_attr "type" "compare")
12234 (set_attr "length" "12,12,16,16")])
12235
12236 (define_split
12237 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12238 (compare:CC
12239 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12240 (match_operand:SI 2 "reg_or_short_operand" ""))
12241 (match_operand:SI 3 "gpc_reg_operand" ""))
12242 (const_int 0)))
12243 (set (match_operand:SI 0 "gpc_reg_operand" "")
12244 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12245 "TARGET_POWER && reload_completed"
12246 [(set (match_dup 0)
12247 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12248 (set (match_dup 4)
12249 (compare:CC (match_dup 0)
12250 (const_int 0)))]
12251 "")
12252
12253 (define_insn ""
12254 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12255 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12256 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
12257 "TARGET_POWER"
12258 "@
12259 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12260 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
12261 [(set_attr "length" "12")])
12262
12263 (define_insn "*leu<mode>"
12264 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12265 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12266 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12267 ""
12268 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12269 [(set_attr "type" "three")
12270 (set_attr "length" "12")])
12271
12272 (define_insn "*leu<mode>_compare"
12273 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12274 (compare:CC
12275 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12276 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12277 (const_int 0)))
12278 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12279 (leu:P (match_dup 1) (match_dup 2)))]
12280 ""
12281 "@
12282 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12283 #"
12284 [(set_attr "type" "compare")
12285 (set_attr "length" "12,16")])
12286
12287 (define_split
12288 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12289 (compare:CC
12290 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12291 (match_operand:P 2 "reg_or_short_operand" ""))
12292 (const_int 0)))
12293 (set (match_operand:P 0 "gpc_reg_operand" "")
12294 (leu:P (match_dup 1) (match_dup 2)))]
12295 "reload_completed"
12296 [(set (match_dup 0)
12297 (leu:P (match_dup 1) (match_dup 2)))
12298 (set (match_dup 3)
12299 (compare:CC (match_dup 0)
12300 (const_int 0)))]
12301 "")
12302
12303 (define_insn "*plus_leu<mode>"
12304 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12305 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12306 (match_operand:P 2 "reg_or_short_operand" "rI"))
12307 (match_operand:P 3 "gpc_reg_operand" "r")))]
12308 ""
12309 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12310 [(set_attr "type" "two")
12311 (set_attr "length" "8")])
12312
12313 (define_insn ""
12314 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12315 (compare:CC
12316 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12317 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12318 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12319 (const_int 0)))
12320 (clobber (match_scratch:SI 4 "=&r,&r"))]
12321 "TARGET_32BIT"
12322 "@
12323 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12324 #"
12325 [(set_attr "type" "compare")
12326 (set_attr "length" "8,12")])
12327
12328 (define_split
12329 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12330 (compare:CC
12331 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12332 (match_operand:SI 2 "reg_or_short_operand" ""))
12333 (match_operand:SI 3 "gpc_reg_operand" ""))
12334 (const_int 0)))
12335 (clobber (match_scratch:SI 4 ""))]
12336 "TARGET_32BIT && reload_completed"
12337 [(set (match_dup 4)
12338 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12339 (match_dup 3)))
12340 (set (match_dup 0)
12341 (compare:CC (match_dup 4)
12342 (const_int 0)))]
12343 "")
12344
12345 (define_insn ""
12346 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12347 (compare:CC
12348 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12349 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12350 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12351 (const_int 0)))
12352 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12353 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12354 "TARGET_32BIT"
12355 "@
12356 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12357 #"
12358 [(set_attr "type" "compare")
12359 (set_attr "length" "8,12")])
12360
12361 (define_split
12362 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12363 (compare:CC
12364 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12365 (match_operand:SI 2 "reg_or_short_operand" ""))
12366 (match_operand:SI 3 "gpc_reg_operand" ""))
12367 (const_int 0)))
12368 (set (match_operand:SI 0 "gpc_reg_operand" "")
12369 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12370 "TARGET_32BIT && reload_completed"
12371 [(set (match_dup 0)
12372 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12373 (set (match_dup 4)
12374 (compare:CC (match_dup 0)
12375 (const_int 0)))]
12376 "")
12377
12378 (define_insn "*neg_leu<mode>"
12379 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12380 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12381 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12382 ""
12383 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12384 [(set_attr "type" "three")
12385 (set_attr "length" "12")])
12386
12387 (define_insn "*and_neg_leu<mode>"
12388 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12389 (and:P (neg:P
12390 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12391 (match_operand:P 2 "reg_or_short_operand" "rI")))
12392 (match_operand:P 3 "gpc_reg_operand" "r")))]
12393 ""
12394 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12395 [(set_attr "type" "three")
12396 (set_attr "length" "12")])
12397
12398 (define_insn ""
12399 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12400 (compare:CC
12401 (and:SI (neg:SI
12402 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12403 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12404 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12405 (const_int 0)))
12406 (clobber (match_scratch:SI 4 "=&r,&r"))]
12407 "TARGET_32BIT"
12408 "@
12409 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12410 #"
12411 [(set_attr "type" "compare")
12412 (set_attr "length" "12,16")])
12413
12414 (define_split
12415 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12416 (compare:CC
12417 (and:SI (neg:SI
12418 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12419 (match_operand:SI 2 "reg_or_short_operand" "")))
12420 (match_operand:SI 3 "gpc_reg_operand" ""))
12421 (const_int 0)))
12422 (clobber (match_scratch:SI 4 ""))]
12423 "TARGET_32BIT && reload_completed"
12424 [(set (match_dup 4)
12425 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12426 (match_dup 3)))
12427 (set (match_dup 0)
12428 (compare:CC (match_dup 4)
12429 (const_int 0)))]
12430 "")
12431
12432 (define_insn ""
12433 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12434 (compare:CC
12435 (and:SI (neg:SI
12436 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12437 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12438 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12439 (const_int 0)))
12440 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12441 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12442 "TARGET_32BIT"
12443 "@
12444 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12445 #"
12446 [(set_attr "type" "compare")
12447 (set_attr "length" "12,16")])
12448
12449 (define_split
12450 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12451 (compare:CC
12452 (and:SI (neg:SI
12453 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12454 (match_operand:SI 2 "reg_or_short_operand" "")))
12455 (match_operand:SI 3 "gpc_reg_operand" ""))
12456 (const_int 0)))
12457 (set (match_operand:SI 0 "gpc_reg_operand" "")
12458 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12459 "TARGET_32BIT && reload_completed"
12460 [(set (match_dup 0)
12461 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12462 (match_dup 3)))
12463 (set (match_dup 4)
12464 (compare:CC (match_dup 0)
12465 (const_int 0)))]
12466 "")
12467
12468 (define_insn ""
12469 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12470 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12471 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12472 "TARGET_POWER"
12473 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12474 [(set_attr "length" "12")])
12475
12476 (define_insn ""
12477 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12478 (compare:CC
12479 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12480 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12481 (const_int 0)))
12482 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12483 (lt:SI (match_dup 1) (match_dup 2)))]
12484 "TARGET_POWER"
12485 "@
12486 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12487 #"
12488 [(set_attr "type" "delayed_compare")
12489 (set_attr "length" "12,16")])
12490
12491 (define_split
12492 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12493 (compare:CC
12494 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12495 (match_operand:SI 2 "reg_or_short_operand" ""))
12496 (const_int 0)))
12497 (set (match_operand:SI 0 "gpc_reg_operand" "")
12498 (lt:SI (match_dup 1) (match_dup 2)))]
12499 "TARGET_POWER && reload_completed"
12500 [(set (match_dup 0)
12501 (lt:SI (match_dup 1) (match_dup 2)))
12502 (set (match_dup 3)
12503 (compare:CC (match_dup 0)
12504 (const_int 0)))]
12505 "")
12506
12507 (define_insn ""
12508 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12509 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12510 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12511 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12512 "TARGET_POWER"
12513 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12514 [(set_attr "length" "12")])
12515
12516 (define_insn ""
12517 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12518 (compare:CC
12519 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12520 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12521 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12522 (const_int 0)))
12523 (clobber (match_scratch:SI 4 "=&r,&r"))]
12524 "TARGET_POWER"
12525 "@
12526 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12527 #"
12528 [(set_attr "type" "compare")
12529 (set_attr "length" "12,16")])
12530
12531 (define_split
12532 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12533 (compare:CC
12534 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12535 (match_operand:SI 2 "reg_or_short_operand" ""))
12536 (match_operand:SI 3 "gpc_reg_operand" ""))
12537 (const_int 0)))
12538 (clobber (match_scratch:SI 4 ""))]
12539 "TARGET_POWER && reload_completed"
12540 [(set (match_dup 4)
12541 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
12542 (match_dup 3)))
12543 (set (match_dup 0)
12544 (compare:CC (match_dup 4)
12545 (const_int 0)))]
12546 "")
12547
12548 (define_insn ""
12549 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12550 (compare:CC
12551 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12552 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12553 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12554 (const_int 0)))
12555 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12556 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12557 "TARGET_POWER"
12558 "@
12559 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12560 #"
12561 [(set_attr "type" "compare")
12562 (set_attr "length" "12,16")])
12563
12564 (define_split
12565 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12566 (compare:CC
12567 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12568 (match_operand:SI 2 "reg_or_short_operand" ""))
12569 (match_operand:SI 3 "gpc_reg_operand" ""))
12570 (const_int 0)))
12571 (set (match_operand:SI 0 "gpc_reg_operand" "")
12572 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12573 "TARGET_POWER && reload_completed"
12574 [(set (match_dup 0)
12575 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12576 (set (match_dup 4)
12577 (compare:CC (match_dup 0)
12578 (const_int 0)))]
12579 "")
12580
12581 (define_insn ""
12582 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12583 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12584 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12585 "TARGET_POWER"
12586 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12587 [(set_attr "length" "12")])
12588
12589 (define_insn_and_split "*ltu<mode>"
12590 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12591 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12592 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12593 ""
12594 "#"
12595 ""
12596 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12597 (set (match_dup 0) (neg:P (match_dup 0)))]
12598 "")
12599
12600 (define_insn_and_split "*ltu<mode>_compare"
12601 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12602 (compare:CC
12603 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12604 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12605 (const_int 0)))
12606 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12607 (ltu:P (match_dup 1) (match_dup 2)))]
12608 ""
12609 "#"
12610 ""
12611 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12612 (parallel [(set (match_dup 3)
12613 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12614 (set (match_dup 0) (neg:P (match_dup 0)))])]
12615 "")
12616
12617 (define_insn_and_split "*plus_ltu<mode>"
12618 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
12619 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12620 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12621 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
12622 ""
12623 "#"
12624 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12625 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12626 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
12627 "")
12628
12629 (define_insn_and_split "*plus_ltu<mode>_compare"
12630 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12631 (compare:CC
12632 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12633 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12634 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
12635 (const_int 0)))
12636 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12637 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
12638 ""
12639 "#"
12640 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12641 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12642 (parallel [(set (match_dup 4)
12643 (compare:CC (minus:P (match_dup 3) (match_dup 0))
12644 (const_int 0)))
12645 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
12646 "")
12647
12648 (define_insn "*neg_ltu<mode>"
12649 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12650 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12651 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
12652 ""
12653 "@
12654 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12655 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12656 [(set_attr "type" "two")
12657 (set_attr "length" "8")])
12658
12659 (define_insn ""
12660 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12661 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12662 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12663 (clobber (match_scratch:SI 3 "=r"))]
12664 "TARGET_POWER"
12665 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
12666 [(set_attr "length" "12")])
12667
12668 (define_insn ""
12669 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12670 (compare:CC
12671 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12672 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12673 (const_int 0)))
12674 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12675 (ge:SI (match_dup 1) (match_dup 2)))
12676 (clobber (match_scratch:SI 3 "=r,r"))]
12677 "TARGET_POWER"
12678 "@
12679 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12680 #"
12681 [(set_attr "type" "compare")
12682 (set_attr "length" "12,16")])
12683
12684 (define_split
12685 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12686 (compare:CC
12687 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12688 (match_operand:SI 2 "reg_or_short_operand" ""))
12689 (const_int 0)))
12690 (set (match_operand:SI 0 "gpc_reg_operand" "")
12691 (ge:SI (match_dup 1) (match_dup 2)))
12692 (clobber (match_scratch:SI 3 ""))]
12693 "TARGET_POWER && reload_completed"
12694 [(parallel [(set (match_dup 0)
12695 (ge:SI (match_dup 1) (match_dup 2)))
12696 (clobber (match_dup 3))])
12697 (set (match_dup 4)
12698 (compare:CC (match_dup 0)
12699 (const_int 0)))]
12700 "")
12701
12702 (define_insn ""
12703 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12704 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12705 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12706 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12707 "TARGET_POWER"
12708 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12709 [(set_attr "length" "12")])
12710
12711 (define_insn ""
12712 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12713 (compare:CC
12714 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12715 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12716 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12717 (const_int 0)))
12718 (clobber (match_scratch:SI 4 "=&r,&r"))]
12719 "TARGET_POWER"
12720 "@
12721 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12722 #"
12723 [(set_attr "type" "compare")
12724 (set_attr "length" "12,16")])
12725
12726 (define_split
12727 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12728 (compare:CC
12729 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12730 (match_operand:SI 2 "reg_or_short_operand" ""))
12731 (match_operand:SI 3 "gpc_reg_operand" ""))
12732 (const_int 0)))
12733 (clobber (match_scratch:SI 4 ""))]
12734 "TARGET_POWER && reload_completed"
12735 [(set (match_dup 4)
12736 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
12737 (match_dup 3)))
12738 (set (match_dup 0)
12739 (compare:CC (match_dup 4)
12740 (const_int 0)))]
12741 "")
12742
12743 (define_insn ""
12744 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12745 (compare:CC
12746 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12747 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12748 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12749 (const_int 0)))
12750 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12751 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12752 "TARGET_POWER"
12753 "@
12754 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12755 #"
12756 [(set_attr "type" "compare")
12757 (set_attr "length" "12,16")])
12758
12759 (define_split
12760 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12761 (compare:CC
12762 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12763 (match_operand:SI 2 "reg_or_short_operand" ""))
12764 (match_operand:SI 3 "gpc_reg_operand" ""))
12765 (const_int 0)))
12766 (set (match_operand:SI 0 "gpc_reg_operand" "")
12767 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12768 "TARGET_POWER && reload_completed"
12769 [(set (match_dup 0)
12770 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12771 (set (match_dup 4)
12772 (compare:CC (match_dup 0)
12773 (const_int 0)))]
12774 "")
12775
12776 (define_insn ""
12777 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12778 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12779 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12780 "TARGET_POWER"
12781 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
12782 [(set_attr "length" "12")])
12783
12784 (define_insn "*geu<mode>"
12785 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12786 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12787 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12788 ""
12789 "@
12790 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12791 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12792 [(set_attr "type" "three")
12793 (set_attr "length" "12")])
12794
12795 (define_insn "*geu<mode>_compare"
12796 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12797 (compare:CC
12798 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12799 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12800 (const_int 0)))
12801 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12802 (geu:P (match_dup 1) (match_dup 2)))]
12803 ""
12804 "@
12805 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12806 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12807 #
12808 #"
12809 [(set_attr "type" "compare")
12810 (set_attr "length" "12,12,16,16")])
12811
12812 (define_split
12813 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12814 (compare:CC
12815 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
12816 (match_operand:P 2 "reg_or_neg_short_operand" ""))
12817 (const_int 0)))
12818 (set (match_operand:P 0 "gpc_reg_operand" "")
12819 (geu:P (match_dup 1) (match_dup 2)))]
12820 "reload_completed"
12821 [(set (match_dup 0)
12822 (geu:P (match_dup 1) (match_dup 2)))
12823 (set (match_dup 3)
12824 (compare:CC (match_dup 0)
12825 (const_int 0)))]
12826 "")
12827
12828 (define_insn "*plus_geu<mode>"
12829 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12830 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12831 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12832 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12833 ""
12834 "@
12835 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
12836 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
12837 [(set_attr "type" "two")
12838 (set_attr "length" "8")])
12839
12840 (define_insn ""
12841 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12842 (compare:CC
12843 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12844 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12845 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12846 (const_int 0)))
12847 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12848 "TARGET_32BIT"
12849 "@
12850 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
12851 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
12852 #
12853 #"
12854 [(set_attr "type" "compare")
12855 (set_attr "length" "8,8,12,12")])
12856
12857 (define_split
12858 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12859 (compare:CC
12860 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12861 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12862 (match_operand:SI 3 "gpc_reg_operand" ""))
12863 (const_int 0)))
12864 (clobber (match_scratch:SI 4 ""))]
12865 "TARGET_32BIT && reload_completed"
12866 [(set (match_dup 4)
12867 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12868 (match_dup 3)))
12869 (set (match_dup 0)
12870 (compare:CC (match_dup 4)
12871 (const_int 0)))]
12872 "")
12873
12874 (define_insn ""
12875 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12876 (compare:CC
12877 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12878 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12879 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12880 (const_int 0)))
12881 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12882 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12883 "TARGET_32BIT"
12884 "@
12885 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
12886 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
12887 #
12888 #"
12889 [(set_attr "type" "compare")
12890 (set_attr "length" "8,8,12,12")])
12891
12892 (define_split
12893 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12894 (compare:CC
12895 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12896 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12897 (match_operand:SI 3 "gpc_reg_operand" ""))
12898 (const_int 0)))
12899 (set (match_operand:SI 0 "gpc_reg_operand" "")
12900 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12901 "TARGET_32BIT && reload_completed"
12902 [(set (match_dup 0)
12903 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12904 (set (match_dup 4)
12905 (compare:CC (match_dup 0)
12906 (const_int 0)))]
12907 "")
12908
12909 (define_insn "*neg_geu<mode>"
12910 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12911 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12912 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
12913 ""
12914 "@
12915 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
12916 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
12917 [(set_attr "type" "three")
12918 (set_attr "length" "12")])
12919
12920 (define_insn "*and_neg_geu<mode>"
12921 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12922 (and:P (neg:P
12923 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12924 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
12925 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12926 ""
12927 "@
12928 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
12929 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12930 [(set_attr "type" "three")
12931 (set_attr "length" "12")])
12932
12933 (define_insn ""
12934 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12935 (compare:CC
12936 (and:SI (neg:SI
12937 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12938 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12939 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12940 (const_int 0)))
12941 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12942 "TARGET_32BIT"
12943 "@
12944 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12945 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12946 #
12947 #"
12948 [(set_attr "type" "compare")
12949 (set_attr "length" "12,12,16,16")])
12950
12951 (define_split
12952 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12953 (compare:CC
12954 (and:SI (neg:SI
12955 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12956 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12957 (match_operand:SI 3 "gpc_reg_operand" ""))
12958 (const_int 0)))
12959 (clobber (match_scratch:SI 4 ""))]
12960 "TARGET_32BIT && reload_completed"
12961 [(set (match_dup 4)
12962 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12963 (match_dup 3)))
12964 (set (match_dup 0)
12965 (compare:CC (match_dup 4)
12966 (const_int 0)))]
12967 "")
12968
12969 (define_insn ""
12970 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12971 (compare:CC
12972 (and:SI (neg:SI
12973 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12974 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12975 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12976 (const_int 0)))
12977 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12978 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12979 "TARGET_32BIT"
12980 "@
12981 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12982 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12983 #
12984 #"
12985 [(set_attr "type" "compare")
12986 (set_attr "length" "12,12,16,16")])
12987
12988 (define_split
12989 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12990 (compare:CC
12991 (and:SI (neg:SI
12992 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12993 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12994 (match_operand:SI 3 "gpc_reg_operand" ""))
12995 (const_int 0)))
12996 (set (match_operand:SI 0 "gpc_reg_operand" "")
12997 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12998 "TARGET_32BIT && reload_completed"
12999 [(set (match_dup 0)
13000 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13001 (set (match_dup 4)
13002 (compare:CC (match_dup 0)
13003 (const_int 0)))]
13004 "")
13005
13006 (define_insn ""
13007 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13008 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13009 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13010 "TARGET_POWER"
13011 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13012 [(set_attr "length" "12")])
13013
13014 (define_insn ""
13015 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13016 (compare:CC
13017 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13018 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13019 (const_int 0)))
13020 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13021 (gt:SI (match_dup 1) (match_dup 2)))]
13022 "TARGET_POWER"
13023 "@
13024 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13025 #"
13026 [(set_attr "type" "delayed_compare")
13027 (set_attr "length" "12,16")])
13028
13029 (define_split
13030 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13031 (compare:CC
13032 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13033 (match_operand:SI 2 "reg_or_short_operand" ""))
13034 (const_int 0)))
13035 (set (match_operand:SI 0 "gpc_reg_operand" "")
13036 (gt:SI (match_dup 1) (match_dup 2)))]
13037 "TARGET_POWER && reload_completed"
13038 [(set (match_dup 0)
13039 (gt:SI (match_dup 1) (match_dup 2)))
13040 (set (match_dup 3)
13041 (compare:CC (match_dup 0)
13042 (const_int 0)))]
13043 "")
13044
13045 (define_insn "*plus_gt0<mode>"
13046 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13047 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13048 (const_int 0))
13049 (match_operand:P 2 "gpc_reg_operand" "r")))]
13050 ""
13051 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13052 [(set_attr "type" "three")
13053 (set_attr "length" "12")])
13054
13055 (define_insn ""
13056 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13057 (compare:CC
13058 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13059 (const_int 0))
13060 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13061 (const_int 0)))
13062 (clobber (match_scratch:SI 3 "=&r,&r"))]
13063 "TARGET_32BIT"
13064 "@
13065 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13066 #"
13067 [(set_attr "type" "compare")
13068 (set_attr "length" "12,16")])
13069
13070 (define_split
13071 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13072 (compare:CC
13073 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13074 (const_int 0))
13075 (match_operand:SI 2 "gpc_reg_operand" ""))
13076 (const_int 0)))
13077 (clobber (match_scratch:SI 3 ""))]
13078 "TARGET_32BIT && reload_completed"
13079 [(set (match_dup 3)
13080 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13081 (match_dup 2)))
13082 (set (match_dup 0)
13083 (compare:CC (match_dup 3)
13084 (const_int 0)))]
13085 "")
13086
13087 (define_insn ""
13088 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13089 (compare:CC
13090 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13091 (const_int 0))
13092 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13093 (const_int 0)))
13094 (clobber (match_scratch:DI 3 "=&r,&r"))]
13095 "TARGET_64BIT"
13096 "@
13097 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13098 #"
13099 [(set_attr "type" "compare")
13100 (set_attr "length" "12,16")])
13101
13102 (define_split
13103 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13104 (compare:CC
13105 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13106 (const_int 0))
13107 (match_operand:DI 2 "gpc_reg_operand" ""))
13108 (const_int 0)))
13109 (clobber (match_scratch:DI 3 ""))]
13110 "TARGET_64BIT && reload_completed"
13111 [(set (match_dup 3)
13112 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13113 (match_dup 2)))
13114 (set (match_dup 0)
13115 (compare:CC (match_dup 3)
13116 (const_int 0)))]
13117 "")
13118
13119 (define_insn ""
13120 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13121 (compare:CC
13122 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13123 (const_int 0))
13124 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13125 (const_int 0)))
13126 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13127 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13128 "TARGET_32BIT"
13129 "@
13130 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13131 #"
13132 [(set_attr "type" "compare")
13133 (set_attr "length" "12,16")])
13134
13135 (define_split
13136 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13137 (compare:CC
13138 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13139 (const_int 0))
13140 (match_operand:SI 2 "gpc_reg_operand" ""))
13141 (const_int 0)))
13142 (set (match_operand:SI 0 "gpc_reg_operand" "")
13143 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13144 "TARGET_32BIT && reload_completed"
13145 [(set (match_dup 0)
13146 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13147 (set (match_dup 3)
13148 (compare:CC (match_dup 0)
13149 (const_int 0)))]
13150 "")
13151
13152 (define_insn ""
13153 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13154 (compare:CC
13155 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13156 (const_int 0))
13157 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13158 (const_int 0)))
13159 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13160 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13161 "TARGET_64BIT"
13162 "@
13163 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13164 #"
13165 [(set_attr "type" "compare")
13166 (set_attr "length" "12,16")])
13167
13168 (define_split
13169 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13170 (compare:CC
13171 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13172 (const_int 0))
13173 (match_operand:DI 2 "gpc_reg_operand" ""))
13174 (const_int 0)))
13175 (set (match_operand:DI 0 "gpc_reg_operand" "")
13176 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13177 "TARGET_64BIT && reload_completed"
13178 [(set (match_dup 0)
13179 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13180 (set (match_dup 3)
13181 (compare:CC (match_dup 0)
13182 (const_int 0)))]
13183 "")
13184
13185 (define_insn ""
13186 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13187 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13188 (match_operand:SI 2 "reg_or_short_operand" "r"))
13189 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13190 "TARGET_POWER"
13191 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13192 [(set_attr "length" "12")])
13193
13194 (define_insn ""
13195 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13196 (compare:CC
13197 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13198 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13199 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13200 (const_int 0)))
13201 (clobber (match_scratch:SI 4 "=&r,&r"))]
13202 "TARGET_POWER"
13203 "@
13204 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13205 #"
13206 [(set_attr "type" "compare")
13207 (set_attr "length" "12,16")])
13208
13209 (define_split
13210 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13211 (compare:CC
13212 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13213 (match_operand:SI 2 "reg_or_short_operand" ""))
13214 (match_operand:SI 3 "gpc_reg_operand" ""))
13215 (const_int 0)))
13216 (clobber (match_scratch:SI 4 ""))]
13217 "TARGET_POWER && reload_completed"
13218 [(set (match_dup 4)
13219 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13220 (set (match_dup 0)
13221 (compare:CC (match_dup 4)
13222 (const_int 0)))]
13223 "")
13224
13225 (define_insn ""
13226 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13227 (compare:CC
13228 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13229 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13230 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13231 (const_int 0)))
13232 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13233 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13234 "TARGET_POWER"
13235 "@
13236 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13237 #"
13238 [(set_attr "type" "compare")
13239 (set_attr "length" "12,16")])
13240
13241 (define_split
13242 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13243 (compare:CC
13244 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13245 (match_operand:SI 2 "reg_or_short_operand" ""))
13246 (match_operand:SI 3 "gpc_reg_operand" ""))
13247 (const_int 0)))
13248 (set (match_operand:SI 0 "gpc_reg_operand" "")
13249 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13250 "TARGET_POWER && reload_completed"
13251 [(set (match_dup 0)
13252 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13253 (set (match_dup 4)
13254 (compare:CC (match_dup 0)
13255 (const_int 0)))]
13256 "")
13257
13258 (define_insn ""
13259 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13260 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13261 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13262 "TARGET_POWER"
13263 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13264 [(set_attr "length" "12")])
13265
13266 (define_insn_and_split "*gtu<mode>"
13267 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13268 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13269 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13270 ""
13271 "#"
13272 ""
13273 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13274 (set (match_dup 0) (neg:P (match_dup 0)))]
13275 "")
13276
13277 (define_insn_and_split "*gtu<mode>_compare"
13278 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13279 (compare:CC
13280 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13281 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13282 (const_int 0)))
13283 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13284 (gtu:P (match_dup 1) (match_dup 2)))]
13285 ""
13286 "#"
13287 ""
13288 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13289 (parallel [(set (match_dup 3)
13290 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13291 (set (match_dup 0) (neg:P (match_dup 0)))])]
13292 "")
13293
13294 (define_insn_and_split "*plus_gtu<mode>"
13295 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13296 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13297 (match_operand:P 2 "reg_or_short_operand" "rI"))
13298 (match_operand:P 3 "reg_or_short_operand" "rI")))]
13299 ""
13300 "#"
13301 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13302 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13303 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13304 "")
13305
13306 (define_insn_and_split "*plus_gtu<mode>_compare"
13307 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13308 (compare:CC
13309 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13310 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13311 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13312 (const_int 0)))
13313 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13314 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13315 ""
13316 "#"
13317 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13318 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13319 (parallel [(set (match_dup 4)
13320 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13321 (const_int 0)))
13322 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13323 "")
13324
13325 (define_insn "*neg_gtu<mode>"
13326 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13327 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13328 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13329 ""
13330 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13331 [(set_attr "type" "two")
13332 (set_attr "length" "8")])
13333
13334 \f
13335 ;; Define both directions of branch and return. If we need a reload
13336 ;; register, we'd rather use CR0 since it is much easier to copy a
13337 ;; register CC value to there.
13338
13339 (define_insn ""
13340 [(set (pc)
13341 (if_then_else (match_operator 1 "branch_comparison_operator"
13342 [(match_operand 2
13343 "cc_reg_operand" "y")
13344 (const_int 0)])
13345 (label_ref (match_operand 0 "" ""))
13346 (pc)))]
13347 ""
13348 "*
13349 {
13350 return output_cbranch (operands[1], \"%l0\", 0, insn);
13351 }"
13352 [(set_attr "type" "branch")])
13353
13354 (define_insn ""
13355 [(set (pc)
13356 (if_then_else (match_operator 0 "branch_comparison_operator"
13357 [(match_operand 1
13358 "cc_reg_operand" "y")
13359 (const_int 0)])
13360 (return)
13361 (pc)))]
13362 "direct_return ()"
13363 "*
13364 {
13365 return output_cbranch (operands[0], NULL, 0, insn);
13366 }"
13367 [(set_attr "type" "jmpreg")
13368 (set_attr "length" "4")])
13369
13370 (define_insn ""
13371 [(set (pc)
13372 (if_then_else (match_operator 1 "branch_comparison_operator"
13373 [(match_operand 2
13374 "cc_reg_operand" "y")
13375 (const_int 0)])
13376 (pc)
13377 (label_ref (match_operand 0 "" ""))))]
13378 ""
13379 "*
13380 {
13381 return output_cbranch (operands[1], \"%l0\", 1, insn);
13382 }"
13383 [(set_attr "type" "branch")])
13384
13385 (define_insn ""
13386 [(set (pc)
13387 (if_then_else (match_operator 0 "branch_comparison_operator"
13388 [(match_operand 1
13389 "cc_reg_operand" "y")
13390 (const_int 0)])
13391 (pc)
13392 (return)))]
13393 "direct_return ()"
13394 "*
13395 {
13396 return output_cbranch (operands[0], NULL, 1, insn);
13397 }"
13398 [(set_attr "type" "jmpreg")
13399 (set_attr "length" "4")])
13400
13401 ;; Logic on condition register values.
13402
13403 ; This pattern matches things like
13404 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13405 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13406 ; (const_int 1)))
13407 ; which are generated by the branch logic.
13408 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13409
13410 (define_insn "*cceq_ior_compare"
13411 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13412 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13413 [(match_operator:SI 2
13414 "branch_positive_comparison_operator"
13415 [(match_operand 3
13416 "cc_reg_operand" "y,y")
13417 (const_int 0)])
13418 (match_operator:SI 4
13419 "branch_positive_comparison_operator"
13420 [(match_operand 5
13421 "cc_reg_operand" "0,y")
13422 (const_int 0)])])
13423 (const_int 1)))]
13424 ""
13425 "cr%q1 %E0,%j2,%j4"
13426 [(set_attr "type" "cr_logical,delayed_cr")])
13427
13428 ; Why is the constant -1 here, but 1 in the previous pattern?
13429 ; Because ~1 has all but the low bit set.
13430 (define_insn ""
13431 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13432 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13433 [(not:SI (match_operator:SI 2
13434 "branch_positive_comparison_operator"
13435 [(match_operand 3
13436 "cc_reg_operand" "y,y")
13437 (const_int 0)]))
13438 (match_operator:SI 4
13439 "branch_positive_comparison_operator"
13440 [(match_operand 5
13441 "cc_reg_operand" "0,y")
13442 (const_int 0)])])
13443 (const_int -1)))]
13444 ""
13445 "cr%q1 %E0,%j2,%j4"
13446 [(set_attr "type" "cr_logical,delayed_cr")])
13447
13448 (define_insn "*cceq_rev_compare"
13449 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13450 (compare:CCEQ (match_operator:SI 1
13451 "branch_positive_comparison_operator"
13452 [(match_operand 2
13453 "cc_reg_operand" "0,y")
13454 (const_int 0)])
13455 (const_int 0)))]
13456 ""
13457 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
13458 [(set_attr "type" "cr_logical,delayed_cr")])
13459
13460 ;; If we are comparing the result of two comparisons, this can be done
13461 ;; using creqv or crxor.
13462
13463 (define_insn_and_split ""
13464 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13465 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13466 [(match_operand 2 "cc_reg_operand" "y")
13467 (const_int 0)])
13468 (match_operator 3 "branch_comparison_operator"
13469 [(match_operand 4 "cc_reg_operand" "y")
13470 (const_int 0)])))]
13471 ""
13472 "#"
13473 ""
13474 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13475 (match_dup 5)))]
13476 "
13477 {
13478 int positive_1, positive_2;
13479
13480 positive_1 = branch_positive_comparison_operator (operands[1],
13481 GET_MODE (operands[1]));
13482 positive_2 = branch_positive_comparison_operator (operands[3],
13483 GET_MODE (operands[3]));
13484
13485 if (! positive_1)
13486 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13487 GET_CODE (operands[1])),
13488 SImode,
13489 operands[2], const0_rtx);
13490 else if (GET_MODE (operands[1]) != SImode)
13491 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13492 operands[2], const0_rtx);
13493
13494 if (! positive_2)
13495 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13496 GET_CODE (operands[3])),
13497 SImode,
13498 operands[4], const0_rtx);
13499 else if (GET_MODE (operands[3]) != SImode)
13500 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13501 operands[4], const0_rtx);
13502
13503 if (positive_1 == positive_2)
13504 {
13505 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13506 operands[5] = constm1_rtx;
13507 }
13508 else
13509 {
13510 operands[5] = const1_rtx;
13511 }
13512 }")
13513
13514 ;; Unconditional branch and return.
13515
13516 (define_insn "jump"
13517 [(set (pc)
13518 (label_ref (match_operand 0 "" "")))]
13519 ""
13520 "b %l0"
13521 [(set_attr "type" "branch")])
13522
13523 (define_insn "return"
13524 [(return)]
13525 "direct_return ()"
13526 "{br|blr}"
13527 [(set_attr "type" "jmpreg")])
13528
13529 (define_expand "indirect_jump"
13530 [(set (pc) (match_operand 0 "register_operand" ""))])
13531
13532 (define_insn "*indirect_jump<mode>"
13533 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
13534 ""
13535 "@
13536 bctr
13537 {br|blr}"
13538 [(set_attr "type" "jmpreg")])
13539
13540 ;; Table jump for switch statements:
13541 (define_expand "tablejump"
13542 [(use (match_operand 0 "" ""))
13543 (use (label_ref (match_operand 1 "" "")))]
13544 ""
13545 "
13546 {
13547 if (TARGET_32BIT)
13548 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13549 else
13550 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13551 DONE;
13552 }")
13553
13554 (define_expand "tablejumpsi"
13555 [(set (match_dup 3)
13556 (plus:SI (match_operand:SI 0 "" "")
13557 (match_dup 2)))
13558 (parallel [(set (pc) (match_dup 3))
13559 (use (label_ref (match_operand 1 "" "")))])]
13560 "TARGET_32BIT"
13561 "
13562 { operands[0] = force_reg (SImode, operands[0]);
13563 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13564 operands[3] = gen_reg_rtx (SImode);
13565 }")
13566
13567 (define_expand "tablejumpdi"
13568 [(set (match_dup 4)
13569 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
13570 (set (match_dup 3)
13571 (plus:DI (match_dup 4)
13572 (match_dup 2)))
13573 (parallel [(set (pc) (match_dup 3))
13574 (use (label_ref (match_operand 1 "" "")))])]
13575 "TARGET_64BIT"
13576 "
13577 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13578 operands[3] = gen_reg_rtx (DImode);
13579 operands[4] = gen_reg_rtx (DImode);
13580 }")
13581
13582 (define_insn "*tablejump<mode>_internal1"
13583 [(set (pc)
13584 (match_operand:P 0 "register_operand" "c,*l"))
13585 (use (label_ref (match_operand 1 "" "")))]
13586 ""
13587 "@
13588 bctr
13589 {br|blr}"
13590 [(set_attr "type" "jmpreg")])
13591
13592 (define_insn "nop"
13593 [(const_int 0)]
13594 ""
13595 "{cror 0,0,0|nop}")
13596 \f
13597 ;; Define the subtract-one-and-jump insns, starting with the template
13598 ;; so loop.c knows what to generate.
13599
13600 (define_expand "doloop_end"
13601 [(use (match_operand 0 "" "")) ; loop pseudo
13602 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13603 (use (match_operand 2 "" "")) ; max iterations
13604 (use (match_operand 3 "" "")) ; loop level
13605 (use (match_operand 4 "" ""))] ; label
13606 ""
13607 "
13608 {
13609 /* Only use this on innermost loops. */
13610 if (INTVAL (operands[3]) > 1)
13611 FAIL;
13612 if (TARGET_64BIT)
13613 {
13614 if (GET_MODE (operands[0]) != DImode)
13615 FAIL;
13616 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13617 }
13618 else
13619 {
13620 if (GET_MODE (operands[0]) != SImode)
13621 FAIL;
13622 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13623 }
13624 DONE;
13625 }")
13626
13627 (define_expand "ctr<mode>"
13628 [(parallel [(set (pc)
13629 (if_then_else (ne (match_operand:P 0 "register_operand" "")
13630 (const_int 1))
13631 (label_ref (match_operand 1 "" ""))
13632 (pc)))
13633 (set (match_dup 0)
13634 (plus:P (match_dup 0)
13635 (const_int -1)))
13636 (clobber (match_scratch:CC 2 ""))
13637 (clobber (match_scratch:P 3 ""))])]
13638 ""
13639 "")
13640
13641 ;; We need to be able to do this for any operand, including MEM, or we
13642 ;; will cause reload to blow up since we don't allow output reloads on
13643 ;; JUMP_INSNs.
13644 ;; For the length attribute to be calculated correctly, the
13645 ;; label MUST be operand 0.
13646
13647 (define_insn "*ctr<mode>_internal1"
13648 [(set (pc)
13649 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13650 (const_int 1))
13651 (label_ref (match_operand 0 "" ""))
13652 (pc)))
13653 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13654 (plus:P (match_dup 1)
13655 (const_int -1)))
13656 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13657 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13658 ""
13659 "*
13660 {
13661 if (which_alternative != 0)
13662 return \"#\";
13663 else if (get_attr_length (insn) == 4)
13664 return \"{bdn|bdnz} %l0\";
13665 else
13666 return \"bdz $+8\;b %l0\";
13667 }"
13668 [(set_attr "type" "branch")
13669 (set_attr "length" "*,12,16,16")])
13670
13671 (define_insn "*ctr<mode>_internal2"
13672 [(set (pc)
13673 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13674 (const_int 1))
13675 (pc)
13676 (label_ref (match_operand 0 "" ""))))
13677 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13678 (plus:P (match_dup 1)
13679 (const_int -1)))
13680 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13681 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13682 ""
13683 "*
13684 {
13685 if (which_alternative != 0)
13686 return \"#\";
13687 else if (get_attr_length (insn) == 4)
13688 return \"bdz %l0\";
13689 else
13690 return \"{bdn|bdnz} $+8\;b %l0\";
13691 }"
13692 [(set_attr "type" "branch")
13693 (set_attr "length" "*,12,16,16")])
13694
13695 ;; Similar but use EQ
13696
13697 (define_insn "*ctr<mode>_internal5"
13698 [(set (pc)
13699 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13700 (const_int 1))
13701 (label_ref (match_operand 0 "" ""))
13702 (pc)))
13703 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13704 (plus:P (match_dup 1)
13705 (const_int -1)))
13706 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13707 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13708 ""
13709 "*
13710 {
13711 if (which_alternative != 0)
13712 return \"#\";
13713 else if (get_attr_length (insn) == 4)
13714 return \"bdz %l0\";
13715 else
13716 return \"{bdn|bdnz} $+8\;b %l0\";
13717 }"
13718 [(set_attr "type" "branch")
13719 (set_attr "length" "*,12,16,16")])
13720
13721 (define_insn "*ctr<mode>_internal6"
13722 [(set (pc)
13723 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13724 (const_int 1))
13725 (pc)
13726 (label_ref (match_operand 0 "" ""))))
13727 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13728 (plus:P (match_dup 1)
13729 (const_int -1)))
13730 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13731 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13732 ""
13733 "*
13734 {
13735 if (which_alternative != 0)
13736 return \"#\";
13737 else if (get_attr_length (insn) == 4)
13738 return \"{bdn|bdnz} %l0\";
13739 else
13740 return \"bdz $+8\;b %l0\";
13741 }"
13742 [(set_attr "type" "branch")
13743 (set_attr "length" "*,12,16,16")])
13744
13745 ;; Now the splitters if we could not allocate the CTR register
13746
13747 (define_split
13748 [(set (pc)
13749 (if_then_else (match_operator 2 "comparison_operator"
13750 [(match_operand:P 1 "gpc_reg_operand" "")
13751 (const_int 1)])
13752 (match_operand 5 "" "")
13753 (match_operand 6 "" "")))
13754 (set (match_operand:P 0 "gpc_reg_operand" "")
13755 (plus:P (match_dup 1) (const_int -1)))
13756 (clobber (match_scratch:CC 3 ""))
13757 (clobber (match_scratch:P 4 ""))]
13758 "reload_completed"
13759 [(parallel [(set (match_dup 3)
13760 (compare:CC (plus:P (match_dup 1)
13761 (const_int -1))
13762 (const_int 0)))
13763 (set (match_dup 0)
13764 (plus:P (match_dup 1)
13765 (const_int -1)))])
13766 (set (pc) (if_then_else (match_dup 7)
13767 (match_dup 5)
13768 (match_dup 6)))]
13769 "
13770 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13771 operands[3], const0_rtx); }")
13772
13773 (define_split
13774 [(set (pc)
13775 (if_then_else (match_operator 2 "comparison_operator"
13776 [(match_operand:P 1 "gpc_reg_operand" "")
13777 (const_int 1)])
13778 (match_operand 5 "" "")
13779 (match_operand 6 "" "")))
13780 (set (match_operand:P 0 "nonimmediate_operand" "")
13781 (plus:P (match_dup 1) (const_int -1)))
13782 (clobber (match_scratch:CC 3 ""))
13783 (clobber (match_scratch:P 4 ""))]
13784 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
13785 [(parallel [(set (match_dup 3)
13786 (compare:CC (plus:P (match_dup 1)
13787 (const_int -1))
13788 (const_int 0)))
13789 (set (match_dup 4)
13790 (plus:P (match_dup 1)
13791 (const_int -1)))])
13792 (set (match_dup 0)
13793 (match_dup 4))
13794 (set (pc) (if_then_else (match_dup 7)
13795 (match_dup 5)
13796 (match_dup 6)))]
13797 "
13798 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13799 operands[3], const0_rtx); }")
13800 \f
13801 (define_insn "trap"
13802 [(trap_if (const_int 1) (const_int 0))]
13803 ""
13804 "{t 31,0,0|trap}")
13805
13806 (define_expand "conditional_trap"
13807 [(trap_if (match_operator 0 "trap_comparison_operator"
13808 [(match_dup 2) (match_dup 3)])
13809 (match_operand 1 "const_int_operand" ""))]
13810 ""
13811 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
13812 operands[2] = rs6000_compare_op0;
13813 operands[3] = rs6000_compare_op1;")
13814
13815 (define_insn ""
13816 [(trap_if (match_operator 0 "trap_comparison_operator"
13817 [(match_operand:GPR 1 "register_operand" "r")
13818 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
13819 (const_int 0))]
13820 ""
13821 "{t|t<wd>}%V0%I2 %1,%2")
13822 \f
13823 ;; Insns related to generating the function prologue and epilogue.
13824
13825 (define_expand "prologue"
13826 [(use (const_int 0))]
13827 "TARGET_SCHED_PROLOG"
13828 "
13829 {
13830 rs6000_emit_prologue ();
13831 DONE;
13832 }")
13833
13834 (define_insn "*movesi_from_cr_one"
13835 [(match_parallel 0 "mfcr_operation"
13836 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13837 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
13838 (match_operand 3 "immediate_operand" "n")]
13839 UNSPEC_MOVESI_FROM_CR))])]
13840 "TARGET_MFCRF"
13841 "*
13842 {
13843 int mask = 0;
13844 int i;
13845 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13846 {
13847 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13848 operands[4] = GEN_INT (mask);
13849 output_asm_insn (\"mfcr %1,%4\", operands);
13850 }
13851 return \"\";
13852 }"
13853 [(set_attr "type" "mfcrf")])
13854
13855 (define_insn "movesi_from_cr"
13856 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13857 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
13858 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
13859 UNSPEC_MOVESI_FROM_CR))]
13860 ""
13861 "mfcr %0"
13862 [(set_attr "type" "mfcr")])
13863
13864 (define_insn "*stmw"
13865 [(match_parallel 0 "stmw_operation"
13866 [(set (match_operand:SI 1 "memory_operand" "=m")
13867 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13868 "TARGET_MULTIPLE"
13869 "{stm|stmw} %2,%1"
13870 [(set_attr "type" "store_ux")])
13871
13872 (define_insn "*save_fpregs_<mode>"
13873 [(match_parallel 0 "any_parallel_operand"
13874 [(clobber (match_operand:P 1 "register_operand" "=l"))
13875 (use (match_operand:P 2 "call_operand" "s"))
13876 (set (match_operand:DF 3 "memory_operand" "=m")
13877 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
13878 ""
13879 "bl %z2"
13880 [(set_attr "type" "branch")
13881 (set_attr "length" "4")])
13882
13883 ; These are to explain that changes to the stack pointer should
13884 ; not be moved over stores to stack memory.
13885 (define_insn "stack_tie"
13886 [(set (match_operand:BLK 0 "memory_operand" "+m")
13887 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
13888 ""
13889 ""
13890 [(set_attr "length" "0")])
13891
13892
13893 (define_expand "epilogue"
13894 [(use (const_int 0))]
13895 "TARGET_SCHED_PROLOG"
13896 "
13897 {
13898 rs6000_emit_epilogue (FALSE);
13899 DONE;
13900 }")
13901
13902 ; On some processors, doing the mtcrf one CC register at a time is
13903 ; faster (like on the 604e). On others, doing them all at once is
13904 ; faster; for instance, on the 601 and 750.
13905
13906 (define_expand "movsi_to_cr_one"
13907 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13908 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13909 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
13910 ""
13911 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
13912
13913 (define_insn "*movsi_to_cr"
13914 [(match_parallel 0 "mtcrf_operation"
13915 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
13916 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
13917 (match_operand 3 "immediate_operand" "n")]
13918 UNSPEC_MOVESI_TO_CR))])]
13919 ""
13920 "*
13921 {
13922 int mask = 0;
13923 int i;
13924 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13925 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13926 operands[4] = GEN_INT (mask);
13927 return \"mtcrf %4,%2\";
13928 }"
13929 [(set_attr "type" "mtcr")])
13930
13931 (define_insn "*mtcrfsi"
13932 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13933 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13934 (match_operand 2 "immediate_operand" "n")]
13935 UNSPEC_MOVESI_TO_CR))]
13936 "GET_CODE (operands[0]) == REG
13937 && CR_REGNO_P (REGNO (operands[0]))
13938 && GET_CODE (operands[2]) == CONST_INT
13939 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
13940 "mtcrf %R0,%1"
13941 [(set_attr "type" "mtcr")])
13942
13943 ; The load-multiple instructions have similar properties.
13944 ; Note that "load_multiple" is a name known to the machine-independent
13945 ; code that actually corresponds to the PowerPC load-string.
13946
13947 (define_insn "*lmw"
13948 [(match_parallel 0 "lmw_operation"
13949 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13950 (match_operand:SI 2 "memory_operand" "m"))])]
13951 "TARGET_MULTIPLE"
13952 "{lm|lmw} %1,%2"
13953 [(set_attr "type" "load_ux")])
13954
13955 (define_insn "*return_internal_<mode>"
13956 [(return)
13957 (use (match_operand:P 0 "register_operand" "lc"))]
13958 ""
13959 "b%T0"
13960 [(set_attr "type" "jmpreg")])
13961
13962 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
13963 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
13964
13965 (define_insn "*return_and_restore_fpregs_<mode>"
13966 [(match_parallel 0 "any_parallel_operand"
13967 [(return)
13968 (use (match_operand:P 1 "register_operand" "l"))
13969 (use (match_operand:P 2 "call_operand" "s"))
13970 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
13971 (match_operand:DF 4 "memory_operand" "m"))])]
13972 ""
13973 "b %z2")
13974
13975 ; This is used in compiling the unwind routines.
13976 (define_expand "eh_return"
13977 [(use (match_operand 0 "general_operand" ""))]
13978 ""
13979 "
13980 {
13981 if (TARGET_32BIT)
13982 emit_insn (gen_eh_set_lr_si (operands[0]));
13983 else
13984 emit_insn (gen_eh_set_lr_di (operands[0]));
13985 DONE;
13986 }")
13987
13988 ; We can't expand this before we know where the link register is stored.
13989 (define_insn "eh_set_lr_<mode>"
13990 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
13991 UNSPECV_EH_RR)
13992 (clobber (match_scratch:P 1 "=&b"))]
13993 ""
13994 "#")
13995
13996 (define_split
13997 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
13998 (clobber (match_scratch 1 ""))]
13999 "reload_completed"
14000 [(const_int 0)]
14001 "
14002 {
14003 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14004 DONE;
14005 }")
14006
14007 (define_insn "prefetch"
14008 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
14009 (match_operand:SI 1 "const_int_operand" "n")
14010 (match_operand:SI 2 "const_int_operand" "n"))]
14011 "TARGET_POWERPC"
14012 "*
14013 {
14014 if (GET_CODE (operands[0]) == REG)
14015 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14016 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14017 }"
14018 [(set_attr "type" "load")])
14019 \f
14020
14021 (include "sync.md")
14022 (include "altivec.md")
14023 (include "spe.md")
Mirror of https://gcc.gnu.org/git/gcc.git