1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 2, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to the
20 ;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
21 ;; MA 02110-1301, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
30 [(UNSPEC_FRSP 0) ; frsp for POWER machines
31 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
32 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
33 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
35 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
37 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
38 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
41 (UNSPEC_MOVESI_FROM_CR 19)
42 (UNSPEC_MOVESI_TO_CR 20)
44 (UNSPEC_TLSDTPRELHA 22)
45 (UNSPEC_TLSDTPRELLO 23)
46 (UNSPEC_TLSGOTDTPREL 24)
48 (UNSPEC_TLSTPRELHA 26)
49 (UNSPEC_TLSTPRELLO 27)
50 (UNSPEC_TLSGOTTPREL 28)
52 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
53 (UNSPEC_MV_CR_GT 31) ; move_from_CR_eq_bit
70 ;; UNSPEC_VOLATILE usage
75 (UNSPECV_LL 1) ; load-locked
76 (UNSPECV_SC 2) ; store-conditional
77 (UNSPECV_EH_RR 9) ; eh_reg_restore
80 ;; Define an insn type attribute. This is used in function unit delay
82 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c"
83 (const_string "integer"))
86 ; '(pc)' in the following doesn't include the instruction itself; it is
87 ; calculated as if the instruction had zero size.
88 (define_attr "length" ""
89 (if_then_else (eq_attr "type" "branch")
90 (if_then_else (and (ge (minus (match_dup 0) (pc))
92 (lt (minus (match_dup 0) (pc))
98 ;; Processor type -- this attribute must exactly match the processor_type
99 ;; enumeration in rs6000.h.
101 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5"
102 (const (symbol_ref "rs6000_cpu_attr")))
104 (automata_option "ndfa")
117 (include "power4.md")
118 (include "power5.md")
120 (include "predicates.md")
122 (include "darwin.md")
127 ; This mode macro allows :GPR to be used to indicate the allowable size
128 ; of whole values in GPRs.
129 (define_mode_macro GPR [SI (DI "TARGET_POWERPC64")])
131 ; Any supported integer mode.
132 (define_mode_macro INT [QI HI SI DI TI])
134 ; Any supported integer mode that fits in one register.
135 (define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")])
137 ; extend modes for DImode
138 (define_mode_macro QHSI [QI HI SI])
140 ; SImode or DImode, even if DImode doesn't fit in GPRs.
141 (define_mode_macro SDI [SI DI])
143 ; The size of a pointer. Also, the size of the value that a record-condition
144 ; (one with a '.') will compare.
145 (define_mode_macro P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
147 ; Any hardware-supported floating-point mode
148 (define_mode_macro FP [(SF "TARGET_HARD_FLOAT")
149 (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
150 (TF "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
151 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128")])
153 ; Various instructions that come in SI and DI forms.
154 ; A generic w/d attribute, for things like cmpw/cmpd.
155 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
158 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
161 ;; Start with fixed-point load and store insns. Here we put only the more
162 ;; complex forms. Basic data transfer is done later.
164 (define_expand "zero_extend<mode>di2"
165 [(set (match_operand:DI 0 "gpc_reg_operand" "")
166 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
170 (define_insn "*zero_extend<mode>di2_internal1"
171 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
172 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
176 rldicl %0,%1,0,<dbits>"
177 [(set_attr "type" "load,*")])
179 (define_insn "*zero_extend<mode>di2_internal2"
180 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
181 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
183 (clobber (match_scratch:DI 2 "=r,r"))]
186 rldicl. %2,%1,0,<dbits>
188 [(set_attr "type" "compare")
189 (set_attr "length" "4,8")])
192 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
193 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
195 (clobber (match_scratch:DI 2 ""))]
196 "TARGET_POWERPC64 && reload_completed"
198 (zero_extend:DI (match_dup 1)))
200 (compare:CC (match_dup 2)
204 (define_insn "*zero_extend<mode>di2_internal3"
205 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
206 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
208 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
209 (zero_extend:DI (match_dup 1)))]
212 rldicl. %0,%1,0,<dbits>
214 [(set_attr "type" "compare")
215 (set_attr "length" "4,8")])
218 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
219 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
221 (set (match_operand:DI 0 "gpc_reg_operand" "")
222 (zero_extend:DI (match_dup 1)))]
223 "TARGET_POWERPC64 && reload_completed"
225 (zero_extend:DI (match_dup 1)))
227 (compare:CC (match_dup 0)
231 (define_insn "extendqidi2"
232 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
233 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
238 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
239 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
241 (clobber (match_scratch:DI 2 "=r,r"))]
246 [(set_attr "type" "compare")
247 (set_attr "length" "4,8")])
250 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
251 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
253 (clobber (match_scratch:DI 2 ""))]
254 "TARGET_POWERPC64 && reload_completed"
256 (sign_extend:DI (match_dup 1)))
258 (compare:CC (match_dup 2)
263 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
264 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
266 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
267 (sign_extend:DI (match_dup 1)))]
272 [(set_attr "type" "compare")
273 (set_attr "length" "4,8")])
276 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
277 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
279 (set (match_operand:DI 0 "gpc_reg_operand" "")
280 (sign_extend:DI (match_dup 1)))]
281 "TARGET_POWERPC64 && reload_completed"
283 (sign_extend:DI (match_dup 1)))
285 (compare:CC (match_dup 0)
289 (define_expand "extendhidi2"
290 [(set (match_operand:DI 0 "gpc_reg_operand" "")
291 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
296 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
297 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
302 [(set_attr "type" "load_ext,*")])
305 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
306 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
308 (clobber (match_scratch:DI 2 "=r,r"))]
313 [(set_attr "type" "compare")
314 (set_attr "length" "4,8")])
317 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
318 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
320 (clobber (match_scratch:DI 2 ""))]
321 "TARGET_POWERPC64 && reload_completed"
323 (sign_extend:DI (match_dup 1)))
325 (compare:CC (match_dup 2)
330 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
331 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
333 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
334 (sign_extend:DI (match_dup 1)))]
339 [(set_attr "type" "compare")
340 (set_attr "length" "4,8")])
343 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
344 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
346 (set (match_operand:DI 0 "gpc_reg_operand" "")
347 (sign_extend:DI (match_dup 1)))]
348 "TARGET_POWERPC64 && reload_completed"
350 (sign_extend:DI (match_dup 1)))
352 (compare:CC (match_dup 0)
356 (define_expand "extendsidi2"
357 [(set (match_operand:DI 0 "gpc_reg_operand" "")
358 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
363 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
364 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
369 [(set_attr "type" "load_ext,*")])
372 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
373 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
375 (clobber (match_scratch:DI 2 "=r,r"))]
380 [(set_attr "type" "compare")
381 (set_attr "length" "4,8")])
384 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
385 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
387 (clobber (match_scratch:DI 2 ""))]
388 "TARGET_POWERPC64 && reload_completed"
390 (sign_extend:DI (match_dup 1)))
392 (compare:CC (match_dup 2)
397 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
398 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
400 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
401 (sign_extend:DI (match_dup 1)))]
406 [(set_attr "type" "compare")
407 (set_attr "length" "4,8")])
410 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
411 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
413 (set (match_operand:DI 0 "gpc_reg_operand" "")
414 (sign_extend:DI (match_dup 1)))]
415 "TARGET_POWERPC64 && reload_completed"
417 (sign_extend:DI (match_dup 1)))
419 (compare:CC (match_dup 0)
423 (define_expand "zero_extendqisi2"
424 [(set (match_operand:SI 0 "gpc_reg_operand" "")
425 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
430 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
431 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
435 {rlinm|rlwinm} %0,%1,0,0xff"
436 [(set_attr "type" "load,*")])
439 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
440 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
442 (clobber (match_scratch:SI 2 "=r,r"))]
445 {andil.|andi.} %2,%1,0xff
447 [(set_attr "type" "compare")
448 (set_attr "length" "4,8")])
451 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
452 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
454 (clobber (match_scratch:SI 2 ""))]
457 (zero_extend:SI (match_dup 1)))
459 (compare:CC (match_dup 2)
464 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
465 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
467 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
468 (zero_extend:SI (match_dup 1)))]
471 {andil.|andi.} %0,%1,0xff
473 [(set_attr "type" "compare")
474 (set_attr "length" "4,8")])
477 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
478 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
480 (set (match_operand:SI 0 "gpc_reg_operand" "")
481 (zero_extend:SI (match_dup 1)))]
484 (zero_extend:SI (match_dup 1)))
486 (compare:CC (match_dup 0)
490 (define_expand "extendqisi2"
491 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
492 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
497 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
498 else if (TARGET_POWER)
499 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
501 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
505 (define_insn "extendqisi2_ppc"
506 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
507 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
512 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
513 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
515 (clobber (match_scratch:SI 2 "=r,r"))]
520 [(set_attr "type" "compare")
521 (set_attr "length" "4,8")])
524 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
525 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
527 (clobber (match_scratch:SI 2 ""))]
528 "TARGET_POWERPC && reload_completed"
530 (sign_extend:SI (match_dup 1)))
532 (compare:CC (match_dup 2)
537 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
538 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
540 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
541 (sign_extend:SI (match_dup 1)))]
546 [(set_attr "type" "compare")
547 (set_attr "length" "4,8")])
550 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
551 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
553 (set (match_operand:SI 0 "gpc_reg_operand" "")
554 (sign_extend:SI (match_dup 1)))]
555 "TARGET_POWERPC && reload_completed"
557 (sign_extend:SI (match_dup 1)))
559 (compare:CC (match_dup 0)
563 (define_expand "extendqisi2_power"
564 [(parallel [(set (match_dup 2)
565 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
567 (clobber (scratch:SI))])
568 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
569 (ashiftrt:SI (match_dup 2)
571 (clobber (scratch:SI))])]
574 { operands[1] = gen_lowpart (SImode, operands[1]);
575 operands[2] = gen_reg_rtx (SImode); }")
577 (define_expand "extendqisi2_no_power"
579 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
581 (set (match_operand:SI 0 "gpc_reg_operand" "")
582 (ashiftrt:SI (match_dup 2)
584 "! TARGET_POWER && ! TARGET_POWERPC"
586 { operands[1] = gen_lowpart (SImode, operands[1]);
587 operands[2] = gen_reg_rtx (SImode); }")
589 (define_expand "zero_extendqihi2"
590 [(set (match_operand:HI 0 "gpc_reg_operand" "")
591 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
596 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
597 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
601 {rlinm|rlwinm} %0,%1,0,0xff"
602 [(set_attr "type" "load,*")])
605 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
606 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
608 (clobber (match_scratch:HI 2 "=r,r"))]
611 {andil.|andi.} %2,%1,0xff
613 [(set_attr "type" "compare")
614 (set_attr "length" "4,8")])
617 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
618 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
620 (clobber (match_scratch:HI 2 ""))]
623 (zero_extend:HI (match_dup 1)))
625 (compare:CC (match_dup 2)
630 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
631 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
633 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
634 (zero_extend:HI (match_dup 1)))]
637 {andil.|andi.} %0,%1,0xff
639 [(set_attr "type" "compare")
640 (set_attr "length" "4,8")])
643 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
644 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
646 (set (match_operand:HI 0 "gpc_reg_operand" "")
647 (zero_extend:HI (match_dup 1)))]
650 (zero_extend:HI (match_dup 1)))
652 (compare:CC (match_dup 0)
656 (define_expand "extendqihi2"
657 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
658 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
663 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
664 else if (TARGET_POWER)
665 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
667 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
671 (define_insn "extendqihi2_ppc"
672 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
673 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
678 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
679 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
681 (clobber (match_scratch:HI 2 "=r,r"))]
686 [(set_attr "type" "compare")
687 (set_attr "length" "4,8")])
690 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
691 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
693 (clobber (match_scratch:HI 2 ""))]
694 "TARGET_POWERPC && reload_completed"
696 (sign_extend:HI (match_dup 1)))
698 (compare:CC (match_dup 2)
703 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
704 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
706 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
707 (sign_extend:HI (match_dup 1)))]
712 [(set_attr "type" "compare")
713 (set_attr "length" "4,8")])
716 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
717 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
719 (set (match_operand:HI 0 "gpc_reg_operand" "")
720 (sign_extend:HI (match_dup 1)))]
721 "TARGET_POWERPC && reload_completed"
723 (sign_extend:HI (match_dup 1)))
725 (compare:CC (match_dup 0)
729 (define_expand "extendqihi2_power"
730 [(parallel [(set (match_dup 2)
731 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
733 (clobber (scratch:SI))])
734 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
735 (ashiftrt:SI (match_dup 2)
737 (clobber (scratch:SI))])]
740 { operands[0] = gen_lowpart (SImode, operands[0]);
741 operands[1] = gen_lowpart (SImode, operands[1]);
742 operands[2] = gen_reg_rtx (SImode); }")
744 (define_expand "extendqihi2_no_power"
746 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
748 (set (match_operand:HI 0 "gpc_reg_operand" "")
749 (ashiftrt:SI (match_dup 2)
751 "! TARGET_POWER && ! TARGET_POWERPC"
753 { operands[0] = gen_lowpart (SImode, operands[0]);
754 operands[1] = gen_lowpart (SImode, operands[1]);
755 operands[2] = gen_reg_rtx (SImode); }")
757 (define_expand "zero_extendhisi2"
758 [(set (match_operand:SI 0 "gpc_reg_operand" "")
759 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
764 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
765 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
769 {rlinm|rlwinm} %0,%1,0,0xffff"
770 [(set_attr "type" "load,*")])
773 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
774 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
776 (clobber (match_scratch:SI 2 "=r,r"))]
779 {andil.|andi.} %2,%1,0xffff
781 [(set_attr "type" "compare")
782 (set_attr "length" "4,8")])
785 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
786 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
788 (clobber (match_scratch:SI 2 ""))]
791 (zero_extend:SI (match_dup 1)))
793 (compare:CC (match_dup 2)
798 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
799 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
801 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
802 (zero_extend:SI (match_dup 1)))]
805 {andil.|andi.} %0,%1,0xffff
807 [(set_attr "type" "compare")
808 (set_attr "length" "4,8")])
811 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
812 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
814 (set (match_operand:SI 0 "gpc_reg_operand" "")
815 (zero_extend:SI (match_dup 1)))]
818 (zero_extend:SI (match_dup 1)))
820 (compare:CC (match_dup 0)
824 (define_expand "extendhisi2"
825 [(set (match_operand:SI 0 "gpc_reg_operand" "")
826 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
831 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
832 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
837 [(set_attr "type" "load_ext,*")])
840 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
841 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
843 (clobber (match_scratch:SI 2 "=r,r"))]
848 [(set_attr "type" "compare")
849 (set_attr "length" "4,8")])
852 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
853 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
855 (clobber (match_scratch:SI 2 ""))]
858 (sign_extend:SI (match_dup 1)))
860 (compare:CC (match_dup 2)
865 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
866 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
868 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
869 (sign_extend:SI (match_dup 1)))]
874 [(set_attr "type" "compare")
875 (set_attr "length" "4,8")])
878 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
879 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
881 (set (match_operand:SI 0 "gpc_reg_operand" "")
882 (sign_extend:SI (match_dup 1)))]
885 (sign_extend:SI (match_dup 1)))
887 (compare:CC (match_dup 0)
891 ;; Fixed-point arithmetic insns.
893 (define_expand "add<mode>3"
894 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
895 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
896 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
900 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
902 if (non_short_cint_operand (operands[2], DImode))
905 else if (GET_CODE (operands[2]) == CONST_INT
906 && ! add_operand (operands[2], <MODE>mode))
908 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
909 ? operands[0] : gen_reg_rtx (<MODE>mode));
911 HOST_WIDE_INT val = INTVAL (operands[2]);
912 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
913 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
915 if (<MODE>mode == DImode && !CONST_OK_FOR_LETTER_P (rest, 'L'))
918 /* The ordering here is important for the prolog expander.
919 When space is allocated from the stack, adding 'low' first may
920 produce a temporary deallocation (which would be bad). */
921 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
922 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
927 ;; Discourage ai/addic because of carry but provide it in an alternative
928 ;; allowing register zero as source.
929 (define_insn "*add<mode>3_internal1"
930 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
931 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
932 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
936 {cal %0,%2(%1)|addi %0,%1,%2}
938 {cau|addis} %0,%1,%v2"
939 [(set_attr "length" "4,4,4,4")])
941 (define_insn "addsi3_high"
942 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
943 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
944 (high:SI (match_operand 2 "" ""))))]
945 "TARGET_MACHO && !TARGET_64BIT"
946 "{cau|addis} %0,%1,ha16(%2)"
947 [(set_attr "length" "4")])
949 (define_insn "*add<mode>3_internal2"
950 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
951 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
952 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
954 (clobber (match_scratch:P 3 "=r,r,r,r"))]
958 {ai.|addic.} %3,%1,%2
961 [(set_attr "type" "fast_compare,compare,compare,compare")
962 (set_attr "length" "4,4,8,8")])
965 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
966 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
967 (match_operand:GPR 2 "reg_or_short_operand" ""))
969 (clobber (match_scratch:GPR 3 ""))]
972 (plus:GPR (match_dup 1)
975 (compare:CC (match_dup 3)
979 (define_insn "*add<mode>3_internal3"
980 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
981 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
982 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
984 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
985 (plus:P (match_dup 1)
990 {ai.|addic.} %0,%1,%2
993 [(set_attr "type" "fast_compare,compare,compare,compare")
994 (set_attr "length" "4,4,8,8")])
997 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
998 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
999 (match_operand:P 2 "reg_or_short_operand" ""))
1001 (set (match_operand:P 0 "gpc_reg_operand" "")
1002 (plus:P (match_dup 1) (match_dup 2)))]
1005 (plus:P (match_dup 1)
1008 (compare:CC (match_dup 0)
1012 ;; Split an add that we can't do in one insn into two insns, each of which
1013 ;; does one 16-bit part. This is used by combine. Note that the low-order
1014 ;; add should be last in case the result gets used in an address.
1017 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1018 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1019 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1021 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1022 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1025 HOST_WIDE_INT val = INTVAL (operands[2]);
1026 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1027 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1029 operands[4] = GEN_INT (low);
1030 if (<MODE>mode == SImode || CONST_OK_FOR_LETTER_P (rest, 'L'))
1031 operands[3] = GEN_INT (rest);
1032 else if (! no_new_pseudos)
1034 operands[3] = gen_reg_rtx (DImode);
1035 emit_move_insn (operands[3], operands[2]);
1036 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1043 (define_insn "one_cmpl<mode>2"
1044 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1045 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1050 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1051 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1053 (clobber (match_scratch:P 2 "=r,r"))]
1058 [(set_attr "type" "compare")
1059 (set_attr "length" "4,8")])
1062 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1063 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1065 (clobber (match_scratch:P 2 ""))]
1068 (not:P (match_dup 1)))
1070 (compare:CC (match_dup 2)
1075 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1076 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1078 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1079 (not:P (match_dup 1)))]
1084 [(set_attr "type" "compare")
1085 (set_attr "length" "4,8")])
1088 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1089 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1091 (set (match_operand:P 0 "gpc_reg_operand" "")
1092 (not:P (match_dup 1)))]
1095 (not:P (match_dup 1)))
1097 (compare:CC (match_dup 0)
1102 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1103 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1104 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1106 "{sf%I1|subf%I1c} %0,%2,%1")
1109 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1110 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1111 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1118 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1119 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1120 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1122 (clobber (match_scratch:SI 3 "=r,r"))]
1125 {sf.|subfc.} %3,%2,%1
1127 [(set_attr "type" "compare")
1128 (set_attr "length" "4,8")])
1131 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1132 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1133 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1135 (clobber (match_scratch:P 3 "=r,r"))]
1140 [(set_attr "type" "fast_compare")
1141 (set_attr "length" "4,8")])
1144 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1145 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1146 (match_operand:P 2 "gpc_reg_operand" ""))
1148 (clobber (match_scratch:P 3 ""))]
1151 (minus:P (match_dup 1)
1154 (compare:CC (match_dup 3)
1159 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1160 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1161 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1163 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1164 (minus:SI (match_dup 1) (match_dup 2)))]
1167 {sf.|subfc.} %0,%2,%1
1169 [(set_attr "type" "compare")
1170 (set_attr "length" "4,8")])
1173 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1174 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1175 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1177 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1178 (minus:P (match_dup 1)
1184 [(set_attr "type" "fast_compare")
1185 (set_attr "length" "4,8")])
1188 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1189 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1190 (match_operand:P 2 "gpc_reg_operand" ""))
1192 (set (match_operand:P 0 "gpc_reg_operand" "")
1193 (minus:P (match_dup 1)
1197 (minus:P (match_dup 1)
1200 (compare:CC (match_dup 0)
1204 (define_expand "sub<mode>3"
1205 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1206 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1207 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1211 if (GET_CODE (operands[2]) == CONST_INT)
1213 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1214 negate_rtx (<MODE>mode, operands[2])));
1219 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1220 ;; instruction and some auxiliary computations. Then we just have a single
1221 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1224 (define_expand "sminsi3"
1226 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1227 (match_operand:SI 2 "reg_or_short_operand" ""))
1229 (minus:SI (match_dup 2) (match_dup 1))))
1230 (set (match_operand:SI 0 "gpc_reg_operand" "")
1231 (minus:SI (match_dup 2) (match_dup 3)))]
1232 "TARGET_POWER || TARGET_ISEL"
1237 operands[2] = force_reg (SImode, operands[2]);
1238 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1242 operands[3] = gen_reg_rtx (SImode);
1246 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1247 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1248 (match_operand:SI 2 "reg_or_short_operand" "")))
1249 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1252 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1254 (minus:SI (match_dup 2) (match_dup 1))))
1255 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1258 (define_expand "smaxsi3"
1260 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1261 (match_operand:SI 2 "reg_or_short_operand" ""))
1263 (minus:SI (match_dup 2) (match_dup 1))))
1264 (set (match_operand:SI 0 "gpc_reg_operand" "")
1265 (plus:SI (match_dup 3) (match_dup 1)))]
1266 "TARGET_POWER || TARGET_ISEL"
1271 operands[2] = force_reg (SImode, operands[2]);
1272 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1275 operands[3] = gen_reg_rtx (SImode);
1279 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1280 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1281 (match_operand:SI 2 "reg_or_short_operand" "")))
1282 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1285 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1287 (minus:SI (match_dup 2) (match_dup 1))))
1288 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1291 (define_expand "uminsi3"
1292 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1294 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1296 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1298 (minus:SI (match_dup 4) (match_dup 3))))
1299 (set (match_operand:SI 0 "gpc_reg_operand" "")
1300 (minus:SI (match_dup 2) (match_dup 3)))]
1301 "TARGET_POWER || TARGET_ISEL"
1306 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1309 operands[3] = gen_reg_rtx (SImode);
1310 operands[4] = gen_reg_rtx (SImode);
1311 operands[5] = GEN_INT (-2147483647 - 1);
1314 (define_expand "umaxsi3"
1315 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1317 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1319 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1321 (minus:SI (match_dup 4) (match_dup 3))))
1322 (set (match_operand:SI 0 "gpc_reg_operand" "")
1323 (plus:SI (match_dup 3) (match_dup 1)))]
1324 "TARGET_POWER || TARGET_ISEL"
1329 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1332 operands[3] = gen_reg_rtx (SImode);
1333 operands[4] = gen_reg_rtx (SImode);
1334 operands[5] = GEN_INT (-2147483647 - 1);
1338 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1339 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1340 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1342 (minus:SI (match_dup 2) (match_dup 1))))]
1347 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1349 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1350 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1352 (minus:SI (match_dup 2) (match_dup 1)))
1354 (clobber (match_scratch:SI 3 "=r,r"))]
1359 [(set_attr "type" "delayed_compare")
1360 (set_attr "length" "4,8")])
1363 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1365 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1366 (match_operand:SI 2 "reg_or_short_operand" ""))
1368 (minus:SI (match_dup 2) (match_dup 1)))
1370 (clobber (match_scratch:SI 3 ""))]
1371 "TARGET_POWER && reload_completed"
1373 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1375 (minus:SI (match_dup 2) (match_dup 1))))
1377 (compare:CC (match_dup 3)
1382 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1384 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1385 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1387 (minus:SI (match_dup 2) (match_dup 1)))
1389 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1390 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1392 (minus:SI (match_dup 2) (match_dup 1))))]
1397 [(set_attr "type" "delayed_compare")
1398 (set_attr "length" "4,8")])
1401 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1403 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1404 (match_operand:SI 2 "reg_or_short_operand" ""))
1406 (minus:SI (match_dup 2) (match_dup 1)))
1408 (set (match_operand:SI 0 "gpc_reg_operand" "")
1409 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1411 (minus:SI (match_dup 2) (match_dup 1))))]
1412 "TARGET_POWER && reload_completed"
1414 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1416 (minus:SI (match_dup 2) (match_dup 1))))
1418 (compare:CC (match_dup 0)
1422 ;; We don't need abs with condition code because such comparisons should
1424 (define_expand "abssi2"
1425 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1426 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1432 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1435 else if (! TARGET_POWER)
1437 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1442 (define_insn "*abssi2_power"
1443 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1444 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1448 (define_insn_and_split "abssi2_isel"
1449 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1450 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
1451 (clobber (match_scratch:SI 2 "=&b"))
1452 (clobber (match_scratch:CC 3 "=y"))]
1455 "&& reload_completed"
1456 [(set (match_dup 2) (neg:SI (match_dup 1)))
1458 (compare:CC (match_dup 1)
1461 (if_then_else:SI (ge (match_dup 3)
1467 (define_insn_and_split "abssi2_nopower"
1468 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1469 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1470 (clobber (match_scratch:SI 2 "=&r,&r"))]
1471 "! TARGET_POWER && ! TARGET_ISEL"
1473 "&& reload_completed"
1474 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1475 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1476 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1479 (define_insn "*nabs_power"
1480 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1481 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1485 (define_insn_and_split "*nabs_nopower"
1486 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1487 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1488 (clobber (match_scratch:SI 2 "=&r,&r"))]
1491 "&& reload_completed"
1492 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1493 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1494 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1497 (define_expand "neg<mode>2"
1498 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1499 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1503 (define_insn "*neg<mode>2_internal"
1504 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1505 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1510 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1511 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1513 (clobber (match_scratch:P 2 "=r,r"))]
1518 [(set_attr "type" "fast_compare")
1519 (set_attr "length" "4,8")])
1522 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1523 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1525 (clobber (match_scratch:P 2 ""))]
1528 (neg:P (match_dup 1)))
1530 (compare:CC (match_dup 2)
1535 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1536 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1538 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1539 (neg:P (match_dup 1)))]
1544 [(set_attr "type" "fast_compare")
1545 (set_attr "length" "4,8")])
1548 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1549 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1551 (set (match_operand:P 0 "gpc_reg_operand" "")
1552 (neg:P (match_dup 1)))]
1555 (neg:P (match_dup 1)))
1557 (compare:CC (match_dup 0)
1561 (define_insn "clz<mode>2"
1562 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1563 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1565 "{cntlz|cntlz<wd>} %0,%1")
1567 (define_expand "ctz<mode>2"
1569 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
1570 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1572 (clobber (scratch:CC))])
1573 (set (match_dup 4) (clz:GPR (match_dup 3)))
1574 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1575 (minus:GPR (match_dup 5) (match_dup 4)))]
1578 operands[2] = gen_reg_rtx (<MODE>mode);
1579 operands[3] = gen_reg_rtx (<MODE>mode);
1580 operands[4] = gen_reg_rtx (<MODE>mode);
1581 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
1584 (define_expand "ffs<mode>2"
1586 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
1587 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1589 (clobber (scratch:CC))])
1590 (set (match_dup 4) (clz:GPR (match_dup 3)))
1591 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1592 (minus:GPR (match_dup 5) (match_dup 4)))]
1595 operands[2] = gen_reg_rtx (<MODE>mode);
1596 operands[3] = gen_reg_rtx (<MODE>mode);
1597 operands[4] = gen_reg_rtx (<MODE>mode);
1598 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
1601 (define_expand "popcount<mode>2"
1603 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1606 (mult:GPR (match_dup 2) (match_dup 4)))
1607 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1608 (lshiftrt:GPR (match_dup 3) (match_dup 5)))]
1611 operands[2] = gen_reg_rtx (<MODE>mode);
1612 operands[3] = gen_reg_rtx (<MODE>mode);
1613 operands[4] = force_reg (<MODE>mode,
1614 <MODE>mode == SImode
1615 ? GEN_INT (0x01010101)
1616 : GEN_INT ((HOST_WIDE_INT)
1617 0x01010101 << 32 | 0x01010101));
1618 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 8);
1621 (define_insn "popcntb<mode>2"
1622 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1623 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1628 (define_expand "mulsi3"
1629 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1630 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1631 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1636 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
1638 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
1642 (define_insn "mulsi3_mq"
1643 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1644 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1645 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1646 (clobber (match_scratch:SI 3 "=q,q"))]
1649 {muls|mullw} %0,%1,%2
1650 {muli|mulli} %0,%1,%2"
1652 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1653 (const_string "imul3")
1654 (match_operand:SI 2 "short_cint_operand" "")
1655 (const_string "imul2")]
1656 (const_string "imul")))])
1658 (define_insn "mulsi3_no_mq"
1659 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1660 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1661 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
1664 {muls|mullw} %0,%1,%2
1665 {muli|mulli} %0,%1,%2"
1667 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1668 (const_string "imul3")
1669 (match_operand:SI 2 "short_cint_operand" "")
1670 (const_string "imul2")]
1671 (const_string "imul")))])
1673 (define_insn "*mulsi3_mq_internal1"
1674 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1675 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1676 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1678 (clobber (match_scratch:SI 3 "=r,r"))
1679 (clobber (match_scratch:SI 4 "=q,q"))]
1682 {muls.|mullw.} %3,%1,%2
1684 [(set_attr "type" "imul_compare")
1685 (set_attr "length" "4,8")])
1688 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1689 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1690 (match_operand:SI 2 "gpc_reg_operand" ""))
1692 (clobber (match_scratch:SI 3 ""))
1693 (clobber (match_scratch:SI 4 ""))]
1694 "TARGET_POWER && reload_completed"
1695 [(parallel [(set (match_dup 3)
1696 (mult:SI (match_dup 1) (match_dup 2)))
1697 (clobber (match_dup 4))])
1699 (compare:CC (match_dup 3)
1703 (define_insn "*mulsi3_no_mq_internal1"
1704 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1705 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1706 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1708 (clobber (match_scratch:SI 3 "=r,r"))]
1711 {muls.|mullw.} %3,%1,%2
1713 [(set_attr "type" "imul_compare")
1714 (set_attr "length" "4,8")])
1717 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1718 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1719 (match_operand:SI 2 "gpc_reg_operand" ""))
1721 (clobber (match_scratch:SI 3 ""))]
1722 "! TARGET_POWER && reload_completed"
1724 (mult:SI (match_dup 1) (match_dup 2)))
1726 (compare:CC (match_dup 3)
1730 (define_insn "*mulsi3_mq_internal2"
1731 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1732 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1733 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1735 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1736 (mult:SI (match_dup 1) (match_dup 2)))
1737 (clobber (match_scratch:SI 4 "=q,q"))]
1740 {muls.|mullw.} %0,%1,%2
1742 [(set_attr "type" "imul_compare")
1743 (set_attr "length" "4,8")])
1746 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1747 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1748 (match_operand:SI 2 "gpc_reg_operand" ""))
1750 (set (match_operand:SI 0 "gpc_reg_operand" "")
1751 (mult:SI (match_dup 1) (match_dup 2)))
1752 (clobber (match_scratch:SI 4 ""))]
1753 "TARGET_POWER && reload_completed"
1754 [(parallel [(set (match_dup 0)
1755 (mult:SI (match_dup 1) (match_dup 2)))
1756 (clobber (match_dup 4))])
1758 (compare:CC (match_dup 0)
1762 (define_insn "*mulsi3_no_mq_internal2"
1763 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1764 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1765 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1767 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1768 (mult:SI (match_dup 1) (match_dup 2)))]
1771 {muls.|mullw.} %0,%1,%2
1773 [(set_attr "type" "imul_compare")
1774 (set_attr "length" "4,8")])
1777 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1778 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1779 (match_operand:SI 2 "gpc_reg_operand" ""))
1781 (set (match_operand:SI 0 "gpc_reg_operand" "")
1782 (mult:SI (match_dup 1) (match_dup 2)))]
1783 "! TARGET_POWER && reload_completed"
1785 (mult:SI (match_dup 1) (match_dup 2)))
1787 (compare:CC (match_dup 0)
1791 ;; Operand 1 is divided by operand 2; quotient goes to operand
1792 ;; 0 and remainder to operand 3.
1793 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1795 (define_expand "divmodsi4"
1796 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1797 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1798 (match_operand:SI 2 "gpc_reg_operand" "")))
1799 (set (match_operand:SI 3 "register_operand" "")
1800 (mod:SI (match_dup 1) (match_dup 2)))])]
1801 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1804 if (! TARGET_POWER && ! TARGET_POWERPC)
1806 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1807 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1808 emit_insn (gen_divss_call ());
1809 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1810 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
1815 (define_insn "*divmodsi4_internal"
1816 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1817 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1818 (match_operand:SI 2 "gpc_reg_operand" "r")))
1819 (set (match_operand:SI 3 "register_operand" "=q")
1820 (mod:SI (match_dup 1) (match_dup 2)))]
1823 [(set_attr "type" "idiv")])
1825 (define_expand "udiv<mode>3"
1826 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1827 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1828 (match_operand:GPR 2 "gpc_reg_operand" "")))]
1829 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1832 if (! TARGET_POWER && ! TARGET_POWERPC)
1834 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1835 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1836 emit_insn (gen_quous_call ());
1837 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1840 else if (TARGET_POWER)
1842 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
1847 (define_insn "udivsi3_mq"
1848 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1849 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1850 (match_operand:SI 2 "gpc_reg_operand" "r")))
1851 (clobber (match_scratch:SI 3 "=q"))]
1852 "TARGET_POWERPC && TARGET_POWER"
1854 [(set_attr "type" "idiv")])
1856 (define_insn "*udivsi3_no_mq"
1857 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1858 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
1859 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
1860 "TARGET_POWERPC && ! TARGET_POWER"
1862 [(set_attr "type" "idiv")])
1864 ;; For powers of two we can do srai/aze for divide and then adjust for
1865 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1866 ;; used; for PowerPC, force operands into register and do a normal divide;
1867 ;; for AIX common-mode, use quoss call on register operands.
1868 (define_expand "div<mode>3"
1869 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1870 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1871 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
1875 if (GET_CODE (operands[2]) == CONST_INT
1876 && INTVAL (operands[2]) > 0
1877 && exact_log2 (INTVAL (operands[2])) >= 0)
1879 else if (TARGET_POWERPC)
1881 operands[2] = force_reg (SImode, operands[2]);
1884 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
1888 else if (TARGET_POWER)
1892 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1893 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1894 emit_insn (gen_quoss_call ());
1895 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1900 (define_insn "divsi3_mq"
1901 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1902 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1903 (match_operand:SI 2 "gpc_reg_operand" "r")))
1904 (clobber (match_scratch:SI 3 "=q"))]
1905 "TARGET_POWERPC && TARGET_POWER"
1907 [(set_attr "type" "idiv")])
1909 (define_insn "*div<mode>3_no_mq"
1910 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1911 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
1912 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
1913 "TARGET_POWERPC && ! TARGET_POWER"
1915 [(set_attr "type" "idiv")])
1917 (define_expand "mod<mode>3"
1918 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
1919 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
1920 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
1928 if (GET_CODE (operands[2]) != CONST_INT
1929 || INTVAL (operands[2]) <= 0
1930 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
1933 temp1 = gen_reg_rtx (<MODE>mode);
1934 temp2 = gen_reg_rtx (<MODE>mode);
1936 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
1937 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
1938 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
1943 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1944 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
1945 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
1947 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
1948 [(set_attr "type" "two")
1949 (set_attr "length" "8")])
1952 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1953 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1954 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
1956 (clobber (match_scratch:P 3 "=r,r"))]
1959 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
1961 [(set_attr "type" "compare")
1962 (set_attr "length" "8,12")])
1965 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1966 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1967 (match_operand:GPR 2 "exact_log2_cint_operand"
1970 (clobber (match_scratch:GPR 3 ""))]
1973 (div:<MODE> (match_dup 1) (match_dup 2)))
1975 (compare:CC (match_dup 3)
1980 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1981 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1982 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
1984 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1985 (div:P (match_dup 1) (match_dup 2)))]
1988 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
1990 [(set_attr "type" "compare")
1991 (set_attr "length" "8,12")])
1994 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1995 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1996 (match_operand:GPR 2 "exact_log2_cint_operand"
1999 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2000 (div:GPR (match_dup 1) (match_dup 2)))]
2003 (div:<MODE> (match_dup 1) (match_dup 2)))
2005 (compare:CC (match_dup 0)
2010 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2013 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2015 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2016 (match_operand:SI 3 "gpc_reg_operand" "r")))
2017 (set (match_operand:SI 2 "register_operand" "=*q")
2020 (zero_extend:DI (match_dup 1)) (const_int 32))
2021 (zero_extend:DI (match_dup 4)))
2025 [(set_attr "type" "idiv")])
2027 ;; To do unsigned divide we handle the cases of the divisor looking like a
2028 ;; negative number. If it is a constant that is less than 2**31, we don't
2029 ;; have to worry about the branches. So make a few subroutines here.
2031 ;; First comes the normal case.
2032 (define_expand "udivmodsi4_normal"
2033 [(set (match_dup 4) (const_int 0))
2034 (parallel [(set (match_operand:SI 0 "" "")
2035 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2037 (zero_extend:DI (match_operand:SI 1 "" "")))
2038 (match_operand:SI 2 "" "")))
2039 (set (match_operand:SI 3 "" "")
2040 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2042 (zero_extend:DI (match_dup 1)))
2046 { operands[4] = gen_reg_rtx (SImode); }")
2048 ;; This handles the branches.
2049 (define_expand "udivmodsi4_tests"
2050 [(set (match_operand:SI 0 "" "") (const_int 0))
2051 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2052 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2053 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2054 (label_ref (match_operand:SI 4 "" "")) (pc)))
2055 (set (match_dup 0) (const_int 1))
2056 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2057 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2058 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2059 (label_ref (match_dup 4)) (pc)))]
2062 { operands[5] = gen_reg_rtx (CCUNSmode);
2063 operands[6] = gen_reg_rtx (CCmode);
2066 (define_expand "udivmodsi4"
2067 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2068 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2069 (match_operand:SI 2 "reg_or_cint_operand" "")))
2070 (set (match_operand:SI 3 "gpc_reg_operand" "")
2071 (umod:SI (match_dup 1) (match_dup 2)))])]
2079 if (! TARGET_POWERPC)
2081 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2082 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2083 emit_insn (gen_divus_call ());
2084 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2085 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2092 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2094 operands[2] = force_reg (SImode, operands[2]);
2095 label = gen_label_rtx ();
2096 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2097 operands[3], label));
2100 operands[2] = force_reg (SImode, operands[2]);
2102 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2110 ;; AIX architecture-independent common-mode multiply (DImode),
2111 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2112 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2113 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2114 ;; assumed unused if generating common-mode, so ignore.
2115 (define_insn "mulh_call"
2118 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2119 (sign_extend:DI (reg:SI 4)))
2121 (clobber (match_scratch:SI 0 "=l"))]
2122 "! TARGET_POWER && ! TARGET_POWERPC"
2124 [(set_attr "type" "imul")])
2126 (define_insn "mull_call"
2128 (mult:DI (sign_extend:DI (reg:SI 3))
2129 (sign_extend:DI (reg:SI 4))))
2130 (clobber (match_scratch:SI 0 "=l"))
2131 (clobber (reg:SI 0))]
2132 "! TARGET_POWER && ! TARGET_POWERPC"
2134 [(set_attr "type" "imul")])
2136 (define_insn "divss_call"
2138 (div:SI (reg:SI 3) (reg:SI 4)))
2140 (mod:SI (reg:SI 3) (reg:SI 4)))
2141 (clobber (match_scratch:SI 0 "=l"))
2142 (clobber (reg:SI 0))]
2143 "! TARGET_POWER && ! TARGET_POWERPC"
2145 [(set_attr "type" "idiv")])
2147 (define_insn "divus_call"
2149 (udiv:SI (reg:SI 3) (reg:SI 4)))
2151 (umod:SI (reg:SI 3) (reg:SI 4)))
2152 (clobber (match_scratch:SI 0 "=l"))
2153 (clobber (reg:SI 0))
2154 (clobber (match_scratch:CC 1 "=x"))
2155 (clobber (reg:CC 69))]
2156 "! TARGET_POWER && ! TARGET_POWERPC"
2158 [(set_attr "type" "idiv")])
2160 (define_insn "quoss_call"
2162 (div:SI (reg:SI 3) (reg:SI 4)))
2163 (clobber (match_scratch:SI 0 "=l"))]
2164 "! TARGET_POWER && ! TARGET_POWERPC"
2166 [(set_attr "type" "idiv")])
2168 (define_insn "quous_call"
2170 (udiv:SI (reg:SI 3) (reg:SI 4)))
2171 (clobber (match_scratch:SI 0 "=l"))
2172 (clobber (reg:SI 0))
2173 (clobber (match_scratch:CC 1 "=x"))
2174 (clobber (reg:CC 69))]
2175 "! TARGET_POWER && ! TARGET_POWERPC"
2177 [(set_attr "type" "idiv")])
2179 ;; Logical instructions
2180 ;; The logical instructions are mostly combined by using match_operator,
2181 ;; but the plain AND insns are somewhat different because there is no
2182 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2183 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2185 (define_insn "andsi3"
2186 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2187 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2188 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2189 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2193 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2194 {andil.|andi.} %0,%1,%b2
2195 {andiu.|andis.} %0,%1,%u2"
2196 [(set_attr "type" "*,*,compare,compare")])
2198 ;; Note to set cr's other than cr0 we do the and immediate and then
2199 ;; the test again -- this avoids a mfcr which on the higher end
2200 ;; machines causes an execution serialization
2202 (define_insn "*andsi3_internal2"
2203 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2204 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2205 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2207 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2208 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2212 {andil.|andi.} %3,%1,%b2
2213 {andiu.|andis.} %3,%1,%u2
2214 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2219 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2220 (set_attr "length" "4,4,4,4,8,8,8,8")])
2222 (define_insn "*andsi3_internal3"
2223 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2224 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2225 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2227 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2228 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2232 {andil.|andi.} %3,%1,%b2
2233 {andiu.|andis.} %3,%1,%u2
2234 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2239 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2240 (set_attr "length" "8,4,4,4,8,8,8,8")])
2243 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2244 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2245 (match_operand:GPR 2 "and_operand" ""))
2247 (clobber (match_scratch:GPR 3 ""))
2248 (clobber (match_scratch:CC 4 ""))]
2250 [(parallel [(set (match_dup 3)
2251 (and:<MODE> (match_dup 1)
2253 (clobber (match_dup 4))])
2255 (compare:CC (match_dup 3)
2259 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2260 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2263 [(set (match_operand:CC 0 "cc_reg_operand" "")
2264 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2265 (match_operand:SI 2 "gpc_reg_operand" ""))
2267 (clobber (match_scratch:SI 3 ""))
2268 (clobber (match_scratch:CC 4 ""))]
2269 "TARGET_POWERPC64 && reload_completed"
2270 [(parallel [(set (match_dup 3)
2271 (and:SI (match_dup 1)
2273 (clobber (match_dup 4))])
2275 (compare:CC (match_dup 3)
2279 (define_insn "*andsi3_internal4"
2280 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2281 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2282 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2284 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2285 (and:SI (match_dup 1)
2287 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2291 {andil.|andi.} %0,%1,%b2
2292 {andiu.|andis.} %0,%1,%u2
2293 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2298 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2299 (set_attr "length" "4,4,4,4,8,8,8,8")])
2301 (define_insn "*andsi3_internal5"
2302 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2303 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2304 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2306 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2307 (and:SI (match_dup 1)
2309 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2313 {andil.|andi.} %0,%1,%b2
2314 {andiu.|andis.} %0,%1,%u2
2315 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2320 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2321 (set_attr "length" "8,4,4,4,8,8,8,8")])
2324 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2325 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2326 (match_operand:SI 2 "and_operand" ""))
2328 (set (match_operand:SI 0 "gpc_reg_operand" "")
2329 (and:SI (match_dup 1)
2331 (clobber (match_scratch:CC 4 ""))]
2333 [(parallel [(set (match_dup 0)
2334 (and:SI (match_dup 1)
2336 (clobber (match_dup 4))])
2338 (compare:CC (match_dup 0)
2343 [(set (match_operand:CC 3 "cc_reg_operand" "")
2344 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2345 (match_operand:SI 2 "gpc_reg_operand" ""))
2347 (set (match_operand:SI 0 "gpc_reg_operand" "")
2348 (and:SI (match_dup 1)
2350 (clobber (match_scratch:CC 4 ""))]
2351 "TARGET_POWERPC64 && reload_completed"
2352 [(parallel [(set (match_dup 0)
2353 (and:SI (match_dup 1)
2355 (clobber (match_dup 4))])
2357 (compare:CC (match_dup 0)
2361 ;; Handle the PowerPC64 rlwinm corner case
2363 (define_insn_and_split "*andsi3_internal6"
2364 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2365 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2366 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2371 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2374 (rotate:SI (match_dup 0) (match_dup 5)))]
2377 int mb = extract_MB (operands[2]);
2378 int me = extract_ME (operands[2]);
2379 operands[3] = GEN_INT (me + 1);
2380 operands[5] = GEN_INT (32 - (me + 1));
2381 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2383 [(set_attr "length" "8")])
2385 (define_expand "iorsi3"
2386 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2387 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2388 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2392 if (GET_CODE (operands[2]) == CONST_INT
2393 && ! logical_operand (operands[2], SImode))
2395 HOST_WIDE_INT value = INTVAL (operands[2]);
2396 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2397 ? operands[0] : gen_reg_rtx (SImode));
2399 emit_insn (gen_iorsi3 (tmp, operands[1],
2400 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2401 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2406 (define_expand "xorsi3"
2407 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2408 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2409 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2413 if (GET_CODE (operands[2]) == CONST_INT
2414 && ! logical_operand (operands[2], SImode))
2416 HOST_WIDE_INT value = INTVAL (operands[2]);
2417 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2418 ? operands[0] : gen_reg_rtx (SImode));
2420 emit_insn (gen_xorsi3 (tmp, operands[1],
2421 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2422 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2427 (define_insn "*boolsi3_internal1"
2428 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2429 (match_operator:SI 3 "boolean_or_operator"
2430 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2431 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2435 {%q3il|%q3i} %0,%1,%b2
2436 {%q3iu|%q3is} %0,%1,%u2")
2438 (define_insn "*boolsi3_internal2"
2439 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2440 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2441 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2442 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2444 (clobber (match_scratch:SI 3 "=r,r"))]
2449 [(set_attr "type" "compare")
2450 (set_attr "length" "4,8")])
2453 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2454 (compare:CC (match_operator:SI 4 "boolean_operator"
2455 [(match_operand:SI 1 "gpc_reg_operand" "")
2456 (match_operand:SI 2 "gpc_reg_operand" "")])
2458 (clobber (match_scratch:SI 3 ""))]
2459 "TARGET_32BIT && reload_completed"
2460 [(set (match_dup 3) (match_dup 4))
2462 (compare:CC (match_dup 3)
2466 (define_insn "*boolsi3_internal3"
2467 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2468 (compare:CC (match_operator:SI 4 "boolean_operator"
2469 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2470 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2472 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2478 [(set_attr "type" "compare")
2479 (set_attr "length" "4,8")])
2482 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2483 (compare:CC (match_operator:SI 4 "boolean_operator"
2484 [(match_operand:SI 1 "gpc_reg_operand" "")
2485 (match_operand:SI 2 "gpc_reg_operand" "")])
2487 (set (match_operand:SI 0 "gpc_reg_operand" "")
2489 "TARGET_32BIT && reload_completed"
2490 [(set (match_dup 0) (match_dup 4))
2492 (compare:CC (match_dup 0)
2496 ;; Split a logical operation that we can't do in one insn into two insns,
2497 ;; each of which does one 16-bit part. This is used by combine.
2500 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2501 (match_operator:SI 3 "boolean_or_operator"
2502 [(match_operand:SI 1 "gpc_reg_operand" "")
2503 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
2505 [(set (match_dup 0) (match_dup 4))
2506 (set (match_dup 0) (match_dup 5))]
2510 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2511 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2513 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2514 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2518 (define_insn "*boolcsi3_internal1"
2519 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2520 (match_operator:SI 3 "boolean_operator"
2521 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2522 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
2526 (define_insn "*boolcsi3_internal2"
2527 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2528 (compare:CC (match_operator:SI 4 "boolean_operator"
2529 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2530 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2532 (clobber (match_scratch:SI 3 "=r,r"))]
2537 [(set_attr "type" "compare")
2538 (set_attr "length" "4,8")])
2541 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2542 (compare:CC (match_operator:SI 4 "boolean_operator"
2543 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2544 (match_operand:SI 2 "gpc_reg_operand" "")])
2546 (clobber (match_scratch:SI 3 ""))]
2547 "TARGET_32BIT && reload_completed"
2548 [(set (match_dup 3) (match_dup 4))
2550 (compare:CC (match_dup 3)
2554 (define_insn "*boolcsi3_internal3"
2555 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2556 (compare:CC (match_operator:SI 4 "boolean_operator"
2557 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2558 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2560 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2566 [(set_attr "type" "compare")
2567 (set_attr "length" "4,8")])
2570 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2571 (compare:CC (match_operator:SI 4 "boolean_operator"
2572 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2573 (match_operand:SI 2 "gpc_reg_operand" "")])
2575 (set (match_operand:SI 0 "gpc_reg_operand" "")
2577 "TARGET_32BIT && reload_completed"
2578 [(set (match_dup 0) (match_dup 4))
2580 (compare:CC (match_dup 0)
2584 (define_insn "*boolccsi3_internal1"
2585 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2586 (match_operator:SI 3 "boolean_operator"
2587 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2588 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
2592 (define_insn "*boolccsi3_internal2"
2593 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2594 (compare:CC (match_operator:SI 4 "boolean_operator"
2595 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2596 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2598 (clobber (match_scratch:SI 3 "=r,r"))]
2603 [(set_attr "type" "compare")
2604 (set_attr "length" "4,8")])
2607 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2608 (compare:CC (match_operator:SI 4 "boolean_operator"
2609 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2610 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2612 (clobber (match_scratch:SI 3 ""))]
2613 "TARGET_32BIT && reload_completed"
2614 [(set (match_dup 3) (match_dup 4))
2616 (compare:CC (match_dup 3)
2620 (define_insn "*boolccsi3_internal3"
2621 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2622 (compare:CC (match_operator:SI 4 "boolean_operator"
2623 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2624 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2626 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2632 [(set_attr "type" "compare")
2633 (set_attr "length" "4,8")])
2636 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2637 (compare:CC (match_operator:SI 4 "boolean_operator"
2638 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2639 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2641 (set (match_operand:SI 0 "gpc_reg_operand" "")
2643 "TARGET_32BIT && reload_completed"
2644 [(set (match_dup 0) (match_dup 4))
2646 (compare:CC (match_dup 0)
2650 ;; maskir insn. We need four forms because things might be in arbitrary
2651 ;; orders. Don't define forms that only set CR fields because these
2652 ;; would modify an input register.
2654 (define_insn "*maskir_internal1"
2655 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2656 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2657 (match_operand:SI 1 "gpc_reg_operand" "0"))
2658 (and:SI (match_dup 2)
2659 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
2663 (define_insn "*maskir_internal2"
2664 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2665 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2666 (match_operand:SI 1 "gpc_reg_operand" "0"))
2667 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2672 (define_insn "*maskir_internal3"
2673 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2674 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2675 (match_operand:SI 3 "gpc_reg_operand" "r"))
2676 (and:SI (not:SI (match_dup 2))
2677 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2681 (define_insn "*maskir_internal4"
2682 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2683 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2684 (match_operand:SI 2 "gpc_reg_operand" "r"))
2685 (and:SI (not:SI (match_dup 2))
2686 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2690 (define_insn "*maskir_internal5"
2691 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2693 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2694 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2695 (and:SI (match_dup 2)
2696 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
2698 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2699 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2700 (and:SI (match_dup 2) (match_dup 3))))]
2705 [(set_attr "type" "compare")
2706 (set_attr "length" "4,8")])
2709 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2711 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2712 (match_operand:SI 1 "gpc_reg_operand" ""))
2713 (and:SI (match_dup 2)
2714 (match_operand:SI 3 "gpc_reg_operand" "")))
2716 (set (match_operand:SI 0 "gpc_reg_operand" "")
2717 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2718 (and:SI (match_dup 2) (match_dup 3))))]
2719 "TARGET_POWER && reload_completed"
2721 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2722 (and:SI (match_dup 2) (match_dup 3))))
2724 (compare:CC (match_dup 0)
2728 (define_insn "*maskir_internal6"
2729 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2731 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2732 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2733 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2736 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2737 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2738 (and:SI (match_dup 3) (match_dup 2))))]
2743 [(set_attr "type" "compare")
2744 (set_attr "length" "4,8")])
2747 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2749 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2750 (match_operand:SI 1 "gpc_reg_operand" ""))
2751 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2754 (set (match_operand:SI 0 "gpc_reg_operand" "")
2755 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2756 (and:SI (match_dup 3) (match_dup 2))))]
2757 "TARGET_POWER && reload_completed"
2759 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2760 (and:SI (match_dup 3) (match_dup 2))))
2762 (compare:CC (match_dup 0)
2766 (define_insn "*maskir_internal7"
2767 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2769 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
2770 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
2771 (and:SI (not:SI (match_dup 2))
2772 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2774 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2775 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2776 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2781 [(set_attr "type" "compare")
2782 (set_attr "length" "4,8")])
2785 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2787 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
2788 (match_operand:SI 3 "gpc_reg_operand" ""))
2789 (and:SI (not:SI (match_dup 2))
2790 (match_operand:SI 1 "gpc_reg_operand" "")))
2792 (set (match_operand:SI 0 "gpc_reg_operand" "")
2793 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2794 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2795 "TARGET_POWER && reload_completed"
2797 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2798 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2800 (compare:CC (match_dup 0)
2804 (define_insn "*maskir_internal8"
2805 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2807 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2808 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2809 (and:SI (not:SI (match_dup 2))
2810 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2812 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2813 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2814 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2819 [(set_attr "type" "compare")
2820 (set_attr "length" "4,8")])
2823 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2825 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2826 (match_operand:SI 2 "gpc_reg_operand" ""))
2827 (and:SI (not:SI (match_dup 2))
2828 (match_operand:SI 1 "gpc_reg_operand" "")))
2830 (set (match_operand:SI 0 "gpc_reg_operand" "")
2831 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2832 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2833 "TARGET_POWER && reload_completed"
2835 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2836 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2838 (compare:CC (match_dup 0)
2842 ;; Rotate and shift insns, in all their variants. These support shifts,
2843 ;; field inserts and extracts, and various combinations thereof.
2844 (define_expand "insv"
2845 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
2846 (match_operand:SI 1 "const_int_operand" "")
2847 (match_operand:SI 2 "const_int_operand" ""))
2848 (match_operand 3 "gpc_reg_operand" ""))]
2852 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2853 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2854 compiler if the address of the structure is taken later. */
2855 if (GET_CODE (operands[0]) == SUBREG
2856 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2859 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
2860 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
2862 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
2866 (define_insn "insvsi"
2867 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2868 (match_operand:SI 1 "const_int_operand" "i")
2869 (match_operand:SI 2 "const_int_operand" "i"))
2870 (match_operand:SI 3 "gpc_reg_operand" "r"))]
2874 int start = INTVAL (operands[2]) & 31;
2875 int size = INTVAL (operands[1]) & 31;
2877 operands[4] = GEN_INT (32 - start - size);
2878 operands[1] = GEN_INT (start + size - 1);
2879 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2881 [(set_attr "type" "insert_word")])
2883 (define_insn "*insvsi_internal1"
2884 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2885 (match_operand:SI 1 "const_int_operand" "i")
2886 (match_operand:SI 2 "const_int_operand" "i"))
2887 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2888 (match_operand:SI 4 "const_int_operand" "i")))]
2889 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2892 int shift = INTVAL (operands[4]) & 31;
2893 int start = INTVAL (operands[2]) & 31;
2894 int size = INTVAL (operands[1]) & 31;
2896 operands[4] = GEN_INT (shift - start - size);
2897 operands[1] = GEN_INT (start + size - 1);
2898 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2900 [(set_attr "type" "insert_word")])
2902 (define_insn "*insvsi_internal2"
2903 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2904 (match_operand:SI 1 "const_int_operand" "i")
2905 (match_operand:SI 2 "const_int_operand" "i"))
2906 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2907 (match_operand:SI 4 "const_int_operand" "i")))]
2908 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2911 int shift = INTVAL (operands[4]) & 31;
2912 int start = INTVAL (operands[2]) & 31;
2913 int size = INTVAL (operands[1]) & 31;
2915 operands[4] = GEN_INT (32 - shift - start - size);
2916 operands[1] = GEN_INT (start + size - 1);
2917 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2919 [(set_attr "type" "insert_word")])
2921 (define_insn "*insvsi_internal3"
2922 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2923 (match_operand:SI 1 "const_int_operand" "i")
2924 (match_operand:SI 2 "const_int_operand" "i"))
2925 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2926 (match_operand:SI 4 "const_int_operand" "i")))]
2927 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2930 int shift = INTVAL (operands[4]) & 31;
2931 int start = INTVAL (operands[2]) & 31;
2932 int size = INTVAL (operands[1]) & 31;
2934 operands[4] = GEN_INT (32 - shift - start - size);
2935 operands[1] = GEN_INT (start + size - 1);
2936 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2938 [(set_attr "type" "insert_word")])
2940 (define_insn "*insvsi_internal4"
2941 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2942 (match_operand:SI 1 "const_int_operand" "i")
2943 (match_operand:SI 2 "const_int_operand" "i"))
2944 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2945 (match_operand:SI 4 "const_int_operand" "i")
2946 (match_operand:SI 5 "const_int_operand" "i")))]
2947 "INTVAL (operands[4]) >= INTVAL (operands[1])"
2950 int extract_start = INTVAL (operands[5]) & 31;
2951 int extract_size = INTVAL (operands[4]) & 31;
2952 int insert_start = INTVAL (operands[2]) & 31;
2953 int insert_size = INTVAL (operands[1]) & 31;
2955 /* Align extract field with insert field */
2956 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
2957 operands[1] = GEN_INT (insert_start + insert_size - 1);
2958 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
2960 [(set_attr "type" "insert_word")])
2962 ;; combine patterns for rlwimi
2963 (define_insn "*insvsi_internal5"
2964 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2965 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
2966 (match_operand:SI 1 "mask_operand" "i"))
2967 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2968 (match_operand:SI 2 "const_int_operand" "i"))
2969 (match_operand:SI 5 "mask_operand" "i"))))]
2970 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
2973 int me = extract_ME(operands[5]);
2974 int mb = extract_MB(operands[5]);
2975 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
2976 operands[2] = GEN_INT(mb);
2977 operands[1] = GEN_INT(me);
2978 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2980 [(set_attr "type" "insert_word")])
2982 (define_insn "*insvsi_internal6"
2983 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2984 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2985 (match_operand:SI 2 "const_int_operand" "i"))
2986 (match_operand:SI 5 "mask_operand" "i"))
2987 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
2988 (match_operand:SI 1 "mask_operand" "i"))))]
2989 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
2992 int me = extract_ME(operands[5]);
2993 int mb = extract_MB(operands[5]);
2994 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
2995 operands[2] = GEN_INT(mb);
2996 operands[1] = GEN_INT(me);
2997 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2999 [(set_attr "type" "insert_word")])
3001 (define_insn "insvdi"
3002 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3003 (match_operand:SI 1 "const_int_operand" "i")
3004 (match_operand:SI 2 "const_int_operand" "i"))
3005 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3009 int start = INTVAL (operands[2]) & 63;
3010 int size = INTVAL (operands[1]) & 63;
3012 operands[1] = GEN_INT (64 - start - size);
3013 return \"rldimi %0,%3,%H1,%H2\";
3016 (define_insn "*insvdi_internal2"
3017 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3018 (match_operand:SI 1 "const_int_operand" "i")
3019 (match_operand:SI 2 "const_int_operand" "i"))
3020 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3021 (match_operand:SI 4 "const_int_operand" "i")))]
3023 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3026 int shift = INTVAL (operands[4]) & 63;
3027 int start = (INTVAL (operands[2]) & 63) - 32;
3028 int size = INTVAL (operands[1]) & 63;
3030 operands[4] = GEN_INT (64 - shift - start - size);
3031 operands[2] = GEN_INT (start);
3032 operands[1] = GEN_INT (start + size - 1);
3033 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3036 (define_insn "*insvdi_internal3"
3037 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3038 (match_operand:SI 1 "const_int_operand" "i")
3039 (match_operand:SI 2 "const_int_operand" "i"))
3040 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3041 (match_operand:SI 4 "const_int_operand" "i")))]
3043 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3046 int shift = INTVAL (operands[4]) & 63;
3047 int start = (INTVAL (operands[2]) & 63) - 32;
3048 int size = INTVAL (operands[1]) & 63;
3050 operands[4] = GEN_INT (64 - shift - start - size);
3051 operands[2] = GEN_INT (start);
3052 operands[1] = GEN_INT (start + size - 1);
3053 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3056 (define_expand "extzv"
3057 [(set (match_operand 0 "gpc_reg_operand" "")
3058 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3059 (match_operand:SI 2 "const_int_operand" "")
3060 (match_operand:SI 3 "const_int_operand" "")))]
3064 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3065 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3066 compiler if the address of the structure is taken later. */
3067 if (GET_CODE (operands[0]) == SUBREG
3068 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3071 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3072 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3074 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3078 (define_insn "extzvsi"
3079 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3080 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3081 (match_operand:SI 2 "const_int_operand" "i")
3082 (match_operand:SI 3 "const_int_operand" "i")))]
3086 int start = INTVAL (operands[3]) & 31;
3087 int size = INTVAL (operands[2]) & 31;
3089 if (start + size >= 32)
3090 operands[3] = const0_rtx;
3092 operands[3] = GEN_INT (start + size);
3093 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3096 (define_insn "*extzvsi_internal1"
3097 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3098 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3099 (match_operand:SI 2 "const_int_operand" "i,i")
3100 (match_operand:SI 3 "const_int_operand" "i,i"))
3102 (clobber (match_scratch:SI 4 "=r,r"))]
3106 int start = INTVAL (operands[3]) & 31;
3107 int size = INTVAL (operands[2]) & 31;
3109 /* Force split for non-cc0 compare. */
3110 if (which_alternative == 1)
3113 /* If the bit-field being tested fits in the upper or lower half of a
3114 word, it is possible to use andiu. or andil. to test it. This is
3115 useful because the condition register set-use delay is smaller for
3116 andi[ul]. than for rlinm. This doesn't work when the starting bit
3117 position is 0 because the LT and GT bits may be set wrong. */
3119 if ((start > 0 && start + size <= 16) || start >= 16)
3121 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3122 - (1 << (16 - (start & 15) - size))));
3124 return \"{andiu.|andis.} %4,%1,%3\";
3126 return \"{andil.|andi.} %4,%1,%3\";
3129 if (start + size >= 32)
3130 operands[3] = const0_rtx;
3132 operands[3] = GEN_INT (start + size);
3133 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3135 [(set_attr "type" "compare")
3136 (set_attr "length" "4,8")])
3139 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3140 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3141 (match_operand:SI 2 "const_int_operand" "")
3142 (match_operand:SI 3 "const_int_operand" ""))
3144 (clobber (match_scratch:SI 4 ""))]
3147 (zero_extract:SI (match_dup 1) (match_dup 2)
3150 (compare:CC (match_dup 4)
3154 (define_insn "*extzvsi_internal2"
3155 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3156 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3157 (match_operand:SI 2 "const_int_operand" "i,i")
3158 (match_operand:SI 3 "const_int_operand" "i,i"))
3160 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3161 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3165 int start = INTVAL (operands[3]) & 31;
3166 int size = INTVAL (operands[2]) & 31;
3168 /* Force split for non-cc0 compare. */
3169 if (which_alternative == 1)
3172 /* Since we are using the output value, we can't ignore any need for
3173 a shift. The bit-field must end at the LSB. */
3174 if (start >= 16 && start + size == 32)
3176 operands[3] = GEN_INT ((1 << size) - 1);
3177 return \"{andil.|andi.} %0,%1,%3\";
3180 if (start + size >= 32)
3181 operands[3] = const0_rtx;
3183 operands[3] = GEN_INT (start + size);
3184 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3186 [(set_attr "type" "compare")
3187 (set_attr "length" "4,8")])
3190 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3191 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3192 (match_operand:SI 2 "const_int_operand" "")
3193 (match_operand:SI 3 "const_int_operand" ""))
3195 (set (match_operand:SI 0 "gpc_reg_operand" "")
3196 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3199 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3201 (compare:CC (match_dup 0)
3205 (define_insn "extzvdi"
3206 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3207 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3208 (match_operand:SI 2 "const_int_operand" "i")
3209 (match_operand:SI 3 "const_int_operand" "i")))]
3213 int start = INTVAL (operands[3]) & 63;
3214 int size = INTVAL (operands[2]) & 63;
3216 if (start + size >= 64)
3217 operands[3] = const0_rtx;
3219 operands[3] = GEN_INT (start + size);
3220 operands[2] = GEN_INT (64 - size);
3221 return \"rldicl %0,%1,%3,%2\";
3224 (define_insn "*extzvdi_internal1"
3225 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3226 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3227 (match_operand:SI 2 "const_int_operand" "i")
3228 (match_operand:SI 3 "const_int_operand" "i"))
3230 (clobber (match_scratch:DI 4 "=r"))]
3234 int start = INTVAL (operands[3]) & 63;
3235 int size = INTVAL (operands[2]) & 63;
3237 if (start + size >= 64)
3238 operands[3] = const0_rtx;
3240 operands[3] = GEN_INT (start + size);
3241 operands[2] = GEN_INT (64 - size);
3242 return \"rldicl. %4,%1,%3,%2\";
3244 [(set_attr "type" "compare")])
3246 (define_insn "*extzvdi_internal2"
3247 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3248 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3249 (match_operand:SI 2 "const_int_operand" "i")
3250 (match_operand:SI 3 "const_int_operand" "i"))
3252 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3253 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3257 int start = INTVAL (operands[3]) & 63;
3258 int size = INTVAL (operands[2]) & 63;
3260 if (start + size >= 64)
3261 operands[3] = const0_rtx;
3263 operands[3] = GEN_INT (start + size);
3264 operands[2] = GEN_INT (64 - size);
3265 return \"rldicl. %0,%1,%3,%2\";
3267 [(set_attr "type" "compare")])
3269 (define_insn "rotlsi3"
3270 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3271 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3272 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3274 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3276 (define_insn "*rotlsi3_internal2"
3277 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3278 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3279 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3281 (clobber (match_scratch:SI 3 "=r,r"))]
3284 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3286 [(set_attr "type" "delayed_compare")
3287 (set_attr "length" "4,8")])
3290 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3291 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3292 (match_operand:SI 2 "reg_or_cint_operand" ""))
3294 (clobber (match_scratch:SI 3 ""))]
3297 (rotate:SI (match_dup 1) (match_dup 2)))
3299 (compare:CC (match_dup 3)
3303 (define_insn "*rotlsi3_internal3"
3304 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3305 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3306 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3308 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3309 (rotate:SI (match_dup 1) (match_dup 2)))]
3312 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3314 [(set_attr "type" "delayed_compare")
3315 (set_attr "length" "4,8")])
3318 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3319 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3320 (match_operand:SI 2 "reg_or_cint_operand" ""))
3322 (set (match_operand:SI 0 "gpc_reg_operand" "")
3323 (rotate:SI (match_dup 1) (match_dup 2)))]
3326 (rotate:SI (match_dup 1) (match_dup 2)))
3328 (compare:CC (match_dup 0)
3332 (define_insn "*rotlsi3_internal4"
3333 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3334 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3335 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3336 (match_operand:SI 3 "mask_operand" "n")))]
3338 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3340 (define_insn "*rotlsi3_internal5"
3341 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3343 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3344 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3345 (match_operand:SI 3 "mask_operand" "n,n"))
3347 (clobber (match_scratch:SI 4 "=r,r"))]
3350 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3352 [(set_attr "type" "delayed_compare")
3353 (set_attr "length" "4,8")])
3356 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3358 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3359 (match_operand:SI 2 "reg_or_cint_operand" ""))
3360 (match_operand:SI 3 "mask_operand" ""))
3362 (clobber (match_scratch:SI 4 ""))]
3365 (and:SI (rotate:SI (match_dup 1)
3369 (compare:CC (match_dup 4)
3373 (define_insn "*rotlsi3_internal6"
3374 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3376 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3377 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3378 (match_operand:SI 3 "mask_operand" "n,n"))
3380 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3381 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3384 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3386 [(set_attr "type" "delayed_compare")
3387 (set_attr "length" "4,8")])
3390 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3392 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3393 (match_operand:SI 2 "reg_or_cint_operand" ""))
3394 (match_operand:SI 3 "mask_operand" ""))
3396 (set (match_operand:SI 0 "gpc_reg_operand" "")
3397 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3400 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3402 (compare:CC (match_dup 0)
3406 (define_insn "*rotlsi3_internal7"
3407 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3410 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3411 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3413 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3415 (define_insn "*rotlsi3_internal8"
3416 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3417 (compare:CC (zero_extend:SI
3419 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3420 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3422 (clobber (match_scratch:SI 3 "=r,r"))]
3425 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3427 [(set_attr "type" "delayed_compare")
3428 (set_attr "length" "4,8")])
3431 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3432 (compare:CC (zero_extend:SI
3434 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3435 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3437 (clobber (match_scratch:SI 3 ""))]
3440 (zero_extend:SI (subreg:QI
3441 (rotate:SI (match_dup 1)
3444 (compare:CC (match_dup 3)
3448 (define_insn "*rotlsi3_internal9"
3449 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3450 (compare:CC (zero_extend:SI
3452 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3453 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3455 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3456 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3459 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3461 [(set_attr "type" "delayed_compare")
3462 (set_attr "length" "4,8")])
3465 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3466 (compare:CC (zero_extend:SI
3468 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3469 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3471 (set (match_operand:SI 0 "gpc_reg_operand" "")
3472 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3475 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3477 (compare:CC (match_dup 0)
3481 (define_insn "*rotlsi3_internal10"
3482 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3485 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3486 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3488 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
3490 (define_insn "*rotlsi3_internal11"
3491 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3492 (compare:CC (zero_extend:SI
3494 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3495 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3497 (clobber (match_scratch:SI 3 "=r,r"))]
3500 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
3502 [(set_attr "type" "delayed_compare")
3503 (set_attr "length" "4,8")])
3506 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3507 (compare:CC (zero_extend:SI
3509 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3510 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3512 (clobber (match_scratch:SI 3 ""))]
3515 (zero_extend:SI (subreg:HI
3516 (rotate:SI (match_dup 1)
3519 (compare:CC (match_dup 3)
3523 (define_insn "*rotlsi3_internal12"
3524 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3525 (compare:CC (zero_extend:SI
3527 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3528 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3530 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3531 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3534 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
3536 [(set_attr "type" "delayed_compare")
3537 (set_attr "length" "4,8")])
3540 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3541 (compare:CC (zero_extend:SI
3543 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3544 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3546 (set (match_operand:SI 0 "gpc_reg_operand" "")
3547 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3550 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3552 (compare:CC (match_dup 0)
3556 ;; Note that we use "sle." instead of "sl." so that we can set
3557 ;; SHIFT_COUNT_TRUNCATED.
3559 (define_expand "ashlsi3"
3560 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3561 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3562 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3567 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
3569 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
3573 (define_insn "ashlsi3_power"
3574 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3575 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3576 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3577 (clobber (match_scratch:SI 3 "=q,X"))]
3581 {sli|slwi} %0,%1,%h2")
3583 (define_insn "ashlsi3_no_power"
3584 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3585 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3586 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3588 "{sl|slw}%I2 %0,%1,%h2")
3591 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3592 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3593 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3595 (clobber (match_scratch:SI 3 "=r,r,r,r"))
3596 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3600 {sli.|slwi.} %3,%1,%h2
3603 [(set_attr "type" "delayed_compare")
3604 (set_attr "length" "4,4,8,8")])
3607 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3608 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3609 (match_operand:SI 2 "reg_or_cint_operand" ""))
3611 (clobber (match_scratch:SI 3 ""))
3612 (clobber (match_scratch:SI 4 ""))]
3613 "TARGET_POWER && reload_completed"
3614 [(parallel [(set (match_dup 3)
3615 (ashift:SI (match_dup 1) (match_dup 2)))
3616 (clobber (match_dup 4))])
3618 (compare:CC (match_dup 3)
3623 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3624 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3625 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3627 (clobber (match_scratch:SI 3 "=r,r"))]
3628 "! TARGET_POWER && TARGET_32BIT"
3630 {sl|slw}%I2. %3,%1,%h2
3632 [(set_attr "type" "delayed_compare")
3633 (set_attr "length" "4,8")])
3636 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3637 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3638 (match_operand:SI 2 "reg_or_cint_operand" ""))
3640 (clobber (match_scratch:SI 3 ""))]
3641 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3643 (ashift:SI (match_dup 1) (match_dup 2)))
3645 (compare:CC (match_dup 3)
3650 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3651 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3652 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3654 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3655 (ashift:SI (match_dup 1) (match_dup 2)))
3656 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3660 {sli.|slwi.} %0,%1,%h2
3663 [(set_attr "type" "delayed_compare")
3664 (set_attr "length" "4,4,8,8")])
3667 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3668 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3669 (match_operand:SI 2 "reg_or_cint_operand" ""))
3671 (set (match_operand:SI 0 "gpc_reg_operand" "")
3672 (ashift:SI (match_dup 1) (match_dup 2)))
3673 (clobber (match_scratch:SI 4 ""))]
3674 "TARGET_POWER && reload_completed"
3675 [(parallel [(set (match_dup 0)
3676 (ashift:SI (match_dup 1) (match_dup 2)))
3677 (clobber (match_dup 4))])
3679 (compare:CC (match_dup 0)
3684 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3685 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3686 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3688 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3689 (ashift:SI (match_dup 1) (match_dup 2)))]
3690 "! TARGET_POWER && TARGET_32BIT"
3692 {sl|slw}%I2. %0,%1,%h2
3694 [(set_attr "type" "delayed_compare")
3695 (set_attr "length" "4,8")])
3698 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3699 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3700 (match_operand:SI 2 "reg_or_cint_operand" ""))
3702 (set (match_operand:SI 0 "gpc_reg_operand" "")
3703 (ashift:SI (match_dup 1) (match_dup 2)))]
3704 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3706 (ashift:SI (match_dup 1) (match_dup 2)))
3708 (compare:CC (match_dup 0)
3712 (define_insn "rlwinm"
3713 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3714 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3715 (match_operand:SI 2 "const_int_operand" "i"))
3716 (match_operand:SI 3 "mask_operand" "n")))]
3717 "includes_lshift_p (operands[2], operands[3])"
3718 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
3721 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3723 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3724 (match_operand:SI 2 "const_int_operand" "i,i"))
3725 (match_operand:SI 3 "mask_operand" "n,n"))
3727 (clobber (match_scratch:SI 4 "=r,r"))]
3728 "includes_lshift_p (operands[2], operands[3])"
3730 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3732 [(set_attr "type" "delayed_compare")
3733 (set_attr "length" "4,8")])
3736 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3738 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3739 (match_operand:SI 2 "const_int_operand" ""))
3740 (match_operand:SI 3 "mask_operand" ""))
3742 (clobber (match_scratch:SI 4 ""))]
3743 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3745 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3748 (compare:CC (match_dup 4)
3753 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3755 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3756 (match_operand:SI 2 "const_int_operand" "i,i"))
3757 (match_operand:SI 3 "mask_operand" "n,n"))
3759 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3760 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3761 "includes_lshift_p (operands[2], operands[3])"
3763 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3765 [(set_attr "type" "delayed_compare")
3766 (set_attr "length" "4,8")])
3769 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3771 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3772 (match_operand:SI 2 "const_int_operand" ""))
3773 (match_operand:SI 3 "mask_operand" ""))
3775 (set (match_operand:SI 0 "gpc_reg_operand" "")
3776 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3777 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3779 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3781 (compare:CC (match_dup 0)
3785 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
3787 (define_expand "lshrsi3"
3788 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3789 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3790 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3795 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
3797 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
3801 (define_insn "lshrsi3_power"
3802 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3803 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
3804 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
3805 (clobber (match_scratch:SI 3 "=q,X,X"))]
3810 {s%A2i|s%A2wi} %0,%1,%h2")
3812 (define_insn "lshrsi3_no_power"
3813 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3814 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3815 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
3819 {sr|srw}%I2 %0,%1,%h2")
3822 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3823 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3824 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3826 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
3827 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3832 {s%A2i.|s%A2wi.} %3,%1,%h2
3836 [(set_attr "type" "delayed_compare")
3837 (set_attr "length" "4,4,4,8,8,8")])
3840 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3841 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3842 (match_operand:SI 2 "reg_or_cint_operand" ""))
3844 (clobber (match_scratch:SI 3 ""))
3845 (clobber (match_scratch:SI 4 ""))]
3846 "TARGET_POWER && reload_completed"
3847 [(parallel [(set (match_dup 3)
3848 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3849 (clobber (match_dup 4))])
3851 (compare:CC (match_dup 3)
3856 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3857 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3858 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3860 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
3861 "! TARGET_POWER && TARGET_32BIT"
3864 {sr|srw}%I2. %3,%1,%h2
3867 [(set_attr "type" "delayed_compare")
3868 (set_attr "length" "4,4,8,8")])
3871 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3872 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3873 (match_operand:SI 2 "reg_or_cint_operand" ""))
3875 (clobber (match_scratch:SI 3 ""))]
3876 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3878 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3880 (compare:CC (match_dup 3)
3885 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3886 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3887 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3889 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
3890 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3891 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3896 {s%A2i.|s%A2wi.} %0,%1,%h2
3900 [(set_attr "type" "delayed_compare")
3901 (set_attr "length" "4,4,4,8,8,8")])
3904 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3905 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3906 (match_operand:SI 2 "reg_or_cint_operand" ""))
3908 (set (match_operand:SI 0 "gpc_reg_operand" "")
3909 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3910 (clobber (match_scratch:SI 4 ""))]
3911 "TARGET_POWER && reload_completed"
3912 [(parallel [(set (match_dup 0)
3913 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3914 (clobber (match_dup 4))])
3916 (compare:CC (match_dup 0)
3921 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3922 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3923 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3925 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3926 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3927 "! TARGET_POWER && TARGET_32BIT"
3930 {sr|srw}%I2. %0,%1,%h2
3933 [(set_attr "type" "delayed_compare")
3934 (set_attr "length" "4,4,8,8")])
3937 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3938 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3939 (match_operand:SI 2 "reg_or_cint_operand" ""))
3941 (set (match_operand:SI 0 "gpc_reg_operand" "")
3942 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3943 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3945 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3947 (compare:CC (match_dup 0)
3952 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3953 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3954 (match_operand:SI 2 "const_int_operand" "i"))
3955 (match_operand:SI 3 "mask_operand" "n")))]
3956 "includes_rshift_p (operands[2], operands[3])"
3957 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
3960 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3962 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3963 (match_operand:SI 2 "const_int_operand" "i,i"))
3964 (match_operand:SI 3 "mask_operand" "n,n"))
3966 (clobber (match_scratch:SI 4 "=r,r"))]
3967 "includes_rshift_p (operands[2], operands[3])"
3969 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
3971 [(set_attr "type" "delayed_compare")
3972 (set_attr "length" "4,8")])
3975 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3977 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3978 (match_operand:SI 2 "const_int_operand" ""))
3979 (match_operand:SI 3 "mask_operand" ""))
3981 (clobber (match_scratch:SI 4 ""))]
3982 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
3984 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
3987 (compare:CC (match_dup 4)
3992 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3994 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3995 (match_operand:SI 2 "const_int_operand" "i,i"))
3996 (match_operand:SI 3 "mask_operand" "n,n"))
3998 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3999 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4000 "includes_rshift_p (operands[2], operands[3])"
4002 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4004 [(set_attr "type" "delayed_compare")
4005 (set_attr "length" "4,8")])
4008 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4010 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4011 (match_operand:SI 2 "const_int_operand" ""))
4012 (match_operand:SI 3 "mask_operand" ""))
4014 (set (match_operand:SI 0 "gpc_reg_operand" "")
4015 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4016 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4018 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4020 (compare:CC (match_dup 0)
4025 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4028 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4029 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4030 "includes_rshift_p (operands[2], GEN_INT (255))"
4031 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4034 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4038 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4039 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4041 (clobber (match_scratch:SI 3 "=r,r"))]
4042 "includes_rshift_p (operands[2], GEN_INT (255))"
4044 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4046 [(set_attr "type" "delayed_compare")
4047 (set_attr "length" "4,8")])
4050 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4054 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4055 (match_operand:SI 2 "const_int_operand" "")) 0))
4057 (clobber (match_scratch:SI 3 ""))]
4058 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4060 (zero_extend:SI (subreg:QI
4061 (lshiftrt:SI (match_dup 1)
4064 (compare:CC (match_dup 3)
4069 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4073 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4074 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4076 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4077 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4078 "includes_rshift_p (operands[2], GEN_INT (255))"
4080 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4082 [(set_attr "type" "delayed_compare")
4083 (set_attr "length" "4,8")])
4086 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4090 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4091 (match_operand:SI 2 "const_int_operand" "")) 0))
4093 (set (match_operand:SI 0 "gpc_reg_operand" "")
4094 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4095 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4097 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4099 (compare:CC (match_dup 0)
4104 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4107 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4108 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4109 "includes_rshift_p (operands[2], GEN_INT (65535))"
4110 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4113 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4117 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4118 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4120 (clobber (match_scratch:SI 3 "=r,r"))]
4121 "includes_rshift_p (operands[2], GEN_INT (65535))"
4123 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4125 [(set_attr "type" "delayed_compare")
4126 (set_attr "length" "4,8")])
4129 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4133 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4134 (match_operand:SI 2 "const_int_operand" "")) 0))
4136 (clobber (match_scratch:SI 3 ""))]
4137 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4139 (zero_extend:SI (subreg:HI
4140 (lshiftrt:SI (match_dup 1)
4143 (compare:CC (match_dup 3)
4148 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4152 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4153 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4155 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4156 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4157 "includes_rshift_p (operands[2], GEN_INT (65535))"
4159 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4161 [(set_attr "type" "delayed_compare")
4162 (set_attr "length" "4,8")])
4165 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4169 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4170 (match_operand:SI 2 "const_int_operand" "")) 0))
4172 (set (match_operand:SI 0 "gpc_reg_operand" "")
4173 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4174 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4176 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4178 (compare:CC (match_dup 0)
4183 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4185 (match_operand:SI 1 "gpc_reg_operand" "r"))
4186 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4192 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4194 (match_operand:SI 1 "gpc_reg_operand" "r"))
4195 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4201 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4203 (match_operand:SI 1 "gpc_reg_operand" "r"))
4204 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4210 (define_expand "ashrsi3"
4211 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4212 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4213 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4218 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4220 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4224 (define_insn "ashrsi3_power"
4225 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4226 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4227 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4228 (clobber (match_scratch:SI 3 "=q,X"))]
4232 {srai|srawi} %0,%1,%h2")
4234 (define_insn "ashrsi3_no_power"
4235 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4236 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4237 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4239 "{sra|sraw}%I2 %0,%1,%h2")
4242 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4243 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4244 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4246 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4247 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4251 {srai.|srawi.} %3,%1,%h2
4254 [(set_attr "type" "delayed_compare")
4255 (set_attr "length" "4,4,8,8")])
4258 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4259 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4260 (match_operand:SI 2 "reg_or_cint_operand" ""))
4262 (clobber (match_scratch:SI 3 ""))
4263 (clobber (match_scratch:SI 4 ""))]
4264 "TARGET_POWER && reload_completed"
4265 [(parallel [(set (match_dup 3)
4266 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4267 (clobber (match_dup 4))])
4269 (compare:CC (match_dup 3)
4274 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4275 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4276 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4278 (clobber (match_scratch:SI 3 "=r,r"))]
4281 {sra|sraw}%I2. %3,%1,%h2
4283 [(set_attr "type" "delayed_compare")
4284 (set_attr "length" "4,8")])
4287 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4288 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4289 (match_operand:SI 2 "reg_or_cint_operand" ""))
4291 (clobber (match_scratch:SI 3 ""))]
4292 "! TARGET_POWER && reload_completed"
4294 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4296 (compare:CC (match_dup 3)
4301 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4302 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4303 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4305 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4306 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4307 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4311 {srai.|srawi.} %0,%1,%h2
4314 [(set_attr "type" "delayed_compare")
4315 (set_attr "length" "4,4,8,8")])
4318 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4319 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4320 (match_operand:SI 2 "reg_or_cint_operand" ""))
4322 (set (match_operand:SI 0 "gpc_reg_operand" "")
4323 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4324 (clobber (match_scratch:SI 4 ""))]
4325 "TARGET_POWER && reload_completed"
4326 [(parallel [(set (match_dup 0)
4327 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4328 (clobber (match_dup 4))])
4330 (compare:CC (match_dup 0)
4335 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4336 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4337 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4339 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4340 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4343 {sra|sraw}%I2. %0,%1,%h2
4345 [(set_attr "type" "delayed_compare")
4346 (set_attr "length" "4,8")])
4349 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4350 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4351 (match_operand:SI 2 "reg_or_cint_operand" ""))
4353 (set (match_operand:SI 0 "gpc_reg_operand" "")
4354 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4355 "! TARGET_POWER && reload_completed"
4357 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4359 (compare:CC (match_dup 0)
4363 ;; Floating-point insns, excluding normal data motion.
4365 ;; PowerPC has a full set of single-precision floating point instructions.
4367 ;; For the POWER architecture, we pretend that we have both SFmode and
4368 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4369 ;; The only conversions we will do will be when storing to memory. In that
4370 ;; case, we will use the "frsp" instruction before storing.
4372 ;; Note that when we store into a single-precision memory location, we need to
4373 ;; use the frsp insn first. If the register being stored isn't dead, we
4374 ;; need a scratch register for the frsp. But this is difficult when the store
4375 ;; is done by reload. It is not incorrect to do the frsp on the register in
4376 ;; this case, we just lose precision that we would have otherwise gotten but
4377 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4379 (define_expand "extendsfdf2"
4380 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4381 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4382 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4385 (define_insn_and_split "*extendsfdf2_fpr"
4386 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
4387 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
4388 "TARGET_HARD_FLOAT && TARGET_FPRS"
4393 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4396 emit_note (NOTE_INSN_DELETED);
4399 [(set_attr "type" "fp,fp,fpload")])
4401 (define_expand "truncdfsf2"
4402 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4403 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4404 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4407 (define_insn "*truncdfsf2_fpr"
4408 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4409 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4410 "TARGET_HARD_FLOAT && TARGET_FPRS"
4412 [(set_attr "type" "fp")])
4414 (define_insn "aux_truncdfsf2"
4415 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4416 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
4417 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4419 [(set_attr "type" "fp")])
4421 (define_expand "negsf2"
4422 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4423 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4427 (define_insn "*negsf2"
4428 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4429 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4430 "TARGET_HARD_FLOAT && TARGET_FPRS"
4432 [(set_attr "type" "fp")])
4434 (define_expand "abssf2"
4435 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4436 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4440 (define_insn "*abssf2"
4441 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4442 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4443 "TARGET_HARD_FLOAT && TARGET_FPRS"
4445 [(set_attr "type" "fp")])
4448 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4449 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4450 "TARGET_HARD_FLOAT && TARGET_FPRS"
4452 [(set_attr "type" "fp")])
4454 (define_expand "addsf3"
4455 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4456 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4457 (match_operand:SF 2 "gpc_reg_operand" "")))]
4462 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4463 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4464 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4465 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4467 [(set_attr "type" "fp")])
4470 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4471 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4472 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4473 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4474 "{fa|fadd} %0,%1,%2"
4475 [(set_attr "type" "fp")])
4477 (define_expand "subsf3"
4478 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4479 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4480 (match_operand:SF 2 "gpc_reg_operand" "")))]
4485 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4486 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4487 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4488 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4490 [(set_attr "type" "fp")])
4493 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4494 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4495 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4496 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4497 "{fs|fsub} %0,%1,%2"
4498 [(set_attr "type" "fp")])
4500 (define_expand "mulsf3"
4501 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4502 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4503 (match_operand:SF 2 "gpc_reg_operand" "")))]
4508 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4509 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4510 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4511 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4513 [(set_attr "type" "fp")])
4516 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4517 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4518 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4519 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4520 "{fm|fmul} %0,%1,%2"
4521 [(set_attr "type" "dmul")])
4524 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4525 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
4526 "TARGET_PPC_GFXOPT && flag_finite_math_only"
4528 [(set_attr "type" "fp")])
4530 (define_expand "divsf3"
4531 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4532 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4533 (match_operand:SF 2 "gpc_reg_operand" "")))]
4536 if (swdiv && !optimize_size && TARGET_PPC_GFXOPT
4537 && flag_finite_math_only && !flag_trapping_math)
4539 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
4545 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4546 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4547 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4548 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4550 [(set_attr "type" "sdiv")])
4553 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4554 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4555 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4556 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4557 "{fd|fdiv} %0,%1,%2"
4558 [(set_attr "type" "ddiv")])
4561 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4562 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4563 (match_operand:SF 2 "gpc_reg_operand" "f"))
4564 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4565 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4566 "fmadds %0,%1,%2,%3"
4567 [(set_attr "type" "fp")])
4570 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4571 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4572 (match_operand:SF 2 "gpc_reg_operand" "f"))
4573 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4574 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4575 "{fma|fmadd} %0,%1,%2,%3"
4576 [(set_attr "type" "dmul")])
4579 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4580 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4581 (match_operand:SF 2 "gpc_reg_operand" "f"))
4582 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4583 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4584 "fmsubs %0,%1,%2,%3"
4585 [(set_attr "type" "fp")])
4588 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4589 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4590 (match_operand:SF 2 "gpc_reg_operand" "f"))
4591 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4592 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4593 "{fms|fmsub} %0,%1,%2,%3"
4594 [(set_attr "type" "dmul")])
4597 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4598 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4599 (match_operand:SF 2 "gpc_reg_operand" "f"))
4600 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4601 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4602 && HONOR_SIGNED_ZEROS (SFmode)"
4603 "fnmadds %0,%1,%2,%3"
4604 [(set_attr "type" "fp")])
4607 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4608 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4609 (match_operand:SF 2 "gpc_reg_operand" "f"))
4610 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4611 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4612 && ! HONOR_SIGNED_ZEROS (SFmode)"
4613 "fnmadds %0,%1,%2,%3"
4614 [(set_attr "type" "fp")])
4617 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4618 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4619 (match_operand:SF 2 "gpc_reg_operand" "f"))
4620 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4621 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4622 "{fnma|fnmadd} %0,%1,%2,%3"
4623 [(set_attr "type" "dmul")])
4626 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4627 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4628 (match_operand:SF 2 "gpc_reg_operand" "f"))
4629 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4630 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4631 && ! HONOR_SIGNED_ZEROS (SFmode)"
4632 "{fnma|fnmadd} %0,%1,%2,%3"
4633 [(set_attr "type" "dmul")])
4636 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4637 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4638 (match_operand:SF 2 "gpc_reg_operand" "f"))
4639 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4640 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4641 && HONOR_SIGNED_ZEROS (SFmode)"
4642 "fnmsubs %0,%1,%2,%3"
4643 [(set_attr "type" "fp")])
4646 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4647 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4648 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4649 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4650 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4651 && ! HONOR_SIGNED_ZEROS (SFmode)"
4652 "fnmsubs %0,%1,%2,%3"
4653 [(set_attr "type" "fp")])
4656 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4657 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4658 (match_operand:SF 2 "gpc_reg_operand" "f"))
4659 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4660 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4661 "{fnms|fnmsub} %0,%1,%2,%3"
4662 [(set_attr "type" "dmul")])
4665 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4666 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4667 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4668 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4669 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4670 && ! HONOR_SIGNED_ZEROS (SFmode)"
4671 "{fnms|fnmsub} %0,%1,%2,%3"
4672 [(set_attr "type" "dmul")])
4674 (define_expand "sqrtsf2"
4675 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4676 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4677 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4681 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4682 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4683 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4685 [(set_attr "type" "ssqrt")])
4688 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4689 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4690 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
4692 [(set_attr "type" "dsqrt")])
4694 (define_expand "copysignsf3"
4696 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
4698 (neg:SF (abs:SF (match_dup 1))))
4699 (set (match_operand:SF 0 "gpc_reg_operand" "")
4700 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
4704 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4705 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
4707 operands[3] = gen_reg_rtx (SFmode);
4708 operands[4] = gen_reg_rtx (SFmode);
4709 operands[5] = CONST0_RTX (SFmode);
4712 (define_expand "copysigndf3"
4714 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
4716 (neg:DF (abs:DF (match_dup 1))))
4717 (set (match_operand:DF 0 "gpc_reg_operand" "")
4718 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
4722 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4723 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
4725 operands[3] = gen_reg_rtx (DFmode);
4726 operands[4] = gen_reg_rtx (DFmode);
4727 operands[5] = CONST0_RTX (DFmode);
4730 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4731 ;; fsel instruction and some auxiliary computations. Then we just have a
4732 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
4734 (define_expand "smaxsf3"
4735 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4736 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4737 (match_operand:SF 2 "gpc_reg_operand" ""))
4740 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4741 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4743 (define_expand "sminsf3"
4744 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4745 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4746 (match_operand:SF 2 "gpc_reg_operand" ""))
4749 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4750 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4753 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4754 (match_operator:SF 3 "min_max_operator"
4755 [(match_operand:SF 1 "gpc_reg_operand" "")
4756 (match_operand:SF 2 "gpc_reg_operand" "")]))]
4757 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4760 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4761 operands[1], operands[2]);
4765 (define_expand "movsicc"
4766 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4767 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4768 (match_operand:SI 2 "gpc_reg_operand" "")
4769 (match_operand:SI 3 "gpc_reg_operand" "")))]
4773 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4779 ;; We use the BASE_REGS for the isel input operands because, if rA is
4780 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
4781 ;; because we may switch the operands and rB may end up being rA.
4783 ;; We need 2 patterns: an unsigned and a signed pattern. We could
4784 ;; leave out the mode in operand 4 and use one pattern, but reload can
4785 ;; change the mode underneath our feet and then gets confused trying
4786 ;; to reload the value.
4787 (define_insn "isel_signed"
4788 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4790 (match_operator 1 "comparison_operator"
4791 [(match_operand:CC 4 "cc_reg_operand" "y")
4793 (match_operand:SI 2 "gpc_reg_operand" "b")
4794 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4797 { return output_isel (operands); }"
4798 [(set_attr "length" "4")])
4800 (define_insn "isel_unsigned"
4801 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4803 (match_operator 1 "comparison_operator"
4804 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
4806 (match_operand:SI 2 "gpc_reg_operand" "b")
4807 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4810 { return output_isel (operands); }"
4811 [(set_attr "length" "4")])
4813 (define_expand "movsfcc"
4814 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4815 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4816 (match_operand:SF 2 "gpc_reg_operand" "")
4817 (match_operand:SF 3 "gpc_reg_operand" "")))]
4818 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4821 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4827 (define_insn "*fselsfsf4"
4828 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4829 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4830 (match_operand:SF 4 "zero_fp_constant" "F"))
4831 (match_operand:SF 2 "gpc_reg_operand" "f")
4832 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4833 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4835 [(set_attr "type" "fp")])
4837 (define_insn "*fseldfsf4"
4838 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4839 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4840 (match_operand:DF 4 "zero_fp_constant" "F"))
4841 (match_operand:SF 2 "gpc_reg_operand" "f")
4842 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4843 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4845 [(set_attr "type" "fp")])
4847 (define_expand "negdf2"
4848 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4849 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4850 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4853 (define_insn "*negdf2_fpr"
4854 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4855 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4856 "TARGET_HARD_FLOAT && TARGET_FPRS"
4858 [(set_attr "type" "fp")])
4860 (define_expand "absdf2"
4861 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4862 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4863 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4866 (define_insn "*absdf2_fpr"
4867 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4868 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4869 "TARGET_HARD_FLOAT && TARGET_FPRS"
4871 [(set_attr "type" "fp")])
4873 (define_insn "*nabsdf2_fpr"
4874 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4875 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
4876 "TARGET_HARD_FLOAT && TARGET_FPRS"
4878 [(set_attr "type" "fp")])
4880 (define_expand "adddf3"
4881 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4882 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
4883 (match_operand:DF 2 "gpc_reg_operand" "")))]
4884 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4887 (define_insn "*adddf3_fpr"
4888 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4889 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4890 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4891 "TARGET_HARD_FLOAT && TARGET_FPRS"
4892 "{fa|fadd} %0,%1,%2"
4893 [(set_attr "type" "fp")])
4895 (define_expand "subdf3"
4896 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4897 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
4898 (match_operand:DF 2 "gpc_reg_operand" "")))]
4899 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4902 (define_insn "*subdf3_fpr"
4903 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4904 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4905 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4906 "TARGET_HARD_FLOAT && TARGET_FPRS"
4907 "{fs|fsub} %0,%1,%2"
4908 [(set_attr "type" "fp")])
4910 (define_expand "muldf3"
4911 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4912 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
4913 (match_operand:DF 2 "gpc_reg_operand" "")))]
4914 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4917 (define_insn "*muldf3_fpr"
4918 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4919 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4920 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4921 "TARGET_HARD_FLOAT && TARGET_FPRS"
4922 "{fm|fmul} %0,%1,%2"
4923 [(set_attr "type" "dmul")])
4926 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4927 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
4928 "TARGET_POPCNTB && flag_finite_math_only"
4930 [(set_attr "type" "fp")])
4932 (define_expand "divdf3"
4933 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4934 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
4935 (match_operand:DF 2 "gpc_reg_operand" "")))]
4936 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4938 if (swdiv && !optimize_size && TARGET_POPCNTB
4939 && flag_finite_math_only && !flag_trapping_math)
4941 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
4946 (define_insn "*divdf3_fpr"
4947 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4948 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4949 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4950 "TARGET_HARD_FLOAT && TARGET_FPRS"
4951 "{fd|fdiv} %0,%1,%2"
4952 [(set_attr "type" "ddiv")])
4955 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4956 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4957 (match_operand:DF 2 "gpc_reg_operand" "f"))
4958 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4959 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4960 "{fma|fmadd} %0,%1,%2,%3"
4961 [(set_attr "type" "dmul")])
4964 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4965 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4966 (match_operand:DF 2 "gpc_reg_operand" "f"))
4967 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4968 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4969 "{fms|fmsub} %0,%1,%2,%3"
4970 [(set_attr "type" "dmul")])
4973 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4974 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4975 (match_operand:DF 2 "gpc_reg_operand" "f"))
4976 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4977 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4978 && HONOR_SIGNED_ZEROS (DFmode)"
4979 "{fnma|fnmadd} %0,%1,%2,%3"
4980 [(set_attr "type" "dmul")])
4983 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4984 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
4985 (match_operand:DF 2 "gpc_reg_operand" "f"))
4986 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4987 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4988 && ! HONOR_SIGNED_ZEROS (DFmode)"
4989 "{fnma|fnmadd} %0,%1,%2,%3"
4990 [(set_attr "type" "dmul")])
4993 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4994 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4995 (match_operand:DF 2 "gpc_reg_operand" "f"))
4996 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4997 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4998 && HONOR_SIGNED_ZEROS (DFmode)"
4999 "{fnms|fnmsub} %0,%1,%2,%3"
5000 [(set_attr "type" "dmul")])
5003 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5004 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5005 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5006 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5007 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5008 && ! HONOR_SIGNED_ZEROS (DFmode)"
5009 "{fnms|fnmsub} %0,%1,%2,%3"
5010 [(set_attr "type" "dmul")])
5012 (define_insn "sqrtdf2"
5013 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5014 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5015 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5017 [(set_attr "type" "dsqrt")])
5019 ;; The conditional move instructions allow us to perform max and min
5020 ;; operations even when
5022 (define_expand "smaxdf3"
5023 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5024 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5025 (match_operand:DF 2 "gpc_reg_operand" ""))
5028 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5029 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5031 (define_expand "smindf3"
5032 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5033 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5034 (match_operand:DF 2 "gpc_reg_operand" ""))
5037 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5038 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5041 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5042 (match_operator:DF 3 "min_max_operator"
5043 [(match_operand:DF 1 "gpc_reg_operand" "")
5044 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5045 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5048 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5049 operands[1], operands[2]);
5053 (define_expand "movdfcc"
5054 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5055 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5056 (match_operand:DF 2 "gpc_reg_operand" "")
5057 (match_operand:DF 3 "gpc_reg_operand" "")))]
5058 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5061 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5067 (define_insn "*fseldfdf4"
5068 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5069 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5070 (match_operand:DF 4 "zero_fp_constant" "F"))
5071 (match_operand:DF 2 "gpc_reg_operand" "f")
5072 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5073 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5075 [(set_attr "type" "fp")])
5077 (define_insn "*fselsfdf4"
5078 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5079 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5080 (match_operand:SF 4 "zero_fp_constant" "F"))
5081 (match_operand:DF 2 "gpc_reg_operand" "f")
5082 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5085 [(set_attr "type" "fp")])
5087 ;; Conversions to and from floating-point.
5089 (define_expand "fixuns_truncsfsi2"
5090 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5091 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5092 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5095 (define_expand "fix_truncsfsi2"
5096 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5097 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5098 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5101 ; For each of these conversions, there is a define_expand, a define_insn
5102 ; with a '#' template, and a define_split (with C code). The idea is
5103 ; to allow constant folding with the template of the define_insn,
5104 ; then to have the insns split later (between sched1 and final).
5106 (define_expand "floatsidf2"
5107 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5108 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5111 (clobber (match_dup 4))
5112 (clobber (match_dup 5))
5113 (clobber (match_dup 6))])]
5114 "TARGET_HARD_FLOAT && TARGET_FPRS"
5117 if (TARGET_E500_DOUBLE)
5119 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5122 if (TARGET_POWERPC64)
5124 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5125 rtx t1 = gen_reg_rtx (DImode);
5126 rtx t2 = gen_reg_rtx (DImode);
5127 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5131 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5132 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5133 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5134 operands[5] = gen_reg_rtx (DFmode);
5135 operands[6] = gen_reg_rtx (SImode);
5138 (define_insn_and_split "*floatsidf2_internal"
5139 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5140 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5141 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5142 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5143 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5144 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5145 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5146 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5148 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5152 rtx lowword, highword;
5153 gcc_assert (MEM_P (operands[4]));
5154 highword = adjust_address (operands[4], SImode, 0);
5155 lowword = adjust_address (operands[4], SImode, 4);
5156 if (! WORDS_BIG_ENDIAN)
5159 tmp = highword; highword = lowword; lowword = tmp;
5162 emit_insn (gen_xorsi3 (operands[6], operands[1],
5163 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5164 emit_move_insn (lowword, operands[6]);
5165 emit_move_insn (highword, operands[2]);
5166 emit_move_insn (operands[5], operands[4]);
5167 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5170 [(set_attr "length" "24")])
5172 (define_expand "floatunssisf2"
5173 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5174 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5175 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5178 (define_expand "floatunssidf2"
5179 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5180 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5183 (clobber (match_dup 4))
5184 (clobber (match_dup 5))])]
5185 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5188 if (TARGET_E500_DOUBLE)
5190 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5193 if (TARGET_POWERPC64)
5195 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5196 rtx t1 = gen_reg_rtx (DImode);
5197 rtx t2 = gen_reg_rtx (DImode);
5198 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5203 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5204 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5205 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5206 operands[5] = gen_reg_rtx (DFmode);
5209 (define_insn_and_split "*floatunssidf2_internal"
5210 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5211 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5212 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5213 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5214 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5215 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5216 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5218 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5222 rtx lowword, highword;
5223 gcc_assert (MEM_P (operands[4]));
5224 highword = adjust_address (operands[4], SImode, 0);
5225 lowword = adjust_address (operands[4], SImode, 4);
5226 if (! WORDS_BIG_ENDIAN)
5229 tmp = highword; highword = lowword; lowword = tmp;
5232 emit_move_insn (lowword, operands[1]);
5233 emit_move_insn (highword, operands[2]);
5234 emit_move_insn (operands[5], operands[4]);
5235 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5238 [(set_attr "length" "20")])
5240 (define_expand "fix_truncdfsi2"
5241 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
5242 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5243 (clobber (match_dup 2))
5244 (clobber (match_dup 3))])]
5245 "(TARGET_POWER2 || TARGET_POWERPC)
5246 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5249 if (TARGET_E500_DOUBLE)
5251 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5254 operands[2] = gen_reg_rtx (DImode);
5255 if (TARGET_PPC_GFXOPT)
5257 rtx orig_dest = operands[0];
5258 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
5259 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5260 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5262 if (operands[0] != orig_dest)
5263 emit_move_insn (orig_dest, operands[0]);
5266 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5269 (define_insn_and_split "*fix_truncdfsi2_internal"
5270 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5271 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5272 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5273 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5274 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5276 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[3]))"
5281 gcc_assert (MEM_P (operands[3]));
5282 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5284 emit_insn (gen_fctiwz (operands[2], operands[1]));
5285 emit_move_insn (operands[3], operands[2]);
5286 emit_move_insn (operands[0], lowword);
5289 [(set_attr "length" "16")])
5291 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
5292 [(set (match_operand:SI 0 "memory_operand" "=Z")
5293 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5294 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
5295 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
5296 && TARGET_PPC_GFXOPT"
5302 emit_insn (gen_fctiwz (operands[2], operands[1]));
5303 emit_insn (gen_stfiwx (operands[0], operands[2]));
5306 [(set_attr "length" "16")])
5308 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5309 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5310 ; because the first makes it clear that operand 0 is not live
5311 ; before the instruction.
5312 (define_insn "fctiwz"
5313 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
5314 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5316 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5317 "{fcirz|fctiwz} %0,%1"
5318 [(set_attr "type" "fp")])
5320 ; An UNSPEC is used so we don't have to support SImode in FP registers.
5321 (define_insn "stfiwx"
5322 [(set (match_operand:SI 0 "memory_operand" "=Z")
5323 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
5327 [(set_attr "type" "fpstore")])
5329 (define_expand "floatsisf2"
5330 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5331 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5332 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5335 (define_insn "floatdidf2"
5336 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5337 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
5338 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5340 [(set_attr "type" "fp")])
5342 (define_insn_and_split "floatsidf_ppc64"
5343 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5344 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5345 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5346 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5347 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5348 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5351 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5352 (set (match_dup 2) (match_dup 3))
5353 (set (match_dup 4) (match_dup 2))
5354 (set (match_dup 0) (float:DF (match_dup 4)))]
5357 (define_insn_and_split "floatunssidf_ppc64"
5358 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5359 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5360 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5361 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5362 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5363 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5366 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5367 (set (match_dup 2) (match_dup 3))
5368 (set (match_dup 4) (match_dup 2))
5369 (set (match_dup 0) (float:DF (match_dup 4)))]
5372 (define_insn "fix_truncdfdi2"
5373 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5374 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5375 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5377 [(set_attr "type" "fp")])
5379 (define_expand "floatdisf2"
5380 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5381 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5382 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5385 rtx val = operands[1];
5386 if (!flag_unsafe_math_optimizations)
5388 rtx label = gen_label_rtx ();
5389 val = gen_reg_rtx (DImode);
5390 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
5393 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
5397 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5398 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5399 ;; from double rounding.
5400 (define_insn_and_split "floatdisf2_internal1"
5401 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5402 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
5403 (clobber (match_scratch:DF 2 "=f"))]
5404 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5406 "&& reload_completed"
5408 (float:DF (match_dup 1)))
5410 (float_truncate:SF (match_dup 2)))]
5413 ;; Twiddles bits to avoid double rounding.
5414 ;; Bits that might be truncated when converting to DFmode are replaced
5415 ;; by a bit that won't be lost at that stage, but is below the SFmode
5416 ;; rounding position.
5417 (define_expand "floatdisf2_internal2"
5418 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
5420 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
5422 (clobber (scratch:CC))])
5423 (set (match_dup 3) (plus:DI (match_dup 3)
5425 (set (match_dup 0) (plus:DI (match_dup 0)
5427 (set (match_dup 4) (compare:CCUNS (match_dup 3)
5429 (set (match_dup 0) (ior:DI (match_dup 0)
5431 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
5433 (clobber (scratch:CC))])
5434 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
5435 (label_ref (match_operand:DI 2 "" ""))
5437 (set (match_dup 0) (match_dup 1))]
5438 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5441 operands[3] = gen_reg_rtx (DImode);
5442 operands[4] = gen_reg_rtx (CCUNSmode);
5445 ;; Define the DImode operations that can be done in a small number
5446 ;; of instructions. The & constraints are to prevent the register
5447 ;; allocator from allocating registers that overlap with the inputs
5448 ;; (for example, having an input in 7,8 and an output in 6,7). We
5449 ;; also allow for the output being the same as one of the inputs.
5451 (define_insn "*adddi3_noppc64"
5452 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5453 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5454 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
5455 "! TARGET_POWERPC64"
5458 if (WORDS_BIG_ENDIAN)
5459 return (GET_CODE (operands[2])) != CONST_INT
5460 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5461 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5463 return (GET_CODE (operands[2])) != CONST_INT
5464 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5465 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5467 [(set_attr "type" "two")
5468 (set_attr "length" "8")])
5470 (define_insn "*subdi3_noppc64"
5471 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5472 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5473 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
5474 "! TARGET_POWERPC64"
5477 if (WORDS_BIG_ENDIAN)
5478 return (GET_CODE (operands[1]) != CONST_INT)
5479 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
5480 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
5482 return (GET_CODE (operands[1]) != CONST_INT)
5483 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
5484 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5486 [(set_attr "type" "two")
5487 (set_attr "length" "8")])
5489 (define_insn "*negdi2_noppc64"
5490 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5491 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
5492 "! TARGET_POWERPC64"
5495 return (WORDS_BIG_ENDIAN)
5496 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
5497 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
5499 [(set_attr "type" "two")
5500 (set_attr "length" "8")])
5502 (define_expand "mulsidi3"
5503 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5504 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5505 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5506 "! TARGET_POWERPC64"
5509 if (! TARGET_POWER && ! TARGET_POWERPC)
5511 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5512 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5513 emit_insn (gen_mull_call ());
5514 if (WORDS_BIG_ENDIAN)
5515 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
5518 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
5519 gen_rtx_REG (SImode, 3));
5520 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
5521 gen_rtx_REG (SImode, 4));
5525 else if (TARGET_POWER)
5527 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
5532 (define_insn "mulsidi3_mq"
5533 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5534 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5535 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5536 (clobber (match_scratch:SI 3 "=q"))]
5538 "mul %0,%1,%2\;mfmq %L0"
5539 [(set_attr "type" "imul")
5540 (set_attr "length" "8")])
5542 (define_insn "*mulsidi3_no_mq"
5543 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5544 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5545 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5546 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5549 return (WORDS_BIG_ENDIAN)
5550 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
5551 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
5553 [(set_attr "type" "imul")
5554 (set_attr "length" "8")])
5557 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5558 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5559 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5560 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5563 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
5564 (sign_extend:DI (match_dup 2)))
5567 (mult:SI (match_dup 1)
5571 int endian = (WORDS_BIG_ENDIAN == 0);
5572 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5573 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5576 (define_expand "umulsidi3"
5577 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5578 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5579 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5580 "TARGET_POWERPC && ! TARGET_POWERPC64"
5585 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
5590 (define_insn "umulsidi3_mq"
5591 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5592 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5593 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5594 (clobber (match_scratch:SI 3 "=q"))]
5595 "TARGET_POWERPC && TARGET_POWER"
5598 return (WORDS_BIG_ENDIAN)
5599 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5600 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5602 [(set_attr "type" "imul")
5603 (set_attr "length" "8")])
5605 (define_insn "*umulsidi3_no_mq"
5606 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5607 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5608 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5609 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5612 return (WORDS_BIG_ENDIAN)
5613 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5614 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5616 [(set_attr "type" "imul")
5617 (set_attr "length" "8")])
5620 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5621 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5622 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5623 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5626 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
5627 (zero_extend:DI (match_dup 2)))
5630 (mult:SI (match_dup 1)
5634 int endian = (WORDS_BIG_ENDIAN == 0);
5635 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5636 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5639 (define_expand "smulsi3_highpart"
5640 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5642 (lshiftrt:DI (mult:DI (sign_extend:DI
5643 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5645 (match_operand:SI 2 "gpc_reg_operand" "r")))
5650 if (! TARGET_POWER && ! TARGET_POWERPC)
5652 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5653 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5654 emit_insn (gen_mulh_call ());
5655 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
5658 else if (TARGET_POWER)
5660 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5665 (define_insn "smulsi3_highpart_mq"
5666 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5668 (lshiftrt:DI (mult:DI (sign_extend:DI
5669 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5671 (match_operand:SI 2 "gpc_reg_operand" "r")))
5673 (clobber (match_scratch:SI 3 "=q"))]
5676 [(set_attr "type" "imul")])
5678 (define_insn "*smulsi3_highpart_no_mq"
5679 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5681 (lshiftrt:DI (mult:DI (sign_extend:DI
5682 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5684 (match_operand:SI 2 "gpc_reg_operand" "r")))
5686 "TARGET_POWERPC && ! TARGET_POWER"
5688 [(set_attr "type" "imul")])
5690 (define_expand "umulsi3_highpart"
5691 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5693 (lshiftrt:DI (mult:DI (zero_extend:DI
5694 (match_operand:SI 1 "gpc_reg_operand" ""))
5696 (match_operand:SI 2 "gpc_reg_operand" "")))
5703 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5708 (define_insn "umulsi3_highpart_mq"
5709 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5711 (lshiftrt:DI (mult:DI (zero_extend:DI
5712 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5714 (match_operand:SI 2 "gpc_reg_operand" "r")))
5716 (clobber (match_scratch:SI 3 "=q"))]
5717 "TARGET_POWERPC && TARGET_POWER"
5719 [(set_attr "type" "imul")])
5721 (define_insn "*umulsi3_highpart_no_mq"
5722 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5724 (lshiftrt:DI (mult:DI (zero_extend:DI
5725 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5727 (match_operand:SI 2 "gpc_reg_operand" "r")))
5729 "TARGET_POWERPC && ! TARGET_POWER"
5731 [(set_attr "type" "imul")])
5733 ;; If operands 0 and 2 are in the same register, we have a problem. But
5734 ;; operands 0 and 1 (the usual case) can be in the same register. That's
5735 ;; why we have the strange constraints below.
5736 (define_insn "ashldi3_power"
5737 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5738 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5739 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5740 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5743 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
5744 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5745 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5746 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
5747 [(set_attr "length" "8")])
5749 (define_insn "lshrdi3_power"
5750 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5751 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5752 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5753 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5756 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
5757 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5758 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5759 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
5760 [(set_attr "length" "8")])
5762 ;; Shift by a variable amount is too complex to be worth open-coding. We
5763 ;; just handle shifts by constants.
5764 (define_insn "ashrdi3_power"
5765 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5766 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5767 (match_operand:SI 2 "const_int_operand" "M,i")))
5768 (clobber (match_scratch:SI 3 "=X,q"))]
5771 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5772 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
5773 [(set_attr "length" "8")])
5775 (define_insn "ashrdi3_no_power"
5776 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
5777 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5778 (match_operand:SI 2 "const_int_operand" "M,i")))]
5779 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
5781 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5782 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
5783 [(set_attr "type" "two,three")
5784 (set_attr "length" "8,12")])
5786 (define_insn "*ashrdisi3_noppc64"
5787 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5788 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5789 (const_int 32)) 4))]
5790 "TARGET_32BIT && !TARGET_POWERPC64"
5793 if (REGNO (operands[0]) == REGNO (operands[1]))
5796 return \"mr %0,%1\";
5798 [(set_attr "length" "4")])
5801 ;; PowerPC64 DImode operations.
5803 (define_insn_and_split "absdi2"
5804 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5805 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
5806 (clobber (match_scratch:DI 2 "=&r,&r"))]
5809 "&& reload_completed"
5810 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5811 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5812 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
5815 (define_insn_and_split "*nabsdi2"
5816 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5817 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
5818 (clobber (match_scratch:DI 2 "=&r,&r"))]
5821 "&& reload_completed"
5822 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5823 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5824 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
5827 (define_insn "muldi3"
5828 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5829 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
5830 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
5836 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
5837 (const_string "imul3")
5838 (match_operand:SI 2 "short_cint_operand" "")
5839 (const_string "imul2")]
5840 (const_string "lmul")))])
5842 (define_insn "*muldi3_internal1"
5843 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5844 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
5845 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5847 (clobber (match_scratch:DI 3 "=r,r"))]
5852 [(set_attr "type" "lmul_compare")
5853 (set_attr "length" "4,8")])
5856 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5857 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
5858 (match_operand:DI 2 "gpc_reg_operand" ""))
5860 (clobber (match_scratch:DI 3 ""))]
5861 "TARGET_POWERPC64 && reload_completed"
5863 (mult:DI (match_dup 1) (match_dup 2)))
5865 (compare:CC (match_dup 3)
5869 (define_insn "*muldi3_internal2"
5870 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5871 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
5872 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5874 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5875 (mult:DI (match_dup 1) (match_dup 2)))]
5880 [(set_attr "type" "lmul_compare")
5881 (set_attr "length" "4,8")])
5884 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5885 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
5886 (match_operand:DI 2 "gpc_reg_operand" ""))
5888 (set (match_operand:DI 0 "gpc_reg_operand" "")
5889 (mult:DI (match_dup 1) (match_dup 2)))]
5890 "TARGET_POWERPC64 && reload_completed"
5892 (mult:DI (match_dup 1) (match_dup 2)))
5894 (compare:CC (match_dup 0)
5898 (define_insn "smuldi3_highpart"
5899 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5901 (lshiftrt:TI (mult:TI (sign_extend:TI
5902 (match_operand:DI 1 "gpc_reg_operand" "%r"))
5904 (match_operand:DI 2 "gpc_reg_operand" "r")))
5908 [(set_attr "type" "lmul")])
5910 (define_insn "umuldi3_highpart"
5911 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5913 (lshiftrt:TI (mult:TI (zero_extend:TI
5914 (match_operand:DI 1 "gpc_reg_operand" "%r"))
5916 (match_operand:DI 2 "gpc_reg_operand" "r")))
5920 [(set_attr "type" "lmul")])
5922 (define_insn "rotldi3"
5923 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5924 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5925 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
5927 "rld%I2cl %0,%1,%H2,0")
5929 (define_insn "*rotldi3_internal2"
5930 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5931 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5932 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
5934 (clobber (match_scratch:DI 3 "=r,r"))]
5937 rld%I2cl. %3,%1,%H2,0
5939 [(set_attr "type" "delayed_compare")
5940 (set_attr "length" "4,8")])
5943 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5944 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
5945 (match_operand:DI 2 "reg_or_cint_operand" ""))
5947 (clobber (match_scratch:DI 3 ""))]
5948 "TARGET_POWERPC64 && reload_completed"
5950 (rotate:DI (match_dup 1) (match_dup 2)))
5952 (compare:CC (match_dup 3)
5956 (define_insn "*rotldi3_internal3"
5957 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5958 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5959 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
5961 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5962 (rotate:DI (match_dup 1) (match_dup 2)))]
5965 rld%I2cl. %0,%1,%H2,0
5967 [(set_attr "type" "delayed_compare")
5968 (set_attr "length" "4,8")])
5971 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5972 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
5973 (match_operand:DI 2 "reg_or_cint_operand" ""))
5975 (set (match_operand:DI 0 "gpc_reg_operand" "")
5976 (rotate:DI (match_dup 1) (match_dup 2)))]
5977 "TARGET_POWERPC64 && reload_completed"
5979 (rotate:DI (match_dup 1) (match_dup 2)))
5981 (compare:CC (match_dup 0)
5985 (define_insn "*rotldi3_internal4"
5986 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5987 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5988 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
5989 (match_operand:DI 3 "mask64_operand" "n")))]
5991 "rld%I2c%B3 %0,%1,%H2,%S3")
5993 (define_insn "*rotldi3_internal5"
5994 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5996 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5997 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
5998 (match_operand:DI 3 "mask64_operand" "n,n"))
6000 (clobber (match_scratch:DI 4 "=r,r"))]
6003 rld%I2c%B3. %4,%1,%H2,%S3
6005 [(set_attr "type" "delayed_compare")
6006 (set_attr "length" "4,8")])
6009 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6011 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6012 (match_operand:DI 2 "reg_or_cint_operand" ""))
6013 (match_operand:DI 3 "mask64_operand" ""))
6015 (clobber (match_scratch:DI 4 ""))]
6016 "TARGET_POWERPC64 && reload_completed"
6018 (and:DI (rotate:DI (match_dup 1)
6022 (compare:CC (match_dup 4)
6026 (define_insn "*rotldi3_internal6"
6027 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6029 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6030 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6031 (match_operand:DI 3 "mask64_operand" "n,n"))
6033 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6034 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6037 rld%I2c%B3. %0,%1,%H2,%S3
6039 [(set_attr "type" "delayed_compare")
6040 (set_attr "length" "4,8")])
6043 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6045 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6046 (match_operand:DI 2 "reg_or_cint_operand" ""))
6047 (match_operand:DI 3 "mask64_operand" ""))
6049 (set (match_operand:DI 0 "gpc_reg_operand" "")
6050 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6051 "TARGET_POWERPC64 && reload_completed"
6053 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6055 (compare:CC (match_dup 0)
6059 (define_insn "*rotldi3_internal7"
6060 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6063 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6064 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6066 "rld%I2cl %0,%1,%H2,56")
6068 (define_insn "*rotldi3_internal8"
6069 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6070 (compare:CC (zero_extend:DI
6072 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6073 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6075 (clobber (match_scratch:DI 3 "=r,r"))]
6078 rld%I2cl. %3,%1,%H2,56
6080 [(set_attr "type" "delayed_compare")
6081 (set_attr "length" "4,8")])
6084 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6085 (compare:CC (zero_extend:DI
6087 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6088 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6090 (clobber (match_scratch:DI 3 ""))]
6091 "TARGET_POWERPC64 && reload_completed"
6093 (zero_extend:DI (subreg:QI
6094 (rotate:DI (match_dup 1)
6097 (compare:CC (match_dup 3)
6101 (define_insn "*rotldi3_internal9"
6102 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6103 (compare:CC (zero_extend:DI
6105 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6106 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6108 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6109 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6112 rld%I2cl. %0,%1,%H2,56
6114 [(set_attr "type" "delayed_compare")
6115 (set_attr "length" "4,8")])
6118 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6119 (compare:CC (zero_extend:DI
6121 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6122 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6124 (set (match_operand:DI 0 "gpc_reg_operand" "")
6125 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6126 "TARGET_POWERPC64 && reload_completed"
6128 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6130 (compare:CC (match_dup 0)
6134 (define_insn "*rotldi3_internal10"
6135 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6138 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6139 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6141 "rld%I2cl %0,%1,%H2,48")
6143 (define_insn "*rotldi3_internal11"
6144 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6145 (compare:CC (zero_extend:DI
6147 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6148 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6150 (clobber (match_scratch:DI 3 "=r,r"))]
6153 rld%I2cl. %3,%1,%H2,48
6155 [(set_attr "type" "delayed_compare")
6156 (set_attr "length" "4,8")])
6159 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6160 (compare:CC (zero_extend:DI
6162 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6163 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6165 (clobber (match_scratch:DI 3 ""))]
6166 "TARGET_POWERPC64 && reload_completed"
6168 (zero_extend:DI (subreg:HI
6169 (rotate:DI (match_dup 1)
6172 (compare:CC (match_dup 3)
6176 (define_insn "*rotldi3_internal12"
6177 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6178 (compare:CC (zero_extend:DI
6180 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6181 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6183 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6184 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6187 rld%I2cl. %0,%1,%H2,48
6189 [(set_attr "type" "delayed_compare")
6190 (set_attr "length" "4,8")])
6193 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6194 (compare:CC (zero_extend:DI
6196 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6197 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6199 (set (match_operand:DI 0 "gpc_reg_operand" "")
6200 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6201 "TARGET_POWERPC64 && reload_completed"
6203 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6205 (compare:CC (match_dup 0)
6209 (define_insn "*rotldi3_internal13"
6210 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6213 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6214 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6216 "rld%I2cl %0,%1,%H2,32")
6218 (define_insn "*rotldi3_internal14"
6219 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6220 (compare:CC (zero_extend:DI
6222 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6223 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6225 (clobber (match_scratch:DI 3 "=r,r"))]
6228 rld%I2cl. %3,%1,%H2,32
6230 [(set_attr "type" "delayed_compare")
6231 (set_attr "length" "4,8")])
6234 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6235 (compare:CC (zero_extend:DI
6237 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6238 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6240 (clobber (match_scratch:DI 3 ""))]
6241 "TARGET_POWERPC64 && reload_completed"
6243 (zero_extend:DI (subreg:SI
6244 (rotate:DI (match_dup 1)
6247 (compare:CC (match_dup 3)
6251 (define_insn "*rotldi3_internal15"
6252 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6253 (compare:CC (zero_extend:DI
6255 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6256 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6258 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6259 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6262 rld%I2cl. %0,%1,%H2,32
6264 [(set_attr "type" "delayed_compare")
6265 (set_attr "length" "4,8")])
6268 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6269 (compare:CC (zero_extend:DI
6271 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6272 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6274 (set (match_operand:DI 0 "gpc_reg_operand" "")
6275 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6276 "TARGET_POWERPC64 && reload_completed"
6278 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6280 (compare:CC (match_dup 0)
6284 (define_expand "ashldi3"
6285 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6286 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6287 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6288 "TARGET_POWERPC64 || TARGET_POWER"
6291 if (TARGET_POWERPC64)
6293 else if (TARGET_POWER)
6295 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6302 (define_insn "*ashldi3_internal1"
6303 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6304 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6305 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6309 (define_insn "*ashldi3_internal2"
6310 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6311 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6312 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6314 (clobber (match_scratch:DI 3 "=r,r"))]
6319 [(set_attr "type" "delayed_compare")
6320 (set_attr "length" "4,8")])
6323 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6324 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6325 (match_operand:SI 2 "reg_or_cint_operand" ""))
6327 (clobber (match_scratch:DI 3 ""))]
6328 "TARGET_POWERPC64 && reload_completed"
6330 (ashift:DI (match_dup 1) (match_dup 2)))
6332 (compare:CC (match_dup 3)
6336 (define_insn "*ashldi3_internal3"
6337 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6338 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6339 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6341 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6342 (ashift:DI (match_dup 1) (match_dup 2)))]
6347 [(set_attr "type" "delayed_compare")
6348 (set_attr "length" "4,8")])
6351 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6352 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6353 (match_operand:SI 2 "reg_or_cint_operand" ""))
6355 (set (match_operand:DI 0 "gpc_reg_operand" "")
6356 (ashift:DI (match_dup 1) (match_dup 2)))]
6357 "TARGET_POWERPC64 && reload_completed"
6359 (ashift:DI (match_dup 1) (match_dup 2)))
6361 (compare:CC (match_dup 0)
6365 (define_insn "*ashldi3_internal4"
6366 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6367 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6368 (match_operand:SI 2 "const_int_operand" "i"))
6369 (match_operand:DI 3 "const_int_operand" "n")))]
6370 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6371 "rldic %0,%1,%H2,%W3")
6373 (define_insn "ashldi3_internal5"
6374 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6376 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6377 (match_operand:SI 2 "const_int_operand" "i,i"))
6378 (match_operand:DI 3 "const_int_operand" "n,n"))
6380 (clobber (match_scratch:DI 4 "=r,r"))]
6381 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6383 rldic. %4,%1,%H2,%W3
6385 [(set_attr "type" "compare")
6386 (set_attr "length" "4,8")])
6389 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6391 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6392 (match_operand:SI 2 "const_int_operand" ""))
6393 (match_operand:DI 3 "const_int_operand" ""))
6395 (clobber (match_scratch:DI 4 ""))]
6396 "TARGET_POWERPC64 && reload_completed
6397 && includes_rldic_lshift_p (operands[2], operands[3])"
6399 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6402 (compare:CC (match_dup 4)
6406 (define_insn "*ashldi3_internal6"
6407 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6409 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6410 (match_operand:SI 2 "const_int_operand" "i,i"))
6411 (match_operand:DI 3 "const_int_operand" "n,n"))
6413 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6414 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6415 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6417 rldic. %0,%1,%H2,%W3
6419 [(set_attr "type" "compare")
6420 (set_attr "length" "4,8")])
6423 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6425 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6426 (match_operand:SI 2 "const_int_operand" ""))
6427 (match_operand:DI 3 "const_int_operand" ""))
6429 (set (match_operand:DI 0 "gpc_reg_operand" "")
6430 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6431 "TARGET_POWERPC64 && reload_completed
6432 && includes_rldic_lshift_p (operands[2], operands[3])"
6434 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6437 (compare:CC (match_dup 0)
6441 (define_insn "*ashldi3_internal7"
6442 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6443 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6444 (match_operand:SI 2 "const_int_operand" "i"))
6445 (match_operand:DI 3 "mask64_operand" "n")))]
6446 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6447 "rldicr %0,%1,%H2,%S3")
6449 (define_insn "ashldi3_internal8"
6450 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6452 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6453 (match_operand:SI 2 "const_int_operand" "i,i"))
6454 (match_operand:DI 3 "mask64_operand" "n,n"))
6456 (clobber (match_scratch:DI 4 "=r,r"))]
6457 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6459 rldicr. %4,%1,%H2,%S3
6461 [(set_attr "type" "compare")
6462 (set_attr "length" "4,8")])
6465 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6467 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6468 (match_operand:SI 2 "const_int_operand" ""))
6469 (match_operand:DI 3 "mask64_operand" ""))
6471 (clobber (match_scratch:DI 4 ""))]
6472 "TARGET_POWERPC64 && reload_completed
6473 && includes_rldicr_lshift_p (operands[2], operands[3])"
6475 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6478 (compare:CC (match_dup 4)
6482 (define_insn "*ashldi3_internal9"
6483 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6485 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6486 (match_operand:SI 2 "const_int_operand" "i,i"))
6487 (match_operand:DI 3 "mask64_operand" "n,n"))
6489 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6490 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6491 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6493 rldicr. %0,%1,%H2,%S3
6495 [(set_attr "type" "compare")
6496 (set_attr "length" "4,8")])
6499 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6501 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6502 (match_operand:SI 2 "const_int_operand" ""))
6503 (match_operand:DI 3 "mask64_operand" ""))
6505 (set (match_operand:DI 0 "gpc_reg_operand" "")
6506 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6507 "TARGET_POWERPC64 && reload_completed
6508 && includes_rldicr_lshift_p (operands[2], operands[3])"
6510 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6513 (compare:CC (match_dup 0)
6517 (define_expand "lshrdi3"
6518 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6519 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6520 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6521 "TARGET_POWERPC64 || TARGET_POWER"
6524 if (TARGET_POWERPC64)
6526 else if (TARGET_POWER)
6528 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
6535 (define_insn "*lshrdi3_internal1"
6536 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6537 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6538 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6542 (define_insn "*lshrdi3_internal2"
6543 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6544 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6545 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6547 (clobber (match_scratch:DI 3 "=r,r"))]
6552 [(set_attr "type" "delayed_compare")
6553 (set_attr "length" "4,8")])
6556 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6557 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6558 (match_operand:SI 2 "reg_or_cint_operand" ""))
6560 (clobber (match_scratch:DI 3 ""))]
6561 "TARGET_POWERPC64 && reload_completed"
6563 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6565 (compare:CC (match_dup 3)
6569 (define_insn "*lshrdi3_internal3"
6570 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6571 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6572 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6574 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6575 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6580 [(set_attr "type" "delayed_compare")
6581 (set_attr "length" "4,8")])
6584 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6585 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6586 (match_operand:SI 2 "reg_or_cint_operand" ""))
6588 (set (match_operand:DI 0 "gpc_reg_operand" "")
6589 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6590 "TARGET_POWERPC64 && reload_completed"
6592 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6594 (compare:CC (match_dup 0)
6598 (define_expand "ashrdi3"
6599 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6600 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6601 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6605 if (TARGET_POWERPC64)
6607 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
6609 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
6612 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
6613 && WORDS_BIG_ENDIAN)
6615 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
6622 (define_insn "*ashrdi3_internal1"
6623 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6624 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6625 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6627 "srad%I2 %0,%1,%H2")
6629 (define_insn "*ashrdi3_internal2"
6630 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6631 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6632 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6634 (clobber (match_scratch:DI 3 "=r,r"))]
6639 [(set_attr "type" "delayed_compare")
6640 (set_attr "length" "4,8")])
6643 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6644 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6645 (match_operand:SI 2 "reg_or_cint_operand" ""))
6647 (clobber (match_scratch:DI 3 ""))]
6648 "TARGET_POWERPC64 && reload_completed"
6650 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6652 (compare:CC (match_dup 3)
6656 (define_insn "*ashrdi3_internal3"
6657 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6658 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6659 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6661 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6662 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6667 [(set_attr "type" "delayed_compare")
6668 (set_attr "length" "4,8")])
6671 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6672 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6673 (match_operand:SI 2 "reg_or_cint_operand" ""))
6675 (set (match_operand:DI 0 "gpc_reg_operand" "")
6676 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6677 "TARGET_POWERPC64 && reload_completed"
6679 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6681 (compare:CC (match_dup 0)
6685 (define_insn "anddi3"
6686 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
6687 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
6688 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
6689 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
6693 rldic%B2 %0,%1,0,%S2
6694 rlwinm %0,%1,0,%m2,%M2
6698 [(set_attr "type" "*,*,*,compare,compare,*")
6699 (set_attr "length" "4,4,4,4,4,8")])
6702 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6703 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6704 (match_operand:DI 2 "mask64_2_operand" "")))
6705 (clobber (match_scratch:CC 3 ""))]
6707 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
6708 && !mask_operand (operands[2], DImode)
6709 && !mask64_operand (operands[2], DImode)"
6711 (and:DI (rotate:DI (match_dup 1)
6715 (and:DI (rotate:DI (match_dup 0)
6719 build_mask64_2_operands (operands[2], &operands[4]);
6722 (define_insn "*anddi3_internal2"
6723 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
6724 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
6725 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
6727 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
6728 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
6732 rldic%B2. %3,%1,0,%S2
6733 rlwinm. %3,%1,0,%m2,%M2
6743 [(set_attr "type" "compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
6744 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
6747 [(set (match_operand:CC 0 "cc_reg_operand" "")
6748 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6749 (match_operand:DI 2 "mask64_2_operand" ""))
6751 (clobber (match_scratch:DI 3 ""))
6752 (clobber (match_scratch:CC 4 ""))]
6753 "TARGET_64BIT && reload_completed
6754 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
6755 && !mask_operand (operands[2], DImode)
6756 && !mask64_operand (operands[2], DImode)"
6758 (and:DI (rotate:DI (match_dup 1)
6761 (parallel [(set (match_dup 0)
6762 (compare:CC (and:DI (rotate:DI (match_dup 3)
6766 (clobber (match_dup 3))])]
6769 build_mask64_2_operands (operands[2], &operands[5]);
6772 (define_insn "*anddi3_internal3"
6773 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
6774 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
6775 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
6777 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
6778 (and:DI (match_dup 1) (match_dup 2)))
6779 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
6783 rldic%B2. %0,%1,0,%S2
6784 rlwinm. %0,%1,0,%m2,%M2
6794 [(set_attr "type" "compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
6795 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
6798 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6799 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6800 (match_operand:DI 2 "and64_2_operand" ""))
6802 (set (match_operand:DI 0 "gpc_reg_operand" "")
6803 (and:DI (match_dup 1) (match_dup 2)))
6804 (clobber (match_scratch:CC 4 ""))]
6805 "TARGET_64BIT && reload_completed"
6806 [(parallel [(set (match_dup 0)
6807 (and:DI (match_dup 1) (match_dup 2)))
6808 (clobber (match_dup 4))])
6810 (compare:CC (match_dup 0)
6815 [(set (match_operand:CC 3 "cc_reg_operand" "")
6816 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6817 (match_operand:DI 2 "mask64_2_operand" ""))
6819 (set (match_operand:DI 0 "gpc_reg_operand" "")
6820 (and:DI (match_dup 1) (match_dup 2)))
6821 (clobber (match_scratch:CC 4 ""))]
6822 "TARGET_64BIT && reload_completed
6823 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
6824 && !mask_operand (operands[2], DImode)
6825 && !mask64_operand (operands[2], DImode)"
6827 (and:DI (rotate:DI (match_dup 1)
6830 (parallel [(set (match_dup 3)
6831 (compare:CC (and:DI (rotate:DI (match_dup 0)
6836 (and:DI (rotate:DI (match_dup 0)
6841 build_mask64_2_operands (operands[2], &operands[5]);
6844 (define_expand "iordi3"
6845 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6846 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
6847 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
6851 if (non_logical_cint_operand (operands[2], DImode))
6853 HOST_WIDE_INT value;
6854 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
6855 ? operands[0] : gen_reg_rtx (DImode));
6857 if (GET_CODE (operands[2]) == CONST_INT)
6859 value = INTVAL (operands[2]);
6860 emit_insn (gen_iordi3 (tmp, operands[1],
6861 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
6865 value = CONST_DOUBLE_LOW (operands[2]);
6866 emit_insn (gen_iordi3 (tmp, operands[1],
6867 immed_double_const (value
6868 & (~ (HOST_WIDE_INT) 0xffff),
6872 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
6877 (define_expand "xordi3"
6878 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6879 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
6880 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
6884 if (non_logical_cint_operand (operands[2], DImode))
6886 HOST_WIDE_INT value;
6887 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
6888 ? operands[0] : gen_reg_rtx (DImode));
6890 if (GET_CODE (operands[2]) == CONST_INT)
6892 value = INTVAL (operands[2]);
6893 emit_insn (gen_xordi3 (tmp, operands[1],
6894 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
6898 value = CONST_DOUBLE_LOW (operands[2]);
6899 emit_insn (gen_xordi3 (tmp, operands[1],
6900 immed_double_const (value
6901 & (~ (HOST_WIDE_INT) 0xffff),
6905 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
6910 (define_insn "*booldi3_internal1"
6911 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
6912 (match_operator:DI 3 "boolean_or_operator"
6913 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
6914 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
6921 (define_insn "*booldi3_internal2"
6922 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6923 (compare:CC (match_operator:DI 4 "boolean_or_operator"
6924 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
6925 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
6927 (clobber (match_scratch:DI 3 "=r,r"))]
6932 [(set_attr "type" "compare")
6933 (set_attr "length" "4,8")])
6936 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6937 (compare:CC (match_operator:DI 4 "boolean_operator"
6938 [(match_operand:DI 1 "gpc_reg_operand" "")
6939 (match_operand:DI 2 "gpc_reg_operand" "")])
6941 (clobber (match_scratch:DI 3 ""))]
6942 "TARGET_POWERPC64 && reload_completed"
6943 [(set (match_dup 3) (match_dup 4))
6945 (compare:CC (match_dup 3)
6949 (define_insn "*booldi3_internal3"
6950 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6951 (compare:CC (match_operator:DI 4 "boolean_operator"
6952 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
6953 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
6955 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6961 [(set_attr "type" "compare")
6962 (set_attr "length" "4,8")])
6965 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6966 (compare:CC (match_operator:DI 4 "boolean_operator"
6967 [(match_operand:DI 1 "gpc_reg_operand" "")
6968 (match_operand:DI 2 "gpc_reg_operand" "")])
6970 (set (match_operand:DI 0 "gpc_reg_operand" "")
6972 "TARGET_POWERPC64 && reload_completed"
6973 [(set (match_dup 0) (match_dup 4))
6975 (compare:CC (match_dup 0)
6979 ;; Split a logical operation that we can't do in one insn into two insns,
6980 ;; each of which does one 16-bit part. This is used by combine.
6983 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6984 (match_operator:DI 3 "boolean_or_operator"
6985 [(match_operand:DI 1 "gpc_reg_operand" "")
6986 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
6988 [(set (match_dup 0) (match_dup 4))
6989 (set (match_dup 0) (match_dup 5))]
6994 if (GET_CODE (operands[2]) == CONST_DOUBLE)
6996 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
6997 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
6999 i4 = GEN_INT (value & 0xffff);
7003 i3 = GEN_INT (INTVAL (operands[2])
7004 & (~ (HOST_WIDE_INT) 0xffff));
7005 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7007 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7009 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7013 (define_insn "*boolcdi3_internal1"
7014 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7015 (match_operator:DI 3 "boolean_operator"
7016 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7017 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7021 (define_insn "*boolcdi3_internal2"
7022 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7023 (compare:CC (match_operator:DI 4 "boolean_operator"
7024 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7025 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7027 (clobber (match_scratch:DI 3 "=r,r"))]
7032 [(set_attr "type" "compare")
7033 (set_attr "length" "4,8")])
7036 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7037 (compare:CC (match_operator:DI 4 "boolean_operator"
7038 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7039 (match_operand:DI 2 "gpc_reg_operand" "")])
7041 (clobber (match_scratch:DI 3 ""))]
7042 "TARGET_POWERPC64 && reload_completed"
7043 [(set (match_dup 3) (match_dup 4))
7045 (compare:CC (match_dup 3)
7049 (define_insn "*boolcdi3_internal3"
7050 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7051 (compare:CC (match_operator:DI 4 "boolean_operator"
7052 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7053 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7055 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7061 [(set_attr "type" "compare")
7062 (set_attr "length" "4,8")])
7065 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7066 (compare:CC (match_operator:DI 4 "boolean_operator"
7067 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7068 (match_operand:DI 2 "gpc_reg_operand" "")])
7070 (set (match_operand:DI 0 "gpc_reg_operand" "")
7072 "TARGET_POWERPC64 && reload_completed"
7073 [(set (match_dup 0) (match_dup 4))
7075 (compare:CC (match_dup 0)
7079 (define_insn "*boolccdi3_internal1"
7080 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7081 (match_operator:DI 3 "boolean_operator"
7082 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7083 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7087 (define_insn "*boolccdi3_internal2"
7088 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7089 (compare:CC (match_operator:DI 4 "boolean_operator"
7090 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7091 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7093 (clobber (match_scratch:DI 3 "=r,r"))]
7098 [(set_attr "type" "compare")
7099 (set_attr "length" "4,8")])
7102 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7103 (compare:CC (match_operator:DI 4 "boolean_operator"
7104 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7105 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7107 (clobber (match_scratch:DI 3 ""))]
7108 "TARGET_POWERPC64 && reload_completed"
7109 [(set (match_dup 3) (match_dup 4))
7111 (compare:CC (match_dup 3)
7115 (define_insn "*boolccdi3_internal3"
7116 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7117 (compare:CC (match_operator:DI 4 "boolean_operator"
7118 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7119 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7121 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7127 [(set_attr "type" "compare")
7128 (set_attr "length" "4,8")])
7131 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7132 (compare:CC (match_operator:DI 4 "boolean_operator"
7133 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7134 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7136 (set (match_operand:DI 0 "gpc_reg_operand" "")
7138 "TARGET_POWERPC64 && reload_completed"
7139 [(set (match_dup 0) (match_dup 4))
7141 (compare:CC (match_dup 0)
7145 ;; Now define ways of moving data around.
7147 ;; Set up a register with a value from the GOT table
7149 (define_expand "movsi_got"
7150 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7151 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7152 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7153 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7156 if (GET_CODE (operands[1]) == CONST)
7158 rtx offset = const0_rtx;
7159 HOST_WIDE_INT value;
7161 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7162 value = INTVAL (offset);
7165 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7166 emit_insn (gen_movsi_got (tmp, operands[1]));
7167 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7172 operands[2] = rs6000_got_register (operands[1]);
7175 (define_insn "*movsi_got_internal"
7176 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7177 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7178 (match_operand:SI 2 "gpc_reg_operand" "b")]
7180 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7181 "{l|lwz} %0,%a1@got(%2)"
7182 [(set_attr "type" "load")])
7184 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7185 ;; didn't get allocated to a hard register.
7187 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7188 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7189 (match_operand:SI 2 "memory_operand" "")]
7191 "DEFAULT_ABI == ABI_V4
7193 && (reload_in_progress || reload_completed)"
7194 [(set (match_dup 0) (match_dup 2))
7195 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7199 ;; For SI, we special-case integers that can't be loaded in one insn. We
7200 ;; do the load 16-bits at a time. We could do this by loading from memory,
7201 ;; and this is even supposed to be faster, but it is simpler not to get
7202 ;; integers in the TOC.
7203 (define_insn "movsi_low"
7204 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7205 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7206 (match_operand 2 "" ""))))]
7207 "TARGET_MACHO && ! TARGET_64BIT"
7208 "{l|lwz} %0,lo16(%2)(%1)"
7209 [(set_attr "type" "load")
7210 (set_attr "length" "4")])
7212 (define_insn "*movsi_internal1"
7213 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7214 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7215 "gpc_reg_operand (operands[0], SImode)
7216 || gpc_reg_operand (operands[1], SImode)"
7220 {l%U1%X1|lwz%U1%X1} %0,%1
7221 {st%U0%X0|stw%U0%X0} %1,%0
7231 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
7232 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7234 ;; Split a load of a large constant into the appropriate two-insn
7238 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7239 (match_operand:SI 1 "const_int_operand" ""))]
7240 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7241 && (INTVAL (operands[1]) & 0xffff) != 0"
7245 (ior:SI (match_dup 0)
7248 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7250 if (tem == operands[0])
7256 (define_insn "*mov<mode>_internal2"
7257 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7258 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
7260 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7263 {cmpi|cmp<wd>i} %2,%0,0
7266 [(set_attr "type" "cmp,compare,cmp")
7267 (set_attr "length" "4,4,8")])
7270 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7271 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
7273 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
7275 [(set (match_dup 0) (match_dup 1))
7277 (compare:CC (match_dup 0)
7281 (define_insn "*movhi_internal"
7282 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7283 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7284 "gpc_reg_operand (operands[0], HImode)
7285 || gpc_reg_operand (operands[1], HImode)"
7295 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7297 (define_expand "mov<mode>"
7298 [(set (match_operand:INT 0 "general_operand" "")
7299 (match_operand:INT 1 "any_operand" ""))]
7301 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7303 (define_insn "*movqi_internal"
7304 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7305 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7306 "gpc_reg_operand (operands[0], QImode)
7307 || gpc_reg_operand (operands[1], QImode)"
7317 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7319 ;; Here is how to move condition codes around. When we store CC data in
7320 ;; an integer register or memory, we store just the high-order 4 bits.
7321 ;; This lets us not shift in the most common case of CR0.
7322 (define_expand "movcc"
7323 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7324 (match_operand:CC 1 "nonimmediate_operand" ""))]
7328 (define_insn "*movcc_internal1"
7329 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m")
7330 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))]
7331 "register_operand (operands[0], CCmode)
7332 || register_operand (operands[1], CCmode)"
7336 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7338 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7343 {l%U1%X1|lwz%U1%X1} %0,%1
7344 {st%U0%U1|stw%U0%U1} %1,%0"
7346 (cond [(eq_attr "alternative" "0")
7347 (const_string "cr_logical")
7348 (eq_attr "alternative" "1,2")
7349 (const_string "mtcr")
7350 (eq_attr "alternative" "5,7")
7351 (const_string "integer")
7352 (eq_attr "alternative" "6")
7353 (const_string "mfjmpr")
7354 (eq_attr "alternative" "8")
7355 (const_string "mtjmpr")
7356 (eq_attr "alternative" "9")
7357 (const_string "load")
7358 (eq_attr "alternative" "10")
7359 (const_string "store")
7360 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
7361 (const_string "mfcrf")
7363 (const_string "mfcr")))
7364 (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
7366 ;; For floating-point, we normally deal with the floating-point registers
7367 ;; unless -msoft-float is used. The sole exception is that parameter passing
7368 ;; can produce floating-point values in fixed-point registers. Unless the
7369 ;; value is a simple constant or already in memory, we deal with this by
7370 ;; allocating memory and copying the value explicitly via that memory location.
7371 (define_expand "movsf"
7372 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7373 (match_operand:SF 1 "any_operand" ""))]
7375 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7378 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7379 (match_operand:SF 1 "const_double_operand" ""))]
7381 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7382 || (GET_CODE (operands[0]) == SUBREG
7383 && GET_CODE (SUBREG_REG (operands[0])) == REG
7384 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7385 [(set (match_dup 2) (match_dup 3))]
7391 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7392 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7394 if (! TARGET_POWERPC64)
7395 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7397 operands[2] = gen_lowpart (SImode, operands[0]);
7399 operands[3] = gen_int_mode (l, SImode);
7402 (define_insn "*movsf_hardfloat"
7403 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
7404 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
7405 "(gpc_reg_operand (operands[0], SFmode)
7406 || gpc_reg_operand (operands[1], SFmode))
7407 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
7410 {l%U1%X1|lwz%U1%X1} %0,%1
7411 {st%U0%X0|stw%U0%X0} %1,%0
7421 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
7422 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
7424 (define_insn "*movsf_softfloat"
7425 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
7426 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
7427 "(gpc_reg_operand (operands[0], SFmode)
7428 || gpc_reg_operand (operands[1], SFmode))
7429 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7435 {l%U1%X1|lwz%U1%X1} %0,%1
7436 {st%U0%X0|stw%U0%X0} %1,%0
7443 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
7444 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
7447 (define_expand "movdf"
7448 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7449 (match_operand:DF 1 "any_operand" ""))]
7451 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
7454 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7455 (match_operand:DF 1 "const_int_operand" ""))]
7456 "! TARGET_POWERPC64 && reload_completed
7457 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7458 || (GET_CODE (operands[0]) == SUBREG
7459 && GET_CODE (SUBREG_REG (operands[0])) == REG
7460 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7461 [(set (match_dup 2) (match_dup 4))
7462 (set (match_dup 3) (match_dup 1))]
7465 int endian = (WORDS_BIG_ENDIAN == 0);
7466 HOST_WIDE_INT value = INTVAL (operands[1]);
7468 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7469 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7470 #if HOST_BITS_PER_WIDE_INT == 32
7471 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7473 operands[4] = GEN_INT (value >> 32);
7474 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7479 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7480 (match_operand:DF 1 "const_double_operand" ""))]
7481 "! TARGET_POWERPC64 && reload_completed
7482 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7483 || (GET_CODE (operands[0]) == SUBREG
7484 && GET_CODE (SUBREG_REG (operands[0])) == REG
7485 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7486 [(set (match_dup 2) (match_dup 4))
7487 (set (match_dup 3) (match_dup 5))]
7490 int endian = (WORDS_BIG_ENDIAN == 0);
7494 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7495 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7497 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7498 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7499 operands[4] = gen_int_mode (l[endian], SImode);
7500 operands[5] = gen_int_mode (l[1 - endian], SImode);
7504 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7505 (match_operand:DF 1 "const_double_operand" ""))]
7506 "TARGET_POWERPC64 && reload_completed
7507 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7508 || (GET_CODE (operands[0]) == SUBREG
7509 && GET_CODE (SUBREG_REG (operands[0])) == REG
7510 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7511 [(set (match_dup 2) (match_dup 3))]
7514 int endian = (WORDS_BIG_ENDIAN == 0);
7517 #if HOST_BITS_PER_WIDE_INT >= 64
7521 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7522 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7524 operands[2] = gen_lowpart (DImode, operands[0]);
7525 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
7526 #if HOST_BITS_PER_WIDE_INT >= 64
7527 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
7528 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
7530 operands[3] = gen_int_mode (val, DImode);
7532 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
7536 ;; Don't have reload use general registers to load a constant. First,
7537 ;; it might not work if the output operand is the equivalent of
7538 ;; a non-offsettable memref, but also it is less efficient than loading
7539 ;; the constant into an FP register, since it will probably be used there.
7540 ;; The "??" is a kludge until we can figure out a more reasonable way
7541 ;; of handling these non-offsettable values.
7542 (define_insn "*movdf_hardfloat32"
7543 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
7544 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
7545 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
7546 && (gpc_reg_operand (operands[0], DFmode)
7547 || gpc_reg_operand (operands[1], DFmode))"
7550 switch (which_alternative)
7555 /* We normally copy the low-numbered register first. However, if
7556 the first register operand 0 is the same as the second register
7557 of operand 1, we must copy in the opposite order. */
7558 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7559 return \"mr %L0,%L1\;mr %0,%1\";
7561 return \"mr %0,%1\;mr %L0,%L1\";
7563 if (GET_CODE (operands[1]) == MEM
7564 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[1], 0),
7565 reload_completed || reload_in_progress)
7566 || rs6000_legitimate_small_data_p (DFmode, XEXP (operands[1], 0))
7567 || GET_CODE (XEXP (operands[1], 0)) == REG
7568 || GET_CODE (XEXP (operands[1], 0)) == LO_SUM
7569 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
7570 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))
7572 /* If the low-address word is used in the address, we must load
7573 it last. Otherwise, load it first. Note that we cannot have
7574 auto-increment in that case since the address register is
7575 known to be dead. */
7576 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7578 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7580 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7586 addreg = find_addr_reg (XEXP (operands[1], 0));
7587 if (refers_to_regno_p (REGNO (operands[0]),
7588 REGNO (operands[0]) + 1,
7591 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7592 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
7593 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7594 return \"{lx|lwzx} %0,%1\";
7598 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
7599 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7600 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
7601 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7606 if (GET_CODE (operands[0]) == MEM
7607 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[0], 0),
7608 reload_completed || reload_in_progress)
7609 || rs6000_legitimate_small_data_p (DFmode, XEXP (operands[0], 0))
7610 || GET_CODE (XEXP (operands[0], 0)) == REG
7611 || GET_CODE (XEXP (operands[0], 0)) == LO_SUM
7612 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
7613 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))
7614 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7619 addreg = find_addr_reg (XEXP (operands[0], 0));
7620 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
7621 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7622 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
7623 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7627 return \"fmr %0,%1\";
7629 return \"lfd%U1%X1 %0,%1\";
7631 return \"stfd%U0%X0 %1,%0\";
7638 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
7639 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
7641 (define_insn "*movdf_softfloat32"
7642 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
7643 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
7644 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
7645 && (gpc_reg_operand (operands[0], DFmode)
7646 || gpc_reg_operand (operands[1], DFmode))"
7649 switch (which_alternative)
7654 /* We normally copy the low-numbered register first. However, if
7655 the first register operand 0 is the same as the second register of
7656 operand 1, we must copy in the opposite order. */
7657 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7658 return \"mr %L0,%L1\;mr %0,%1\";
7660 return \"mr %0,%1\;mr %L0,%L1\";
7662 /* If the low-address word is used in the address, we must load
7663 it last. Otherwise, load it first. Note that we cannot have
7664 auto-increment in that case since the address register is
7665 known to be dead. */
7666 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7668 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7670 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7672 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7679 [(set_attr "type" "two,load,store,*,*,*")
7680 (set_attr "length" "8,8,8,8,12,16")])
7682 ; ld/std require word-aligned displacements -> 'Y' constraint.
7683 ; List Y->r and r->Y before r->r for reload.
7684 (define_insn "*movdf_hardfloat64"
7685 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
7686 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
7687 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
7688 && (gpc_reg_operand (operands[0], DFmode)
7689 || gpc_reg_operand (operands[1], DFmode))"
7703 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
7704 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
7706 (define_insn "*movdf_softfloat64"
7707 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
7708 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
7709 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
7710 && (gpc_reg_operand (operands[0], DFmode)
7711 || gpc_reg_operand (operands[1], DFmode))"
7722 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
7723 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
7725 (define_expand "movtf"
7726 [(set (match_operand:TF 0 "general_operand" "")
7727 (match_operand:TF 1 "any_operand" ""))]
7728 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7729 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7730 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
7732 ; It's important to list the o->f and f->o moves before f->f because
7733 ; otherwise reload, given m->f, will try to pick f->f and reload it,
7734 ; which doesn't make progress. Likewise r->Y must be before r->r.
7735 (define_insn_and_split "*movtf_internal"
7736 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
7737 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
7738 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7739 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
7740 && (gpc_reg_operand (operands[0], TFmode)
7741 || gpc_reg_operand (operands[1], TFmode))"
7743 "&& reload_completed"
7745 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
7746 [(set_attr "length" "8,8,8,20,20,16")])
7748 (define_expand "extenddftf2"
7749 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
7750 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
7751 (use (match_dup 2))])]
7752 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7753 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7755 operands[2] = CONST0_RTX (DFmode);
7758 (define_insn_and_split "*extenddftf2_internal"
7759 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
7760 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
7761 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
7762 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7763 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7765 "&& reload_completed"
7768 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
7769 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
7770 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
7772 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
7777 (define_expand "extendsftf2"
7778 [(set (match_operand:TF 0 "nonimmediate_operand" "")
7779 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
7780 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7781 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7783 rtx tmp = gen_reg_rtx (DFmode);
7784 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
7785 emit_insn (gen_extenddftf2 (operands[0], tmp));
7789 (define_expand "trunctfdf2"
7790 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7791 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
7792 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7793 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7796 (define_insn_and_split "trunctfdf2_internal1"
7797 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
7798 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
7799 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
7800 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7804 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
7807 emit_note (NOTE_INSN_DELETED);
7810 [(set_attr "type" "fp")])
7812 (define_insn "trunctfdf2_internal2"
7813 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
7814 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
7815 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
7816 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7818 [(set_attr "type" "fp")])
7820 (define_insn_and_split "trunctfsf2"
7821 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7822 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
7823 (clobber (match_scratch:DF 2 "=f"))]
7824 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7825 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7827 "&& reload_completed"
7829 (float_truncate:DF (match_dup 1)))
7831 (float_truncate:SF (match_dup 2)))]
7834 (define_expand "floatsitf2"
7835 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
7836 (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))]
7837 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7838 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7840 rtx tmp = gen_reg_rtx (DFmode);
7841 expand_float (tmp, operands[1], false);
7842 emit_insn (gen_extenddftf2 (operands[0], tmp));
7846 ; fadd, but rounding towards zero.
7847 ; This is probably not the optimal code sequence.
7848 (define_insn "fix_trunc_helper"
7849 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
7850 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
7851 UNSPEC_FIX_TRUNC_TF))
7852 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
7853 "TARGET_HARD_FLOAT && TARGET_FPRS"
7854 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
7855 [(set_attr "type" "fp")
7856 (set_attr "length" "20")])
7858 (define_expand "fix_trunctfsi2"
7859 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
7860 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
7861 (clobber (match_dup 2))
7862 (clobber (match_dup 3))
7863 (clobber (match_dup 4))
7864 (clobber (match_dup 5))])]
7865 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7866 && (TARGET_POWER2 || TARGET_POWERPC)
7867 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7869 operands[2] = gen_reg_rtx (DFmode);
7870 operands[3] = gen_reg_rtx (DFmode);
7871 operands[4] = gen_reg_rtx (DImode);
7872 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
7875 (define_insn_and_split "*fix_trunctfsi2_internal"
7876 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7877 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
7878 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
7879 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
7880 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
7881 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
7882 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7883 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7885 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[5]))"
7889 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
7891 gcc_assert (MEM_P (operands[5]));
7892 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
7894 emit_insn (gen_fctiwz (operands[4], operands[2]));
7895 emit_move_insn (operands[5], operands[4]);
7896 emit_move_insn (operands[0], lowword);
7900 (define_insn "negtf2"
7901 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
7902 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
7903 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7904 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7907 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7908 return \"fneg %L0,%L1\;fneg %0,%1\";
7910 return \"fneg %0,%1\;fneg %L0,%L1\";
7912 [(set_attr "type" "fp")
7913 (set_attr "length" "8")])
7915 (define_expand "abstf2"
7916 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
7917 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
7918 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7919 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7922 rtx label = gen_label_rtx ();
7923 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
7928 (define_expand "abstf2_internal"
7929 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
7930 (match_operand:TF 1 "gpc_reg_operand" "f"))
7931 (set (match_dup 3) (match_dup 5))
7932 (set (match_dup 5) (abs:DF (match_dup 5)))
7933 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
7934 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
7935 (label_ref (match_operand 2 "" ""))
7937 (set (match_dup 6) (neg:DF (match_dup 6)))]
7938 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7939 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7942 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
7943 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
7944 operands[3] = gen_reg_rtx (DFmode);
7945 operands[4] = gen_reg_rtx (CCFPmode);
7946 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
7947 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
7950 ;; Next come the multi-word integer load and store and the load and store
7953 ; List r->r after r->"o<>", otherwise reload will try to reload a
7954 ; non-offsettable address by using r->r which won't make progress.
7955 (define_insn "*movdi_internal32"
7956 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
7957 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
7959 && (gpc_reg_operand (operands[0], DImode)
7960 || gpc_reg_operand (operands[1], DImode))"
7969 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
7972 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7973 (match_operand:DI 1 "const_int_operand" ""))]
7974 "! TARGET_POWERPC64 && reload_completed"
7975 [(set (match_dup 2) (match_dup 4))
7976 (set (match_dup 3) (match_dup 1))]
7979 HOST_WIDE_INT value = INTVAL (operands[1]);
7980 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
7982 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
7984 #if HOST_BITS_PER_WIDE_INT == 32
7985 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7987 operands[4] = GEN_INT (value >> 32);
7988 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7993 [(set (match_operand:DI 0 "nonimmediate_operand" "")
7994 (match_operand:DI 1 "input_operand" ""))]
7995 "reload_completed && !TARGET_POWERPC64
7996 && gpr_or_gpr_p (operands[0], operands[1])"
7998 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8000 (define_insn "*movdi_internal64"
8001 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
8002 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8004 && (gpc_reg_operand (operands[0], DImode)
8005 || gpc_reg_operand (operands[1], DImode))"
8020 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
8021 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8023 ;; immediate value valid for a single instruction hiding in a const_double
8025 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8026 (match_operand:DI 1 "const_double_operand" "F"))]
8027 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8028 && GET_CODE (operands[1]) == CONST_DOUBLE
8029 && num_insns_constant (operands[1], DImode) == 1"
8032 return ((unsigned HOST_WIDE_INT)
8033 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8034 ? \"li %0,%1\" : \"lis %0,%v1\";
8037 ;; Generate all one-bits and clear left or right.
8038 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8040 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8041 (match_operand:DI 1 "mask64_operand" ""))]
8042 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8043 [(set (match_dup 0) (const_int -1))
8045 (and:DI (rotate:DI (match_dup 0)
8050 ;; Split a load of a large constant into the appropriate five-instruction
8051 ;; sequence. Handle anything in a constant number of insns.
8052 ;; When non-easy constants can go in the TOC, this should use
8053 ;; easy_fp_constant predicate.
8055 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8056 (match_operand:DI 1 "const_int_operand" ""))]
8057 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8058 [(set (match_dup 0) (match_dup 2))
8059 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8061 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8063 if (tem == operands[0])
8070 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8071 (match_operand:DI 1 "const_double_operand" ""))]
8072 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8073 [(set (match_dup 0) (match_dup 2))
8074 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8076 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8078 if (tem == operands[0])
8084 ;; TImode is similar, except that we usually want to compute the address into
8085 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8086 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8088 ;; We say that MQ is clobbered in the last alternative because the first
8089 ;; alternative would never get used otherwise since it would need a reload
8090 ;; while the 2nd alternative would not. We put memory cases first so they
8091 ;; are preferred. Otherwise, we'd try to reload the output instead of
8092 ;; giving the SCRATCH mq.
8094 (define_insn "*movti_power"
8095 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
8096 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
8097 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
8098 "TARGET_POWER && ! TARGET_POWERPC64
8099 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8102 switch (which_alternative)
8109 return \"{stsi|stswi} %1,%P0,16\";
8114 /* If the address is not used in the output, we can use lsi. Otherwise,
8115 fall through to generating four loads. */
8117 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8118 return \"{lsi|lswi} %0,%P1,16\";
8119 /* ... fall through ... */
8125 [(set_attr "type" "store,store,*,load,load,*")])
8127 (define_insn "*movti_string"
8128 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
8129 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
8130 "! TARGET_POWER && ! TARGET_POWERPC64
8131 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8134 switch (which_alternative)
8140 return \"{stsi|stswi} %1,%P0,16\";
8145 /* If the address is not used in the output, we can use lsi. Otherwise,
8146 fall through to generating four loads. */
8148 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8149 return \"{lsi|lswi} %0,%P1,16\";
8150 /* ... fall through ... */
8156 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")])
8158 (define_insn "*movti_ppc64"
8159 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
8160 (match_operand:TI 1 "input_operand" "r,r,m"))]
8161 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8162 || gpc_reg_operand (operands[1], TImode))"
8164 [(set_attr "type" "*,load,store")])
8167 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8168 (match_operand:TI 1 "const_double_operand" ""))]
8170 [(set (match_dup 2) (match_dup 4))
8171 (set (match_dup 3) (match_dup 5))]
8174 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8176 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8178 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8180 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8181 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8183 else if (GET_CODE (operands[1]) == CONST_INT)
8185 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8186 operands[5] = operands[1];
8193 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8194 (match_operand:TI 1 "input_operand" ""))]
8196 && gpr_or_gpr_p (operands[0], operands[1])"
8198 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8200 (define_expand "load_multiple"
8201 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8202 (match_operand:SI 1 "" ""))
8203 (use (match_operand:SI 2 "" ""))])]
8204 "TARGET_STRING && !TARGET_POWERPC64"
8212 /* Support only loading a constant number of fixed-point registers from
8213 memory and only bother with this if more than two; the machine
8214 doesn't support more than eight. */
8215 if (GET_CODE (operands[2]) != CONST_INT
8216 || INTVAL (operands[2]) <= 2
8217 || INTVAL (operands[2]) > 8
8218 || GET_CODE (operands[1]) != MEM
8219 || GET_CODE (operands[0]) != REG
8220 || REGNO (operands[0]) >= 32)
8223 count = INTVAL (operands[2]);
8224 regno = REGNO (operands[0]);
8226 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8227 op1 = replace_equiv_address (operands[1],
8228 force_reg (SImode, XEXP (operands[1], 0)));
8230 for (i = 0; i < count; i++)
8231 XVECEXP (operands[3], 0, i)
8232 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8233 adjust_address_nv (op1, SImode, i * 4));
8236 (define_insn "*ldmsi8"
8237 [(match_parallel 0 "load_multiple_operation"
8238 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8239 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8240 (set (match_operand:SI 3 "gpc_reg_operand" "")
8241 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8242 (set (match_operand:SI 4 "gpc_reg_operand" "")
8243 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8244 (set (match_operand:SI 5 "gpc_reg_operand" "")
8245 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8246 (set (match_operand:SI 6 "gpc_reg_operand" "")
8247 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8248 (set (match_operand:SI 7 "gpc_reg_operand" "")
8249 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8250 (set (match_operand:SI 8 "gpc_reg_operand" "")
8251 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8252 (set (match_operand:SI 9 "gpc_reg_operand" "")
8253 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8254 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8256 { return rs6000_output_load_multiple (operands); }"
8257 [(set_attr "type" "load_ux")
8258 (set_attr "length" "32")])
8260 (define_insn "*ldmsi7"
8261 [(match_parallel 0 "load_multiple_operation"
8262 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8263 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8264 (set (match_operand:SI 3 "gpc_reg_operand" "")
8265 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8266 (set (match_operand:SI 4 "gpc_reg_operand" "")
8267 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8268 (set (match_operand:SI 5 "gpc_reg_operand" "")
8269 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8270 (set (match_operand:SI 6 "gpc_reg_operand" "")
8271 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8272 (set (match_operand:SI 7 "gpc_reg_operand" "")
8273 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8274 (set (match_operand:SI 8 "gpc_reg_operand" "")
8275 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8276 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8278 { return rs6000_output_load_multiple (operands); }"
8279 [(set_attr "type" "load_ux")
8280 (set_attr "length" "32")])
8282 (define_insn "*ldmsi6"
8283 [(match_parallel 0 "load_multiple_operation"
8284 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8285 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8286 (set (match_operand:SI 3 "gpc_reg_operand" "")
8287 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8288 (set (match_operand:SI 4 "gpc_reg_operand" "")
8289 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8290 (set (match_operand:SI 5 "gpc_reg_operand" "")
8291 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8292 (set (match_operand:SI 6 "gpc_reg_operand" "")
8293 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8294 (set (match_operand:SI 7 "gpc_reg_operand" "")
8295 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8296 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8298 { return rs6000_output_load_multiple (operands); }"
8299 [(set_attr "type" "load_ux")
8300 (set_attr "length" "32")])
8302 (define_insn "*ldmsi5"
8303 [(match_parallel 0 "load_multiple_operation"
8304 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8305 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8306 (set (match_operand:SI 3 "gpc_reg_operand" "")
8307 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8308 (set (match_operand:SI 4 "gpc_reg_operand" "")
8309 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8310 (set (match_operand:SI 5 "gpc_reg_operand" "")
8311 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8312 (set (match_operand:SI 6 "gpc_reg_operand" "")
8313 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8314 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8316 { return rs6000_output_load_multiple (operands); }"
8317 [(set_attr "type" "load_ux")
8318 (set_attr "length" "32")])
8320 (define_insn "*ldmsi4"
8321 [(match_parallel 0 "load_multiple_operation"
8322 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8323 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8324 (set (match_operand:SI 3 "gpc_reg_operand" "")
8325 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8326 (set (match_operand:SI 4 "gpc_reg_operand" "")
8327 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8328 (set (match_operand:SI 5 "gpc_reg_operand" "")
8329 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8330 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8332 { return rs6000_output_load_multiple (operands); }"
8333 [(set_attr "type" "load_ux")
8334 (set_attr "length" "32")])
8336 (define_insn "*ldmsi3"
8337 [(match_parallel 0 "load_multiple_operation"
8338 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8339 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8340 (set (match_operand:SI 3 "gpc_reg_operand" "")
8341 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8342 (set (match_operand:SI 4 "gpc_reg_operand" "")
8343 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8344 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8346 { return rs6000_output_load_multiple (operands); }"
8347 [(set_attr "type" "load_ux")
8348 (set_attr "length" "32")])
8350 (define_expand "store_multiple"
8351 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8352 (match_operand:SI 1 "" ""))
8353 (clobber (scratch:SI))
8354 (use (match_operand:SI 2 "" ""))])]
8355 "TARGET_STRING && !TARGET_POWERPC64"
8364 /* Support only storing a constant number of fixed-point registers to
8365 memory and only bother with this if more than two; the machine
8366 doesn't support more than eight. */
8367 if (GET_CODE (operands[2]) != CONST_INT
8368 || INTVAL (operands[2]) <= 2
8369 || INTVAL (operands[2]) > 8
8370 || GET_CODE (operands[0]) != MEM
8371 || GET_CODE (operands[1]) != REG
8372 || REGNO (operands[1]) >= 32)
8375 count = INTVAL (operands[2]);
8376 regno = REGNO (operands[1]);
8378 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8379 to = force_reg (SImode, XEXP (operands[0], 0));
8380 op0 = replace_equiv_address (operands[0], to);
8382 XVECEXP (operands[3], 0, 0)
8383 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
8384 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8385 gen_rtx_SCRATCH (SImode));
8387 for (i = 1; i < count; i++)
8388 XVECEXP (operands[3], 0, i + 1)
8389 = gen_rtx_SET (VOIDmode,
8390 adjust_address_nv (op0, SImode, i * 4),
8391 gen_rtx_REG (SImode, regno + i));
8394 (define_insn "*store_multiple_power"
8395 [(match_parallel 0 "store_multiple_operation"
8396 [(set (match_operand:SI 1 "indirect_operand" "=Q")
8397 (match_operand:SI 2 "gpc_reg_operand" "r"))
8398 (clobber (match_scratch:SI 3 "=q"))])]
8399 "TARGET_STRING && TARGET_POWER"
8400 "{stsi|stswi} %2,%P1,%O0"
8401 [(set_attr "type" "store")])
8403 (define_insn "*stmsi8"
8404 [(match_parallel 0 "store_multiple_operation"
8405 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8406 (match_operand:SI 2 "gpc_reg_operand" "r"))
8407 (clobber (match_scratch:SI 3 "X"))
8408 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8409 (match_operand:SI 4 "gpc_reg_operand" "r"))
8410 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8411 (match_operand:SI 5 "gpc_reg_operand" "r"))
8412 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8413 (match_operand:SI 6 "gpc_reg_operand" "r"))
8414 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8415 (match_operand:SI 7 "gpc_reg_operand" "r"))
8416 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8417 (match_operand:SI 8 "gpc_reg_operand" "r"))
8418 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8419 (match_operand:SI 9 "gpc_reg_operand" "r"))
8420 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
8421 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
8422 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
8423 "{stsi|stswi} %2,%1,%O0"
8424 [(set_attr "type" "store_ux")])
8426 (define_insn "*stmsi7"
8427 [(match_parallel 0 "store_multiple_operation"
8428 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8429 (match_operand:SI 2 "gpc_reg_operand" "r"))
8430 (clobber (match_scratch:SI 3 "X"))
8431 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8432 (match_operand:SI 4 "gpc_reg_operand" "r"))
8433 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8434 (match_operand:SI 5 "gpc_reg_operand" "r"))
8435 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8436 (match_operand:SI 6 "gpc_reg_operand" "r"))
8437 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8438 (match_operand:SI 7 "gpc_reg_operand" "r"))
8439 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8440 (match_operand:SI 8 "gpc_reg_operand" "r"))
8441 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8442 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
8443 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
8444 "{stsi|stswi} %2,%1,%O0"
8445 [(set_attr "type" "store_ux")])
8447 (define_insn "*stmsi6"
8448 [(match_parallel 0 "store_multiple_operation"
8449 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8450 (match_operand:SI 2 "gpc_reg_operand" "r"))
8451 (clobber (match_scratch:SI 3 "X"))
8452 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8453 (match_operand:SI 4 "gpc_reg_operand" "r"))
8454 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8455 (match_operand:SI 5 "gpc_reg_operand" "r"))
8456 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8457 (match_operand:SI 6 "gpc_reg_operand" "r"))
8458 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8459 (match_operand:SI 7 "gpc_reg_operand" "r"))
8460 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8461 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
8462 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
8463 "{stsi|stswi} %2,%1,%O0"
8464 [(set_attr "type" "store_ux")])
8466 (define_insn "*stmsi5"
8467 [(match_parallel 0 "store_multiple_operation"
8468 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8469 (match_operand:SI 2 "gpc_reg_operand" "r"))
8470 (clobber (match_scratch:SI 3 "X"))
8471 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8472 (match_operand:SI 4 "gpc_reg_operand" "r"))
8473 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8474 (match_operand:SI 5 "gpc_reg_operand" "r"))
8475 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8476 (match_operand:SI 6 "gpc_reg_operand" "r"))
8477 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8478 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
8479 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
8480 "{stsi|stswi} %2,%1,%O0"
8481 [(set_attr "type" "store_ux")])
8483 (define_insn "*stmsi4"
8484 [(match_parallel 0 "store_multiple_operation"
8485 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8486 (match_operand:SI 2 "gpc_reg_operand" "r"))
8487 (clobber (match_scratch:SI 3 "X"))
8488 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8489 (match_operand:SI 4 "gpc_reg_operand" "r"))
8490 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8491 (match_operand:SI 5 "gpc_reg_operand" "r"))
8492 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8493 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
8494 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
8495 "{stsi|stswi} %2,%1,%O0"
8496 [(set_attr "type" "store_ux")])
8498 (define_insn "*stmsi3"
8499 [(match_parallel 0 "store_multiple_operation"
8500 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8501 (match_operand:SI 2 "gpc_reg_operand" "r"))
8502 (clobber (match_scratch:SI 3 "X"))
8503 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8504 (match_operand:SI 4 "gpc_reg_operand" "r"))
8505 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8506 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
8507 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
8508 "{stsi|stswi} %2,%1,%O0"
8509 [(set_attr "type" "store_ux")])
8511 (define_expand "setmemsi"
8512 [(parallel [(set (match_operand:BLK 0 "" "")
8513 (match_operand 2 "const_int_operand" ""))
8514 (use (match_operand:SI 1 "" ""))
8515 (use (match_operand:SI 3 "" ""))])]
8519 /* If value to set is not zero, use the library routine. */
8520 if (operands[2] != const0_rtx)
8523 if (expand_block_clear (operands))
8529 ;; String/block move insn.
8530 ;; Argument 0 is the destination
8531 ;; Argument 1 is the source
8532 ;; Argument 2 is the length
8533 ;; Argument 3 is the alignment
8535 (define_expand "movmemsi"
8536 [(parallel [(set (match_operand:BLK 0 "" "")
8537 (match_operand:BLK 1 "" ""))
8538 (use (match_operand:SI 2 "" ""))
8539 (use (match_operand:SI 3 "" ""))])]
8543 if (expand_block_move (operands))
8549 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
8550 ;; register allocator doesn't have a clue about allocating 8 word registers.
8551 ;; rD/rS = r5 is preferred, efficient form.
8552 (define_expand "movmemsi_8reg"
8553 [(parallel [(set (match_operand 0 "" "")
8554 (match_operand 1 "" ""))
8555 (use (match_operand 2 "" ""))
8556 (use (match_operand 3 "" ""))
8557 (clobber (reg:SI 5))
8558 (clobber (reg:SI 6))
8559 (clobber (reg:SI 7))
8560 (clobber (reg:SI 8))
8561 (clobber (reg:SI 9))
8562 (clobber (reg:SI 10))
8563 (clobber (reg:SI 11))
8564 (clobber (reg:SI 12))
8565 (clobber (match_scratch:SI 4 ""))])]
8570 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8571 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8572 (use (match_operand:SI 2 "immediate_operand" "i"))
8573 (use (match_operand:SI 3 "immediate_operand" "i"))
8574 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8575 (clobber (reg:SI 6))
8576 (clobber (reg:SI 7))
8577 (clobber (reg:SI 8))
8578 (clobber (reg:SI 9))
8579 (clobber (reg:SI 10))
8580 (clobber (reg:SI 11))
8581 (clobber (reg:SI 12))
8582 (clobber (match_scratch:SI 5 "=q"))]
8583 "TARGET_STRING && TARGET_POWER
8584 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8585 || INTVAL (operands[2]) == 0)
8586 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8587 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8588 && REGNO (operands[4]) == 5"
8589 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8590 [(set_attr "type" "store_ux")
8591 (set_attr "length" "8")])
8594 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8595 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
8596 (use (match_operand:SI 2 "immediate_operand" "i"))
8597 (use (match_operand:SI 3 "immediate_operand" "i"))
8598 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8599 (clobber (reg:SI 6))
8600 (clobber (reg:SI 7))
8601 (clobber (reg:SI 8))
8602 (clobber (reg:SI 9))
8603 (clobber (reg:SI 10))
8604 (clobber (reg:SI 11))
8605 (clobber (reg:SI 12))
8606 (clobber (match_scratch:SI 5 "X"))]
8607 "TARGET_STRING && ! TARGET_POWER
8608 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8609 || INTVAL (operands[2]) == 0)
8610 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8611 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8612 && REGNO (operands[4]) == 5"
8613 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8614 [(set_attr "type" "store_ux")
8615 (set_attr "length" "8")])
8617 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
8618 ;; register allocator doesn't have a clue about allocating 6 word registers.
8619 ;; rD/rS = r5 is preferred, efficient form.
8620 (define_expand "movmemsi_6reg"
8621 [(parallel [(set (match_operand 0 "" "")
8622 (match_operand 1 "" ""))
8623 (use (match_operand 2 "" ""))
8624 (use (match_operand 3 "" ""))
8625 (clobber (reg:SI 5))
8626 (clobber (reg:SI 6))
8627 (clobber (reg:SI 7))
8628 (clobber (reg:SI 8))
8629 (clobber (reg:SI 9))
8630 (clobber (reg:SI 10))
8631 (clobber (match_scratch:SI 4 ""))])]
8636 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8637 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8638 (use (match_operand:SI 2 "immediate_operand" "i"))
8639 (use (match_operand:SI 3 "immediate_operand" "i"))
8640 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8641 (clobber (reg:SI 6))
8642 (clobber (reg:SI 7))
8643 (clobber (reg:SI 8))
8644 (clobber (reg:SI 9))
8645 (clobber (reg:SI 10))
8646 (clobber (match_scratch:SI 5 "=q"))]
8647 "TARGET_STRING && TARGET_POWER
8648 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
8649 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8650 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8651 && REGNO (operands[4]) == 5"
8652 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8653 [(set_attr "type" "store_ux")
8654 (set_attr "length" "8")])
8657 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8658 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
8659 (use (match_operand:SI 2 "immediate_operand" "i"))
8660 (use (match_operand:SI 3 "immediate_operand" "i"))
8661 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8662 (clobber (reg:SI 6))
8663 (clobber (reg:SI 7))
8664 (clobber (reg:SI 8))
8665 (clobber (reg:SI 9))
8666 (clobber (reg:SI 10))
8667 (clobber (match_scratch:SI 5 "X"))]
8668 "TARGET_STRING && ! TARGET_POWER
8669 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
8670 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8671 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8672 && REGNO (operands[4]) == 5"
8673 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8674 [(set_attr "type" "store_ux")
8675 (set_attr "length" "8")])
8677 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
8678 ;; problems with TImode.
8679 ;; rD/rS = r5 is preferred, efficient form.
8680 (define_expand "movmemsi_4reg"
8681 [(parallel [(set (match_operand 0 "" "")
8682 (match_operand 1 "" ""))
8683 (use (match_operand 2 "" ""))
8684 (use (match_operand 3 "" ""))
8685 (clobber (reg:SI 5))
8686 (clobber (reg:SI 6))
8687 (clobber (reg:SI 7))
8688 (clobber (reg:SI 8))
8689 (clobber (match_scratch:SI 4 ""))])]
8694 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8695 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8696 (use (match_operand:SI 2 "immediate_operand" "i"))
8697 (use (match_operand:SI 3 "immediate_operand" "i"))
8698 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8699 (clobber (reg:SI 6))
8700 (clobber (reg:SI 7))
8701 (clobber (reg:SI 8))
8702 (clobber (match_scratch:SI 5 "=q"))]
8703 "TARGET_STRING && TARGET_POWER
8704 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
8705 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
8706 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
8707 && REGNO (operands[4]) == 5"
8708 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8709 [(set_attr "type" "store_ux")
8710 (set_attr "length" "8")])
8713 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8714 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
8715 (use (match_operand:SI 2 "immediate_operand" "i"))
8716 (use (match_operand:SI 3 "immediate_operand" "i"))
8717 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8718 (clobber (reg:SI 6))
8719 (clobber (reg:SI 7))
8720 (clobber (reg:SI 8))
8721 (clobber (match_scratch:SI 5 "X"))]
8722 "TARGET_STRING && ! TARGET_POWER
8723 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
8724 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
8725 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
8726 && REGNO (operands[4]) == 5"
8727 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8728 [(set_attr "type" "store_ux")
8729 (set_attr "length" "8")])
8731 ;; Move up to 8 bytes at a time.
8732 (define_expand "movmemsi_2reg"
8733 [(parallel [(set (match_operand 0 "" "")
8734 (match_operand 1 "" ""))
8735 (use (match_operand 2 "" ""))
8736 (use (match_operand 3 "" ""))
8737 (clobber (match_scratch:DI 4 ""))
8738 (clobber (match_scratch:SI 5 ""))])]
8739 "TARGET_STRING && ! TARGET_POWERPC64"
8743 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8744 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8745 (use (match_operand:SI 2 "immediate_operand" "i"))
8746 (use (match_operand:SI 3 "immediate_operand" "i"))
8747 (clobber (match_scratch:DI 4 "=&r"))
8748 (clobber (match_scratch:SI 5 "=q"))]
8749 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
8750 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
8751 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8752 [(set_attr "type" "store_ux")
8753 (set_attr "length" "8")])
8756 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8757 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8758 (use (match_operand:SI 2 "immediate_operand" "i"))
8759 (use (match_operand:SI 3 "immediate_operand" "i"))
8760 (clobber (match_scratch:DI 4 "=&r"))
8761 (clobber (match_scratch:SI 5 "X"))]
8762 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
8763 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
8764 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8765 [(set_attr "type" "store_ux")
8766 (set_attr "length" "8")])
8768 ;; Move up to 4 bytes at a time.
8769 (define_expand "movmemsi_1reg"
8770 [(parallel [(set (match_operand 0 "" "")
8771 (match_operand 1 "" ""))
8772 (use (match_operand 2 "" ""))
8773 (use (match_operand 3 "" ""))
8774 (clobber (match_scratch:SI 4 ""))
8775 (clobber (match_scratch:SI 5 ""))])]
8780 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8781 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8782 (use (match_operand:SI 2 "immediate_operand" "i"))
8783 (use (match_operand:SI 3 "immediate_operand" "i"))
8784 (clobber (match_scratch:SI 4 "=&r"))
8785 (clobber (match_scratch:SI 5 "=q"))]
8786 "TARGET_STRING && TARGET_POWER
8787 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
8788 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8789 [(set_attr "type" "store_ux")
8790 (set_attr "length" "8")])
8793 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8794 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
8795 (use (match_operand:SI 2 "immediate_operand" "i"))
8796 (use (match_operand:SI 3 "immediate_operand" "i"))
8797 (clobber (match_scratch:SI 4 "=&r"))
8798 (clobber (match_scratch:SI 5 "X"))]
8799 "TARGET_STRING && ! TARGET_POWER
8800 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
8801 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8802 [(set_attr "type" "store_ux")
8803 (set_attr "length" "8")])
8805 ;; Define insns that do load or store with update. Some of these we can
8806 ;; get by using pre-decrement or pre-increment, but the hardware can also
8807 ;; do cases where the increment is not the size of the object.
8809 ;; In all these cases, we use operands 0 and 1 for the register being
8810 ;; incremented because those are the operands that local-alloc will
8811 ;; tie and these are the pair most likely to be tieable (and the ones
8812 ;; that will benefit the most).
8814 (define_insn "*movdi_update1"
8815 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
8816 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
8817 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
8818 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
8819 (plus:DI (match_dup 1) (match_dup 2)))]
8820 "TARGET_POWERPC64 && TARGET_UPDATE"
8824 [(set_attr "type" "load_ux,load_u")])
8826 (define_insn "movdi_<mode>_update"
8827 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
8828 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
8829 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
8830 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
8831 (plus:P (match_dup 1) (match_dup 2)))]
8832 "TARGET_POWERPC64 && TARGET_UPDATE"
8836 [(set_attr "type" "store_ux,store_u")])
8838 (define_insn "*movsi_update1"
8839 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8840 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8841 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8842 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8843 (plus:SI (match_dup 1) (match_dup 2)))]
8846 {lux|lwzux} %3,%0,%2
8847 {lu|lwzu} %3,%2(%0)"
8848 [(set_attr "type" "load_ux,load_u")])
8850 (define_insn "*movsi_update2"
8851 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
8853 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
8854 (match_operand:DI 2 "gpc_reg_operand" "r")))))
8855 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
8856 (plus:DI (match_dup 1) (match_dup 2)))]
8859 [(set_attr "type" "load_ext_ux")])
8861 (define_insn "movsi_update"
8862 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8863 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8864 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8865 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8866 (plus:SI (match_dup 1) (match_dup 2)))]
8869 {stux|stwux} %3,%0,%2
8870 {stu|stwu} %3,%2(%0)"
8871 [(set_attr "type" "store_ux,store_u")])
8873 (define_insn "*movhi_update1"
8874 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
8875 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8876 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8877 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8878 (plus:SI (match_dup 1) (match_dup 2)))]
8883 [(set_attr "type" "load_ux,load_u")])
8885 (define_insn "*movhi_update2"
8886 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8888 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8889 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
8890 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8891 (plus:SI (match_dup 1) (match_dup 2)))]
8896 [(set_attr "type" "load_ux,load_u")])
8898 (define_insn "*movhi_update3"
8899 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8901 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8902 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
8903 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8904 (plus:SI (match_dup 1) (match_dup 2)))]
8909 [(set_attr "type" "load_ext_ux,load_ext_u")])
8911 (define_insn "*movhi_update4"
8912 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8913 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8914 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
8915 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8916 (plus:SI (match_dup 1) (match_dup 2)))]
8921 [(set_attr "type" "store_ux,store_u")])
8923 (define_insn "*movqi_update1"
8924 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
8925 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8926 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8927 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8928 (plus:SI (match_dup 1) (match_dup 2)))]
8933 [(set_attr "type" "load_ux,load_u")])
8935 (define_insn "*movqi_update2"
8936 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8938 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8939 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
8940 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8941 (plus:SI (match_dup 1) (match_dup 2)))]
8946 [(set_attr "type" "load_ux,load_u")])
8948 (define_insn "*movqi_update3"
8949 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8950 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8951 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
8952 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8953 (plus:SI (match_dup 1) (match_dup 2)))]
8958 [(set_attr "type" "store_ux,store_u")])
8960 (define_insn "*movsf_update1"
8961 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
8962 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8963 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8964 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8965 (plus:SI (match_dup 1) (match_dup 2)))]
8966 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
8970 [(set_attr "type" "fpload_ux,fpload_u")])
8972 (define_insn "*movsf_update2"
8973 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8974 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8975 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
8976 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8977 (plus:SI (match_dup 1) (match_dup 2)))]
8978 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
8982 [(set_attr "type" "fpstore_ux,fpstore_u")])
8984 (define_insn "*movsf_update3"
8985 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
8986 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8987 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8988 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8989 (plus:SI (match_dup 1) (match_dup 2)))]
8990 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
8992 {lux|lwzux} %3,%0,%2
8993 {lu|lwzu} %3,%2(%0)"
8994 [(set_attr "type" "load_ux,load_u")])
8996 (define_insn "*movsf_update4"
8997 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8998 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8999 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9000 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9001 (plus:SI (match_dup 1) (match_dup 2)))]
9002 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9004 {stux|stwux} %3,%0,%2
9005 {stu|stwu} %3,%2(%0)"
9006 [(set_attr "type" "store_ux,store_u")])
9008 (define_insn "*movdf_update1"
9009 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9010 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9011 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9012 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9013 (plus:SI (match_dup 1) (match_dup 2)))]
9014 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9018 [(set_attr "type" "fpload_ux,fpload_u")])
9020 (define_insn "*movdf_update2"
9021 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9022 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9023 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9024 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9025 (plus:SI (match_dup 1) (match_dup 2)))]
9026 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9030 [(set_attr "type" "fpstore_ux,fpstore_u")])
9032 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9034 (define_insn "*lfq_power2"
9035 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
9036 (match_operand:V2DF 1 "memory_operand" ""))]
9038 && TARGET_HARD_FLOAT && TARGET_FPRS"
9042 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9043 (match_operand:DF 1 "memory_operand" ""))
9044 (set (match_operand:DF 2 "gpc_reg_operand" "")
9045 (match_operand:DF 3 "memory_operand" ""))]
9047 && TARGET_HARD_FLOAT && TARGET_FPRS
9048 && registers_ok_for_quad_peep (operands[0], operands[2])
9049 && mems_ok_for_quad_peep (operands[1], operands[3])"
9052 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
9053 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
9055 (define_insn "*stfq_power2"
9056 [(set (match_operand:V2DF 0 "memory_operand" "")
9057 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
9059 && TARGET_HARD_FLOAT && TARGET_FPRS"
9064 [(set (match_operand:DF 0 "memory_operand" "")
9065 (match_operand:DF 1 "gpc_reg_operand" ""))
9066 (set (match_operand:DF 2 "memory_operand" "")
9067 (match_operand:DF 3 "gpc_reg_operand" ""))]
9069 && TARGET_HARD_FLOAT && TARGET_FPRS
9070 && registers_ok_for_quad_peep (operands[1], operands[3])
9071 && mems_ok_for_quad_peep (operands[0], operands[2])"
9074 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
9075 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
9077 ;; after inserting conditional returns we can sometimes have
9078 ;; unnecessary register moves. Unfortunately we cannot have a
9079 ;; modeless peephole here, because some single SImode sets have early
9080 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9081 ;; sequences, using get_attr_length here will smash the operands
9082 ;; array. Neither is there an early_cobbler_p predicate.
9084 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9085 (match_operand:DF 1 "any_operand" ""))
9086 (set (match_operand:DF 2 "gpc_reg_operand" "")
9088 "peep2_reg_dead_p (2, operands[0])"
9089 [(set (match_dup 2) (match_dup 1))])
9092 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9093 (match_operand:SF 1 "any_operand" ""))
9094 (set (match_operand:SF 2 "gpc_reg_operand" "")
9096 "peep2_reg_dead_p (2, operands[0])"
9097 [(set (match_dup 2) (match_dup 1))])
9102 ;; "b" output constraint here and on tls_ld to support tls linker optimization.
9103 (define_insn "tls_gd_32"
9104 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9105 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9106 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9108 "HAVE_AS_TLS && !TARGET_64BIT"
9109 "addi %0,%1,%2@got@tlsgd")
9111 (define_insn "tls_gd_64"
9112 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9113 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9114 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9116 "HAVE_AS_TLS && TARGET_64BIT"
9117 "addi %0,%1,%2@got@tlsgd")
9119 (define_insn "tls_ld_32"
9120 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9121 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
9123 "HAVE_AS_TLS && !TARGET_64BIT"
9124 "addi %0,%1,%&@got@tlsld")
9126 (define_insn "tls_ld_64"
9127 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9128 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
9130 "HAVE_AS_TLS && TARGET_64BIT"
9131 "addi %0,%1,%&@got@tlsld")
9133 (define_insn "tls_dtprel_32"
9134 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9135 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9136 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9138 "HAVE_AS_TLS && !TARGET_64BIT"
9139 "addi %0,%1,%2@dtprel")
9141 (define_insn "tls_dtprel_64"
9142 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9143 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9144 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9146 "HAVE_AS_TLS && TARGET_64BIT"
9147 "addi %0,%1,%2@dtprel")
9149 (define_insn "tls_dtprel_ha_32"
9150 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9151 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9152 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9153 UNSPEC_TLSDTPRELHA))]
9154 "HAVE_AS_TLS && !TARGET_64BIT"
9155 "addis %0,%1,%2@dtprel@ha")
9157 (define_insn "tls_dtprel_ha_64"
9158 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9159 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9160 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9161 UNSPEC_TLSDTPRELHA))]
9162 "HAVE_AS_TLS && TARGET_64BIT"
9163 "addis %0,%1,%2@dtprel@ha")
9165 (define_insn "tls_dtprel_lo_32"
9166 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9167 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9168 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9169 UNSPEC_TLSDTPRELLO))]
9170 "HAVE_AS_TLS && !TARGET_64BIT"
9171 "addi %0,%1,%2@dtprel@l")
9173 (define_insn "tls_dtprel_lo_64"
9174 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9175 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9176 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9177 UNSPEC_TLSDTPRELLO))]
9178 "HAVE_AS_TLS && TARGET_64BIT"
9179 "addi %0,%1,%2@dtprel@l")
9181 (define_insn "tls_got_dtprel_32"
9182 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9183 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9184 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9185 UNSPEC_TLSGOTDTPREL))]
9186 "HAVE_AS_TLS && !TARGET_64BIT"
9187 "lwz %0,%2@got@dtprel(%1)")
9189 (define_insn "tls_got_dtprel_64"
9190 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9191 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9192 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9193 UNSPEC_TLSGOTDTPREL))]
9194 "HAVE_AS_TLS && TARGET_64BIT"
9195 "ld %0,%2@got@dtprel(%1)")
9197 (define_insn "tls_tprel_32"
9198 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9199 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9200 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9202 "HAVE_AS_TLS && !TARGET_64BIT"
9203 "addi %0,%1,%2@tprel")
9205 (define_insn "tls_tprel_64"
9206 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9207 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9208 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9210 "HAVE_AS_TLS && TARGET_64BIT"
9211 "addi %0,%1,%2@tprel")
9213 (define_insn "tls_tprel_ha_32"
9214 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9215 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9216 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9217 UNSPEC_TLSTPRELHA))]
9218 "HAVE_AS_TLS && !TARGET_64BIT"
9219 "addis %0,%1,%2@tprel@ha")
9221 (define_insn "tls_tprel_ha_64"
9222 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9223 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9224 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9225 UNSPEC_TLSTPRELHA))]
9226 "HAVE_AS_TLS && TARGET_64BIT"
9227 "addis %0,%1,%2@tprel@ha")
9229 (define_insn "tls_tprel_lo_32"
9230 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9231 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9232 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9233 UNSPEC_TLSTPRELLO))]
9234 "HAVE_AS_TLS && !TARGET_64BIT"
9235 "addi %0,%1,%2@tprel@l")
9237 (define_insn "tls_tprel_lo_64"
9238 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9239 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9240 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9241 UNSPEC_TLSTPRELLO))]
9242 "HAVE_AS_TLS && TARGET_64BIT"
9243 "addi %0,%1,%2@tprel@l")
9245 ;; "b" output constraint here and on tls_tls input to support linker tls
9246 ;; optimization. The linker may edit the instructions emitted by a
9247 ;; tls_got_tprel/tls_tls pair to addis,addi.
9248 (define_insn "tls_got_tprel_32"
9249 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9250 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9251 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9252 UNSPEC_TLSGOTTPREL))]
9253 "HAVE_AS_TLS && !TARGET_64BIT"
9254 "lwz %0,%2@got@tprel(%1)")
9256 (define_insn "tls_got_tprel_64"
9257 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9258 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9259 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9260 UNSPEC_TLSGOTTPREL))]
9261 "HAVE_AS_TLS && TARGET_64BIT"
9262 "ld %0,%2@got@tprel(%1)")
9264 (define_insn "tls_tls_32"
9265 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9266 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9267 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9269 "HAVE_AS_TLS && !TARGET_64BIT"
9272 (define_insn "tls_tls_64"
9273 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9274 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9275 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9277 "HAVE_AS_TLS && TARGET_64BIT"
9280 ;; Next come insns related to the calling sequence.
9282 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9283 ;; We move the back-chain and decrement the stack pointer.
9285 (define_expand "allocate_stack"
9286 [(set (match_operand 0 "gpc_reg_operand" "=r")
9287 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9289 (minus (reg 1) (match_dup 1)))]
9292 { rtx chain = gen_reg_rtx (Pmode);
9293 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
9296 emit_move_insn (chain, stack_bot);
9298 /* Check stack bounds if necessary. */
9299 if (current_function_limit_stack)
9302 available = expand_binop (Pmode, sub_optab,
9303 stack_pointer_rtx, stack_limit_rtx,
9304 NULL_RTX, 1, OPTAB_WIDEN);
9305 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
9308 if (GET_CODE (operands[1]) != CONST_INT
9309 || INTVAL (operands[1]) < -32767
9310 || INTVAL (operands[1]) > 32768)
9312 neg_op0 = gen_reg_rtx (Pmode);
9314 emit_insn (gen_negsi2 (neg_op0, operands[1]));
9316 emit_insn (gen_negdi2 (neg_op0, operands[1]));
9319 neg_op0 = GEN_INT (- INTVAL (operands[1]));
9322 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
9323 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
9327 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
9328 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
9329 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
9332 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9336 ;; These patterns say how to save and restore the stack pointer. We need not
9337 ;; save the stack pointer at function level since we are careful to
9338 ;; preserve the backchain. At block level, we have to restore the backchain
9339 ;; when we restore the stack pointer.
9341 ;; For nonlocal gotos, we must save both the stack pointer and its
9342 ;; backchain and restore both. Note that in the nonlocal case, the
9343 ;; save area is a memory location.
9345 (define_expand "save_stack_function"
9346 [(match_operand 0 "any_operand" "")
9347 (match_operand 1 "any_operand" "")]
9351 (define_expand "restore_stack_function"
9352 [(match_operand 0 "any_operand" "")
9353 (match_operand 1 "any_operand" "")]
9357 ;; Adjust stack pointer (op0) to a new value (op1).
9358 ;; First copy old stack backchain to new location, and ensure that the
9359 ;; scheduler won't reorder the sp assignment before the backchain write.
9360 (define_expand "restore_stack_block"
9361 [(set (match_dup 2) (match_dup 3))
9362 (set (match_dup 4) (match_dup 2))
9363 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
9364 (set (match_operand 0 "register_operand" "")
9365 (match_operand 1 "register_operand" ""))]
9369 operands[2] = gen_reg_rtx (Pmode);
9370 operands[3] = gen_frame_mem (Pmode, operands[0]);
9371 operands[4] = gen_frame_mem (Pmode, operands[1]);
9372 operands[5] = gen_frame_mem (BLKmode, operands[0]);
9375 (define_expand "save_stack_nonlocal"
9376 [(set (match_dup 3) (match_dup 4))
9377 (set (match_operand 0 "memory_operand" "") (match_dup 3))
9378 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
9382 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9384 /* Copy the backchain to the first word, sp to the second. */
9385 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
9386 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
9387 operands[3] = gen_reg_rtx (Pmode);
9388 operands[4] = gen_frame_mem (Pmode, operands[1]);
9391 (define_expand "restore_stack_nonlocal"
9392 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
9393 (set (match_dup 3) (match_dup 4))
9394 (set (match_dup 5) (match_dup 2))
9395 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
9396 (set (match_operand 0 "register_operand" "") (match_dup 3))]
9400 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9402 /* Restore the backchain from the first word, sp from the second. */
9403 operands[2] = gen_reg_rtx (Pmode);
9404 operands[3] = gen_reg_rtx (Pmode);
9405 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
9406 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
9407 operands[5] = gen_frame_mem (Pmode, operands[3]);
9408 operands[6] = gen_frame_mem (BLKmode, operands[0]);
9411 ;; TOC register handling.
9413 ;; Code to initialize the TOC register...
9415 (define_insn "load_toc_aix_si"
9416 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9417 (unspec:SI [(const_int 0)] UNSPEC_TOC))
9419 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
9423 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9424 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9425 operands[2] = gen_rtx_REG (Pmode, 2);
9426 return \"{l|lwz} %0,%1(%2)\";
9428 [(set_attr "type" "load")])
9430 (define_insn "load_toc_aix_di"
9431 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9432 (unspec:DI [(const_int 0)] UNSPEC_TOC))
9434 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
9438 #ifdef TARGET_RELOCATABLE
9439 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
9440 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
9442 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9445 strcat (buf, \"@toc\");
9446 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9447 operands[2] = gen_rtx_REG (Pmode, 2);
9448 return \"ld %0,%1(%2)\";
9450 [(set_attr "type" "load")])
9452 (define_insn "load_toc_v4_pic_si"
9453 [(set (match_operand:SI 0 "register_operand" "=l")
9454 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
9455 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
9456 "bl _GLOBAL_OFFSET_TABLE_@local-4"
9457 [(set_attr "type" "branch")
9458 (set_attr "length" "4")])
9460 (define_insn "load_toc_v4_PIC_1"
9461 [(set (match_operand:SI 0 "register_operand" "=l")
9462 (match_operand:SI 1 "immediate_operand" "s"))
9463 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
9464 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
9465 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
9466 "bcl 20,31,%1\\n%1:"
9467 [(set_attr "type" "branch")
9468 (set_attr "length" "4")])
9470 (define_insn "load_toc_v4_PIC_1b"
9471 [(set (match_operand:SI 0 "register_operand" "=l")
9472 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
9474 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9475 "bcl 20,31,$+8\\n\\t.long %1-$"
9476 [(set_attr "type" "branch")
9477 (set_attr "length" "8")])
9479 (define_insn "load_toc_v4_PIC_2"
9480 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9481 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9482 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
9483 (match_operand:SI 3 "immediate_operand" "s")))))]
9484 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9485 "{l|lwz} %0,%2-%3(%1)"
9486 [(set_attr "type" "load")])
9488 (define_insn "load_toc_v4_PIC_3b"
9489 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9490 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9492 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
9493 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
9494 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
9495 "{cau|addis} %0,%1,%2-%3@ha")
9497 (define_insn "load_toc_v4_PIC_3c"
9498 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9499 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9500 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
9501 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
9502 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
9503 "{cal|addi} %0,%1,%2-%3@l")
9505 ;; If the TOC is shared over a translation unit, as happens with all
9506 ;; the kinds of PIC that we support, we need to restore the TOC
9507 ;; pointer only when jumping over units of translation.
9508 ;; On Darwin, we need to reload the picbase.
9510 (define_expand "builtin_setjmp_receiver"
9511 [(use (label_ref (match_operand 0 "" "")))]
9512 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
9513 || (TARGET_TOC && TARGET_MINIMAL_TOC)
9514 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
9518 if (DEFAULT_ABI == ABI_DARWIN)
9520 const char *picbase = machopic_function_base_name ();
9521 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
9522 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
9526 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
9527 CODE_LABEL_NUMBER (operands[0]));
9528 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
9530 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
9531 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
9535 rs6000_emit_load_toc_table (FALSE);
9539 ;; Elf specific ways of loading addresses for non-PIC code.
9540 ;; The output of this could be r0, but we make a very strong
9541 ;; preference for a base register because it will usually
9543 (define_insn "elf_high"
9544 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
9545 (high:SI (match_operand 1 "" "")))]
9546 "TARGET_ELF && ! TARGET_64BIT"
9547 "{liu|lis} %0,%1@ha")
9549 (define_insn "elf_low"
9550 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9551 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
9552 (match_operand 2 "" "")))]
9553 "TARGET_ELF && ! TARGET_64BIT"
9555 {cal|la} %0,%2@l(%1)
9556 {ai|addic} %0,%1,%K2")
9558 ;; A function pointer under AIX is a pointer to a data area whose first word
9559 ;; contains the actual address of the function, whose second word contains a
9560 ;; pointer to its TOC, and whose third word contains a value to place in the
9561 ;; static chain register (r11). Note that if we load the static chain, our
9562 ;; "trampoline" need not have any executable code.
9564 (define_expand "call_indirect_aix32"
9566 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
9567 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9570 (mem:SI (plus:SI (match_dup 0)
9573 (mem:SI (plus:SI (match_dup 0)
9575 (parallel [(call (mem:SI (match_dup 2))
9576 (match_operand 1 "" ""))
9580 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9581 (clobber (scratch:SI))])]
9584 { operands[2] = gen_reg_rtx (SImode); }")
9586 (define_expand "call_indirect_aix64"
9588 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
9589 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9592 (mem:DI (plus:DI (match_dup 0)
9595 (mem:DI (plus:DI (match_dup 0)
9597 (parallel [(call (mem:SI (match_dup 2))
9598 (match_operand 1 "" ""))
9602 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9603 (clobber (scratch:SI))])]
9606 { operands[2] = gen_reg_rtx (DImode); }")
9608 (define_expand "call_value_indirect_aix32"
9610 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
9611 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9614 (mem:SI (plus:SI (match_dup 1)
9617 (mem:SI (plus:SI (match_dup 1)
9619 (parallel [(set (match_operand 0 "" "")
9620 (call (mem:SI (match_dup 3))
9621 (match_operand 2 "" "")))
9625 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9626 (clobber (scratch:SI))])]
9629 { operands[3] = gen_reg_rtx (SImode); }")
9631 (define_expand "call_value_indirect_aix64"
9633 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
9634 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9637 (mem:DI (plus:DI (match_dup 1)
9640 (mem:DI (plus:DI (match_dup 1)
9642 (parallel [(set (match_operand 0 "" "")
9643 (call (mem:SI (match_dup 3))
9644 (match_operand 2 "" "")))
9648 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9649 (clobber (scratch:SI))])]
9652 { operands[3] = gen_reg_rtx (DImode); }")
9654 ;; Now the definitions for the call and call_value insns
9655 (define_expand "call"
9656 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
9657 (match_operand 1 "" ""))
9658 (use (match_operand 2 "" ""))
9659 (clobber (scratch:SI))])]
9664 if (MACHOPIC_INDIRECT)
9665 operands[0] = machopic_indirect_call_target (operands[0]);
9668 gcc_assert (GET_CODE (operands[0]) == MEM);
9669 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
9671 operands[0] = XEXP (operands[0], 0);
9673 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
9675 && GET_CODE (operands[0]) == SYMBOL_REF
9676 && !SYMBOL_REF_LOCAL_P (operands[0]))
9682 gen_rtx_CALL (VOIDmode,
9683 gen_rtx_MEM (SImode, operands[0]),
9685 gen_rtx_USE (VOIDmode, operands[2]),
9686 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
9687 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
9688 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
9692 if (GET_CODE (operands[0]) != SYMBOL_REF
9693 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
9694 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
9696 if (INTVAL (operands[2]) & CALL_LONG)
9697 operands[0] = rs6000_longcall_ref (operands[0]);
9699 switch (DEFAULT_ABI)
9703 operands[0] = force_reg (Pmode, operands[0]);
9707 /* AIX function pointers are really pointers to a three word
9709 emit_call_insn (TARGET_32BIT
9710 ? gen_call_indirect_aix32 (force_reg (SImode,
9713 : gen_call_indirect_aix64 (force_reg (DImode,
9724 (define_expand "call_value"
9725 [(parallel [(set (match_operand 0 "" "")
9726 (call (mem:SI (match_operand 1 "address_operand" ""))
9727 (match_operand 2 "" "")))
9728 (use (match_operand 3 "" ""))
9729 (clobber (scratch:SI))])]
9734 if (MACHOPIC_INDIRECT)
9735 operands[1] = machopic_indirect_call_target (operands[1]);
9738 gcc_assert (GET_CODE (operands[1]) == MEM);
9739 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
9741 operands[1] = XEXP (operands[1], 0);
9743 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
9745 && GET_CODE (operands[1]) == SYMBOL_REF
9746 && !SYMBOL_REF_LOCAL_P (operands[1]))
9752 gen_rtx_SET (VOIDmode,
9754 gen_rtx_CALL (VOIDmode,
9755 gen_rtx_MEM (SImode,
9758 gen_rtx_USE (VOIDmode, operands[3]),
9759 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
9760 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
9761 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
9765 if (GET_CODE (operands[1]) != SYMBOL_REF
9766 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
9767 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
9769 if (INTVAL (operands[3]) & CALL_LONG)
9770 operands[1] = rs6000_longcall_ref (operands[1]);
9772 switch (DEFAULT_ABI)
9776 operands[1] = force_reg (Pmode, operands[1]);
9780 /* AIX function pointers are really pointers to a three word
9782 emit_call_insn (TARGET_32BIT
9783 ? gen_call_value_indirect_aix32 (operands[0],
9787 : gen_call_value_indirect_aix64 (operands[0],
9799 ;; Call to function in current module. No TOC pointer reload needed.
9800 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
9801 ;; either the function was not prototyped, or it was prototyped as a
9802 ;; variable argument function. It is > 0 if FP registers were passed
9803 ;; and < 0 if they were not.
9805 (define_insn "*call_local32"
9806 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
9807 (match_operand 1 "" "g,g"))
9808 (use (match_operand:SI 2 "immediate_operand" "O,n"))
9809 (clobber (match_scratch:SI 3 "=l,l"))]
9810 "(INTVAL (operands[2]) & CALL_LONG) == 0"
9813 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
9814 output_asm_insn (\"crxor 6,6,6\", operands);
9816 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
9817 output_asm_insn (\"creqv 6,6,6\", operands);
9819 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
9821 [(set_attr "type" "branch")
9822 (set_attr "length" "4,8")])
9824 (define_insn "*call_local64"
9825 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
9826 (match_operand 1 "" "g,g"))
9827 (use (match_operand:SI 2 "immediate_operand" "O,n"))
9828 (clobber (match_scratch:SI 3 "=l,l"))]
9829 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
9832 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
9833 output_asm_insn (\"crxor 6,6,6\", operands);
9835 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
9836 output_asm_insn (\"creqv 6,6,6\", operands);
9838 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
9840 [(set_attr "type" "branch")
9841 (set_attr "length" "4,8")])
9843 (define_insn "*call_value_local32"
9844 [(set (match_operand 0 "" "")
9845 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
9846 (match_operand 2 "" "g,g")))
9847 (use (match_operand:SI 3 "immediate_operand" "O,n"))
9848 (clobber (match_scratch:SI 4 "=l,l"))]
9849 "(INTVAL (operands[3]) & CALL_LONG) == 0"
9852 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
9853 output_asm_insn (\"crxor 6,6,6\", operands);
9855 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
9856 output_asm_insn (\"creqv 6,6,6\", operands);
9858 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
9860 [(set_attr "type" "branch")
9861 (set_attr "length" "4,8")])
9864 (define_insn "*call_value_local64"
9865 [(set (match_operand 0 "" "")
9866 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
9867 (match_operand 2 "" "g,g")))
9868 (use (match_operand:SI 3 "immediate_operand" "O,n"))
9869 (clobber (match_scratch:SI 4 "=l,l"))]
9870 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
9873 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
9874 output_asm_insn (\"crxor 6,6,6\", operands);
9876 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
9877 output_asm_insn (\"creqv 6,6,6\", operands);
9879 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
9881 [(set_attr "type" "branch")
9882 (set_attr "length" "4,8")])
9884 ;; Call to function which may be in another module. Restore the TOC
9885 ;; pointer (r2) after the call unless this is System V.
9886 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
9887 ;; either the function was not prototyped, or it was prototyped as a
9888 ;; variable argument function. It is > 0 if FP registers were passed
9889 ;; and < 0 if they were not.
9891 (define_insn "*call_indirect_nonlocal_aix32"
9892 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
9893 (match_operand 1 "" "g,g"))
9897 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9898 (clobber (match_scratch:SI 2 "=l,l"))]
9899 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
9900 "b%T0l\;{l|lwz} 2,20(1)"
9901 [(set_attr "type" "jmpreg")
9902 (set_attr "length" "8")])
9904 (define_insn "*call_nonlocal_aix32"
9905 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
9906 (match_operand 1 "" "g"))
9907 (use (match_operand:SI 2 "immediate_operand" "O"))
9908 (clobber (match_scratch:SI 3 "=l"))]
9910 && DEFAULT_ABI == ABI_AIX
9911 && (INTVAL (operands[2]) & CALL_LONG) == 0"
9913 [(set_attr "type" "branch")
9914 (set_attr "length" "8")])
9916 (define_insn "*call_indirect_nonlocal_aix64"
9917 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
9918 (match_operand 1 "" "g,g"))
9922 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9923 (clobber (match_scratch:SI 2 "=l,l"))]
9924 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
9926 [(set_attr "type" "jmpreg")
9927 (set_attr "length" "8")])
9929 (define_insn "*call_nonlocal_aix64"
9930 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
9931 (match_operand 1 "" "g"))
9932 (use (match_operand:SI 2 "immediate_operand" "O"))
9933 (clobber (match_scratch:SI 3 "=l"))]
9935 && DEFAULT_ABI == ABI_AIX
9936 && (INTVAL (operands[2]) & CALL_LONG) == 0"
9938 [(set_attr "type" "branch")
9939 (set_attr "length" "8")])
9941 (define_insn "*call_value_indirect_nonlocal_aix32"
9942 [(set (match_operand 0 "" "")
9943 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
9944 (match_operand 2 "" "g,g")))
9948 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9949 (clobber (match_scratch:SI 3 "=l,l"))]
9950 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
9951 "b%T1l\;{l|lwz} 2,20(1)"
9952 [(set_attr "type" "jmpreg")
9953 (set_attr "length" "8")])
9955 (define_insn "*call_value_nonlocal_aix32"
9956 [(set (match_operand 0 "" "")
9957 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
9958 (match_operand 2 "" "g")))
9959 (use (match_operand:SI 3 "immediate_operand" "O"))
9960 (clobber (match_scratch:SI 4 "=l"))]
9962 && DEFAULT_ABI == ABI_AIX
9963 && (INTVAL (operands[3]) & CALL_LONG) == 0"
9965 [(set_attr "type" "branch")
9966 (set_attr "length" "8")])
9968 (define_insn "*call_value_indirect_nonlocal_aix64"
9969 [(set (match_operand 0 "" "")
9970 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
9971 (match_operand 2 "" "g,g")))
9975 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9976 (clobber (match_scratch:SI 3 "=l,l"))]
9977 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
9979 [(set_attr "type" "jmpreg")
9980 (set_attr "length" "8")])
9982 (define_insn "*call_value_nonlocal_aix64"
9983 [(set (match_operand 0 "" "")
9984 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
9985 (match_operand 2 "" "g")))
9986 (use (match_operand:SI 3 "immediate_operand" "O"))
9987 (clobber (match_scratch:SI 4 "=l"))]
9989 && DEFAULT_ABI == ABI_AIX
9990 && (INTVAL (operands[3]) & CALL_LONG) == 0"
9992 [(set_attr "type" "branch")
9993 (set_attr "length" "8")])
9995 ;; A function pointer under System V is just a normal pointer
9996 ;; operands[0] is the function pointer
9997 ;; operands[1] is the stack size to clean up
9998 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
9999 ;; which indicates how to set cr1
10001 (define_insn "*call_indirect_nonlocal_sysv"
10002 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l,c,*l"))
10003 (match_operand 1 "" "g,g,g,g"))
10004 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
10005 (clobber (match_scratch:SI 3 "=l,l,l,l"))]
10006 "DEFAULT_ABI == ABI_V4
10007 || DEFAULT_ABI == ABI_DARWIN"
10009 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10010 output_asm_insn ("crxor 6,6,6", operands);
10012 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10013 output_asm_insn ("creqv 6,6,6", operands);
10017 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10018 (set_attr "length" "4,4,8,8")])
10020 (define_insn "*call_nonlocal_sysv"
10021 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10022 (match_operand 1 "" "g,g"))
10023 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10024 (clobber (match_scratch:SI 3 "=l,l"))]
10025 "(DEFAULT_ABI == ABI_DARWIN
10026 || (DEFAULT_ABI == ABI_V4
10027 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10029 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10030 output_asm_insn ("crxor 6,6,6", operands);
10032 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10033 output_asm_insn ("creqv 6,6,6", operands);
10036 return output_call(insn, operands, 0, 2);
10038 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10040 if (TARGET_SECURE_PLT && flag_pic == 2)
10041 /* The magic 32768 offset here and in the other sysv call insns
10042 corresponds to the offset of r30 in .got2, as given by LCTOC1.
10043 See sysv4.h:toc_section. */
10044 return "bl %z0+32768@plt";
10046 return "bl %z0@plt";
10052 [(set_attr "type" "branch,branch")
10053 (set_attr "length" "4,8")])
10055 (define_insn "*call_value_indirect_nonlocal_sysv"
10056 [(set (match_operand 0 "" "")
10057 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l,c,*l"))
10058 (match_operand 2 "" "g,g,g,g")))
10059 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
10060 (clobber (match_scratch:SI 4 "=l,l,l,l"))]
10061 "DEFAULT_ABI == ABI_V4
10062 || DEFAULT_ABI == ABI_DARWIN"
10064 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10065 output_asm_insn ("crxor 6,6,6", operands);
10067 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10068 output_asm_insn ("creqv 6,6,6", operands);
10072 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10073 (set_attr "length" "4,4,8,8")])
10075 (define_insn "*call_value_nonlocal_sysv"
10076 [(set (match_operand 0 "" "")
10077 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10078 (match_operand 2 "" "g,g")))
10079 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10080 (clobber (match_scratch:SI 4 "=l,l"))]
10081 "(DEFAULT_ABI == ABI_DARWIN
10082 || (DEFAULT_ABI == ABI_V4
10083 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10085 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10086 output_asm_insn ("crxor 6,6,6", operands);
10088 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10089 output_asm_insn ("creqv 6,6,6", operands);
10092 return output_call(insn, operands, 1, 3);
10094 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10096 if (TARGET_SECURE_PLT && flag_pic == 2)
10097 return "bl %z1+32768@plt";
10099 return "bl %z1@plt";
10105 [(set_attr "type" "branch,branch")
10106 (set_attr "length" "4,8")])
10108 ;; Call subroutine returning any type.
10109 (define_expand "untyped_call"
10110 [(parallel [(call (match_operand 0 "" "")
10112 (match_operand 1 "" "")
10113 (match_operand 2 "" "")])]
10119 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10121 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10123 rtx set = XVECEXP (operands[2], 0, i);
10124 emit_move_insn (SET_DEST (set), SET_SRC (set));
10127 /* The optimizer does not know that the call sets the function value
10128 registers we stored in the result block. We avoid problems by
10129 claiming that all hard registers are used and clobbered at this
10131 emit_insn (gen_blockage ());
10136 ;; sibling call patterns
10137 (define_expand "sibcall"
10138 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10139 (match_operand 1 "" ""))
10140 (use (match_operand 2 "" ""))
10141 (use (match_operand 3 "" ""))
10147 if (MACHOPIC_INDIRECT)
10148 operands[0] = machopic_indirect_call_target (operands[0]);
10151 gcc_assert (GET_CODE (operands[0]) == MEM);
10152 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10154 operands[0] = XEXP (operands[0], 0);
10155 operands[3] = gen_reg_rtx (SImode);
10159 ;; this and similar patterns must be marked as using LR, otherwise
10160 ;; dataflow will try to delete the store into it. This is true
10161 ;; even when the actual reg to jump to is in CTR, when LR was
10162 ;; saved and restored around the PIC-setting BCL.
10163 (define_insn "*sibcall_local32"
10164 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10165 (match_operand 1 "" "g,g"))
10166 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10167 (use (match_operand:SI 3 "register_operand" "l,l"))
10169 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10172 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10173 output_asm_insn (\"crxor 6,6,6\", operands);
10175 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10176 output_asm_insn (\"creqv 6,6,6\", operands);
10178 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10180 [(set_attr "type" "branch")
10181 (set_attr "length" "4,8")])
10183 (define_insn "*sibcall_local64"
10184 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10185 (match_operand 1 "" "g,g"))
10186 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10187 (use (match_operand:SI 3 "register_operand" "l,l"))
10189 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10192 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10193 output_asm_insn (\"crxor 6,6,6\", operands);
10195 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10196 output_asm_insn (\"creqv 6,6,6\", operands);
10198 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10200 [(set_attr "type" "branch")
10201 (set_attr "length" "4,8")])
10203 (define_insn "*sibcall_value_local32"
10204 [(set (match_operand 0 "" "")
10205 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10206 (match_operand 2 "" "g,g")))
10207 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10208 (use (match_operand:SI 4 "register_operand" "l,l"))
10210 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10213 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10214 output_asm_insn (\"crxor 6,6,6\", operands);
10216 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10217 output_asm_insn (\"creqv 6,6,6\", operands);
10219 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10221 [(set_attr "type" "branch")
10222 (set_attr "length" "4,8")])
10225 (define_insn "*sibcall_value_local64"
10226 [(set (match_operand 0 "" "")
10227 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10228 (match_operand 2 "" "g,g")))
10229 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10230 (use (match_operand:SI 4 "register_operand" "l,l"))
10232 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10235 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10236 output_asm_insn (\"crxor 6,6,6\", operands);
10238 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10239 output_asm_insn (\"creqv 6,6,6\", operands);
10241 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10243 [(set_attr "type" "branch")
10244 (set_attr "length" "4,8")])
10246 (define_insn "*sibcall_nonlocal_aix32"
10247 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10248 (match_operand 1 "" "g"))
10249 (use (match_operand:SI 2 "immediate_operand" "O"))
10250 (use (match_operand:SI 3 "register_operand" "l"))
10253 && DEFAULT_ABI == ABI_AIX
10254 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10256 [(set_attr "type" "branch")
10257 (set_attr "length" "4")])
10259 (define_insn "*sibcall_nonlocal_aix64"
10260 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10261 (match_operand 1 "" "g"))
10262 (use (match_operand:SI 2 "immediate_operand" "O"))
10263 (use (match_operand:SI 3 "register_operand" "l"))
10266 && DEFAULT_ABI == ABI_AIX
10267 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10269 [(set_attr "type" "branch")
10270 (set_attr "length" "4")])
10272 (define_insn "*sibcall_value_nonlocal_aix32"
10273 [(set (match_operand 0 "" "")
10274 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10275 (match_operand 2 "" "g")))
10276 (use (match_operand:SI 3 "immediate_operand" "O"))
10277 (use (match_operand:SI 4 "register_operand" "l"))
10280 && DEFAULT_ABI == ABI_AIX
10281 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10283 [(set_attr "type" "branch")
10284 (set_attr "length" "4")])
10286 (define_insn "*sibcall_value_nonlocal_aix64"
10287 [(set (match_operand 0 "" "")
10288 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10289 (match_operand 2 "" "g")))
10290 (use (match_operand:SI 3 "immediate_operand" "O"))
10291 (use (match_operand:SI 4 "register_operand" "l"))
10294 && DEFAULT_ABI == ABI_AIX
10295 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10297 [(set_attr "type" "branch")
10298 (set_attr "length" "4")])
10300 (define_insn "*sibcall_nonlocal_sysv"
10301 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10302 (match_operand 1 "" ""))
10303 (use (match_operand 2 "immediate_operand" "O,n"))
10304 (use (match_operand:SI 3 "register_operand" "l,l"))
10306 "(DEFAULT_ABI == ABI_DARWIN
10307 || DEFAULT_ABI == ABI_V4)
10308 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10311 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10312 output_asm_insn (\"crxor 6,6,6\", operands);
10314 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10315 output_asm_insn (\"creqv 6,6,6\", operands);
10317 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10319 if (TARGET_SECURE_PLT && flag_pic == 2)
10320 return \"b %z0+32768@plt\";
10322 return \"b %z0@plt\";
10327 [(set_attr "type" "branch,branch")
10328 (set_attr "length" "4,8")])
10330 (define_expand "sibcall_value"
10331 [(parallel [(set (match_operand 0 "register_operand" "")
10332 (call (mem:SI (match_operand 1 "address_operand" ""))
10333 (match_operand 2 "" "")))
10334 (use (match_operand 3 "" ""))
10335 (use (match_operand 4 "" ""))
10341 if (MACHOPIC_INDIRECT)
10342 operands[1] = machopic_indirect_call_target (operands[1]);
10345 gcc_assert (GET_CODE (operands[1]) == MEM);
10346 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10348 operands[1] = XEXP (operands[1], 0);
10349 operands[4] = gen_reg_rtx (SImode);
10353 (define_insn "*sibcall_value_nonlocal_sysv"
10354 [(set (match_operand 0 "" "")
10355 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10356 (match_operand 2 "" "")))
10357 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10358 (use (match_operand:SI 4 "register_operand" "l,l"))
10360 "(DEFAULT_ABI == ABI_DARWIN
10361 || DEFAULT_ABI == ABI_V4)
10362 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10365 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10366 output_asm_insn (\"crxor 6,6,6\", operands);
10368 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10369 output_asm_insn (\"creqv 6,6,6\", operands);
10371 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10373 if (TARGET_SECURE_PLT && flag_pic == 2)
10374 return \"b %z1+32768@plt\";
10376 return \"b %z1@plt\";
10381 [(set_attr "type" "branch,branch")
10382 (set_attr "length" "4,8")])
10384 (define_expand "sibcall_epilogue"
10385 [(use (const_int 0))]
10386 "TARGET_SCHED_PROLOG"
10389 rs6000_emit_epilogue (TRUE);
10393 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10394 ;; all of memory. This blocks insns from being moved across this point.
10396 (define_insn "blockage"
10397 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
10401 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
10402 ;; signed & unsigned, and one type of branch.
10404 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
10405 ;; insns, and branches. We store the operands of compares until we see
10407 (define_expand "cmp<mode>"
10409 (compare (match_operand:GPR 0 "gpc_reg_operand" "")
10410 (match_operand:GPR 1 "reg_or_short_operand" "")))]
10414 /* Take care of the possibility that operands[1] might be negative but
10415 this might be a logical operation. That insn doesn't exist. */
10416 if (GET_CODE (operands[1]) == CONST_INT
10417 && INTVAL (operands[1]) < 0)
10418 operands[1] = force_reg (<MODE>mode, operands[1]);
10420 rs6000_compare_op0 = operands[0];
10421 rs6000_compare_op1 = operands[1];
10422 rs6000_compare_fp_p = 0;
10426 (define_expand "cmp<mode>"
10427 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
10428 (match_operand:FP 1 "gpc_reg_operand" "")))]
10432 rs6000_compare_op0 = operands[0];
10433 rs6000_compare_op1 = operands[1];
10434 rs6000_compare_fp_p = 1;
10438 (define_expand "beq"
10439 [(use (match_operand 0 "" ""))]
10441 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
10443 (define_expand "bne"
10444 [(use (match_operand 0 "" ""))]
10446 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
10448 (define_expand "bge"
10449 [(use (match_operand 0 "" ""))]
10451 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
10453 (define_expand "bgt"
10454 [(use (match_operand 0 "" ""))]
10456 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
10458 (define_expand "ble"
10459 [(use (match_operand 0 "" ""))]
10461 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
10463 (define_expand "blt"
10464 [(use (match_operand 0 "" ""))]
10466 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
10468 (define_expand "bgeu"
10469 [(use (match_operand 0 "" ""))]
10471 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
10473 (define_expand "bgtu"
10474 [(use (match_operand 0 "" ""))]
10476 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
10478 (define_expand "bleu"
10479 [(use (match_operand 0 "" ""))]
10481 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
10483 (define_expand "bltu"
10484 [(use (match_operand 0 "" ""))]
10486 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
10488 (define_expand "bunordered"
10489 [(use (match_operand 0 "" ""))]
10490 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10491 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
10493 (define_expand "bordered"
10494 [(use (match_operand 0 "" ""))]
10495 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10496 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
10498 (define_expand "buneq"
10499 [(use (match_operand 0 "" ""))]
10501 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
10503 (define_expand "bunge"
10504 [(use (match_operand 0 "" ""))]
10506 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
10508 (define_expand "bungt"
10509 [(use (match_operand 0 "" ""))]
10511 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
10513 (define_expand "bunle"
10514 [(use (match_operand 0 "" ""))]
10516 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
10518 (define_expand "bunlt"
10519 [(use (match_operand 0 "" ""))]
10521 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
10523 (define_expand "bltgt"
10524 [(use (match_operand 0 "" ""))]
10526 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
10528 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
10529 ;; For SEQ, likewise, except that comparisons with zero should be done
10530 ;; with an scc insns. However, due to the order that combine see the
10531 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
10532 ;; the cases we don't want to handle.
10533 (define_expand "seq"
10534 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10536 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
10538 (define_expand "sne"
10539 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10543 if (! rs6000_compare_fp_p)
10546 rs6000_emit_sCOND (NE, operands[0]);
10550 ;; A >= 0 is best done the portable way for A an integer.
10551 (define_expand "sge"
10552 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10556 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10559 rs6000_emit_sCOND (GE, operands[0]);
10563 ;; A > 0 is best done using the portable sequence, so fail in that case.
10564 (define_expand "sgt"
10565 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10569 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10572 rs6000_emit_sCOND (GT, operands[0]);
10576 ;; A <= 0 is best done the portable way for A an integer.
10577 (define_expand "sle"
10578 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10582 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10585 rs6000_emit_sCOND (LE, operands[0]);
10589 ;; A < 0 is best done in the portable way for A an integer.
10590 (define_expand "slt"
10591 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10595 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10598 rs6000_emit_sCOND (LT, operands[0]);
10602 (define_expand "sgeu"
10603 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10605 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
10607 (define_expand "sgtu"
10608 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10610 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
10612 (define_expand "sleu"
10613 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10615 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
10617 (define_expand "sltu"
10618 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10620 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
10622 (define_expand "sunordered"
10623 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10624 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10625 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
10627 (define_expand "sordered"
10628 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10629 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10630 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
10632 (define_expand "suneq"
10633 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10635 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
10637 (define_expand "sunge"
10638 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10640 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
10642 (define_expand "sungt"
10643 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10645 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
10647 (define_expand "sunle"
10648 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10650 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
10652 (define_expand "sunlt"
10653 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10655 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
10657 (define_expand "sltgt"
10658 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10660 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
10662 (define_expand "stack_protect_set"
10663 [(match_operand 0 "memory_operand" "")
10664 (match_operand 1 "memory_operand" "")]
10667 #ifdef TARGET_THREAD_SSP_OFFSET
10668 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
10669 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
10670 operands[1] = gen_rtx_MEM (Pmode, addr);
10673 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
10675 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
10679 (define_insn "stack_protect_setsi"
10680 [(set (match_operand:SI 0 "memory_operand" "=m")
10681 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
10682 (set (match_scratch:SI 2 "=&r") (const_int 0))]
10684 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
10685 [(set_attr "type" "three")
10686 (set_attr "length" "12")])
10688 (define_insn "stack_protect_setdi"
10689 [(set (match_operand:DI 0 "memory_operand" "=m")
10690 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
10691 (set (match_scratch:DI 2 "=&r") (const_int 0))]
10693 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
10694 [(set_attr "type" "three")
10695 (set_attr "length" "12")])
10697 (define_expand "stack_protect_test"
10698 [(match_operand 0 "memory_operand" "")
10699 (match_operand 1 "memory_operand" "")
10700 (match_operand 2 "" "")]
10703 #ifdef TARGET_THREAD_SSP_OFFSET
10704 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
10705 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
10706 operands[1] = gen_rtx_MEM (Pmode, addr);
10708 rs6000_compare_op0 = operands[0];
10709 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
10711 rs6000_compare_fp_p = 0;
10712 emit_jump_insn (gen_beq (operands[2]));
10716 (define_insn "stack_protect_testsi"
10717 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
10718 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
10719 (match_operand:SI 2 "memory_operand" "m,m")]
10721 (set (match_scratch:SI 4 "=r,r") (const_int 0))
10722 (clobber (match_scratch:SI 3 "=&r,&r"))]
10725 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
10726 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
10727 [(set_attr "length" "16,20")])
10729 (define_insn "stack_protect_testdi"
10730 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
10731 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
10732 (match_operand:DI 2 "memory_operand" "m,m")]
10734 (set (match_scratch:DI 4 "=r,r") (const_int 0))
10735 (clobber (match_scratch:DI 3 "=&r,&r"))]
10738 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
10739 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
10740 [(set_attr "length" "16,20")])
10743 ;; Here are the actual compare insns.
10744 (define_insn "*cmp<mode>_internal1"
10745 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
10746 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
10747 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
10749 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
10750 [(set_attr "type" "cmp")])
10752 ;; If we are comparing a register for equality with a large constant,
10753 ;; we can do this with an XOR followed by a compare. But this is profitable
10754 ;; only if the large constant is only used for the comparison (and in this
10755 ;; case we already have a register to reuse as scratch).
10757 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
10758 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
10761 [(set (match_operand:SI 0 "register_operand")
10762 (match_operand:SI 1 "logical_operand" ""))
10763 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
10765 (match_operand:SI 2 "logical_operand" "")]))
10766 (set (match_operand:CC 4 "cc_reg_operand" "")
10767 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
10770 (if_then_else (match_operator 6 "equality_operator"
10771 [(match_dup 4) (const_int 0)])
10772 (match_operand 7 "" "")
10773 (match_operand 8 "" "")))]
10774 "peep2_reg_dead_p (3, operands[0])
10775 && peep2_reg_dead_p (4, operands[4])"
10776 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
10777 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
10778 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
10781 /* Get the constant we are comparing against, and see what it looks like
10782 when sign-extended from 16 to 32 bits. Then see what constant we could
10783 XOR with SEXTC to get the sign-extended value. */
10784 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
10786 operands[1], operands[2]);
10787 HOST_WIDE_INT c = INTVAL (cnst);
10788 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
10789 HOST_WIDE_INT xorv = c ^ sextc;
10791 operands[9] = GEN_INT (xorv);
10792 operands[10] = GEN_INT (sextc);
10795 (define_insn "*cmpsi_internal2"
10796 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
10797 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
10798 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
10800 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
10801 [(set_attr "type" "cmp")])
10803 (define_insn "*cmpdi_internal2"
10804 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
10805 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
10806 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
10808 "cmpld%I2 %0,%1,%b2"
10809 [(set_attr "type" "cmp")])
10811 ;; The following two insns don't exist as single insns, but if we provide
10812 ;; them, we can swap an add and compare, which will enable us to overlap more
10813 ;; of the required delay between a compare and branch. We generate code for
10814 ;; them by splitting.
10817 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
10818 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
10819 (match_operand:SI 2 "short_cint_operand" "i")))
10820 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
10821 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
10824 [(set_attr "length" "8")])
10827 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
10828 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
10829 (match_operand:SI 2 "u_short_cint_operand" "i")))
10830 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
10831 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
10834 [(set_attr "length" "8")])
10837 [(set (match_operand:CC 3 "cc_reg_operand" "")
10838 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
10839 (match_operand:SI 2 "short_cint_operand" "")))
10840 (set (match_operand:SI 0 "gpc_reg_operand" "")
10841 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
10843 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
10844 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
10847 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
10848 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
10849 (match_operand:SI 2 "u_short_cint_operand" "")))
10850 (set (match_operand:SI 0 "gpc_reg_operand" "")
10851 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
10853 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
10854 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
10856 (define_insn "*cmpsf_internal1"
10857 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10858 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
10859 (match_operand:SF 2 "gpc_reg_operand" "f")))]
10860 "TARGET_HARD_FLOAT && TARGET_FPRS"
10862 [(set_attr "type" "fpcompare")])
10864 (define_insn "*cmpdf_internal1"
10865 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10866 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
10867 (match_operand:DF 2 "gpc_reg_operand" "f")))]
10868 "TARGET_HARD_FLOAT && TARGET_FPRS"
10870 [(set_attr "type" "fpcompare")])
10872 ;; Only need to compare second words if first words equal
10873 (define_insn "*cmptf_internal1"
10874 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10875 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
10876 (match_operand:TF 2 "gpc_reg_operand" "f")))]
10877 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
10878 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
10879 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
10880 [(set_attr "type" "fpcompare")
10881 (set_attr "length" "12")])
10883 (define_insn_and_split "*cmptf_internal2"
10884 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10885 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
10886 (match_operand:TF 2 "gpc_reg_operand" "f")))
10887 (clobber (match_scratch:DF 3 "=f"))
10888 (clobber (match_scratch:DF 4 "=f"))
10889 (clobber (match_scratch:DF 5 "=f"))
10890 (clobber (match_scratch:DF 6 "=f"))
10891 (clobber (match_scratch:DF 7 "=f"))
10892 (clobber (match_scratch:DF 8 "=f"))
10893 (clobber (match_scratch:DF 9 "=f"))
10894 (clobber (match_scratch:DF 10 "=f"))]
10895 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
10896 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
10898 "&& reload_completed"
10899 [(set (match_dup 3) (match_dup 13))
10900 (set (match_dup 4) (match_dup 14))
10901 (set (match_dup 9) (abs:DF (match_dup 5)))
10902 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
10903 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
10904 (label_ref (match_dup 11))
10906 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
10907 (set (pc) (label_ref (match_dup 12)))
10909 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
10910 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
10911 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
10912 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
10915 REAL_VALUE_TYPE rv;
10916 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
10917 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
10919 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
10920 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
10921 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
10922 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
10923 operands[11] = gen_label_rtx ();
10924 operands[12] = gen_label_rtx ();
10926 operands[13] = force_const_mem (DFmode,
10927 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
10928 operands[14] = force_const_mem (DFmode,
10929 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
10933 operands[13] = gen_const_mem (DFmode,
10934 create_TOC_reference (XEXP (operands[13], 0)));
10935 operands[14] = gen_const_mem (DFmode,
10936 create_TOC_reference (XEXP (operands[14], 0)));
10937 set_mem_alias_set (operands[13], get_TOC_alias_set ());
10938 set_mem_alias_set (operands[14], get_TOC_alias_set ());
10942 ;; Now we have the scc insns. We can do some combinations because of the
10943 ;; way the machine works.
10945 ;; Note that this is probably faster if we can put an insn between the
10946 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
10947 ;; cases the insns below which don't use an intermediate CR field will
10948 ;; be used instead.
10950 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10951 (match_operator:SI 1 "scc_comparison_operator"
10952 [(match_operand 2 "cc_reg_operand" "y")
10955 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
10956 [(set (attr "type")
10957 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
10958 (const_string "mfcrf")
10960 (const_string "mfcr")))
10961 (set_attr "length" "8")])
10963 ;; Same as above, but get the GT bit.
10964 (define_insn "move_from_CR_gt_bit"
10965 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10966 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
10968 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
10969 [(set_attr "type" "mfcr")
10970 (set_attr "length" "8")])
10972 ;; Same as above, but get the OV/ORDERED bit.
10973 (define_insn "move_from_CR_ov_bit"
10974 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10975 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
10977 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
10978 [(set_attr "type" "mfcr")
10979 (set_attr "length" "8")])
10982 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10983 (match_operator:DI 1 "scc_comparison_operator"
10984 [(match_operand 2 "cc_reg_operand" "y")
10987 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
10988 [(set (attr "type")
10989 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
10990 (const_string "mfcrf")
10992 (const_string "mfcr")))
10993 (set_attr "length" "8")])
10996 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
10997 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
10998 [(match_operand 2 "cc_reg_operand" "y,y")
11001 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11002 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11005 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
11007 [(set_attr "type" "delayed_compare")
11008 (set_attr "length" "8,16")])
11011 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11012 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11013 [(match_operand 2 "cc_reg_operand" "")
11016 (set (match_operand:SI 3 "gpc_reg_operand" "")
11017 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11018 "TARGET_32BIT && reload_completed"
11019 [(set (match_dup 3)
11020 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11022 (compare:CC (match_dup 3)
11027 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11028 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11029 [(match_operand 2 "cc_reg_operand" "y")
11031 (match_operand:SI 3 "const_int_operand" "n")))]
11035 int is_bit = ccr_bit (operands[1], 1);
11036 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11039 if (is_bit >= put_bit)
11040 count = is_bit - put_bit;
11042 count = 32 - (put_bit - is_bit);
11044 operands[4] = GEN_INT (count);
11045 operands[5] = GEN_INT (put_bit);
11047 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11049 [(set (attr "type")
11050 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11051 (const_string "mfcrf")
11053 (const_string "mfcr")))
11054 (set_attr "length" "8")])
11057 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11059 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11060 [(match_operand 2 "cc_reg_operand" "y,y")
11062 (match_operand:SI 3 "const_int_operand" "n,n"))
11064 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11065 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11070 int is_bit = ccr_bit (operands[1], 1);
11071 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11074 /* Force split for non-cc0 compare. */
11075 if (which_alternative == 1)
11078 if (is_bit >= put_bit)
11079 count = is_bit - put_bit;
11081 count = 32 - (put_bit - is_bit);
11083 operands[5] = GEN_INT (count);
11084 operands[6] = GEN_INT (put_bit);
11086 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
11088 [(set_attr "type" "delayed_compare")
11089 (set_attr "length" "8,16")])
11092 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11094 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11095 [(match_operand 2 "cc_reg_operand" "")
11097 (match_operand:SI 3 "const_int_operand" ""))
11099 (set (match_operand:SI 4 "gpc_reg_operand" "")
11100 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11103 [(set (match_dup 4)
11104 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11107 (compare:CC (match_dup 4)
11111 ;; There is a 3 cycle delay between consecutive mfcr instructions
11112 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11115 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11116 (match_operator:SI 1 "scc_comparison_operator"
11117 [(match_operand 2 "cc_reg_operand" "y")
11119 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11120 (match_operator:SI 4 "scc_comparison_operator"
11121 [(match_operand 5 "cc_reg_operand" "y")
11123 "REGNO (operands[2]) != REGNO (operands[5])"
11124 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11125 [(set_attr "type" "mfcr")
11126 (set_attr "length" "12")])
11129 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11130 (match_operator:DI 1 "scc_comparison_operator"
11131 [(match_operand 2 "cc_reg_operand" "y")
11133 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11134 (match_operator:DI 4 "scc_comparison_operator"
11135 [(match_operand 5 "cc_reg_operand" "y")
11137 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11138 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11139 [(set_attr "type" "mfcr")
11140 (set_attr "length" "12")])
11142 ;; There are some scc insns that can be done directly, without a compare.
11143 ;; These are faster because they don't involve the communications between
11144 ;; the FXU and branch units. In fact, we will be replacing all of the
11145 ;; integer scc insns here or in the portable methods in emit_store_flag.
11147 ;; Also support (neg (scc ..)) since that construct is used to replace
11148 ;; branches, (plus (scc ..) ..) since that construct is common and
11149 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11150 ;; cases where it is no more expensive than (neg (scc ..)).
11152 ;; Have reload force a constant into a register for the simple insns that
11153 ;; otherwise won't accept constants. We do this because it is faster than
11154 ;; the cmp/mfcr sequence we would otherwise generate.
11156 (define_mode_attr scc_eq_op2 [(SI "rKLI")
11159 (define_insn_and_split "*eq<mode>"
11160 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
11161 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
11162 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
11166 [(set (match_dup 0)
11167 (clz:GPR (match_dup 3)))
11169 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
11171 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11173 /* Use output operand as intermediate. */
11174 operands[3] = operands[0];
11176 if (logical_operand (operands[2], <MODE>mode))
11177 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11178 gen_rtx_XOR (<MODE>mode,
11179 operands[1], operands[2])));
11181 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11182 gen_rtx_PLUS (<MODE>mode, operands[1],
11183 negate_rtx (<MODE>mode,
11187 operands[3] = operands[1];
11189 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11192 (define_insn_and_split "*eq<mode>_compare"
11193 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11195 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
11196 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
11198 (set (match_operand:P 0 "gpc_reg_operand" "=r")
11199 (eq:P (match_dup 1) (match_dup 2)))]
11200 "!TARGET_POWER && optimize_size"
11202 "!TARGET_POWER && optimize_size"
11203 [(set (match_dup 0)
11204 (clz:P (match_dup 4)))
11205 (parallel [(set (match_dup 3)
11206 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
11209 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
11211 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11213 /* Use output operand as intermediate. */
11214 operands[4] = operands[0];
11216 if (logical_operand (operands[2], <MODE>mode))
11217 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11218 gen_rtx_XOR (<MODE>mode,
11219 operands[1], operands[2])));
11221 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11222 gen_rtx_PLUS (<MODE>mode, operands[1],
11223 negate_rtx (<MODE>mode,
11227 operands[4] = operands[1];
11229 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11232 ;; We have insns of the form shown by the first define_insn below. If
11233 ;; there is something inside the comparison operation, we must split it.
11235 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11236 (plus:SI (match_operator 1 "comparison_operator"
11237 [(match_operand:SI 2 "" "")
11238 (match_operand:SI 3
11239 "reg_or_cint_operand" "")])
11240 (match_operand:SI 4 "gpc_reg_operand" "")))
11241 (clobber (match_operand:SI 5 "register_operand" ""))]
11242 "! gpc_reg_operand (operands[2], SImode)"
11243 [(set (match_dup 5) (match_dup 2))
11244 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11247 (define_insn "*plus_eqsi"
11248 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11249 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11250 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
11251 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11252 "TARGET_32BIT && optimize_size"
11254 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11255 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11256 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11257 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11258 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
11259 [(set_attr "type" "three,two,three,three,three")
11260 (set_attr "length" "12,8,12,12,12")])
11262 (define_insn "*compare_plus_eqsi"
11263 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11266 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11267 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
11268 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11270 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11271 "TARGET_32BIT && optimize_size"
11273 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11274 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
11275 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11276 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11277 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11283 [(set_attr "type" "compare")
11284 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11287 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11290 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11291 (match_operand:SI 2 "scc_eq_operand" ""))
11292 (match_operand:SI 3 "gpc_reg_operand" ""))
11294 (clobber (match_scratch:SI 4 ""))]
11295 "TARGET_32BIT && optimize_size && reload_completed"
11296 [(set (match_dup 4)
11297 (plus:SI (eq:SI (match_dup 1)
11301 (compare:CC (match_dup 4)
11305 (define_insn "*plus_eqsi_compare"
11306 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11309 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11310 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
11311 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11313 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11314 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11315 "TARGET_32BIT && optimize_size"
11317 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11318 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
11319 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11320 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11321 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11327 [(set_attr "type" "compare")
11328 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11331 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11334 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11335 (match_operand:SI 2 "scc_eq_operand" ""))
11336 (match_operand:SI 3 "gpc_reg_operand" ""))
11338 (set (match_operand:SI 0 "gpc_reg_operand" "")
11339 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11340 "TARGET_32BIT && optimize_size && reload_completed"
11341 [(set (match_dup 0)
11342 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11344 (compare:CC (match_dup 0)
11348 (define_insn "*neg_eq0<mode>"
11349 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11350 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
11353 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
11354 [(set_attr "type" "two")
11355 (set_attr "length" "8")])
11357 (define_insn_and_split "*neg_eq<mode>"
11358 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11359 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
11360 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
11364 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
11366 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11368 /* Use output operand as intermediate. */
11369 operands[3] = operands[0];
11371 if (logical_operand (operands[2], <MODE>mode))
11372 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11373 gen_rtx_XOR (<MODE>mode,
11374 operands[1], operands[2])));
11376 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11377 gen_rtx_PLUS (<MODE>mode, operands[1],
11378 negate_rtx (<MODE>mode,
11382 operands[3] = operands[1];
11385 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
11386 ;; since it nabs/sr is just as fast.
11387 (define_insn "*ne0si"
11388 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11389 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11391 (clobber (match_scratch:SI 2 "=&r"))]
11392 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
11393 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
11394 [(set_attr "type" "two")
11395 (set_attr "length" "8")])
11397 (define_insn "*ne0di"
11398 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11399 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11401 (clobber (match_scratch:DI 2 "=&r"))]
11403 "addic %2,%1,-1\;subfe %0,%2,%1"
11404 [(set_attr "type" "two")
11405 (set_attr "length" "8")])
11407 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
11408 (define_insn "*plus_ne0si"
11409 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11410 (plus:SI (lshiftrt:SI
11411 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11413 (match_operand:SI 2 "gpc_reg_operand" "r")))
11414 (clobber (match_scratch:SI 3 "=&r"))]
11416 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
11417 [(set_attr "type" "two")
11418 (set_attr "length" "8")])
11420 (define_insn "*plus_ne0di"
11421 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11422 (plus:DI (lshiftrt:DI
11423 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11425 (match_operand:DI 2 "gpc_reg_operand" "r")))
11426 (clobber (match_scratch:DI 3 "=&r"))]
11428 "addic %3,%1,-1\;addze %0,%2"
11429 [(set_attr "type" "two")
11430 (set_attr "length" "8")])
11432 (define_insn "*compare_plus_ne0si"
11433 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11435 (plus:SI (lshiftrt:SI
11436 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11438 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11440 (clobber (match_scratch:SI 3 "=&r,&r"))
11441 (clobber (match_scratch:SI 4 "=X,&r"))]
11444 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
11446 [(set_attr "type" "compare")
11447 (set_attr "length" "8,12")])
11450 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11452 (plus:SI (lshiftrt:SI
11453 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11455 (match_operand:SI 2 "gpc_reg_operand" ""))
11457 (clobber (match_scratch:SI 3 ""))
11458 (clobber (match_scratch:SI 4 ""))]
11459 "TARGET_32BIT && reload_completed"
11460 [(parallel [(set (match_dup 3)
11461 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
11464 (clobber (match_dup 4))])
11466 (compare:CC (match_dup 3)
11470 (define_insn "*compare_plus_ne0di"
11471 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11473 (plus:DI (lshiftrt:DI
11474 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11476 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11478 (clobber (match_scratch:DI 3 "=&r,&r"))]
11481 addic %3,%1,-1\;addze. %3,%2
11483 [(set_attr "type" "compare")
11484 (set_attr "length" "8,12")])
11487 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11489 (plus:DI (lshiftrt:DI
11490 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11492 (match_operand:DI 2 "gpc_reg_operand" ""))
11494 (clobber (match_scratch:DI 3 ""))]
11495 "TARGET_64BIT && reload_completed"
11496 [(set (match_dup 3)
11497 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
11501 (compare:CC (match_dup 3)
11505 (define_insn "*plus_ne0si_compare"
11506 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11508 (plus:SI (lshiftrt:SI
11509 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11511 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11513 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11514 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11516 (clobber (match_scratch:SI 3 "=&r,&r"))]
11519 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
11521 [(set_attr "type" "compare")
11522 (set_attr "length" "8,12")])
11525 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11527 (plus:SI (lshiftrt:SI
11528 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11530 (match_operand:SI 2 "gpc_reg_operand" ""))
11532 (set (match_operand:SI 0 "gpc_reg_operand" "")
11533 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11535 (clobber (match_scratch:SI 3 ""))]
11536 "TARGET_32BIT && reload_completed"
11537 [(parallel [(set (match_dup 0)
11538 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11540 (clobber (match_dup 3))])
11542 (compare:CC (match_dup 0)
11546 (define_insn "*plus_ne0di_compare"
11547 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11549 (plus:DI (lshiftrt:DI
11550 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11552 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11554 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11555 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11557 (clobber (match_scratch:DI 3 "=&r,&r"))]
11560 addic %3,%1,-1\;addze. %0,%2
11562 [(set_attr "type" "compare")
11563 (set_attr "length" "8,12")])
11566 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11568 (plus:DI (lshiftrt:DI
11569 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11571 (match_operand:DI 2 "gpc_reg_operand" ""))
11573 (set (match_operand:DI 0 "gpc_reg_operand" "")
11574 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11576 (clobber (match_scratch:DI 3 ""))]
11577 "TARGET_64BIT && reload_completed"
11578 [(parallel [(set (match_dup 0)
11579 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11581 (clobber (match_dup 3))])
11583 (compare:CC (match_dup 0)
11588 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11589 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11590 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
11591 (clobber (match_scratch:SI 3 "=r,X"))]
11594 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
11595 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
11596 [(set_attr "length" "12")])
11599 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
11601 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11602 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11604 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11605 (le:SI (match_dup 1) (match_dup 2)))
11606 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
11609 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
11610 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
11613 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
11614 (set_attr "length" "12,12,16,16")])
11617 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11619 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11620 (match_operand:SI 2 "reg_or_short_operand" ""))
11622 (set (match_operand:SI 0 "gpc_reg_operand" "")
11623 (le:SI (match_dup 1) (match_dup 2)))
11624 (clobber (match_scratch:SI 3 ""))]
11625 "TARGET_POWER && reload_completed"
11626 [(parallel [(set (match_dup 0)
11627 (le:SI (match_dup 1) (match_dup 2)))
11628 (clobber (match_dup 3))])
11630 (compare:CC (match_dup 0)
11635 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
11636 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11637 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
11638 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
11641 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11642 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
11643 [(set_attr "length" "12")])
11646 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
11648 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11649 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11650 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11652 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11655 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11656 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
11659 [(set_attr "type" "compare")
11660 (set_attr "length" "12,12,16,16")])
11663 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11665 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11666 (match_operand:SI 2 "reg_or_short_operand" ""))
11667 (match_operand:SI 3 "gpc_reg_operand" ""))
11669 (clobber (match_scratch:SI 4 ""))]
11670 "TARGET_POWER && reload_completed"
11671 [(set (match_dup 4)
11672 (plus:SI (le:SI (match_dup 1) (match_dup 2))
11675 (compare:CC (match_dup 4)
11680 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
11682 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11683 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11684 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11686 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
11687 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11690 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11691 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
11694 [(set_attr "type" "compare")
11695 (set_attr "length" "12,12,16,16")])
11698 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11700 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11701 (match_operand:SI 2 "reg_or_short_operand" ""))
11702 (match_operand:SI 3 "gpc_reg_operand" ""))
11704 (set (match_operand:SI 0 "gpc_reg_operand" "")
11705 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11706 "TARGET_POWER && reload_completed"
11707 [(set (match_dup 0)
11708 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11710 (compare:CC (match_dup 0)
11715 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11716 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11717 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
11720 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11721 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
11722 [(set_attr "length" "12")])
11724 (define_insn "*leu<mode>"
11725 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11726 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
11727 (match_operand:P 2 "reg_or_short_operand" "rI")))]
11729 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
11730 [(set_attr "type" "three")
11731 (set_attr "length" "12")])
11733 (define_insn "*leu<mode>_compare"
11734 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11736 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
11737 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
11739 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
11740 (leu:P (match_dup 1) (match_dup 2)))]
11743 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
11745 [(set_attr "type" "compare")
11746 (set_attr "length" "12,16")])
11749 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11751 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
11752 (match_operand:P 2 "reg_or_short_operand" ""))
11754 (set (match_operand:P 0 "gpc_reg_operand" "")
11755 (leu:P (match_dup 1) (match_dup 2)))]
11757 [(set (match_dup 0)
11758 (leu:P (match_dup 1) (match_dup 2)))
11760 (compare:CC (match_dup 0)
11764 (define_insn "*plus_leu<mode>"
11765 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
11766 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
11767 (match_operand:P 2 "reg_or_short_operand" "rI"))
11768 (match_operand:P 3 "gpc_reg_operand" "r")))]
11770 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
11771 [(set_attr "type" "two")
11772 (set_attr "length" "8")])
11775 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11777 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11778 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11779 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11781 (clobber (match_scratch:SI 4 "=&r,&r"))]
11784 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
11786 [(set_attr "type" "compare")
11787 (set_attr "length" "8,12")])
11790 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11792 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11793 (match_operand:SI 2 "reg_or_short_operand" ""))
11794 (match_operand:SI 3 "gpc_reg_operand" ""))
11796 (clobber (match_scratch:SI 4 ""))]
11797 "TARGET_32BIT && reload_completed"
11798 [(set (match_dup 4)
11799 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
11802 (compare:CC (match_dup 4)
11807 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11809 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11810 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11811 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11813 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
11814 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11817 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
11819 [(set_attr "type" "compare")
11820 (set_attr "length" "8,12")])
11823 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11825 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11826 (match_operand:SI 2 "reg_or_short_operand" ""))
11827 (match_operand:SI 3 "gpc_reg_operand" ""))
11829 (set (match_operand:SI 0 "gpc_reg_operand" "")
11830 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11831 "TARGET_32BIT && reload_completed"
11832 [(set (match_dup 0)
11833 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11835 (compare:CC (match_dup 0)
11839 (define_insn "*neg_leu<mode>"
11840 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11841 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
11842 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
11844 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
11845 [(set_attr "type" "three")
11846 (set_attr "length" "12")])
11848 (define_insn "*and_neg_leu<mode>"
11849 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
11851 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
11852 (match_operand:P 2 "reg_or_short_operand" "rI")))
11853 (match_operand:P 3 "gpc_reg_operand" "r")))]
11855 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
11856 [(set_attr "type" "three")
11857 (set_attr "length" "12")])
11860 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11863 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11864 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
11865 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11867 (clobber (match_scratch:SI 4 "=&r,&r"))]
11870 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
11872 [(set_attr "type" "compare")
11873 (set_attr "length" "12,16")])
11876 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11879 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11880 (match_operand:SI 2 "reg_or_short_operand" "")))
11881 (match_operand:SI 3 "gpc_reg_operand" ""))
11883 (clobber (match_scratch:SI 4 ""))]
11884 "TARGET_32BIT && reload_completed"
11885 [(set (match_dup 4)
11886 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
11889 (compare:CC (match_dup 4)
11894 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11897 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11898 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
11899 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11901 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
11902 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
11905 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
11907 [(set_attr "type" "compare")
11908 (set_attr "length" "12,16")])
11911 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11914 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11915 (match_operand:SI 2 "reg_or_short_operand" "")))
11916 (match_operand:SI 3 "gpc_reg_operand" ""))
11918 (set (match_operand:SI 0 "gpc_reg_operand" "")
11919 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
11920 "TARGET_32BIT && reload_completed"
11921 [(set (match_dup 0)
11922 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
11925 (compare:CC (match_dup 0)
11930 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11931 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11932 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11934 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
11935 [(set_attr "length" "12")])
11938 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11940 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11941 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11943 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11944 (lt:SI (match_dup 1) (match_dup 2)))]
11947 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
11949 [(set_attr "type" "delayed_compare")
11950 (set_attr "length" "12,16")])
11953 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11955 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11956 (match_operand:SI 2 "reg_or_short_operand" ""))
11958 (set (match_operand:SI 0 "gpc_reg_operand" "")
11959 (lt:SI (match_dup 1) (match_dup 2)))]
11960 "TARGET_POWER && reload_completed"
11961 [(set (match_dup 0)
11962 (lt:SI (match_dup 1) (match_dup 2)))
11964 (compare:CC (match_dup 0)
11969 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11970 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11971 (match_operand:SI 2 "reg_or_short_operand" "rI"))
11972 (match_operand:SI 3 "gpc_reg_operand" "r")))]
11974 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
11975 [(set_attr "length" "12")])
11978 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11980 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11981 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11982 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11984 (clobber (match_scratch:SI 4 "=&r,&r"))]
11987 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
11989 [(set_attr "type" "compare")
11990 (set_attr "length" "12,16")])
11993 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11995 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11996 (match_operand:SI 2 "reg_or_short_operand" ""))
11997 (match_operand:SI 3 "gpc_reg_operand" ""))
11999 (clobber (match_scratch:SI 4 ""))]
12000 "TARGET_POWER && reload_completed"
12001 [(set (match_dup 4)
12002 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
12005 (compare:CC (match_dup 4)
12010 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12012 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12013 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12014 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12016 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12017 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12020 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12022 [(set_attr "type" "compare")
12023 (set_attr "length" "12,16")])
12026 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12028 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12029 (match_operand:SI 2 "reg_or_short_operand" ""))
12030 (match_operand:SI 3 "gpc_reg_operand" ""))
12032 (set (match_operand:SI 0 "gpc_reg_operand" "")
12033 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12034 "TARGET_POWER && reload_completed"
12035 [(set (match_dup 0)
12036 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12038 (compare:CC (match_dup 0)
12043 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12044 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12045 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12047 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12048 [(set_attr "length" "12")])
12050 (define_insn_and_split "*ltu<mode>"
12051 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12052 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12053 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12057 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12058 (set (match_dup 0) (neg:P (match_dup 0)))]
12061 (define_insn_and_split "*ltu<mode>_compare"
12062 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12064 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12065 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12067 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12068 (ltu:P (match_dup 1) (match_dup 2)))]
12072 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12073 (parallel [(set (match_dup 3)
12074 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12075 (set (match_dup 0) (neg:P (match_dup 0)))])]
12078 (define_insn_and_split "*plus_ltu<mode>"
12079 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
12080 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12081 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12082 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
12085 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12086 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12087 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
12090 (define_insn_and_split "*plus_ltu<mode>_compare"
12091 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12093 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12094 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12095 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
12097 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12098 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
12101 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12102 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12103 (parallel [(set (match_dup 4)
12104 (compare:CC (minus:P (match_dup 3) (match_dup 0))
12106 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
12109 (define_insn "*neg_ltu<mode>"
12110 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12111 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12112 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
12115 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12116 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12117 [(set_attr "type" "two")
12118 (set_attr "length" "8")])
12121 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12122 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12123 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12124 (clobber (match_scratch:SI 3 "=r"))]
12126 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
12127 [(set_attr "length" "12")])
12130 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12132 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12133 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12135 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12136 (ge:SI (match_dup 1) (match_dup 2)))
12137 (clobber (match_scratch:SI 3 "=r,r"))]
12140 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12142 [(set_attr "type" "compare")
12143 (set_attr "length" "12,16")])
12146 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12148 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12149 (match_operand:SI 2 "reg_or_short_operand" ""))
12151 (set (match_operand:SI 0 "gpc_reg_operand" "")
12152 (ge:SI (match_dup 1) (match_dup 2)))
12153 (clobber (match_scratch:SI 3 ""))]
12154 "TARGET_POWER && reload_completed"
12155 [(parallel [(set (match_dup 0)
12156 (ge:SI (match_dup 1) (match_dup 2)))
12157 (clobber (match_dup 3))])
12159 (compare:CC (match_dup 0)
12164 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12165 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12166 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12167 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12169 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12170 [(set_attr "length" "12")])
12173 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12175 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12176 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12177 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12179 (clobber (match_scratch:SI 4 "=&r,&r"))]
12182 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12184 [(set_attr "type" "compare")
12185 (set_attr "length" "12,16")])
12188 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12190 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12191 (match_operand:SI 2 "reg_or_short_operand" ""))
12192 (match_operand:SI 3 "gpc_reg_operand" ""))
12194 (clobber (match_scratch:SI 4 ""))]
12195 "TARGET_POWER && reload_completed"
12196 [(set (match_dup 4)
12197 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
12200 (compare:CC (match_dup 4)
12205 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12207 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12208 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12209 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12211 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12212 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12215 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12217 [(set_attr "type" "compare")
12218 (set_attr "length" "12,16")])
12221 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12223 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12224 (match_operand:SI 2 "reg_or_short_operand" ""))
12225 (match_operand:SI 3 "gpc_reg_operand" ""))
12227 (set (match_operand:SI 0 "gpc_reg_operand" "")
12228 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12229 "TARGET_POWER && reload_completed"
12230 [(set (match_dup 0)
12231 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12233 (compare:CC (match_dup 0)
12238 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12239 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12240 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12242 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
12243 [(set_attr "length" "12")])
12245 (define_insn "*geu<mode>"
12246 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12247 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12248 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12251 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12252 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12253 [(set_attr "type" "three")
12254 (set_attr "length" "12")])
12256 (define_insn "*geu<mode>_compare"
12257 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12259 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12260 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12262 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12263 (geu:P (match_dup 1) (match_dup 2)))]
12266 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12267 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12270 [(set_attr "type" "compare")
12271 (set_attr "length" "12,12,16,16")])
12274 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12276 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
12277 (match_operand:P 2 "reg_or_neg_short_operand" ""))
12279 (set (match_operand:P 0 "gpc_reg_operand" "")
12280 (geu:P (match_dup 1) (match_dup 2)))]
12282 [(set (match_dup 0)
12283 (geu:P (match_dup 1) (match_dup 2)))
12285 (compare:CC (match_dup 0)
12289 (define_insn "*plus_geu<mode>"
12290 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12291 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12292 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12293 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12296 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
12297 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
12298 [(set_attr "type" "two")
12299 (set_attr "length" "8")])
12302 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12304 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12305 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12306 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12308 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12311 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
12312 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
12315 [(set_attr "type" "compare")
12316 (set_attr "length" "8,8,12,12")])
12319 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12321 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12322 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12323 (match_operand:SI 3 "gpc_reg_operand" ""))
12325 (clobber (match_scratch:SI 4 ""))]
12326 "TARGET_32BIT && reload_completed"
12327 [(set (match_dup 4)
12328 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12331 (compare:CC (match_dup 4)
12336 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12338 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12339 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12340 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12342 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12343 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12346 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
12347 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
12350 [(set_attr "type" "compare")
12351 (set_attr "length" "8,8,12,12")])
12354 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12356 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12357 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12358 (match_operand:SI 3 "gpc_reg_operand" ""))
12360 (set (match_operand:SI 0 "gpc_reg_operand" "")
12361 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12362 "TARGET_32BIT && reload_completed"
12363 [(set (match_dup 0)
12364 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12366 (compare:CC (match_dup 0)
12370 (define_insn "*neg_geu<mode>"
12371 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12372 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12373 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
12376 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
12377 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
12378 [(set_attr "type" "three")
12379 (set_attr "length" "12")])
12381 (define_insn "*and_neg_geu<mode>"
12382 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12384 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12385 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
12386 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12389 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
12390 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12391 [(set_attr "type" "three")
12392 (set_attr "length" "12")])
12395 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12398 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12399 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12400 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12402 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12405 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12406 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12409 [(set_attr "type" "compare")
12410 (set_attr "length" "12,12,16,16")])
12413 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12416 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12417 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12418 (match_operand:SI 3 "gpc_reg_operand" ""))
12420 (clobber (match_scratch:SI 4 ""))]
12421 "TARGET_32BIT && reload_completed"
12422 [(set (match_dup 4)
12423 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12426 (compare:CC (match_dup 4)
12431 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12434 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12435 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12436 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12438 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12439 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12442 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12443 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12446 [(set_attr "type" "compare")
12447 (set_attr "length" "12,12,16,16")])
12450 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12453 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12454 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12455 (match_operand:SI 3 "gpc_reg_operand" ""))
12457 (set (match_operand:SI 0 "gpc_reg_operand" "")
12458 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12459 "TARGET_32BIT && reload_completed"
12460 [(set (match_dup 0)
12461 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
12463 (compare:CC (match_dup 0)
12468 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12469 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12470 (match_operand:SI 2 "reg_or_short_operand" "r")))]
12472 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12473 [(set_attr "length" "12")])
12476 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12478 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12479 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12481 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12482 (gt:SI (match_dup 1) (match_dup 2)))]
12485 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12487 [(set_attr "type" "delayed_compare")
12488 (set_attr "length" "12,16")])
12491 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12493 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12494 (match_operand:SI 2 "reg_or_short_operand" ""))
12496 (set (match_operand:SI 0 "gpc_reg_operand" "")
12497 (gt:SI (match_dup 1) (match_dup 2)))]
12498 "TARGET_POWER && reload_completed"
12499 [(set (match_dup 0)
12500 (gt:SI (match_dup 1) (match_dup 2)))
12502 (compare:CC (match_dup 0)
12506 (define_insn "*plus_gt0<mode>"
12507 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12508 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
12510 (match_operand:P 2 "gpc_reg_operand" "r")))]
12512 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
12513 [(set_attr "type" "three")
12514 (set_attr "length" "12")])
12517 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12519 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12521 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12523 (clobber (match_scratch:SI 3 "=&r,&r"))]
12526 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
12528 [(set_attr "type" "compare")
12529 (set_attr "length" "12,16")])
12532 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12534 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12536 (match_operand:SI 2 "gpc_reg_operand" ""))
12538 (clobber (match_scratch:SI 3 ""))]
12539 "TARGET_32BIT && reload_completed"
12540 [(set (match_dup 3)
12541 (plus:SI (gt:SI (match_dup 1) (const_int 0))
12544 (compare:CC (match_dup 3)
12549 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12551 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12553 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12555 (clobber (match_scratch:DI 3 "=&r,&r"))]
12558 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
12560 [(set_attr "type" "compare")
12561 (set_attr "length" "12,16")])
12564 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12566 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12568 (match_operand:DI 2 "gpc_reg_operand" ""))
12570 (clobber (match_scratch:DI 3 ""))]
12571 "TARGET_64BIT && reload_completed"
12572 [(set (match_dup 3)
12573 (plus:DI (gt:DI (match_dup 1) (const_int 0))
12576 (compare:CC (match_dup 3)
12581 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12583 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12585 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12587 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12588 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
12591 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
12593 [(set_attr "type" "compare")
12594 (set_attr "length" "12,16")])
12597 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12599 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12601 (match_operand:SI 2 "gpc_reg_operand" ""))
12603 (set (match_operand:SI 0 "gpc_reg_operand" "")
12604 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
12605 "TARGET_32BIT && reload_completed"
12606 [(set (match_dup 0)
12607 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
12609 (compare:CC (match_dup 0)
12614 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12616 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12618 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12620 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
12621 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
12624 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
12626 [(set_attr "type" "compare")
12627 (set_attr "length" "12,16")])
12630 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12632 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12634 (match_operand:DI 2 "gpc_reg_operand" ""))
12636 (set (match_operand:DI 0 "gpc_reg_operand" "")
12637 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
12638 "TARGET_64BIT && reload_completed"
12639 [(set (match_dup 0)
12640 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
12642 (compare:CC (match_dup 0)
12647 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12648 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12649 (match_operand:SI 2 "reg_or_short_operand" "r"))
12650 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12652 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12653 [(set_attr "length" "12")])
12656 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12658 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12659 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12660 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12662 (clobber (match_scratch:SI 4 "=&r,&r"))]
12665 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12667 [(set_attr "type" "compare")
12668 (set_attr "length" "12,16")])
12671 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12673 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12674 (match_operand:SI 2 "reg_or_short_operand" ""))
12675 (match_operand:SI 3 "gpc_reg_operand" ""))
12677 (clobber (match_scratch:SI 4 ""))]
12678 "TARGET_POWER && reload_completed"
12679 [(set (match_dup 4)
12680 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12682 (compare:CC (match_dup 4)
12687 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12689 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12690 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12691 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12693 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12694 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12697 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12699 [(set_attr "type" "compare")
12700 (set_attr "length" "12,16")])
12703 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12705 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12706 (match_operand:SI 2 "reg_or_short_operand" ""))
12707 (match_operand:SI 3 "gpc_reg_operand" ""))
12709 (set (match_operand:SI 0 "gpc_reg_operand" "")
12710 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12711 "TARGET_POWER && reload_completed"
12712 [(set (match_dup 0)
12713 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12715 (compare:CC (match_dup 0)
12720 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12721 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12722 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
12724 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12725 [(set_attr "length" "12")])
12727 (define_insn_and_split "*gtu<mode>"
12728 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12729 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
12730 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12734 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12735 (set (match_dup 0) (neg:P (match_dup 0)))]
12738 (define_insn_and_split "*gtu<mode>_compare"
12739 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12741 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12742 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12744 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12745 (gtu:P (match_dup 1) (match_dup 2)))]
12749 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12750 (parallel [(set (match_dup 3)
12751 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12752 (set (match_dup 0) (neg:P (match_dup 0)))])]
12755 (define_insn_and_split "*plus_gtu<mode>"
12756 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12757 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
12758 (match_operand:P 2 "reg_or_short_operand" "rI"))
12759 (match_operand:P 3 "reg_or_short_operand" "rI")))]
12762 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12763 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12764 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
12767 (define_insn_and_split "*plus_gtu<mode>_compare"
12768 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12770 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12771 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
12772 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
12774 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12775 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
12778 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12779 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12780 (parallel [(set (match_dup 4)
12781 (compare:CC (minus:P (match_dup 3) (match_dup 0))
12783 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
12786 (define_insn "*neg_gtu<mode>"
12787 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12788 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
12789 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12791 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
12792 [(set_attr "type" "two")
12793 (set_attr "length" "8")])
12796 ;; Define both directions of branch and return. If we need a reload
12797 ;; register, we'd rather use CR0 since it is much easier to copy a
12798 ;; register CC value to there.
12802 (if_then_else (match_operator 1 "branch_comparison_operator"
12804 "cc_reg_operand" "y")
12806 (label_ref (match_operand 0 "" ""))
12811 return output_cbranch (operands[1], \"%l0\", 0, insn);
12813 [(set_attr "type" "branch")])
12817 (if_then_else (match_operator 0 "branch_comparison_operator"
12819 "cc_reg_operand" "y")
12826 return output_cbranch (operands[0], NULL, 0, insn);
12828 [(set_attr "type" "jmpreg")
12829 (set_attr "length" "4")])
12833 (if_then_else (match_operator 1 "branch_comparison_operator"
12835 "cc_reg_operand" "y")
12838 (label_ref (match_operand 0 "" ""))))]
12842 return output_cbranch (operands[1], \"%l0\", 1, insn);
12844 [(set_attr "type" "branch")])
12848 (if_then_else (match_operator 0 "branch_comparison_operator"
12850 "cc_reg_operand" "y")
12857 return output_cbranch (operands[0], NULL, 1, insn);
12859 [(set_attr "type" "jmpreg")
12860 (set_attr "length" "4")])
12862 ;; Logic on condition register values.
12864 ; This pattern matches things like
12865 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
12866 ; (eq:SI (reg:CCFP 68) (const_int 0)))
12868 ; which are generated by the branch logic.
12869 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
12871 (define_insn "*cceq_ior_compare"
12872 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
12873 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
12874 [(match_operator:SI 2
12875 "branch_positive_comparison_operator"
12877 "cc_reg_operand" "y,y")
12879 (match_operator:SI 4
12880 "branch_positive_comparison_operator"
12882 "cc_reg_operand" "0,y")
12886 "cr%q1 %E0,%j2,%j4"
12887 [(set_attr "type" "cr_logical,delayed_cr")])
12889 ; Why is the constant -1 here, but 1 in the previous pattern?
12890 ; Because ~1 has all but the low bit set.
12892 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
12893 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
12894 [(not:SI (match_operator:SI 2
12895 "branch_positive_comparison_operator"
12897 "cc_reg_operand" "y,y")
12899 (match_operator:SI 4
12900 "branch_positive_comparison_operator"
12902 "cc_reg_operand" "0,y")
12906 "cr%q1 %E0,%j2,%j4"
12907 [(set_attr "type" "cr_logical,delayed_cr")])
12909 (define_insn "*cceq_rev_compare"
12910 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
12911 (compare:CCEQ (match_operator:SI 1
12912 "branch_positive_comparison_operator"
12914 "cc_reg_operand" "0,y")
12918 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
12919 [(set_attr "type" "cr_logical,delayed_cr")])
12921 ;; If we are comparing the result of two comparisons, this can be done
12922 ;; using creqv or crxor.
12924 (define_insn_and_split ""
12925 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
12926 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
12927 [(match_operand 2 "cc_reg_operand" "y")
12929 (match_operator 3 "branch_comparison_operator"
12930 [(match_operand 4 "cc_reg_operand" "y")
12935 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
12939 int positive_1, positive_2;
12941 positive_1 = branch_positive_comparison_operator (operands[1],
12942 GET_MODE (operands[1]));
12943 positive_2 = branch_positive_comparison_operator (operands[3],
12944 GET_MODE (operands[3]));
12947 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
12948 GET_CODE (operands[1])),
12950 operands[2], const0_rtx);
12951 else if (GET_MODE (operands[1]) != SImode)
12952 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
12953 operands[2], const0_rtx);
12956 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
12957 GET_CODE (operands[3])),
12959 operands[4], const0_rtx);
12960 else if (GET_MODE (operands[3]) != SImode)
12961 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
12962 operands[4], const0_rtx);
12964 if (positive_1 == positive_2)
12966 operands[1] = gen_rtx_NOT (SImode, operands[1]);
12967 operands[5] = constm1_rtx;
12971 operands[5] = const1_rtx;
12975 ;; Unconditional branch and return.
12977 (define_insn "jump"
12979 (label_ref (match_operand 0 "" "")))]
12982 [(set_attr "type" "branch")])
12984 (define_insn "return"
12988 [(set_attr "type" "jmpreg")])
12990 (define_expand "indirect_jump"
12991 [(set (pc) (match_operand 0 "register_operand" ""))])
12993 (define_insn "*indirect_jump<mode>"
12994 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
12999 [(set_attr "type" "jmpreg")])
13001 ;; Table jump for switch statements:
13002 (define_expand "tablejump"
13003 [(use (match_operand 0 "" ""))
13004 (use (label_ref (match_operand 1 "" "")))]
13009 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13011 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13015 (define_expand "tablejumpsi"
13016 [(set (match_dup 3)
13017 (plus:SI (match_operand:SI 0 "" "")
13019 (parallel [(set (pc) (match_dup 3))
13020 (use (label_ref (match_operand 1 "" "")))])]
13023 { operands[0] = force_reg (SImode, operands[0]);
13024 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13025 operands[3] = gen_reg_rtx (SImode);
13028 (define_expand "tablejumpdi"
13029 [(set (match_dup 4)
13030 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
13032 (plus:DI (match_dup 4)
13034 (parallel [(set (pc) (match_dup 3))
13035 (use (label_ref (match_operand 1 "" "")))])]
13038 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13039 operands[3] = gen_reg_rtx (DImode);
13040 operands[4] = gen_reg_rtx (DImode);
13043 (define_insn "*tablejump<mode>_internal1"
13045 (match_operand:P 0 "register_operand" "c,*l"))
13046 (use (label_ref (match_operand 1 "" "")))]
13051 [(set_attr "type" "jmpreg")])
13056 "{cror 0,0,0|nop}")
13058 ;; Define the subtract-one-and-jump insns, starting with the template
13059 ;; so loop.c knows what to generate.
13061 (define_expand "doloop_end"
13062 [(use (match_operand 0 "" "")) ; loop pseudo
13063 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13064 (use (match_operand 2 "" "")) ; max iterations
13065 (use (match_operand 3 "" "")) ; loop level
13066 (use (match_operand 4 "" ""))] ; label
13070 /* Only use this on innermost loops. */
13071 if (INTVAL (operands[3]) > 1)
13075 if (GET_MODE (operands[0]) != DImode)
13077 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13081 if (GET_MODE (operands[0]) != SImode)
13083 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13088 (define_expand "ctr<mode>"
13089 [(parallel [(set (pc)
13090 (if_then_else (ne (match_operand:P 0 "register_operand" "")
13092 (label_ref (match_operand 1 "" ""))
13095 (plus:P (match_dup 0)
13097 (clobber (match_scratch:CC 2 ""))
13098 (clobber (match_scratch:P 3 ""))])]
13102 ;; We need to be able to do this for any operand, including MEM, or we
13103 ;; will cause reload to blow up since we don't allow output reloads on
13105 ;; For the length attribute to be calculated correctly, the
13106 ;; label MUST be operand 0.
13108 (define_insn "*ctr<mode>_internal1"
13110 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13112 (label_ref (match_operand 0 "" ""))
13114 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13115 (plus:P (match_dup 1)
13117 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13118 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13122 if (which_alternative != 0)
13124 else if (get_attr_length (insn) == 4)
13125 return \"{bdn|bdnz} %l0\";
13127 return \"bdz $+8\;b %l0\";
13129 [(set_attr "type" "branch")
13130 (set_attr "length" "*,12,16,16")])
13132 (define_insn "*ctr<mode>_internal2"
13134 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13137 (label_ref (match_operand 0 "" ""))))
13138 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13139 (plus:P (match_dup 1)
13141 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13142 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13146 if (which_alternative != 0)
13148 else if (get_attr_length (insn) == 4)
13149 return \"bdz %l0\";
13151 return \"{bdn|bdnz} $+8\;b %l0\";
13153 [(set_attr "type" "branch")
13154 (set_attr "length" "*,12,16,16")])
13156 ;; Similar but use EQ
13158 (define_insn "*ctr<mode>_internal5"
13160 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13162 (label_ref (match_operand 0 "" ""))
13164 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13165 (plus:P (match_dup 1)
13167 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13168 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13172 if (which_alternative != 0)
13174 else if (get_attr_length (insn) == 4)
13175 return \"bdz %l0\";
13177 return \"{bdn|bdnz} $+8\;b %l0\";
13179 [(set_attr "type" "branch")
13180 (set_attr "length" "*,12,16,16")])
13182 (define_insn "*ctr<mode>_internal6"
13184 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13187 (label_ref (match_operand 0 "" ""))))
13188 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13189 (plus:P (match_dup 1)
13191 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13192 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13196 if (which_alternative != 0)
13198 else if (get_attr_length (insn) == 4)
13199 return \"{bdn|bdnz} %l0\";
13201 return \"bdz $+8\;b %l0\";
13203 [(set_attr "type" "branch")
13204 (set_attr "length" "*,12,16,16")])
13206 ;; Now the splitters if we could not allocate the CTR register
13210 (if_then_else (match_operator 2 "comparison_operator"
13211 [(match_operand:P 1 "gpc_reg_operand" "")
13213 (match_operand 5 "" "")
13214 (match_operand 6 "" "")))
13215 (set (match_operand:P 0 "gpc_reg_operand" "")
13216 (plus:P (match_dup 1) (const_int -1)))
13217 (clobber (match_scratch:CC 3 ""))
13218 (clobber (match_scratch:P 4 ""))]
13220 [(parallel [(set (match_dup 3)
13221 (compare:CC (plus:P (match_dup 1)
13225 (plus:P (match_dup 1)
13227 (set (pc) (if_then_else (match_dup 7)
13231 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13232 operands[3], const0_rtx); }")
13236 (if_then_else (match_operator 2 "comparison_operator"
13237 [(match_operand:P 1 "gpc_reg_operand" "")
13239 (match_operand 5 "" "")
13240 (match_operand 6 "" "")))
13241 (set (match_operand:P 0 "nonimmediate_operand" "")
13242 (plus:P (match_dup 1) (const_int -1)))
13243 (clobber (match_scratch:CC 3 ""))
13244 (clobber (match_scratch:P 4 ""))]
13245 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
13246 [(parallel [(set (match_dup 3)
13247 (compare:CC (plus:P (match_dup 1)
13251 (plus:P (match_dup 1)
13255 (set (pc) (if_then_else (match_dup 7)
13259 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13260 operands[3], const0_rtx); }")
13262 (define_insn "trap"
13263 [(trap_if (const_int 1) (const_int 0))]
13267 (define_expand "conditional_trap"
13268 [(trap_if (match_operator 0 "trap_comparison_operator"
13269 [(match_dup 2) (match_dup 3)])
13270 (match_operand 1 "const_int_operand" ""))]
13272 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
13273 operands[2] = rs6000_compare_op0;
13274 operands[3] = rs6000_compare_op1;")
13277 [(trap_if (match_operator 0 "trap_comparison_operator"
13278 [(match_operand:GPR 1 "register_operand" "r")
13279 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
13282 "{t|t<wd>}%V0%I2 %1,%2")
13284 ;; Insns related to generating the function prologue and epilogue.
13286 (define_expand "prologue"
13287 [(use (const_int 0))]
13288 "TARGET_SCHED_PROLOG"
13291 rs6000_emit_prologue ();
13295 (define_insn "*movesi_from_cr_one"
13296 [(match_parallel 0 "mfcr_operation"
13297 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13298 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
13299 (match_operand 3 "immediate_operand" "n")]
13300 UNSPEC_MOVESI_FROM_CR))])]
13306 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13308 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13309 operands[4] = GEN_INT (mask);
13310 output_asm_insn (\"mfcr %1,%4\", operands);
13314 [(set_attr "type" "mfcrf")])
13316 (define_insn "movesi_from_cr"
13317 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13318 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
13319 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
13320 UNSPEC_MOVESI_FROM_CR))]
13323 [(set_attr "type" "mfcr")])
13325 (define_insn "*stmw"
13326 [(match_parallel 0 "stmw_operation"
13327 [(set (match_operand:SI 1 "memory_operand" "=m")
13328 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13331 [(set_attr "type" "store_ux")])
13333 (define_insn "*save_fpregs_<mode>"
13334 [(match_parallel 0 "any_parallel_operand"
13335 [(clobber (match_operand:P 1 "register_operand" "=l"))
13336 (use (match_operand:P 2 "call_operand" "s"))
13337 (set (match_operand:DF 3 "memory_operand" "=m")
13338 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
13341 [(set_attr "type" "branch")
13342 (set_attr "length" "4")])
13344 ; These are to explain that changes to the stack pointer should
13345 ; not be moved over stores to stack memory.
13346 (define_insn "stack_tie"
13347 [(set (match_operand:BLK 0 "memory_operand" "+m")
13348 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
13351 [(set_attr "length" "0")])
13354 (define_expand "epilogue"
13355 [(use (const_int 0))]
13356 "TARGET_SCHED_PROLOG"
13359 rs6000_emit_epilogue (FALSE);
13363 ; On some processors, doing the mtcrf one CC register at a time is
13364 ; faster (like on the 604e). On others, doing them all at once is
13365 ; faster; for instance, on the 601 and 750.
13367 (define_expand "movsi_to_cr_one"
13368 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13369 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13370 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
13372 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
13374 (define_insn "*movsi_to_cr"
13375 [(match_parallel 0 "mtcrf_operation"
13376 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
13377 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
13378 (match_operand 3 "immediate_operand" "n")]
13379 UNSPEC_MOVESI_TO_CR))])]
13385 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13386 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13387 operands[4] = GEN_INT (mask);
13388 return \"mtcrf %4,%2\";
13390 [(set_attr "type" "mtcr")])
13392 (define_insn "*mtcrfsi"
13393 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13394 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13395 (match_operand 2 "immediate_operand" "n")]
13396 UNSPEC_MOVESI_TO_CR))]
13397 "GET_CODE (operands[0]) == REG
13398 && CR_REGNO_P (REGNO (operands[0]))
13399 && GET_CODE (operands[2]) == CONST_INT
13400 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
13402 [(set_attr "type" "mtcr")])
13404 ; The load-multiple instructions have similar properties.
13405 ; Note that "load_multiple" is a name known to the machine-independent
13406 ; code that actually corresponds to the PowerPC load-string.
13408 (define_insn "*lmw"
13409 [(match_parallel 0 "lmw_operation"
13410 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13411 (match_operand:SI 2 "memory_operand" "m"))])]
13414 [(set_attr "type" "load_ux")])
13416 (define_insn "*return_internal_<mode>"
13418 (use (match_operand:P 0 "register_operand" "lc"))]
13421 [(set_attr "type" "jmpreg")])
13423 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
13424 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
13426 (define_insn "*return_and_restore_fpregs_<mode>"
13427 [(match_parallel 0 "any_parallel_operand"
13429 (use (match_operand:P 1 "register_operand" "l"))
13430 (use (match_operand:P 2 "call_operand" "s"))
13431 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
13432 (match_operand:DF 4 "memory_operand" "m"))])]
13436 ; This is used in compiling the unwind routines.
13437 (define_expand "eh_return"
13438 [(use (match_operand 0 "general_operand" ""))]
13443 emit_insn (gen_eh_set_lr_si (operands[0]));
13445 emit_insn (gen_eh_set_lr_di (operands[0]));
13449 ; We can't expand this before we know where the link register is stored.
13450 (define_insn "eh_set_lr_<mode>"
13451 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
13453 (clobber (match_scratch:P 1 "=&b"))]
13458 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
13459 (clobber (match_scratch 1 ""))]
13464 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
13468 (define_insn "prefetch"
13469 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
13470 (match_operand:SI 1 "const_int_operand" "n")
13471 (match_operand:SI 2 "const_int_operand" "n"))]
13475 if (GET_CODE (operands[0]) == REG)
13476 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
13477 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
13479 [(set_attr "type" "load")])
13482 (include "sync.md")
13483 (include "altivec.md")