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rs6000-protos.h (rs6000_output_addr_const_extra): Declare.
[thirdparty/gcc.git] / gcc / config / rs6000 / rs6000.md
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6
7 ;; This file is part of GCC.
8
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 3, or (at your
12 ;; option) any later version.
13
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
18
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
22
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
24
25 ;;
26 ;; REGNOS
27 ;;
28
29 (define_constants
30 [(MQ_REGNO 64)
31 (LR_REGNO 65)
32 (CTR_REGNO 66)
33 (CR0_REGNO 68)
34 (CR1_REGNO 69)
35 (CR2_REGNO 70)
36 (CR3_REGNO 71)
37 (CR4_REGNO 72)
38 (CR5_REGNO 73)
39 (CR6_REGNO 74)
40 (CR7_REGNO 75)
41 (MAX_CR_REGNO 75)
42 (XER_REGNO 76)
43 (FIRST_ALTIVEC_REGNO 77)
44 (LAST_ALTIVEC_REGNO 108)
45 (VRSAVE_REGNO 109)
46 (VSCR_REGNO 110)
47 (SPE_ACC_REGNO 111)
48 (SPEFSCR_REGNO 112)
49 (SFP_REGNO 113)
50 ])
51
52 ;;
53 ;; UNSPEC usage
54 ;;
55
56 (define_constants
57 [(UNSPEC_FRSP 0) ; frsp for POWER machines
58 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
59 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
60 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
61 (UNSPEC_MOVSI_GOT 8)
62 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
63 (UNSPEC_FCTIWZ 10)
64 (UNSPEC_FRIM 11)
65 (UNSPEC_FRIN 12)
66 (UNSPEC_FRIP 13)
67 (UNSPEC_FRIZ 14)
68 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
69 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
70 (UNSPEC_TLSGD 17)
71 (UNSPEC_TLSLD 18)
72 (UNSPEC_MOVESI_FROM_CR 19)
73 (UNSPEC_MOVESI_TO_CR 20)
74 (UNSPEC_TLSDTPREL 21)
75 (UNSPEC_TLSDTPRELHA 22)
76 (UNSPEC_TLSDTPRELLO 23)
77 (UNSPEC_TLSGOTDTPREL 24)
78 (UNSPEC_TLSTPREL 25)
79 (UNSPEC_TLSTPRELHA 26)
80 (UNSPEC_TLSTPRELLO 27)
81 (UNSPEC_TLSGOTTPREL 28)
82 (UNSPEC_TLSTLS 29)
83 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
84 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
85 (UNSPEC_STFIWX 32)
86 (UNSPEC_POPCNTB 33)
87 (UNSPEC_FRES 34)
88 (UNSPEC_SP_SET 35)
89 (UNSPEC_SP_TEST 36)
90 (UNSPEC_SYNC 37)
91 (UNSPEC_LWSYNC 38)
92 (UNSPEC_ISYNC 39)
93 (UNSPEC_SYNC_OP 40)
94 (UNSPEC_ATOMIC 41)
95 (UNSPEC_CMPXCHG 42)
96 (UNSPEC_XCHG 43)
97 (UNSPEC_AND 44)
98 (UNSPEC_DLMZB 45)
99 (UNSPEC_DLMZB_CR 46)
100 (UNSPEC_DLMZB_STRLEN 47)
101 (UNSPEC_RSQRT 48)
102 (UNSPEC_TOCREL 49)
103 ])
104
105 ;;
106 ;; UNSPEC_VOLATILE usage
107 ;;
108
109 (define_constants
110 [(UNSPECV_BLOCK 0)
111 (UNSPECV_LL 1) ; load-locked
112 (UNSPECV_SC 2) ; store-conditional
113 (UNSPECV_EH_RR 9) ; eh_reg_restore
114 ])
115 \f
116 ;; Define an insn type attribute. This is used in function unit delay
117 ;; computations.
118 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr"
119 (const_string "integer"))
120
121 ;; Length (in bytes).
122 ; '(pc)' in the following doesn't include the instruction itself; it is
123 ; calculated as if the instruction had zero size.
124 (define_attr "length" ""
125 (if_then_else (eq_attr "type" "branch")
126 (if_then_else (and (ge (minus (match_dup 0) (pc))
127 (const_int -32768))
128 (lt (minus (match_dup 0) (pc))
129 (const_int 32764)))
130 (const_int 4)
131 (const_int 8))
132 (const_int 4)))
133
134 ;; Processor type -- this attribute must exactly match the processor_type
135 ;; enumeration in rs6000.h.
136
137 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,power4,power5,power6,cell"
138 (const (symbol_ref "rs6000_cpu_attr")))
139
140
141 ;; If this instruction is microcoded on the CELL processor
142 ; The default for load and stores is conditional
143 ; The default for load extended and the recorded instructions is always microcoded
144 (define_attr "cell_micro" "not,conditional,always"
145 (if_then_else (ior (ior (eq_attr "type" "load")
146 (eq_attr "type" "store"))
147 (ior (eq_attr "type" "fpload")
148 (eq_attr "type" "fpstore")))
149 (const_string "conditional")
150 (if_then_else (ior (eq_attr "type" "load_ext")
151 (ior (eq_attr "type" "compare")
152 (eq_attr "type" "delayed_compare")))
153 (const_string "always")
154 (const_string "not"))))
155
156
157 (automata_option "ndfa")
158
159 (include "rios1.md")
160 (include "rios2.md")
161 (include "rs64.md")
162 (include "mpc.md")
163 (include "40x.md")
164 (include "440.md")
165 (include "603.md")
166 (include "6xx.md")
167 (include "7xx.md")
168 (include "7450.md")
169 (include "8540.md")
170 (include "e300c2c3.md")
171 (include "e500mc.md")
172 (include "power4.md")
173 (include "power5.md")
174 (include "power6.md")
175 (include "cell.md")
176
177 (include "predicates.md")
178 (include "constraints.md")
179
180 (include "darwin.md")
181
182 \f
183 ;; Mode iterators
184
185 ; This mode iterator allows :GPR to be used to indicate the allowable size
186 ; of whole values in GPRs.
187 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
188
189 ; Any supported integer mode.
190 (define_mode_iterator INT [QI HI SI DI TI])
191
192 ; Any supported integer mode that fits in one register.
193 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
194
195 ; extend modes for DImode
196 (define_mode_iterator QHSI [QI HI SI])
197
198 ; SImode or DImode, even if DImode doesn't fit in GPRs.
199 (define_mode_iterator SDI [SI DI])
200
201 ; The size of a pointer. Also, the size of the value that a record-condition
202 ; (one with a '.') will compare.
203 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
204
205 ; Any hardware-supported floating-point mode
206 (define_mode_iterator FP [
207 (SF "TARGET_HARD_FLOAT
208 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
209 (DF "TARGET_HARD_FLOAT
210 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
211 (TF "!TARGET_IEEEQUAD
212 && TARGET_HARD_FLOAT
213 && (TARGET_FPRS || TARGET_E500_DOUBLE)
214 && TARGET_LONG_DOUBLE_128")
215 (DD "TARGET_DFP")
216 (TD "TARGET_DFP")])
217
218 ; Various instructions that come in SI and DI forms.
219 ; A generic w/d attribute, for things like cmpw/cmpd.
220 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
221
222 ; DImode bits
223 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
224
225 \f
226 ;; Start with fixed-point load and store insns. Here we put only the more
227 ;; complex forms. Basic data transfer is done later.
228
229 (define_expand "zero_extend<mode>di2"
230 [(set (match_operand:DI 0 "gpc_reg_operand" "")
231 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
232 "TARGET_POWERPC64"
233 "")
234
235 (define_insn "*zero_extend<mode>di2_internal1"
236 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
237 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
238 "TARGET_POWERPC64"
239 "@
240 l<wd>z%U1%X1 %0,%1
241 rldicl %0,%1,0,<dbits>"
242 [(set_attr "type" "load,*")])
243
244 (define_insn "*zero_extend<mode>di2_internal2"
245 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
246 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
247 (const_int 0)))
248 (clobber (match_scratch:DI 2 "=r,r"))]
249 "TARGET_64BIT"
250 "@
251 rldicl. %2,%1,0,<dbits>
252 #"
253 [(set_attr "type" "compare")
254 (set_attr "length" "4,8")])
255
256 (define_split
257 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
258 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
259 (const_int 0)))
260 (clobber (match_scratch:DI 2 ""))]
261 "TARGET_POWERPC64 && reload_completed"
262 [(set (match_dup 2)
263 (zero_extend:DI (match_dup 1)))
264 (set (match_dup 0)
265 (compare:CC (match_dup 2)
266 (const_int 0)))]
267 "")
268
269 (define_insn "*zero_extend<mode>di2_internal3"
270 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
271 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
272 (const_int 0)))
273 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
274 (zero_extend:DI (match_dup 1)))]
275 "TARGET_64BIT"
276 "@
277 rldicl. %0,%1,0,<dbits>
278 #"
279 [(set_attr "type" "compare")
280 (set_attr "length" "4,8")])
281
282 (define_split
283 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
284 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
285 (const_int 0)))
286 (set (match_operand:DI 0 "gpc_reg_operand" "")
287 (zero_extend:DI (match_dup 1)))]
288 "TARGET_POWERPC64 && reload_completed"
289 [(set (match_dup 0)
290 (zero_extend:DI (match_dup 1)))
291 (set (match_dup 2)
292 (compare:CC (match_dup 0)
293 (const_int 0)))]
294 "")
295
296 (define_insn "extendqidi2"
297 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
298 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
299 "TARGET_POWERPC64"
300 "extsb %0,%1"
301 [(set_attr "type" "exts")])
302
303 (define_insn ""
304 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
305 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
306 (const_int 0)))
307 (clobber (match_scratch:DI 2 "=r,r"))]
308 "TARGET_64BIT"
309 "@
310 extsb. %2,%1
311 #"
312 [(set_attr "type" "compare")
313 (set_attr "length" "4,8")])
314
315 (define_split
316 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
317 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
318 (const_int 0)))
319 (clobber (match_scratch:DI 2 ""))]
320 "TARGET_POWERPC64 && reload_completed"
321 [(set (match_dup 2)
322 (sign_extend:DI (match_dup 1)))
323 (set (match_dup 0)
324 (compare:CC (match_dup 2)
325 (const_int 0)))]
326 "")
327
328 (define_insn ""
329 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
330 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
331 (const_int 0)))
332 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
333 (sign_extend:DI (match_dup 1)))]
334 "TARGET_64BIT"
335 "@
336 extsb. %0,%1
337 #"
338 [(set_attr "type" "compare")
339 (set_attr "length" "4,8")])
340
341 (define_split
342 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
343 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
344 (const_int 0)))
345 (set (match_operand:DI 0 "gpc_reg_operand" "")
346 (sign_extend:DI (match_dup 1)))]
347 "TARGET_POWERPC64 && reload_completed"
348 [(set (match_dup 0)
349 (sign_extend:DI (match_dup 1)))
350 (set (match_dup 2)
351 (compare:CC (match_dup 0)
352 (const_int 0)))]
353 "")
354
355 (define_expand "extendhidi2"
356 [(set (match_operand:DI 0 "gpc_reg_operand" "")
357 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
358 "TARGET_POWERPC64"
359 "")
360
361 (define_insn ""
362 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
363 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
364 "TARGET_POWERPC64"
365 "@
366 lha%U1%X1 %0,%1
367 extsh %0,%1"
368 [(set_attr "type" "load_ext,exts")])
369
370 (define_insn ""
371 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
372 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
373 (const_int 0)))
374 (clobber (match_scratch:DI 2 "=r,r"))]
375 "TARGET_64BIT"
376 "@
377 extsh. %2,%1
378 #"
379 [(set_attr "type" "compare")
380 (set_attr "length" "4,8")])
381
382 (define_split
383 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
384 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
385 (const_int 0)))
386 (clobber (match_scratch:DI 2 ""))]
387 "TARGET_POWERPC64 && reload_completed"
388 [(set (match_dup 2)
389 (sign_extend:DI (match_dup 1)))
390 (set (match_dup 0)
391 (compare:CC (match_dup 2)
392 (const_int 0)))]
393 "")
394
395 (define_insn ""
396 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
397 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
398 (const_int 0)))
399 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
400 (sign_extend:DI (match_dup 1)))]
401 "TARGET_64BIT"
402 "@
403 extsh. %0,%1
404 #"
405 [(set_attr "type" "compare")
406 (set_attr "length" "4,8")])
407
408 (define_split
409 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
410 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
411 (const_int 0)))
412 (set (match_operand:DI 0 "gpc_reg_operand" "")
413 (sign_extend:DI (match_dup 1)))]
414 "TARGET_POWERPC64 && reload_completed"
415 [(set (match_dup 0)
416 (sign_extend:DI (match_dup 1)))
417 (set (match_dup 2)
418 (compare:CC (match_dup 0)
419 (const_int 0)))]
420 "")
421
422 (define_expand "extendsidi2"
423 [(set (match_operand:DI 0 "gpc_reg_operand" "")
424 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
425 "TARGET_POWERPC64"
426 "")
427
428 (define_insn ""
429 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
430 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
431 "TARGET_POWERPC64"
432 "@
433 lwa%U1%X1 %0,%1
434 extsw %0,%1"
435 [(set_attr "type" "load_ext,exts")])
436
437 (define_insn ""
438 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
439 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
440 (const_int 0)))
441 (clobber (match_scratch:DI 2 "=r,r"))]
442 "TARGET_64BIT"
443 "@
444 extsw. %2,%1
445 #"
446 [(set_attr "type" "compare")
447 (set_attr "length" "4,8")])
448
449 (define_split
450 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
451 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
452 (const_int 0)))
453 (clobber (match_scratch:DI 2 ""))]
454 "TARGET_POWERPC64 && reload_completed"
455 [(set (match_dup 2)
456 (sign_extend:DI (match_dup 1)))
457 (set (match_dup 0)
458 (compare:CC (match_dup 2)
459 (const_int 0)))]
460 "")
461
462 (define_insn ""
463 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
464 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
465 (const_int 0)))
466 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
467 (sign_extend:DI (match_dup 1)))]
468 "TARGET_64BIT"
469 "@
470 extsw. %0,%1
471 #"
472 [(set_attr "type" "compare")
473 (set_attr "length" "4,8")])
474
475 (define_split
476 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
477 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
478 (const_int 0)))
479 (set (match_operand:DI 0 "gpc_reg_operand" "")
480 (sign_extend:DI (match_dup 1)))]
481 "TARGET_POWERPC64 && reload_completed"
482 [(set (match_dup 0)
483 (sign_extend:DI (match_dup 1)))
484 (set (match_dup 2)
485 (compare:CC (match_dup 0)
486 (const_int 0)))]
487 "")
488
489 (define_expand "zero_extendqisi2"
490 [(set (match_operand:SI 0 "gpc_reg_operand" "")
491 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
492 ""
493 "")
494
495 (define_insn ""
496 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
497 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
498 ""
499 "@
500 lbz%U1%X1 %0,%1
501 {rlinm|rlwinm} %0,%1,0,0xff"
502 [(set_attr "type" "load,*")])
503
504 (define_insn ""
505 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
506 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
507 (const_int 0)))
508 (clobber (match_scratch:SI 2 "=r,r"))]
509 ""
510 "@
511 {andil.|andi.} %2,%1,0xff
512 #"
513 [(set_attr "type" "compare")
514 (set_attr "length" "4,8")])
515
516 (define_split
517 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
518 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
519 (const_int 0)))
520 (clobber (match_scratch:SI 2 ""))]
521 "reload_completed"
522 [(set (match_dup 2)
523 (zero_extend:SI (match_dup 1)))
524 (set (match_dup 0)
525 (compare:CC (match_dup 2)
526 (const_int 0)))]
527 "")
528
529 (define_insn ""
530 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
531 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
532 (const_int 0)))
533 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
534 (zero_extend:SI (match_dup 1)))]
535 ""
536 "@
537 {andil.|andi.} %0,%1,0xff
538 #"
539 [(set_attr "type" "compare")
540 (set_attr "length" "4,8")])
541
542 (define_split
543 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
544 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
545 (const_int 0)))
546 (set (match_operand:SI 0 "gpc_reg_operand" "")
547 (zero_extend:SI (match_dup 1)))]
548 "reload_completed"
549 [(set (match_dup 0)
550 (zero_extend:SI (match_dup 1)))
551 (set (match_dup 2)
552 (compare:CC (match_dup 0)
553 (const_int 0)))]
554 "")
555
556 (define_expand "extendqisi2"
557 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
558 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
559 ""
560 "
561 {
562 if (TARGET_POWERPC)
563 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
564 else if (TARGET_POWER)
565 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
566 else
567 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
568 DONE;
569 }")
570
571 (define_insn "extendqisi2_ppc"
572 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
573 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
574 "TARGET_POWERPC"
575 "extsb %0,%1"
576 [(set_attr "type" "exts")])
577
578 (define_insn ""
579 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
580 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
581 (const_int 0)))
582 (clobber (match_scratch:SI 2 "=r,r"))]
583 "TARGET_POWERPC"
584 "@
585 extsb. %2,%1
586 #"
587 [(set_attr "type" "compare")
588 (set_attr "length" "4,8")])
589
590 (define_split
591 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
592 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
593 (const_int 0)))
594 (clobber (match_scratch:SI 2 ""))]
595 "TARGET_POWERPC && reload_completed"
596 [(set (match_dup 2)
597 (sign_extend:SI (match_dup 1)))
598 (set (match_dup 0)
599 (compare:CC (match_dup 2)
600 (const_int 0)))]
601 "")
602
603 (define_insn ""
604 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
605 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
606 (const_int 0)))
607 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
608 (sign_extend:SI (match_dup 1)))]
609 "TARGET_POWERPC"
610 "@
611 extsb. %0,%1
612 #"
613 [(set_attr "type" "compare")
614 (set_attr "length" "4,8")])
615
616 (define_split
617 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
618 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
619 (const_int 0)))
620 (set (match_operand:SI 0 "gpc_reg_operand" "")
621 (sign_extend:SI (match_dup 1)))]
622 "TARGET_POWERPC && reload_completed"
623 [(set (match_dup 0)
624 (sign_extend:SI (match_dup 1)))
625 (set (match_dup 2)
626 (compare:CC (match_dup 0)
627 (const_int 0)))]
628 "")
629
630 (define_expand "extendqisi2_power"
631 [(parallel [(set (match_dup 2)
632 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
633 (const_int 24)))
634 (clobber (scratch:SI))])
635 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
636 (ashiftrt:SI (match_dup 2)
637 (const_int 24)))
638 (clobber (scratch:SI))])]
639 "TARGET_POWER"
640 "
641 { operands[1] = gen_lowpart (SImode, operands[1]);
642 operands[2] = gen_reg_rtx (SImode); }")
643
644 (define_expand "extendqisi2_no_power"
645 [(set (match_dup 2)
646 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
647 (const_int 24)))
648 (set (match_operand:SI 0 "gpc_reg_operand" "")
649 (ashiftrt:SI (match_dup 2)
650 (const_int 24)))]
651 "! TARGET_POWER && ! TARGET_POWERPC"
652 "
653 { operands[1] = gen_lowpart (SImode, operands[1]);
654 operands[2] = gen_reg_rtx (SImode); }")
655
656 (define_expand "zero_extendqihi2"
657 [(set (match_operand:HI 0 "gpc_reg_operand" "")
658 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
659 ""
660 "")
661
662 (define_insn ""
663 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
664 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
665 ""
666 "@
667 lbz%U1%X1 %0,%1
668 {rlinm|rlwinm} %0,%1,0,0xff"
669 [(set_attr "type" "load,*")])
670
671 (define_insn ""
672 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
673 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
674 (const_int 0)))
675 (clobber (match_scratch:HI 2 "=r,r"))]
676 ""
677 "@
678 {andil.|andi.} %2,%1,0xff
679 #"
680 [(set_attr "type" "compare")
681 (set_attr "length" "4,8")])
682
683 (define_split
684 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
685 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
686 (const_int 0)))
687 (clobber (match_scratch:HI 2 ""))]
688 "reload_completed"
689 [(set (match_dup 2)
690 (zero_extend:HI (match_dup 1)))
691 (set (match_dup 0)
692 (compare:CC (match_dup 2)
693 (const_int 0)))]
694 "")
695
696 (define_insn ""
697 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
698 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
699 (const_int 0)))
700 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
701 (zero_extend:HI (match_dup 1)))]
702 ""
703 "@
704 {andil.|andi.} %0,%1,0xff
705 #"
706 [(set_attr "type" "compare")
707 (set_attr "length" "4,8")])
708
709 (define_split
710 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
711 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
712 (const_int 0)))
713 (set (match_operand:HI 0 "gpc_reg_operand" "")
714 (zero_extend:HI (match_dup 1)))]
715 "reload_completed"
716 [(set (match_dup 0)
717 (zero_extend:HI (match_dup 1)))
718 (set (match_dup 2)
719 (compare:CC (match_dup 0)
720 (const_int 0)))]
721 "")
722
723 (define_expand "extendqihi2"
724 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
725 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
726 ""
727 "
728 {
729 if (TARGET_POWERPC)
730 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
731 else if (TARGET_POWER)
732 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
733 else
734 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
735 DONE;
736 }")
737
738 (define_insn "extendqihi2_ppc"
739 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
740 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
741 "TARGET_POWERPC"
742 "extsb %0,%1"
743 [(set_attr "type" "exts")])
744
745 (define_insn ""
746 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
747 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
748 (const_int 0)))
749 (clobber (match_scratch:HI 2 "=r,r"))]
750 "TARGET_POWERPC"
751 "@
752 extsb. %2,%1
753 #"
754 [(set_attr "type" "compare")
755 (set_attr "length" "4,8")])
756
757 (define_split
758 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
759 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
760 (const_int 0)))
761 (clobber (match_scratch:HI 2 ""))]
762 "TARGET_POWERPC && reload_completed"
763 [(set (match_dup 2)
764 (sign_extend:HI (match_dup 1)))
765 (set (match_dup 0)
766 (compare:CC (match_dup 2)
767 (const_int 0)))]
768 "")
769
770 (define_insn ""
771 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
772 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
773 (const_int 0)))
774 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
775 (sign_extend:HI (match_dup 1)))]
776 "TARGET_POWERPC"
777 "@
778 extsb. %0,%1
779 #"
780 [(set_attr "type" "compare")
781 (set_attr "length" "4,8")])
782
783 (define_split
784 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
785 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
786 (const_int 0)))
787 (set (match_operand:HI 0 "gpc_reg_operand" "")
788 (sign_extend:HI (match_dup 1)))]
789 "TARGET_POWERPC && reload_completed"
790 [(set (match_dup 0)
791 (sign_extend:HI (match_dup 1)))
792 (set (match_dup 2)
793 (compare:CC (match_dup 0)
794 (const_int 0)))]
795 "")
796
797 (define_expand "extendqihi2_power"
798 [(parallel [(set (match_dup 2)
799 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
800 (const_int 24)))
801 (clobber (scratch:SI))])
802 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
803 (ashiftrt:SI (match_dup 2)
804 (const_int 24)))
805 (clobber (scratch:SI))])]
806 "TARGET_POWER"
807 "
808 { operands[0] = gen_lowpart (SImode, operands[0]);
809 operands[1] = gen_lowpart (SImode, operands[1]);
810 operands[2] = gen_reg_rtx (SImode); }")
811
812 (define_expand "extendqihi2_no_power"
813 [(set (match_dup 2)
814 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
815 (const_int 24)))
816 (set (match_operand:HI 0 "gpc_reg_operand" "")
817 (ashiftrt:SI (match_dup 2)
818 (const_int 24)))]
819 "! TARGET_POWER && ! TARGET_POWERPC"
820 "
821 { operands[0] = gen_lowpart (SImode, operands[0]);
822 operands[1] = gen_lowpart (SImode, operands[1]);
823 operands[2] = gen_reg_rtx (SImode); }")
824
825 (define_expand "zero_extendhisi2"
826 [(set (match_operand:SI 0 "gpc_reg_operand" "")
827 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
828 ""
829 "")
830
831 (define_insn ""
832 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
833 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
834 ""
835 "@
836 lhz%U1%X1 %0,%1
837 {rlinm|rlwinm} %0,%1,0,0xffff"
838 [(set_attr "type" "load,*")])
839
840 (define_insn ""
841 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
842 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
843 (const_int 0)))
844 (clobber (match_scratch:SI 2 "=r,r"))]
845 ""
846 "@
847 {andil.|andi.} %2,%1,0xffff
848 #"
849 [(set_attr "type" "compare")
850 (set_attr "length" "4,8")])
851
852 (define_split
853 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
854 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
855 (const_int 0)))
856 (clobber (match_scratch:SI 2 ""))]
857 "reload_completed"
858 [(set (match_dup 2)
859 (zero_extend:SI (match_dup 1)))
860 (set (match_dup 0)
861 (compare:CC (match_dup 2)
862 (const_int 0)))]
863 "")
864
865 (define_insn ""
866 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
867 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
868 (const_int 0)))
869 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
870 (zero_extend:SI (match_dup 1)))]
871 ""
872 "@
873 {andil.|andi.} %0,%1,0xffff
874 #"
875 [(set_attr "type" "compare")
876 (set_attr "length" "4,8")])
877
878 (define_split
879 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
880 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
881 (const_int 0)))
882 (set (match_operand:SI 0 "gpc_reg_operand" "")
883 (zero_extend:SI (match_dup 1)))]
884 "reload_completed"
885 [(set (match_dup 0)
886 (zero_extend:SI (match_dup 1)))
887 (set (match_dup 2)
888 (compare:CC (match_dup 0)
889 (const_int 0)))]
890 "")
891
892 (define_expand "extendhisi2"
893 [(set (match_operand:SI 0 "gpc_reg_operand" "")
894 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
895 ""
896 "")
897
898 (define_insn ""
899 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
900 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
901 ""
902 "@
903 lha%U1%X1 %0,%1
904 {exts|extsh} %0,%1"
905 [(set_attr "type" "load_ext,exts")])
906
907 (define_insn ""
908 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
909 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
910 (const_int 0)))
911 (clobber (match_scratch:SI 2 "=r,r"))]
912 ""
913 "@
914 {exts.|extsh.} %2,%1
915 #"
916 [(set_attr "type" "compare")
917 (set_attr "length" "4,8")])
918
919 (define_split
920 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
921 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
922 (const_int 0)))
923 (clobber (match_scratch:SI 2 ""))]
924 "reload_completed"
925 [(set (match_dup 2)
926 (sign_extend:SI (match_dup 1)))
927 (set (match_dup 0)
928 (compare:CC (match_dup 2)
929 (const_int 0)))]
930 "")
931
932 (define_insn ""
933 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
934 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
935 (const_int 0)))
936 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
937 (sign_extend:SI (match_dup 1)))]
938 ""
939 "@
940 {exts.|extsh.} %0,%1
941 #"
942 [(set_attr "type" "compare")
943 (set_attr "length" "4,8")])
944 \f
945 ;; IBM 405, 440 and 464 half-word multiplication operations.
946
947 (define_insn "*macchwc"
948 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
949 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
950 (match_operand:SI 2 "gpc_reg_operand" "r")
951 (const_int 16))
952 (sign_extend:SI
953 (match_operand:HI 1 "gpc_reg_operand" "r")))
954 (match_operand:SI 4 "gpc_reg_operand" "0"))
955 (const_int 0)))
956 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
957 (plus:SI (mult:SI (ashiftrt:SI
958 (match_dup 2)
959 (const_int 16))
960 (sign_extend:SI
961 (match_dup 1)))
962 (match_dup 4)))]
963 "TARGET_MULHW"
964 "macchw. %0, %1, %2"
965 [(set_attr "type" "imul3")])
966
967 (define_insn "*macchw"
968 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
969 (plus:SI (mult:SI (ashiftrt:SI
970 (match_operand:SI 2 "gpc_reg_operand" "r")
971 (const_int 16))
972 (sign_extend:SI
973 (match_operand:HI 1 "gpc_reg_operand" "r")))
974 (match_operand:SI 3 "gpc_reg_operand" "0")))]
975 "TARGET_MULHW"
976 "macchw %0, %1, %2"
977 [(set_attr "type" "imul3")])
978
979 (define_insn "*macchwuc"
980 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
981 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
982 (match_operand:SI 2 "gpc_reg_operand" "r")
983 (const_int 16))
984 (zero_extend:SI
985 (match_operand:HI 1 "gpc_reg_operand" "r")))
986 (match_operand:SI 4 "gpc_reg_operand" "0"))
987 (const_int 0)))
988 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
989 (plus:SI (mult:SI (lshiftrt:SI
990 (match_dup 2)
991 (const_int 16))
992 (zero_extend:SI
993 (match_dup 1)))
994 (match_dup 4)))]
995 "TARGET_MULHW"
996 "macchwu. %0, %1, %2"
997 [(set_attr "type" "imul3")])
998
999 (define_insn "*macchwu"
1000 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1001 (plus:SI (mult:SI (lshiftrt:SI
1002 (match_operand:SI 2 "gpc_reg_operand" "r")
1003 (const_int 16))
1004 (zero_extend:SI
1005 (match_operand:HI 1 "gpc_reg_operand" "r")))
1006 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1007 "TARGET_MULHW"
1008 "macchwu %0, %1, %2"
1009 [(set_attr "type" "imul3")])
1010
1011 (define_insn "*machhwc"
1012 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1013 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1014 (match_operand:SI 1 "gpc_reg_operand" "%r")
1015 (const_int 16))
1016 (ashiftrt:SI
1017 (match_operand:SI 2 "gpc_reg_operand" "r")
1018 (const_int 16)))
1019 (match_operand:SI 4 "gpc_reg_operand" "0"))
1020 (const_int 0)))
1021 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1022 (plus:SI (mult:SI (ashiftrt:SI
1023 (match_dup 1)
1024 (const_int 16))
1025 (ashiftrt:SI
1026 (match_dup 2)
1027 (const_int 16)))
1028 (match_dup 4)))]
1029 "TARGET_MULHW"
1030 "machhw. %0, %1, %2"
1031 [(set_attr "type" "imul3")])
1032
1033 (define_insn "*machhw"
1034 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1035 (plus:SI (mult:SI (ashiftrt:SI
1036 (match_operand:SI 1 "gpc_reg_operand" "%r")
1037 (const_int 16))
1038 (ashiftrt:SI
1039 (match_operand:SI 2 "gpc_reg_operand" "r")
1040 (const_int 16)))
1041 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1042 "TARGET_MULHW"
1043 "machhw %0, %1, %2"
1044 [(set_attr "type" "imul3")])
1045
1046 (define_insn "*machhwuc"
1047 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1048 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1049 (match_operand:SI 1 "gpc_reg_operand" "%r")
1050 (const_int 16))
1051 (lshiftrt:SI
1052 (match_operand:SI 2 "gpc_reg_operand" "r")
1053 (const_int 16)))
1054 (match_operand:SI 4 "gpc_reg_operand" "0"))
1055 (const_int 0)))
1056 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1057 (plus:SI (mult:SI (lshiftrt:SI
1058 (match_dup 1)
1059 (const_int 16))
1060 (lshiftrt:SI
1061 (match_dup 2)
1062 (const_int 16)))
1063 (match_dup 4)))]
1064 "TARGET_MULHW"
1065 "machhwu. %0, %1, %2"
1066 [(set_attr "type" "imul3")])
1067
1068 (define_insn "*machhwu"
1069 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1070 (plus:SI (mult:SI (lshiftrt:SI
1071 (match_operand:SI 1 "gpc_reg_operand" "%r")
1072 (const_int 16))
1073 (lshiftrt:SI
1074 (match_operand:SI 2 "gpc_reg_operand" "r")
1075 (const_int 16)))
1076 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1077 "TARGET_MULHW"
1078 "machhwu %0, %1, %2"
1079 [(set_attr "type" "imul3")])
1080
1081 (define_insn "*maclhwc"
1082 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1083 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1084 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1085 (sign_extend:SI
1086 (match_operand:HI 2 "gpc_reg_operand" "r")))
1087 (match_operand:SI 4 "gpc_reg_operand" "0"))
1088 (const_int 0)))
1089 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1090 (plus:SI (mult:SI (sign_extend:SI
1091 (match_dup 1))
1092 (sign_extend:SI
1093 (match_dup 2)))
1094 (match_dup 4)))]
1095 "TARGET_MULHW"
1096 "maclhw. %0, %1, %2"
1097 [(set_attr "type" "imul3")])
1098
1099 (define_insn "*maclhw"
1100 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1101 (plus:SI (mult:SI (sign_extend:SI
1102 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1103 (sign_extend:SI
1104 (match_operand:HI 2 "gpc_reg_operand" "r")))
1105 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1106 "TARGET_MULHW"
1107 "maclhw %0, %1, %2"
1108 [(set_attr "type" "imul3")])
1109
1110 (define_insn "*maclhwuc"
1111 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1112 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1113 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1114 (zero_extend:SI
1115 (match_operand:HI 2 "gpc_reg_operand" "r")))
1116 (match_operand:SI 4 "gpc_reg_operand" "0"))
1117 (const_int 0)))
1118 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1119 (plus:SI (mult:SI (zero_extend:SI
1120 (match_dup 1))
1121 (zero_extend:SI
1122 (match_dup 2)))
1123 (match_dup 4)))]
1124 "TARGET_MULHW"
1125 "maclhwu. %0, %1, %2"
1126 [(set_attr "type" "imul3")])
1127
1128 (define_insn "*maclhwu"
1129 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1130 (plus:SI (mult:SI (zero_extend:SI
1131 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1132 (zero_extend:SI
1133 (match_operand:HI 2 "gpc_reg_operand" "r")))
1134 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1135 "TARGET_MULHW"
1136 "maclhwu %0, %1, %2"
1137 [(set_attr "type" "imul3")])
1138
1139 (define_insn "*nmacchwc"
1140 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1141 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1142 (mult:SI (ashiftrt:SI
1143 (match_operand:SI 2 "gpc_reg_operand" "r")
1144 (const_int 16))
1145 (sign_extend:SI
1146 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1147 (const_int 0)))
1148 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1149 (minus:SI (match_dup 4)
1150 (mult:SI (ashiftrt:SI
1151 (match_dup 2)
1152 (const_int 16))
1153 (sign_extend:SI
1154 (match_dup 1)))))]
1155 "TARGET_MULHW"
1156 "nmacchw. %0, %1, %2"
1157 [(set_attr "type" "imul3")])
1158
1159 (define_insn "*nmacchw"
1160 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1161 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1162 (mult:SI (ashiftrt:SI
1163 (match_operand:SI 2 "gpc_reg_operand" "r")
1164 (const_int 16))
1165 (sign_extend:SI
1166 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1167 "TARGET_MULHW"
1168 "nmacchw %0, %1, %2"
1169 [(set_attr "type" "imul3")])
1170
1171 (define_insn "*nmachhwc"
1172 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1173 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1174 (mult:SI (ashiftrt:SI
1175 (match_operand:SI 1 "gpc_reg_operand" "%r")
1176 (const_int 16))
1177 (ashiftrt:SI
1178 (match_operand:SI 2 "gpc_reg_operand" "r")
1179 (const_int 16))))
1180 (const_int 0)))
1181 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1182 (minus:SI (match_dup 4)
1183 (mult:SI (ashiftrt:SI
1184 (match_dup 1)
1185 (const_int 16))
1186 (ashiftrt:SI
1187 (match_dup 2)
1188 (const_int 16)))))]
1189 "TARGET_MULHW"
1190 "nmachhw. %0, %1, %2"
1191 [(set_attr "type" "imul3")])
1192
1193 (define_insn "*nmachhw"
1194 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1195 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1196 (mult:SI (ashiftrt:SI
1197 (match_operand:SI 1 "gpc_reg_operand" "%r")
1198 (const_int 16))
1199 (ashiftrt:SI
1200 (match_operand:SI 2 "gpc_reg_operand" "r")
1201 (const_int 16)))))]
1202 "TARGET_MULHW"
1203 "nmachhw %0, %1, %2"
1204 [(set_attr "type" "imul3")])
1205
1206 (define_insn "*nmaclhwc"
1207 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1208 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1209 (mult:SI (sign_extend:SI
1210 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1211 (sign_extend:SI
1212 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1213 (const_int 0)))
1214 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1215 (minus:SI (match_dup 4)
1216 (mult:SI (sign_extend:SI
1217 (match_dup 1))
1218 (sign_extend:SI
1219 (match_dup 2)))))]
1220 "TARGET_MULHW"
1221 "nmaclhw. %0, %1, %2"
1222 [(set_attr "type" "imul3")])
1223
1224 (define_insn "*nmaclhw"
1225 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1226 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1227 (mult:SI (sign_extend:SI
1228 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1229 (sign_extend:SI
1230 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1231 "TARGET_MULHW"
1232 "nmaclhw %0, %1, %2"
1233 [(set_attr "type" "imul3")])
1234
1235 (define_insn "*mulchwc"
1236 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1237 (compare:CC (mult:SI (ashiftrt:SI
1238 (match_operand:SI 2 "gpc_reg_operand" "r")
1239 (const_int 16))
1240 (sign_extend:SI
1241 (match_operand:HI 1 "gpc_reg_operand" "r")))
1242 (const_int 0)))
1243 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1244 (mult:SI (ashiftrt:SI
1245 (match_dup 2)
1246 (const_int 16))
1247 (sign_extend:SI
1248 (match_dup 1))))]
1249 "TARGET_MULHW"
1250 "mulchw. %0, %1, %2"
1251 [(set_attr "type" "imul3")])
1252
1253 (define_insn "*mulchw"
1254 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1255 (mult:SI (ashiftrt:SI
1256 (match_operand:SI 2 "gpc_reg_operand" "r")
1257 (const_int 16))
1258 (sign_extend:SI
1259 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1260 "TARGET_MULHW"
1261 "mulchw %0, %1, %2"
1262 [(set_attr "type" "imul3")])
1263
1264 (define_insn "*mulchwuc"
1265 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1266 (compare:CC (mult:SI (lshiftrt:SI
1267 (match_operand:SI 2 "gpc_reg_operand" "r")
1268 (const_int 16))
1269 (zero_extend:SI
1270 (match_operand:HI 1 "gpc_reg_operand" "r")))
1271 (const_int 0)))
1272 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1273 (mult:SI (lshiftrt:SI
1274 (match_dup 2)
1275 (const_int 16))
1276 (zero_extend:SI
1277 (match_dup 1))))]
1278 "TARGET_MULHW"
1279 "mulchwu. %0, %1, %2"
1280 [(set_attr "type" "imul3")])
1281
1282 (define_insn "*mulchwu"
1283 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1284 (mult:SI (lshiftrt:SI
1285 (match_operand:SI 2 "gpc_reg_operand" "r")
1286 (const_int 16))
1287 (zero_extend:SI
1288 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1289 "TARGET_MULHW"
1290 "mulchwu %0, %1, %2"
1291 [(set_attr "type" "imul3")])
1292
1293 (define_insn "*mulhhwc"
1294 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1295 (compare:CC (mult:SI (ashiftrt:SI
1296 (match_operand:SI 1 "gpc_reg_operand" "%r")
1297 (const_int 16))
1298 (ashiftrt:SI
1299 (match_operand:SI 2 "gpc_reg_operand" "r")
1300 (const_int 16)))
1301 (const_int 0)))
1302 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1303 (mult:SI (ashiftrt:SI
1304 (match_dup 1)
1305 (const_int 16))
1306 (ashiftrt:SI
1307 (match_dup 2)
1308 (const_int 16))))]
1309 "TARGET_MULHW"
1310 "mulhhw. %0, %1, %2"
1311 [(set_attr "type" "imul3")])
1312
1313 (define_insn "*mulhhw"
1314 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1315 (mult:SI (ashiftrt:SI
1316 (match_operand:SI 1 "gpc_reg_operand" "%r")
1317 (const_int 16))
1318 (ashiftrt:SI
1319 (match_operand:SI 2 "gpc_reg_operand" "r")
1320 (const_int 16))))]
1321 "TARGET_MULHW"
1322 "mulhhw %0, %1, %2"
1323 [(set_attr "type" "imul3")])
1324
1325 (define_insn "*mulhhwuc"
1326 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1327 (compare:CC (mult:SI (lshiftrt:SI
1328 (match_operand:SI 1 "gpc_reg_operand" "%r")
1329 (const_int 16))
1330 (lshiftrt:SI
1331 (match_operand:SI 2 "gpc_reg_operand" "r")
1332 (const_int 16)))
1333 (const_int 0)))
1334 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1335 (mult:SI (lshiftrt:SI
1336 (match_dup 1)
1337 (const_int 16))
1338 (lshiftrt:SI
1339 (match_dup 2)
1340 (const_int 16))))]
1341 "TARGET_MULHW"
1342 "mulhhwu. %0, %1, %2"
1343 [(set_attr "type" "imul3")])
1344
1345 (define_insn "*mulhhwu"
1346 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1347 (mult:SI (lshiftrt:SI
1348 (match_operand:SI 1 "gpc_reg_operand" "%r")
1349 (const_int 16))
1350 (lshiftrt:SI
1351 (match_operand:SI 2 "gpc_reg_operand" "r")
1352 (const_int 16))))]
1353 "TARGET_MULHW"
1354 "mulhhwu %0, %1, %2"
1355 [(set_attr "type" "imul3")])
1356
1357 (define_insn "*mullhwc"
1358 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1359 (compare:CC (mult:SI (sign_extend:SI
1360 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1361 (sign_extend:SI
1362 (match_operand:HI 2 "gpc_reg_operand" "r")))
1363 (const_int 0)))
1364 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1365 (mult:SI (sign_extend:SI
1366 (match_dup 1))
1367 (sign_extend:SI
1368 (match_dup 2))))]
1369 "TARGET_MULHW"
1370 "mullhw. %0, %1, %2"
1371 [(set_attr "type" "imul3")])
1372
1373 (define_insn "*mullhw"
1374 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1375 (mult:SI (sign_extend:SI
1376 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1377 (sign_extend:SI
1378 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1379 "TARGET_MULHW"
1380 "mullhw %0, %1, %2"
1381 [(set_attr "type" "imul3")])
1382
1383 (define_insn "*mullhwuc"
1384 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1385 (compare:CC (mult:SI (zero_extend:SI
1386 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1387 (zero_extend:SI
1388 (match_operand:HI 2 "gpc_reg_operand" "r")))
1389 (const_int 0)))
1390 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1391 (mult:SI (zero_extend:SI
1392 (match_dup 1))
1393 (zero_extend:SI
1394 (match_dup 2))))]
1395 "TARGET_MULHW"
1396 "mullhwu. %0, %1, %2"
1397 [(set_attr "type" "imul3")])
1398
1399 (define_insn "*mullhwu"
1400 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1401 (mult:SI (zero_extend:SI
1402 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1403 (zero_extend:SI
1404 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1405 "TARGET_MULHW"
1406 "mullhwu %0, %1, %2"
1407 [(set_attr "type" "imul3")])
1408 \f
1409 ;; IBM 405, 440 and 464 string-search dlmzb instruction support.
1410 (define_insn "dlmzb"
1411 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1412 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1413 (match_operand:SI 2 "gpc_reg_operand" "r")]
1414 UNSPEC_DLMZB_CR))
1415 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1416 (unspec:SI [(match_dup 1)
1417 (match_dup 2)]
1418 UNSPEC_DLMZB))]
1419 "TARGET_DLMZB"
1420 "dlmzb. %0, %1, %2")
1421
1422 (define_expand "strlensi"
1423 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1424 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1425 (match_operand:QI 2 "const_int_operand" "")
1426 (match_operand 3 "const_int_operand" "")]
1427 UNSPEC_DLMZB_STRLEN))
1428 (clobber (match_scratch:CC 4 "=x"))]
1429 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1430 {
1431 rtx result = operands[0];
1432 rtx src = operands[1];
1433 rtx search_char = operands[2];
1434 rtx align = operands[3];
1435 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1436 rtx loop_label, end_label, mem, cr0, cond;
1437 if (search_char != const0_rtx
1438 || GET_CODE (align) != CONST_INT
1439 || INTVAL (align) < 8)
1440 FAIL;
1441 word1 = gen_reg_rtx (SImode);
1442 word2 = gen_reg_rtx (SImode);
1443 scratch_dlmzb = gen_reg_rtx (SImode);
1444 scratch_string = gen_reg_rtx (Pmode);
1445 loop_label = gen_label_rtx ();
1446 end_label = gen_label_rtx ();
1447 addr = force_reg (Pmode, XEXP (src, 0));
1448 emit_move_insn (scratch_string, addr);
1449 emit_label (loop_label);
1450 mem = change_address (src, SImode, scratch_string);
1451 emit_move_insn (word1, mem);
1452 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1453 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1454 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1455 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1456 emit_jump_insn (gen_rtx_SET (VOIDmode,
1457 pc_rtx,
1458 gen_rtx_IF_THEN_ELSE (VOIDmode,
1459 cond,
1460 gen_rtx_LABEL_REF
1461 (VOIDmode,
1462 end_label),
1463 pc_rtx)));
1464 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1465 emit_jump_insn (gen_rtx_SET (VOIDmode,
1466 pc_rtx,
1467 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1468 emit_barrier ();
1469 emit_label (end_label);
1470 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1471 emit_insn (gen_subsi3 (result, scratch_string, addr));
1472 emit_insn (gen_subsi3 (result, result, const1_rtx));
1473 DONE;
1474 })
1475 \f
1476 (define_split
1477 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1478 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1479 (const_int 0)))
1480 (set (match_operand:SI 0 "gpc_reg_operand" "")
1481 (sign_extend:SI (match_dup 1)))]
1482 "reload_completed"
1483 [(set (match_dup 0)
1484 (sign_extend:SI (match_dup 1)))
1485 (set (match_dup 2)
1486 (compare:CC (match_dup 0)
1487 (const_int 0)))]
1488 "")
1489
1490 ;; Fixed-point arithmetic insns.
1491
1492 (define_expand "add<mode>3"
1493 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1494 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1495 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1496 ""
1497 {
1498 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1499 {
1500 if (non_short_cint_operand (operands[2], DImode))
1501 FAIL;
1502 }
1503 else if (GET_CODE (operands[2]) == CONST_INT
1504 && ! add_operand (operands[2], <MODE>mode))
1505 {
1506 rtx tmp = ((!can_create_pseudo_p ()
1507 || rtx_equal_p (operands[0], operands[1]))
1508 ? operands[0] : gen_reg_rtx (<MODE>mode));
1509
1510 HOST_WIDE_INT val = INTVAL (operands[2]);
1511 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1512 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1513
1514 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1515 FAIL;
1516
1517 /* The ordering here is important for the prolog expander.
1518 When space is allocated from the stack, adding 'low' first may
1519 produce a temporary deallocation (which would be bad). */
1520 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1521 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1522 DONE;
1523 }
1524 })
1525
1526 ;; Discourage ai/addic because of carry but provide it in an alternative
1527 ;; allowing register zero as source.
1528 (define_insn "*add<mode>3_internal1"
1529 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1530 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1531 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1532 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1533 "@
1534 {cax|add} %0,%1,%2
1535 {cal %0,%2(%1)|addi %0,%1,%2}
1536 {ai|addic} %0,%1,%2
1537 {cau|addis} %0,%1,%v2"
1538 [(set_attr "length" "4,4,4,4")])
1539
1540 (define_insn "addsi3_high"
1541 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1542 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1543 (high:SI (match_operand 2 "" ""))))]
1544 "TARGET_MACHO && !TARGET_64BIT"
1545 "{cau|addis} %0,%1,ha16(%2)"
1546 [(set_attr "length" "4")])
1547
1548 (define_insn "*add<mode>3_internal2"
1549 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1550 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1551 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1552 (const_int 0)))
1553 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1554 ""
1555 "@
1556 {cax.|add.} %3,%1,%2
1557 {ai.|addic.} %3,%1,%2
1558 #
1559 #"
1560 [(set_attr "type" "fast_compare,compare,compare,compare")
1561 (set_attr "length" "4,4,8,8")])
1562
1563 (define_split
1564 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1565 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1566 (match_operand:GPR 2 "reg_or_short_operand" ""))
1567 (const_int 0)))
1568 (clobber (match_scratch:GPR 3 ""))]
1569 "reload_completed"
1570 [(set (match_dup 3)
1571 (plus:GPR (match_dup 1)
1572 (match_dup 2)))
1573 (set (match_dup 0)
1574 (compare:CC (match_dup 3)
1575 (const_int 0)))]
1576 "")
1577
1578 (define_insn "*add<mode>3_internal3"
1579 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1580 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1581 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1582 (const_int 0)))
1583 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1584 (plus:P (match_dup 1)
1585 (match_dup 2)))]
1586 ""
1587 "@
1588 {cax.|add.} %0,%1,%2
1589 {ai.|addic.} %0,%1,%2
1590 #
1591 #"
1592 [(set_attr "type" "fast_compare,compare,compare,compare")
1593 (set_attr "length" "4,4,8,8")])
1594
1595 (define_split
1596 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1597 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1598 (match_operand:P 2 "reg_or_short_operand" ""))
1599 (const_int 0)))
1600 (set (match_operand:P 0 "gpc_reg_operand" "")
1601 (plus:P (match_dup 1) (match_dup 2)))]
1602 "reload_completed"
1603 [(set (match_dup 0)
1604 (plus:P (match_dup 1)
1605 (match_dup 2)))
1606 (set (match_dup 3)
1607 (compare:CC (match_dup 0)
1608 (const_int 0)))]
1609 "")
1610
1611 ;; Split an add that we can't do in one insn into two insns, each of which
1612 ;; does one 16-bit part. This is used by combine. Note that the low-order
1613 ;; add should be last in case the result gets used in an address.
1614
1615 (define_split
1616 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1617 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1618 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1619 ""
1620 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1621 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1622 {
1623 HOST_WIDE_INT val = INTVAL (operands[2]);
1624 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1625 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1626
1627 operands[4] = GEN_INT (low);
1628 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1629 operands[3] = GEN_INT (rest);
1630 else if (can_create_pseudo_p ())
1631 {
1632 operands[3] = gen_reg_rtx (DImode);
1633 emit_move_insn (operands[3], operands[2]);
1634 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1635 DONE;
1636 }
1637 else
1638 FAIL;
1639 })
1640
1641 (define_insn "one_cmpl<mode>2"
1642 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1643 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1644 ""
1645 "nor %0,%1,%1")
1646
1647 (define_insn ""
1648 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1649 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1650 (const_int 0)))
1651 (clobber (match_scratch:P 2 "=r,r"))]
1652 ""
1653 "@
1654 nor. %2,%1,%1
1655 #"
1656 [(set_attr "type" "compare")
1657 (set_attr "length" "4,8")])
1658
1659 (define_split
1660 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1661 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1662 (const_int 0)))
1663 (clobber (match_scratch:P 2 ""))]
1664 "reload_completed"
1665 [(set (match_dup 2)
1666 (not:P (match_dup 1)))
1667 (set (match_dup 0)
1668 (compare:CC (match_dup 2)
1669 (const_int 0)))]
1670 "")
1671
1672 (define_insn ""
1673 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1674 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1675 (const_int 0)))
1676 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1677 (not:P (match_dup 1)))]
1678 ""
1679 "@
1680 nor. %0,%1,%1
1681 #"
1682 [(set_attr "type" "compare")
1683 (set_attr "length" "4,8")])
1684
1685 (define_split
1686 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1687 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1688 (const_int 0)))
1689 (set (match_operand:P 0 "gpc_reg_operand" "")
1690 (not:P (match_dup 1)))]
1691 "reload_completed"
1692 [(set (match_dup 0)
1693 (not:P (match_dup 1)))
1694 (set (match_dup 2)
1695 (compare:CC (match_dup 0)
1696 (const_int 0)))]
1697 "")
1698
1699 (define_insn ""
1700 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1701 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1702 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1703 "! TARGET_POWERPC"
1704 "{sf%I1|subf%I1c} %0,%2,%1")
1705
1706 (define_insn ""
1707 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1708 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1709 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1710 "TARGET_POWERPC"
1711 "@
1712 subf %0,%2,%1
1713 subfic %0,%2,%1")
1714
1715 (define_insn ""
1716 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1717 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1718 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1719 (const_int 0)))
1720 (clobber (match_scratch:SI 3 "=r,r"))]
1721 "! TARGET_POWERPC"
1722 "@
1723 {sf.|subfc.} %3,%2,%1
1724 #"
1725 [(set_attr "type" "compare")
1726 (set_attr "length" "4,8")])
1727
1728 (define_insn ""
1729 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1730 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1731 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1732 (const_int 0)))
1733 (clobber (match_scratch:P 3 "=r,r"))]
1734 "TARGET_POWERPC"
1735 "@
1736 subf. %3,%2,%1
1737 #"
1738 [(set_attr "type" "fast_compare")
1739 (set_attr "length" "4,8")])
1740
1741 (define_split
1742 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1743 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1744 (match_operand:P 2 "gpc_reg_operand" ""))
1745 (const_int 0)))
1746 (clobber (match_scratch:P 3 ""))]
1747 "reload_completed"
1748 [(set (match_dup 3)
1749 (minus:P (match_dup 1)
1750 (match_dup 2)))
1751 (set (match_dup 0)
1752 (compare:CC (match_dup 3)
1753 (const_int 0)))]
1754 "")
1755
1756 (define_insn ""
1757 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1758 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1759 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1760 (const_int 0)))
1761 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1762 (minus:SI (match_dup 1) (match_dup 2)))]
1763 "! TARGET_POWERPC"
1764 "@
1765 {sf.|subfc.} %0,%2,%1
1766 #"
1767 [(set_attr "type" "compare")
1768 (set_attr "length" "4,8")])
1769
1770 (define_insn ""
1771 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1772 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1773 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1774 (const_int 0)))
1775 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1776 (minus:P (match_dup 1)
1777 (match_dup 2)))]
1778 "TARGET_POWERPC"
1779 "@
1780 subf. %0,%2,%1
1781 #"
1782 [(set_attr "type" "fast_compare")
1783 (set_attr "length" "4,8")])
1784
1785 (define_split
1786 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1787 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1788 (match_operand:P 2 "gpc_reg_operand" ""))
1789 (const_int 0)))
1790 (set (match_operand:P 0 "gpc_reg_operand" "")
1791 (minus:P (match_dup 1)
1792 (match_dup 2)))]
1793 "reload_completed"
1794 [(set (match_dup 0)
1795 (minus:P (match_dup 1)
1796 (match_dup 2)))
1797 (set (match_dup 3)
1798 (compare:CC (match_dup 0)
1799 (const_int 0)))]
1800 "")
1801
1802 (define_expand "sub<mode>3"
1803 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1804 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1805 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1806 ""
1807 "
1808 {
1809 if (GET_CODE (operands[2]) == CONST_INT)
1810 {
1811 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1812 negate_rtx (<MODE>mode, operands[2])));
1813 DONE;
1814 }
1815 }")
1816
1817 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1818 ;; instruction and some auxiliary computations. Then we just have a single
1819 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1820 ;; combine.
1821
1822 (define_expand "sminsi3"
1823 [(set (match_dup 3)
1824 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1825 (match_operand:SI 2 "reg_or_short_operand" ""))
1826 (const_int 0)
1827 (minus:SI (match_dup 2) (match_dup 1))))
1828 (set (match_operand:SI 0 "gpc_reg_operand" "")
1829 (minus:SI (match_dup 2) (match_dup 3)))]
1830 "TARGET_POWER || TARGET_ISEL"
1831 "
1832 {
1833 if (TARGET_ISEL)
1834 {
1835 operands[2] = force_reg (SImode, operands[2]);
1836 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1837 DONE;
1838 }
1839
1840 operands[3] = gen_reg_rtx (SImode);
1841 }")
1842
1843 (define_split
1844 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1845 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1846 (match_operand:SI 2 "reg_or_short_operand" "")))
1847 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1848 "TARGET_POWER"
1849 [(set (match_dup 3)
1850 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1851 (const_int 0)
1852 (minus:SI (match_dup 2) (match_dup 1))))
1853 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1854 "")
1855
1856 (define_expand "smaxsi3"
1857 [(set (match_dup 3)
1858 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1859 (match_operand:SI 2 "reg_or_short_operand" ""))
1860 (const_int 0)
1861 (minus:SI (match_dup 2) (match_dup 1))))
1862 (set (match_operand:SI 0 "gpc_reg_operand" "")
1863 (plus:SI (match_dup 3) (match_dup 1)))]
1864 "TARGET_POWER || TARGET_ISEL"
1865 "
1866 {
1867 if (TARGET_ISEL)
1868 {
1869 operands[2] = force_reg (SImode, operands[2]);
1870 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1871 DONE;
1872 }
1873 operands[3] = gen_reg_rtx (SImode);
1874 }")
1875
1876 (define_split
1877 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1878 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1879 (match_operand:SI 2 "reg_or_short_operand" "")))
1880 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1881 "TARGET_POWER"
1882 [(set (match_dup 3)
1883 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1884 (const_int 0)
1885 (minus:SI (match_dup 2) (match_dup 1))))
1886 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1887 "")
1888
1889 (define_expand "uminsi3"
1890 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1891 (match_dup 5)))
1892 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1893 (match_dup 5)))
1894 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1895 (const_int 0)
1896 (minus:SI (match_dup 4) (match_dup 3))))
1897 (set (match_operand:SI 0 "gpc_reg_operand" "")
1898 (minus:SI (match_dup 2) (match_dup 3)))]
1899 "TARGET_POWER || TARGET_ISEL"
1900 "
1901 {
1902 if (TARGET_ISEL)
1903 {
1904 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1905 DONE;
1906 }
1907 operands[3] = gen_reg_rtx (SImode);
1908 operands[4] = gen_reg_rtx (SImode);
1909 operands[5] = GEN_INT (-2147483647 - 1);
1910 }")
1911
1912 (define_expand "umaxsi3"
1913 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1914 (match_dup 5)))
1915 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1916 (match_dup 5)))
1917 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1918 (const_int 0)
1919 (minus:SI (match_dup 4) (match_dup 3))))
1920 (set (match_operand:SI 0 "gpc_reg_operand" "")
1921 (plus:SI (match_dup 3) (match_dup 1)))]
1922 "TARGET_POWER || TARGET_ISEL"
1923 "
1924 {
1925 if (TARGET_ISEL)
1926 {
1927 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1928 DONE;
1929 }
1930 operands[3] = gen_reg_rtx (SImode);
1931 operands[4] = gen_reg_rtx (SImode);
1932 operands[5] = GEN_INT (-2147483647 - 1);
1933 }")
1934
1935 (define_insn ""
1936 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1937 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1938 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1939 (const_int 0)
1940 (minus:SI (match_dup 2) (match_dup 1))))]
1941 "TARGET_POWER"
1942 "doz%I2 %0,%1,%2")
1943
1944 (define_insn ""
1945 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1946 (compare:CC
1947 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1948 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1949 (const_int 0)
1950 (minus:SI (match_dup 2) (match_dup 1)))
1951 (const_int 0)))
1952 (clobber (match_scratch:SI 3 "=r,r"))]
1953 "TARGET_POWER"
1954 "@
1955 doz%I2. %3,%1,%2
1956 #"
1957 [(set_attr "type" "delayed_compare")
1958 (set_attr "length" "4,8")])
1959
1960 (define_split
1961 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1962 (compare:CC
1963 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1964 (match_operand:SI 2 "reg_or_short_operand" ""))
1965 (const_int 0)
1966 (minus:SI (match_dup 2) (match_dup 1)))
1967 (const_int 0)))
1968 (clobber (match_scratch:SI 3 ""))]
1969 "TARGET_POWER && reload_completed"
1970 [(set (match_dup 3)
1971 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1972 (const_int 0)
1973 (minus:SI (match_dup 2) (match_dup 1))))
1974 (set (match_dup 0)
1975 (compare:CC (match_dup 3)
1976 (const_int 0)))]
1977 "")
1978
1979 (define_insn ""
1980 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1981 (compare:CC
1982 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1983 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1984 (const_int 0)
1985 (minus:SI (match_dup 2) (match_dup 1)))
1986 (const_int 0)))
1987 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1988 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1989 (const_int 0)
1990 (minus:SI (match_dup 2) (match_dup 1))))]
1991 "TARGET_POWER"
1992 "@
1993 doz%I2. %0,%1,%2
1994 #"
1995 [(set_attr "type" "delayed_compare")
1996 (set_attr "length" "4,8")])
1997
1998 (define_split
1999 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2000 (compare:CC
2001 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2002 (match_operand:SI 2 "reg_or_short_operand" ""))
2003 (const_int 0)
2004 (minus:SI (match_dup 2) (match_dup 1)))
2005 (const_int 0)))
2006 (set (match_operand:SI 0 "gpc_reg_operand" "")
2007 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2008 (const_int 0)
2009 (minus:SI (match_dup 2) (match_dup 1))))]
2010 "TARGET_POWER && reload_completed"
2011 [(set (match_dup 0)
2012 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2013 (const_int 0)
2014 (minus:SI (match_dup 2) (match_dup 1))))
2015 (set (match_dup 3)
2016 (compare:CC (match_dup 0)
2017 (const_int 0)))]
2018 "")
2019
2020 ;; We don't need abs with condition code because such comparisons should
2021 ;; never be done.
2022 (define_expand "abssi2"
2023 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2024 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2025 ""
2026 "
2027 {
2028 if (TARGET_ISEL)
2029 {
2030 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
2031 DONE;
2032 }
2033 else if (! TARGET_POWER)
2034 {
2035 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2036 DONE;
2037 }
2038 }")
2039
2040 (define_insn "*abssi2_power"
2041 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2042 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2043 "TARGET_POWER"
2044 "abs %0,%1")
2045
2046 (define_insn_and_split "abssi2_isel"
2047 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2048 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
2049 (clobber (match_scratch:SI 2 "=&b"))
2050 (clobber (match_scratch:CC 3 "=y"))]
2051 "TARGET_ISEL"
2052 "#"
2053 "&& reload_completed"
2054 [(set (match_dup 2) (neg:SI (match_dup 1)))
2055 (set (match_dup 3)
2056 (compare:CC (match_dup 1)
2057 (const_int 0)))
2058 (set (match_dup 0)
2059 (if_then_else:SI (ge (match_dup 3)
2060 (const_int 0))
2061 (match_dup 1)
2062 (match_dup 2)))]
2063 "")
2064
2065 (define_insn_and_split "abssi2_nopower"
2066 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2067 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2068 (clobber (match_scratch:SI 2 "=&r,&r"))]
2069 "! TARGET_POWER && ! TARGET_ISEL"
2070 "#"
2071 "&& reload_completed"
2072 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2073 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2074 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2075 "")
2076
2077 (define_insn "*nabs_power"
2078 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2079 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2080 "TARGET_POWER"
2081 "nabs %0,%1")
2082
2083 (define_insn_and_split "*nabs_nopower"
2084 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2085 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2086 (clobber (match_scratch:SI 2 "=&r,&r"))]
2087 "! TARGET_POWER"
2088 "#"
2089 "&& reload_completed"
2090 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2091 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2092 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2093 "")
2094
2095 (define_expand "neg<mode>2"
2096 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2097 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2098 ""
2099 "")
2100
2101 (define_insn "*neg<mode>2_internal"
2102 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2103 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2104 ""
2105 "neg %0,%1")
2106
2107 (define_insn ""
2108 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2109 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2110 (const_int 0)))
2111 (clobber (match_scratch:P 2 "=r,r"))]
2112 ""
2113 "@
2114 neg. %2,%1
2115 #"
2116 [(set_attr "type" "fast_compare")
2117 (set_attr "length" "4,8")])
2118
2119 (define_split
2120 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2121 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2122 (const_int 0)))
2123 (clobber (match_scratch:P 2 ""))]
2124 "reload_completed"
2125 [(set (match_dup 2)
2126 (neg:P (match_dup 1)))
2127 (set (match_dup 0)
2128 (compare:CC (match_dup 2)
2129 (const_int 0)))]
2130 "")
2131
2132 (define_insn ""
2133 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2134 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2135 (const_int 0)))
2136 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2137 (neg:P (match_dup 1)))]
2138 ""
2139 "@
2140 neg. %0,%1
2141 #"
2142 [(set_attr "type" "fast_compare")
2143 (set_attr "length" "4,8")])
2144
2145 (define_split
2146 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2147 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2148 (const_int 0)))
2149 (set (match_operand:P 0 "gpc_reg_operand" "")
2150 (neg:P (match_dup 1)))]
2151 "reload_completed"
2152 [(set (match_dup 0)
2153 (neg:P (match_dup 1)))
2154 (set (match_dup 2)
2155 (compare:CC (match_dup 0)
2156 (const_int 0)))]
2157 "")
2158
2159 (define_insn "clz<mode>2"
2160 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2161 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2162 ""
2163 "{cntlz|cntlz<wd>} %0,%1"
2164 [(set_attr "type" "cntlz")])
2165
2166 (define_expand "ctz<mode>2"
2167 [(set (match_dup 2)
2168 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2169 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2170 (match_dup 2)))
2171 (clobber (scratch:CC))])
2172 (set (match_dup 4) (clz:GPR (match_dup 3)))
2173 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2174 (minus:GPR (match_dup 5) (match_dup 4)))]
2175 ""
2176 {
2177 operands[2] = gen_reg_rtx (<MODE>mode);
2178 operands[3] = gen_reg_rtx (<MODE>mode);
2179 operands[4] = gen_reg_rtx (<MODE>mode);
2180 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2181 })
2182
2183 (define_expand "ffs<mode>2"
2184 [(set (match_dup 2)
2185 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2186 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2187 (match_dup 2)))
2188 (clobber (scratch:CC))])
2189 (set (match_dup 4) (clz:GPR (match_dup 3)))
2190 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2191 (minus:GPR (match_dup 5) (match_dup 4)))]
2192 ""
2193 {
2194 operands[2] = gen_reg_rtx (<MODE>mode);
2195 operands[3] = gen_reg_rtx (<MODE>mode);
2196 operands[4] = gen_reg_rtx (<MODE>mode);
2197 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2198 })
2199
2200 (define_insn "popcntb<mode>2"
2201 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2202 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2203 UNSPEC_POPCNTB))]
2204 "TARGET_POPCNTB"
2205 "popcntb %0,%1")
2206
2207 (define_expand "popcount<mode>2"
2208 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2209 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2210 "TARGET_POPCNTB"
2211 {
2212 rs6000_emit_popcount (operands[0], operands[1]);
2213 DONE;
2214 })
2215
2216 (define_expand "parity<mode>2"
2217 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2218 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2219 "TARGET_POPCNTB"
2220 {
2221 rs6000_emit_parity (operands[0], operands[1]);
2222 DONE;
2223 })
2224
2225 (define_insn "bswapsi2"
2226 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2227 (bswap:SI (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2228 ""
2229 "@
2230 {lbrx|lwbrx} %0,%y1
2231 {stbrx|stwbrx} %1,%y0
2232 #"
2233 [(set_attr "length" "4,4,12")])
2234
2235 (define_split
2236 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2237 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2238 "reload_completed"
2239 [(set (match_dup 0)
2240 (rotate:SI (match_dup 1) (const_int 8)))
2241 (set (zero_extract:SI (match_dup 0)
2242 (const_int 8)
2243 (const_int 0))
2244 (match_dup 1))
2245 (set (zero_extract:SI (match_dup 0)
2246 (const_int 8)
2247 (const_int 16))
2248 (rotate:SI (match_dup 1)
2249 (const_int 16)))]
2250 "")
2251
2252 (define_expand "mulsi3"
2253 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2254 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2255 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2256 ""
2257 "
2258 {
2259 if (TARGET_POWER)
2260 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2261 else
2262 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2263 DONE;
2264 }")
2265
2266 (define_insn "mulsi3_mq"
2267 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2268 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2269 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2270 (clobber (match_scratch:SI 3 "=q,q"))]
2271 "TARGET_POWER"
2272 "@
2273 {muls|mullw} %0,%1,%2
2274 {muli|mulli} %0,%1,%2"
2275 [(set (attr "type")
2276 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2277 (const_string "imul3")
2278 (match_operand:SI 2 "short_cint_operand" "")
2279 (const_string "imul2")]
2280 (const_string "imul")))])
2281
2282 (define_insn "mulsi3_no_mq"
2283 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2284 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2285 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2286 "! TARGET_POWER"
2287 "@
2288 {muls|mullw} %0,%1,%2
2289 {muli|mulli} %0,%1,%2"
2290 [(set (attr "type")
2291 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2292 (const_string "imul3")
2293 (match_operand:SI 2 "short_cint_operand" "")
2294 (const_string "imul2")]
2295 (const_string "imul")))])
2296
2297 (define_insn "*mulsi3_mq_internal1"
2298 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2299 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2300 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2301 (const_int 0)))
2302 (clobber (match_scratch:SI 3 "=r,r"))
2303 (clobber (match_scratch:SI 4 "=q,q"))]
2304 "TARGET_POWER"
2305 "@
2306 {muls.|mullw.} %3,%1,%2
2307 #"
2308 [(set_attr "type" "imul_compare")
2309 (set_attr "length" "4,8")])
2310
2311 (define_split
2312 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2313 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2314 (match_operand:SI 2 "gpc_reg_operand" ""))
2315 (const_int 0)))
2316 (clobber (match_scratch:SI 3 ""))
2317 (clobber (match_scratch:SI 4 ""))]
2318 "TARGET_POWER && reload_completed"
2319 [(parallel [(set (match_dup 3)
2320 (mult:SI (match_dup 1) (match_dup 2)))
2321 (clobber (match_dup 4))])
2322 (set (match_dup 0)
2323 (compare:CC (match_dup 3)
2324 (const_int 0)))]
2325 "")
2326
2327 (define_insn "*mulsi3_no_mq_internal1"
2328 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2329 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2330 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2331 (const_int 0)))
2332 (clobber (match_scratch:SI 3 "=r,r"))]
2333 "! TARGET_POWER"
2334 "@
2335 {muls.|mullw.} %3,%1,%2
2336 #"
2337 [(set_attr "type" "imul_compare")
2338 (set_attr "length" "4,8")])
2339
2340 (define_split
2341 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2342 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2343 (match_operand:SI 2 "gpc_reg_operand" ""))
2344 (const_int 0)))
2345 (clobber (match_scratch:SI 3 ""))]
2346 "! TARGET_POWER && reload_completed"
2347 [(set (match_dup 3)
2348 (mult:SI (match_dup 1) (match_dup 2)))
2349 (set (match_dup 0)
2350 (compare:CC (match_dup 3)
2351 (const_int 0)))]
2352 "")
2353
2354 (define_insn "*mulsi3_mq_internal2"
2355 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2356 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2357 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2358 (const_int 0)))
2359 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2360 (mult:SI (match_dup 1) (match_dup 2)))
2361 (clobber (match_scratch:SI 4 "=q,q"))]
2362 "TARGET_POWER"
2363 "@
2364 {muls.|mullw.} %0,%1,%2
2365 #"
2366 [(set_attr "type" "imul_compare")
2367 (set_attr "length" "4,8")])
2368
2369 (define_split
2370 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2371 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2372 (match_operand:SI 2 "gpc_reg_operand" ""))
2373 (const_int 0)))
2374 (set (match_operand:SI 0 "gpc_reg_operand" "")
2375 (mult:SI (match_dup 1) (match_dup 2)))
2376 (clobber (match_scratch:SI 4 ""))]
2377 "TARGET_POWER && reload_completed"
2378 [(parallel [(set (match_dup 0)
2379 (mult:SI (match_dup 1) (match_dup 2)))
2380 (clobber (match_dup 4))])
2381 (set (match_dup 3)
2382 (compare:CC (match_dup 0)
2383 (const_int 0)))]
2384 "")
2385
2386 (define_insn "*mulsi3_no_mq_internal2"
2387 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2388 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2389 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2390 (const_int 0)))
2391 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2392 (mult:SI (match_dup 1) (match_dup 2)))]
2393 "! TARGET_POWER"
2394 "@
2395 {muls.|mullw.} %0,%1,%2
2396 #"
2397 [(set_attr "type" "imul_compare")
2398 (set_attr "length" "4,8")])
2399
2400 (define_split
2401 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2402 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2403 (match_operand:SI 2 "gpc_reg_operand" ""))
2404 (const_int 0)))
2405 (set (match_operand:SI 0 "gpc_reg_operand" "")
2406 (mult:SI (match_dup 1) (match_dup 2)))]
2407 "! TARGET_POWER && reload_completed"
2408 [(set (match_dup 0)
2409 (mult:SI (match_dup 1) (match_dup 2)))
2410 (set (match_dup 3)
2411 (compare:CC (match_dup 0)
2412 (const_int 0)))]
2413 "")
2414
2415 ;; Operand 1 is divided by operand 2; quotient goes to operand
2416 ;; 0 and remainder to operand 3.
2417 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2418
2419 (define_expand "divmodsi4"
2420 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2421 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2422 (match_operand:SI 2 "gpc_reg_operand" "")))
2423 (set (match_operand:SI 3 "register_operand" "")
2424 (mod:SI (match_dup 1) (match_dup 2)))])]
2425 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2426 "
2427 {
2428 if (! TARGET_POWER && ! TARGET_POWERPC)
2429 {
2430 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2431 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2432 emit_insn (gen_divss_call ());
2433 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2434 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2435 DONE;
2436 }
2437 }")
2438
2439 (define_insn "*divmodsi4_internal"
2440 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2441 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2442 (match_operand:SI 2 "gpc_reg_operand" "r")))
2443 (set (match_operand:SI 3 "register_operand" "=q")
2444 (mod:SI (match_dup 1) (match_dup 2)))]
2445 "TARGET_POWER"
2446 "divs %0,%1,%2"
2447 [(set_attr "type" "idiv")])
2448
2449 (define_expand "udiv<mode>3"
2450 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2451 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2452 (match_operand:GPR 2 "gpc_reg_operand" "")))]
2453 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2454 "
2455 {
2456 if (! TARGET_POWER && ! TARGET_POWERPC)
2457 {
2458 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2459 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2460 emit_insn (gen_quous_call ());
2461 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2462 DONE;
2463 }
2464 else if (TARGET_POWER)
2465 {
2466 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2467 DONE;
2468 }
2469 }")
2470
2471 (define_insn "udivsi3_mq"
2472 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2473 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2474 (match_operand:SI 2 "gpc_reg_operand" "r")))
2475 (clobber (match_scratch:SI 3 "=q"))]
2476 "TARGET_POWERPC && TARGET_POWER"
2477 "divwu %0,%1,%2"
2478 [(set_attr "type" "idiv")])
2479
2480 (define_insn "*udivsi3_no_mq"
2481 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2482 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2483 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2484 "TARGET_POWERPC && ! TARGET_POWER"
2485 "div<wd>u %0,%1,%2"
2486 [(set (attr "type")
2487 (cond [(match_operand:SI 0 "" "")
2488 (const_string "idiv")]
2489 (const_string "ldiv")))])
2490
2491
2492 ;; For powers of two we can do srai/aze for divide and then adjust for
2493 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2494 ;; used; for PowerPC, force operands into register and do a normal divide;
2495 ;; for AIX common-mode, use quoss call on register operands.
2496 (define_expand "div<mode>3"
2497 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2498 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2499 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2500 ""
2501 "
2502 {
2503 if (GET_CODE (operands[2]) == CONST_INT
2504 && INTVAL (operands[2]) > 0
2505 && exact_log2 (INTVAL (operands[2])) >= 0)
2506 ;
2507 else if (TARGET_POWERPC)
2508 {
2509 operands[2] = force_reg (<MODE>mode, operands[2]);
2510 if (TARGET_POWER)
2511 {
2512 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2513 DONE;
2514 }
2515 }
2516 else if (TARGET_POWER)
2517 FAIL;
2518 else
2519 {
2520 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2521 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2522 emit_insn (gen_quoss_call ());
2523 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2524 DONE;
2525 }
2526 }")
2527
2528 (define_insn "divsi3_mq"
2529 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2530 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2531 (match_operand:SI 2 "gpc_reg_operand" "r")))
2532 (clobber (match_scratch:SI 3 "=q"))]
2533 "TARGET_POWERPC && TARGET_POWER"
2534 "divw %0,%1,%2"
2535 [(set_attr "type" "idiv")])
2536
2537 (define_insn "*div<mode>3_no_mq"
2538 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2539 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2540 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2541 "TARGET_POWERPC && ! TARGET_POWER"
2542 "div<wd> %0,%1,%2"
2543 [(set (attr "type")
2544 (cond [(match_operand:SI 0 "" "")
2545 (const_string "idiv")]
2546 (const_string "ldiv")))])
2547
2548 (define_expand "mod<mode>3"
2549 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2550 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2551 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2552 ""
2553 "
2554 {
2555 int i;
2556 rtx temp1;
2557 rtx temp2;
2558
2559 if (GET_CODE (operands[2]) != CONST_INT
2560 || INTVAL (operands[2]) <= 0
2561 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2562 FAIL;
2563
2564 temp1 = gen_reg_rtx (<MODE>mode);
2565 temp2 = gen_reg_rtx (<MODE>mode);
2566
2567 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2568 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2569 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2570 DONE;
2571 }")
2572
2573 (define_insn ""
2574 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2575 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2576 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2577 ""
2578 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
2579 [(set_attr "type" "two")
2580 (set_attr "length" "8")])
2581
2582 (define_insn ""
2583 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2584 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2585 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2586 (const_int 0)))
2587 (clobber (match_scratch:P 3 "=r,r"))]
2588 ""
2589 "@
2590 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
2591 #"
2592 [(set_attr "type" "compare")
2593 (set_attr "length" "8,12")])
2594
2595 (define_split
2596 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2597 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2598 (match_operand:GPR 2 "exact_log2_cint_operand"
2599 ""))
2600 (const_int 0)))
2601 (clobber (match_scratch:GPR 3 ""))]
2602 "reload_completed"
2603 [(set (match_dup 3)
2604 (div:<MODE> (match_dup 1) (match_dup 2)))
2605 (set (match_dup 0)
2606 (compare:CC (match_dup 3)
2607 (const_int 0)))]
2608 "")
2609
2610 (define_insn ""
2611 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2612 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2613 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2614 (const_int 0)))
2615 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2616 (div:P (match_dup 1) (match_dup 2)))]
2617 ""
2618 "@
2619 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
2620 #"
2621 [(set_attr "type" "compare")
2622 (set_attr "length" "8,12")])
2623
2624 (define_split
2625 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2626 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2627 (match_operand:GPR 2 "exact_log2_cint_operand"
2628 ""))
2629 (const_int 0)))
2630 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2631 (div:GPR (match_dup 1) (match_dup 2)))]
2632 "reload_completed"
2633 [(set (match_dup 0)
2634 (div:<MODE> (match_dup 1) (match_dup 2)))
2635 (set (match_dup 3)
2636 (compare:CC (match_dup 0)
2637 (const_int 0)))]
2638 "")
2639
2640 (define_insn ""
2641 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2642 (udiv:SI
2643 (plus:DI (ashift:DI
2644 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2645 (const_int 32))
2646 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2647 (match_operand:SI 3 "gpc_reg_operand" "r")))
2648 (set (match_operand:SI 2 "register_operand" "=*q")
2649 (umod:SI
2650 (plus:DI (ashift:DI
2651 (zero_extend:DI (match_dup 1)) (const_int 32))
2652 (zero_extend:DI (match_dup 4)))
2653 (match_dup 3)))]
2654 "TARGET_POWER"
2655 "div %0,%1,%3"
2656 [(set_attr "type" "idiv")])
2657
2658 ;; To do unsigned divide we handle the cases of the divisor looking like a
2659 ;; negative number. If it is a constant that is less than 2**31, we don't
2660 ;; have to worry about the branches. So make a few subroutines here.
2661 ;;
2662 ;; First comes the normal case.
2663 (define_expand "udivmodsi4_normal"
2664 [(set (match_dup 4) (const_int 0))
2665 (parallel [(set (match_operand:SI 0 "" "")
2666 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2667 (const_int 32))
2668 (zero_extend:DI (match_operand:SI 1 "" "")))
2669 (match_operand:SI 2 "" "")))
2670 (set (match_operand:SI 3 "" "")
2671 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2672 (const_int 32))
2673 (zero_extend:DI (match_dup 1)))
2674 (match_dup 2)))])]
2675 "TARGET_POWER"
2676 "
2677 { operands[4] = gen_reg_rtx (SImode); }")
2678
2679 ;; This handles the branches.
2680 (define_expand "udivmodsi4_tests"
2681 [(set (match_operand:SI 0 "" "") (const_int 0))
2682 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2683 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2684 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2685 (label_ref (match_operand:SI 4 "" "")) (pc)))
2686 (set (match_dup 0) (const_int 1))
2687 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2688 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2689 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2690 (label_ref (match_dup 4)) (pc)))]
2691 "TARGET_POWER"
2692 "
2693 { operands[5] = gen_reg_rtx (CCUNSmode);
2694 operands[6] = gen_reg_rtx (CCmode);
2695 }")
2696
2697 (define_expand "udivmodsi4"
2698 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2699 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2700 (match_operand:SI 2 "reg_or_cint_operand" "")))
2701 (set (match_operand:SI 3 "gpc_reg_operand" "")
2702 (umod:SI (match_dup 1) (match_dup 2)))])]
2703 ""
2704 "
2705 {
2706 rtx label = 0;
2707
2708 if (! TARGET_POWER)
2709 {
2710 if (! TARGET_POWERPC)
2711 {
2712 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2713 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2714 emit_insn (gen_divus_call ());
2715 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2716 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2717 DONE;
2718 }
2719 else
2720 FAIL;
2721 }
2722
2723 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2724 {
2725 operands[2] = force_reg (SImode, operands[2]);
2726 label = gen_label_rtx ();
2727 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2728 operands[3], label));
2729 }
2730 else
2731 operands[2] = force_reg (SImode, operands[2]);
2732
2733 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2734 operands[3]));
2735 if (label)
2736 emit_label (label);
2737
2738 DONE;
2739 }")
2740
2741 ;; AIX architecture-independent common-mode multiply (DImode),
2742 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2743 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2744 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2745 ;; assumed unused if generating common-mode, so ignore.
2746 (define_insn "mulh_call"
2747 [(set (reg:SI 3)
2748 (truncate:SI
2749 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2750 (sign_extend:DI (reg:SI 4)))
2751 (const_int 32))))
2752 (clobber (reg:SI LR_REGNO))]
2753 "! TARGET_POWER && ! TARGET_POWERPC"
2754 "bla __mulh"
2755 [(set_attr "type" "imul")])
2756
2757 (define_insn "mull_call"
2758 [(set (reg:DI 3)
2759 (mult:DI (sign_extend:DI (reg:SI 3))
2760 (sign_extend:DI (reg:SI 4))))
2761 (clobber (reg:SI LR_REGNO))
2762 (clobber (reg:SI 0))]
2763 "! TARGET_POWER && ! TARGET_POWERPC"
2764 "bla __mull"
2765 [(set_attr "type" "imul")])
2766
2767 (define_insn "divss_call"
2768 [(set (reg:SI 3)
2769 (div:SI (reg:SI 3) (reg:SI 4)))
2770 (set (reg:SI 4)
2771 (mod:SI (reg:SI 3) (reg:SI 4)))
2772 (clobber (reg:SI LR_REGNO))
2773 (clobber (reg:SI 0))]
2774 "! TARGET_POWER && ! TARGET_POWERPC"
2775 "bla __divss"
2776 [(set_attr "type" "idiv")])
2777
2778 (define_insn "divus_call"
2779 [(set (reg:SI 3)
2780 (udiv:SI (reg:SI 3) (reg:SI 4)))
2781 (set (reg:SI 4)
2782 (umod:SI (reg:SI 3) (reg:SI 4)))
2783 (clobber (reg:SI LR_REGNO))
2784 (clobber (reg:SI 0))
2785 (clobber (match_scratch:CC 0 "=x"))
2786 (clobber (reg:CC CR1_REGNO))]
2787 "! TARGET_POWER && ! TARGET_POWERPC"
2788 "bla __divus"
2789 [(set_attr "type" "idiv")])
2790
2791 (define_insn "quoss_call"
2792 [(set (reg:SI 3)
2793 (div:SI (reg:SI 3) (reg:SI 4)))
2794 (clobber (reg:SI LR_REGNO))]
2795 "! TARGET_POWER && ! TARGET_POWERPC"
2796 "bla __quoss"
2797 [(set_attr "type" "idiv")])
2798
2799 (define_insn "quous_call"
2800 [(set (reg:SI 3)
2801 (udiv:SI (reg:SI 3) (reg:SI 4)))
2802 (clobber (reg:SI LR_REGNO))
2803 (clobber (reg:SI 0))
2804 (clobber (match_scratch:CC 0 "=x"))
2805 (clobber (reg:CC CR1_REGNO))]
2806 "! TARGET_POWER && ! TARGET_POWERPC"
2807 "bla __quous"
2808 [(set_attr "type" "idiv")])
2809 \f
2810 ;; Logical instructions
2811 ;; The logical instructions are mostly combined by using match_operator,
2812 ;; but the plain AND insns are somewhat different because there is no
2813 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2814 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2815
2816 (define_insn "andsi3"
2817 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2818 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2819 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2820 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2821 ""
2822 "@
2823 and %0,%1,%2
2824 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2825 {andil.|andi.} %0,%1,%b2
2826 {andiu.|andis.} %0,%1,%u2"
2827 [(set_attr "type" "*,*,compare,compare")])
2828
2829 ;; Note to set cr's other than cr0 we do the and immediate and then
2830 ;; the test again -- this avoids a mfcr which on the higher end
2831 ;; machines causes an execution serialization
2832
2833 (define_insn "*andsi3_internal2"
2834 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2835 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2836 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2837 (const_int 0)))
2838 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2839 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2840 "TARGET_32BIT"
2841 "@
2842 and. %3,%1,%2
2843 {andil.|andi.} %3,%1,%b2
2844 {andiu.|andis.} %3,%1,%u2
2845 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2846 #
2847 #
2848 #
2849 #"
2850 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2851 (set_attr "length" "4,4,4,4,8,8,8,8")])
2852
2853 (define_insn "*andsi3_internal3"
2854 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2855 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2856 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2857 (const_int 0)))
2858 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2859 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2860 "TARGET_64BIT"
2861 "@
2862 #
2863 {andil.|andi.} %3,%1,%b2
2864 {andiu.|andis.} %3,%1,%u2
2865 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2866 #
2867 #
2868 #
2869 #"
2870 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2871 (set_attr "length" "8,4,4,4,8,8,8,8")])
2872
2873 (define_split
2874 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2875 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2876 (match_operand:GPR 2 "and_operand" ""))
2877 (const_int 0)))
2878 (clobber (match_scratch:GPR 3 ""))
2879 (clobber (match_scratch:CC 4 ""))]
2880 "reload_completed"
2881 [(parallel [(set (match_dup 3)
2882 (and:<MODE> (match_dup 1)
2883 (match_dup 2)))
2884 (clobber (match_dup 4))])
2885 (set (match_dup 0)
2886 (compare:CC (match_dup 3)
2887 (const_int 0)))]
2888 "")
2889
2890 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2891 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2892
2893 (define_split
2894 [(set (match_operand:CC 0 "cc_reg_operand" "")
2895 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2896 (match_operand:SI 2 "gpc_reg_operand" ""))
2897 (const_int 0)))
2898 (clobber (match_scratch:SI 3 ""))
2899 (clobber (match_scratch:CC 4 ""))]
2900 "TARGET_POWERPC64 && reload_completed"
2901 [(parallel [(set (match_dup 3)
2902 (and:SI (match_dup 1)
2903 (match_dup 2)))
2904 (clobber (match_dup 4))])
2905 (set (match_dup 0)
2906 (compare:CC (match_dup 3)
2907 (const_int 0)))]
2908 "")
2909
2910 (define_insn "*andsi3_internal4"
2911 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2912 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2913 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2914 (const_int 0)))
2915 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2916 (and:SI (match_dup 1)
2917 (match_dup 2)))
2918 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2919 "TARGET_32BIT"
2920 "@
2921 and. %0,%1,%2
2922 {andil.|andi.} %0,%1,%b2
2923 {andiu.|andis.} %0,%1,%u2
2924 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2925 #
2926 #
2927 #
2928 #"
2929 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2930 (set_attr "length" "4,4,4,4,8,8,8,8")])
2931
2932 (define_insn "*andsi3_internal5"
2933 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2934 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2935 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2936 (const_int 0)))
2937 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2938 (and:SI (match_dup 1)
2939 (match_dup 2)))
2940 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2941 "TARGET_64BIT"
2942 "@
2943 #
2944 {andil.|andi.} %0,%1,%b2
2945 {andiu.|andis.} %0,%1,%u2
2946 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2947 #
2948 #
2949 #
2950 #"
2951 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2952 (set_attr "length" "8,4,4,4,8,8,8,8")])
2953
2954 (define_split
2955 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2956 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2957 (match_operand:SI 2 "and_operand" ""))
2958 (const_int 0)))
2959 (set (match_operand:SI 0 "gpc_reg_operand" "")
2960 (and:SI (match_dup 1)
2961 (match_dup 2)))
2962 (clobber (match_scratch:CC 4 ""))]
2963 "reload_completed"
2964 [(parallel [(set (match_dup 0)
2965 (and:SI (match_dup 1)
2966 (match_dup 2)))
2967 (clobber (match_dup 4))])
2968 (set (match_dup 3)
2969 (compare:CC (match_dup 0)
2970 (const_int 0)))]
2971 "")
2972
2973 (define_split
2974 [(set (match_operand:CC 3 "cc_reg_operand" "")
2975 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2976 (match_operand:SI 2 "gpc_reg_operand" ""))
2977 (const_int 0)))
2978 (set (match_operand:SI 0 "gpc_reg_operand" "")
2979 (and:SI (match_dup 1)
2980 (match_dup 2)))
2981 (clobber (match_scratch:CC 4 ""))]
2982 "TARGET_POWERPC64 && reload_completed"
2983 [(parallel [(set (match_dup 0)
2984 (and:SI (match_dup 1)
2985 (match_dup 2)))
2986 (clobber (match_dup 4))])
2987 (set (match_dup 3)
2988 (compare:CC (match_dup 0)
2989 (const_int 0)))]
2990 "")
2991
2992 ;; Handle the PowerPC64 rlwinm corner case
2993
2994 (define_insn_and_split "*andsi3_internal6"
2995 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2996 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2997 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2998 "TARGET_POWERPC64"
2999 "#"
3000 "TARGET_POWERPC64"
3001 [(set (match_dup 0)
3002 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3003 (match_dup 4)))
3004 (set (match_dup 0)
3005 (rotate:SI (match_dup 0) (match_dup 5)))]
3006 "
3007 {
3008 int mb = extract_MB (operands[2]);
3009 int me = extract_ME (operands[2]);
3010 operands[3] = GEN_INT (me + 1);
3011 operands[5] = GEN_INT (32 - (me + 1));
3012 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3013 }"
3014 [(set_attr "length" "8")])
3015
3016 (define_expand "iorsi3"
3017 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3018 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
3019 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3020 ""
3021 "
3022 {
3023 if (GET_CODE (operands[2]) == CONST_INT
3024 && ! logical_operand (operands[2], SImode))
3025 {
3026 HOST_WIDE_INT value = INTVAL (operands[2]);
3027 rtx tmp = ((!can_create_pseudo_p ()
3028 || rtx_equal_p (operands[0], operands[1]))
3029 ? operands[0] : gen_reg_rtx (SImode));
3030
3031 emit_insn (gen_iorsi3 (tmp, operands[1],
3032 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3033 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3034 DONE;
3035 }
3036 }")
3037
3038 (define_expand "xorsi3"
3039 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3040 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3041 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3042 ""
3043 "
3044 {
3045 if (GET_CODE (operands[2]) == CONST_INT
3046 && ! logical_operand (operands[2], SImode))
3047 {
3048 HOST_WIDE_INT value = INTVAL (operands[2]);
3049 rtx tmp = ((!can_create_pseudo_p ()
3050 || rtx_equal_p (operands[0], operands[1]))
3051 ? operands[0] : gen_reg_rtx (SImode));
3052
3053 emit_insn (gen_xorsi3 (tmp, operands[1],
3054 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3055 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3056 DONE;
3057 }
3058 }")
3059
3060 (define_insn "*boolsi3_internal1"
3061 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3062 (match_operator:SI 3 "boolean_or_operator"
3063 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3064 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3065 ""
3066 "@
3067 %q3 %0,%1,%2
3068 {%q3il|%q3i} %0,%1,%b2
3069 {%q3iu|%q3is} %0,%1,%u2")
3070
3071 (define_insn "*boolsi3_internal2"
3072 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3073 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3074 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3075 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3076 (const_int 0)))
3077 (clobber (match_scratch:SI 3 "=r,r"))]
3078 "TARGET_32BIT"
3079 "@
3080 %q4. %3,%1,%2
3081 #"
3082 [(set_attr "type" "compare")
3083 (set_attr "length" "4,8")])
3084
3085 (define_split
3086 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3087 (compare:CC (match_operator:SI 4 "boolean_operator"
3088 [(match_operand:SI 1 "gpc_reg_operand" "")
3089 (match_operand:SI 2 "gpc_reg_operand" "")])
3090 (const_int 0)))
3091 (clobber (match_scratch:SI 3 ""))]
3092 "TARGET_32BIT && reload_completed"
3093 [(set (match_dup 3) (match_dup 4))
3094 (set (match_dup 0)
3095 (compare:CC (match_dup 3)
3096 (const_int 0)))]
3097 "")
3098
3099 (define_insn "*boolsi3_internal3"
3100 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3101 (compare:CC (match_operator:SI 4 "boolean_operator"
3102 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3103 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3104 (const_int 0)))
3105 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3106 (match_dup 4))]
3107 "TARGET_32BIT"
3108 "@
3109 %q4. %0,%1,%2
3110 #"
3111 [(set_attr "type" "compare")
3112 (set_attr "length" "4,8")])
3113
3114 (define_split
3115 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3116 (compare:CC (match_operator:SI 4 "boolean_operator"
3117 [(match_operand:SI 1 "gpc_reg_operand" "")
3118 (match_operand:SI 2 "gpc_reg_operand" "")])
3119 (const_int 0)))
3120 (set (match_operand:SI 0 "gpc_reg_operand" "")
3121 (match_dup 4))]
3122 "TARGET_32BIT && reload_completed"
3123 [(set (match_dup 0) (match_dup 4))
3124 (set (match_dup 3)
3125 (compare:CC (match_dup 0)
3126 (const_int 0)))]
3127 "")
3128
3129 ;; Split a logical operation that we can't do in one insn into two insns,
3130 ;; each of which does one 16-bit part. This is used by combine.
3131
3132 (define_split
3133 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3134 (match_operator:SI 3 "boolean_or_operator"
3135 [(match_operand:SI 1 "gpc_reg_operand" "")
3136 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3137 ""
3138 [(set (match_dup 0) (match_dup 4))
3139 (set (match_dup 0) (match_dup 5))]
3140 "
3141 {
3142 rtx i;
3143 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3144 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3145 operands[1], i);
3146 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3147 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3148 operands[0], i);
3149 }")
3150
3151 (define_insn "*boolcsi3_internal1"
3152 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3153 (match_operator:SI 3 "boolean_operator"
3154 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3155 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3156 ""
3157 "%q3 %0,%2,%1")
3158
3159 (define_insn "*boolcsi3_internal2"
3160 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3161 (compare:CC (match_operator:SI 4 "boolean_operator"
3162 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3163 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3164 (const_int 0)))
3165 (clobber (match_scratch:SI 3 "=r,r"))]
3166 "TARGET_32BIT"
3167 "@
3168 %q4. %3,%2,%1
3169 #"
3170 [(set_attr "type" "compare")
3171 (set_attr "length" "4,8")])
3172
3173 (define_split
3174 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3175 (compare:CC (match_operator:SI 4 "boolean_operator"
3176 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3177 (match_operand:SI 2 "gpc_reg_operand" "")])
3178 (const_int 0)))
3179 (clobber (match_scratch:SI 3 ""))]
3180 "TARGET_32BIT && reload_completed"
3181 [(set (match_dup 3) (match_dup 4))
3182 (set (match_dup 0)
3183 (compare:CC (match_dup 3)
3184 (const_int 0)))]
3185 "")
3186
3187 (define_insn "*boolcsi3_internal3"
3188 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3189 (compare:CC (match_operator:SI 4 "boolean_operator"
3190 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3191 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3192 (const_int 0)))
3193 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3194 (match_dup 4))]
3195 "TARGET_32BIT"
3196 "@
3197 %q4. %0,%2,%1
3198 #"
3199 [(set_attr "type" "compare")
3200 (set_attr "length" "4,8")])
3201
3202 (define_split
3203 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3204 (compare:CC (match_operator:SI 4 "boolean_operator"
3205 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3206 (match_operand:SI 2 "gpc_reg_operand" "")])
3207 (const_int 0)))
3208 (set (match_operand:SI 0 "gpc_reg_operand" "")
3209 (match_dup 4))]
3210 "TARGET_32BIT && reload_completed"
3211 [(set (match_dup 0) (match_dup 4))
3212 (set (match_dup 3)
3213 (compare:CC (match_dup 0)
3214 (const_int 0)))]
3215 "")
3216
3217 (define_insn "*boolccsi3_internal1"
3218 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3219 (match_operator:SI 3 "boolean_operator"
3220 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3221 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3222 ""
3223 "%q3 %0,%1,%2")
3224
3225 (define_insn "*boolccsi3_internal2"
3226 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3227 (compare:CC (match_operator:SI 4 "boolean_operator"
3228 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3229 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3230 (const_int 0)))
3231 (clobber (match_scratch:SI 3 "=r,r"))]
3232 "TARGET_32BIT"
3233 "@
3234 %q4. %3,%1,%2
3235 #"
3236 [(set_attr "type" "compare")
3237 (set_attr "length" "4,8")])
3238
3239 (define_split
3240 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3241 (compare:CC (match_operator:SI 4 "boolean_operator"
3242 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3243 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3244 (const_int 0)))
3245 (clobber (match_scratch:SI 3 ""))]
3246 "TARGET_32BIT && reload_completed"
3247 [(set (match_dup 3) (match_dup 4))
3248 (set (match_dup 0)
3249 (compare:CC (match_dup 3)
3250 (const_int 0)))]
3251 "")
3252
3253 (define_insn "*boolccsi3_internal3"
3254 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3255 (compare:CC (match_operator:SI 4 "boolean_operator"
3256 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3257 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3258 (const_int 0)))
3259 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3260 (match_dup 4))]
3261 "TARGET_32BIT"
3262 "@
3263 %q4. %0,%1,%2
3264 #"
3265 [(set_attr "type" "compare")
3266 (set_attr "length" "4,8")])
3267
3268 (define_split
3269 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3270 (compare:CC (match_operator:SI 4 "boolean_operator"
3271 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3272 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3273 (const_int 0)))
3274 (set (match_operand:SI 0 "gpc_reg_operand" "")
3275 (match_dup 4))]
3276 "TARGET_32BIT && reload_completed"
3277 [(set (match_dup 0) (match_dup 4))
3278 (set (match_dup 3)
3279 (compare:CC (match_dup 0)
3280 (const_int 0)))]
3281 "")
3282
3283 ;; maskir insn. We need four forms because things might be in arbitrary
3284 ;; orders. Don't define forms that only set CR fields because these
3285 ;; would modify an input register.
3286
3287 (define_insn "*maskir_internal1"
3288 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3289 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3290 (match_operand:SI 1 "gpc_reg_operand" "0"))
3291 (and:SI (match_dup 2)
3292 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3293 "TARGET_POWER"
3294 "maskir %0,%3,%2")
3295
3296 (define_insn "*maskir_internal2"
3297 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3298 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3299 (match_operand:SI 1 "gpc_reg_operand" "0"))
3300 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3301 (match_dup 2))))]
3302 "TARGET_POWER"
3303 "maskir %0,%3,%2")
3304
3305 (define_insn "*maskir_internal3"
3306 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3307 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3308 (match_operand:SI 3 "gpc_reg_operand" "r"))
3309 (and:SI (not:SI (match_dup 2))
3310 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3311 "TARGET_POWER"
3312 "maskir %0,%3,%2")
3313
3314 (define_insn "*maskir_internal4"
3315 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3316 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3317 (match_operand:SI 2 "gpc_reg_operand" "r"))
3318 (and:SI (not:SI (match_dup 2))
3319 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3320 "TARGET_POWER"
3321 "maskir %0,%3,%2")
3322
3323 (define_insn "*maskir_internal5"
3324 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3325 (compare:CC
3326 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3327 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3328 (and:SI (match_dup 2)
3329 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3330 (const_int 0)))
3331 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3332 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3333 (and:SI (match_dup 2) (match_dup 3))))]
3334 "TARGET_POWER"
3335 "@
3336 maskir. %0,%3,%2
3337 #"
3338 [(set_attr "type" "compare")
3339 (set_attr "length" "4,8")])
3340
3341 (define_split
3342 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3343 (compare:CC
3344 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3345 (match_operand:SI 1 "gpc_reg_operand" ""))
3346 (and:SI (match_dup 2)
3347 (match_operand:SI 3 "gpc_reg_operand" "")))
3348 (const_int 0)))
3349 (set (match_operand:SI 0 "gpc_reg_operand" "")
3350 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3351 (and:SI (match_dup 2) (match_dup 3))))]
3352 "TARGET_POWER && reload_completed"
3353 [(set (match_dup 0)
3354 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3355 (and:SI (match_dup 2) (match_dup 3))))
3356 (set (match_dup 4)
3357 (compare:CC (match_dup 0)
3358 (const_int 0)))]
3359 "")
3360
3361 (define_insn "*maskir_internal6"
3362 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3363 (compare:CC
3364 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3365 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3366 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3367 (match_dup 2)))
3368 (const_int 0)))
3369 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3370 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3371 (and:SI (match_dup 3) (match_dup 2))))]
3372 "TARGET_POWER"
3373 "@
3374 maskir. %0,%3,%2
3375 #"
3376 [(set_attr "type" "compare")
3377 (set_attr "length" "4,8")])
3378
3379 (define_split
3380 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3381 (compare:CC
3382 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3383 (match_operand:SI 1 "gpc_reg_operand" ""))
3384 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3385 (match_dup 2)))
3386 (const_int 0)))
3387 (set (match_operand:SI 0 "gpc_reg_operand" "")
3388 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3389 (and:SI (match_dup 3) (match_dup 2))))]
3390 "TARGET_POWER && reload_completed"
3391 [(set (match_dup 0)
3392 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3393 (and:SI (match_dup 3) (match_dup 2))))
3394 (set (match_dup 4)
3395 (compare:CC (match_dup 0)
3396 (const_int 0)))]
3397 "")
3398
3399 (define_insn "*maskir_internal7"
3400 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3401 (compare:CC
3402 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3403 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3404 (and:SI (not:SI (match_dup 2))
3405 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3406 (const_int 0)))
3407 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3408 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3409 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3410 "TARGET_POWER"
3411 "@
3412 maskir. %0,%3,%2
3413 #"
3414 [(set_attr "type" "compare")
3415 (set_attr "length" "4,8")])
3416
3417 (define_split
3418 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3419 (compare:CC
3420 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3421 (match_operand:SI 3 "gpc_reg_operand" ""))
3422 (and:SI (not:SI (match_dup 2))
3423 (match_operand:SI 1 "gpc_reg_operand" "")))
3424 (const_int 0)))
3425 (set (match_operand:SI 0 "gpc_reg_operand" "")
3426 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3427 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3428 "TARGET_POWER && reload_completed"
3429 [(set (match_dup 0)
3430 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3431 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3432 (set (match_dup 4)
3433 (compare:CC (match_dup 0)
3434 (const_int 0)))]
3435 "")
3436
3437 (define_insn "*maskir_internal8"
3438 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3439 (compare:CC
3440 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3441 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3442 (and:SI (not:SI (match_dup 2))
3443 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3444 (const_int 0)))
3445 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3446 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3447 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3448 "TARGET_POWER"
3449 "@
3450 maskir. %0,%3,%2
3451 #"
3452 [(set_attr "type" "compare")
3453 (set_attr "length" "4,8")])
3454
3455 (define_split
3456 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3457 (compare:CC
3458 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3459 (match_operand:SI 2 "gpc_reg_operand" ""))
3460 (and:SI (not:SI (match_dup 2))
3461 (match_operand:SI 1 "gpc_reg_operand" "")))
3462 (const_int 0)))
3463 (set (match_operand:SI 0 "gpc_reg_operand" "")
3464 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3465 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3466 "TARGET_POWER && reload_completed"
3467 [(set (match_dup 0)
3468 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3469 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3470 (set (match_dup 4)
3471 (compare:CC (match_dup 0)
3472 (const_int 0)))]
3473 "")
3474 \f
3475 ;; Rotate and shift insns, in all their variants. These support shifts,
3476 ;; field inserts and extracts, and various combinations thereof.
3477 (define_expand "insv"
3478 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3479 (match_operand:SI 1 "const_int_operand" "")
3480 (match_operand:SI 2 "const_int_operand" ""))
3481 (match_operand 3 "gpc_reg_operand" ""))]
3482 ""
3483 "
3484 {
3485 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3486 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3487 compiler if the address of the structure is taken later. Likewise, do
3488 not handle invalid E500 subregs. */
3489 if (GET_CODE (operands[0]) == SUBREG
3490 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3491 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3492 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3493 FAIL;
3494
3495 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3496 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3497 else
3498 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3499 DONE;
3500 }")
3501
3502 (define_insn "insvsi"
3503 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3504 (match_operand:SI 1 "const_int_operand" "i")
3505 (match_operand:SI 2 "const_int_operand" "i"))
3506 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3507 ""
3508 "*
3509 {
3510 int start = INTVAL (operands[2]) & 31;
3511 int size = INTVAL (operands[1]) & 31;
3512
3513 operands[4] = GEN_INT (32 - start - size);
3514 operands[1] = GEN_INT (start + size - 1);
3515 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3516 }"
3517 [(set_attr "type" "insert_word")])
3518
3519 (define_insn "*insvsi_internal1"
3520 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3521 (match_operand:SI 1 "const_int_operand" "i")
3522 (match_operand:SI 2 "const_int_operand" "i"))
3523 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3524 (match_operand:SI 4 "const_int_operand" "i")))]
3525 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3526 "*
3527 {
3528 int shift = INTVAL (operands[4]) & 31;
3529 int start = INTVAL (operands[2]) & 31;
3530 int size = INTVAL (operands[1]) & 31;
3531
3532 operands[4] = GEN_INT (shift - start - size);
3533 operands[1] = GEN_INT (start + size - 1);
3534 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3535 }"
3536 [(set_attr "type" "insert_word")])
3537
3538 (define_insn "*insvsi_internal2"
3539 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3540 (match_operand:SI 1 "const_int_operand" "i")
3541 (match_operand:SI 2 "const_int_operand" "i"))
3542 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3543 (match_operand:SI 4 "const_int_operand" "i")))]
3544 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3545 "*
3546 {
3547 int shift = INTVAL (operands[4]) & 31;
3548 int start = INTVAL (operands[2]) & 31;
3549 int size = INTVAL (operands[1]) & 31;
3550
3551 operands[4] = GEN_INT (32 - shift - start - size);
3552 operands[1] = GEN_INT (start + size - 1);
3553 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3554 }"
3555 [(set_attr "type" "insert_word")])
3556
3557 (define_insn "*insvsi_internal3"
3558 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3559 (match_operand:SI 1 "const_int_operand" "i")
3560 (match_operand:SI 2 "const_int_operand" "i"))
3561 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3562 (match_operand:SI 4 "const_int_operand" "i")))]
3563 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3564 "*
3565 {
3566 int shift = INTVAL (operands[4]) & 31;
3567 int start = INTVAL (operands[2]) & 31;
3568 int size = INTVAL (operands[1]) & 31;
3569
3570 operands[4] = GEN_INT (32 - shift - start - size);
3571 operands[1] = GEN_INT (start + size - 1);
3572 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3573 }"
3574 [(set_attr "type" "insert_word")])
3575
3576 (define_insn "*insvsi_internal4"
3577 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3578 (match_operand:SI 1 "const_int_operand" "i")
3579 (match_operand:SI 2 "const_int_operand" "i"))
3580 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3581 (match_operand:SI 4 "const_int_operand" "i")
3582 (match_operand:SI 5 "const_int_operand" "i")))]
3583 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3584 "*
3585 {
3586 int extract_start = INTVAL (operands[5]) & 31;
3587 int extract_size = INTVAL (operands[4]) & 31;
3588 int insert_start = INTVAL (operands[2]) & 31;
3589 int insert_size = INTVAL (operands[1]) & 31;
3590
3591 /* Align extract field with insert field */
3592 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3593 operands[1] = GEN_INT (insert_start + insert_size - 1);
3594 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3595 }"
3596 [(set_attr "type" "insert_word")])
3597
3598 ;; combine patterns for rlwimi
3599 (define_insn "*insvsi_internal5"
3600 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3601 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3602 (match_operand:SI 1 "mask_operand" "i"))
3603 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3604 (match_operand:SI 2 "const_int_operand" "i"))
3605 (match_operand:SI 5 "mask_operand" "i"))))]
3606 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3607 "*
3608 {
3609 int me = extract_ME(operands[5]);
3610 int mb = extract_MB(operands[5]);
3611 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3612 operands[2] = GEN_INT(mb);
3613 operands[1] = GEN_INT(me);
3614 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3615 }"
3616 [(set_attr "type" "insert_word")])
3617
3618 (define_insn "*insvsi_internal6"
3619 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3620 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3621 (match_operand:SI 2 "const_int_operand" "i"))
3622 (match_operand:SI 5 "mask_operand" "i"))
3623 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3624 (match_operand:SI 1 "mask_operand" "i"))))]
3625 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3626 "*
3627 {
3628 int me = extract_ME(operands[5]);
3629 int mb = extract_MB(operands[5]);
3630 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3631 operands[2] = GEN_INT(mb);
3632 operands[1] = GEN_INT(me);
3633 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3634 }"
3635 [(set_attr "type" "insert_word")])
3636
3637 (define_insn "insvdi"
3638 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3639 (match_operand:SI 1 "const_int_operand" "i")
3640 (match_operand:SI 2 "const_int_operand" "i"))
3641 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3642 "TARGET_POWERPC64"
3643 "*
3644 {
3645 int start = INTVAL (operands[2]) & 63;
3646 int size = INTVAL (operands[1]) & 63;
3647
3648 operands[1] = GEN_INT (64 - start - size);
3649 return \"rldimi %0,%3,%H1,%H2\";
3650 }"
3651 [(set_attr "type" "insert_dword")])
3652
3653 (define_insn "*insvdi_internal2"
3654 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3655 (match_operand:SI 1 "const_int_operand" "i")
3656 (match_operand:SI 2 "const_int_operand" "i"))
3657 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3658 (match_operand:SI 4 "const_int_operand" "i")))]
3659 "TARGET_POWERPC64
3660 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3661 "*
3662 {
3663 int shift = INTVAL (operands[4]) & 63;
3664 int start = (INTVAL (operands[2]) & 63) - 32;
3665 int size = INTVAL (operands[1]) & 63;
3666
3667 operands[4] = GEN_INT (64 - shift - start - size);
3668 operands[2] = GEN_INT (start);
3669 operands[1] = GEN_INT (start + size - 1);
3670 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3671 }")
3672
3673 (define_insn "*insvdi_internal3"
3674 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3675 (match_operand:SI 1 "const_int_operand" "i")
3676 (match_operand:SI 2 "const_int_operand" "i"))
3677 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3678 (match_operand:SI 4 "const_int_operand" "i")))]
3679 "TARGET_POWERPC64
3680 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3681 "*
3682 {
3683 int shift = INTVAL (operands[4]) & 63;
3684 int start = (INTVAL (operands[2]) & 63) - 32;
3685 int size = INTVAL (operands[1]) & 63;
3686
3687 operands[4] = GEN_INT (64 - shift - start - size);
3688 operands[2] = GEN_INT (start);
3689 operands[1] = GEN_INT (start + size - 1);
3690 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3691 }")
3692
3693 (define_expand "extzv"
3694 [(set (match_operand 0 "gpc_reg_operand" "")
3695 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3696 (match_operand:SI 2 "const_int_operand" "")
3697 (match_operand:SI 3 "const_int_operand" "")))]
3698 ""
3699 "
3700 {
3701 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3702 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3703 compiler if the address of the structure is taken later. */
3704 if (GET_CODE (operands[0]) == SUBREG
3705 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3706 FAIL;
3707
3708 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3709 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3710 else
3711 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3712 DONE;
3713 }")
3714
3715 (define_insn "extzvsi"
3716 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3717 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3718 (match_operand:SI 2 "const_int_operand" "i")
3719 (match_operand:SI 3 "const_int_operand" "i")))]
3720 ""
3721 "*
3722 {
3723 int start = INTVAL (operands[3]) & 31;
3724 int size = INTVAL (operands[2]) & 31;
3725
3726 if (start + size >= 32)
3727 operands[3] = const0_rtx;
3728 else
3729 operands[3] = GEN_INT (start + size);
3730 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3731 }")
3732
3733 (define_insn "*extzvsi_internal1"
3734 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3735 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3736 (match_operand:SI 2 "const_int_operand" "i,i")
3737 (match_operand:SI 3 "const_int_operand" "i,i"))
3738 (const_int 0)))
3739 (clobber (match_scratch:SI 4 "=r,r"))]
3740 ""
3741 "*
3742 {
3743 int start = INTVAL (operands[3]) & 31;
3744 int size = INTVAL (operands[2]) & 31;
3745
3746 /* Force split for non-cc0 compare. */
3747 if (which_alternative == 1)
3748 return \"#\";
3749
3750 /* If the bit-field being tested fits in the upper or lower half of a
3751 word, it is possible to use andiu. or andil. to test it. This is
3752 useful because the condition register set-use delay is smaller for
3753 andi[ul]. than for rlinm. This doesn't work when the starting bit
3754 position is 0 because the LT and GT bits may be set wrong. */
3755
3756 if ((start > 0 && start + size <= 16) || start >= 16)
3757 {
3758 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3759 - (1 << (16 - (start & 15) - size))));
3760 if (start < 16)
3761 return \"{andiu.|andis.} %4,%1,%3\";
3762 else
3763 return \"{andil.|andi.} %4,%1,%3\";
3764 }
3765
3766 if (start + size >= 32)
3767 operands[3] = const0_rtx;
3768 else
3769 operands[3] = GEN_INT (start + size);
3770 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3771 }"
3772 [(set_attr "type" "delayed_compare")
3773 (set_attr "length" "4,8")])
3774
3775 (define_split
3776 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3777 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3778 (match_operand:SI 2 "const_int_operand" "")
3779 (match_operand:SI 3 "const_int_operand" ""))
3780 (const_int 0)))
3781 (clobber (match_scratch:SI 4 ""))]
3782 "reload_completed"
3783 [(set (match_dup 4)
3784 (zero_extract:SI (match_dup 1) (match_dup 2)
3785 (match_dup 3)))
3786 (set (match_dup 0)
3787 (compare:CC (match_dup 4)
3788 (const_int 0)))]
3789 "")
3790
3791 (define_insn "*extzvsi_internal2"
3792 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3793 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3794 (match_operand:SI 2 "const_int_operand" "i,i")
3795 (match_operand:SI 3 "const_int_operand" "i,i"))
3796 (const_int 0)))
3797 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3798 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3799 ""
3800 "*
3801 {
3802 int start = INTVAL (operands[3]) & 31;
3803 int size = INTVAL (operands[2]) & 31;
3804
3805 /* Force split for non-cc0 compare. */
3806 if (which_alternative == 1)
3807 return \"#\";
3808
3809 /* Since we are using the output value, we can't ignore any need for
3810 a shift. The bit-field must end at the LSB. */
3811 if (start >= 16 && start + size == 32)
3812 {
3813 operands[3] = GEN_INT ((1 << size) - 1);
3814 return \"{andil.|andi.} %0,%1,%3\";
3815 }
3816
3817 if (start + size >= 32)
3818 operands[3] = const0_rtx;
3819 else
3820 operands[3] = GEN_INT (start + size);
3821 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3822 }"
3823 [(set_attr "type" "delayed_compare")
3824 (set_attr "length" "4,8")])
3825
3826 (define_split
3827 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3828 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3829 (match_operand:SI 2 "const_int_operand" "")
3830 (match_operand:SI 3 "const_int_operand" ""))
3831 (const_int 0)))
3832 (set (match_operand:SI 0 "gpc_reg_operand" "")
3833 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3834 "reload_completed"
3835 [(set (match_dup 0)
3836 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3837 (set (match_dup 4)
3838 (compare:CC (match_dup 0)
3839 (const_int 0)))]
3840 "")
3841
3842 (define_insn "extzvdi"
3843 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3844 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3845 (match_operand:SI 2 "const_int_operand" "i")
3846 (match_operand:SI 3 "const_int_operand" "i")))]
3847 "TARGET_POWERPC64"
3848 "*
3849 {
3850 int start = INTVAL (operands[3]) & 63;
3851 int size = INTVAL (operands[2]) & 63;
3852
3853 if (start + size >= 64)
3854 operands[3] = const0_rtx;
3855 else
3856 operands[3] = GEN_INT (start + size);
3857 operands[2] = GEN_INT (64 - size);
3858 return \"rldicl %0,%1,%3,%2\";
3859 }")
3860
3861 (define_insn "*extzvdi_internal1"
3862 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3863 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3864 (match_operand:SI 2 "const_int_operand" "i")
3865 (match_operand:SI 3 "const_int_operand" "i"))
3866 (const_int 0)))
3867 (clobber (match_scratch:DI 4 "=r"))]
3868 "TARGET_64BIT"
3869 "*
3870 {
3871 int start = INTVAL (operands[3]) & 63;
3872 int size = INTVAL (operands[2]) & 63;
3873
3874 if (start + size >= 64)
3875 operands[3] = const0_rtx;
3876 else
3877 operands[3] = GEN_INT (start + size);
3878 operands[2] = GEN_INT (64 - size);
3879 return \"rldicl. %4,%1,%3,%2\";
3880 }"
3881 [(set_attr "type" "compare")])
3882
3883 (define_insn "*extzvdi_internal2"
3884 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3885 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3886 (match_operand:SI 2 "const_int_operand" "i")
3887 (match_operand:SI 3 "const_int_operand" "i"))
3888 (const_int 0)))
3889 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3890 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3891 "TARGET_64BIT"
3892 "*
3893 {
3894 int start = INTVAL (operands[3]) & 63;
3895 int size = INTVAL (operands[2]) & 63;
3896
3897 if (start + size >= 64)
3898 operands[3] = const0_rtx;
3899 else
3900 operands[3] = GEN_INT (start + size);
3901 operands[2] = GEN_INT (64 - size);
3902 return \"rldicl. %0,%1,%3,%2\";
3903 }"
3904 [(set_attr "type" "compare")])
3905
3906 (define_insn "rotlsi3"
3907 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3908 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3909 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
3910 ""
3911 "@
3912 {rlnm|rlwnm} %0,%1,%2,0xffffffff
3913 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
3914 [(set_attr "type" "var_shift_rotate,integer")])
3915
3916 (define_insn "*rotlsi3_internal2"
3917 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3918 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3919 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3920 (const_int 0)))
3921 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3922 ""
3923 "@
3924 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
3925 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
3926 #
3927 #"
3928 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3929 (set_attr "length" "4,4,8,8")])
3930
3931 (define_split
3932 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3933 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3934 (match_operand:SI 2 "reg_or_cint_operand" ""))
3935 (const_int 0)))
3936 (clobber (match_scratch:SI 3 ""))]
3937 "reload_completed"
3938 [(set (match_dup 3)
3939 (rotate:SI (match_dup 1) (match_dup 2)))
3940 (set (match_dup 0)
3941 (compare:CC (match_dup 3)
3942 (const_int 0)))]
3943 "")
3944
3945 (define_insn "*rotlsi3_internal3"
3946 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3947 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3948 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3949 (const_int 0)))
3950 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3951 (rotate:SI (match_dup 1) (match_dup 2)))]
3952 ""
3953 "@
3954 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
3955 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
3956 #
3957 #"
3958 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3959 (set_attr "length" "4,4,8,8")])
3960
3961 (define_split
3962 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3963 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3964 (match_operand:SI 2 "reg_or_cint_operand" ""))
3965 (const_int 0)))
3966 (set (match_operand:SI 0 "gpc_reg_operand" "")
3967 (rotate:SI (match_dup 1) (match_dup 2)))]
3968 "reload_completed"
3969 [(set (match_dup 0)
3970 (rotate:SI (match_dup 1) (match_dup 2)))
3971 (set (match_dup 3)
3972 (compare:CC (match_dup 0)
3973 (const_int 0)))]
3974 "")
3975
3976 (define_insn "*rotlsi3_internal4"
3977 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3978 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3979 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
3980 (match_operand:SI 3 "mask_operand" "n,n")))]
3981 ""
3982 "@
3983 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
3984 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
3985 [(set_attr "type" "var_shift_rotate,integer")])
3986
3987 (define_insn "*rotlsi3_internal5"
3988 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3989 (compare:CC (and:SI
3990 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3991 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3992 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3993 (const_int 0)))
3994 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
3995 ""
3996 "@
3997 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
3998 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3999 #
4000 #"
4001 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4002 (set_attr "length" "4,4,8,8")])
4003
4004 (define_split
4005 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4006 (compare:CC (and:SI
4007 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4008 (match_operand:SI 2 "reg_or_cint_operand" ""))
4009 (match_operand:SI 3 "mask_operand" ""))
4010 (const_int 0)))
4011 (clobber (match_scratch:SI 4 ""))]
4012 "reload_completed"
4013 [(set (match_dup 4)
4014 (and:SI (rotate:SI (match_dup 1)
4015 (match_dup 2))
4016 (match_dup 3)))
4017 (set (match_dup 0)
4018 (compare:CC (match_dup 4)
4019 (const_int 0)))]
4020 "")
4021
4022 (define_insn "*rotlsi3_internal6"
4023 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
4024 (compare:CC (and:SI
4025 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4026 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4027 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4028 (const_int 0)))
4029 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4030 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4031 ""
4032 "@
4033 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
4034 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4035 #
4036 #"
4037 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4038 (set_attr "length" "4,4,8,8")])
4039
4040 (define_split
4041 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4042 (compare:CC (and:SI
4043 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4044 (match_operand:SI 2 "reg_or_cint_operand" ""))
4045 (match_operand:SI 3 "mask_operand" ""))
4046 (const_int 0)))
4047 (set (match_operand:SI 0 "gpc_reg_operand" "")
4048 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4049 "reload_completed"
4050 [(set (match_dup 0)
4051 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4052 (set (match_dup 4)
4053 (compare:CC (match_dup 0)
4054 (const_int 0)))]
4055 "")
4056
4057 (define_insn "*rotlsi3_internal7"
4058 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4059 (zero_extend:SI
4060 (subreg:QI
4061 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4062 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4063 ""
4064 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
4065
4066 (define_insn "*rotlsi3_internal8"
4067 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4068 (compare:CC (zero_extend:SI
4069 (subreg:QI
4070 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4071 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4072 (const_int 0)))
4073 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4074 ""
4075 "@
4076 {rlnm.|rlwnm.} %3,%1,%2,0xff
4077 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4078 #
4079 #"
4080 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4081 (set_attr "length" "4,4,8,8")])
4082
4083 (define_split
4084 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4085 (compare:CC (zero_extend:SI
4086 (subreg:QI
4087 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4088 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4089 (const_int 0)))
4090 (clobber (match_scratch:SI 3 ""))]
4091 "reload_completed"
4092 [(set (match_dup 3)
4093 (zero_extend:SI (subreg:QI
4094 (rotate:SI (match_dup 1)
4095 (match_dup 2)) 0)))
4096 (set (match_dup 0)
4097 (compare:CC (match_dup 3)
4098 (const_int 0)))]
4099 "")
4100
4101 (define_insn "*rotlsi3_internal9"
4102 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4103 (compare:CC (zero_extend:SI
4104 (subreg:QI
4105 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4106 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4107 (const_int 0)))
4108 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4109 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4110 ""
4111 "@
4112 {rlnm.|rlwnm.} %0,%1,%2,0xff
4113 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4114 #
4115 #"
4116 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4117 (set_attr "length" "4,4,8,8")])
4118
4119 (define_split
4120 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4121 (compare:CC (zero_extend:SI
4122 (subreg:QI
4123 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4124 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4125 (const_int 0)))
4126 (set (match_operand:SI 0 "gpc_reg_operand" "")
4127 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4128 "reload_completed"
4129 [(set (match_dup 0)
4130 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4131 (set (match_dup 3)
4132 (compare:CC (match_dup 0)
4133 (const_int 0)))]
4134 "")
4135
4136 (define_insn "*rotlsi3_internal10"
4137 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4138 (zero_extend:SI
4139 (subreg:HI
4140 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4141 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4142 ""
4143 "@
4144 {rlnm|rlwnm} %0,%1,%2,0xffff
4145 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4146 [(set_attr "type" "var_shift_rotate,integer")])
4147
4148
4149 (define_insn "*rotlsi3_internal11"
4150 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4151 (compare:CC (zero_extend:SI
4152 (subreg:HI
4153 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4154 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4155 (const_int 0)))
4156 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4157 ""
4158 "@
4159 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4160 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4161 #
4162 #"
4163 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4164 (set_attr "length" "4,4,8,8")])
4165
4166 (define_split
4167 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4168 (compare:CC (zero_extend:SI
4169 (subreg:HI
4170 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4171 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4172 (const_int 0)))
4173 (clobber (match_scratch:SI 3 ""))]
4174 "reload_completed"
4175 [(set (match_dup 3)
4176 (zero_extend:SI (subreg:HI
4177 (rotate:SI (match_dup 1)
4178 (match_dup 2)) 0)))
4179 (set (match_dup 0)
4180 (compare:CC (match_dup 3)
4181 (const_int 0)))]
4182 "")
4183
4184 (define_insn "*rotlsi3_internal12"
4185 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4186 (compare:CC (zero_extend:SI
4187 (subreg:HI
4188 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4189 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4190 (const_int 0)))
4191 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4192 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4193 ""
4194 "@
4195 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4196 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4197 #
4198 #"
4199 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4200 (set_attr "length" "4,4,8,8")])
4201
4202 (define_split
4203 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4204 (compare:CC (zero_extend:SI
4205 (subreg:HI
4206 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4207 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4208 (const_int 0)))
4209 (set (match_operand:SI 0 "gpc_reg_operand" "")
4210 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4211 "reload_completed"
4212 [(set (match_dup 0)
4213 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4214 (set (match_dup 3)
4215 (compare:CC (match_dup 0)
4216 (const_int 0)))]
4217 "")
4218
4219 ;; Note that we use "sle." instead of "sl." so that we can set
4220 ;; SHIFT_COUNT_TRUNCATED.
4221
4222 (define_expand "ashlsi3"
4223 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4224 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4225 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4226 ""
4227 "
4228 {
4229 if (TARGET_POWER)
4230 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4231 else
4232 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4233 DONE;
4234 }")
4235
4236 (define_insn "ashlsi3_power"
4237 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4238 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4239 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4240 (clobber (match_scratch:SI 3 "=q,X"))]
4241 "TARGET_POWER"
4242 "@
4243 sle %0,%1,%2
4244 {sli|slwi} %0,%1,%h2")
4245
4246 (define_insn "ashlsi3_no_power"
4247 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4248 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4249 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4250 "! TARGET_POWER"
4251 "@
4252 {sl|slw} %0,%1,%2
4253 {sli|slwi} %0,%1,%h2"
4254 [(set_attr "type" "var_shift_rotate,shift")])
4255
4256 (define_insn ""
4257 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4258 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4259 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4260 (const_int 0)))
4261 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4262 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4263 "TARGET_POWER"
4264 "@
4265 sle. %3,%1,%2
4266 {sli.|slwi.} %3,%1,%h2
4267 #
4268 #"
4269 [(set_attr "type" "delayed_compare")
4270 (set_attr "length" "4,4,8,8")])
4271
4272 (define_split
4273 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4274 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4275 (match_operand:SI 2 "reg_or_cint_operand" ""))
4276 (const_int 0)))
4277 (clobber (match_scratch:SI 3 ""))
4278 (clobber (match_scratch:SI 4 ""))]
4279 "TARGET_POWER && reload_completed"
4280 [(parallel [(set (match_dup 3)
4281 (ashift:SI (match_dup 1) (match_dup 2)))
4282 (clobber (match_dup 4))])
4283 (set (match_dup 0)
4284 (compare:CC (match_dup 3)
4285 (const_int 0)))]
4286 "")
4287
4288 (define_insn ""
4289 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4290 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4291 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4292 (const_int 0)))
4293 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4294 "! TARGET_POWER && TARGET_32BIT"
4295 "@
4296 {sl.|slw.} %3,%1,%2
4297 {sli.|slwi.} %3,%1,%h2
4298 #
4299 #"
4300 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4301 (set_attr "length" "4,4,8,8")])
4302
4303 (define_split
4304 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4305 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4306 (match_operand:SI 2 "reg_or_cint_operand" ""))
4307 (const_int 0)))
4308 (clobber (match_scratch:SI 3 ""))]
4309 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4310 [(set (match_dup 3)
4311 (ashift:SI (match_dup 1) (match_dup 2)))
4312 (set (match_dup 0)
4313 (compare:CC (match_dup 3)
4314 (const_int 0)))]
4315 "")
4316
4317 (define_insn ""
4318 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4319 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4320 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4321 (const_int 0)))
4322 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4323 (ashift:SI (match_dup 1) (match_dup 2)))
4324 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4325 "TARGET_POWER"
4326 "@
4327 sle. %0,%1,%2
4328 {sli.|slwi.} %0,%1,%h2
4329 #
4330 #"
4331 [(set_attr "type" "delayed_compare")
4332 (set_attr "length" "4,4,8,8")])
4333
4334 (define_split
4335 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4336 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4337 (match_operand:SI 2 "reg_or_cint_operand" ""))
4338 (const_int 0)))
4339 (set (match_operand:SI 0 "gpc_reg_operand" "")
4340 (ashift:SI (match_dup 1) (match_dup 2)))
4341 (clobber (match_scratch:SI 4 ""))]
4342 "TARGET_POWER && reload_completed"
4343 [(parallel [(set (match_dup 0)
4344 (ashift:SI (match_dup 1) (match_dup 2)))
4345 (clobber (match_dup 4))])
4346 (set (match_dup 3)
4347 (compare:CC (match_dup 0)
4348 (const_int 0)))]
4349 "")
4350
4351 (define_insn ""
4352 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4353 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4354 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4355 (const_int 0)))
4356 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4357 (ashift:SI (match_dup 1) (match_dup 2)))]
4358 "! TARGET_POWER && TARGET_32BIT"
4359 "@
4360 {sl.|slw.} %0,%1,%2
4361 {sli.|slwi.} %0,%1,%h2
4362 #
4363 #"
4364 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4365 (set_attr "length" "4,4,8,8")])
4366
4367 (define_split
4368 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4369 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4370 (match_operand:SI 2 "reg_or_cint_operand" ""))
4371 (const_int 0)))
4372 (set (match_operand:SI 0 "gpc_reg_operand" "")
4373 (ashift:SI (match_dup 1) (match_dup 2)))]
4374 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4375 [(set (match_dup 0)
4376 (ashift:SI (match_dup 1) (match_dup 2)))
4377 (set (match_dup 3)
4378 (compare:CC (match_dup 0)
4379 (const_int 0)))]
4380 "")
4381
4382 (define_insn "rlwinm"
4383 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4384 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4385 (match_operand:SI 2 "const_int_operand" "i"))
4386 (match_operand:SI 3 "mask_operand" "n")))]
4387 "includes_lshift_p (operands[2], operands[3])"
4388 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4389
4390 (define_insn ""
4391 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4392 (compare:CC
4393 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4394 (match_operand:SI 2 "const_int_operand" "i,i"))
4395 (match_operand:SI 3 "mask_operand" "n,n"))
4396 (const_int 0)))
4397 (clobber (match_scratch:SI 4 "=r,r"))]
4398 "includes_lshift_p (operands[2], operands[3])"
4399 "@
4400 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4401 #"
4402 [(set_attr "type" "delayed_compare")
4403 (set_attr "length" "4,8")])
4404
4405 (define_split
4406 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4407 (compare:CC
4408 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4409 (match_operand:SI 2 "const_int_operand" ""))
4410 (match_operand:SI 3 "mask_operand" ""))
4411 (const_int 0)))
4412 (clobber (match_scratch:SI 4 ""))]
4413 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4414 [(set (match_dup 4)
4415 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4416 (match_dup 3)))
4417 (set (match_dup 0)
4418 (compare:CC (match_dup 4)
4419 (const_int 0)))]
4420 "")
4421
4422 (define_insn ""
4423 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4424 (compare:CC
4425 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4426 (match_operand:SI 2 "const_int_operand" "i,i"))
4427 (match_operand:SI 3 "mask_operand" "n,n"))
4428 (const_int 0)))
4429 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4430 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4431 "includes_lshift_p (operands[2], operands[3])"
4432 "@
4433 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4434 #"
4435 [(set_attr "type" "delayed_compare")
4436 (set_attr "length" "4,8")])
4437
4438 (define_split
4439 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4440 (compare:CC
4441 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4442 (match_operand:SI 2 "const_int_operand" ""))
4443 (match_operand:SI 3 "mask_operand" ""))
4444 (const_int 0)))
4445 (set (match_operand:SI 0 "gpc_reg_operand" "")
4446 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4447 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4448 [(set (match_dup 0)
4449 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4450 (set (match_dup 4)
4451 (compare:CC (match_dup 0)
4452 (const_int 0)))]
4453 "")
4454
4455 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
4456 ;; "sli x,x,0".
4457 (define_expand "lshrsi3"
4458 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4459 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4460 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4461 ""
4462 "
4463 {
4464 if (TARGET_POWER)
4465 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4466 else
4467 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
4468 DONE;
4469 }")
4470
4471 (define_insn "lshrsi3_power"
4472 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4473 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4474 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4475 (clobber (match_scratch:SI 3 "=q,X,X"))]
4476 "TARGET_POWER"
4477 "@
4478 sre %0,%1,%2
4479 mr %0,%1
4480 {s%A2i|s%A2wi} %0,%1,%h2")
4481
4482 (define_insn "lshrsi3_no_power"
4483 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4484 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4485 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
4486 "! TARGET_POWER"
4487 "@
4488 mr %0,%1
4489 {sr|srw} %0,%1,%2
4490 {sri|srwi} %0,%1,%h2"
4491 [(set_attr "type" "integer,var_shift_rotate,shift")])
4492
4493 (define_insn ""
4494 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4495 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4496 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4497 (const_int 0)))
4498 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4499 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4500 "TARGET_POWER"
4501 "@
4502 sre. %3,%1,%2
4503 mr. %1,%1
4504 {s%A2i.|s%A2wi.} %3,%1,%h2
4505 #
4506 #
4507 #"
4508 [(set_attr "type" "delayed_compare")
4509 (set_attr "length" "4,4,4,8,8,8")])
4510
4511 (define_split
4512 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4513 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4514 (match_operand:SI 2 "reg_or_cint_operand" ""))
4515 (const_int 0)))
4516 (clobber (match_scratch:SI 3 ""))
4517 (clobber (match_scratch:SI 4 ""))]
4518 "TARGET_POWER && reload_completed"
4519 [(parallel [(set (match_dup 3)
4520 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4521 (clobber (match_dup 4))])
4522 (set (match_dup 0)
4523 (compare:CC (match_dup 3)
4524 (const_int 0)))]
4525 "")
4526
4527 (define_insn ""
4528 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4529 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4530 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4531 (const_int 0)))
4532 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4533 "! TARGET_POWER && TARGET_32BIT"
4534 "@
4535 mr. %1,%1
4536 {sr.|srw.} %3,%1,%2
4537 {sri.|srwi.} %3,%1,%h2
4538 #
4539 #
4540 #"
4541 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4542 (set_attr "length" "4,4,4,8,8,8")])
4543
4544 (define_split
4545 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4546 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4547 (match_operand:SI 2 "reg_or_cint_operand" ""))
4548 (const_int 0)))
4549 (clobber (match_scratch:SI 3 ""))]
4550 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4551 [(set (match_dup 3)
4552 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4553 (set (match_dup 0)
4554 (compare:CC (match_dup 3)
4555 (const_int 0)))]
4556 "")
4557
4558 (define_insn ""
4559 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4560 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4561 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4562 (const_int 0)))
4563 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4564 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4565 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4566 "TARGET_POWER"
4567 "@
4568 sre. %0,%1,%2
4569 mr. %0,%1
4570 {s%A2i.|s%A2wi.} %0,%1,%h2
4571 #
4572 #
4573 #"
4574 [(set_attr "type" "delayed_compare")
4575 (set_attr "length" "4,4,4,8,8,8")])
4576
4577 (define_split
4578 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4579 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4580 (match_operand:SI 2 "reg_or_cint_operand" ""))
4581 (const_int 0)))
4582 (set (match_operand:SI 0 "gpc_reg_operand" "")
4583 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4584 (clobber (match_scratch:SI 4 ""))]
4585 "TARGET_POWER && reload_completed"
4586 [(parallel [(set (match_dup 0)
4587 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4588 (clobber (match_dup 4))])
4589 (set (match_dup 3)
4590 (compare:CC (match_dup 0)
4591 (const_int 0)))]
4592 "")
4593
4594 (define_insn ""
4595 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4596 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4597 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4598 (const_int 0)))
4599 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4600 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4601 "! TARGET_POWER && TARGET_32BIT"
4602 "@
4603 mr. %0,%1
4604 {sr.|srw.} %0,%1,%2
4605 {sri.|srwi.} %0,%1,%h2
4606 #
4607 #
4608 #"
4609 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4610 (set_attr "length" "4,4,4,8,8,8")])
4611
4612 (define_split
4613 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4614 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4615 (match_operand:SI 2 "reg_or_cint_operand" ""))
4616 (const_int 0)))
4617 (set (match_operand:SI 0 "gpc_reg_operand" "")
4618 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4619 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4620 [(set (match_dup 0)
4621 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4622 (set (match_dup 3)
4623 (compare:CC (match_dup 0)
4624 (const_int 0)))]
4625 "")
4626
4627 (define_insn ""
4628 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4629 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4630 (match_operand:SI 2 "const_int_operand" "i"))
4631 (match_operand:SI 3 "mask_operand" "n")))]
4632 "includes_rshift_p (operands[2], operands[3])"
4633 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4634
4635 (define_insn ""
4636 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4637 (compare:CC
4638 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4639 (match_operand:SI 2 "const_int_operand" "i,i"))
4640 (match_operand:SI 3 "mask_operand" "n,n"))
4641 (const_int 0)))
4642 (clobber (match_scratch:SI 4 "=r,r"))]
4643 "includes_rshift_p (operands[2], operands[3])"
4644 "@
4645 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4646 #"
4647 [(set_attr "type" "delayed_compare")
4648 (set_attr "length" "4,8")])
4649
4650 (define_split
4651 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4652 (compare:CC
4653 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4654 (match_operand:SI 2 "const_int_operand" ""))
4655 (match_operand:SI 3 "mask_operand" ""))
4656 (const_int 0)))
4657 (clobber (match_scratch:SI 4 ""))]
4658 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4659 [(set (match_dup 4)
4660 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4661 (match_dup 3)))
4662 (set (match_dup 0)
4663 (compare:CC (match_dup 4)
4664 (const_int 0)))]
4665 "")
4666
4667 (define_insn ""
4668 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4669 (compare:CC
4670 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4671 (match_operand:SI 2 "const_int_operand" "i,i"))
4672 (match_operand:SI 3 "mask_operand" "n,n"))
4673 (const_int 0)))
4674 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4675 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4676 "includes_rshift_p (operands[2], operands[3])"
4677 "@
4678 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4679 #"
4680 [(set_attr "type" "delayed_compare")
4681 (set_attr "length" "4,8")])
4682
4683 (define_split
4684 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4685 (compare:CC
4686 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4687 (match_operand:SI 2 "const_int_operand" ""))
4688 (match_operand:SI 3 "mask_operand" ""))
4689 (const_int 0)))
4690 (set (match_operand:SI 0 "gpc_reg_operand" "")
4691 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4692 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4693 [(set (match_dup 0)
4694 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4695 (set (match_dup 4)
4696 (compare:CC (match_dup 0)
4697 (const_int 0)))]
4698 "")
4699
4700 (define_insn ""
4701 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4702 (zero_extend:SI
4703 (subreg:QI
4704 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4705 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4706 "includes_rshift_p (operands[2], GEN_INT (255))"
4707 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4708
4709 (define_insn ""
4710 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4711 (compare:CC
4712 (zero_extend:SI
4713 (subreg:QI
4714 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4715 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4716 (const_int 0)))
4717 (clobber (match_scratch:SI 3 "=r,r"))]
4718 "includes_rshift_p (operands[2], GEN_INT (255))"
4719 "@
4720 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4721 #"
4722 [(set_attr "type" "delayed_compare")
4723 (set_attr "length" "4,8")])
4724
4725 (define_split
4726 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4727 (compare:CC
4728 (zero_extend:SI
4729 (subreg:QI
4730 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4731 (match_operand:SI 2 "const_int_operand" "")) 0))
4732 (const_int 0)))
4733 (clobber (match_scratch:SI 3 ""))]
4734 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4735 [(set (match_dup 3)
4736 (zero_extend:SI (subreg:QI
4737 (lshiftrt:SI (match_dup 1)
4738 (match_dup 2)) 0)))
4739 (set (match_dup 0)
4740 (compare:CC (match_dup 3)
4741 (const_int 0)))]
4742 "")
4743
4744 (define_insn ""
4745 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4746 (compare:CC
4747 (zero_extend:SI
4748 (subreg:QI
4749 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4750 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4751 (const_int 0)))
4752 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4753 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4754 "includes_rshift_p (operands[2], GEN_INT (255))"
4755 "@
4756 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4757 #"
4758 [(set_attr "type" "delayed_compare")
4759 (set_attr "length" "4,8")])
4760
4761 (define_split
4762 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4763 (compare:CC
4764 (zero_extend:SI
4765 (subreg:QI
4766 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4767 (match_operand:SI 2 "const_int_operand" "")) 0))
4768 (const_int 0)))
4769 (set (match_operand:SI 0 "gpc_reg_operand" "")
4770 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4771 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4772 [(set (match_dup 0)
4773 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4774 (set (match_dup 3)
4775 (compare:CC (match_dup 0)
4776 (const_int 0)))]
4777 "")
4778
4779 (define_insn ""
4780 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4781 (zero_extend:SI
4782 (subreg:HI
4783 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4784 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4785 "includes_rshift_p (operands[2], GEN_INT (65535))"
4786 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4787
4788 (define_insn ""
4789 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4790 (compare:CC
4791 (zero_extend:SI
4792 (subreg:HI
4793 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4794 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4795 (const_int 0)))
4796 (clobber (match_scratch:SI 3 "=r,r"))]
4797 "includes_rshift_p (operands[2], GEN_INT (65535))"
4798 "@
4799 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4800 #"
4801 [(set_attr "type" "delayed_compare")
4802 (set_attr "length" "4,8")])
4803
4804 (define_split
4805 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4806 (compare:CC
4807 (zero_extend:SI
4808 (subreg:HI
4809 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4810 (match_operand:SI 2 "const_int_operand" "")) 0))
4811 (const_int 0)))
4812 (clobber (match_scratch:SI 3 ""))]
4813 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4814 [(set (match_dup 3)
4815 (zero_extend:SI (subreg:HI
4816 (lshiftrt:SI (match_dup 1)
4817 (match_dup 2)) 0)))
4818 (set (match_dup 0)
4819 (compare:CC (match_dup 3)
4820 (const_int 0)))]
4821 "")
4822
4823 (define_insn ""
4824 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4825 (compare:CC
4826 (zero_extend:SI
4827 (subreg:HI
4828 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4829 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4830 (const_int 0)))
4831 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4832 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4833 "includes_rshift_p (operands[2], GEN_INT (65535))"
4834 "@
4835 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4836 #"
4837 [(set_attr "type" "delayed_compare")
4838 (set_attr "length" "4,8")])
4839
4840 (define_split
4841 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4842 (compare:CC
4843 (zero_extend:SI
4844 (subreg:HI
4845 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4846 (match_operand:SI 2 "const_int_operand" "")) 0))
4847 (const_int 0)))
4848 (set (match_operand:SI 0 "gpc_reg_operand" "")
4849 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4850 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4851 [(set (match_dup 0)
4852 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4853 (set (match_dup 3)
4854 (compare:CC (match_dup 0)
4855 (const_int 0)))]
4856 "")
4857
4858 (define_insn ""
4859 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4860 (const_int 1)
4861 (match_operand:SI 1 "gpc_reg_operand" "r"))
4862 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4863 (const_int 31)))]
4864 "TARGET_POWER"
4865 "rrib %0,%1,%2")
4866
4867 (define_insn ""
4868 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4869 (const_int 1)
4870 (match_operand:SI 1 "gpc_reg_operand" "r"))
4871 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4872 (const_int 31)))]
4873 "TARGET_POWER"
4874 "rrib %0,%1,%2")
4875
4876 (define_insn ""
4877 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4878 (const_int 1)
4879 (match_operand:SI 1 "gpc_reg_operand" "r"))
4880 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4881 (const_int 1)
4882 (const_int 0)))]
4883 "TARGET_POWER"
4884 "rrib %0,%1,%2")
4885
4886 (define_expand "ashrsi3"
4887 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4888 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4889 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4890 ""
4891 "
4892 {
4893 if (TARGET_POWER)
4894 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4895 else
4896 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4897 DONE;
4898 }")
4899
4900 (define_insn "ashrsi3_power"
4901 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4902 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4903 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4904 (clobber (match_scratch:SI 3 "=q,X"))]
4905 "TARGET_POWER"
4906 "@
4907 srea %0,%1,%2
4908 {srai|srawi} %0,%1,%h2"
4909 [(set_attr "type" "shift")])
4910
4911 (define_insn "ashrsi3_no_power"
4912 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4913 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4914 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4915 "! TARGET_POWER"
4916 "@
4917 {sra|sraw} %0,%1,%2
4918 {srai|srawi} %0,%1,%h2"
4919 [(set_attr "type" "var_shift_rotate,shift")])
4920
4921 (define_insn ""
4922 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4923 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4924 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4925 (const_int 0)))
4926 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4927 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4928 "TARGET_POWER"
4929 "@
4930 srea. %3,%1,%2
4931 {srai.|srawi.} %3,%1,%h2
4932 #
4933 #"
4934 [(set_attr "type" "delayed_compare")
4935 (set_attr "length" "4,4,8,8")])
4936
4937 (define_split
4938 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4939 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4940 (match_operand:SI 2 "reg_or_cint_operand" ""))
4941 (const_int 0)))
4942 (clobber (match_scratch:SI 3 ""))
4943 (clobber (match_scratch:SI 4 ""))]
4944 "TARGET_POWER && reload_completed"
4945 [(parallel [(set (match_dup 3)
4946 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4947 (clobber (match_dup 4))])
4948 (set (match_dup 0)
4949 (compare:CC (match_dup 3)
4950 (const_int 0)))]
4951 "")
4952
4953 (define_insn ""
4954 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4955 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4956 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4957 (const_int 0)))
4958 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4959 "! TARGET_POWER"
4960 "@
4961 {sra.|sraw.} %3,%1,%2
4962 {srai.|srawi.} %3,%1,%h2
4963 #
4964 #"
4965 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4966 (set_attr "length" "4,4,8,8")])
4967
4968 (define_split
4969 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4970 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4971 (match_operand:SI 2 "reg_or_cint_operand" ""))
4972 (const_int 0)))
4973 (clobber (match_scratch:SI 3 ""))]
4974 "! TARGET_POWER && reload_completed"
4975 [(set (match_dup 3)
4976 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4977 (set (match_dup 0)
4978 (compare:CC (match_dup 3)
4979 (const_int 0)))]
4980 "")
4981
4982 (define_insn ""
4983 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4984 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4985 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4986 (const_int 0)))
4987 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4988 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4989 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4990 "TARGET_POWER"
4991 "@
4992 srea. %0,%1,%2
4993 {srai.|srawi.} %0,%1,%h2
4994 #
4995 #"
4996 [(set_attr "type" "delayed_compare")
4997 (set_attr "length" "4,4,8,8")])
4998
4999 (define_split
5000 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5001 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5002 (match_operand:SI 2 "reg_or_cint_operand" ""))
5003 (const_int 0)))
5004 (set (match_operand:SI 0 "gpc_reg_operand" "")
5005 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5006 (clobber (match_scratch:SI 4 ""))]
5007 "TARGET_POWER && reload_completed"
5008 [(parallel [(set (match_dup 0)
5009 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5010 (clobber (match_dup 4))])
5011 (set (match_dup 3)
5012 (compare:CC (match_dup 0)
5013 (const_int 0)))]
5014 "")
5015
5016 (define_insn ""
5017 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5018 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5019 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5020 (const_int 0)))
5021 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5022 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5023 "! TARGET_POWER"
5024 "@
5025 {sra.|sraw.} %0,%1,%2
5026 {srai.|srawi.} %0,%1,%h2
5027 #
5028 #"
5029 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5030 (set_attr "length" "4,4,8,8")])
5031 \f
5032 (define_split
5033 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5034 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5035 (match_operand:SI 2 "reg_or_cint_operand" ""))
5036 (const_int 0)))
5037 (set (match_operand:SI 0 "gpc_reg_operand" "")
5038 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5039 "! TARGET_POWER && reload_completed"
5040 [(set (match_dup 0)
5041 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5042 (set (match_dup 3)
5043 (compare:CC (match_dup 0)
5044 (const_int 0)))]
5045 "")
5046
5047 ;; Floating-point insns, excluding normal data motion.
5048 ;;
5049 ;; PowerPC has a full set of single-precision floating point instructions.
5050 ;;
5051 ;; For the POWER architecture, we pretend that we have both SFmode and
5052 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
5053 ;; The only conversions we will do will be when storing to memory. In that
5054 ;; case, we will use the "frsp" instruction before storing.
5055 ;;
5056 ;; Note that when we store into a single-precision memory location, we need to
5057 ;; use the frsp insn first. If the register being stored isn't dead, we
5058 ;; need a scratch register for the frsp. But this is difficult when the store
5059 ;; is done by reload. It is not incorrect to do the frsp on the register in
5060 ;; this case, we just lose precision that we would have otherwise gotten but
5061 ;; is not guaranteed. Perhaps this should be tightened up at some point.
5062
5063 (define_expand "extendsfdf2"
5064 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5065 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5066 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5067 "")
5068
5069 (define_insn_and_split "*extendsfdf2_fpr"
5070 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
5071 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
5072 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5073 "@
5074 #
5075 fmr %0,%1
5076 lfs%U1%X1 %0,%1"
5077 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5078 [(const_int 0)]
5079 {
5080 emit_note (NOTE_INSN_DELETED);
5081 DONE;
5082 }
5083 [(set_attr "type" "fp,fp,fpload")])
5084
5085 (define_expand "truncdfsf2"
5086 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5087 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5088 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5089 "")
5090
5091 (define_insn "*truncdfsf2_fpr"
5092 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5093 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5094 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5095 "frsp %0,%1"
5096 [(set_attr "type" "fp")])
5097
5098 (define_insn "aux_truncdfsf2"
5099 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5100 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
5101 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5102 "frsp %0,%1"
5103 [(set_attr "type" "fp")])
5104
5105 (define_expand "negsf2"
5106 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5107 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5108 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5109 "")
5110
5111 (define_insn "*negsf2"
5112 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5113 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5114 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5115 "fneg %0,%1"
5116 [(set_attr "type" "fp")])
5117
5118 (define_expand "abssf2"
5119 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5120 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5121 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5122 "")
5123
5124 (define_insn "*abssf2"
5125 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5126 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5127 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5128 "fabs %0,%1"
5129 [(set_attr "type" "fp")])
5130
5131 (define_insn ""
5132 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5133 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
5134 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5135 "fnabs %0,%1"
5136 [(set_attr "type" "fp")])
5137
5138 (define_expand "addsf3"
5139 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5140 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5141 (match_operand:SF 2 "gpc_reg_operand" "")))]
5142 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5143 "")
5144
5145 (define_insn ""
5146 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5147 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5148 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5149 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5150 "fadds %0,%1,%2"
5151 [(set_attr "type" "fp")])
5152
5153 (define_insn ""
5154 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5155 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5156 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5157 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5158 "{fa|fadd} %0,%1,%2"
5159 [(set_attr "type" "fp")])
5160
5161 (define_expand "subsf3"
5162 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5163 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5164 (match_operand:SF 2 "gpc_reg_operand" "")))]
5165 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5166 "")
5167
5168 (define_insn ""
5169 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5170 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5171 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5172 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5173 "fsubs %0,%1,%2"
5174 [(set_attr "type" "fp")])
5175
5176 (define_insn ""
5177 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5178 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5179 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5180 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5181 "{fs|fsub} %0,%1,%2"
5182 [(set_attr "type" "fp")])
5183
5184 (define_expand "mulsf3"
5185 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5186 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5187 (match_operand:SF 2 "gpc_reg_operand" "")))]
5188 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5189 "")
5190
5191 (define_insn ""
5192 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5193 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5194 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5195 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5196 "fmuls %0,%1,%2"
5197 [(set_attr "type" "fp")])
5198
5199 (define_insn ""
5200 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5201 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5202 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5203 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5204 "{fm|fmul} %0,%1,%2"
5205 [(set_attr "type" "dmul")])
5206
5207 (define_expand "divsf3"
5208 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5209 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5210 (match_operand:SF 2 "gpc_reg_operand" "")))]
5211 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5212 "")
5213
5214 (define_insn ""
5215 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5216 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5217 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5218 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5219 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5220 "fdivs %0,%1,%2"
5221 [(set_attr "type" "sdiv")])
5222
5223 (define_insn ""
5224 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5225 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5226 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5227 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5228 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5229 "{fd|fdiv} %0,%1,%2"
5230 [(set_attr "type" "ddiv")])
5231
5232 (define_expand "recipsf3"
5233 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5234 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")
5235 (match_operand:SF 2 "gpc_reg_operand" "f")]
5236 UNSPEC_FRES))]
5237 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5238 && flag_finite_math_only && !flag_trapping_math"
5239 {
5240 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5241 DONE;
5242 })
5243
5244 (define_insn "fres"
5245 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5246 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5247 "TARGET_PPC_GFXOPT && flag_finite_math_only"
5248 "fres %0,%1"
5249 [(set_attr "type" "fp")])
5250
5251 (define_insn ""
5252 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5253 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5254 (match_operand:SF 2 "gpc_reg_operand" "f"))
5255 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5256 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5257 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5258 "fmadds %0,%1,%2,%3"
5259 [(set_attr "type" "fp")])
5260
5261 (define_insn ""
5262 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5263 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5264 (match_operand:SF 2 "gpc_reg_operand" "f"))
5265 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5266 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5267 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5268 "{fma|fmadd} %0,%1,%2,%3"
5269 [(set_attr "type" "dmul")])
5270
5271 (define_insn ""
5272 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5273 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5274 (match_operand:SF 2 "gpc_reg_operand" "f"))
5275 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5276 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5277 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5278 "fmsubs %0,%1,%2,%3"
5279 [(set_attr "type" "fp")])
5280
5281 (define_insn ""
5282 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5283 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5284 (match_operand:SF 2 "gpc_reg_operand" "f"))
5285 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5286 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5287 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5288 "{fms|fmsub} %0,%1,%2,%3"
5289 [(set_attr "type" "dmul")])
5290
5291 (define_insn ""
5292 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5293 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5294 (match_operand:SF 2 "gpc_reg_operand" "f"))
5295 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5296 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5297 && TARGET_SINGLE_FLOAT && HONOR_SIGNED_ZEROS (SFmode)"
5298 "fnmadds %0,%1,%2,%3"
5299 [(set_attr "type" "fp")])
5300
5301 (define_insn ""
5302 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5303 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5304 (match_operand:SF 2 "gpc_reg_operand" "f"))
5305 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5306 "TARGET_POWERPC && TARGET_SINGLE_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5307 && ! HONOR_SIGNED_ZEROS (SFmode)"
5308 "fnmadds %0,%1,%2,%3"
5309 [(set_attr "type" "fp")])
5310
5311 (define_insn ""
5312 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5313 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5314 (match_operand:SF 2 "gpc_reg_operand" "f"))
5315 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5316 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5317 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5318 "{fnma|fnmadd} %0,%1,%2,%3"
5319 [(set_attr "type" "dmul")])
5320
5321 (define_insn ""
5322 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5323 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5324 (match_operand:SF 2 "gpc_reg_operand" "f"))
5325 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5326 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5327 && TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)"
5328 "{fnma|fnmadd} %0,%1,%2,%3"
5329 [(set_attr "type" "dmul")])
5330
5331 (define_insn ""
5332 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5333 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5334 (match_operand:SF 2 "gpc_reg_operand" "f"))
5335 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5336 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5337 && TARGET_SINGLE_FLOAT && HONOR_SIGNED_ZEROS (SFmode)"
5338 "fnmsubs %0,%1,%2,%3"
5339 [(set_attr "type" "fp")])
5340
5341 (define_insn ""
5342 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5343 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5344 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5345 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5346 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5347 && TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)"
5348 "fnmsubs %0,%1,%2,%3"
5349 [(set_attr "type" "fp")])
5350
5351 (define_insn ""
5352 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5353 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5354 (match_operand:SF 2 "gpc_reg_operand" "f"))
5355 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5356 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5357 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5358 "{fnms|fnmsub} %0,%1,%2,%3"
5359 [(set_attr "type" "dmul")])
5360
5361 (define_insn ""
5362 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5363 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5364 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5365 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5366 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5367 && TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)"
5368 "{fnms|fnmsub} %0,%1,%2,%3"
5369 [(set_attr "type" "dmul")])
5370
5371 (define_expand "sqrtsf2"
5372 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5373 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5374 "(TARGET_PPC_GPOPT || TARGET_POWER2)
5375 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5376 && !TARGET_SIMPLE_FPU"
5377 "")
5378
5379 (define_insn ""
5380 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5381 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5382 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT
5383 && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5384 "fsqrts %0,%1"
5385 [(set_attr "type" "ssqrt")])
5386
5387 (define_insn ""
5388 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5389 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5390 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS
5391 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5392 "fsqrt %0,%1"
5393 [(set_attr "type" "dsqrt")])
5394
5395 (define_expand "rsqrtsf2"
5396 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5397 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5398 UNSPEC_RSQRT))]
5399 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5400 && flag_finite_math_only && !flag_trapping_math"
5401 {
5402 rs6000_emit_swrsqrtsf (operands[0], operands[1]);
5403 DONE;
5404 })
5405
5406 (define_insn "*rsqrt_internal1"
5407 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5408 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5409 UNSPEC_RSQRT))]
5410 "TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT"
5411 "frsqrte %0,%1"
5412 [(set_attr "type" "fp")])
5413
5414 (define_expand "copysignsf3"
5415 [(set (match_dup 3)
5416 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5417 (set (match_dup 4)
5418 (neg:SF (abs:SF (match_dup 1))))
5419 (set (match_operand:SF 0 "gpc_reg_operand" "")
5420 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5421 (match_dup 5))
5422 (match_dup 3)
5423 (match_dup 4)))]
5424 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5425 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
5426 {
5427 operands[3] = gen_reg_rtx (SFmode);
5428 operands[4] = gen_reg_rtx (SFmode);
5429 operands[5] = CONST0_RTX (SFmode);
5430 })
5431
5432 (define_expand "copysigndf3"
5433 [(set (match_dup 3)
5434 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5435 (set (match_dup 4)
5436 (neg:DF (abs:DF (match_dup 1))))
5437 (set (match_operand:DF 0 "gpc_reg_operand" "")
5438 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5439 (match_dup 5))
5440 (match_dup 3)
5441 (match_dup 4)))]
5442 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5443 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
5444 {
5445 operands[3] = gen_reg_rtx (DFmode);
5446 operands[4] = gen_reg_rtx (DFmode);
5447 operands[5] = CONST0_RTX (DFmode);
5448 })
5449
5450 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5451 ;; fsel instruction and some auxiliary computations. Then we just have a
5452 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5453 ;; combine.
5454 (define_expand "smaxsf3"
5455 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5456 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5457 (match_operand:SF 2 "gpc_reg_operand" ""))
5458 (match_dup 1)
5459 (match_dup 2)))]
5460 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5461 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5462 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5463
5464 (define_expand "sminsf3"
5465 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5466 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5467 (match_operand:SF 2 "gpc_reg_operand" ""))
5468 (match_dup 2)
5469 (match_dup 1)))]
5470 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5471 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5472 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5473
5474 (define_split
5475 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5476 (match_operator:SF 3 "min_max_operator"
5477 [(match_operand:SF 1 "gpc_reg_operand" "")
5478 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5479 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5480 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5481 [(const_int 0)]
5482 "
5483 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5484 operands[1], operands[2]);
5485 DONE;
5486 }")
5487
5488 (define_expand "movsicc"
5489 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5490 (if_then_else:SI (match_operand 1 "comparison_operator" "")
5491 (match_operand:SI 2 "gpc_reg_operand" "")
5492 (match_operand:SI 3 "gpc_reg_operand" "")))]
5493 "TARGET_ISEL"
5494 "
5495 {
5496 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5497 DONE;
5498 else
5499 FAIL;
5500 }")
5501
5502 ;; We use the BASE_REGS for the isel input operands because, if rA is
5503 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5504 ;; because we may switch the operands and rB may end up being rA.
5505 ;;
5506 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5507 ;; leave out the mode in operand 4 and use one pattern, but reload can
5508 ;; change the mode underneath our feet and then gets confused trying
5509 ;; to reload the value.
5510 (define_insn "isel_signed"
5511 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5512 (if_then_else:SI
5513 (match_operator 1 "comparison_operator"
5514 [(match_operand:CC 4 "cc_reg_operand" "y")
5515 (const_int 0)])
5516 (match_operand:SI 2 "gpc_reg_operand" "b")
5517 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5518 "TARGET_ISEL"
5519 "*
5520 { return output_isel (operands); }"
5521 [(set_attr "length" "4")])
5522
5523 (define_insn "isel_unsigned"
5524 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5525 (if_then_else:SI
5526 (match_operator 1 "comparison_operator"
5527 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5528 (const_int 0)])
5529 (match_operand:SI 2 "gpc_reg_operand" "b")
5530 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5531 "TARGET_ISEL"
5532 "*
5533 { return output_isel (operands); }"
5534 [(set_attr "length" "4")])
5535
5536 (define_expand "movsfcc"
5537 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5538 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5539 (match_operand:SF 2 "gpc_reg_operand" "")
5540 (match_operand:SF 3 "gpc_reg_operand" "")))]
5541 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5542 "
5543 {
5544 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5545 DONE;
5546 else
5547 FAIL;
5548 }")
5549
5550 (define_insn "*fselsfsf4"
5551 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5552 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5553 (match_operand:SF 4 "zero_fp_constant" "F"))
5554 (match_operand:SF 2 "gpc_reg_operand" "f")
5555 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5556 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5557 "fsel %0,%1,%2,%3"
5558 [(set_attr "type" "fp")])
5559
5560 (define_insn "*fseldfsf4"
5561 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5562 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5563 (match_operand:DF 4 "zero_fp_constant" "F"))
5564 (match_operand:SF 2 "gpc_reg_operand" "f")
5565 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5566 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5567 "fsel %0,%1,%2,%3"
5568 [(set_attr "type" "fp")])
5569
5570 (define_expand "negdf2"
5571 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5572 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5573 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5574 "")
5575
5576 (define_insn "*negdf2_fpr"
5577 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5578 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5579 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5580 "fneg %0,%1"
5581 [(set_attr "type" "fp")])
5582
5583 (define_expand "absdf2"
5584 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5585 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5586 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5587 "")
5588
5589 (define_insn "*absdf2_fpr"
5590 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5591 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5592 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5593 "fabs %0,%1"
5594 [(set_attr "type" "fp")])
5595
5596 (define_insn "*nabsdf2_fpr"
5597 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5598 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
5599 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5600 "fnabs %0,%1"
5601 [(set_attr "type" "fp")])
5602
5603 (define_expand "adddf3"
5604 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5605 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5606 (match_operand:DF 2 "gpc_reg_operand" "")))]
5607 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5608 "")
5609
5610 (define_insn "*adddf3_fpr"
5611 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5612 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5613 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5614 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5615 "{fa|fadd} %0,%1,%2"
5616 [(set_attr "type" "fp")])
5617
5618 (define_expand "subdf3"
5619 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5620 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5621 (match_operand:DF 2 "gpc_reg_operand" "")))]
5622 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5623 "")
5624
5625 (define_insn "*subdf3_fpr"
5626 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5627 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5628 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5629 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5630 "{fs|fsub} %0,%1,%2"
5631 [(set_attr "type" "fp")])
5632
5633 (define_expand "muldf3"
5634 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5635 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5636 (match_operand:DF 2 "gpc_reg_operand" "")))]
5637 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5638 "")
5639
5640 (define_insn "*muldf3_fpr"
5641 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5642 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5643 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5644 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5645 "{fm|fmul} %0,%1,%2"
5646 [(set_attr "type" "dmul")])
5647
5648 (define_expand "divdf3"
5649 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5650 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5651 (match_operand:DF 2 "gpc_reg_operand" "")))]
5652 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE) && !TARGET_SIMPLE_FPU"
5653 "")
5654
5655 (define_insn "*divdf3_fpr"
5656 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5657 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5658 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5659 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU"
5660 "{fd|fdiv} %0,%1,%2"
5661 [(set_attr "type" "ddiv")])
5662
5663 (define_expand "recipdf3"
5664 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5665 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")
5666 (match_operand:DF 2 "gpc_reg_operand" "f")]
5667 UNSPEC_FRES))]
5668 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_POPCNTB && !optimize_size
5669 && flag_finite_math_only && !flag_trapping_math"
5670 {
5671 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5672 DONE;
5673 })
5674
5675 (define_insn "fred"
5676 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5677 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5678 "TARGET_POPCNTB && flag_finite_math_only"
5679 "fre %0,%1"
5680 [(set_attr "type" "fp")])
5681
5682 (define_insn ""
5683 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5684 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5685 (match_operand:DF 2 "gpc_reg_operand" "f"))
5686 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5687 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT"
5688 "{fma|fmadd} %0,%1,%2,%3"
5689 [(set_attr "type" "dmul")])
5690
5691 (define_insn ""
5692 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5693 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5694 (match_operand:DF 2 "gpc_reg_operand" "f"))
5695 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5696 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT"
5697 "{fms|fmsub} %0,%1,%2,%3"
5698 [(set_attr "type" "dmul")])
5699
5700 (define_insn ""
5701 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5702 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5703 (match_operand:DF 2 "gpc_reg_operand" "f"))
5704 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5705 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
5706 && HONOR_SIGNED_ZEROS (DFmode)"
5707 "{fnma|fnmadd} %0,%1,%2,%3"
5708 [(set_attr "type" "dmul")])
5709
5710 (define_insn ""
5711 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5712 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5713 (match_operand:DF 2 "gpc_reg_operand" "f"))
5714 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5715 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
5716 && ! HONOR_SIGNED_ZEROS (DFmode)"
5717 "{fnma|fnmadd} %0,%1,%2,%3"
5718 [(set_attr "type" "dmul")])
5719
5720 (define_insn ""
5721 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5722 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5723 (match_operand:DF 2 "gpc_reg_operand" "f"))
5724 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5725 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
5726 && HONOR_SIGNED_ZEROS (DFmode)"
5727 "{fnms|fnmsub} %0,%1,%2,%3"
5728 [(set_attr "type" "dmul")])
5729
5730 (define_insn ""
5731 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5732 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5733 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5734 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5735 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
5736 && ! HONOR_SIGNED_ZEROS (DFmode)"
5737 "{fnms|fnmsub} %0,%1,%2,%3"
5738 [(set_attr "type" "dmul")])
5739
5740 (define_insn "sqrtdf2"
5741 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5742 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5743 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
5744 && TARGET_DOUBLE_FLOAT"
5745 "fsqrt %0,%1"
5746 [(set_attr "type" "dsqrt")])
5747
5748 ;; The conditional move instructions allow us to perform max and min
5749 ;; operations even when
5750
5751 (define_expand "smaxdf3"
5752 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5753 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5754 (match_operand:DF 2 "gpc_reg_operand" ""))
5755 (match_dup 1)
5756 (match_dup 2)))]
5757 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5758 && !flag_trapping_math"
5759 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5760
5761 (define_expand "smindf3"
5762 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5763 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5764 (match_operand:DF 2 "gpc_reg_operand" ""))
5765 (match_dup 2)
5766 (match_dup 1)))]
5767 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5768 && !flag_trapping_math"
5769 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5770
5771 (define_split
5772 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5773 (match_operator:DF 3 "min_max_operator"
5774 [(match_operand:DF 1 "gpc_reg_operand" "")
5775 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5776 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5777 && !flag_trapping_math"
5778 [(const_int 0)]
5779 "
5780 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5781 operands[1], operands[2]);
5782 DONE;
5783 }")
5784
5785 (define_expand "movdfcc"
5786 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5787 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5788 (match_operand:DF 2 "gpc_reg_operand" "")
5789 (match_operand:DF 3 "gpc_reg_operand" "")))]
5790 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5791 "
5792 {
5793 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5794 DONE;
5795 else
5796 FAIL;
5797 }")
5798
5799 (define_insn "*fseldfdf4"
5800 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5801 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5802 (match_operand:DF 4 "zero_fp_constant" "F"))
5803 (match_operand:DF 2 "gpc_reg_operand" "f")
5804 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5805 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5806 "fsel %0,%1,%2,%3"
5807 [(set_attr "type" "fp")])
5808
5809 (define_insn "*fselsfdf4"
5810 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5811 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5812 (match_operand:SF 4 "zero_fp_constant" "F"))
5813 (match_operand:DF 2 "gpc_reg_operand" "f")
5814 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5815 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5816 "fsel %0,%1,%2,%3"
5817 [(set_attr "type" "fp")])
5818 \f
5819 ;; Conversions to and from floating-point.
5820
5821 (define_expand "fixuns_truncsfsi2"
5822 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5823 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5824 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
5825 "")
5826
5827 (define_expand "fix_truncsfsi2"
5828 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5829 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5830 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
5831 "")
5832
5833 ; For each of these conversions, there is a define_expand, a define_insn
5834 ; with a '#' template, and a define_split (with C code). The idea is
5835 ; to allow constant folding with the template of the define_insn,
5836 ; then to have the insns split later (between sched1 and final).
5837
5838 (define_expand "floatsidf2"
5839 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5840 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5841 (use (match_dup 2))
5842 (use (match_dup 3))
5843 (clobber (match_dup 4))
5844 (clobber (match_dup 5))
5845 (clobber (match_dup 6))])]
5846 "TARGET_HARD_FLOAT
5847 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5848 "
5849 {
5850 if (TARGET_E500_DOUBLE)
5851 {
5852 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5853 DONE;
5854 }
5855 if (TARGET_POWERPC64)
5856 {
5857 rtx x = convert_to_mode (DImode, operands[1], 0);
5858 emit_insn (gen_floatdidf2 (operands[0], x));
5859 DONE;
5860 }
5861
5862 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5863 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5864 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5865 operands[5] = gen_reg_rtx (DFmode);
5866 operands[6] = gen_reg_rtx (SImode);
5867 }")
5868
5869 (define_insn_and_split "*floatsidf2_internal"
5870 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5871 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5872 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5873 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5874 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5875 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5876 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5877 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5878 "#"
5879 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
5880 [(pc)]
5881 "
5882 {
5883 rtx lowword, highword;
5884 gcc_assert (MEM_P (operands[4]));
5885 highword = adjust_address (operands[4], SImode, 0);
5886 lowword = adjust_address (operands[4], SImode, 4);
5887 if (! WORDS_BIG_ENDIAN)
5888 {
5889 rtx tmp;
5890 tmp = highword; highword = lowword; lowword = tmp;
5891 }
5892
5893 emit_insn (gen_xorsi3 (operands[6], operands[1],
5894 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5895 emit_move_insn (lowword, operands[6]);
5896 emit_move_insn (highword, operands[2]);
5897 emit_move_insn (operands[5], operands[4]);
5898 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5899 DONE;
5900 }"
5901 [(set_attr "length" "24")])
5902
5903 (define_expand "floatunssisf2"
5904 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5905 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5906 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
5907 "")
5908
5909 (define_expand "floatunssidf2"
5910 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5911 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5912 (use (match_dup 2))
5913 (use (match_dup 3))
5914 (clobber (match_dup 4))
5915 (clobber (match_dup 5))])]
5916 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5917 "
5918 {
5919 if (TARGET_E500_DOUBLE)
5920 {
5921 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5922 DONE;
5923 }
5924 if (TARGET_POWERPC64)
5925 {
5926 rtx x = convert_to_mode (DImode, operands[1], 1);
5927 emit_insn (gen_floatdidf2 (operands[0], x));
5928 DONE;
5929 }
5930
5931 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5932 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5933 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5934 operands[5] = gen_reg_rtx (DFmode);
5935 }")
5936
5937 (define_insn_and_split "*floatunssidf2_internal"
5938 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5939 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5940 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5941 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5942 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5943 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5944 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5945 "#"
5946 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
5947 [(pc)]
5948 "
5949 {
5950 rtx lowword, highword;
5951 gcc_assert (MEM_P (operands[4]));
5952 highword = adjust_address (operands[4], SImode, 0);
5953 lowword = adjust_address (operands[4], SImode, 4);
5954 if (! WORDS_BIG_ENDIAN)
5955 {
5956 rtx tmp;
5957 tmp = highword; highword = lowword; lowword = tmp;
5958 }
5959
5960 emit_move_insn (lowword, operands[1]);
5961 emit_move_insn (highword, operands[2]);
5962 emit_move_insn (operands[5], operands[4]);
5963 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5964 DONE;
5965 }"
5966 [(set_attr "length" "20")])
5967
5968 (define_expand "fix_truncdfsi2"
5969 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
5970 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5971 (clobber (match_dup 2))
5972 (clobber (match_dup 3))])]
5973 "(TARGET_POWER2 || TARGET_POWERPC)
5974 && TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5975 "
5976 {
5977 if (TARGET_E500_DOUBLE)
5978 {
5979 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5980 DONE;
5981 }
5982 operands[2] = gen_reg_rtx (DImode);
5983 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
5984 && gpc_reg_operand(operands[0], GET_MODE (operands[0])))
5985 {
5986 operands[3] = gen_reg_rtx (DImode);
5987 emit_insn (gen_fix_truncdfsi2_mfpgpr (operands[0], operands[1],
5988 operands[2], operands[3]));
5989 DONE;
5990 }
5991 if (TARGET_PPC_GFXOPT)
5992 {
5993 rtx orig_dest = operands[0];
5994 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
5995 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5996 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5997 operands[2]));
5998 if (operands[0] != orig_dest)
5999 emit_move_insn (orig_dest, operands[0]);
6000 DONE;
6001 }
6002 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
6003 }")
6004
6005 (define_insn_and_split "*fix_truncdfsi2_internal"
6006 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6007 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
6008 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
6009 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))]
6010 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6011 && TARGET_DOUBLE_FLOAT"
6012 "#"
6013 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[3]))"
6014 [(pc)]
6015 "
6016 {
6017 rtx lowword;
6018 gcc_assert (MEM_P (operands[3]));
6019 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
6020
6021 emit_insn (gen_fctiwz (operands[2], operands[1]));
6022 emit_move_insn (operands[3], operands[2]);
6023 emit_move_insn (operands[0], lowword);
6024 DONE;
6025 }"
6026 [(set_attr "length" "16")])
6027
6028 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
6029 [(set (match_operand:SI 0 "memory_operand" "=Z")
6030 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
6031 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
6032 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6033 && TARGET_DOUBLE_FLOAT
6034 && TARGET_PPC_GFXOPT"
6035 "#"
6036 "&& 1"
6037 [(pc)]
6038 "
6039 {
6040 emit_insn (gen_fctiwz (operands[2], operands[1]));
6041 emit_insn (gen_stfiwx (operands[0], operands[2]));
6042 DONE;
6043 }"
6044 [(set_attr "length" "16")])
6045
6046 (define_insn_and_split "fix_truncdfsi2_mfpgpr"
6047 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6048 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
6049 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
6050 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
6051 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
6052 && TARGET_DOUBLE_FLOAT"
6053 "#"
6054 "&& 1"
6055 [(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
6056 (set (match_dup 3) (match_dup 2))
6057 (set (match_dup 0) (subreg:SI (match_dup 3) 4))]
6058 ""
6059 [(set_attr "length" "12")])
6060
6061 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6062 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6063 ; because the first makes it clear that operand 0 is not live
6064 ; before the instruction.
6065 (define_insn "fctiwz"
6066 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
6067 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
6068 UNSPEC_FCTIWZ))]
6069 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6070 && TARGET_DOUBLE_FLOAT"
6071 "{fcirz|fctiwz} %0,%1"
6072 [(set_attr "type" "fp")])
6073
6074 (define_insn "btruncdf2"
6075 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6076 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6077 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6078 "friz %0,%1"
6079 [(set_attr "type" "fp")])
6080
6081 (define_insn "btruncsf2"
6082 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6083 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6084 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6085 "friz %0,%1"
6086 [(set_attr "type" "fp")])
6087
6088 (define_insn "ceildf2"
6089 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6090 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6091 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6092 "frip %0,%1"
6093 [(set_attr "type" "fp")])
6094
6095 (define_insn "ceilsf2"
6096 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6097 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6098 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6099 "frip %0,%1"
6100 [(set_attr "type" "fp")])
6101
6102 (define_insn "floordf2"
6103 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6104 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6105 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6106 "frim %0,%1"
6107 [(set_attr "type" "fp")])
6108
6109 (define_insn "floorsf2"
6110 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6111 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6112 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6113 "frim %0,%1"
6114 [(set_attr "type" "fp")])
6115
6116 (define_insn "rounddf2"
6117 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6118 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6119 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6120 "frin %0,%1"
6121 [(set_attr "type" "fp")])
6122
6123 (define_insn "roundsf2"
6124 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6125 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6126 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6127 "frin %0,%1"
6128 [(set_attr "type" "fp")])
6129
6130 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6131 (define_insn "stfiwx"
6132 [(set (match_operand:SI 0 "memory_operand" "=Z")
6133 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
6134 UNSPEC_STFIWX))]
6135 "TARGET_PPC_GFXOPT"
6136 "stfiwx %1,%y0"
6137 [(set_attr "type" "fpstore")])
6138
6139 (define_expand "floatsisf2"
6140 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6141 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6142 "TARGET_HARD_FLOAT && (!TARGET_FPRS || TARGET_SINGLE_FPU)"
6143 "")
6144
6145 (define_insn "floatdidf2"
6146 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6147 (float:DF (match_operand:DI 1 "gpc_reg_operand" "!f#r")))]
6148 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6149 "fcfid %0,%1"
6150 [(set_attr "type" "fp")])
6151
6152 (define_insn "fix_truncdfdi2"
6153 [(set (match_operand:DI 0 "gpc_reg_operand" "=!f#r")
6154 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
6155 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6156 "fctidz %0,%1"
6157 [(set_attr "type" "fp")])
6158
6159 (define_expand "floatdisf2"
6160 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6161 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6162 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6163 "
6164 {
6165 rtx val = operands[1];
6166 if (!flag_unsafe_math_optimizations)
6167 {
6168 rtx label = gen_label_rtx ();
6169 val = gen_reg_rtx (DImode);
6170 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6171 emit_label (label);
6172 }
6173 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6174 DONE;
6175 }")
6176
6177 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6178 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6179 ;; from double rounding.
6180 (define_insn_and_split "floatdisf2_internal1"
6181 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6182 (float:SF (match_operand:DI 1 "gpc_reg_operand" "!f#r")))
6183 (clobber (match_scratch:DF 2 "=f"))]
6184 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6185 "#"
6186 "&& reload_completed"
6187 [(set (match_dup 2)
6188 (float:DF (match_dup 1)))
6189 (set (match_dup 0)
6190 (float_truncate:SF (match_dup 2)))]
6191 "")
6192
6193 ;; Twiddles bits to avoid double rounding.
6194 ;; Bits that might be truncated when converting to DFmode are replaced
6195 ;; by a bit that won't be lost at that stage, but is below the SFmode
6196 ;; rounding position.
6197 (define_expand "floatdisf2_internal2"
6198 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6199 (const_int 53)))
6200 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6201 (const_int 2047)))
6202 (clobber (scratch:CC))])
6203 (set (match_dup 3) (plus:DI (match_dup 3)
6204 (const_int 1)))
6205 (set (match_dup 0) (plus:DI (match_dup 0)
6206 (const_int 2047)))
6207 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6208 (const_int 2)))
6209 (set (match_dup 0) (ior:DI (match_dup 0)
6210 (match_dup 1)))
6211 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6212 (const_int -2048)))
6213 (clobber (scratch:CC))])
6214 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6215 (label_ref (match_operand:DI 2 "" ""))
6216 (pc)))
6217 (set (match_dup 0) (match_dup 1))]
6218 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6219 "
6220 {
6221 operands[3] = gen_reg_rtx (DImode);
6222 operands[4] = gen_reg_rtx (CCUNSmode);
6223 }")
6224 \f
6225 ;; Define the DImode operations that can be done in a small number
6226 ;; of instructions. The & constraints are to prevent the register
6227 ;; allocator from allocating registers that overlap with the inputs
6228 ;; (for example, having an input in 7,8 and an output in 6,7). We
6229 ;; also allow for the output being the same as one of the inputs.
6230
6231 (define_insn "*adddi3_noppc64"
6232 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6233 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6234 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6235 "! TARGET_POWERPC64"
6236 "*
6237 {
6238 if (WORDS_BIG_ENDIAN)
6239 return (GET_CODE (operands[2])) != CONST_INT
6240 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6241 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6242 else
6243 return (GET_CODE (operands[2])) != CONST_INT
6244 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6245 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6246 }"
6247 [(set_attr "type" "two")
6248 (set_attr "length" "8")])
6249
6250 (define_insn "*subdi3_noppc64"
6251 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6252 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6253 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6254 "! TARGET_POWERPC64"
6255 "*
6256 {
6257 if (WORDS_BIG_ENDIAN)
6258 return (GET_CODE (operands[1]) != CONST_INT)
6259 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6260 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6261 else
6262 return (GET_CODE (operands[1]) != CONST_INT)
6263 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6264 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
6265 }"
6266 [(set_attr "type" "two")
6267 (set_attr "length" "8")])
6268
6269 (define_insn "*negdi2_noppc64"
6270 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6271 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6272 "! TARGET_POWERPC64"
6273 "*
6274 {
6275 return (WORDS_BIG_ENDIAN)
6276 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6277 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6278 }"
6279 [(set_attr "type" "two")
6280 (set_attr "length" "8")])
6281
6282 (define_expand "mulsidi3"
6283 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6284 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6285 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6286 "! TARGET_POWERPC64"
6287 "
6288 {
6289 if (! TARGET_POWER && ! TARGET_POWERPC)
6290 {
6291 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6292 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6293 emit_insn (gen_mull_call ());
6294 if (WORDS_BIG_ENDIAN)
6295 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
6296 else
6297 {
6298 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
6299 gen_rtx_REG (SImode, 3));
6300 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
6301 gen_rtx_REG (SImode, 4));
6302 }
6303 DONE;
6304 }
6305 else if (TARGET_POWER)
6306 {
6307 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6308 DONE;
6309 }
6310 }")
6311
6312 (define_insn "mulsidi3_mq"
6313 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6314 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6315 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6316 (clobber (match_scratch:SI 3 "=q"))]
6317 "TARGET_POWER"
6318 "mul %0,%1,%2\;mfmq %L0"
6319 [(set_attr "type" "imul")
6320 (set_attr "length" "8")])
6321
6322 (define_insn "*mulsidi3_no_mq"
6323 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6324 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6325 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6326 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6327 "*
6328 {
6329 return (WORDS_BIG_ENDIAN)
6330 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6331 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6332 }"
6333 [(set_attr "type" "imul")
6334 (set_attr "length" "8")])
6335
6336 (define_split
6337 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6338 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6339 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6340 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6341 [(set (match_dup 3)
6342 (truncate:SI
6343 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6344 (sign_extend:DI (match_dup 2)))
6345 (const_int 32))))
6346 (set (match_dup 4)
6347 (mult:SI (match_dup 1)
6348 (match_dup 2)))]
6349 "
6350 {
6351 int endian = (WORDS_BIG_ENDIAN == 0);
6352 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6353 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6354 }")
6355
6356 (define_expand "umulsidi3"
6357 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6358 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6359 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6360 "TARGET_POWERPC && ! TARGET_POWERPC64"
6361 "
6362 {
6363 if (TARGET_POWER)
6364 {
6365 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6366 DONE;
6367 }
6368 }")
6369
6370 (define_insn "umulsidi3_mq"
6371 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6372 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6373 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6374 (clobber (match_scratch:SI 3 "=q"))]
6375 "TARGET_POWERPC && TARGET_POWER"
6376 "*
6377 {
6378 return (WORDS_BIG_ENDIAN)
6379 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6380 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6381 }"
6382 [(set_attr "type" "imul")
6383 (set_attr "length" "8")])
6384
6385 (define_insn "*umulsidi3_no_mq"
6386 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6387 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6388 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6389 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6390 "*
6391 {
6392 return (WORDS_BIG_ENDIAN)
6393 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6394 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6395 }"
6396 [(set_attr "type" "imul")
6397 (set_attr "length" "8")])
6398
6399 (define_split
6400 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6401 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6402 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6403 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6404 [(set (match_dup 3)
6405 (truncate:SI
6406 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6407 (zero_extend:DI (match_dup 2)))
6408 (const_int 32))))
6409 (set (match_dup 4)
6410 (mult:SI (match_dup 1)
6411 (match_dup 2)))]
6412 "
6413 {
6414 int endian = (WORDS_BIG_ENDIAN == 0);
6415 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6416 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6417 }")
6418
6419 (define_expand "smulsi3_highpart"
6420 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6421 (truncate:SI
6422 (lshiftrt:DI (mult:DI (sign_extend:DI
6423 (match_operand:SI 1 "gpc_reg_operand" ""))
6424 (sign_extend:DI
6425 (match_operand:SI 2 "gpc_reg_operand" "")))
6426 (const_int 32))))]
6427 ""
6428 "
6429 {
6430 if (! TARGET_POWER && ! TARGET_POWERPC)
6431 {
6432 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6433 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6434 emit_insn (gen_mulh_call ());
6435 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
6436 DONE;
6437 }
6438 else if (TARGET_POWER)
6439 {
6440 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6441 DONE;
6442 }
6443 }")
6444
6445 (define_insn "smulsi3_highpart_mq"
6446 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6447 (truncate:SI
6448 (lshiftrt:DI (mult:DI (sign_extend:DI
6449 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6450 (sign_extend:DI
6451 (match_operand:SI 2 "gpc_reg_operand" "r")))
6452 (const_int 32))))
6453 (clobber (match_scratch:SI 3 "=q"))]
6454 "TARGET_POWER"
6455 "mul %0,%1,%2"
6456 [(set_attr "type" "imul")])
6457
6458 (define_insn "*smulsi3_highpart_no_mq"
6459 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6460 (truncate:SI
6461 (lshiftrt:DI (mult:DI (sign_extend:DI
6462 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6463 (sign_extend:DI
6464 (match_operand:SI 2 "gpc_reg_operand" "r")))
6465 (const_int 32))))]
6466 "TARGET_POWERPC && ! TARGET_POWER"
6467 "mulhw %0,%1,%2"
6468 [(set_attr "type" "imul")])
6469
6470 (define_expand "umulsi3_highpart"
6471 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6472 (truncate:SI
6473 (lshiftrt:DI (mult:DI (zero_extend:DI
6474 (match_operand:SI 1 "gpc_reg_operand" ""))
6475 (zero_extend:DI
6476 (match_operand:SI 2 "gpc_reg_operand" "")))
6477 (const_int 32))))]
6478 "TARGET_POWERPC"
6479 "
6480 {
6481 if (TARGET_POWER)
6482 {
6483 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6484 DONE;
6485 }
6486 }")
6487
6488 (define_insn "umulsi3_highpart_mq"
6489 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6490 (truncate:SI
6491 (lshiftrt:DI (mult:DI (zero_extend:DI
6492 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6493 (zero_extend:DI
6494 (match_operand:SI 2 "gpc_reg_operand" "r")))
6495 (const_int 32))))
6496 (clobber (match_scratch:SI 3 "=q"))]
6497 "TARGET_POWERPC && TARGET_POWER"
6498 "mulhwu %0,%1,%2"
6499 [(set_attr "type" "imul")])
6500
6501 (define_insn "*umulsi3_highpart_no_mq"
6502 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6503 (truncate:SI
6504 (lshiftrt:DI (mult:DI (zero_extend:DI
6505 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6506 (zero_extend:DI
6507 (match_operand:SI 2 "gpc_reg_operand" "r")))
6508 (const_int 32))))]
6509 "TARGET_POWERPC && ! TARGET_POWER"
6510 "mulhwu %0,%1,%2"
6511 [(set_attr "type" "imul")])
6512
6513 ;; If operands 0 and 2 are in the same register, we have a problem. But
6514 ;; operands 0 and 1 (the usual case) can be in the same register. That's
6515 ;; why we have the strange constraints below.
6516 (define_insn "ashldi3_power"
6517 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6518 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6519 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6520 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6521 "TARGET_POWER"
6522 "@
6523 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
6524 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6525 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6526 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
6527 [(set_attr "length" "8")])
6528
6529 (define_insn "lshrdi3_power"
6530 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6531 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6532 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6533 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6534 "TARGET_POWER"
6535 "@
6536 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
6537 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6538 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6539 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
6540 [(set_attr "length" "8")])
6541
6542 ;; Shift by a variable amount is too complex to be worth open-coding. We
6543 ;; just handle shifts by constants.
6544 (define_insn "ashrdi3_power"
6545 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6546 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6547 (match_operand:SI 2 "const_int_operand" "M,i")))
6548 (clobber (match_scratch:SI 3 "=X,q"))]
6549 "TARGET_POWER"
6550 "@
6551 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6552 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
6553 [(set_attr "type" "shift")
6554 (set_attr "length" "8")])
6555
6556 (define_insn "ashrdi3_no_power"
6557 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6558 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6559 (match_operand:SI 2 "const_int_operand" "M,i")))]
6560 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
6561 "@
6562 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6563 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
6564 [(set_attr "type" "two,three")
6565 (set_attr "length" "8,12")])
6566
6567 (define_insn "*ashrdisi3_noppc64"
6568 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6569 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6570 (const_int 32)) 4))]
6571 "TARGET_32BIT && !TARGET_POWERPC64"
6572 "*
6573 {
6574 if (REGNO (operands[0]) == REGNO (operands[1]))
6575 return \"\";
6576 else
6577 return \"mr %0,%1\";
6578 }"
6579 [(set_attr "length" "4")])
6580
6581 \f
6582 ;; PowerPC64 DImode operations.
6583
6584 (define_insn_and_split "absdi2"
6585 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6586 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6587 (clobber (match_scratch:DI 2 "=&r,&r"))]
6588 "TARGET_POWERPC64"
6589 "#"
6590 "&& reload_completed"
6591 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6592 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6593 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6594 "")
6595
6596 (define_insn_and_split "*nabsdi2"
6597 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6598 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6599 (clobber (match_scratch:DI 2 "=&r,&r"))]
6600 "TARGET_POWERPC64"
6601 "#"
6602 "&& reload_completed"
6603 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6604 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6605 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
6606 "")
6607
6608 (define_insn "muldi3"
6609 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6610 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6611 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6612 "TARGET_POWERPC64"
6613 "@
6614 mulld %0,%1,%2
6615 mulli %0,%1,%2"
6616 [(set (attr "type")
6617 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6618 (const_string "imul3")
6619 (match_operand:SI 2 "short_cint_operand" "")
6620 (const_string "imul2")]
6621 (const_string "lmul")))])
6622
6623 (define_insn "*muldi3_internal1"
6624 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6625 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6626 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6627 (const_int 0)))
6628 (clobber (match_scratch:DI 3 "=r,r"))]
6629 "TARGET_POWERPC64"
6630 "@
6631 mulld. %3,%1,%2
6632 #"
6633 [(set_attr "type" "lmul_compare")
6634 (set_attr "length" "4,8")])
6635
6636 (define_split
6637 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6638 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6639 (match_operand:DI 2 "gpc_reg_operand" ""))
6640 (const_int 0)))
6641 (clobber (match_scratch:DI 3 ""))]
6642 "TARGET_POWERPC64 && reload_completed"
6643 [(set (match_dup 3)
6644 (mult:DI (match_dup 1) (match_dup 2)))
6645 (set (match_dup 0)
6646 (compare:CC (match_dup 3)
6647 (const_int 0)))]
6648 "")
6649
6650 (define_insn "*muldi3_internal2"
6651 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6652 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6653 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6654 (const_int 0)))
6655 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6656 (mult:DI (match_dup 1) (match_dup 2)))]
6657 "TARGET_POWERPC64"
6658 "@
6659 mulld. %0,%1,%2
6660 #"
6661 [(set_attr "type" "lmul_compare")
6662 (set_attr "length" "4,8")])
6663
6664 (define_split
6665 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6666 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6667 (match_operand:DI 2 "gpc_reg_operand" ""))
6668 (const_int 0)))
6669 (set (match_operand:DI 0 "gpc_reg_operand" "")
6670 (mult:DI (match_dup 1) (match_dup 2)))]
6671 "TARGET_POWERPC64 && reload_completed"
6672 [(set (match_dup 0)
6673 (mult:DI (match_dup 1) (match_dup 2)))
6674 (set (match_dup 3)
6675 (compare:CC (match_dup 0)
6676 (const_int 0)))]
6677 "")
6678
6679 (define_insn "smuldi3_highpart"
6680 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6681 (truncate:DI
6682 (lshiftrt:TI (mult:TI (sign_extend:TI
6683 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6684 (sign_extend:TI
6685 (match_operand:DI 2 "gpc_reg_operand" "r")))
6686 (const_int 64))))]
6687 "TARGET_POWERPC64"
6688 "mulhd %0,%1,%2"
6689 [(set_attr "type" "lmul")])
6690
6691 (define_insn "umuldi3_highpart"
6692 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6693 (truncate:DI
6694 (lshiftrt:TI (mult:TI (zero_extend:TI
6695 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6696 (zero_extend:TI
6697 (match_operand:DI 2 "gpc_reg_operand" "r")))
6698 (const_int 64))))]
6699 "TARGET_POWERPC64"
6700 "mulhdu %0,%1,%2"
6701 [(set_attr "type" "lmul")])
6702
6703 (define_insn "rotldi3"
6704 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6705 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6706 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
6707 "TARGET_POWERPC64"
6708 "@
6709 rldcl %0,%1,%2,0
6710 rldicl %0,%1,%H2,0"
6711 [(set_attr "type" "var_shift_rotate,integer")])
6712
6713 (define_insn "*rotldi3_internal2"
6714 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6715 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6716 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6717 (const_int 0)))
6718 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6719 "TARGET_64BIT"
6720 "@
6721 rldcl. %3,%1,%2,0
6722 rldicl. %3,%1,%H2,0
6723 #
6724 #"
6725 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6726 (set_attr "length" "4,4,8,8")])
6727
6728 (define_split
6729 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6730 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6731 (match_operand:DI 2 "reg_or_cint_operand" ""))
6732 (const_int 0)))
6733 (clobber (match_scratch:DI 3 ""))]
6734 "TARGET_POWERPC64 && reload_completed"
6735 [(set (match_dup 3)
6736 (rotate:DI (match_dup 1) (match_dup 2)))
6737 (set (match_dup 0)
6738 (compare:CC (match_dup 3)
6739 (const_int 0)))]
6740 "")
6741
6742 (define_insn "*rotldi3_internal3"
6743 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6744 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6745 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6746 (const_int 0)))
6747 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6748 (rotate:DI (match_dup 1) (match_dup 2)))]
6749 "TARGET_64BIT"
6750 "@
6751 rldcl. %0,%1,%2,0
6752 rldicl. %0,%1,%H2,0
6753 #
6754 #"
6755 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6756 (set_attr "length" "4,4,8,8")])
6757
6758 (define_split
6759 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6760 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6761 (match_operand:DI 2 "reg_or_cint_operand" ""))
6762 (const_int 0)))
6763 (set (match_operand:DI 0 "gpc_reg_operand" "")
6764 (rotate:DI (match_dup 1) (match_dup 2)))]
6765 "TARGET_POWERPC64 && reload_completed"
6766 [(set (match_dup 0)
6767 (rotate:DI (match_dup 1) (match_dup 2)))
6768 (set (match_dup 3)
6769 (compare:CC (match_dup 0)
6770 (const_int 0)))]
6771 "")
6772
6773 (define_insn "*rotldi3_internal4"
6774 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6775 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6776 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6777 (match_operand:DI 3 "mask64_operand" "n,n")))]
6778 "TARGET_POWERPC64"
6779 "@
6780 rldc%B3 %0,%1,%2,%S3
6781 rldic%B3 %0,%1,%H2,%S3"
6782 [(set_attr "type" "var_shift_rotate,integer")])
6783
6784 (define_insn "*rotldi3_internal5"
6785 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6786 (compare:CC (and:DI
6787 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6788 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6789 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6790 (const_int 0)))
6791 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
6792 "TARGET_64BIT"
6793 "@
6794 rldc%B3. %4,%1,%2,%S3
6795 rldic%B3. %4,%1,%H2,%S3
6796 #
6797 #"
6798 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6799 (set_attr "length" "4,4,8,8")])
6800
6801 (define_split
6802 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6803 (compare:CC (and:DI
6804 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6805 (match_operand:DI 2 "reg_or_cint_operand" ""))
6806 (match_operand:DI 3 "mask64_operand" ""))
6807 (const_int 0)))
6808 (clobber (match_scratch:DI 4 ""))]
6809 "TARGET_POWERPC64 && reload_completed"
6810 [(set (match_dup 4)
6811 (and:DI (rotate:DI (match_dup 1)
6812 (match_dup 2))
6813 (match_dup 3)))
6814 (set (match_dup 0)
6815 (compare:CC (match_dup 4)
6816 (const_int 0)))]
6817 "")
6818
6819 (define_insn "*rotldi3_internal6"
6820 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
6821 (compare:CC (and:DI
6822 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6823 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6824 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6825 (const_int 0)))
6826 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6827 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6828 "TARGET_64BIT"
6829 "@
6830 rldc%B3. %0,%1,%2,%S3
6831 rldic%B3. %0,%1,%H2,%S3
6832 #
6833 #"
6834 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6835 (set_attr "length" "4,4,8,8")])
6836
6837 (define_split
6838 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6839 (compare:CC (and:DI
6840 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6841 (match_operand:DI 2 "reg_or_cint_operand" ""))
6842 (match_operand:DI 3 "mask64_operand" ""))
6843 (const_int 0)))
6844 (set (match_operand:DI 0 "gpc_reg_operand" "")
6845 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6846 "TARGET_POWERPC64 && reload_completed"
6847 [(set (match_dup 0)
6848 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6849 (set (match_dup 4)
6850 (compare:CC (match_dup 0)
6851 (const_int 0)))]
6852 "")
6853
6854 (define_insn "*rotldi3_internal7"
6855 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6856 (zero_extend:DI
6857 (subreg:QI
6858 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6859 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6860 "TARGET_POWERPC64"
6861 "@
6862 rldcl %0,%1,%2,56
6863 rldicl %0,%1,%H2,56"
6864 [(set_attr "type" "var_shift_rotate,integer")])
6865
6866 (define_insn "*rotldi3_internal8"
6867 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6868 (compare:CC (zero_extend:DI
6869 (subreg:QI
6870 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6871 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6872 (const_int 0)))
6873 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6874 "TARGET_64BIT"
6875 "@
6876 rldcl. %3,%1,%2,56
6877 rldicl. %3,%1,%H2,56
6878 #
6879 #"
6880 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6881 (set_attr "length" "4,4,8,8")])
6882
6883 (define_split
6884 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6885 (compare:CC (zero_extend:DI
6886 (subreg:QI
6887 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6888 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6889 (const_int 0)))
6890 (clobber (match_scratch:DI 3 ""))]
6891 "TARGET_POWERPC64 && reload_completed"
6892 [(set (match_dup 3)
6893 (zero_extend:DI (subreg:QI
6894 (rotate:DI (match_dup 1)
6895 (match_dup 2)) 0)))
6896 (set (match_dup 0)
6897 (compare:CC (match_dup 3)
6898 (const_int 0)))]
6899 "")
6900
6901 (define_insn "*rotldi3_internal9"
6902 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6903 (compare:CC (zero_extend:DI
6904 (subreg:QI
6905 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6906 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6907 (const_int 0)))
6908 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6909 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6910 "TARGET_64BIT"
6911 "@
6912 rldcl. %0,%1,%2,56
6913 rldicl. %0,%1,%H2,56
6914 #
6915 #"
6916 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6917 (set_attr "length" "4,4,8,8")])
6918
6919 (define_split
6920 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6921 (compare:CC (zero_extend:DI
6922 (subreg:QI
6923 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6924 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6925 (const_int 0)))
6926 (set (match_operand:DI 0 "gpc_reg_operand" "")
6927 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6928 "TARGET_POWERPC64 && reload_completed"
6929 [(set (match_dup 0)
6930 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6931 (set (match_dup 3)
6932 (compare:CC (match_dup 0)
6933 (const_int 0)))]
6934 "")
6935
6936 (define_insn "*rotldi3_internal10"
6937 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6938 (zero_extend:DI
6939 (subreg:HI
6940 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6941 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6942 "TARGET_POWERPC64"
6943 "@
6944 rldcl %0,%1,%2,48
6945 rldicl %0,%1,%H2,48"
6946 [(set_attr "type" "var_shift_rotate,integer")])
6947
6948 (define_insn "*rotldi3_internal11"
6949 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6950 (compare:CC (zero_extend:DI
6951 (subreg:HI
6952 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6953 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6954 (const_int 0)))
6955 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6956 "TARGET_64BIT"
6957 "@
6958 rldcl. %3,%1,%2,48
6959 rldicl. %3,%1,%H2,48
6960 #
6961 #"
6962 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6963 (set_attr "length" "4,4,8,8")])
6964
6965 (define_split
6966 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6967 (compare:CC (zero_extend:DI
6968 (subreg:HI
6969 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6970 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6971 (const_int 0)))
6972 (clobber (match_scratch:DI 3 ""))]
6973 "TARGET_POWERPC64 && reload_completed"
6974 [(set (match_dup 3)
6975 (zero_extend:DI (subreg:HI
6976 (rotate:DI (match_dup 1)
6977 (match_dup 2)) 0)))
6978 (set (match_dup 0)
6979 (compare:CC (match_dup 3)
6980 (const_int 0)))]
6981 "")
6982
6983 (define_insn "*rotldi3_internal12"
6984 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6985 (compare:CC (zero_extend:DI
6986 (subreg:HI
6987 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6988 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6989 (const_int 0)))
6990 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6991 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6992 "TARGET_64BIT"
6993 "@
6994 rldcl. %0,%1,%2,48
6995 rldicl. %0,%1,%H2,48
6996 #
6997 #"
6998 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6999 (set_attr "length" "4,4,8,8")])
7000
7001 (define_split
7002 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7003 (compare:CC (zero_extend:DI
7004 (subreg:HI
7005 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7006 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7007 (const_int 0)))
7008 (set (match_operand:DI 0 "gpc_reg_operand" "")
7009 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7010 "TARGET_POWERPC64 && reload_completed"
7011 [(set (match_dup 0)
7012 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7013 (set (match_dup 3)
7014 (compare:CC (match_dup 0)
7015 (const_int 0)))]
7016 "")
7017
7018 (define_insn "*rotldi3_internal13"
7019 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7020 (zero_extend:DI
7021 (subreg:SI
7022 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7023 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7024 "TARGET_POWERPC64"
7025 "@
7026 rldcl %0,%1,%2,32
7027 rldicl %0,%1,%H2,32"
7028 [(set_attr "type" "var_shift_rotate,integer")])
7029
7030 (define_insn "*rotldi3_internal14"
7031 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7032 (compare:CC (zero_extend:DI
7033 (subreg:SI
7034 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7035 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7036 (const_int 0)))
7037 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7038 "TARGET_64BIT"
7039 "@
7040 rldcl. %3,%1,%2,32
7041 rldicl. %3,%1,%H2,32
7042 #
7043 #"
7044 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7045 (set_attr "length" "4,4,8,8")])
7046
7047 (define_split
7048 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7049 (compare:CC (zero_extend:DI
7050 (subreg:SI
7051 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7052 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7053 (const_int 0)))
7054 (clobber (match_scratch:DI 3 ""))]
7055 "TARGET_POWERPC64 && reload_completed"
7056 [(set (match_dup 3)
7057 (zero_extend:DI (subreg:SI
7058 (rotate:DI (match_dup 1)
7059 (match_dup 2)) 0)))
7060 (set (match_dup 0)
7061 (compare:CC (match_dup 3)
7062 (const_int 0)))]
7063 "")
7064
7065 (define_insn "*rotldi3_internal15"
7066 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7067 (compare:CC (zero_extend:DI
7068 (subreg:SI
7069 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7070 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7071 (const_int 0)))
7072 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7073 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7074 "TARGET_64BIT"
7075 "@
7076 rldcl. %0,%1,%2,32
7077 rldicl. %0,%1,%H2,32
7078 #
7079 #"
7080 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7081 (set_attr "length" "4,4,8,8")])
7082
7083 (define_split
7084 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7085 (compare:CC (zero_extend:DI
7086 (subreg:SI
7087 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7088 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7089 (const_int 0)))
7090 (set (match_operand:DI 0 "gpc_reg_operand" "")
7091 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7092 "TARGET_POWERPC64 && reload_completed"
7093 [(set (match_dup 0)
7094 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7095 (set (match_dup 3)
7096 (compare:CC (match_dup 0)
7097 (const_int 0)))]
7098 "")
7099
7100 (define_expand "ashldi3"
7101 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7102 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7103 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7104 "TARGET_POWERPC64 || TARGET_POWER"
7105 "
7106 {
7107 if (TARGET_POWERPC64)
7108 ;
7109 else if (TARGET_POWER)
7110 {
7111 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
7112 DONE;
7113 }
7114 else
7115 FAIL;
7116 }")
7117
7118 (define_insn "*ashldi3_internal1"
7119 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7120 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7121 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7122 "TARGET_POWERPC64"
7123 "@
7124 sld %0,%1,%2
7125 sldi %0,%1,%H2"
7126 [(set_attr "type" "var_shift_rotate,shift")])
7127
7128 (define_insn "*ashldi3_internal2"
7129 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7130 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7131 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7132 (const_int 0)))
7133 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7134 "TARGET_64BIT"
7135 "@
7136 sld. %3,%1,%2
7137 sldi. %3,%1,%H2
7138 #
7139 #"
7140 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7141 (set_attr "length" "4,4,8,8")])
7142
7143 (define_split
7144 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7145 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7146 (match_operand:SI 2 "reg_or_cint_operand" ""))
7147 (const_int 0)))
7148 (clobber (match_scratch:DI 3 ""))]
7149 "TARGET_POWERPC64 && reload_completed"
7150 [(set (match_dup 3)
7151 (ashift:DI (match_dup 1) (match_dup 2)))
7152 (set (match_dup 0)
7153 (compare:CC (match_dup 3)
7154 (const_int 0)))]
7155 "")
7156
7157 (define_insn "*ashldi3_internal3"
7158 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7159 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7160 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7161 (const_int 0)))
7162 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7163 (ashift:DI (match_dup 1) (match_dup 2)))]
7164 "TARGET_64BIT"
7165 "@
7166 sld. %0,%1,%2
7167 sldi. %0,%1,%H2
7168 #
7169 #"
7170 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7171 (set_attr "length" "4,4,8,8")])
7172
7173 (define_split
7174 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7175 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7176 (match_operand:SI 2 "reg_or_cint_operand" ""))
7177 (const_int 0)))
7178 (set (match_operand:DI 0 "gpc_reg_operand" "")
7179 (ashift:DI (match_dup 1) (match_dup 2)))]
7180 "TARGET_POWERPC64 && reload_completed"
7181 [(set (match_dup 0)
7182 (ashift:DI (match_dup 1) (match_dup 2)))
7183 (set (match_dup 3)
7184 (compare:CC (match_dup 0)
7185 (const_int 0)))]
7186 "")
7187
7188 (define_insn "*ashldi3_internal4"
7189 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7190 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7191 (match_operand:SI 2 "const_int_operand" "i"))
7192 (match_operand:DI 3 "const_int_operand" "n")))]
7193 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7194 "rldic %0,%1,%H2,%W3")
7195
7196 (define_insn "ashldi3_internal5"
7197 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7198 (compare:CC
7199 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7200 (match_operand:SI 2 "const_int_operand" "i,i"))
7201 (match_operand:DI 3 "const_int_operand" "n,n"))
7202 (const_int 0)))
7203 (clobber (match_scratch:DI 4 "=r,r"))]
7204 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7205 "@
7206 rldic. %4,%1,%H2,%W3
7207 #"
7208 [(set_attr "type" "compare")
7209 (set_attr "length" "4,8")])
7210
7211 (define_split
7212 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7213 (compare:CC
7214 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7215 (match_operand:SI 2 "const_int_operand" ""))
7216 (match_operand:DI 3 "const_int_operand" ""))
7217 (const_int 0)))
7218 (clobber (match_scratch:DI 4 ""))]
7219 "TARGET_POWERPC64 && reload_completed
7220 && includes_rldic_lshift_p (operands[2], operands[3])"
7221 [(set (match_dup 4)
7222 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7223 (match_dup 3)))
7224 (set (match_dup 0)
7225 (compare:CC (match_dup 4)
7226 (const_int 0)))]
7227 "")
7228
7229 (define_insn "*ashldi3_internal6"
7230 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7231 (compare:CC
7232 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7233 (match_operand:SI 2 "const_int_operand" "i,i"))
7234 (match_operand:DI 3 "const_int_operand" "n,n"))
7235 (const_int 0)))
7236 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7237 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7238 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7239 "@
7240 rldic. %0,%1,%H2,%W3
7241 #"
7242 [(set_attr "type" "compare")
7243 (set_attr "length" "4,8")])
7244
7245 (define_split
7246 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7247 (compare:CC
7248 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7249 (match_operand:SI 2 "const_int_operand" ""))
7250 (match_operand:DI 3 "const_int_operand" ""))
7251 (const_int 0)))
7252 (set (match_operand:DI 0 "gpc_reg_operand" "")
7253 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7254 "TARGET_POWERPC64 && reload_completed
7255 && includes_rldic_lshift_p (operands[2], operands[3])"
7256 [(set (match_dup 0)
7257 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7258 (match_dup 3)))
7259 (set (match_dup 4)
7260 (compare:CC (match_dup 0)
7261 (const_int 0)))]
7262 "")
7263
7264 (define_insn "*ashldi3_internal7"
7265 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7266 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7267 (match_operand:SI 2 "const_int_operand" "i"))
7268 (match_operand:DI 3 "mask64_operand" "n")))]
7269 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7270 "rldicr %0,%1,%H2,%S3")
7271
7272 (define_insn "ashldi3_internal8"
7273 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7274 (compare:CC
7275 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7276 (match_operand:SI 2 "const_int_operand" "i,i"))
7277 (match_operand:DI 3 "mask64_operand" "n,n"))
7278 (const_int 0)))
7279 (clobber (match_scratch:DI 4 "=r,r"))]
7280 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7281 "@
7282 rldicr. %4,%1,%H2,%S3
7283 #"
7284 [(set_attr "type" "compare")
7285 (set_attr "length" "4,8")])
7286
7287 (define_split
7288 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7289 (compare:CC
7290 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7291 (match_operand:SI 2 "const_int_operand" ""))
7292 (match_operand:DI 3 "mask64_operand" ""))
7293 (const_int 0)))
7294 (clobber (match_scratch:DI 4 ""))]
7295 "TARGET_POWERPC64 && reload_completed
7296 && includes_rldicr_lshift_p (operands[2], operands[3])"
7297 [(set (match_dup 4)
7298 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7299 (match_dup 3)))
7300 (set (match_dup 0)
7301 (compare:CC (match_dup 4)
7302 (const_int 0)))]
7303 "")
7304
7305 (define_insn "*ashldi3_internal9"
7306 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7307 (compare:CC
7308 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7309 (match_operand:SI 2 "const_int_operand" "i,i"))
7310 (match_operand:DI 3 "mask64_operand" "n,n"))
7311 (const_int 0)))
7312 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7313 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7314 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7315 "@
7316 rldicr. %0,%1,%H2,%S3
7317 #"
7318 [(set_attr "type" "compare")
7319 (set_attr "length" "4,8")])
7320
7321 (define_split
7322 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7323 (compare:CC
7324 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7325 (match_operand:SI 2 "const_int_operand" ""))
7326 (match_operand:DI 3 "mask64_operand" ""))
7327 (const_int 0)))
7328 (set (match_operand:DI 0 "gpc_reg_operand" "")
7329 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7330 "TARGET_POWERPC64 && reload_completed
7331 && includes_rldicr_lshift_p (operands[2], operands[3])"
7332 [(set (match_dup 0)
7333 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7334 (match_dup 3)))
7335 (set (match_dup 4)
7336 (compare:CC (match_dup 0)
7337 (const_int 0)))]
7338 "")
7339
7340 (define_expand "lshrdi3"
7341 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7342 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7343 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7344 "TARGET_POWERPC64 || TARGET_POWER"
7345 "
7346 {
7347 if (TARGET_POWERPC64)
7348 ;
7349 else if (TARGET_POWER)
7350 {
7351 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7352 DONE;
7353 }
7354 else
7355 FAIL;
7356 }")
7357
7358 (define_insn "*lshrdi3_internal1"
7359 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7360 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7361 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7362 "TARGET_POWERPC64"
7363 "@
7364 srd %0,%1,%2
7365 srdi %0,%1,%H2"
7366 [(set_attr "type" "var_shift_rotate,shift")])
7367
7368 (define_insn "*lshrdi3_internal2"
7369 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7370 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7371 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7372 (const_int 0)))
7373 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7374 "TARGET_64BIT "
7375 "@
7376 srd. %3,%1,%2
7377 srdi. %3,%1,%H2
7378 #
7379 #"
7380 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7381 (set_attr "length" "4,4,8,8")])
7382
7383 (define_split
7384 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7385 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7386 (match_operand:SI 2 "reg_or_cint_operand" ""))
7387 (const_int 0)))
7388 (clobber (match_scratch:DI 3 ""))]
7389 "TARGET_POWERPC64 && reload_completed"
7390 [(set (match_dup 3)
7391 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7392 (set (match_dup 0)
7393 (compare:CC (match_dup 3)
7394 (const_int 0)))]
7395 "")
7396
7397 (define_insn "*lshrdi3_internal3"
7398 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7399 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7400 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7401 (const_int 0)))
7402 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7403 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7404 "TARGET_64BIT"
7405 "@
7406 srd. %0,%1,%2
7407 srdi. %0,%1,%H2
7408 #
7409 #"
7410 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7411 (set_attr "length" "4,4,8,8")])
7412
7413 (define_split
7414 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7415 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7416 (match_operand:SI 2 "reg_or_cint_operand" ""))
7417 (const_int 0)))
7418 (set (match_operand:DI 0 "gpc_reg_operand" "")
7419 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7420 "TARGET_POWERPC64 && reload_completed"
7421 [(set (match_dup 0)
7422 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7423 (set (match_dup 3)
7424 (compare:CC (match_dup 0)
7425 (const_int 0)))]
7426 "")
7427
7428 (define_expand "ashrdi3"
7429 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7430 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7431 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7432 "WORDS_BIG_ENDIAN"
7433 "
7434 {
7435 if (TARGET_POWERPC64)
7436 ;
7437 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7438 {
7439 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7440 DONE;
7441 }
7442 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7443 && WORDS_BIG_ENDIAN)
7444 {
7445 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7446 DONE;
7447 }
7448 else
7449 FAIL;
7450 }")
7451
7452 (define_insn "*ashrdi3_internal1"
7453 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7454 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7455 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7456 "TARGET_POWERPC64"
7457 "@
7458 srad %0,%1,%2
7459 sradi %0,%1,%H2"
7460 [(set_attr "type" "var_shift_rotate,shift")])
7461
7462 (define_insn "*ashrdi3_internal2"
7463 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7464 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7465 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7466 (const_int 0)))
7467 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7468 "TARGET_64BIT"
7469 "@
7470 srad. %3,%1,%2
7471 sradi. %3,%1,%H2
7472 #
7473 #"
7474 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7475 (set_attr "length" "4,4,8,8")])
7476
7477 (define_split
7478 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7479 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7480 (match_operand:SI 2 "reg_or_cint_operand" ""))
7481 (const_int 0)))
7482 (clobber (match_scratch:DI 3 ""))]
7483 "TARGET_POWERPC64 && reload_completed"
7484 [(set (match_dup 3)
7485 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7486 (set (match_dup 0)
7487 (compare:CC (match_dup 3)
7488 (const_int 0)))]
7489 "")
7490
7491 (define_insn "*ashrdi3_internal3"
7492 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7493 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7494 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7495 (const_int 0)))
7496 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7497 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7498 "TARGET_64BIT"
7499 "@
7500 srad. %0,%1,%2
7501 sradi. %0,%1,%H2
7502 #
7503 #"
7504 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7505 (set_attr "length" "4,4,8,8")])
7506
7507 (define_split
7508 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7509 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7510 (match_operand:SI 2 "reg_or_cint_operand" ""))
7511 (const_int 0)))
7512 (set (match_operand:DI 0 "gpc_reg_operand" "")
7513 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7514 "TARGET_POWERPC64 && reload_completed"
7515 [(set (match_dup 0)
7516 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7517 (set (match_dup 3)
7518 (compare:CC (match_dup 0)
7519 (const_int 0)))]
7520 "")
7521
7522 (define_insn "anddi3"
7523 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7524 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7525 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7526 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7527 "TARGET_POWERPC64"
7528 "@
7529 and %0,%1,%2
7530 rldic%B2 %0,%1,0,%S2
7531 rlwinm %0,%1,0,%m2,%M2
7532 andi. %0,%1,%b2
7533 andis. %0,%1,%u2
7534 #"
7535 [(set_attr "type" "*,*,*,compare,compare,*")
7536 (set_attr "length" "4,4,4,4,4,8")])
7537
7538 (define_split
7539 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7540 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7541 (match_operand:DI 2 "mask64_2_operand" "")))
7542 (clobber (match_scratch:CC 3 ""))]
7543 "TARGET_POWERPC64
7544 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7545 && !mask_operand (operands[2], DImode)
7546 && !mask64_operand (operands[2], DImode)"
7547 [(set (match_dup 0)
7548 (and:DI (rotate:DI (match_dup 1)
7549 (match_dup 4))
7550 (match_dup 5)))
7551 (set (match_dup 0)
7552 (and:DI (rotate:DI (match_dup 0)
7553 (match_dup 6))
7554 (match_dup 7)))]
7555 {
7556 build_mask64_2_operands (operands[2], &operands[4]);
7557 })
7558
7559 (define_insn "*anddi3_internal2"
7560 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7561 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7562 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7563 (const_int 0)))
7564 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7565 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7566 "TARGET_64BIT"
7567 "@
7568 and. %3,%1,%2
7569 rldic%B2. %3,%1,0,%S2
7570 rlwinm. %3,%1,0,%m2,%M2
7571 andi. %3,%1,%b2
7572 andis. %3,%1,%u2
7573 #
7574 #
7575 #
7576 #
7577 #
7578 #
7579 #"
7580 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7581 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7582
7583 (define_split
7584 [(set (match_operand:CC 0 "cc_reg_operand" "")
7585 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7586 (match_operand:DI 2 "mask64_2_operand" ""))
7587 (const_int 0)))
7588 (clobber (match_scratch:DI 3 ""))
7589 (clobber (match_scratch:CC 4 ""))]
7590 "TARGET_64BIT && reload_completed
7591 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7592 && !mask_operand (operands[2], DImode)
7593 && !mask64_operand (operands[2], DImode)"
7594 [(set (match_dup 3)
7595 (and:DI (rotate:DI (match_dup 1)
7596 (match_dup 5))
7597 (match_dup 6)))
7598 (parallel [(set (match_dup 0)
7599 (compare:CC (and:DI (rotate:DI (match_dup 3)
7600 (match_dup 7))
7601 (match_dup 8))
7602 (const_int 0)))
7603 (clobber (match_dup 3))])]
7604 "
7605 {
7606 build_mask64_2_operands (operands[2], &operands[5]);
7607 }")
7608
7609 (define_insn "*anddi3_internal3"
7610 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7611 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7612 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7613 (const_int 0)))
7614 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
7615 (and:DI (match_dup 1) (match_dup 2)))
7616 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7617 "TARGET_64BIT"
7618 "@
7619 and. %0,%1,%2
7620 rldic%B2. %0,%1,0,%S2
7621 rlwinm. %0,%1,0,%m2,%M2
7622 andi. %0,%1,%b2
7623 andis. %0,%1,%u2
7624 #
7625 #
7626 #
7627 #
7628 #
7629 #
7630 #"
7631 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7632 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7633
7634 (define_split
7635 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7636 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7637 (match_operand:DI 2 "and64_2_operand" ""))
7638 (const_int 0)))
7639 (set (match_operand:DI 0 "gpc_reg_operand" "")
7640 (and:DI (match_dup 1) (match_dup 2)))
7641 (clobber (match_scratch:CC 4 ""))]
7642 "TARGET_64BIT && reload_completed"
7643 [(parallel [(set (match_dup 0)
7644 (and:DI (match_dup 1) (match_dup 2)))
7645 (clobber (match_dup 4))])
7646 (set (match_dup 3)
7647 (compare:CC (match_dup 0)
7648 (const_int 0)))]
7649 "")
7650
7651 (define_split
7652 [(set (match_operand:CC 3 "cc_reg_operand" "")
7653 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7654 (match_operand:DI 2 "mask64_2_operand" ""))
7655 (const_int 0)))
7656 (set (match_operand:DI 0 "gpc_reg_operand" "")
7657 (and:DI (match_dup 1) (match_dup 2)))
7658 (clobber (match_scratch:CC 4 ""))]
7659 "TARGET_64BIT && reload_completed
7660 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7661 && !mask_operand (operands[2], DImode)
7662 && !mask64_operand (operands[2], DImode)"
7663 [(set (match_dup 0)
7664 (and:DI (rotate:DI (match_dup 1)
7665 (match_dup 5))
7666 (match_dup 6)))
7667 (parallel [(set (match_dup 3)
7668 (compare:CC (and:DI (rotate:DI (match_dup 0)
7669 (match_dup 7))
7670 (match_dup 8))
7671 (const_int 0)))
7672 (set (match_dup 0)
7673 (and:DI (rotate:DI (match_dup 0)
7674 (match_dup 7))
7675 (match_dup 8)))])]
7676 "
7677 {
7678 build_mask64_2_operands (operands[2], &operands[5]);
7679 }")
7680
7681 (define_expand "iordi3"
7682 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7683 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7684 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7685 "TARGET_POWERPC64"
7686 "
7687 {
7688 if (non_logical_cint_operand (operands[2], DImode))
7689 {
7690 HOST_WIDE_INT value;
7691 rtx tmp = ((!can_create_pseudo_p ()
7692 || rtx_equal_p (operands[0], operands[1]))
7693 ? operands[0] : gen_reg_rtx (DImode));
7694
7695 if (GET_CODE (operands[2]) == CONST_INT)
7696 {
7697 value = INTVAL (operands[2]);
7698 emit_insn (gen_iordi3 (tmp, operands[1],
7699 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7700 }
7701 else
7702 {
7703 value = CONST_DOUBLE_LOW (operands[2]);
7704 emit_insn (gen_iordi3 (tmp, operands[1],
7705 immed_double_const (value
7706 & (~ (HOST_WIDE_INT) 0xffff),
7707 0, DImode)));
7708 }
7709
7710 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7711 DONE;
7712 }
7713 }")
7714
7715 (define_expand "xordi3"
7716 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7717 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7718 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7719 "TARGET_POWERPC64"
7720 "
7721 {
7722 if (non_logical_cint_operand (operands[2], DImode))
7723 {
7724 HOST_WIDE_INT value;
7725 rtx tmp = ((!can_create_pseudo_p ()
7726 || rtx_equal_p (operands[0], operands[1]))
7727 ? operands[0] : gen_reg_rtx (DImode));
7728
7729 if (GET_CODE (operands[2]) == CONST_INT)
7730 {
7731 value = INTVAL (operands[2]);
7732 emit_insn (gen_xordi3 (tmp, operands[1],
7733 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7734 }
7735 else
7736 {
7737 value = CONST_DOUBLE_LOW (operands[2]);
7738 emit_insn (gen_xordi3 (tmp, operands[1],
7739 immed_double_const (value
7740 & (~ (HOST_WIDE_INT) 0xffff),
7741 0, DImode)));
7742 }
7743
7744 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7745 DONE;
7746 }
7747 }")
7748
7749 (define_insn "*booldi3_internal1"
7750 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7751 (match_operator:DI 3 "boolean_or_operator"
7752 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7753 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7754 "TARGET_POWERPC64"
7755 "@
7756 %q3 %0,%1,%2
7757 %q3i %0,%1,%b2
7758 %q3is %0,%1,%u2")
7759
7760 (define_insn "*booldi3_internal2"
7761 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7762 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7763 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7764 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7765 (const_int 0)))
7766 (clobber (match_scratch:DI 3 "=r,r"))]
7767 "TARGET_64BIT"
7768 "@
7769 %q4. %3,%1,%2
7770 #"
7771 [(set_attr "type" "compare")
7772 (set_attr "length" "4,8")])
7773
7774 (define_split
7775 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7776 (compare:CC (match_operator:DI 4 "boolean_operator"
7777 [(match_operand:DI 1 "gpc_reg_operand" "")
7778 (match_operand:DI 2 "gpc_reg_operand" "")])
7779 (const_int 0)))
7780 (clobber (match_scratch:DI 3 ""))]
7781 "TARGET_POWERPC64 && reload_completed"
7782 [(set (match_dup 3) (match_dup 4))
7783 (set (match_dup 0)
7784 (compare:CC (match_dup 3)
7785 (const_int 0)))]
7786 "")
7787
7788 (define_insn "*booldi3_internal3"
7789 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7790 (compare:CC (match_operator:DI 4 "boolean_operator"
7791 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7792 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7793 (const_int 0)))
7794 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7795 (match_dup 4))]
7796 "TARGET_64BIT"
7797 "@
7798 %q4. %0,%1,%2
7799 #"
7800 [(set_attr "type" "compare")
7801 (set_attr "length" "4,8")])
7802
7803 (define_split
7804 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7805 (compare:CC (match_operator:DI 4 "boolean_operator"
7806 [(match_operand:DI 1 "gpc_reg_operand" "")
7807 (match_operand:DI 2 "gpc_reg_operand" "")])
7808 (const_int 0)))
7809 (set (match_operand:DI 0 "gpc_reg_operand" "")
7810 (match_dup 4))]
7811 "TARGET_POWERPC64 && reload_completed"
7812 [(set (match_dup 0) (match_dup 4))
7813 (set (match_dup 3)
7814 (compare:CC (match_dup 0)
7815 (const_int 0)))]
7816 "")
7817
7818 ;; Split a logical operation that we can't do in one insn into two insns,
7819 ;; each of which does one 16-bit part. This is used by combine.
7820
7821 (define_split
7822 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7823 (match_operator:DI 3 "boolean_or_operator"
7824 [(match_operand:DI 1 "gpc_reg_operand" "")
7825 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7826 "TARGET_POWERPC64"
7827 [(set (match_dup 0) (match_dup 4))
7828 (set (match_dup 0) (match_dup 5))]
7829 "
7830 {
7831 rtx i3,i4;
7832
7833 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7834 {
7835 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7836 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7837 0, DImode);
7838 i4 = GEN_INT (value & 0xffff);
7839 }
7840 else
7841 {
7842 i3 = GEN_INT (INTVAL (operands[2])
7843 & (~ (HOST_WIDE_INT) 0xffff));
7844 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7845 }
7846 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7847 operands[1], i3);
7848 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7849 operands[0], i4);
7850 }")
7851
7852 (define_insn "*boolcdi3_internal1"
7853 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7854 (match_operator:DI 3 "boolean_operator"
7855 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7856 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7857 "TARGET_POWERPC64"
7858 "%q3 %0,%2,%1")
7859
7860 (define_insn "*boolcdi3_internal2"
7861 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7862 (compare:CC (match_operator:DI 4 "boolean_operator"
7863 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7864 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7865 (const_int 0)))
7866 (clobber (match_scratch:DI 3 "=r,r"))]
7867 "TARGET_64BIT"
7868 "@
7869 %q4. %3,%2,%1
7870 #"
7871 [(set_attr "type" "compare")
7872 (set_attr "length" "4,8")])
7873
7874 (define_split
7875 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7876 (compare:CC (match_operator:DI 4 "boolean_operator"
7877 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7878 (match_operand:DI 2 "gpc_reg_operand" "")])
7879 (const_int 0)))
7880 (clobber (match_scratch:DI 3 ""))]
7881 "TARGET_POWERPC64 && reload_completed"
7882 [(set (match_dup 3) (match_dup 4))
7883 (set (match_dup 0)
7884 (compare:CC (match_dup 3)
7885 (const_int 0)))]
7886 "")
7887
7888 (define_insn "*boolcdi3_internal3"
7889 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7890 (compare:CC (match_operator:DI 4 "boolean_operator"
7891 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7892 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7893 (const_int 0)))
7894 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7895 (match_dup 4))]
7896 "TARGET_64BIT"
7897 "@
7898 %q4. %0,%2,%1
7899 #"
7900 [(set_attr "type" "compare")
7901 (set_attr "length" "4,8")])
7902
7903 (define_split
7904 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7905 (compare:CC (match_operator:DI 4 "boolean_operator"
7906 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7907 (match_operand:DI 2 "gpc_reg_operand" "")])
7908 (const_int 0)))
7909 (set (match_operand:DI 0 "gpc_reg_operand" "")
7910 (match_dup 4))]
7911 "TARGET_POWERPC64 && reload_completed"
7912 [(set (match_dup 0) (match_dup 4))
7913 (set (match_dup 3)
7914 (compare:CC (match_dup 0)
7915 (const_int 0)))]
7916 "")
7917
7918 (define_insn "*boolccdi3_internal1"
7919 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7920 (match_operator:DI 3 "boolean_operator"
7921 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7922 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7923 "TARGET_POWERPC64"
7924 "%q3 %0,%1,%2")
7925
7926 (define_insn "*boolccdi3_internal2"
7927 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7928 (compare:CC (match_operator:DI 4 "boolean_operator"
7929 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7930 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7931 (const_int 0)))
7932 (clobber (match_scratch:DI 3 "=r,r"))]
7933 "TARGET_64BIT"
7934 "@
7935 %q4. %3,%1,%2
7936 #"
7937 [(set_attr "type" "compare")
7938 (set_attr "length" "4,8")])
7939
7940 (define_split
7941 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7942 (compare:CC (match_operator:DI 4 "boolean_operator"
7943 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7944 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7945 (const_int 0)))
7946 (clobber (match_scratch:DI 3 ""))]
7947 "TARGET_POWERPC64 && reload_completed"
7948 [(set (match_dup 3) (match_dup 4))
7949 (set (match_dup 0)
7950 (compare:CC (match_dup 3)
7951 (const_int 0)))]
7952 "")
7953
7954 (define_insn "*boolccdi3_internal3"
7955 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7956 (compare:CC (match_operator:DI 4 "boolean_operator"
7957 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7958 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7959 (const_int 0)))
7960 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7961 (match_dup 4))]
7962 "TARGET_64BIT"
7963 "@
7964 %q4. %0,%1,%2
7965 #"
7966 [(set_attr "type" "compare")
7967 (set_attr "length" "4,8")])
7968
7969 (define_split
7970 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7971 (compare:CC (match_operator:DI 4 "boolean_operator"
7972 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7973 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7974 (const_int 0)))
7975 (set (match_operand:DI 0 "gpc_reg_operand" "")
7976 (match_dup 4))]
7977 "TARGET_POWERPC64 && reload_completed"
7978 [(set (match_dup 0) (match_dup 4))
7979 (set (match_dup 3)
7980 (compare:CC (match_dup 0)
7981 (const_int 0)))]
7982 "")
7983 \f
7984 ;; Now define ways of moving data around.
7985
7986 ;; Set up a register with a value from the GOT table
7987
7988 (define_expand "movsi_got"
7989 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7990 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7991 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7992 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7993 "
7994 {
7995 if (GET_CODE (operands[1]) == CONST)
7996 {
7997 rtx offset = const0_rtx;
7998 HOST_WIDE_INT value;
7999
8000 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8001 value = INTVAL (offset);
8002 if (value != 0)
8003 {
8004 rtx tmp = (!can_create_pseudo_p ()
8005 ? operands[0]
8006 : gen_reg_rtx (Pmode));
8007 emit_insn (gen_movsi_got (tmp, operands[1]));
8008 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8009 DONE;
8010 }
8011 }
8012
8013 operands[2] = rs6000_got_register (operands[1]);
8014 }")
8015
8016 (define_insn "*movsi_got_internal"
8017 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8018 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8019 (match_operand:SI 2 "gpc_reg_operand" "b")]
8020 UNSPEC_MOVSI_GOT))]
8021 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8022 "{l|lwz} %0,%a1@got(%2)"
8023 [(set_attr "type" "load")])
8024
8025 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
8026 ;; didn't get allocated to a hard register.
8027 (define_split
8028 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8029 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8030 (match_operand:SI 2 "memory_operand" "")]
8031 UNSPEC_MOVSI_GOT))]
8032 "DEFAULT_ABI == ABI_V4
8033 && flag_pic == 1
8034 && (reload_in_progress || reload_completed)"
8035 [(set (match_dup 0) (match_dup 2))
8036 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8037 UNSPEC_MOVSI_GOT))]
8038 "")
8039
8040 ;; For SI, we special-case integers that can't be loaded in one insn. We
8041 ;; do the load 16-bits at a time. We could do this by loading from memory,
8042 ;; and this is even supposed to be faster, but it is simpler not to get
8043 ;; integers in the TOC.
8044 (define_insn "movsi_low"
8045 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8046 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
8047 (match_operand 2 "" ""))))]
8048 "TARGET_MACHO && ! TARGET_64BIT"
8049 "{l|lwz} %0,lo16(%2)(%1)"
8050 [(set_attr "type" "load")
8051 (set_attr "length" "4")])
8052
8053 (define_insn "*movsi_internal1"
8054 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
8055 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
8056 "gpc_reg_operand (operands[0], SImode)
8057 || gpc_reg_operand (operands[1], SImode)"
8058 "@
8059 mr %0,%1
8060 {cal|la} %0,%a1
8061 {l%U1%X1|lwz%U1%X1} %0,%1
8062 {st%U0%X0|stw%U0%X0} %1,%0
8063 {lil|li} %0,%1
8064 {liu|lis} %0,%v1
8065 #
8066 {cal|la} %0,%a1
8067 mf%1 %0
8068 mt%0 %1
8069 mt%0 %1
8070 mt%0 %1
8071 {cror 0,0,0|nop}"
8072 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
8073 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
8074
8075 ;; Split a load of a large constant into the appropriate two-insn
8076 ;; sequence.
8077
8078 (define_split
8079 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8080 (match_operand:SI 1 "const_int_operand" ""))]
8081 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
8082 && (INTVAL (operands[1]) & 0xffff) != 0"
8083 [(set (match_dup 0)
8084 (match_dup 2))
8085 (set (match_dup 0)
8086 (ior:SI (match_dup 0)
8087 (match_dup 3)))]
8088 "
8089 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8090
8091 if (tem == operands[0])
8092 DONE;
8093 else
8094 FAIL;
8095 }")
8096
8097 (define_insn "*mov<mode>_internal2"
8098 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8099 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
8100 (const_int 0)))
8101 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8102 ""
8103 "@
8104 {cmpi|cmp<wd>i} %2,%0,0
8105 mr. %0,%1
8106 #"
8107 [(set_attr "type" "cmp,compare,cmp")
8108 (set_attr "length" "4,4,8")])
8109
8110 (define_split
8111 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8112 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
8113 (const_int 0)))
8114 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8115 "reload_completed"
8116 [(set (match_dup 0) (match_dup 1))
8117 (set (match_dup 2)
8118 (compare:CC (match_dup 0)
8119 (const_int 0)))]
8120 "")
8121 \f
8122 (define_insn "*movhi_internal"
8123 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8124 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8125 "gpc_reg_operand (operands[0], HImode)
8126 || gpc_reg_operand (operands[1], HImode)"
8127 "@
8128 mr %0,%1
8129 lhz%U1%X1 %0,%1
8130 sth%U0%X0 %1,%0
8131 {lil|li} %0,%w1
8132 mf%1 %0
8133 mt%0 %1
8134 mt%0 %1
8135 {cror 0,0,0|nop}"
8136 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8137
8138 (define_expand "mov<mode>"
8139 [(set (match_operand:INT 0 "general_operand" "")
8140 (match_operand:INT 1 "any_operand" ""))]
8141 ""
8142 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8143
8144 (define_insn "*movqi_internal"
8145 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8146 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8147 "gpc_reg_operand (operands[0], QImode)
8148 || gpc_reg_operand (operands[1], QImode)"
8149 "@
8150 mr %0,%1
8151 lbz%U1%X1 %0,%1
8152 stb%U0%X0 %1,%0
8153 {lil|li} %0,%1
8154 mf%1 %0
8155 mt%0 %1
8156 mt%0 %1
8157 {cror 0,0,0|nop}"
8158 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8159 \f
8160 ;; Here is how to move condition codes around. When we store CC data in
8161 ;; an integer register or memory, we store just the high-order 4 bits.
8162 ;; This lets us not shift in the most common case of CR0.
8163 (define_expand "movcc"
8164 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8165 (match_operand:CC 1 "nonimmediate_operand" ""))]
8166 ""
8167 "")
8168
8169 (define_insn "*movcc_internal1"
8170 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
8171 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
8172 "register_operand (operands[0], CCmode)
8173 || register_operand (operands[1], CCmode)"
8174 "@
8175 mcrf %0,%1
8176 mtcrf 128,%1
8177 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
8178 crxor %0,%0,%0
8179 mfcr %0%Q1
8180 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
8181 mr %0,%1
8182 {lil|li} %0,%1
8183 mf%1 %0
8184 mt%0 %1
8185 mt%0 %1
8186 {l%U1%X1|lwz%U1%X1} %0,%1
8187 {st%U0%U1|stw%U0%U1} %1,%0"
8188 [(set (attr "type")
8189 (cond [(eq_attr "alternative" "0,3")
8190 (const_string "cr_logical")
8191 (eq_attr "alternative" "1,2")
8192 (const_string "mtcr")
8193 (eq_attr "alternative" "6,7,9")
8194 (const_string "integer")
8195 (eq_attr "alternative" "8")
8196 (const_string "mfjmpr")
8197 (eq_attr "alternative" "10")
8198 (const_string "mtjmpr")
8199 (eq_attr "alternative" "11")
8200 (const_string "load")
8201 (eq_attr "alternative" "12")
8202 (const_string "store")
8203 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
8204 (const_string "mfcrf")
8205 ]
8206 (const_string "mfcr")))
8207 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
8208 \f
8209 ;; For floating-point, we normally deal with the floating-point registers
8210 ;; unless -msoft-float is used. The sole exception is that parameter passing
8211 ;; can produce floating-point values in fixed-point registers. Unless the
8212 ;; value is a simple constant or already in memory, we deal with this by
8213 ;; allocating memory and copying the value explicitly via that memory location.
8214 (define_expand "movsf"
8215 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8216 (match_operand:SF 1 "any_operand" ""))]
8217 ""
8218 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
8219
8220 (define_split
8221 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8222 (match_operand:SF 1 "const_double_operand" ""))]
8223 "reload_completed
8224 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8225 || (GET_CODE (operands[0]) == SUBREG
8226 && GET_CODE (SUBREG_REG (operands[0])) == REG
8227 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8228 [(set (match_dup 2) (match_dup 3))]
8229 "
8230 {
8231 long l;
8232 REAL_VALUE_TYPE rv;
8233
8234 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8235 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
8236
8237 if (! TARGET_POWERPC64)
8238 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
8239 else
8240 operands[2] = gen_lowpart (SImode, operands[0]);
8241
8242 operands[3] = gen_int_mode (l, SImode);
8243 }")
8244
8245 (define_insn "*movsf_hardfloat"
8246 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
8247 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
8248 "(gpc_reg_operand (operands[0], SFmode)
8249 || gpc_reg_operand (operands[1], SFmode))
8250 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
8251 "@
8252 mr %0,%1
8253 {l%U1%X1|lwz%U1%X1} %0,%1
8254 {st%U0%X0|stw%U0%X0} %1,%0
8255 fmr %0,%1
8256 lfs%U1%X1 %0,%1
8257 stfs%U0%X0 %1,%0
8258 mt%0 %1
8259 mt%0 %1
8260 mf%1 %0
8261 {cror 0,0,0|nop}
8262 #
8263 #"
8264 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
8265 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
8266
8267 (define_insn "*movsf_softfloat"
8268 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
8269 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
8270 "(gpc_reg_operand (operands[0], SFmode)
8271 || gpc_reg_operand (operands[1], SFmode))
8272 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
8273 "@
8274 mr %0,%1
8275 mt%0 %1
8276 mt%0 %1
8277 mf%1 %0
8278 {l%U1%X1|lwz%U1%X1} %0,%1
8279 {st%U0%X0|stw%U0%X0} %1,%0
8280 {lil|li} %0,%1
8281 {liu|lis} %0,%v1
8282 {cal|la} %0,%a1
8283 #
8284 #
8285 {cror 0,0,0|nop}"
8286 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
8287 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
8288
8289 \f
8290 (define_expand "movdf"
8291 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8292 (match_operand:DF 1 "any_operand" ""))]
8293 ""
8294 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
8295
8296 (define_split
8297 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8298 (match_operand:DF 1 "const_int_operand" ""))]
8299 "! TARGET_POWERPC64 && reload_completed
8300 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8301 || (GET_CODE (operands[0]) == SUBREG
8302 && GET_CODE (SUBREG_REG (operands[0])) == REG
8303 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8304 [(set (match_dup 2) (match_dup 4))
8305 (set (match_dup 3) (match_dup 1))]
8306 "
8307 {
8308 int endian = (WORDS_BIG_ENDIAN == 0);
8309 HOST_WIDE_INT value = INTVAL (operands[1]);
8310
8311 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8312 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8313 #if HOST_BITS_PER_WIDE_INT == 32
8314 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8315 #else
8316 operands[4] = GEN_INT (value >> 32);
8317 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8318 #endif
8319 }")
8320
8321 (define_split
8322 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8323 (match_operand:DF 1 "const_double_operand" ""))]
8324 "! TARGET_POWERPC64 && reload_completed
8325 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8326 || (GET_CODE (operands[0]) == SUBREG
8327 && GET_CODE (SUBREG_REG (operands[0])) == REG
8328 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8329 [(set (match_dup 2) (match_dup 4))
8330 (set (match_dup 3) (match_dup 5))]
8331 "
8332 {
8333 int endian = (WORDS_BIG_ENDIAN == 0);
8334 long l[2];
8335 REAL_VALUE_TYPE rv;
8336
8337 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8338 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8339
8340 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8341 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8342 operands[4] = gen_int_mode (l[endian], SImode);
8343 operands[5] = gen_int_mode (l[1 - endian], SImode);
8344 }")
8345
8346 (define_split
8347 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8348 (match_operand:DF 1 "const_double_operand" ""))]
8349 "TARGET_POWERPC64 && reload_completed
8350 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8351 || (GET_CODE (operands[0]) == SUBREG
8352 && GET_CODE (SUBREG_REG (operands[0])) == REG
8353 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8354 [(set (match_dup 2) (match_dup 3))]
8355 "
8356 {
8357 int endian = (WORDS_BIG_ENDIAN == 0);
8358 long l[2];
8359 REAL_VALUE_TYPE rv;
8360 #if HOST_BITS_PER_WIDE_INT >= 64
8361 HOST_WIDE_INT val;
8362 #endif
8363
8364 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8365 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8366
8367 operands[2] = gen_lowpart (DImode, operands[0]);
8368 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8369 #if HOST_BITS_PER_WIDE_INT >= 64
8370 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8371 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8372
8373 operands[3] = gen_int_mode (val, DImode);
8374 #else
8375 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8376 #endif
8377 }")
8378
8379 ;; Don't have reload use general registers to load a constant. First,
8380 ;; it might not work if the output operand is the equivalent of
8381 ;; a non-offsettable memref, but also it is less efficient than loading
8382 ;; the constant into an FP register, since it will probably be used there.
8383 ;; The "??" is a kludge until we can figure out a more reasonable way
8384 ;; of handling these non-offsettable values.
8385 (define_insn "*movdf_hardfloat32"
8386 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8387 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
8388 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8389 && (gpc_reg_operand (operands[0], DFmode)
8390 || gpc_reg_operand (operands[1], DFmode))"
8391 "*
8392 {
8393 switch (which_alternative)
8394 {
8395 default:
8396 gcc_unreachable ();
8397 case 0:
8398 /* We normally copy the low-numbered register first. However, if
8399 the first register operand 0 is the same as the second register
8400 of operand 1, we must copy in the opposite order. */
8401 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8402 return \"mr %L0,%L1\;mr %0,%1\";
8403 else
8404 return \"mr %0,%1\;mr %L0,%L1\";
8405 case 1:
8406 if (rs6000_offsettable_memref_p (operands[1])
8407 || (GET_CODE (operands[1]) == MEM
8408 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8409 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8410 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC
8411 || GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)))
8412 {
8413 /* If the low-address word is used in the address, we must load
8414 it last. Otherwise, load it first. Note that we cannot have
8415 auto-increment in that case since the address register is
8416 known to be dead. */
8417 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8418 operands[1], 0))
8419 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8420 else
8421 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
8422 }
8423 else
8424 {
8425 rtx addreg;
8426
8427 addreg = find_addr_reg (XEXP (operands[1], 0));
8428 if (refers_to_regno_p (REGNO (operands[0]),
8429 REGNO (operands[0]) + 1,
8430 operands[1], 0))
8431 {
8432 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8433 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
8434 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8435 return \"{l%X1|lwz%X1} %0,%1\";
8436 }
8437 else
8438 {
8439 output_asm_insn (\"{l%X1|lwz%X1} %0,%1\", operands);
8440 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8441 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
8442 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8443 return \"\";
8444 }
8445 }
8446 case 2:
8447 if (rs6000_offsettable_memref_p (operands[0])
8448 || (GET_CODE (operands[0]) == MEM
8449 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8450 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8451 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
8452 || GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)))
8453 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
8454 else
8455 {
8456 rtx addreg;
8457
8458 addreg = find_addr_reg (XEXP (operands[0], 0));
8459 output_asm_insn (\"{st%X0|stw%X0} %1,%0\", operands);
8460 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8461 output_asm_insn (\"{st%X0|stw%X0} %L1,%0\", operands);
8462 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8463 return \"\";
8464 }
8465 case 3:
8466 return \"fmr %0,%1\";
8467 case 4:
8468 return \"lfd%U1%X1 %0,%1\";
8469 case 5:
8470 return \"stfd%U0%X0 %1,%0\";
8471 case 6:
8472 case 7:
8473 case 8:
8474 return \"#\";
8475 }
8476 }"
8477 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
8478 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
8479
8480 (define_insn "*movdf_softfloat32"
8481 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8482 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8483 "! TARGET_POWERPC64
8484 && ((TARGET_FPRS && !TARGET_DOUBLE_FLOAT)
8485 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8486 && (gpc_reg_operand (operands[0], DFmode)
8487 || gpc_reg_operand (operands[1], DFmode))"
8488 "*
8489 {
8490 switch (which_alternative)
8491 {
8492 default:
8493 gcc_unreachable ();
8494 case 0:
8495 /* We normally copy the low-numbered register first. However, if
8496 the first register operand 0 is the same as the second register of
8497 operand 1, we must copy in the opposite order. */
8498 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8499 return \"mr %L0,%L1\;mr %0,%1\";
8500 else
8501 return \"mr %0,%1\;mr %L0,%L1\";
8502 case 1:
8503 /* If the low-address word is used in the address, we must load
8504 it last. Otherwise, load it first. Note that we cannot have
8505 auto-increment in that case since the address register is
8506 known to be dead. */
8507 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8508 operands[1], 0))
8509 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8510 else
8511 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
8512 case 2:
8513 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
8514 case 3:
8515 case 4:
8516 case 5:
8517 return \"#\";
8518 }
8519 }"
8520 [(set_attr "type" "two,load,store,*,*,*")
8521 (set_attr "length" "8,8,8,8,12,16")])
8522
8523 ; ld/std require word-aligned displacements -> 'Y' constraint.
8524 ; List Y->r and r->Y before r->r for reload.
8525 (define_insn "*movdf_hardfloat64_mfpgpr"
8526 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f")
8527 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))]
8528 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8529 && TARGET_DOUBLE_FLOAT
8530 && (gpc_reg_operand (operands[0], DFmode)
8531 || gpc_reg_operand (operands[1], DFmode))"
8532 "@
8533 std%U0%X0 %1,%0
8534 ld%U1%X1 %0,%1
8535 mr %0,%1
8536 fmr %0,%1
8537 lfd%U1%X1 %0,%1
8538 stfd%U0%X0 %1,%0
8539 mt%0 %1
8540 mf%1 %0
8541 {cror 0,0,0|nop}
8542 #
8543 #
8544 #
8545 mftgpr %0,%1
8546 mffgpr %0,%1"
8547 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
8548 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
8549
8550 ; ld/std require word-aligned displacements -> 'Y' constraint.
8551 ; List Y->r and r->Y before r->r for reload.
8552 (define_insn "*movdf_hardfloat64"
8553 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
8554 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
8555 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8556 && TARGET_DOUBLE_FLOAT
8557 && (gpc_reg_operand (operands[0], DFmode)
8558 || gpc_reg_operand (operands[1], DFmode))"
8559 "@
8560 std%U0%X0 %1,%0
8561 ld%U1%X1 %0,%1
8562 mr %0,%1
8563 fmr %0,%1
8564 lfd%U1%X1 %0,%1
8565 stfd%U0%X0 %1,%0
8566 mt%0 %1
8567 mf%1 %0
8568 {cror 0,0,0|nop}
8569 #
8570 #
8571 #"
8572 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
8573 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
8574
8575 (define_insn "*movdf_softfloat64"
8576 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8577 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
8578 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8579 && (gpc_reg_operand (operands[0], DFmode)
8580 || gpc_reg_operand (operands[1], DFmode))"
8581 "@
8582 ld%U1%X1 %0,%1
8583 std%U0%X0 %1,%0
8584 mr %0,%1
8585 mt%0 %1
8586 mf%1 %0
8587 #
8588 #
8589 #
8590 {cror 0,0,0|nop}"
8591 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
8592 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8593 \f
8594 (define_expand "movtf"
8595 [(set (match_operand:TF 0 "general_operand" "")
8596 (match_operand:TF 1 "any_operand" ""))]
8597 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
8598 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8599
8600 ; It's important to list the o->f and f->o moves before f->f because
8601 ; otherwise reload, given m->f, will try to pick f->f and reload it,
8602 ; which doesn't make progress. Likewise r->Y must be before r->r.
8603 (define_insn_and_split "*movtf_internal"
8604 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
8605 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
8606 "!TARGET_IEEEQUAD
8607 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8608 && (gpc_reg_operand (operands[0], TFmode)
8609 || gpc_reg_operand (operands[1], TFmode))"
8610 "#"
8611 "&& reload_completed"
8612 [(pc)]
8613 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8614 [(set_attr "length" "8,8,8,20,20,16")])
8615
8616 (define_insn_and_split "*movtf_softfloat"
8617 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
8618 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
8619 "!TARGET_IEEEQUAD
8620 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
8621 && (gpc_reg_operand (operands[0], TFmode)
8622 || gpc_reg_operand (operands[1], TFmode))"
8623 "#"
8624 "&& reload_completed"
8625 [(pc)]
8626 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8627 [(set_attr "length" "20,20,16")])
8628
8629 (define_expand "extenddftf2"
8630 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8631 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8632 "!TARGET_IEEEQUAD
8633 && TARGET_HARD_FLOAT
8634 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8635 && TARGET_LONG_DOUBLE_128"
8636 {
8637 if (TARGET_E500_DOUBLE)
8638 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8639 else
8640 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8641 DONE;
8642 })
8643
8644 (define_expand "extenddftf2_fprs"
8645 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8646 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8647 (use (match_dup 2))])]
8648 "!TARGET_IEEEQUAD
8649 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8650 && TARGET_LONG_DOUBLE_128"
8651 {
8652 operands[2] = CONST0_RTX (DFmode);
8653 /* Generate GOT reference early for SVR4 PIC. */
8654 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8655 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8656 })
8657
8658 (define_insn_and_split "*extenddftf2_internal"
8659 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8660 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8661 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
8662 "!TARGET_IEEEQUAD
8663 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8664 && TARGET_LONG_DOUBLE_128"
8665 "#"
8666 "&& reload_completed"
8667 [(pc)]
8668 {
8669 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8670 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8671 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8672 operands[1]);
8673 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8674 operands[2]);
8675 DONE;
8676 })
8677
8678 (define_expand "extendsftf2"
8679 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8680 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8681 "!TARGET_IEEEQUAD
8682 && TARGET_HARD_FLOAT
8683 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8684 && TARGET_LONG_DOUBLE_128"
8685 {
8686 rtx tmp = gen_reg_rtx (DFmode);
8687 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8688 emit_insn (gen_extenddftf2 (operands[0], tmp));
8689 DONE;
8690 })
8691
8692 (define_expand "trunctfdf2"
8693 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8694 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8695 "!TARGET_IEEEQUAD
8696 && TARGET_HARD_FLOAT
8697 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8698 && TARGET_LONG_DOUBLE_128"
8699 "")
8700
8701 (define_insn_and_split "trunctfdf2_internal1"
8702 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8703 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
8704 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8705 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8706 "@
8707 #
8708 fmr %0,%1"
8709 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8710 [(const_int 0)]
8711 {
8712 emit_note (NOTE_INSN_DELETED);
8713 DONE;
8714 }
8715 [(set_attr "type" "fp")])
8716
8717 (define_insn "trunctfdf2_internal2"
8718 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8719 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8720 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8721 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8722 && TARGET_LONG_DOUBLE_128"
8723 "fadd %0,%1,%L1"
8724 [(set_attr "type" "fp")])
8725
8726 (define_expand "trunctfsf2"
8727 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8728 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8729 "!TARGET_IEEEQUAD
8730 && TARGET_HARD_FLOAT
8731 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8732 && TARGET_LONG_DOUBLE_128"
8733 {
8734 if (TARGET_E500_DOUBLE)
8735 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8736 else
8737 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8738 DONE;
8739 })
8740
8741 (define_insn_and_split "trunctfsf2_fprs"
8742 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8743 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8744 (clobber (match_scratch:DF 2 "=f"))]
8745 "!TARGET_IEEEQUAD
8746 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
8747 && TARGET_LONG_DOUBLE_128"
8748 "#"
8749 "&& reload_completed"
8750 [(set (match_dup 2)
8751 (float_truncate:DF (match_dup 1)))
8752 (set (match_dup 0)
8753 (float_truncate:SF (match_dup 2)))]
8754 "")
8755
8756 (define_expand "floatsitf2"
8757 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8758 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
8759 "!TARGET_IEEEQUAD
8760 && TARGET_HARD_FLOAT
8761 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8762 && TARGET_LONG_DOUBLE_128"
8763 {
8764 rtx tmp = gen_reg_rtx (DFmode);
8765 expand_float (tmp, operands[1], false);
8766 emit_insn (gen_extenddftf2 (operands[0], tmp));
8767 DONE;
8768 })
8769
8770 ; fadd, but rounding towards zero.
8771 ; This is probably not the optimal code sequence.
8772 (define_insn "fix_trunc_helper"
8773 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8774 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8775 UNSPEC_FIX_TRUNC_TF))
8776 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8777 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
8778 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8779 [(set_attr "type" "fp")
8780 (set_attr "length" "20")])
8781
8782 (define_expand "fix_trunctfsi2"
8783 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8784 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8785 "!TARGET_IEEEQUAD
8786 && (TARGET_POWER2 || TARGET_POWERPC)
8787 && TARGET_HARD_FLOAT
8788 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8789 && TARGET_LONG_DOUBLE_128"
8790 {
8791 if (TARGET_E500_DOUBLE)
8792 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8793 else
8794 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8795 DONE;
8796 })
8797
8798 (define_expand "fix_trunctfsi2_fprs"
8799 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8800 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8801 (clobber (match_dup 2))
8802 (clobber (match_dup 3))
8803 (clobber (match_dup 4))
8804 (clobber (match_dup 5))])]
8805 "!TARGET_IEEEQUAD
8806 && (TARGET_POWER2 || TARGET_POWERPC)
8807 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8808 {
8809 operands[2] = gen_reg_rtx (DFmode);
8810 operands[3] = gen_reg_rtx (DFmode);
8811 operands[4] = gen_reg_rtx (DImode);
8812 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8813 })
8814
8815 (define_insn_and_split "*fix_trunctfsi2_internal"
8816 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8817 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8818 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8819 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8820 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8821 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
8822 "!TARGET_IEEEQUAD
8823 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8824 "#"
8825 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[5]))"
8826 [(pc)]
8827 {
8828 rtx lowword;
8829 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8830
8831 gcc_assert (MEM_P (operands[5]));
8832 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8833
8834 emit_insn (gen_fctiwz (operands[4], operands[2]));
8835 emit_move_insn (operands[5], operands[4]);
8836 emit_move_insn (operands[0], lowword);
8837 DONE;
8838 })
8839
8840 (define_expand "negtf2"
8841 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8842 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8843 "!TARGET_IEEEQUAD
8844 && TARGET_HARD_FLOAT
8845 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8846 && TARGET_LONG_DOUBLE_128"
8847 "")
8848
8849 (define_insn "negtf2_internal"
8850 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8851 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8852 "!TARGET_IEEEQUAD
8853 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8854 "*
8855 {
8856 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8857 return \"fneg %L0,%L1\;fneg %0,%1\";
8858 else
8859 return \"fneg %0,%1\;fneg %L0,%L1\";
8860 }"
8861 [(set_attr "type" "fp")
8862 (set_attr "length" "8")])
8863
8864 (define_expand "abstf2"
8865 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8866 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8867 "!TARGET_IEEEQUAD
8868 && TARGET_HARD_FLOAT
8869 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8870 && TARGET_LONG_DOUBLE_128"
8871 "
8872 {
8873 rtx label = gen_label_rtx ();
8874 if (TARGET_E500_DOUBLE)
8875 {
8876 if (flag_unsafe_math_optimizations)
8877 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
8878 else
8879 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
8880 }
8881 else
8882 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8883 emit_label (label);
8884 DONE;
8885 }")
8886
8887 (define_expand "abstf2_internal"
8888 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8889 (match_operand:TF 1 "gpc_reg_operand" ""))
8890 (set (match_dup 3) (match_dup 5))
8891 (set (match_dup 5) (abs:DF (match_dup 5)))
8892 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8893 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8894 (label_ref (match_operand 2 "" ""))
8895 (pc)))
8896 (set (match_dup 6) (neg:DF (match_dup 6)))]
8897 "!TARGET_IEEEQUAD
8898 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8899 && TARGET_LONG_DOUBLE_128"
8900 "
8901 {
8902 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8903 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8904 operands[3] = gen_reg_rtx (DFmode);
8905 operands[4] = gen_reg_rtx (CCFPmode);
8906 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8907 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8908 }")
8909 \f
8910 ;; Next come the multi-word integer load and store and the load and store
8911 ;; multiple insns.
8912
8913 ; List r->r after r->"o<>", otherwise reload will try to reload a
8914 ; non-offsettable address by using r->r which won't make progress.
8915 (define_insn "*movdi_internal32"
8916 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
8917 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
8918 "! TARGET_POWERPC64
8919 && (gpc_reg_operand (operands[0], DImode)
8920 || gpc_reg_operand (operands[1], DImode))"
8921 "@
8922 #
8923 #
8924 #
8925 fmr %0,%1
8926 lfd%U1%X1 %0,%1
8927 stfd%U0%X0 %1,%0
8928 #"
8929 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
8930
8931 (define_split
8932 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8933 (match_operand:DI 1 "const_int_operand" ""))]
8934 "! TARGET_POWERPC64 && reload_completed"
8935 [(set (match_dup 2) (match_dup 4))
8936 (set (match_dup 3) (match_dup 1))]
8937 "
8938 {
8939 HOST_WIDE_INT value = INTVAL (operands[1]);
8940 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8941 DImode);
8942 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8943 DImode);
8944 #if HOST_BITS_PER_WIDE_INT == 32
8945 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8946 #else
8947 operands[4] = GEN_INT (value >> 32);
8948 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8949 #endif
8950 }")
8951
8952 (define_split
8953 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "")
8954 (match_operand:DI 1 "input_operand" ""))]
8955 "reload_completed && !TARGET_POWERPC64
8956 && gpr_or_gpr_p (operands[0], operands[1])"
8957 [(pc)]
8958 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8959
8960 (define_insn "*movdi_mfpgpr"
8961 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h,r,*f")
8962 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0,*f,r"))]
8963 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8964 && (gpc_reg_operand (operands[0], DImode)
8965 || gpc_reg_operand (operands[1], DImode))"
8966 "@
8967 mr %0,%1
8968 ld%U1%X1 %0,%1
8969 std%U0%X0 %1,%0
8970 li %0,%1
8971 lis %0,%v1
8972 #
8973 {cal|la} %0,%a1
8974 fmr %0,%1
8975 lfd%U1%X1 %0,%1
8976 stfd%U0%X0 %1,%0
8977 mf%1 %0
8978 mt%0 %1
8979 {cror 0,0,0|nop}
8980 mftgpr %0,%1
8981 mffgpr %0,%1"
8982 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
8983 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
8984
8985 (define_insn "*movdi_internal64"
8986 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
8987 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8988 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
8989 && (gpc_reg_operand (operands[0], DImode)
8990 || gpc_reg_operand (operands[1], DImode))"
8991 "@
8992 mr %0,%1
8993 ld%U1%X1 %0,%1
8994 std%U0%X0 %1,%0
8995 li %0,%1
8996 lis %0,%v1
8997 #
8998 {cal|la} %0,%a1
8999 fmr %0,%1
9000 lfd%U1%X1 %0,%1
9001 stfd%U0%X0 %1,%0
9002 mf%1 %0
9003 mt%0 %1
9004 {cror 0,0,0|nop}"
9005 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
9006 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
9007
9008 ;; immediate value valid for a single instruction hiding in a const_double
9009 (define_insn ""
9010 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9011 (match_operand:DI 1 "const_double_operand" "F"))]
9012 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
9013 && GET_CODE (operands[1]) == CONST_DOUBLE
9014 && num_insns_constant (operands[1], DImode) == 1"
9015 "*
9016 {
9017 return ((unsigned HOST_WIDE_INT)
9018 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
9019 ? \"li %0,%1\" : \"lis %0,%v1\";
9020 }")
9021
9022 ;; Generate all one-bits and clear left or right.
9023 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9024 (define_split
9025 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9026 (match_operand:DI 1 "mask64_operand" ""))]
9027 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9028 [(set (match_dup 0) (const_int -1))
9029 (set (match_dup 0)
9030 (and:DI (rotate:DI (match_dup 0)
9031 (const_int 0))
9032 (match_dup 1)))]
9033 "")
9034
9035 ;; Split a load of a large constant into the appropriate five-instruction
9036 ;; sequence. Handle anything in a constant number of insns.
9037 ;; When non-easy constants can go in the TOC, this should use
9038 ;; easy_fp_constant predicate.
9039 (define_split
9040 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9041 (match_operand:DI 1 "const_int_operand" ""))]
9042 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9043 [(set (match_dup 0) (match_dup 2))
9044 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9045 "
9046 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9047
9048 if (tem == operands[0])
9049 DONE;
9050 else
9051 FAIL;
9052 }")
9053
9054 (define_split
9055 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9056 (match_operand:DI 1 "const_double_operand" ""))]
9057 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9058 [(set (match_dup 0) (match_dup 2))
9059 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9060 "
9061 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9062
9063 if (tem == operands[0])
9064 DONE;
9065 else
9066 FAIL;
9067 }")
9068 \f
9069 ;; TImode is similar, except that we usually want to compute the address into
9070 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
9071 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
9072
9073 ;; We say that MQ is clobbered in the last alternative because the first
9074 ;; alternative would never get used otherwise since it would need a reload
9075 ;; while the 2nd alternative would not. We put memory cases first so they
9076 ;; are preferred. Otherwise, we'd try to reload the output instead of
9077 ;; giving the SCRATCH mq.
9078
9079 (define_insn "*movti_power"
9080 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
9081 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
9082 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
9083 "TARGET_POWER && ! TARGET_POWERPC64
9084 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9085 "*
9086 {
9087 switch (which_alternative)
9088 {
9089 default:
9090 gcc_unreachable ();
9091
9092 case 0:
9093 if (TARGET_STRING)
9094 return \"{stsi|stswi} %1,%P0,16\";
9095 case 1:
9096 case 2:
9097 return \"#\";
9098 case 3:
9099 /* If the address is not used in the output, we can use lsi. Otherwise,
9100 fall through to generating four loads. */
9101 if (TARGET_STRING
9102 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9103 return \"{lsi|lswi} %0,%P1,16\";
9104 /* ... fall through ... */
9105 case 4:
9106 case 5:
9107 return \"#\";
9108 }
9109 }"
9110 [(set_attr "type" "store,store,*,load,load,*")])
9111
9112 (define_insn "*movti_string"
9113 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
9114 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
9115 "! TARGET_POWER && ! TARGET_POWERPC64
9116 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9117 "*
9118 {
9119 switch (which_alternative)
9120 {
9121 default:
9122 gcc_unreachable ();
9123 case 0:
9124 if (TARGET_STRING)
9125 return \"{stsi|stswi} %1,%P0,16\";
9126 case 1:
9127 case 2:
9128 return \"#\";
9129 case 3:
9130 /* If the address is not used in the output, we can use lsi. Otherwise,
9131 fall through to generating four loads. */
9132 if (TARGET_STRING
9133 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9134 return \"{lsi|lswi} %0,%P1,16\";
9135 /* ... fall through ... */
9136 case 4:
9137 case 5:
9138 return \"#\";
9139 }
9140 }"
9141 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")])
9142
9143 (define_insn "*movti_ppc64"
9144 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
9145 (match_operand:TI 1 "input_operand" "r,r,m"))]
9146 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
9147 || gpc_reg_operand (operands[1], TImode))"
9148 "#"
9149 [(set_attr "type" "*,load,store")])
9150
9151 (define_split
9152 [(set (match_operand:TI 0 "gpc_reg_operand" "")
9153 (match_operand:TI 1 "const_double_operand" ""))]
9154 "TARGET_POWERPC64"
9155 [(set (match_dup 2) (match_dup 4))
9156 (set (match_dup 3) (match_dup 5))]
9157 "
9158 {
9159 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9160 TImode);
9161 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9162 TImode);
9163 if (GET_CODE (operands[1]) == CONST_DOUBLE)
9164 {
9165 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9166 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9167 }
9168 else if (GET_CODE (operands[1]) == CONST_INT)
9169 {
9170 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9171 operands[5] = operands[1];
9172 }
9173 else
9174 FAIL;
9175 }")
9176
9177 (define_split
9178 [(set (match_operand:TI 0 "nonimmediate_operand" "")
9179 (match_operand:TI 1 "input_operand" ""))]
9180 "reload_completed
9181 && gpr_or_gpr_p (operands[0], operands[1])"
9182 [(pc)]
9183 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9184 \f
9185 (define_expand "load_multiple"
9186 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9187 (match_operand:SI 1 "" ""))
9188 (use (match_operand:SI 2 "" ""))])]
9189 "TARGET_STRING && !TARGET_POWERPC64"
9190 "
9191 {
9192 int regno;
9193 int count;
9194 rtx op1;
9195 int i;
9196
9197 /* Support only loading a constant number of fixed-point registers from
9198 memory and only bother with this if more than two; the machine
9199 doesn't support more than eight. */
9200 if (GET_CODE (operands[2]) != CONST_INT
9201 || INTVAL (operands[2]) <= 2
9202 || INTVAL (operands[2]) > 8
9203 || GET_CODE (operands[1]) != MEM
9204 || GET_CODE (operands[0]) != REG
9205 || REGNO (operands[0]) >= 32)
9206 FAIL;
9207
9208 count = INTVAL (operands[2]);
9209 regno = REGNO (operands[0]);
9210
9211 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9212 op1 = replace_equiv_address (operands[1],
9213 force_reg (SImode, XEXP (operands[1], 0)));
9214
9215 for (i = 0; i < count; i++)
9216 XVECEXP (operands[3], 0, i)
9217 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
9218 adjust_address_nv (op1, SImode, i * 4));
9219 }")
9220
9221 (define_insn "*ldmsi8"
9222 [(match_parallel 0 "load_multiple_operation"
9223 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9224 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9225 (set (match_operand:SI 3 "gpc_reg_operand" "")
9226 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9227 (set (match_operand:SI 4 "gpc_reg_operand" "")
9228 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9229 (set (match_operand:SI 5 "gpc_reg_operand" "")
9230 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9231 (set (match_operand:SI 6 "gpc_reg_operand" "")
9232 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9233 (set (match_operand:SI 7 "gpc_reg_operand" "")
9234 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9235 (set (match_operand:SI 8 "gpc_reg_operand" "")
9236 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9237 (set (match_operand:SI 9 "gpc_reg_operand" "")
9238 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9239 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9240 "*
9241 { return rs6000_output_load_multiple (operands); }"
9242 [(set_attr "type" "load_ux")
9243 (set_attr "length" "32")])
9244
9245 (define_insn "*ldmsi7"
9246 [(match_parallel 0 "load_multiple_operation"
9247 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9248 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9249 (set (match_operand:SI 3 "gpc_reg_operand" "")
9250 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9251 (set (match_operand:SI 4 "gpc_reg_operand" "")
9252 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9253 (set (match_operand:SI 5 "gpc_reg_operand" "")
9254 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9255 (set (match_operand:SI 6 "gpc_reg_operand" "")
9256 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9257 (set (match_operand:SI 7 "gpc_reg_operand" "")
9258 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9259 (set (match_operand:SI 8 "gpc_reg_operand" "")
9260 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9261 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9262 "*
9263 { return rs6000_output_load_multiple (operands); }"
9264 [(set_attr "type" "load_ux")
9265 (set_attr "length" "32")])
9266
9267 (define_insn "*ldmsi6"
9268 [(match_parallel 0 "load_multiple_operation"
9269 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9270 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9271 (set (match_operand:SI 3 "gpc_reg_operand" "")
9272 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9273 (set (match_operand:SI 4 "gpc_reg_operand" "")
9274 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9275 (set (match_operand:SI 5 "gpc_reg_operand" "")
9276 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9277 (set (match_operand:SI 6 "gpc_reg_operand" "")
9278 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9279 (set (match_operand:SI 7 "gpc_reg_operand" "")
9280 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9281 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9282 "*
9283 { return rs6000_output_load_multiple (operands); }"
9284 [(set_attr "type" "load_ux")
9285 (set_attr "length" "32")])
9286
9287 (define_insn "*ldmsi5"
9288 [(match_parallel 0 "load_multiple_operation"
9289 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9290 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9291 (set (match_operand:SI 3 "gpc_reg_operand" "")
9292 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9293 (set (match_operand:SI 4 "gpc_reg_operand" "")
9294 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9295 (set (match_operand:SI 5 "gpc_reg_operand" "")
9296 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9297 (set (match_operand:SI 6 "gpc_reg_operand" "")
9298 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9299 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9300 "*
9301 { return rs6000_output_load_multiple (operands); }"
9302 [(set_attr "type" "load_ux")
9303 (set_attr "length" "32")])
9304
9305 (define_insn "*ldmsi4"
9306 [(match_parallel 0 "load_multiple_operation"
9307 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9308 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9309 (set (match_operand:SI 3 "gpc_reg_operand" "")
9310 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9311 (set (match_operand:SI 4 "gpc_reg_operand" "")
9312 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9313 (set (match_operand:SI 5 "gpc_reg_operand" "")
9314 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9315 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9316 "*
9317 { return rs6000_output_load_multiple (operands); }"
9318 [(set_attr "type" "load_ux")
9319 (set_attr "length" "32")])
9320
9321 (define_insn "*ldmsi3"
9322 [(match_parallel 0 "load_multiple_operation"
9323 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9324 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9325 (set (match_operand:SI 3 "gpc_reg_operand" "")
9326 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9327 (set (match_operand:SI 4 "gpc_reg_operand" "")
9328 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9329 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9330 "*
9331 { return rs6000_output_load_multiple (operands); }"
9332 [(set_attr "type" "load_ux")
9333 (set_attr "length" "32")])
9334
9335 (define_expand "store_multiple"
9336 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9337 (match_operand:SI 1 "" ""))
9338 (clobber (scratch:SI))
9339 (use (match_operand:SI 2 "" ""))])]
9340 "TARGET_STRING && !TARGET_POWERPC64"
9341 "
9342 {
9343 int regno;
9344 int count;
9345 rtx to;
9346 rtx op0;
9347 int i;
9348
9349 /* Support only storing a constant number of fixed-point registers to
9350 memory and only bother with this if more than two; the machine
9351 doesn't support more than eight. */
9352 if (GET_CODE (operands[2]) != CONST_INT
9353 || INTVAL (operands[2]) <= 2
9354 || INTVAL (operands[2]) > 8
9355 || GET_CODE (operands[0]) != MEM
9356 || GET_CODE (operands[1]) != REG
9357 || REGNO (operands[1]) >= 32)
9358 FAIL;
9359
9360 count = INTVAL (operands[2]);
9361 regno = REGNO (operands[1]);
9362
9363 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
9364 to = force_reg (SImode, XEXP (operands[0], 0));
9365 op0 = replace_equiv_address (operands[0], to);
9366
9367 XVECEXP (operands[3], 0, 0)
9368 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
9369 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
9370 gen_rtx_SCRATCH (SImode));
9371
9372 for (i = 1; i < count; i++)
9373 XVECEXP (operands[3], 0, i + 1)
9374 = gen_rtx_SET (VOIDmode,
9375 adjust_address_nv (op0, SImode, i * 4),
9376 gen_rtx_REG (SImode, regno + i));
9377 }")
9378
9379 (define_insn "*stmsi8"
9380 [(match_parallel 0 "store_multiple_operation"
9381 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9382 (match_operand:SI 2 "gpc_reg_operand" "r"))
9383 (clobber (match_scratch:SI 3 "=X"))
9384 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9385 (match_operand:SI 4 "gpc_reg_operand" "r"))
9386 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9387 (match_operand:SI 5 "gpc_reg_operand" "r"))
9388 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9389 (match_operand:SI 6 "gpc_reg_operand" "r"))
9390 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9391 (match_operand:SI 7 "gpc_reg_operand" "r"))
9392 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9393 (match_operand:SI 8 "gpc_reg_operand" "r"))
9394 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9395 (match_operand:SI 9 "gpc_reg_operand" "r"))
9396 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9397 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9398 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9399 "{stsi|stswi} %2,%1,%O0"
9400 [(set_attr "type" "store_ux")])
9401
9402 (define_insn "*stmsi7"
9403 [(match_parallel 0 "store_multiple_operation"
9404 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9405 (match_operand:SI 2 "gpc_reg_operand" "r"))
9406 (clobber (match_scratch:SI 3 "=X"))
9407 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9408 (match_operand:SI 4 "gpc_reg_operand" "r"))
9409 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9410 (match_operand:SI 5 "gpc_reg_operand" "r"))
9411 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9412 (match_operand:SI 6 "gpc_reg_operand" "r"))
9413 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9414 (match_operand:SI 7 "gpc_reg_operand" "r"))
9415 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9416 (match_operand:SI 8 "gpc_reg_operand" "r"))
9417 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9418 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9419 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9420 "{stsi|stswi} %2,%1,%O0"
9421 [(set_attr "type" "store_ux")])
9422
9423 (define_insn "*stmsi6"
9424 [(match_parallel 0 "store_multiple_operation"
9425 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9426 (match_operand:SI 2 "gpc_reg_operand" "r"))
9427 (clobber (match_scratch:SI 3 "=X"))
9428 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9429 (match_operand:SI 4 "gpc_reg_operand" "r"))
9430 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9431 (match_operand:SI 5 "gpc_reg_operand" "r"))
9432 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9433 (match_operand:SI 6 "gpc_reg_operand" "r"))
9434 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9435 (match_operand:SI 7 "gpc_reg_operand" "r"))
9436 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9437 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9438 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9439 "{stsi|stswi} %2,%1,%O0"
9440 [(set_attr "type" "store_ux")])
9441
9442 (define_insn "*stmsi5"
9443 [(match_parallel 0 "store_multiple_operation"
9444 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9445 (match_operand:SI 2 "gpc_reg_operand" "r"))
9446 (clobber (match_scratch:SI 3 "=X"))
9447 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9448 (match_operand:SI 4 "gpc_reg_operand" "r"))
9449 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9450 (match_operand:SI 5 "gpc_reg_operand" "r"))
9451 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9452 (match_operand:SI 6 "gpc_reg_operand" "r"))
9453 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9454 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9455 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9456 "{stsi|stswi} %2,%1,%O0"
9457 [(set_attr "type" "store_ux")])
9458
9459 (define_insn "*stmsi4"
9460 [(match_parallel 0 "store_multiple_operation"
9461 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9462 (match_operand:SI 2 "gpc_reg_operand" "r"))
9463 (clobber (match_scratch:SI 3 "=X"))
9464 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9465 (match_operand:SI 4 "gpc_reg_operand" "r"))
9466 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9467 (match_operand:SI 5 "gpc_reg_operand" "r"))
9468 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9469 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9470 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9471 "{stsi|stswi} %2,%1,%O0"
9472 [(set_attr "type" "store_ux")])
9473
9474 (define_insn "*stmsi3"
9475 [(match_parallel 0 "store_multiple_operation"
9476 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9477 (match_operand:SI 2 "gpc_reg_operand" "r"))
9478 (clobber (match_scratch:SI 3 "=X"))
9479 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9480 (match_operand:SI 4 "gpc_reg_operand" "r"))
9481 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9482 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9483 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9484 "{stsi|stswi} %2,%1,%O0"
9485 [(set_attr "type" "store_ux")])
9486
9487 (define_insn "*stmsi8_power"
9488 [(match_parallel 0 "store_multiple_operation"
9489 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9490 (match_operand:SI 2 "gpc_reg_operand" "r"))
9491 (clobber (match_scratch:SI 3 "=q"))
9492 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9493 (match_operand:SI 4 "gpc_reg_operand" "r"))
9494 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9495 (match_operand:SI 5 "gpc_reg_operand" "r"))
9496 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9497 (match_operand:SI 6 "gpc_reg_operand" "r"))
9498 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9499 (match_operand:SI 7 "gpc_reg_operand" "r"))
9500 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9501 (match_operand:SI 8 "gpc_reg_operand" "r"))
9502 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9503 (match_operand:SI 9 "gpc_reg_operand" "r"))
9504 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9505 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9506 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9507 "{stsi|stswi} %2,%1,%O0"
9508 [(set_attr "type" "store_ux")])
9509
9510 (define_insn "*stmsi7_power"
9511 [(match_parallel 0 "store_multiple_operation"
9512 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9513 (match_operand:SI 2 "gpc_reg_operand" "r"))
9514 (clobber (match_scratch:SI 3 "=q"))
9515 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9516 (match_operand:SI 4 "gpc_reg_operand" "r"))
9517 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9518 (match_operand:SI 5 "gpc_reg_operand" "r"))
9519 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9520 (match_operand:SI 6 "gpc_reg_operand" "r"))
9521 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9522 (match_operand:SI 7 "gpc_reg_operand" "r"))
9523 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9524 (match_operand:SI 8 "gpc_reg_operand" "r"))
9525 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9526 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9527 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9528 "{stsi|stswi} %2,%1,%O0"
9529 [(set_attr "type" "store_ux")])
9530
9531 (define_insn "*stmsi6_power"
9532 [(match_parallel 0 "store_multiple_operation"
9533 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9534 (match_operand:SI 2 "gpc_reg_operand" "r"))
9535 (clobber (match_scratch:SI 3 "=q"))
9536 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9537 (match_operand:SI 4 "gpc_reg_operand" "r"))
9538 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9539 (match_operand:SI 5 "gpc_reg_operand" "r"))
9540 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9541 (match_operand:SI 6 "gpc_reg_operand" "r"))
9542 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9543 (match_operand:SI 7 "gpc_reg_operand" "r"))
9544 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9545 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9546 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9547 "{stsi|stswi} %2,%1,%O0"
9548 [(set_attr "type" "store_ux")])
9549
9550 (define_insn "*stmsi5_power"
9551 [(match_parallel 0 "store_multiple_operation"
9552 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9553 (match_operand:SI 2 "gpc_reg_operand" "r"))
9554 (clobber (match_scratch:SI 3 "=q"))
9555 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9556 (match_operand:SI 4 "gpc_reg_operand" "r"))
9557 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9558 (match_operand:SI 5 "gpc_reg_operand" "r"))
9559 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9560 (match_operand:SI 6 "gpc_reg_operand" "r"))
9561 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9562 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9563 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9564 "{stsi|stswi} %2,%1,%O0"
9565 [(set_attr "type" "store_ux")])
9566
9567 (define_insn "*stmsi4_power"
9568 [(match_parallel 0 "store_multiple_operation"
9569 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9570 (match_operand:SI 2 "gpc_reg_operand" "r"))
9571 (clobber (match_scratch:SI 3 "=q"))
9572 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9573 (match_operand:SI 4 "gpc_reg_operand" "r"))
9574 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9575 (match_operand:SI 5 "gpc_reg_operand" "r"))
9576 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9577 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9578 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9579 "{stsi|stswi} %2,%1,%O0"
9580 [(set_attr "type" "store_ux")])
9581
9582 (define_insn "*stmsi3_power"
9583 [(match_parallel 0 "store_multiple_operation"
9584 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9585 (match_operand:SI 2 "gpc_reg_operand" "r"))
9586 (clobber (match_scratch:SI 3 "=q"))
9587 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9588 (match_operand:SI 4 "gpc_reg_operand" "r"))
9589 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9590 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9591 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9592 "{stsi|stswi} %2,%1,%O0"
9593 [(set_attr "type" "store_ux")])
9594 \f
9595 (define_expand "setmemsi"
9596 [(parallel [(set (match_operand:BLK 0 "" "")
9597 (match_operand 2 "const_int_operand" ""))
9598 (use (match_operand:SI 1 "" ""))
9599 (use (match_operand:SI 3 "" ""))])]
9600 ""
9601 "
9602 {
9603 /* If value to set is not zero, use the library routine. */
9604 if (operands[2] != const0_rtx)
9605 FAIL;
9606
9607 if (expand_block_clear (operands))
9608 DONE;
9609 else
9610 FAIL;
9611 }")
9612
9613 ;; String/block move insn.
9614 ;; Argument 0 is the destination
9615 ;; Argument 1 is the source
9616 ;; Argument 2 is the length
9617 ;; Argument 3 is the alignment
9618
9619 (define_expand "movmemsi"
9620 [(parallel [(set (match_operand:BLK 0 "" "")
9621 (match_operand:BLK 1 "" ""))
9622 (use (match_operand:SI 2 "" ""))
9623 (use (match_operand:SI 3 "" ""))])]
9624 ""
9625 "
9626 {
9627 if (expand_block_move (operands))
9628 DONE;
9629 else
9630 FAIL;
9631 }")
9632
9633 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9634 ;; register allocator doesn't have a clue about allocating 8 word registers.
9635 ;; rD/rS = r5 is preferred, efficient form.
9636 (define_expand "movmemsi_8reg"
9637 [(parallel [(set (match_operand 0 "" "")
9638 (match_operand 1 "" ""))
9639 (use (match_operand 2 "" ""))
9640 (use (match_operand 3 "" ""))
9641 (clobber (reg:SI 5))
9642 (clobber (reg:SI 6))
9643 (clobber (reg:SI 7))
9644 (clobber (reg:SI 8))
9645 (clobber (reg:SI 9))
9646 (clobber (reg:SI 10))
9647 (clobber (reg:SI 11))
9648 (clobber (reg:SI 12))
9649 (clobber (match_scratch:SI 4 ""))])]
9650 "TARGET_STRING"
9651 "")
9652
9653 (define_insn ""
9654 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9655 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9656 (use (match_operand:SI 2 "immediate_operand" "i"))
9657 (use (match_operand:SI 3 "immediate_operand" "i"))
9658 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9659 (clobber (reg:SI 6))
9660 (clobber (reg:SI 7))
9661 (clobber (reg:SI 8))
9662 (clobber (reg:SI 9))
9663 (clobber (reg:SI 10))
9664 (clobber (reg:SI 11))
9665 (clobber (reg:SI 12))
9666 (clobber (match_scratch:SI 5 "=q"))]
9667 "TARGET_STRING && TARGET_POWER
9668 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9669 || INTVAL (operands[2]) == 0)
9670 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9671 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9672 && REGNO (operands[4]) == 5"
9673 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9674 [(set_attr "type" "store_ux")
9675 (set_attr "length" "8")])
9676
9677 (define_insn ""
9678 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9679 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9680 (use (match_operand:SI 2 "immediate_operand" "i"))
9681 (use (match_operand:SI 3 "immediate_operand" "i"))
9682 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9683 (clobber (reg:SI 6))
9684 (clobber (reg:SI 7))
9685 (clobber (reg:SI 8))
9686 (clobber (reg:SI 9))
9687 (clobber (reg:SI 10))
9688 (clobber (reg:SI 11))
9689 (clobber (reg:SI 12))
9690 (clobber (match_scratch:SI 5 "=X"))]
9691 "TARGET_STRING && ! TARGET_POWER
9692 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9693 || INTVAL (operands[2]) == 0)
9694 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9695 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9696 && REGNO (operands[4]) == 5"
9697 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9698 [(set_attr "type" "store_ux")
9699 (set_attr "length" "8")])
9700
9701 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9702 ;; register allocator doesn't have a clue about allocating 6 word registers.
9703 ;; rD/rS = r5 is preferred, efficient form.
9704 (define_expand "movmemsi_6reg"
9705 [(parallel [(set (match_operand 0 "" "")
9706 (match_operand 1 "" ""))
9707 (use (match_operand 2 "" ""))
9708 (use (match_operand 3 "" ""))
9709 (clobber (reg:SI 5))
9710 (clobber (reg:SI 6))
9711 (clobber (reg:SI 7))
9712 (clobber (reg:SI 8))
9713 (clobber (reg:SI 9))
9714 (clobber (reg:SI 10))
9715 (clobber (match_scratch:SI 4 ""))])]
9716 "TARGET_STRING"
9717 "")
9718
9719 (define_insn ""
9720 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9721 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9722 (use (match_operand:SI 2 "immediate_operand" "i"))
9723 (use (match_operand:SI 3 "immediate_operand" "i"))
9724 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9725 (clobber (reg:SI 6))
9726 (clobber (reg:SI 7))
9727 (clobber (reg:SI 8))
9728 (clobber (reg:SI 9))
9729 (clobber (reg:SI 10))
9730 (clobber (match_scratch:SI 5 "=q"))]
9731 "TARGET_STRING && TARGET_POWER
9732 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9733 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9734 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9735 && REGNO (operands[4]) == 5"
9736 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9737 [(set_attr "type" "store_ux")
9738 (set_attr "length" "8")])
9739
9740 (define_insn ""
9741 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9742 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9743 (use (match_operand:SI 2 "immediate_operand" "i"))
9744 (use (match_operand:SI 3 "immediate_operand" "i"))
9745 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9746 (clobber (reg:SI 6))
9747 (clobber (reg:SI 7))
9748 (clobber (reg:SI 8))
9749 (clobber (reg:SI 9))
9750 (clobber (reg:SI 10))
9751 (clobber (match_scratch:SI 5 "=X"))]
9752 "TARGET_STRING && ! TARGET_POWER
9753 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9754 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9755 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9756 && REGNO (operands[4]) == 5"
9757 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9758 [(set_attr "type" "store_ux")
9759 (set_attr "length" "8")])
9760
9761 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9762 ;; problems with TImode.
9763 ;; rD/rS = r5 is preferred, efficient form.
9764 (define_expand "movmemsi_4reg"
9765 [(parallel [(set (match_operand 0 "" "")
9766 (match_operand 1 "" ""))
9767 (use (match_operand 2 "" ""))
9768 (use (match_operand 3 "" ""))
9769 (clobber (reg:SI 5))
9770 (clobber (reg:SI 6))
9771 (clobber (reg:SI 7))
9772 (clobber (reg:SI 8))
9773 (clobber (match_scratch:SI 4 ""))])]
9774 "TARGET_STRING"
9775 "")
9776
9777 (define_insn ""
9778 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9779 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9780 (use (match_operand:SI 2 "immediate_operand" "i"))
9781 (use (match_operand:SI 3 "immediate_operand" "i"))
9782 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9783 (clobber (reg:SI 6))
9784 (clobber (reg:SI 7))
9785 (clobber (reg:SI 8))
9786 (clobber (match_scratch:SI 5 "=q"))]
9787 "TARGET_STRING && TARGET_POWER
9788 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9789 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9790 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9791 && REGNO (operands[4]) == 5"
9792 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9793 [(set_attr "type" "store_ux")
9794 (set_attr "length" "8")])
9795
9796 (define_insn ""
9797 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9798 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9799 (use (match_operand:SI 2 "immediate_operand" "i"))
9800 (use (match_operand:SI 3 "immediate_operand" "i"))
9801 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9802 (clobber (reg:SI 6))
9803 (clobber (reg:SI 7))
9804 (clobber (reg:SI 8))
9805 (clobber (match_scratch:SI 5 "=X"))]
9806 "TARGET_STRING && ! TARGET_POWER
9807 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9808 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9809 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9810 && REGNO (operands[4]) == 5"
9811 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9812 [(set_attr "type" "store_ux")
9813 (set_attr "length" "8")])
9814
9815 ;; Move up to 8 bytes at a time.
9816 (define_expand "movmemsi_2reg"
9817 [(parallel [(set (match_operand 0 "" "")
9818 (match_operand 1 "" ""))
9819 (use (match_operand 2 "" ""))
9820 (use (match_operand 3 "" ""))
9821 (clobber (match_scratch:DI 4 ""))
9822 (clobber (match_scratch:SI 5 ""))])]
9823 "TARGET_STRING && ! TARGET_POWERPC64"
9824 "")
9825
9826 (define_insn ""
9827 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9828 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9829 (use (match_operand:SI 2 "immediate_operand" "i"))
9830 (use (match_operand:SI 3 "immediate_operand" "i"))
9831 (clobber (match_scratch:DI 4 "=&r"))
9832 (clobber (match_scratch:SI 5 "=q"))]
9833 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9834 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9835 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9836 [(set_attr "type" "store_ux")
9837 (set_attr "length" "8")])
9838
9839 (define_insn ""
9840 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9841 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9842 (use (match_operand:SI 2 "immediate_operand" "i"))
9843 (use (match_operand:SI 3 "immediate_operand" "i"))
9844 (clobber (match_scratch:DI 4 "=&r"))
9845 (clobber (match_scratch:SI 5 "=X"))]
9846 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9847 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9848 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9849 [(set_attr "type" "store_ux")
9850 (set_attr "length" "8")])
9851
9852 ;; Move up to 4 bytes at a time.
9853 (define_expand "movmemsi_1reg"
9854 [(parallel [(set (match_operand 0 "" "")
9855 (match_operand 1 "" ""))
9856 (use (match_operand 2 "" ""))
9857 (use (match_operand 3 "" ""))
9858 (clobber (match_scratch:SI 4 ""))
9859 (clobber (match_scratch:SI 5 ""))])]
9860 "TARGET_STRING"
9861 "")
9862
9863 (define_insn ""
9864 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9865 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9866 (use (match_operand:SI 2 "immediate_operand" "i"))
9867 (use (match_operand:SI 3 "immediate_operand" "i"))
9868 (clobber (match_scratch:SI 4 "=&r"))
9869 (clobber (match_scratch:SI 5 "=q"))]
9870 "TARGET_STRING && TARGET_POWER
9871 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9872 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9873 [(set_attr "type" "store_ux")
9874 (set_attr "length" "8")])
9875
9876 (define_insn ""
9877 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9878 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9879 (use (match_operand:SI 2 "immediate_operand" "i"))
9880 (use (match_operand:SI 3 "immediate_operand" "i"))
9881 (clobber (match_scratch:SI 4 "=&r"))
9882 (clobber (match_scratch:SI 5 "=X"))]
9883 "TARGET_STRING && ! TARGET_POWER
9884 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9885 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9886 [(set_attr "type" "store_ux")
9887 (set_attr "length" "8")])
9888 \f
9889 ;; Define insns that do load or store with update. Some of these we can
9890 ;; get by using pre-decrement or pre-increment, but the hardware can also
9891 ;; do cases where the increment is not the size of the object.
9892 ;;
9893 ;; In all these cases, we use operands 0 and 1 for the register being
9894 ;; incremented because those are the operands that local-alloc will
9895 ;; tie and these are the pair most likely to be tieable (and the ones
9896 ;; that will benefit the most).
9897
9898 (define_insn "*movdi_update1"
9899 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9900 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9901 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9902 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9903 (plus:DI (match_dup 1) (match_dup 2)))]
9904 "TARGET_POWERPC64 && TARGET_UPDATE"
9905 "@
9906 ldux %3,%0,%2
9907 ldu %3,%2(%0)"
9908 [(set_attr "type" "load_ux,load_u")])
9909
9910 (define_insn "movdi_<mode>_update"
9911 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9912 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9913 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9914 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9915 (plus:P (match_dup 1) (match_dup 2)))]
9916 "TARGET_POWERPC64 && TARGET_UPDATE"
9917 "@
9918 stdux %3,%0,%2
9919 stdu %3,%2(%0)"
9920 [(set_attr "type" "store_ux,store_u")])
9921
9922 (define_insn "*movsi_update1"
9923 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9924 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9925 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9926 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9927 (plus:SI (match_dup 1) (match_dup 2)))]
9928 "TARGET_UPDATE"
9929 "@
9930 {lux|lwzux} %3,%0,%2
9931 {lu|lwzu} %3,%2(%0)"
9932 [(set_attr "type" "load_ux,load_u")])
9933
9934 (define_insn "*movsi_update2"
9935 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9936 (sign_extend:DI
9937 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9938 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9939 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9940 (plus:DI (match_dup 1) (match_dup 2)))]
9941 "TARGET_POWERPC64"
9942 "lwaux %3,%0,%2"
9943 [(set_attr "type" "load_ext_ux")])
9944
9945 (define_insn "movsi_update"
9946 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9947 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9948 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9949 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9950 (plus:SI (match_dup 1) (match_dup 2)))]
9951 "TARGET_UPDATE"
9952 "@
9953 {stux|stwux} %3,%0,%2
9954 {stu|stwu} %3,%2(%0)"
9955 [(set_attr "type" "store_ux,store_u")])
9956
9957 (define_insn "*movhi_update1"
9958 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9959 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9960 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9961 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9962 (plus:SI (match_dup 1) (match_dup 2)))]
9963 "TARGET_UPDATE"
9964 "@
9965 lhzux %3,%0,%2
9966 lhzu %3,%2(%0)"
9967 [(set_attr "type" "load_ux,load_u")])
9968
9969 (define_insn "*movhi_update2"
9970 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9971 (zero_extend:SI
9972 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9973 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9974 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9975 (plus:SI (match_dup 1) (match_dup 2)))]
9976 "TARGET_UPDATE"
9977 "@
9978 lhzux %3,%0,%2
9979 lhzu %3,%2(%0)"
9980 [(set_attr "type" "load_ux,load_u")])
9981
9982 (define_insn "*movhi_update3"
9983 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9984 (sign_extend:SI
9985 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9986 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9987 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9988 (plus:SI (match_dup 1) (match_dup 2)))]
9989 "TARGET_UPDATE"
9990 "@
9991 lhaux %3,%0,%2
9992 lhau %3,%2(%0)"
9993 [(set_attr "type" "load_ext_ux,load_ext_u")])
9994
9995 (define_insn "*movhi_update4"
9996 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9997 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9998 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9999 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10000 (plus:SI (match_dup 1) (match_dup 2)))]
10001 "TARGET_UPDATE"
10002 "@
10003 sthux %3,%0,%2
10004 sthu %3,%2(%0)"
10005 [(set_attr "type" "store_ux,store_u")])
10006
10007 (define_insn "*movqi_update1"
10008 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
10009 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10010 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10011 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10012 (plus:SI (match_dup 1) (match_dup 2)))]
10013 "TARGET_UPDATE"
10014 "@
10015 lbzux %3,%0,%2
10016 lbzu %3,%2(%0)"
10017 [(set_attr "type" "load_ux,load_u")])
10018
10019 (define_insn "*movqi_update2"
10020 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10021 (zero_extend:SI
10022 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10023 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10024 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10025 (plus:SI (match_dup 1) (match_dup 2)))]
10026 "TARGET_UPDATE"
10027 "@
10028 lbzux %3,%0,%2
10029 lbzu %3,%2(%0)"
10030 [(set_attr "type" "load_ux,load_u")])
10031
10032 (define_insn "*movqi_update3"
10033 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10034 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10035 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
10036 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10037 (plus:SI (match_dup 1) (match_dup 2)))]
10038 "TARGET_UPDATE"
10039 "@
10040 stbux %3,%0,%2
10041 stbu %3,%2(%0)"
10042 [(set_attr "type" "store_ux,store_u")])
10043
10044 (define_insn "*movsf_update1"
10045 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
10046 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10047 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10048 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10049 (plus:SI (match_dup 1) (match_dup 2)))]
10050 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE"
10051 "@
10052 lfsux %3,%0,%2
10053 lfsu %3,%2(%0)"
10054 [(set_attr "type" "fpload_ux,fpload_u")])
10055
10056 (define_insn "*movsf_update2"
10057 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10058 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10059 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10060 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10061 (plus:SI (match_dup 1) (match_dup 2)))]
10062 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE"
10063 "@
10064 stfsux %3,%0,%2
10065 stfsu %3,%2(%0)"
10066 [(set_attr "type" "fpstore_ux,fpstore_u")])
10067
10068 (define_insn "*movsf_update3"
10069 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10070 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10071 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10072 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10073 (plus:SI (match_dup 1) (match_dup 2)))]
10074 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
10075 "@
10076 {lux|lwzux} %3,%0,%2
10077 {lu|lwzu} %3,%2(%0)"
10078 [(set_attr "type" "load_ux,load_u")])
10079
10080 (define_insn "*movsf_update4"
10081 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10082 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10083 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10084 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10085 (plus:SI (match_dup 1) (match_dup 2)))]
10086 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
10087 "@
10088 {stux|stwux} %3,%0,%2
10089 {stu|stwu} %3,%2(%0)"
10090 [(set_attr "type" "store_ux,store_u")])
10091
10092 (define_insn "*movdf_update1"
10093 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
10094 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10095 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10096 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10097 (plus:SI (match_dup 1) (match_dup 2)))]
10098 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE"
10099 "@
10100 lfdux %3,%0,%2
10101 lfdu %3,%2(%0)"
10102 [(set_attr "type" "fpload_ux,fpload_u")])
10103
10104 (define_insn "*movdf_update2"
10105 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10106 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10107 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
10108 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10109 (plus:SI (match_dup 1) (match_dup 2)))]
10110 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE"
10111 "@
10112 stfdux %3,%0,%2
10113 stfdu %3,%2(%0)"
10114 [(set_attr "type" "fpstore_ux,fpstore_u")])
10115
10116 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
10117
10118 (define_insn "*lfq_power2"
10119 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
10120 (match_operand:V2DF 1 "memory_operand" ""))]
10121 "TARGET_POWER2
10122 && TARGET_HARD_FLOAT && TARGET_FPRS"
10123 "lfq%U1%X1 %0,%1")
10124
10125 (define_peephole2
10126 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10127 (match_operand:DF 1 "memory_operand" ""))
10128 (set (match_operand:DF 2 "gpc_reg_operand" "")
10129 (match_operand:DF 3 "memory_operand" ""))]
10130 "TARGET_POWER2
10131 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
10132 && registers_ok_for_quad_peep (operands[0], operands[2])
10133 && mems_ok_for_quad_peep (operands[1], operands[3])"
10134 [(set (match_dup 0)
10135 (match_dup 1))]
10136 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
10137 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
10138
10139 (define_insn "*stfq_power2"
10140 [(set (match_operand:V2DF 0 "memory_operand" "")
10141 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
10142 "TARGET_POWER2
10143 && TARGET_HARD_FLOAT && TARGET_FPRS"
10144 "stfq%U0%X0 %1,%0")
10145
10146
10147 (define_peephole2
10148 [(set (match_operand:DF 0 "memory_operand" "")
10149 (match_operand:DF 1 "gpc_reg_operand" ""))
10150 (set (match_operand:DF 2 "memory_operand" "")
10151 (match_operand:DF 3 "gpc_reg_operand" ""))]
10152 "TARGET_POWER2
10153 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
10154 && registers_ok_for_quad_peep (operands[1], operands[3])
10155 && mems_ok_for_quad_peep (operands[0], operands[2])"
10156 [(set (match_dup 0)
10157 (match_dup 1))]
10158 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
10159 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
10160
10161 ;; After inserting conditional returns we can sometimes have
10162 ;; unnecessary register moves. Unfortunately we cannot have a
10163 ;; modeless peephole here, because some single SImode sets have early
10164 ;; clobber outputs. Although those sets expand to multi-ppc-insn
10165 ;; sequences, using get_attr_length here will smash the operands
10166 ;; array. Neither is there an early_cobbler_p predicate.
10167 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
10168 (define_peephole2
10169 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10170 (match_operand:DF 1 "any_operand" ""))
10171 (set (match_operand:DF 2 "gpc_reg_operand" "")
10172 (match_dup 0))]
10173 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10174 && peep2_reg_dead_p (2, operands[0])"
10175 [(set (match_dup 2) (match_dup 1))])
10176
10177 (define_peephole2
10178 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10179 (match_operand:SF 1 "any_operand" ""))
10180 (set (match_operand:SF 2 "gpc_reg_operand" "")
10181 (match_dup 0))]
10182 "peep2_reg_dead_p (2, operands[0])"
10183 [(set (match_dup 2) (match_dup 1))])
10184
10185 \f
10186 ;; TLS support.
10187
10188 ;; Mode attributes for different ABIs.
10189 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
10190 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
10191 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
10192 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
10193
10194 (define_insn "tls_gd_aix<TLSmode:tls_abi_suffix>"
10195 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10196 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10197 (match_operand 4 "" "g")))
10198 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10199 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10200 UNSPEC_TLSGD)
10201 (clobber (reg:SI LR_REGNO))]
10202 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10203 "addi %0,%1,%2@got@tlsgd\;bl %z3\;%."
10204 [(set_attr "type" "two")
10205 (set_attr "length" "12")])
10206
10207 (define_insn "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
10208 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10209 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10210 (match_operand 4 "" "g")))
10211 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10212 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10213 UNSPEC_TLSGD)
10214 (clobber (reg:SI LR_REGNO))]
10215 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10216 {
10217 if (flag_pic)
10218 {
10219 if (TARGET_SECURE_PLT && flag_pic == 2)
10220 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
10221 else
10222 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
10223 }
10224 else
10225 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
10226 }
10227 [(set_attr "type" "two")
10228 (set_attr "length" "8")])
10229
10230 (define_insn "tls_ld_aix<TLSmode:tls_abi_suffix>"
10231 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10232 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10233 (match_operand 3 "" "g")))
10234 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10235 UNSPEC_TLSLD)
10236 (clobber (reg:SI LR_REGNO))]
10237 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10238 "addi %0,%1,%&@got@tlsld\;bl %z2\;%."
10239 [(set_attr "length" "12")])
10240
10241 (define_insn "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
10242 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10243 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10244 (match_operand 3 "" "g")))
10245 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10246 UNSPEC_TLSLD)
10247 (clobber (reg:SI LR_REGNO))]
10248 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10249 {
10250 if (flag_pic)
10251 {
10252 if (TARGET_SECURE_PLT && flag_pic == 2)
10253 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
10254 else
10255 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
10256 }
10257 else
10258 return "addi %0,%1,%&@got@tlsld\;bl %z2";
10259 }
10260 [(set_attr "length" "8")])
10261
10262 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
10263 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10264 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10265 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10266 UNSPEC_TLSDTPREL))]
10267 "HAVE_AS_TLS"
10268 "addi %0,%1,%2@dtprel")
10269
10270 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
10271 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10272 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10273 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10274 UNSPEC_TLSDTPRELHA))]
10275 "HAVE_AS_TLS"
10276 "addis %0,%1,%2@dtprel@ha")
10277
10278 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
10279 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10280 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10281 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10282 UNSPEC_TLSDTPRELLO))]
10283 "HAVE_AS_TLS"
10284 "addi %0,%1,%2@dtprel@l")
10285
10286 (define_insn "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
10287 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10288 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10289 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10290 UNSPEC_TLSGOTDTPREL))]
10291 "HAVE_AS_TLS"
10292 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)")
10293
10294 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
10295 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10296 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10297 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10298 UNSPEC_TLSTPREL))]
10299 "HAVE_AS_TLS"
10300 "addi %0,%1,%2@tprel")
10301
10302 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
10303 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10304 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10305 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10306 UNSPEC_TLSTPRELHA))]
10307 "HAVE_AS_TLS"
10308 "addis %0,%1,%2@tprel@ha")
10309
10310 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
10311 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10312 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10313 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10314 UNSPEC_TLSTPRELLO))]
10315 "HAVE_AS_TLS"
10316 "addi %0,%1,%2@tprel@l")
10317
10318 ;; "b" output constraint here and on tls_tls input to support linker tls
10319 ;; optimization. The linker may edit the instructions emitted by a
10320 ;; tls_got_tprel/tls_tls pair to addis,addi.
10321 (define_insn "tls_got_tprel_<TLSmode:tls_abi_suffix>"
10322 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10323 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10324 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10325 UNSPEC_TLSGOTTPREL))]
10326 "HAVE_AS_TLS"
10327 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)")
10328
10329 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
10330 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10331 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10332 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10333 UNSPEC_TLSTLS))]
10334 "HAVE_AS_TLS"
10335 "add %0,%1,%2@tls")
10336
10337 \f
10338 ;; Next come insns related to the calling sequence.
10339 ;;
10340 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
10341 ;; We move the back-chain and decrement the stack pointer.
10342
10343 (define_expand "allocate_stack"
10344 [(set (match_operand 0 "gpc_reg_operand" "")
10345 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10346 (set (reg 1)
10347 (minus (reg 1) (match_dup 1)))]
10348 ""
10349 "
10350 { rtx chain = gen_reg_rtx (Pmode);
10351 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
10352 rtx neg_op0;
10353
10354 emit_move_insn (chain, stack_bot);
10355
10356 /* Check stack bounds if necessary. */
10357 if (crtl->limit_stack)
10358 {
10359 rtx available;
10360 available = expand_binop (Pmode, sub_optab,
10361 stack_pointer_rtx, stack_limit_rtx,
10362 NULL_RTX, 1, OPTAB_WIDEN);
10363 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10364 }
10365
10366 if (GET_CODE (operands[1]) != CONST_INT
10367 || INTVAL (operands[1]) < -32767
10368 || INTVAL (operands[1]) > 32768)
10369 {
10370 neg_op0 = gen_reg_rtx (Pmode);
10371 if (TARGET_32BIT)
10372 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10373 else
10374 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10375 }
10376 else
10377 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10378
10379 if (TARGET_UPDATE)
10380 {
10381 rtx insn, par, set, mem;
10382
10383 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update
10384 : gen_movdi_di_update))
10385 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
10386 chain));
10387 /* Since we didn't use gen_frame_mem to generate the MEM, grab
10388 it now and set the alias set/attributes. The above gen_*_update
10389 calls will generate a PARALLEL with the MEM set being the first
10390 operation. */
10391 par = PATTERN (insn);
10392 gcc_assert (GET_CODE (par) == PARALLEL);
10393 set = XVECEXP (par, 0, 0);
10394 gcc_assert (GET_CODE (set) == SET);
10395 mem = SET_DEST (set);
10396 gcc_assert (MEM_P (mem));
10397 MEM_NOTRAP_P (mem) = 1;
10398 set_mem_alias_set (mem, get_frame_alias_set ());
10399 }
10400
10401 else
10402 {
10403 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
10404 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
10405 emit_move_insn (gen_frame_mem (Pmode, stack_pointer_rtx), chain);
10406 }
10407
10408 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10409 DONE;
10410 }")
10411
10412 ;; These patterns say how to save and restore the stack pointer. We need not
10413 ;; save the stack pointer at function level since we are careful to
10414 ;; preserve the backchain. At block level, we have to restore the backchain
10415 ;; when we restore the stack pointer.
10416 ;;
10417 ;; For nonlocal gotos, we must save both the stack pointer and its
10418 ;; backchain and restore both. Note that in the nonlocal case, the
10419 ;; save area is a memory location.
10420
10421 (define_expand "save_stack_function"
10422 [(match_operand 0 "any_operand" "")
10423 (match_operand 1 "any_operand" "")]
10424 ""
10425 "DONE;")
10426
10427 (define_expand "restore_stack_function"
10428 [(match_operand 0 "any_operand" "")
10429 (match_operand 1 "any_operand" "")]
10430 ""
10431 "DONE;")
10432
10433 ;; Adjust stack pointer (op0) to a new value (op1).
10434 ;; First copy old stack backchain to new location, and ensure that the
10435 ;; scheduler won't reorder the sp assignment before the backchain write.
10436 (define_expand "restore_stack_block"
10437 [(set (match_dup 2) (match_dup 3))
10438 (set (match_dup 4) (match_dup 2))
10439 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
10440 (set (match_operand 0 "register_operand" "")
10441 (match_operand 1 "register_operand" ""))]
10442 ""
10443 "
10444 {
10445 operands[1] = force_reg (Pmode, operands[1]);
10446 operands[2] = gen_reg_rtx (Pmode);
10447 operands[3] = gen_frame_mem (Pmode, operands[0]);
10448 operands[4] = gen_frame_mem (Pmode, operands[1]);
10449 operands[5] = gen_frame_mem (BLKmode, operands[0]);
10450 }")
10451
10452 (define_expand "save_stack_nonlocal"
10453 [(set (match_dup 3) (match_dup 4))
10454 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10455 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
10456 ""
10457 "
10458 {
10459 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10460
10461 /* Copy the backchain to the first word, sp to the second. */
10462 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10463 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10464 operands[3] = gen_reg_rtx (Pmode);
10465 operands[4] = gen_frame_mem (Pmode, operands[1]);
10466 }")
10467
10468 (define_expand "restore_stack_nonlocal"
10469 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10470 (set (match_dup 3) (match_dup 4))
10471 (set (match_dup 5) (match_dup 2))
10472 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
10473 (set (match_operand 0 "register_operand" "") (match_dup 3))]
10474 ""
10475 "
10476 {
10477 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10478
10479 /* Restore the backchain from the first word, sp from the second. */
10480 operands[2] = gen_reg_rtx (Pmode);
10481 operands[3] = gen_reg_rtx (Pmode);
10482 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10483 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10484 operands[5] = gen_frame_mem (Pmode, operands[3]);
10485 operands[6] = gen_frame_mem (BLKmode, operands[0]);
10486 }")
10487 \f
10488 ;; TOC register handling.
10489
10490 ;; Code to initialize the TOC register...
10491
10492 (define_insn "load_toc_aix_si"
10493 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10494 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10495 (use (reg:SI 2))])]
10496 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10497 "*
10498 {
10499 char buf[30];
10500 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10501 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10502 operands[2] = gen_rtx_REG (Pmode, 2);
10503 return \"{l|lwz} %0,%1(%2)\";
10504 }"
10505 [(set_attr "type" "load")])
10506
10507 (define_insn "load_toc_aix_di"
10508 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10509 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10510 (use (reg:DI 2))])]
10511 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10512 "*
10513 {
10514 char buf[30];
10515 #ifdef TARGET_RELOCATABLE
10516 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10517 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10518 #else
10519 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10520 #endif
10521 if (TARGET_ELF)
10522 strcat (buf, \"@toc\");
10523 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10524 operands[2] = gen_rtx_REG (Pmode, 2);
10525 return \"ld %0,%1(%2)\";
10526 }"
10527 [(set_attr "type" "load")])
10528
10529 (define_insn "load_toc_v4_pic_si"
10530 [(set (reg:SI LR_REGNO)
10531 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10532 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10533 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10534 [(set_attr "type" "branch")
10535 (set_attr "length" "4")])
10536
10537 (define_insn "load_toc_v4_PIC_1"
10538 [(set (reg:SI LR_REGNO)
10539 (match_operand:SI 0 "immediate_operand" "s"))
10540 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10541 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
10542 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10543 "bcl 20,31,%0\\n%0:"
10544 [(set_attr "type" "branch")
10545 (set_attr "length" "4")])
10546
10547 (define_insn "load_toc_v4_PIC_1b"
10548 [(set (reg:SI LR_REGNO)
10549 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")]
10550 UNSPEC_TOCPTR))]
10551 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10552 "bcl 20,31,$+8\\n\\t.long %0-$"
10553 [(set_attr "type" "branch")
10554 (set_attr "length" "8")])
10555
10556 (define_insn "load_toc_v4_PIC_2"
10557 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10558 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10559 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10560 (match_operand:SI 3 "immediate_operand" "s")))))]
10561 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10562 "{l|lwz} %0,%2-%3(%1)"
10563 [(set_attr "type" "load")])
10564
10565 (define_insn "load_toc_v4_PIC_3b"
10566 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10567 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10568 (high:SI
10569 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10570 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10571 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10572 "{cau|addis} %0,%1,%2-%3@ha")
10573
10574 (define_insn "load_toc_v4_PIC_3c"
10575 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10576 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10577 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10578 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10579 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10580 "{cal|addi} %0,%1,%2-%3@l")
10581
10582 ;; If the TOC is shared over a translation unit, as happens with all
10583 ;; the kinds of PIC that we support, we need to restore the TOC
10584 ;; pointer only when jumping over units of translation.
10585 ;; On Darwin, we need to reload the picbase.
10586
10587 (define_expand "builtin_setjmp_receiver"
10588 [(use (label_ref (match_operand 0 "" "")))]
10589 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10590 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10591 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10592 "
10593 {
10594 #if TARGET_MACHO
10595 if (DEFAULT_ABI == ABI_DARWIN)
10596 {
10597 const char *picbase = machopic_function_base_name ();
10598 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
10599 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10600 rtx tmplabrtx;
10601 char tmplab[20];
10602
10603 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10604 CODE_LABEL_NUMBER (operands[0]));
10605 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10606
10607 emit_insn (gen_load_macho_picbase (tmplabrtx));
10608 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
10609 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10610 }
10611 else
10612 #endif
10613 rs6000_emit_load_toc_table (FALSE);
10614 DONE;
10615 }")
10616
10617 ;; Elf specific ways of loading addresses for non-PIC code.
10618 ;; The output of this could be r0, but we make a very strong
10619 ;; preference for a base register because it will usually
10620 ;; be needed there.
10621 (define_insn "elf_high"
10622 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10623 (high:SI (match_operand 1 "" "")))]
10624 "TARGET_ELF && ! TARGET_64BIT"
10625 "{liu|lis} %0,%1@ha")
10626
10627 (define_insn "elf_low"
10628 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10629 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10630 (match_operand 2 "" "")))]
10631 "TARGET_ELF && ! TARGET_64BIT"
10632 "@
10633 {cal|la} %0,%2@l(%1)
10634 {ai|addic} %0,%1,%K2")
10635 \f
10636 ;; A function pointer under AIX is a pointer to a data area whose first word
10637 ;; contains the actual address of the function, whose second word contains a
10638 ;; pointer to its TOC, and whose third word contains a value to place in the
10639 ;; static chain register (r11). Note that if we load the static chain, our
10640 ;; "trampoline" need not have any executable code.
10641
10642 (define_expand "call_indirect_aix32"
10643 [(set (match_dup 2)
10644 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10645 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10646 (reg:SI 2))
10647 (set (reg:SI 2)
10648 (mem:SI (plus:SI (match_dup 0)
10649 (const_int 4))))
10650 (set (reg:SI 11)
10651 (mem:SI (plus:SI (match_dup 0)
10652 (const_int 8))))
10653 (parallel [(call (mem:SI (match_dup 2))
10654 (match_operand 1 "" ""))
10655 (use (reg:SI 2))
10656 (use (reg:SI 11))
10657 (set (reg:SI 2)
10658 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10659 (clobber (reg:SI LR_REGNO))])]
10660 "TARGET_32BIT"
10661 "
10662 { operands[2] = gen_reg_rtx (SImode); }")
10663
10664 (define_expand "call_indirect_aix64"
10665 [(set (match_dup 2)
10666 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10667 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10668 (reg:DI 2))
10669 (set (reg:DI 2)
10670 (mem:DI (plus:DI (match_dup 0)
10671 (const_int 8))))
10672 (set (reg:DI 11)
10673 (mem:DI (plus:DI (match_dup 0)
10674 (const_int 16))))
10675 (parallel [(call (mem:SI (match_dup 2))
10676 (match_operand 1 "" ""))
10677 (use (reg:DI 2))
10678 (use (reg:DI 11))
10679 (set (reg:DI 2)
10680 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10681 (clobber (reg:SI LR_REGNO))])]
10682 "TARGET_64BIT"
10683 "
10684 { operands[2] = gen_reg_rtx (DImode); }")
10685
10686 (define_expand "call_value_indirect_aix32"
10687 [(set (match_dup 3)
10688 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10689 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10690 (reg:SI 2))
10691 (set (reg:SI 2)
10692 (mem:SI (plus:SI (match_dup 1)
10693 (const_int 4))))
10694 (set (reg:SI 11)
10695 (mem:SI (plus:SI (match_dup 1)
10696 (const_int 8))))
10697 (parallel [(set (match_operand 0 "" "")
10698 (call (mem:SI (match_dup 3))
10699 (match_operand 2 "" "")))
10700 (use (reg:SI 2))
10701 (use (reg:SI 11))
10702 (set (reg:SI 2)
10703 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10704 (clobber (reg:SI LR_REGNO))])]
10705 "TARGET_32BIT"
10706 "
10707 { operands[3] = gen_reg_rtx (SImode); }")
10708
10709 (define_expand "call_value_indirect_aix64"
10710 [(set (match_dup 3)
10711 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10712 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10713 (reg:DI 2))
10714 (set (reg:DI 2)
10715 (mem:DI (plus:DI (match_dup 1)
10716 (const_int 8))))
10717 (set (reg:DI 11)
10718 (mem:DI (plus:DI (match_dup 1)
10719 (const_int 16))))
10720 (parallel [(set (match_operand 0 "" "")
10721 (call (mem:SI (match_dup 3))
10722 (match_operand 2 "" "")))
10723 (use (reg:DI 2))
10724 (use (reg:DI 11))
10725 (set (reg:DI 2)
10726 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10727 (clobber (reg:SI LR_REGNO))])]
10728 "TARGET_64BIT"
10729 "
10730 { operands[3] = gen_reg_rtx (DImode); }")
10731
10732 ;; Now the definitions for the call and call_value insns
10733 (define_expand "call"
10734 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10735 (match_operand 1 "" ""))
10736 (use (match_operand 2 "" ""))
10737 (clobber (reg:SI LR_REGNO))])]
10738 ""
10739 "
10740 {
10741 #if TARGET_MACHO
10742 if (MACHOPIC_INDIRECT)
10743 operands[0] = machopic_indirect_call_target (operands[0]);
10744 #endif
10745
10746 gcc_assert (GET_CODE (operands[0]) == MEM);
10747 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10748
10749 operands[0] = XEXP (operands[0], 0);
10750
10751 if (GET_CODE (operands[0]) != SYMBOL_REF
10752 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10753 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10754 {
10755 if (INTVAL (operands[2]) & CALL_LONG)
10756 operands[0] = rs6000_longcall_ref (operands[0]);
10757
10758 switch (DEFAULT_ABI)
10759 {
10760 case ABI_V4:
10761 case ABI_DARWIN:
10762 operands[0] = force_reg (Pmode, operands[0]);
10763 break;
10764
10765 case ABI_AIX:
10766 /* AIX function pointers are really pointers to a three word
10767 area. */
10768 emit_call_insn (TARGET_32BIT
10769 ? gen_call_indirect_aix32 (force_reg (SImode,
10770 operands[0]),
10771 operands[1])
10772 : gen_call_indirect_aix64 (force_reg (DImode,
10773 operands[0]),
10774 operands[1]));
10775 DONE;
10776
10777 default:
10778 gcc_unreachable ();
10779 }
10780 }
10781 }")
10782
10783 (define_expand "call_value"
10784 [(parallel [(set (match_operand 0 "" "")
10785 (call (mem:SI (match_operand 1 "address_operand" ""))
10786 (match_operand 2 "" "")))
10787 (use (match_operand 3 "" ""))
10788 (clobber (reg:SI LR_REGNO))])]
10789 ""
10790 "
10791 {
10792 #if TARGET_MACHO
10793 if (MACHOPIC_INDIRECT)
10794 operands[1] = machopic_indirect_call_target (operands[1]);
10795 #endif
10796
10797 gcc_assert (GET_CODE (operands[1]) == MEM);
10798 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10799
10800 operands[1] = XEXP (operands[1], 0);
10801
10802 if (GET_CODE (operands[1]) != SYMBOL_REF
10803 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10804 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10805 {
10806 if (INTVAL (operands[3]) & CALL_LONG)
10807 operands[1] = rs6000_longcall_ref (operands[1]);
10808
10809 switch (DEFAULT_ABI)
10810 {
10811 case ABI_V4:
10812 case ABI_DARWIN:
10813 operands[1] = force_reg (Pmode, operands[1]);
10814 break;
10815
10816 case ABI_AIX:
10817 /* AIX function pointers are really pointers to a three word
10818 area. */
10819 emit_call_insn (TARGET_32BIT
10820 ? gen_call_value_indirect_aix32 (operands[0],
10821 force_reg (SImode,
10822 operands[1]),
10823 operands[2])
10824 : gen_call_value_indirect_aix64 (operands[0],
10825 force_reg (DImode,
10826 operands[1]),
10827 operands[2]));
10828 DONE;
10829
10830 default:
10831 gcc_unreachable ();
10832 }
10833 }
10834 }")
10835
10836 ;; Call to function in current module. No TOC pointer reload needed.
10837 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10838 ;; either the function was not prototyped, or it was prototyped as a
10839 ;; variable argument function. It is > 0 if FP registers were passed
10840 ;; and < 0 if they were not.
10841
10842 (define_insn "*call_local32"
10843 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10844 (match_operand 1 "" "g,g"))
10845 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10846 (clobber (reg:SI LR_REGNO))]
10847 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10848 "*
10849 {
10850 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10851 output_asm_insn (\"crxor 6,6,6\", operands);
10852
10853 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10854 output_asm_insn (\"creqv 6,6,6\", operands);
10855
10856 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10857 }"
10858 [(set_attr "type" "branch")
10859 (set_attr "length" "4,8")])
10860
10861 (define_insn "*call_local64"
10862 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10863 (match_operand 1 "" "g,g"))
10864 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10865 (clobber (reg:SI LR_REGNO))]
10866 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10867 "*
10868 {
10869 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10870 output_asm_insn (\"crxor 6,6,6\", operands);
10871
10872 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10873 output_asm_insn (\"creqv 6,6,6\", operands);
10874
10875 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10876 }"
10877 [(set_attr "type" "branch")
10878 (set_attr "length" "4,8")])
10879
10880 (define_insn "*call_value_local32"
10881 [(set (match_operand 0 "" "")
10882 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10883 (match_operand 2 "" "g,g")))
10884 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10885 (clobber (reg:SI LR_REGNO))]
10886 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10887 "*
10888 {
10889 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10890 output_asm_insn (\"crxor 6,6,6\", operands);
10891
10892 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10893 output_asm_insn (\"creqv 6,6,6\", operands);
10894
10895 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10896 }"
10897 [(set_attr "type" "branch")
10898 (set_attr "length" "4,8")])
10899
10900
10901 (define_insn "*call_value_local64"
10902 [(set (match_operand 0 "" "")
10903 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10904 (match_operand 2 "" "g,g")))
10905 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10906 (clobber (reg:SI LR_REGNO))]
10907 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10908 "*
10909 {
10910 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10911 output_asm_insn (\"crxor 6,6,6\", operands);
10912
10913 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10914 output_asm_insn (\"creqv 6,6,6\", operands);
10915
10916 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10917 }"
10918 [(set_attr "type" "branch")
10919 (set_attr "length" "4,8")])
10920
10921 ;; Call to function which may be in another module. Restore the TOC
10922 ;; pointer (r2) after the call unless this is System V.
10923 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10924 ;; either the function was not prototyped, or it was prototyped as a
10925 ;; variable argument function. It is > 0 if FP registers were passed
10926 ;; and < 0 if they were not.
10927
10928 (define_insn "*call_indirect_nonlocal_aix32"
10929 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
10930 (match_operand 1 "" "g,g"))
10931 (use (reg:SI 2))
10932 (use (reg:SI 11))
10933 (set (reg:SI 2)
10934 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10935 (clobber (reg:SI LR_REGNO))]
10936 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10937 "b%T0l\;{l|lwz} 2,20(1)"
10938 [(set_attr "type" "jmpreg")
10939 (set_attr "length" "8")])
10940
10941 (define_insn "*call_nonlocal_aix32"
10942 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10943 (match_operand 1 "" "g"))
10944 (use (match_operand:SI 2 "immediate_operand" "O"))
10945 (clobber (reg:SI LR_REGNO))]
10946 "TARGET_32BIT
10947 && DEFAULT_ABI == ABI_AIX
10948 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10949 "bl %z0\;%."
10950 [(set_attr "type" "branch")
10951 (set_attr "length" "8")])
10952
10953 (define_insn "*call_indirect_nonlocal_aix64"
10954 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
10955 (match_operand 1 "" "g,g"))
10956 (use (reg:DI 2))
10957 (use (reg:DI 11))
10958 (set (reg:DI 2)
10959 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10960 (clobber (reg:SI LR_REGNO))]
10961 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10962 "b%T0l\;ld 2,40(1)"
10963 [(set_attr "type" "jmpreg")
10964 (set_attr "length" "8")])
10965
10966 (define_insn "*call_nonlocal_aix64"
10967 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10968 (match_operand 1 "" "g"))
10969 (use (match_operand:SI 2 "immediate_operand" "O"))
10970 (clobber (reg:SI LR_REGNO))]
10971 "TARGET_64BIT
10972 && DEFAULT_ABI == ABI_AIX
10973 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10974 "bl %z0\;%."
10975 [(set_attr "type" "branch")
10976 (set_attr "length" "8")])
10977
10978 (define_insn "*call_value_indirect_nonlocal_aix32"
10979 [(set (match_operand 0 "" "")
10980 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
10981 (match_operand 2 "" "g,g")))
10982 (use (reg:SI 2))
10983 (use (reg:SI 11))
10984 (set (reg:SI 2)
10985 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10986 (clobber (reg:SI LR_REGNO))]
10987 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10988 "b%T1l\;{l|lwz} 2,20(1)"
10989 [(set_attr "type" "jmpreg")
10990 (set_attr "length" "8")])
10991
10992 (define_insn "*call_value_nonlocal_aix32"
10993 [(set (match_operand 0 "" "")
10994 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10995 (match_operand 2 "" "g")))
10996 (use (match_operand:SI 3 "immediate_operand" "O"))
10997 (clobber (reg:SI LR_REGNO))]
10998 "TARGET_32BIT
10999 && DEFAULT_ABI == ABI_AIX
11000 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11001 "bl %z1\;%."
11002 [(set_attr "type" "branch")
11003 (set_attr "length" "8")])
11004
11005 (define_insn "*call_value_indirect_nonlocal_aix64"
11006 [(set (match_operand 0 "" "")
11007 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
11008 (match_operand 2 "" "g,g")))
11009 (use (reg:DI 2))
11010 (use (reg:DI 11))
11011 (set (reg:DI 2)
11012 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11013 (clobber (reg:SI LR_REGNO))]
11014 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11015 "b%T1l\;ld 2,40(1)"
11016 [(set_attr "type" "jmpreg")
11017 (set_attr "length" "8")])
11018
11019 (define_insn "*call_value_nonlocal_aix64"
11020 [(set (match_operand 0 "" "")
11021 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11022 (match_operand 2 "" "g")))
11023 (use (match_operand:SI 3 "immediate_operand" "O"))
11024 (clobber (reg:SI LR_REGNO))]
11025 "TARGET_64BIT
11026 && DEFAULT_ABI == ABI_AIX
11027 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11028 "bl %z1\;%."
11029 [(set_attr "type" "branch")
11030 (set_attr "length" "8")])
11031
11032 ;; A function pointer under System V is just a normal pointer
11033 ;; operands[0] is the function pointer
11034 ;; operands[1] is the stack size to clean up
11035 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
11036 ;; which indicates how to set cr1
11037
11038 (define_insn "*call_indirect_nonlocal_sysv<mode>"
11039 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
11040 (match_operand 1 "" "g,g,g,g"))
11041 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
11042 (clobber (reg:SI LR_REGNO))]
11043 "DEFAULT_ABI == ABI_V4
11044 || DEFAULT_ABI == ABI_DARWIN"
11045 {
11046 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11047 output_asm_insn ("crxor 6,6,6", operands);
11048
11049 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11050 output_asm_insn ("creqv 6,6,6", operands);
11051
11052 return "b%T0l";
11053 }
11054 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11055 (set_attr "length" "4,4,8,8")])
11056
11057 (define_insn_and_split "*call_nonlocal_sysv<mode>"
11058 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11059 (match_operand 1 "" "g,g"))
11060 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11061 (clobber (reg:SI LR_REGNO))]
11062 "(DEFAULT_ABI == ABI_DARWIN
11063 || (DEFAULT_ABI == ABI_V4
11064 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
11065 {
11066 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11067 output_asm_insn ("crxor 6,6,6", operands);
11068
11069 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11070 output_asm_insn ("creqv 6,6,6", operands);
11071
11072 #if TARGET_MACHO
11073 return output_call(insn, operands, 0, 2);
11074 #else
11075 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11076 {
11077 gcc_assert (!TARGET_SECURE_PLT);
11078 return "bl %z0@plt";
11079 }
11080 else
11081 return "bl %z0";
11082 #endif
11083 }
11084 "DEFAULT_ABI == ABI_V4
11085 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11086 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11087 [(parallel [(call (mem:SI (match_dup 0))
11088 (match_dup 1))
11089 (use (match_dup 2))
11090 (use (match_dup 3))
11091 (clobber (reg:SI LR_REGNO))])]
11092 {
11093 operands[3] = pic_offset_table_rtx;
11094 }
11095 [(set_attr "type" "branch,branch")
11096 (set_attr "length" "4,8")])
11097
11098 (define_insn "*call_nonlocal_sysv_secure<mode>"
11099 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11100 (match_operand 1 "" "g,g"))
11101 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11102 (use (match_operand:SI 3 "register_operand" "r,r"))
11103 (clobber (reg:SI LR_REGNO))]
11104 "(DEFAULT_ABI == ABI_V4
11105 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11106 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
11107 {
11108 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11109 output_asm_insn ("crxor 6,6,6", operands);
11110
11111 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11112 output_asm_insn ("creqv 6,6,6", operands);
11113
11114 if (flag_pic == 2)
11115 /* The magic 32768 offset here and in the other sysv call insns
11116 corresponds to the offset of r30 in .got2, as given by LCTOC1.
11117 See sysv4.h:toc_section. */
11118 return "bl %z0+32768@plt";
11119 else
11120 return "bl %z0@plt";
11121 }
11122 [(set_attr "type" "branch,branch")
11123 (set_attr "length" "4,8")])
11124
11125 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
11126 [(set (match_operand 0 "" "")
11127 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
11128 (match_operand 2 "" "g,g,g,g")))
11129 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
11130 (clobber (reg:SI LR_REGNO))]
11131 "DEFAULT_ABI == ABI_V4
11132 || DEFAULT_ABI == ABI_DARWIN"
11133 {
11134 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11135 output_asm_insn ("crxor 6,6,6", operands);
11136
11137 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11138 output_asm_insn ("creqv 6,6,6", operands);
11139
11140 return "b%T1l";
11141 }
11142 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11143 (set_attr "length" "4,4,8,8")])
11144
11145 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
11146 [(set (match_operand 0 "" "")
11147 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11148 (match_operand 2 "" "g,g")))
11149 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11150 (clobber (reg:SI LR_REGNO))]
11151 "(DEFAULT_ABI == ABI_DARWIN
11152 || (DEFAULT_ABI == ABI_V4
11153 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
11154 {
11155 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11156 output_asm_insn ("crxor 6,6,6", operands);
11157
11158 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11159 output_asm_insn ("creqv 6,6,6", operands);
11160
11161 #if TARGET_MACHO
11162 return output_call(insn, operands, 1, 3);
11163 #else
11164 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11165 {
11166 gcc_assert (!TARGET_SECURE_PLT);
11167 return "bl %z1@plt";
11168 }
11169 else
11170 return "bl %z1";
11171 #endif
11172 }
11173 "DEFAULT_ABI == ABI_V4
11174 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11175 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11176 [(parallel [(set (match_dup 0)
11177 (call (mem:SI (match_dup 1))
11178 (match_dup 2)))
11179 (use (match_dup 3))
11180 (use (match_dup 4))
11181 (clobber (reg:SI LR_REGNO))])]
11182 {
11183 operands[4] = pic_offset_table_rtx;
11184 }
11185 [(set_attr "type" "branch,branch")
11186 (set_attr "length" "4,8")])
11187
11188 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
11189 [(set (match_operand 0 "" "")
11190 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11191 (match_operand 2 "" "g,g")))
11192 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11193 (use (match_operand:SI 4 "register_operand" "r,r"))
11194 (clobber (reg:SI LR_REGNO))]
11195 "(DEFAULT_ABI == ABI_V4
11196 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11197 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
11198 {
11199 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11200 output_asm_insn ("crxor 6,6,6", operands);
11201
11202 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11203 output_asm_insn ("creqv 6,6,6", operands);
11204
11205 if (flag_pic == 2)
11206 return "bl %z1+32768@plt";
11207 else
11208 return "bl %z1@plt";
11209 }
11210 [(set_attr "type" "branch,branch")
11211 (set_attr "length" "4,8")])
11212
11213 ;; Call subroutine returning any type.
11214 (define_expand "untyped_call"
11215 [(parallel [(call (match_operand 0 "" "")
11216 (const_int 0))
11217 (match_operand 1 "" "")
11218 (match_operand 2 "" "")])]
11219 ""
11220 "
11221 {
11222 int i;
11223
11224 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
11225
11226 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11227 {
11228 rtx set = XVECEXP (operands[2], 0, i);
11229 emit_move_insn (SET_DEST (set), SET_SRC (set));
11230 }
11231
11232 /* The optimizer does not know that the call sets the function value
11233 registers we stored in the result block. We avoid problems by
11234 claiming that all hard registers are used and clobbered at this
11235 point. */
11236 emit_insn (gen_blockage ());
11237
11238 DONE;
11239 }")
11240
11241 ;; sibling call patterns
11242 (define_expand "sibcall"
11243 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11244 (match_operand 1 "" ""))
11245 (use (match_operand 2 "" ""))
11246 (use (reg:SI LR_REGNO))
11247 (return)])]
11248 ""
11249 "
11250 {
11251 #if TARGET_MACHO
11252 if (MACHOPIC_INDIRECT)
11253 operands[0] = machopic_indirect_call_target (operands[0]);
11254 #endif
11255
11256 gcc_assert (GET_CODE (operands[0]) == MEM);
11257 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11258
11259 operands[0] = XEXP (operands[0], 0);
11260 }")
11261
11262 ;; this and similar patterns must be marked as using LR, otherwise
11263 ;; dataflow will try to delete the store into it. This is true
11264 ;; even when the actual reg to jump to is in CTR, when LR was
11265 ;; saved and restored around the PIC-setting BCL.
11266 (define_insn "*sibcall_local32"
11267 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11268 (match_operand 1 "" "g,g"))
11269 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11270 (use (reg:SI LR_REGNO))
11271 (return)]
11272 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11273 "*
11274 {
11275 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11276 output_asm_insn (\"crxor 6,6,6\", operands);
11277
11278 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11279 output_asm_insn (\"creqv 6,6,6\", operands);
11280
11281 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11282 }"
11283 [(set_attr "type" "branch")
11284 (set_attr "length" "4,8")])
11285
11286 (define_insn "*sibcall_local64"
11287 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11288 (match_operand 1 "" "g,g"))
11289 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11290 (use (reg:SI LR_REGNO))
11291 (return)]
11292 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11293 "*
11294 {
11295 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11296 output_asm_insn (\"crxor 6,6,6\", operands);
11297
11298 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11299 output_asm_insn (\"creqv 6,6,6\", operands);
11300
11301 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11302 }"
11303 [(set_attr "type" "branch")
11304 (set_attr "length" "4,8")])
11305
11306 (define_insn "*sibcall_value_local32"
11307 [(set (match_operand 0 "" "")
11308 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11309 (match_operand 2 "" "g,g")))
11310 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11311 (use (reg:SI LR_REGNO))
11312 (return)]
11313 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11314 "*
11315 {
11316 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11317 output_asm_insn (\"crxor 6,6,6\", operands);
11318
11319 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11320 output_asm_insn (\"creqv 6,6,6\", operands);
11321
11322 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11323 }"
11324 [(set_attr "type" "branch")
11325 (set_attr "length" "4,8")])
11326
11327
11328 (define_insn "*sibcall_value_local64"
11329 [(set (match_operand 0 "" "")
11330 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11331 (match_operand 2 "" "g,g")))
11332 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11333 (use (reg:SI LR_REGNO))
11334 (return)]
11335 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11336 "*
11337 {
11338 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11339 output_asm_insn (\"crxor 6,6,6\", operands);
11340
11341 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11342 output_asm_insn (\"creqv 6,6,6\", operands);
11343
11344 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11345 }"
11346 [(set_attr "type" "branch")
11347 (set_attr "length" "4,8")])
11348
11349 (define_insn "*sibcall_nonlocal_aix32"
11350 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11351 (match_operand 1 "" "g"))
11352 (use (match_operand:SI 2 "immediate_operand" "O"))
11353 (use (reg:SI LR_REGNO))
11354 (return)]
11355 "TARGET_32BIT
11356 && DEFAULT_ABI == ABI_AIX
11357 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11358 "b %z0"
11359 [(set_attr "type" "branch")
11360 (set_attr "length" "4")])
11361
11362 (define_insn "*sibcall_nonlocal_aix64"
11363 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11364 (match_operand 1 "" "g"))
11365 (use (match_operand:SI 2 "immediate_operand" "O"))
11366 (use (reg:SI LR_REGNO))
11367 (return)]
11368 "TARGET_64BIT
11369 && DEFAULT_ABI == ABI_AIX
11370 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11371 "b %z0"
11372 [(set_attr "type" "branch")
11373 (set_attr "length" "4")])
11374
11375 (define_insn "*sibcall_value_nonlocal_aix32"
11376 [(set (match_operand 0 "" "")
11377 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11378 (match_operand 2 "" "g")))
11379 (use (match_operand:SI 3 "immediate_operand" "O"))
11380 (use (reg:SI LR_REGNO))
11381 (return)]
11382 "TARGET_32BIT
11383 && DEFAULT_ABI == ABI_AIX
11384 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11385 "b %z1"
11386 [(set_attr "type" "branch")
11387 (set_attr "length" "4")])
11388
11389 (define_insn "*sibcall_value_nonlocal_aix64"
11390 [(set (match_operand 0 "" "")
11391 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11392 (match_operand 2 "" "g")))
11393 (use (match_operand:SI 3 "immediate_operand" "O"))
11394 (use (reg:SI LR_REGNO))
11395 (return)]
11396 "TARGET_64BIT
11397 && DEFAULT_ABI == ABI_AIX
11398 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11399 "b %z1"
11400 [(set_attr "type" "branch")
11401 (set_attr "length" "4")])
11402
11403 (define_insn "*sibcall_nonlocal_sysv<mode>"
11404 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11405 (match_operand 1 "" ""))
11406 (use (match_operand 2 "immediate_operand" "O,n"))
11407 (use (reg:SI LR_REGNO))
11408 (return)]
11409 "(DEFAULT_ABI == ABI_DARWIN
11410 || DEFAULT_ABI == ABI_V4)
11411 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11412 "*
11413 {
11414 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11415 output_asm_insn (\"crxor 6,6,6\", operands);
11416
11417 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11418 output_asm_insn (\"creqv 6,6,6\", operands);
11419
11420 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11421 {
11422 gcc_assert (!TARGET_SECURE_PLT);
11423 return \"b %z0@plt\";
11424 }
11425 else
11426 return \"b %z0\";
11427 }"
11428 [(set_attr "type" "branch,branch")
11429 (set_attr "length" "4,8")])
11430
11431 (define_expand "sibcall_value"
11432 [(parallel [(set (match_operand 0 "register_operand" "")
11433 (call (mem:SI (match_operand 1 "address_operand" ""))
11434 (match_operand 2 "" "")))
11435 (use (match_operand 3 "" ""))
11436 (use (reg:SI LR_REGNO))
11437 (return)])]
11438 ""
11439 "
11440 {
11441 #if TARGET_MACHO
11442 if (MACHOPIC_INDIRECT)
11443 operands[1] = machopic_indirect_call_target (operands[1]);
11444 #endif
11445
11446 gcc_assert (GET_CODE (operands[1]) == MEM);
11447 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11448
11449 operands[1] = XEXP (operands[1], 0);
11450 }")
11451
11452 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
11453 [(set (match_operand 0 "" "")
11454 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11455 (match_operand 2 "" "")))
11456 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11457 (use (reg:SI LR_REGNO))
11458 (return)]
11459 "(DEFAULT_ABI == ABI_DARWIN
11460 || DEFAULT_ABI == ABI_V4)
11461 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11462 "*
11463 {
11464 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11465 output_asm_insn (\"crxor 6,6,6\", operands);
11466
11467 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11468 output_asm_insn (\"creqv 6,6,6\", operands);
11469
11470 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11471 {
11472 gcc_assert (!TARGET_SECURE_PLT);
11473 return \"b %z1@plt\";
11474 }
11475 else
11476 return \"b %z1\";
11477 }"
11478 [(set_attr "type" "branch,branch")
11479 (set_attr "length" "4,8")])
11480
11481 (define_expand "sibcall_epilogue"
11482 [(use (const_int 0))]
11483 "TARGET_SCHED_PROLOG"
11484 "
11485 {
11486 rs6000_emit_epilogue (TRUE);
11487 DONE;
11488 }")
11489
11490 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11491 ;; all of memory. This blocks insns from being moved across this point.
11492
11493 (define_insn "blockage"
11494 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
11495 ""
11496 "")
11497 \f
11498 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
11499 ;; signed & unsigned, and one type of branch.
11500 ;;
11501 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11502 ;; insns, and branches. We store the operands of compares until we see
11503 ;; how it is used.
11504 (define_expand "cmp<mode>"
11505 [(set (cc0)
11506 (compare (match_operand:GPR 0 "gpc_reg_operand" "")
11507 (match_operand:GPR 1 "reg_or_short_operand" "")))]
11508 ""
11509 "
11510 {
11511 /* Take care of the possibility that operands[1] might be negative but
11512 this might be a logical operation. That insn doesn't exist. */
11513 if (GET_CODE (operands[1]) == CONST_INT
11514 && INTVAL (operands[1]) < 0)
11515 operands[1] = force_reg (<MODE>mode, operands[1]);
11516
11517 rs6000_compare_op0 = operands[0];
11518 rs6000_compare_op1 = operands[1];
11519 rs6000_compare_fp_p = 0;
11520 DONE;
11521 }")
11522
11523 (define_expand "cmp<mode>"
11524 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
11525 (match_operand:FP 1 "gpc_reg_operand" "")))]
11526 ""
11527 "
11528 {
11529 rs6000_compare_op0 = operands[0];
11530 rs6000_compare_op1 = operands[1];
11531 rs6000_compare_fp_p = 1;
11532 DONE;
11533 }")
11534
11535 (define_expand "beq"
11536 [(use (match_operand 0 "" ""))]
11537 ""
11538 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
11539
11540 (define_expand "bne"
11541 [(use (match_operand 0 "" ""))]
11542 ""
11543 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
11544
11545 (define_expand "bge"
11546 [(use (match_operand 0 "" ""))]
11547 ""
11548 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
11549
11550 (define_expand "bgt"
11551 [(use (match_operand 0 "" ""))]
11552 ""
11553 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
11554
11555 (define_expand "ble"
11556 [(use (match_operand 0 "" ""))]
11557 ""
11558 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
11559
11560 (define_expand "blt"
11561 [(use (match_operand 0 "" ""))]
11562 ""
11563 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
11564
11565 (define_expand "bgeu"
11566 [(use (match_operand 0 "" ""))]
11567 ""
11568 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
11569
11570 (define_expand "bgtu"
11571 [(use (match_operand 0 "" ""))]
11572 ""
11573 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
11574
11575 (define_expand "bleu"
11576 [(use (match_operand 0 "" ""))]
11577 ""
11578 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
11579
11580 (define_expand "bltu"
11581 [(use (match_operand 0 "" ""))]
11582 ""
11583 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
11584
11585 (define_expand "bunordered"
11586 [(use (match_operand 0 "" ""))]
11587 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11588 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
11589
11590 (define_expand "bordered"
11591 [(use (match_operand 0 "" ""))]
11592 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11593 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
11594
11595 (define_expand "buneq"
11596 [(use (match_operand 0 "" ""))]
11597 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11598 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
11599
11600 (define_expand "bunge"
11601 [(use (match_operand 0 "" ""))]
11602 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11603 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
11604
11605 (define_expand "bungt"
11606 [(use (match_operand 0 "" ""))]
11607 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11608 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
11609
11610 (define_expand "bunle"
11611 [(use (match_operand 0 "" ""))]
11612 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11613 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
11614
11615 (define_expand "bunlt"
11616 [(use (match_operand 0 "" ""))]
11617 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11618 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
11619
11620 (define_expand "bltgt"
11621 [(use (match_operand 0 "" ""))]
11622 ""
11623 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
11624
11625 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11626 ;; For SEQ, likewise, except that comparisons with zero should be done
11627 ;; with an scc insns. However, due to the order that combine see the
11628 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11629 ;; the cases we don't want to handle.
11630 (define_expand "seq"
11631 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11632 ""
11633 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
11634
11635 (define_expand "sne"
11636 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11637 ""
11638 "
11639 {
11640 if (! rs6000_compare_fp_p)
11641 FAIL;
11642
11643 rs6000_emit_sCOND (NE, operands[0]);
11644 DONE;
11645 }")
11646
11647 ;; A >= 0 is best done the portable way for A an integer.
11648 (define_expand "sge"
11649 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11650 ""
11651 "
11652 {
11653 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11654 FAIL;
11655
11656 rs6000_emit_sCOND (GE, operands[0]);
11657 DONE;
11658 }")
11659
11660 ;; A > 0 is best done using the portable sequence, so fail in that case.
11661 (define_expand "sgt"
11662 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11663 ""
11664 "
11665 {
11666 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11667 FAIL;
11668
11669 rs6000_emit_sCOND (GT, operands[0]);
11670 DONE;
11671 }")
11672
11673 ;; A <= 0 is best done the portable way for A an integer.
11674 (define_expand "sle"
11675 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11676 ""
11677 "
11678 {
11679 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11680 FAIL;
11681
11682 rs6000_emit_sCOND (LE, operands[0]);
11683 DONE;
11684 }")
11685
11686 ;; A < 0 is best done in the portable way for A an integer.
11687 (define_expand "slt"
11688 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11689 ""
11690 "
11691 {
11692 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11693 FAIL;
11694
11695 rs6000_emit_sCOND (LT, operands[0]);
11696 DONE;
11697 }")
11698
11699 (define_expand "sgeu"
11700 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11701 ""
11702 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11703
11704 (define_expand "sgtu"
11705 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11706 ""
11707 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
11708
11709 (define_expand "sleu"
11710 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11711 ""
11712 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11713
11714 (define_expand "sltu"
11715 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11716 ""
11717 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
11718
11719 (define_expand "sunordered"
11720 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11721 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11722 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
11723
11724 (define_expand "sordered"
11725 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11726 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11727 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11728
11729 (define_expand "suneq"
11730 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11731 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11732 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11733
11734 (define_expand "sunge"
11735 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11736 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11737 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11738
11739 (define_expand "sungt"
11740 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11741 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11742 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11743
11744 (define_expand "sunle"
11745 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11746 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11747 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11748
11749 (define_expand "sunlt"
11750 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11751 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11752 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11753
11754 (define_expand "sltgt"
11755 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11756 ""
11757 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11758
11759 (define_expand "stack_protect_set"
11760 [(match_operand 0 "memory_operand" "")
11761 (match_operand 1 "memory_operand" "")]
11762 ""
11763 {
11764 #ifdef TARGET_THREAD_SSP_OFFSET
11765 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11766 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11767 operands[1] = gen_rtx_MEM (Pmode, addr);
11768 #endif
11769 if (TARGET_64BIT)
11770 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11771 else
11772 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11773 DONE;
11774 })
11775
11776 (define_insn "stack_protect_setsi"
11777 [(set (match_operand:SI 0 "memory_operand" "=m")
11778 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11779 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11780 "TARGET_32BIT"
11781 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
11782 [(set_attr "type" "three")
11783 (set_attr "length" "12")])
11784
11785 (define_insn "stack_protect_setdi"
11786 [(set (match_operand:DI 0 "memory_operand" "=m")
11787 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11788 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11789 "TARGET_64BIT"
11790 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
11791 [(set_attr "type" "three")
11792 (set_attr "length" "12")])
11793
11794 (define_expand "stack_protect_test"
11795 [(match_operand 0 "memory_operand" "")
11796 (match_operand 1 "memory_operand" "")
11797 (match_operand 2 "" "")]
11798 ""
11799 {
11800 #ifdef TARGET_THREAD_SSP_OFFSET
11801 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11802 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11803 operands[1] = gen_rtx_MEM (Pmode, addr);
11804 #endif
11805 rs6000_compare_op0 = operands[0];
11806 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
11807 UNSPEC_SP_TEST);
11808 rs6000_compare_fp_p = 0;
11809 emit_jump_insn (gen_beq (operands[2]));
11810 DONE;
11811 })
11812
11813 (define_insn "stack_protect_testsi"
11814 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11815 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11816 (match_operand:SI 2 "memory_operand" "m,m")]
11817 UNSPEC_SP_TEST))
11818 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11819 (clobber (match_scratch:SI 3 "=&r,&r"))]
11820 "TARGET_32BIT"
11821 "@
11822 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11823 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11824 [(set_attr "length" "16,20")])
11825
11826 (define_insn "stack_protect_testdi"
11827 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11828 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
11829 (match_operand:DI 2 "memory_operand" "m,m")]
11830 UNSPEC_SP_TEST))
11831 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11832 (clobber (match_scratch:DI 3 "=&r,&r"))]
11833 "TARGET_64BIT"
11834 "@
11835 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11836 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11837 [(set_attr "length" "16,20")])
11838
11839 \f
11840 ;; Here are the actual compare insns.
11841 (define_insn "*cmp<mode>_internal1"
11842 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11843 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11844 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
11845 ""
11846 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
11847 [(set_attr "type" "cmp")])
11848
11849 ;; If we are comparing a register for equality with a large constant,
11850 ;; we can do this with an XOR followed by a compare. But this is profitable
11851 ;; only if the large constant is only used for the comparison (and in this
11852 ;; case we already have a register to reuse as scratch).
11853 ;;
11854 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11855 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
11856
11857 (define_peephole2
11858 [(set (match_operand:SI 0 "register_operand")
11859 (match_operand:SI 1 "logical_const_operand" ""))
11860 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
11861 [(match_dup 0)
11862 (match_operand:SI 2 "logical_const_operand" "")]))
11863 (set (match_operand:CC 4 "cc_reg_operand" "")
11864 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
11865 (match_dup 0)))
11866 (set (pc)
11867 (if_then_else (match_operator 6 "equality_operator"
11868 [(match_dup 4) (const_int 0)])
11869 (match_operand 7 "" "")
11870 (match_operand 8 "" "")))]
11871 "peep2_reg_dead_p (3, operands[0])
11872 && peep2_reg_dead_p (4, operands[4])"
11873 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
11874 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11875 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11876
11877 {
11878 /* Get the constant we are comparing against, and see what it looks like
11879 when sign-extended from 16 to 32 bits. Then see what constant we could
11880 XOR with SEXTC to get the sign-extended value. */
11881 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
11882 SImode,
11883 operands[1], operands[2]);
11884 HOST_WIDE_INT c = INTVAL (cnst);
11885 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11886 HOST_WIDE_INT xorv = c ^ sextc;
11887
11888 operands[9] = GEN_INT (xorv);
11889 operands[10] = GEN_INT (sextc);
11890 })
11891
11892 (define_insn "*cmpsi_internal2"
11893 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11894 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11895 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11896 ""
11897 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
11898 [(set_attr "type" "cmp")])
11899
11900 (define_insn "*cmpdi_internal2"
11901 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11902 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11903 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11904 ""
11905 "cmpld%I2 %0,%1,%b2"
11906 [(set_attr "type" "cmp")])
11907
11908 ;; The following two insns don't exist as single insns, but if we provide
11909 ;; them, we can swap an add and compare, which will enable us to overlap more
11910 ;; of the required delay between a compare and branch. We generate code for
11911 ;; them by splitting.
11912
11913 (define_insn ""
11914 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11915 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11916 (match_operand:SI 2 "short_cint_operand" "i")))
11917 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11918 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11919 ""
11920 "#"
11921 [(set_attr "length" "8")])
11922
11923 (define_insn ""
11924 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11925 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11926 (match_operand:SI 2 "u_short_cint_operand" "i")))
11927 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11928 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11929 ""
11930 "#"
11931 [(set_attr "length" "8")])
11932
11933 (define_split
11934 [(set (match_operand:CC 3 "cc_reg_operand" "")
11935 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11936 (match_operand:SI 2 "short_cint_operand" "")))
11937 (set (match_operand:SI 0 "gpc_reg_operand" "")
11938 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11939 ""
11940 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11941 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11942
11943 (define_split
11944 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11945 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11946 (match_operand:SI 2 "u_short_cint_operand" "")))
11947 (set (match_operand:SI 0 "gpc_reg_operand" "")
11948 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11949 ""
11950 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11951 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11952
11953 (define_insn "*cmpsf_internal1"
11954 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11955 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11956 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11957 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
11958 "fcmpu %0,%1,%2"
11959 [(set_attr "type" "fpcompare")])
11960
11961 (define_insn "*cmpdf_internal1"
11962 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11963 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11964 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11965 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
11966 "fcmpu %0,%1,%2"
11967 [(set_attr "type" "fpcompare")])
11968
11969 ;; Only need to compare second words if first words equal
11970 (define_insn "*cmptf_internal1"
11971 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11972 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11973 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11974 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
11975 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
11976 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11977 [(set_attr "type" "fpcompare")
11978 (set_attr "length" "12")])
11979
11980 (define_insn_and_split "*cmptf_internal2"
11981 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11982 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11983 (match_operand:TF 2 "gpc_reg_operand" "f")))
11984 (clobber (match_scratch:DF 3 "=f"))
11985 (clobber (match_scratch:DF 4 "=f"))
11986 (clobber (match_scratch:DF 5 "=f"))
11987 (clobber (match_scratch:DF 6 "=f"))
11988 (clobber (match_scratch:DF 7 "=f"))
11989 (clobber (match_scratch:DF 8 "=f"))
11990 (clobber (match_scratch:DF 9 "=f"))
11991 (clobber (match_scratch:DF 10 "=f"))]
11992 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
11993 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
11994 "#"
11995 "&& reload_completed"
11996 [(set (match_dup 3) (match_dup 13))
11997 (set (match_dup 4) (match_dup 14))
11998 (set (match_dup 9) (abs:DF (match_dup 5)))
11999 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
12000 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
12001 (label_ref (match_dup 11))
12002 (pc)))
12003 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
12004 (set (pc) (label_ref (match_dup 12)))
12005 (match_dup 11)
12006 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
12007 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
12008 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
12009 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
12010 (match_dup 12)]
12011 {
12012 REAL_VALUE_TYPE rv;
12013 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
12014 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
12015
12016 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
12017 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
12018 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
12019 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
12020 operands[11] = gen_label_rtx ();
12021 operands[12] = gen_label_rtx ();
12022 real_inf (&rv);
12023 operands[13] = force_const_mem (DFmode,
12024 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
12025 operands[14] = force_const_mem (DFmode,
12026 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
12027 DFmode));
12028 if (TARGET_TOC)
12029 {
12030 operands[13] = gen_const_mem (DFmode,
12031 create_TOC_reference (XEXP (operands[13], 0)));
12032 operands[14] = gen_const_mem (DFmode,
12033 create_TOC_reference (XEXP (operands[14], 0)));
12034 set_mem_alias_set (operands[13], get_TOC_alias_set ());
12035 set_mem_alias_set (operands[14], get_TOC_alias_set ());
12036 }
12037 })
12038 \f
12039 ;; Now we have the scc insns. We can do some combinations because of the
12040 ;; way the machine works.
12041 ;;
12042 ;; Note that this is probably faster if we can put an insn between the
12043 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
12044 ;; cases the insns below which don't use an intermediate CR field will
12045 ;; be used instead.
12046 (define_insn ""
12047 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12048 (match_operator:SI 1 "scc_comparison_operator"
12049 [(match_operand 2 "cc_reg_operand" "y")
12050 (const_int 0)]))]
12051 ""
12052 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12053 [(set (attr "type")
12054 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12055 (const_string "mfcrf")
12056 ]
12057 (const_string "mfcr")))
12058 (set_attr "length" "8")])
12059
12060 ;; Same as above, but get the GT bit.
12061 (define_insn "move_from_CR_gt_bit"
12062 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12063 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
12064 "TARGET_E500"
12065 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
12066 [(set_attr "type" "mfcr")
12067 (set_attr "length" "8")])
12068
12069 ;; Same as above, but get the OV/ORDERED bit.
12070 (define_insn "move_from_CR_ov_bit"
12071 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12072 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
12073 "TARGET_ISEL"
12074 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
12075 [(set_attr "type" "mfcr")
12076 (set_attr "length" "8")])
12077
12078 (define_insn ""
12079 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12080 (match_operator:DI 1 "scc_comparison_operator"
12081 [(match_operand 2 "cc_reg_operand" "y")
12082 (const_int 0)]))]
12083 "TARGET_POWERPC64"
12084 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12085 [(set (attr "type")
12086 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12087 (const_string "mfcrf")
12088 ]
12089 (const_string "mfcr")))
12090 (set_attr "length" "8")])
12091
12092 (define_insn ""
12093 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12094 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12095 [(match_operand 2 "cc_reg_operand" "y,y")
12096 (const_int 0)])
12097 (const_int 0)))
12098 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
12099 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12100 "TARGET_32BIT"
12101 "@
12102 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
12103 #"
12104 [(set_attr "type" "delayed_compare")
12105 (set_attr "length" "8,16")])
12106
12107 (define_split
12108 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12109 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12110 [(match_operand 2 "cc_reg_operand" "")
12111 (const_int 0)])
12112 (const_int 0)))
12113 (set (match_operand:SI 3 "gpc_reg_operand" "")
12114 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12115 "TARGET_32BIT && reload_completed"
12116 [(set (match_dup 3)
12117 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12118 (set (match_dup 0)
12119 (compare:CC (match_dup 3)
12120 (const_int 0)))]
12121 "")
12122
12123 (define_insn ""
12124 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12125 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12126 [(match_operand 2 "cc_reg_operand" "y")
12127 (const_int 0)])
12128 (match_operand:SI 3 "const_int_operand" "n")))]
12129 ""
12130 "*
12131 {
12132 int is_bit = ccr_bit (operands[1], 1);
12133 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12134 int count;
12135
12136 if (is_bit >= put_bit)
12137 count = is_bit - put_bit;
12138 else
12139 count = 32 - (put_bit - is_bit);
12140
12141 operands[4] = GEN_INT (count);
12142 operands[5] = GEN_INT (put_bit);
12143
12144 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
12145 }"
12146 [(set (attr "type")
12147 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12148 (const_string "mfcrf")
12149 ]
12150 (const_string "mfcr")))
12151 (set_attr "length" "8")])
12152
12153 (define_insn ""
12154 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12155 (compare:CC
12156 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12157 [(match_operand 2 "cc_reg_operand" "y,y")
12158 (const_int 0)])
12159 (match_operand:SI 3 "const_int_operand" "n,n"))
12160 (const_int 0)))
12161 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
12162 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12163 (match_dup 3)))]
12164 ""
12165 "*
12166 {
12167 int is_bit = ccr_bit (operands[1], 1);
12168 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12169 int count;
12170
12171 /* Force split for non-cc0 compare. */
12172 if (which_alternative == 1)
12173 return \"#\";
12174
12175 if (is_bit >= put_bit)
12176 count = is_bit - put_bit;
12177 else
12178 count = 32 - (put_bit - is_bit);
12179
12180 operands[5] = GEN_INT (count);
12181 operands[6] = GEN_INT (put_bit);
12182
12183 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
12184 }"
12185 [(set_attr "type" "delayed_compare")
12186 (set_attr "length" "8,16")])
12187
12188 (define_split
12189 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12190 (compare:CC
12191 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12192 [(match_operand 2 "cc_reg_operand" "")
12193 (const_int 0)])
12194 (match_operand:SI 3 "const_int_operand" ""))
12195 (const_int 0)))
12196 (set (match_operand:SI 4 "gpc_reg_operand" "")
12197 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12198 (match_dup 3)))]
12199 "reload_completed"
12200 [(set (match_dup 4)
12201 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12202 (match_dup 3)))
12203 (set (match_dup 0)
12204 (compare:CC (match_dup 4)
12205 (const_int 0)))]
12206 "")
12207
12208 ;; There is a 3 cycle delay between consecutive mfcr instructions
12209 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
12210
12211 (define_peephole
12212 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12213 (match_operator:SI 1 "scc_comparison_operator"
12214 [(match_operand 2 "cc_reg_operand" "y")
12215 (const_int 0)]))
12216 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
12217 (match_operator:SI 4 "scc_comparison_operator"
12218 [(match_operand 5 "cc_reg_operand" "y")
12219 (const_int 0)]))]
12220 "REGNO (operands[2]) != REGNO (operands[5])"
12221 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
12222 [(set_attr "type" "mfcr")
12223 (set_attr "length" "12")])
12224
12225 (define_peephole
12226 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12227 (match_operator:DI 1 "scc_comparison_operator"
12228 [(match_operand 2 "cc_reg_operand" "y")
12229 (const_int 0)]))
12230 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12231 (match_operator:DI 4 "scc_comparison_operator"
12232 [(match_operand 5 "cc_reg_operand" "y")
12233 (const_int 0)]))]
12234 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
12235 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
12236 [(set_attr "type" "mfcr")
12237 (set_attr "length" "12")])
12238
12239 ;; There are some scc insns that can be done directly, without a compare.
12240 ;; These are faster because they don't involve the communications between
12241 ;; the FXU and branch units. In fact, we will be replacing all of the
12242 ;; integer scc insns here or in the portable methods in emit_store_flag.
12243 ;;
12244 ;; Also support (neg (scc ..)) since that construct is used to replace
12245 ;; branches, (plus (scc ..) ..) since that construct is common and
12246 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12247 ;; cases where it is no more expensive than (neg (scc ..)).
12248
12249 ;; Have reload force a constant into a register for the simple insns that
12250 ;; otherwise won't accept constants. We do this because it is faster than
12251 ;; the cmp/mfcr sequence we would otherwise generate.
12252
12253 (define_mode_attr scc_eq_op2 [(SI "rKLI")
12254 (DI "rKJI")])
12255
12256 (define_insn_and_split "*eq<mode>"
12257 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12258 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
12259 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
12260 "!TARGET_POWER"
12261 "#"
12262 "!TARGET_POWER"
12263 [(set (match_dup 0)
12264 (clz:GPR (match_dup 3)))
12265 (set (match_dup 0)
12266 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
12267 {
12268 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12269 {
12270 /* Use output operand as intermediate. */
12271 operands[3] = operands[0];
12272
12273 if (logical_operand (operands[2], <MODE>mode))
12274 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12275 gen_rtx_XOR (<MODE>mode,
12276 operands[1], operands[2])));
12277 else
12278 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12279 gen_rtx_PLUS (<MODE>mode, operands[1],
12280 negate_rtx (<MODE>mode,
12281 operands[2]))));
12282 }
12283 else
12284 operands[3] = operands[1];
12285
12286 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12287 })
12288
12289 (define_insn_and_split "*eq<mode>_compare"
12290 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12291 (compare:CC
12292 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12293 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
12294 (const_int 0)))
12295 (set (match_operand:P 0 "gpc_reg_operand" "=r")
12296 (eq:P (match_dup 1) (match_dup 2)))]
12297 "!TARGET_POWER && optimize_size"
12298 "#"
12299 "!TARGET_POWER && optimize_size"
12300 [(set (match_dup 0)
12301 (clz:P (match_dup 4)))
12302 (parallel [(set (match_dup 3)
12303 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
12304 (const_int 0)))
12305 (set (match_dup 0)
12306 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
12307 {
12308 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12309 {
12310 /* Use output operand as intermediate. */
12311 operands[4] = operands[0];
12312
12313 if (logical_operand (operands[2], <MODE>mode))
12314 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12315 gen_rtx_XOR (<MODE>mode,
12316 operands[1], operands[2])));
12317 else
12318 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12319 gen_rtx_PLUS (<MODE>mode, operands[1],
12320 negate_rtx (<MODE>mode,
12321 operands[2]))));
12322 }
12323 else
12324 operands[4] = operands[1];
12325
12326 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12327 })
12328
12329 (define_insn "*eqsi_power"
12330 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
12331 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12332 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
12333 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
12334 "TARGET_POWER"
12335 "@
12336 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12337 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
12338 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12339 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12340 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
12341 [(set_attr "type" "three,two,three,three,three")
12342 (set_attr "length" "12,8,12,12,12")])
12343
12344 ;; We have insns of the form shown by the first define_insn below. If
12345 ;; there is something inside the comparison operation, we must split it.
12346 (define_split
12347 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12348 (plus:SI (match_operator 1 "comparison_operator"
12349 [(match_operand:SI 2 "" "")
12350 (match_operand:SI 3
12351 "reg_or_cint_operand" "")])
12352 (match_operand:SI 4 "gpc_reg_operand" "")))
12353 (clobber (match_operand:SI 5 "register_operand" ""))]
12354 "! gpc_reg_operand (operands[2], SImode)"
12355 [(set (match_dup 5) (match_dup 2))
12356 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
12357 (match_dup 4)))])
12358
12359 (define_insn "*plus_eqsi"
12360 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
12361 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12362 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
12363 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
12364 "TARGET_32BIT"
12365 "@
12366 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12367 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
12368 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12369 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12370 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12371 [(set_attr "type" "three,two,three,three,three")
12372 (set_attr "length" "12,8,12,12,12")])
12373
12374 (define_insn "*compare_plus_eqsi"
12375 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12376 (compare:CC
12377 (plus:SI
12378 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12379 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12380 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12381 (const_int 0)))
12382 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
12383 "TARGET_32BIT && optimize_size"
12384 "@
12385 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12386 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
12387 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12388 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12389 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12390 #
12391 #
12392 #
12393 #
12394 #"
12395 [(set_attr "type" "compare")
12396 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12397
12398 (define_split
12399 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12400 (compare:CC
12401 (plus:SI
12402 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12403 (match_operand:SI 2 "scc_eq_operand" ""))
12404 (match_operand:SI 3 "gpc_reg_operand" ""))
12405 (const_int 0)))
12406 (clobber (match_scratch:SI 4 ""))]
12407 "TARGET_32BIT && optimize_size && reload_completed"
12408 [(set (match_dup 4)
12409 (plus:SI (eq:SI (match_dup 1)
12410 (match_dup 2))
12411 (match_dup 3)))
12412 (set (match_dup 0)
12413 (compare:CC (match_dup 4)
12414 (const_int 0)))]
12415 "")
12416
12417 (define_insn "*plus_eqsi_compare"
12418 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12419 (compare:CC
12420 (plus:SI
12421 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12422 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12423 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12424 (const_int 0)))
12425 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12426 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12427 "TARGET_32BIT && optimize_size"
12428 "@
12429 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12430 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
12431 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12432 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12433 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12434 #
12435 #
12436 #
12437 #
12438 #"
12439 [(set_attr "type" "compare")
12440 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12441
12442 (define_split
12443 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12444 (compare:CC
12445 (plus:SI
12446 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12447 (match_operand:SI 2 "scc_eq_operand" ""))
12448 (match_operand:SI 3 "gpc_reg_operand" ""))
12449 (const_int 0)))
12450 (set (match_operand:SI 0 "gpc_reg_operand" "")
12451 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12452 "TARGET_32BIT && optimize_size && reload_completed"
12453 [(set (match_dup 0)
12454 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12455 (set (match_dup 4)
12456 (compare:CC (match_dup 0)
12457 (const_int 0)))]
12458 "")
12459
12460 (define_insn "*neg_eq0<mode>"
12461 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12462 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12463 (const_int 0))))]
12464 ""
12465 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
12466 [(set_attr "type" "two")
12467 (set_attr "length" "8")])
12468
12469 (define_insn_and_split "*neg_eq<mode>"
12470 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12471 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12472 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
12473 ""
12474 "#"
12475 ""
12476 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12477 {
12478 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12479 {
12480 /* Use output operand as intermediate. */
12481 operands[3] = operands[0];
12482
12483 if (logical_operand (operands[2], <MODE>mode))
12484 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12485 gen_rtx_XOR (<MODE>mode,
12486 operands[1], operands[2])));
12487 else
12488 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12489 gen_rtx_PLUS (<MODE>mode, operands[1],
12490 negate_rtx (<MODE>mode,
12491 operands[2]))));
12492 }
12493 else
12494 operands[3] = operands[1];
12495 })
12496
12497 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
12498 ;; since it nabs/sr is just as fast.
12499 (define_insn "*ne0si"
12500 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12501 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12502 (const_int 31)))
12503 (clobber (match_scratch:SI 2 "=&r"))]
12504 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
12505 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
12506 [(set_attr "type" "two")
12507 (set_attr "length" "8")])
12508
12509 (define_insn "*ne0di"
12510 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12511 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12512 (const_int 63)))
12513 (clobber (match_scratch:DI 2 "=&r"))]
12514 "TARGET_64BIT"
12515 "addic %2,%1,-1\;subfe %0,%2,%1"
12516 [(set_attr "type" "two")
12517 (set_attr "length" "8")])
12518
12519 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
12520 (define_insn "*plus_ne0si"
12521 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12522 (plus:SI (lshiftrt:SI
12523 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12524 (const_int 31))
12525 (match_operand:SI 2 "gpc_reg_operand" "r")))
12526 (clobber (match_scratch:SI 3 "=&r"))]
12527 "TARGET_32BIT"
12528 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
12529 [(set_attr "type" "two")
12530 (set_attr "length" "8")])
12531
12532 (define_insn "*plus_ne0di"
12533 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12534 (plus:DI (lshiftrt:DI
12535 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12536 (const_int 63))
12537 (match_operand:DI 2 "gpc_reg_operand" "r")))
12538 (clobber (match_scratch:DI 3 "=&r"))]
12539 "TARGET_64BIT"
12540 "addic %3,%1,-1\;addze %0,%2"
12541 [(set_attr "type" "two")
12542 (set_attr "length" "8")])
12543
12544 (define_insn "*compare_plus_ne0si"
12545 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12546 (compare:CC
12547 (plus:SI (lshiftrt:SI
12548 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12549 (const_int 31))
12550 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12551 (const_int 0)))
12552 (clobber (match_scratch:SI 3 "=&r,&r"))
12553 (clobber (match_scratch:SI 4 "=X,&r"))]
12554 "TARGET_32BIT"
12555 "@
12556 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
12557 #"
12558 [(set_attr "type" "compare")
12559 (set_attr "length" "8,12")])
12560
12561 (define_split
12562 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12563 (compare:CC
12564 (plus:SI (lshiftrt:SI
12565 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12566 (const_int 31))
12567 (match_operand:SI 2 "gpc_reg_operand" ""))
12568 (const_int 0)))
12569 (clobber (match_scratch:SI 3 ""))
12570 (clobber (match_scratch:SI 4 ""))]
12571 "TARGET_32BIT && reload_completed"
12572 [(parallel [(set (match_dup 3)
12573 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
12574 (const_int 31))
12575 (match_dup 2)))
12576 (clobber (match_dup 4))])
12577 (set (match_dup 0)
12578 (compare:CC (match_dup 3)
12579 (const_int 0)))]
12580 "")
12581
12582 (define_insn "*compare_plus_ne0di"
12583 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12584 (compare:CC
12585 (plus:DI (lshiftrt:DI
12586 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12587 (const_int 63))
12588 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12589 (const_int 0)))
12590 (clobber (match_scratch:DI 3 "=&r,&r"))]
12591 "TARGET_64BIT"
12592 "@
12593 addic %3,%1,-1\;addze. %3,%2
12594 #"
12595 [(set_attr "type" "compare")
12596 (set_attr "length" "8,12")])
12597
12598 (define_split
12599 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12600 (compare:CC
12601 (plus:DI (lshiftrt:DI
12602 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12603 (const_int 63))
12604 (match_operand:DI 2 "gpc_reg_operand" ""))
12605 (const_int 0)))
12606 (clobber (match_scratch:DI 3 ""))]
12607 "TARGET_64BIT && reload_completed"
12608 [(set (match_dup 3)
12609 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12610 (const_int 63))
12611 (match_dup 2)))
12612 (set (match_dup 0)
12613 (compare:CC (match_dup 3)
12614 (const_int 0)))]
12615 "")
12616
12617 (define_insn "*plus_ne0si_compare"
12618 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12619 (compare:CC
12620 (plus:SI (lshiftrt:SI
12621 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12622 (const_int 31))
12623 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12624 (const_int 0)))
12625 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12626 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12627 (match_dup 2)))
12628 (clobber (match_scratch:SI 3 "=&r,&r"))]
12629 "TARGET_32BIT"
12630 "@
12631 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
12632 #"
12633 [(set_attr "type" "compare")
12634 (set_attr "length" "8,12")])
12635
12636 (define_split
12637 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12638 (compare:CC
12639 (plus:SI (lshiftrt:SI
12640 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12641 (const_int 31))
12642 (match_operand:SI 2 "gpc_reg_operand" ""))
12643 (const_int 0)))
12644 (set (match_operand:SI 0 "gpc_reg_operand" "")
12645 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12646 (match_dup 2)))
12647 (clobber (match_scratch:SI 3 ""))]
12648 "TARGET_32BIT && reload_completed"
12649 [(parallel [(set (match_dup 0)
12650 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12651 (match_dup 2)))
12652 (clobber (match_dup 3))])
12653 (set (match_dup 4)
12654 (compare:CC (match_dup 0)
12655 (const_int 0)))]
12656 "")
12657
12658 (define_insn "*plus_ne0di_compare"
12659 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12660 (compare:CC
12661 (plus:DI (lshiftrt:DI
12662 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12663 (const_int 63))
12664 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12665 (const_int 0)))
12666 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12667 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12668 (match_dup 2)))
12669 (clobber (match_scratch:DI 3 "=&r,&r"))]
12670 "TARGET_64BIT"
12671 "@
12672 addic %3,%1,-1\;addze. %0,%2
12673 #"
12674 [(set_attr "type" "compare")
12675 (set_attr "length" "8,12")])
12676
12677 (define_split
12678 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12679 (compare:CC
12680 (plus:DI (lshiftrt:DI
12681 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12682 (const_int 63))
12683 (match_operand:DI 2 "gpc_reg_operand" ""))
12684 (const_int 0)))
12685 (set (match_operand:DI 0 "gpc_reg_operand" "")
12686 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12687 (match_dup 2)))
12688 (clobber (match_scratch:DI 3 ""))]
12689 "TARGET_64BIT && reload_completed"
12690 [(parallel [(set (match_dup 0)
12691 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12692 (match_dup 2)))
12693 (clobber (match_dup 3))])
12694 (set (match_dup 4)
12695 (compare:CC (match_dup 0)
12696 (const_int 0)))]
12697 "")
12698
12699 (define_insn ""
12700 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12701 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12702 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12703 (clobber (match_scratch:SI 3 "=r,X"))]
12704 "TARGET_POWER"
12705 "@
12706 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
12707 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
12708 [(set_attr "length" "12")])
12709
12710 (define_insn ""
12711 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12712 (compare:CC
12713 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12714 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12715 (const_int 0)))
12716 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12717 (le:SI (match_dup 1) (match_dup 2)))
12718 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
12719 "TARGET_POWER"
12720 "@
12721 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12722 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
12723 #
12724 #"
12725 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
12726 (set_attr "length" "12,12,16,16")])
12727
12728 (define_split
12729 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12730 (compare:CC
12731 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12732 (match_operand:SI 2 "reg_or_short_operand" ""))
12733 (const_int 0)))
12734 (set (match_operand:SI 0 "gpc_reg_operand" "")
12735 (le:SI (match_dup 1) (match_dup 2)))
12736 (clobber (match_scratch:SI 3 ""))]
12737 "TARGET_POWER && reload_completed"
12738 [(parallel [(set (match_dup 0)
12739 (le:SI (match_dup 1) (match_dup 2)))
12740 (clobber (match_dup 3))])
12741 (set (match_dup 4)
12742 (compare:CC (match_dup 0)
12743 (const_int 0)))]
12744 "")
12745
12746 (define_insn ""
12747 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12748 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12749 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
12750 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12751 "TARGET_POWER"
12752 "@
12753 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12754 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
12755 [(set_attr "length" "12")])
12756
12757 (define_insn ""
12758 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12759 (compare:CC
12760 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12761 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12762 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12763 (const_int 0)))
12764 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12765 "TARGET_POWER"
12766 "@
12767 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12768 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12769 #
12770 #"
12771 [(set_attr "type" "compare")
12772 (set_attr "length" "12,12,16,16")])
12773
12774 (define_split
12775 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12776 (compare:CC
12777 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12778 (match_operand:SI 2 "reg_or_short_operand" ""))
12779 (match_operand:SI 3 "gpc_reg_operand" ""))
12780 (const_int 0)))
12781 (clobber (match_scratch:SI 4 ""))]
12782 "TARGET_POWER && reload_completed"
12783 [(set (match_dup 4)
12784 (plus:SI (le:SI (match_dup 1) (match_dup 2))
12785 (match_dup 3)))
12786 (set (match_dup 0)
12787 (compare:CC (match_dup 4)
12788 (const_int 0)))]
12789 "")
12790
12791 (define_insn ""
12792 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12793 (compare:CC
12794 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12795 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12796 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12797 (const_int 0)))
12798 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12799 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12800 "TARGET_POWER"
12801 "@
12802 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12803 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
12804 #
12805 #"
12806 [(set_attr "type" "compare")
12807 (set_attr "length" "12,12,16,16")])
12808
12809 (define_split
12810 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12811 (compare:CC
12812 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12813 (match_operand:SI 2 "reg_or_short_operand" ""))
12814 (match_operand:SI 3 "gpc_reg_operand" ""))
12815 (const_int 0)))
12816 (set (match_operand:SI 0 "gpc_reg_operand" "")
12817 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12818 "TARGET_POWER && reload_completed"
12819 [(set (match_dup 0)
12820 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12821 (set (match_dup 4)
12822 (compare:CC (match_dup 0)
12823 (const_int 0)))]
12824 "")
12825
12826 (define_insn ""
12827 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12828 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12829 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
12830 "TARGET_POWER"
12831 "@
12832 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12833 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
12834 [(set_attr "length" "12")])
12835
12836 (define_insn "*leu<mode>"
12837 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12838 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12839 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12840 ""
12841 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12842 [(set_attr "type" "three")
12843 (set_attr "length" "12")])
12844
12845 (define_insn "*leu<mode>_compare"
12846 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12847 (compare:CC
12848 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12849 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12850 (const_int 0)))
12851 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12852 (leu:P (match_dup 1) (match_dup 2)))]
12853 ""
12854 "@
12855 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12856 #"
12857 [(set_attr "type" "compare")
12858 (set_attr "length" "12,16")])
12859
12860 (define_split
12861 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12862 (compare:CC
12863 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12864 (match_operand:P 2 "reg_or_short_operand" ""))
12865 (const_int 0)))
12866 (set (match_operand:P 0 "gpc_reg_operand" "")
12867 (leu:P (match_dup 1) (match_dup 2)))]
12868 "reload_completed"
12869 [(set (match_dup 0)
12870 (leu:P (match_dup 1) (match_dup 2)))
12871 (set (match_dup 3)
12872 (compare:CC (match_dup 0)
12873 (const_int 0)))]
12874 "")
12875
12876 (define_insn "*plus_leu<mode>"
12877 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12878 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12879 (match_operand:P 2 "reg_or_short_operand" "rI"))
12880 (match_operand:P 3 "gpc_reg_operand" "r")))]
12881 ""
12882 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12883 [(set_attr "type" "two")
12884 (set_attr "length" "8")])
12885
12886 (define_insn ""
12887 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12888 (compare:CC
12889 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12890 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12891 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12892 (const_int 0)))
12893 (clobber (match_scratch:SI 4 "=&r,&r"))]
12894 "TARGET_32BIT"
12895 "@
12896 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12897 #"
12898 [(set_attr "type" "compare")
12899 (set_attr "length" "8,12")])
12900
12901 (define_split
12902 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12903 (compare:CC
12904 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12905 (match_operand:SI 2 "reg_or_short_operand" ""))
12906 (match_operand:SI 3 "gpc_reg_operand" ""))
12907 (const_int 0)))
12908 (clobber (match_scratch:SI 4 ""))]
12909 "TARGET_32BIT && reload_completed"
12910 [(set (match_dup 4)
12911 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12912 (match_dup 3)))
12913 (set (match_dup 0)
12914 (compare:CC (match_dup 4)
12915 (const_int 0)))]
12916 "")
12917
12918 (define_insn ""
12919 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12920 (compare:CC
12921 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12922 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12923 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12924 (const_int 0)))
12925 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12926 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12927 "TARGET_32BIT"
12928 "@
12929 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12930 #"
12931 [(set_attr "type" "compare")
12932 (set_attr "length" "8,12")])
12933
12934 (define_split
12935 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12936 (compare:CC
12937 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12938 (match_operand:SI 2 "reg_or_short_operand" ""))
12939 (match_operand:SI 3 "gpc_reg_operand" ""))
12940 (const_int 0)))
12941 (set (match_operand:SI 0 "gpc_reg_operand" "")
12942 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12943 "TARGET_32BIT && reload_completed"
12944 [(set (match_dup 0)
12945 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12946 (set (match_dup 4)
12947 (compare:CC (match_dup 0)
12948 (const_int 0)))]
12949 "")
12950
12951 (define_insn "*neg_leu<mode>"
12952 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12953 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12954 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12955 ""
12956 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12957 [(set_attr "type" "three")
12958 (set_attr "length" "12")])
12959
12960 (define_insn "*and_neg_leu<mode>"
12961 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12962 (and:P (neg:P
12963 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12964 (match_operand:P 2 "reg_or_short_operand" "rI")))
12965 (match_operand:P 3 "gpc_reg_operand" "r")))]
12966 ""
12967 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12968 [(set_attr "type" "three")
12969 (set_attr "length" "12")])
12970
12971 (define_insn ""
12972 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12973 (compare:CC
12974 (and:SI (neg:SI
12975 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12976 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12977 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12978 (const_int 0)))
12979 (clobber (match_scratch:SI 4 "=&r,&r"))]
12980 "TARGET_32BIT"
12981 "@
12982 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12983 #"
12984 [(set_attr "type" "compare")
12985 (set_attr "length" "12,16")])
12986
12987 (define_split
12988 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12989 (compare:CC
12990 (and:SI (neg:SI
12991 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12992 (match_operand:SI 2 "reg_or_short_operand" "")))
12993 (match_operand:SI 3 "gpc_reg_operand" ""))
12994 (const_int 0)))
12995 (clobber (match_scratch:SI 4 ""))]
12996 "TARGET_32BIT && reload_completed"
12997 [(set (match_dup 4)
12998 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12999 (match_dup 3)))
13000 (set (match_dup 0)
13001 (compare:CC (match_dup 4)
13002 (const_int 0)))]
13003 "")
13004
13005 (define_insn ""
13006 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13007 (compare:CC
13008 (and:SI (neg:SI
13009 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13010 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13011 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13012 (const_int 0)))
13013 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13014 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13015 "TARGET_32BIT"
13016 "@
13017 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13018 #"
13019 [(set_attr "type" "compare")
13020 (set_attr "length" "12,16")])
13021
13022 (define_split
13023 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13024 (compare:CC
13025 (and:SI (neg:SI
13026 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13027 (match_operand:SI 2 "reg_or_short_operand" "")))
13028 (match_operand:SI 3 "gpc_reg_operand" ""))
13029 (const_int 0)))
13030 (set (match_operand:SI 0 "gpc_reg_operand" "")
13031 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13032 "TARGET_32BIT && reload_completed"
13033 [(set (match_dup 0)
13034 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13035 (match_dup 3)))
13036 (set (match_dup 4)
13037 (compare:CC (match_dup 0)
13038 (const_int 0)))]
13039 "")
13040
13041 (define_insn ""
13042 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13043 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13044 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13045 "TARGET_POWER"
13046 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13047 [(set_attr "length" "12")])
13048
13049 (define_insn ""
13050 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13051 (compare:CC
13052 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13053 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13054 (const_int 0)))
13055 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13056 (lt:SI (match_dup 1) (match_dup 2)))]
13057 "TARGET_POWER"
13058 "@
13059 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13060 #"
13061 [(set_attr "type" "delayed_compare")
13062 (set_attr "length" "12,16")])
13063
13064 (define_split
13065 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13066 (compare:CC
13067 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13068 (match_operand:SI 2 "reg_or_short_operand" ""))
13069 (const_int 0)))
13070 (set (match_operand:SI 0 "gpc_reg_operand" "")
13071 (lt:SI (match_dup 1) (match_dup 2)))]
13072 "TARGET_POWER && reload_completed"
13073 [(set (match_dup 0)
13074 (lt:SI (match_dup 1) (match_dup 2)))
13075 (set (match_dup 3)
13076 (compare:CC (match_dup 0)
13077 (const_int 0)))]
13078 "")
13079
13080 (define_insn ""
13081 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13082 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13083 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13084 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13085 "TARGET_POWER"
13086 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13087 [(set_attr "length" "12")])
13088
13089 (define_insn ""
13090 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13091 (compare:CC
13092 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13093 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13094 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13095 (const_int 0)))
13096 (clobber (match_scratch:SI 4 "=&r,&r"))]
13097 "TARGET_POWER"
13098 "@
13099 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13100 #"
13101 [(set_attr "type" "compare")
13102 (set_attr "length" "12,16")])
13103
13104 (define_split
13105 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13106 (compare:CC
13107 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13108 (match_operand:SI 2 "reg_or_short_operand" ""))
13109 (match_operand:SI 3 "gpc_reg_operand" ""))
13110 (const_int 0)))
13111 (clobber (match_scratch:SI 4 ""))]
13112 "TARGET_POWER && reload_completed"
13113 [(set (match_dup 4)
13114 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
13115 (match_dup 3)))
13116 (set (match_dup 0)
13117 (compare:CC (match_dup 4)
13118 (const_int 0)))]
13119 "")
13120
13121 (define_insn ""
13122 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13123 (compare:CC
13124 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13125 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13126 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13127 (const_int 0)))
13128 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13129 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13130 "TARGET_POWER"
13131 "@
13132 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13133 #"
13134 [(set_attr "type" "compare")
13135 (set_attr "length" "12,16")])
13136
13137 (define_split
13138 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13139 (compare:CC
13140 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13141 (match_operand:SI 2 "reg_or_short_operand" ""))
13142 (match_operand:SI 3 "gpc_reg_operand" ""))
13143 (const_int 0)))
13144 (set (match_operand:SI 0 "gpc_reg_operand" "")
13145 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13146 "TARGET_POWER && reload_completed"
13147 [(set (match_dup 0)
13148 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13149 (set (match_dup 4)
13150 (compare:CC (match_dup 0)
13151 (const_int 0)))]
13152 "")
13153
13154 (define_insn ""
13155 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13156 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13157 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13158 "TARGET_POWER"
13159 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13160 [(set_attr "length" "12")])
13161
13162 (define_insn_and_split "*ltu<mode>"
13163 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13164 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13165 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13166 ""
13167 "#"
13168 ""
13169 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13170 (set (match_dup 0) (neg:P (match_dup 0)))]
13171 "")
13172
13173 (define_insn_and_split "*ltu<mode>_compare"
13174 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13175 (compare:CC
13176 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13177 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13178 (const_int 0)))
13179 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13180 (ltu:P (match_dup 1) (match_dup 2)))]
13181 ""
13182 "#"
13183 ""
13184 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13185 (parallel [(set (match_dup 3)
13186 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13187 (set (match_dup 0) (neg:P (match_dup 0)))])]
13188 "")
13189
13190 (define_insn_and_split "*plus_ltu<mode>"
13191 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
13192 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13193 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13194 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
13195 ""
13196 "#"
13197 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13198 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13199 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13200 "")
13201
13202 (define_insn_and_split "*plus_ltu<mode>_compare"
13203 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13204 (compare:CC
13205 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13206 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13207 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13208 (const_int 0)))
13209 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13210 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13211 ""
13212 "#"
13213 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13214 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13215 (parallel [(set (match_dup 4)
13216 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13217 (const_int 0)))
13218 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13219 "")
13220
13221 (define_insn "*neg_ltu<mode>"
13222 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13223 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13224 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
13225 ""
13226 "@
13227 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
13228 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
13229 [(set_attr "type" "two")
13230 (set_attr "length" "8")])
13231
13232 (define_insn ""
13233 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13234 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13235 (match_operand:SI 2 "reg_or_short_operand" "rI")))
13236 (clobber (match_scratch:SI 3 "=r"))]
13237 "TARGET_POWER"
13238 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
13239 [(set_attr "length" "12")])
13240
13241 (define_insn ""
13242 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13243 (compare:CC
13244 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13245 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13246 (const_int 0)))
13247 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13248 (ge:SI (match_dup 1) (match_dup 2)))
13249 (clobber (match_scratch:SI 3 "=r,r"))]
13250 "TARGET_POWER"
13251 "@
13252 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13253 #"
13254 [(set_attr "type" "compare")
13255 (set_attr "length" "12,16")])
13256
13257 (define_split
13258 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13259 (compare:CC
13260 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13261 (match_operand:SI 2 "reg_or_short_operand" ""))
13262 (const_int 0)))
13263 (set (match_operand:SI 0 "gpc_reg_operand" "")
13264 (ge:SI (match_dup 1) (match_dup 2)))
13265 (clobber (match_scratch:SI 3 ""))]
13266 "TARGET_POWER && reload_completed"
13267 [(parallel [(set (match_dup 0)
13268 (ge:SI (match_dup 1) (match_dup 2)))
13269 (clobber (match_dup 3))])
13270 (set (match_dup 4)
13271 (compare:CC (match_dup 0)
13272 (const_int 0)))]
13273 "")
13274
13275 (define_insn ""
13276 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13277 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13278 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13279 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13280 "TARGET_POWER"
13281 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
13282 [(set_attr "length" "12")])
13283
13284 (define_insn ""
13285 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13286 (compare:CC
13287 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13288 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13289 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13290 (const_int 0)))
13291 (clobber (match_scratch:SI 4 "=&r,&r"))]
13292 "TARGET_POWER"
13293 "@
13294 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13295 #"
13296 [(set_attr "type" "compare")
13297 (set_attr "length" "12,16")])
13298
13299 (define_split
13300 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13301 (compare:CC
13302 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13303 (match_operand:SI 2 "reg_or_short_operand" ""))
13304 (match_operand:SI 3 "gpc_reg_operand" ""))
13305 (const_int 0)))
13306 (clobber (match_scratch:SI 4 ""))]
13307 "TARGET_POWER && reload_completed"
13308 [(set (match_dup 4)
13309 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
13310 (match_dup 3)))
13311 (set (match_dup 0)
13312 (compare:CC (match_dup 4)
13313 (const_int 0)))]
13314 "")
13315
13316 (define_insn ""
13317 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13318 (compare:CC
13319 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13320 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13321 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13322 (const_int 0)))
13323 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13324 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13325 "TARGET_POWER"
13326 "@
13327 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13328 #"
13329 [(set_attr "type" "compare")
13330 (set_attr "length" "12,16")])
13331
13332 (define_split
13333 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13334 (compare:CC
13335 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13336 (match_operand:SI 2 "reg_or_short_operand" ""))
13337 (match_operand:SI 3 "gpc_reg_operand" ""))
13338 (const_int 0)))
13339 (set (match_operand:SI 0 "gpc_reg_operand" "")
13340 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13341 "TARGET_POWER && reload_completed"
13342 [(set (match_dup 0)
13343 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13344 (set (match_dup 4)
13345 (compare:CC (match_dup 0)
13346 (const_int 0)))]
13347 "")
13348
13349 (define_insn ""
13350 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13351 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13352 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13353 "TARGET_POWER"
13354 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
13355 [(set_attr "length" "12")])
13356
13357 (define_insn "*geu<mode>"
13358 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13359 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13360 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13361 ""
13362 "@
13363 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
13364 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
13365 [(set_attr "type" "three")
13366 (set_attr "length" "12")])
13367
13368 (define_insn "*geu<mode>_compare"
13369 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13370 (compare:CC
13371 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13372 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13373 (const_int 0)))
13374 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13375 (geu:P (match_dup 1) (match_dup 2)))]
13376 ""
13377 "@
13378 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13379 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13380 #
13381 #"
13382 [(set_attr "type" "compare")
13383 (set_attr "length" "12,12,16,16")])
13384
13385 (define_split
13386 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13387 (compare:CC
13388 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
13389 (match_operand:P 2 "reg_or_neg_short_operand" ""))
13390 (const_int 0)))
13391 (set (match_operand:P 0 "gpc_reg_operand" "")
13392 (geu:P (match_dup 1) (match_dup 2)))]
13393 "reload_completed"
13394 [(set (match_dup 0)
13395 (geu:P (match_dup 1) (match_dup 2)))
13396 (set (match_dup 3)
13397 (compare:CC (match_dup 0)
13398 (const_int 0)))]
13399 "")
13400
13401 (define_insn "*plus_geu<mode>"
13402 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13403 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13404 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13405 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13406 ""
13407 "@
13408 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
13409 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
13410 [(set_attr "type" "two")
13411 (set_attr "length" "8")])
13412
13413 (define_insn ""
13414 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13415 (compare:CC
13416 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13417 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13418 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13419 (const_int 0)))
13420 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13421 "TARGET_32BIT"
13422 "@
13423 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
13424 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
13425 #
13426 #"
13427 [(set_attr "type" "compare")
13428 (set_attr "length" "8,8,12,12")])
13429
13430 (define_split
13431 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13432 (compare:CC
13433 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13434 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13435 (match_operand:SI 3 "gpc_reg_operand" ""))
13436 (const_int 0)))
13437 (clobber (match_scratch:SI 4 ""))]
13438 "TARGET_32BIT && reload_completed"
13439 [(set (match_dup 4)
13440 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13441 (match_dup 3)))
13442 (set (match_dup 0)
13443 (compare:CC (match_dup 4)
13444 (const_int 0)))]
13445 "")
13446
13447 (define_insn ""
13448 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13449 (compare:CC
13450 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13451 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13452 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13453 (const_int 0)))
13454 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13455 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13456 "TARGET_32BIT"
13457 "@
13458 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
13459 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
13460 #
13461 #"
13462 [(set_attr "type" "compare")
13463 (set_attr "length" "8,8,12,12")])
13464
13465 (define_split
13466 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13467 (compare:CC
13468 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13469 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13470 (match_operand:SI 3 "gpc_reg_operand" ""))
13471 (const_int 0)))
13472 (set (match_operand:SI 0 "gpc_reg_operand" "")
13473 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13474 "TARGET_32BIT && reload_completed"
13475 [(set (match_dup 0)
13476 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13477 (set (match_dup 4)
13478 (compare:CC (match_dup 0)
13479 (const_int 0)))]
13480 "")
13481
13482 (define_insn "*neg_geu<mode>"
13483 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13484 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13485 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13486 ""
13487 "@
13488 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
13489 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
13490 [(set_attr "type" "three")
13491 (set_attr "length" "12")])
13492
13493 (define_insn "*and_neg_geu<mode>"
13494 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13495 (and:P (neg:P
13496 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13497 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13498 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13499 ""
13500 "@
13501 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
13502 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13503 [(set_attr "type" "three")
13504 (set_attr "length" "12")])
13505
13506 (define_insn ""
13507 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13508 (compare:CC
13509 (and:SI (neg:SI
13510 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13511 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13512 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13513 (const_int 0)))
13514 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13515 "TARGET_32BIT"
13516 "@
13517 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13518 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13519 #
13520 #"
13521 [(set_attr "type" "compare")
13522 (set_attr "length" "12,12,16,16")])
13523
13524 (define_split
13525 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13526 (compare:CC
13527 (and:SI (neg:SI
13528 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13529 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13530 (match_operand:SI 3 "gpc_reg_operand" ""))
13531 (const_int 0)))
13532 (clobber (match_scratch:SI 4 ""))]
13533 "TARGET_32BIT && reload_completed"
13534 [(set (match_dup 4)
13535 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13536 (match_dup 3)))
13537 (set (match_dup 0)
13538 (compare:CC (match_dup 4)
13539 (const_int 0)))]
13540 "")
13541
13542 (define_insn ""
13543 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13544 (compare:CC
13545 (and:SI (neg:SI
13546 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13547 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13548 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13549 (const_int 0)))
13550 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13551 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13552 "TARGET_32BIT"
13553 "@
13554 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13555 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13556 #
13557 #"
13558 [(set_attr "type" "compare")
13559 (set_attr "length" "12,12,16,16")])
13560
13561 (define_split
13562 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13563 (compare:CC
13564 (and:SI (neg:SI
13565 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13566 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13567 (match_operand:SI 3 "gpc_reg_operand" ""))
13568 (const_int 0)))
13569 (set (match_operand:SI 0 "gpc_reg_operand" "")
13570 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13571 "TARGET_32BIT && reload_completed"
13572 [(set (match_dup 0)
13573 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13574 (set (match_dup 4)
13575 (compare:CC (match_dup 0)
13576 (const_int 0)))]
13577 "")
13578
13579 (define_insn ""
13580 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13581 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13582 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13583 "TARGET_POWER"
13584 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13585 [(set_attr "length" "12")])
13586
13587 (define_insn ""
13588 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13589 (compare:CC
13590 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13591 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13592 (const_int 0)))
13593 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13594 (gt:SI (match_dup 1) (match_dup 2)))]
13595 "TARGET_POWER"
13596 "@
13597 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13598 #"
13599 [(set_attr "type" "delayed_compare")
13600 (set_attr "length" "12,16")])
13601
13602 (define_split
13603 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13604 (compare:CC
13605 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13606 (match_operand:SI 2 "reg_or_short_operand" ""))
13607 (const_int 0)))
13608 (set (match_operand:SI 0 "gpc_reg_operand" "")
13609 (gt:SI (match_dup 1) (match_dup 2)))]
13610 "TARGET_POWER && reload_completed"
13611 [(set (match_dup 0)
13612 (gt:SI (match_dup 1) (match_dup 2)))
13613 (set (match_dup 3)
13614 (compare:CC (match_dup 0)
13615 (const_int 0)))]
13616 "")
13617
13618 (define_insn "*plus_gt0<mode>"
13619 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13620 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13621 (const_int 0))
13622 (match_operand:P 2 "gpc_reg_operand" "r")))]
13623 ""
13624 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13625 [(set_attr "type" "three")
13626 (set_attr "length" "12")])
13627
13628 (define_insn ""
13629 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13630 (compare:CC
13631 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13632 (const_int 0))
13633 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13634 (const_int 0)))
13635 (clobber (match_scratch:SI 3 "=&r,&r"))]
13636 "TARGET_32BIT"
13637 "@
13638 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13639 #"
13640 [(set_attr "type" "compare")
13641 (set_attr "length" "12,16")])
13642
13643 (define_split
13644 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13645 (compare:CC
13646 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13647 (const_int 0))
13648 (match_operand:SI 2 "gpc_reg_operand" ""))
13649 (const_int 0)))
13650 (clobber (match_scratch:SI 3 ""))]
13651 "TARGET_32BIT && reload_completed"
13652 [(set (match_dup 3)
13653 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13654 (match_dup 2)))
13655 (set (match_dup 0)
13656 (compare:CC (match_dup 3)
13657 (const_int 0)))]
13658 "")
13659
13660 (define_insn ""
13661 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13662 (compare:CC
13663 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13664 (const_int 0))
13665 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13666 (const_int 0)))
13667 (clobber (match_scratch:DI 3 "=&r,&r"))]
13668 "TARGET_64BIT"
13669 "@
13670 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13671 #"
13672 [(set_attr "type" "compare")
13673 (set_attr "length" "12,16")])
13674
13675 (define_split
13676 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13677 (compare:CC
13678 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13679 (const_int 0))
13680 (match_operand:DI 2 "gpc_reg_operand" ""))
13681 (const_int 0)))
13682 (clobber (match_scratch:DI 3 ""))]
13683 "TARGET_64BIT && reload_completed"
13684 [(set (match_dup 3)
13685 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13686 (match_dup 2)))
13687 (set (match_dup 0)
13688 (compare:CC (match_dup 3)
13689 (const_int 0)))]
13690 "")
13691
13692 (define_insn ""
13693 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13694 (compare:CC
13695 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13696 (const_int 0))
13697 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13698 (const_int 0)))
13699 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13700 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13701 "TARGET_32BIT"
13702 "@
13703 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13704 #"
13705 [(set_attr "type" "compare")
13706 (set_attr "length" "12,16")])
13707
13708 (define_split
13709 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13710 (compare:CC
13711 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13712 (const_int 0))
13713 (match_operand:SI 2 "gpc_reg_operand" ""))
13714 (const_int 0)))
13715 (set (match_operand:SI 0 "gpc_reg_operand" "")
13716 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13717 "TARGET_32BIT && reload_completed"
13718 [(set (match_dup 0)
13719 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13720 (set (match_dup 3)
13721 (compare:CC (match_dup 0)
13722 (const_int 0)))]
13723 "")
13724
13725 (define_insn ""
13726 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13727 (compare:CC
13728 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13729 (const_int 0))
13730 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13731 (const_int 0)))
13732 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13733 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13734 "TARGET_64BIT"
13735 "@
13736 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13737 #"
13738 [(set_attr "type" "compare")
13739 (set_attr "length" "12,16")])
13740
13741 (define_split
13742 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13743 (compare:CC
13744 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13745 (const_int 0))
13746 (match_operand:DI 2 "gpc_reg_operand" ""))
13747 (const_int 0)))
13748 (set (match_operand:DI 0 "gpc_reg_operand" "")
13749 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13750 "TARGET_64BIT && reload_completed"
13751 [(set (match_dup 0)
13752 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13753 (set (match_dup 3)
13754 (compare:CC (match_dup 0)
13755 (const_int 0)))]
13756 "")
13757
13758 (define_insn ""
13759 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13760 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13761 (match_operand:SI 2 "reg_or_short_operand" "r"))
13762 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13763 "TARGET_POWER"
13764 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13765 [(set_attr "length" "12")])
13766
13767 (define_insn ""
13768 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13769 (compare:CC
13770 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13771 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13772 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13773 (const_int 0)))
13774 (clobber (match_scratch:SI 4 "=&r,&r"))]
13775 "TARGET_POWER"
13776 "@
13777 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13778 #"
13779 [(set_attr "type" "compare")
13780 (set_attr "length" "12,16")])
13781
13782 (define_split
13783 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13784 (compare:CC
13785 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13786 (match_operand:SI 2 "reg_or_short_operand" ""))
13787 (match_operand:SI 3 "gpc_reg_operand" ""))
13788 (const_int 0)))
13789 (clobber (match_scratch:SI 4 ""))]
13790 "TARGET_POWER && reload_completed"
13791 [(set (match_dup 4)
13792 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13793 (set (match_dup 0)
13794 (compare:CC (match_dup 4)
13795 (const_int 0)))]
13796 "")
13797
13798 (define_insn ""
13799 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13800 (compare:CC
13801 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13802 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13803 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13804 (const_int 0)))
13805 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13806 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13807 "TARGET_POWER"
13808 "@
13809 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13810 #"
13811 [(set_attr "type" "compare")
13812 (set_attr "length" "12,16")])
13813
13814 (define_split
13815 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13816 (compare:CC
13817 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13818 (match_operand:SI 2 "reg_or_short_operand" ""))
13819 (match_operand:SI 3 "gpc_reg_operand" ""))
13820 (const_int 0)))
13821 (set (match_operand:SI 0 "gpc_reg_operand" "")
13822 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13823 "TARGET_POWER && reload_completed"
13824 [(set (match_dup 0)
13825 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13826 (set (match_dup 4)
13827 (compare:CC (match_dup 0)
13828 (const_int 0)))]
13829 "")
13830
13831 (define_insn ""
13832 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13833 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13834 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13835 "TARGET_POWER"
13836 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13837 [(set_attr "length" "12")])
13838
13839 (define_insn_and_split "*gtu<mode>"
13840 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13841 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13842 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13843 ""
13844 "#"
13845 ""
13846 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13847 (set (match_dup 0) (neg:P (match_dup 0)))]
13848 "")
13849
13850 (define_insn_and_split "*gtu<mode>_compare"
13851 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13852 (compare:CC
13853 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13854 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13855 (const_int 0)))
13856 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13857 (gtu:P (match_dup 1) (match_dup 2)))]
13858 ""
13859 "#"
13860 ""
13861 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13862 (parallel [(set (match_dup 3)
13863 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13864 (set (match_dup 0) (neg:P (match_dup 0)))])]
13865 "")
13866
13867 (define_insn_and_split "*plus_gtu<mode>"
13868 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13869 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13870 (match_operand:P 2 "reg_or_short_operand" "rI"))
13871 (match_operand:P 3 "reg_or_short_operand" "rI")))]
13872 ""
13873 "#"
13874 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13875 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13876 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13877 "")
13878
13879 (define_insn_and_split "*plus_gtu<mode>_compare"
13880 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13881 (compare:CC
13882 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13883 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13884 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13885 (const_int 0)))
13886 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13887 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13888 ""
13889 "#"
13890 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13891 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13892 (parallel [(set (match_dup 4)
13893 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13894 (const_int 0)))
13895 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13896 "")
13897
13898 (define_insn "*neg_gtu<mode>"
13899 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13900 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13901 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13902 ""
13903 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13904 [(set_attr "type" "two")
13905 (set_attr "length" "8")])
13906
13907 \f
13908 ;; Define both directions of branch and return. If we need a reload
13909 ;; register, we'd rather use CR0 since it is much easier to copy a
13910 ;; register CC value to there.
13911
13912 (define_insn ""
13913 [(set (pc)
13914 (if_then_else (match_operator 1 "branch_comparison_operator"
13915 [(match_operand 2
13916 "cc_reg_operand" "y")
13917 (const_int 0)])
13918 (label_ref (match_operand 0 "" ""))
13919 (pc)))]
13920 ""
13921 "*
13922 {
13923 return output_cbranch (operands[1], \"%l0\", 0, insn);
13924 }"
13925 [(set_attr "type" "branch")])
13926
13927 (define_insn ""
13928 [(set (pc)
13929 (if_then_else (match_operator 0 "branch_comparison_operator"
13930 [(match_operand 1
13931 "cc_reg_operand" "y")
13932 (const_int 0)])
13933 (return)
13934 (pc)))]
13935 "direct_return ()"
13936 "*
13937 {
13938 return output_cbranch (operands[0], NULL, 0, insn);
13939 }"
13940 [(set_attr "type" "jmpreg")
13941 (set_attr "length" "4")])
13942
13943 (define_insn ""
13944 [(set (pc)
13945 (if_then_else (match_operator 1 "branch_comparison_operator"
13946 [(match_operand 2
13947 "cc_reg_operand" "y")
13948 (const_int 0)])
13949 (pc)
13950 (label_ref (match_operand 0 "" ""))))]
13951 ""
13952 "*
13953 {
13954 return output_cbranch (operands[1], \"%l0\", 1, insn);
13955 }"
13956 [(set_attr "type" "branch")])
13957
13958 (define_insn ""
13959 [(set (pc)
13960 (if_then_else (match_operator 0 "branch_comparison_operator"
13961 [(match_operand 1
13962 "cc_reg_operand" "y")
13963 (const_int 0)])
13964 (pc)
13965 (return)))]
13966 "direct_return ()"
13967 "*
13968 {
13969 return output_cbranch (operands[0], NULL, 1, insn);
13970 }"
13971 [(set_attr "type" "jmpreg")
13972 (set_attr "length" "4")])
13973
13974 ;; Logic on condition register values.
13975
13976 ; This pattern matches things like
13977 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13978 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13979 ; (const_int 1)))
13980 ; which are generated by the branch logic.
13981 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13982
13983 (define_insn "*cceq_ior_compare"
13984 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13985 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13986 [(match_operator:SI 2
13987 "branch_positive_comparison_operator"
13988 [(match_operand 3
13989 "cc_reg_operand" "y,y")
13990 (const_int 0)])
13991 (match_operator:SI 4
13992 "branch_positive_comparison_operator"
13993 [(match_operand 5
13994 "cc_reg_operand" "0,y")
13995 (const_int 0)])])
13996 (const_int 1)))]
13997 ""
13998 "cr%q1 %E0,%j2,%j4"
13999 [(set_attr "type" "cr_logical,delayed_cr")])
14000
14001 ; Why is the constant -1 here, but 1 in the previous pattern?
14002 ; Because ~1 has all but the low bit set.
14003 (define_insn ""
14004 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14005 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
14006 [(not:SI (match_operator:SI 2
14007 "branch_positive_comparison_operator"
14008 [(match_operand 3
14009 "cc_reg_operand" "y,y")
14010 (const_int 0)]))
14011 (match_operator:SI 4
14012 "branch_positive_comparison_operator"
14013 [(match_operand 5
14014 "cc_reg_operand" "0,y")
14015 (const_int 0)])])
14016 (const_int -1)))]
14017 ""
14018 "cr%q1 %E0,%j2,%j4"
14019 [(set_attr "type" "cr_logical,delayed_cr")])
14020
14021 (define_insn "*cceq_rev_compare"
14022 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14023 (compare:CCEQ (match_operator:SI 1
14024 "branch_positive_comparison_operator"
14025 [(match_operand 2
14026 "cc_reg_operand" "0,y")
14027 (const_int 0)])
14028 (const_int 0)))]
14029 ""
14030 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
14031 [(set_attr "type" "cr_logical,delayed_cr")])
14032
14033 ;; If we are comparing the result of two comparisons, this can be done
14034 ;; using creqv or crxor.
14035
14036 (define_insn_and_split ""
14037 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14038 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
14039 [(match_operand 2 "cc_reg_operand" "y")
14040 (const_int 0)])
14041 (match_operator 3 "branch_comparison_operator"
14042 [(match_operand 4 "cc_reg_operand" "y")
14043 (const_int 0)])))]
14044 ""
14045 "#"
14046 ""
14047 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14048 (match_dup 5)))]
14049 "
14050 {
14051 int positive_1, positive_2;
14052
14053 positive_1 = branch_positive_comparison_operator (operands[1],
14054 GET_MODE (operands[1]));
14055 positive_2 = branch_positive_comparison_operator (operands[3],
14056 GET_MODE (operands[3]));
14057
14058 if (! positive_1)
14059 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
14060 GET_CODE (operands[1])),
14061 SImode,
14062 operands[2], const0_rtx);
14063 else if (GET_MODE (operands[1]) != SImode)
14064 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14065 operands[2], const0_rtx);
14066
14067 if (! positive_2)
14068 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
14069 GET_CODE (operands[3])),
14070 SImode,
14071 operands[4], const0_rtx);
14072 else if (GET_MODE (operands[3]) != SImode)
14073 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14074 operands[4], const0_rtx);
14075
14076 if (positive_1 == positive_2)
14077 {
14078 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14079 operands[5] = constm1_rtx;
14080 }
14081 else
14082 {
14083 operands[5] = const1_rtx;
14084 }
14085 }")
14086
14087 ;; Unconditional branch and return.
14088
14089 (define_insn "jump"
14090 [(set (pc)
14091 (label_ref (match_operand 0 "" "")))]
14092 ""
14093 "b %l0"
14094 [(set_attr "type" "branch")])
14095
14096 (define_insn "return"
14097 [(return)]
14098 "direct_return ()"
14099 "{br|blr}"
14100 [(set_attr "type" "jmpreg")])
14101
14102 (define_expand "indirect_jump"
14103 [(set (pc) (match_operand 0 "register_operand" ""))])
14104
14105 (define_insn "*indirect_jump<mode>"
14106 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14107 ""
14108 "@
14109 bctr
14110 {br|blr}"
14111 [(set_attr "type" "jmpreg")])
14112
14113 ;; Table jump for switch statements:
14114 (define_expand "tablejump"
14115 [(use (match_operand 0 "" ""))
14116 (use (label_ref (match_operand 1 "" "")))]
14117 ""
14118 "
14119 {
14120 if (TARGET_32BIT)
14121 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14122 else
14123 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14124 DONE;
14125 }")
14126
14127 (define_expand "tablejumpsi"
14128 [(set (match_dup 3)
14129 (plus:SI (match_operand:SI 0 "" "")
14130 (match_dup 2)))
14131 (parallel [(set (pc) (match_dup 3))
14132 (use (label_ref (match_operand 1 "" "")))])]
14133 "TARGET_32BIT"
14134 "
14135 { operands[0] = force_reg (SImode, operands[0]);
14136 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
14137 operands[3] = gen_reg_rtx (SImode);
14138 }")
14139
14140 (define_expand "tablejumpdi"
14141 [(set (match_dup 4)
14142 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
14143 (set (match_dup 3)
14144 (plus:DI (match_dup 4)
14145 (match_dup 2)))
14146 (parallel [(set (pc) (match_dup 3))
14147 (use (label_ref (match_operand 1 "" "")))])]
14148 "TARGET_64BIT"
14149 "
14150 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
14151 operands[3] = gen_reg_rtx (DImode);
14152 operands[4] = gen_reg_rtx (DImode);
14153 }")
14154
14155 (define_insn "*tablejump<mode>_internal1"
14156 [(set (pc)
14157 (match_operand:P 0 "register_operand" "c,*l"))
14158 (use (label_ref (match_operand 1 "" "")))]
14159 ""
14160 "@
14161 bctr
14162 {br|blr}"
14163 [(set_attr "type" "jmpreg")])
14164
14165 (define_insn "nop"
14166 [(const_int 0)]
14167 ""
14168 "{cror 0,0,0|nop}")
14169 \f
14170 ;; Define the subtract-one-and-jump insns, starting with the template
14171 ;; so loop.c knows what to generate.
14172
14173 (define_expand "doloop_end"
14174 [(use (match_operand 0 "" "")) ; loop pseudo
14175 (use (match_operand 1 "" "")) ; iterations; zero if unknown
14176 (use (match_operand 2 "" "")) ; max iterations
14177 (use (match_operand 3 "" "")) ; loop level
14178 (use (match_operand 4 "" ""))] ; label
14179 ""
14180 "
14181 {
14182 /* Only use this on innermost loops. */
14183 if (INTVAL (operands[3]) > 1)
14184 FAIL;
14185 if (TARGET_64BIT)
14186 {
14187 if (GET_MODE (operands[0]) != DImode)
14188 FAIL;
14189 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
14190 }
14191 else
14192 {
14193 if (GET_MODE (operands[0]) != SImode)
14194 FAIL;
14195 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
14196 }
14197 DONE;
14198 }")
14199
14200 (define_expand "ctr<mode>"
14201 [(parallel [(set (pc)
14202 (if_then_else (ne (match_operand:P 0 "register_operand" "")
14203 (const_int 1))
14204 (label_ref (match_operand 1 "" ""))
14205 (pc)))
14206 (set (match_dup 0)
14207 (plus:P (match_dup 0)
14208 (const_int -1)))
14209 (clobber (match_scratch:CC 2 ""))
14210 (clobber (match_scratch:P 3 ""))])]
14211 ""
14212 "")
14213
14214 ;; We need to be able to do this for any operand, including MEM, or we
14215 ;; will cause reload to blow up since we don't allow output reloads on
14216 ;; JUMP_INSNs.
14217 ;; For the length attribute to be calculated correctly, the
14218 ;; label MUST be operand 0.
14219
14220 (define_insn "*ctr<mode>_internal1"
14221 [(set (pc)
14222 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14223 (const_int 1))
14224 (label_ref (match_operand 0 "" ""))
14225 (pc)))
14226 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14227 (plus:P (match_dup 1)
14228 (const_int -1)))
14229 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14230 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14231 ""
14232 "*
14233 {
14234 if (which_alternative != 0)
14235 return \"#\";
14236 else if (get_attr_length (insn) == 4)
14237 return \"{bdn|bdnz} %l0\";
14238 else
14239 return \"bdz $+8\;b %l0\";
14240 }"
14241 [(set_attr "type" "branch")
14242 (set_attr "length" "*,12,16,16")])
14243
14244 (define_insn "*ctr<mode>_internal2"
14245 [(set (pc)
14246 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14247 (const_int 1))
14248 (pc)
14249 (label_ref (match_operand 0 "" ""))))
14250 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14251 (plus:P (match_dup 1)
14252 (const_int -1)))
14253 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14254 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14255 ""
14256 "*
14257 {
14258 if (which_alternative != 0)
14259 return \"#\";
14260 else if (get_attr_length (insn) == 4)
14261 return \"bdz %l0\";
14262 else
14263 return \"{bdn|bdnz} $+8\;b %l0\";
14264 }"
14265 [(set_attr "type" "branch")
14266 (set_attr "length" "*,12,16,16")])
14267
14268 ;; Similar but use EQ
14269
14270 (define_insn "*ctr<mode>_internal5"
14271 [(set (pc)
14272 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14273 (const_int 1))
14274 (label_ref (match_operand 0 "" ""))
14275 (pc)))
14276 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14277 (plus:P (match_dup 1)
14278 (const_int -1)))
14279 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14280 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14281 ""
14282 "*
14283 {
14284 if (which_alternative != 0)
14285 return \"#\";
14286 else if (get_attr_length (insn) == 4)
14287 return \"bdz %l0\";
14288 else
14289 return \"{bdn|bdnz} $+8\;b %l0\";
14290 }"
14291 [(set_attr "type" "branch")
14292 (set_attr "length" "*,12,16,16")])
14293
14294 (define_insn "*ctr<mode>_internal6"
14295 [(set (pc)
14296 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14297 (const_int 1))
14298 (pc)
14299 (label_ref (match_operand 0 "" ""))))
14300 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14301 (plus:P (match_dup 1)
14302 (const_int -1)))
14303 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14304 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14305 ""
14306 "*
14307 {
14308 if (which_alternative != 0)
14309 return \"#\";
14310 else if (get_attr_length (insn) == 4)
14311 return \"{bdn|bdnz} %l0\";
14312 else
14313 return \"bdz $+8\;b %l0\";
14314 }"
14315 [(set_attr "type" "branch")
14316 (set_attr "length" "*,12,16,16")])
14317
14318 ;; Now the splitters if we could not allocate the CTR register
14319
14320 (define_split
14321 [(set (pc)
14322 (if_then_else (match_operator 2 "comparison_operator"
14323 [(match_operand:P 1 "gpc_reg_operand" "")
14324 (const_int 1)])
14325 (match_operand 5 "" "")
14326 (match_operand 6 "" "")))
14327 (set (match_operand:P 0 "gpc_reg_operand" "")
14328 (plus:P (match_dup 1) (const_int -1)))
14329 (clobber (match_scratch:CC 3 ""))
14330 (clobber (match_scratch:P 4 ""))]
14331 "reload_completed"
14332 [(parallel [(set (match_dup 3)
14333 (compare:CC (plus:P (match_dup 1)
14334 (const_int -1))
14335 (const_int 0)))
14336 (set (match_dup 0)
14337 (plus:P (match_dup 1)
14338 (const_int -1)))])
14339 (set (pc) (if_then_else (match_dup 7)
14340 (match_dup 5)
14341 (match_dup 6)))]
14342 "
14343 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14344 operands[3], const0_rtx); }")
14345
14346 (define_split
14347 [(set (pc)
14348 (if_then_else (match_operator 2 "comparison_operator"
14349 [(match_operand:P 1 "gpc_reg_operand" "")
14350 (const_int 1)])
14351 (match_operand 5 "" "")
14352 (match_operand 6 "" "")))
14353 (set (match_operand:P 0 "nonimmediate_operand" "")
14354 (plus:P (match_dup 1) (const_int -1)))
14355 (clobber (match_scratch:CC 3 ""))
14356 (clobber (match_scratch:P 4 ""))]
14357 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
14358 [(parallel [(set (match_dup 3)
14359 (compare:CC (plus:P (match_dup 1)
14360 (const_int -1))
14361 (const_int 0)))
14362 (set (match_dup 4)
14363 (plus:P (match_dup 1)
14364 (const_int -1)))])
14365 (set (match_dup 0)
14366 (match_dup 4))
14367 (set (pc) (if_then_else (match_dup 7)
14368 (match_dup 5)
14369 (match_dup 6)))]
14370 "
14371 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14372 operands[3], const0_rtx); }")
14373 \f
14374 (define_insn "trap"
14375 [(trap_if (const_int 1) (const_int 0))]
14376 ""
14377 "{t 31,0,0|trap}"
14378 [(set_attr "type" "trap")])
14379
14380 (define_expand "conditional_trap"
14381 [(trap_if (match_operator 0 "trap_comparison_operator"
14382 [(match_dup 2) (match_dup 3)])
14383 (match_operand 1 "const_int_operand" ""))]
14384 ""
14385 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14386 operands[2] = rs6000_compare_op0;
14387 operands[3] = rs6000_compare_op1;")
14388
14389 (define_insn ""
14390 [(trap_if (match_operator 0 "trap_comparison_operator"
14391 [(match_operand:GPR 1 "register_operand" "r")
14392 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
14393 (const_int 0))]
14394 ""
14395 "{t|t<wd>}%V0%I2 %1,%2"
14396 [(set_attr "type" "trap")])
14397 \f
14398 ;; Insns related to generating the function prologue and epilogue.
14399
14400 (define_expand "prologue"
14401 [(use (const_int 0))]
14402 "TARGET_SCHED_PROLOG"
14403 "
14404 {
14405 rs6000_emit_prologue ();
14406 DONE;
14407 }")
14408
14409 (define_insn "*movesi_from_cr_one"
14410 [(match_parallel 0 "mfcr_operation"
14411 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14412 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14413 (match_operand 3 "immediate_operand" "n")]
14414 UNSPEC_MOVESI_FROM_CR))])]
14415 "TARGET_MFCRF"
14416 "*
14417 {
14418 int mask = 0;
14419 int i;
14420 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14421 {
14422 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14423 operands[4] = GEN_INT (mask);
14424 output_asm_insn (\"mfcr %1,%4\", operands);
14425 }
14426 return \"\";
14427 }"
14428 [(set_attr "type" "mfcrf")])
14429
14430 (define_insn "movesi_from_cr"
14431 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14432 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
14433 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
14434 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
14435 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
14436 UNSPEC_MOVESI_FROM_CR))]
14437 ""
14438 "mfcr %0"
14439 [(set_attr "type" "mfcr")])
14440
14441 (define_insn "*stmw"
14442 [(match_parallel 0 "stmw_operation"
14443 [(set (match_operand:SI 1 "memory_operand" "=m")
14444 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14445 "TARGET_MULTIPLE"
14446 "{stm|stmw} %2,%1"
14447 [(set_attr "type" "store_ux")])
14448
14449 (define_insn "*save_gpregs_<mode>"
14450 [(match_parallel 0 "any_parallel_operand"
14451 [(clobber (reg:P 65))
14452 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14453 (use (match_operand:P 2 "gpc_reg_operand" "r"))
14454 (set (match_operand:P 3 "memory_operand" "=m")
14455 (match_operand:P 4 "gpc_reg_operand" "r"))])]
14456 ""
14457 "bl %z1"
14458 [(set_attr "type" "branch")
14459 (set_attr "length" "4")])
14460
14461 (define_insn "*save_fpregs_<mode>"
14462 [(match_parallel 0 "any_parallel_operand"
14463 [(clobber (reg:P 65))
14464 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14465 (use (match_operand:P 2 "gpc_reg_operand" "r"))
14466 (set (match_operand:DF 3 "memory_operand" "=m")
14467 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14468 ""
14469 "bl %z1"
14470 [(set_attr "type" "branch")
14471 (set_attr "length" "4")])
14472
14473 ; These are to explain that changes to the stack pointer should
14474 ; not be moved over stores to stack memory.
14475 (define_insn "stack_tie"
14476 [(set (match_operand:BLK 0 "memory_operand" "+m")
14477 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
14478 ""
14479 ""
14480 [(set_attr "length" "0")])
14481
14482
14483 (define_expand "epilogue"
14484 [(use (const_int 0))]
14485 "TARGET_SCHED_PROLOG"
14486 "
14487 {
14488 rs6000_emit_epilogue (FALSE);
14489 DONE;
14490 }")
14491
14492 ; On some processors, doing the mtcrf one CC register at a time is
14493 ; faster (like on the 604e). On others, doing them all at once is
14494 ; faster; for instance, on the 601 and 750.
14495
14496 (define_expand "movsi_to_cr_one"
14497 [(set (match_operand:CC 0 "cc_reg_operand" "")
14498 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
14499 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14500 ""
14501 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14502
14503 (define_insn "*movsi_to_cr"
14504 [(match_parallel 0 "mtcrf_operation"
14505 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14506 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14507 (match_operand 3 "immediate_operand" "n")]
14508 UNSPEC_MOVESI_TO_CR))])]
14509 ""
14510 "*
14511 {
14512 int mask = 0;
14513 int i;
14514 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14515 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14516 operands[4] = GEN_INT (mask);
14517 return \"mtcrf %4,%2\";
14518 }"
14519 [(set_attr "type" "mtcr")])
14520
14521 (define_insn "*mtcrfsi"
14522 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14523 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14524 (match_operand 2 "immediate_operand" "n")]
14525 UNSPEC_MOVESI_TO_CR))]
14526 "GET_CODE (operands[0]) == REG
14527 && CR_REGNO_P (REGNO (operands[0]))
14528 && GET_CODE (operands[2]) == CONST_INT
14529 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14530 "mtcrf %R0,%1"
14531 [(set_attr "type" "mtcr")])
14532
14533 ; The load-multiple instructions have similar properties.
14534 ; Note that "load_multiple" is a name known to the machine-independent
14535 ; code that actually corresponds to the PowerPC load-string.
14536
14537 (define_insn "*lmw"
14538 [(match_parallel 0 "lmw_operation"
14539 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14540 (match_operand:SI 2 "memory_operand" "m"))])]
14541 "TARGET_MULTIPLE"
14542 "{lm|lmw} %1,%2"
14543 [(set_attr "type" "load_ux")])
14544
14545 (define_insn "*return_internal_<mode>"
14546 [(return)
14547 (use (match_operand:P 0 "register_operand" "lc"))]
14548 ""
14549 "b%T0"
14550 [(set_attr "type" "jmpreg")])
14551
14552 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14553 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14554
14555 (define_insn "*restore_gpregs_<mode>"
14556 [(match_parallel 0 "any_parallel_operand"
14557 [(clobber (match_operand:P 1 "register_operand" "=l"))
14558 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14559 (use (match_operand:P 3 "gpc_reg_operand" "r"))
14560 (set (match_operand:P 4 "gpc_reg_operand" "=r")
14561 (match_operand:P 5 "memory_operand" "m"))])]
14562 ""
14563 "bl %z2"
14564 [(set_attr "type" "branch")
14565 (set_attr "length" "4")])
14566
14567 (define_insn "*return_and_restore_gpregs_<mode>"
14568 [(match_parallel 0 "any_parallel_operand"
14569 [(return)
14570 (clobber (match_operand:P 1 "register_operand" "=l"))
14571 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14572 (use (match_operand:P 3 "gpc_reg_operand" "r"))
14573 (set (match_operand:P 4 "gpc_reg_operand" "=r")
14574 (match_operand:P 5 "memory_operand" "m"))])]
14575 ""
14576 "b %z2"
14577 [(set_attr "type" "branch")
14578 (set_attr "length" "4")])
14579
14580 (define_insn "*return_and_restore_fpregs_<mode>"
14581 [(match_parallel 0 "any_parallel_operand"
14582 [(return)
14583 (clobber (match_operand:P 1 "register_operand" "=l"))
14584 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14585 (use (match_operand:P 3 "gpc_reg_operand" "r"))
14586 (set (match_operand:DF 4 "gpc_reg_operand" "=f")
14587 (match_operand:DF 5 "memory_operand" "m"))])]
14588 ""
14589 "b %z2"
14590 [(set_attr "type" "branch")
14591 (set_attr "length" "4")])
14592
14593 ; This is used in compiling the unwind routines.
14594 (define_expand "eh_return"
14595 [(use (match_operand 0 "general_operand" ""))]
14596 ""
14597 "
14598 {
14599 if (TARGET_32BIT)
14600 emit_insn (gen_eh_set_lr_si (operands[0]));
14601 else
14602 emit_insn (gen_eh_set_lr_di (operands[0]));
14603 DONE;
14604 }")
14605
14606 ; We can't expand this before we know where the link register is stored.
14607 (define_insn "eh_set_lr_<mode>"
14608 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
14609 UNSPECV_EH_RR)
14610 (clobber (match_scratch:P 1 "=&b"))]
14611 ""
14612 "#")
14613
14614 (define_split
14615 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14616 (clobber (match_scratch 1 ""))]
14617 "reload_completed"
14618 [(const_int 0)]
14619 "
14620 {
14621 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14622 DONE;
14623 }")
14624
14625 (define_insn "prefetch"
14626 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
14627 (match_operand:SI 1 "const_int_operand" "n")
14628 (match_operand:SI 2 "const_int_operand" "n"))]
14629 "TARGET_POWERPC"
14630 "*
14631 {
14632 if (GET_CODE (operands[0]) == REG)
14633 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14634 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14635 }"
14636 [(set_attr "type" "load")])
14637 \f
14638
14639 (include "sync.md")
14640 (include "altivec.md")
14641 (include "spe.md")
14642 (include "dfp.md")
14643 (include "paired.md")
Mirror of https://gcc.gnu.org/git/gcc.git