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md.texi (Iterators): Renamed from Macros.
[thirdparty/gcc.git] / gcc / config / rs6000 / rs6000.md
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6
7 ;; This file is part of GCC.
8
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 3, or (at your
12 ;; option) any later version.
13
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
18
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
22
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
24
25 ;;
26 ;; REGNOS
27 ;;
28
29 (define_constants
30 [(MQ_REGNO 64)
31 (LR_REGNO 65)
32 (CTR_REGNO 66)
33 (CR0_REGNO 68)
34 (CR1_REGNO 69)
35 (CR2_REGNO 70)
36 (CR3_REGNO 71)
37 (CR4_REGNO 72)
38 (CR5_REGNO 73)
39 (CR6_REGNO 74)
40 (CR7_REGNO 75)
41 (MAX_CR_REGNO 75)
42 (XER_REGNO 76)
43 (FIRST_ALTIVEC_REGNO 77)
44 (LAST_ALTIVEC_REGNO 108)
45 (VRSAVE_REGNO 109)
46 (VSCR_REGNO 110)
47 (SPE_ACC_REGNO 111)
48 (SPEFSCR_REGNO 112)
49 (SFP_REGNO 113)
50 ])
51
52 ;;
53 ;; UNSPEC usage
54 ;;
55
56 (define_constants
57 [(UNSPEC_FRSP 0) ; frsp for POWER machines
58 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
59 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
60 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
61 (UNSPEC_MOVSI_GOT 8)
62 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
63 (UNSPEC_FCTIWZ 10)
64 (UNSPEC_FRIM 11)
65 (UNSPEC_FRIN 12)
66 (UNSPEC_FRIP 13)
67 (UNSPEC_FRIZ 14)
68 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
69 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
70 (UNSPEC_TLSGD 17)
71 (UNSPEC_TLSLD 18)
72 (UNSPEC_MOVESI_FROM_CR 19)
73 (UNSPEC_MOVESI_TO_CR 20)
74 (UNSPEC_TLSDTPREL 21)
75 (UNSPEC_TLSDTPRELHA 22)
76 (UNSPEC_TLSDTPRELLO 23)
77 (UNSPEC_TLSGOTDTPREL 24)
78 (UNSPEC_TLSTPREL 25)
79 (UNSPEC_TLSTPRELHA 26)
80 (UNSPEC_TLSTPRELLO 27)
81 (UNSPEC_TLSGOTTPREL 28)
82 (UNSPEC_TLSTLS 29)
83 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
84 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
85 (UNSPEC_STFIWX 32)
86 (UNSPEC_POPCNTB 33)
87 (UNSPEC_FRES 34)
88 (UNSPEC_SP_SET 35)
89 (UNSPEC_SP_TEST 36)
90 (UNSPEC_SYNC 37)
91 (UNSPEC_LWSYNC 38)
92 (UNSPEC_ISYNC 39)
93 (UNSPEC_SYNC_OP 40)
94 (UNSPEC_ATOMIC 41)
95 (UNSPEC_CMPXCHG 42)
96 (UNSPEC_XCHG 43)
97 (UNSPEC_AND 44)
98 (UNSPEC_DLMZB 45)
99 (UNSPEC_DLMZB_CR 46)
100 (UNSPEC_DLMZB_STRLEN 47)
101 ])
102
103 ;;
104 ;; UNSPEC_VOLATILE usage
105 ;;
106
107 (define_constants
108 [(UNSPECV_BLOCK 0)
109 (UNSPECV_LL 1) ; load-locked
110 (UNSPECV_SC 2) ; store-conditional
111 (UNSPECV_EH_RR 9) ; eh_reg_restore
112 ])
113 \f
114 ;; Define an insn type attribute. This is used in function unit delay
115 ;; computations.
116 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr"
117 (const_string "integer"))
118
119 ;; Length (in bytes).
120 ; '(pc)' in the following doesn't include the instruction itself; it is
121 ; calculated as if the instruction had zero size.
122 (define_attr "length" ""
123 (if_then_else (eq_attr "type" "branch")
124 (if_then_else (and (ge (minus (match_dup 0) (pc))
125 (const_int -32768))
126 (lt (minus (match_dup 0) (pc))
127 (const_int 32764)))
128 (const_int 4)
129 (const_int 8))
130 (const_int 4)))
131
132 ;; Processor type -- this attribute must exactly match the processor_type
133 ;; enumeration in rs6000.h.
134
135 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5,power6,cell"
136 (const (symbol_ref "rs6000_cpu_attr")))
137
138
139 ;; If this instruction is microcoded on the CELL processor
140 ; The default for load and stores is conditional
141 ; The default for load extended and the recorded instructions is always microcoded
142 (define_attr "cell_micro" "not,conditional,always"
143 (if_then_else (ior (ior (eq_attr "type" "load")
144 (eq_attr "type" "store"))
145 (ior (eq_attr "type" "fpload")
146 (eq_attr "type" "fpstore")))
147 (const_string "conditional")
148 (if_then_else (ior (eq_attr "type" "load_ext")
149 (ior (eq_attr "type" "compare")
150 (eq_attr "type" "delayed_compare")))
151 (const_string "always")
152 (const_string "not"))))
153
154
155 (automata_option "ndfa")
156
157 (include "rios1.md")
158 (include "rios2.md")
159 (include "rs64.md")
160 (include "mpc.md")
161 (include "40x.md")
162 (include "440.md")
163 (include "603.md")
164 (include "6xx.md")
165 (include "7xx.md")
166 (include "7450.md")
167 (include "8540.md")
168 (include "power4.md")
169 (include "power5.md")
170 (include "power6.md")
171 (include "cell.md")
172
173 (include "predicates.md")
174 (include "constraints.md")
175
176 (include "darwin.md")
177
178 \f
179 ;; Mode iterators
180
181 ; This mode iterator allows :GPR to be used to indicate the allowable size
182 ; of whole values in GPRs.
183 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
184
185 ; Any supported integer mode.
186 (define_mode_iterator INT [QI HI SI DI TI])
187
188 ; Any supported integer mode that fits in one register.
189 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
190
191 ; extend modes for DImode
192 (define_mode_iterator QHSI [QI HI SI])
193
194 ; SImode or DImode, even if DImode doesn't fit in GPRs.
195 (define_mode_iterator SDI [SI DI])
196
197 ; The size of a pointer. Also, the size of the value that a record-condition
198 ; (one with a '.') will compare.
199 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
200
201 ; Any hardware-supported floating-point mode
202 (define_mode_iterator FP [(SF "TARGET_HARD_FLOAT")
203 (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
204 (TF "!TARGET_IEEEQUAD
205 && TARGET_HARD_FLOAT
206 && (TARGET_FPRS || TARGET_E500_DOUBLE)
207 && TARGET_LONG_DOUBLE_128")])
208
209 ; Various instructions that come in SI and DI forms.
210 ; A generic w/d attribute, for things like cmpw/cmpd.
211 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
212
213 ; DImode bits
214 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
215
216 \f
217 ;; Start with fixed-point load and store insns. Here we put only the more
218 ;; complex forms. Basic data transfer is done later.
219
220 (define_expand "zero_extend<mode>di2"
221 [(set (match_operand:DI 0 "gpc_reg_operand" "")
222 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
223 "TARGET_POWERPC64"
224 "")
225
226 (define_insn "*zero_extend<mode>di2_internal1"
227 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
228 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
229 "TARGET_POWERPC64"
230 "@
231 l<wd>z%U1%X1 %0,%1
232 rldicl %0,%1,0,<dbits>"
233 [(set_attr "type" "load,*")])
234
235 (define_insn "*zero_extend<mode>di2_internal2"
236 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
237 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
238 (const_int 0)))
239 (clobber (match_scratch:DI 2 "=r,r"))]
240 "TARGET_64BIT"
241 "@
242 rldicl. %2,%1,0,<dbits>
243 #"
244 [(set_attr "type" "compare")
245 (set_attr "length" "4,8")])
246
247 (define_split
248 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
249 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
250 (const_int 0)))
251 (clobber (match_scratch:DI 2 ""))]
252 "TARGET_POWERPC64 && reload_completed"
253 [(set (match_dup 2)
254 (zero_extend:DI (match_dup 1)))
255 (set (match_dup 0)
256 (compare:CC (match_dup 2)
257 (const_int 0)))]
258 "")
259
260 (define_insn "*zero_extend<mode>di2_internal3"
261 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
262 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
263 (const_int 0)))
264 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
265 (zero_extend:DI (match_dup 1)))]
266 "TARGET_64BIT"
267 "@
268 rldicl. %0,%1,0,<dbits>
269 #"
270 [(set_attr "type" "compare")
271 (set_attr "length" "4,8")])
272
273 (define_split
274 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
275 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
276 (const_int 0)))
277 (set (match_operand:DI 0 "gpc_reg_operand" "")
278 (zero_extend:DI (match_dup 1)))]
279 "TARGET_POWERPC64 && reload_completed"
280 [(set (match_dup 0)
281 (zero_extend:DI (match_dup 1)))
282 (set (match_dup 2)
283 (compare:CC (match_dup 0)
284 (const_int 0)))]
285 "")
286
287 (define_insn "extendqidi2"
288 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
289 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
290 "TARGET_POWERPC64"
291 "extsb %0,%1"
292 [(set_attr "type" "exts")])
293
294 (define_insn ""
295 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
296 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
297 (const_int 0)))
298 (clobber (match_scratch:DI 2 "=r,r"))]
299 "TARGET_64BIT"
300 "@
301 extsb. %2,%1
302 #"
303 [(set_attr "type" "compare")
304 (set_attr "length" "4,8")])
305
306 (define_split
307 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
308 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
309 (const_int 0)))
310 (clobber (match_scratch:DI 2 ""))]
311 "TARGET_POWERPC64 && reload_completed"
312 [(set (match_dup 2)
313 (sign_extend:DI (match_dup 1)))
314 (set (match_dup 0)
315 (compare:CC (match_dup 2)
316 (const_int 0)))]
317 "")
318
319 (define_insn ""
320 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
321 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
322 (const_int 0)))
323 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
324 (sign_extend:DI (match_dup 1)))]
325 "TARGET_64BIT"
326 "@
327 extsb. %0,%1
328 #"
329 [(set_attr "type" "compare")
330 (set_attr "length" "4,8")])
331
332 (define_split
333 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
334 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
335 (const_int 0)))
336 (set (match_operand:DI 0 "gpc_reg_operand" "")
337 (sign_extend:DI (match_dup 1)))]
338 "TARGET_POWERPC64 && reload_completed"
339 [(set (match_dup 0)
340 (sign_extend:DI (match_dup 1)))
341 (set (match_dup 2)
342 (compare:CC (match_dup 0)
343 (const_int 0)))]
344 "")
345
346 (define_expand "extendhidi2"
347 [(set (match_operand:DI 0 "gpc_reg_operand" "")
348 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
349 "TARGET_POWERPC64"
350 "")
351
352 (define_insn ""
353 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
354 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
355 "TARGET_POWERPC64"
356 "@
357 lha%U1%X1 %0,%1
358 extsh %0,%1"
359 [(set_attr "type" "load_ext,exts")])
360
361 (define_insn ""
362 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
363 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
364 (const_int 0)))
365 (clobber (match_scratch:DI 2 "=r,r"))]
366 "TARGET_64BIT"
367 "@
368 extsh. %2,%1
369 #"
370 [(set_attr "type" "compare")
371 (set_attr "length" "4,8")])
372
373 (define_split
374 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
375 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
376 (const_int 0)))
377 (clobber (match_scratch:DI 2 ""))]
378 "TARGET_POWERPC64 && reload_completed"
379 [(set (match_dup 2)
380 (sign_extend:DI (match_dup 1)))
381 (set (match_dup 0)
382 (compare:CC (match_dup 2)
383 (const_int 0)))]
384 "")
385
386 (define_insn ""
387 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
388 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
389 (const_int 0)))
390 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
391 (sign_extend:DI (match_dup 1)))]
392 "TARGET_64BIT"
393 "@
394 extsh. %0,%1
395 #"
396 [(set_attr "type" "compare")
397 (set_attr "length" "4,8")])
398
399 (define_split
400 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
401 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
402 (const_int 0)))
403 (set (match_operand:DI 0 "gpc_reg_operand" "")
404 (sign_extend:DI (match_dup 1)))]
405 "TARGET_POWERPC64 && reload_completed"
406 [(set (match_dup 0)
407 (sign_extend:DI (match_dup 1)))
408 (set (match_dup 2)
409 (compare:CC (match_dup 0)
410 (const_int 0)))]
411 "")
412
413 (define_expand "extendsidi2"
414 [(set (match_operand:DI 0 "gpc_reg_operand" "")
415 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
416 "TARGET_POWERPC64"
417 "")
418
419 (define_insn ""
420 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
421 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
422 "TARGET_POWERPC64"
423 "@
424 lwa%U1%X1 %0,%1
425 extsw %0,%1"
426 [(set_attr "type" "load_ext,exts")])
427
428 (define_insn ""
429 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
430 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
431 (const_int 0)))
432 (clobber (match_scratch:DI 2 "=r,r"))]
433 "TARGET_64BIT"
434 "@
435 extsw. %2,%1
436 #"
437 [(set_attr "type" "compare")
438 (set_attr "length" "4,8")])
439
440 (define_split
441 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
442 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
443 (const_int 0)))
444 (clobber (match_scratch:DI 2 ""))]
445 "TARGET_POWERPC64 && reload_completed"
446 [(set (match_dup 2)
447 (sign_extend:DI (match_dup 1)))
448 (set (match_dup 0)
449 (compare:CC (match_dup 2)
450 (const_int 0)))]
451 "")
452
453 (define_insn ""
454 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
455 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
456 (const_int 0)))
457 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
458 (sign_extend:DI (match_dup 1)))]
459 "TARGET_64BIT"
460 "@
461 extsw. %0,%1
462 #"
463 [(set_attr "type" "compare")
464 (set_attr "length" "4,8")])
465
466 (define_split
467 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
468 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
469 (const_int 0)))
470 (set (match_operand:DI 0 "gpc_reg_operand" "")
471 (sign_extend:DI (match_dup 1)))]
472 "TARGET_POWERPC64 && reload_completed"
473 [(set (match_dup 0)
474 (sign_extend:DI (match_dup 1)))
475 (set (match_dup 2)
476 (compare:CC (match_dup 0)
477 (const_int 0)))]
478 "")
479
480 (define_expand "zero_extendqisi2"
481 [(set (match_operand:SI 0 "gpc_reg_operand" "")
482 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
483 ""
484 "")
485
486 (define_insn ""
487 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
488 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
489 ""
490 "@
491 lbz%U1%X1 %0,%1
492 {rlinm|rlwinm} %0,%1,0,0xff"
493 [(set_attr "type" "load,*")])
494
495 (define_insn ""
496 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
497 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
498 (const_int 0)))
499 (clobber (match_scratch:SI 2 "=r,r"))]
500 ""
501 "@
502 {andil.|andi.} %2,%1,0xff
503 #"
504 [(set_attr "type" "compare")
505 (set_attr "length" "4,8")])
506
507 (define_split
508 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
509 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
510 (const_int 0)))
511 (clobber (match_scratch:SI 2 ""))]
512 "reload_completed"
513 [(set (match_dup 2)
514 (zero_extend:SI (match_dup 1)))
515 (set (match_dup 0)
516 (compare:CC (match_dup 2)
517 (const_int 0)))]
518 "")
519
520 (define_insn ""
521 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
522 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
523 (const_int 0)))
524 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
525 (zero_extend:SI (match_dup 1)))]
526 ""
527 "@
528 {andil.|andi.} %0,%1,0xff
529 #"
530 [(set_attr "type" "compare")
531 (set_attr "length" "4,8")])
532
533 (define_split
534 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
535 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
536 (const_int 0)))
537 (set (match_operand:SI 0 "gpc_reg_operand" "")
538 (zero_extend:SI (match_dup 1)))]
539 "reload_completed"
540 [(set (match_dup 0)
541 (zero_extend:SI (match_dup 1)))
542 (set (match_dup 2)
543 (compare:CC (match_dup 0)
544 (const_int 0)))]
545 "")
546
547 (define_expand "extendqisi2"
548 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
549 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
550 ""
551 "
552 {
553 if (TARGET_POWERPC)
554 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
555 else if (TARGET_POWER)
556 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
557 else
558 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
559 DONE;
560 }")
561
562 (define_insn "extendqisi2_ppc"
563 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
564 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
565 "TARGET_POWERPC"
566 "extsb %0,%1"
567 [(set_attr "type" "exts")])
568
569 (define_insn ""
570 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
571 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
572 (const_int 0)))
573 (clobber (match_scratch:SI 2 "=r,r"))]
574 "TARGET_POWERPC"
575 "@
576 extsb. %2,%1
577 #"
578 [(set_attr "type" "compare")
579 (set_attr "length" "4,8")])
580
581 (define_split
582 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
583 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
584 (const_int 0)))
585 (clobber (match_scratch:SI 2 ""))]
586 "TARGET_POWERPC && reload_completed"
587 [(set (match_dup 2)
588 (sign_extend:SI (match_dup 1)))
589 (set (match_dup 0)
590 (compare:CC (match_dup 2)
591 (const_int 0)))]
592 "")
593
594 (define_insn ""
595 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
596 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
597 (const_int 0)))
598 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
599 (sign_extend:SI (match_dup 1)))]
600 "TARGET_POWERPC"
601 "@
602 extsb. %0,%1
603 #"
604 [(set_attr "type" "compare")
605 (set_attr "length" "4,8")])
606
607 (define_split
608 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
609 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
610 (const_int 0)))
611 (set (match_operand:SI 0 "gpc_reg_operand" "")
612 (sign_extend:SI (match_dup 1)))]
613 "TARGET_POWERPC && reload_completed"
614 [(set (match_dup 0)
615 (sign_extend:SI (match_dup 1)))
616 (set (match_dup 2)
617 (compare:CC (match_dup 0)
618 (const_int 0)))]
619 "")
620
621 (define_expand "extendqisi2_power"
622 [(parallel [(set (match_dup 2)
623 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
624 (const_int 24)))
625 (clobber (scratch:SI))])
626 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
627 (ashiftrt:SI (match_dup 2)
628 (const_int 24)))
629 (clobber (scratch:SI))])]
630 "TARGET_POWER"
631 "
632 { operands[1] = gen_lowpart (SImode, operands[1]);
633 operands[2] = gen_reg_rtx (SImode); }")
634
635 (define_expand "extendqisi2_no_power"
636 [(set (match_dup 2)
637 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
638 (const_int 24)))
639 (set (match_operand:SI 0 "gpc_reg_operand" "")
640 (ashiftrt:SI (match_dup 2)
641 (const_int 24)))]
642 "! TARGET_POWER && ! TARGET_POWERPC"
643 "
644 { operands[1] = gen_lowpart (SImode, operands[1]);
645 operands[2] = gen_reg_rtx (SImode); }")
646
647 (define_expand "zero_extendqihi2"
648 [(set (match_operand:HI 0 "gpc_reg_operand" "")
649 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
650 ""
651 "")
652
653 (define_insn ""
654 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
655 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
656 ""
657 "@
658 lbz%U1%X1 %0,%1
659 {rlinm|rlwinm} %0,%1,0,0xff"
660 [(set_attr "type" "load,*")])
661
662 (define_insn ""
663 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
664 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
665 (const_int 0)))
666 (clobber (match_scratch:HI 2 "=r,r"))]
667 ""
668 "@
669 {andil.|andi.} %2,%1,0xff
670 #"
671 [(set_attr "type" "compare")
672 (set_attr "length" "4,8")])
673
674 (define_split
675 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
676 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
677 (const_int 0)))
678 (clobber (match_scratch:HI 2 ""))]
679 "reload_completed"
680 [(set (match_dup 2)
681 (zero_extend:HI (match_dup 1)))
682 (set (match_dup 0)
683 (compare:CC (match_dup 2)
684 (const_int 0)))]
685 "")
686
687 (define_insn ""
688 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
689 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
690 (const_int 0)))
691 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
692 (zero_extend:HI (match_dup 1)))]
693 ""
694 "@
695 {andil.|andi.} %0,%1,0xff
696 #"
697 [(set_attr "type" "compare")
698 (set_attr "length" "4,8")])
699
700 (define_split
701 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
702 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
703 (const_int 0)))
704 (set (match_operand:HI 0 "gpc_reg_operand" "")
705 (zero_extend:HI (match_dup 1)))]
706 "reload_completed"
707 [(set (match_dup 0)
708 (zero_extend:HI (match_dup 1)))
709 (set (match_dup 2)
710 (compare:CC (match_dup 0)
711 (const_int 0)))]
712 "")
713
714 (define_expand "extendqihi2"
715 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
716 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
717 ""
718 "
719 {
720 if (TARGET_POWERPC)
721 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
722 else if (TARGET_POWER)
723 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
724 else
725 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
726 DONE;
727 }")
728
729 (define_insn "extendqihi2_ppc"
730 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
731 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
732 "TARGET_POWERPC"
733 "extsb %0,%1"
734 [(set_attr "type" "exts")])
735
736 (define_insn ""
737 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
738 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
739 (const_int 0)))
740 (clobber (match_scratch:HI 2 "=r,r"))]
741 "TARGET_POWERPC"
742 "@
743 extsb. %2,%1
744 #"
745 [(set_attr "type" "compare")
746 (set_attr "length" "4,8")])
747
748 (define_split
749 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
750 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
751 (const_int 0)))
752 (clobber (match_scratch:HI 2 ""))]
753 "TARGET_POWERPC && reload_completed"
754 [(set (match_dup 2)
755 (sign_extend:HI (match_dup 1)))
756 (set (match_dup 0)
757 (compare:CC (match_dup 2)
758 (const_int 0)))]
759 "")
760
761 (define_insn ""
762 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
763 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
764 (const_int 0)))
765 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
766 (sign_extend:HI (match_dup 1)))]
767 "TARGET_POWERPC"
768 "@
769 extsb. %0,%1
770 #"
771 [(set_attr "type" "compare")
772 (set_attr "length" "4,8")])
773
774 (define_split
775 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
776 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
777 (const_int 0)))
778 (set (match_operand:HI 0 "gpc_reg_operand" "")
779 (sign_extend:HI (match_dup 1)))]
780 "TARGET_POWERPC && reload_completed"
781 [(set (match_dup 0)
782 (sign_extend:HI (match_dup 1)))
783 (set (match_dup 2)
784 (compare:CC (match_dup 0)
785 (const_int 0)))]
786 "")
787
788 (define_expand "extendqihi2_power"
789 [(parallel [(set (match_dup 2)
790 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
791 (const_int 24)))
792 (clobber (scratch:SI))])
793 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
794 (ashiftrt:SI (match_dup 2)
795 (const_int 24)))
796 (clobber (scratch:SI))])]
797 "TARGET_POWER"
798 "
799 { operands[0] = gen_lowpart (SImode, operands[0]);
800 operands[1] = gen_lowpart (SImode, operands[1]);
801 operands[2] = gen_reg_rtx (SImode); }")
802
803 (define_expand "extendqihi2_no_power"
804 [(set (match_dup 2)
805 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
806 (const_int 24)))
807 (set (match_operand:HI 0 "gpc_reg_operand" "")
808 (ashiftrt:SI (match_dup 2)
809 (const_int 24)))]
810 "! TARGET_POWER && ! TARGET_POWERPC"
811 "
812 { operands[0] = gen_lowpart (SImode, operands[0]);
813 operands[1] = gen_lowpart (SImode, operands[1]);
814 operands[2] = gen_reg_rtx (SImode); }")
815
816 (define_expand "zero_extendhisi2"
817 [(set (match_operand:SI 0 "gpc_reg_operand" "")
818 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
819 ""
820 "")
821
822 (define_insn ""
823 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
824 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
825 ""
826 "@
827 lhz%U1%X1 %0,%1
828 {rlinm|rlwinm} %0,%1,0,0xffff"
829 [(set_attr "type" "load,*")])
830
831 (define_insn ""
832 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
833 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
834 (const_int 0)))
835 (clobber (match_scratch:SI 2 "=r,r"))]
836 ""
837 "@
838 {andil.|andi.} %2,%1,0xffff
839 #"
840 [(set_attr "type" "compare")
841 (set_attr "length" "4,8")])
842
843 (define_split
844 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
845 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
846 (const_int 0)))
847 (clobber (match_scratch:SI 2 ""))]
848 "reload_completed"
849 [(set (match_dup 2)
850 (zero_extend:SI (match_dup 1)))
851 (set (match_dup 0)
852 (compare:CC (match_dup 2)
853 (const_int 0)))]
854 "")
855
856 (define_insn ""
857 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
858 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
859 (const_int 0)))
860 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
861 (zero_extend:SI (match_dup 1)))]
862 ""
863 "@
864 {andil.|andi.} %0,%1,0xffff
865 #"
866 [(set_attr "type" "compare")
867 (set_attr "length" "4,8")])
868
869 (define_split
870 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
871 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
872 (const_int 0)))
873 (set (match_operand:SI 0 "gpc_reg_operand" "")
874 (zero_extend:SI (match_dup 1)))]
875 "reload_completed"
876 [(set (match_dup 0)
877 (zero_extend:SI (match_dup 1)))
878 (set (match_dup 2)
879 (compare:CC (match_dup 0)
880 (const_int 0)))]
881 "")
882
883 (define_expand "extendhisi2"
884 [(set (match_operand:SI 0 "gpc_reg_operand" "")
885 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
886 ""
887 "")
888
889 (define_insn ""
890 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
891 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
892 ""
893 "@
894 lha%U1%X1 %0,%1
895 {exts|extsh} %0,%1"
896 [(set_attr "type" "load_ext,exts")])
897
898 (define_insn ""
899 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
900 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
901 (const_int 0)))
902 (clobber (match_scratch:SI 2 "=r,r"))]
903 ""
904 "@
905 {exts.|extsh.} %2,%1
906 #"
907 [(set_attr "type" "compare")
908 (set_attr "length" "4,8")])
909
910 (define_split
911 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
912 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
913 (const_int 0)))
914 (clobber (match_scratch:SI 2 ""))]
915 "reload_completed"
916 [(set (match_dup 2)
917 (sign_extend:SI (match_dup 1)))
918 (set (match_dup 0)
919 (compare:CC (match_dup 2)
920 (const_int 0)))]
921 "")
922
923 (define_insn ""
924 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
925 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
926 (const_int 0)))
927 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
928 (sign_extend:SI (match_dup 1)))]
929 ""
930 "@
931 {exts.|extsh.} %0,%1
932 #"
933 [(set_attr "type" "compare")
934 (set_attr "length" "4,8")])
935 \f
936 ;; IBM 405 and 440 half-word multiplication operations.
937
938 (define_insn "*macchwc"
939 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
940 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
941 (match_operand:SI 2 "gpc_reg_operand" "r")
942 (const_int 16))
943 (sign_extend:SI
944 (match_operand:HI 1 "gpc_reg_operand" "r")))
945 (match_operand:SI 4 "gpc_reg_operand" "0"))
946 (const_int 0)))
947 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
948 (plus:SI (mult:SI (ashiftrt:SI
949 (match_dup 2)
950 (const_int 16))
951 (sign_extend:SI
952 (match_dup 1)))
953 (match_dup 4)))]
954 "TARGET_MULHW"
955 "macchw. %0, %1, %2"
956 [(set_attr "type" "imul3")])
957
958 (define_insn "*macchw"
959 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
960 (plus:SI (mult:SI (ashiftrt:SI
961 (match_operand:SI 2 "gpc_reg_operand" "r")
962 (const_int 16))
963 (sign_extend:SI
964 (match_operand:HI 1 "gpc_reg_operand" "r")))
965 (match_operand:SI 3 "gpc_reg_operand" "0")))]
966 "TARGET_MULHW"
967 "macchw %0, %1, %2"
968 [(set_attr "type" "imul3")])
969
970 (define_insn "*macchwuc"
971 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
972 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
973 (match_operand:SI 2 "gpc_reg_operand" "r")
974 (const_int 16))
975 (zero_extend:SI
976 (match_operand:HI 1 "gpc_reg_operand" "r")))
977 (match_operand:SI 4 "gpc_reg_operand" "0"))
978 (const_int 0)))
979 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
980 (plus:SI (mult:SI (lshiftrt:SI
981 (match_dup 2)
982 (const_int 16))
983 (zero_extend:SI
984 (match_dup 1)))
985 (match_dup 4)))]
986 "TARGET_MULHW"
987 "macchwu. %0, %1, %2"
988 [(set_attr "type" "imul3")])
989
990 (define_insn "*macchwu"
991 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
992 (plus:SI (mult:SI (lshiftrt:SI
993 (match_operand:SI 2 "gpc_reg_operand" "r")
994 (const_int 16))
995 (zero_extend:SI
996 (match_operand:HI 1 "gpc_reg_operand" "r")))
997 (match_operand:SI 3 "gpc_reg_operand" "0")))]
998 "TARGET_MULHW"
999 "macchwu %0, %1, %2"
1000 [(set_attr "type" "imul3")])
1001
1002 (define_insn "*machhwc"
1003 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1004 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1005 (match_operand:SI 1 "gpc_reg_operand" "%r")
1006 (const_int 16))
1007 (ashiftrt:SI
1008 (match_operand:SI 2 "gpc_reg_operand" "r")
1009 (const_int 16)))
1010 (match_operand:SI 4 "gpc_reg_operand" "0"))
1011 (const_int 0)))
1012 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1013 (plus:SI (mult:SI (ashiftrt:SI
1014 (match_dup 1)
1015 (const_int 16))
1016 (ashiftrt:SI
1017 (match_dup 2)
1018 (const_int 16)))
1019 (match_dup 4)))]
1020 "TARGET_MULHW"
1021 "machhw. %0, %1, %2"
1022 [(set_attr "type" "imul3")])
1023
1024 (define_insn "*machhw"
1025 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1026 (plus:SI (mult:SI (ashiftrt:SI
1027 (match_operand:SI 1 "gpc_reg_operand" "%r")
1028 (const_int 16))
1029 (ashiftrt:SI
1030 (match_operand:SI 2 "gpc_reg_operand" "r")
1031 (const_int 16)))
1032 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1033 "TARGET_MULHW"
1034 "machhw %0, %1, %2"
1035 [(set_attr "type" "imul3")])
1036
1037 (define_insn "*machhwuc"
1038 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1039 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1040 (match_operand:SI 1 "gpc_reg_operand" "%r")
1041 (const_int 16))
1042 (lshiftrt:SI
1043 (match_operand:SI 2 "gpc_reg_operand" "r")
1044 (const_int 16)))
1045 (match_operand:SI 4 "gpc_reg_operand" "0"))
1046 (const_int 0)))
1047 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1048 (plus:SI (mult:SI (lshiftrt:SI
1049 (match_dup 1)
1050 (const_int 16))
1051 (lshiftrt:SI
1052 (match_dup 2)
1053 (const_int 16)))
1054 (match_dup 4)))]
1055 "TARGET_MULHW"
1056 "machhwu. %0, %1, %2"
1057 [(set_attr "type" "imul3")])
1058
1059 (define_insn "*machhwu"
1060 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1061 (plus:SI (mult:SI (lshiftrt:SI
1062 (match_operand:SI 1 "gpc_reg_operand" "%r")
1063 (const_int 16))
1064 (lshiftrt:SI
1065 (match_operand:SI 2 "gpc_reg_operand" "r")
1066 (const_int 16)))
1067 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1068 "TARGET_MULHW"
1069 "machhwu %0, %1, %2"
1070 [(set_attr "type" "imul3")])
1071
1072 (define_insn "*maclhwc"
1073 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1074 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1075 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1076 (sign_extend:SI
1077 (match_operand:HI 2 "gpc_reg_operand" "r")))
1078 (match_operand:SI 4 "gpc_reg_operand" "0"))
1079 (const_int 0)))
1080 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1081 (plus:SI (mult:SI (sign_extend:SI
1082 (match_dup 1))
1083 (sign_extend:SI
1084 (match_dup 2)))
1085 (match_dup 4)))]
1086 "TARGET_MULHW"
1087 "maclhw. %0, %1, %2"
1088 [(set_attr "type" "imul3")])
1089
1090 (define_insn "*maclhw"
1091 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1092 (plus:SI (mult:SI (sign_extend:SI
1093 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1094 (sign_extend:SI
1095 (match_operand:HI 2 "gpc_reg_operand" "r")))
1096 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1097 "TARGET_MULHW"
1098 "maclhw %0, %1, %2"
1099 [(set_attr "type" "imul3")])
1100
1101 (define_insn "*maclhwuc"
1102 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1103 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1104 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1105 (zero_extend:SI
1106 (match_operand:HI 2 "gpc_reg_operand" "r")))
1107 (match_operand:SI 4 "gpc_reg_operand" "0"))
1108 (const_int 0)))
1109 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1110 (plus:SI (mult:SI (zero_extend:SI
1111 (match_dup 1))
1112 (zero_extend:SI
1113 (match_dup 2)))
1114 (match_dup 4)))]
1115 "TARGET_MULHW"
1116 "maclhwu. %0, %1, %2"
1117 [(set_attr "type" "imul3")])
1118
1119 (define_insn "*maclhwu"
1120 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1121 (plus:SI (mult:SI (zero_extend:SI
1122 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1123 (zero_extend:SI
1124 (match_operand:HI 2 "gpc_reg_operand" "r")))
1125 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1126 "TARGET_MULHW"
1127 "maclhwu %0, %1, %2"
1128 [(set_attr "type" "imul3")])
1129
1130 (define_insn "*nmacchwc"
1131 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1132 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1133 (mult:SI (ashiftrt:SI
1134 (match_operand:SI 2 "gpc_reg_operand" "r")
1135 (const_int 16))
1136 (sign_extend:SI
1137 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1138 (const_int 0)))
1139 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1140 (minus:SI (match_dup 4)
1141 (mult:SI (ashiftrt:SI
1142 (match_dup 2)
1143 (const_int 16))
1144 (sign_extend:SI
1145 (match_dup 1)))))]
1146 "TARGET_MULHW"
1147 "nmacchw. %0, %1, %2"
1148 [(set_attr "type" "imul3")])
1149
1150 (define_insn "*nmacchw"
1151 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1152 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1153 (mult:SI (ashiftrt:SI
1154 (match_operand:SI 2 "gpc_reg_operand" "r")
1155 (const_int 16))
1156 (sign_extend:SI
1157 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1158 "TARGET_MULHW"
1159 "nmacchw %0, %1, %2"
1160 [(set_attr "type" "imul3")])
1161
1162 (define_insn "*nmachhwc"
1163 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1164 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1165 (mult:SI (ashiftrt:SI
1166 (match_operand:SI 1 "gpc_reg_operand" "%r")
1167 (const_int 16))
1168 (ashiftrt:SI
1169 (match_operand:SI 2 "gpc_reg_operand" "r")
1170 (const_int 16))))
1171 (const_int 0)))
1172 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1173 (minus:SI (match_dup 4)
1174 (mult:SI (ashiftrt:SI
1175 (match_dup 1)
1176 (const_int 16))
1177 (ashiftrt:SI
1178 (match_dup 2)
1179 (const_int 16)))))]
1180 "TARGET_MULHW"
1181 "nmachhw. %0, %1, %2"
1182 [(set_attr "type" "imul3")])
1183
1184 (define_insn "*nmachhw"
1185 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1186 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1187 (mult:SI (ashiftrt:SI
1188 (match_operand:SI 1 "gpc_reg_operand" "%r")
1189 (const_int 16))
1190 (ashiftrt:SI
1191 (match_operand:SI 2 "gpc_reg_operand" "r")
1192 (const_int 16)))))]
1193 "TARGET_MULHW"
1194 "nmachhw %0, %1, %2"
1195 [(set_attr "type" "imul3")])
1196
1197 (define_insn "*nmaclhwc"
1198 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1199 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1200 (mult:SI (sign_extend:SI
1201 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1202 (sign_extend:SI
1203 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1204 (const_int 0)))
1205 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1206 (minus:SI (match_dup 4)
1207 (mult:SI (sign_extend:SI
1208 (match_dup 1))
1209 (sign_extend:SI
1210 (match_dup 2)))))]
1211 "TARGET_MULHW"
1212 "nmaclhw. %0, %1, %2"
1213 [(set_attr "type" "imul3")])
1214
1215 (define_insn "*nmaclhw"
1216 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1217 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1218 (mult:SI (sign_extend:SI
1219 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1220 (sign_extend:SI
1221 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1222 "TARGET_MULHW"
1223 "nmaclhw %0, %1, %2"
1224 [(set_attr "type" "imul3")])
1225
1226 (define_insn "*mulchwc"
1227 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1228 (compare:CC (mult:SI (ashiftrt:SI
1229 (match_operand:SI 2 "gpc_reg_operand" "r")
1230 (const_int 16))
1231 (sign_extend:SI
1232 (match_operand:HI 1 "gpc_reg_operand" "r")))
1233 (const_int 0)))
1234 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1235 (mult:SI (ashiftrt:SI
1236 (match_dup 2)
1237 (const_int 16))
1238 (sign_extend:SI
1239 (match_dup 1))))]
1240 "TARGET_MULHW"
1241 "mulchw. %0, %1, %2"
1242 [(set_attr "type" "imul3")])
1243
1244 (define_insn "*mulchw"
1245 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1246 (mult:SI (ashiftrt:SI
1247 (match_operand:SI 2 "gpc_reg_operand" "r")
1248 (const_int 16))
1249 (sign_extend:SI
1250 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1251 "TARGET_MULHW"
1252 "mulchw %0, %1, %2"
1253 [(set_attr "type" "imul3")])
1254
1255 (define_insn "*mulchwuc"
1256 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1257 (compare:CC (mult:SI (lshiftrt:SI
1258 (match_operand:SI 2 "gpc_reg_operand" "r")
1259 (const_int 16))
1260 (zero_extend:SI
1261 (match_operand:HI 1 "gpc_reg_operand" "r")))
1262 (const_int 0)))
1263 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1264 (mult:SI (lshiftrt:SI
1265 (match_dup 2)
1266 (const_int 16))
1267 (zero_extend:SI
1268 (match_dup 1))))]
1269 "TARGET_MULHW"
1270 "mulchwu. %0, %1, %2"
1271 [(set_attr "type" "imul3")])
1272
1273 (define_insn "*mulchwu"
1274 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1275 (mult:SI (lshiftrt:SI
1276 (match_operand:SI 2 "gpc_reg_operand" "r")
1277 (const_int 16))
1278 (zero_extend:SI
1279 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1280 "TARGET_MULHW"
1281 "mulchwu %0, %1, %2"
1282 [(set_attr "type" "imul3")])
1283
1284 (define_insn "*mulhhwc"
1285 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1286 (compare:CC (mult:SI (ashiftrt:SI
1287 (match_operand:SI 1 "gpc_reg_operand" "%r")
1288 (const_int 16))
1289 (ashiftrt:SI
1290 (match_operand:SI 2 "gpc_reg_operand" "r")
1291 (const_int 16)))
1292 (const_int 0)))
1293 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1294 (mult:SI (ashiftrt:SI
1295 (match_dup 1)
1296 (const_int 16))
1297 (ashiftrt:SI
1298 (match_dup 2)
1299 (const_int 16))))]
1300 "TARGET_MULHW"
1301 "mulhhw. %0, %1, %2"
1302 [(set_attr "type" "imul3")])
1303
1304 (define_insn "*mulhhw"
1305 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1306 (mult:SI (ashiftrt:SI
1307 (match_operand:SI 1 "gpc_reg_operand" "%r")
1308 (const_int 16))
1309 (ashiftrt:SI
1310 (match_operand:SI 2 "gpc_reg_operand" "r")
1311 (const_int 16))))]
1312 "TARGET_MULHW"
1313 "mulhhw %0, %1, %2"
1314 [(set_attr "type" "imul3")])
1315
1316 (define_insn "*mulhhwuc"
1317 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1318 (compare:CC (mult:SI (lshiftrt:SI
1319 (match_operand:SI 1 "gpc_reg_operand" "%r")
1320 (const_int 16))
1321 (lshiftrt:SI
1322 (match_operand:SI 2 "gpc_reg_operand" "r")
1323 (const_int 16)))
1324 (const_int 0)))
1325 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1326 (mult:SI (lshiftrt:SI
1327 (match_dup 1)
1328 (const_int 16))
1329 (lshiftrt:SI
1330 (match_dup 2)
1331 (const_int 16))))]
1332 "TARGET_MULHW"
1333 "mulhhwu. %0, %1, %2"
1334 [(set_attr "type" "imul3")])
1335
1336 (define_insn "*mulhhwu"
1337 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1338 (mult:SI (lshiftrt:SI
1339 (match_operand:SI 1 "gpc_reg_operand" "%r")
1340 (const_int 16))
1341 (lshiftrt:SI
1342 (match_operand:SI 2 "gpc_reg_operand" "r")
1343 (const_int 16))))]
1344 "TARGET_MULHW"
1345 "mulhhwu %0, %1, %2"
1346 [(set_attr "type" "imul3")])
1347
1348 (define_insn "*mullhwc"
1349 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1350 (compare:CC (mult:SI (sign_extend:SI
1351 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1352 (sign_extend:SI
1353 (match_operand:HI 2 "gpc_reg_operand" "r")))
1354 (const_int 0)))
1355 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1356 (mult:SI (sign_extend:SI
1357 (match_dup 1))
1358 (sign_extend:SI
1359 (match_dup 2))))]
1360 "TARGET_MULHW"
1361 "mullhw. %0, %1, %2"
1362 [(set_attr "type" "imul3")])
1363
1364 (define_insn "*mullhw"
1365 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1366 (mult:SI (sign_extend:SI
1367 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1368 (sign_extend:SI
1369 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1370 "TARGET_MULHW"
1371 "mullhw %0, %1, %2"
1372 [(set_attr "type" "imul3")])
1373
1374 (define_insn "*mullhwuc"
1375 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1376 (compare:CC (mult:SI (zero_extend:SI
1377 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1378 (zero_extend:SI
1379 (match_operand:HI 2 "gpc_reg_operand" "r")))
1380 (const_int 0)))
1381 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1382 (mult:SI (zero_extend:SI
1383 (match_dup 1))
1384 (zero_extend:SI
1385 (match_dup 2))))]
1386 "TARGET_MULHW"
1387 "mullhwu. %0, %1, %2"
1388 [(set_attr "type" "imul3")])
1389
1390 (define_insn "*mullhwu"
1391 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1392 (mult:SI (zero_extend:SI
1393 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1394 (zero_extend:SI
1395 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1396 "TARGET_MULHW"
1397 "mullhwu %0, %1, %2"
1398 [(set_attr "type" "imul3")])
1399 \f
1400 ;; IBM 405 and 440 string-search dlmzb instruction support.
1401 (define_insn "dlmzb"
1402 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1403 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1404 (match_operand:SI 2 "gpc_reg_operand" "r")]
1405 UNSPEC_DLMZB_CR))
1406 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1407 (unspec:SI [(match_dup 1)
1408 (match_dup 2)]
1409 UNSPEC_DLMZB))]
1410 "TARGET_DLMZB"
1411 "dlmzb. %0, %1, %2")
1412
1413 (define_expand "strlensi"
1414 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1415 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1416 (match_operand:QI 2 "const_int_operand" "")
1417 (match_operand 3 "const_int_operand" "")]
1418 UNSPEC_DLMZB_STRLEN))
1419 (clobber (match_scratch:CC 4 "=x"))]
1420 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1421 {
1422 rtx result = operands[0];
1423 rtx src = operands[1];
1424 rtx search_char = operands[2];
1425 rtx align = operands[3];
1426 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1427 rtx loop_label, end_label, mem, cr0, cond;
1428 if (search_char != const0_rtx
1429 || GET_CODE (align) != CONST_INT
1430 || INTVAL (align) < 8)
1431 FAIL;
1432 word1 = gen_reg_rtx (SImode);
1433 word2 = gen_reg_rtx (SImode);
1434 scratch_dlmzb = gen_reg_rtx (SImode);
1435 scratch_string = gen_reg_rtx (Pmode);
1436 loop_label = gen_label_rtx ();
1437 end_label = gen_label_rtx ();
1438 addr = force_reg (Pmode, XEXP (src, 0));
1439 emit_move_insn (scratch_string, addr);
1440 emit_label (loop_label);
1441 mem = change_address (src, SImode, scratch_string);
1442 emit_move_insn (word1, mem);
1443 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1444 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1445 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1446 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1447 emit_jump_insn (gen_rtx_SET (VOIDmode,
1448 pc_rtx,
1449 gen_rtx_IF_THEN_ELSE (VOIDmode,
1450 cond,
1451 gen_rtx_LABEL_REF
1452 (VOIDmode,
1453 end_label),
1454 pc_rtx)));
1455 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1456 emit_jump_insn (gen_rtx_SET (VOIDmode,
1457 pc_rtx,
1458 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1459 emit_barrier ();
1460 emit_label (end_label);
1461 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1462 emit_insn (gen_subsi3 (result, scratch_string, addr));
1463 emit_insn (gen_subsi3 (result, result, const1_rtx));
1464 DONE;
1465 })
1466 \f
1467 (define_split
1468 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1469 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1470 (const_int 0)))
1471 (set (match_operand:SI 0 "gpc_reg_operand" "")
1472 (sign_extend:SI (match_dup 1)))]
1473 "reload_completed"
1474 [(set (match_dup 0)
1475 (sign_extend:SI (match_dup 1)))
1476 (set (match_dup 2)
1477 (compare:CC (match_dup 0)
1478 (const_int 0)))]
1479 "")
1480
1481 ;; Fixed-point arithmetic insns.
1482
1483 (define_expand "add<mode>3"
1484 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1485 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1486 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1487 ""
1488 {
1489 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1490 {
1491 if (non_short_cint_operand (operands[2], DImode))
1492 FAIL;
1493 }
1494 else if (GET_CODE (operands[2]) == CONST_INT
1495 && ! add_operand (operands[2], <MODE>mode))
1496 {
1497 rtx tmp = ((!can_create_pseudo_p ()
1498 || rtx_equal_p (operands[0], operands[1]))
1499 ? operands[0] : gen_reg_rtx (<MODE>mode));
1500
1501 HOST_WIDE_INT val = INTVAL (operands[2]);
1502 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1503 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1504
1505 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1506 FAIL;
1507
1508 /* The ordering here is important for the prolog expander.
1509 When space is allocated from the stack, adding 'low' first may
1510 produce a temporary deallocation (which would be bad). */
1511 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1512 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1513 DONE;
1514 }
1515 })
1516
1517 ;; Discourage ai/addic because of carry but provide it in an alternative
1518 ;; allowing register zero as source.
1519 (define_insn "*add<mode>3_internal1"
1520 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1521 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1522 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1523 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1524 "@
1525 {cax|add} %0,%1,%2
1526 {cal %0,%2(%1)|addi %0,%1,%2}
1527 {ai|addic} %0,%1,%2
1528 {cau|addis} %0,%1,%v2"
1529 [(set_attr "length" "4,4,4,4")])
1530
1531 (define_insn "addsi3_high"
1532 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1533 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1534 (high:SI (match_operand 2 "" ""))))]
1535 "TARGET_MACHO && !TARGET_64BIT"
1536 "{cau|addis} %0,%1,ha16(%2)"
1537 [(set_attr "length" "4")])
1538
1539 (define_insn "*add<mode>3_internal2"
1540 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1541 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1542 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1543 (const_int 0)))
1544 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1545 ""
1546 "@
1547 {cax.|add.} %3,%1,%2
1548 {ai.|addic.} %3,%1,%2
1549 #
1550 #"
1551 [(set_attr "type" "fast_compare,compare,compare,compare")
1552 (set_attr "length" "4,4,8,8")])
1553
1554 (define_split
1555 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1556 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1557 (match_operand:GPR 2 "reg_or_short_operand" ""))
1558 (const_int 0)))
1559 (clobber (match_scratch:GPR 3 ""))]
1560 "reload_completed"
1561 [(set (match_dup 3)
1562 (plus:GPR (match_dup 1)
1563 (match_dup 2)))
1564 (set (match_dup 0)
1565 (compare:CC (match_dup 3)
1566 (const_int 0)))]
1567 "")
1568
1569 (define_insn "*add<mode>3_internal3"
1570 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1571 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1572 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1573 (const_int 0)))
1574 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1575 (plus:P (match_dup 1)
1576 (match_dup 2)))]
1577 ""
1578 "@
1579 {cax.|add.} %0,%1,%2
1580 {ai.|addic.} %0,%1,%2
1581 #
1582 #"
1583 [(set_attr "type" "fast_compare,compare,compare,compare")
1584 (set_attr "length" "4,4,8,8")])
1585
1586 (define_split
1587 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1588 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1589 (match_operand:P 2 "reg_or_short_operand" ""))
1590 (const_int 0)))
1591 (set (match_operand:P 0 "gpc_reg_operand" "")
1592 (plus:P (match_dup 1) (match_dup 2)))]
1593 "reload_completed"
1594 [(set (match_dup 0)
1595 (plus:P (match_dup 1)
1596 (match_dup 2)))
1597 (set (match_dup 3)
1598 (compare:CC (match_dup 0)
1599 (const_int 0)))]
1600 "")
1601
1602 ;; Split an add that we can't do in one insn into two insns, each of which
1603 ;; does one 16-bit part. This is used by combine. Note that the low-order
1604 ;; add should be last in case the result gets used in an address.
1605
1606 (define_split
1607 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1608 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1609 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1610 ""
1611 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1612 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1613 {
1614 HOST_WIDE_INT val = INTVAL (operands[2]);
1615 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1616 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1617
1618 operands[4] = GEN_INT (low);
1619 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1620 operands[3] = GEN_INT (rest);
1621 else if (can_create_pseudo_p ())
1622 {
1623 operands[3] = gen_reg_rtx (DImode);
1624 emit_move_insn (operands[3], operands[2]);
1625 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1626 DONE;
1627 }
1628 else
1629 FAIL;
1630 })
1631
1632 (define_insn "one_cmpl<mode>2"
1633 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1634 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1635 ""
1636 "nor %0,%1,%1")
1637
1638 (define_insn ""
1639 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1640 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1641 (const_int 0)))
1642 (clobber (match_scratch:P 2 "=r,r"))]
1643 ""
1644 "@
1645 nor. %2,%1,%1
1646 #"
1647 [(set_attr "type" "compare")
1648 (set_attr "length" "4,8")])
1649
1650 (define_split
1651 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1652 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1653 (const_int 0)))
1654 (clobber (match_scratch:P 2 ""))]
1655 "reload_completed"
1656 [(set (match_dup 2)
1657 (not:P (match_dup 1)))
1658 (set (match_dup 0)
1659 (compare:CC (match_dup 2)
1660 (const_int 0)))]
1661 "")
1662
1663 (define_insn ""
1664 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1665 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1666 (const_int 0)))
1667 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1668 (not:P (match_dup 1)))]
1669 ""
1670 "@
1671 nor. %0,%1,%1
1672 #"
1673 [(set_attr "type" "compare")
1674 (set_attr "length" "4,8")])
1675
1676 (define_split
1677 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1678 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1679 (const_int 0)))
1680 (set (match_operand:P 0 "gpc_reg_operand" "")
1681 (not:P (match_dup 1)))]
1682 "reload_completed"
1683 [(set (match_dup 0)
1684 (not:P (match_dup 1)))
1685 (set (match_dup 2)
1686 (compare:CC (match_dup 0)
1687 (const_int 0)))]
1688 "")
1689
1690 (define_insn ""
1691 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1692 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1693 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1694 "! TARGET_POWERPC"
1695 "{sf%I1|subf%I1c} %0,%2,%1")
1696
1697 (define_insn ""
1698 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1699 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1700 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1701 "TARGET_POWERPC"
1702 "@
1703 subf %0,%2,%1
1704 subfic %0,%2,%1")
1705
1706 (define_insn ""
1707 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1708 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1709 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1710 (const_int 0)))
1711 (clobber (match_scratch:SI 3 "=r,r"))]
1712 "! TARGET_POWERPC"
1713 "@
1714 {sf.|subfc.} %3,%2,%1
1715 #"
1716 [(set_attr "type" "compare")
1717 (set_attr "length" "4,8")])
1718
1719 (define_insn ""
1720 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1721 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1722 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1723 (const_int 0)))
1724 (clobber (match_scratch:P 3 "=r,r"))]
1725 "TARGET_POWERPC"
1726 "@
1727 subf. %3,%2,%1
1728 #"
1729 [(set_attr "type" "fast_compare")
1730 (set_attr "length" "4,8")])
1731
1732 (define_split
1733 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1734 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1735 (match_operand:P 2 "gpc_reg_operand" ""))
1736 (const_int 0)))
1737 (clobber (match_scratch:P 3 ""))]
1738 "reload_completed"
1739 [(set (match_dup 3)
1740 (minus:P (match_dup 1)
1741 (match_dup 2)))
1742 (set (match_dup 0)
1743 (compare:CC (match_dup 3)
1744 (const_int 0)))]
1745 "")
1746
1747 (define_insn ""
1748 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1749 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1750 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1751 (const_int 0)))
1752 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1753 (minus:SI (match_dup 1) (match_dup 2)))]
1754 "! TARGET_POWERPC"
1755 "@
1756 {sf.|subfc.} %0,%2,%1
1757 #"
1758 [(set_attr "type" "compare")
1759 (set_attr "length" "4,8")])
1760
1761 (define_insn ""
1762 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1763 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1764 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1765 (const_int 0)))
1766 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1767 (minus:P (match_dup 1)
1768 (match_dup 2)))]
1769 "TARGET_POWERPC"
1770 "@
1771 subf. %0,%2,%1
1772 #"
1773 [(set_attr "type" "fast_compare")
1774 (set_attr "length" "4,8")])
1775
1776 (define_split
1777 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1778 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1779 (match_operand:P 2 "gpc_reg_operand" ""))
1780 (const_int 0)))
1781 (set (match_operand:P 0 "gpc_reg_operand" "")
1782 (minus:P (match_dup 1)
1783 (match_dup 2)))]
1784 "reload_completed"
1785 [(set (match_dup 0)
1786 (minus:P (match_dup 1)
1787 (match_dup 2)))
1788 (set (match_dup 3)
1789 (compare:CC (match_dup 0)
1790 (const_int 0)))]
1791 "")
1792
1793 (define_expand "sub<mode>3"
1794 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1795 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1796 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1797 ""
1798 "
1799 {
1800 if (GET_CODE (operands[2]) == CONST_INT)
1801 {
1802 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1803 negate_rtx (<MODE>mode, operands[2])));
1804 DONE;
1805 }
1806 }")
1807
1808 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1809 ;; instruction and some auxiliary computations. Then we just have a single
1810 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1811 ;; combine.
1812
1813 (define_expand "sminsi3"
1814 [(set (match_dup 3)
1815 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1816 (match_operand:SI 2 "reg_or_short_operand" ""))
1817 (const_int 0)
1818 (minus:SI (match_dup 2) (match_dup 1))))
1819 (set (match_operand:SI 0 "gpc_reg_operand" "")
1820 (minus:SI (match_dup 2) (match_dup 3)))]
1821 "TARGET_POWER || TARGET_ISEL"
1822 "
1823 {
1824 if (TARGET_ISEL)
1825 {
1826 operands[2] = force_reg (SImode, operands[2]);
1827 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1828 DONE;
1829 }
1830
1831 operands[3] = gen_reg_rtx (SImode);
1832 }")
1833
1834 (define_split
1835 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1836 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1837 (match_operand:SI 2 "reg_or_short_operand" "")))
1838 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1839 "TARGET_POWER"
1840 [(set (match_dup 3)
1841 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1842 (const_int 0)
1843 (minus:SI (match_dup 2) (match_dup 1))))
1844 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1845 "")
1846
1847 (define_expand "smaxsi3"
1848 [(set (match_dup 3)
1849 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1850 (match_operand:SI 2 "reg_or_short_operand" ""))
1851 (const_int 0)
1852 (minus:SI (match_dup 2) (match_dup 1))))
1853 (set (match_operand:SI 0 "gpc_reg_operand" "")
1854 (plus:SI (match_dup 3) (match_dup 1)))]
1855 "TARGET_POWER || TARGET_ISEL"
1856 "
1857 {
1858 if (TARGET_ISEL)
1859 {
1860 operands[2] = force_reg (SImode, operands[2]);
1861 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1862 DONE;
1863 }
1864 operands[3] = gen_reg_rtx (SImode);
1865 }")
1866
1867 (define_split
1868 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1869 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1870 (match_operand:SI 2 "reg_or_short_operand" "")))
1871 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1872 "TARGET_POWER"
1873 [(set (match_dup 3)
1874 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1875 (const_int 0)
1876 (minus:SI (match_dup 2) (match_dup 1))))
1877 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1878 "")
1879
1880 (define_expand "uminsi3"
1881 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1882 (match_dup 5)))
1883 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1884 (match_dup 5)))
1885 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1886 (const_int 0)
1887 (minus:SI (match_dup 4) (match_dup 3))))
1888 (set (match_operand:SI 0 "gpc_reg_operand" "")
1889 (minus:SI (match_dup 2) (match_dup 3)))]
1890 "TARGET_POWER || TARGET_ISEL"
1891 "
1892 {
1893 if (TARGET_ISEL)
1894 {
1895 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1896 DONE;
1897 }
1898 operands[3] = gen_reg_rtx (SImode);
1899 operands[4] = gen_reg_rtx (SImode);
1900 operands[5] = GEN_INT (-2147483647 - 1);
1901 }")
1902
1903 (define_expand "umaxsi3"
1904 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1905 (match_dup 5)))
1906 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1907 (match_dup 5)))
1908 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1909 (const_int 0)
1910 (minus:SI (match_dup 4) (match_dup 3))))
1911 (set (match_operand:SI 0 "gpc_reg_operand" "")
1912 (plus:SI (match_dup 3) (match_dup 1)))]
1913 "TARGET_POWER || TARGET_ISEL"
1914 "
1915 {
1916 if (TARGET_ISEL)
1917 {
1918 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1919 DONE;
1920 }
1921 operands[3] = gen_reg_rtx (SImode);
1922 operands[4] = gen_reg_rtx (SImode);
1923 operands[5] = GEN_INT (-2147483647 - 1);
1924 }")
1925
1926 (define_insn ""
1927 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1928 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1929 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1930 (const_int 0)
1931 (minus:SI (match_dup 2) (match_dup 1))))]
1932 "TARGET_POWER"
1933 "doz%I2 %0,%1,%2")
1934
1935 (define_insn ""
1936 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1937 (compare:CC
1938 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1939 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1940 (const_int 0)
1941 (minus:SI (match_dup 2) (match_dup 1)))
1942 (const_int 0)))
1943 (clobber (match_scratch:SI 3 "=r,r"))]
1944 "TARGET_POWER"
1945 "@
1946 doz%I2. %3,%1,%2
1947 #"
1948 [(set_attr "type" "delayed_compare")
1949 (set_attr "length" "4,8")])
1950
1951 (define_split
1952 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1953 (compare:CC
1954 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1955 (match_operand:SI 2 "reg_or_short_operand" ""))
1956 (const_int 0)
1957 (minus:SI (match_dup 2) (match_dup 1)))
1958 (const_int 0)))
1959 (clobber (match_scratch:SI 3 ""))]
1960 "TARGET_POWER && reload_completed"
1961 [(set (match_dup 3)
1962 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1963 (const_int 0)
1964 (minus:SI (match_dup 2) (match_dup 1))))
1965 (set (match_dup 0)
1966 (compare:CC (match_dup 3)
1967 (const_int 0)))]
1968 "")
1969
1970 (define_insn ""
1971 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1972 (compare:CC
1973 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1974 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1975 (const_int 0)
1976 (minus:SI (match_dup 2) (match_dup 1)))
1977 (const_int 0)))
1978 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1979 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1980 (const_int 0)
1981 (minus:SI (match_dup 2) (match_dup 1))))]
1982 "TARGET_POWER"
1983 "@
1984 doz%I2. %0,%1,%2
1985 #"
1986 [(set_attr "type" "delayed_compare")
1987 (set_attr "length" "4,8")])
1988
1989 (define_split
1990 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1991 (compare:CC
1992 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1993 (match_operand:SI 2 "reg_or_short_operand" ""))
1994 (const_int 0)
1995 (minus:SI (match_dup 2) (match_dup 1)))
1996 (const_int 0)))
1997 (set (match_operand:SI 0 "gpc_reg_operand" "")
1998 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1999 (const_int 0)
2000 (minus:SI (match_dup 2) (match_dup 1))))]
2001 "TARGET_POWER && reload_completed"
2002 [(set (match_dup 0)
2003 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2004 (const_int 0)
2005 (minus:SI (match_dup 2) (match_dup 1))))
2006 (set (match_dup 3)
2007 (compare:CC (match_dup 0)
2008 (const_int 0)))]
2009 "")
2010
2011 ;; We don't need abs with condition code because such comparisons should
2012 ;; never be done.
2013 (define_expand "abssi2"
2014 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2015 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2016 ""
2017 "
2018 {
2019 if (TARGET_ISEL)
2020 {
2021 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
2022 DONE;
2023 }
2024 else if (! TARGET_POWER)
2025 {
2026 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2027 DONE;
2028 }
2029 }")
2030
2031 (define_insn "*abssi2_power"
2032 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2033 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2034 "TARGET_POWER"
2035 "abs %0,%1")
2036
2037 (define_insn_and_split "abssi2_isel"
2038 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2039 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
2040 (clobber (match_scratch:SI 2 "=&b"))
2041 (clobber (match_scratch:CC 3 "=y"))]
2042 "TARGET_ISEL"
2043 "#"
2044 "&& reload_completed"
2045 [(set (match_dup 2) (neg:SI (match_dup 1)))
2046 (set (match_dup 3)
2047 (compare:CC (match_dup 1)
2048 (const_int 0)))
2049 (set (match_dup 0)
2050 (if_then_else:SI (ge (match_dup 3)
2051 (const_int 0))
2052 (match_dup 1)
2053 (match_dup 2)))]
2054 "")
2055
2056 (define_insn_and_split "abssi2_nopower"
2057 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2058 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2059 (clobber (match_scratch:SI 2 "=&r,&r"))]
2060 "! TARGET_POWER && ! TARGET_ISEL"
2061 "#"
2062 "&& reload_completed"
2063 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2064 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2065 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2066 "")
2067
2068 (define_insn "*nabs_power"
2069 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2070 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2071 "TARGET_POWER"
2072 "nabs %0,%1")
2073
2074 (define_insn_and_split "*nabs_nopower"
2075 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2076 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2077 (clobber (match_scratch:SI 2 "=&r,&r"))]
2078 "! TARGET_POWER"
2079 "#"
2080 "&& reload_completed"
2081 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2082 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2083 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2084 "")
2085
2086 (define_expand "neg<mode>2"
2087 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2088 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2089 ""
2090 "")
2091
2092 (define_insn "*neg<mode>2_internal"
2093 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2094 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2095 ""
2096 "neg %0,%1")
2097
2098 (define_insn ""
2099 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2100 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2101 (const_int 0)))
2102 (clobber (match_scratch:P 2 "=r,r"))]
2103 ""
2104 "@
2105 neg. %2,%1
2106 #"
2107 [(set_attr "type" "fast_compare")
2108 (set_attr "length" "4,8")])
2109
2110 (define_split
2111 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2112 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2113 (const_int 0)))
2114 (clobber (match_scratch:P 2 ""))]
2115 "reload_completed"
2116 [(set (match_dup 2)
2117 (neg:P (match_dup 1)))
2118 (set (match_dup 0)
2119 (compare:CC (match_dup 2)
2120 (const_int 0)))]
2121 "")
2122
2123 (define_insn ""
2124 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2125 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2126 (const_int 0)))
2127 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2128 (neg:P (match_dup 1)))]
2129 ""
2130 "@
2131 neg. %0,%1
2132 #"
2133 [(set_attr "type" "fast_compare")
2134 (set_attr "length" "4,8")])
2135
2136 (define_split
2137 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2138 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2139 (const_int 0)))
2140 (set (match_operand:P 0 "gpc_reg_operand" "")
2141 (neg:P (match_dup 1)))]
2142 "reload_completed"
2143 [(set (match_dup 0)
2144 (neg:P (match_dup 1)))
2145 (set (match_dup 2)
2146 (compare:CC (match_dup 0)
2147 (const_int 0)))]
2148 "")
2149
2150 (define_insn "clz<mode>2"
2151 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2152 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2153 ""
2154 "{cntlz|cntlz<wd>} %0,%1"
2155 [(set_attr "type" "cntlz")])
2156
2157 (define_expand "ctz<mode>2"
2158 [(set (match_dup 2)
2159 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2160 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2161 (match_dup 2)))
2162 (clobber (scratch:CC))])
2163 (set (match_dup 4) (clz:GPR (match_dup 3)))
2164 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2165 (minus:GPR (match_dup 5) (match_dup 4)))]
2166 ""
2167 {
2168 operands[2] = gen_reg_rtx (<MODE>mode);
2169 operands[3] = gen_reg_rtx (<MODE>mode);
2170 operands[4] = gen_reg_rtx (<MODE>mode);
2171 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2172 })
2173
2174 (define_expand "ffs<mode>2"
2175 [(set (match_dup 2)
2176 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2177 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2178 (match_dup 2)))
2179 (clobber (scratch:CC))])
2180 (set (match_dup 4) (clz:GPR (match_dup 3)))
2181 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2182 (minus:GPR (match_dup 5) (match_dup 4)))]
2183 ""
2184 {
2185 operands[2] = gen_reg_rtx (<MODE>mode);
2186 operands[3] = gen_reg_rtx (<MODE>mode);
2187 operands[4] = gen_reg_rtx (<MODE>mode);
2188 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2189 })
2190
2191 (define_insn "popcntb<mode>2"
2192 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2193 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2194 UNSPEC_POPCNTB))]
2195 "TARGET_POPCNTB"
2196 "popcntb %0,%1")
2197
2198 (define_expand "popcount<mode>2"
2199 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2200 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2201 "TARGET_POPCNTB"
2202 {
2203 rs6000_emit_popcount (operands[0], operands[1]);
2204 DONE;
2205 })
2206
2207 (define_expand "parity<mode>2"
2208 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2209 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2210 "TARGET_POPCNTB"
2211 {
2212 rs6000_emit_parity (operands[0], operands[1]);
2213 DONE;
2214 })
2215
2216 (define_insn "bswapsi2"
2217 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2218 (bswap:SI (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2219 ""
2220 "@
2221 {lbrx|lwbrx} %0,%y1
2222 {stbrx|stwbrx} %1,%y0
2223 #"
2224 [(set_attr "length" "4,4,12")])
2225
2226 (define_split
2227 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2228 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2229 "reload_completed"
2230 [(set (match_dup 0)
2231 (rotate:SI (match_dup 1) (const_int 8)))
2232 (set (zero_extract:SI (match_dup 0)
2233 (const_int 8)
2234 (const_int 0))
2235 (match_dup 1))
2236 (set (zero_extract:SI (match_dup 0)
2237 (const_int 8)
2238 (const_int 16))
2239 (rotate:SI (match_dup 1)
2240 (const_int 16)))]
2241 "")
2242
2243 (define_expand "mulsi3"
2244 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2245 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2246 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2247 ""
2248 "
2249 {
2250 if (TARGET_POWER)
2251 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2252 else
2253 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2254 DONE;
2255 }")
2256
2257 (define_insn "mulsi3_mq"
2258 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2259 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2260 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2261 (clobber (match_scratch:SI 3 "=q,q"))]
2262 "TARGET_POWER"
2263 "@
2264 {muls|mullw} %0,%1,%2
2265 {muli|mulli} %0,%1,%2"
2266 [(set (attr "type")
2267 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2268 (const_string "imul3")
2269 (match_operand:SI 2 "short_cint_operand" "")
2270 (const_string "imul2")]
2271 (const_string "imul")))])
2272
2273 (define_insn "mulsi3_no_mq"
2274 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2275 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2276 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2277 "! TARGET_POWER"
2278 "@
2279 {muls|mullw} %0,%1,%2
2280 {muli|mulli} %0,%1,%2"
2281 [(set (attr "type")
2282 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2283 (const_string "imul3")
2284 (match_operand:SI 2 "short_cint_operand" "")
2285 (const_string "imul2")]
2286 (const_string "imul")))])
2287
2288 (define_insn "*mulsi3_mq_internal1"
2289 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2290 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2291 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2292 (const_int 0)))
2293 (clobber (match_scratch:SI 3 "=r,r"))
2294 (clobber (match_scratch:SI 4 "=q,q"))]
2295 "TARGET_POWER"
2296 "@
2297 {muls.|mullw.} %3,%1,%2
2298 #"
2299 [(set_attr "type" "imul_compare")
2300 (set_attr "length" "4,8")])
2301
2302 (define_split
2303 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2304 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2305 (match_operand:SI 2 "gpc_reg_operand" ""))
2306 (const_int 0)))
2307 (clobber (match_scratch:SI 3 ""))
2308 (clobber (match_scratch:SI 4 ""))]
2309 "TARGET_POWER && reload_completed"
2310 [(parallel [(set (match_dup 3)
2311 (mult:SI (match_dup 1) (match_dup 2)))
2312 (clobber (match_dup 4))])
2313 (set (match_dup 0)
2314 (compare:CC (match_dup 3)
2315 (const_int 0)))]
2316 "")
2317
2318 (define_insn "*mulsi3_no_mq_internal1"
2319 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2320 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2321 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2322 (const_int 0)))
2323 (clobber (match_scratch:SI 3 "=r,r"))]
2324 "! TARGET_POWER"
2325 "@
2326 {muls.|mullw.} %3,%1,%2
2327 #"
2328 [(set_attr "type" "imul_compare")
2329 (set_attr "length" "4,8")])
2330
2331 (define_split
2332 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2333 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2334 (match_operand:SI 2 "gpc_reg_operand" ""))
2335 (const_int 0)))
2336 (clobber (match_scratch:SI 3 ""))]
2337 "! TARGET_POWER && reload_completed"
2338 [(set (match_dup 3)
2339 (mult:SI (match_dup 1) (match_dup 2)))
2340 (set (match_dup 0)
2341 (compare:CC (match_dup 3)
2342 (const_int 0)))]
2343 "")
2344
2345 (define_insn "*mulsi3_mq_internal2"
2346 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2347 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2348 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2349 (const_int 0)))
2350 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2351 (mult:SI (match_dup 1) (match_dup 2)))
2352 (clobber (match_scratch:SI 4 "=q,q"))]
2353 "TARGET_POWER"
2354 "@
2355 {muls.|mullw.} %0,%1,%2
2356 #"
2357 [(set_attr "type" "imul_compare")
2358 (set_attr "length" "4,8")])
2359
2360 (define_split
2361 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2362 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2363 (match_operand:SI 2 "gpc_reg_operand" ""))
2364 (const_int 0)))
2365 (set (match_operand:SI 0 "gpc_reg_operand" "")
2366 (mult:SI (match_dup 1) (match_dup 2)))
2367 (clobber (match_scratch:SI 4 ""))]
2368 "TARGET_POWER && reload_completed"
2369 [(parallel [(set (match_dup 0)
2370 (mult:SI (match_dup 1) (match_dup 2)))
2371 (clobber (match_dup 4))])
2372 (set (match_dup 3)
2373 (compare:CC (match_dup 0)
2374 (const_int 0)))]
2375 "")
2376
2377 (define_insn "*mulsi3_no_mq_internal2"
2378 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2379 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2380 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2381 (const_int 0)))
2382 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2383 (mult:SI (match_dup 1) (match_dup 2)))]
2384 "! TARGET_POWER"
2385 "@
2386 {muls.|mullw.} %0,%1,%2
2387 #"
2388 [(set_attr "type" "imul_compare")
2389 (set_attr "length" "4,8")])
2390
2391 (define_split
2392 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2393 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2394 (match_operand:SI 2 "gpc_reg_operand" ""))
2395 (const_int 0)))
2396 (set (match_operand:SI 0 "gpc_reg_operand" "")
2397 (mult:SI (match_dup 1) (match_dup 2)))]
2398 "! TARGET_POWER && reload_completed"
2399 [(set (match_dup 0)
2400 (mult:SI (match_dup 1) (match_dup 2)))
2401 (set (match_dup 3)
2402 (compare:CC (match_dup 0)
2403 (const_int 0)))]
2404 "")
2405
2406 ;; Operand 1 is divided by operand 2; quotient goes to operand
2407 ;; 0 and remainder to operand 3.
2408 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2409
2410 (define_expand "divmodsi4"
2411 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2412 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2413 (match_operand:SI 2 "gpc_reg_operand" "")))
2414 (set (match_operand:SI 3 "register_operand" "")
2415 (mod:SI (match_dup 1) (match_dup 2)))])]
2416 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2417 "
2418 {
2419 if (! TARGET_POWER && ! TARGET_POWERPC)
2420 {
2421 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2422 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2423 emit_insn (gen_divss_call ());
2424 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2425 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2426 DONE;
2427 }
2428 }")
2429
2430 (define_insn "*divmodsi4_internal"
2431 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2432 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2433 (match_operand:SI 2 "gpc_reg_operand" "r")))
2434 (set (match_operand:SI 3 "register_operand" "=q")
2435 (mod:SI (match_dup 1) (match_dup 2)))]
2436 "TARGET_POWER"
2437 "divs %0,%1,%2"
2438 [(set_attr "type" "idiv")])
2439
2440 (define_expand "udiv<mode>3"
2441 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2442 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2443 (match_operand:GPR 2 "gpc_reg_operand" "")))]
2444 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2445 "
2446 {
2447 if (! TARGET_POWER && ! TARGET_POWERPC)
2448 {
2449 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2450 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2451 emit_insn (gen_quous_call ());
2452 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2453 DONE;
2454 }
2455 else if (TARGET_POWER)
2456 {
2457 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2458 DONE;
2459 }
2460 }")
2461
2462 (define_insn "udivsi3_mq"
2463 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2464 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2465 (match_operand:SI 2 "gpc_reg_operand" "r")))
2466 (clobber (match_scratch:SI 3 "=q"))]
2467 "TARGET_POWERPC && TARGET_POWER"
2468 "divwu %0,%1,%2"
2469 [(set_attr "type" "idiv")])
2470
2471 (define_insn "*udivsi3_no_mq"
2472 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2473 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2474 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2475 "TARGET_POWERPC && ! TARGET_POWER"
2476 "div<wd>u %0,%1,%2"
2477 [(set (attr "type")
2478 (cond [(match_operand:SI 0 "" "")
2479 (const_string "idiv")]
2480 (const_string "ldiv")))])
2481
2482
2483 ;; For powers of two we can do srai/aze for divide and then adjust for
2484 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2485 ;; used; for PowerPC, force operands into register and do a normal divide;
2486 ;; for AIX common-mode, use quoss call on register operands.
2487 (define_expand "div<mode>3"
2488 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2489 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2490 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2491 ""
2492 "
2493 {
2494 if (GET_CODE (operands[2]) == CONST_INT
2495 && INTVAL (operands[2]) > 0
2496 && exact_log2 (INTVAL (operands[2])) >= 0)
2497 ;
2498 else if (TARGET_POWERPC)
2499 {
2500 operands[2] = force_reg (<MODE>mode, operands[2]);
2501 if (TARGET_POWER)
2502 {
2503 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2504 DONE;
2505 }
2506 }
2507 else if (TARGET_POWER)
2508 FAIL;
2509 else
2510 {
2511 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2512 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2513 emit_insn (gen_quoss_call ());
2514 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2515 DONE;
2516 }
2517 }")
2518
2519 (define_insn "divsi3_mq"
2520 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2521 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2522 (match_operand:SI 2 "gpc_reg_operand" "r")))
2523 (clobber (match_scratch:SI 3 "=q"))]
2524 "TARGET_POWERPC && TARGET_POWER"
2525 "divw %0,%1,%2"
2526 [(set_attr "type" "idiv")])
2527
2528 (define_insn "*div<mode>3_no_mq"
2529 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2530 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2531 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2532 "TARGET_POWERPC && ! TARGET_POWER"
2533 "div<wd> %0,%1,%2"
2534 [(set (attr "type")
2535 (cond [(match_operand:SI 0 "" "")
2536 (const_string "idiv")]
2537 (const_string "ldiv")))])
2538
2539 (define_expand "mod<mode>3"
2540 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2541 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2542 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2543 ""
2544 "
2545 {
2546 int i;
2547 rtx temp1;
2548 rtx temp2;
2549
2550 if (GET_CODE (operands[2]) != CONST_INT
2551 || INTVAL (operands[2]) <= 0
2552 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2553 FAIL;
2554
2555 temp1 = gen_reg_rtx (<MODE>mode);
2556 temp2 = gen_reg_rtx (<MODE>mode);
2557
2558 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2559 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2560 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2561 DONE;
2562 }")
2563
2564 (define_insn ""
2565 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2566 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2567 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2568 ""
2569 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
2570 [(set_attr "type" "two")
2571 (set_attr "length" "8")])
2572
2573 (define_insn ""
2574 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2575 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2576 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2577 (const_int 0)))
2578 (clobber (match_scratch:P 3 "=r,r"))]
2579 ""
2580 "@
2581 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
2582 #"
2583 [(set_attr "type" "compare")
2584 (set_attr "length" "8,12")])
2585
2586 (define_split
2587 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2588 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2589 (match_operand:GPR 2 "exact_log2_cint_operand"
2590 ""))
2591 (const_int 0)))
2592 (clobber (match_scratch:GPR 3 ""))]
2593 "reload_completed"
2594 [(set (match_dup 3)
2595 (div:<MODE> (match_dup 1) (match_dup 2)))
2596 (set (match_dup 0)
2597 (compare:CC (match_dup 3)
2598 (const_int 0)))]
2599 "")
2600
2601 (define_insn ""
2602 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2603 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2604 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2605 (const_int 0)))
2606 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2607 (div:P (match_dup 1) (match_dup 2)))]
2608 ""
2609 "@
2610 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
2611 #"
2612 [(set_attr "type" "compare")
2613 (set_attr "length" "8,12")])
2614
2615 (define_split
2616 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2617 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2618 (match_operand:GPR 2 "exact_log2_cint_operand"
2619 ""))
2620 (const_int 0)))
2621 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2622 (div:GPR (match_dup 1) (match_dup 2)))]
2623 "reload_completed"
2624 [(set (match_dup 0)
2625 (div:<MODE> (match_dup 1) (match_dup 2)))
2626 (set (match_dup 3)
2627 (compare:CC (match_dup 0)
2628 (const_int 0)))]
2629 "")
2630
2631 (define_insn ""
2632 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2633 (udiv:SI
2634 (plus:DI (ashift:DI
2635 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2636 (const_int 32))
2637 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2638 (match_operand:SI 3 "gpc_reg_operand" "r")))
2639 (set (match_operand:SI 2 "register_operand" "=*q")
2640 (umod:SI
2641 (plus:DI (ashift:DI
2642 (zero_extend:DI (match_dup 1)) (const_int 32))
2643 (zero_extend:DI (match_dup 4)))
2644 (match_dup 3)))]
2645 "TARGET_POWER"
2646 "div %0,%1,%3"
2647 [(set_attr "type" "idiv")])
2648
2649 ;; To do unsigned divide we handle the cases of the divisor looking like a
2650 ;; negative number. If it is a constant that is less than 2**31, we don't
2651 ;; have to worry about the branches. So make a few subroutines here.
2652 ;;
2653 ;; First comes the normal case.
2654 (define_expand "udivmodsi4_normal"
2655 [(set (match_dup 4) (const_int 0))
2656 (parallel [(set (match_operand:SI 0 "" "")
2657 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2658 (const_int 32))
2659 (zero_extend:DI (match_operand:SI 1 "" "")))
2660 (match_operand:SI 2 "" "")))
2661 (set (match_operand:SI 3 "" "")
2662 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2663 (const_int 32))
2664 (zero_extend:DI (match_dup 1)))
2665 (match_dup 2)))])]
2666 "TARGET_POWER"
2667 "
2668 { operands[4] = gen_reg_rtx (SImode); }")
2669
2670 ;; This handles the branches.
2671 (define_expand "udivmodsi4_tests"
2672 [(set (match_operand:SI 0 "" "") (const_int 0))
2673 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2674 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2675 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2676 (label_ref (match_operand:SI 4 "" "")) (pc)))
2677 (set (match_dup 0) (const_int 1))
2678 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2679 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2680 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2681 (label_ref (match_dup 4)) (pc)))]
2682 "TARGET_POWER"
2683 "
2684 { operands[5] = gen_reg_rtx (CCUNSmode);
2685 operands[6] = gen_reg_rtx (CCmode);
2686 }")
2687
2688 (define_expand "udivmodsi4"
2689 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2690 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2691 (match_operand:SI 2 "reg_or_cint_operand" "")))
2692 (set (match_operand:SI 3 "gpc_reg_operand" "")
2693 (umod:SI (match_dup 1) (match_dup 2)))])]
2694 ""
2695 "
2696 {
2697 rtx label = 0;
2698
2699 if (! TARGET_POWER)
2700 {
2701 if (! TARGET_POWERPC)
2702 {
2703 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2704 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2705 emit_insn (gen_divus_call ());
2706 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2707 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2708 DONE;
2709 }
2710 else
2711 FAIL;
2712 }
2713
2714 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2715 {
2716 operands[2] = force_reg (SImode, operands[2]);
2717 label = gen_label_rtx ();
2718 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2719 operands[3], label));
2720 }
2721 else
2722 operands[2] = force_reg (SImode, operands[2]);
2723
2724 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2725 operands[3]));
2726 if (label)
2727 emit_label (label);
2728
2729 DONE;
2730 }")
2731
2732 ;; AIX architecture-independent common-mode multiply (DImode),
2733 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2734 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2735 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2736 ;; assumed unused if generating common-mode, so ignore.
2737 (define_insn "mulh_call"
2738 [(set (reg:SI 3)
2739 (truncate:SI
2740 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2741 (sign_extend:DI (reg:SI 4)))
2742 (const_int 32))))
2743 (clobber (reg:SI LR_REGNO))]
2744 "! TARGET_POWER && ! TARGET_POWERPC"
2745 "bla __mulh"
2746 [(set_attr "type" "imul")])
2747
2748 (define_insn "mull_call"
2749 [(set (reg:DI 3)
2750 (mult:DI (sign_extend:DI (reg:SI 3))
2751 (sign_extend:DI (reg:SI 4))))
2752 (clobber (reg:SI LR_REGNO))
2753 (clobber (reg:SI 0))]
2754 "! TARGET_POWER && ! TARGET_POWERPC"
2755 "bla __mull"
2756 [(set_attr "type" "imul")])
2757
2758 (define_insn "divss_call"
2759 [(set (reg:SI 3)
2760 (div:SI (reg:SI 3) (reg:SI 4)))
2761 (set (reg:SI 4)
2762 (mod:SI (reg:SI 3) (reg:SI 4)))
2763 (clobber (reg:SI LR_REGNO))
2764 (clobber (reg:SI 0))]
2765 "! TARGET_POWER && ! TARGET_POWERPC"
2766 "bla __divss"
2767 [(set_attr "type" "idiv")])
2768
2769 (define_insn "divus_call"
2770 [(set (reg:SI 3)
2771 (udiv:SI (reg:SI 3) (reg:SI 4)))
2772 (set (reg:SI 4)
2773 (umod:SI (reg:SI 3) (reg:SI 4)))
2774 (clobber (reg:SI LR_REGNO))
2775 (clobber (reg:SI 0))
2776 (clobber (match_scratch:CC 0 "=x"))
2777 (clobber (reg:CC CR1_REGNO))]
2778 "! TARGET_POWER && ! TARGET_POWERPC"
2779 "bla __divus"
2780 [(set_attr "type" "idiv")])
2781
2782 (define_insn "quoss_call"
2783 [(set (reg:SI 3)
2784 (div:SI (reg:SI 3) (reg:SI 4)))
2785 (clobber (reg:SI LR_REGNO))]
2786 "! TARGET_POWER && ! TARGET_POWERPC"
2787 "bla __quoss"
2788 [(set_attr "type" "idiv")])
2789
2790 (define_insn "quous_call"
2791 [(set (reg:SI 3)
2792 (udiv:SI (reg:SI 3) (reg:SI 4)))
2793 (clobber (reg:SI LR_REGNO))
2794 (clobber (reg:SI 0))
2795 (clobber (match_scratch:CC 0 "=x"))
2796 (clobber (reg:CC CR1_REGNO))]
2797 "! TARGET_POWER && ! TARGET_POWERPC"
2798 "bla __quous"
2799 [(set_attr "type" "idiv")])
2800 \f
2801 ;; Logical instructions
2802 ;; The logical instructions are mostly combined by using match_operator,
2803 ;; but the plain AND insns are somewhat different because there is no
2804 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2805 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2806
2807 (define_insn "andsi3"
2808 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2809 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2810 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2811 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2812 ""
2813 "@
2814 and %0,%1,%2
2815 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2816 {andil.|andi.} %0,%1,%b2
2817 {andiu.|andis.} %0,%1,%u2"
2818 [(set_attr "type" "*,*,compare,compare")])
2819
2820 ;; Note to set cr's other than cr0 we do the and immediate and then
2821 ;; the test again -- this avoids a mfcr which on the higher end
2822 ;; machines causes an execution serialization
2823
2824 (define_insn "*andsi3_internal2"
2825 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2826 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2827 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2828 (const_int 0)))
2829 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2830 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2831 "TARGET_32BIT"
2832 "@
2833 and. %3,%1,%2
2834 {andil.|andi.} %3,%1,%b2
2835 {andiu.|andis.} %3,%1,%u2
2836 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2837 #
2838 #
2839 #
2840 #"
2841 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2842 (set_attr "length" "4,4,4,4,8,8,8,8")])
2843
2844 (define_insn "*andsi3_internal3"
2845 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2846 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2847 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2848 (const_int 0)))
2849 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2850 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2851 "TARGET_64BIT"
2852 "@
2853 #
2854 {andil.|andi.} %3,%1,%b2
2855 {andiu.|andis.} %3,%1,%u2
2856 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2857 #
2858 #
2859 #
2860 #"
2861 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2862 (set_attr "length" "8,4,4,4,8,8,8,8")])
2863
2864 (define_split
2865 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2866 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2867 (match_operand:GPR 2 "and_operand" ""))
2868 (const_int 0)))
2869 (clobber (match_scratch:GPR 3 ""))
2870 (clobber (match_scratch:CC 4 ""))]
2871 "reload_completed"
2872 [(parallel [(set (match_dup 3)
2873 (and:<MODE> (match_dup 1)
2874 (match_dup 2)))
2875 (clobber (match_dup 4))])
2876 (set (match_dup 0)
2877 (compare:CC (match_dup 3)
2878 (const_int 0)))]
2879 "")
2880
2881 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2882 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2883
2884 (define_split
2885 [(set (match_operand:CC 0 "cc_reg_operand" "")
2886 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2887 (match_operand:SI 2 "gpc_reg_operand" ""))
2888 (const_int 0)))
2889 (clobber (match_scratch:SI 3 ""))
2890 (clobber (match_scratch:CC 4 ""))]
2891 "TARGET_POWERPC64 && reload_completed"
2892 [(parallel [(set (match_dup 3)
2893 (and:SI (match_dup 1)
2894 (match_dup 2)))
2895 (clobber (match_dup 4))])
2896 (set (match_dup 0)
2897 (compare:CC (match_dup 3)
2898 (const_int 0)))]
2899 "")
2900
2901 (define_insn "*andsi3_internal4"
2902 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2903 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2904 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2905 (const_int 0)))
2906 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2907 (and:SI (match_dup 1)
2908 (match_dup 2)))
2909 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2910 "TARGET_32BIT"
2911 "@
2912 and. %0,%1,%2
2913 {andil.|andi.} %0,%1,%b2
2914 {andiu.|andis.} %0,%1,%u2
2915 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2916 #
2917 #
2918 #
2919 #"
2920 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2921 (set_attr "length" "4,4,4,4,8,8,8,8")])
2922
2923 (define_insn "*andsi3_internal5"
2924 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2925 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2926 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2927 (const_int 0)))
2928 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2929 (and:SI (match_dup 1)
2930 (match_dup 2)))
2931 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2932 "TARGET_64BIT"
2933 "@
2934 #
2935 {andil.|andi.} %0,%1,%b2
2936 {andiu.|andis.} %0,%1,%u2
2937 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2938 #
2939 #
2940 #
2941 #"
2942 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2943 (set_attr "length" "8,4,4,4,8,8,8,8")])
2944
2945 (define_split
2946 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2947 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2948 (match_operand:SI 2 "and_operand" ""))
2949 (const_int 0)))
2950 (set (match_operand:SI 0 "gpc_reg_operand" "")
2951 (and:SI (match_dup 1)
2952 (match_dup 2)))
2953 (clobber (match_scratch:CC 4 ""))]
2954 "reload_completed"
2955 [(parallel [(set (match_dup 0)
2956 (and:SI (match_dup 1)
2957 (match_dup 2)))
2958 (clobber (match_dup 4))])
2959 (set (match_dup 3)
2960 (compare:CC (match_dup 0)
2961 (const_int 0)))]
2962 "")
2963
2964 (define_split
2965 [(set (match_operand:CC 3 "cc_reg_operand" "")
2966 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2967 (match_operand:SI 2 "gpc_reg_operand" ""))
2968 (const_int 0)))
2969 (set (match_operand:SI 0 "gpc_reg_operand" "")
2970 (and:SI (match_dup 1)
2971 (match_dup 2)))
2972 (clobber (match_scratch:CC 4 ""))]
2973 "TARGET_POWERPC64 && reload_completed"
2974 [(parallel [(set (match_dup 0)
2975 (and:SI (match_dup 1)
2976 (match_dup 2)))
2977 (clobber (match_dup 4))])
2978 (set (match_dup 3)
2979 (compare:CC (match_dup 0)
2980 (const_int 0)))]
2981 "")
2982
2983 ;; Handle the PowerPC64 rlwinm corner case
2984
2985 (define_insn_and_split "*andsi3_internal6"
2986 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2987 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2988 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2989 "TARGET_POWERPC64"
2990 "#"
2991 "TARGET_POWERPC64"
2992 [(set (match_dup 0)
2993 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2994 (match_dup 4)))
2995 (set (match_dup 0)
2996 (rotate:SI (match_dup 0) (match_dup 5)))]
2997 "
2998 {
2999 int mb = extract_MB (operands[2]);
3000 int me = extract_ME (operands[2]);
3001 operands[3] = GEN_INT (me + 1);
3002 operands[5] = GEN_INT (32 - (me + 1));
3003 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3004 }"
3005 [(set_attr "length" "8")])
3006
3007 (define_expand "iorsi3"
3008 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3009 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
3010 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3011 ""
3012 "
3013 {
3014 if (GET_CODE (operands[2]) == CONST_INT
3015 && ! logical_operand (operands[2], SImode))
3016 {
3017 HOST_WIDE_INT value = INTVAL (operands[2]);
3018 rtx tmp = ((!can_create_pseudo_p ()
3019 || rtx_equal_p (operands[0], operands[1]))
3020 ? operands[0] : gen_reg_rtx (SImode));
3021
3022 emit_insn (gen_iorsi3 (tmp, operands[1],
3023 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3024 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3025 DONE;
3026 }
3027 }")
3028
3029 (define_expand "xorsi3"
3030 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3031 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3032 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3033 ""
3034 "
3035 {
3036 if (GET_CODE (operands[2]) == CONST_INT
3037 && ! logical_operand (operands[2], SImode))
3038 {
3039 HOST_WIDE_INT value = INTVAL (operands[2]);
3040 rtx tmp = ((!can_create_pseudo_p ()
3041 || rtx_equal_p (operands[0], operands[1]))
3042 ? operands[0] : gen_reg_rtx (SImode));
3043
3044 emit_insn (gen_xorsi3 (tmp, operands[1],
3045 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3046 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3047 DONE;
3048 }
3049 }")
3050
3051 (define_insn "*boolsi3_internal1"
3052 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3053 (match_operator:SI 3 "boolean_or_operator"
3054 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3055 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3056 ""
3057 "@
3058 %q3 %0,%1,%2
3059 {%q3il|%q3i} %0,%1,%b2
3060 {%q3iu|%q3is} %0,%1,%u2")
3061
3062 (define_insn "*boolsi3_internal2"
3063 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3064 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3065 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3066 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3067 (const_int 0)))
3068 (clobber (match_scratch:SI 3 "=r,r"))]
3069 "TARGET_32BIT"
3070 "@
3071 %q4. %3,%1,%2
3072 #"
3073 [(set_attr "type" "compare")
3074 (set_attr "length" "4,8")])
3075
3076 (define_split
3077 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3078 (compare:CC (match_operator:SI 4 "boolean_operator"
3079 [(match_operand:SI 1 "gpc_reg_operand" "")
3080 (match_operand:SI 2 "gpc_reg_operand" "")])
3081 (const_int 0)))
3082 (clobber (match_scratch:SI 3 ""))]
3083 "TARGET_32BIT && reload_completed"
3084 [(set (match_dup 3) (match_dup 4))
3085 (set (match_dup 0)
3086 (compare:CC (match_dup 3)
3087 (const_int 0)))]
3088 "")
3089
3090 (define_insn "*boolsi3_internal3"
3091 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3092 (compare:CC (match_operator:SI 4 "boolean_operator"
3093 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3094 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3095 (const_int 0)))
3096 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3097 (match_dup 4))]
3098 "TARGET_32BIT"
3099 "@
3100 %q4. %0,%1,%2
3101 #"
3102 [(set_attr "type" "compare")
3103 (set_attr "length" "4,8")])
3104
3105 (define_split
3106 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3107 (compare:CC (match_operator:SI 4 "boolean_operator"
3108 [(match_operand:SI 1 "gpc_reg_operand" "")
3109 (match_operand:SI 2 "gpc_reg_operand" "")])
3110 (const_int 0)))
3111 (set (match_operand:SI 0 "gpc_reg_operand" "")
3112 (match_dup 4))]
3113 "TARGET_32BIT && reload_completed"
3114 [(set (match_dup 0) (match_dup 4))
3115 (set (match_dup 3)
3116 (compare:CC (match_dup 0)
3117 (const_int 0)))]
3118 "")
3119
3120 ;; Split a logical operation that we can't do in one insn into two insns,
3121 ;; each of which does one 16-bit part. This is used by combine.
3122
3123 (define_split
3124 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3125 (match_operator:SI 3 "boolean_or_operator"
3126 [(match_operand:SI 1 "gpc_reg_operand" "")
3127 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3128 ""
3129 [(set (match_dup 0) (match_dup 4))
3130 (set (match_dup 0) (match_dup 5))]
3131 "
3132 {
3133 rtx i;
3134 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3135 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3136 operands[1], i);
3137 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3138 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3139 operands[0], i);
3140 }")
3141
3142 (define_insn "*boolcsi3_internal1"
3143 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3144 (match_operator:SI 3 "boolean_operator"
3145 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3146 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3147 ""
3148 "%q3 %0,%2,%1")
3149
3150 (define_insn "*boolcsi3_internal2"
3151 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3152 (compare:CC (match_operator:SI 4 "boolean_operator"
3153 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3154 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3155 (const_int 0)))
3156 (clobber (match_scratch:SI 3 "=r,r"))]
3157 "TARGET_32BIT"
3158 "@
3159 %q4. %3,%2,%1
3160 #"
3161 [(set_attr "type" "compare")
3162 (set_attr "length" "4,8")])
3163
3164 (define_split
3165 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3166 (compare:CC (match_operator:SI 4 "boolean_operator"
3167 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3168 (match_operand:SI 2 "gpc_reg_operand" "")])
3169 (const_int 0)))
3170 (clobber (match_scratch:SI 3 ""))]
3171 "TARGET_32BIT && reload_completed"
3172 [(set (match_dup 3) (match_dup 4))
3173 (set (match_dup 0)
3174 (compare:CC (match_dup 3)
3175 (const_int 0)))]
3176 "")
3177
3178 (define_insn "*boolcsi3_internal3"
3179 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3180 (compare:CC (match_operator:SI 4 "boolean_operator"
3181 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3182 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3183 (const_int 0)))
3184 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3185 (match_dup 4))]
3186 "TARGET_32BIT"
3187 "@
3188 %q4. %0,%2,%1
3189 #"
3190 [(set_attr "type" "compare")
3191 (set_attr "length" "4,8")])
3192
3193 (define_split
3194 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3195 (compare:CC (match_operator:SI 4 "boolean_operator"
3196 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3197 (match_operand:SI 2 "gpc_reg_operand" "")])
3198 (const_int 0)))
3199 (set (match_operand:SI 0 "gpc_reg_operand" "")
3200 (match_dup 4))]
3201 "TARGET_32BIT && reload_completed"
3202 [(set (match_dup 0) (match_dup 4))
3203 (set (match_dup 3)
3204 (compare:CC (match_dup 0)
3205 (const_int 0)))]
3206 "")
3207
3208 (define_insn "*boolccsi3_internal1"
3209 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3210 (match_operator:SI 3 "boolean_operator"
3211 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3212 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3213 ""
3214 "%q3 %0,%1,%2")
3215
3216 (define_insn "*boolccsi3_internal2"
3217 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3218 (compare:CC (match_operator:SI 4 "boolean_operator"
3219 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3220 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3221 (const_int 0)))
3222 (clobber (match_scratch:SI 3 "=r,r"))]
3223 "TARGET_32BIT"
3224 "@
3225 %q4. %3,%1,%2
3226 #"
3227 [(set_attr "type" "compare")
3228 (set_attr "length" "4,8")])
3229
3230 (define_split
3231 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3232 (compare:CC (match_operator:SI 4 "boolean_operator"
3233 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3234 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3235 (const_int 0)))
3236 (clobber (match_scratch:SI 3 ""))]
3237 "TARGET_32BIT && reload_completed"
3238 [(set (match_dup 3) (match_dup 4))
3239 (set (match_dup 0)
3240 (compare:CC (match_dup 3)
3241 (const_int 0)))]
3242 "")
3243
3244 (define_insn "*boolccsi3_internal3"
3245 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3246 (compare:CC (match_operator:SI 4 "boolean_operator"
3247 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3248 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3249 (const_int 0)))
3250 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3251 (match_dup 4))]
3252 "TARGET_32BIT"
3253 "@
3254 %q4. %0,%1,%2
3255 #"
3256 [(set_attr "type" "compare")
3257 (set_attr "length" "4,8")])
3258
3259 (define_split
3260 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3261 (compare:CC (match_operator:SI 4 "boolean_operator"
3262 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3263 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3264 (const_int 0)))
3265 (set (match_operand:SI 0 "gpc_reg_operand" "")
3266 (match_dup 4))]
3267 "TARGET_32BIT && reload_completed"
3268 [(set (match_dup 0) (match_dup 4))
3269 (set (match_dup 3)
3270 (compare:CC (match_dup 0)
3271 (const_int 0)))]
3272 "")
3273
3274 ;; maskir insn. We need four forms because things might be in arbitrary
3275 ;; orders. Don't define forms that only set CR fields because these
3276 ;; would modify an input register.
3277
3278 (define_insn "*maskir_internal1"
3279 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3280 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3281 (match_operand:SI 1 "gpc_reg_operand" "0"))
3282 (and:SI (match_dup 2)
3283 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3284 "TARGET_POWER"
3285 "maskir %0,%3,%2")
3286
3287 (define_insn "*maskir_internal2"
3288 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3289 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3290 (match_operand:SI 1 "gpc_reg_operand" "0"))
3291 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3292 (match_dup 2))))]
3293 "TARGET_POWER"
3294 "maskir %0,%3,%2")
3295
3296 (define_insn "*maskir_internal3"
3297 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3298 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3299 (match_operand:SI 3 "gpc_reg_operand" "r"))
3300 (and:SI (not:SI (match_dup 2))
3301 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3302 "TARGET_POWER"
3303 "maskir %0,%3,%2")
3304
3305 (define_insn "*maskir_internal4"
3306 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3307 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3308 (match_operand:SI 2 "gpc_reg_operand" "r"))
3309 (and:SI (not:SI (match_dup 2))
3310 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3311 "TARGET_POWER"
3312 "maskir %0,%3,%2")
3313
3314 (define_insn "*maskir_internal5"
3315 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3316 (compare:CC
3317 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3318 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3319 (and:SI (match_dup 2)
3320 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3321 (const_int 0)))
3322 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3323 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3324 (and:SI (match_dup 2) (match_dup 3))))]
3325 "TARGET_POWER"
3326 "@
3327 maskir. %0,%3,%2
3328 #"
3329 [(set_attr "type" "compare")
3330 (set_attr "length" "4,8")])
3331
3332 (define_split
3333 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3334 (compare:CC
3335 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3336 (match_operand:SI 1 "gpc_reg_operand" ""))
3337 (and:SI (match_dup 2)
3338 (match_operand:SI 3 "gpc_reg_operand" "")))
3339 (const_int 0)))
3340 (set (match_operand:SI 0 "gpc_reg_operand" "")
3341 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3342 (and:SI (match_dup 2) (match_dup 3))))]
3343 "TARGET_POWER && reload_completed"
3344 [(set (match_dup 0)
3345 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3346 (and:SI (match_dup 2) (match_dup 3))))
3347 (set (match_dup 4)
3348 (compare:CC (match_dup 0)
3349 (const_int 0)))]
3350 "")
3351
3352 (define_insn "*maskir_internal6"
3353 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3354 (compare:CC
3355 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3356 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3357 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3358 (match_dup 2)))
3359 (const_int 0)))
3360 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3361 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3362 (and:SI (match_dup 3) (match_dup 2))))]
3363 "TARGET_POWER"
3364 "@
3365 maskir. %0,%3,%2
3366 #"
3367 [(set_attr "type" "compare")
3368 (set_attr "length" "4,8")])
3369
3370 (define_split
3371 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3372 (compare:CC
3373 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3374 (match_operand:SI 1 "gpc_reg_operand" ""))
3375 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3376 (match_dup 2)))
3377 (const_int 0)))
3378 (set (match_operand:SI 0 "gpc_reg_operand" "")
3379 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3380 (and:SI (match_dup 3) (match_dup 2))))]
3381 "TARGET_POWER && reload_completed"
3382 [(set (match_dup 0)
3383 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3384 (and:SI (match_dup 3) (match_dup 2))))
3385 (set (match_dup 4)
3386 (compare:CC (match_dup 0)
3387 (const_int 0)))]
3388 "")
3389
3390 (define_insn "*maskir_internal7"
3391 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3392 (compare:CC
3393 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3394 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3395 (and:SI (not:SI (match_dup 2))
3396 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3397 (const_int 0)))
3398 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3399 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3400 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3401 "TARGET_POWER"
3402 "@
3403 maskir. %0,%3,%2
3404 #"
3405 [(set_attr "type" "compare")
3406 (set_attr "length" "4,8")])
3407
3408 (define_split
3409 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3410 (compare:CC
3411 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3412 (match_operand:SI 3 "gpc_reg_operand" ""))
3413 (and:SI (not:SI (match_dup 2))
3414 (match_operand:SI 1 "gpc_reg_operand" "")))
3415 (const_int 0)))
3416 (set (match_operand:SI 0 "gpc_reg_operand" "")
3417 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3418 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3419 "TARGET_POWER && reload_completed"
3420 [(set (match_dup 0)
3421 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3422 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3423 (set (match_dup 4)
3424 (compare:CC (match_dup 0)
3425 (const_int 0)))]
3426 "")
3427
3428 (define_insn "*maskir_internal8"
3429 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3430 (compare:CC
3431 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3432 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3433 (and:SI (not:SI (match_dup 2))
3434 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3435 (const_int 0)))
3436 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3437 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3438 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3439 "TARGET_POWER"
3440 "@
3441 maskir. %0,%3,%2
3442 #"
3443 [(set_attr "type" "compare")
3444 (set_attr "length" "4,8")])
3445
3446 (define_split
3447 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3448 (compare:CC
3449 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3450 (match_operand:SI 2 "gpc_reg_operand" ""))
3451 (and:SI (not:SI (match_dup 2))
3452 (match_operand:SI 1 "gpc_reg_operand" "")))
3453 (const_int 0)))
3454 (set (match_operand:SI 0 "gpc_reg_operand" "")
3455 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3456 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3457 "TARGET_POWER && reload_completed"
3458 [(set (match_dup 0)
3459 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3460 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3461 (set (match_dup 4)
3462 (compare:CC (match_dup 0)
3463 (const_int 0)))]
3464 "")
3465 \f
3466 ;; Rotate and shift insns, in all their variants. These support shifts,
3467 ;; field inserts and extracts, and various combinations thereof.
3468 (define_expand "insv"
3469 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3470 (match_operand:SI 1 "const_int_operand" "")
3471 (match_operand:SI 2 "const_int_operand" ""))
3472 (match_operand 3 "gpc_reg_operand" ""))]
3473 ""
3474 "
3475 {
3476 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3477 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3478 compiler if the address of the structure is taken later. Likewise, do
3479 not handle invalid E500 subregs. */
3480 if (GET_CODE (operands[0]) == SUBREG
3481 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3482 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3483 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3484 FAIL;
3485
3486 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3487 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3488 else
3489 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3490 DONE;
3491 }")
3492
3493 (define_insn "insvsi"
3494 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3495 (match_operand:SI 1 "const_int_operand" "i")
3496 (match_operand:SI 2 "const_int_operand" "i"))
3497 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3498 ""
3499 "*
3500 {
3501 int start = INTVAL (operands[2]) & 31;
3502 int size = INTVAL (operands[1]) & 31;
3503
3504 operands[4] = GEN_INT (32 - start - size);
3505 operands[1] = GEN_INT (start + size - 1);
3506 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3507 }"
3508 [(set_attr "type" "insert_word")])
3509
3510 (define_insn "*insvsi_internal1"
3511 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3512 (match_operand:SI 1 "const_int_operand" "i")
3513 (match_operand:SI 2 "const_int_operand" "i"))
3514 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3515 (match_operand:SI 4 "const_int_operand" "i")))]
3516 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3517 "*
3518 {
3519 int shift = INTVAL (operands[4]) & 31;
3520 int start = INTVAL (operands[2]) & 31;
3521 int size = INTVAL (operands[1]) & 31;
3522
3523 operands[4] = GEN_INT (shift - start - size);
3524 operands[1] = GEN_INT (start + size - 1);
3525 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3526 }"
3527 [(set_attr "type" "insert_word")])
3528
3529 (define_insn "*insvsi_internal2"
3530 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3531 (match_operand:SI 1 "const_int_operand" "i")
3532 (match_operand:SI 2 "const_int_operand" "i"))
3533 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3534 (match_operand:SI 4 "const_int_operand" "i")))]
3535 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3536 "*
3537 {
3538 int shift = INTVAL (operands[4]) & 31;
3539 int start = INTVAL (operands[2]) & 31;
3540 int size = INTVAL (operands[1]) & 31;
3541
3542 operands[4] = GEN_INT (32 - shift - start - size);
3543 operands[1] = GEN_INT (start + size - 1);
3544 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3545 }"
3546 [(set_attr "type" "insert_word")])
3547
3548 (define_insn "*insvsi_internal3"
3549 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3550 (match_operand:SI 1 "const_int_operand" "i")
3551 (match_operand:SI 2 "const_int_operand" "i"))
3552 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3553 (match_operand:SI 4 "const_int_operand" "i")))]
3554 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3555 "*
3556 {
3557 int shift = INTVAL (operands[4]) & 31;
3558 int start = INTVAL (operands[2]) & 31;
3559 int size = INTVAL (operands[1]) & 31;
3560
3561 operands[4] = GEN_INT (32 - shift - start - size);
3562 operands[1] = GEN_INT (start + size - 1);
3563 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3564 }"
3565 [(set_attr "type" "insert_word")])
3566
3567 (define_insn "*insvsi_internal4"
3568 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3569 (match_operand:SI 1 "const_int_operand" "i")
3570 (match_operand:SI 2 "const_int_operand" "i"))
3571 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3572 (match_operand:SI 4 "const_int_operand" "i")
3573 (match_operand:SI 5 "const_int_operand" "i")))]
3574 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3575 "*
3576 {
3577 int extract_start = INTVAL (operands[5]) & 31;
3578 int extract_size = INTVAL (operands[4]) & 31;
3579 int insert_start = INTVAL (operands[2]) & 31;
3580 int insert_size = INTVAL (operands[1]) & 31;
3581
3582 /* Align extract field with insert field */
3583 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3584 operands[1] = GEN_INT (insert_start + insert_size - 1);
3585 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3586 }"
3587 [(set_attr "type" "insert_word")])
3588
3589 ;; combine patterns for rlwimi
3590 (define_insn "*insvsi_internal5"
3591 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3592 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3593 (match_operand:SI 1 "mask_operand" "i"))
3594 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3595 (match_operand:SI 2 "const_int_operand" "i"))
3596 (match_operand:SI 5 "mask_operand" "i"))))]
3597 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3598 "*
3599 {
3600 int me = extract_ME(operands[5]);
3601 int mb = extract_MB(operands[5]);
3602 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3603 operands[2] = GEN_INT(mb);
3604 operands[1] = GEN_INT(me);
3605 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3606 }"
3607 [(set_attr "type" "insert_word")])
3608
3609 (define_insn "*insvsi_internal6"
3610 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3611 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3612 (match_operand:SI 2 "const_int_operand" "i"))
3613 (match_operand:SI 5 "mask_operand" "i"))
3614 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3615 (match_operand:SI 1 "mask_operand" "i"))))]
3616 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3617 "*
3618 {
3619 int me = extract_ME(operands[5]);
3620 int mb = extract_MB(operands[5]);
3621 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3622 operands[2] = GEN_INT(mb);
3623 operands[1] = GEN_INT(me);
3624 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3625 }"
3626 [(set_attr "type" "insert_word")])
3627
3628 (define_insn "insvdi"
3629 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3630 (match_operand:SI 1 "const_int_operand" "i")
3631 (match_operand:SI 2 "const_int_operand" "i"))
3632 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3633 "TARGET_POWERPC64"
3634 "*
3635 {
3636 int start = INTVAL (operands[2]) & 63;
3637 int size = INTVAL (operands[1]) & 63;
3638
3639 operands[1] = GEN_INT (64 - start - size);
3640 return \"rldimi %0,%3,%H1,%H2\";
3641 }"
3642 [(set_attr "type" "insert_dword")])
3643
3644 (define_insn "*insvdi_internal2"
3645 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3646 (match_operand:SI 1 "const_int_operand" "i")
3647 (match_operand:SI 2 "const_int_operand" "i"))
3648 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3649 (match_operand:SI 4 "const_int_operand" "i")))]
3650 "TARGET_POWERPC64
3651 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3652 "*
3653 {
3654 int shift = INTVAL (operands[4]) & 63;
3655 int start = (INTVAL (operands[2]) & 63) - 32;
3656 int size = INTVAL (operands[1]) & 63;
3657
3658 operands[4] = GEN_INT (64 - shift - start - size);
3659 operands[2] = GEN_INT (start);
3660 operands[1] = GEN_INT (start + size - 1);
3661 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3662 }")
3663
3664 (define_insn "*insvdi_internal3"
3665 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3666 (match_operand:SI 1 "const_int_operand" "i")
3667 (match_operand:SI 2 "const_int_operand" "i"))
3668 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3669 (match_operand:SI 4 "const_int_operand" "i")))]
3670 "TARGET_POWERPC64
3671 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3672 "*
3673 {
3674 int shift = INTVAL (operands[4]) & 63;
3675 int start = (INTVAL (operands[2]) & 63) - 32;
3676 int size = INTVAL (operands[1]) & 63;
3677
3678 operands[4] = GEN_INT (64 - shift - start - size);
3679 operands[2] = GEN_INT (start);
3680 operands[1] = GEN_INT (start + size - 1);
3681 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3682 }")
3683
3684 (define_expand "extzv"
3685 [(set (match_operand 0 "gpc_reg_operand" "")
3686 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3687 (match_operand:SI 2 "const_int_operand" "")
3688 (match_operand:SI 3 "const_int_operand" "")))]
3689 ""
3690 "
3691 {
3692 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3693 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3694 compiler if the address of the structure is taken later. */
3695 if (GET_CODE (operands[0]) == SUBREG
3696 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3697 FAIL;
3698
3699 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3700 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3701 else
3702 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3703 DONE;
3704 }")
3705
3706 (define_insn "extzvsi"
3707 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3708 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3709 (match_operand:SI 2 "const_int_operand" "i")
3710 (match_operand:SI 3 "const_int_operand" "i")))]
3711 ""
3712 "*
3713 {
3714 int start = INTVAL (operands[3]) & 31;
3715 int size = INTVAL (operands[2]) & 31;
3716
3717 if (start + size >= 32)
3718 operands[3] = const0_rtx;
3719 else
3720 operands[3] = GEN_INT (start + size);
3721 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3722 }")
3723
3724 (define_insn "*extzvsi_internal1"
3725 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3726 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3727 (match_operand:SI 2 "const_int_operand" "i,i")
3728 (match_operand:SI 3 "const_int_operand" "i,i"))
3729 (const_int 0)))
3730 (clobber (match_scratch:SI 4 "=r,r"))]
3731 ""
3732 "*
3733 {
3734 int start = INTVAL (operands[3]) & 31;
3735 int size = INTVAL (operands[2]) & 31;
3736
3737 /* Force split for non-cc0 compare. */
3738 if (which_alternative == 1)
3739 return \"#\";
3740
3741 /* If the bit-field being tested fits in the upper or lower half of a
3742 word, it is possible to use andiu. or andil. to test it. This is
3743 useful because the condition register set-use delay is smaller for
3744 andi[ul]. than for rlinm. This doesn't work when the starting bit
3745 position is 0 because the LT and GT bits may be set wrong. */
3746
3747 if ((start > 0 && start + size <= 16) || start >= 16)
3748 {
3749 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3750 - (1 << (16 - (start & 15) - size))));
3751 if (start < 16)
3752 return \"{andiu.|andis.} %4,%1,%3\";
3753 else
3754 return \"{andil.|andi.} %4,%1,%3\";
3755 }
3756
3757 if (start + size >= 32)
3758 operands[3] = const0_rtx;
3759 else
3760 operands[3] = GEN_INT (start + size);
3761 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3762 }"
3763 [(set_attr "type" "delayed_compare")
3764 (set_attr "length" "4,8")])
3765
3766 (define_split
3767 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3768 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3769 (match_operand:SI 2 "const_int_operand" "")
3770 (match_operand:SI 3 "const_int_operand" ""))
3771 (const_int 0)))
3772 (clobber (match_scratch:SI 4 ""))]
3773 "reload_completed"
3774 [(set (match_dup 4)
3775 (zero_extract:SI (match_dup 1) (match_dup 2)
3776 (match_dup 3)))
3777 (set (match_dup 0)
3778 (compare:CC (match_dup 4)
3779 (const_int 0)))]
3780 "")
3781
3782 (define_insn "*extzvsi_internal2"
3783 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3784 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3785 (match_operand:SI 2 "const_int_operand" "i,i")
3786 (match_operand:SI 3 "const_int_operand" "i,i"))
3787 (const_int 0)))
3788 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3789 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3790 ""
3791 "*
3792 {
3793 int start = INTVAL (operands[3]) & 31;
3794 int size = INTVAL (operands[2]) & 31;
3795
3796 /* Force split for non-cc0 compare. */
3797 if (which_alternative == 1)
3798 return \"#\";
3799
3800 /* Since we are using the output value, we can't ignore any need for
3801 a shift. The bit-field must end at the LSB. */
3802 if (start >= 16 && start + size == 32)
3803 {
3804 operands[3] = GEN_INT ((1 << size) - 1);
3805 return \"{andil.|andi.} %0,%1,%3\";
3806 }
3807
3808 if (start + size >= 32)
3809 operands[3] = const0_rtx;
3810 else
3811 operands[3] = GEN_INT (start + size);
3812 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3813 }"
3814 [(set_attr "type" "delayed_compare")
3815 (set_attr "length" "4,8")])
3816
3817 (define_split
3818 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3819 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3820 (match_operand:SI 2 "const_int_operand" "")
3821 (match_operand:SI 3 "const_int_operand" ""))
3822 (const_int 0)))
3823 (set (match_operand:SI 0 "gpc_reg_operand" "")
3824 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3825 "reload_completed"
3826 [(set (match_dup 0)
3827 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3828 (set (match_dup 4)
3829 (compare:CC (match_dup 0)
3830 (const_int 0)))]
3831 "")
3832
3833 (define_insn "extzvdi"
3834 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3835 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3836 (match_operand:SI 2 "const_int_operand" "i")
3837 (match_operand:SI 3 "const_int_operand" "i")))]
3838 "TARGET_POWERPC64"
3839 "*
3840 {
3841 int start = INTVAL (operands[3]) & 63;
3842 int size = INTVAL (operands[2]) & 63;
3843
3844 if (start + size >= 64)
3845 operands[3] = const0_rtx;
3846 else
3847 operands[3] = GEN_INT (start + size);
3848 operands[2] = GEN_INT (64 - size);
3849 return \"rldicl %0,%1,%3,%2\";
3850 }")
3851
3852 (define_insn "*extzvdi_internal1"
3853 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3854 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3855 (match_operand:SI 2 "const_int_operand" "i")
3856 (match_operand:SI 3 "const_int_operand" "i"))
3857 (const_int 0)))
3858 (clobber (match_scratch:DI 4 "=r"))]
3859 "TARGET_64BIT"
3860 "*
3861 {
3862 int start = INTVAL (operands[3]) & 63;
3863 int size = INTVAL (operands[2]) & 63;
3864
3865 if (start + size >= 64)
3866 operands[3] = const0_rtx;
3867 else
3868 operands[3] = GEN_INT (start + size);
3869 operands[2] = GEN_INT (64 - size);
3870 return \"rldicl. %4,%1,%3,%2\";
3871 }"
3872 [(set_attr "type" "compare")])
3873
3874 (define_insn "*extzvdi_internal2"
3875 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3876 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3877 (match_operand:SI 2 "const_int_operand" "i")
3878 (match_operand:SI 3 "const_int_operand" "i"))
3879 (const_int 0)))
3880 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3881 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3882 "TARGET_64BIT"
3883 "*
3884 {
3885 int start = INTVAL (operands[3]) & 63;
3886 int size = INTVAL (operands[2]) & 63;
3887
3888 if (start + size >= 64)
3889 operands[3] = const0_rtx;
3890 else
3891 operands[3] = GEN_INT (start + size);
3892 operands[2] = GEN_INT (64 - size);
3893 return \"rldicl. %0,%1,%3,%2\";
3894 }"
3895 [(set_attr "type" "compare")])
3896
3897 (define_insn "rotlsi3"
3898 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3899 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3900 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
3901 ""
3902 "@
3903 {rlnm|rlwnm} %0,%1,%2,0xffffffff
3904 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
3905 [(set_attr "type" "var_shift_rotate,integer")])
3906
3907 (define_insn "*rotlsi3_internal2"
3908 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3909 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3910 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3911 (const_int 0)))
3912 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3913 ""
3914 "@
3915 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
3916 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
3917 #
3918 #"
3919 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3920 (set_attr "length" "4,4,8,8")])
3921
3922 (define_split
3923 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3924 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3925 (match_operand:SI 2 "reg_or_cint_operand" ""))
3926 (const_int 0)))
3927 (clobber (match_scratch:SI 3 ""))]
3928 "reload_completed"
3929 [(set (match_dup 3)
3930 (rotate:SI (match_dup 1) (match_dup 2)))
3931 (set (match_dup 0)
3932 (compare:CC (match_dup 3)
3933 (const_int 0)))]
3934 "")
3935
3936 (define_insn "*rotlsi3_internal3"
3937 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3938 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3939 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3940 (const_int 0)))
3941 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3942 (rotate:SI (match_dup 1) (match_dup 2)))]
3943 ""
3944 "@
3945 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
3946 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
3947 #
3948 #"
3949 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3950 (set_attr "length" "4,4,8,8")])
3951
3952 (define_split
3953 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3954 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3955 (match_operand:SI 2 "reg_or_cint_operand" ""))
3956 (const_int 0)))
3957 (set (match_operand:SI 0 "gpc_reg_operand" "")
3958 (rotate:SI (match_dup 1) (match_dup 2)))]
3959 "reload_completed"
3960 [(set (match_dup 0)
3961 (rotate:SI (match_dup 1) (match_dup 2)))
3962 (set (match_dup 3)
3963 (compare:CC (match_dup 0)
3964 (const_int 0)))]
3965 "")
3966
3967 (define_insn "*rotlsi3_internal4"
3968 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3969 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3970 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
3971 (match_operand:SI 3 "mask_operand" "n,n")))]
3972 ""
3973 "@
3974 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
3975 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
3976 [(set_attr "type" "var_shift_rotate,integer")])
3977
3978 (define_insn "*rotlsi3_internal5"
3979 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3980 (compare:CC (and:SI
3981 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3982 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3983 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3984 (const_int 0)))
3985 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
3986 ""
3987 "@
3988 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
3989 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3990 #
3991 #"
3992 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3993 (set_attr "length" "4,4,8,8")])
3994
3995 (define_split
3996 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3997 (compare:CC (and:SI
3998 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3999 (match_operand:SI 2 "reg_or_cint_operand" ""))
4000 (match_operand:SI 3 "mask_operand" ""))
4001 (const_int 0)))
4002 (clobber (match_scratch:SI 4 ""))]
4003 "reload_completed"
4004 [(set (match_dup 4)
4005 (and:SI (rotate:SI (match_dup 1)
4006 (match_dup 2))
4007 (match_dup 3)))
4008 (set (match_dup 0)
4009 (compare:CC (match_dup 4)
4010 (const_int 0)))]
4011 "")
4012
4013 (define_insn "*rotlsi3_internal6"
4014 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
4015 (compare:CC (and:SI
4016 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4017 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4018 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4019 (const_int 0)))
4020 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4021 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4022 ""
4023 "@
4024 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
4025 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4026 #
4027 #"
4028 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4029 (set_attr "length" "4,4,8,8")])
4030
4031 (define_split
4032 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4033 (compare:CC (and:SI
4034 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4035 (match_operand:SI 2 "reg_or_cint_operand" ""))
4036 (match_operand:SI 3 "mask_operand" ""))
4037 (const_int 0)))
4038 (set (match_operand:SI 0 "gpc_reg_operand" "")
4039 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4040 "reload_completed"
4041 [(set (match_dup 0)
4042 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4043 (set (match_dup 4)
4044 (compare:CC (match_dup 0)
4045 (const_int 0)))]
4046 "")
4047
4048 (define_insn "*rotlsi3_internal7"
4049 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4050 (zero_extend:SI
4051 (subreg:QI
4052 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4053 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4054 ""
4055 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
4056
4057 (define_insn "*rotlsi3_internal8"
4058 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4059 (compare:CC (zero_extend:SI
4060 (subreg:QI
4061 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4062 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4063 (const_int 0)))
4064 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4065 ""
4066 "@
4067 {rlnm.|rlwnm.} %3,%1,%2,0xff
4068 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4069 #
4070 #"
4071 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4072 (set_attr "length" "4,4,8,8")])
4073
4074 (define_split
4075 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4076 (compare:CC (zero_extend:SI
4077 (subreg:QI
4078 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4079 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4080 (const_int 0)))
4081 (clobber (match_scratch:SI 3 ""))]
4082 "reload_completed"
4083 [(set (match_dup 3)
4084 (zero_extend:SI (subreg:QI
4085 (rotate:SI (match_dup 1)
4086 (match_dup 2)) 0)))
4087 (set (match_dup 0)
4088 (compare:CC (match_dup 3)
4089 (const_int 0)))]
4090 "")
4091
4092 (define_insn "*rotlsi3_internal9"
4093 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4094 (compare:CC (zero_extend:SI
4095 (subreg:QI
4096 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4097 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4098 (const_int 0)))
4099 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4100 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4101 ""
4102 "@
4103 {rlnm.|rlwnm.} %0,%1,%2,0xff
4104 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4105 #
4106 #"
4107 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4108 (set_attr "length" "4,4,8,8")])
4109
4110 (define_split
4111 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4112 (compare:CC (zero_extend:SI
4113 (subreg:QI
4114 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4115 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4116 (const_int 0)))
4117 (set (match_operand:SI 0 "gpc_reg_operand" "")
4118 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4119 "reload_completed"
4120 [(set (match_dup 0)
4121 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4122 (set (match_dup 3)
4123 (compare:CC (match_dup 0)
4124 (const_int 0)))]
4125 "")
4126
4127 (define_insn "*rotlsi3_internal10"
4128 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4129 (zero_extend:SI
4130 (subreg:HI
4131 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4132 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4133 ""
4134 "@
4135 {rlnm|rlwnm} %0,%1,%2,0xffff
4136 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4137 [(set_attr "type" "var_shift_rotate,integer")])
4138
4139
4140 (define_insn "*rotlsi3_internal11"
4141 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4142 (compare:CC (zero_extend:SI
4143 (subreg:HI
4144 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4145 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4146 (const_int 0)))
4147 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4148 ""
4149 "@
4150 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4151 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4152 #
4153 #"
4154 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4155 (set_attr "length" "4,4,8,8")])
4156
4157 (define_split
4158 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4159 (compare:CC (zero_extend:SI
4160 (subreg:HI
4161 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4162 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4163 (const_int 0)))
4164 (clobber (match_scratch:SI 3 ""))]
4165 "reload_completed"
4166 [(set (match_dup 3)
4167 (zero_extend:SI (subreg:HI
4168 (rotate:SI (match_dup 1)
4169 (match_dup 2)) 0)))
4170 (set (match_dup 0)
4171 (compare:CC (match_dup 3)
4172 (const_int 0)))]
4173 "")
4174
4175 (define_insn "*rotlsi3_internal12"
4176 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4177 (compare:CC (zero_extend:SI
4178 (subreg:HI
4179 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4180 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4181 (const_int 0)))
4182 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4183 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4184 ""
4185 "@
4186 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4187 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4188 #
4189 #"
4190 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4191 (set_attr "length" "4,4,8,8")])
4192
4193 (define_split
4194 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4195 (compare:CC (zero_extend:SI
4196 (subreg:HI
4197 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4198 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4199 (const_int 0)))
4200 (set (match_operand:SI 0 "gpc_reg_operand" "")
4201 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4202 "reload_completed"
4203 [(set (match_dup 0)
4204 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4205 (set (match_dup 3)
4206 (compare:CC (match_dup 0)
4207 (const_int 0)))]
4208 "")
4209
4210 ;; Note that we use "sle." instead of "sl." so that we can set
4211 ;; SHIFT_COUNT_TRUNCATED.
4212
4213 (define_expand "ashlsi3"
4214 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4215 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4216 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4217 ""
4218 "
4219 {
4220 if (TARGET_POWER)
4221 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4222 else
4223 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4224 DONE;
4225 }")
4226
4227 (define_insn "ashlsi3_power"
4228 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4229 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4230 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4231 (clobber (match_scratch:SI 3 "=q,X"))]
4232 "TARGET_POWER"
4233 "@
4234 sle %0,%1,%2
4235 {sli|slwi} %0,%1,%h2")
4236
4237 (define_insn "ashlsi3_no_power"
4238 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4239 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4240 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4241 "! TARGET_POWER"
4242 "@
4243 {sl|slw} %0,%1,%2
4244 {sli|slwi} %0,%1,%h2"
4245 [(set_attr "type" "var_shift_rotate,shift")])
4246
4247 (define_insn ""
4248 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4249 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4250 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4251 (const_int 0)))
4252 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4253 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4254 "TARGET_POWER"
4255 "@
4256 sle. %3,%1,%2
4257 {sli.|slwi.} %3,%1,%h2
4258 #
4259 #"
4260 [(set_attr "type" "delayed_compare")
4261 (set_attr "length" "4,4,8,8")])
4262
4263 (define_split
4264 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4265 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4266 (match_operand:SI 2 "reg_or_cint_operand" ""))
4267 (const_int 0)))
4268 (clobber (match_scratch:SI 3 ""))
4269 (clobber (match_scratch:SI 4 ""))]
4270 "TARGET_POWER && reload_completed"
4271 [(parallel [(set (match_dup 3)
4272 (ashift:SI (match_dup 1) (match_dup 2)))
4273 (clobber (match_dup 4))])
4274 (set (match_dup 0)
4275 (compare:CC (match_dup 3)
4276 (const_int 0)))]
4277 "")
4278
4279 (define_insn ""
4280 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4281 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4282 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4283 (const_int 0)))
4284 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4285 "! TARGET_POWER && TARGET_32BIT"
4286 "@
4287 {sl.|slw.} %3,%1,%2
4288 {sli.|slwi.} %3,%1,%h2
4289 #
4290 #"
4291 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4292 (set_attr "length" "4,4,8,8")])
4293
4294 (define_split
4295 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4296 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4297 (match_operand:SI 2 "reg_or_cint_operand" ""))
4298 (const_int 0)))
4299 (clobber (match_scratch:SI 3 ""))]
4300 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4301 [(set (match_dup 3)
4302 (ashift:SI (match_dup 1) (match_dup 2)))
4303 (set (match_dup 0)
4304 (compare:CC (match_dup 3)
4305 (const_int 0)))]
4306 "")
4307
4308 (define_insn ""
4309 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4310 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4311 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4312 (const_int 0)))
4313 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4314 (ashift:SI (match_dup 1) (match_dup 2)))
4315 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4316 "TARGET_POWER"
4317 "@
4318 sle. %0,%1,%2
4319 {sli.|slwi.} %0,%1,%h2
4320 #
4321 #"
4322 [(set_attr "type" "delayed_compare")
4323 (set_attr "length" "4,4,8,8")])
4324
4325 (define_split
4326 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4327 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4328 (match_operand:SI 2 "reg_or_cint_operand" ""))
4329 (const_int 0)))
4330 (set (match_operand:SI 0 "gpc_reg_operand" "")
4331 (ashift:SI (match_dup 1) (match_dup 2)))
4332 (clobber (match_scratch:SI 4 ""))]
4333 "TARGET_POWER && reload_completed"
4334 [(parallel [(set (match_dup 0)
4335 (ashift:SI (match_dup 1) (match_dup 2)))
4336 (clobber (match_dup 4))])
4337 (set (match_dup 3)
4338 (compare:CC (match_dup 0)
4339 (const_int 0)))]
4340 "")
4341
4342 (define_insn ""
4343 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4344 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4345 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4346 (const_int 0)))
4347 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4348 (ashift:SI (match_dup 1) (match_dup 2)))]
4349 "! TARGET_POWER && TARGET_32BIT"
4350 "@
4351 {sl.|slw.} %0,%1,%2
4352 {sli.|slwi.} %0,%1,%h2
4353 #
4354 #"
4355 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4356 (set_attr "length" "4,4,8,8")])
4357
4358 (define_split
4359 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4360 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4361 (match_operand:SI 2 "reg_or_cint_operand" ""))
4362 (const_int 0)))
4363 (set (match_operand:SI 0 "gpc_reg_operand" "")
4364 (ashift:SI (match_dup 1) (match_dup 2)))]
4365 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4366 [(set (match_dup 0)
4367 (ashift:SI (match_dup 1) (match_dup 2)))
4368 (set (match_dup 3)
4369 (compare:CC (match_dup 0)
4370 (const_int 0)))]
4371 "")
4372
4373 (define_insn "rlwinm"
4374 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4375 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4376 (match_operand:SI 2 "const_int_operand" "i"))
4377 (match_operand:SI 3 "mask_operand" "n")))]
4378 "includes_lshift_p (operands[2], operands[3])"
4379 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4380
4381 (define_insn ""
4382 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4383 (compare:CC
4384 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4385 (match_operand:SI 2 "const_int_operand" "i,i"))
4386 (match_operand:SI 3 "mask_operand" "n,n"))
4387 (const_int 0)))
4388 (clobber (match_scratch:SI 4 "=r,r"))]
4389 "includes_lshift_p (operands[2], operands[3])"
4390 "@
4391 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4392 #"
4393 [(set_attr "type" "delayed_compare")
4394 (set_attr "length" "4,8")])
4395
4396 (define_split
4397 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4398 (compare:CC
4399 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4400 (match_operand:SI 2 "const_int_operand" ""))
4401 (match_operand:SI 3 "mask_operand" ""))
4402 (const_int 0)))
4403 (clobber (match_scratch:SI 4 ""))]
4404 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4405 [(set (match_dup 4)
4406 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4407 (match_dup 3)))
4408 (set (match_dup 0)
4409 (compare:CC (match_dup 4)
4410 (const_int 0)))]
4411 "")
4412
4413 (define_insn ""
4414 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4415 (compare:CC
4416 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4417 (match_operand:SI 2 "const_int_operand" "i,i"))
4418 (match_operand:SI 3 "mask_operand" "n,n"))
4419 (const_int 0)))
4420 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4421 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4422 "includes_lshift_p (operands[2], operands[3])"
4423 "@
4424 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4425 #"
4426 [(set_attr "type" "delayed_compare")
4427 (set_attr "length" "4,8")])
4428
4429 (define_split
4430 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4431 (compare:CC
4432 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4433 (match_operand:SI 2 "const_int_operand" ""))
4434 (match_operand:SI 3 "mask_operand" ""))
4435 (const_int 0)))
4436 (set (match_operand:SI 0 "gpc_reg_operand" "")
4437 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4438 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4439 [(set (match_dup 0)
4440 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4441 (set (match_dup 4)
4442 (compare:CC (match_dup 0)
4443 (const_int 0)))]
4444 "")
4445
4446 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
4447 ;; "sli x,x,0".
4448 (define_expand "lshrsi3"
4449 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4450 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4451 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4452 ""
4453 "
4454 {
4455 if (TARGET_POWER)
4456 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4457 else
4458 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
4459 DONE;
4460 }")
4461
4462 (define_insn "lshrsi3_power"
4463 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4464 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4465 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4466 (clobber (match_scratch:SI 3 "=q,X,X"))]
4467 "TARGET_POWER"
4468 "@
4469 sre %0,%1,%2
4470 mr %0,%1
4471 {s%A2i|s%A2wi} %0,%1,%h2")
4472
4473 (define_insn "lshrsi3_no_power"
4474 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4475 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4476 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
4477 "! TARGET_POWER"
4478 "@
4479 mr %0,%1
4480 {sr|srw} %0,%1,%2
4481 {sri|srwi} %0,%1,%h2"
4482 [(set_attr "type" "integer,var_shift_rotate,shift")])
4483
4484 (define_insn ""
4485 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4486 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4487 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4488 (const_int 0)))
4489 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4490 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4491 "TARGET_POWER"
4492 "@
4493 sre. %3,%1,%2
4494 mr. %1,%1
4495 {s%A2i.|s%A2wi.} %3,%1,%h2
4496 #
4497 #
4498 #"
4499 [(set_attr "type" "delayed_compare")
4500 (set_attr "length" "4,4,4,8,8,8")])
4501
4502 (define_split
4503 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4504 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4505 (match_operand:SI 2 "reg_or_cint_operand" ""))
4506 (const_int 0)))
4507 (clobber (match_scratch:SI 3 ""))
4508 (clobber (match_scratch:SI 4 ""))]
4509 "TARGET_POWER && reload_completed"
4510 [(parallel [(set (match_dup 3)
4511 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4512 (clobber (match_dup 4))])
4513 (set (match_dup 0)
4514 (compare:CC (match_dup 3)
4515 (const_int 0)))]
4516 "")
4517
4518 (define_insn ""
4519 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4520 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4521 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4522 (const_int 0)))
4523 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4524 "! TARGET_POWER && TARGET_32BIT"
4525 "@
4526 mr. %1,%1
4527 {sr.|srw.} %3,%1,%2
4528 {sri.|srwi.} %3,%1,%h2
4529 #
4530 #
4531 #"
4532 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4533 (set_attr "length" "4,4,4,8,8,8")])
4534
4535 (define_split
4536 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4537 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4538 (match_operand:SI 2 "reg_or_cint_operand" ""))
4539 (const_int 0)))
4540 (clobber (match_scratch:SI 3 ""))]
4541 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4542 [(set (match_dup 3)
4543 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4544 (set (match_dup 0)
4545 (compare:CC (match_dup 3)
4546 (const_int 0)))]
4547 "")
4548
4549 (define_insn ""
4550 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4551 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4552 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4553 (const_int 0)))
4554 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4555 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4556 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4557 "TARGET_POWER"
4558 "@
4559 sre. %0,%1,%2
4560 mr. %0,%1
4561 {s%A2i.|s%A2wi.} %0,%1,%h2
4562 #
4563 #
4564 #"
4565 [(set_attr "type" "delayed_compare")
4566 (set_attr "length" "4,4,4,8,8,8")])
4567
4568 (define_split
4569 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4570 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4571 (match_operand:SI 2 "reg_or_cint_operand" ""))
4572 (const_int 0)))
4573 (set (match_operand:SI 0 "gpc_reg_operand" "")
4574 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4575 (clobber (match_scratch:SI 4 ""))]
4576 "TARGET_POWER && reload_completed"
4577 [(parallel [(set (match_dup 0)
4578 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4579 (clobber (match_dup 4))])
4580 (set (match_dup 3)
4581 (compare:CC (match_dup 0)
4582 (const_int 0)))]
4583 "")
4584
4585 (define_insn ""
4586 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4587 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4588 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4589 (const_int 0)))
4590 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4591 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4592 "! TARGET_POWER && TARGET_32BIT"
4593 "@
4594 mr. %0,%1
4595 {sr.|srw.} %0,%1,%2
4596 {sri.|srwi.} %0,%1,%h2
4597 #
4598 #
4599 #"
4600 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4601 (set_attr "length" "4,4,4,8,8,8")])
4602
4603 (define_split
4604 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4605 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4606 (match_operand:SI 2 "reg_or_cint_operand" ""))
4607 (const_int 0)))
4608 (set (match_operand:SI 0 "gpc_reg_operand" "")
4609 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4610 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4611 [(set (match_dup 0)
4612 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4613 (set (match_dup 3)
4614 (compare:CC (match_dup 0)
4615 (const_int 0)))]
4616 "")
4617
4618 (define_insn ""
4619 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4620 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4621 (match_operand:SI 2 "const_int_operand" "i"))
4622 (match_operand:SI 3 "mask_operand" "n")))]
4623 "includes_rshift_p (operands[2], operands[3])"
4624 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4625
4626 (define_insn ""
4627 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4628 (compare:CC
4629 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4630 (match_operand:SI 2 "const_int_operand" "i,i"))
4631 (match_operand:SI 3 "mask_operand" "n,n"))
4632 (const_int 0)))
4633 (clobber (match_scratch:SI 4 "=r,r"))]
4634 "includes_rshift_p (operands[2], operands[3])"
4635 "@
4636 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4637 #"
4638 [(set_attr "type" "delayed_compare")
4639 (set_attr "length" "4,8")])
4640
4641 (define_split
4642 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4643 (compare:CC
4644 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4645 (match_operand:SI 2 "const_int_operand" ""))
4646 (match_operand:SI 3 "mask_operand" ""))
4647 (const_int 0)))
4648 (clobber (match_scratch:SI 4 ""))]
4649 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4650 [(set (match_dup 4)
4651 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4652 (match_dup 3)))
4653 (set (match_dup 0)
4654 (compare:CC (match_dup 4)
4655 (const_int 0)))]
4656 "")
4657
4658 (define_insn ""
4659 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4660 (compare:CC
4661 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4662 (match_operand:SI 2 "const_int_operand" "i,i"))
4663 (match_operand:SI 3 "mask_operand" "n,n"))
4664 (const_int 0)))
4665 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4666 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4667 "includes_rshift_p (operands[2], operands[3])"
4668 "@
4669 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4670 #"
4671 [(set_attr "type" "delayed_compare")
4672 (set_attr "length" "4,8")])
4673
4674 (define_split
4675 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4676 (compare:CC
4677 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4678 (match_operand:SI 2 "const_int_operand" ""))
4679 (match_operand:SI 3 "mask_operand" ""))
4680 (const_int 0)))
4681 (set (match_operand:SI 0 "gpc_reg_operand" "")
4682 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4683 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4684 [(set (match_dup 0)
4685 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4686 (set (match_dup 4)
4687 (compare:CC (match_dup 0)
4688 (const_int 0)))]
4689 "")
4690
4691 (define_insn ""
4692 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4693 (zero_extend:SI
4694 (subreg:QI
4695 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4696 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4697 "includes_rshift_p (operands[2], GEN_INT (255))"
4698 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4699
4700 (define_insn ""
4701 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4702 (compare:CC
4703 (zero_extend:SI
4704 (subreg:QI
4705 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4706 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4707 (const_int 0)))
4708 (clobber (match_scratch:SI 3 "=r,r"))]
4709 "includes_rshift_p (operands[2], GEN_INT (255))"
4710 "@
4711 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4712 #"
4713 [(set_attr "type" "delayed_compare")
4714 (set_attr "length" "4,8")])
4715
4716 (define_split
4717 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4718 (compare:CC
4719 (zero_extend:SI
4720 (subreg:QI
4721 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4722 (match_operand:SI 2 "const_int_operand" "")) 0))
4723 (const_int 0)))
4724 (clobber (match_scratch:SI 3 ""))]
4725 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4726 [(set (match_dup 3)
4727 (zero_extend:SI (subreg:QI
4728 (lshiftrt:SI (match_dup 1)
4729 (match_dup 2)) 0)))
4730 (set (match_dup 0)
4731 (compare:CC (match_dup 3)
4732 (const_int 0)))]
4733 "")
4734
4735 (define_insn ""
4736 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4737 (compare:CC
4738 (zero_extend:SI
4739 (subreg:QI
4740 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4741 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4742 (const_int 0)))
4743 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4744 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4745 "includes_rshift_p (operands[2], GEN_INT (255))"
4746 "@
4747 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4748 #"
4749 [(set_attr "type" "delayed_compare")
4750 (set_attr "length" "4,8")])
4751
4752 (define_split
4753 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4754 (compare:CC
4755 (zero_extend:SI
4756 (subreg:QI
4757 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4758 (match_operand:SI 2 "const_int_operand" "")) 0))
4759 (const_int 0)))
4760 (set (match_operand:SI 0 "gpc_reg_operand" "")
4761 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4762 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4763 [(set (match_dup 0)
4764 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4765 (set (match_dup 3)
4766 (compare:CC (match_dup 0)
4767 (const_int 0)))]
4768 "")
4769
4770 (define_insn ""
4771 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4772 (zero_extend:SI
4773 (subreg:HI
4774 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4775 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4776 "includes_rshift_p (operands[2], GEN_INT (65535))"
4777 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4778
4779 (define_insn ""
4780 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4781 (compare:CC
4782 (zero_extend:SI
4783 (subreg:HI
4784 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4785 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4786 (const_int 0)))
4787 (clobber (match_scratch:SI 3 "=r,r"))]
4788 "includes_rshift_p (operands[2], GEN_INT (65535))"
4789 "@
4790 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4791 #"
4792 [(set_attr "type" "delayed_compare")
4793 (set_attr "length" "4,8")])
4794
4795 (define_split
4796 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4797 (compare:CC
4798 (zero_extend:SI
4799 (subreg:HI
4800 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4801 (match_operand:SI 2 "const_int_operand" "")) 0))
4802 (const_int 0)))
4803 (clobber (match_scratch:SI 3 ""))]
4804 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4805 [(set (match_dup 3)
4806 (zero_extend:SI (subreg:HI
4807 (lshiftrt:SI (match_dup 1)
4808 (match_dup 2)) 0)))
4809 (set (match_dup 0)
4810 (compare:CC (match_dup 3)
4811 (const_int 0)))]
4812 "")
4813
4814 (define_insn ""
4815 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4816 (compare:CC
4817 (zero_extend:SI
4818 (subreg:HI
4819 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4820 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4821 (const_int 0)))
4822 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4823 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4824 "includes_rshift_p (operands[2], GEN_INT (65535))"
4825 "@
4826 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4827 #"
4828 [(set_attr "type" "delayed_compare")
4829 (set_attr "length" "4,8")])
4830
4831 (define_split
4832 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4833 (compare:CC
4834 (zero_extend:SI
4835 (subreg:HI
4836 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4837 (match_operand:SI 2 "const_int_operand" "")) 0))
4838 (const_int 0)))
4839 (set (match_operand:SI 0 "gpc_reg_operand" "")
4840 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4841 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4842 [(set (match_dup 0)
4843 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4844 (set (match_dup 3)
4845 (compare:CC (match_dup 0)
4846 (const_int 0)))]
4847 "")
4848
4849 (define_insn ""
4850 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4851 (const_int 1)
4852 (match_operand:SI 1 "gpc_reg_operand" "r"))
4853 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4854 (const_int 31)))]
4855 "TARGET_POWER"
4856 "rrib %0,%1,%2")
4857
4858 (define_insn ""
4859 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4860 (const_int 1)
4861 (match_operand:SI 1 "gpc_reg_operand" "r"))
4862 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4863 (const_int 31)))]
4864 "TARGET_POWER"
4865 "rrib %0,%1,%2")
4866
4867 (define_insn ""
4868 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4869 (const_int 1)
4870 (match_operand:SI 1 "gpc_reg_operand" "r"))
4871 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4872 (const_int 1)
4873 (const_int 0)))]
4874 "TARGET_POWER"
4875 "rrib %0,%1,%2")
4876
4877 (define_expand "ashrsi3"
4878 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4879 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4880 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4881 ""
4882 "
4883 {
4884 if (TARGET_POWER)
4885 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4886 else
4887 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4888 DONE;
4889 }")
4890
4891 (define_insn "ashrsi3_power"
4892 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4893 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4894 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4895 (clobber (match_scratch:SI 3 "=q,X"))]
4896 "TARGET_POWER"
4897 "@
4898 srea %0,%1,%2
4899 {srai|srawi} %0,%1,%h2"
4900 [(set_attr "type" "shift")])
4901
4902 (define_insn "ashrsi3_no_power"
4903 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4904 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4905 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4906 "! TARGET_POWER"
4907 "@
4908 {sra|sraw} %0,%1,%2
4909 {srai|srawi} %0,%1,%h2"
4910 [(set_attr "type" "var_shift_rotate,shift")])
4911
4912 (define_insn ""
4913 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4914 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4915 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4916 (const_int 0)))
4917 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4918 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4919 "TARGET_POWER"
4920 "@
4921 srea. %3,%1,%2
4922 {srai.|srawi.} %3,%1,%h2
4923 #
4924 #"
4925 [(set_attr "type" "delayed_compare")
4926 (set_attr "length" "4,4,8,8")])
4927
4928 (define_split
4929 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4930 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4931 (match_operand:SI 2 "reg_or_cint_operand" ""))
4932 (const_int 0)))
4933 (clobber (match_scratch:SI 3 ""))
4934 (clobber (match_scratch:SI 4 ""))]
4935 "TARGET_POWER && reload_completed"
4936 [(parallel [(set (match_dup 3)
4937 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4938 (clobber (match_dup 4))])
4939 (set (match_dup 0)
4940 (compare:CC (match_dup 3)
4941 (const_int 0)))]
4942 "")
4943
4944 (define_insn ""
4945 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4946 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4947 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4948 (const_int 0)))
4949 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4950 "! TARGET_POWER"
4951 "@
4952 {sra.|sraw.} %3,%1,%2
4953 {srai.|srawi.} %3,%1,%h2
4954 #
4955 #"
4956 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4957 (set_attr "length" "4,4,8,8")])
4958
4959 (define_split
4960 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4961 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4962 (match_operand:SI 2 "reg_or_cint_operand" ""))
4963 (const_int 0)))
4964 (clobber (match_scratch:SI 3 ""))]
4965 "! TARGET_POWER && reload_completed"
4966 [(set (match_dup 3)
4967 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4968 (set (match_dup 0)
4969 (compare:CC (match_dup 3)
4970 (const_int 0)))]
4971 "")
4972
4973 (define_insn ""
4974 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4975 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4976 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4977 (const_int 0)))
4978 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4979 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4980 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4981 "TARGET_POWER"
4982 "@
4983 srea. %0,%1,%2
4984 {srai.|srawi.} %0,%1,%h2
4985 #
4986 #"
4987 [(set_attr "type" "delayed_compare")
4988 (set_attr "length" "4,4,8,8")])
4989
4990 (define_split
4991 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4992 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4993 (match_operand:SI 2 "reg_or_cint_operand" ""))
4994 (const_int 0)))
4995 (set (match_operand:SI 0 "gpc_reg_operand" "")
4996 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4997 (clobber (match_scratch:SI 4 ""))]
4998 "TARGET_POWER && reload_completed"
4999 [(parallel [(set (match_dup 0)
5000 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5001 (clobber (match_dup 4))])
5002 (set (match_dup 3)
5003 (compare:CC (match_dup 0)
5004 (const_int 0)))]
5005 "")
5006
5007 (define_insn ""
5008 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5009 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5010 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5011 (const_int 0)))
5012 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5013 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5014 "! TARGET_POWER"
5015 "@
5016 {sra.|sraw.} %0,%1,%2
5017 {srai.|srawi.} %0,%1,%h2
5018 #
5019 #"
5020 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5021 (set_attr "length" "4,4,8,8")])
5022 \f
5023 (define_split
5024 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5025 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5026 (match_operand:SI 2 "reg_or_cint_operand" ""))
5027 (const_int 0)))
5028 (set (match_operand:SI 0 "gpc_reg_operand" "")
5029 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5030 "! TARGET_POWER && reload_completed"
5031 [(set (match_dup 0)
5032 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5033 (set (match_dup 3)
5034 (compare:CC (match_dup 0)
5035 (const_int 0)))]
5036 "")
5037
5038 ;; Floating-point insns, excluding normal data motion.
5039 ;;
5040 ;; PowerPC has a full set of single-precision floating point instructions.
5041 ;;
5042 ;; For the POWER architecture, we pretend that we have both SFmode and
5043 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
5044 ;; The only conversions we will do will be when storing to memory. In that
5045 ;; case, we will use the "frsp" instruction before storing.
5046 ;;
5047 ;; Note that when we store into a single-precision memory location, we need to
5048 ;; use the frsp insn first. If the register being stored isn't dead, we
5049 ;; need a scratch register for the frsp. But this is difficult when the store
5050 ;; is done by reload. It is not incorrect to do the frsp on the register in
5051 ;; this case, we just lose precision that we would have otherwise gotten but
5052 ;; is not guaranteed. Perhaps this should be tightened up at some point.
5053
5054 (define_expand "extendsfdf2"
5055 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5056 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5057 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5058 "")
5059
5060 (define_insn_and_split "*extendsfdf2_fpr"
5061 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
5062 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
5063 "TARGET_HARD_FLOAT && TARGET_FPRS"
5064 "@
5065 #
5066 fmr %0,%1
5067 lfs%U1%X1 %0,%1"
5068 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5069 [(const_int 0)]
5070 {
5071 emit_note (NOTE_INSN_DELETED);
5072 DONE;
5073 }
5074 [(set_attr "type" "fp,fp,fpload")])
5075
5076 (define_expand "truncdfsf2"
5077 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5078 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5079 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5080 "")
5081
5082 (define_insn "*truncdfsf2_fpr"
5083 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5084 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5085 "TARGET_HARD_FLOAT && TARGET_FPRS"
5086 "frsp %0,%1"
5087 [(set_attr "type" "fp")])
5088
5089 (define_insn "aux_truncdfsf2"
5090 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5091 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
5092 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5093 "frsp %0,%1"
5094 [(set_attr "type" "fp")])
5095
5096 (define_expand "negsf2"
5097 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5098 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5099 "TARGET_HARD_FLOAT"
5100 "")
5101
5102 (define_insn "*negsf2"
5103 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5104 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5105 "TARGET_HARD_FLOAT && TARGET_FPRS"
5106 "fneg %0,%1"
5107 [(set_attr "type" "fp")])
5108
5109 (define_expand "abssf2"
5110 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5111 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5112 "TARGET_HARD_FLOAT"
5113 "")
5114
5115 (define_insn "*abssf2"
5116 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5117 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5118 "TARGET_HARD_FLOAT && TARGET_FPRS"
5119 "fabs %0,%1"
5120 [(set_attr "type" "fp")])
5121
5122 (define_insn ""
5123 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5124 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
5125 "TARGET_HARD_FLOAT && TARGET_FPRS"
5126 "fnabs %0,%1"
5127 [(set_attr "type" "fp")])
5128
5129 (define_expand "addsf3"
5130 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5131 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5132 (match_operand:SF 2 "gpc_reg_operand" "")))]
5133 "TARGET_HARD_FLOAT"
5134 "")
5135
5136 (define_insn ""
5137 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5138 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5139 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5140 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5141 "fadds %0,%1,%2"
5142 [(set_attr "type" "fp")])
5143
5144 (define_insn ""
5145 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5146 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5147 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5148 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5149 "{fa|fadd} %0,%1,%2"
5150 [(set_attr "type" "fp")])
5151
5152 (define_expand "subsf3"
5153 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5154 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5155 (match_operand:SF 2 "gpc_reg_operand" "")))]
5156 "TARGET_HARD_FLOAT"
5157 "")
5158
5159 (define_insn ""
5160 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5161 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5162 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5163 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5164 "fsubs %0,%1,%2"
5165 [(set_attr "type" "fp")])
5166
5167 (define_insn ""
5168 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5169 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5170 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5171 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5172 "{fs|fsub} %0,%1,%2"
5173 [(set_attr "type" "fp")])
5174
5175 (define_expand "mulsf3"
5176 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5177 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5178 (match_operand:SF 2 "gpc_reg_operand" "")))]
5179 "TARGET_HARD_FLOAT"
5180 "")
5181
5182 (define_insn ""
5183 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5184 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5185 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5186 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5187 "fmuls %0,%1,%2"
5188 [(set_attr "type" "fp")])
5189
5190 (define_insn ""
5191 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5192 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5193 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5194 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5195 "{fm|fmul} %0,%1,%2"
5196 [(set_attr "type" "dmul")])
5197
5198 (define_insn "fres"
5199 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5200 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5201 "TARGET_PPC_GFXOPT && flag_finite_math_only"
5202 "fres %0,%1"
5203 [(set_attr "type" "fp")])
5204
5205 (define_expand "divsf3"
5206 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5207 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5208 (match_operand:SF 2 "gpc_reg_operand" "")))]
5209 "TARGET_HARD_FLOAT"
5210 {
5211 if (swdiv && !optimize_size && TARGET_PPC_GFXOPT
5212 && flag_finite_math_only && !flag_trapping_math)
5213 {
5214 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5215 DONE;
5216 }
5217 })
5218
5219 (define_insn ""
5220 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5221 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5222 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5223 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5224 "fdivs %0,%1,%2"
5225 [(set_attr "type" "sdiv")])
5226
5227 (define_insn ""
5228 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5229 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5230 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5231 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5232 "{fd|fdiv} %0,%1,%2"
5233 [(set_attr "type" "ddiv")])
5234
5235 (define_insn ""
5236 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5237 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5238 (match_operand:SF 2 "gpc_reg_operand" "f"))
5239 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5240 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5241 "fmadds %0,%1,%2,%3"
5242 [(set_attr "type" "fp")])
5243
5244 (define_insn ""
5245 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5246 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5247 (match_operand:SF 2 "gpc_reg_operand" "f"))
5248 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5249 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5250 "{fma|fmadd} %0,%1,%2,%3"
5251 [(set_attr "type" "dmul")])
5252
5253 (define_insn ""
5254 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5255 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5256 (match_operand:SF 2 "gpc_reg_operand" "f"))
5257 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5258 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5259 "fmsubs %0,%1,%2,%3"
5260 [(set_attr "type" "fp")])
5261
5262 (define_insn ""
5263 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5264 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5265 (match_operand:SF 2 "gpc_reg_operand" "f"))
5266 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5267 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5268 "{fms|fmsub} %0,%1,%2,%3"
5269 [(set_attr "type" "dmul")])
5270
5271 (define_insn ""
5272 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5273 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5274 (match_operand:SF 2 "gpc_reg_operand" "f"))
5275 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5276 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5277 && HONOR_SIGNED_ZEROS (SFmode)"
5278 "fnmadds %0,%1,%2,%3"
5279 [(set_attr "type" "fp")])
5280
5281 (define_insn ""
5282 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5283 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5284 (match_operand:SF 2 "gpc_reg_operand" "f"))
5285 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5286 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5287 && ! HONOR_SIGNED_ZEROS (SFmode)"
5288 "fnmadds %0,%1,%2,%3"
5289 [(set_attr "type" "fp")])
5290
5291 (define_insn ""
5292 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5293 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5294 (match_operand:SF 2 "gpc_reg_operand" "f"))
5295 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5296 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5297 "{fnma|fnmadd} %0,%1,%2,%3"
5298 [(set_attr "type" "dmul")])
5299
5300 (define_insn ""
5301 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5302 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5303 (match_operand:SF 2 "gpc_reg_operand" "f"))
5304 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5305 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5306 && ! HONOR_SIGNED_ZEROS (SFmode)"
5307 "{fnma|fnmadd} %0,%1,%2,%3"
5308 [(set_attr "type" "dmul")])
5309
5310 (define_insn ""
5311 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5312 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5313 (match_operand:SF 2 "gpc_reg_operand" "f"))
5314 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5315 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5316 && HONOR_SIGNED_ZEROS (SFmode)"
5317 "fnmsubs %0,%1,%2,%3"
5318 [(set_attr "type" "fp")])
5319
5320 (define_insn ""
5321 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5322 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5323 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5324 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5325 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5326 && ! HONOR_SIGNED_ZEROS (SFmode)"
5327 "fnmsubs %0,%1,%2,%3"
5328 [(set_attr "type" "fp")])
5329
5330 (define_insn ""
5331 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5332 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5333 (match_operand:SF 2 "gpc_reg_operand" "f"))
5334 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5335 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5336 "{fnms|fnmsub} %0,%1,%2,%3"
5337 [(set_attr "type" "dmul")])
5338
5339 (define_insn ""
5340 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5341 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5342 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5343 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5344 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5345 && ! HONOR_SIGNED_ZEROS (SFmode)"
5346 "{fnms|fnmsub} %0,%1,%2,%3"
5347 [(set_attr "type" "dmul")])
5348
5349 (define_expand "sqrtsf2"
5350 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5351 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5352 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5353 "")
5354
5355 (define_insn ""
5356 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5357 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5358 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5359 "fsqrts %0,%1"
5360 [(set_attr "type" "ssqrt")])
5361
5362 (define_insn ""
5363 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5364 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5365 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
5366 "fsqrt %0,%1"
5367 [(set_attr "type" "dsqrt")])
5368
5369 (define_expand "copysignsf3"
5370 [(set (match_dup 3)
5371 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5372 (set (match_dup 4)
5373 (neg:SF (abs:SF (match_dup 1))))
5374 (set (match_operand:SF 0 "gpc_reg_operand" "")
5375 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5376 (match_dup 5))
5377 (match_dup 3)
5378 (match_dup 4)))]
5379 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5380 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
5381 {
5382 operands[3] = gen_reg_rtx (SFmode);
5383 operands[4] = gen_reg_rtx (SFmode);
5384 operands[5] = CONST0_RTX (SFmode);
5385 })
5386
5387 (define_expand "copysigndf3"
5388 [(set (match_dup 3)
5389 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5390 (set (match_dup 4)
5391 (neg:DF (abs:DF (match_dup 1))))
5392 (set (match_operand:DF 0 "gpc_reg_operand" "")
5393 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5394 (match_dup 5))
5395 (match_dup 3)
5396 (match_dup 4)))]
5397 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5398 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
5399 {
5400 operands[3] = gen_reg_rtx (DFmode);
5401 operands[4] = gen_reg_rtx (DFmode);
5402 operands[5] = CONST0_RTX (DFmode);
5403 })
5404
5405 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5406 ;; fsel instruction and some auxiliary computations. Then we just have a
5407 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5408 ;; combine.
5409 (define_expand "smaxsf3"
5410 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5411 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5412 (match_operand:SF 2 "gpc_reg_operand" ""))
5413 (match_dup 1)
5414 (match_dup 2)))]
5415 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5416 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5417
5418 (define_expand "sminsf3"
5419 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5420 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5421 (match_operand:SF 2 "gpc_reg_operand" ""))
5422 (match_dup 2)
5423 (match_dup 1)))]
5424 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5425 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5426
5427 (define_split
5428 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5429 (match_operator:SF 3 "min_max_operator"
5430 [(match_operand:SF 1 "gpc_reg_operand" "")
5431 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5432 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5433 [(const_int 0)]
5434 "
5435 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5436 operands[1], operands[2]);
5437 DONE;
5438 }")
5439
5440 (define_expand "movsicc"
5441 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5442 (if_then_else:SI (match_operand 1 "comparison_operator" "")
5443 (match_operand:SI 2 "gpc_reg_operand" "")
5444 (match_operand:SI 3 "gpc_reg_operand" "")))]
5445 "TARGET_ISEL"
5446 "
5447 {
5448 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5449 DONE;
5450 else
5451 FAIL;
5452 }")
5453
5454 ;; We use the BASE_REGS for the isel input operands because, if rA is
5455 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5456 ;; because we may switch the operands and rB may end up being rA.
5457 ;;
5458 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5459 ;; leave out the mode in operand 4 and use one pattern, but reload can
5460 ;; change the mode underneath our feet and then gets confused trying
5461 ;; to reload the value.
5462 (define_insn "isel_signed"
5463 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5464 (if_then_else:SI
5465 (match_operator 1 "comparison_operator"
5466 [(match_operand:CC 4 "cc_reg_operand" "y")
5467 (const_int 0)])
5468 (match_operand:SI 2 "gpc_reg_operand" "b")
5469 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5470 "TARGET_ISEL"
5471 "*
5472 { return output_isel (operands); }"
5473 [(set_attr "length" "4")])
5474
5475 (define_insn "isel_unsigned"
5476 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5477 (if_then_else:SI
5478 (match_operator 1 "comparison_operator"
5479 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5480 (const_int 0)])
5481 (match_operand:SI 2 "gpc_reg_operand" "b")
5482 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5483 "TARGET_ISEL"
5484 "*
5485 { return output_isel (operands); }"
5486 [(set_attr "length" "4")])
5487
5488 (define_expand "movsfcc"
5489 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5490 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5491 (match_operand:SF 2 "gpc_reg_operand" "")
5492 (match_operand:SF 3 "gpc_reg_operand" "")))]
5493 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5494 "
5495 {
5496 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5497 DONE;
5498 else
5499 FAIL;
5500 }")
5501
5502 (define_insn "*fselsfsf4"
5503 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5504 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5505 (match_operand:SF 4 "zero_fp_constant" "F"))
5506 (match_operand:SF 2 "gpc_reg_operand" "f")
5507 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5508 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5509 "fsel %0,%1,%2,%3"
5510 [(set_attr "type" "fp")])
5511
5512 (define_insn "*fseldfsf4"
5513 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5514 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5515 (match_operand:DF 4 "zero_fp_constant" "F"))
5516 (match_operand:SF 2 "gpc_reg_operand" "f")
5517 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5518 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5519 "fsel %0,%1,%2,%3"
5520 [(set_attr "type" "fp")])
5521
5522 (define_expand "negdf2"
5523 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5524 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5525 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5526 "")
5527
5528 (define_insn "*negdf2_fpr"
5529 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5530 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5531 "TARGET_HARD_FLOAT && TARGET_FPRS"
5532 "fneg %0,%1"
5533 [(set_attr "type" "fp")])
5534
5535 (define_expand "absdf2"
5536 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5537 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5538 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5539 "")
5540
5541 (define_insn "*absdf2_fpr"
5542 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5543 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5544 "TARGET_HARD_FLOAT && TARGET_FPRS"
5545 "fabs %0,%1"
5546 [(set_attr "type" "fp")])
5547
5548 (define_insn "*nabsdf2_fpr"
5549 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5550 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
5551 "TARGET_HARD_FLOAT && TARGET_FPRS"
5552 "fnabs %0,%1"
5553 [(set_attr "type" "fp")])
5554
5555 (define_expand "adddf3"
5556 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5557 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5558 (match_operand:DF 2 "gpc_reg_operand" "")))]
5559 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5560 "")
5561
5562 (define_insn "*adddf3_fpr"
5563 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5564 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5565 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5566 "TARGET_HARD_FLOAT && TARGET_FPRS"
5567 "{fa|fadd} %0,%1,%2"
5568 [(set_attr "type" "fp")])
5569
5570 (define_expand "subdf3"
5571 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5572 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5573 (match_operand:DF 2 "gpc_reg_operand" "")))]
5574 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5575 "")
5576
5577 (define_insn "*subdf3_fpr"
5578 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5579 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5580 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5581 "TARGET_HARD_FLOAT && TARGET_FPRS"
5582 "{fs|fsub} %0,%1,%2"
5583 [(set_attr "type" "fp")])
5584
5585 (define_expand "muldf3"
5586 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5587 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5588 (match_operand:DF 2 "gpc_reg_operand" "")))]
5589 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5590 "")
5591
5592 (define_insn "*muldf3_fpr"
5593 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5594 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5595 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5596 "TARGET_HARD_FLOAT && TARGET_FPRS"
5597 "{fm|fmul} %0,%1,%2"
5598 [(set_attr "type" "dmul")])
5599
5600 (define_insn "fred"
5601 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5602 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5603 "TARGET_POPCNTB && flag_finite_math_only"
5604 "fre %0,%1"
5605 [(set_attr "type" "fp")])
5606
5607 (define_expand "divdf3"
5608 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5609 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5610 (match_operand:DF 2 "gpc_reg_operand" "")))]
5611 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5612 {
5613 if (swdiv && !optimize_size && TARGET_POPCNTB
5614 && flag_finite_math_only && !flag_trapping_math)
5615 {
5616 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5617 DONE;
5618 }
5619 })
5620
5621 (define_insn "*divdf3_fpr"
5622 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5623 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5624 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5625 "TARGET_HARD_FLOAT && TARGET_FPRS"
5626 "{fd|fdiv} %0,%1,%2"
5627 [(set_attr "type" "ddiv")])
5628
5629 (define_insn ""
5630 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5631 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5632 (match_operand:DF 2 "gpc_reg_operand" "f"))
5633 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5634 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5635 "{fma|fmadd} %0,%1,%2,%3"
5636 [(set_attr "type" "dmul")])
5637
5638 (define_insn ""
5639 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5640 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5641 (match_operand:DF 2 "gpc_reg_operand" "f"))
5642 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5643 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5644 "{fms|fmsub} %0,%1,%2,%3"
5645 [(set_attr "type" "dmul")])
5646
5647 (define_insn ""
5648 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5649 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5650 (match_operand:DF 2 "gpc_reg_operand" "f"))
5651 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5652 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5653 && HONOR_SIGNED_ZEROS (DFmode)"
5654 "{fnma|fnmadd} %0,%1,%2,%3"
5655 [(set_attr "type" "dmul")])
5656
5657 (define_insn ""
5658 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5659 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5660 (match_operand:DF 2 "gpc_reg_operand" "f"))
5661 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5662 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5663 && ! HONOR_SIGNED_ZEROS (DFmode)"
5664 "{fnma|fnmadd} %0,%1,%2,%3"
5665 [(set_attr "type" "dmul")])
5666
5667 (define_insn ""
5668 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5669 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5670 (match_operand:DF 2 "gpc_reg_operand" "f"))
5671 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5672 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5673 && HONOR_SIGNED_ZEROS (DFmode)"
5674 "{fnms|fnmsub} %0,%1,%2,%3"
5675 [(set_attr "type" "dmul")])
5676
5677 (define_insn ""
5678 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5679 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5680 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5681 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5682 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5683 && ! HONOR_SIGNED_ZEROS (DFmode)"
5684 "{fnms|fnmsub} %0,%1,%2,%3"
5685 [(set_attr "type" "dmul")])
5686
5687 (define_insn "sqrtdf2"
5688 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5689 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5690 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5691 "fsqrt %0,%1"
5692 [(set_attr "type" "dsqrt")])
5693
5694 ;; The conditional move instructions allow us to perform max and min
5695 ;; operations even when
5696
5697 (define_expand "smaxdf3"
5698 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5699 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5700 (match_operand:DF 2 "gpc_reg_operand" ""))
5701 (match_dup 1)
5702 (match_dup 2)))]
5703 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5704 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5705
5706 (define_expand "smindf3"
5707 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5708 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5709 (match_operand:DF 2 "gpc_reg_operand" ""))
5710 (match_dup 2)
5711 (match_dup 1)))]
5712 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5713 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5714
5715 (define_split
5716 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5717 (match_operator:DF 3 "min_max_operator"
5718 [(match_operand:DF 1 "gpc_reg_operand" "")
5719 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5720 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5721 [(const_int 0)]
5722 "
5723 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5724 operands[1], operands[2]);
5725 DONE;
5726 }")
5727
5728 (define_expand "movdfcc"
5729 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5730 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5731 (match_operand:DF 2 "gpc_reg_operand" "")
5732 (match_operand:DF 3 "gpc_reg_operand" "")))]
5733 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5734 "
5735 {
5736 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5737 DONE;
5738 else
5739 FAIL;
5740 }")
5741
5742 (define_insn "*fseldfdf4"
5743 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5744 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5745 (match_operand:DF 4 "zero_fp_constant" "F"))
5746 (match_operand:DF 2 "gpc_reg_operand" "f")
5747 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5748 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5749 "fsel %0,%1,%2,%3"
5750 [(set_attr "type" "fp")])
5751
5752 (define_insn "*fselsfdf4"
5753 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5754 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5755 (match_operand:SF 4 "zero_fp_constant" "F"))
5756 (match_operand:DF 2 "gpc_reg_operand" "f")
5757 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5758 "TARGET_PPC_GFXOPT"
5759 "fsel %0,%1,%2,%3"
5760 [(set_attr "type" "fp")])
5761 \f
5762 ;; Conversions to and from floating-point.
5763
5764 (define_expand "fixuns_truncsfsi2"
5765 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5766 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5767 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5768 "")
5769
5770 (define_expand "fix_truncsfsi2"
5771 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5772 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5773 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5774 "")
5775
5776 ; For each of these conversions, there is a define_expand, a define_insn
5777 ; with a '#' template, and a define_split (with C code). The idea is
5778 ; to allow constant folding with the template of the define_insn,
5779 ; then to have the insns split later (between sched1 and final).
5780
5781 (define_expand "floatsidf2"
5782 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5783 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5784 (use (match_dup 2))
5785 (use (match_dup 3))
5786 (clobber (match_dup 4))
5787 (clobber (match_dup 5))
5788 (clobber (match_dup 6))])]
5789 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5790 "
5791 {
5792 if (TARGET_E500_DOUBLE)
5793 {
5794 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5795 DONE;
5796 }
5797 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS)
5798 {
5799 rtx t1 = gen_reg_rtx (DImode);
5800 emit_insn (gen_floatsidf_ppc64_mfpgpr (operands[0], operands[1], t1));
5801 DONE;
5802 }
5803 if (TARGET_POWERPC64)
5804 {
5805 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5806 rtx t1 = gen_reg_rtx (DImode);
5807 rtx t2 = gen_reg_rtx (DImode);
5808 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5809 DONE;
5810 }
5811
5812 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5813 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5814 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5815 operands[5] = gen_reg_rtx (DFmode);
5816 operands[6] = gen_reg_rtx (SImode);
5817 }")
5818
5819 (define_insn_and_split "*floatsidf2_internal"
5820 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5821 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5822 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5823 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5824 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5825 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5826 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5827 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5828 "#"
5829 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
5830 [(pc)]
5831 "
5832 {
5833 rtx lowword, highword;
5834 gcc_assert (MEM_P (operands[4]));
5835 highword = adjust_address (operands[4], SImode, 0);
5836 lowword = adjust_address (operands[4], SImode, 4);
5837 if (! WORDS_BIG_ENDIAN)
5838 {
5839 rtx tmp;
5840 tmp = highword; highword = lowword; lowword = tmp;
5841 }
5842
5843 emit_insn (gen_xorsi3 (operands[6], operands[1],
5844 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5845 emit_move_insn (lowword, operands[6]);
5846 emit_move_insn (highword, operands[2]);
5847 emit_move_insn (operands[5], operands[4]);
5848 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5849 DONE;
5850 }"
5851 [(set_attr "length" "24")])
5852
5853 (define_expand "floatunssisf2"
5854 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5855 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5856 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5857 "")
5858
5859 (define_expand "floatunssidf2"
5860 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5861 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5862 (use (match_dup 2))
5863 (use (match_dup 3))
5864 (clobber (match_dup 4))
5865 (clobber (match_dup 5))])]
5866 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5867 "
5868 {
5869 if (TARGET_E500_DOUBLE)
5870 {
5871 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5872 DONE;
5873 }
5874 if (TARGET_POWERPC64)
5875 {
5876 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5877 rtx t1 = gen_reg_rtx (DImode);
5878 rtx t2 = gen_reg_rtx (DImode);
5879 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5880 t1, t2));
5881 DONE;
5882 }
5883
5884 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5885 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5886 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5887 operands[5] = gen_reg_rtx (DFmode);
5888 }")
5889
5890 (define_insn_and_split "*floatunssidf2_internal"
5891 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5892 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5893 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5894 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5895 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5896 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5897 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5898 "#"
5899 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
5900 [(pc)]
5901 "
5902 {
5903 rtx lowword, highword;
5904 gcc_assert (MEM_P (operands[4]));
5905 highword = adjust_address (operands[4], SImode, 0);
5906 lowword = adjust_address (operands[4], SImode, 4);
5907 if (! WORDS_BIG_ENDIAN)
5908 {
5909 rtx tmp;
5910 tmp = highword; highword = lowword; lowword = tmp;
5911 }
5912
5913 emit_move_insn (lowword, operands[1]);
5914 emit_move_insn (highword, operands[2]);
5915 emit_move_insn (operands[5], operands[4]);
5916 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5917 DONE;
5918 }"
5919 [(set_attr "length" "20")])
5920
5921 (define_expand "fix_truncdfsi2"
5922 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
5923 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5924 (clobber (match_dup 2))
5925 (clobber (match_dup 3))])]
5926 "(TARGET_POWER2 || TARGET_POWERPC)
5927 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5928 "
5929 {
5930 if (TARGET_E500_DOUBLE)
5931 {
5932 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5933 DONE;
5934 }
5935 operands[2] = gen_reg_rtx (DImode);
5936 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
5937 && gpc_reg_operand(operands[0], GET_MODE (operands[0])))
5938 {
5939 operands[3] = gen_reg_rtx (DImode);
5940 emit_insn (gen_fix_truncdfsi2_mfpgpr (operands[0], operands[1],
5941 operands[2], operands[3]));
5942 DONE;
5943 }
5944 if (TARGET_PPC_GFXOPT)
5945 {
5946 rtx orig_dest = operands[0];
5947 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
5948 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5949 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5950 operands[2]));
5951 if (operands[0] != orig_dest)
5952 emit_move_insn (orig_dest, operands[0]);
5953 DONE;
5954 }
5955 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5956 }")
5957
5958 (define_insn_and_split "*fix_truncdfsi2_internal"
5959 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5960 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5961 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5962 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5963 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5964 "#"
5965 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[3]))"
5966 [(pc)]
5967 "
5968 {
5969 rtx lowword;
5970 gcc_assert (MEM_P (operands[3]));
5971 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5972
5973 emit_insn (gen_fctiwz (operands[2], operands[1]));
5974 emit_move_insn (operands[3], operands[2]);
5975 emit_move_insn (operands[0], lowword);
5976 DONE;
5977 }"
5978 [(set_attr "length" "16")])
5979
5980 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
5981 [(set (match_operand:SI 0 "memory_operand" "=Z")
5982 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5983 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
5984 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
5985 && TARGET_PPC_GFXOPT"
5986 "#"
5987 "&& 1"
5988 [(pc)]
5989 "
5990 {
5991 emit_insn (gen_fctiwz (operands[2], operands[1]));
5992 emit_insn (gen_stfiwx (operands[0], operands[2]));
5993 DONE;
5994 }"
5995 [(set_attr "length" "16")])
5996
5997 (define_insn_and_split "fix_truncdfsi2_mfpgpr"
5998 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5999 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
6000 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
6001 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
6002 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
6003 "#"
6004 "&& 1"
6005 [(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
6006 (set (match_dup 3) (match_dup 2))
6007 (set (match_dup 0) (subreg:SI (match_dup 3) 4))]
6008 ""
6009 [(set_attr "length" "12")])
6010
6011 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6012 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6013 ; because the first makes it clear that operand 0 is not live
6014 ; before the instruction.
6015 (define_insn "fctiwz"
6016 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
6017 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
6018 UNSPEC_FCTIWZ))]
6019 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
6020 "{fcirz|fctiwz} %0,%1"
6021 [(set_attr "type" "fp")])
6022
6023 (define_insn "btruncdf2"
6024 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6025 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6026 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6027 "friz %0,%1"
6028 [(set_attr "type" "fp")])
6029
6030 (define_insn "btruncsf2"
6031 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6032 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6033 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6034 "friz %0,%1"
6035 [(set_attr "type" "fp")])
6036
6037 (define_insn "ceildf2"
6038 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6039 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6040 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6041 "frip %0,%1"
6042 [(set_attr "type" "fp")])
6043
6044 (define_insn "ceilsf2"
6045 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6046 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6047 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6048 "frip %0,%1"
6049 [(set_attr "type" "fp")])
6050
6051 (define_insn "floordf2"
6052 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6053 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6054 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6055 "frim %0,%1"
6056 [(set_attr "type" "fp")])
6057
6058 (define_insn "floorsf2"
6059 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6060 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6061 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6062 "frim %0,%1"
6063 [(set_attr "type" "fp")])
6064
6065 (define_insn "rounddf2"
6066 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6067 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6068 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6069 "frin %0,%1"
6070 [(set_attr "type" "fp")])
6071
6072 (define_insn "roundsf2"
6073 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6074 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6075 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6076 "frin %0,%1"
6077 [(set_attr "type" "fp")])
6078
6079 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6080 (define_insn "stfiwx"
6081 [(set (match_operand:SI 0 "memory_operand" "=Z")
6082 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
6083 UNSPEC_STFIWX))]
6084 "TARGET_PPC_GFXOPT"
6085 "stfiwx %1,%y0"
6086 [(set_attr "type" "fpstore")])
6087
6088 (define_expand "floatsisf2"
6089 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6090 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6091 "TARGET_HARD_FLOAT && !TARGET_FPRS"
6092 "")
6093
6094 (define_insn "floatdidf2"
6095 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6096 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
6097 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6098 "fcfid %0,%1"
6099 [(set_attr "type" "fp")])
6100
6101 (define_insn_and_split "floatsidf_ppc64_mfpgpr"
6102 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6103 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6104 (clobber (match_operand:DI 2 "gpc_reg_operand" "=r"))]
6105 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
6106 "#"
6107 "&& 1"
6108 [(set (match_dup 2) (sign_extend:DI (match_dup 1)))
6109 (set (match_dup 0) (float:DF (match_dup 2)))]
6110 "")
6111
6112 (define_insn_and_split "floatsidf_ppc64"
6113 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6114 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6115 (clobber (match_operand:DI 2 "memory_operand" "=o"))
6116 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
6117 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
6118 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
6119 "#"
6120 "&& 1"
6121 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
6122 (set (match_dup 2) (match_dup 3))
6123 (set (match_dup 4) (match_dup 2))
6124 (set (match_dup 0) (float:DF (match_dup 4)))]
6125 "")
6126
6127 (define_insn_and_split "floatunssidf_ppc64"
6128 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6129 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6130 (clobber (match_operand:DI 2 "memory_operand" "=o"))
6131 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
6132 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
6133 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6134 "#"
6135 "&& 1"
6136 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
6137 (set (match_dup 2) (match_dup 3))
6138 (set (match_dup 4) (match_dup 2))
6139 (set (match_dup 0) (float:DF (match_dup 4)))]
6140 "")
6141
6142 (define_insn "fix_truncdfdi2"
6143 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
6144 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
6145 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6146 "fctidz %0,%1"
6147 [(set_attr "type" "fp")])
6148
6149 (define_expand "floatdisf2"
6150 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6151 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6152 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6153 "
6154 {
6155 rtx val = operands[1];
6156 if (!flag_unsafe_math_optimizations)
6157 {
6158 rtx label = gen_label_rtx ();
6159 val = gen_reg_rtx (DImode);
6160 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6161 emit_label (label);
6162 }
6163 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6164 DONE;
6165 }")
6166
6167 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6168 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6169 ;; from double rounding.
6170 (define_insn_and_split "floatdisf2_internal1"
6171 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6172 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
6173 (clobber (match_scratch:DF 2 "=f"))]
6174 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6175 "#"
6176 "&& reload_completed"
6177 [(set (match_dup 2)
6178 (float:DF (match_dup 1)))
6179 (set (match_dup 0)
6180 (float_truncate:SF (match_dup 2)))]
6181 "")
6182
6183 ;; Twiddles bits to avoid double rounding.
6184 ;; Bits that might be truncated when converting to DFmode are replaced
6185 ;; by a bit that won't be lost at that stage, but is below the SFmode
6186 ;; rounding position.
6187 (define_expand "floatdisf2_internal2"
6188 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6189 (const_int 53)))
6190 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6191 (const_int 2047)))
6192 (clobber (scratch:CC))])
6193 (set (match_dup 3) (plus:DI (match_dup 3)
6194 (const_int 1)))
6195 (set (match_dup 0) (plus:DI (match_dup 0)
6196 (const_int 2047)))
6197 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6198 (const_int 2)))
6199 (set (match_dup 0) (ior:DI (match_dup 0)
6200 (match_dup 1)))
6201 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6202 (const_int -2048)))
6203 (clobber (scratch:CC))])
6204 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6205 (label_ref (match_operand:DI 2 "" ""))
6206 (pc)))
6207 (set (match_dup 0) (match_dup 1))]
6208 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6209 "
6210 {
6211 operands[3] = gen_reg_rtx (DImode);
6212 operands[4] = gen_reg_rtx (CCUNSmode);
6213 }")
6214 \f
6215 ;; Define the DImode operations that can be done in a small number
6216 ;; of instructions. The & constraints are to prevent the register
6217 ;; allocator from allocating registers that overlap with the inputs
6218 ;; (for example, having an input in 7,8 and an output in 6,7). We
6219 ;; also allow for the output being the same as one of the inputs.
6220
6221 (define_insn "*adddi3_noppc64"
6222 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6223 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6224 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6225 "! TARGET_POWERPC64"
6226 "*
6227 {
6228 if (WORDS_BIG_ENDIAN)
6229 return (GET_CODE (operands[2])) != CONST_INT
6230 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6231 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6232 else
6233 return (GET_CODE (operands[2])) != CONST_INT
6234 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6235 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6236 }"
6237 [(set_attr "type" "two")
6238 (set_attr "length" "8")])
6239
6240 (define_insn "*subdi3_noppc64"
6241 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6242 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6243 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6244 "! TARGET_POWERPC64"
6245 "*
6246 {
6247 if (WORDS_BIG_ENDIAN)
6248 return (GET_CODE (operands[1]) != CONST_INT)
6249 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6250 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6251 else
6252 return (GET_CODE (operands[1]) != CONST_INT)
6253 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6254 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
6255 }"
6256 [(set_attr "type" "two")
6257 (set_attr "length" "8")])
6258
6259 (define_insn "*negdi2_noppc64"
6260 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6261 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6262 "! TARGET_POWERPC64"
6263 "*
6264 {
6265 return (WORDS_BIG_ENDIAN)
6266 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6267 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6268 }"
6269 [(set_attr "type" "two")
6270 (set_attr "length" "8")])
6271
6272 (define_expand "mulsidi3"
6273 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6274 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6275 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6276 "! TARGET_POWERPC64"
6277 "
6278 {
6279 if (! TARGET_POWER && ! TARGET_POWERPC)
6280 {
6281 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6282 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6283 emit_insn (gen_mull_call ());
6284 if (WORDS_BIG_ENDIAN)
6285 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
6286 else
6287 {
6288 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
6289 gen_rtx_REG (SImode, 3));
6290 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
6291 gen_rtx_REG (SImode, 4));
6292 }
6293 DONE;
6294 }
6295 else if (TARGET_POWER)
6296 {
6297 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6298 DONE;
6299 }
6300 }")
6301
6302 (define_insn "mulsidi3_mq"
6303 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6304 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6305 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6306 (clobber (match_scratch:SI 3 "=q"))]
6307 "TARGET_POWER"
6308 "mul %0,%1,%2\;mfmq %L0"
6309 [(set_attr "type" "imul")
6310 (set_attr "length" "8")])
6311
6312 (define_insn "*mulsidi3_no_mq"
6313 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6314 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6315 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6316 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6317 "*
6318 {
6319 return (WORDS_BIG_ENDIAN)
6320 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6321 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6322 }"
6323 [(set_attr "type" "imul")
6324 (set_attr "length" "8")])
6325
6326 (define_split
6327 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6328 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6329 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6330 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6331 [(set (match_dup 3)
6332 (truncate:SI
6333 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6334 (sign_extend:DI (match_dup 2)))
6335 (const_int 32))))
6336 (set (match_dup 4)
6337 (mult:SI (match_dup 1)
6338 (match_dup 2)))]
6339 "
6340 {
6341 int endian = (WORDS_BIG_ENDIAN == 0);
6342 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6343 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6344 }")
6345
6346 (define_expand "umulsidi3"
6347 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6348 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6349 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6350 "TARGET_POWERPC && ! TARGET_POWERPC64"
6351 "
6352 {
6353 if (TARGET_POWER)
6354 {
6355 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6356 DONE;
6357 }
6358 }")
6359
6360 (define_insn "umulsidi3_mq"
6361 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6362 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6363 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6364 (clobber (match_scratch:SI 3 "=q"))]
6365 "TARGET_POWERPC && TARGET_POWER"
6366 "*
6367 {
6368 return (WORDS_BIG_ENDIAN)
6369 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6370 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6371 }"
6372 [(set_attr "type" "imul")
6373 (set_attr "length" "8")])
6374
6375 (define_insn "*umulsidi3_no_mq"
6376 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6377 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6378 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6379 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6380 "*
6381 {
6382 return (WORDS_BIG_ENDIAN)
6383 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6384 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6385 }"
6386 [(set_attr "type" "imul")
6387 (set_attr "length" "8")])
6388
6389 (define_split
6390 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6391 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6392 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6393 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6394 [(set (match_dup 3)
6395 (truncate:SI
6396 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6397 (zero_extend:DI (match_dup 2)))
6398 (const_int 32))))
6399 (set (match_dup 4)
6400 (mult:SI (match_dup 1)
6401 (match_dup 2)))]
6402 "
6403 {
6404 int endian = (WORDS_BIG_ENDIAN == 0);
6405 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6406 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6407 }")
6408
6409 (define_expand "smulsi3_highpart"
6410 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6411 (truncate:SI
6412 (lshiftrt:DI (mult:DI (sign_extend:DI
6413 (match_operand:SI 1 "gpc_reg_operand" ""))
6414 (sign_extend:DI
6415 (match_operand:SI 2 "gpc_reg_operand" "")))
6416 (const_int 32))))]
6417 ""
6418 "
6419 {
6420 if (! TARGET_POWER && ! TARGET_POWERPC)
6421 {
6422 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6423 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6424 emit_insn (gen_mulh_call ());
6425 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
6426 DONE;
6427 }
6428 else if (TARGET_POWER)
6429 {
6430 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6431 DONE;
6432 }
6433 }")
6434
6435 (define_insn "smulsi3_highpart_mq"
6436 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6437 (truncate:SI
6438 (lshiftrt:DI (mult:DI (sign_extend:DI
6439 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6440 (sign_extend:DI
6441 (match_operand:SI 2 "gpc_reg_operand" "r")))
6442 (const_int 32))))
6443 (clobber (match_scratch:SI 3 "=q"))]
6444 "TARGET_POWER"
6445 "mul %0,%1,%2"
6446 [(set_attr "type" "imul")])
6447
6448 (define_insn "*smulsi3_highpart_no_mq"
6449 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6450 (truncate:SI
6451 (lshiftrt:DI (mult:DI (sign_extend:DI
6452 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6453 (sign_extend:DI
6454 (match_operand:SI 2 "gpc_reg_operand" "r")))
6455 (const_int 32))))]
6456 "TARGET_POWERPC && ! TARGET_POWER"
6457 "mulhw %0,%1,%2"
6458 [(set_attr "type" "imul")])
6459
6460 (define_expand "umulsi3_highpart"
6461 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6462 (truncate:SI
6463 (lshiftrt:DI (mult:DI (zero_extend:DI
6464 (match_operand:SI 1 "gpc_reg_operand" ""))
6465 (zero_extend:DI
6466 (match_operand:SI 2 "gpc_reg_operand" "")))
6467 (const_int 32))))]
6468 "TARGET_POWERPC"
6469 "
6470 {
6471 if (TARGET_POWER)
6472 {
6473 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6474 DONE;
6475 }
6476 }")
6477
6478 (define_insn "umulsi3_highpart_mq"
6479 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6480 (truncate:SI
6481 (lshiftrt:DI (mult:DI (zero_extend:DI
6482 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6483 (zero_extend:DI
6484 (match_operand:SI 2 "gpc_reg_operand" "r")))
6485 (const_int 32))))
6486 (clobber (match_scratch:SI 3 "=q"))]
6487 "TARGET_POWERPC && TARGET_POWER"
6488 "mulhwu %0,%1,%2"
6489 [(set_attr "type" "imul")])
6490
6491 (define_insn "*umulsi3_highpart_no_mq"
6492 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6493 (truncate:SI
6494 (lshiftrt:DI (mult:DI (zero_extend:DI
6495 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6496 (zero_extend:DI
6497 (match_operand:SI 2 "gpc_reg_operand" "r")))
6498 (const_int 32))))]
6499 "TARGET_POWERPC && ! TARGET_POWER"
6500 "mulhwu %0,%1,%2"
6501 [(set_attr "type" "imul")])
6502
6503 ;; If operands 0 and 2 are in the same register, we have a problem. But
6504 ;; operands 0 and 1 (the usual case) can be in the same register. That's
6505 ;; why we have the strange constraints below.
6506 (define_insn "ashldi3_power"
6507 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6508 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6509 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6510 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6511 "TARGET_POWER"
6512 "@
6513 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
6514 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6515 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6516 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
6517 [(set_attr "length" "8")])
6518
6519 (define_insn "lshrdi3_power"
6520 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6521 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6522 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6523 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6524 "TARGET_POWER"
6525 "@
6526 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
6527 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6528 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6529 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
6530 [(set_attr "length" "8")])
6531
6532 ;; Shift by a variable amount is too complex to be worth open-coding. We
6533 ;; just handle shifts by constants.
6534 (define_insn "ashrdi3_power"
6535 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6536 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6537 (match_operand:SI 2 "const_int_operand" "M,i")))
6538 (clobber (match_scratch:SI 3 "=X,q"))]
6539 "TARGET_POWER"
6540 "@
6541 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6542 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
6543 [(set_attr "type" "shift")
6544 (set_attr "length" "8")])
6545
6546 (define_insn "ashrdi3_no_power"
6547 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6548 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6549 (match_operand:SI 2 "const_int_operand" "M,i")))]
6550 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
6551 "@
6552 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6553 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
6554 [(set_attr "type" "two,three")
6555 (set_attr "length" "8,12")])
6556
6557 (define_insn "*ashrdisi3_noppc64"
6558 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6559 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6560 (const_int 32)) 4))]
6561 "TARGET_32BIT && !TARGET_POWERPC64"
6562 "*
6563 {
6564 if (REGNO (operands[0]) == REGNO (operands[1]))
6565 return \"\";
6566 else
6567 return \"mr %0,%1\";
6568 }"
6569 [(set_attr "length" "4")])
6570
6571 \f
6572 ;; PowerPC64 DImode operations.
6573
6574 (define_insn_and_split "absdi2"
6575 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6576 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6577 (clobber (match_scratch:DI 2 "=&r,&r"))]
6578 "TARGET_POWERPC64"
6579 "#"
6580 "&& reload_completed"
6581 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6582 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6583 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6584 "")
6585
6586 (define_insn_and_split "*nabsdi2"
6587 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6588 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6589 (clobber (match_scratch:DI 2 "=&r,&r"))]
6590 "TARGET_POWERPC64"
6591 "#"
6592 "&& reload_completed"
6593 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6594 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6595 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
6596 "")
6597
6598 (define_insn "muldi3"
6599 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6600 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6601 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6602 "TARGET_POWERPC64"
6603 "@
6604 mulld %0,%1,%2
6605 mulli %0,%1,%2"
6606 [(set (attr "type")
6607 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6608 (const_string "imul3")
6609 (match_operand:SI 2 "short_cint_operand" "")
6610 (const_string "imul2")]
6611 (const_string "lmul")))])
6612
6613 (define_insn "*muldi3_internal1"
6614 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6615 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6616 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6617 (const_int 0)))
6618 (clobber (match_scratch:DI 3 "=r,r"))]
6619 "TARGET_POWERPC64"
6620 "@
6621 mulld. %3,%1,%2
6622 #"
6623 [(set_attr "type" "lmul_compare")
6624 (set_attr "length" "4,8")])
6625
6626 (define_split
6627 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6628 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6629 (match_operand:DI 2 "gpc_reg_operand" ""))
6630 (const_int 0)))
6631 (clobber (match_scratch:DI 3 ""))]
6632 "TARGET_POWERPC64 && reload_completed"
6633 [(set (match_dup 3)
6634 (mult:DI (match_dup 1) (match_dup 2)))
6635 (set (match_dup 0)
6636 (compare:CC (match_dup 3)
6637 (const_int 0)))]
6638 "")
6639
6640 (define_insn "*muldi3_internal2"
6641 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6642 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6643 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6644 (const_int 0)))
6645 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6646 (mult:DI (match_dup 1) (match_dup 2)))]
6647 "TARGET_POWERPC64"
6648 "@
6649 mulld. %0,%1,%2
6650 #"
6651 [(set_attr "type" "lmul_compare")
6652 (set_attr "length" "4,8")])
6653
6654 (define_split
6655 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6656 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6657 (match_operand:DI 2 "gpc_reg_operand" ""))
6658 (const_int 0)))
6659 (set (match_operand:DI 0 "gpc_reg_operand" "")
6660 (mult:DI (match_dup 1) (match_dup 2)))]
6661 "TARGET_POWERPC64 && reload_completed"
6662 [(set (match_dup 0)
6663 (mult:DI (match_dup 1) (match_dup 2)))
6664 (set (match_dup 3)
6665 (compare:CC (match_dup 0)
6666 (const_int 0)))]
6667 "")
6668
6669 (define_insn "smuldi3_highpart"
6670 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6671 (truncate:DI
6672 (lshiftrt:TI (mult:TI (sign_extend:TI
6673 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6674 (sign_extend:TI
6675 (match_operand:DI 2 "gpc_reg_operand" "r")))
6676 (const_int 64))))]
6677 "TARGET_POWERPC64"
6678 "mulhd %0,%1,%2"
6679 [(set_attr "type" "lmul")])
6680
6681 (define_insn "umuldi3_highpart"
6682 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6683 (truncate:DI
6684 (lshiftrt:TI (mult:TI (zero_extend:TI
6685 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6686 (zero_extend:TI
6687 (match_operand:DI 2 "gpc_reg_operand" "r")))
6688 (const_int 64))))]
6689 "TARGET_POWERPC64"
6690 "mulhdu %0,%1,%2"
6691 [(set_attr "type" "lmul")])
6692
6693 (define_insn "rotldi3"
6694 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6695 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6696 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
6697 "TARGET_POWERPC64"
6698 "@
6699 rldcl %0,%1,%2,0
6700 rldicl %0,%1,%H2,0"
6701 [(set_attr "type" "var_shift_rotate,integer")])
6702
6703 (define_insn "*rotldi3_internal2"
6704 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6705 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6706 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6707 (const_int 0)))
6708 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6709 "TARGET_64BIT"
6710 "@
6711 rldcl. %3,%1,%2,0
6712 rldicl. %3,%1,%H2,0
6713 #
6714 #"
6715 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6716 (set_attr "length" "4,4,8,8")])
6717
6718 (define_split
6719 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6720 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6721 (match_operand:DI 2 "reg_or_cint_operand" ""))
6722 (const_int 0)))
6723 (clobber (match_scratch:DI 3 ""))]
6724 "TARGET_POWERPC64 && reload_completed"
6725 [(set (match_dup 3)
6726 (rotate:DI (match_dup 1) (match_dup 2)))
6727 (set (match_dup 0)
6728 (compare:CC (match_dup 3)
6729 (const_int 0)))]
6730 "")
6731
6732 (define_insn "*rotldi3_internal3"
6733 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6734 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6735 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6736 (const_int 0)))
6737 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6738 (rotate:DI (match_dup 1) (match_dup 2)))]
6739 "TARGET_64BIT"
6740 "@
6741 rldcl. %0,%1,%2,0
6742 rldicl. %0,%1,%H2,0
6743 #
6744 #"
6745 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6746 (set_attr "length" "4,4,8,8")])
6747
6748 (define_split
6749 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6750 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6751 (match_operand:DI 2 "reg_or_cint_operand" ""))
6752 (const_int 0)))
6753 (set (match_operand:DI 0 "gpc_reg_operand" "")
6754 (rotate:DI (match_dup 1) (match_dup 2)))]
6755 "TARGET_POWERPC64 && reload_completed"
6756 [(set (match_dup 0)
6757 (rotate:DI (match_dup 1) (match_dup 2)))
6758 (set (match_dup 3)
6759 (compare:CC (match_dup 0)
6760 (const_int 0)))]
6761 "")
6762
6763 (define_insn "*rotldi3_internal4"
6764 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6765 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6766 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6767 (match_operand:DI 3 "mask64_operand" "n,n")))]
6768 "TARGET_POWERPC64"
6769 "@
6770 rldc%B3 %0,%1,%2,%S3
6771 rldic%B3 %0,%1,%H2,%S3"
6772 [(set_attr "type" "var_shift_rotate,integer")])
6773
6774 (define_insn "*rotldi3_internal5"
6775 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6776 (compare:CC (and:DI
6777 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6778 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6779 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6780 (const_int 0)))
6781 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
6782 "TARGET_64BIT"
6783 "@
6784 rldc%B3. %4,%1,%2,%S3
6785 rldic%B3. %4,%1,%H2,%S3
6786 #
6787 #"
6788 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6789 (set_attr "length" "4,4,8,8")])
6790
6791 (define_split
6792 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6793 (compare:CC (and:DI
6794 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6795 (match_operand:DI 2 "reg_or_cint_operand" ""))
6796 (match_operand:DI 3 "mask64_operand" ""))
6797 (const_int 0)))
6798 (clobber (match_scratch:DI 4 ""))]
6799 "TARGET_POWERPC64 && reload_completed"
6800 [(set (match_dup 4)
6801 (and:DI (rotate:DI (match_dup 1)
6802 (match_dup 2))
6803 (match_dup 3)))
6804 (set (match_dup 0)
6805 (compare:CC (match_dup 4)
6806 (const_int 0)))]
6807 "")
6808
6809 (define_insn "*rotldi3_internal6"
6810 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
6811 (compare:CC (and:DI
6812 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6813 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6814 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6815 (const_int 0)))
6816 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6817 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6818 "TARGET_64BIT"
6819 "@
6820 rldc%B3. %0,%1,%2,%S3
6821 rldic%B3. %0,%1,%H2,%S3
6822 #
6823 #"
6824 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6825 (set_attr "length" "4,4,8,8")])
6826
6827 (define_split
6828 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6829 (compare:CC (and:DI
6830 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6831 (match_operand:DI 2 "reg_or_cint_operand" ""))
6832 (match_operand:DI 3 "mask64_operand" ""))
6833 (const_int 0)))
6834 (set (match_operand:DI 0 "gpc_reg_operand" "")
6835 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6836 "TARGET_POWERPC64 && reload_completed"
6837 [(set (match_dup 0)
6838 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6839 (set (match_dup 4)
6840 (compare:CC (match_dup 0)
6841 (const_int 0)))]
6842 "")
6843
6844 (define_insn "*rotldi3_internal7"
6845 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6846 (zero_extend:DI
6847 (subreg:QI
6848 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6849 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6850 "TARGET_POWERPC64"
6851 "@
6852 rldcl %0,%1,%2,56
6853 rldicl %0,%1,%H2,56"
6854 [(set_attr "type" "var_shift_rotate,integer")])
6855
6856 (define_insn "*rotldi3_internal8"
6857 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6858 (compare:CC (zero_extend:DI
6859 (subreg:QI
6860 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6861 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6862 (const_int 0)))
6863 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6864 "TARGET_64BIT"
6865 "@
6866 rldcl. %3,%1,%2,56
6867 rldicl. %3,%1,%H2,56
6868 #
6869 #"
6870 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6871 (set_attr "length" "4,4,8,8")])
6872
6873 (define_split
6874 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6875 (compare:CC (zero_extend:DI
6876 (subreg:QI
6877 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6878 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6879 (const_int 0)))
6880 (clobber (match_scratch:DI 3 ""))]
6881 "TARGET_POWERPC64 && reload_completed"
6882 [(set (match_dup 3)
6883 (zero_extend:DI (subreg:QI
6884 (rotate:DI (match_dup 1)
6885 (match_dup 2)) 0)))
6886 (set (match_dup 0)
6887 (compare:CC (match_dup 3)
6888 (const_int 0)))]
6889 "")
6890
6891 (define_insn "*rotldi3_internal9"
6892 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6893 (compare:CC (zero_extend:DI
6894 (subreg:QI
6895 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6896 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6897 (const_int 0)))
6898 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6899 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6900 "TARGET_64BIT"
6901 "@
6902 rldcl. %0,%1,%2,56
6903 rldicl. %0,%1,%H2,56
6904 #
6905 #"
6906 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6907 (set_attr "length" "4,4,8,8")])
6908
6909 (define_split
6910 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6911 (compare:CC (zero_extend:DI
6912 (subreg:QI
6913 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6914 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6915 (const_int 0)))
6916 (set (match_operand:DI 0 "gpc_reg_operand" "")
6917 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6918 "TARGET_POWERPC64 && reload_completed"
6919 [(set (match_dup 0)
6920 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6921 (set (match_dup 3)
6922 (compare:CC (match_dup 0)
6923 (const_int 0)))]
6924 "")
6925
6926 (define_insn "*rotldi3_internal10"
6927 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6928 (zero_extend:DI
6929 (subreg:HI
6930 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6931 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6932 "TARGET_POWERPC64"
6933 "@
6934 rldcl %0,%1,%2,48
6935 rldicl %0,%1,%H2,48"
6936 [(set_attr "type" "var_shift_rotate,integer")])
6937
6938 (define_insn "*rotldi3_internal11"
6939 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6940 (compare:CC (zero_extend:DI
6941 (subreg:HI
6942 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6943 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6944 (const_int 0)))
6945 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6946 "TARGET_64BIT"
6947 "@
6948 rldcl. %3,%1,%2,48
6949 rldicl. %3,%1,%H2,48
6950 #
6951 #"
6952 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6953 (set_attr "length" "4,4,8,8")])
6954
6955 (define_split
6956 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6957 (compare:CC (zero_extend:DI
6958 (subreg:HI
6959 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6960 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6961 (const_int 0)))
6962 (clobber (match_scratch:DI 3 ""))]
6963 "TARGET_POWERPC64 && reload_completed"
6964 [(set (match_dup 3)
6965 (zero_extend:DI (subreg:HI
6966 (rotate:DI (match_dup 1)
6967 (match_dup 2)) 0)))
6968 (set (match_dup 0)
6969 (compare:CC (match_dup 3)
6970 (const_int 0)))]
6971 "")
6972
6973 (define_insn "*rotldi3_internal12"
6974 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6975 (compare:CC (zero_extend:DI
6976 (subreg:HI
6977 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6978 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6979 (const_int 0)))
6980 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6981 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6982 "TARGET_64BIT"
6983 "@
6984 rldcl. %0,%1,%2,48
6985 rldicl. %0,%1,%H2,48
6986 #
6987 #"
6988 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6989 (set_attr "length" "4,4,8,8")])
6990
6991 (define_split
6992 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6993 (compare:CC (zero_extend:DI
6994 (subreg:HI
6995 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6996 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6997 (const_int 0)))
6998 (set (match_operand:DI 0 "gpc_reg_operand" "")
6999 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7000 "TARGET_POWERPC64 && reload_completed"
7001 [(set (match_dup 0)
7002 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7003 (set (match_dup 3)
7004 (compare:CC (match_dup 0)
7005 (const_int 0)))]
7006 "")
7007
7008 (define_insn "*rotldi3_internal13"
7009 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7010 (zero_extend:DI
7011 (subreg:SI
7012 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7013 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7014 "TARGET_POWERPC64"
7015 "@
7016 rldcl %0,%1,%2,32
7017 rldicl %0,%1,%H2,32"
7018 [(set_attr "type" "var_shift_rotate,integer")])
7019
7020 (define_insn "*rotldi3_internal14"
7021 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7022 (compare:CC (zero_extend:DI
7023 (subreg:SI
7024 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7025 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7026 (const_int 0)))
7027 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7028 "TARGET_64BIT"
7029 "@
7030 rldcl. %3,%1,%2,32
7031 rldicl. %3,%1,%H2,32
7032 #
7033 #"
7034 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7035 (set_attr "length" "4,4,8,8")])
7036
7037 (define_split
7038 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7039 (compare:CC (zero_extend:DI
7040 (subreg:SI
7041 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7042 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7043 (const_int 0)))
7044 (clobber (match_scratch:DI 3 ""))]
7045 "TARGET_POWERPC64 && reload_completed"
7046 [(set (match_dup 3)
7047 (zero_extend:DI (subreg:SI
7048 (rotate:DI (match_dup 1)
7049 (match_dup 2)) 0)))
7050 (set (match_dup 0)
7051 (compare:CC (match_dup 3)
7052 (const_int 0)))]
7053 "")
7054
7055 (define_insn "*rotldi3_internal15"
7056 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7057 (compare:CC (zero_extend:DI
7058 (subreg:SI
7059 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7060 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7061 (const_int 0)))
7062 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7063 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7064 "TARGET_64BIT"
7065 "@
7066 rldcl. %0,%1,%2,32
7067 rldicl. %0,%1,%H2,32
7068 #
7069 #"
7070 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7071 (set_attr "length" "4,4,8,8")])
7072
7073 (define_split
7074 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7075 (compare:CC (zero_extend:DI
7076 (subreg:SI
7077 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7078 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7079 (const_int 0)))
7080 (set (match_operand:DI 0 "gpc_reg_operand" "")
7081 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7082 "TARGET_POWERPC64 && reload_completed"
7083 [(set (match_dup 0)
7084 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7085 (set (match_dup 3)
7086 (compare:CC (match_dup 0)
7087 (const_int 0)))]
7088 "")
7089
7090 (define_expand "ashldi3"
7091 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7092 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7093 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7094 "TARGET_POWERPC64 || TARGET_POWER"
7095 "
7096 {
7097 if (TARGET_POWERPC64)
7098 ;
7099 else if (TARGET_POWER)
7100 {
7101 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
7102 DONE;
7103 }
7104 else
7105 FAIL;
7106 }")
7107
7108 (define_insn "*ashldi3_internal1"
7109 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7110 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7111 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7112 "TARGET_POWERPC64"
7113 "@
7114 sld %0,%1,%2
7115 sldi %0,%1,%H2"
7116 [(set_attr "type" "var_shift_rotate,shift")])
7117
7118 (define_insn "*ashldi3_internal2"
7119 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7120 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7121 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7122 (const_int 0)))
7123 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7124 "TARGET_64BIT"
7125 "@
7126 sld. %3,%1,%2
7127 sldi. %3,%1,%H2
7128 #
7129 #"
7130 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7131 (set_attr "length" "4,4,8,8")])
7132
7133 (define_split
7134 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7135 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7136 (match_operand:SI 2 "reg_or_cint_operand" ""))
7137 (const_int 0)))
7138 (clobber (match_scratch:DI 3 ""))]
7139 "TARGET_POWERPC64 && reload_completed"
7140 [(set (match_dup 3)
7141 (ashift:DI (match_dup 1) (match_dup 2)))
7142 (set (match_dup 0)
7143 (compare:CC (match_dup 3)
7144 (const_int 0)))]
7145 "")
7146
7147 (define_insn "*ashldi3_internal3"
7148 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7149 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7150 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7151 (const_int 0)))
7152 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7153 (ashift:DI (match_dup 1) (match_dup 2)))]
7154 "TARGET_64BIT"
7155 "@
7156 sld. %0,%1,%2
7157 sldi. %0,%1,%H2
7158 #
7159 #"
7160 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7161 (set_attr "length" "4,4,8,8")])
7162
7163 (define_split
7164 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7165 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7166 (match_operand:SI 2 "reg_or_cint_operand" ""))
7167 (const_int 0)))
7168 (set (match_operand:DI 0 "gpc_reg_operand" "")
7169 (ashift:DI (match_dup 1) (match_dup 2)))]
7170 "TARGET_POWERPC64 && reload_completed"
7171 [(set (match_dup 0)
7172 (ashift:DI (match_dup 1) (match_dup 2)))
7173 (set (match_dup 3)
7174 (compare:CC (match_dup 0)
7175 (const_int 0)))]
7176 "")
7177
7178 (define_insn "*ashldi3_internal4"
7179 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7180 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7181 (match_operand:SI 2 "const_int_operand" "i"))
7182 (match_operand:DI 3 "const_int_operand" "n")))]
7183 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7184 "rldic %0,%1,%H2,%W3")
7185
7186 (define_insn "ashldi3_internal5"
7187 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7188 (compare:CC
7189 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7190 (match_operand:SI 2 "const_int_operand" "i,i"))
7191 (match_operand:DI 3 "const_int_operand" "n,n"))
7192 (const_int 0)))
7193 (clobber (match_scratch:DI 4 "=r,r"))]
7194 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7195 "@
7196 rldic. %4,%1,%H2,%W3
7197 #"
7198 [(set_attr "type" "compare")
7199 (set_attr "length" "4,8")])
7200
7201 (define_split
7202 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7203 (compare:CC
7204 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7205 (match_operand:SI 2 "const_int_operand" ""))
7206 (match_operand:DI 3 "const_int_operand" ""))
7207 (const_int 0)))
7208 (clobber (match_scratch:DI 4 ""))]
7209 "TARGET_POWERPC64 && reload_completed
7210 && includes_rldic_lshift_p (operands[2], operands[3])"
7211 [(set (match_dup 4)
7212 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7213 (match_dup 3)))
7214 (set (match_dup 0)
7215 (compare:CC (match_dup 4)
7216 (const_int 0)))]
7217 "")
7218
7219 (define_insn "*ashldi3_internal6"
7220 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7221 (compare:CC
7222 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7223 (match_operand:SI 2 "const_int_operand" "i,i"))
7224 (match_operand:DI 3 "const_int_operand" "n,n"))
7225 (const_int 0)))
7226 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7227 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7228 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7229 "@
7230 rldic. %0,%1,%H2,%W3
7231 #"
7232 [(set_attr "type" "compare")
7233 (set_attr "length" "4,8")])
7234
7235 (define_split
7236 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7237 (compare:CC
7238 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7239 (match_operand:SI 2 "const_int_operand" ""))
7240 (match_operand:DI 3 "const_int_operand" ""))
7241 (const_int 0)))
7242 (set (match_operand:DI 0 "gpc_reg_operand" "")
7243 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7244 "TARGET_POWERPC64 && reload_completed
7245 && includes_rldic_lshift_p (operands[2], operands[3])"
7246 [(set (match_dup 0)
7247 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7248 (match_dup 3)))
7249 (set (match_dup 4)
7250 (compare:CC (match_dup 0)
7251 (const_int 0)))]
7252 "")
7253
7254 (define_insn "*ashldi3_internal7"
7255 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7256 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7257 (match_operand:SI 2 "const_int_operand" "i"))
7258 (match_operand:DI 3 "mask64_operand" "n")))]
7259 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7260 "rldicr %0,%1,%H2,%S3")
7261
7262 (define_insn "ashldi3_internal8"
7263 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7264 (compare:CC
7265 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7266 (match_operand:SI 2 "const_int_operand" "i,i"))
7267 (match_operand:DI 3 "mask64_operand" "n,n"))
7268 (const_int 0)))
7269 (clobber (match_scratch:DI 4 "=r,r"))]
7270 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7271 "@
7272 rldicr. %4,%1,%H2,%S3
7273 #"
7274 [(set_attr "type" "compare")
7275 (set_attr "length" "4,8")])
7276
7277 (define_split
7278 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7279 (compare:CC
7280 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7281 (match_operand:SI 2 "const_int_operand" ""))
7282 (match_operand:DI 3 "mask64_operand" ""))
7283 (const_int 0)))
7284 (clobber (match_scratch:DI 4 ""))]
7285 "TARGET_POWERPC64 && reload_completed
7286 && includes_rldicr_lshift_p (operands[2], operands[3])"
7287 [(set (match_dup 4)
7288 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7289 (match_dup 3)))
7290 (set (match_dup 0)
7291 (compare:CC (match_dup 4)
7292 (const_int 0)))]
7293 "")
7294
7295 (define_insn "*ashldi3_internal9"
7296 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7297 (compare:CC
7298 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7299 (match_operand:SI 2 "const_int_operand" "i,i"))
7300 (match_operand:DI 3 "mask64_operand" "n,n"))
7301 (const_int 0)))
7302 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7303 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7304 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7305 "@
7306 rldicr. %0,%1,%H2,%S3
7307 #"
7308 [(set_attr "type" "compare")
7309 (set_attr "length" "4,8")])
7310
7311 (define_split
7312 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7313 (compare:CC
7314 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7315 (match_operand:SI 2 "const_int_operand" ""))
7316 (match_operand:DI 3 "mask64_operand" ""))
7317 (const_int 0)))
7318 (set (match_operand:DI 0 "gpc_reg_operand" "")
7319 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7320 "TARGET_POWERPC64 && reload_completed
7321 && includes_rldicr_lshift_p (operands[2], operands[3])"
7322 [(set (match_dup 0)
7323 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7324 (match_dup 3)))
7325 (set (match_dup 4)
7326 (compare:CC (match_dup 0)
7327 (const_int 0)))]
7328 "")
7329
7330 (define_expand "lshrdi3"
7331 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7332 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7333 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7334 "TARGET_POWERPC64 || TARGET_POWER"
7335 "
7336 {
7337 if (TARGET_POWERPC64)
7338 ;
7339 else if (TARGET_POWER)
7340 {
7341 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7342 DONE;
7343 }
7344 else
7345 FAIL;
7346 }")
7347
7348 (define_insn "*lshrdi3_internal1"
7349 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7350 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7351 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7352 "TARGET_POWERPC64"
7353 "@
7354 srd %0,%1,%2
7355 srdi %0,%1,%H2"
7356 [(set_attr "type" "var_shift_rotate,shift")])
7357
7358 (define_insn "*lshrdi3_internal2"
7359 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7360 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7361 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7362 (const_int 0)))
7363 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7364 "TARGET_64BIT "
7365 "@
7366 srd. %3,%1,%2
7367 srdi. %3,%1,%H2
7368 #
7369 #"
7370 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7371 (set_attr "length" "4,4,8,8")])
7372
7373 (define_split
7374 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7375 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7376 (match_operand:SI 2 "reg_or_cint_operand" ""))
7377 (const_int 0)))
7378 (clobber (match_scratch:DI 3 ""))]
7379 "TARGET_POWERPC64 && reload_completed"
7380 [(set (match_dup 3)
7381 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7382 (set (match_dup 0)
7383 (compare:CC (match_dup 3)
7384 (const_int 0)))]
7385 "")
7386
7387 (define_insn "*lshrdi3_internal3"
7388 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7389 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7390 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7391 (const_int 0)))
7392 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7393 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7394 "TARGET_64BIT"
7395 "@
7396 srd. %0,%1,%2
7397 srdi. %0,%1,%H2
7398 #
7399 #"
7400 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7401 (set_attr "length" "4,4,8,8")])
7402
7403 (define_split
7404 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7405 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7406 (match_operand:SI 2 "reg_or_cint_operand" ""))
7407 (const_int 0)))
7408 (set (match_operand:DI 0 "gpc_reg_operand" "")
7409 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7410 "TARGET_POWERPC64 && reload_completed"
7411 [(set (match_dup 0)
7412 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7413 (set (match_dup 3)
7414 (compare:CC (match_dup 0)
7415 (const_int 0)))]
7416 "")
7417
7418 (define_expand "ashrdi3"
7419 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7420 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7421 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7422 "WORDS_BIG_ENDIAN"
7423 "
7424 {
7425 if (TARGET_POWERPC64)
7426 ;
7427 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7428 {
7429 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7430 DONE;
7431 }
7432 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7433 && WORDS_BIG_ENDIAN)
7434 {
7435 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7436 DONE;
7437 }
7438 else
7439 FAIL;
7440 }")
7441
7442 (define_insn "*ashrdi3_internal1"
7443 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7444 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7445 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7446 "TARGET_POWERPC64"
7447 "@
7448 srad %0,%1,%2
7449 sradi %0,%1,%H2"
7450 [(set_attr "type" "var_shift_rotate,shift")])
7451
7452 (define_insn "*ashrdi3_internal2"
7453 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7454 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7455 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7456 (const_int 0)))
7457 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7458 "TARGET_64BIT"
7459 "@
7460 srad. %3,%1,%2
7461 sradi. %3,%1,%H2
7462 #
7463 #"
7464 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7465 (set_attr "length" "4,4,8,8")])
7466
7467 (define_split
7468 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7469 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7470 (match_operand:SI 2 "reg_or_cint_operand" ""))
7471 (const_int 0)))
7472 (clobber (match_scratch:DI 3 ""))]
7473 "TARGET_POWERPC64 && reload_completed"
7474 [(set (match_dup 3)
7475 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7476 (set (match_dup 0)
7477 (compare:CC (match_dup 3)
7478 (const_int 0)))]
7479 "")
7480
7481 (define_insn "*ashrdi3_internal3"
7482 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7483 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7484 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7485 (const_int 0)))
7486 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7487 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7488 "TARGET_64BIT"
7489 "@
7490 srad. %0,%1,%2
7491 sradi. %0,%1,%H2
7492 #
7493 #"
7494 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7495 (set_attr "length" "4,4,8,8")])
7496
7497 (define_split
7498 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7499 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7500 (match_operand:SI 2 "reg_or_cint_operand" ""))
7501 (const_int 0)))
7502 (set (match_operand:DI 0 "gpc_reg_operand" "")
7503 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7504 "TARGET_POWERPC64 && reload_completed"
7505 [(set (match_dup 0)
7506 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7507 (set (match_dup 3)
7508 (compare:CC (match_dup 0)
7509 (const_int 0)))]
7510 "")
7511
7512 (define_insn "anddi3"
7513 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7514 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7515 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7516 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7517 "TARGET_POWERPC64"
7518 "@
7519 and %0,%1,%2
7520 rldic%B2 %0,%1,0,%S2
7521 rlwinm %0,%1,0,%m2,%M2
7522 andi. %0,%1,%b2
7523 andis. %0,%1,%u2
7524 #"
7525 [(set_attr "type" "*,*,*,compare,compare,*")
7526 (set_attr "length" "4,4,4,4,4,8")])
7527
7528 (define_split
7529 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7530 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7531 (match_operand:DI 2 "mask64_2_operand" "")))
7532 (clobber (match_scratch:CC 3 ""))]
7533 "TARGET_POWERPC64
7534 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7535 && !mask_operand (operands[2], DImode)
7536 && !mask64_operand (operands[2], DImode)"
7537 [(set (match_dup 0)
7538 (and:DI (rotate:DI (match_dup 1)
7539 (match_dup 4))
7540 (match_dup 5)))
7541 (set (match_dup 0)
7542 (and:DI (rotate:DI (match_dup 0)
7543 (match_dup 6))
7544 (match_dup 7)))]
7545 {
7546 build_mask64_2_operands (operands[2], &operands[4]);
7547 })
7548
7549 (define_insn "*anddi3_internal2"
7550 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7551 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7552 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7553 (const_int 0)))
7554 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7555 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7556 "TARGET_64BIT"
7557 "@
7558 and. %3,%1,%2
7559 rldic%B2. %3,%1,0,%S2
7560 rlwinm. %3,%1,0,%m2,%M2
7561 andi. %3,%1,%b2
7562 andis. %3,%1,%u2
7563 #
7564 #
7565 #
7566 #
7567 #
7568 #
7569 #"
7570 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7571 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7572
7573 (define_split
7574 [(set (match_operand:CC 0 "cc_reg_operand" "")
7575 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7576 (match_operand:DI 2 "mask64_2_operand" ""))
7577 (const_int 0)))
7578 (clobber (match_scratch:DI 3 ""))
7579 (clobber (match_scratch:CC 4 ""))]
7580 "TARGET_64BIT && reload_completed
7581 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7582 && !mask_operand (operands[2], DImode)
7583 && !mask64_operand (operands[2], DImode)"
7584 [(set (match_dup 3)
7585 (and:DI (rotate:DI (match_dup 1)
7586 (match_dup 5))
7587 (match_dup 6)))
7588 (parallel [(set (match_dup 0)
7589 (compare:CC (and:DI (rotate:DI (match_dup 3)
7590 (match_dup 7))
7591 (match_dup 8))
7592 (const_int 0)))
7593 (clobber (match_dup 3))])]
7594 "
7595 {
7596 build_mask64_2_operands (operands[2], &operands[5]);
7597 }")
7598
7599 (define_insn "*anddi3_internal3"
7600 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7601 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7602 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7603 (const_int 0)))
7604 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
7605 (and:DI (match_dup 1) (match_dup 2)))
7606 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7607 "TARGET_64BIT"
7608 "@
7609 and. %0,%1,%2
7610 rldic%B2. %0,%1,0,%S2
7611 rlwinm. %0,%1,0,%m2,%M2
7612 andi. %0,%1,%b2
7613 andis. %0,%1,%u2
7614 #
7615 #
7616 #
7617 #
7618 #
7619 #
7620 #"
7621 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7622 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7623
7624 (define_split
7625 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7626 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7627 (match_operand:DI 2 "and64_2_operand" ""))
7628 (const_int 0)))
7629 (set (match_operand:DI 0 "gpc_reg_operand" "")
7630 (and:DI (match_dup 1) (match_dup 2)))
7631 (clobber (match_scratch:CC 4 ""))]
7632 "TARGET_64BIT && reload_completed"
7633 [(parallel [(set (match_dup 0)
7634 (and:DI (match_dup 1) (match_dup 2)))
7635 (clobber (match_dup 4))])
7636 (set (match_dup 3)
7637 (compare:CC (match_dup 0)
7638 (const_int 0)))]
7639 "")
7640
7641 (define_split
7642 [(set (match_operand:CC 3 "cc_reg_operand" "")
7643 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7644 (match_operand:DI 2 "mask64_2_operand" ""))
7645 (const_int 0)))
7646 (set (match_operand:DI 0 "gpc_reg_operand" "")
7647 (and:DI (match_dup 1) (match_dup 2)))
7648 (clobber (match_scratch:CC 4 ""))]
7649 "TARGET_64BIT && reload_completed
7650 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7651 && !mask_operand (operands[2], DImode)
7652 && !mask64_operand (operands[2], DImode)"
7653 [(set (match_dup 0)
7654 (and:DI (rotate:DI (match_dup 1)
7655 (match_dup 5))
7656 (match_dup 6)))
7657 (parallel [(set (match_dup 3)
7658 (compare:CC (and:DI (rotate:DI (match_dup 0)
7659 (match_dup 7))
7660 (match_dup 8))
7661 (const_int 0)))
7662 (set (match_dup 0)
7663 (and:DI (rotate:DI (match_dup 0)
7664 (match_dup 7))
7665 (match_dup 8)))])]
7666 "
7667 {
7668 build_mask64_2_operands (operands[2], &operands[5]);
7669 }")
7670
7671 (define_expand "iordi3"
7672 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7673 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7674 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7675 "TARGET_POWERPC64"
7676 "
7677 {
7678 if (non_logical_cint_operand (operands[2], DImode))
7679 {
7680 HOST_WIDE_INT value;
7681 rtx tmp = ((!can_create_pseudo_p ()
7682 || rtx_equal_p (operands[0], operands[1]))
7683 ? operands[0] : gen_reg_rtx (DImode));
7684
7685 if (GET_CODE (operands[2]) == CONST_INT)
7686 {
7687 value = INTVAL (operands[2]);
7688 emit_insn (gen_iordi3 (tmp, operands[1],
7689 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7690 }
7691 else
7692 {
7693 value = CONST_DOUBLE_LOW (operands[2]);
7694 emit_insn (gen_iordi3 (tmp, operands[1],
7695 immed_double_const (value
7696 & (~ (HOST_WIDE_INT) 0xffff),
7697 0, DImode)));
7698 }
7699
7700 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7701 DONE;
7702 }
7703 }")
7704
7705 (define_expand "xordi3"
7706 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7707 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7708 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7709 "TARGET_POWERPC64"
7710 "
7711 {
7712 if (non_logical_cint_operand (operands[2], DImode))
7713 {
7714 HOST_WIDE_INT value;
7715 rtx tmp = ((!can_create_pseudo_p ()
7716 || rtx_equal_p (operands[0], operands[1]))
7717 ? operands[0] : gen_reg_rtx (DImode));
7718
7719 if (GET_CODE (operands[2]) == CONST_INT)
7720 {
7721 value = INTVAL (operands[2]);
7722 emit_insn (gen_xordi3 (tmp, operands[1],
7723 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7724 }
7725 else
7726 {
7727 value = CONST_DOUBLE_LOW (operands[2]);
7728 emit_insn (gen_xordi3 (tmp, operands[1],
7729 immed_double_const (value
7730 & (~ (HOST_WIDE_INT) 0xffff),
7731 0, DImode)));
7732 }
7733
7734 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7735 DONE;
7736 }
7737 }")
7738
7739 (define_insn "*booldi3_internal1"
7740 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7741 (match_operator:DI 3 "boolean_or_operator"
7742 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7743 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7744 "TARGET_POWERPC64"
7745 "@
7746 %q3 %0,%1,%2
7747 %q3i %0,%1,%b2
7748 %q3is %0,%1,%u2")
7749
7750 (define_insn "*booldi3_internal2"
7751 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7752 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7753 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7754 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7755 (const_int 0)))
7756 (clobber (match_scratch:DI 3 "=r,r"))]
7757 "TARGET_64BIT"
7758 "@
7759 %q4. %3,%1,%2
7760 #"
7761 [(set_attr "type" "compare")
7762 (set_attr "length" "4,8")])
7763
7764 (define_split
7765 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7766 (compare:CC (match_operator:DI 4 "boolean_operator"
7767 [(match_operand:DI 1 "gpc_reg_operand" "")
7768 (match_operand:DI 2 "gpc_reg_operand" "")])
7769 (const_int 0)))
7770 (clobber (match_scratch:DI 3 ""))]
7771 "TARGET_POWERPC64 && reload_completed"
7772 [(set (match_dup 3) (match_dup 4))
7773 (set (match_dup 0)
7774 (compare:CC (match_dup 3)
7775 (const_int 0)))]
7776 "")
7777
7778 (define_insn "*booldi3_internal3"
7779 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7780 (compare:CC (match_operator:DI 4 "boolean_operator"
7781 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7782 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7783 (const_int 0)))
7784 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7785 (match_dup 4))]
7786 "TARGET_64BIT"
7787 "@
7788 %q4. %0,%1,%2
7789 #"
7790 [(set_attr "type" "compare")
7791 (set_attr "length" "4,8")])
7792
7793 (define_split
7794 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7795 (compare:CC (match_operator:DI 4 "boolean_operator"
7796 [(match_operand:DI 1 "gpc_reg_operand" "")
7797 (match_operand:DI 2 "gpc_reg_operand" "")])
7798 (const_int 0)))
7799 (set (match_operand:DI 0 "gpc_reg_operand" "")
7800 (match_dup 4))]
7801 "TARGET_POWERPC64 && reload_completed"
7802 [(set (match_dup 0) (match_dup 4))
7803 (set (match_dup 3)
7804 (compare:CC (match_dup 0)
7805 (const_int 0)))]
7806 "")
7807
7808 ;; Split a logical operation that we can't do in one insn into two insns,
7809 ;; each of which does one 16-bit part. This is used by combine.
7810
7811 (define_split
7812 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7813 (match_operator:DI 3 "boolean_or_operator"
7814 [(match_operand:DI 1 "gpc_reg_operand" "")
7815 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7816 "TARGET_POWERPC64"
7817 [(set (match_dup 0) (match_dup 4))
7818 (set (match_dup 0) (match_dup 5))]
7819 "
7820 {
7821 rtx i3,i4;
7822
7823 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7824 {
7825 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7826 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7827 0, DImode);
7828 i4 = GEN_INT (value & 0xffff);
7829 }
7830 else
7831 {
7832 i3 = GEN_INT (INTVAL (operands[2])
7833 & (~ (HOST_WIDE_INT) 0xffff));
7834 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7835 }
7836 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7837 operands[1], i3);
7838 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7839 operands[0], i4);
7840 }")
7841
7842 (define_insn "*boolcdi3_internal1"
7843 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7844 (match_operator:DI 3 "boolean_operator"
7845 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7846 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7847 "TARGET_POWERPC64"
7848 "%q3 %0,%2,%1")
7849
7850 (define_insn "*boolcdi3_internal2"
7851 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7852 (compare:CC (match_operator:DI 4 "boolean_operator"
7853 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7854 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7855 (const_int 0)))
7856 (clobber (match_scratch:DI 3 "=r,r"))]
7857 "TARGET_64BIT"
7858 "@
7859 %q4. %3,%2,%1
7860 #"
7861 [(set_attr "type" "compare")
7862 (set_attr "length" "4,8")])
7863
7864 (define_split
7865 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7866 (compare:CC (match_operator:DI 4 "boolean_operator"
7867 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7868 (match_operand:DI 2 "gpc_reg_operand" "")])
7869 (const_int 0)))
7870 (clobber (match_scratch:DI 3 ""))]
7871 "TARGET_POWERPC64 && reload_completed"
7872 [(set (match_dup 3) (match_dup 4))
7873 (set (match_dup 0)
7874 (compare:CC (match_dup 3)
7875 (const_int 0)))]
7876 "")
7877
7878 (define_insn "*boolcdi3_internal3"
7879 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7880 (compare:CC (match_operator:DI 4 "boolean_operator"
7881 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7882 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7883 (const_int 0)))
7884 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7885 (match_dup 4))]
7886 "TARGET_64BIT"
7887 "@
7888 %q4. %0,%2,%1
7889 #"
7890 [(set_attr "type" "compare")
7891 (set_attr "length" "4,8")])
7892
7893 (define_split
7894 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7895 (compare:CC (match_operator:DI 4 "boolean_operator"
7896 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7897 (match_operand:DI 2 "gpc_reg_operand" "")])
7898 (const_int 0)))
7899 (set (match_operand:DI 0 "gpc_reg_operand" "")
7900 (match_dup 4))]
7901 "TARGET_POWERPC64 && reload_completed"
7902 [(set (match_dup 0) (match_dup 4))
7903 (set (match_dup 3)
7904 (compare:CC (match_dup 0)
7905 (const_int 0)))]
7906 "")
7907
7908 (define_insn "*boolccdi3_internal1"
7909 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7910 (match_operator:DI 3 "boolean_operator"
7911 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7912 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7913 "TARGET_POWERPC64"
7914 "%q3 %0,%1,%2")
7915
7916 (define_insn "*boolccdi3_internal2"
7917 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7918 (compare:CC (match_operator:DI 4 "boolean_operator"
7919 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7920 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7921 (const_int 0)))
7922 (clobber (match_scratch:DI 3 "=r,r"))]
7923 "TARGET_64BIT"
7924 "@
7925 %q4. %3,%1,%2
7926 #"
7927 [(set_attr "type" "compare")
7928 (set_attr "length" "4,8")])
7929
7930 (define_split
7931 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7932 (compare:CC (match_operator:DI 4 "boolean_operator"
7933 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7934 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7935 (const_int 0)))
7936 (clobber (match_scratch:DI 3 ""))]
7937 "TARGET_POWERPC64 && reload_completed"
7938 [(set (match_dup 3) (match_dup 4))
7939 (set (match_dup 0)
7940 (compare:CC (match_dup 3)
7941 (const_int 0)))]
7942 "")
7943
7944 (define_insn "*boolccdi3_internal3"
7945 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7946 (compare:CC (match_operator:DI 4 "boolean_operator"
7947 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7948 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7949 (const_int 0)))
7950 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7951 (match_dup 4))]
7952 "TARGET_64BIT"
7953 "@
7954 %q4. %0,%1,%2
7955 #"
7956 [(set_attr "type" "compare")
7957 (set_attr "length" "4,8")])
7958
7959 (define_split
7960 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7961 (compare:CC (match_operator:DI 4 "boolean_operator"
7962 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7963 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7964 (const_int 0)))
7965 (set (match_operand:DI 0 "gpc_reg_operand" "")
7966 (match_dup 4))]
7967 "TARGET_POWERPC64 && reload_completed"
7968 [(set (match_dup 0) (match_dup 4))
7969 (set (match_dup 3)
7970 (compare:CC (match_dup 0)
7971 (const_int 0)))]
7972 "")
7973 \f
7974 ;; Now define ways of moving data around.
7975
7976 ;; Set up a register with a value from the GOT table
7977
7978 (define_expand "movsi_got"
7979 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7980 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7981 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7982 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7983 "
7984 {
7985 if (GET_CODE (operands[1]) == CONST)
7986 {
7987 rtx offset = const0_rtx;
7988 HOST_WIDE_INT value;
7989
7990 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7991 value = INTVAL (offset);
7992 if (value != 0)
7993 {
7994 rtx tmp = (!can_create_pseudo_p ()
7995 ? operands[0]
7996 : gen_reg_rtx (Pmode));
7997 emit_insn (gen_movsi_got (tmp, operands[1]));
7998 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7999 DONE;
8000 }
8001 }
8002
8003 operands[2] = rs6000_got_register (operands[1]);
8004 }")
8005
8006 (define_insn "*movsi_got_internal"
8007 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8008 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8009 (match_operand:SI 2 "gpc_reg_operand" "b")]
8010 UNSPEC_MOVSI_GOT))]
8011 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8012 "{l|lwz} %0,%a1@got(%2)"
8013 [(set_attr "type" "load")])
8014
8015 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
8016 ;; didn't get allocated to a hard register.
8017 (define_split
8018 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8019 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8020 (match_operand:SI 2 "memory_operand" "")]
8021 UNSPEC_MOVSI_GOT))]
8022 "DEFAULT_ABI == ABI_V4
8023 && flag_pic == 1
8024 && (reload_in_progress || reload_completed)"
8025 [(set (match_dup 0) (match_dup 2))
8026 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8027 UNSPEC_MOVSI_GOT))]
8028 "")
8029
8030 ;; For SI, we special-case integers that can't be loaded in one insn. We
8031 ;; do the load 16-bits at a time. We could do this by loading from memory,
8032 ;; and this is even supposed to be faster, but it is simpler not to get
8033 ;; integers in the TOC.
8034 (define_insn "movsi_low"
8035 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8036 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
8037 (match_operand 2 "" ""))))]
8038 "TARGET_MACHO && ! TARGET_64BIT"
8039 "{l|lwz} %0,lo16(%2)(%1)"
8040 [(set_attr "type" "load")
8041 (set_attr "length" "4")])
8042
8043 (define_insn "*movsi_internal1"
8044 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
8045 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
8046 "gpc_reg_operand (operands[0], SImode)
8047 || gpc_reg_operand (operands[1], SImode)"
8048 "@
8049 mr %0,%1
8050 {cal|la} %0,%a1
8051 {l%U1%X1|lwz%U1%X1} %0,%1
8052 {st%U0%X0|stw%U0%X0} %1,%0
8053 {lil|li} %0,%1
8054 {liu|lis} %0,%v1
8055 #
8056 {cal|la} %0,%a1
8057 mf%1 %0
8058 mt%0 %1
8059 mt%0 %1
8060 mt%0 %1
8061 {cror 0,0,0|nop}"
8062 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
8063 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
8064
8065 ;; Split a load of a large constant into the appropriate two-insn
8066 ;; sequence.
8067
8068 (define_split
8069 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8070 (match_operand:SI 1 "const_int_operand" ""))]
8071 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
8072 && (INTVAL (operands[1]) & 0xffff) != 0"
8073 [(set (match_dup 0)
8074 (match_dup 2))
8075 (set (match_dup 0)
8076 (ior:SI (match_dup 0)
8077 (match_dup 3)))]
8078 "
8079 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8080
8081 if (tem == operands[0])
8082 DONE;
8083 else
8084 FAIL;
8085 }")
8086
8087 (define_insn "*mov<mode>_internal2"
8088 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8089 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
8090 (const_int 0)))
8091 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8092 ""
8093 "@
8094 {cmpi|cmp<wd>i} %2,%0,0
8095 mr. %0,%1
8096 #"
8097 [(set_attr "type" "cmp,compare,cmp")
8098 (set_attr "length" "4,4,8")])
8099
8100 (define_split
8101 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8102 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
8103 (const_int 0)))
8104 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8105 "reload_completed"
8106 [(set (match_dup 0) (match_dup 1))
8107 (set (match_dup 2)
8108 (compare:CC (match_dup 0)
8109 (const_int 0)))]
8110 "")
8111 \f
8112 (define_insn "*movhi_internal"
8113 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8114 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8115 "gpc_reg_operand (operands[0], HImode)
8116 || gpc_reg_operand (operands[1], HImode)"
8117 "@
8118 mr %0,%1
8119 lhz%U1%X1 %0,%1
8120 sth%U0%X0 %1,%0
8121 {lil|li} %0,%w1
8122 mf%1 %0
8123 mt%0 %1
8124 mt%0 %1
8125 {cror 0,0,0|nop}"
8126 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8127
8128 (define_expand "mov<mode>"
8129 [(set (match_operand:INT 0 "general_operand" "")
8130 (match_operand:INT 1 "any_operand" ""))]
8131 ""
8132 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8133
8134 (define_insn "*movqi_internal"
8135 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8136 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8137 "gpc_reg_operand (operands[0], QImode)
8138 || gpc_reg_operand (operands[1], QImode)"
8139 "@
8140 mr %0,%1
8141 lbz%U1%X1 %0,%1
8142 stb%U0%X0 %1,%0
8143 {lil|li} %0,%1
8144 mf%1 %0
8145 mt%0 %1
8146 mt%0 %1
8147 {cror 0,0,0|nop}"
8148 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8149 \f
8150 ;; Here is how to move condition codes around. When we store CC data in
8151 ;; an integer register or memory, we store just the high-order 4 bits.
8152 ;; This lets us not shift in the most common case of CR0.
8153 (define_expand "movcc"
8154 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8155 (match_operand:CC 1 "nonimmediate_operand" ""))]
8156 ""
8157 "")
8158
8159 (define_insn "*movcc_internal1"
8160 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
8161 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
8162 "register_operand (operands[0], CCmode)
8163 || register_operand (operands[1], CCmode)"
8164 "@
8165 mcrf %0,%1
8166 mtcrf 128,%1
8167 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
8168 crxor %0,%0,%0
8169 mfcr %0%Q1
8170 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
8171 mr %0,%1
8172 {lil|li} %0,%1
8173 mf%1 %0
8174 mt%0 %1
8175 mt%0 %1
8176 {l%U1%X1|lwz%U1%X1} %0,%1
8177 {st%U0%U1|stw%U0%U1} %1,%0"
8178 [(set (attr "type")
8179 (cond [(eq_attr "alternative" "0,3")
8180 (const_string "cr_logical")
8181 (eq_attr "alternative" "1,2")
8182 (const_string "mtcr")
8183 (eq_attr "alternative" "6,7,9")
8184 (const_string "integer")
8185 (eq_attr "alternative" "8")
8186 (const_string "mfjmpr")
8187 (eq_attr "alternative" "10")
8188 (const_string "mtjmpr")
8189 (eq_attr "alternative" "11")
8190 (const_string "load")
8191 (eq_attr "alternative" "12")
8192 (const_string "store")
8193 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
8194 (const_string "mfcrf")
8195 ]
8196 (const_string "mfcr")))
8197 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
8198 \f
8199 ;; For floating-point, we normally deal with the floating-point registers
8200 ;; unless -msoft-float is used. The sole exception is that parameter passing
8201 ;; can produce floating-point values in fixed-point registers. Unless the
8202 ;; value is a simple constant or already in memory, we deal with this by
8203 ;; allocating memory and copying the value explicitly via that memory location.
8204 (define_expand "movsf"
8205 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8206 (match_operand:SF 1 "any_operand" ""))]
8207 ""
8208 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
8209
8210 (define_split
8211 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8212 (match_operand:SF 1 "const_double_operand" ""))]
8213 "reload_completed
8214 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8215 || (GET_CODE (operands[0]) == SUBREG
8216 && GET_CODE (SUBREG_REG (operands[0])) == REG
8217 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8218 [(set (match_dup 2) (match_dup 3))]
8219 "
8220 {
8221 long l;
8222 REAL_VALUE_TYPE rv;
8223
8224 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8225 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
8226
8227 if (! TARGET_POWERPC64)
8228 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
8229 else
8230 operands[2] = gen_lowpart (SImode, operands[0]);
8231
8232 operands[3] = gen_int_mode (l, SImode);
8233 }")
8234
8235 (define_insn "*movsf_hardfloat"
8236 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
8237 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
8238 "(gpc_reg_operand (operands[0], SFmode)
8239 || gpc_reg_operand (operands[1], SFmode))
8240 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
8241 "@
8242 mr %0,%1
8243 {l%U1%X1|lwz%U1%X1} %0,%1
8244 {st%U0%X0|stw%U0%X0} %1,%0
8245 fmr %0,%1
8246 lfs%U1%X1 %0,%1
8247 stfs%U0%X0 %1,%0
8248 mt%0 %1
8249 mt%0 %1
8250 mf%1 %0
8251 {cror 0,0,0|nop}
8252 #
8253 #"
8254 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
8255 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
8256
8257 (define_insn "*movsf_softfloat"
8258 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
8259 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
8260 "(gpc_reg_operand (operands[0], SFmode)
8261 || gpc_reg_operand (operands[1], SFmode))
8262 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
8263 "@
8264 mr %0,%1
8265 mt%0 %1
8266 mt%0 %1
8267 mf%1 %0
8268 {l%U1%X1|lwz%U1%X1} %0,%1
8269 {st%U0%X0|stw%U0%X0} %1,%0
8270 {lil|li} %0,%1
8271 {liu|lis} %0,%v1
8272 {cal|la} %0,%a1
8273 #
8274 #
8275 {cror 0,0,0|nop}"
8276 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
8277 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
8278
8279 \f
8280 (define_expand "movdf"
8281 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8282 (match_operand:DF 1 "any_operand" ""))]
8283 ""
8284 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
8285
8286 (define_split
8287 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8288 (match_operand:DF 1 "const_int_operand" ""))]
8289 "! TARGET_POWERPC64 && reload_completed
8290 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8291 || (GET_CODE (operands[0]) == SUBREG
8292 && GET_CODE (SUBREG_REG (operands[0])) == REG
8293 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8294 [(set (match_dup 2) (match_dup 4))
8295 (set (match_dup 3) (match_dup 1))]
8296 "
8297 {
8298 int endian = (WORDS_BIG_ENDIAN == 0);
8299 HOST_WIDE_INT value = INTVAL (operands[1]);
8300
8301 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8302 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8303 #if HOST_BITS_PER_WIDE_INT == 32
8304 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8305 #else
8306 operands[4] = GEN_INT (value >> 32);
8307 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8308 #endif
8309 }")
8310
8311 (define_split
8312 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8313 (match_operand:DF 1 "const_double_operand" ""))]
8314 "! TARGET_POWERPC64 && reload_completed
8315 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8316 || (GET_CODE (operands[0]) == SUBREG
8317 && GET_CODE (SUBREG_REG (operands[0])) == REG
8318 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8319 [(set (match_dup 2) (match_dup 4))
8320 (set (match_dup 3) (match_dup 5))]
8321 "
8322 {
8323 int endian = (WORDS_BIG_ENDIAN == 0);
8324 long l[2];
8325 REAL_VALUE_TYPE rv;
8326
8327 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8328 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8329
8330 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8331 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8332 operands[4] = gen_int_mode (l[endian], SImode);
8333 operands[5] = gen_int_mode (l[1 - endian], SImode);
8334 }")
8335
8336 (define_split
8337 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8338 (match_operand:DF 1 "const_double_operand" ""))]
8339 "TARGET_POWERPC64 && reload_completed
8340 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8341 || (GET_CODE (operands[0]) == SUBREG
8342 && GET_CODE (SUBREG_REG (operands[0])) == REG
8343 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8344 [(set (match_dup 2) (match_dup 3))]
8345 "
8346 {
8347 int endian = (WORDS_BIG_ENDIAN == 0);
8348 long l[2];
8349 REAL_VALUE_TYPE rv;
8350 #if HOST_BITS_PER_WIDE_INT >= 64
8351 HOST_WIDE_INT val;
8352 #endif
8353
8354 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8355 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8356
8357 operands[2] = gen_lowpart (DImode, operands[0]);
8358 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8359 #if HOST_BITS_PER_WIDE_INT >= 64
8360 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8361 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8362
8363 operands[3] = gen_int_mode (val, DImode);
8364 #else
8365 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8366 #endif
8367 }")
8368
8369 ;; Don't have reload use general registers to load a constant. First,
8370 ;; it might not work if the output operand is the equivalent of
8371 ;; a non-offsettable memref, but also it is less efficient than loading
8372 ;; the constant into an FP register, since it will probably be used there.
8373 ;; The "??" is a kludge until we can figure out a more reasonable way
8374 ;; of handling these non-offsettable values.
8375 (define_insn "*movdf_hardfloat32"
8376 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8377 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
8378 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8379 && (gpc_reg_operand (operands[0], DFmode)
8380 || gpc_reg_operand (operands[1], DFmode))"
8381 "*
8382 {
8383 switch (which_alternative)
8384 {
8385 default:
8386 gcc_unreachable ();
8387 case 0:
8388 /* We normally copy the low-numbered register first. However, if
8389 the first register operand 0 is the same as the second register
8390 of operand 1, we must copy in the opposite order. */
8391 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8392 return \"mr %L0,%L1\;mr %0,%1\";
8393 else
8394 return \"mr %0,%1\;mr %L0,%L1\";
8395 case 1:
8396 if (rs6000_offsettable_memref_p (operands[1])
8397 || (GET_CODE (operands[1]) == MEM
8398 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8399 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8400 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC
8401 || GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)))
8402 {
8403 /* If the low-address word is used in the address, we must load
8404 it last. Otherwise, load it first. Note that we cannot have
8405 auto-increment in that case since the address register is
8406 known to be dead. */
8407 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8408 operands[1], 0))
8409 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8410 else
8411 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
8412 }
8413 else
8414 {
8415 rtx addreg;
8416
8417 addreg = find_addr_reg (XEXP (operands[1], 0));
8418 if (refers_to_regno_p (REGNO (operands[0]),
8419 REGNO (operands[0]) + 1,
8420 operands[1], 0))
8421 {
8422 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8423 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
8424 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8425 return \"{l%X1|lwz%X1} %0,%1\";
8426 }
8427 else
8428 {
8429 output_asm_insn (\"{l%X1|lwz%X1} %0,%1\", operands);
8430 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8431 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
8432 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8433 return \"\";
8434 }
8435 }
8436 case 2:
8437 if (rs6000_offsettable_memref_p (operands[0])
8438 || (GET_CODE (operands[0]) == MEM
8439 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8440 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8441 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
8442 || GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)))
8443 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
8444 else
8445 {
8446 rtx addreg;
8447
8448 addreg = find_addr_reg (XEXP (operands[0], 0));
8449 output_asm_insn (\"{st%X0|stw%X0} %1,%0\", operands);
8450 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8451 output_asm_insn (\"{st%X0|stw%X0} %L1,%0\", operands);
8452 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8453 return \"\";
8454 }
8455 case 3:
8456 return \"fmr %0,%1\";
8457 case 4:
8458 return \"lfd%U1%X1 %0,%1\";
8459 case 5:
8460 return \"stfd%U0%X0 %1,%0\";
8461 case 6:
8462 case 7:
8463 case 8:
8464 return \"#\";
8465 }
8466 }"
8467 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
8468 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
8469
8470 (define_insn "*movdf_softfloat32"
8471 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8472 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8473 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8474 && (gpc_reg_operand (operands[0], DFmode)
8475 || gpc_reg_operand (operands[1], DFmode))"
8476 "*
8477 {
8478 switch (which_alternative)
8479 {
8480 default:
8481 gcc_unreachable ();
8482 case 0:
8483 /* We normally copy the low-numbered register first. However, if
8484 the first register operand 0 is the same as the second register of
8485 operand 1, we must copy in the opposite order. */
8486 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8487 return \"mr %L0,%L1\;mr %0,%1\";
8488 else
8489 return \"mr %0,%1\;mr %L0,%L1\";
8490 case 1:
8491 /* If the low-address word is used in the address, we must load
8492 it last. Otherwise, load it first. Note that we cannot have
8493 auto-increment in that case since the address register is
8494 known to be dead. */
8495 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8496 operands[1], 0))
8497 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8498 else
8499 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
8500 case 2:
8501 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
8502 case 3:
8503 case 4:
8504 case 5:
8505 return \"#\";
8506 }
8507 }"
8508 [(set_attr "type" "two,load,store,*,*,*")
8509 (set_attr "length" "8,8,8,8,12,16")])
8510
8511 ; ld/std require word-aligned displacements -> 'Y' constraint.
8512 ; List Y->r and r->Y before r->r for reload.
8513 (define_insn "*movdf_hardfloat64_mfpgpr"
8514 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f")
8515 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))]
8516 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8517 && (gpc_reg_operand (operands[0], DFmode)
8518 || gpc_reg_operand (operands[1], DFmode))"
8519 "@
8520 std%U0%X0 %1,%0
8521 ld%U1%X1 %0,%1
8522 mr %0,%1
8523 fmr %0,%1
8524 lfd%U1%X1 %0,%1
8525 stfd%U0%X0 %1,%0
8526 mt%0 %1
8527 mf%1 %0
8528 {cror 0,0,0|nop}
8529 #
8530 #
8531 #
8532 mftgpr %0,%1
8533 mffgpr %0,%1"
8534 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
8535 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
8536
8537 ; ld/std require word-aligned displacements -> 'Y' constraint.
8538 ; List Y->r and r->Y before r->r for reload.
8539 (define_insn "*movdf_hardfloat64"
8540 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
8541 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
8542 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8543 && (gpc_reg_operand (operands[0], DFmode)
8544 || gpc_reg_operand (operands[1], DFmode))"
8545 "@
8546 std%U0%X0 %1,%0
8547 ld%U1%X1 %0,%1
8548 mr %0,%1
8549 fmr %0,%1
8550 lfd%U1%X1 %0,%1
8551 stfd%U0%X0 %1,%0
8552 mt%0 %1
8553 mf%1 %0
8554 {cror 0,0,0|nop}
8555 #
8556 #
8557 #"
8558 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
8559 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
8560
8561 (define_insn "*movdf_softfloat64"
8562 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8563 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
8564 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8565 && (gpc_reg_operand (operands[0], DFmode)
8566 || gpc_reg_operand (operands[1], DFmode))"
8567 "@
8568 ld%U1%X1 %0,%1
8569 std%U0%X0 %1,%0
8570 mr %0,%1
8571 mt%0 %1
8572 mf%1 %0
8573 #
8574 #
8575 #
8576 {cror 0,0,0|nop}"
8577 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
8578 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8579 \f
8580 (define_expand "movtf"
8581 [(set (match_operand:TF 0 "general_operand" "")
8582 (match_operand:TF 1 "any_operand" ""))]
8583 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
8584 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8585
8586 ; It's important to list the o->f and f->o moves before f->f because
8587 ; otherwise reload, given m->f, will try to pick f->f and reload it,
8588 ; which doesn't make progress. Likewise r->Y must be before r->r.
8589 (define_insn_and_split "*movtf_internal"
8590 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
8591 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
8592 "!TARGET_IEEEQUAD
8593 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8594 && (gpc_reg_operand (operands[0], TFmode)
8595 || gpc_reg_operand (operands[1], TFmode))"
8596 "#"
8597 "&& reload_completed"
8598 [(pc)]
8599 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8600 [(set_attr "length" "8,8,8,20,20,16")])
8601
8602 (define_insn_and_split "*movtf_softfloat"
8603 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
8604 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
8605 "!TARGET_IEEEQUAD
8606 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
8607 && (gpc_reg_operand (operands[0], TFmode)
8608 || gpc_reg_operand (operands[1], TFmode))"
8609 "#"
8610 "&& reload_completed"
8611 [(pc)]
8612 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8613 [(set_attr "length" "20,20,16")])
8614
8615 (define_expand "extenddftf2"
8616 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8617 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8618 "!TARGET_IEEEQUAD
8619 && TARGET_HARD_FLOAT
8620 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8621 && TARGET_LONG_DOUBLE_128"
8622 {
8623 if (TARGET_E500_DOUBLE)
8624 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8625 else
8626 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8627 DONE;
8628 })
8629
8630 (define_expand "extenddftf2_fprs"
8631 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8632 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8633 (use (match_dup 2))])]
8634 "!TARGET_IEEEQUAD
8635 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8636 {
8637 operands[2] = CONST0_RTX (DFmode);
8638 /* Generate GOT reference early for SVR4 PIC. */
8639 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8640 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8641 })
8642
8643 (define_insn_and_split "*extenddftf2_internal"
8644 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8645 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8646 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
8647 "!TARGET_IEEEQUAD
8648 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8649 "#"
8650 "&& reload_completed"
8651 [(pc)]
8652 {
8653 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8654 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8655 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8656 operands[1]);
8657 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8658 operands[2]);
8659 DONE;
8660 })
8661
8662 (define_expand "extendsftf2"
8663 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8664 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8665 "!TARGET_IEEEQUAD
8666 && TARGET_HARD_FLOAT
8667 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8668 && TARGET_LONG_DOUBLE_128"
8669 {
8670 rtx tmp = gen_reg_rtx (DFmode);
8671 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8672 emit_insn (gen_extenddftf2 (operands[0], tmp));
8673 DONE;
8674 })
8675
8676 (define_expand "trunctfdf2"
8677 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8678 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8679 "!TARGET_IEEEQUAD
8680 && TARGET_HARD_FLOAT
8681 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8682 && TARGET_LONG_DOUBLE_128"
8683 "")
8684
8685 (define_insn_and_split "trunctfdf2_internal1"
8686 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8687 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
8688 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8689 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8690 "@
8691 #
8692 fmr %0,%1"
8693 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8694 [(const_int 0)]
8695 {
8696 emit_note (NOTE_INSN_DELETED);
8697 DONE;
8698 }
8699 [(set_attr "type" "fp")])
8700
8701 (define_insn "trunctfdf2_internal2"
8702 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8703 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8704 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8705 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8706 "fadd %0,%1,%L1"
8707 [(set_attr "type" "fp")])
8708
8709 (define_expand "trunctfsf2"
8710 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8711 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8712 "!TARGET_IEEEQUAD
8713 && TARGET_HARD_FLOAT
8714 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8715 && TARGET_LONG_DOUBLE_128"
8716 {
8717 if (TARGET_E500_DOUBLE)
8718 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8719 else
8720 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8721 DONE;
8722 })
8723
8724 (define_insn_and_split "trunctfsf2_fprs"
8725 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8726 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8727 (clobber (match_scratch:DF 2 "=f"))]
8728 "!TARGET_IEEEQUAD
8729 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8730 "#"
8731 "&& reload_completed"
8732 [(set (match_dup 2)
8733 (float_truncate:DF (match_dup 1)))
8734 (set (match_dup 0)
8735 (float_truncate:SF (match_dup 2)))]
8736 "")
8737
8738 (define_expand "floatsitf2"
8739 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8740 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
8741 "!TARGET_IEEEQUAD
8742 && TARGET_HARD_FLOAT
8743 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8744 && TARGET_LONG_DOUBLE_128"
8745 {
8746 rtx tmp = gen_reg_rtx (DFmode);
8747 expand_float (tmp, operands[1], false);
8748 emit_insn (gen_extenddftf2 (operands[0], tmp));
8749 DONE;
8750 })
8751
8752 ; fadd, but rounding towards zero.
8753 ; This is probably not the optimal code sequence.
8754 (define_insn "fix_trunc_helper"
8755 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8756 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8757 UNSPEC_FIX_TRUNC_TF))
8758 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8759 "TARGET_HARD_FLOAT && TARGET_FPRS"
8760 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8761 [(set_attr "type" "fp")
8762 (set_attr "length" "20")])
8763
8764 (define_expand "fix_trunctfsi2"
8765 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8766 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8767 "!TARGET_IEEEQUAD
8768 && (TARGET_POWER2 || TARGET_POWERPC)
8769 && TARGET_HARD_FLOAT
8770 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8771 && TARGET_LONG_DOUBLE_128"
8772 {
8773 if (TARGET_E500_DOUBLE)
8774 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8775 else
8776 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8777 DONE;
8778 })
8779
8780 (define_expand "fix_trunctfsi2_fprs"
8781 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8782 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8783 (clobber (match_dup 2))
8784 (clobber (match_dup 3))
8785 (clobber (match_dup 4))
8786 (clobber (match_dup 5))])]
8787 "!TARGET_IEEEQUAD
8788 && (TARGET_POWER2 || TARGET_POWERPC)
8789 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8790 {
8791 operands[2] = gen_reg_rtx (DFmode);
8792 operands[3] = gen_reg_rtx (DFmode);
8793 operands[4] = gen_reg_rtx (DImode);
8794 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8795 })
8796
8797 (define_insn_and_split "*fix_trunctfsi2_internal"
8798 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8799 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8800 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8801 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8802 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8803 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
8804 "!TARGET_IEEEQUAD
8805 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8806 "#"
8807 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[5]))"
8808 [(pc)]
8809 {
8810 rtx lowword;
8811 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8812
8813 gcc_assert (MEM_P (operands[5]));
8814 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8815
8816 emit_insn (gen_fctiwz (operands[4], operands[2]));
8817 emit_move_insn (operands[5], operands[4]);
8818 emit_move_insn (operands[0], lowword);
8819 DONE;
8820 })
8821
8822 (define_expand "negtf2"
8823 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8824 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8825 "!TARGET_IEEEQUAD
8826 && TARGET_HARD_FLOAT
8827 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8828 && TARGET_LONG_DOUBLE_128"
8829 "")
8830
8831 (define_insn "negtf2_internal"
8832 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8833 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8834 "!TARGET_IEEEQUAD
8835 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8836 "*
8837 {
8838 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8839 return \"fneg %L0,%L1\;fneg %0,%1\";
8840 else
8841 return \"fneg %0,%1\;fneg %L0,%L1\";
8842 }"
8843 [(set_attr "type" "fp")
8844 (set_attr "length" "8")])
8845
8846 (define_expand "abstf2"
8847 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8848 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8849 "!TARGET_IEEEQUAD
8850 && TARGET_HARD_FLOAT
8851 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8852 && TARGET_LONG_DOUBLE_128"
8853 "
8854 {
8855 rtx label = gen_label_rtx ();
8856 if (TARGET_E500_DOUBLE)
8857 {
8858 if (flag_unsafe_math_optimizations)
8859 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
8860 else
8861 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
8862 }
8863 else
8864 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8865 emit_label (label);
8866 DONE;
8867 }")
8868
8869 (define_expand "abstf2_internal"
8870 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8871 (match_operand:TF 1 "gpc_reg_operand" ""))
8872 (set (match_dup 3) (match_dup 5))
8873 (set (match_dup 5) (abs:DF (match_dup 5)))
8874 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8875 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8876 (label_ref (match_operand 2 "" ""))
8877 (pc)))
8878 (set (match_dup 6) (neg:DF (match_dup 6)))]
8879 "!TARGET_IEEEQUAD
8880 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8881 "
8882 {
8883 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8884 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8885 operands[3] = gen_reg_rtx (DFmode);
8886 operands[4] = gen_reg_rtx (CCFPmode);
8887 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8888 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8889 }")
8890 \f
8891 ;; Next come the multi-word integer load and store and the load and store
8892 ;; multiple insns.
8893
8894 ; List r->r after r->"o<>", otherwise reload will try to reload a
8895 ; non-offsettable address by using r->r which won't make progress.
8896 (define_insn "*movdi_internal32"
8897 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
8898 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
8899 "! TARGET_POWERPC64
8900 && (gpc_reg_operand (operands[0], DImode)
8901 || gpc_reg_operand (operands[1], DImode))"
8902 "@
8903 #
8904 #
8905 #
8906 fmr %0,%1
8907 lfd%U1%X1 %0,%1
8908 stfd%U0%X0 %1,%0
8909 #"
8910 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
8911
8912 (define_split
8913 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8914 (match_operand:DI 1 "const_int_operand" ""))]
8915 "! TARGET_POWERPC64 && reload_completed"
8916 [(set (match_dup 2) (match_dup 4))
8917 (set (match_dup 3) (match_dup 1))]
8918 "
8919 {
8920 HOST_WIDE_INT value = INTVAL (operands[1]);
8921 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8922 DImode);
8923 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8924 DImode);
8925 #if HOST_BITS_PER_WIDE_INT == 32
8926 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8927 #else
8928 operands[4] = GEN_INT (value >> 32);
8929 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8930 #endif
8931 }")
8932
8933 (define_split
8934 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "")
8935 (match_operand:DI 1 "input_operand" ""))]
8936 "reload_completed && !TARGET_POWERPC64
8937 && gpr_or_gpr_p (operands[0], operands[1])"
8938 [(pc)]
8939 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8940
8941 (define_insn "*movdi_mfpgpr"
8942 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h,r,*f")
8943 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0,*f,r"))]
8944 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8945 && (gpc_reg_operand (operands[0], DImode)
8946 || gpc_reg_operand (operands[1], DImode))"
8947 "@
8948 mr %0,%1
8949 ld%U1%X1 %0,%1
8950 std%U0%X0 %1,%0
8951 li %0,%1
8952 lis %0,%v1
8953 #
8954 {cal|la} %0,%a1
8955 fmr %0,%1
8956 lfd%U1%X1 %0,%1
8957 stfd%U0%X0 %1,%0
8958 mf%1 %0
8959 mt%0 %1
8960 {cror 0,0,0|nop}
8961 mftgpr %0,%1
8962 mffgpr %0,%1"
8963 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
8964 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
8965
8966 (define_insn "*movdi_internal64"
8967 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
8968 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8969 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
8970 && (gpc_reg_operand (operands[0], DImode)
8971 || gpc_reg_operand (operands[1], DImode))"
8972 "@
8973 mr %0,%1
8974 ld%U1%X1 %0,%1
8975 std%U0%X0 %1,%0
8976 li %0,%1
8977 lis %0,%v1
8978 #
8979 {cal|la} %0,%a1
8980 fmr %0,%1
8981 lfd%U1%X1 %0,%1
8982 stfd%U0%X0 %1,%0
8983 mf%1 %0
8984 mt%0 %1
8985 {cror 0,0,0|nop}"
8986 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
8987 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8988
8989 ;; immediate value valid for a single instruction hiding in a const_double
8990 (define_insn ""
8991 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8992 (match_operand:DI 1 "const_double_operand" "F"))]
8993 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8994 && GET_CODE (operands[1]) == CONST_DOUBLE
8995 && num_insns_constant (operands[1], DImode) == 1"
8996 "*
8997 {
8998 return ((unsigned HOST_WIDE_INT)
8999 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
9000 ? \"li %0,%1\" : \"lis %0,%v1\";
9001 }")
9002
9003 ;; Generate all one-bits and clear left or right.
9004 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9005 (define_split
9006 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9007 (match_operand:DI 1 "mask64_operand" ""))]
9008 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9009 [(set (match_dup 0) (const_int -1))
9010 (set (match_dup 0)
9011 (and:DI (rotate:DI (match_dup 0)
9012 (const_int 0))
9013 (match_dup 1)))]
9014 "")
9015
9016 ;; Split a load of a large constant into the appropriate five-instruction
9017 ;; sequence. Handle anything in a constant number of insns.
9018 ;; When non-easy constants can go in the TOC, this should use
9019 ;; easy_fp_constant predicate.
9020 (define_split
9021 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9022 (match_operand:DI 1 "const_int_operand" ""))]
9023 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9024 [(set (match_dup 0) (match_dup 2))
9025 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9026 "
9027 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9028
9029 if (tem == operands[0])
9030 DONE;
9031 else
9032 FAIL;
9033 }")
9034
9035 (define_split
9036 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9037 (match_operand:DI 1 "const_double_operand" ""))]
9038 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9039 [(set (match_dup 0) (match_dup 2))
9040 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9041 "
9042 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9043
9044 if (tem == operands[0])
9045 DONE;
9046 else
9047 FAIL;
9048 }")
9049 \f
9050 ;; TImode is similar, except that we usually want to compute the address into
9051 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
9052 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
9053
9054 ;; We say that MQ is clobbered in the last alternative because the first
9055 ;; alternative would never get used otherwise since it would need a reload
9056 ;; while the 2nd alternative would not. We put memory cases first so they
9057 ;; are preferred. Otherwise, we'd try to reload the output instead of
9058 ;; giving the SCRATCH mq.
9059
9060 (define_insn "*movti_power"
9061 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
9062 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
9063 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
9064 "TARGET_POWER && ! TARGET_POWERPC64
9065 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9066 "*
9067 {
9068 switch (which_alternative)
9069 {
9070 default:
9071 gcc_unreachable ();
9072
9073 case 0:
9074 if (TARGET_STRING)
9075 return \"{stsi|stswi} %1,%P0,16\";
9076 case 1:
9077 case 2:
9078 return \"#\";
9079 case 3:
9080 /* If the address is not used in the output, we can use lsi. Otherwise,
9081 fall through to generating four loads. */
9082 if (TARGET_STRING
9083 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9084 return \"{lsi|lswi} %0,%P1,16\";
9085 /* ... fall through ... */
9086 case 4:
9087 case 5:
9088 return \"#\";
9089 }
9090 }"
9091 [(set_attr "type" "store,store,*,load,load,*")])
9092
9093 (define_insn "*movti_string"
9094 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
9095 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
9096 "! TARGET_POWER && ! TARGET_POWERPC64
9097 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9098 "*
9099 {
9100 switch (which_alternative)
9101 {
9102 default:
9103 gcc_unreachable ();
9104 case 0:
9105 if (TARGET_STRING)
9106 return \"{stsi|stswi} %1,%P0,16\";
9107 case 1:
9108 case 2:
9109 return \"#\";
9110 case 3:
9111 /* If the address is not used in the output, we can use lsi. Otherwise,
9112 fall through to generating four loads. */
9113 if (TARGET_STRING
9114 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9115 return \"{lsi|lswi} %0,%P1,16\";
9116 /* ... fall through ... */
9117 case 4:
9118 case 5:
9119 return \"#\";
9120 }
9121 }"
9122 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")])
9123
9124 (define_insn "*movti_ppc64"
9125 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
9126 (match_operand:TI 1 "input_operand" "r,r,m"))]
9127 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
9128 || gpc_reg_operand (operands[1], TImode))"
9129 "#"
9130 [(set_attr "type" "*,load,store")])
9131
9132 (define_split
9133 [(set (match_operand:TI 0 "gpc_reg_operand" "")
9134 (match_operand:TI 1 "const_double_operand" ""))]
9135 "TARGET_POWERPC64"
9136 [(set (match_dup 2) (match_dup 4))
9137 (set (match_dup 3) (match_dup 5))]
9138 "
9139 {
9140 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9141 TImode);
9142 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9143 TImode);
9144 if (GET_CODE (operands[1]) == CONST_DOUBLE)
9145 {
9146 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9147 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9148 }
9149 else if (GET_CODE (operands[1]) == CONST_INT)
9150 {
9151 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9152 operands[5] = operands[1];
9153 }
9154 else
9155 FAIL;
9156 }")
9157
9158 (define_split
9159 [(set (match_operand:TI 0 "nonimmediate_operand" "")
9160 (match_operand:TI 1 "input_operand" ""))]
9161 "reload_completed
9162 && gpr_or_gpr_p (operands[0], operands[1])"
9163 [(pc)]
9164 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9165 \f
9166 (define_expand "load_multiple"
9167 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9168 (match_operand:SI 1 "" ""))
9169 (use (match_operand:SI 2 "" ""))])]
9170 "TARGET_STRING && !TARGET_POWERPC64"
9171 "
9172 {
9173 int regno;
9174 int count;
9175 rtx op1;
9176 int i;
9177
9178 /* Support only loading a constant number of fixed-point registers from
9179 memory and only bother with this if more than two; the machine
9180 doesn't support more than eight. */
9181 if (GET_CODE (operands[2]) != CONST_INT
9182 || INTVAL (operands[2]) <= 2
9183 || INTVAL (operands[2]) > 8
9184 || GET_CODE (operands[1]) != MEM
9185 || GET_CODE (operands[0]) != REG
9186 || REGNO (operands[0]) >= 32)
9187 FAIL;
9188
9189 count = INTVAL (operands[2]);
9190 regno = REGNO (operands[0]);
9191
9192 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9193 op1 = replace_equiv_address (operands[1],
9194 force_reg (SImode, XEXP (operands[1], 0)));
9195
9196 for (i = 0; i < count; i++)
9197 XVECEXP (operands[3], 0, i)
9198 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
9199 adjust_address_nv (op1, SImode, i * 4));
9200 }")
9201
9202 (define_insn "*ldmsi8"
9203 [(match_parallel 0 "load_multiple_operation"
9204 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9205 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9206 (set (match_operand:SI 3 "gpc_reg_operand" "")
9207 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9208 (set (match_operand:SI 4 "gpc_reg_operand" "")
9209 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9210 (set (match_operand:SI 5 "gpc_reg_operand" "")
9211 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9212 (set (match_operand:SI 6 "gpc_reg_operand" "")
9213 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9214 (set (match_operand:SI 7 "gpc_reg_operand" "")
9215 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9216 (set (match_operand:SI 8 "gpc_reg_operand" "")
9217 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9218 (set (match_operand:SI 9 "gpc_reg_operand" "")
9219 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9220 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9221 "*
9222 { return rs6000_output_load_multiple (operands); }"
9223 [(set_attr "type" "load_ux")
9224 (set_attr "length" "32")])
9225
9226 (define_insn "*ldmsi7"
9227 [(match_parallel 0 "load_multiple_operation"
9228 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9229 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9230 (set (match_operand:SI 3 "gpc_reg_operand" "")
9231 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9232 (set (match_operand:SI 4 "gpc_reg_operand" "")
9233 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9234 (set (match_operand:SI 5 "gpc_reg_operand" "")
9235 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9236 (set (match_operand:SI 6 "gpc_reg_operand" "")
9237 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9238 (set (match_operand:SI 7 "gpc_reg_operand" "")
9239 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9240 (set (match_operand:SI 8 "gpc_reg_operand" "")
9241 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9242 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9243 "*
9244 { return rs6000_output_load_multiple (operands); }"
9245 [(set_attr "type" "load_ux")
9246 (set_attr "length" "32")])
9247
9248 (define_insn "*ldmsi6"
9249 [(match_parallel 0 "load_multiple_operation"
9250 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9251 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9252 (set (match_operand:SI 3 "gpc_reg_operand" "")
9253 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9254 (set (match_operand:SI 4 "gpc_reg_operand" "")
9255 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9256 (set (match_operand:SI 5 "gpc_reg_operand" "")
9257 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9258 (set (match_operand:SI 6 "gpc_reg_operand" "")
9259 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9260 (set (match_operand:SI 7 "gpc_reg_operand" "")
9261 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9262 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9263 "*
9264 { return rs6000_output_load_multiple (operands); }"
9265 [(set_attr "type" "load_ux")
9266 (set_attr "length" "32")])
9267
9268 (define_insn "*ldmsi5"
9269 [(match_parallel 0 "load_multiple_operation"
9270 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9271 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9272 (set (match_operand:SI 3 "gpc_reg_operand" "")
9273 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9274 (set (match_operand:SI 4 "gpc_reg_operand" "")
9275 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9276 (set (match_operand:SI 5 "gpc_reg_operand" "")
9277 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9278 (set (match_operand:SI 6 "gpc_reg_operand" "")
9279 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9280 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9281 "*
9282 { return rs6000_output_load_multiple (operands); }"
9283 [(set_attr "type" "load_ux")
9284 (set_attr "length" "32")])
9285
9286 (define_insn "*ldmsi4"
9287 [(match_parallel 0 "load_multiple_operation"
9288 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9289 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9290 (set (match_operand:SI 3 "gpc_reg_operand" "")
9291 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9292 (set (match_operand:SI 4 "gpc_reg_operand" "")
9293 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9294 (set (match_operand:SI 5 "gpc_reg_operand" "")
9295 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9296 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9297 "*
9298 { return rs6000_output_load_multiple (operands); }"
9299 [(set_attr "type" "load_ux")
9300 (set_attr "length" "32")])
9301
9302 (define_insn "*ldmsi3"
9303 [(match_parallel 0 "load_multiple_operation"
9304 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9305 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9306 (set (match_operand:SI 3 "gpc_reg_operand" "")
9307 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9308 (set (match_operand:SI 4 "gpc_reg_operand" "")
9309 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9310 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9311 "*
9312 { return rs6000_output_load_multiple (operands); }"
9313 [(set_attr "type" "load_ux")
9314 (set_attr "length" "32")])
9315
9316 (define_expand "store_multiple"
9317 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9318 (match_operand:SI 1 "" ""))
9319 (clobber (scratch:SI))
9320 (use (match_operand:SI 2 "" ""))])]
9321 "TARGET_STRING && !TARGET_POWERPC64"
9322 "
9323 {
9324 int regno;
9325 int count;
9326 rtx to;
9327 rtx op0;
9328 int i;
9329
9330 /* Support only storing a constant number of fixed-point registers to
9331 memory and only bother with this if more than two; the machine
9332 doesn't support more than eight. */
9333 if (GET_CODE (operands[2]) != CONST_INT
9334 || INTVAL (operands[2]) <= 2
9335 || INTVAL (operands[2]) > 8
9336 || GET_CODE (operands[0]) != MEM
9337 || GET_CODE (operands[1]) != REG
9338 || REGNO (operands[1]) >= 32)
9339 FAIL;
9340
9341 count = INTVAL (operands[2]);
9342 regno = REGNO (operands[1]);
9343
9344 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
9345 to = force_reg (SImode, XEXP (operands[0], 0));
9346 op0 = replace_equiv_address (operands[0], to);
9347
9348 XVECEXP (operands[3], 0, 0)
9349 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
9350 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
9351 gen_rtx_SCRATCH (SImode));
9352
9353 for (i = 1; i < count; i++)
9354 XVECEXP (operands[3], 0, i + 1)
9355 = gen_rtx_SET (VOIDmode,
9356 adjust_address_nv (op0, SImode, i * 4),
9357 gen_rtx_REG (SImode, regno + i));
9358 }")
9359
9360 (define_insn "*stmsi8"
9361 [(match_parallel 0 "store_multiple_operation"
9362 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9363 (match_operand:SI 2 "gpc_reg_operand" "r"))
9364 (clobber (match_scratch:SI 3 "=X"))
9365 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9366 (match_operand:SI 4 "gpc_reg_operand" "r"))
9367 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9368 (match_operand:SI 5 "gpc_reg_operand" "r"))
9369 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9370 (match_operand:SI 6 "gpc_reg_operand" "r"))
9371 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9372 (match_operand:SI 7 "gpc_reg_operand" "r"))
9373 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9374 (match_operand:SI 8 "gpc_reg_operand" "r"))
9375 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9376 (match_operand:SI 9 "gpc_reg_operand" "r"))
9377 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9378 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9379 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9380 "{stsi|stswi} %2,%1,%O0"
9381 [(set_attr "type" "store_ux")])
9382
9383 (define_insn "*stmsi7"
9384 [(match_parallel 0 "store_multiple_operation"
9385 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9386 (match_operand:SI 2 "gpc_reg_operand" "r"))
9387 (clobber (match_scratch:SI 3 "=X"))
9388 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9389 (match_operand:SI 4 "gpc_reg_operand" "r"))
9390 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9391 (match_operand:SI 5 "gpc_reg_operand" "r"))
9392 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9393 (match_operand:SI 6 "gpc_reg_operand" "r"))
9394 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9395 (match_operand:SI 7 "gpc_reg_operand" "r"))
9396 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9397 (match_operand:SI 8 "gpc_reg_operand" "r"))
9398 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9399 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9400 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9401 "{stsi|stswi} %2,%1,%O0"
9402 [(set_attr "type" "store_ux")])
9403
9404 (define_insn "*stmsi6"
9405 [(match_parallel 0 "store_multiple_operation"
9406 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9407 (match_operand:SI 2 "gpc_reg_operand" "r"))
9408 (clobber (match_scratch:SI 3 "=X"))
9409 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9410 (match_operand:SI 4 "gpc_reg_operand" "r"))
9411 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9412 (match_operand:SI 5 "gpc_reg_operand" "r"))
9413 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9414 (match_operand:SI 6 "gpc_reg_operand" "r"))
9415 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9416 (match_operand:SI 7 "gpc_reg_operand" "r"))
9417 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9418 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9419 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9420 "{stsi|stswi} %2,%1,%O0"
9421 [(set_attr "type" "store_ux")])
9422
9423 (define_insn "*stmsi5"
9424 [(match_parallel 0 "store_multiple_operation"
9425 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9426 (match_operand:SI 2 "gpc_reg_operand" "r"))
9427 (clobber (match_scratch:SI 3 "=X"))
9428 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9429 (match_operand:SI 4 "gpc_reg_operand" "r"))
9430 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9431 (match_operand:SI 5 "gpc_reg_operand" "r"))
9432 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9433 (match_operand:SI 6 "gpc_reg_operand" "r"))
9434 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9435 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9436 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9437 "{stsi|stswi} %2,%1,%O0"
9438 [(set_attr "type" "store_ux")])
9439
9440 (define_insn "*stmsi4"
9441 [(match_parallel 0 "store_multiple_operation"
9442 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9443 (match_operand:SI 2 "gpc_reg_operand" "r"))
9444 (clobber (match_scratch:SI 3 "=X"))
9445 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9446 (match_operand:SI 4 "gpc_reg_operand" "r"))
9447 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9448 (match_operand:SI 5 "gpc_reg_operand" "r"))
9449 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9450 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9451 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9452 "{stsi|stswi} %2,%1,%O0"
9453 [(set_attr "type" "store_ux")])
9454
9455 (define_insn "*stmsi3"
9456 [(match_parallel 0 "store_multiple_operation"
9457 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9458 (match_operand:SI 2 "gpc_reg_operand" "r"))
9459 (clobber (match_scratch:SI 3 "=X"))
9460 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9461 (match_operand:SI 4 "gpc_reg_operand" "r"))
9462 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9463 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9464 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9465 "{stsi|stswi} %2,%1,%O0"
9466 [(set_attr "type" "store_ux")])
9467
9468 (define_insn "*stmsi8_power"
9469 [(match_parallel 0 "store_multiple_operation"
9470 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9471 (match_operand:SI 2 "gpc_reg_operand" "r"))
9472 (clobber (match_scratch:SI 3 "=q"))
9473 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9474 (match_operand:SI 4 "gpc_reg_operand" "r"))
9475 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9476 (match_operand:SI 5 "gpc_reg_operand" "r"))
9477 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9478 (match_operand:SI 6 "gpc_reg_operand" "r"))
9479 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9480 (match_operand:SI 7 "gpc_reg_operand" "r"))
9481 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9482 (match_operand:SI 8 "gpc_reg_operand" "r"))
9483 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9484 (match_operand:SI 9 "gpc_reg_operand" "r"))
9485 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9486 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9487 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9488 "{stsi|stswi} %2,%1,%O0"
9489 [(set_attr "type" "store_ux")])
9490
9491 (define_insn "*stmsi7_power"
9492 [(match_parallel 0 "store_multiple_operation"
9493 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9494 (match_operand:SI 2 "gpc_reg_operand" "r"))
9495 (clobber (match_scratch:SI 3 "=q"))
9496 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9497 (match_operand:SI 4 "gpc_reg_operand" "r"))
9498 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9499 (match_operand:SI 5 "gpc_reg_operand" "r"))
9500 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9501 (match_operand:SI 6 "gpc_reg_operand" "r"))
9502 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9503 (match_operand:SI 7 "gpc_reg_operand" "r"))
9504 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9505 (match_operand:SI 8 "gpc_reg_operand" "r"))
9506 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9507 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9508 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9509 "{stsi|stswi} %2,%1,%O0"
9510 [(set_attr "type" "store_ux")])
9511
9512 (define_insn "*stmsi6_power"
9513 [(match_parallel 0 "store_multiple_operation"
9514 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9515 (match_operand:SI 2 "gpc_reg_operand" "r"))
9516 (clobber (match_scratch:SI 3 "=q"))
9517 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9518 (match_operand:SI 4 "gpc_reg_operand" "r"))
9519 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9520 (match_operand:SI 5 "gpc_reg_operand" "r"))
9521 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9522 (match_operand:SI 6 "gpc_reg_operand" "r"))
9523 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9524 (match_operand:SI 7 "gpc_reg_operand" "r"))
9525 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9526 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9527 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9528 "{stsi|stswi} %2,%1,%O0"
9529 [(set_attr "type" "store_ux")])
9530
9531 (define_insn "*stmsi5_power"
9532 [(match_parallel 0 "store_multiple_operation"
9533 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9534 (match_operand:SI 2 "gpc_reg_operand" "r"))
9535 (clobber (match_scratch:SI 3 "=q"))
9536 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9537 (match_operand:SI 4 "gpc_reg_operand" "r"))
9538 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9539 (match_operand:SI 5 "gpc_reg_operand" "r"))
9540 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9541 (match_operand:SI 6 "gpc_reg_operand" "r"))
9542 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9543 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9544 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9545 "{stsi|stswi} %2,%1,%O0"
9546 [(set_attr "type" "store_ux")])
9547
9548 (define_insn "*stmsi4_power"
9549 [(match_parallel 0 "store_multiple_operation"
9550 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9551 (match_operand:SI 2 "gpc_reg_operand" "r"))
9552 (clobber (match_scratch:SI 3 "=q"))
9553 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9554 (match_operand:SI 4 "gpc_reg_operand" "r"))
9555 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9556 (match_operand:SI 5 "gpc_reg_operand" "r"))
9557 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9558 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9559 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9560 "{stsi|stswi} %2,%1,%O0"
9561 [(set_attr "type" "store_ux")])
9562
9563 (define_insn "*stmsi3_power"
9564 [(match_parallel 0 "store_multiple_operation"
9565 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9566 (match_operand:SI 2 "gpc_reg_operand" "r"))
9567 (clobber (match_scratch:SI 3 "=q"))
9568 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9569 (match_operand:SI 4 "gpc_reg_operand" "r"))
9570 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9571 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9572 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9573 "{stsi|stswi} %2,%1,%O0"
9574 [(set_attr "type" "store_ux")])
9575 \f
9576 (define_expand "setmemsi"
9577 [(parallel [(set (match_operand:BLK 0 "" "")
9578 (match_operand 2 "const_int_operand" ""))
9579 (use (match_operand:SI 1 "" ""))
9580 (use (match_operand:SI 3 "" ""))])]
9581 ""
9582 "
9583 {
9584 /* If value to set is not zero, use the library routine. */
9585 if (operands[2] != const0_rtx)
9586 FAIL;
9587
9588 if (expand_block_clear (operands))
9589 DONE;
9590 else
9591 FAIL;
9592 }")
9593
9594 ;; String/block move insn.
9595 ;; Argument 0 is the destination
9596 ;; Argument 1 is the source
9597 ;; Argument 2 is the length
9598 ;; Argument 3 is the alignment
9599
9600 (define_expand "movmemsi"
9601 [(parallel [(set (match_operand:BLK 0 "" "")
9602 (match_operand:BLK 1 "" ""))
9603 (use (match_operand:SI 2 "" ""))
9604 (use (match_operand:SI 3 "" ""))])]
9605 ""
9606 "
9607 {
9608 if (expand_block_move (operands))
9609 DONE;
9610 else
9611 FAIL;
9612 }")
9613
9614 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9615 ;; register allocator doesn't have a clue about allocating 8 word registers.
9616 ;; rD/rS = r5 is preferred, efficient form.
9617 (define_expand "movmemsi_8reg"
9618 [(parallel [(set (match_operand 0 "" "")
9619 (match_operand 1 "" ""))
9620 (use (match_operand 2 "" ""))
9621 (use (match_operand 3 "" ""))
9622 (clobber (reg:SI 5))
9623 (clobber (reg:SI 6))
9624 (clobber (reg:SI 7))
9625 (clobber (reg:SI 8))
9626 (clobber (reg:SI 9))
9627 (clobber (reg:SI 10))
9628 (clobber (reg:SI 11))
9629 (clobber (reg:SI 12))
9630 (clobber (match_scratch:SI 4 ""))])]
9631 "TARGET_STRING"
9632 "")
9633
9634 (define_insn ""
9635 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9636 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9637 (use (match_operand:SI 2 "immediate_operand" "i"))
9638 (use (match_operand:SI 3 "immediate_operand" "i"))
9639 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9640 (clobber (reg:SI 6))
9641 (clobber (reg:SI 7))
9642 (clobber (reg:SI 8))
9643 (clobber (reg:SI 9))
9644 (clobber (reg:SI 10))
9645 (clobber (reg:SI 11))
9646 (clobber (reg:SI 12))
9647 (clobber (match_scratch:SI 5 "=q"))]
9648 "TARGET_STRING && TARGET_POWER
9649 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9650 || INTVAL (operands[2]) == 0)
9651 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9652 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9653 && REGNO (operands[4]) == 5"
9654 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9655 [(set_attr "type" "store_ux")
9656 (set_attr "length" "8")])
9657
9658 (define_insn ""
9659 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9660 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9661 (use (match_operand:SI 2 "immediate_operand" "i"))
9662 (use (match_operand:SI 3 "immediate_operand" "i"))
9663 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9664 (clobber (reg:SI 6))
9665 (clobber (reg:SI 7))
9666 (clobber (reg:SI 8))
9667 (clobber (reg:SI 9))
9668 (clobber (reg:SI 10))
9669 (clobber (reg:SI 11))
9670 (clobber (reg:SI 12))
9671 (clobber (match_scratch:SI 5 "=X"))]
9672 "TARGET_STRING && ! TARGET_POWER
9673 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9674 || INTVAL (operands[2]) == 0)
9675 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9676 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9677 && REGNO (operands[4]) == 5"
9678 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9679 [(set_attr "type" "store_ux")
9680 (set_attr "length" "8")])
9681
9682 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9683 ;; register allocator doesn't have a clue about allocating 6 word registers.
9684 ;; rD/rS = r5 is preferred, efficient form.
9685 (define_expand "movmemsi_6reg"
9686 [(parallel [(set (match_operand 0 "" "")
9687 (match_operand 1 "" ""))
9688 (use (match_operand 2 "" ""))
9689 (use (match_operand 3 "" ""))
9690 (clobber (reg:SI 5))
9691 (clobber (reg:SI 6))
9692 (clobber (reg:SI 7))
9693 (clobber (reg:SI 8))
9694 (clobber (reg:SI 9))
9695 (clobber (reg:SI 10))
9696 (clobber (match_scratch:SI 4 ""))])]
9697 "TARGET_STRING"
9698 "")
9699
9700 (define_insn ""
9701 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9702 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9703 (use (match_operand:SI 2 "immediate_operand" "i"))
9704 (use (match_operand:SI 3 "immediate_operand" "i"))
9705 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9706 (clobber (reg:SI 6))
9707 (clobber (reg:SI 7))
9708 (clobber (reg:SI 8))
9709 (clobber (reg:SI 9))
9710 (clobber (reg:SI 10))
9711 (clobber (match_scratch:SI 5 "=q"))]
9712 "TARGET_STRING && TARGET_POWER
9713 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9714 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9715 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9716 && REGNO (operands[4]) == 5"
9717 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9718 [(set_attr "type" "store_ux")
9719 (set_attr "length" "8")])
9720
9721 (define_insn ""
9722 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9723 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9724 (use (match_operand:SI 2 "immediate_operand" "i"))
9725 (use (match_operand:SI 3 "immediate_operand" "i"))
9726 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9727 (clobber (reg:SI 6))
9728 (clobber (reg:SI 7))
9729 (clobber (reg:SI 8))
9730 (clobber (reg:SI 9))
9731 (clobber (reg:SI 10))
9732 (clobber (match_scratch:SI 5 "=X"))]
9733 "TARGET_STRING && ! TARGET_POWER
9734 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9735 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9736 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9737 && REGNO (operands[4]) == 5"
9738 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9739 [(set_attr "type" "store_ux")
9740 (set_attr "length" "8")])
9741
9742 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9743 ;; problems with TImode.
9744 ;; rD/rS = r5 is preferred, efficient form.
9745 (define_expand "movmemsi_4reg"
9746 [(parallel [(set (match_operand 0 "" "")
9747 (match_operand 1 "" ""))
9748 (use (match_operand 2 "" ""))
9749 (use (match_operand 3 "" ""))
9750 (clobber (reg:SI 5))
9751 (clobber (reg:SI 6))
9752 (clobber (reg:SI 7))
9753 (clobber (reg:SI 8))
9754 (clobber (match_scratch:SI 4 ""))])]
9755 "TARGET_STRING"
9756 "")
9757
9758 (define_insn ""
9759 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9760 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9761 (use (match_operand:SI 2 "immediate_operand" "i"))
9762 (use (match_operand:SI 3 "immediate_operand" "i"))
9763 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9764 (clobber (reg:SI 6))
9765 (clobber (reg:SI 7))
9766 (clobber (reg:SI 8))
9767 (clobber (match_scratch:SI 5 "=q"))]
9768 "TARGET_STRING && TARGET_POWER
9769 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9770 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9771 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9772 && REGNO (operands[4]) == 5"
9773 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9774 [(set_attr "type" "store_ux")
9775 (set_attr "length" "8")])
9776
9777 (define_insn ""
9778 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9779 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9780 (use (match_operand:SI 2 "immediate_operand" "i"))
9781 (use (match_operand:SI 3 "immediate_operand" "i"))
9782 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9783 (clobber (reg:SI 6))
9784 (clobber (reg:SI 7))
9785 (clobber (reg:SI 8))
9786 (clobber (match_scratch:SI 5 "=X"))]
9787 "TARGET_STRING && ! TARGET_POWER
9788 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9789 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9790 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9791 && REGNO (operands[4]) == 5"
9792 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9793 [(set_attr "type" "store_ux")
9794 (set_attr "length" "8")])
9795
9796 ;; Move up to 8 bytes at a time.
9797 (define_expand "movmemsi_2reg"
9798 [(parallel [(set (match_operand 0 "" "")
9799 (match_operand 1 "" ""))
9800 (use (match_operand 2 "" ""))
9801 (use (match_operand 3 "" ""))
9802 (clobber (match_scratch:DI 4 ""))
9803 (clobber (match_scratch:SI 5 ""))])]
9804 "TARGET_STRING && ! TARGET_POWERPC64"
9805 "")
9806
9807 (define_insn ""
9808 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9809 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9810 (use (match_operand:SI 2 "immediate_operand" "i"))
9811 (use (match_operand:SI 3 "immediate_operand" "i"))
9812 (clobber (match_scratch:DI 4 "=&r"))
9813 (clobber (match_scratch:SI 5 "=q"))]
9814 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9815 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9816 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9817 [(set_attr "type" "store_ux")
9818 (set_attr "length" "8")])
9819
9820 (define_insn ""
9821 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9822 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9823 (use (match_operand:SI 2 "immediate_operand" "i"))
9824 (use (match_operand:SI 3 "immediate_operand" "i"))
9825 (clobber (match_scratch:DI 4 "=&r"))
9826 (clobber (match_scratch:SI 5 "=X"))]
9827 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9828 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9829 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9830 [(set_attr "type" "store_ux")
9831 (set_attr "length" "8")])
9832
9833 ;; Move up to 4 bytes at a time.
9834 (define_expand "movmemsi_1reg"
9835 [(parallel [(set (match_operand 0 "" "")
9836 (match_operand 1 "" ""))
9837 (use (match_operand 2 "" ""))
9838 (use (match_operand 3 "" ""))
9839 (clobber (match_scratch:SI 4 ""))
9840 (clobber (match_scratch:SI 5 ""))])]
9841 "TARGET_STRING"
9842 "")
9843
9844 (define_insn ""
9845 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9846 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9847 (use (match_operand:SI 2 "immediate_operand" "i"))
9848 (use (match_operand:SI 3 "immediate_operand" "i"))
9849 (clobber (match_scratch:SI 4 "=&r"))
9850 (clobber (match_scratch:SI 5 "=q"))]
9851 "TARGET_STRING && TARGET_POWER
9852 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9853 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9854 [(set_attr "type" "store_ux")
9855 (set_attr "length" "8")])
9856
9857 (define_insn ""
9858 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9859 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9860 (use (match_operand:SI 2 "immediate_operand" "i"))
9861 (use (match_operand:SI 3 "immediate_operand" "i"))
9862 (clobber (match_scratch:SI 4 "=&r"))
9863 (clobber (match_scratch:SI 5 "=X"))]
9864 "TARGET_STRING && ! TARGET_POWER
9865 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9866 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9867 [(set_attr "type" "store_ux")
9868 (set_attr "length" "8")])
9869 \f
9870 ;; Define insns that do load or store with update. Some of these we can
9871 ;; get by using pre-decrement or pre-increment, but the hardware can also
9872 ;; do cases where the increment is not the size of the object.
9873 ;;
9874 ;; In all these cases, we use operands 0 and 1 for the register being
9875 ;; incremented because those are the operands that local-alloc will
9876 ;; tie and these are the pair most likely to be tieable (and the ones
9877 ;; that will benefit the most).
9878
9879 (define_insn "*movdi_update1"
9880 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9881 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9882 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9883 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9884 (plus:DI (match_dup 1) (match_dup 2)))]
9885 "TARGET_POWERPC64 && TARGET_UPDATE"
9886 "@
9887 ldux %3,%0,%2
9888 ldu %3,%2(%0)"
9889 [(set_attr "type" "load_ux,load_u")])
9890
9891 (define_insn "movdi_<mode>_update"
9892 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9893 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9894 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9895 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9896 (plus:P (match_dup 1) (match_dup 2)))]
9897 "TARGET_POWERPC64 && TARGET_UPDATE"
9898 "@
9899 stdux %3,%0,%2
9900 stdu %3,%2(%0)"
9901 [(set_attr "type" "store_ux,store_u")])
9902
9903 (define_insn "*movsi_update1"
9904 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9905 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9906 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9907 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9908 (plus:SI (match_dup 1) (match_dup 2)))]
9909 "TARGET_UPDATE"
9910 "@
9911 {lux|lwzux} %3,%0,%2
9912 {lu|lwzu} %3,%2(%0)"
9913 [(set_attr "type" "load_ux,load_u")])
9914
9915 (define_insn "*movsi_update2"
9916 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9917 (sign_extend:DI
9918 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9919 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9920 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9921 (plus:DI (match_dup 1) (match_dup 2)))]
9922 "TARGET_POWERPC64"
9923 "lwaux %3,%0,%2"
9924 [(set_attr "type" "load_ext_ux")])
9925
9926 (define_insn "movsi_update"
9927 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9928 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9929 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9930 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9931 (plus:SI (match_dup 1) (match_dup 2)))]
9932 "TARGET_UPDATE"
9933 "@
9934 {stux|stwux} %3,%0,%2
9935 {stu|stwu} %3,%2(%0)"
9936 [(set_attr "type" "store_ux,store_u")])
9937
9938 (define_insn "*movhi_update1"
9939 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9940 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9941 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9942 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9943 (plus:SI (match_dup 1) (match_dup 2)))]
9944 "TARGET_UPDATE"
9945 "@
9946 lhzux %3,%0,%2
9947 lhzu %3,%2(%0)"
9948 [(set_attr "type" "load_ux,load_u")])
9949
9950 (define_insn "*movhi_update2"
9951 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9952 (zero_extend:SI
9953 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9954 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9955 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9956 (plus:SI (match_dup 1) (match_dup 2)))]
9957 "TARGET_UPDATE"
9958 "@
9959 lhzux %3,%0,%2
9960 lhzu %3,%2(%0)"
9961 [(set_attr "type" "load_ux,load_u")])
9962
9963 (define_insn "*movhi_update3"
9964 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9965 (sign_extend:SI
9966 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9967 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9968 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9969 (plus:SI (match_dup 1) (match_dup 2)))]
9970 "TARGET_UPDATE"
9971 "@
9972 lhaux %3,%0,%2
9973 lhau %3,%2(%0)"
9974 [(set_attr "type" "load_ext_ux,load_ext_u")])
9975
9976 (define_insn "*movhi_update4"
9977 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9978 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9979 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9980 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9981 (plus:SI (match_dup 1) (match_dup 2)))]
9982 "TARGET_UPDATE"
9983 "@
9984 sthux %3,%0,%2
9985 sthu %3,%2(%0)"
9986 [(set_attr "type" "store_ux,store_u")])
9987
9988 (define_insn "*movqi_update1"
9989 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9990 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9991 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9992 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9993 (plus:SI (match_dup 1) (match_dup 2)))]
9994 "TARGET_UPDATE"
9995 "@
9996 lbzux %3,%0,%2
9997 lbzu %3,%2(%0)"
9998 [(set_attr "type" "load_ux,load_u")])
9999
10000 (define_insn "*movqi_update2"
10001 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10002 (zero_extend:SI
10003 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10004 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10005 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10006 (plus:SI (match_dup 1) (match_dup 2)))]
10007 "TARGET_UPDATE"
10008 "@
10009 lbzux %3,%0,%2
10010 lbzu %3,%2(%0)"
10011 [(set_attr "type" "load_ux,load_u")])
10012
10013 (define_insn "*movqi_update3"
10014 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10015 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10016 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
10017 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10018 (plus:SI (match_dup 1) (match_dup 2)))]
10019 "TARGET_UPDATE"
10020 "@
10021 stbux %3,%0,%2
10022 stbu %3,%2(%0)"
10023 [(set_attr "type" "store_ux,store_u")])
10024
10025 (define_insn "*movsf_update1"
10026 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
10027 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10028 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10029 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10030 (plus:SI (match_dup 1) (match_dup 2)))]
10031 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
10032 "@
10033 lfsux %3,%0,%2
10034 lfsu %3,%2(%0)"
10035 [(set_attr "type" "fpload_ux,fpload_u")])
10036
10037 (define_insn "*movsf_update2"
10038 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10039 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10040 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10041 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10042 (plus:SI (match_dup 1) (match_dup 2)))]
10043 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
10044 "@
10045 stfsux %3,%0,%2
10046 stfsu %3,%2(%0)"
10047 [(set_attr "type" "fpstore_ux,fpstore_u")])
10048
10049 (define_insn "*movsf_update3"
10050 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10051 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10052 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10053 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10054 (plus:SI (match_dup 1) (match_dup 2)))]
10055 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
10056 "@
10057 {lux|lwzux} %3,%0,%2
10058 {lu|lwzu} %3,%2(%0)"
10059 [(set_attr "type" "load_ux,load_u")])
10060
10061 (define_insn "*movsf_update4"
10062 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10063 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10064 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10065 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10066 (plus:SI (match_dup 1) (match_dup 2)))]
10067 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
10068 "@
10069 {stux|stwux} %3,%0,%2
10070 {stu|stwu} %3,%2(%0)"
10071 [(set_attr "type" "store_ux,store_u")])
10072
10073 (define_insn "*movdf_update1"
10074 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
10075 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10076 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10077 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10078 (plus:SI (match_dup 1) (match_dup 2)))]
10079 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
10080 "@
10081 lfdux %3,%0,%2
10082 lfdu %3,%2(%0)"
10083 [(set_attr "type" "fpload_ux,fpload_u")])
10084
10085 (define_insn "*movdf_update2"
10086 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10087 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10088 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
10089 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10090 (plus:SI (match_dup 1) (match_dup 2)))]
10091 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
10092 "@
10093 stfdux %3,%0,%2
10094 stfdu %3,%2(%0)"
10095 [(set_attr "type" "fpstore_ux,fpstore_u")])
10096
10097 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
10098
10099 (define_insn "*lfq_power2"
10100 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
10101 (match_operand:V2DF 1 "memory_operand" ""))]
10102 "TARGET_POWER2
10103 && TARGET_HARD_FLOAT && TARGET_FPRS"
10104 "lfq%U1%X1 %0,%1")
10105
10106 (define_peephole2
10107 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10108 (match_operand:DF 1 "memory_operand" ""))
10109 (set (match_operand:DF 2 "gpc_reg_operand" "")
10110 (match_operand:DF 3 "memory_operand" ""))]
10111 "TARGET_POWER2
10112 && TARGET_HARD_FLOAT && TARGET_FPRS
10113 && registers_ok_for_quad_peep (operands[0], operands[2])
10114 && mems_ok_for_quad_peep (operands[1], operands[3])"
10115 [(set (match_dup 0)
10116 (match_dup 1))]
10117 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
10118 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
10119
10120 (define_insn "*stfq_power2"
10121 [(set (match_operand:V2DF 0 "memory_operand" "")
10122 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
10123 "TARGET_POWER2
10124 && TARGET_HARD_FLOAT && TARGET_FPRS"
10125 "stfq%U0%X0 %1,%0")
10126
10127
10128 (define_peephole2
10129 [(set (match_operand:DF 0 "memory_operand" "")
10130 (match_operand:DF 1 "gpc_reg_operand" ""))
10131 (set (match_operand:DF 2 "memory_operand" "")
10132 (match_operand:DF 3 "gpc_reg_operand" ""))]
10133 "TARGET_POWER2
10134 && TARGET_HARD_FLOAT && TARGET_FPRS
10135 && registers_ok_for_quad_peep (operands[1], operands[3])
10136 && mems_ok_for_quad_peep (operands[0], operands[2])"
10137 [(set (match_dup 0)
10138 (match_dup 1))]
10139 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
10140 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
10141
10142 ;; After inserting conditional returns we can sometimes have
10143 ;; unnecessary register moves. Unfortunately we cannot have a
10144 ;; modeless peephole here, because some single SImode sets have early
10145 ;; clobber outputs. Although those sets expand to multi-ppc-insn
10146 ;; sequences, using get_attr_length here will smash the operands
10147 ;; array. Neither is there an early_cobbler_p predicate.
10148 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
10149 (define_peephole2
10150 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10151 (match_operand:DF 1 "any_operand" ""))
10152 (set (match_operand:DF 2 "gpc_reg_operand" "")
10153 (match_dup 0))]
10154 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10155 && peep2_reg_dead_p (2, operands[0])"
10156 [(set (match_dup 2) (match_dup 1))])
10157
10158 (define_peephole2
10159 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10160 (match_operand:SF 1 "any_operand" ""))
10161 (set (match_operand:SF 2 "gpc_reg_operand" "")
10162 (match_dup 0))]
10163 "peep2_reg_dead_p (2, operands[0])"
10164 [(set (match_dup 2) (match_dup 1))])
10165
10166 \f
10167 ;; TLS support.
10168
10169 ;; "b" output constraint here and on tls_ld to support tls linker optimization.
10170 (define_insn "tls_gd_32"
10171 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10172 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10173 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10174 UNSPEC_TLSGD))]
10175 "HAVE_AS_TLS && !TARGET_64BIT"
10176 "addi %0,%1,%2@got@tlsgd")
10177
10178 (define_insn "tls_gd_64"
10179 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10180 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10181 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10182 UNSPEC_TLSGD))]
10183 "HAVE_AS_TLS && TARGET_64BIT"
10184 "addi %0,%1,%2@got@tlsgd")
10185
10186 (define_insn "tls_ld_32"
10187 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10188 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
10189 UNSPEC_TLSLD))]
10190 "HAVE_AS_TLS && !TARGET_64BIT"
10191 "addi %0,%1,%&@got@tlsld")
10192
10193 (define_insn "tls_ld_64"
10194 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10195 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
10196 UNSPEC_TLSLD))]
10197 "HAVE_AS_TLS && TARGET_64BIT"
10198 "addi %0,%1,%&@got@tlsld")
10199
10200 (define_insn "tls_dtprel_32"
10201 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10202 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10203 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10204 UNSPEC_TLSDTPREL))]
10205 "HAVE_AS_TLS && !TARGET_64BIT"
10206 "addi %0,%1,%2@dtprel")
10207
10208 (define_insn "tls_dtprel_64"
10209 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10210 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10211 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10212 UNSPEC_TLSDTPREL))]
10213 "HAVE_AS_TLS && TARGET_64BIT"
10214 "addi %0,%1,%2@dtprel")
10215
10216 (define_insn "tls_dtprel_ha_32"
10217 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10218 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10219 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10220 UNSPEC_TLSDTPRELHA))]
10221 "HAVE_AS_TLS && !TARGET_64BIT"
10222 "addis %0,%1,%2@dtprel@ha")
10223
10224 (define_insn "tls_dtprel_ha_64"
10225 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10226 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10227 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10228 UNSPEC_TLSDTPRELHA))]
10229 "HAVE_AS_TLS && TARGET_64BIT"
10230 "addis %0,%1,%2@dtprel@ha")
10231
10232 (define_insn "tls_dtprel_lo_32"
10233 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10234 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10235 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10236 UNSPEC_TLSDTPRELLO))]
10237 "HAVE_AS_TLS && !TARGET_64BIT"
10238 "addi %0,%1,%2@dtprel@l")
10239
10240 (define_insn "tls_dtprel_lo_64"
10241 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10242 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10243 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10244 UNSPEC_TLSDTPRELLO))]
10245 "HAVE_AS_TLS && TARGET_64BIT"
10246 "addi %0,%1,%2@dtprel@l")
10247
10248 (define_insn "tls_got_dtprel_32"
10249 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10250 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10251 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10252 UNSPEC_TLSGOTDTPREL))]
10253 "HAVE_AS_TLS && !TARGET_64BIT"
10254 "lwz %0,%2@got@dtprel(%1)")
10255
10256 (define_insn "tls_got_dtprel_64"
10257 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10258 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10259 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10260 UNSPEC_TLSGOTDTPREL))]
10261 "HAVE_AS_TLS && TARGET_64BIT"
10262 "ld %0,%2@got@dtprel(%1)")
10263
10264 (define_insn "tls_tprel_32"
10265 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10266 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10267 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10268 UNSPEC_TLSTPREL))]
10269 "HAVE_AS_TLS && !TARGET_64BIT"
10270 "addi %0,%1,%2@tprel")
10271
10272 (define_insn "tls_tprel_64"
10273 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10274 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10275 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10276 UNSPEC_TLSTPREL))]
10277 "HAVE_AS_TLS && TARGET_64BIT"
10278 "addi %0,%1,%2@tprel")
10279
10280 (define_insn "tls_tprel_ha_32"
10281 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10282 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10283 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10284 UNSPEC_TLSTPRELHA))]
10285 "HAVE_AS_TLS && !TARGET_64BIT"
10286 "addis %0,%1,%2@tprel@ha")
10287
10288 (define_insn "tls_tprel_ha_64"
10289 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10290 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10291 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10292 UNSPEC_TLSTPRELHA))]
10293 "HAVE_AS_TLS && TARGET_64BIT"
10294 "addis %0,%1,%2@tprel@ha")
10295
10296 (define_insn "tls_tprel_lo_32"
10297 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10298 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10299 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10300 UNSPEC_TLSTPRELLO))]
10301 "HAVE_AS_TLS && !TARGET_64BIT"
10302 "addi %0,%1,%2@tprel@l")
10303
10304 (define_insn "tls_tprel_lo_64"
10305 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10306 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10307 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10308 UNSPEC_TLSTPRELLO))]
10309 "HAVE_AS_TLS && TARGET_64BIT"
10310 "addi %0,%1,%2@tprel@l")
10311
10312 ;; "b" output constraint here and on tls_tls input to support linker tls
10313 ;; optimization. The linker may edit the instructions emitted by a
10314 ;; tls_got_tprel/tls_tls pair to addis,addi.
10315 (define_insn "tls_got_tprel_32"
10316 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10317 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10318 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10319 UNSPEC_TLSGOTTPREL))]
10320 "HAVE_AS_TLS && !TARGET_64BIT"
10321 "lwz %0,%2@got@tprel(%1)")
10322
10323 (define_insn "tls_got_tprel_64"
10324 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10325 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10326 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10327 UNSPEC_TLSGOTTPREL))]
10328 "HAVE_AS_TLS && TARGET_64BIT"
10329 "ld %0,%2@got@tprel(%1)")
10330
10331 (define_insn "tls_tls_32"
10332 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10333 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10334 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10335 UNSPEC_TLSTLS))]
10336 "HAVE_AS_TLS && !TARGET_64BIT"
10337 "add %0,%1,%2@tls")
10338
10339 (define_insn "tls_tls_64"
10340 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10341 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10342 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10343 UNSPEC_TLSTLS))]
10344 "HAVE_AS_TLS && TARGET_64BIT"
10345 "add %0,%1,%2@tls")
10346 \f
10347 ;; Next come insns related to the calling sequence.
10348 ;;
10349 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
10350 ;; We move the back-chain and decrement the stack pointer.
10351
10352 (define_expand "allocate_stack"
10353 [(set (match_operand 0 "gpc_reg_operand" "")
10354 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10355 (set (reg 1)
10356 (minus (reg 1) (match_dup 1)))]
10357 ""
10358 "
10359 { rtx chain = gen_reg_rtx (Pmode);
10360 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
10361 rtx neg_op0;
10362
10363 emit_move_insn (chain, stack_bot);
10364
10365 /* Check stack bounds if necessary. */
10366 if (current_function_limit_stack)
10367 {
10368 rtx available;
10369 available = expand_binop (Pmode, sub_optab,
10370 stack_pointer_rtx, stack_limit_rtx,
10371 NULL_RTX, 1, OPTAB_WIDEN);
10372 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10373 }
10374
10375 if (GET_CODE (operands[1]) != CONST_INT
10376 || INTVAL (operands[1]) < -32767
10377 || INTVAL (operands[1]) > 32768)
10378 {
10379 neg_op0 = gen_reg_rtx (Pmode);
10380 if (TARGET_32BIT)
10381 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10382 else
10383 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10384 }
10385 else
10386 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10387
10388 if (TARGET_UPDATE)
10389 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
10390 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
10391
10392 else
10393 {
10394 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
10395 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
10396 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
10397 }
10398
10399 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10400 DONE;
10401 }")
10402
10403 ;; These patterns say how to save and restore the stack pointer. We need not
10404 ;; save the stack pointer at function level since we are careful to
10405 ;; preserve the backchain. At block level, we have to restore the backchain
10406 ;; when we restore the stack pointer.
10407 ;;
10408 ;; For nonlocal gotos, we must save both the stack pointer and its
10409 ;; backchain and restore both. Note that in the nonlocal case, the
10410 ;; save area is a memory location.
10411
10412 (define_expand "save_stack_function"
10413 [(match_operand 0 "any_operand" "")
10414 (match_operand 1 "any_operand" "")]
10415 ""
10416 "DONE;")
10417
10418 (define_expand "restore_stack_function"
10419 [(match_operand 0 "any_operand" "")
10420 (match_operand 1 "any_operand" "")]
10421 ""
10422 "DONE;")
10423
10424 ;; Adjust stack pointer (op0) to a new value (op1).
10425 ;; First copy old stack backchain to new location, and ensure that the
10426 ;; scheduler won't reorder the sp assignment before the backchain write.
10427 (define_expand "restore_stack_block"
10428 [(set (match_dup 2) (match_dup 3))
10429 (set (match_dup 4) (match_dup 2))
10430 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
10431 (set (match_operand 0 "register_operand" "")
10432 (match_operand 1 "register_operand" ""))]
10433 ""
10434 "
10435 {
10436 operands[2] = gen_reg_rtx (Pmode);
10437 operands[3] = gen_frame_mem (Pmode, operands[0]);
10438 operands[4] = gen_frame_mem (Pmode, operands[1]);
10439 operands[5] = gen_frame_mem (BLKmode, operands[0]);
10440 }")
10441
10442 (define_expand "save_stack_nonlocal"
10443 [(set (match_dup 3) (match_dup 4))
10444 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10445 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
10446 ""
10447 "
10448 {
10449 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10450
10451 /* Copy the backchain to the first word, sp to the second. */
10452 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10453 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10454 operands[3] = gen_reg_rtx (Pmode);
10455 operands[4] = gen_frame_mem (Pmode, operands[1]);
10456 }")
10457
10458 (define_expand "restore_stack_nonlocal"
10459 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10460 (set (match_dup 3) (match_dup 4))
10461 (set (match_dup 5) (match_dup 2))
10462 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
10463 (set (match_operand 0 "register_operand" "") (match_dup 3))]
10464 ""
10465 "
10466 {
10467 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10468
10469 /* Restore the backchain from the first word, sp from the second. */
10470 operands[2] = gen_reg_rtx (Pmode);
10471 operands[3] = gen_reg_rtx (Pmode);
10472 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10473 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10474 operands[5] = gen_frame_mem (Pmode, operands[3]);
10475 operands[6] = gen_frame_mem (BLKmode, operands[0]);
10476 }")
10477 \f
10478 ;; TOC register handling.
10479
10480 ;; Code to initialize the TOC register...
10481
10482 (define_insn "load_toc_aix_si"
10483 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10484 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10485 (use (reg:SI 2))])]
10486 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10487 "*
10488 {
10489 char buf[30];
10490 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10491 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10492 operands[2] = gen_rtx_REG (Pmode, 2);
10493 return \"{l|lwz} %0,%1(%2)\";
10494 }"
10495 [(set_attr "type" "load")])
10496
10497 (define_insn "load_toc_aix_di"
10498 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10499 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10500 (use (reg:DI 2))])]
10501 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10502 "*
10503 {
10504 char buf[30];
10505 #ifdef TARGET_RELOCATABLE
10506 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10507 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10508 #else
10509 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10510 #endif
10511 if (TARGET_ELF)
10512 strcat (buf, \"@toc\");
10513 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10514 operands[2] = gen_rtx_REG (Pmode, 2);
10515 return \"ld %0,%1(%2)\";
10516 }"
10517 [(set_attr "type" "load")])
10518
10519 (define_insn "load_toc_v4_pic_si"
10520 [(set (reg:SI LR_REGNO)
10521 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10522 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10523 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10524 [(set_attr "type" "branch")
10525 (set_attr "length" "4")])
10526
10527 (define_insn "load_toc_v4_PIC_1"
10528 [(set (reg:SI LR_REGNO)
10529 (match_operand:SI 0 "immediate_operand" "s"))
10530 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10531 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
10532 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10533 "bcl 20,31,%0\\n%0:"
10534 [(set_attr "type" "branch")
10535 (set_attr "length" "4")])
10536
10537 (define_insn "load_toc_v4_PIC_1b"
10538 [(set (reg:SI LR_REGNO)
10539 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")]
10540 UNSPEC_TOCPTR))]
10541 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10542 "bcl 20,31,$+8\\n\\t.long %0-$"
10543 [(set_attr "type" "branch")
10544 (set_attr "length" "8")])
10545
10546 (define_insn "load_toc_v4_PIC_2"
10547 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10548 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10549 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10550 (match_operand:SI 3 "immediate_operand" "s")))))]
10551 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10552 "{l|lwz} %0,%2-%3(%1)"
10553 [(set_attr "type" "load")])
10554
10555 (define_insn "load_toc_v4_PIC_3b"
10556 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10557 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10558 (high:SI
10559 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10560 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10561 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10562 "{cau|addis} %0,%1,%2-%3@ha")
10563
10564 (define_insn "load_toc_v4_PIC_3c"
10565 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10566 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10567 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10568 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10569 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10570 "{cal|addi} %0,%1,%2-%3@l")
10571
10572 ;; If the TOC is shared over a translation unit, as happens with all
10573 ;; the kinds of PIC that we support, we need to restore the TOC
10574 ;; pointer only when jumping over units of translation.
10575 ;; On Darwin, we need to reload the picbase.
10576
10577 (define_expand "builtin_setjmp_receiver"
10578 [(use (label_ref (match_operand 0 "" "")))]
10579 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10580 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10581 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10582 "
10583 {
10584 #if TARGET_MACHO
10585 if (DEFAULT_ABI == ABI_DARWIN)
10586 {
10587 const char *picbase = machopic_function_base_name ();
10588 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
10589 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10590 rtx tmplabrtx;
10591 char tmplab[20];
10592
10593 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10594 CODE_LABEL_NUMBER (operands[0]));
10595 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10596
10597 emit_insn (gen_load_macho_picbase (tmplabrtx));
10598 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
10599 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10600 }
10601 else
10602 #endif
10603 rs6000_emit_load_toc_table (FALSE);
10604 DONE;
10605 }")
10606
10607 ;; Elf specific ways of loading addresses for non-PIC code.
10608 ;; The output of this could be r0, but we make a very strong
10609 ;; preference for a base register because it will usually
10610 ;; be needed there.
10611 (define_insn "elf_high"
10612 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10613 (high:SI (match_operand 1 "" "")))]
10614 "TARGET_ELF && ! TARGET_64BIT"
10615 "{liu|lis} %0,%1@ha")
10616
10617 (define_insn "elf_low"
10618 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10619 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10620 (match_operand 2 "" "")))]
10621 "TARGET_ELF && ! TARGET_64BIT"
10622 "@
10623 {cal|la} %0,%2@l(%1)
10624 {ai|addic} %0,%1,%K2")
10625 \f
10626 ;; A function pointer under AIX is a pointer to a data area whose first word
10627 ;; contains the actual address of the function, whose second word contains a
10628 ;; pointer to its TOC, and whose third word contains a value to place in the
10629 ;; static chain register (r11). Note that if we load the static chain, our
10630 ;; "trampoline" need not have any executable code.
10631
10632 (define_expand "call_indirect_aix32"
10633 [(set (match_dup 2)
10634 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10635 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10636 (reg:SI 2))
10637 (set (reg:SI 2)
10638 (mem:SI (plus:SI (match_dup 0)
10639 (const_int 4))))
10640 (set (reg:SI 11)
10641 (mem:SI (plus:SI (match_dup 0)
10642 (const_int 8))))
10643 (parallel [(call (mem:SI (match_dup 2))
10644 (match_operand 1 "" ""))
10645 (use (reg:SI 2))
10646 (use (reg:SI 11))
10647 (set (reg:SI 2)
10648 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10649 (clobber (reg:SI LR_REGNO))])]
10650 "TARGET_32BIT"
10651 "
10652 { operands[2] = gen_reg_rtx (SImode); }")
10653
10654 (define_expand "call_indirect_aix64"
10655 [(set (match_dup 2)
10656 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10657 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10658 (reg:DI 2))
10659 (set (reg:DI 2)
10660 (mem:DI (plus:DI (match_dup 0)
10661 (const_int 8))))
10662 (set (reg:DI 11)
10663 (mem:DI (plus:DI (match_dup 0)
10664 (const_int 16))))
10665 (parallel [(call (mem:SI (match_dup 2))
10666 (match_operand 1 "" ""))
10667 (use (reg:DI 2))
10668 (use (reg:DI 11))
10669 (set (reg:DI 2)
10670 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10671 (clobber (reg:SI LR_REGNO))])]
10672 "TARGET_64BIT"
10673 "
10674 { operands[2] = gen_reg_rtx (DImode); }")
10675
10676 (define_expand "call_value_indirect_aix32"
10677 [(set (match_dup 3)
10678 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10679 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10680 (reg:SI 2))
10681 (set (reg:SI 2)
10682 (mem:SI (plus:SI (match_dup 1)
10683 (const_int 4))))
10684 (set (reg:SI 11)
10685 (mem:SI (plus:SI (match_dup 1)
10686 (const_int 8))))
10687 (parallel [(set (match_operand 0 "" "")
10688 (call (mem:SI (match_dup 3))
10689 (match_operand 2 "" "")))
10690 (use (reg:SI 2))
10691 (use (reg:SI 11))
10692 (set (reg:SI 2)
10693 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10694 (clobber (reg:SI LR_REGNO))])]
10695 "TARGET_32BIT"
10696 "
10697 { operands[3] = gen_reg_rtx (SImode); }")
10698
10699 (define_expand "call_value_indirect_aix64"
10700 [(set (match_dup 3)
10701 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10702 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10703 (reg:DI 2))
10704 (set (reg:DI 2)
10705 (mem:DI (plus:DI (match_dup 1)
10706 (const_int 8))))
10707 (set (reg:DI 11)
10708 (mem:DI (plus:DI (match_dup 1)
10709 (const_int 16))))
10710 (parallel [(set (match_operand 0 "" "")
10711 (call (mem:SI (match_dup 3))
10712 (match_operand 2 "" "")))
10713 (use (reg:DI 2))
10714 (use (reg:DI 11))
10715 (set (reg:DI 2)
10716 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10717 (clobber (reg:SI LR_REGNO))])]
10718 "TARGET_64BIT"
10719 "
10720 { operands[3] = gen_reg_rtx (DImode); }")
10721
10722 ;; Now the definitions for the call and call_value insns
10723 (define_expand "call"
10724 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10725 (match_operand 1 "" ""))
10726 (use (match_operand 2 "" ""))
10727 (clobber (reg:SI LR_REGNO))])]
10728 ""
10729 "
10730 {
10731 #if TARGET_MACHO
10732 if (MACHOPIC_INDIRECT)
10733 operands[0] = machopic_indirect_call_target (operands[0]);
10734 #endif
10735
10736 gcc_assert (GET_CODE (operands[0]) == MEM);
10737 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10738
10739 operands[0] = XEXP (operands[0], 0);
10740
10741 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10742 && flag_pic
10743 && GET_CODE (operands[0]) == SYMBOL_REF
10744 && !SYMBOL_REF_LOCAL_P (operands[0]))
10745 {
10746 rtx call;
10747 rtvec tmp;
10748
10749 tmp = gen_rtvec (3,
10750 gen_rtx_CALL (VOIDmode,
10751 gen_rtx_MEM (SImode, operands[0]),
10752 operands[1]),
10753 gen_rtx_USE (VOIDmode, operands[2]),
10754 gen_rtx_CLOBBER (VOIDmode,
10755 gen_rtx_REG (Pmode, LR_REGNO)));
10756 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10757 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10758 DONE;
10759 }
10760
10761 if (GET_CODE (operands[0]) != SYMBOL_REF
10762 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10763 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10764 {
10765 if (INTVAL (operands[2]) & CALL_LONG)
10766 operands[0] = rs6000_longcall_ref (operands[0]);
10767
10768 switch (DEFAULT_ABI)
10769 {
10770 case ABI_V4:
10771 case ABI_DARWIN:
10772 operands[0] = force_reg (Pmode, operands[0]);
10773 break;
10774
10775 case ABI_AIX:
10776 /* AIX function pointers are really pointers to a three word
10777 area. */
10778 emit_call_insn (TARGET_32BIT
10779 ? gen_call_indirect_aix32 (force_reg (SImode,
10780 operands[0]),
10781 operands[1])
10782 : gen_call_indirect_aix64 (force_reg (DImode,
10783 operands[0]),
10784 operands[1]));
10785 DONE;
10786
10787 default:
10788 gcc_unreachable ();
10789 }
10790 }
10791 }")
10792
10793 (define_expand "call_value"
10794 [(parallel [(set (match_operand 0 "" "")
10795 (call (mem:SI (match_operand 1 "address_operand" ""))
10796 (match_operand 2 "" "")))
10797 (use (match_operand 3 "" ""))
10798 (clobber (reg:SI LR_REGNO))])]
10799 ""
10800 "
10801 {
10802 #if TARGET_MACHO
10803 if (MACHOPIC_INDIRECT)
10804 operands[1] = machopic_indirect_call_target (operands[1]);
10805 #endif
10806
10807 gcc_assert (GET_CODE (operands[1]) == MEM);
10808 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10809
10810 operands[1] = XEXP (operands[1], 0);
10811
10812 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10813 && flag_pic
10814 && GET_CODE (operands[1]) == SYMBOL_REF
10815 && !SYMBOL_REF_LOCAL_P (operands[1]))
10816 {
10817 rtx call;
10818 rtvec tmp;
10819
10820 tmp = gen_rtvec (3,
10821 gen_rtx_SET (VOIDmode,
10822 operands[0],
10823 gen_rtx_CALL (VOIDmode,
10824 gen_rtx_MEM (SImode,
10825 operands[1]),
10826 operands[2])),
10827 gen_rtx_USE (VOIDmode, operands[3]),
10828 gen_rtx_CLOBBER (VOIDmode,
10829 gen_rtx_REG (Pmode, LR_REGNO)));
10830 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10831 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10832 DONE;
10833 }
10834
10835 if (GET_CODE (operands[1]) != SYMBOL_REF
10836 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10837 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10838 {
10839 if (INTVAL (operands[3]) & CALL_LONG)
10840 operands[1] = rs6000_longcall_ref (operands[1]);
10841
10842 switch (DEFAULT_ABI)
10843 {
10844 case ABI_V4:
10845 case ABI_DARWIN:
10846 operands[1] = force_reg (Pmode, operands[1]);
10847 break;
10848
10849 case ABI_AIX:
10850 /* AIX function pointers are really pointers to a three word
10851 area. */
10852 emit_call_insn (TARGET_32BIT
10853 ? gen_call_value_indirect_aix32 (operands[0],
10854 force_reg (SImode,
10855 operands[1]),
10856 operands[2])
10857 : gen_call_value_indirect_aix64 (operands[0],
10858 force_reg (DImode,
10859 operands[1]),
10860 operands[2]));
10861 DONE;
10862
10863 default:
10864 gcc_unreachable ();
10865 }
10866 }
10867 }")
10868
10869 ;; Call to function in current module. No TOC pointer reload needed.
10870 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10871 ;; either the function was not prototyped, or it was prototyped as a
10872 ;; variable argument function. It is > 0 if FP registers were passed
10873 ;; and < 0 if they were not.
10874
10875 (define_insn "*call_local32"
10876 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10877 (match_operand 1 "" "g,g"))
10878 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10879 (clobber (reg:SI LR_REGNO))]
10880 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10881 "*
10882 {
10883 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10884 output_asm_insn (\"crxor 6,6,6\", operands);
10885
10886 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10887 output_asm_insn (\"creqv 6,6,6\", operands);
10888
10889 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10890 }"
10891 [(set_attr "type" "branch")
10892 (set_attr "length" "4,8")])
10893
10894 (define_insn "*call_local64"
10895 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10896 (match_operand 1 "" "g,g"))
10897 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10898 (clobber (reg:SI LR_REGNO))]
10899 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10900 "*
10901 {
10902 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10903 output_asm_insn (\"crxor 6,6,6\", operands);
10904
10905 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10906 output_asm_insn (\"creqv 6,6,6\", operands);
10907
10908 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10909 }"
10910 [(set_attr "type" "branch")
10911 (set_attr "length" "4,8")])
10912
10913 (define_insn "*call_value_local32"
10914 [(set (match_operand 0 "" "")
10915 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10916 (match_operand 2 "" "g,g")))
10917 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10918 (clobber (reg:SI LR_REGNO))]
10919 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10920 "*
10921 {
10922 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10923 output_asm_insn (\"crxor 6,6,6\", operands);
10924
10925 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10926 output_asm_insn (\"creqv 6,6,6\", operands);
10927
10928 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10929 }"
10930 [(set_attr "type" "branch")
10931 (set_attr "length" "4,8")])
10932
10933
10934 (define_insn "*call_value_local64"
10935 [(set (match_operand 0 "" "")
10936 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10937 (match_operand 2 "" "g,g")))
10938 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10939 (clobber (reg:SI LR_REGNO))]
10940 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10941 "*
10942 {
10943 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10944 output_asm_insn (\"crxor 6,6,6\", operands);
10945
10946 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10947 output_asm_insn (\"creqv 6,6,6\", operands);
10948
10949 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10950 }"
10951 [(set_attr "type" "branch")
10952 (set_attr "length" "4,8")])
10953
10954 ;; Call to function which may be in another module. Restore the TOC
10955 ;; pointer (r2) after the call unless this is System V.
10956 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10957 ;; either the function was not prototyped, or it was prototyped as a
10958 ;; variable argument function. It is > 0 if FP registers were passed
10959 ;; and < 0 if they were not.
10960
10961 (define_insn "*call_indirect_nonlocal_aix32"
10962 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
10963 (match_operand 1 "" "g,g"))
10964 (use (reg:SI 2))
10965 (use (reg:SI 11))
10966 (set (reg:SI 2)
10967 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10968 (clobber (reg:SI LR_REGNO))]
10969 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10970 "b%T0l\;{l|lwz} 2,20(1)"
10971 [(set_attr "type" "jmpreg")
10972 (set_attr "length" "8")])
10973
10974 (define_insn "*call_nonlocal_aix32"
10975 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10976 (match_operand 1 "" "g"))
10977 (use (match_operand:SI 2 "immediate_operand" "O"))
10978 (clobber (reg:SI LR_REGNO))]
10979 "TARGET_32BIT
10980 && DEFAULT_ABI == ABI_AIX
10981 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10982 "bl %z0\;%."
10983 [(set_attr "type" "branch")
10984 (set_attr "length" "8")])
10985
10986 (define_insn "*call_indirect_nonlocal_aix64"
10987 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
10988 (match_operand 1 "" "g,g"))
10989 (use (reg:DI 2))
10990 (use (reg:DI 11))
10991 (set (reg:DI 2)
10992 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10993 (clobber (reg:SI LR_REGNO))]
10994 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10995 "b%T0l\;ld 2,40(1)"
10996 [(set_attr "type" "jmpreg")
10997 (set_attr "length" "8")])
10998
10999 (define_insn "*call_nonlocal_aix64"
11000 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11001 (match_operand 1 "" "g"))
11002 (use (match_operand:SI 2 "immediate_operand" "O"))
11003 (clobber (reg:SI LR_REGNO))]
11004 "TARGET_64BIT
11005 && DEFAULT_ABI == ABI_AIX
11006 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11007 "bl %z0\;%."
11008 [(set_attr "type" "branch")
11009 (set_attr "length" "8")])
11010
11011 (define_insn "*call_value_indirect_nonlocal_aix32"
11012 [(set (match_operand 0 "" "")
11013 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
11014 (match_operand 2 "" "g,g")))
11015 (use (reg:SI 2))
11016 (use (reg:SI 11))
11017 (set (reg:SI 2)
11018 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11019 (clobber (reg:SI LR_REGNO))]
11020 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11021 "b%T1l\;{l|lwz} 2,20(1)"
11022 [(set_attr "type" "jmpreg")
11023 (set_attr "length" "8")])
11024
11025 (define_insn "*call_value_nonlocal_aix32"
11026 [(set (match_operand 0 "" "")
11027 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11028 (match_operand 2 "" "g")))
11029 (use (match_operand:SI 3 "immediate_operand" "O"))
11030 (clobber (reg:SI LR_REGNO))]
11031 "TARGET_32BIT
11032 && DEFAULT_ABI == ABI_AIX
11033 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11034 "bl %z1\;%."
11035 [(set_attr "type" "branch")
11036 (set_attr "length" "8")])
11037
11038 (define_insn "*call_value_indirect_nonlocal_aix64"
11039 [(set (match_operand 0 "" "")
11040 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
11041 (match_operand 2 "" "g,g")))
11042 (use (reg:DI 2))
11043 (use (reg:DI 11))
11044 (set (reg:DI 2)
11045 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11046 (clobber (reg:SI LR_REGNO))]
11047 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11048 "b%T1l\;ld 2,40(1)"
11049 [(set_attr "type" "jmpreg")
11050 (set_attr "length" "8")])
11051
11052 (define_insn "*call_value_nonlocal_aix64"
11053 [(set (match_operand 0 "" "")
11054 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11055 (match_operand 2 "" "g")))
11056 (use (match_operand:SI 3 "immediate_operand" "O"))
11057 (clobber (reg:SI LR_REGNO))]
11058 "TARGET_64BIT
11059 && DEFAULT_ABI == ABI_AIX
11060 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11061 "bl %z1\;%."
11062 [(set_attr "type" "branch")
11063 (set_attr "length" "8")])
11064
11065 ;; A function pointer under System V is just a normal pointer
11066 ;; operands[0] is the function pointer
11067 ;; operands[1] is the stack size to clean up
11068 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
11069 ;; which indicates how to set cr1
11070
11071 (define_insn "*call_indirect_nonlocal_sysv<mode>"
11072 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
11073 (match_operand 1 "" "g,g,g,g"))
11074 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
11075 (clobber (reg:SI LR_REGNO))]
11076 "DEFAULT_ABI == ABI_V4
11077 || DEFAULT_ABI == ABI_DARWIN"
11078 {
11079 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11080 output_asm_insn ("crxor 6,6,6", operands);
11081
11082 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11083 output_asm_insn ("creqv 6,6,6", operands);
11084
11085 return "b%T0l";
11086 }
11087 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11088 (set_attr "length" "4,4,8,8")])
11089
11090 (define_insn "*call_nonlocal_sysv<mode>"
11091 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11092 (match_operand 1 "" "g,g"))
11093 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11094 (clobber (reg:SI LR_REGNO))]
11095 "(DEFAULT_ABI == ABI_DARWIN
11096 || (DEFAULT_ABI == ABI_V4
11097 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
11098 {
11099 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11100 output_asm_insn ("crxor 6,6,6", operands);
11101
11102 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11103 output_asm_insn ("creqv 6,6,6", operands);
11104
11105 #if TARGET_MACHO
11106 return output_call(insn, operands, 0, 2);
11107 #else
11108 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11109 {
11110 if (TARGET_SECURE_PLT && flag_pic == 2)
11111 /* The magic 32768 offset here and in the other sysv call insns
11112 corresponds to the offset of r30 in .got2, as given by LCTOC1.
11113 See sysv4.h:toc_section. */
11114 return "bl %z0+32768@plt";
11115 else
11116 return "bl %z0@plt";
11117 }
11118 else
11119 return "bl %z0";
11120 #endif
11121 }
11122 [(set_attr "type" "branch,branch")
11123 (set_attr "length" "4,8")])
11124
11125 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
11126 [(set (match_operand 0 "" "")
11127 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
11128 (match_operand 2 "" "g,g,g,g")))
11129 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
11130 (clobber (reg:SI LR_REGNO))]
11131 "DEFAULT_ABI == ABI_V4
11132 || DEFAULT_ABI == ABI_DARWIN"
11133 {
11134 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11135 output_asm_insn ("crxor 6,6,6", operands);
11136
11137 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11138 output_asm_insn ("creqv 6,6,6", operands);
11139
11140 return "b%T1l";
11141 }
11142 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11143 (set_attr "length" "4,4,8,8")])
11144
11145 (define_insn "*call_value_nonlocal_sysv<mode>"
11146 [(set (match_operand 0 "" "")
11147 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11148 (match_operand 2 "" "g,g")))
11149 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11150 (clobber (reg:SI LR_REGNO))]
11151 "(DEFAULT_ABI == ABI_DARWIN
11152 || (DEFAULT_ABI == ABI_V4
11153 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
11154 {
11155 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11156 output_asm_insn ("crxor 6,6,6", operands);
11157
11158 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11159 output_asm_insn ("creqv 6,6,6", operands);
11160
11161 #if TARGET_MACHO
11162 return output_call(insn, operands, 1, 3);
11163 #else
11164 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11165 {
11166 if (TARGET_SECURE_PLT && flag_pic == 2)
11167 return "bl %z1+32768@plt";
11168 else
11169 return "bl %z1@plt";
11170 }
11171 else
11172 return "bl %z1";
11173 #endif
11174 }
11175 [(set_attr "type" "branch,branch")
11176 (set_attr "length" "4,8")])
11177
11178 ;; Call subroutine returning any type.
11179 (define_expand "untyped_call"
11180 [(parallel [(call (match_operand 0 "" "")
11181 (const_int 0))
11182 (match_operand 1 "" "")
11183 (match_operand 2 "" "")])]
11184 ""
11185 "
11186 {
11187 int i;
11188
11189 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
11190
11191 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11192 {
11193 rtx set = XVECEXP (operands[2], 0, i);
11194 emit_move_insn (SET_DEST (set), SET_SRC (set));
11195 }
11196
11197 /* The optimizer does not know that the call sets the function value
11198 registers we stored in the result block. We avoid problems by
11199 claiming that all hard registers are used and clobbered at this
11200 point. */
11201 emit_insn (gen_blockage ());
11202
11203 DONE;
11204 }")
11205
11206 ;; sibling call patterns
11207 (define_expand "sibcall"
11208 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11209 (match_operand 1 "" ""))
11210 (use (match_operand 2 "" ""))
11211 (use (reg:SI LR_REGNO))
11212 (return)])]
11213 ""
11214 "
11215 {
11216 #if TARGET_MACHO
11217 if (MACHOPIC_INDIRECT)
11218 operands[0] = machopic_indirect_call_target (operands[0]);
11219 #endif
11220
11221 gcc_assert (GET_CODE (operands[0]) == MEM);
11222 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11223
11224 operands[0] = XEXP (operands[0], 0);
11225 }")
11226
11227 ;; this and similar patterns must be marked as using LR, otherwise
11228 ;; dataflow will try to delete the store into it. This is true
11229 ;; even when the actual reg to jump to is in CTR, when LR was
11230 ;; saved and restored around the PIC-setting BCL.
11231 (define_insn "*sibcall_local32"
11232 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11233 (match_operand 1 "" "g,g"))
11234 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11235 (use (reg:SI LR_REGNO))
11236 (return)]
11237 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11238 "*
11239 {
11240 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11241 output_asm_insn (\"crxor 6,6,6\", operands);
11242
11243 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11244 output_asm_insn (\"creqv 6,6,6\", operands);
11245
11246 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11247 }"
11248 [(set_attr "type" "branch")
11249 (set_attr "length" "4,8")])
11250
11251 (define_insn "*sibcall_local64"
11252 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11253 (match_operand 1 "" "g,g"))
11254 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11255 (use (reg:SI LR_REGNO))
11256 (return)]
11257 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11258 "*
11259 {
11260 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11261 output_asm_insn (\"crxor 6,6,6\", operands);
11262
11263 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11264 output_asm_insn (\"creqv 6,6,6\", operands);
11265
11266 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11267 }"
11268 [(set_attr "type" "branch")
11269 (set_attr "length" "4,8")])
11270
11271 (define_insn "*sibcall_value_local32"
11272 [(set (match_operand 0 "" "")
11273 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11274 (match_operand 2 "" "g,g")))
11275 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11276 (use (reg:SI LR_REGNO))
11277 (return)]
11278 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11279 "*
11280 {
11281 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11282 output_asm_insn (\"crxor 6,6,6\", operands);
11283
11284 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11285 output_asm_insn (\"creqv 6,6,6\", operands);
11286
11287 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11288 }"
11289 [(set_attr "type" "branch")
11290 (set_attr "length" "4,8")])
11291
11292
11293 (define_insn "*sibcall_value_local64"
11294 [(set (match_operand 0 "" "")
11295 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11296 (match_operand 2 "" "g,g")))
11297 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11298 (use (reg:SI LR_REGNO))
11299 (return)]
11300 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11301 "*
11302 {
11303 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11304 output_asm_insn (\"crxor 6,6,6\", operands);
11305
11306 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11307 output_asm_insn (\"creqv 6,6,6\", operands);
11308
11309 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11310 }"
11311 [(set_attr "type" "branch")
11312 (set_attr "length" "4,8")])
11313
11314 (define_insn "*sibcall_nonlocal_aix32"
11315 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11316 (match_operand 1 "" "g"))
11317 (use (match_operand:SI 2 "immediate_operand" "O"))
11318 (use (reg:SI LR_REGNO))
11319 (return)]
11320 "TARGET_32BIT
11321 && DEFAULT_ABI == ABI_AIX
11322 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11323 "b %z0"
11324 [(set_attr "type" "branch")
11325 (set_attr "length" "4")])
11326
11327 (define_insn "*sibcall_nonlocal_aix64"
11328 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11329 (match_operand 1 "" "g"))
11330 (use (match_operand:SI 2 "immediate_operand" "O"))
11331 (use (reg:SI LR_REGNO))
11332 (return)]
11333 "TARGET_64BIT
11334 && DEFAULT_ABI == ABI_AIX
11335 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11336 "b %z0"
11337 [(set_attr "type" "branch")
11338 (set_attr "length" "4")])
11339
11340 (define_insn "*sibcall_value_nonlocal_aix32"
11341 [(set (match_operand 0 "" "")
11342 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11343 (match_operand 2 "" "g")))
11344 (use (match_operand:SI 3 "immediate_operand" "O"))
11345 (use (reg:SI LR_REGNO))
11346 (return)]
11347 "TARGET_32BIT
11348 && DEFAULT_ABI == ABI_AIX
11349 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11350 "b %z1"
11351 [(set_attr "type" "branch")
11352 (set_attr "length" "4")])
11353
11354 (define_insn "*sibcall_value_nonlocal_aix64"
11355 [(set (match_operand 0 "" "")
11356 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11357 (match_operand 2 "" "g")))
11358 (use (match_operand:SI 3 "immediate_operand" "O"))
11359 (use (reg:SI LR_REGNO))
11360 (return)]
11361 "TARGET_64BIT
11362 && DEFAULT_ABI == ABI_AIX
11363 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11364 "b %z1"
11365 [(set_attr "type" "branch")
11366 (set_attr "length" "4")])
11367
11368 (define_insn "*sibcall_nonlocal_sysv<mode>"
11369 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11370 (match_operand 1 "" ""))
11371 (use (match_operand 2 "immediate_operand" "O,n"))
11372 (use (reg:SI LR_REGNO))
11373 (return)]
11374 "(DEFAULT_ABI == ABI_DARWIN
11375 || DEFAULT_ABI == ABI_V4)
11376 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11377 "*
11378 {
11379 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11380 output_asm_insn (\"crxor 6,6,6\", operands);
11381
11382 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11383 output_asm_insn (\"creqv 6,6,6\", operands);
11384
11385 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11386 {
11387 if (TARGET_SECURE_PLT && flag_pic == 2)
11388 return \"b %z0+32768@plt\";
11389 else
11390 return \"b %z0@plt\";
11391 }
11392 else
11393 return \"b %z0\";
11394 }"
11395 [(set_attr "type" "branch,branch")
11396 (set_attr "length" "4,8")])
11397
11398 (define_expand "sibcall_value"
11399 [(parallel [(set (match_operand 0 "register_operand" "")
11400 (call (mem:SI (match_operand 1 "address_operand" ""))
11401 (match_operand 2 "" "")))
11402 (use (match_operand 3 "" ""))
11403 (use (reg:SI LR_REGNO))
11404 (return)])]
11405 ""
11406 "
11407 {
11408 #if TARGET_MACHO
11409 if (MACHOPIC_INDIRECT)
11410 operands[1] = machopic_indirect_call_target (operands[1]);
11411 #endif
11412
11413 gcc_assert (GET_CODE (operands[1]) == MEM);
11414 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11415
11416 operands[1] = XEXP (operands[1], 0);
11417 }")
11418
11419 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
11420 [(set (match_operand 0 "" "")
11421 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11422 (match_operand 2 "" "")))
11423 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11424 (use (reg:SI LR_REGNO))
11425 (return)]
11426 "(DEFAULT_ABI == ABI_DARWIN
11427 || DEFAULT_ABI == ABI_V4)
11428 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11429 "*
11430 {
11431 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11432 output_asm_insn (\"crxor 6,6,6\", operands);
11433
11434 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11435 output_asm_insn (\"creqv 6,6,6\", operands);
11436
11437 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11438 {
11439 if (TARGET_SECURE_PLT && flag_pic == 2)
11440 return \"b %z1+32768@plt\";
11441 else
11442 return \"b %z1@plt\";
11443 }
11444 else
11445 return \"b %z1\";
11446 }"
11447 [(set_attr "type" "branch,branch")
11448 (set_attr "length" "4,8")])
11449
11450 (define_expand "sibcall_epilogue"
11451 [(use (const_int 0))]
11452 "TARGET_SCHED_PROLOG"
11453 "
11454 {
11455 rs6000_emit_epilogue (TRUE);
11456 DONE;
11457 }")
11458
11459 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11460 ;; all of memory. This blocks insns from being moved across this point.
11461
11462 (define_insn "blockage"
11463 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
11464 ""
11465 "")
11466 \f
11467 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
11468 ;; signed & unsigned, and one type of branch.
11469 ;;
11470 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11471 ;; insns, and branches. We store the operands of compares until we see
11472 ;; how it is used.
11473 (define_expand "cmp<mode>"
11474 [(set (cc0)
11475 (compare (match_operand:GPR 0 "gpc_reg_operand" "")
11476 (match_operand:GPR 1 "reg_or_short_operand" "")))]
11477 ""
11478 "
11479 {
11480 /* Take care of the possibility that operands[1] might be negative but
11481 this might be a logical operation. That insn doesn't exist. */
11482 if (GET_CODE (operands[1]) == CONST_INT
11483 && INTVAL (operands[1]) < 0)
11484 operands[1] = force_reg (<MODE>mode, operands[1]);
11485
11486 rs6000_compare_op0 = operands[0];
11487 rs6000_compare_op1 = operands[1];
11488 rs6000_compare_fp_p = 0;
11489 DONE;
11490 }")
11491
11492 (define_expand "cmp<mode>"
11493 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
11494 (match_operand:FP 1 "gpc_reg_operand" "")))]
11495 ""
11496 "
11497 {
11498 rs6000_compare_op0 = operands[0];
11499 rs6000_compare_op1 = operands[1];
11500 rs6000_compare_fp_p = 1;
11501 DONE;
11502 }")
11503
11504 (define_expand "beq"
11505 [(use (match_operand 0 "" ""))]
11506 ""
11507 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
11508
11509 (define_expand "bne"
11510 [(use (match_operand 0 "" ""))]
11511 ""
11512 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
11513
11514 (define_expand "bge"
11515 [(use (match_operand 0 "" ""))]
11516 ""
11517 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
11518
11519 (define_expand "bgt"
11520 [(use (match_operand 0 "" ""))]
11521 ""
11522 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
11523
11524 (define_expand "ble"
11525 [(use (match_operand 0 "" ""))]
11526 ""
11527 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
11528
11529 (define_expand "blt"
11530 [(use (match_operand 0 "" ""))]
11531 ""
11532 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
11533
11534 (define_expand "bgeu"
11535 [(use (match_operand 0 "" ""))]
11536 ""
11537 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
11538
11539 (define_expand "bgtu"
11540 [(use (match_operand 0 "" ""))]
11541 ""
11542 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
11543
11544 (define_expand "bleu"
11545 [(use (match_operand 0 "" ""))]
11546 ""
11547 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
11548
11549 (define_expand "bltu"
11550 [(use (match_operand 0 "" ""))]
11551 ""
11552 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
11553
11554 (define_expand "bunordered"
11555 [(use (match_operand 0 "" ""))]
11556 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11557 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
11558
11559 (define_expand "bordered"
11560 [(use (match_operand 0 "" ""))]
11561 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11562 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
11563
11564 (define_expand "buneq"
11565 [(use (match_operand 0 "" ""))]
11566 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11567 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
11568
11569 (define_expand "bunge"
11570 [(use (match_operand 0 "" ""))]
11571 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11572 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
11573
11574 (define_expand "bungt"
11575 [(use (match_operand 0 "" ""))]
11576 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11577 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
11578
11579 (define_expand "bunle"
11580 [(use (match_operand 0 "" ""))]
11581 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11582 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
11583
11584 (define_expand "bunlt"
11585 [(use (match_operand 0 "" ""))]
11586 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11587 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
11588
11589 (define_expand "bltgt"
11590 [(use (match_operand 0 "" ""))]
11591 ""
11592 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
11593
11594 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11595 ;; For SEQ, likewise, except that comparisons with zero should be done
11596 ;; with an scc insns. However, due to the order that combine see the
11597 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11598 ;; the cases we don't want to handle.
11599 (define_expand "seq"
11600 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11601 ""
11602 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
11603
11604 (define_expand "sne"
11605 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11606 ""
11607 "
11608 {
11609 if (! rs6000_compare_fp_p)
11610 FAIL;
11611
11612 rs6000_emit_sCOND (NE, operands[0]);
11613 DONE;
11614 }")
11615
11616 ;; A >= 0 is best done the portable way for A an integer.
11617 (define_expand "sge"
11618 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11619 ""
11620 "
11621 {
11622 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11623 FAIL;
11624
11625 rs6000_emit_sCOND (GE, operands[0]);
11626 DONE;
11627 }")
11628
11629 ;; A > 0 is best done using the portable sequence, so fail in that case.
11630 (define_expand "sgt"
11631 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11632 ""
11633 "
11634 {
11635 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11636 FAIL;
11637
11638 rs6000_emit_sCOND (GT, operands[0]);
11639 DONE;
11640 }")
11641
11642 ;; A <= 0 is best done the portable way for A an integer.
11643 (define_expand "sle"
11644 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11645 ""
11646 "
11647 {
11648 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11649 FAIL;
11650
11651 rs6000_emit_sCOND (LE, operands[0]);
11652 DONE;
11653 }")
11654
11655 ;; A < 0 is best done in the portable way for A an integer.
11656 (define_expand "slt"
11657 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11658 ""
11659 "
11660 {
11661 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11662 FAIL;
11663
11664 rs6000_emit_sCOND (LT, operands[0]);
11665 DONE;
11666 }")
11667
11668 (define_expand "sgeu"
11669 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11670 ""
11671 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11672
11673 (define_expand "sgtu"
11674 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11675 ""
11676 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
11677
11678 (define_expand "sleu"
11679 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11680 ""
11681 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11682
11683 (define_expand "sltu"
11684 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11685 ""
11686 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
11687
11688 (define_expand "sunordered"
11689 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11690 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11691 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
11692
11693 (define_expand "sordered"
11694 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11695 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11696 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11697
11698 (define_expand "suneq"
11699 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11700 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11701 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11702
11703 (define_expand "sunge"
11704 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11705 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11706 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11707
11708 (define_expand "sungt"
11709 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11710 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11711 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11712
11713 (define_expand "sunle"
11714 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11715 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11716 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11717
11718 (define_expand "sunlt"
11719 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11720 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11721 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11722
11723 (define_expand "sltgt"
11724 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11725 ""
11726 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11727
11728 (define_expand "stack_protect_set"
11729 [(match_operand 0 "memory_operand" "")
11730 (match_operand 1 "memory_operand" "")]
11731 ""
11732 {
11733 #ifdef TARGET_THREAD_SSP_OFFSET
11734 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11735 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11736 operands[1] = gen_rtx_MEM (Pmode, addr);
11737 #endif
11738 if (TARGET_64BIT)
11739 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11740 else
11741 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11742 DONE;
11743 })
11744
11745 (define_insn "stack_protect_setsi"
11746 [(set (match_operand:SI 0 "memory_operand" "=m")
11747 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11748 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11749 "TARGET_32BIT"
11750 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
11751 [(set_attr "type" "three")
11752 (set_attr "length" "12")])
11753
11754 (define_insn "stack_protect_setdi"
11755 [(set (match_operand:DI 0 "memory_operand" "=m")
11756 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11757 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11758 "TARGET_64BIT"
11759 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
11760 [(set_attr "type" "three")
11761 (set_attr "length" "12")])
11762
11763 (define_expand "stack_protect_test"
11764 [(match_operand 0 "memory_operand" "")
11765 (match_operand 1 "memory_operand" "")
11766 (match_operand 2 "" "")]
11767 ""
11768 {
11769 #ifdef TARGET_THREAD_SSP_OFFSET
11770 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11771 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11772 operands[1] = gen_rtx_MEM (Pmode, addr);
11773 #endif
11774 rs6000_compare_op0 = operands[0];
11775 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
11776 UNSPEC_SP_TEST);
11777 rs6000_compare_fp_p = 0;
11778 emit_jump_insn (gen_beq (operands[2]));
11779 DONE;
11780 })
11781
11782 (define_insn "stack_protect_testsi"
11783 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11784 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11785 (match_operand:SI 2 "memory_operand" "m,m")]
11786 UNSPEC_SP_TEST))
11787 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11788 (clobber (match_scratch:SI 3 "=&r,&r"))]
11789 "TARGET_32BIT"
11790 "@
11791 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11792 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11793 [(set_attr "length" "16,20")])
11794
11795 (define_insn "stack_protect_testdi"
11796 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11797 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
11798 (match_operand:DI 2 "memory_operand" "m,m")]
11799 UNSPEC_SP_TEST))
11800 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11801 (clobber (match_scratch:DI 3 "=&r,&r"))]
11802 "TARGET_64BIT"
11803 "@
11804 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11805 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11806 [(set_attr "length" "16,20")])
11807
11808 \f
11809 ;; Here are the actual compare insns.
11810 (define_insn "*cmp<mode>_internal1"
11811 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11812 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11813 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
11814 ""
11815 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
11816 [(set_attr "type" "cmp")])
11817
11818 ;; If we are comparing a register for equality with a large constant,
11819 ;; we can do this with an XOR followed by a compare. But this is profitable
11820 ;; only if the large constant is only used for the comparison (and in this
11821 ;; case we already have a register to reuse as scratch).
11822 ;;
11823 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11824 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
11825
11826 (define_peephole2
11827 [(set (match_operand:SI 0 "register_operand")
11828 (match_operand:SI 1 "logical_const_operand" ""))
11829 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
11830 [(match_dup 0)
11831 (match_operand:SI 2 "logical_const_operand" "")]))
11832 (set (match_operand:CC 4 "cc_reg_operand" "")
11833 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
11834 (match_dup 0)))
11835 (set (pc)
11836 (if_then_else (match_operator 6 "equality_operator"
11837 [(match_dup 4) (const_int 0)])
11838 (match_operand 7 "" "")
11839 (match_operand 8 "" "")))]
11840 "peep2_reg_dead_p (3, operands[0])
11841 && peep2_reg_dead_p (4, operands[4])"
11842 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
11843 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11844 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11845
11846 {
11847 /* Get the constant we are comparing against, and see what it looks like
11848 when sign-extended from 16 to 32 bits. Then see what constant we could
11849 XOR with SEXTC to get the sign-extended value. */
11850 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
11851 SImode,
11852 operands[1], operands[2]);
11853 HOST_WIDE_INT c = INTVAL (cnst);
11854 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11855 HOST_WIDE_INT xorv = c ^ sextc;
11856
11857 operands[9] = GEN_INT (xorv);
11858 operands[10] = GEN_INT (sextc);
11859 })
11860
11861 (define_insn "*cmpsi_internal2"
11862 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11863 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11864 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11865 ""
11866 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
11867 [(set_attr "type" "cmp")])
11868
11869 (define_insn "*cmpdi_internal2"
11870 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11871 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11872 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11873 ""
11874 "cmpld%I2 %0,%1,%b2"
11875 [(set_attr "type" "cmp")])
11876
11877 ;; The following two insns don't exist as single insns, but if we provide
11878 ;; them, we can swap an add and compare, which will enable us to overlap more
11879 ;; of the required delay between a compare and branch. We generate code for
11880 ;; them by splitting.
11881
11882 (define_insn ""
11883 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11884 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11885 (match_operand:SI 2 "short_cint_operand" "i")))
11886 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11887 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11888 ""
11889 "#"
11890 [(set_attr "length" "8")])
11891
11892 (define_insn ""
11893 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11894 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11895 (match_operand:SI 2 "u_short_cint_operand" "i")))
11896 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11897 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11898 ""
11899 "#"
11900 [(set_attr "length" "8")])
11901
11902 (define_split
11903 [(set (match_operand:CC 3 "cc_reg_operand" "")
11904 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11905 (match_operand:SI 2 "short_cint_operand" "")))
11906 (set (match_operand:SI 0 "gpc_reg_operand" "")
11907 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11908 ""
11909 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11910 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11911
11912 (define_split
11913 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11914 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11915 (match_operand:SI 2 "u_short_cint_operand" "")))
11916 (set (match_operand:SI 0 "gpc_reg_operand" "")
11917 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11918 ""
11919 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11920 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11921
11922 (define_insn "*cmpsf_internal1"
11923 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11924 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11925 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11926 "TARGET_HARD_FLOAT && TARGET_FPRS"
11927 "fcmpu %0,%1,%2"
11928 [(set_attr "type" "fpcompare")])
11929
11930 (define_insn "*cmpdf_internal1"
11931 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11932 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11933 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11934 "TARGET_HARD_FLOAT && TARGET_FPRS"
11935 "fcmpu %0,%1,%2"
11936 [(set_attr "type" "fpcompare")])
11937
11938 ;; Only need to compare second words if first words equal
11939 (define_insn "*cmptf_internal1"
11940 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11941 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11942 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11943 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
11944 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11945 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11946 [(set_attr "type" "fpcompare")
11947 (set_attr "length" "12")])
11948
11949 (define_insn_and_split "*cmptf_internal2"
11950 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11951 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11952 (match_operand:TF 2 "gpc_reg_operand" "f")))
11953 (clobber (match_scratch:DF 3 "=f"))
11954 (clobber (match_scratch:DF 4 "=f"))
11955 (clobber (match_scratch:DF 5 "=f"))
11956 (clobber (match_scratch:DF 6 "=f"))
11957 (clobber (match_scratch:DF 7 "=f"))
11958 (clobber (match_scratch:DF 8 "=f"))
11959 (clobber (match_scratch:DF 9 "=f"))
11960 (clobber (match_scratch:DF 10 "=f"))]
11961 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
11962 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11963 "#"
11964 "&& reload_completed"
11965 [(set (match_dup 3) (match_dup 13))
11966 (set (match_dup 4) (match_dup 14))
11967 (set (match_dup 9) (abs:DF (match_dup 5)))
11968 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11969 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11970 (label_ref (match_dup 11))
11971 (pc)))
11972 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11973 (set (pc) (label_ref (match_dup 12)))
11974 (match_dup 11)
11975 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11976 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11977 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11978 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
11979 (match_dup 12)]
11980 {
11981 REAL_VALUE_TYPE rv;
11982 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
11983 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
11984
11985 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11986 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11987 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11988 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11989 operands[11] = gen_label_rtx ();
11990 operands[12] = gen_label_rtx ();
11991 real_inf (&rv);
11992 operands[13] = force_const_mem (DFmode,
11993 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11994 operands[14] = force_const_mem (DFmode,
11995 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11996 DFmode));
11997 if (TARGET_TOC)
11998 {
11999 operands[13] = gen_const_mem (DFmode,
12000 create_TOC_reference (XEXP (operands[13], 0)));
12001 operands[14] = gen_const_mem (DFmode,
12002 create_TOC_reference (XEXP (operands[14], 0)));
12003 set_mem_alias_set (operands[13], get_TOC_alias_set ());
12004 set_mem_alias_set (operands[14], get_TOC_alias_set ());
12005 }
12006 })
12007 \f
12008 ;; Now we have the scc insns. We can do some combinations because of the
12009 ;; way the machine works.
12010 ;;
12011 ;; Note that this is probably faster if we can put an insn between the
12012 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
12013 ;; cases the insns below which don't use an intermediate CR field will
12014 ;; be used instead.
12015 (define_insn ""
12016 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12017 (match_operator:SI 1 "scc_comparison_operator"
12018 [(match_operand 2 "cc_reg_operand" "y")
12019 (const_int 0)]))]
12020 ""
12021 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12022 [(set (attr "type")
12023 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12024 (const_string "mfcrf")
12025 ]
12026 (const_string "mfcr")))
12027 (set_attr "length" "8")])
12028
12029 ;; Same as above, but get the GT bit.
12030 (define_insn "move_from_CR_gt_bit"
12031 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12032 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
12033 "TARGET_E500"
12034 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
12035 [(set_attr "type" "mfcr")
12036 (set_attr "length" "8")])
12037
12038 ;; Same as above, but get the OV/ORDERED bit.
12039 (define_insn "move_from_CR_ov_bit"
12040 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12041 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
12042 "TARGET_ISEL"
12043 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
12044 [(set_attr "type" "mfcr")
12045 (set_attr "length" "8")])
12046
12047 (define_insn ""
12048 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12049 (match_operator:DI 1 "scc_comparison_operator"
12050 [(match_operand 2 "cc_reg_operand" "y")
12051 (const_int 0)]))]
12052 "TARGET_POWERPC64"
12053 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12054 [(set (attr "type")
12055 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12056 (const_string "mfcrf")
12057 ]
12058 (const_string "mfcr")))
12059 (set_attr "length" "8")])
12060
12061 (define_insn ""
12062 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12063 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12064 [(match_operand 2 "cc_reg_operand" "y,y")
12065 (const_int 0)])
12066 (const_int 0)))
12067 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
12068 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12069 "TARGET_32BIT"
12070 "@
12071 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
12072 #"
12073 [(set_attr "type" "delayed_compare")
12074 (set_attr "length" "8,16")])
12075
12076 (define_split
12077 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12078 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12079 [(match_operand 2 "cc_reg_operand" "")
12080 (const_int 0)])
12081 (const_int 0)))
12082 (set (match_operand:SI 3 "gpc_reg_operand" "")
12083 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12084 "TARGET_32BIT && reload_completed"
12085 [(set (match_dup 3)
12086 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12087 (set (match_dup 0)
12088 (compare:CC (match_dup 3)
12089 (const_int 0)))]
12090 "")
12091
12092 (define_insn ""
12093 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12094 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12095 [(match_operand 2 "cc_reg_operand" "y")
12096 (const_int 0)])
12097 (match_operand:SI 3 "const_int_operand" "n")))]
12098 ""
12099 "*
12100 {
12101 int is_bit = ccr_bit (operands[1], 1);
12102 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12103 int count;
12104
12105 if (is_bit >= put_bit)
12106 count = is_bit - put_bit;
12107 else
12108 count = 32 - (put_bit - is_bit);
12109
12110 operands[4] = GEN_INT (count);
12111 operands[5] = GEN_INT (put_bit);
12112
12113 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
12114 }"
12115 [(set (attr "type")
12116 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12117 (const_string "mfcrf")
12118 ]
12119 (const_string "mfcr")))
12120 (set_attr "length" "8")])
12121
12122 (define_insn ""
12123 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12124 (compare:CC
12125 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12126 [(match_operand 2 "cc_reg_operand" "y,y")
12127 (const_int 0)])
12128 (match_operand:SI 3 "const_int_operand" "n,n"))
12129 (const_int 0)))
12130 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
12131 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12132 (match_dup 3)))]
12133 ""
12134 "*
12135 {
12136 int is_bit = ccr_bit (operands[1], 1);
12137 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12138 int count;
12139
12140 /* Force split for non-cc0 compare. */
12141 if (which_alternative == 1)
12142 return \"#\";
12143
12144 if (is_bit >= put_bit)
12145 count = is_bit - put_bit;
12146 else
12147 count = 32 - (put_bit - is_bit);
12148
12149 operands[5] = GEN_INT (count);
12150 operands[6] = GEN_INT (put_bit);
12151
12152 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
12153 }"
12154 [(set_attr "type" "delayed_compare")
12155 (set_attr "length" "8,16")])
12156
12157 (define_split
12158 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12159 (compare:CC
12160 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12161 [(match_operand 2 "cc_reg_operand" "")
12162 (const_int 0)])
12163 (match_operand:SI 3 "const_int_operand" ""))
12164 (const_int 0)))
12165 (set (match_operand:SI 4 "gpc_reg_operand" "")
12166 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12167 (match_dup 3)))]
12168 "reload_completed"
12169 [(set (match_dup 4)
12170 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12171 (match_dup 3)))
12172 (set (match_dup 0)
12173 (compare:CC (match_dup 4)
12174 (const_int 0)))]
12175 "")
12176
12177 ;; There is a 3 cycle delay between consecutive mfcr instructions
12178 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
12179
12180 (define_peephole
12181 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12182 (match_operator:SI 1 "scc_comparison_operator"
12183 [(match_operand 2 "cc_reg_operand" "y")
12184 (const_int 0)]))
12185 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
12186 (match_operator:SI 4 "scc_comparison_operator"
12187 [(match_operand 5 "cc_reg_operand" "y")
12188 (const_int 0)]))]
12189 "REGNO (operands[2]) != REGNO (operands[5])"
12190 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
12191 [(set_attr "type" "mfcr")
12192 (set_attr "length" "12")])
12193
12194 (define_peephole
12195 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12196 (match_operator:DI 1 "scc_comparison_operator"
12197 [(match_operand 2 "cc_reg_operand" "y")
12198 (const_int 0)]))
12199 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12200 (match_operator:DI 4 "scc_comparison_operator"
12201 [(match_operand 5 "cc_reg_operand" "y")
12202 (const_int 0)]))]
12203 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
12204 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
12205 [(set_attr "type" "mfcr")
12206 (set_attr "length" "12")])
12207
12208 ;; There are some scc insns that can be done directly, without a compare.
12209 ;; These are faster because they don't involve the communications between
12210 ;; the FXU and branch units. In fact, we will be replacing all of the
12211 ;; integer scc insns here or in the portable methods in emit_store_flag.
12212 ;;
12213 ;; Also support (neg (scc ..)) since that construct is used to replace
12214 ;; branches, (plus (scc ..) ..) since that construct is common and
12215 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12216 ;; cases where it is no more expensive than (neg (scc ..)).
12217
12218 ;; Have reload force a constant into a register for the simple insns that
12219 ;; otherwise won't accept constants. We do this because it is faster than
12220 ;; the cmp/mfcr sequence we would otherwise generate.
12221
12222 (define_mode_attr scc_eq_op2 [(SI "rKLI")
12223 (DI "rKJI")])
12224
12225 (define_insn_and_split "*eq<mode>"
12226 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12227 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
12228 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
12229 "!TARGET_POWER"
12230 "#"
12231 "!TARGET_POWER"
12232 [(set (match_dup 0)
12233 (clz:GPR (match_dup 3)))
12234 (set (match_dup 0)
12235 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
12236 {
12237 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12238 {
12239 /* Use output operand as intermediate. */
12240 operands[3] = operands[0];
12241
12242 if (logical_operand (operands[2], <MODE>mode))
12243 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12244 gen_rtx_XOR (<MODE>mode,
12245 operands[1], operands[2])));
12246 else
12247 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12248 gen_rtx_PLUS (<MODE>mode, operands[1],
12249 negate_rtx (<MODE>mode,
12250 operands[2]))));
12251 }
12252 else
12253 operands[3] = operands[1];
12254
12255 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12256 })
12257
12258 (define_insn_and_split "*eq<mode>_compare"
12259 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12260 (compare:CC
12261 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12262 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
12263 (const_int 0)))
12264 (set (match_operand:P 0 "gpc_reg_operand" "=r")
12265 (eq:P (match_dup 1) (match_dup 2)))]
12266 "!TARGET_POWER && optimize_size"
12267 "#"
12268 "!TARGET_POWER && optimize_size"
12269 [(set (match_dup 0)
12270 (clz:P (match_dup 4)))
12271 (parallel [(set (match_dup 3)
12272 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
12273 (const_int 0)))
12274 (set (match_dup 0)
12275 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
12276 {
12277 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12278 {
12279 /* Use output operand as intermediate. */
12280 operands[4] = operands[0];
12281
12282 if (logical_operand (operands[2], <MODE>mode))
12283 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12284 gen_rtx_XOR (<MODE>mode,
12285 operands[1], operands[2])));
12286 else
12287 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12288 gen_rtx_PLUS (<MODE>mode, operands[1],
12289 negate_rtx (<MODE>mode,
12290 operands[2]))));
12291 }
12292 else
12293 operands[4] = operands[1];
12294
12295 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12296 })
12297
12298 (define_insn "*eqsi_power"
12299 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
12300 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12301 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
12302 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
12303 "TARGET_POWER"
12304 "@
12305 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12306 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
12307 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12308 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12309 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
12310 [(set_attr "type" "three,two,three,three,three")
12311 (set_attr "length" "12,8,12,12,12")])
12312
12313 ;; We have insns of the form shown by the first define_insn below. If
12314 ;; there is something inside the comparison operation, we must split it.
12315 (define_split
12316 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12317 (plus:SI (match_operator 1 "comparison_operator"
12318 [(match_operand:SI 2 "" "")
12319 (match_operand:SI 3
12320 "reg_or_cint_operand" "")])
12321 (match_operand:SI 4 "gpc_reg_operand" "")))
12322 (clobber (match_operand:SI 5 "register_operand" ""))]
12323 "! gpc_reg_operand (operands[2], SImode)"
12324 [(set (match_dup 5) (match_dup 2))
12325 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
12326 (match_dup 4)))])
12327
12328 (define_insn "*plus_eqsi"
12329 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
12330 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12331 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
12332 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
12333 "TARGET_32BIT"
12334 "@
12335 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12336 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
12337 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12338 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12339 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12340 [(set_attr "type" "three,two,three,three,three")
12341 (set_attr "length" "12,8,12,12,12")])
12342
12343 (define_insn "*compare_plus_eqsi"
12344 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12345 (compare:CC
12346 (plus:SI
12347 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12348 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12349 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12350 (const_int 0)))
12351 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
12352 "TARGET_32BIT && optimize_size"
12353 "@
12354 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12355 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
12356 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12357 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12358 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12359 #
12360 #
12361 #
12362 #
12363 #"
12364 [(set_attr "type" "compare")
12365 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12366
12367 (define_split
12368 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12369 (compare:CC
12370 (plus:SI
12371 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12372 (match_operand:SI 2 "scc_eq_operand" ""))
12373 (match_operand:SI 3 "gpc_reg_operand" ""))
12374 (const_int 0)))
12375 (clobber (match_scratch:SI 4 ""))]
12376 "TARGET_32BIT && optimize_size && reload_completed"
12377 [(set (match_dup 4)
12378 (plus:SI (eq:SI (match_dup 1)
12379 (match_dup 2))
12380 (match_dup 3)))
12381 (set (match_dup 0)
12382 (compare:CC (match_dup 4)
12383 (const_int 0)))]
12384 "")
12385
12386 (define_insn "*plus_eqsi_compare"
12387 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12388 (compare:CC
12389 (plus:SI
12390 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12391 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12392 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12393 (const_int 0)))
12394 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12395 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12396 "TARGET_32BIT && optimize_size"
12397 "@
12398 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12399 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
12400 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12401 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12402 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12403 #
12404 #
12405 #
12406 #
12407 #"
12408 [(set_attr "type" "compare")
12409 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12410
12411 (define_split
12412 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12413 (compare:CC
12414 (plus:SI
12415 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12416 (match_operand:SI 2 "scc_eq_operand" ""))
12417 (match_operand:SI 3 "gpc_reg_operand" ""))
12418 (const_int 0)))
12419 (set (match_operand:SI 0 "gpc_reg_operand" "")
12420 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12421 "TARGET_32BIT && optimize_size && reload_completed"
12422 [(set (match_dup 0)
12423 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12424 (set (match_dup 4)
12425 (compare:CC (match_dup 0)
12426 (const_int 0)))]
12427 "")
12428
12429 (define_insn "*neg_eq0<mode>"
12430 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12431 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12432 (const_int 0))))]
12433 ""
12434 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
12435 [(set_attr "type" "two")
12436 (set_attr "length" "8")])
12437
12438 (define_insn_and_split "*neg_eq<mode>"
12439 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12440 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12441 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
12442 ""
12443 "#"
12444 ""
12445 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12446 {
12447 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12448 {
12449 /* Use output operand as intermediate. */
12450 operands[3] = operands[0];
12451
12452 if (logical_operand (operands[2], <MODE>mode))
12453 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12454 gen_rtx_XOR (<MODE>mode,
12455 operands[1], operands[2])));
12456 else
12457 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12458 gen_rtx_PLUS (<MODE>mode, operands[1],
12459 negate_rtx (<MODE>mode,
12460 operands[2]))));
12461 }
12462 else
12463 operands[3] = operands[1];
12464 })
12465
12466 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
12467 ;; since it nabs/sr is just as fast.
12468 (define_insn "*ne0si"
12469 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12470 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12471 (const_int 31)))
12472 (clobber (match_scratch:SI 2 "=&r"))]
12473 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
12474 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
12475 [(set_attr "type" "two")
12476 (set_attr "length" "8")])
12477
12478 (define_insn "*ne0di"
12479 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12480 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12481 (const_int 63)))
12482 (clobber (match_scratch:DI 2 "=&r"))]
12483 "TARGET_64BIT"
12484 "addic %2,%1,-1\;subfe %0,%2,%1"
12485 [(set_attr "type" "two")
12486 (set_attr "length" "8")])
12487
12488 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
12489 (define_insn "*plus_ne0si"
12490 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12491 (plus:SI (lshiftrt:SI
12492 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12493 (const_int 31))
12494 (match_operand:SI 2 "gpc_reg_operand" "r")))
12495 (clobber (match_scratch:SI 3 "=&r"))]
12496 "TARGET_32BIT"
12497 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
12498 [(set_attr "type" "two")
12499 (set_attr "length" "8")])
12500
12501 (define_insn "*plus_ne0di"
12502 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12503 (plus:DI (lshiftrt:DI
12504 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12505 (const_int 63))
12506 (match_operand:DI 2 "gpc_reg_operand" "r")))
12507 (clobber (match_scratch:DI 3 "=&r"))]
12508 "TARGET_64BIT"
12509 "addic %3,%1,-1\;addze %0,%2"
12510 [(set_attr "type" "two")
12511 (set_attr "length" "8")])
12512
12513 (define_insn "*compare_plus_ne0si"
12514 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12515 (compare:CC
12516 (plus:SI (lshiftrt:SI
12517 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12518 (const_int 31))
12519 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12520 (const_int 0)))
12521 (clobber (match_scratch:SI 3 "=&r,&r"))
12522 (clobber (match_scratch:SI 4 "=X,&r"))]
12523 "TARGET_32BIT"
12524 "@
12525 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
12526 #"
12527 [(set_attr "type" "compare")
12528 (set_attr "length" "8,12")])
12529
12530 (define_split
12531 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12532 (compare:CC
12533 (plus:SI (lshiftrt:SI
12534 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12535 (const_int 31))
12536 (match_operand:SI 2 "gpc_reg_operand" ""))
12537 (const_int 0)))
12538 (clobber (match_scratch:SI 3 ""))
12539 (clobber (match_scratch:SI 4 ""))]
12540 "TARGET_32BIT && reload_completed"
12541 [(parallel [(set (match_dup 3)
12542 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
12543 (const_int 31))
12544 (match_dup 2)))
12545 (clobber (match_dup 4))])
12546 (set (match_dup 0)
12547 (compare:CC (match_dup 3)
12548 (const_int 0)))]
12549 "")
12550
12551 (define_insn "*compare_plus_ne0di"
12552 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12553 (compare:CC
12554 (plus:DI (lshiftrt:DI
12555 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12556 (const_int 63))
12557 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12558 (const_int 0)))
12559 (clobber (match_scratch:DI 3 "=&r,&r"))]
12560 "TARGET_64BIT"
12561 "@
12562 addic %3,%1,-1\;addze. %3,%2
12563 #"
12564 [(set_attr "type" "compare")
12565 (set_attr "length" "8,12")])
12566
12567 (define_split
12568 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12569 (compare:CC
12570 (plus:DI (lshiftrt:DI
12571 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12572 (const_int 63))
12573 (match_operand:DI 2 "gpc_reg_operand" ""))
12574 (const_int 0)))
12575 (clobber (match_scratch:DI 3 ""))]
12576 "TARGET_64BIT && reload_completed"
12577 [(set (match_dup 3)
12578 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12579 (const_int 63))
12580 (match_dup 2)))
12581 (set (match_dup 0)
12582 (compare:CC (match_dup 3)
12583 (const_int 0)))]
12584 "")
12585
12586 (define_insn "*plus_ne0si_compare"
12587 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12588 (compare:CC
12589 (plus:SI (lshiftrt:SI
12590 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12591 (const_int 31))
12592 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12593 (const_int 0)))
12594 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12595 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12596 (match_dup 2)))
12597 (clobber (match_scratch:SI 3 "=&r,&r"))]
12598 "TARGET_32BIT"
12599 "@
12600 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
12601 #"
12602 [(set_attr "type" "compare")
12603 (set_attr "length" "8,12")])
12604
12605 (define_split
12606 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12607 (compare:CC
12608 (plus:SI (lshiftrt:SI
12609 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12610 (const_int 31))
12611 (match_operand:SI 2 "gpc_reg_operand" ""))
12612 (const_int 0)))
12613 (set (match_operand:SI 0 "gpc_reg_operand" "")
12614 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12615 (match_dup 2)))
12616 (clobber (match_scratch:SI 3 ""))]
12617 "TARGET_32BIT && reload_completed"
12618 [(parallel [(set (match_dup 0)
12619 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12620 (match_dup 2)))
12621 (clobber (match_dup 3))])
12622 (set (match_dup 4)
12623 (compare:CC (match_dup 0)
12624 (const_int 0)))]
12625 "")
12626
12627 (define_insn "*plus_ne0di_compare"
12628 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12629 (compare:CC
12630 (plus:DI (lshiftrt:DI
12631 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12632 (const_int 63))
12633 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12634 (const_int 0)))
12635 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12636 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12637 (match_dup 2)))
12638 (clobber (match_scratch:DI 3 "=&r,&r"))]
12639 "TARGET_64BIT"
12640 "@
12641 addic %3,%1,-1\;addze. %0,%2
12642 #"
12643 [(set_attr "type" "compare")
12644 (set_attr "length" "8,12")])
12645
12646 (define_split
12647 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12648 (compare:CC
12649 (plus:DI (lshiftrt:DI
12650 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12651 (const_int 63))
12652 (match_operand:DI 2 "gpc_reg_operand" ""))
12653 (const_int 0)))
12654 (set (match_operand:DI 0 "gpc_reg_operand" "")
12655 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12656 (match_dup 2)))
12657 (clobber (match_scratch:DI 3 ""))]
12658 "TARGET_64BIT && reload_completed"
12659 [(parallel [(set (match_dup 0)
12660 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12661 (match_dup 2)))
12662 (clobber (match_dup 3))])
12663 (set (match_dup 4)
12664 (compare:CC (match_dup 0)
12665 (const_int 0)))]
12666 "")
12667
12668 (define_insn ""
12669 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12670 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12671 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12672 (clobber (match_scratch:SI 3 "=r,X"))]
12673 "TARGET_POWER"
12674 "@
12675 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
12676 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
12677 [(set_attr "length" "12")])
12678
12679 (define_insn ""
12680 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12681 (compare:CC
12682 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12683 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12684 (const_int 0)))
12685 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12686 (le:SI (match_dup 1) (match_dup 2)))
12687 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
12688 "TARGET_POWER"
12689 "@
12690 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12691 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
12692 #
12693 #"
12694 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
12695 (set_attr "length" "12,12,16,16")])
12696
12697 (define_split
12698 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12699 (compare:CC
12700 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12701 (match_operand:SI 2 "reg_or_short_operand" ""))
12702 (const_int 0)))
12703 (set (match_operand:SI 0 "gpc_reg_operand" "")
12704 (le:SI (match_dup 1) (match_dup 2)))
12705 (clobber (match_scratch:SI 3 ""))]
12706 "TARGET_POWER && reload_completed"
12707 [(parallel [(set (match_dup 0)
12708 (le:SI (match_dup 1) (match_dup 2)))
12709 (clobber (match_dup 3))])
12710 (set (match_dup 4)
12711 (compare:CC (match_dup 0)
12712 (const_int 0)))]
12713 "")
12714
12715 (define_insn ""
12716 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12717 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12718 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
12719 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12720 "TARGET_POWER"
12721 "@
12722 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12723 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
12724 [(set_attr "length" "12")])
12725
12726 (define_insn ""
12727 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12728 (compare:CC
12729 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12730 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12731 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12732 (const_int 0)))
12733 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12734 "TARGET_POWER"
12735 "@
12736 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12737 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12738 #
12739 #"
12740 [(set_attr "type" "compare")
12741 (set_attr "length" "12,12,16,16")])
12742
12743 (define_split
12744 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12745 (compare:CC
12746 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12747 (match_operand:SI 2 "reg_or_short_operand" ""))
12748 (match_operand:SI 3 "gpc_reg_operand" ""))
12749 (const_int 0)))
12750 (clobber (match_scratch:SI 4 ""))]
12751 "TARGET_POWER && reload_completed"
12752 [(set (match_dup 4)
12753 (plus:SI (le:SI (match_dup 1) (match_dup 2))
12754 (match_dup 3)))
12755 (set (match_dup 0)
12756 (compare:CC (match_dup 4)
12757 (const_int 0)))]
12758 "")
12759
12760 (define_insn ""
12761 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12762 (compare:CC
12763 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12764 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12765 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12766 (const_int 0)))
12767 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12768 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12769 "TARGET_POWER"
12770 "@
12771 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12772 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
12773 #
12774 #"
12775 [(set_attr "type" "compare")
12776 (set_attr "length" "12,12,16,16")])
12777
12778 (define_split
12779 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12780 (compare:CC
12781 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12782 (match_operand:SI 2 "reg_or_short_operand" ""))
12783 (match_operand:SI 3 "gpc_reg_operand" ""))
12784 (const_int 0)))
12785 (set (match_operand:SI 0 "gpc_reg_operand" "")
12786 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12787 "TARGET_POWER && reload_completed"
12788 [(set (match_dup 0)
12789 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12790 (set (match_dup 4)
12791 (compare:CC (match_dup 0)
12792 (const_int 0)))]
12793 "")
12794
12795 (define_insn ""
12796 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12797 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12798 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
12799 "TARGET_POWER"
12800 "@
12801 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12802 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
12803 [(set_attr "length" "12")])
12804
12805 (define_insn "*leu<mode>"
12806 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12807 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12808 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12809 ""
12810 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12811 [(set_attr "type" "three")
12812 (set_attr "length" "12")])
12813
12814 (define_insn "*leu<mode>_compare"
12815 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12816 (compare:CC
12817 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12818 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12819 (const_int 0)))
12820 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12821 (leu:P (match_dup 1) (match_dup 2)))]
12822 ""
12823 "@
12824 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12825 #"
12826 [(set_attr "type" "compare")
12827 (set_attr "length" "12,16")])
12828
12829 (define_split
12830 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12831 (compare:CC
12832 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12833 (match_operand:P 2 "reg_or_short_operand" ""))
12834 (const_int 0)))
12835 (set (match_operand:P 0 "gpc_reg_operand" "")
12836 (leu:P (match_dup 1) (match_dup 2)))]
12837 "reload_completed"
12838 [(set (match_dup 0)
12839 (leu:P (match_dup 1) (match_dup 2)))
12840 (set (match_dup 3)
12841 (compare:CC (match_dup 0)
12842 (const_int 0)))]
12843 "")
12844
12845 (define_insn "*plus_leu<mode>"
12846 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12847 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12848 (match_operand:P 2 "reg_or_short_operand" "rI"))
12849 (match_operand:P 3 "gpc_reg_operand" "r")))]
12850 ""
12851 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12852 [(set_attr "type" "two")
12853 (set_attr "length" "8")])
12854
12855 (define_insn ""
12856 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12857 (compare:CC
12858 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12859 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12860 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12861 (const_int 0)))
12862 (clobber (match_scratch:SI 4 "=&r,&r"))]
12863 "TARGET_32BIT"
12864 "@
12865 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12866 #"
12867 [(set_attr "type" "compare")
12868 (set_attr "length" "8,12")])
12869
12870 (define_split
12871 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12872 (compare:CC
12873 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12874 (match_operand:SI 2 "reg_or_short_operand" ""))
12875 (match_operand:SI 3 "gpc_reg_operand" ""))
12876 (const_int 0)))
12877 (clobber (match_scratch:SI 4 ""))]
12878 "TARGET_32BIT && reload_completed"
12879 [(set (match_dup 4)
12880 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12881 (match_dup 3)))
12882 (set (match_dup 0)
12883 (compare:CC (match_dup 4)
12884 (const_int 0)))]
12885 "")
12886
12887 (define_insn ""
12888 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12889 (compare:CC
12890 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12891 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12892 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12893 (const_int 0)))
12894 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12895 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12896 "TARGET_32BIT"
12897 "@
12898 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12899 #"
12900 [(set_attr "type" "compare")
12901 (set_attr "length" "8,12")])
12902
12903 (define_split
12904 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12905 (compare:CC
12906 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12907 (match_operand:SI 2 "reg_or_short_operand" ""))
12908 (match_operand:SI 3 "gpc_reg_operand" ""))
12909 (const_int 0)))
12910 (set (match_operand:SI 0 "gpc_reg_operand" "")
12911 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12912 "TARGET_32BIT && reload_completed"
12913 [(set (match_dup 0)
12914 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12915 (set (match_dup 4)
12916 (compare:CC (match_dup 0)
12917 (const_int 0)))]
12918 "")
12919
12920 (define_insn "*neg_leu<mode>"
12921 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12922 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12923 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12924 ""
12925 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12926 [(set_attr "type" "three")
12927 (set_attr "length" "12")])
12928
12929 (define_insn "*and_neg_leu<mode>"
12930 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12931 (and:P (neg:P
12932 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12933 (match_operand:P 2 "reg_or_short_operand" "rI")))
12934 (match_operand:P 3 "gpc_reg_operand" "r")))]
12935 ""
12936 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12937 [(set_attr "type" "three")
12938 (set_attr "length" "12")])
12939
12940 (define_insn ""
12941 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12942 (compare:CC
12943 (and:SI (neg:SI
12944 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12945 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12946 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12947 (const_int 0)))
12948 (clobber (match_scratch:SI 4 "=&r,&r"))]
12949 "TARGET_32BIT"
12950 "@
12951 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12952 #"
12953 [(set_attr "type" "compare")
12954 (set_attr "length" "12,16")])
12955
12956 (define_split
12957 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12958 (compare:CC
12959 (and:SI (neg:SI
12960 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12961 (match_operand:SI 2 "reg_or_short_operand" "")))
12962 (match_operand:SI 3 "gpc_reg_operand" ""))
12963 (const_int 0)))
12964 (clobber (match_scratch:SI 4 ""))]
12965 "TARGET_32BIT && reload_completed"
12966 [(set (match_dup 4)
12967 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12968 (match_dup 3)))
12969 (set (match_dup 0)
12970 (compare:CC (match_dup 4)
12971 (const_int 0)))]
12972 "")
12973
12974 (define_insn ""
12975 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12976 (compare:CC
12977 (and:SI (neg:SI
12978 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12979 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12980 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12981 (const_int 0)))
12982 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12983 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12984 "TARGET_32BIT"
12985 "@
12986 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12987 #"
12988 [(set_attr "type" "compare")
12989 (set_attr "length" "12,16")])
12990
12991 (define_split
12992 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12993 (compare:CC
12994 (and:SI (neg:SI
12995 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12996 (match_operand:SI 2 "reg_or_short_operand" "")))
12997 (match_operand:SI 3 "gpc_reg_operand" ""))
12998 (const_int 0)))
12999 (set (match_operand:SI 0 "gpc_reg_operand" "")
13000 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13001 "TARGET_32BIT && reload_completed"
13002 [(set (match_dup 0)
13003 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13004 (match_dup 3)))
13005 (set (match_dup 4)
13006 (compare:CC (match_dup 0)
13007 (const_int 0)))]
13008 "")
13009
13010 (define_insn ""
13011 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13012 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13013 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13014 "TARGET_POWER"
13015 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13016 [(set_attr "length" "12")])
13017
13018 (define_insn ""
13019 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13020 (compare:CC
13021 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13022 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13023 (const_int 0)))
13024 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13025 (lt:SI (match_dup 1) (match_dup 2)))]
13026 "TARGET_POWER"
13027 "@
13028 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13029 #"
13030 [(set_attr "type" "delayed_compare")
13031 (set_attr "length" "12,16")])
13032
13033 (define_split
13034 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13035 (compare:CC
13036 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13037 (match_operand:SI 2 "reg_or_short_operand" ""))
13038 (const_int 0)))
13039 (set (match_operand:SI 0 "gpc_reg_operand" "")
13040 (lt:SI (match_dup 1) (match_dup 2)))]
13041 "TARGET_POWER && reload_completed"
13042 [(set (match_dup 0)
13043 (lt:SI (match_dup 1) (match_dup 2)))
13044 (set (match_dup 3)
13045 (compare:CC (match_dup 0)
13046 (const_int 0)))]
13047 "")
13048
13049 (define_insn ""
13050 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13051 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13052 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13053 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13054 "TARGET_POWER"
13055 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13056 [(set_attr "length" "12")])
13057
13058 (define_insn ""
13059 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13060 (compare:CC
13061 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13062 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13063 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13064 (const_int 0)))
13065 (clobber (match_scratch:SI 4 "=&r,&r"))]
13066 "TARGET_POWER"
13067 "@
13068 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13069 #"
13070 [(set_attr "type" "compare")
13071 (set_attr "length" "12,16")])
13072
13073 (define_split
13074 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13075 (compare:CC
13076 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13077 (match_operand:SI 2 "reg_or_short_operand" ""))
13078 (match_operand:SI 3 "gpc_reg_operand" ""))
13079 (const_int 0)))
13080 (clobber (match_scratch:SI 4 ""))]
13081 "TARGET_POWER && reload_completed"
13082 [(set (match_dup 4)
13083 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
13084 (match_dup 3)))
13085 (set (match_dup 0)
13086 (compare:CC (match_dup 4)
13087 (const_int 0)))]
13088 "")
13089
13090 (define_insn ""
13091 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13092 (compare:CC
13093 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13094 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13095 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13096 (const_int 0)))
13097 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13098 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13099 "TARGET_POWER"
13100 "@
13101 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13102 #"
13103 [(set_attr "type" "compare")
13104 (set_attr "length" "12,16")])
13105
13106 (define_split
13107 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13108 (compare:CC
13109 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13110 (match_operand:SI 2 "reg_or_short_operand" ""))
13111 (match_operand:SI 3 "gpc_reg_operand" ""))
13112 (const_int 0)))
13113 (set (match_operand:SI 0 "gpc_reg_operand" "")
13114 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13115 "TARGET_POWER && reload_completed"
13116 [(set (match_dup 0)
13117 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13118 (set (match_dup 4)
13119 (compare:CC (match_dup 0)
13120 (const_int 0)))]
13121 "")
13122
13123 (define_insn ""
13124 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13125 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13126 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13127 "TARGET_POWER"
13128 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13129 [(set_attr "length" "12")])
13130
13131 (define_insn_and_split "*ltu<mode>"
13132 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13133 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13134 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13135 ""
13136 "#"
13137 ""
13138 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13139 (set (match_dup 0) (neg:P (match_dup 0)))]
13140 "")
13141
13142 (define_insn_and_split "*ltu<mode>_compare"
13143 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13144 (compare:CC
13145 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13146 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13147 (const_int 0)))
13148 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13149 (ltu:P (match_dup 1) (match_dup 2)))]
13150 ""
13151 "#"
13152 ""
13153 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13154 (parallel [(set (match_dup 3)
13155 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13156 (set (match_dup 0) (neg:P (match_dup 0)))])]
13157 "")
13158
13159 (define_insn_and_split "*plus_ltu<mode>"
13160 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
13161 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13162 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13163 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
13164 ""
13165 "#"
13166 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13167 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13168 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13169 "")
13170
13171 (define_insn_and_split "*plus_ltu<mode>_compare"
13172 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13173 (compare:CC
13174 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13175 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13176 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13177 (const_int 0)))
13178 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13179 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13180 ""
13181 "#"
13182 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13183 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13184 (parallel [(set (match_dup 4)
13185 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13186 (const_int 0)))
13187 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13188 "")
13189
13190 (define_insn "*neg_ltu<mode>"
13191 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13192 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13193 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
13194 ""
13195 "@
13196 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
13197 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
13198 [(set_attr "type" "two")
13199 (set_attr "length" "8")])
13200
13201 (define_insn ""
13202 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13203 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13204 (match_operand:SI 2 "reg_or_short_operand" "rI")))
13205 (clobber (match_scratch:SI 3 "=r"))]
13206 "TARGET_POWER"
13207 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
13208 [(set_attr "length" "12")])
13209
13210 (define_insn ""
13211 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13212 (compare:CC
13213 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13214 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13215 (const_int 0)))
13216 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13217 (ge:SI (match_dup 1) (match_dup 2)))
13218 (clobber (match_scratch:SI 3 "=r,r"))]
13219 "TARGET_POWER"
13220 "@
13221 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13222 #"
13223 [(set_attr "type" "compare")
13224 (set_attr "length" "12,16")])
13225
13226 (define_split
13227 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13228 (compare:CC
13229 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13230 (match_operand:SI 2 "reg_or_short_operand" ""))
13231 (const_int 0)))
13232 (set (match_operand:SI 0 "gpc_reg_operand" "")
13233 (ge:SI (match_dup 1) (match_dup 2)))
13234 (clobber (match_scratch:SI 3 ""))]
13235 "TARGET_POWER && reload_completed"
13236 [(parallel [(set (match_dup 0)
13237 (ge:SI (match_dup 1) (match_dup 2)))
13238 (clobber (match_dup 3))])
13239 (set (match_dup 4)
13240 (compare:CC (match_dup 0)
13241 (const_int 0)))]
13242 "")
13243
13244 (define_insn ""
13245 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13246 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13247 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13248 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13249 "TARGET_POWER"
13250 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
13251 [(set_attr "length" "12")])
13252
13253 (define_insn ""
13254 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13255 (compare:CC
13256 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13257 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13258 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13259 (const_int 0)))
13260 (clobber (match_scratch:SI 4 "=&r,&r"))]
13261 "TARGET_POWER"
13262 "@
13263 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13264 #"
13265 [(set_attr "type" "compare")
13266 (set_attr "length" "12,16")])
13267
13268 (define_split
13269 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13270 (compare:CC
13271 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13272 (match_operand:SI 2 "reg_or_short_operand" ""))
13273 (match_operand:SI 3 "gpc_reg_operand" ""))
13274 (const_int 0)))
13275 (clobber (match_scratch:SI 4 ""))]
13276 "TARGET_POWER && reload_completed"
13277 [(set (match_dup 4)
13278 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
13279 (match_dup 3)))
13280 (set (match_dup 0)
13281 (compare:CC (match_dup 4)
13282 (const_int 0)))]
13283 "")
13284
13285 (define_insn ""
13286 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13287 (compare:CC
13288 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13289 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13290 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13291 (const_int 0)))
13292 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13293 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13294 "TARGET_POWER"
13295 "@
13296 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13297 #"
13298 [(set_attr "type" "compare")
13299 (set_attr "length" "12,16")])
13300
13301 (define_split
13302 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13303 (compare:CC
13304 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13305 (match_operand:SI 2 "reg_or_short_operand" ""))
13306 (match_operand:SI 3 "gpc_reg_operand" ""))
13307 (const_int 0)))
13308 (set (match_operand:SI 0 "gpc_reg_operand" "")
13309 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13310 "TARGET_POWER && reload_completed"
13311 [(set (match_dup 0)
13312 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13313 (set (match_dup 4)
13314 (compare:CC (match_dup 0)
13315 (const_int 0)))]
13316 "")
13317
13318 (define_insn ""
13319 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13320 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13321 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13322 "TARGET_POWER"
13323 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
13324 [(set_attr "length" "12")])
13325
13326 (define_insn "*geu<mode>"
13327 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13328 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13329 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13330 ""
13331 "@
13332 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
13333 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
13334 [(set_attr "type" "three")
13335 (set_attr "length" "12")])
13336
13337 (define_insn "*geu<mode>_compare"
13338 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13339 (compare:CC
13340 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13341 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13342 (const_int 0)))
13343 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13344 (geu:P (match_dup 1) (match_dup 2)))]
13345 ""
13346 "@
13347 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13348 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13349 #
13350 #"
13351 [(set_attr "type" "compare")
13352 (set_attr "length" "12,12,16,16")])
13353
13354 (define_split
13355 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13356 (compare:CC
13357 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
13358 (match_operand:P 2 "reg_or_neg_short_operand" ""))
13359 (const_int 0)))
13360 (set (match_operand:P 0 "gpc_reg_operand" "")
13361 (geu:P (match_dup 1) (match_dup 2)))]
13362 "reload_completed"
13363 [(set (match_dup 0)
13364 (geu:P (match_dup 1) (match_dup 2)))
13365 (set (match_dup 3)
13366 (compare:CC (match_dup 0)
13367 (const_int 0)))]
13368 "")
13369
13370 (define_insn "*plus_geu<mode>"
13371 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13372 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13373 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13374 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13375 ""
13376 "@
13377 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
13378 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
13379 [(set_attr "type" "two")
13380 (set_attr "length" "8")])
13381
13382 (define_insn ""
13383 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13384 (compare:CC
13385 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13386 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13387 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13388 (const_int 0)))
13389 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13390 "TARGET_32BIT"
13391 "@
13392 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
13393 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
13394 #
13395 #"
13396 [(set_attr "type" "compare")
13397 (set_attr "length" "8,8,12,12")])
13398
13399 (define_split
13400 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13401 (compare:CC
13402 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13403 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13404 (match_operand:SI 3 "gpc_reg_operand" ""))
13405 (const_int 0)))
13406 (clobber (match_scratch:SI 4 ""))]
13407 "TARGET_32BIT && reload_completed"
13408 [(set (match_dup 4)
13409 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13410 (match_dup 3)))
13411 (set (match_dup 0)
13412 (compare:CC (match_dup 4)
13413 (const_int 0)))]
13414 "")
13415
13416 (define_insn ""
13417 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13418 (compare:CC
13419 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13420 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13421 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13422 (const_int 0)))
13423 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13424 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13425 "TARGET_32BIT"
13426 "@
13427 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
13428 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
13429 #
13430 #"
13431 [(set_attr "type" "compare")
13432 (set_attr "length" "8,8,12,12")])
13433
13434 (define_split
13435 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13436 (compare:CC
13437 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13438 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13439 (match_operand:SI 3 "gpc_reg_operand" ""))
13440 (const_int 0)))
13441 (set (match_operand:SI 0 "gpc_reg_operand" "")
13442 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13443 "TARGET_32BIT && reload_completed"
13444 [(set (match_dup 0)
13445 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13446 (set (match_dup 4)
13447 (compare:CC (match_dup 0)
13448 (const_int 0)))]
13449 "")
13450
13451 (define_insn "*neg_geu<mode>"
13452 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13453 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13454 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13455 ""
13456 "@
13457 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
13458 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
13459 [(set_attr "type" "three")
13460 (set_attr "length" "12")])
13461
13462 (define_insn "*and_neg_geu<mode>"
13463 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13464 (and:P (neg:P
13465 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13466 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13467 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13468 ""
13469 "@
13470 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
13471 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13472 [(set_attr "type" "three")
13473 (set_attr "length" "12")])
13474
13475 (define_insn ""
13476 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13477 (compare:CC
13478 (and:SI (neg:SI
13479 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13480 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13481 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13482 (const_int 0)))
13483 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13484 "TARGET_32BIT"
13485 "@
13486 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13487 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13488 #
13489 #"
13490 [(set_attr "type" "compare")
13491 (set_attr "length" "12,12,16,16")])
13492
13493 (define_split
13494 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13495 (compare:CC
13496 (and:SI (neg:SI
13497 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13498 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13499 (match_operand:SI 3 "gpc_reg_operand" ""))
13500 (const_int 0)))
13501 (clobber (match_scratch:SI 4 ""))]
13502 "TARGET_32BIT && reload_completed"
13503 [(set (match_dup 4)
13504 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13505 (match_dup 3)))
13506 (set (match_dup 0)
13507 (compare:CC (match_dup 4)
13508 (const_int 0)))]
13509 "")
13510
13511 (define_insn ""
13512 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13513 (compare:CC
13514 (and:SI (neg:SI
13515 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13516 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13517 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13518 (const_int 0)))
13519 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13520 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13521 "TARGET_32BIT"
13522 "@
13523 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13524 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13525 #
13526 #"
13527 [(set_attr "type" "compare")
13528 (set_attr "length" "12,12,16,16")])
13529
13530 (define_split
13531 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13532 (compare:CC
13533 (and:SI (neg:SI
13534 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13535 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13536 (match_operand:SI 3 "gpc_reg_operand" ""))
13537 (const_int 0)))
13538 (set (match_operand:SI 0 "gpc_reg_operand" "")
13539 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13540 "TARGET_32BIT && reload_completed"
13541 [(set (match_dup 0)
13542 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13543 (set (match_dup 4)
13544 (compare:CC (match_dup 0)
13545 (const_int 0)))]
13546 "")
13547
13548 (define_insn ""
13549 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13550 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13551 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13552 "TARGET_POWER"
13553 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13554 [(set_attr "length" "12")])
13555
13556 (define_insn ""
13557 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13558 (compare:CC
13559 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13560 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13561 (const_int 0)))
13562 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13563 (gt:SI (match_dup 1) (match_dup 2)))]
13564 "TARGET_POWER"
13565 "@
13566 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13567 #"
13568 [(set_attr "type" "delayed_compare")
13569 (set_attr "length" "12,16")])
13570
13571 (define_split
13572 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13573 (compare:CC
13574 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13575 (match_operand:SI 2 "reg_or_short_operand" ""))
13576 (const_int 0)))
13577 (set (match_operand:SI 0 "gpc_reg_operand" "")
13578 (gt:SI (match_dup 1) (match_dup 2)))]
13579 "TARGET_POWER && reload_completed"
13580 [(set (match_dup 0)
13581 (gt:SI (match_dup 1) (match_dup 2)))
13582 (set (match_dup 3)
13583 (compare:CC (match_dup 0)
13584 (const_int 0)))]
13585 "")
13586
13587 (define_insn "*plus_gt0<mode>"
13588 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13589 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13590 (const_int 0))
13591 (match_operand:P 2 "gpc_reg_operand" "r")))]
13592 ""
13593 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13594 [(set_attr "type" "three")
13595 (set_attr "length" "12")])
13596
13597 (define_insn ""
13598 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13599 (compare:CC
13600 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13601 (const_int 0))
13602 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13603 (const_int 0)))
13604 (clobber (match_scratch:SI 3 "=&r,&r"))]
13605 "TARGET_32BIT"
13606 "@
13607 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13608 #"
13609 [(set_attr "type" "compare")
13610 (set_attr "length" "12,16")])
13611
13612 (define_split
13613 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13614 (compare:CC
13615 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13616 (const_int 0))
13617 (match_operand:SI 2 "gpc_reg_operand" ""))
13618 (const_int 0)))
13619 (clobber (match_scratch:SI 3 ""))]
13620 "TARGET_32BIT && reload_completed"
13621 [(set (match_dup 3)
13622 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13623 (match_dup 2)))
13624 (set (match_dup 0)
13625 (compare:CC (match_dup 3)
13626 (const_int 0)))]
13627 "")
13628
13629 (define_insn ""
13630 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13631 (compare:CC
13632 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13633 (const_int 0))
13634 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13635 (const_int 0)))
13636 (clobber (match_scratch:DI 3 "=&r,&r"))]
13637 "TARGET_64BIT"
13638 "@
13639 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13640 #"
13641 [(set_attr "type" "compare")
13642 (set_attr "length" "12,16")])
13643
13644 (define_split
13645 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13646 (compare:CC
13647 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13648 (const_int 0))
13649 (match_operand:DI 2 "gpc_reg_operand" ""))
13650 (const_int 0)))
13651 (clobber (match_scratch:DI 3 ""))]
13652 "TARGET_64BIT && reload_completed"
13653 [(set (match_dup 3)
13654 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13655 (match_dup 2)))
13656 (set (match_dup 0)
13657 (compare:CC (match_dup 3)
13658 (const_int 0)))]
13659 "")
13660
13661 (define_insn ""
13662 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13663 (compare:CC
13664 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13665 (const_int 0))
13666 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13667 (const_int 0)))
13668 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13669 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13670 "TARGET_32BIT"
13671 "@
13672 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13673 #"
13674 [(set_attr "type" "compare")
13675 (set_attr "length" "12,16")])
13676
13677 (define_split
13678 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13679 (compare:CC
13680 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13681 (const_int 0))
13682 (match_operand:SI 2 "gpc_reg_operand" ""))
13683 (const_int 0)))
13684 (set (match_operand:SI 0 "gpc_reg_operand" "")
13685 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13686 "TARGET_32BIT && reload_completed"
13687 [(set (match_dup 0)
13688 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13689 (set (match_dup 3)
13690 (compare:CC (match_dup 0)
13691 (const_int 0)))]
13692 "")
13693
13694 (define_insn ""
13695 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13696 (compare:CC
13697 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13698 (const_int 0))
13699 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13700 (const_int 0)))
13701 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13702 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13703 "TARGET_64BIT"
13704 "@
13705 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13706 #"
13707 [(set_attr "type" "compare")
13708 (set_attr "length" "12,16")])
13709
13710 (define_split
13711 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13712 (compare:CC
13713 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13714 (const_int 0))
13715 (match_operand:DI 2 "gpc_reg_operand" ""))
13716 (const_int 0)))
13717 (set (match_operand:DI 0 "gpc_reg_operand" "")
13718 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13719 "TARGET_64BIT && reload_completed"
13720 [(set (match_dup 0)
13721 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13722 (set (match_dup 3)
13723 (compare:CC (match_dup 0)
13724 (const_int 0)))]
13725 "")
13726
13727 (define_insn ""
13728 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13729 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13730 (match_operand:SI 2 "reg_or_short_operand" "r"))
13731 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13732 "TARGET_POWER"
13733 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13734 [(set_attr "length" "12")])
13735
13736 (define_insn ""
13737 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13738 (compare:CC
13739 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13740 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13741 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13742 (const_int 0)))
13743 (clobber (match_scratch:SI 4 "=&r,&r"))]
13744 "TARGET_POWER"
13745 "@
13746 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13747 #"
13748 [(set_attr "type" "compare")
13749 (set_attr "length" "12,16")])
13750
13751 (define_split
13752 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13753 (compare:CC
13754 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13755 (match_operand:SI 2 "reg_or_short_operand" ""))
13756 (match_operand:SI 3 "gpc_reg_operand" ""))
13757 (const_int 0)))
13758 (clobber (match_scratch:SI 4 ""))]
13759 "TARGET_POWER && reload_completed"
13760 [(set (match_dup 4)
13761 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13762 (set (match_dup 0)
13763 (compare:CC (match_dup 4)
13764 (const_int 0)))]
13765 "")
13766
13767 (define_insn ""
13768 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13769 (compare:CC
13770 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13771 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13772 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13773 (const_int 0)))
13774 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13775 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13776 "TARGET_POWER"
13777 "@
13778 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13779 #"
13780 [(set_attr "type" "compare")
13781 (set_attr "length" "12,16")])
13782
13783 (define_split
13784 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13785 (compare:CC
13786 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13787 (match_operand:SI 2 "reg_or_short_operand" ""))
13788 (match_operand:SI 3 "gpc_reg_operand" ""))
13789 (const_int 0)))
13790 (set (match_operand:SI 0 "gpc_reg_operand" "")
13791 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13792 "TARGET_POWER && reload_completed"
13793 [(set (match_dup 0)
13794 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13795 (set (match_dup 4)
13796 (compare:CC (match_dup 0)
13797 (const_int 0)))]
13798 "")
13799
13800 (define_insn ""
13801 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13802 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13803 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13804 "TARGET_POWER"
13805 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13806 [(set_attr "length" "12")])
13807
13808 (define_insn_and_split "*gtu<mode>"
13809 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13810 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13811 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13812 ""
13813 "#"
13814 ""
13815 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13816 (set (match_dup 0) (neg:P (match_dup 0)))]
13817 "")
13818
13819 (define_insn_and_split "*gtu<mode>_compare"
13820 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13821 (compare:CC
13822 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13823 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13824 (const_int 0)))
13825 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13826 (gtu:P (match_dup 1) (match_dup 2)))]
13827 ""
13828 "#"
13829 ""
13830 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13831 (parallel [(set (match_dup 3)
13832 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13833 (set (match_dup 0) (neg:P (match_dup 0)))])]
13834 "")
13835
13836 (define_insn_and_split "*plus_gtu<mode>"
13837 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13838 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13839 (match_operand:P 2 "reg_or_short_operand" "rI"))
13840 (match_operand:P 3 "reg_or_short_operand" "rI")))]
13841 ""
13842 "#"
13843 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13844 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13845 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13846 "")
13847
13848 (define_insn_and_split "*plus_gtu<mode>_compare"
13849 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13850 (compare:CC
13851 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13852 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13853 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13854 (const_int 0)))
13855 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13856 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13857 ""
13858 "#"
13859 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13860 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13861 (parallel [(set (match_dup 4)
13862 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13863 (const_int 0)))
13864 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13865 "")
13866
13867 (define_insn "*neg_gtu<mode>"
13868 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13869 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13870 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13871 ""
13872 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13873 [(set_attr "type" "two")
13874 (set_attr "length" "8")])
13875
13876 \f
13877 ;; Define both directions of branch and return. If we need a reload
13878 ;; register, we'd rather use CR0 since it is much easier to copy a
13879 ;; register CC value to there.
13880
13881 (define_insn ""
13882 [(set (pc)
13883 (if_then_else (match_operator 1 "branch_comparison_operator"
13884 [(match_operand 2
13885 "cc_reg_operand" "y")
13886 (const_int 0)])
13887 (label_ref (match_operand 0 "" ""))
13888 (pc)))]
13889 ""
13890 "*
13891 {
13892 return output_cbranch (operands[1], \"%l0\", 0, insn);
13893 }"
13894 [(set_attr "type" "branch")])
13895
13896 (define_insn ""
13897 [(set (pc)
13898 (if_then_else (match_operator 0 "branch_comparison_operator"
13899 [(match_operand 1
13900 "cc_reg_operand" "y")
13901 (const_int 0)])
13902 (return)
13903 (pc)))]
13904 "direct_return ()"
13905 "*
13906 {
13907 return output_cbranch (operands[0], NULL, 0, insn);
13908 }"
13909 [(set_attr "type" "jmpreg")
13910 (set_attr "length" "4")])
13911
13912 (define_insn ""
13913 [(set (pc)
13914 (if_then_else (match_operator 1 "branch_comparison_operator"
13915 [(match_operand 2
13916 "cc_reg_operand" "y")
13917 (const_int 0)])
13918 (pc)
13919 (label_ref (match_operand 0 "" ""))))]
13920 ""
13921 "*
13922 {
13923 return output_cbranch (operands[1], \"%l0\", 1, insn);
13924 }"
13925 [(set_attr "type" "branch")])
13926
13927 (define_insn ""
13928 [(set (pc)
13929 (if_then_else (match_operator 0 "branch_comparison_operator"
13930 [(match_operand 1
13931 "cc_reg_operand" "y")
13932 (const_int 0)])
13933 (pc)
13934 (return)))]
13935 "direct_return ()"
13936 "*
13937 {
13938 return output_cbranch (operands[0], NULL, 1, insn);
13939 }"
13940 [(set_attr "type" "jmpreg")
13941 (set_attr "length" "4")])
13942
13943 ;; Logic on condition register values.
13944
13945 ; This pattern matches things like
13946 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13947 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13948 ; (const_int 1)))
13949 ; which are generated by the branch logic.
13950 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13951
13952 (define_insn "*cceq_ior_compare"
13953 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13954 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13955 [(match_operator:SI 2
13956 "branch_positive_comparison_operator"
13957 [(match_operand 3
13958 "cc_reg_operand" "y,y")
13959 (const_int 0)])
13960 (match_operator:SI 4
13961 "branch_positive_comparison_operator"
13962 [(match_operand 5
13963 "cc_reg_operand" "0,y")
13964 (const_int 0)])])
13965 (const_int 1)))]
13966 ""
13967 "cr%q1 %E0,%j2,%j4"
13968 [(set_attr "type" "cr_logical,delayed_cr")])
13969
13970 ; Why is the constant -1 here, but 1 in the previous pattern?
13971 ; Because ~1 has all but the low bit set.
13972 (define_insn ""
13973 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13974 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13975 [(not:SI (match_operator:SI 2
13976 "branch_positive_comparison_operator"
13977 [(match_operand 3
13978 "cc_reg_operand" "y,y")
13979 (const_int 0)]))
13980 (match_operator:SI 4
13981 "branch_positive_comparison_operator"
13982 [(match_operand 5
13983 "cc_reg_operand" "0,y")
13984 (const_int 0)])])
13985 (const_int -1)))]
13986 ""
13987 "cr%q1 %E0,%j2,%j4"
13988 [(set_attr "type" "cr_logical,delayed_cr")])
13989
13990 (define_insn "*cceq_rev_compare"
13991 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13992 (compare:CCEQ (match_operator:SI 1
13993 "branch_positive_comparison_operator"
13994 [(match_operand 2
13995 "cc_reg_operand" "0,y")
13996 (const_int 0)])
13997 (const_int 0)))]
13998 ""
13999 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
14000 [(set_attr "type" "cr_logical,delayed_cr")])
14001
14002 ;; If we are comparing the result of two comparisons, this can be done
14003 ;; using creqv or crxor.
14004
14005 (define_insn_and_split ""
14006 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14007 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
14008 [(match_operand 2 "cc_reg_operand" "y")
14009 (const_int 0)])
14010 (match_operator 3 "branch_comparison_operator"
14011 [(match_operand 4 "cc_reg_operand" "y")
14012 (const_int 0)])))]
14013 ""
14014 "#"
14015 ""
14016 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14017 (match_dup 5)))]
14018 "
14019 {
14020 int positive_1, positive_2;
14021
14022 positive_1 = branch_positive_comparison_operator (operands[1],
14023 GET_MODE (operands[1]));
14024 positive_2 = branch_positive_comparison_operator (operands[3],
14025 GET_MODE (operands[3]));
14026
14027 if (! positive_1)
14028 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
14029 GET_CODE (operands[1])),
14030 SImode,
14031 operands[2], const0_rtx);
14032 else if (GET_MODE (operands[1]) != SImode)
14033 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14034 operands[2], const0_rtx);
14035
14036 if (! positive_2)
14037 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
14038 GET_CODE (operands[3])),
14039 SImode,
14040 operands[4], const0_rtx);
14041 else if (GET_MODE (operands[3]) != SImode)
14042 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14043 operands[4], const0_rtx);
14044
14045 if (positive_1 == positive_2)
14046 {
14047 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14048 operands[5] = constm1_rtx;
14049 }
14050 else
14051 {
14052 operands[5] = const1_rtx;
14053 }
14054 }")
14055
14056 ;; Unconditional branch and return.
14057
14058 (define_insn "jump"
14059 [(set (pc)
14060 (label_ref (match_operand 0 "" "")))]
14061 ""
14062 "b %l0"
14063 [(set_attr "type" "branch")])
14064
14065 (define_insn "return"
14066 [(return)]
14067 "direct_return ()"
14068 "{br|blr}"
14069 [(set_attr "type" "jmpreg")])
14070
14071 (define_expand "indirect_jump"
14072 [(set (pc) (match_operand 0 "register_operand" ""))])
14073
14074 (define_insn "*indirect_jump<mode>"
14075 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14076 ""
14077 "@
14078 bctr
14079 {br|blr}"
14080 [(set_attr "type" "jmpreg")])
14081
14082 ;; Table jump for switch statements:
14083 (define_expand "tablejump"
14084 [(use (match_operand 0 "" ""))
14085 (use (label_ref (match_operand 1 "" "")))]
14086 ""
14087 "
14088 {
14089 if (TARGET_32BIT)
14090 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14091 else
14092 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14093 DONE;
14094 }")
14095
14096 (define_expand "tablejumpsi"
14097 [(set (match_dup 3)
14098 (plus:SI (match_operand:SI 0 "" "")
14099 (match_dup 2)))
14100 (parallel [(set (pc) (match_dup 3))
14101 (use (label_ref (match_operand 1 "" "")))])]
14102 "TARGET_32BIT"
14103 "
14104 { operands[0] = force_reg (SImode, operands[0]);
14105 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
14106 operands[3] = gen_reg_rtx (SImode);
14107 }")
14108
14109 (define_expand "tablejumpdi"
14110 [(set (match_dup 4)
14111 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
14112 (set (match_dup 3)
14113 (plus:DI (match_dup 4)
14114 (match_dup 2)))
14115 (parallel [(set (pc) (match_dup 3))
14116 (use (label_ref (match_operand 1 "" "")))])]
14117 "TARGET_64BIT"
14118 "
14119 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
14120 operands[3] = gen_reg_rtx (DImode);
14121 operands[4] = gen_reg_rtx (DImode);
14122 }")
14123
14124 (define_insn "*tablejump<mode>_internal1"
14125 [(set (pc)
14126 (match_operand:P 0 "register_operand" "c,*l"))
14127 (use (label_ref (match_operand 1 "" "")))]
14128 ""
14129 "@
14130 bctr
14131 {br|blr}"
14132 [(set_attr "type" "jmpreg")])
14133
14134 (define_insn "nop"
14135 [(const_int 0)]
14136 ""
14137 "{cror 0,0,0|nop}")
14138 \f
14139 ;; Define the subtract-one-and-jump insns, starting with the template
14140 ;; so loop.c knows what to generate.
14141
14142 (define_expand "doloop_end"
14143 [(use (match_operand 0 "" "")) ; loop pseudo
14144 (use (match_operand 1 "" "")) ; iterations; zero if unknown
14145 (use (match_operand 2 "" "")) ; max iterations
14146 (use (match_operand 3 "" "")) ; loop level
14147 (use (match_operand 4 "" ""))] ; label
14148 ""
14149 "
14150 {
14151 /* Only use this on innermost loops. */
14152 if (INTVAL (operands[3]) > 1)
14153 FAIL;
14154 if (TARGET_64BIT)
14155 {
14156 if (GET_MODE (operands[0]) != DImode)
14157 FAIL;
14158 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
14159 }
14160 else
14161 {
14162 if (GET_MODE (operands[0]) != SImode)
14163 FAIL;
14164 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
14165 }
14166 DONE;
14167 }")
14168
14169 (define_expand "ctr<mode>"
14170 [(parallel [(set (pc)
14171 (if_then_else (ne (match_operand:P 0 "register_operand" "")
14172 (const_int 1))
14173 (label_ref (match_operand 1 "" ""))
14174 (pc)))
14175 (set (match_dup 0)
14176 (plus:P (match_dup 0)
14177 (const_int -1)))
14178 (clobber (match_scratch:CC 2 ""))
14179 (clobber (match_scratch:P 3 ""))])]
14180 ""
14181 "")
14182
14183 ;; We need to be able to do this for any operand, including MEM, or we
14184 ;; will cause reload to blow up since we don't allow output reloads on
14185 ;; JUMP_INSNs.
14186 ;; For the length attribute to be calculated correctly, the
14187 ;; label MUST be operand 0.
14188
14189 (define_insn "*ctr<mode>_internal1"
14190 [(set (pc)
14191 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14192 (const_int 1))
14193 (label_ref (match_operand 0 "" ""))
14194 (pc)))
14195 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14196 (plus:P (match_dup 1)
14197 (const_int -1)))
14198 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14199 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14200 ""
14201 "*
14202 {
14203 if (which_alternative != 0)
14204 return \"#\";
14205 else if (get_attr_length (insn) == 4)
14206 return \"{bdn|bdnz} %l0\";
14207 else
14208 return \"bdz $+8\;b %l0\";
14209 }"
14210 [(set_attr "type" "branch")
14211 (set_attr "length" "*,12,16,16")])
14212
14213 (define_insn "*ctr<mode>_internal2"
14214 [(set (pc)
14215 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14216 (const_int 1))
14217 (pc)
14218 (label_ref (match_operand 0 "" ""))))
14219 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14220 (plus:P (match_dup 1)
14221 (const_int -1)))
14222 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14223 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14224 ""
14225 "*
14226 {
14227 if (which_alternative != 0)
14228 return \"#\";
14229 else if (get_attr_length (insn) == 4)
14230 return \"bdz %l0\";
14231 else
14232 return \"{bdn|bdnz} $+8\;b %l0\";
14233 }"
14234 [(set_attr "type" "branch")
14235 (set_attr "length" "*,12,16,16")])
14236
14237 ;; Similar but use EQ
14238
14239 (define_insn "*ctr<mode>_internal5"
14240 [(set (pc)
14241 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14242 (const_int 1))
14243 (label_ref (match_operand 0 "" ""))
14244 (pc)))
14245 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14246 (plus:P (match_dup 1)
14247 (const_int -1)))
14248 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14249 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14250 ""
14251 "*
14252 {
14253 if (which_alternative != 0)
14254 return \"#\";
14255 else if (get_attr_length (insn) == 4)
14256 return \"bdz %l0\";
14257 else
14258 return \"{bdn|bdnz} $+8\;b %l0\";
14259 }"
14260 [(set_attr "type" "branch")
14261 (set_attr "length" "*,12,16,16")])
14262
14263 (define_insn "*ctr<mode>_internal6"
14264 [(set (pc)
14265 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14266 (const_int 1))
14267 (pc)
14268 (label_ref (match_operand 0 "" ""))))
14269 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14270 (plus:P (match_dup 1)
14271 (const_int -1)))
14272 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14273 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14274 ""
14275 "*
14276 {
14277 if (which_alternative != 0)
14278 return \"#\";
14279 else if (get_attr_length (insn) == 4)
14280 return \"{bdn|bdnz} %l0\";
14281 else
14282 return \"bdz $+8\;b %l0\";
14283 }"
14284 [(set_attr "type" "branch")
14285 (set_attr "length" "*,12,16,16")])
14286
14287 ;; Now the splitters if we could not allocate the CTR register
14288
14289 (define_split
14290 [(set (pc)
14291 (if_then_else (match_operator 2 "comparison_operator"
14292 [(match_operand:P 1 "gpc_reg_operand" "")
14293 (const_int 1)])
14294 (match_operand 5 "" "")
14295 (match_operand 6 "" "")))
14296 (set (match_operand:P 0 "gpc_reg_operand" "")
14297 (plus:P (match_dup 1) (const_int -1)))
14298 (clobber (match_scratch:CC 3 ""))
14299 (clobber (match_scratch:P 4 ""))]
14300 "reload_completed"
14301 [(parallel [(set (match_dup 3)
14302 (compare:CC (plus:P (match_dup 1)
14303 (const_int -1))
14304 (const_int 0)))
14305 (set (match_dup 0)
14306 (plus:P (match_dup 1)
14307 (const_int -1)))])
14308 (set (pc) (if_then_else (match_dup 7)
14309 (match_dup 5)
14310 (match_dup 6)))]
14311 "
14312 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14313 operands[3], const0_rtx); }")
14314
14315 (define_split
14316 [(set (pc)
14317 (if_then_else (match_operator 2 "comparison_operator"
14318 [(match_operand:P 1 "gpc_reg_operand" "")
14319 (const_int 1)])
14320 (match_operand 5 "" "")
14321 (match_operand 6 "" "")))
14322 (set (match_operand:P 0 "nonimmediate_operand" "")
14323 (plus:P (match_dup 1) (const_int -1)))
14324 (clobber (match_scratch:CC 3 ""))
14325 (clobber (match_scratch:P 4 ""))]
14326 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
14327 [(parallel [(set (match_dup 3)
14328 (compare:CC (plus:P (match_dup 1)
14329 (const_int -1))
14330 (const_int 0)))
14331 (set (match_dup 4)
14332 (plus:P (match_dup 1)
14333 (const_int -1)))])
14334 (set (match_dup 0)
14335 (match_dup 4))
14336 (set (pc) (if_then_else (match_dup 7)
14337 (match_dup 5)
14338 (match_dup 6)))]
14339 "
14340 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14341 operands[3], const0_rtx); }")
14342 \f
14343 (define_insn "trap"
14344 [(trap_if (const_int 1) (const_int 0))]
14345 ""
14346 "{t 31,0,0|trap}"
14347 [(set_attr "type" "trap")])
14348
14349 (define_expand "conditional_trap"
14350 [(trap_if (match_operator 0 "trap_comparison_operator"
14351 [(match_dup 2) (match_dup 3)])
14352 (match_operand 1 "const_int_operand" ""))]
14353 ""
14354 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14355 operands[2] = rs6000_compare_op0;
14356 operands[3] = rs6000_compare_op1;")
14357
14358 (define_insn ""
14359 [(trap_if (match_operator 0 "trap_comparison_operator"
14360 [(match_operand:GPR 1 "register_operand" "r")
14361 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
14362 (const_int 0))]
14363 ""
14364 "{t|t<wd>}%V0%I2 %1,%2"
14365 [(set_attr "type" "trap")])
14366 \f
14367 ;; Insns related to generating the function prologue and epilogue.
14368
14369 (define_expand "prologue"
14370 [(use (const_int 0))]
14371 "TARGET_SCHED_PROLOG"
14372 "
14373 {
14374 rs6000_emit_prologue ();
14375 DONE;
14376 }")
14377
14378 (define_insn "*movesi_from_cr_one"
14379 [(match_parallel 0 "mfcr_operation"
14380 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14381 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14382 (match_operand 3 "immediate_operand" "n")]
14383 UNSPEC_MOVESI_FROM_CR))])]
14384 "TARGET_MFCRF"
14385 "*
14386 {
14387 int mask = 0;
14388 int i;
14389 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14390 {
14391 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14392 operands[4] = GEN_INT (mask);
14393 output_asm_insn (\"mfcr %1,%4\", operands);
14394 }
14395 return \"\";
14396 }"
14397 [(set_attr "type" "mfcrf")])
14398
14399 (define_insn "movesi_from_cr"
14400 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14401 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
14402 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
14403 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
14404 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
14405 UNSPEC_MOVESI_FROM_CR))]
14406 ""
14407 "mfcr %0"
14408 [(set_attr "type" "mfcr")])
14409
14410 (define_insn "*stmw"
14411 [(match_parallel 0 "stmw_operation"
14412 [(set (match_operand:SI 1 "memory_operand" "=m")
14413 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14414 "TARGET_MULTIPLE"
14415 "{stm|stmw} %2,%1"
14416 [(set_attr "type" "store_ux")])
14417
14418 (define_insn "*save_fpregs_<mode>"
14419 [(match_parallel 0 "any_parallel_operand"
14420 [(clobber (reg:P 65))
14421 (use (match_operand:P 1 "call_operand" "s"))
14422 (set (match_operand:DF 2 "memory_operand" "=m")
14423 (match_operand:DF 3 "gpc_reg_operand" "f"))])]
14424 ""
14425 "bl %z1"
14426 [(set_attr "type" "branch")
14427 (set_attr "length" "4")])
14428
14429 ; These are to explain that changes to the stack pointer should
14430 ; not be moved over stores to stack memory.
14431 (define_insn "stack_tie"
14432 [(set (match_operand:BLK 0 "memory_operand" "+m")
14433 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
14434 ""
14435 ""
14436 [(set_attr "length" "0")])
14437
14438
14439 (define_expand "epilogue"
14440 [(use (const_int 0))]
14441 "TARGET_SCHED_PROLOG"
14442 "
14443 {
14444 rs6000_emit_epilogue (FALSE);
14445 DONE;
14446 }")
14447
14448 ; On some processors, doing the mtcrf one CC register at a time is
14449 ; faster (like on the 604e). On others, doing them all at once is
14450 ; faster; for instance, on the 601 and 750.
14451
14452 (define_expand "movsi_to_cr_one"
14453 [(set (match_operand:CC 0 "cc_reg_operand" "")
14454 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
14455 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14456 ""
14457 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14458
14459 (define_insn "*movsi_to_cr"
14460 [(match_parallel 0 "mtcrf_operation"
14461 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14462 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14463 (match_operand 3 "immediate_operand" "n")]
14464 UNSPEC_MOVESI_TO_CR))])]
14465 ""
14466 "*
14467 {
14468 int mask = 0;
14469 int i;
14470 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14471 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14472 operands[4] = GEN_INT (mask);
14473 return \"mtcrf %4,%2\";
14474 }"
14475 [(set_attr "type" "mtcr")])
14476
14477 (define_insn "*mtcrfsi"
14478 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14479 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14480 (match_operand 2 "immediate_operand" "n")]
14481 UNSPEC_MOVESI_TO_CR))]
14482 "GET_CODE (operands[0]) == REG
14483 && CR_REGNO_P (REGNO (operands[0]))
14484 && GET_CODE (operands[2]) == CONST_INT
14485 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14486 "mtcrf %R0,%1"
14487 [(set_attr "type" "mtcr")])
14488
14489 ; The load-multiple instructions have similar properties.
14490 ; Note that "load_multiple" is a name known to the machine-independent
14491 ; code that actually corresponds to the PowerPC load-string.
14492
14493 (define_insn "*lmw"
14494 [(match_parallel 0 "lmw_operation"
14495 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14496 (match_operand:SI 2 "memory_operand" "m"))])]
14497 "TARGET_MULTIPLE"
14498 "{lm|lmw} %1,%2"
14499 [(set_attr "type" "load_ux")])
14500
14501 (define_insn "*return_internal_<mode>"
14502 [(return)
14503 (use (match_operand:P 0 "register_operand" "lc"))]
14504 ""
14505 "b%T0"
14506 [(set_attr "type" "jmpreg")])
14507
14508 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14509 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14510
14511 (define_insn "*return_and_restore_fpregs_<mode>"
14512 [(match_parallel 0 "any_parallel_operand"
14513 [(return)
14514 (use (reg:P 65))
14515 (use (match_operand:P 1 "call_operand" "s"))
14516 (set (match_operand:DF 2 "gpc_reg_operand" "=f")
14517 (match_operand:DF 3 "memory_operand" "m"))])]
14518 ""
14519 "b %z1")
14520
14521 ; This is used in compiling the unwind routines.
14522 (define_expand "eh_return"
14523 [(use (match_operand 0 "general_operand" ""))]
14524 ""
14525 "
14526 {
14527 if (TARGET_32BIT)
14528 emit_insn (gen_eh_set_lr_si (operands[0]));
14529 else
14530 emit_insn (gen_eh_set_lr_di (operands[0]));
14531 DONE;
14532 }")
14533
14534 ; We can't expand this before we know where the link register is stored.
14535 (define_insn "eh_set_lr_<mode>"
14536 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
14537 UNSPECV_EH_RR)
14538 (clobber (match_scratch:P 1 "=&b"))]
14539 ""
14540 "#")
14541
14542 (define_split
14543 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14544 (clobber (match_scratch 1 ""))]
14545 "reload_completed"
14546 [(const_int 0)]
14547 "
14548 {
14549 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14550 DONE;
14551 }")
14552
14553 (define_insn "prefetch"
14554 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
14555 (match_operand:SI 1 "const_int_operand" "n")
14556 (match_operand:SI 2 "const_int_operand" "n"))]
14557 "TARGET_POWERPC"
14558 "*
14559 {
14560 if (GET_CODE (operands[0]) == REG)
14561 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14562 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14563 }"
14564 [(set_attr "type" "load")])
14565 \f
14566
14567 (include "sync.md")
14568 (include "altivec.md")
14569 (include "spe.md")
14570 (include "dfp.md")
Mirror of https://gcc.gnu.org/git/gcc.git