1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 3, or (at your
12 ;; option) any later version.
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
43 (FIRST_ALTIVEC_REGNO 77)
44 (LAST_ALTIVEC_REGNO 108)
57 [(UNSPEC_FRSP 0) ; frsp for POWER machines
58 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
59 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
60 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
62 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
68 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
69 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
72 (UNSPEC_MOVESI_FROM_CR 19)
73 (UNSPEC_MOVESI_TO_CR 20)
75 (UNSPEC_TLSDTPRELHA 22)
76 (UNSPEC_TLSDTPRELLO 23)
77 (UNSPEC_TLSGOTDTPREL 24)
79 (UNSPEC_TLSTPRELHA 26)
80 (UNSPEC_TLSTPRELLO 27)
81 (UNSPEC_TLSGOTTPREL 28)
83 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
84 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
100 (UNSPEC_DLMZB_STRLEN 47)
105 ;; UNSPEC_VOLATILE usage
110 (UNSPECV_LL 1) ; load-locked
111 (UNSPECV_SC 2) ; store-conditional
112 (UNSPECV_EH_RR 9) ; eh_reg_restore
115 ;; Define an insn type attribute. This is used in function unit delay
117 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr"
118 (const_string "integer"))
120 ;; Length (in bytes).
121 ; '(pc)' in the following doesn't include the instruction itself; it is
122 ; calculated as if the instruction had zero size.
123 (define_attr "length" ""
124 (if_then_else (eq_attr "type" "branch")
125 (if_then_else (and (ge (minus (match_dup 0) (pc))
127 (lt (minus (match_dup 0) (pc))
133 ;; Processor type -- this attribute must exactly match the processor_type
134 ;; enumeration in rs6000.h.
136 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,power4,power5,power6,cell"
137 (const (symbol_ref "rs6000_cpu_attr")))
140 ;; If this instruction is microcoded on the CELL processor
141 ; The default for load and stores is conditional
142 ; The default for load extended and the recorded instructions is always microcoded
143 (define_attr "cell_micro" "not,conditional,always"
144 (if_then_else (ior (ior (eq_attr "type" "load")
145 (eq_attr "type" "store"))
146 (ior (eq_attr "type" "fpload")
147 (eq_attr "type" "fpstore")))
148 (const_string "conditional")
149 (if_then_else (ior (eq_attr "type" "load_ext")
150 (ior (eq_attr "type" "compare")
151 (eq_attr "type" "delayed_compare")))
152 (const_string "always")
153 (const_string "not"))))
156 (automata_option "ndfa")
169 (include "e300c2c3.md")
170 (include "power4.md")
171 (include "power5.md")
172 (include "power6.md")
175 (include "predicates.md")
176 (include "constraints.md")
178 (include "darwin.md")
183 ; This mode iterator allows :GPR to be used to indicate the allowable size
184 ; of whole values in GPRs.
185 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
187 ; Any supported integer mode.
188 (define_mode_iterator INT [QI HI SI DI TI])
190 ; Any supported integer mode that fits in one register.
191 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
193 ; extend modes for DImode
194 (define_mode_iterator QHSI [QI HI SI])
196 ; SImode or DImode, even if DImode doesn't fit in GPRs.
197 (define_mode_iterator SDI [SI DI])
199 ; The size of a pointer. Also, the size of the value that a record-condition
200 ; (one with a '.') will compare.
201 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
203 ; Any hardware-supported floating-point mode
204 (define_mode_iterator FP [(SF "TARGET_HARD_FLOAT")
205 (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
206 (TF "!TARGET_IEEEQUAD
208 && (TARGET_FPRS || TARGET_E500_DOUBLE)
209 && TARGET_LONG_DOUBLE_128")
213 ; Various instructions that come in SI and DI forms.
214 ; A generic w/d attribute, for things like cmpw/cmpd.
215 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
218 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
221 ;; Start with fixed-point load and store insns. Here we put only the more
222 ;; complex forms. Basic data transfer is done later.
224 (define_expand "zero_extend<mode>di2"
225 [(set (match_operand:DI 0 "gpc_reg_operand" "")
226 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
230 (define_insn "*zero_extend<mode>di2_internal1"
231 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
232 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
236 rldicl %0,%1,0,<dbits>"
237 [(set_attr "type" "load,*")])
239 (define_insn "*zero_extend<mode>di2_internal2"
240 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
241 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
243 (clobber (match_scratch:DI 2 "=r,r"))]
246 rldicl. %2,%1,0,<dbits>
248 [(set_attr "type" "compare")
249 (set_attr "length" "4,8")])
252 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
253 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
255 (clobber (match_scratch:DI 2 ""))]
256 "TARGET_POWERPC64 && reload_completed"
258 (zero_extend:DI (match_dup 1)))
260 (compare:CC (match_dup 2)
264 (define_insn "*zero_extend<mode>di2_internal3"
265 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
266 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
268 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
269 (zero_extend:DI (match_dup 1)))]
272 rldicl. %0,%1,0,<dbits>
274 [(set_attr "type" "compare")
275 (set_attr "length" "4,8")])
278 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
279 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
281 (set (match_operand:DI 0 "gpc_reg_operand" "")
282 (zero_extend:DI (match_dup 1)))]
283 "TARGET_POWERPC64 && reload_completed"
285 (zero_extend:DI (match_dup 1)))
287 (compare:CC (match_dup 0)
291 (define_insn "extendqidi2"
292 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
293 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
296 [(set_attr "type" "exts")])
299 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
300 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
302 (clobber (match_scratch:DI 2 "=r,r"))]
307 [(set_attr "type" "compare")
308 (set_attr "length" "4,8")])
311 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
312 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
314 (clobber (match_scratch:DI 2 ""))]
315 "TARGET_POWERPC64 && reload_completed"
317 (sign_extend:DI (match_dup 1)))
319 (compare:CC (match_dup 2)
324 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
325 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
327 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
328 (sign_extend:DI (match_dup 1)))]
333 [(set_attr "type" "compare")
334 (set_attr "length" "4,8")])
337 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
338 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
340 (set (match_operand:DI 0 "gpc_reg_operand" "")
341 (sign_extend:DI (match_dup 1)))]
342 "TARGET_POWERPC64 && reload_completed"
344 (sign_extend:DI (match_dup 1)))
346 (compare:CC (match_dup 0)
350 (define_expand "extendhidi2"
351 [(set (match_operand:DI 0 "gpc_reg_operand" "")
352 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
357 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
358 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
363 [(set_attr "type" "load_ext,exts")])
366 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
367 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
369 (clobber (match_scratch:DI 2 "=r,r"))]
374 [(set_attr "type" "compare")
375 (set_attr "length" "4,8")])
378 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
379 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
381 (clobber (match_scratch:DI 2 ""))]
382 "TARGET_POWERPC64 && reload_completed"
384 (sign_extend:DI (match_dup 1)))
386 (compare:CC (match_dup 2)
391 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
392 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
394 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
395 (sign_extend:DI (match_dup 1)))]
400 [(set_attr "type" "compare")
401 (set_attr "length" "4,8")])
404 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
405 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
407 (set (match_operand:DI 0 "gpc_reg_operand" "")
408 (sign_extend:DI (match_dup 1)))]
409 "TARGET_POWERPC64 && reload_completed"
411 (sign_extend:DI (match_dup 1)))
413 (compare:CC (match_dup 0)
417 (define_expand "extendsidi2"
418 [(set (match_operand:DI 0 "gpc_reg_operand" "")
419 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
424 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
425 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
430 [(set_attr "type" "load_ext,exts")])
433 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
434 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
436 (clobber (match_scratch:DI 2 "=r,r"))]
441 [(set_attr "type" "compare")
442 (set_attr "length" "4,8")])
445 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
446 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
448 (clobber (match_scratch:DI 2 ""))]
449 "TARGET_POWERPC64 && reload_completed"
451 (sign_extend:DI (match_dup 1)))
453 (compare:CC (match_dup 2)
458 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
459 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
461 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
462 (sign_extend:DI (match_dup 1)))]
467 [(set_attr "type" "compare")
468 (set_attr "length" "4,8")])
471 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
472 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
474 (set (match_operand:DI 0 "gpc_reg_operand" "")
475 (sign_extend:DI (match_dup 1)))]
476 "TARGET_POWERPC64 && reload_completed"
478 (sign_extend:DI (match_dup 1)))
480 (compare:CC (match_dup 0)
484 (define_expand "zero_extendqisi2"
485 [(set (match_operand:SI 0 "gpc_reg_operand" "")
486 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
491 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
492 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
496 {rlinm|rlwinm} %0,%1,0,0xff"
497 [(set_attr "type" "load,*")])
500 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
501 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
503 (clobber (match_scratch:SI 2 "=r,r"))]
506 {andil.|andi.} %2,%1,0xff
508 [(set_attr "type" "compare")
509 (set_attr "length" "4,8")])
512 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
513 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
515 (clobber (match_scratch:SI 2 ""))]
518 (zero_extend:SI (match_dup 1)))
520 (compare:CC (match_dup 2)
525 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
526 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
528 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
529 (zero_extend:SI (match_dup 1)))]
532 {andil.|andi.} %0,%1,0xff
534 [(set_attr "type" "compare")
535 (set_attr "length" "4,8")])
538 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
539 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
541 (set (match_operand:SI 0 "gpc_reg_operand" "")
542 (zero_extend:SI (match_dup 1)))]
545 (zero_extend:SI (match_dup 1)))
547 (compare:CC (match_dup 0)
551 (define_expand "extendqisi2"
552 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
553 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
558 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
559 else if (TARGET_POWER)
560 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
562 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
566 (define_insn "extendqisi2_ppc"
567 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
568 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
571 [(set_attr "type" "exts")])
574 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
575 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
577 (clobber (match_scratch:SI 2 "=r,r"))]
582 [(set_attr "type" "compare")
583 (set_attr "length" "4,8")])
586 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
587 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
589 (clobber (match_scratch:SI 2 ""))]
590 "TARGET_POWERPC && reload_completed"
592 (sign_extend:SI (match_dup 1)))
594 (compare:CC (match_dup 2)
599 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
600 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
602 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
603 (sign_extend:SI (match_dup 1)))]
608 [(set_attr "type" "compare")
609 (set_attr "length" "4,8")])
612 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
613 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
615 (set (match_operand:SI 0 "gpc_reg_operand" "")
616 (sign_extend:SI (match_dup 1)))]
617 "TARGET_POWERPC && reload_completed"
619 (sign_extend:SI (match_dup 1)))
621 (compare:CC (match_dup 0)
625 (define_expand "extendqisi2_power"
626 [(parallel [(set (match_dup 2)
627 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
629 (clobber (scratch:SI))])
630 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
631 (ashiftrt:SI (match_dup 2)
633 (clobber (scratch:SI))])]
636 { operands[1] = gen_lowpart (SImode, operands[1]);
637 operands[2] = gen_reg_rtx (SImode); }")
639 (define_expand "extendqisi2_no_power"
641 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
643 (set (match_operand:SI 0 "gpc_reg_operand" "")
644 (ashiftrt:SI (match_dup 2)
646 "! TARGET_POWER && ! TARGET_POWERPC"
648 { operands[1] = gen_lowpart (SImode, operands[1]);
649 operands[2] = gen_reg_rtx (SImode); }")
651 (define_expand "zero_extendqihi2"
652 [(set (match_operand:HI 0 "gpc_reg_operand" "")
653 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
658 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
659 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
663 {rlinm|rlwinm} %0,%1,0,0xff"
664 [(set_attr "type" "load,*")])
667 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
668 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
670 (clobber (match_scratch:HI 2 "=r,r"))]
673 {andil.|andi.} %2,%1,0xff
675 [(set_attr "type" "compare")
676 (set_attr "length" "4,8")])
679 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
680 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
682 (clobber (match_scratch:HI 2 ""))]
685 (zero_extend:HI (match_dup 1)))
687 (compare:CC (match_dup 2)
692 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
693 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
695 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
696 (zero_extend:HI (match_dup 1)))]
699 {andil.|andi.} %0,%1,0xff
701 [(set_attr "type" "compare")
702 (set_attr "length" "4,8")])
705 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
706 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
708 (set (match_operand:HI 0 "gpc_reg_operand" "")
709 (zero_extend:HI (match_dup 1)))]
712 (zero_extend:HI (match_dup 1)))
714 (compare:CC (match_dup 0)
718 (define_expand "extendqihi2"
719 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
720 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
725 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
726 else if (TARGET_POWER)
727 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
729 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
733 (define_insn "extendqihi2_ppc"
734 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
735 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
738 [(set_attr "type" "exts")])
741 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
742 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
744 (clobber (match_scratch:HI 2 "=r,r"))]
749 [(set_attr "type" "compare")
750 (set_attr "length" "4,8")])
753 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
754 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
756 (clobber (match_scratch:HI 2 ""))]
757 "TARGET_POWERPC && reload_completed"
759 (sign_extend:HI (match_dup 1)))
761 (compare:CC (match_dup 2)
766 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
767 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
769 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
770 (sign_extend:HI (match_dup 1)))]
775 [(set_attr "type" "compare")
776 (set_attr "length" "4,8")])
779 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
780 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
782 (set (match_operand:HI 0 "gpc_reg_operand" "")
783 (sign_extend:HI (match_dup 1)))]
784 "TARGET_POWERPC && reload_completed"
786 (sign_extend:HI (match_dup 1)))
788 (compare:CC (match_dup 0)
792 (define_expand "extendqihi2_power"
793 [(parallel [(set (match_dup 2)
794 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
796 (clobber (scratch:SI))])
797 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
798 (ashiftrt:SI (match_dup 2)
800 (clobber (scratch:SI))])]
803 { operands[0] = gen_lowpart (SImode, operands[0]);
804 operands[1] = gen_lowpart (SImode, operands[1]);
805 operands[2] = gen_reg_rtx (SImode); }")
807 (define_expand "extendqihi2_no_power"
809 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
811 (set (match_operand:HI 0 "gpc_reg_operand" "")
812 (ashiftrt:SI (match_dup 2)
814 "! TARGET_POWER && ! TARGET_POWERPC"
816 { operands[0] = gen_lowpart (SImode, operands[0]);
817 operands[1] = gen_lowpart (SImode, operands[1]);
818 operands[2] = gen_reg_rtx (SImode); }")
820 (define_expand "zero_extendhisi2"
821 [(set (match_operand:SI 0 "gpc_reg_operand" "")
822 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
827 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
828 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
832 {rlinm|rlwinm} %0,%1,0,0xffff"
833 [(set_attr "type" "load,*")])
836 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
837 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
839 (clobber (match_scratch:SI 2 "=r,r"))]
842 {andil.|andi.} %2,%1,0xffff
844 [(set_attr "type" "compare")
845 (set_attr "length" "4,8")])
848 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
849 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
851 (clobber (match_scratch:SI 2 ""))]
854 (zero_extend:SI (match_dup 1)))
856 (compare:CC (match_dup 2)
861 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
862 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
864 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
865 (zero_extend:SI (match_dup 1)))]
868 {andil.|andi.} %0,%1,0xffff
870 [(set_attr "type" "compare")
871 (set_attr "length" "4,8")])
874 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
875 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
877 (set (match_operand:SI 0 "gpc_reg_operand" "")
878 (zero_extend:SI (match_dup 1)))]
881 (zero_extend:SI (match_dup 1)))
883 (compare:CC (match_dup 0)
887 (define_expand "extendhisi2"
888 [(set (match_operand:SI 0 "gpc_reg_operand" "")
889 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
894 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
895 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
900 [(set_attr "type" "load_ext,exts")])
903 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
904 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
906 (clobber (match_scratch:SI 2 "=r,r"))]
911 [(set_attr "type" "compare")
912 (set_attr "length" "4,8")])
915 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
916 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
918 (clobber (match_scratch:SI 2 ""))]
921 (sign_extend:SI (match_dup 1)))
923 (compare:CC (match_dup 2)
928 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
929 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
931 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
932 (sign_extend:SI (match_dup 1)))]
937 [(set_attr "type" "compare")
938 (set_attr "length" "4,8")])
940 ;; IBM 405, 440 and 464 half-word multiplication operations.
942 (define_insn "*macchwc"
943 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
944 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
945 (match_operand:SI 2 "gpc_reg_operand" "r")
948 (match_operand:HI 1 "gpc_reg_operand" "r")))
949 (match_operand:SI 4 "gpc_reg_operand" "0"))
951 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
952 (plus:SI (mult:SI (ashiftrt:SI
960 [(set_attr "type" "imul3")])
962 (define_insn "*macchw"
963 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
964 (plus:SI (mult:SI (ashiftrt:SI
965 (match_operand:SI 2 "gpc_reg_operand" "r")
968 (match_operand:HI 1 "gpc_reg_operand" "r")))
969 (match_operand:SI 3 "gpc_reg_operand" "0")))]
972 [(set_attr "type" "imul3")])
974 (define_insn "*macchwuc"
975 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
976 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
977 (match_operand:SI 2 "gpc_reg_operand" "r")
980 (match_operand:HI 1 "gpc_reg_operand" "r")))
981 (match_operand:SI 4 "gpc_reg_operand" "0"))
983 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
984 (plus:SI (mult:SI (lshiftrt:SI
991 "macchwu. %0, %1, %2"
992 [(set_attr "type" "imul3")])
994 (define_insn "*macchwu"
995 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
996 (plus:SI (mult:SI (lshiftrt:SI
997 (match_operand:SI 2 "gpc_reg_operand" "r")
1000 (match_operand:HI 1 "gpc_reg_operand" "r")))
1001 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1003 "macchwu %0, %1, %2"
1004 [(set_attr "type" "imul3")])
1006 (define_insn "*machhwc"
1007 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1008 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1009 (match_operand:SI 1 "gpc_reg_operand" "%r")
1012 (match_operand:SI 2 "gpc_reg_operand" "r")
1014 (match_operand:SI 4 "gpc_reg_operand" "0"))
1016 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1017 (plus:SI (mult:SI (ashiftrt:SI
1025 "machhw. %0, %1, %2"
1026 [(set_attr "type" "imul3")])
1028 (define_insn "*machhw"
1029 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1030 (plus:SI (mult:SI (ashiftrt:SI
1031 (match_operand:SI 1 "gpc_reg_operand" "%r")
1034 (match_operand:SI 2 "gpc_reg_operand" "r")
1036 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1039 [(set_attr "type" "imul3")])
1041 (define_insn "*machhwuc"
1042 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1043 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1044 (match_operand:SI 1 "gpc_reg_operand" "%r")
1047 (match_operand:SI 2 "gpc_reg_operand" "r")
1049 (match_operand:SI 4 "gpc_reg_operand" "0"))
1051 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1052 (plus:SI (mult:SI (lshiftrt:SI
1060 "machhwu. %0, %1, %2"
1061 [(set_attr "type" "imul3")])
1063 (define_insn "*machhwu"
1064 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1065 (plus:SI (mult:SI (lshiftrt:SI
1066 (match_operand:SI 1 "gpc_reg_operand" "%r")
1069 (match_operand:SI 2 "gpc_reg_operand" "r")
1071 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1073 "machhwu %0, %1, %2"
1074 [(set_attr "type" "imul3")])
1076 (define_insn "*maclhwc"
1077 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1078 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1079 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1081 (match_operand:HI 2 "gpc_reg_operand" "r")))
1082 (match_operand:SI 4 "gpc_reg_operand" "0"))
1084 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1085 (plus:SI (mult:SI (sign_extend:SI
1091 "maclhw. %0, %1, %2"
1092 [(set_attr "type" "imul3")])
1094 (define_insn "*maclhw"
1095 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1096 (plus:SI (mult:SI (sign_extend:SI
1097 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1099 (match_operand:HI 2 "gpc_reg_operand" "r")))
1100 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1103 [(set_attr "type" "imul3")])
1105 (define_insn "*maclhwuc"
1106 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1107 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1108 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1110 (match_operand:HI 2 "gpc_reg_operand" "r")))
1111 (match_operand:SI 4 "gpc_reg_operand" "0"))
1113 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1114 (plus:SI (mult:SI (zero_extend:SI
1120 "maclhwu. %0, %1, %2"
1121 [(set_attr "type" "imul3")])
1123 (define_insn "*maclhwu"
1124 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1125 (plus:SI (mult:SI (zero_extend:SI
1126 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1128 (match_operand:HI 2 "gpc_reg_operand" "r")))
1129 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1131 "maclhwu %0, %1, %2"
1132 [(set_attr "type" "imul3")])
1134 (define_insn "*nmacchwc"
1135 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1136 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1137 (mult:SI (ashiftrt:SI
1138 (match_operand:SI 2 "gpc_reg_operand" "r")
1141 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1143 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1144 (minus:SI (match_dup 4)
1145 (mult:SI (ashiftrt:SI
1151 "nmacchw. %0, %1, %2"
1152 [(set_attr "type" "imul3")])
1154 (define_insn "*nmacchw"
1155 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1156 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1157 (mult:SI (ashiftrt:SI
1158 (match_operand:SI 2 "gpc_reg_operand" "r")
1161 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1163 "nmacchw %0, %1, %2"
1164 [(set_attr "type" "imul3")])
1166 (define_insn "*nmachhwc"
1167 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1168 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1169 (mult:SI (ashiftrt:SI
1170 (match_operand:SI 1 "gpc_reg_operand" "%r")
1173 (match_operand:SI 2 "gpc_reg_operand" "r")
1176 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1177 (minus:SI (match_dup 4)
1178 (mult:SI (ashiftrt:SI
1185 "nmachhw. %0, %1, %2"
1186 [(set_attr "type" "imul3")])
1188 (define_insn "*nmachhw"
1189 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1190 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1191 (mult:SI (ashiftrt:SI
1192 (match_operand:SI 1 "gpc_reg_operand" "%r")
1195 (match_operand:SI 2 "gpc_reg_operand" "r")
1198 "nmachhw %0, %1, %2"
1199 [(set_attr "type" "imul3")])
1201 (define_insn "*nmaclhwc"
1202 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1203 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1204 (mult:SI (sign_extend:SI
1205 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1207 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1209 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1210 (minus:SI (match_dup 4)
1211 (mult:SI (sign_extend:SI
1216 "nmaclhw. %0, %1, %2"
1217 [(set_attr "type" "imul3")])
1219 (define_insn "*nmaclhw"
1220 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1221 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1222 (mult:SI (sign_extend:SI
1223 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1225 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1227 "nmaclhw %0, %1, %2"
1228 [(set_attr "type" "imul3")])
1230 (define_insn "*mulchwc"
1231 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1232 (compare:CC (mult:SI (ashiftrt:SI
1233 (match_operand:SI 2 "gpc_reg_operand" "r")
1236 (match_operand:HI 1 "gpc_reg_operand" "r")))
1238 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1239 (mult:SI (ashiftrt:SI
1245 "mulchw. %0, %1, %2"
1246 [(set_attr "type" "imul3")])
1248 (define_insn "*mulchw"
1249 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1250 (mult:SI (ashiftrt:SI
1251 (match_operand:SI 2 "gpc_reg_operand" "r")
1254 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1257 [(set_attr "type" "imul3")])
1259 (define_insn "*mulchwuc"
1260 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1261 (compare:CC (mult:SI (lshiftrt:SI
1262 (match_operand:SI 2 "gpc_reg_operand" "r")
1265 (match_operand:HI 1 "gpc_reg_operand" "r")))
1267 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1268 (mult:SI (lshiftrt:SI
1274 "mulchwu. %0, %1, %2"
1275 [(set_attr "type" "imul3")])
1277 (define_insn "*mulchwu"
1278 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1279 (mult:SI (lshiftrt:SI
1280 (match_operand:SI 2 "gpc_reg_operand" "r")
1283 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1285 "mulchwu %0, %1, %2"
1286 [(set_attr "type" "imul3")])
1288 (define_insn "*mulhhwc"
1289 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1290 (compare:CC (mult:SI (ashiftrt:SI
1291 (match_operand:SI 1 "gpc_reg_operand" "%r")
1294 (match_operand:SI 2 "gpc_reg_operand" "r")
1297 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1298 (mult:SI (ashiftrt:SI
1305 "mulhhw. %0, %1, %2"
1306 [(set_attr "type" "imul3")])
1308 (define_insn "*mulhhw"
1309 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1310 (mult:SI (ashiftrt:SI
1311 (match_operand:SI 1 "gpc_reg_operand" "%r")
1314 (match_operand:SI 2 "gpc_reg_operand" "r")
1318 [(set_attr "type" "imul3")])
1320 (define_insn "*mulhhwuc"
1321 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1322 (compare:CC (mult:SI (lshiftrt:SI
1323 (match_operand:SI 1 "gpc_reg_operand" "%r")
1326 (match_operand:SI 2 "gpc_reg_operand" "r")
1329 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1330 (mult:SI (lshiftrt:SI
1337 "mulhhwu. %0, %1, %2"
1338 [(set_attr "type" "imul3")])
1340 (define_insn "*mulhhwu"
1341 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1342 (mult:SI (lshiftrt:SI
1343 (match_operand:SI 1 "gpc_reg_operand" "%r")
1346 (match_operand:SI 2 "gpc_reg_operand" "r")
1349 "mulhhwu %0, %1, %2"
1350 [(set_attr "type" "imul3")])
1352 (define_insn "*mullhwc"
1353 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1354 (compare:CC (mult:SI (sign_extend:SI
1355 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1357 (match_operand:HI 2 "gpc_reg_operand" "r")))
1359 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1360 (mult:SI (sign_extend:SI
1365 "mullhw. %0, %1, %2"
1366 [(set_attr "type" "imul3")])
1368 (define_insn "*mullhw"
1369 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1370 (mult:SI (sign_extend:SI
1371 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1373 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1376 [(set_attr "type" "imul3")])
1378 (define_insn "*mullhwuc"
1379 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1380 (compare:CC (mult:SI (zero_extend:SI
1381 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1383 (match_operand:HI 2 "gpc_reg_operand" "r")))
1385 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1386 (mult:SI (zero_extend:SI
1391 "mullhwu. %0, %1, %2"
1392 [(set_attr "type" "imul3")])
1394 (define_insn "*mullhwu"
1395 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1396 (mult:SI (zero_extend:SI
1397 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1399 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1401 "mullhwu %0, %1, %2"
1402 [(set_attr "type" "imul3")])
1404 ;; IBM 405, 440 and 464 string-search dlmzb instruction support.
1405 (define_insn "dlmzb"
1406 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1407 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1408 (match_operand:SI 2 "gpc_reg_operand" "r")]
1410 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1411 (unspec:SI [(match_dup 1)
1415 "dlmzb. %0, %1, %2")
1417 (define_expand "strlensi"
1418 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1419 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1420 (match_operand:QI 2 "const_int_operand" "")
1421 (match_operand 3 "const_int_operand" "")]
1422 UNSPEC_DLMZB_STRLEN))
1423 (clobber (match_scratch:CC 4 "=x"))]
1424 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1426 rtx result = operands[0];
1427 rtx src = operands[1];
1428 rtx search_char = operands[2];
1429 rtx align = operands[3];
1430 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1431 rtx loop_label, end_label, mem, cr0, cond;
1432 if (search_char != const0_rtx
1433 || GET_CODE (align) != CONST_INT
1434 || INTVAL (align) < 8)
1436 word1 = gen_reg_rtx (SImode);
1437 word2 = gen_reg_rtx (SImode);
1438 scratch_dlmzb = gen_reg_rtx (SImode);
1439 scratch_string = gen_reg_rtx (Pmode);
1440 loop_label = gen_label_rtx ();
1441 end_label = gen_label_rtx ();
1442 addr = force_reg (Pmode, XEXP (src, 0));
1443 emit_move_insn (scratch_string, addr);
1444 emit_label (loop_label);
1445 mem = change_address (src, SImode, scratch_string);
1446 emit_move_insn (word1, mem);
1447 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1448 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1449 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1450 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1451 emit_jump_insn (gen_rtx_SET (VOIDmode,
1453 gen_rtx_IF_THEN_ELSE (VOIDmode,
1459 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1460 emit_jump_insn (gen_rtx_SET (VOIDmode,
1462 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1464 emit_label (end_label);
1465 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1466 emit_insn (gen_subsi3 (result, scratch_string, addr));
1467 emit_insn (gen_subsi3 (result, result, const1_rtx));
1472 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1473 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1475 (set (match_operand:SI 0 "gpc_reg_operand" "")
1476 (sign_extend:SI (match_dup 1)))]
1479 (sign_extend:SI (match_dup 1)))
1481 (compare:CC (match_dup 0)
1485 ;; Fixed-point arithmetic insns.
1487 (define_expand "add<mode>3"
1488 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1489 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1490 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1493 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1495 if (non_short_cint_operand (operands[2], DImode))
1498 else if (GET_CODE (operands[2]) == CONST_INT
1499 && ! add_operand (operands[2], <MODE>mode))
1501 rtx tmp = ((!can_create_pseudo_p ()
1502 || rtx_equal_p (operands[0], operands[1]))
1503 ? operands[0] : gen_reg_rtx (<MODE>mode));
1505 HOST_WIDE_INT val = INTVAL (operands[2]);
1506 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1507 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1509 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1512 /* The ordering here is important for the prolog expander.
1513 When space is allocated from the stack, adding 'low' first may
1514 produce a temporary deallocation (which would be bad). */
1515 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1516 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1521 ;; Discourage ai/addic because of carry but provide it in an alternative
1522 ;; allowing register zero as source.
1523 (define_insn "*add<mode>3_internal1"
1524 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1525 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1526 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1527 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1530 {cal %0,%2(%1)|addi %0,%1,%2}
1532 {cau|addis} %0,%1,%v2"
1533 [(set_attr "length" "4,4,4,4")])
1535 (define_insn "addsi3_high"
1536 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1537 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1538 (high:SI (match_operand 2 "" ""))))]
1539 "TARGET_MACHO && !TARGET_64BIT"
1540 "{cau|addis} %0,%1,ha16(%2)"
1541 [(set_attr "length" "4")])
1543 (define_insn "*add<mode>3_internal2"
1544 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1545 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1546 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1548 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1551 {cax.|add.} %3,%1,%2
1552 {ai.|addic.} %3,%1,%2
1555 [(set_attr "type" "fast_compare,compare,compare,compare")
1556 (set_attr "length" "4,4,8,8")])
1559 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1560 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1561 (match_operand:GPR 2 "reg_or_short_operand" ""))
1563 (clobber (match_scratch:GPR 3 ""))]
1566 (plus:GPR (match_dup 1)
1569 (compare:CC (match_dup 3)
1573 (define_insn "*add<mode>3_internal3"
1574 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1575 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1576 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1578 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1579 (plus:P (match_dup 1)
1583 {cax.|add.} %0,%1,%2
1584 {ai.|addic.} %0,%1,%2
1587 [(set_attr "type" "fast_compare,compare,compare,compare")
1588 (set_attr "length" "4,4,8,8")])
1591 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1592 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1593 (match_operand:P 2 "reg_or_short_operand" ""))
1595 (set (match_operand:P 0 "gpc_reg_operand" "")
1596 (plus:P (match_dup 1) (match_dup 2)))]
1599 (plus:P (match_dup 1)
1602 (compare:CC (match_dup 0)
1606 ;; Split an add that we can't do in one insn into two insns, each of which
1607 ;; does one 16-bit part. This is used by combine. Note that the low-order
1608 ;; add should be last in case the result gets used in an address.
1611 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1612 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1613 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1615 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1616 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1618 HOST_WIDE_INT val = INTVAL (operands[2]);
1619 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1620 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1622 operands[4] = GEN_INT (low);
1623 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1624 operands[3] = GEN_INT (rest);
1625 else if (can_create_pseudo_p ())
1627 operands[3] = gen_reg_rtx (DImode);
1628 emit_move_insn (operands[3], operands[2]);
1629 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1636 (define_insn "one_cmpl<mode>2"
1637 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1638 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1643 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1644 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1646 (clobber (match_scratch:P 2 "=r,r"))]
1651 [(set_attr "type" "compare")
1652 (set_attr "length" "4,8")])
1655 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1656 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1658 (clobber (match_scratch:P 2 ""))]
1661 (not:P (match_dup 1)))
1663 (compare:CC (match_dup 2)
1668 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1669 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1671 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1672 (not:P (match_dup 1)))]
1677 [(set_attr "type" "compare")
1678 (set_attr "length" "4,8")])
1681 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1682 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1684 (set (match_operand:P 0 "gpc_reg_operand" "")
1685 (not:P (match_dup 1)))]
1688 (not:P (match_dup 1)))
1690 (compare:CC (match_dup 0)
1695 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1696 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1697 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1699 "{sf%I1|subf%I1c} %0,%2,%1")
1702 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1703 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1704 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1711 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1712 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1713 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1715 (clobber (match_scratch:SI 3 "=r,r"))]
1718 {sf.|subfc.} %3,%2,%1
1720 [(set_attr "type" "compare")
1721 (set_attr "length" "4,8")])
1724 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1725 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1726 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1728 (clobber (match_scratch:P 3 "=r,r"))]
1733 [(set_attr "type" "fast_compare")
1734 (set_attr "length" "4,8")])
1737 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1738 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1739 (match_operand:P 2 "gpc_reg_operand" ""))
1741 (clobber (match_scratch:P 3 ""))]
1744 (minus:P (match_dup 1)
1747 (compare:CC (match_dup 3)
1752 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1753 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1754 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1756 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1757 (minus:SI (match_dup 1) (match_dup 2)))]
1760 {sf.|subfc.} %0,%2,%1
1762 [(set_attr "type" "compare")
1763 (set_attr "length" "4,8")])
1766 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1767 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1768 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1770 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1771 (minus:P (match_dup 1)
1777 [(set_attr "type" "fast_compare")
1778 (set_attr "length" "4,8")])
1781 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1782 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1783 (match_operand:P 2 "gpc_reg_operand" ""))
1785 (set (match_operand:P 0 "gpc_reg_operand" "")
1786 (minus:P (match_dup 1)
1790 (minus:P (match_dup 1)
1793 (compare:CC (match_dup 0)
1797 (define_expand "sub<mode>3"
1798 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1799 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1800 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1804 if (GET_CODE (operands[2]) == CONST_INT)
1806 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1807 negate_rtx (<MODE>mode, operands[2])));
1812 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1813 ;; instruction and some auxiliary computations. Then we just have a single
1814 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1817 (define_expand "sminsi3"
1819 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1820 (match_operand:SI 2 "reg_or_short_operand" ""))
1822 (minus:SI (match_dup 2) (match_dup 1))))
1823 (set (match_operand:SI 0 "gpc_reg_operand" "")
1824 (minus:SI (match_dup 2) (match_dup 3)))]
1825 "TARGET_POWER || TARGET_ISEL"
1830 operands[2] = force_reg (SImode, operands[2]);
1831 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1835 operands[3] = gen_reg_rtx (SImode);
1839 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1840 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1841 (match_operand:SI 2 "reg_or_short_operand" "")))
1842 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1845 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1847 (minus:SI (match_dup 2) (match_dup 1))))
1848 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1851 (define_expand "smaxsi3"
1853 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1854 (match_operand:SI 2 "reg_or_short_operand" ""))
1856 (minus:SI (match_dup 2) (match_dup 1))))
1857 (set (match_operand:SI 0 "gpc_reg_operand" "")
1858 (plus:SI (match_dup 3) (match_dup 1)))]
1859 "TARGET_POWER || TARGET_ISEL"
1864 operands[2] = force_reg (SImode, operands[2]);
1865 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1868 operands[3] = gen_reg_rtx (SImode);
1872 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1873 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1874 (match_operand:SI 2 "reg_or_short_operand" "")))
1875 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1878 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1880 (minus:SI (match_dup 2) (match_dup 1))))
1881 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1884 (define_expand "uminsi3"
1885 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1887 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1889 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1891 (minus:SI (match_dup 4) (match_dup 3))))
1892 (set (match_operand:SI 0 "gpc_reg_operand" "")
1893 (minus:SI (match_dup 2) (match_dup 3)))]
1894 "TARGET_POWER || TARGET_ISEL"
1899 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1902 operands[3] = gen_reg_rtx (SImode);
1903 operands[4] = gen_reg_rtx (SImode);
1904 operands[5] = GEN_INT (-2147483647 - 1);
1907 (define_expand "umaxsi3"
1908 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1910 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1912 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1914 (minus:SI (match_dup 4) (match_dup 3))))
1915 (set (match_operand:SI 0 "gpc_reg_operand" "")
1916 (plus:SI (match_dup 3) (match_dup 1)))]
1917 "TARGET_POWER || TARGET_ISEL"
1922 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1925 operands[3] = gen_reg_rtx (SImode);
1926 operands[4] = gen_reg_rtx (SImode);
1927 operands[5] = GEN_INT (-2147483647 - 1);
1931 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1932 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1933 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1935 (minus:SI (match_dup 2) (match_dup 1))))]
1940 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1942 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1943 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1945 (minus:SI (match_dup 2) (match_dup 1)))
1947 (clobber (match_scratch:SI 3 "=r,r"))]
1952 [(set_attr "type" "delayed_compare")
1953 (set_attr "length" "4,8")])
1956 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1958 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1959 (match_operand:SI 2 "reg_or_short_operand" ""))
1961 (minus:SI (match_dup 2) (match_dup 1)))
1963 (clobber (match_scratch:SI 3 ""))]
1964 "TARGET_POWER && reload_completed"
1966 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1968 (minus:SI (match_dup 2) (match_dup 1))))
1970 (compare:CC (match_dup 3)
1975 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1977 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1978 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1980 (minus:SI (match_dup 2) (match_dup 1)))
1982 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1983 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1985 (minus:SI (match_dup 2) (match_dup 1))))]
1990 [(set_attr "type" "delayed_compare")
1991 (set_attr "length" "4,8")])
1994 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1996 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1997 (match_operand:SI 2 "reg_or_short_operand" ""))
1999 (minus:SI (match_dup 2) (match_dup 1)))
2001 (set (match_operand:SI 0 "gpc_reg_operand" "")
2002 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2004 (minus:SI (match_dup 2) (match_dup 1))))]
2005 "TARGET_POWER && reload_completed"
2007 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2009 (minus:SI (match_dup 2) (match_dup 1))))
2011 (compare:CC (match_dup 0)
2015 ;; We don't need abs with condition code because such comparisons should
2017 (define_expand "abssi2"
2018 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2019 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2025 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
2028 else if (! TARGET_POWER)
2030 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2035 (define_insn "*abssi2_power"
2036 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2037 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2041 (define_insn_and_split "abssi2_isel"
2042 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2043 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
2044 (clobber (match_scratch:SI 2 "=&b"))
2045 (clobber (match_scratch:CC 3 "=y"))]
2048 "&& reload_completed"
2049 [(set (match_dup 2) (neg:SI (match_dup 1)))
2051 (compare:CC (match_dup 1)
2054 (if_then_else:SI (ge (match_dup 3)
2060 (define_insn_and_split "abssi2_nopower"
2061 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2062 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2063 (clobber (match_scratch:SI 2 "=&r,&r"))]
2064 "! TARGET_POWER && ! TARGET_ISEL"
2066 "&& reload_completed"
2067 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2068 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2069 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2072 (define_insn "*nabs_power"
2073 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2074 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2078 (define_insn_and_split "*nabs_nopower"
2079 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2080 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2081 (clobber (match_scratch:SI 2 "=&r,&r"))]
2084 "&& reload_completed"
2085 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2086 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2087 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2090 (define_expand "neg<mode>2"
2091 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2092 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2096 (define_insn "*neg<mode>2_internal"
2097 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2098 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2103 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2104 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2106 (clobber (match_scratch:P 2 "=r,r"))]
2111 [(set_attr "type" "fast_compare")
2112 (set_attr "length" "4,8")])
2115 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2116 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2118 (clobber (match_scratch:P 2 ""))]
2121 (neg:P (match_dup 1)))
2123 (compare:CC (match_dup 2)
2128 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2129 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2131 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2132 (neg:P (match_dup 1)))]
2137 [(set_attr "type" "fast_compare")
2138 (set_attr "length" "4,8")])
2141 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2142 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2144 (set (match_operand:P 0 "gpc_reg_operand" "")
2145 (neg:P (match_dup 1)))]
2148 (neg:P (match_dup 1)))
2150 (compare:CC (match_dup 0)
2154 (define_insn "clz<mode>2"
2155 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2156 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2158 "{cntlz|cntlz<wd>} %0,%1"
2159 [(set_attr "type" "cntlz")])
2161 (define_expand "ctz<mode>2"
2163 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2164 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2166 (clobber (scratch:CC))])
2167 (set (match_dup 4) (clz:GPR (match_dup 3)))
2168 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2169 (minus:GPR (match_dup 5) (match_dup 4)))]
2172 operands[2] = gen_reg_rtx (<MODE>mode);
2173 operands[3] = gen_reg_rtx (<MODE>mode);
2174 operands[4] = gen_reg_rtx (<MODE>mode);
2175 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2178 (define_expand "ffs<mode>2"
2180 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2181 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2183 (clobber (scratch:CC))])
2184 (set (match_dup 4) (clz:GPR (match_dup 3)))
2185 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2186 (minus:GPR (match_dup 5) (match_dup 4)))]
2189 operands[2] = gen_reg_rtx (<MODE>mode);
2190 operands[3] = gen_reg_rtx (<MODE>mode);
2191 operands[4] = gen_reg_rtx (<MODE>mode);
2192 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2195 (define_insn "popcntb<mode>2"
2196 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2197 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2202 (define_expand "popcount<mode>2"
2203 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2204 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2207 rs6000_emit_popcount (operands[0], operands[1]);
2211 (define_expand "parity<mode>2"
2212 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2213 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2216 rs6000_emit_parity (operands[0], operands[1]);
2220 (define_insn "bswapsi2"
2221 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2222 (bswap:SI (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2226 {stbrx|stwbrx} %1,%y0
2228 [(set_attr "length" "4,4,12")])
2231 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2232 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2235 (rotate:SI (match_dup 1) (const_int 8)))
2236 (set (zero_extract:SI (match_dup 0)
2240 (set (zero_extract:SI (match_dup 0)
2243 (rotate:SI (match_dup 1)
2247 (define_expand "mulsi3"
2248 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2249 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2250 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2255 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2257 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2261 (define_insn "mulsi3_mq"
2262 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2263 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2264 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2265 (clobber (match_scratch:SI 3 "=q,q"))]
2268 {muls|mullw} %0,%1,%2
2269 {muli|mulli} %0,%1,%2"
2271 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2272 (const_string "imul3")
2273 (match_operand:SI 2 "short_cint_operand" "")
2274 (const_string "imul2")]
2275 (const_string "imul")))])
2277 (define_insn "mulsi3_no_mq"
2278 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2279 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2280 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2283 {muls|mullw} %0,%1,%2
2284 {muli|mulli} %0,%1,%2"
2286 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2287 (const_string "imul3")
2288 (match_operand:SI 2 "short_cint_operand" "")
2289 (const_string "imul2")]
2290 (const_string "imul")))])
2292 (define_insn "*mulsi3_mq_internal1"
2293 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2294 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2295 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2297 (clobber (match_scratch:SI 3 "=r,r"))
2298 (clobber (match_scratch:SI 4 "=q,q"))]
2301 {muls.|mullw.} %3,%1,%2
2303 [(set_attr "type" "imul_compare")
2304 (set_attr "length" "4,8")])
2307 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2308 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2309 (match_operand:SI 2 "gpc_reg_operand" ""))
2311 (clobber (match_scratch:SI 3 ""))
2312 (clobber (match_scratch:SI 4 ""))]
2313 "TARGET_POWER && reload_completed"
2314 [(parallel [(set (match_dup 3)
2315 (mult:SI (match_dup 1) (match_dup 2)))
2316 (clobber (match_dup 4))])
2318 (compare:CC (match_dup 3)
2322 (define_insn "*mulsi3_no_mq_internal1"
2323 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2324 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2325 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2327 (clobber (match_scratch:SI 3 "=r,r"))]
2330 {muls.|mullw.} %3,%1,%2
2332 [(set_attr "type" "imul_compare")
2333 (set_attr "length" "4,8")])
2336 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2337 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2338 (match_operand:SI 2 "gpc_reg_operand" ""))
2340 (clobber (match_scratch:SI 3 ""))]
2341 "! TARGET_POWER && reload_completed"
2343 (mult:SI (match_dup 1) (match_dup 2)))
2345 (compare:CC (match_dup 3)
2349 (define_insn "*mulsi3_mq_internal2"
2350 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2351 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2352 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2354 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2355 (mult:SI (match_dup 1) (match_dup 2)))
2356 (clobber (match_scratch:SI 4 "=q,q"))]
2359 {muls.|mullw.} %0,%1,%2
2361 [(set_attr "type" "imul_compare")
2362 (set_attr "length" "4,8")])
2365 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2366 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2367 (match_operand:SI 2 "gpc_reg_operand" ""))
2369 (set (match_operand:SI 0 "gpc_reg_operand" "")
2370 (mult:SI (match_dup 1) (match_dup 2)))
2371 (clobber (match_scratch:SI 4 ""))]
2372 "TARGET_POWER && reload_completed"
2373 [(parallel [(set (match_dup 0)
2374 (mult:SI (match_dup 1) (match_dup 2)))
2375 (clobber (match_dup 4))])
2377 (compare:CC (match_dup 0)
2381 (define_insn "*mulsi3_no_mq_internal2"
2382 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2383 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2384 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2386 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2387 (mult:SI (match_dup 1) (match_dup 2)))]
2390 {muls.|mullw.} %0,%1,%2
2392 [(set_attr "type" "imul_compare")
2393 (set_attr "length" "4,8")])
2396 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2397 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2398 (match_operand:SI 2 "gpc_reg_operand" ""))
2400 (set (match_operand:SI 0 "gpc_reg_operand" "")
2401 (mult:SI (match_dup 1) (match_dup 2)))]
2402 "! TARGET_POWER && reload_completed"
2404 (mult:SI (match_dup 1) (match_dup 2)))
2406 (compare:CC (match_dup 0)
2410 ;; Operand 1 is divided by operand 2; quotient goes to operand
2411 ;; 0 and remainder to operand 3.
2412 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2414 (define_expand "divmodsi4"
2415 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2416 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2417 (match_operand:SI 2 "gpc_reg_operand" "")))
2418 (set (match_operand:SI 3 "register_operand" "")
2419 (mod:SI (match_dup 1) (match_dup 2)))])]
2420 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2423 if (! TARGET_POWER && ! TARGET_POWERPC)
2425 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2426 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2427 emit_insn (gen_divss_call ());
2428 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2429 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2434 (define_insn "*divmodsi4_internal"
2435 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2436 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2437 (match_operand:SI 2 "gpc_reg_operand" "r")))
2438 (set (match_operand:SI 3 "register_operand" "=q")
2439 (mod:SI (match_dup 1) (match_dup 2)))]
2442 [(set_attr "type" "idiv")])
2444 (define_expand "udiv<mode>3"
2445 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2446 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2447 (match_operand:GPR 2 "gpc_reg_operand" "")))]
2448 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2451 if (! TARGET_POWER && ! TARGET_POWERPC)
2453 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2454 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2455 emit_insn (gen_quous_call ());
2456 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2459 else if (TARGET_POWER)
2461 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2466 (define_insn "udivsi3_mq"
2467 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2468 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2469 (match_operand:SI 2 "gpc_reg_operand" "r")))
2470 (clobber (match_scratch:SI 3 "=q"))]
2471 "TARGET_POWERPC && TARGET_POWER"
2473 [(set_attr "type" "idiv")])
2475 (define_insn "*udivsi3_no_mq"
2476 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2477 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2478 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2479 "TARGET_POWERPC && ! TARGET_POWER"
2482 (cond [(match_operand:SI 0 "" "")
2483 (const_string "idiv")]
2484 (const_string "ldiv")))])
2487 ;; For powers of two we can do srai/aze for divide and then adjust for
2488 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2489 ;; used; for PowerPC, force operands into register and do a normal divide;
2490 ;; for AIX common-mode, use quoss call on register operands.
2491 (define_expand "div<mode>3"
2492 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2493 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2494 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2498 if (GET_CODE (operands[2]) == CONST_INT
2499 && INTVAL (operands[2]) > 0
2500 && exact_log2 (INTVAL (operands[2])) >= 0)
2502 else if (TARGET_POWERPC)
2504 operands[2] = force_reg (<MODE>mode, operands[2]);
2507 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2511 else if (TARGET_POWER)
2515 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2516 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2517 emit_insn (gen_quoss_call ());
2518 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2523 (define_insn "divsi3_mq"
2524 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2525 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2526 (match_operand:SI 2 "gpc_reg_operand" "r")))
2527 (clobber (match_scratch:SI 3 "=q"))]
2528 "TARGET_POWERPC && TARGET_POWER"
2530 [(set_attr "type" "idiv")])
2532 (define_insn "*div<mode>3_no_mq"
2533 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2534 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2535 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2536 "TARGET_POWERPC && ! TARGET_POWER"
2539 (cond [(match_operand:SI 0 "" "")
2540 (const_string "idiv")]
2541 (const_string "ldiv")))])
2543 (define_expand "mod<mode>3"
2544 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2545 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2546 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2554 if (GET_CODE (operands[2]) != CONST_INT
2555 || INTVAL (operands[2]) <= 0
2556 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2559 temp1 = gen_reg_rtx (<MODE>mode);
2560 temp2 = gen_reg_rtx (<MODE>mode);
2562 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2563 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2564 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2569 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2570 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2571 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2573 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
2574 [(set_attr "type" "two")
2575 (set_attr "length" "8")])
2578 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2579 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2580 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2582 (clobber (match_scratch:P 3 "=r,r"))]
2585 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
2587 [(set_attr "type" "compare")
2588 (set_attr "length" "8,12")])
2591 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2592 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2593 (match_operand:GPR 2 "exact_log2_cint_operand"
2596 (clobber (match_scratch:GPR 3 ""))]
2599 (div:<MODE> (match_dup 1) (match_dup 2)))
2601 (compare:CC (match_dup 3)
2606 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2607 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2608 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2610 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2611 (div:P (match_dup 1) (match_dup 2)))]
2614 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
2616 [(set_attr "type" "compare")
2617 (set_attr "length" "8,12")])
2620 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2621 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2622 (match_operand:GPR 2 "exact_log2_cint_operand"
2625 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2626 (div:GPR (match_dup 1) (match_dup 2)))]
2629 (div:<MODE> (match_dup 1) (match_dup 2)))
2631 (compare:CC (match_dup 0)
2636 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2639 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2641 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2642 (match_operand:SI 3 "gpc_reg_operand" "r")))
2643 (set (match_operand:SI 2 "register_operand" "=*q")
2646 (zero_extend:DI (match_dup 1)) (const_int 32))
2647 (zero_extend:DI (match_dup 4)))
2651 [(set_attr "type" "idiv")])
2653 ;; To do unsigned divide we handle the cases of the divisor looking like a
2654 ;; negative number. If it is a constant that is less than 2**31, we don't
2655 ;; have to worry about the branches. So make a few subroutines here.
2657 ;; First comes the normal case.
2658 (define_expand "udivmodsi4_normal"
2659 [(set (match_dup 4) (const_int 0))
2660 (parallel [(set (match_operand:SI 0 "" "")
2661 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2663 (zero_extend:DI (match_operand:SI 1 "" "")))
2664 (match_operand:SI 2 "" "")))
2665 (set (match_operand:SI 3 "" "")
2666 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2668 (zero_extend:DI (match_dup 1)))
2672 { operands[4] = gen_reg_rtx (SImode); }")
2674 ;; This handles the branches.
2675 (define_expand "udivmodsi4_tests"
2676 [(set (match_operand:SI 0 "" "") (const_int 0))
2677 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2678 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2679 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2680 (label_ref (match_operand:SI 4 "" "")) (pc)))
2681 (set (match_dup 0) (const_int 1))
2682 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2683 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2684 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2685 (label_ref (match_dup 4)) (pc)))]
2688 { operands[5] = gen_reg_rtx (CCUNSmode);
2689 operands[6] = gen_reg_rtx (CCmode);
2692 (define_expand "udivmodsi4"
2693 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2694 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2695 (match_operand:SI 2 "reg_or_cint_operand" "")))
2696 (set (match_operand:SI 3 "gpc_reg_operand" "")
2697 (umod:SI (match_dup 1) (match_dup 2)))])]
2705 if (! TARGET_POWERPC)
2707 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2708 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2709 emit_insn (gen_divus_call ());
2710 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2711 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2718 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2720 operands[2] = force_reg (SImode, operands[2]);
2721 label = gen_label_rtx ();
2722 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2723 operands[3], label));
2726 operands[2] = force_reg (SImode, operands[2]);
2728 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2736 ;; AIX architecture-independent common-mode multiply (DImode),
2737 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2738 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2739 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2740 ;; assumed unused if generating common-mode, so ignore.
2741 (define_insn "mulh_call"
2744 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2745 (sign_extend:DI (reg:SI 4)))
2747 (clobber (reg:SI LR_REGNO))]
2748 "! TARGET_POWER && ! TARGET_POWERPC"
2750 [(set_attr "type" "imul")])
2752 (define_insn "mull_call"
2754 (mult:DI (sign_extend:DI (reg:SI 3))
2755 (sign_extend:DI (reg:SI 4))))
2756 (clobber (reg:SI LR_REGNO))
2757 (clobber (reg:SI 0))]
2758 "! TARGET_POWER && ! TARGET_POWERPC"
2760 [(set_attr "type" "imul")])
2762 (define_insn "divss_call"
2764 (div:SI (reg:SI 3) (reg:SI 4)))
2766 (mod:SI (reg:SI 3) (reg:SI 4)))
2767 (clobber (reg:SI LR_REGNO))
2768 (clobber (reg:SI 0))]
2769 "! TARGET_POWER && ! TARGET_POWERPC"
2771 [(set_attr "type" "idiv")])
2773 (define_insn "divus_call"
2775 (udiv:SI (reg:SI 3) (reg:SI 4)))
2777 (umod:SI (reg:SI 3) (reg:SI 4)))
2778 (clobber (reg:SI LR_REGNO))
2779 (clobber (reg:SI 0))
2780 (clobber (match_scratch:CC 0 "=x"))
2781 (clobber (reg:CC CR1_REGNO))]
2782 "! TARGET_POWER && ! TARGET_POWERPC"
2784 [(set_attr "type" "idiv")])
2786 (define_insn "quoss_call"
2788 (div:SI (reg:SI 3) (reg:SI 4)))
2789 (clobber (reg:SI LR_REGNO))]
2790 "! TARGET_POWER && ! TARGET_POWERPC"
2792 [(set_attr "type" "idiv")])
2794 (define_insn "quous_call"
2796 (udiv:SI (reg:SI 3) (reg:SI 4)))
2797 (clobber (reg:SI LR_REGNO))
2798 (clobber (reg:SI 0))
2799 (clobber (match_scratch:CC 0 "=x"))
2800 (clobber (reg:CC CR1_REGNO))]
2801 "! TARGET_POWER && ! TARGET_POWERPC"
2803 [(set_attr "type" "idiv")])
2805 ;; Logical instructions
2806 ;; The logical instructions are mostly combined by using match_operator,
2807 ;; but the plain AND insns are somewhat different because there is no
2808 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2809 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2811 (define_insn "andsi3"
2812 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2813 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2814 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2815 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2819 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2820 {andil.|andi.} %0,%1,%b2
2821 {andiu.|andis.} %0,%1,%u2"
2822 [(set_attr "type" "*,*,compare,compare")])
2824 ;; Note to set cr's other than cr0 we do the and immediate and then
2825 ;; the test again -- this avoids a mfcr which on the higher end
2826 ;; machines causes an execution serialization
2828 (define_insn "*andsi3_internal2"
2829 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2830 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2831 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2833 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2834 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2838 {andil.|andi.} %3,%1,%b2
2839 {andiu.|andis.} %3,%1,%u2
2840 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2845 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2846 (set_attr "length" "4,4,4,4,8,8,8,8")])
2848 (define_insn "*andsi3_internal3"
2849 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2850 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2851 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2853 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2854 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2858 {andil.|andi.} %3,%1,%b2
2859 {andiu.|andis.} %3,%1,%u2
2860 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2865 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2866 (set_attr "length" "8,4,4,4,8,8,8,8")])
2869 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2870 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2871 (match_operand:GPR 2 "and_operand" ""))
2873 (clobber (match_scratch:GPR 3 ""))
2874 (clobber (match_scratch:CC 4 ""))]
2876 [(parallel [(set (match_dup 3)
2877 (and:<MODE> (match_dup 1)
2879 (clobber (match_dup 4))])
2881 (compare:CC (match_dup 3)
2885 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2886 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2889 [(set (match_operand:CC 0 "cc_reg_operand" "")
2890 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2891 (match_operand:SI 2 "gpc_reg_operand" ""))
2893 (clobber (match_scratch:SI 3 ""))
2894 (clobber (match_scratch:CC 4 ""))]
2895 "TARGET_POWERPC64 && reload_completed"
2896 [(parallel [(set (match_dup 3)
2897 (and:SI (match_dup 1)
2899 (clobber (match_dup 4))])
2901 (compare:CC (match_dup 3)
2905 (define_insn "*andsi3_internal4"
2906 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2907 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2908 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2910 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2911 (and:SI (match_dup 1)
2913 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2917 {andil.|andi.} %0,%1,%b2
2918 {andiu.|andis.} %0,%1,%u2
2919 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2924 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2925 (set_attr "length" "4,4,4,4,8,8,8,8")])
2927 (define_insn "*andsi3_internal5"
2928 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2929 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2930 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2932 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2933 (and:SI (match_dup 1)
2935 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2939 {andil.|andi.} %0,%1,%b2
2940 {andiu.|andis.} %0,%1,%u2
2941 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2946 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2947 (set_attr "length" "8,4,4,4,8,8,8,8")])
2950 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2951 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2952 (match_operand:SI 2 "and_operand" ""))
2954 (set (match_operand:SI 0 "gpc_reg_operand" "")
2955 (and:SI (match_dup 1)
2957 (clobber (match_scratch:CC 4 ""))]
2959 [(parallel [(set (match_dup 0)
2960 (and:SI (match_dup 1)
2962 (clobber (match_dup 4))])
2964 (compare:CC (match_dup 0)
2969 [(set (match_operand:CC 3 "cc_reg_operand" "")
2970 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2971 (match_operand:SI 2 "gpc_reg_operand" ""))
2973 (set (match_operand:SI 0 "gpc_reg_operand" "")
2974 (and:SI (match_dup 1)
2976 (clobber (match_scratch:CC 4 ""))]
2977 "TARGET_POWERPC64 && reload_completed"
2978 [(parallel [(set (match_dup 0)
2979 (and:SI (match_dup 1)
2981 (clobber (match_dup 4))])
2983 (compare:CC (match_dup 0)
2987 ;; Handle the PowerPC64 rlwinm corner case
2989 (define_insn_and_split "*andsi3_internal6"
2990 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2991 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2992 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2997 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3000 (rotate:SI (match_dup 0) (match_dup 5)))]
3003 int mb = extract_MB (operands[2]);
3004 int me = extract_ME (operands[2]);
3005 operands[3] = GEN_INT (me + 1);
3006 operands[5] = GEN_INT (32 - (me + 1));
3007 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3009 [(set_attr "length" "8")])
3011 (define_expand "iorsi3"
3012 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3013 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
3014 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3018 if (GET_CODE (operands[2]) == CONST_INT
3019 && ! logical_operand (operands[2], SImode))
3021 HOST_WIDE_INT value = INTVAL (operands[2]);
3022 rtx tmp = ((!can_create_pseudo_p ()
3023 || rtx_equal_p (operands[0], operands[1]))
3024 ? operands[0] : gen_reg_rtx (SImode));
3026 emit_insn (gen_iorsi3 (tmp, operands[1],
3027 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3028 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3033 (define_expand "xorsi3"
3034 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3035 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3036 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3040 if (GET_CODE (operands[2]) == CONST_INT
3041 && ! logical_operand (operands[2], SImode))
3043 HOST_WIDE_INT value = INTVAL (operands[2]);
3044 rtx tmp = ((!can_create_pseudo_p ()
3045 || rtx_equal_p (operands[0], operands[1]))
3046 ? operands[0] : gen_reg_rtx (SImode));
3048 emit_insn (gen_xorsi3 (tmp, operands[1],
3049 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3050 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3055 (define_insn "*boolsi3_internal1"
3056 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3057 (match_operator:SI 3 "boolean_or_operator"
3058 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3059 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3063 {%q3il|%q3i} %0,%1,%b2
3064 {%q3iu|%q3is} %0,%1,%u2")
3066 (define_insn "*boolsi3_internal2"
3067 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3068 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3069 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3070 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3072 (clobber (match_scratch:SI 3 "=r,r"))]
3077 [(set_attr "type" "compare")
3078 (set_attr "length" "4,8")])
3081 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3082 (compare:CC (match_operator:SI 4 "boolean_operator"
3083 [(match_operand:SI 1 "gpc_reg_operand" "")
3084 (match_operand:SI 2 "gpc_reg_operand" "")])
3086 (clobber (match_scratch:SI 3 ""))]
3087 "TARGET_32BIT && reload_completed"
3088 [(set (match_dup 3) (match_dup 4))
3090 (compare:CC (match_dup 3)
3094 (define_insn "*boolsi3_internal3"
3095 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3096 (compare:CC (match_operator:SI 4 "boolean_operator"
3097 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3098 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3100 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3106 [(set_attr "type" "compare")
3107 (set_attr "length" "4,8")])
3110 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3111 (compare:CC (match_operator:SI 4 "boolean_operator"
3112 [(match_operand:SI 1 "gpc_reg_operand" "")
3113 (match_operand:SI 2 "gpc_reg_operand" "")])
3115 (set (match_operand:SI 0 "gpc_reg_operand" "")
3117 "TARGET_32BIT && reload_completed"
3118 [(set (match_dup 0) (match_dup 4))
3120 (compare:CC (match_dup 0)
3124 ;; Split a logical operation that we can't do in one insn into two insns,
3125 ;; each of which does one 16-bit part. This is used by combine.
3128 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3129 (match_operator:SI 3 "boolean_or_operator"
3130 [(match_operand:SI 1 "gpc_reg_operand" "")
3131 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3133 [(set (match_dup 0) (match_dup 4))
3134 (set (match_dup 0) (match_dup 5))]
3138 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3139 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3141 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3142 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3146 (define_insn "*boolcsi3_internal1"
3147 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3148 (match_operator:SI 3 "boolean_operator"
3149 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3150 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3154 (define_insn "*boolcsi3_internal2"
3155 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3156 (compare:CC (match_operator:SI 4 "boolean_operator"
3157 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3158 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3160 (clobber (match_scratch:SI 3 "=r,r"))]
3165 [(set_attr "type" "compare")
3166 (set_attr "length" "4,8")])
3169 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3170 (compare:CC (match_operator:SI 4 "boolean_operator"
3171 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3172 (match_operand:SI 2 "gpc_reg_operand" "")])
3174 (clobber (match_scratch:SI 3 ""))]
3175 "TARGET_32BIT && reload_completed"
3176 [(set (match_dup 3) (match_dup 4))
3178 (compare:CC (match_dup 3)
3182 (define_insn "*boolcsi3_internal3"
3183 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3184 (compare:CC (match_operator:SI 4 "boolean_operator"
3185 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3186 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3188 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3194 [(set_attr "type" "compare")
3195 (set_attr "length" "4,8")])
3198 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3199 (compare:CC (match_operator:SI 4 "boolean_operator"
3200 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3201 (match_operand:SI 2 "gpc_reg_operand" "")])
3203 (set (match_operand:SI 0 "gpc_reg_operand" "")
3205 "TARGET_32BIT && reload_completed"
3206 [(set (match_dup 0) (match_dup 4))
3208 (compare:CC (match_dup 0)
3212 (define_insn "*boolccsi3_internal1"
3213 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3214 (match_operator:SI 3 "boolean_operator"
3215 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3216 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3220 (define_insn "*boolccsi3_internal2"
3221 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3222 (compare:CC (match_operator:SI 4 "boolean_operator"
3223 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3224 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3226 (clobber (match_scratch:SI 3 "=r,r"))]
3231 [(set_attr "type" "compare")
3232 (set_attr "length" "4,8")])
3235 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3236 (compare:CC (match_operator:SI 4 "boolean_operator"
3237 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3238 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3240 (clobber (match_scratch:SI 3 ""))]
3241 "TARGET_32BIT && reload_completed"
3242 [(set (match_dup 3) (match_dup 4))
3244 (compare:CC (match_dup 3)
3248 (define_insn "*boolccsi3_internal3"
3249 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3250 (compare:CC (match_operator:SI 4 "boolean_operator"
3251 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3252 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3254 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3260 [(set_attr "type" "compare")
3261 (set_attr "length" "4,8")])
3264 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3265 (compare:CC (match_operator:SI 4 "boolean_operator"
3266 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3267 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3269 (set (match_operand:SI 0 "gpc_reg_operand" "")
3271 "TARGET_32BIT && reload_completed"
3272 [(set (match_dup 0) (match_dup 4))
3274 (compare:CC (match_dup 0)
3278 ;; maskir insn. We need four forms because things might be in arbitrary
3279 ;; orders. Don't define forms that only set CR fields because these
3280 ;; would modify an input register.
3282 (define_insn "*maskir_internal1"
3283 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3284 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3285 (match_operand:SI 1 "gpc_reg_operand" "0"))
3286 (and:SI (match_dup 2)
3287 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3291 (define_insn "*maskir_internal2"
3292 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3293 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3294 (match_operand:SI 1 "gpc_reg_operand" "0"))
3295 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3300 (define_insn "*maskir_internal3"
3301 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3302 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3303 (match_operand:SI 3 "gpc_reg_operand" "r"))
3304 (and:SI (not:SI (match_dup 2))
3305 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3309 (define_insn "*maskir_internal4"
3310 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3311 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3312 (match_operand:SI 2 "gpc_reg_operand" "r"))
3313 (and:SI (not:SI (match_dup 2))
3314 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3318 (define_insn "*maskir_internal5"
3319 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3321 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3322 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3323 (and:SI (match_dup 2)
3324 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3326 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3327 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3328 (and:SI (match_dup 2) (match_dup 3))))]
3333 [(set_attr "type" "compare")
3334 (set_attr "length" "4,8")])
3337 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3339 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3340 (match_operand:SI 1 "gpc_reg_operand" ""))
3341 (and:SI (match_dup 2)
3342 (match_operand:SI 3 "gpc_reg_operand" "")))
3344 (set (match_operand:SI 0 "gpc_reg_operand" "")
3345 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3346 (and:SI (match_dup 2) (match_dup 3))))]
3347 "TARGET_POWER && reload_completed"
3349 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3350 (and:SI (match_dup 2) (match_dup 3))))
3352 (compare:CC (match_dup 0)
3356 (define_insn "*maskir_internal6"
3357 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3359 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3360 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3361 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3364 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3365 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3366 (and:SI (match_dup 3) (match_dup 2))))]
3371 [(set_attr "type" "compare")
3372 (set_attr "length" "4,8")])
3375 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3377 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3378 (match_operand:SI 1 "gpc_reg_operand" ""))
3379 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3382 (set (match_operand:SI 0 "gpc_reg_operand" "")
3383 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3384 (and:SI (match_dup 3) (match_dup 2))))]
3385 "TARGET_POWER && reload_completed"
3387 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3388 (and:SI (match_dup 3) (match_dup 2))))
3390 (compare:CC (match_dup 0)
3394 (define_insn "*maskir_internal7"
3395 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3397 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3398 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3399 (and:SI (not:SI (match_dup 2))
3400 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3402 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3403 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3404 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3409 [(set_attr "type" "compare")
3410 (set_attr "length" "4,8")])
3413 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3415 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3416 (match_operand:SI 3 "gpc_reg_operand" ""))
3417 (and:SI (not:SI (match_dup 2))
3418 (match_operand:SI 1 "gpc_reg_operand" "")))
3420 (set (match_operand:SI 0 "gpc_reg_operand" "")
3421 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3422 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3423 "TARGET_POWER && reload_completed"
3425 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3426 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3428 (compare:CC (match_dup 0)
3432 (define_insn "*maskir_internal8"
3433 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3435 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3436 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3437 (and:SI (not:SI (match_dup 2))
3438 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3440 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3441 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3442 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3447 [(set_attr "type" "compare")
3448 (set_attr "length" "4,8")])
3451 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3453 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3454 (match_operand:SI 2 "gpc_reg_operand" ""))
3455 (and:SI (not:SI (match_dup 2))
3456 (match_operand:SI 1 "gpc_reg_operand" "")))
3458 (set (match_operand:SI 0 "gpc_reg_operand" "")
3459 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3460 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3461 "TARGET_POWER && reload_completed"
3463 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3464 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3466 (compare:CC (match_dup 0)
3470 ;; Rotate and shift insns, in all their variants. These support shifts,
3471 ;; field inserts and extracts, and various combinations thereof.
3472 (define_expand "insv"
3473 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3474 (match_operand:SI 1 "const_int_operand" "")
3475 (match_operand:SI 2 "const_int_operand" ""))
3476 (match_operand 3 "gpc_reg_operand" ""))]
3480 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3481 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3482 compiler if the address of the structure is taken later. Likewise, do
3483 not handle invalid E500 subregs. */
3484 if (GET_CODE (operands[0]) == SUBREG
3485 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3486 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3487 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3490 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3491 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3493 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3497 (define_insn "insvsi"
3498 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3499 (match_operand:SI 1 "const_int_operand" "i")
3500 (match_operand:SI 2 "const_int_operand" "i"))
3501 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3505 int start = INTVAL (operands[2]) & 31;
3506 int size = INTVAL (operands[1]) & 31;
3508 operands[4] = GEN_INT (32 - start - size);
3509 operands[1] = GEN_INT (start + size - 1);
3510 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3512 [(set_attr "type" "insert_word")])
3514 (define_insn "*insvsi_internal1"
3515 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3516 (match_operand:SI 1 "const_int_operand" "i")
3517 (match_operand:SI 2 "const_int_operand" "i"))
3518 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3519 (match_operand:SI 4 "const_int_operand" "i")))]
3520 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3523 int shift = INTVAL (operands[4]) & 31;
3524 int start = INTVAL (operands[2]) & 31;
3525 int size = INTVAL (operands[1]) & 31;
3527 operands[4] = GEN_INT (shift - start - size);
3528 operands[1] = GEN_INT (start + size - 1);
3529 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3531 [(set_attr "type" "insert_word")])
3533 (define_insn "*insvsi_internal2"
3534 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3535 (match_operand:SI 1 "const_int_operand" "i")
3536 (match_operand:SI 2 "const_int_operand" "i"))
3537 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3538 (match_operand:SI 4 "const_int_operand" "i")))]
3539 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3542 int shift = INTVAL (operands[4]) & 31;
3543 int start = INTVAL (operands[2]) & 31;
3544 int size = INTVAL (operands[1]) & 31;
3546 operands[4] = GEN_INT (32 - shift - start - size);
3547 operands[1] = GEN_INT (start + size - 1);
3548 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3550 [(set_attr "type" "insert_word")])
3552 (define_insn "*insvsi_internal3"
3553 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3554 (match_operand:SI 1 "const_int_operand" "i")
3555 (match_operand:SI 2 "const_int_operand" "i"))
3556 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3557 (match_operand:SI 4 "const_int_operand" "i")))]
3558 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3561 int shift = INTVAL (operands[4]) & 31;
3562 int start = INTVAL (operands[2]) & 31;
3563 int size = INTVAL (operands[1]) & 31;
3565 operands[4] = GEN_INT (32 - shift - start - size);
3566 operands[1] = GEN_INT (start + size - 1);
3567 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3569 [(set_attr "type" "insert_word")])
3571 (define_insn "*insvsi_internal4"
3572 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3573 (match_operand:SI 1 "const_int_operand" "i")
3574 (match_operand:SI 2 "const_int_operand" "i"))
3575 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3576 (match_operand:SI 4 "const_int_operand" "i")
3577 (match_operand:SI 5 "const_int_operand" "i")))]
3578 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3581 int extract_start = INTVAL (operands[5]) & 31;
3582 int extract_size = INTVAL (operands[4]) & 31;
3583 int insert_start = INTVAL (operands[2]) & 31;
3584 int insert_size = INTVAL (operands[1]) & 31;
3586 /* Align extract field with insert field */
3587 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3588 operands[1] = GEN_INT (insert_start + insert_size - 1);
3589 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3591 [(set_attr "type" "insert_word")])
3593 ;; combine patterns for rlwimi
3594 (define_insn "*insvsi_internal5"
3595 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3596 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3597 (match_operand:SI 1 "mask_operand" "i"))
3598 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3599 (match_operand:SI 2 "const_int_operand" "i"))
3600 (match_operand:SI 5 "mask_operand" "i"))))]
3601 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3604 int me = extract_ME(operands[5]);
3605 int mb = extract_MB(operands[5]);
3606 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3607 operands[2] = GEN_INT(mb);
3608 operands[1] = GEN_INT(me);
3609 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3611 [(set_attr "type" "insert_word")])
3613 (define_insn "*insvsi_internal6"
3614 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3615 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3616 (match_operand:SI 2 "const_int_operand" "i"))
3617 (match_operand:SI 5 "mask_operand" "i"))
3618 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3619 (match_operand:SI 1 "mask_operand" "i"))))]
3620 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3623 int me = extract_ME(operands[5]);
3624 int mb = extract_MB(operands[5]);
3625 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3626 operands[2] = GEN_INT(mb);
3627 operands[1] = GEN_INT(me);
3628 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3630 [(set_attr "type" "insert_word")])
3632 (define_insn "insvdi"
3633 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3634 (match_operand:SI 1 "const_int_operand" "i")
3635 (match_operand:SI 2 "const_int_operand" "i"))
3636 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3640 int start = INTVAL (operands[2]) & 63;
3641 int size = INTVAL (operands[1]) & 63;
3643 operands[1] = GEN_INT (64 - start - size);
3644 return \"rldimi %0,%3,%H1,%H2\";
3646 [(set_attr "type" "insert_dword")])
3648 (define_insn "*insvdi_internal2"
3649 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3650 (match_operand:SI 1 "const_int_operand" "i")
3651 (match_operand:SI 2 "const_int_operand" "i"))
3652 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3653 (match_operand:SI 4 "const_int_operand" "i")))]
3655 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3658 int shift = INTVAL (operands[4]) & 63;
3659 int start = (INTVAL (operands[2]) & 63) - 32;
3660 int size = INTVAL (operands[1]) & 63;
3662 operands[4] = GEN_INT (64 - shift - start - size);
3663 operands[2] = GEN_INT (start);
3664 operands[1] = GEN_INT (start + size - 1);
3665 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3668 (define_insn "*insvdi_internal3"
3669 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3670 (match_operand:SI 1 "const_int_operand" "i")
3671 (match_operand:SI 2 "const_int_operand" "i"))
3672 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3673 (match_operand:SI 4 "const_int_operand" "i")))]
3675 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3678 int shift = INTVAL (operands[4]) & 63;
3679 int start = (INTVAL (operands[2]) & 63) - 32;
3680 int size = INTVAL (operands[1]) & 63;
3682 operands[4] = GEN_INT (64 - shift - start - size);
3683 operands[2] = GEN_INT (start);
3684 operands[1] = GEN_INT (start + size - 1);
3685 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3688 (define_expand "extzv"
3689 [(set (match_operand 0 "gpc_reg_operand" "")
3690 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3691 (match_operand:SI 2 "const_int_operand" "")
3692 (match_operand:SI 3 "const_int_operand" "")))]
3696 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3697 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3698 compiler if the address of the structure is taken later. */
3699 if (GET_CODE (operands[0]) == SUBREG
3700 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3703 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3704 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3706 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3710 (define_insn "extzvsi"
3711 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3712 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3713 (match_operand:SI 2 "const_int_operand" "i")
3714 (match_operand:SI 3 "const_int_operand" "i")))]
3718 int start = INTVAL (operands[3]) & 31;
3719 int size = INTVAL (operands[2]) & 31;
3721 if (start + size >= 32)
3722 operands[3] = const0_rtx;
3724 operands[3] = GEN_INT (start + size);
3725 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3728 (define_insn "*extzvsi_internal1"
3729 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3730 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3731 (match_operand:SI 2 "const_int_operand" "i,i")
3732 (match_operand:SI 3 "const_int_operand" "i,i"))
3734 (clobber (match_scratch:SI 4 "=r,r"))]
3738 int start = INTVAL (operands[3]) & 31;
3739 int size = INTVAL (operands[2]) & 31;
3741 /* Force split for non-cc0 compare. */
3742 if (which_alternative == 1)
3745 /* If the bit-field being tested fits in the upper or lower half of a
3746 word, it is possible to use andiu. or andil. to test it. This is
3747 useful because the condition register set-use delay is smaller for
3748 andi[ul]. than for rlinm. This doesn't work when the starting bit
3749 position is 0 because the LT and GT bits may be set wrong. */
3751 if ((start > 0 && start + size <= 16) || start >= 16)
3753 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3754 - (1 << (16 - (start & 15) - size))));
3756 return \"{andiu.|andis.} %4,%1,%3\";
3758 return \"{andil.|andi.} %4,%1,%3\";
3761 if (start + size >= 32)
3762 operands[3] = const0_rtx;
3764 operands[3] = GEN_INT (start + size);
3765 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3767 [(set_attr "type" "delayed_compare")
3768 (set_attr "length" "4,8")])
3771 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3772 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3773 (match_operand:SI 2 "const_int_operand" "")
3774 (match_operand:SI 3 "const_int_operand" ""))
3776 (clobber (match_scratch:SI 4 ""))]
3779 (zero_extract:SI (match_dup 1) (match_dup 2)
3782 (compare:CC (match_dup 4)
3786 (define_insn "*extzvsi_internal2"
3787 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3788 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3789 (match_operand:SI 2 "const_int_operand" "i,i")
3790 (match_operand:SI 3 "const_int_operand" "i,i"))
3792 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3793 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3797 int start = INTVAL (operands[3]) & 31;
3798 int size = INTVAL (operands[2]) & 31;
3800 /* Force split for non-cc0 compare. */
3801 if (which_alternative == 1)
3804 /* Since we are using the output value, we can't ignore any need for
3805 a shift. The bit-field must end at the LSB. */
3806 if (start >= 16 && start + size == 32)
3808 operands[3] = GEN_INT ((1 << size) - 1);
3809 return \"{andil.|andi.} %0,%1,%3\";
3812 if (start + size >= 32)
3813 operands[3] = const0_rtx;
3815 operands[3] = GEN_INT (start + size);
3816 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3818 [(set_attr "type" "delayed_compare")
3819 (set_attr "length" "4,8")])
3822 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3823 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3824 (match_operand:SI 2 "const_int_operand" "")
3825 (match_operand:SI 3 "const_int_operand" ""))
3827 (set (match_operand:SI 0 "gpc_reg_operand" "")
3828 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3831 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3833 (compare:CC (match_dup 0)
3837 (define_insn "extzvdi"
3838 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3839 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3840 (match_operand:SI 2 "const_int_operand" "i")
3841 (match_operand:SI 3 "const_int_operand" "i")))]
3845 int start = INTVAL (operands[3]) & 63;
3846 int size = INTVAL (operands[2]) & 63;
3848 if (start + size >= 64)
3849 operands[3] = const0_rtx;
3851 operands[3] = GEN_INT (start + size);
3852 operands[2] = GEN_INT (64 - size);
3853 return \"rldicl %0,%1,%3,%2\";
3856 (define_insn "*extzvdi_internal1"
3857 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3858 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3859 (match_operand:SI 2 "const_int_operand" "i")
3860 (match_operand:SI 3 "const_int_operand" "i"))
3862 (clobber (match_scratch:DI 4 "=r"))]
3866 int start = INTVAL (operands[3]) & 63;
3867 int size = INTVAL (operands[2]) & 63;
3869 if (start + size >= 64)
3870 operands[3] = const0_rtx;
3872 operands[3] = GEN_INT (start + size);
3873 operands[2] = GEN_INT (64 - size);
3874 return \"rldicl. %4,%1,%3,%2\";
3876 [(set_attr "type" "compare")])
3878 (define_insn "*extzvdi_internal2"
3879 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3880 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3881 (match_operand:SI 2 "const_int_operand" "i")
3882 (match_operand:SI 3 "const_int_operand" "i"))
3884 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3885 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3889 int start = INTVAL (operands[3]) & 63;
3890 int size = INTVAL (operands[2]) & 63;
3892 if (start + size >= 64)
3893 operands[3] = const0_rtx;
3895 operands[3] = GEN_INT (start + size);
3896 operands[2] = GEN_INT (64 - size);
3897 return \"rldicl. %0,%1,%3,%2\";
3899 [(set_attr "type" "compare")])
3901 (define_insn "rotlsi3"
3902 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3903 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3904 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
3907 {rlnm|rlwnm} %0,%1,%2,0xffffffff
3908 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
3909 [(set_attr "type" "var_shift_rotate,integer")])
3911 (define_insn "*rotlsi3_internal2"
3912 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3913 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3914 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3916 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3919 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
3920 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
3923 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3924 (set_attr "length" "4,4,8,8")])
3927 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3928 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3929 (match_operand:SI 2 "reg_or_cint_operand" ""))
3931 (clobber (match_scratch:SI 3 ""))]
3934 (rotate:SI (match_dup 1) (match_dup 2)))
3936 (compare:CC (match_dup 3)
3940 (define_insn "*rotlsi3_internal3"
3941 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3942 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3943 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3945 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3946 (rotate:SI (match_dup 1) (match_dup 2)))]
3949 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
3950 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
3953 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3954 (set_attr "length" "4,4,8,8")])
3957 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3958 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3959 (match_operand:SI 2 "reg_or_cint_operand" ""))
3961 (set (match_operand:SI 0 "gpc_reg_operand" "")
3962 (rotate:SI (match_dup 1) (match_dup 2)))]
3965 (rotate:SI (match_dup 1) (match_dup 2)))
3967 (compare:CC (match_dup 0)
3971 (define_insn "*rotlsi3_internal4"
3972 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3973 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3974 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
3975 (match_operand:SI 3 "mask_operand" "n,n")))]
3978 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
3979 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
3980 [(set_attr "type" "var_shift_rotate,integer")])
3982 (define_insn "*rotlsi3_internal5"
3983 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3985 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3986 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3987 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3989 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
3992 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
3993 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3996 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3997 (set_attr "length" "4,4,8,8")])
4000 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4002 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4003 (match_operand:SI 2 "reg_or_cint_operand" ""))
4004 (match_operand:SI 3 "mask_operand" ""))
4006 (clobber (match_scratch:SI 4 ""))]
4009 (and:SI (rotate:SI (match_dup 1)
4013 (compare:CC (match_dup 4)
4017 (define_insn "*rotlsi3_internal6"
4018 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
4020 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4021 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4022 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4024 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4025 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4028 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
4029 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4032 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4033 (set_attr "length" "4,4,8,8")])
4036 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4038 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4039 (match_operand:SI 2 "reg_or_cint_operand" ""))
4040 (match_operand:SI 3 "mask_operand" ""))
4042 (set (match_operand:SI 0 "gpc_reg_operand" "")
4043 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4046 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4048 (compare:CC (match_dup 0)
4052 (define_insn "*rotlsi3_internal7"
4053 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4056 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4057 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4059 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
4061 (define_insn "*rotlsi3_internal8"
4062 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4063 (compare:CC (zero_extend:SI
4065 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4066 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4068 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4071 {rlnm.|rlwnm.} %3,%1,%2,0xff
4072 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4075 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4076 (set_attr "length" "4,4,8,8")])
4079 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4080 (compare:CC (zero_extend:SI
4082 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4083 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4085 (clobber (match_scratch:SI 3 ""))]
4088 (zero_extend:SI (subreg:QI
4089 (rotate:SI (match_dup 1)
4092 (compare:CC (match_dup 3)
4096 (define_insn "*rotlsi3_internal9"
4097 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4098 (compare:CC (zero_extend:SI
4100 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4101 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4103 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4104 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4107 {rlnm.|rlwnm.} %0,%1,%2,0xff
4108 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4111 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4112 (set_attr "length" "4,4,8,8")])
4115 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4116 (compare:CC (zero_extend:SI
4118 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4119 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4121 (set (match_operand:SI 0 "gpc_reg_operand" "")
4122 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4125 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4127 (compare:CC (match_dup 0)
4131 (define_insn "*rotlsi3_internal10"
4132 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4135 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4136 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4139 {rlnm|rlwnm} %0,%1,%2,0xffff
4140 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4141 [(set_attr "type" "var_shift_rotate,integer")])
4144 (define_insn "*rotlsi3_internal11"
4145 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4146 (compare:CC (zero_extend:SI
4148 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4149 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4151 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4154 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4155 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4158 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4159 (set_attr "length" "4,4,8,8")])
4162 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4163 (compare:CC (zero_extend:SI
4165 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4166 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4168 (clobber (match_scratch:SI 3 ""))]
4171 (zero_extend:SI (subreg:HI
4172 (rotate:SI (match_dup 1)
4175 (compare:CC (match_dup 3)
4179 (define_insn "*rotlsi3_internal12"
4180 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4181 (compare:CC (zero_extend:SI
4183 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4184 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4186 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4187 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4190 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4191 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4194 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4195 (set_attr "length" "4,4,8,8")])
4198 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4199 (compare:CC (zero_extend:SI
4201 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4202 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4204 (set (match_operand:SI 0 "gpc_reg_operand" "")
4205 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4208 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4210 (compare:CC (match_dup 0)
4214 ;; Note that we use "sle." instead of "sl." so that we can set
4215 ;; SHIFT_COUNT_TRUNCATED.
4217 (define_expand "ashlsi3"
4218 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4219 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4220 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4225 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4227 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4231 (define_insn "ashlsi3_power"
4232 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4233 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4234 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4235 (clobber (match_scratch:SI 3 "=q,X"))]
4239 {sli|slwi} %0,%1,%h2")
4241 (define_insn "ashlsi3_no_power"
4242 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4243 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4244 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4248 {sli|slwi} %0,%1,%h2"
4249 [(set_attr "type" "var_shift_rotate,shift")])
4252 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4253 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4254 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4256 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4257 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4261 {sli.|slwi.} %3,%1,%h2
4264 [(set_attr "type" "delayed_compare")
4265 (set_attr "length" "4,4,8,8")])
4268 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4269 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4270 (match_operand:SI 2 "reg_or_cint_operand" ""))
4272 (clobber (match_scratch:SI 3 ""))
4273 (clobber (match_scratch:SI 4 ""))]
4274 "TARGET_POWER && reload_completed"
4275 [(parallel [(set (match_dup 3)
4276 (ashift:SI (match_dup 1) (match_dup 2)))
4277 (clobber (match_dup 4))])
4279 (compare:CC (match_dup 3)
4284 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4285 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4286 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4288 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4289 "! TARGET_POWER && TARGET_32BIT"
4292 {sli.|slwi.} %3,%1,%h2
4295 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4296 (set_attr "length" "4,4,8,8")])
4299 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4300 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4301 (match_operand:SI 2 "reg_or_cint_operand" ""))
4303 (clobber (match_scratch:SI 3 ""))]
4304 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4306 (ashift:SI (match_dup 1) (match_dup 2)))
4308 (compare:CC (match_dup 3)
4313 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4314 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4315 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4317 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4318 (ashift:SI (match_dup 1) (match_dup 2)))
4319 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4323 {sli.|slwi.} %0,%1,%h2
4326 [(set_attr "type" "delayed_compare")
4327 (set_attr "length" "4,4,8,8")])
4330 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4331 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4332 (match_operand:SI 2 "reg_or_cint_operand" ""))
4334 (set (match_operand:SI 0 "gpc_reg_operand" "")
4335 (ashift:SI (match_dup 1) (match_dup 2)))
4336 (clobber (match_scratch:SI 4 ""))]
4337 "TARGET_POWER && reload_completed"
4338 [(parallel [(set (match_dup 0)
4339 (ashift:SI (match_dup 1) (match_dup 2)))
4340 (clobber (match_dup 4))])
4342 (compare:CC (match_dup 0)
4347 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4348 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4349 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4351 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4352 (ashift:SI (match_dup 1) (match_dup 2)))]
4353 "! TARGET_POWER && TARGET_32BIT"
4356 {sli.|slwi.} %0,%1,%h2
4359 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4360 (set_attr "length" "4,4,8,8")])
4363 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4364 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4365 (match_operand:SI 2 "reg_or_cint_operand" ""))
4367 (set (match_operand:SI 0 "gpc_reg_operand" "")
4368 (ashift:SI (match_dup 1) (match_dup 2)))]
4369 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4371 (ashift:SI (match_dup 1) (match_dup 2)))
4373 (compare:CC (match_dup 0)
4377 (define_insn "rlwinm"
4378 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4379 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4380 (match_operand:SI 2 "const_int_operand" "i"))
4381 (match_operand:SI 3 "mask_operand" "n")))]
4382 "includes_lshift_p (operands[2], operands[3])"
4383 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4386 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4388 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4389 (match_operand:SI 2 "const_int_operand" "i,i"))
4390 (match_operand:SI 3 "mask_operand" "n,n"))
4392 (clobber (match_scratch:SI 4 "=r,r"))]
4393 "includes_lshift_p (operands[2], operands[3])"
4395 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4397 [(set_attr "type" "delayed_compare")
4398 (set_attr "length" "4,8")])
4401 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4403 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4404 (match_operand:SI 2 "const_int_operand" ""))
4405 (match_operand:SI 3 "mask_operand" ""))
4407 (clobber (match_scratch:SI 4 ""))]
4408 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4410 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4413 (compare:CC (match_dup 4)
4418 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4420 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4421 (match_operand:SI 2 "const_int_operand" "i,i"))
4422 (match_operand:SI 3 "mask_operand" "n,n"))
4424 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4425 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4426 "includes_lshift_p (operands[2], operands[3])"
4428 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4430 [(set_attr "type" "delayed_compare")
4431 (set_attr "length" "4,8")])
4434 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4436 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4437 (match_operand:SI 2 "const_int_operand" ""))
4438 (match_operand:SI 3 "mask_operand" ""))
4440 (set (match_operand:SI 0 "gpc_reg_operand" "")
4441 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4442 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4444 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4446 (compare:CC (match_dup 0)
4450 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
4452 (define_expand "lshrsi3"
4453 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4454 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4455 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4460 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4462 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
4466 (define_insn "lshrsi3_power"
4467 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4468 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4469 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4470 (clobber (match_scratch:SI 3 "=q,X,X"))]
4475 {s%A2i|s%A2wi} %0,%1,%h2")
4477 (define_insn "lshrsi3_no_power"
4478 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4479 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4480 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
4485 {sri|srwi} %0,%1,%h2"
4486 [(set_attr "type" "integer,var_shift_rotate,shift")])
4489 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4490 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4491 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4493 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4494 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4499 {s%A2i.|s%A2wi.} %3,%1,%h2
4503 [(set_attr "type" "delayed_compare")
4504 (set_attr "length" "4,4,4,8,8,8")])
4507 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4508 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4509 (match_operand:SI 2 "reg_or_cint_operand" ""))
4511 (clobber (match_scratch:SI 3 ""))
4512 (clobber (match_scratch:SI 4 ""))]
4513 "TARGET_POWER && reload_completed"
4514 [(parallel [(set (match_dup 3)
4515 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4516 (clobber (match_dup 4))])
4518 (compare:CC (match_dup 3)
4523 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4524 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4525 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4527 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4528 "! TARGET_POWER && TARGET_32BIT"
4532 {sri.|srwi.} %3,%1,%h2
4536 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4537 (set_attr "length" "4,4,4,8,8,8")])
4540 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4541 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4542 (match_operand:SI 2 "reg_or_cint_operand" ""))
4544 (clobber (match_scratch:SI 3 ""))]
4545 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4547 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4549 (compare:CC (match_dup 3)
4554 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4555 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4556 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4558 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4559 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4560 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4565 {s%A2i.|s%A2wi.} %0,%1,%h2
4569 [(set_attr "type" "delayed_compare")
4570 (set_attr "length" "4,4,4,8,8,8")])
4573 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4574 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4575 (match_operand:SI 2 "reg_or_cint_operand" ""))
4577 (set (match_operand:SI 0 "gpc_reg_operand" "")
4578 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4579 (clobber (match_scratch:SI 4 ""))]
4580 "TARGET_POWER && reload_completed"
4581 [(parallel [(set (match_dup 0)
4582 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4583 (clobber (match_dup 4))])
4585 (compare:CC (match_dup 0)
4590 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4591 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4592 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4594 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4595 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4596 "! TARGET_POWER && TARGET_32BIT"
4600 {sri.|srwi.} %0,%1,%h2
4604 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4605 (set_attr "length" "4,4,4,8,8,8")])
4608 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4609 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4610 (match_operand:SI 2 "reg_or_cint_operand" ""))
4612 (set (match_operand:SI 0 "gpc_reg_operand" "")
4613 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4614 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4616 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4618 (compare:CC (match_dup 0)
4623 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4624 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4625 (match_operand:SI 2 "const_int_operand" "i"))
4626 (match_operand:SI 3 "mask_operand" "n")))]
4627 "includes_rshift_p (operands[2], operands[3])"
4628 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4631 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4633 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4634 (match_operand:SI 2 "const_int_operand" "i,i"))
4635 (match_operand:SI 3 "mask_operand" "n,n"))
4637 (clobber (match_scratch:SI 4 "=r,r"))]
4638 "includes_rshift_p (operands[2], operands[3])"
4640 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4642 [(set_attr "type" "delayed_compare")
4643 (set_attr "length" "4,8")])
4646 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4648 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4649 (match_operand:SI 2 "const_int_operand" ""))
4650 (match_operand:SI 3 "mask_operand" ""))
4652 (clobber (match_scratch:SI 4 ""))]
4653 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4655 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4658 (compare:CC (match_dup 4)
4663 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4665 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4666 (match_operand:SI 2 "const_int_operand" "i,i"))
4667 (match_operand:SI 3 "mask_operand" "n,n"))
4669 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4670 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4671 "includes_rshift_p (operands[2], operands[3])"
4673 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4675 [(set_attr "type" "delayed_compare")
4676 (set_attr "length" "4,8")])
4679 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4681 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4682 (match_operand:SI 2 "const_int_operand" ""))
4683 (match_operand:SI 3 "mask_operand" ""))
4685 (set (match_operand:SI 0 "gpc_reg_operand" "")
4686 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4687 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4689 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4691 (compare:CC (match_dup 0)
4696 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4699 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4700 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4701 "includes_rshift_p (operands[2], GEN_INT (255))"
4702 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4705 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4709 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4710 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4712 (clobber (match_scratch:SI 3 "=r,r"))]
4713 "includes_rshift_p (operands[2], GEN_INT (255))"
4715 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4717 [(set_attr "type" "delayed_compare")
4718 (set_attr "length" "4,8")])
4721 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4725 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4726 (match_operand:SI 2 "const_int_operand" "")) 0))
4728 (clobber (match_scratch:SI 3 ""))]
4729 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4731 (zero_extend:SI (subreg:QI
4732 (lshiftrt:SI (match_dup 1)
4735 (compare:CC (match_dup 3)
4740 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4744 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4745 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4747 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4748 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4749 "includes_rshift_p (operands[2], GEN_INT (255))"
4751 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4753 [(set_attr "type" "delayed_compare")
4754 (set_attr "length" "4,8")])
4757 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4761 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4762 (match_operand:SI 2 "const_int_operand" "")) 0))
4764 (set (match_operand:SI 0 "gpc_reg_operand" "")
4765 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4766 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4768 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4770 (compare:CC (match_dup 0)
4775 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4778 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4779 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4780 "includes_rshift_p (operands[2], GEN_INT (65535))"
4781 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4784 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4788 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4789 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4791 (clobber (match_scratch:SI 3 "=r,r"))]
4792 "includes_rshift_p (operands[2], GEN_INT (65535))"
4794 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4796 [(set_attr "type" "delayed_compare")
4797 (set_attr "length" "4,8")])
4800 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4804 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4805 (match_operand:SI 2 "const_int_operand" "")) 0))
4807 (clobber (match_scratch:SI 3 ""))]
4808 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4810 (zero_extend:SI (subreg:HI
4811 (lshiftrt:SI (match_dup 1)
4814 (compare:CC (match_dup 3)
4819 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4823 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4824 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4826 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4827 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4828 "includes_rshift_p (operands[2], GEN_INT (65535))"
4830 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4832 [(set_attr "type" "delayed_compare")
4833 (set_attr "length" "4,8")])
4836 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4840 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4841 (match_operand:SI 2 "const_int_operand" "")) 0))
4843 (set (match_operand:SI 0 "gpc_reg_operand" "")
4844 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4845 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4847 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4849 (compare:CC (match_dup 0)
4854 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4856 (match_operand:SI 1 "gpc_reg_operand" "r"))
4857 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4863 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4865 (match_operand:SI 1 "gpc_reg_operand" "r"))
4866 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4872 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4874 (match_operand:SI 1 "gpc_reg_operand" "r"))
4875 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4881 (define_expand "ashrsi3"
4882 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4883 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4884 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4889 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4891 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4895 (define_insn "ashrsi3_power"
4896 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4897 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4898 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4899 (clobber (match_scratch:SI 3 "=q,X"))]
4903 {srai|srawi} %0,%1,%h2"
4904 [(set_attr "type" "shift")])
4906 (define_insn "ashrsi3_no_power"
4907 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4908 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4909 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4913 {srai|srawi} %0,%1,%h2"
4914 [(set_attr "type" "var_shift_rotate,shift")])
4917 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4918 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4919 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4921 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4922 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4926 {srai.|srawi.} %3,%1,%h2
4929 [(set_attr "type" "delayed_compare")
4930 (set_attr "length" "4,4,8,8")])
4933 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4934 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4935 (match_operand:SI 2 "reg_or_cint_operand" ""))
4937 (clobber (match_scratch:SI 3 ""))
4938 (clobber (match_scratch:SI 4 ""))]
4939 "TARGET_POWER && reload_completed"
4940 [(parallel [(set (match_dup 3)
4941 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4942 (clobber (match_dup 4))])
4944 (compare:CC (match_dup 3)
4949 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4950 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4951 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4953 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4956 {sra.|sraw.} %3,%1,%2
4957 {srai.|srawi.} %3,%1,%h2
4960 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4961 (set_attr "length" "4,4,8,8")])
4964 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4965 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4966 (match_operand:SI 2 "reg_or_cint_operand" ""))
4968 (clobber (match_scratch:SI 3 ""))]
4969 "! TARGET_POWER && reload_completed"
4971 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4973 (compare:CC (match_dup 3)
4978 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4979 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4980 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4982 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4983 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4984 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4988 {srai.|srawi.} %0,%1,%h2
4991 [(set_attr "type" "delayed_compare")
4992 (set_attr "length" "4,4,8,8")])
4995 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4996 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4997 (match_operand:SI 2 "reg_or_cint_operand" ""))
4999 (set (match_operand:SI 0 "gpc_reg_operand" "")
5000 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5001 (clobber (match_scratch:SI 4 ""))]
5002 "TARGET_POWER && reload_completed"
5003 [(parallel [(set (match_dup 0)
5004 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5005 (clobber (match_dup 4))])
5007 (compare:CC (match_dup 0)
5012 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5013 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5014 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5016 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5017 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5020 {sra.|sraw.} %0,%1,%2
5021 {srai.|srawi.} %0,%1,%h2
5024 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5025 (set_attr "length" "4,4,8,8")])
5028 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5029 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5030 (match_operand:SI 2 "reg_or_cint_operand" ""))
5032 (set (match_operand:SI 0 "gpc_reg_operand" "")
5033 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5034 "! TARGET_POWER && reload_completed"
5036 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5038 (compare:CC (match_dup 0)
5042 ;; Floating-point insns, excluding normal data motion.
5044 ;; PowerPC has a full set of single-precision floating point instructions.
5046 ;; For the POWER architecture, we pretend that we have both SFmode and
5047 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
5048 ;; The only conversions we will do will be when storing to memory. In that
5049 ;; case, we will use the "frsp" instruction before storing.
5051 ;; Note that when we store into a single-precision memory location, we need to
5052 ;; use the frsp insn first. If the register being stored isn't dead, we
5053 ;; need a scratch register for the frsp. But this is difficult when the store
5054 ;; is done by reload. It is not incorrect to do the frsp on the register in
5055 ;; this case, we just lose precision that we would have otherwise gotten but
5056 ;; is not guaranteed. Perhaps this should be tightened up at some point.
5058 (define_expand "extendsfdf2"
5059 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5060 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5061 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5064 (define_insn_and_split "*extendsfdf2_fpr"
5065 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
5066 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
5067 "TARGET_HARD_FLOAT && TARGET_FPRS"
5072 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5075 emit_note (NOTE_INSN_DELETED);
5078 [(set_attr "type" "fp,fp,fpload")])
5080 (define_expand "truncdfsf2"
5081 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5082 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5083 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5086 (define_insn "*truncdfsf2_fpr"
5087 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5088 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5089 "TARGET_HARD_FLOAT && TARGET_FPRS"
5091 [(set_attr "type" "fp")])
5093 (define_insn "aux_truncdfsf2"
5094 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5095 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
5096 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5098 [(set_attr "type" "fp")])
5100 (define_expand "negsf2"
5101 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5102 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5106 (define_insn "*negsf2"
5107 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5108 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5109 "TARGET_HARD_FLOAT && TARGET_FPRS"
5111 [(set_attr "type" "fp")])
5113 (define_expand "abssf2"
5114 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5115 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5119 (define_insn "*abssf2"
5120 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5121 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5122 "TARGET_HARD_FLOAT && TARGET_FPRS"
5124 [(set_attr "type" "fp")])
5127 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5128 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
5129 "TARGET_HARD_FLOAT && TARGET_FPRS"
5131 [(set_attr "type" "fp")])
5133 (define_expand "addsf3"
5134 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5135 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5136 (match_operand:SF 2 "gpc_reg_operand" "")))]
5141 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5142 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5143 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5144 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5146 [(set_attr "type" "fp")])
5149 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5150 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5151 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5152 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5153 "{fa|fadd} %0,%1,%2"
5154 [(set_attr "type" "fp")])
5156 (define_expand "subsf3"
5157 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5158 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5159 (match_operand:SF 2 "gpc_reg_operand" "")))]
5164 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5165 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5166 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5167 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5169 [(set_attr "type" "fp")])
5172 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5173 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5174 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5175 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5176 "{fs|fsub} %0,%1,%2"
5177 [(set_attr "type" "fp")])
5179 (define_expand "mulsf3"
5180 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5181 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5182 (match_operand:SF 2 "gpc_reg_operand" "")))]
5187 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5188 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5189 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5190 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5192 [(set_attr "type" "fp")])
5195 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5196 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5197 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5198 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5199 "{fm|fmul} %0,%1,%2"
5200 [(set_attr "type" "dmul")])
5202 (define_expand "divsf3"
5203 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5204 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5205 (match_operand:SF 2 "gpc_reg_operand" "")))]
5210 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5211 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5212 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5213 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5215 [(set_attr "type" "sdiv")])
5218 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5219 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5220 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5221 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5222 "{fd|fdiv} %0,%1,%2"
5223 [(set_attr "type" "ddiv")])
5225 (define_expand "recipsf3"
5226 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5227 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")
5228 (match_operand:SF 2 "gpc_reg_operand" "f")]
5230 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5231 && flag_finite_math_only && !flag_trapping_math"
5233 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5238 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5239 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5240 "TARGET_PPC_GFXOPT && flag_finite_math_only"
5242 [(set_attr "type" "fp")])
5245 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5246 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5247 (match_operand:SF 2 "gpc_reg_operand" "f"))
5248 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5249 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5250 "fmadds %0,%1,%2,%3"
5251 [(set_attr "type" "fp")])
5254 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5255 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5256 (match_operand:SF 2 "gpc_reg_operand" "f"))
5257 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5258 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5259 "{fma|fmadd} %0,%1,%2,%3"
5260 [(set_attr "type" "dmul")])
5263 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5264 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5265 (match_operand:SF 2 "gpc_reg_operand" "f"))
5266 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5267 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5268 "fmsubs %0,%1,%2,%3"
5269 [(set_attr "type" "fp")])
5272 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5273 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5274 (match_operand:SF 2 "gpc_reg_operand" "f"))
5275 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5276 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5277 "{fms|fmsub} %0,%1,%2,%3"
5278 [(set_attr "type" "dmul")])
5281 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5282 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5283 (match_operand:SF 2 "gpc_reg_operand" "f"))
5284 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5285 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5286 && HONOR_SIGNED_ZEROS (SFmode)"
5287 "fnmadds %0,%1,%2,%3"
5288 [(set_attr "type" "fp")])
5291 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5292 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5293 (match_operand:SF 2 "gpc_reg_operand" "f"))
5294 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5295 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5296 && ! HONOR_SIGNED_ZEROS (SFmode)"
5297 "fnmadds %0,%1,%2,%3"
5298 [(set_attr "type" "fp")])
5301 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5302 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5303 (match_operand:SF 2 "gpc_reg_operand" "f"))
5304 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5305 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5306 "{fnma|fnmadd} %0,%1,%2,%3"
5307 [(set_attr "type" "dmul")])
5310 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5311 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5312 (match_operand:SF 2 "gpc_reg_operand" "f"))
5313 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5314 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5315 && ! HONOR_SIGNED_ZEROS (SFmode)"
5316 "{fnma|fnmadd} %0,%1,%2,%3"
5317 [(set_attr "type" "dmul")])
5320 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5321 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5322 (match_operand:SF 2 "gpc_reg_operand" "f"))
5323 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5324 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5325 && HONOR_SIGNED_ZEROS (SFmode)"
5326 "fnmsubs %0,%1,%2,%3"
5327 [(set_attr "type" "fp")])
5330 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5331 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5332 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5333 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5334 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5335 && ! HONOR_SIGNED_ZEROS (SFmode)"
5336 "fnmsubs %0,%1,%2,%3"
5337 [(set_attr "type" "fp")])
5340 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5341 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5342 (match_operand:SF 2 "gpc_reg_operand" "f"))
5343 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5344 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5345 "{fnms|fnmsub} %0,%1,%2,%3"
5346 [(set_attr "type" "dmul")])
5349 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5350 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5351 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5352 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5353 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5354 && ! HONOR_SIGNED_ZEROS (SFmode)"
5355 "{fnms|fnmsub} %0,%1,%2,%3"
5356 [(set_attr "type" "dmul")])
5358 (define_expand "sqrtsf2"
5359 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5360 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5361 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5365 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5366 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5367 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5369 [(set_attr "type" "ssqrt")])
5372 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5373 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5374 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
5376 [(set_attr "type" "dsqrt")])
5378 (define_expand "rsqrtsf2"
5379 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5380 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5382 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5383 && flag_finite_math_only && !flag_trapping_math"
5385 rs6000_emit_swrsqrtsf (operands[0], operands[1]);
5389 (define_insn "*rsqrt_internal1"
5390 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5391 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5393 "TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT"
5395 [(set_attr "type" "fp")])
5397 (define_expand "copysignsf3"
5399 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5401 (neg:SF (abs:SF (match_dup 1))))
5402 (set (match_operand:SF 0 "gpc_reg_operand" "")
5403 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5407 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5408 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
5410 operands[3] = gen_reg_rtx (SFmode);
5411 operands[4] = gen_reg_rtx (SFmode);
5412 operands[5] = CONST0_RTX (SFmode);
5415 (define_expand "copysigndf3"
5417 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5419 (neg:DF (abs:DF (match_dup 1))))
5420 (set (match_operand:DF 0 "gpc_reg_operand" "")
5421 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5425 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5426 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
5428 operands[3] = gen_reg_rtx (DFmode);
5429 operands[4] = gen_reg_rtx (DFmode);
5430 operands[5] = CONST0_RTX (DFmode);
5433 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5434 ;; fsel instruction and some auxiliary computations. Then we just have a
5435 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5437 (define_expand "smaxsf3"
5438 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5439 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5440 (match_operand:SF 2 "gpc_reg_operand" ""))
5443 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5444 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5446 (define_expand "sminsf3"
5447 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5448 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5449 (match_operand:SF 2 "gpc_reg_operand" ""))
5452 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5453 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5456 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5457 (match_operator:SF 3 "min_max_operator"
5458 [(match_operand:SF 1 "gpc_reg_operand" "")
5459 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5460 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5463 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5464 operands[1], operands[2]);
5468 (define_expand "movsicc"
5469 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5470 (if_then_else:SI (match_operand 1 "comparison_operator" "")
5471 (match_operand:SI 2 "gpc_reg_operand" "")
5472 (match_operand:SI 3 "gpc_reg_operand" "")))]
5476 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5482 ;; We use the BASE_REGS for the isel input operands because, if rA is
5483 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5484 ;; because we may switch the operands and rB may end up being rA.
5486 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5487 ;; leave out the mode in operand 4 and use one pattern, but reload can
5488 ;; change the mode underneath our feet and then gets confused trying
5489 ;; to reload the value.
5490 (define_insn "isel_signed"
5491 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5493 (match_operator 1 "comparison_operator"
5494 [(match_operand:CC 4 "cc_reg_operand" "y")
5496 (match_operand:SI 2 "gpc_reg_operand" "b")
5497 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5500 { return output_isel (operands); }"
5501 [(set_attr "length" "4")])
5503 (define_insn "isel_unsigned"
5504 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5506 (match_operator 1 "comparison_operator"
5507 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5509 (match_operand:SI 2 "gpc_reg_operand" "b")
5510 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5513 { return output_isel (operands); }"
5514 [(set_attr "length" "4")])
5516 (define_expand "movsfcc"
5517 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5518 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5519 (match_operand:SF 2 "gpc_reg_operand" "")
5520 (match_operand:SF 3 "gpc_reg_operand" "")))]
5521 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5524 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5530 (define_insn "*fselsfsf4"
5531 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5532 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5533 (match_operand:SF 4 "zero_fp_constant" "F"))
5534 (match_operand:SF 2 "gpc_reg_operand" "f")
5535 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5536 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5538 [(set_attr "type" "fp")])
5540 (define_insn "*fseldfsf4"
5541 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5542 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5543 (match_operand:DF 4 "zero_fp_constant" "F"))
5544 (match_operand:SF 2 "gpc_reg_operand" "f")
5545 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5546 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5548 [(set_attr "type" "fp")])
5550 (define_expand "negdf2"
5551 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5552 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5553 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5556 (define_insn "*negdf2_fpr"
5557 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5558 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5559 "TARGET_HARD_FLOAT && TARGET_FPRS"
5561 [(set_attr "type" "fp")])
5563 (define_expand "absdf2"
5564 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5565 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5566 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5569 (define_insn "*absdf2_fpr"
5570 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5571 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5572 "TARGET_HARD_FLOAT && TARGET_FPRS"
5574 [(set_attr "type" "fp")])
5576 (define_insn "*nabsdf2_fpr"
5577 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5578 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
5579 "TARGET_HARD_FLOAT && TARGET_FPRS"
5581 [(set_attr "type" "fp")])
5583 (define_expand "adddf3"
5584 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5585 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5586 (match_operand:DF 2 "gpc_reg_operand" "")))]
5587 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5590 (define_insn "*adddf3_fpr"
5591 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5592 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5593 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5594 "TARGET_HARD_FLOAT && TARGET_FPRS"
5595 "{fa|fadd} %0,%1,%2"
5596 [(set_attr "type" "fp")])
5598 (define_expand "subdf3"
5599 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5600 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5601 (match_operand:DF 2 "gpc_reg_operand" "")))]
5602 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5605 (define_insn "*subdf3_fpr"
5606 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5607 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5608 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5609 "TARGET_HARD_FLOAT && TARGET_FPRS"
5610 "{fs|fsub} %0,%1,%2"
5611 [(set_attr "type" "fp")])
5613 (define_expand "muldf3"
5614 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5615 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5616 (match_operand:DF 2 "gpc_reg_operand" "")))]
5617 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5620 (define_insn "*muldf3_fpr"
5621 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5622 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5623 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5624 "TARGET_HARD_FLOAT && TARGET_FPRS"
5625 "{fm|fmul} %0,%1,%2"
5626 [(set_attr "type" "dmul")])
5628 (define_expand "divdf3"
5629 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5630 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5631 (match_operand:DF 2 "gpc_reg_operand" "")))]
5632 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5635 (define_insn "*divdf3_fpr"
5636 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5637 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5638 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5639 "TARGET_HARD_FLOAT && TARGET_FPRS"
5640 "{fd|fdiv} %0,%1,%2"
5641 [(set_attr "type" "ddiv")])
5643 (define_expand "recipdf3"
5644 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5645 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")
5646 (match_operand:DF 2 "gpc_reg_operand" "f")]
5648 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_POPCNTB && !optimize_size
5649 && flag_finite_math_only && !flag_trapping_math"
5651 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5656 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5657 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5658 "TARGET_POPCNTB && flag_finite_math_only"
5660 [(set_attr "type" "fp")])
5663 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5664 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5665 (match_operand:DF 2 "gpc_reg_operand" "f"))
5666 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5667 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5668 "{fma|fmadd} %0,%1,%2,%3"
5669 [(set_attr "type" "dmul")])
5672 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5673 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5674 (match_operand:DF 2 "gpc_reg_operand" "f"))
5675 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5676 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5677 "{fms|fmsub} %0,%1,%2,%3"
5678 [(set_attr "type" "dmul")])
5681 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5682 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5683 (match_operand:DF 2 "gpc_reg_operand" "f"))
5684 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5685 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5686 && HONOR_SIGNED_ZEROS (DFmode)"
5687 "{fnma|fnmadd} %0,%1,%2,%3"
5688 [(set_attr "type" "dmul")])
5691 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5692 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5693 (match_operand:DF 2 "gpc_reg_operand" "f"))
5694 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5695 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5696 && ! HONOR_SIGNED_ZEROS (DFmode)"
5697 "{fnma|fnmadd} %0,%1,%2,%3"
5698 [(set_attr "type" "dmul")])
5701 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5702 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5703 (match_operand:DF 2 "gpc_reg_operand" "f"))
5704 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5705 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5706 && HONOR_SIGNED_ZEROS (DFmode)"
5707 "{fnms|fnmsub} %0,%1,%2,%3"
5708 [(set_attr "type" "dmul")])
5711 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5712 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5713 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5714 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5715 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5716 && ! HONOR_SIGNED_ZEROS (DFmode)"
5717 "{fnms|fnmsub} %0,%1,%2,%3"
5718 [(set_attr "type" "dmul")])
5720 (define_insn "sqrtdf2"
5721 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5722 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5723 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5725 [(set_attr "type" "dsqrt")])
5727 ;; The conditional move instructions allow us to perform max and min
5728 ;; operations even when
5730 (define_expand "smaxdf3"
5731 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5732 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5733 (match_operand:DF 2 "gpc_reg_operand" ""))
5736 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5737 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5739 (define_expand "smindf3"
5740 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5741 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5742 (match_operand:DF 2 "gpc_reg_operand" ""))
5745 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5746 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5749 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5750 (match_operator:DF 3 "min_max_operator"
5751 [(match_operand:DF 1 "gpc_reg_operand" "")
5752 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5753 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5756 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5757 operands[1], operands[2]);
5761 (define_expand "movdfcc"
5762 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5763 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5764 (match_operand:DF 2 "gpc_reg_operand" "")
5765 (match_operand:DF 3 "gpc_reg_operand" "")))]
5766 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5769 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5775 (define_insn "*fseldfdf4"
5776 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5777 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5778 (match_operand:DF 4 "zero_fp_constant" "F"))
5779 (match_operand:DF 2 "gpc_reg_operand" "f")
5780 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5781 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5783 [(set_attr "type" "fp")])
5785 (define_insn "*fselsfdf4"
5786 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5787 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5788 (match_operand:SF 4 "zero_fp_constant" "F"))
5789 (match_operand:DF 2 "gpc_reg_operand" "f")
5790 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5793 [(set_attr "type" "fp")])
5795 ;; Conversions to and from floating-point.
5797 (define_expand "fixuns_truncsfsi2"
5798 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5799 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5800 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5803 (define_expand "fix_truncsfsi2"
5804 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5805 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5806 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5809 ; For each of these conversions, there is a define_expand, a define_insn
5810 ; with a '#' template, and a define_split (with C code). The idea is
5811 ; to allow constant folding with the template of the define_insn,
5812 ; then to have the insns split later (between sched1 and final).
5814 (define_expand "floatsidf2"
5815 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5816 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5819 (clobber (match_dup 4))
5820 (clobber (match_dup 5))
5821 (clobber (match_dup 6))])]
5822 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5825 if (TARGET_E500_DOUBLE)
5827 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5830 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS)
5832 rtx t1 = gen_reg_rtx (DImode);
5833 emit_insn (gen_floatsidf_ppc64_mfpgpr (operands[0], operands[1], t1));
5836 if (TARGET_POWERPC64)
5838 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5839 rtx t1 = gen_reg_rtx (DImode);
5840 rtx t2 = gen_reg_rtx (DImode);
5841 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5845 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5846 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5847 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5848 operands[5] = gen_reg_rtx (DFmode);
5849 operands[6] = gen_reg_rtx (SImode);
5852 (define_insn_and_split "*floatsidf2_internal"
5853 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5854 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5855 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5856 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5857 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5858 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5859 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5860 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5862 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
5866 rtx lowword, highword;
5867 gcc_assert (MEM_P (operands[4]));
5868 highword = adjust_address (operands[4], SImode, 0);
5869 lowword = adjust_address (operands[4], SImode, 4);
5870 if (! WORDS_BIG_ENDIAN)
5873 tmp = highword; highword = lowword; lowword = tmp;
5876 emit_insn (gen_xorsi3 (operands[6], operands[1],
5877 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5878 emit_move_insn (lowword, operands[6]);
5879 emit_move_insn (highword, operands[2]);
5880 emit_move_insn (operands[5], operands[4]);
5881 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5884 [(set_attr "length" "24")])
5886 (define_expand "floatunssisf2"
5887 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5888 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5889 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5892 (define_expand "floatunssidf2"
5893 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5894 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5897 (clobber (match_dup 4))
5898 (clobber (match_dup 5))])]
5899 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5902 if (TARGET_E500_DOUBLE)
5904 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5907 if (TARGET_POWERPC64)
5909 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5910 rtx t1 = gen_reg_rtx (DImode);
5911 rtx t2 = gen_reg_rtx (DImode);
5912 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5917 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5918 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5919 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5920 operands[5] = gen_reg_rtx (DFmode);
5923 (define_insn_and_split "*floatunssidf2_internal"
5924 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5925 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5926 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5927 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5928 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5929 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5930 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5932 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
5936 rtx lowword, highword;
5937 gcc_assert (MEM_P (operands[4]));
5938 highword = adjust_address (operands[4], SImode, 0);
5939 lowword = adjust_address (operands[4], SImode, 4);
5940 if (! WORDS_BIG_ENDIAN)
5943 tmp = highword; highword = lowword; lowword = tmp;
5946 emit_move_insn (lowword, operands[1]);
5947 emit_move_insn (highword, operands[2]);
5948 emit_move_insn (operands[5], operands[4]);
5949 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5952 [(set_attr "length" "20")])
5954 (define_expand "fix_truncdfsi2"
5955 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
5956 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5957 (clobber (match_dup 2))
5958 (clobber (match_dup 3))])]
5959 "(TARGET_POWER2 || TARGET_POWERPC)
5960 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5963 if (TARGET_E500_DOUBLE)
5965 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5968 operands[2] = gen_reg_rtx (DImode);
5969 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
5970 && gpc_reg_operand(operands[0], GET_MODE (operands[0])))
5972 operands[3] = gen_reg_rtx (DImode);
5973 emit_insn (gen_fix_truncdfsi2_mfpgpr (operands[0], operands[1],
5974 operands[2], operands[3]));
5977 if (TARGET_PPC_GFXOPT)
5979 rtx orig_dest = operands[0];
5980 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
5981 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5982 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5984 if (operands[0] != orig_dest)
5985 emit_move_insn (orig_dest, operands[0]);
5988 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5991 (define_insn_and_split "*fix_truncdfsi2_internal"
5992 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5993 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5994 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5995 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))]
5996 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5998 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[3]))"
6003 gcc_assert (MEM_P (operands[3]));
6004 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
6006 emit_insn (gen_fctiwz (operands[2], operands[1]));
6007 emit_move_insn (operands[3], operands[2]);
6008 emit_move_insn (operands[0], lowword);
6011 [(set_attr "length" "16")])
6013 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
6014 [(set (match_operand:SI 0 "memory_operand" "=Z")
6015 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
6016 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
6017 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6018 && TARGET_PPC_GFXOPT"
6024 emit_insn (gen_fctiwz (operands[2], operands[1]));
6025 emit_insn (gen_stfiwx (operands[0], operands[2]));
6028 [(set_attr "length" "16")])
6030 (define_insn_and_split "fix_truncdfsi2_mfpgpr"
6031 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6032 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
6033 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
6034 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
6035 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
6038 [(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
6039 (set (match_dup 3) (match_dup 2))
6040 (set (match_dup 0) (subreg:SI (match_dup 3) 4))]
6042 [(set_attr "length" "12")])
6044 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6045 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6046 ; because the first makes it clear that operand 0 is not live
6047 ; before the instruction.
6048 (define_insn "fctiwz"
6049 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
6050 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
6052 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
6053 "{fcirz|fctiwz} %0,%1"
6054 [(set_attr "type" "fp")])
6056 (define_insn "btruncdf2"
6057 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6058 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6059 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6061 [(set_attr "type" "fp")])
6063 (define_insn "btruncsf2"
6064 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6065 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6066 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6068 [(set_attr "type" "fp")])
6070 (define_insn "ceildf2"
6071 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6072 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6073 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6075 [(set_attr "type" "fp")])
6077 (define_insn "ceilsf2"
6078 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6079 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6080 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6082 [(set_attr "type" "fp")])
6084 (define_insn "floordf2"
6085 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6086 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6087 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6089 [(set_attr "type" "fp")])
6091 (define_insn "floorsf2"
6092 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6093 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6094 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6096 [(set_attr "type" "fp")])
6098 (define_insn "rounddf2"
6099 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6100 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6101 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6103 [(set_attr "type" "fp")])
6105 (define_insn "roundsf2"
6106 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6107 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6108 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6110 [(set_attr "type" "fp")])
6112 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6113 (define_insn "stfiwx"
6114 [(set (match_operand:SI 0 "memory_operand" "=Z")
6115 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
6119 [(set_attr "type" "fpstore")])
6121 (define_expand "floatsisf2"
6122 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6123 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6124 "TARGET_HARD_FLOAT && !TARGET_FPRS"
6127 (define_insn "floatdidf2"
6128 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6129 (float:DF (match_operand:DI 1 "gpc_reg_operand" "!f#r")))]
6130 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6132 [(set_attr "type" "fp")])
6134 (define_insn_and_split "floatsidf_ppc64_mfpgpr"
6135 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6136 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6137 (clobber (match_operand:DI 2 "gpc_reg_operand" "=r"))]
6138 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
6141 [(set (match_dup 2) (sign_extend:DI (match_dup 1)))
6142 (set (match_dup 0) (float:DF (match_dup 2)))]
6145 (define_insn_and_split "floatsidf_ppc64"
6146 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6147 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6148 (clobber (match_operand:DI 2 "offsettable_mem_operand" "=o"))
6149 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
6150 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
6151 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
6154 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
6155 (set (match_dup 2) (match_dup 3))
6156 (set (match_dup 4) (match_dup 2))
6157 (set (match_dup 0) (float:DF (match_dup 4)))]
6160 (define_insn_and_split "floatunssidf_ppc64"
6161 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6162 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6163 (clobber (match_operand:DI 2 "offsettable_mem_operand" "=o"))
6164 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
6165 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
6166 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6169 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
6170 (set (match_dup 2) (match_dup 3))
6171 (set (match_dup 4) (match_dup 2))
6172 (set (match_dup 0) (float:DF (match_dup 4)))]
6175 (define_insn "fix_truncdfdi2"
6176 [(set (match_operand:DI 0 "gpc_reg_operand" "=!f#r")
6177 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
6178 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6180 [(set_attr "type" "fp")])
6182 (define_expand "floatdisf2"
6183 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6184 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6185 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6188 rtx val = operands[1];
6189 if (!flag_unsafe_math_optimizations)
6191 rtx label = gen_label_rtx ();
6192 val = gen_reg_rtx (DImode);
6193 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6196 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6200 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6201 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6202 ;; from double rounding.
6203 (define_insn_and_split "floatdisf2_internal1"
6204 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6205 (float:SF (match_operand:DI 1 "gpc_reg_operand" "!f#r")))
6206 (clobber (match_scratch:DF 2 "=f"))]
6207 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6209 "&& reload_completed"
6211 (float:DF (match_dup 1)))
6213 (float_truncate:SF (match_dup 2)))]
6216 ;; Twiddles bits to avoid double rounding.
6217 ;; Bits that might be truncated when converting to DFmode are replaced
6218 ;; by a bit that won't be lost at that stage, but is below the SFmode
6219 ;; rounding position.
6220 (define_expand "floatdisf2_internal2"
6221 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6223 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6225 (clobber (scratch:CC))])
6226 (set (match_dup 3) (plus:DI (match_dup 3)
6228 (set (match_dup 0) (plus:DI (match_dup 0)
6230 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6232 (set (match_dup 0) (ior:DI (match_dup 0)
6234 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6236 (clobber (scratch:CC))])
6237 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6238 (label_ref (match_operand:DI 2 "" ""))
6240 (set (match_dup 0) (match_dup 1))]
6241 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6244 operands[3] = gen_reg_rtx (DImode);
6245 operands[4] = gen_reg_rtx (CCUNSmode);
6248 ;; Define the DImode operations that can be done in a small number
6249 ;; of instructions. The & constraints are to prevent the register
6250 ;; allocator from allocating registers that overlap with the inputs
6251 ;; (for example, having an input in 7,8 and an output in 6,7). We
6252 ;; also allow for the output being the same as one of the inputs.
6254 (define_insn "*adddi3_noppc64"
6255 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6256 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6257 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6258 "! TARGET_POWERPC64"
6261 if (WORDS_BIG_ENDIAN)
6262 return (GET_CODE (operands[2])) != CONST_INT
6263 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6264 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6266 return (GET_CODE (operands[2])) != CONST_INT
6267 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6268 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6270 [(set_attr "type" "two")
6271 (set_attr "length" "8")])
6273 (define_insn "*subdi3_noppc64"
6274 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6275 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6276 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6277 "! TARGET_POWERPC64"
6280 if (WORDS_BIG_ENDIAN)
6281 return (GET_CODE (operands[1]) != CONST_INT)
6282 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6283 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6285 return (GET_CODE (operands[1]) != CONST_INT)
6286 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6287 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
6289 [(set_attr "type" "two")
6290 (set_attr "length" "8")])
6292 (define_insn "*negdi2_noppc64"
6293 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6294 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6295 "! TARGET_POWERPC64"
6298 return (WORDS_BIG_ENDIAN)
6299 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6300 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6302 [(set_attr "type" "two")
6303 (set_attr "length" "8")])
6305 (define_expand "mulsidi3"
6306 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6307 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6308 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6309 "! TARGET_POWERPC64"
6312 if (! TARGET_POWER && ! TARGET_POWERPC)
6314 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6315 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6316 emit_insn (gen_mull_call ());
6317 if (WORDS_BIG_ENDIAN)
6318 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
6321 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
6322 gen_rtx_REG (SImode, 3));
6323 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
6324 gen_rtx_REG (SImode, 4));
6328 else if (TARGET_POWER)
6330 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6335 (define_insn "mulsidi3_mq"
6336 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6337 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6338 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6339 (clobber (match_scratch:SI 3 "=q"))]
6341 "mul %0,%1,%2\;mfmq %L0"
6342 [(set_attr "type" "imul")
6343 (set_attr "length" "8")])
6345 (define_insn "*mulsidi3_no_mq"
6346 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6347 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6348 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6349 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6352 return (WORDS_BIG_ENDIAN)
6353 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6354 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6356 [(set_attr "type" "imul")
6357 (set_attr "length" "8")])
6360 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6361 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6362 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6363 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6366 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6367 (sign_extend:DI (match_dup 2)))
6370 (mult:SI (match_dup 1)
6374 int endian = (WORDS_BIG_ENDIAN == 0);
6375 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6376 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6379 (define_expand "umulsidi3"
6380 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6381 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6382 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6383 "TARGET_POWERPC && ! TARGET_POWERPC64"
6388 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6393 (define_insn "umulsidi3_mq"
6394 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6395 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6396 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6397 (clobber (match_scratch:SI 3 "=q"))]
6398 "TARGET_POWERPC && TARGET_POWER"
6401 return (WORDS_BIG_ENDIAN)
6402 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6403 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6405 [(set_attr "type" "imul")
6406 (set_attr "length" "8")])
6408 (define_insn "*umulsidi3_no_mq"
6409 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6410 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6411 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6412 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6415 return (WORDS_BIG_ENDIAN)
6416 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6417 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6419 [(set_attr "type" "imul")
6420 (set_attr "length" "8")])
6423 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6424 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6425 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6426 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6429 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6430 (zero_extend:DI (match_dup 2)))
6433 (mult:SI (match_dup 1)
6437 int endian = (WORDS_BIG_ENDIAN == 0);
6438 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6439 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6442 (define_expand "smulsi3_highpart"
6443 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6445 (lshiftrt:DI (mult:DI (sign_extend:DI
6446 (match_operand:SI 1 "gpc_reg_operand" ""))
6448 (match_operand:SI 2 "gpc_reg_operand" "")))
6453 if (! TARGET_POWER && ! TARGET_POWERPC)
6455 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6456 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6457 emit_insn (gen_mulh_call ());
6458 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
6461 else if (TARGET_POWER)
6463 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6468 (define_insn "smulsi3_highpart_mq"
6469 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6471 (lshiftrt:DI (mult:DI (sign_extend:DI
6472 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6474 (match_operand:SI 2 "gpc_reg_operand" "r")))
6476 (clobber (match_scratch:SI 3 "=q"))]
6479 [(set_attr "type" "imul")])
6481 (define_insn "*smulsi3_highpart_no_mq"
6482 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6484 (lshiftrt:DI (mult:DI (sign_extend:DI
6485 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6487 (match_operand:SI 2 "gpc_reg_operand" "r")))
6489 "TARGET_POWERPC && ! TARGET_POWER"
6491 [(set_attr "type" "imul")])
6493 (define_expand "umulsi3_highpart"
6494 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6496 (lshiftrt:DI (mult:DI (zero_extend:DI
6497 (match_operand:SI 1 "gpc_reg_operand" ""))
6499 (match_operand:SI 2 "gpc_reg_operand" "")))
6506 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6511 (define_insn "umulsi3_highpart_mq"
6512 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6514 (lshiftrt:DI (mult:DI (zero_extend:DI
6515 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6517 (match_operand:SI 2 "gpc_reg_operand" "r")))
6519 (clobber (match_scratch:SI 3 "=q"))]
6520 "TARGET_POWERPC && TARGET_POWER"
6522 [(set_attr "type" "imul")])
6524 (define_insn "*umulsi3_highpart_no_mq"
6525 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6527 (lshiftrt:DI (mult:DI (zero_extend:DI
6528 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6530 (match_operand:SI 2 "gpc_reg_operand" "r")))
6532 "TARGET_POWERPC && ! TARGET_POWER"
6534 [(set_attr "type" "imul")])
6536 ;; If operands 0 and 2 are in the same register, we have a problem. But
6537 ;; operands 0 and 1 (the usual case) can be in the same register. That's
6538 ;; why we have the strange constraints below.
6539 (define_insn "ashldi3_power"
6540 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6541 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6542 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6543 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6546 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
6547 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6548 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6549 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
6550 [(set_attr "length" "8")])
6552 (define_insn "lshrdi3_power"
6553 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6554 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6555 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6556 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6559 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
6560 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6561 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6562 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
6563 [(set_attr "length" "8")])
6565 ;; Shift by a variable amount is too complex to be worth open-coding. We
6566 ;; just handle shifts by constants.
6567 (define_insn "ashrdi3_power"
6568 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6569 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6570 (match_operand:SI 2 "const_int_operand" "M,i")))
6571 (clobber (match_scratch:SI 3 "=X,q"))]
6574 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6575 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
6576 [(set_attr "type" "shift")
6577 (set_attr "length" "8")])
6579 (define_insn "ashrdi3_no_power"
6580 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6581 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6582 (match_operand:SI 2 "const_int_operand" "M,i")))]
6583 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
6585 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6586 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
6587 [(set_attr "type" "two,three")
6588 (set_attr "length" "8,12")])
6590 (define_insn "*ashrdisi3_noppc64"
6591 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6592 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6593 (const_int 32)) 4))]
6594 "TARGET_32BIT && !TARGET_POWERPC64"
6597 if (REGNO (operands[0]) == REGNO (operands[1]))
6600 return \"mr %0,%1\";
6602 [(set_attr "length" "4")])
6605 ;; PowerPC64 DImode operations.
6607 (define_insn_and_split "absdi2"
6608 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6609 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6610 (clobber (match_scratch:DI 2 "=&r,&r"))]
6613 "&& reload_completed"
6614 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6615 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6616 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6619 (define_insn_and_split "*nabsdi2"
6620 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6621 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6622 (clobber (match_scratch:DI 2 "=&r,&r"))]
6625 "&& reload_completed"
6626 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6627 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6628 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
6631 (define_insn "muldi3"
6632 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6633 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6634 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6640 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6641 (const_string "imul3")
6642 (match_operand:SI 2 "short_cint_operand" "")
6643 (const_string "imul2")]
6644 (const_string "lmul")))])
6646 (define_insn "*muldi3_internal1"
6647 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6648 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6649 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6651 (clobber (match_scratch:DI 3 "=r,r"))]
6656 [(set_attr "type" "lmul_compare")
6657 (set_attr "length" "4,8")])
6660 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6661 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6662 (match_operand:DI 2 "gpc_reg_operand" ""))
6664 (clobber (match_scratch:DI 3 ""))]
6665 "TARGET_POWERPC64 && reload_completed"
6667 (mult:DI (match_dup 1) (match_dup 2)))
6669 (compare:CC (match_dup 3)
6673 (define_insn "*muldi3_internal2"
6674 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6675 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6676 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6678 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6679 (mult:DI (match_dup 1) (match_dup 2)))]
6684 [(set_attr "type" "lmul_compare")
6685 (set_attr "length" "4,8")])
6688 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6689 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6690 (match_operand:DI 2 "gpc_reg_operand" ""))
6692 (set (match_operand:DI 0 "gpc_reg_operand" "")
6693 (mult:DI (match_dup 1) (match_dup 2)))]
6694 "TARGET_POWERPC64 && reload_completed"
6696 (mult:DI (match_dup 1) (match_dup 2)))
6698 (compare:CC (match_dup 0)
6702 (define_insn "smuldi3_highpart"
6703 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6705 (lshiftrt:TI (mult:TI (sign_extend:TI
6706 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6708 (match_operand:DI 2 "gpc_reg_operand" "r")))
6712 [(set_attr "type" "lmul")])
6714 (define_insn "umuldi3_highpart"
6715 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6717 (lshiftrt:TI (mult:TI (zero_extend:TI
6718 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6720 (match_operand:DI 2 "gpc_reg_operand" "r")))
6724 [(set_attr "type" "lmul")])
6726 (define_insn "rotldi3"
6727 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6728 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6729 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
6734 [(set_attr "type" "var_shift_rotate,integer")])
6736 (define_insn "*rotldi3_internal2"
6737 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6738 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6739 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6741 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6748 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6749 (set_attr "length" "4,4,8,8")])
6752 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6753 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6754 (match_operand:DI 2 "reg_or_cint_operand" ""))
6756 (clobber (match_scratch:DI 3 ""))]
6757 "TARGET_POWERPC64 && reload_completed"
6759 (rotate:DI (match_dup 1) (match_dup 2)))
6761 (compare:CC (match_dup 3)
6765 (define_insn "*rotldi3_internal3"
6766 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6767 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6768 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6770 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6771 (rotate:DI (match_dup 1) (match_dup 2)))]
6778 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6779 (set_attr "length" "4,4,8,8")])
6782 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6783 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6784 (match_operand:DI 2 "reg_or_cint_operand" ""))
6786 (set (match_operand:DI 0 "gpc_reg_operand" "")
6787 (rotate:DI (match_dup 1) (match_dup 2)))]
6788 "TARGET_POWERPC64 && reload_completed"
6790 (rotate:DI (match_dup 1) (match_dup 2)))
6792 (compare:CC (match_dup 0)
6796 (define_insn "*rotldi3_internal4"
6797 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6798 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6799 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6800 (match_operand:DI 3 "mask64_operand" "n,n")))]
6803 rldc%B3 %0,%1,%2,%S3
6804 rldic%B3 %0,%1,%H2,%S3"
6805 [(set_attr "type" "var_shift_rotate,integer")])
6807 (define_insn "*rotldi3_internal5"
6808 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6810 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6811 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6812 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6814 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
6817 rldc%B3. %4,%1,%2,%S3
6818 rldic%B3. %4,%1,%H2,%S3
6821 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6822 (set_attr "length" "4,4,8,8")])
6825 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6827 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6828 (match_operand:DI 2 "reg_or_cint_operand" ""))
6829 (match_operand:DI 3 "mask64_operand" ""))
6831 (clobber (match_scratch:DI 4 ""))]
6832 "TARGET_POWERPC64 && reload_completed"
6834 (and:DI (rotate:DI (match_dup 1)
6838 (compare:CC (match_dup 4)
6842 (define_insn "*rotldi3_internal6"
6843 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
6845 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6846 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6847 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6849 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6850 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6853 rldc%B3. %0,%1,%2,%S3
6854 rldic%B3. %0,%1,%H2,%S3
6857 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6858 (set_attr "length" "4,4,8,8")])
6861 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6863 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6864 (match_operand:DI 2 "reg_or_cint_operand" ""))
6865 (match_operand:DI 3 "mask64_operand" ""))
6867 (set (match_operand:DI 0 "gpc_reg_operand" "")
6868 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6869 "TARGET_POWERPC64 && reload_completed"
6871 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6873 (compare:CC (match_dup 0)
6877 (define_insn "*rotldi3_internal7"
6878 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6881 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6882 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6886 rldicl %0,%1,%H2,56"
6887 [(set_attr "type" "var_shift_rotate,integer")])
6889 (define_insn "*rotldi3_internal8"
6890 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6891 (compare:CC (zero_extend:DI
6893 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6894 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6896 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6900 rldicl. %3,%1,%H2,56
6903 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6904 (set_attr "length" "4,4,8,8")])
6907 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6908 (compare:CC (zero_extend:DI
6910 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6911 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6913 (clobber (match_scratch:DI 3 ""))]
6914 "TARGET_POWERPC64 && reload_completed"
6916 (zero_extend:DI (subreg:QI
6917 (rotate:DI (match_dup 1)
6920 (compare:CC (match_dup 3)
6924 (define_insn "*rotldi3_internal9"
6925 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6926 (compare:CC (zero_extend:DI
6928 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6929 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6931 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6932 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6936 rldicl. %0,%1,%H2,56
6939 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6940 (set_attr "length" "4,4,8,8")])
6943 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6944 (compare:CC (zero_extend:DI
6946 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6947 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6949 (set (match_operand:DI 0 "gpc_reg_operand" "")
6950 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6951 "TARGET_POWERPC64 && reload_completed"
6953 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6955 (compare:CC (match_dup 0)
6959 (define_insn "*rotldi3_internal10"
6960 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6963 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6964 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6968 rldicl %0,%1,%H2,48"
6969 [(set_attr "type" "var_shift_rotate,integer")])
6971 (define_insn "*rotldi3_internal11"
6972 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6973 (compare:CC (zero_extend:DI
6975 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6976 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6978 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6982 rldicl. %3,%1,%H2,48
6985 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6986 (set_attr "length" "4,4,8,8")])
6989 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6990 (compare:CC (zero_extend:DI
6992 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6993 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6995 (clobber (match_scratch:DI 3 ""))]
6996 "TARGET_POWERPC64 && reload_completed"
6998 (zero_extend:DI (subreg:HI
6999 (rotate:DI (match_dup 1)
7002 (compare:CC (match_dup 3)
7006 (define_insn "*rotldi3_internal12"
7007 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7008 (compare:CC (zero_extend:DI
7010 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7011 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7013 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7014 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7018 rldicl. %0,%1,%H2,48
7021 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7022 (set_attr "length" "4,4,8,8")])
7025 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7026 (compare:CC (zero_extend:DI
7028 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7029 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7031 (set (match_operand:DI 0 "gpc_reg_operand" "")
7032 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7033 "TARGET_POWERPC64 && reload_completed"
7035 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7037 (compare:CC (match_dup 0)
7041 (define_insn "*rotldi3_internal13"
7042 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7045 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7046 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7050 rldicl %0,%1,%H2,32"
7051 [(set_attr "type" "var_shift_rotate,integer")])
7053 (define_insn "*rotldi3_internal14"
7054 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7055 (compare:CC (zero_extend:DI
7057 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7058 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7060 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7064 rldicl. %3,%1,%H2,32
7067 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7068 (set_attr "length" "4,4,8,8")])
7071 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7072 (compare:CC (zero_extend:DI
7074 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7075 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7077 (clobber (match_scratch:DI 3 ""))]
7078 "TARGET_POWERPC64 && reload_completed"
7080 (zero_extend:DI (subreg:SI
7081 (rotate:DI (match_dup 1)
7084 (compare:CC (match_dup 3)
7088 (define_insn "*rotldi3_internal15"
7089 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7090 (compare:CC (zero_extend:DI
7092 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7093 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7095 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7096 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7100 rldicl. %0,%1,%H2,32
7103 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7104 (set_attr "length" "4,4,8,8")])
7107 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7108 (compare:CC (zero_extend:DI
7110 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7111 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7113 (set (match_operand:DI 0 "gpc_reg_operand" "")
7114 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7115 "TARGET_POWERPC64 && reload_completed"
7117 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7119 (compare:CC (match_dup 0)
7123 (define_expand "ashldi3"
7124 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7125 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7126 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7127 "TARGET_POWERPC64 || TARGET_POWER"
7130 if (TARGET_POWERPC64)
7132 else if (TARGET_POWER)
7134 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
7141 (define_insn "*ashldi3_internal1"
7142 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7143 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7144 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7149 [(set_attr "type" "var_shift_rotate,shift")])
7151 (define_insn "*ashldi3_internal2"
7152 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7153 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7154 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7156 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7163 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7164 (set_attr "length" "4,4,8,8")])
7167 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7168 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7169 (match_operand:SI 2 "reg_or_cint_operand" ""))
7171 (clobber (match_scratch:DI 3 ""))]
7172 "TARGET_POWERPC64 && reload_completed"
7174 (ashift:DI (match_dup 1) (match_dup 2)))
7176 (compare:CC (match_dup 3)
7180 (define_insn "*ashldi3_internal3"
7181 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7182 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7183 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7185 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7186 (ashift:DI (match_dup 1) (match_dup 2)))]
7193 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7194 (set_attr "length" "4,4,8,8")])
7197 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7198 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7199 (match_operand:SI 2 "reg_or_cint_operand" ""))
7201 (set (match_operand:DI 0 "gpc_reg_operand" "")
7202 (ashift:DI (match_dup 1) (match_dup 2)))]
7203 "TARGET_POWERPC64 && reload_completed"
7205 (ashift:DI (match_dup 1) (match_dup 2)))
7207 (compare:CC (match_dup 0)
7211 (define_insn "*ashldi3_internal4"
7212 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7213 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7214 (match_operand:SI 2 "const_int_operand" "i"))
7215 (match_operand:DI 3 "const_int_operand" "n")))]
7216 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7217 "rldic %0,%1,%H2,%W3")
7219 (define_insn "ashldi3_internal5"
7220 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7222 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7223 (match_operand:SI 2 "const_int_operand" "i,i"))
7224 (match_operand:DI 3 "const_int_operand" "n,n"))
7226 (clobber (match_scratch:DI 4 "=r,r"))]
7227 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7229 rldic. %4,%1,%H2,%W3
7231 [(set_attr "type" "compare")
7232 (set_attr "length" "4,8")])
7235 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7237 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7238 (match_operand:SI 2 "const_int_operand" ""))
7239 (match_operand:DI 3 "const_int_operand" ""))
7241 (clobber (match_scratch:DI 4 ""))]
7242 "TARGET_POWERPC64 && reload_completed
7243 && includes_rldic_lshift_p (operands[2], operands[3])"
7245 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7248 (compare:CC (match_dup 4)
7252 (define_insn "*ashldi3_internal6"
7253 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7255 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7256 (match_operand:SI 2 "const_int_operand" "i,i"))
7257 (match_operand:DI 3 "const_int_operand" "n,n"))
7259 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7260 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7261 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7263 rldic. %0,%1,%H2,%W3
7265 [(set_attr "type" "compare")
7266 (set_attr "length" "4,8")])
7269 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7271 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7272 (match_operand:SI 2 "const_int_operand" ""))
7273 (match_operand:DI 3 "const_int_operand" ""))
7275 (set (match_operand:DI 0 "gpc_reg_operand" "")
7276 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7277 "TARGET_POWERPC64 && reload_completed
7278 && includes_rldic_lshift_p (operands[2], operands[3])"
7280 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7283 (compare:CC (match_dup 0)
7287 (define_insn "*ashldi3_internal7"
7288 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7289 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7290 (match_operand:SI 2 "const_int_operand" "i"))
7291 (match_operand:DI 3 "mask64_operand" "n")))]
7292 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7293 "rldicr %0,%1,%H2,%S3")
7295 (define_insn "ashldi3_internal8"
7296 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7298 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7299 (match_operand:SI 2 "const_int_operand" "i,i"))
7300 (match_operand:DI 3 "mask64_operand" "n,n"))
7302 (clobber (match_scratch:DI 4 "=r,r"))]
7303 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7305 rldicr. %4,%1,%H2,%S3
7307 [(set_attr "type" "compare")
7308 (set_attr "length" "4,8")])
7311 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7313 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7314 (match_operand:SI 2 "const_int_operand" ""))
7315 (match_operand:DI 3 "mask64_operand" ""))
7317 (clobber (match_scratch:DI 4 ""))]
7318 "TARGET_POWERPC64 && reload_completed
7319 && includes_rldicr_lshift_p (operands[2], operands[3])"
7321 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7324 (compare:CC (match_dup 4)
7328 (define_insn "*ashldi3_internal9"
7329 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7331 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7332 (match_operand:SI 2 "const_int_operand" "i,i"))
7333 (match_operand:DI 3 "mask64_operand" "n,n"))
7335 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7336 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7337 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7339 rldicr. %0,%1,%H2,%S3
7341 [(set_attr "type" "compare")
7342 (set_attr "length" "4,8")])
7345 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7347 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7348 (match_operand:SI 2 "const_int_operand" ""))
7349 (match_operand:DI 3 "mask64_operand" ""))
7351 (set (match_operand:DI 0 "gpc_reg_operand" "")
7352 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7353 "TARGET_POWERPC64 && reload_completed
7354 && includes_rldicr_lshift_p (operands[2], operands[3])"
7356 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7359 (compare:CC (match_dup 0)
7363 (define_expand "lshrdi3"
7364 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7365 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7366 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7367 "TARGET_POWERPC64 || TARGET_POWER"
7370 if (TARGET_POWERPC64)
7372 else if (TARGET_POWER)
7374 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7381 (define_insn "*lshrdi3_internal1"
7382 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7383 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7384 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7389 [(set_attr "type" "var_shift_rotate,shift")])
7391 (define_insn "*lshrdi3_internal2"
7392 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7393 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7394 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7396 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7403 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7404 (set_attr "length" "4,4,8,8")])
7407 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7408 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7409 (match_operand:SI 2 "reg_or_cint_operand" ""))
7411 (clobber (match_scratch:DI 3 ""))]
7412 "TARGET_POWERPC64 && reload_completed"
7414 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7416 (compare:CC (match_dup 3)
7420 (define_insn "*lshrdi3_internal3"
7421 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7422 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7423 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7425 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7426 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7433 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7434 (set_attr "length" "4,4,8,8")])
7437 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7438 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7439 (match_operand:SI 2 "reg_or_cint_operand" ""))
7441 (set (match_operand:DI 0 "gpc_reg_operand" "")
7442 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7443 "TARGET_POWERPC64 && reload_completed"
7445 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7447 (compare:CC (match_dup 0)
7451 (define_expand "ashrdi3"
7452 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7453 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7454 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7458 if (TARGET_POWERPC64)
7460 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7462 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7465 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7466 && WORDS_BIG_ENDIAN)
7468 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7475 (define_insn "*ashrdi3_internal1"
7476 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7477 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7478 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7483 [(set_attr "type" "var_shift_rotate,shift")])
7485 (define_insn "*ashrdi3_internal2"
7486 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7487 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7488 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7490 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7497 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7498 (set_attr "length" "4,4,8,8")])
7501 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7502 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7503 (match_operand:SI 2 "reg_or_cint_operand" ""))
7505 (clobber (match_scratch:DI 3 ""))]
7506 "TARGET_POWERPC64 && reload_completed"
7508 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7510 (compare:CC (match_dup 3)
7514 (define_insn "*ashrdi3_internal3"
7515 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7516 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7517 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7519 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7520 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7527 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7528 (set_attr "length" "4,4,8,8")])
7531 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7532 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7533 (match_operand:SI 2 "reg_or_cint_operand" ""))
7535 (set (match_operand:DI 0 "gpc_reg_operand" "")
7536 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7537 "TARGET_POWERPC64 && reload_completed"
7539 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7541 (compare:CC (match_dup 0)
7545 (define_insn "anddi3"
7546 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7547 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7548 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7549 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7553 rldic%B2 %0,%1,0,%S2
7554 rlwinm %0,%1,0,%m2,%M2
7558 [(set_attr "type" "*,*,*,compare,compare,*")
7559 (set_attr "length" "4,4,4,4,4,8")])
7562 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7563 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7564 (match_operand:DI 2 "mask64_2_operand" "")))
7565 (clobber (match_scratch:CC 3 ""))]
7567 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7568 && !mask_operand (operands[2], DImode)
7569 && !mask64_operand (operands[2], DImode)"
7571 (and:DI (rotate:DI (match_dup 1)
7575 (and:DI (rotate:DI (match_dup 0)
7579 build_mask64_2_operands (operands[2], &operands[4]);
7582 (define_insn "*anddi3_internal2"
7583 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7584 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7585 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7587 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7588 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7592 rldic%B2. %3,%1,0,%S2
7593 rlwinm. %3,%1,0,%m2,%M2
7603 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7604 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7607 [(set (match_operand:CC 0 "cc_reg_operand" "")
7608 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7609 (match_operand:DI 2 "mask64_2_operand" ""))
7611 (clobber (match_scratch:DI 3 ""))
7612 (clobber (match_scratch:CC 4 ""))]
7613 "TARGET_64BIT && reload_completed
7614 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7615 && !mask_operand (operands[2], DImode)
7616 && !mask64_operand (operands[2], DImode)"
7618 (and:DI (rotate:DI (match_dup 1)
7621 (parallel [(set (match_dup 0)
7622 (compare:CC (and:DI (rotate:DI (match_dup 3)
7626 (clobber (match_dup 3))])]
7629 build_mask64_2_operands (operands[2], &operands[5]);
7632 (define_insn "*anddi3_internal3"
7633 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7634 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7635 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7637 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
7638 (and:DI (match_dup 1) (match_dup 2)))
7639 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7643 rldic%B2. %0,%1,0,%S2
7644 rlwinm. %0,%1,0,%m2,%M2
7654 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7655 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7658 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7659 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7660 (match_operand:DI 2 "and64_2_operand" ""))
7662 (set (match_operand:DI 0 "gpc_reg_operand" "")
7663 (and:DI (match_dup 1) (match_dup 2)))
7664 (clobber (match_scratch:CC 4 ""))]
7665 "TARGET_64BIT && reload_completed"
7666 [(parallel [(set (match_dup 0)
7667 (and:DI (match_dup 1) (match_dup 2)))
7668 (clobber (match_dup 4))])
7670 (compare:CC (match_dup 0)
7675 [(set (match_operand:CC 3 "cc_reg_operand" "")
7676 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7677 (match_operand:DI 2 "mask64_2_operand" ""))
7679 (set (match_operand:DI 0 "gpc_reg_operand" "")
7680 (and:DI (match_dup 1) (match_dup 2)))
7681 (clobber (match_scratch:CC 4 ""))]
7682 "TARGET_64BIT && reload_completed
7683 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7684 && !mask_operand (operands[2], DImode)
7685 && !mask64_operand (operands[2], DImode)"
7687 (and:DI (rotate:DI (match_dup 1)
7690 (parallel [(set (match_dup 3)
7691 (compare:CC (and:DI (rotate:DI (match_dup 0)
7696 (and:DI (rotate:DI (match_dup 0)
7701 build_mask64_2_operands (operands[2], &operands[5]);
7704 (define_expand "iordi3"
7705 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7706 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7707 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7711 if (non_logical_cint_operand (operands[2], DImode))
7713 HOST_WIDE_INT value;
7714 rtx tmp = ((!can_create_pseudo_p ()
7715 || rtx_equal_p (operands[0], operands[1]))
7716 ? operands[0] : gen_reg_rtx (DImode));
7718 if (GET_CODE (operands[2]) == CONST_INT)
7720 value = INTVAL (operands[2]);
7721 emit_insn (gen_iordi3 (tmp, operands[1],
7722 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7726 value = CONST_DOUBLE_LOW (operands[2]);
7727 emit_insn (gen_iordi3 (tmp, operands[1],
7728 immed_double_const (value
7729 & (~ (HOST_WIDE_INT) 0xffff),
7733 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7738 (define_expand "xordi3"
7739 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7740 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7741 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7745 if (non_logical_cint_operand (operands[2], DImode))
7747 HOST_WIDE_INT value;
7748 rtx tmp = ((!can_create_pseudo_p ()
7749 || rtx_equal_p (operands[0], operands[1]))
7750 ? operands[0] : gen_reg_rtx (DImode));
7752 if (GET_CODE (operands[2]) == CONST_INT)
7754 value = INTVAL (operands[2]);
7755 emit_insn (gen_xordi3 (tmp, operands[1],
7756 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7760 value = CONST_DOUBLE_LOW (operands[2]);
7761 emit_insn (gen_xordi3 (tmp, operands[1],
7762 immed_double_const (value
7763 & (~ (HOST_WIDE_INT) 0xffff),
7767 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7772 (define_insn "*booldi3_internal1"
7773 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7774 (match_operator:DI 3 "boolean_or_operator"
7775 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7776 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7783 (define_insn "*booldi3_internal2"
7784 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7785 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7786 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7787 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7789 (clobber (match_scratch:DI 3 "=r,r"))]
7794 [(set_attr "type" "compare")
7795 (set_attr "length" "4,8")])
7798 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7799 (compare:CC (match_operator:DI 4 "boolean_operator"
7800 [(match_operand:DI 1 "gpc_reg_operand" "")
7801 (match_operand:DI 2 "gpc_reg_operand" "")])
7803 (clobber (match_scratch:DI 3 ""))]
7804 "TARGET_POWERPC64 && reload_completed"
7805 [(set (match_dup 3) (match_dup 4))
7807 (compare:CC (match_dup 3)
7811 (define_insn "*booldi3_internal3"
7812 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7813 (compare:CC (match_operator:DI 4 "boolean_operator"
7814 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7815 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7817 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7823 [(set_attr "type" "compare")
7824 (set_attr "length" "4,8")])
7827 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7828 (compare:CC (match_operator:DI 4 "boolean_operator"
7829 [(match_operand:DI 1 "gpc_reg_operand" "")
7830 (match_operand:DI 2 "gpc_reg_operand" "")])
7832 (set (match_operand:DI 0 "gpc_reg_operand" "")
7834 "TARGET_POWERPC64 && reload_completed"
7835 [(set (match_dup 0) (match_dup 4))
7837 (compare:CC (match_dup 0)
7841 ;; Split a logical operation that we can't do in one insn into two insns,
7842 ;; each of which does one 16-bit part. This is used by combine.
7845 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7846 (match_operator:DI 3 "boolean_or_operator"
7847 [(match_operand:DI 1 "gpc_reg_operand" "")
7848 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7850 [(set (match_dup 0) (match_dup 4))
7851 (set (match_dup 0) (match_dup 5))]
7856 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7858 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7859 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7861 i4 = GEN_INT (value & 0xffff);
7865 i3 = GEN_INT (INTVAL (operands[2])
7866 & (~ (HOST_WIDE_INT) 0xffff));
7867 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7869 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7871 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7875 (define_insn "*boolcdi3_internal1"
7876 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7877 (match_operator:DI 3 "boolean_operator"
7878 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7879 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7883 (define_insn "*boolcdi3_internal2"
7884 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7885 (compare:CC (match_operator:DI 4 "boolean_operator"
7886 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7887 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7889 (clobber (match_scratch:DI 3 "=r,r"))]
7894 [(set_attr "type" "compare")
7895 (set_attr "length" "4,8")])
7898 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7899 (compare:CC (match_operator:DI 4 "boolean_operator"
7900 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7901 (match_operand:DI 2 "gpc_reg_operand" "")])
7903 (clobber (match_scratch:DI 3 ""))]
7904 "TARGET_POWERPC64 && reload_completed"
7905 [(set (match_dup 3) (match_dup 4))
7907 (compare:CC (match_dup 3)
7911 (define_insn "*boolcdi3_internal3"
7912 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7913 (compare:CC (match_operator:DI 4 "boolean_operator"
7914 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7915 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7917 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7923 [(set_attr "type" "compare")
7924 (set_attr "length" "4,8")])
7927 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7928 (compare:CC (match_operator:DI 4 "boolean_operator"
7929 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7930 (match_operand:DI 2 "gpc_reg_operand" "")])
7932 (set (match_operand:DI 0 "gpc_reg_operand" "")
7934 "TARGET_POWERPC64 && reload_completed"
7935 [(set (match_dup 0) (match_dup 4))
7937 (compare:CC (match_dup 0)
7941 (define_insn "*boolccdi3_internal1"
7942 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7943 (match_operator:DI 3 "boolean_operator"
7944 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7945 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7949 (define_insn "*boolccdi3_internal2"
7950 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7951 (compare:CC (match_operator:DI 4 "boolean_operator"
7952 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7953 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7955 (clobber (match_scratch:DI 3 "=r,r"))]
7960 [(set_attr "type" "compare")
7961 (set_attr "length" "4,8")])
7964 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7965 (compare:CC (match_operator:DI 4 "boolean_operator"
7966 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7967 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7969 (clobber (match_scratch:DI 3 ""))]
7970 "TARGET_POWERPC64 && reload_completed"
7971 [(set (match_dup 3) (match_dup 4))
7973 (compare:CC (match_dup 3)
7977 (define_insn "*boolccdi3_internal3"
7978 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7979 (compare:CC (match_operator:DI 4 "boolean_operator"
7980 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7981 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7983 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7989 [(set_attr "type" "compare")
7990 (set_attr "length" "4,8")])
7993 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7994 (compare:CC (match_operator:DI 4 "boolean_operator"
7995 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7996 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7998 (set (match_operand:DI 0 "gpc_reg_operand" "")
8000 "TARGET_POWERPC64 && reload_completed"
8001 [(set (match_dup 0) (match_dup 4))
8003 (compare:CC (match_dup 0)
8007 ;; Now define ways of moving data around.
8009 ;; Set up a register with a value from the GOT table
8011 (define_expand "movsi_got"
8012 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8013 (unspec:SI [(match_operand:SI 1 "got_operand" "")
8014 (match_dup 2)] UNSPEC_MOVSI_GOT))]
8015 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8018 if (GET_CODE (operands[1]) == CONST)
8020 rtx offset = const0_rtx;
8021 HOST_WIDE_INT value;
8023 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8024 value = INTVAL (offset);
8027 rtx tmp = (!can_create_pseudo_p ()
8029 : gen_reg_rtx (Pmode));
8030 emit_insn (gen_movsi_got (tmp, operands[1]));
8031 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8036 operands[2] = rs6000_got_register (operands[1]);
8039 (define_insn "*movsi_got_internal"
8040 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8041 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8042 (match_operand:SI 2 "gpc_reg_operand" "b")]
8044 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8045 "{l|lwz} %0,%a1@got(%2)"
8046 [(set_attr "type" "load")])
8048 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
8049 ;; didn't get allocated to a hard register.
8051 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8052 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8053 (match_operand:SI 2 "memory_operand" "")]
8055 "DEFAULT_ABI == ABI_V4
8057 && (reload_in_progress || reload_completed)"
8058 [(set (match_dup 0) (match_dup 2))
8059 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8063 ;; For SI, we special-case integers that can't be loaded in one insn. We
8064 ;; do the load 16-bits at a time. We could do this by loading from memory,
8065 ;; and this is even supposed to be faster, but it is simpler not to get
8066 ;; integers in the TOC.
8067 (define_insn "movsi_low"
8068 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8069 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
8070 (match_operand 2 "" ""))))]
8071 "TARGET_MACHO && ! TARGET_64BIT"
8072 "{l|lwz} %0,lo16(%2)(%1)"
8073 [(set_attr "type" "load")
8074 (set_attr "length" "4")])
8076 (define_insn "*movsi_internal1"
8077 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
8078 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
8079 "gpc_reg_operand (operands[0], SImode)
8080 || gpc_reg_operand (operands[1], SImode)"
8084 {l%U1%X1|lwz%U1%X1} %0,%1
8085 {st%U0%X0|stw%U0%X0} %1,%0
8095 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
8096 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
8098 ;; Split a load of a large constant into the appropriate two-insn
8102 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8103 (match_operand:SI 1 "const_int_operand" ""))]
8104 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
8105 && (INTVAL (operands[1]) & 0xffff) != 0"
8109 (ior:SI (match_dup 0)
8112 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8114 if (tem == operands[0])
8120 (define_insn "*mov<mode>_internal2"
8121 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8122 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
8124 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8127 {cmpi|cmp<wd>i} %2,%0,0
8130 [(set_attr "type" "cmp,compare,cmp")
8131 (set_attr "length" "4,4,8")])
8134 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8135 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
8137 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8139 [(set (match_dup 0) (match_dup 1))
8141 (compare:CC (match_dup 0)
8145 (define_insn "*movhi_internal"
8146 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8147 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8148 "gpc_reg_operand (operands[0], HImode)
8149 || gpc_reg_operand (operands[1], HImode)"
8159 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8161 (define_expand "mov<mode>"
8162 [(set (match_operand:INT 0 "general_operand" "")
8163 (match_operand:INT 1 "any_operand" ""))]
8165 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8167 (define_insn "*movqi_internal"
8168 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8169 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8170 "gpc_reg_operand (operands[0], QImode)
8171 || gpc_reg_operand (operands[1], QImode)"
8181 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8183 ;; Here is how to move condition codes around. When we store CC data in
8184 ;; an integer register or memory, we store just the high-order 4 bits.
8185 ;; This lets us not shift in the most common case of CR0.
8186 (define_expand "movcc"
8187 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8188 (match_operand:CC 1 "nonimmediate_operand" ""))]
8192 (define_insn "*movcc_internal1"
8193 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
8194 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
8195 "register_operand (operands[0], CCmode)
8196 || register_operand (operands[1], CCmode)"
8200 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
8203 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
8209 {l%U1%X1|lwz%U1%X1} %0,%1
8210 {st%U0%U1|stw%U0%U1} %1,%0"
8212 (cond [(eq_attr "alternative" "0,3")
8213 (const_string "cr_logical")
8214 (eq_attr "alternative" "1,2")
8215 (const_string "mtcr")
8216 (eq_attr "alternative" "6,7,9")
8217 (const_string "integer")
8218 (eq_attr "alternative" "8")
8219 (const_string "mfjmpr")
8220 (eq_attr "alternative" "10")
8221 (const_string "mtjmpr")
8222 (eq_attr "alternative" "11")
8223 (const_string "load")
8224 (eq_attr "alternative" "12")
8225 (const_string "store")
8226 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
8227 (const_string "mfcrf")
8229 (const_string "mfcr")))
8230 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
8232 ;; For floating-point, we normally deal with the floating-point registers
8233 ;; unless -msoft-float is used. The sole exception is that parameter passing
8234 ;; can produce floating-point values in fixed-point registers. Unless the
8235 ;; value is a simple constant or already in memory, we deal with this by
8236 ;; allocating memory and copying the value explicitly via that memory location.
8237 (define_expand "movsf"
8238 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8239 (match_operand:SF 1 "any_operand" ""))]
8241 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
8244 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8245 (match_operand:SF 1 "const_double_operand" ""))]
8247 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8248 || (GET_CODE (operands[0]) == SUBREG
8249 && GET_CODE (SUBREG_REG (operands[0])) == REG
8250 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8251 [(set (match_dup 2) (match_dup 3))]
8257 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8258 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
8260 if (! TARGET_POWERPC64)
8261 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
8263 operands[2] = gen_lowpart (SImode, operands[0]);
8265 operands[3] = gen_int_mode (l, SImode);
8268 (define_insn "*movsf_hardfloat"
8269 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
8270 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
8271 "(gpc_reg_operand (operands[0], SFmode)
8272 || gpc_reg_operand (operands[1], SFmode))
8273 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
8276 {l%U1%X1|lwz%U1%X1} %0,%1
8277 {st%U0%X0|stw%U0%X0} %1,%0
8287 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
8288 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
8290 (define_insn "*movsf_softfloat"
8291 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
8292 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
8293 "(gpc_reg_operand (operands[0], SFmode)
8294 || gpc_reg_operand (operands[1], SFmode))
8295 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
8301 {l%U1%X1|lwz%U1%X1} %0,%1
8302 {st%U0%X0|stw%U0%X0} %1,%0
8309 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
8310 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
8313 (define_expand "movdf"
8314 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8315 (match_operand:DF 1 "any_operand" ""))]
8317 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
8320 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8321 (match_operand:DF 1 "const_int_operand" ""))]
8322 "! TARGET_POWERPC64 && reload_completed
8323 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8324 || (GET_CODE (operands[0]) == SUBREG
8325 && GET_CODE (SUBREG_REG (operands[0])) == REG
8326 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8327 [(set (match_dup 2) (match_dup 4))
8328 (set (match_dup 3) (match_dup 1))]
8331 int endian = (WORDS_BIG_ENDIAN == 0);
8332 HOST_WIDE_INT value = INTVAL (operands[1]);
8334 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8335 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8336 #if HOST_BITS_PER_WIDE_INT == 32
8337 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8339 operands[4] = GEN_INT (value >> 32);
8340 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8345 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8346 (match_operand:DF 1 "const_double_operand" ""))]
8347 "! TARGET_POWERPC64 && reload_completed
8348 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8349 || (GET_CODE (operands[0]) == SUBREG
8350 && GET_CODE (SUBREG_REG (operands[0])) == REG
8351 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8352 [(set (match_dup 2) (match_dup 4))
8353 (set (match_dup 3) (match_dup 5))]
8356 int endian = (WORDS_BIG_ENDIAN == 0);
8360 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8361 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8363 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8364 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8365 operands[4] = gen_int_mode (l[endian], SImode);
8366 operands[5] = gen_int_mode (l[1 - endian], SImode);
8370 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8371 (match_operand:DF 1 "const_double_operand" ""))]
8372 "TARGET_POWERPC64 && reload_completed
8373 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8374 || (GET_CODE (operands[0]) == SUBREG
8375 && GET_CODE (SUBREG_REG (operands[0])) == REG
8376 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8377 [(set (match_dup 2) (match_dup 3))]
8380 int endian = (WORDS_BIG_ENDIAN == 0);
8383 #if HOST_BITS_PER_WIDE_INT >= 64
8387 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8388 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8390 operands[2] = gen_lowpart (DImode, operands[0]);
8391 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8392 #if HOST_BITS_PER_WIDE_INT >= 64
8393 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8394 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8396 operands[3] = gen_int_mode (val, DImode);
8398 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8402 ;; Don't have reload use general registers to load a constant. First,
8403 ;; it might not work if the output operand is the equivalent of
8404 ;; a non-offsettable memref, but also it is less efficient than loading
8405 ;; the constant into an FP register, since it will probably be used there.
8406 ;; The "??" is a kludge until we can figure out a more reasonable way
8407 ;; of handling these non-offsettable values.
8408 (define_insn "*movdf_hardfloat32"
8409 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8410 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
8411 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8412 && (gpc_reg_operand (operands[0], DFmode)
8413 || gpc_reg_operand (operands[1], DFmode))"
8416 switch (which_alternative)
8421 /* We normally copy the low-numbered register first. However, if
8422 the first register operand 0 is the same as the second register
8423 of operand 1, we must copy in the opposite order. */
8424 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8425 return \"mr %L0,%L1\;mr %0,%1\";
8427 return \"mr %0,%1\;mr %L0,%L1\";
8429 if (rs6000_offsettable_memref_p (operands[1])
8430 || (GET_CODE (operands[1]) == MEM
8431 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8432 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8433 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC
8434 || GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)))
8436 /* If the low-address word is used in the address, we must load
8437 it last. Otherwise, load it first. Note that we cannot have
8438 auto-increment in that case since the address register is
8439 known to be dead. */
8440 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8442 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8444 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
8450 addreg = find_addr_reg (XEXP (operands[1], 0));
8451 if (refers_to_regno_p (REGNO (operands[0]),
8452 REGNO (operands[0]) + 1,
8455 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8456 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
8457 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8458 return \"{l%X1|lwz%X1} %0,%1\";
8462 output_asm_insn (\"{l%X1|lwz%X1} %0,%1\", operands);
8463 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8464 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
8465 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8470 if (rs6000_offsettable_memref_p (operands[0])
8471 || (GET_CODE (operands[0]) == MEM
8472 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8473 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8474 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
8475 || GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)))
8476 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
8481 addreg = find_addr_reg (XEXP (operands[0], 0));
8482 output_asm_insn (\"{st%X0|stw%X0} %1,%0\", operands);
8483 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8484 output_asm_insn (\"{st%X0|stw%X0} %L1,%0\", operands);
8485 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8489 return \"fmr %0,%1\";
8491 return \"lfd%U1%X1 %0,%1\";
8493 return \"stfd%U0%X0 %1,%0\";
8500 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
8501 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
8503 (define_insn "*movdf_softfloat32"
8504 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8505 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8506 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8507 && (gpc_reg_operand (operands[0], DFmode)
8508 || gpc_reg_operand (operands[1], DFmode))"
8511 switch (which_alternative)
8516 /* We normally copy the low-numbered register first. However, if
8517 the first register operand 0 is the same as the second register of
8518 operand 1, we must copy in the opposite order. */
8519 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8520 return \"mr %L0,%L1\;mr %0,%1\";
8522 return \"mr %0,%1\;mr %L0,%L1\";
8524 /* If the low-address word is used in the address, we must load
8525 it last. Otherwise, load it first. Note that we cannot have
8526 auto-increment in that case since the address register is
8527 known to be dead. */
8528 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8530 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8532 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
8534 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
8541 [(set_attr "type" "two,load,store,*,*,*")
8542 (set_attr "length" "8,8,8,8,12,16")])
8544 ; ld/std require word-aligned displacements -> 'Y' constraint.
8545 ; List Y->r and r->Y before r->r for reload.
8546 (define_insn "*movdf_hardfloat64_mfpgpr"
8547 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f")
8548 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))]
8549 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8550 && (gpc_reg_operand (operands[0], DFmode)
8551 || gpc_reg_operand (operands[1], DFmode))"
8567 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
8568 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
8570 ; ld/std require word-aligned displacements -> 'Y' constraint.
8571 ; List Y->r and r->Y before r->r for reload.
8572 (define_insn "*movdf_hardfloat64"
8573 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
8574 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
8575 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8576 && (gpc_reg_operand (operands[0], DFmode)
8577 || gpc_reg_operand (operands[1], DFmode))"
8591 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
8592 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
8594 (define_insn "*movdf_softfloat64"
8595 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8596 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
8597 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8598 && (gpc_reg_operand (operands[0], DFmode)
8599 || gpc_reg_operand (operands[1], DFmode))"
8610 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
8611 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8613 (define_expand "movtf"
8614 [(set (match_operand:TF 0 "general_operand" "")
8615 (match_operand:TF 1 "any_operand" ""))]
8616 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
8617 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8619 ; It's important to list the o->f and f->o moves before f->f because
8620 ; otherwise reload, given m->f, will try to pick f->f and reload it,
8621 ; which doesn't make progress. Likewise r->Y must be before r->r.
8622 (define_insn_and_split "*movtf_internal"
8623 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
8624 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
8626 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8627 && (gpc_reg_operand (operands[0], TFmode)
8628 || gpc_reg_operand (operands[1], TFmode))"
8630 "&& reload_completed"
8632 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8633 [(set_attr "length" "8,8,8,20,20,16")])
8635 (define_insn_and_split "*movtf_softfloat"
8636 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
8637 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
8639 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
8640 && (gpc_reg_operand (operands[0], TFmode)
8641 || gpc_reg_operand (operands[1], TFmode))"
8643 "&& reload_completed"
8645 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8646 [(set_attr "length" "20,20,16")])
8648 (define_expand "extenddftf2"
8649 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8650 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8652 && TARGET_HARD_FLOAT
8653 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8654 && TARGET_LONG_DOUBLE_128"
8656 if (TARGET_E500_DOUBLE)
8657 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8659 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8663 (define_expand "extenddftf2_fprs"
8664 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8665 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8666 (use (match_dup 2))])]
8668 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8670 operands[2] = CONST0_RTX (DFmode);
8671 /* Generate GOT reference early for SVR4 PIC. */
8672 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8673 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8676 (define_insn_and_split "*extenddftf2_internal"
8677 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8678 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8679 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
8681 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8683 "&& reload_completed"
8686 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8687 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8688 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8690 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8695 (define_expand "extendsftf2"
8696 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8697 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8699 && TARGET_HARD_FLOAT
8700 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8701 && TARGET_LONG_DOUBLE_128"
8703 rtx tmp = gen_reg_rtx (DFmode);
8704 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8705 emit_insn (gen_extenddftf2 (operands[0], tmp));
8709 (define_expand "trunctfdf2"
8710 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8711 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8713 && TARGET_HARD_FLOAT
8714 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8715 && TARGET_LONG_DOUBLE_128"
8718 (define_insn_and_split "trunctfdf2_internal1"
8719 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8720 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
8721 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8722 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8726 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8729 emit_note (NOTE_INSN_DELETED);
8732 [(set_attr "type" "fp")])
8734 (define_insn "trunctfdf2_internal2"
8735 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8736 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8737 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8738 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8740 [(set_attr "type" "fp")])
8742 (define_expand "trunctfsf2"
8743 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8744 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8746 && TARGET_HARD_FLOAT
8747 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8748 && TARGET_LONG_DOUBLE_128"
8750 if (TARGET_E500_DOUBLE)
8751 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8753 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8757 (define_insn_and_split "trunctfsf2_fprs"
8758 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8759 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8760 (clobber (match_scratch:DF 2 "=f"))]
8762 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8764 "&& reload_completed"
8766 (float_truncate:DF (match_dup 1)))
8768 (float_truncate:SF (match_dup 2)))]
8771 (define_expand "floatsitf2"
8772 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8773 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
8775 && TARGET_HARD_FLOAT
8776 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8777 && TARGET_LONG_DOUBLE_128"
8779 rtx tmp = gen_reg_rtx (DFmode);
8780 expand_float (tmp, operands[1], false);
8781 emit_insn (gen_extenddftf2 (operands[0], tmp));
8785 ; fadd, but rounding towards zero.
8786 ; This is probably not the optimal code sequence.
8787 (define_insn "fix_trunc_helper"
8788 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8789 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8790 UNSPEC_FIX_TRUNC_TF))
8791 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8792 "TARGET_HARD_FLOAT && TARGET_FPRS"
8793 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8794 [(set_attr "type" "fp")
8795 (set_attr "length" "20")])
8797 (define_expand "fix_trunctfsi2"
8798 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8799 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8801 && (TARGET_POWER2 || TARGET_POWERPC)
8802 && TARGET_HARD_FLOAT
8803 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8804 && TARGET_LONG_DOUBLE_128"
8806 if (TARGET_E500_DOUBLE)
8807 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8809 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8813 (define_expand "fix_trunctfsi2_fprs"
8814 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8815 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8816 (clobber (match_dup 2))
8817 (clobber (match_dup 3))
8818 (clobber (match_dup 4))
8819 (clobber (match_dup 5))])]
8821 && (TARGET_POWER2 || TARGET_POWERPC)
8822 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8824 operands[2] = gen_reg_rtx (DFmode);
8825 operands[3] = gen_reg_rtx (DFmode);
8826 operands[4] = gen_reg_rtx (DImode);
8827 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8830 (define_insn_and_split "*fix_trunctfsi2_internal"
8831 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8832 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8833 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8834 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8835 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8836 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
8838 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8840 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[5]))"
8844 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8846 gcc_assert (MEM_P (operands[5]));
8847 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8849 emit_insn (gen_fctiwz (operands[4], operands[2]));
8850 emit_move_insn (operands[5], operands[4]);
8851 emit_move_insn (operands[0], lowword);
8855 (define_expand "negtf2"
8856 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8857 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8859 && TARGET_HARD_FLOAT
8860 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8861 && TARGET_LONG_DOUBLE_128"
8864 (define_insn "negtf2_internal"
8865 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8866 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8868 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8871 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8872 return \"fneg %L0,%L1\;fneg %0,%1\";
8874 return \"fneg %0,%1\;fneg %L0,%L1\";
8876 [(set_attr "type" "fp")
8877 (set_attr "length" "8")])
8879 (define_expand "abstf2"
8880 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8881 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8883 && TARGET_HARD_FLOAT
8884 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8885 && TARGET_LONG_DOUBLE_128"
8888 rtx label = gen_label_rtx ();
8889 if (TARGET_E500_DOUBLE)
8891 if (flag_unsafe_math_optimizations)
8892 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
8894 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
8897 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8902 (define_expand "abstf2_internal"
8903 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8904 (match_operand:TF 1 "gpc_reg_operand" ""))
8905 (set (match_dup 3) (match_dup 5))
8906 (set (match_dup 5) (abs:DF (match_dup 5)))
8907 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8908 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8909 (label_ref (match_operand 2 "" ""))
8911 (set (match_dup 6) (neg:DF (match_dup 6)))]
8913 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8916 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8917 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8918 operands[3] = gen_reg_rtx (DFmode);
8919 operands[4] = gen_reg_rtx (CCFPmode);
8920 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8921 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8924 ;; Next come the multi-word integer load and store and the load and store
8927 ; List r->r after r->"o<>", otherwise reload will try to reload a
8928 ; non-offsettable address by using r->r which won't make progress.
8929 (define_insn "*movdi_internal32"
8930 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
8931 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
8933 && (gpc_reg_operand (operands[0], DImode)
8934 || gpc_reg_operand (operands[1], DImode))"
8943 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
8946 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8947 (match_operand:DI 1 "const_int_operand" ""))]
8948 "! TARGET_POWERPC64 && reload_completed"
8949 [(set (match_dup 2) (match_dup 4))
8950 (set (match_dup 3) (match_dup 1))]
8953 HOST_WIDE_INT value = INTVAL (operands[1]);
8954 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8956 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8958 #if HOST_BITS_PER_WIDE_INT == 32
8959 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8961 operands[4] = GEN_INT (value >> 32);
8962 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8967 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "")
8968 (match_operand:DI 1 "input_operand" ""))]
8969 "reload_completed && !TARGET_POWERPC64
8970 && gpr_or_gpr_p (operands[0], operands[1])"
8972 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8974 (define_insn "*movdi_mfpgpr"
8975 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h,r,*f")
8976 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0,*f,r"))]
8977 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8978 && (gpc_reg_operand (operands[0], DImode)
8979 || gpc_reg_operand (operands[1], DImode))"
8996 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
8997 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
8999 (define_insn "*movdi_internal64"
9000 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
9001 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
9002 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
9003 && (gpc_reg_operand (operands[0], DImode)
9004 || gpc_reg_operand (operands[1], DImode))"
9019 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
9020 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
9022 ;; immediate value valid for a single instruction hiding in a const_double
9024 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9025 (match_operand:DI 1 "const_double_operand" "F"))]
9026 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
9027 && GET_CODE (operands[1]) == CONST_DOUBLE
9028 && num_insns_constant (operands[1], DImode) == 1"
9031 return ((unsigned HOST_WIDE_INT)
9032 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
9033 ? \"li %0,%1\" : \"lis %0,%v1\";
9036 ;; Generate all one-bits and clear left or right.
9037 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9039 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9040 (match_operand:DI 1 "mask64_operand" ""))]
9041 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9042 [(set (match_dup 0) (const_int -1))
9044 (and:DI (rotate:DI (match_dup 0)
9049 ;; Split a load of a large constant into the appropriate five-instruction
9050 ;; sequence. Handle anything in a constant number of insns.
9051 ;; When non-easy constants can go in the TOC, this should use
9052 ;; easy_fp_constant predicate.
9054 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9055 (match_operand:DI 1 "const_int_operand" ""))]
9056 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9057 [(set (match_dup 0) (match_dup 2))
9058 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9060 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9062 if (tem == operands[0])
9069 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9070 (match_operand:DI 1 "const_double_operand" ""))]
9071 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9072 [(set (match_dup 0) (match_dup 2))
9073 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9075 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9077 if (tem == operands[0])
9083 ;; TImode is similar, except that we usually want to compute the address into
9084 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
9085 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
9087 ;; We say that MQ is clobbered in the last alternative because the first
9088 ;; alternative would never get used otherwise since it would need a reload
9089 ;; while the 2nd alternative would not. We put memory cases first so they
9090 ;; are preferred. Otherwise, we'd try to reload the output instead of
9091 ;; giving the SCRATCH mq.
9093 (define_insn "*movti_power"
9094 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
9095 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
9096 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
9097 "TARGET_POWER && ! TARGET_POWERPC64
9098 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9101 switch (which_alternative)
9108 return \"{stsi|stswi} %1,%P0,16\";
9113 /* If the address is not used in the output, we can use lsi. Otherwise,
9114 fall through to generating four loads. */
9116 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9117 return \"{lsi|lswi} %0,%P1,16\";
9118 /* ... fall through ... */
9124 [(set_attr "type" "store,store,*,load,load,*")])
9126 (define_insn "*movti_string"
9127 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
9128 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
9129 "! TARGET_POWER && ! TARGET_POWERPC64
9130 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9133 switch (which_alternative)
9139 return \"{stsi|stswi} %1,%P0,16\";
9144 /* If the address is not used in the output, we can use lsi. Otherwise,
9145 fall through to generating four loads. */
9147 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9148 return \"{lsi|lswi} %0,%P1,16\";
9149 /* ... fall through ... */
9155 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")])
9157 (define_insn "*movti_ppc64"
9158 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
9159 (match_operand:TI 1 "input_operand" "r,r,m"))]
9160 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
9161 || gpc_reg_operand (operands[1], TImode))"
9163 [(set_attr "type" "*,load,store")])
9166 [(set (match_operand:TI 0 "gpc_reg_operand" "")
9167 (match_operand:TI 1 "const_double_operand" ""))]
9169 [(set (match_dup 2) (match_dup 4))
9170 (set (match_dup 3) (match_dup 5))]
9173 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9175 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9177 if (GET_CODE (operands[1]) == CONST_DOUBLE)
9179 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9180 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9182 else if (GET_CODE (operands[1]) == CONST_INT)
9184 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9185 operands[5] = operands[1];
9192 [(set (match_operand:TI 0 "nonimmediate_operand" "")
9193 (match_operand:TI 1 "input_operand" ""))]
9195 && gpr_or_gpr_p (operands[0], operands[1])"
9197 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9199 (define_expand "load_multiple"
9200 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9201 (match_operand:SI 1 "" ""))
9202 (use (match_operand:SI 2 "" ""))])]
9203 "TARGET_STRING && !TARGET_POWERPC64"
9211 /* Support only loading a constant number of fixed-point registers from
9212 memory and only bother with this if more than two; the machine
9213 doesn't support more than eight. */
9214 if (GET_CODE (operands[2]) != CONST_INT
9215 || INTVAL (operands[2]) <= 2
9216 || INTVAL (operands[2]) > 8
9217 || GET_CODE (operands[1]) != MEM
9218 || GET_CODE (operands[0]) != REG
9219 || REGNO (operands[0]) >= 32)
9222 count = INTVAL (operands[2]);
9223 regno = REGNO (operands[0]);
9225 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9226 op1 = replace_equiv_address (operands[1],
9227 force_reg (SImode, XEXP (operands[1], 0)));
9229 for (i = 0; i < count; i++)
9230 XVECEXP (operands[3], 0, i)
9231 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
9232 adjust_address_nv (op1, SImode, i * 4));
9235 (define_insn "*ldmsi8"
9236 [(match_parallel 0 "load_multiple_operation"
9237 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9238 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9239 (set (match_operand:SI 3 "gpc_reg_operand" "")
9240 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9241 (set (match_operand:SI 4 "gpc_reg_operand" "")
9242 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9243 (set (match_operand:SI 5 "gpc_reg_operand" "")
9244 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9245 (set (match_operand:SI 6 "gpc_reg_operand" "")
9246 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9247 (set (match_operand:SI 7 "gpc_reg_operand" "")
9248 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9249 (set (match_operand:SI 8 "gpc_reg_operand" "")
9250 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9251 (set (match_operand:SI 9 "gpc_reg_operand" "")
9252 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9253 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9255 { return rs6000_output_load_multiple (operands); }"
9256 [(set_attr "type" "load_ux")
9257 (set_attr "length" "32")])
9259 (define_insn "*ldmsi7"
9260 [(match_parallel 0 "load_multiple_operation"
9261 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9262 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9263 (set (match_operand:SI 3 "gpc_reg_operand" "")
9264 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9265 (set (match_operand:SI 4 "gpc_reg_operand" "")
9266 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9267 (set (match_operand:SI 5 "gpc_reg_operand" "")
9268 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9269 (set (match_operand:SI 6 "gpc_reg_operand" "")
9270 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9271 (set (match_operand:SI 7 "gpc_reg_operand" "")
9272 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9273 (set (match_operand:SI 8 "gpc_reg_operand" "")
9274 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9275 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9277 { return rs6000_output_load_multiple (operands); }"
9278 [(set_attr "type" "load_ux")
9279 (set_attr "length" "32")])
9281 (define_insn "*ldmsi6"
9282 [(match_parallel 0 "load_multiple_operation"
9283 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9284 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9285 (set (match_operand:SI 3 "gpc_reg_operand" "")
9286 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9287 (set (match_operand:SI 4 "gpc_reg_operand" "")
9288 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9289 (set (match_operand:SI 5 "gpc_reg_operand" "")
9290 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9291 (set (match_operand:SI 6 "gpc_reg_operand" "")
9292 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9293 (set (match_operand:SI 7 "gpc_reg_operand" "")
9294 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9295 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9297 { return rs6000_output_load_multiple (operands); }"
9298 [(set_attr "type" "load_ux")
9299 (set_attr "length" "32")])
9301 (define_insn "*ldmsi5"
9302 [(match_parallel 0 "load_multiple_operation"
9303 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9304 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9305 (set (match_operand:SI 3 "gpc_reg_operand" "")
9306 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9307 (set (match_operand:SI 4 "gpc_reg_operand" "")
9308 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9309 (set (match_operand:SI 5 "gpc_reg_operand" "")
9310 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9311 (set (match_operand:SI 6 "gpc_reg_operand" "")
9312 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9313 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9315 { return rs6000_output_load_multiple (operands); }"
9316 [(set_attr "type" "load_ux")
9317 (set_attr "length" "32")])
9319 (define_insn "*ldmsi4"
9320 [(match_parallel 0 "load_multiple_operation"
9321 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9322 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9323 (set (match_operand:SI 3 "gpc_reg_operand" "")
9324 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9325 (set (match_operand:SI 4 "gpc_reg_operand" "")
9326 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9327 (set (match_operand:SI 5 "gpc_reg_operand" "")
9328 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9329 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9331 { return rs6000_output_load_multiple (operands); }"
9332 [(set_attr "type" "load_ux")
9333 (set_attr "length" "32")])
9335 (define_insn "*ldmsi3"
9336 [(match_parallel 0 "load_multiple_operation"
9337 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9338 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9339 (set (match_operand:SI 3 "gpc_reg_operand" "")
9340 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9341 (set (match_operand:SI 4 "gpc_reg_operand" "")
9342 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9343 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9345 { return rs6000_output_load_multiple (operands); }"
9346 [(set_attr "type" "load_ux")
9347 (set_attr "length" "32")])
9349 (define_expand "store_multiple"
9350 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9351 (match_operand:SI 1 "" ""))
9352 (clobber (scratch:SI))
9353 (use (match_operand:SI 2 "" ""))])]
9354 "TARGET_STRING && !TARGET_POWERPC64"
9363 /* Support only storing a constant number of fixed-point registers to
9364 memory and only bother with this if more than two; the machine
9365 doesn't support more than eight. */
9366 if (GET_CODE (operands[2]) != CONST_INT
9367 || INTVAL (operands[2]) <= 2
9368 || INTVAL (operands[2]) > 8
9369 || GET_CODE (operands[0]) != MEM
9370 || GET_CODE (operands[1]) != REG
9371 || REGNO (operands[1]) >= 32)
9374 count = INTVAL (operands[2]);
9375 regno = REGNO (operands[1]);
9377 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
9378 to = force_reg (SImode, XEXP (operands[0], 0));
9379 op0 = replace_equiv_address (operands[0], to);
9381 XVECEXP (operands[3], 0, 0)
9382 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
9383 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
9384 gen_rtx_SCRATCH (SImode));
9386 for (i = 1; i < count; i++)
9387 XVECEXP (operands[3], 0, i + 1)
9388 = gen_rtx_SET (VOIDmode,
9389 adjust_address_nv (op0, SImode, i * 4),
9390 gen_rtx_REG (SImode, regno + i));
9393 (define_insn "*stmsi8"
9394 [(match_parallel 0 "store_multiple_operation"
9395 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9396 (match_operand:SI 2 "gpc_reg_operand" "r"))
9397 (clobber (match_scratch:SI 3 "=X"))
9398 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9399 (match_operand:SI 4 "gpc_reg_operand" "r"))
9400 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9401 (match_operand:SI 5 "gpc_reg_operand" "r"))
9402 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9403 (match_operand:SI 6 "gpc_reg_operand" "r"))
9404 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9405 (match_operand:SI 7 "gpc_reg_operand" "r"))
9406 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9407 (match_operand:SI 8 "gpc_reg_operand" "r"))
9408 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9409 (match_operand:SI 9 "gpc_reg_operand" "r"))
9410 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9411 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9412 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9413 "{stsi|stswi} %2,%1,%O0"
9414 [(set_attr "type" "store_ux")])
9416 (define_insn "*stmsi7"
9417 [(match_parallel 0 "store_multiple_operation"
9418 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9419 (match_operand:SI 2 "gpc_reg_operand" "r"))
9420 (clobber (match_scratch:SI 3 "=X"))
9421 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9422 (match_operand:SI 4 "gpc_reg_operand" "r"))
9423 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9424 (match_operand:SI 5 "gpc_reg_operand" "r"))
9425 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9426 (match_operand:SI 6 "gpc_reg_operand" "r"))
9427 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9428 (match_operand:SI 7 "gpc_reg_operand" "r"))
9429 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9430 (match_operand:SI 8 "gpc_reg_operand" "r"))
9431 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9432 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9433 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9434 "{stsi|stswi} %2,%1,%O0"
9435 [(set_attr "type" "store_ux")])
9437 (define_insn "*stmsi6"
9438 [(match_parallel 0 "store_multiple_operation"
9439 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9440 (match_operand:SI 2 "gpc_reg_operand" "r"))
9441 (clobber (match_scratch:SI 3 "=X"))
9442 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9443 (match_operand:SI 4 "gpc_reg_operand" "r"))
9444 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9445 (match_operand:SI 5 "gpc_reg_operand" "r"))
9446 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9447 (match_operand:SI 6 "gpc_reg_operand" "r"))
9448 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9449 (match_operand:SI 7 "gpc_reg_operand" "r"))
9450 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9451 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9452 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9453 "{stsi|stswi} %2,%1,%O0"
9454 [(set_attr "type" "store_ux")])
9456 (define_insn "*stmsi5"
9457 [(match_parallel 0 "store_multiple_operation"
9458 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9459 (match_operand:SI 2 "gpc_reg_operand" "r"))
9460 (clobber (match_scratch:SI 3 "=X"))
9461 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9462 (match_operand:SI 4 "gpc_reg_operand" "r"))
9463 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9464 (match_operand:SI 5 "gpc_reg_operand" "r"))
9465 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9466 (match_operand:SI 6 "gpc_reg_operand" "r"))
9467 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9468 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9469 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9470 "{stsi|stswi} %2,%1,%O0"
9471 [(set_attr "type" "store_ux")])
9473 (define_insn "*stmsi4"
9474 [(match_parallel 0 "store_multiple_operation"
9475 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9476 (match_operand:SI 2 "gpc_reg_operand" "r"))
9477 (clobber (match_scratch:SI 3 "=X"))
9478 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9479 (match_operand:SI 4 "gpc_reg_operand" "r"))
9480 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9481 (match_operand:SI 5 "gpc_reg_operand" "r"))
9482 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9483 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9484 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9485 "{stsi|stswi} %2,%1,%O0"
9486 [(set_attr "type" "store_ux")])
9488 (define_insn "*stmsi3"
9489 [(match_parallel 0 "store_multiple_operation"
9490 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9491 (match_operand:SI 2 "gpc_reg_operand" "r"))
9492 (clobber (match_scratch:SI 3 "=X"))
9493 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9494 (match_operand:SI 4 "gpc_reg_operand" "r"))
9495 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9496 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9497 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9498 "{stsi|stswi} %2,%1,%O0"
9499 [(set_attr "type" "store_ux")])
9501 (define_insn "*stmsi8_power"
9502 [(match_parallel 0 "store_multiple_operation"
9503 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9504 (match_operand:SI 2 "gpc_reg_operand" "r"))
9505 (clobber (match_scratch:SI 3 "=q"))
9506 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9507 (match_operand:SI 4 "gpc_reg_operand" "r"))
9508 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9509 (match_operand:SI 5 "gpc_reg_operand" "r"))
9510 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9511 (match_operand:SI 6 "gpc_reg_operand" "r"))
9512 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9513 (match_operand:SI 7 "gpc_reg_operand" "r"))
9514 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9515 (match_operand:SI 8 "gpc_reg_operand" "r"))
9516 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9517 (match_operand:SI 9 "gpc_reg_operand" "r"))
9518 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9519 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9520 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9521 "{stsi|stswi} %2,%1,%O0"
9522 [(set_attr "type" "store_ux")])
9524 (define_insn "*stmsi7_power"
9525 [(match_parallel 0 "store_multiple_operation"
9526 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9527 (match_operand:SI 2 "gpc_reg_operand" "r"))
9528 (clobber (match_scratch:SI 3 "=q"))
9529 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9530 (match_operand:SI 4 "gpc_reg_operand" "r"))
9531 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9532 (match_operand:SI 5 "gpc_reg_operand" "r"))
9533 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9534 (match_operand:SI 6 "gpc_reg_operand" "r"))
9535 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9536 (match_operand:SI 7 "gpc_reg_operand" "r"))
9537 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9538 (match_operand:SI 8 "gpc_reg_operand" "r"))
9539 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9540 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9541 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9542 "{stsi|stswi} %2,%1,%O0"
9543 [(set_attr "type" "store_ux")])
9545 (define_insn "*stmsi6_power"
9546 [(match_parallel 0 "store_multiple_operation"
9547 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9548 (match_operand:SI 2 "gpc_reg_operand" "r"))
9549 (clobber (match_scratch:SI 3 "=q"))
9550 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9551 (match_operand:SI 4 "gpc_reg_operand" "r"))
9552 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9553 (match_operand:SI 5 "gpc_reg_operand" "r"))
9554 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9555 (match_operand:SI 6 "gpc_reg_operand" "r"))
9556 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9557 (match_operand:SI 7 "gpc_reg_operand" "r"))
9558 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9559 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9560 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9561 "{stsi|stswi} %2,%1,%O0"
9562 [(set_attr "type" "store_ux")])
9564 (define_insn "*stmsi5_power"
9565 [(match_parallel 0 "store_multiple_operation"
9566 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9567 (match_operand:SI 2 "gpc_reg_operand" "r"))
9568 (clobber (match_scratch:SI 3 "=q"))
9569 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9570 (match_operand:SI 4 "gpc_reg_operand" "r"))
9571 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9572 (match_operand:SI 5 "gpc_reg_operand" "r"))
9573 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9574 (match_operand:SI 6 "gpc_reg_operand" "r"))
9575 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9576 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9577 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9578 "{stsi|stswi} %2,%1,%O0"
9579 [(set_attr "type" "store_ux")])
9581 (define_insn "*stmsi4_power"
9582 [(match_parallel 0 "store_multiple_operation"
9583 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9584 (match_operand:SI 2 "gpc_reg_operand" "r"))
9585 (clobber (match_scratch:SI 3 "=q"))
9586 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9587 (match_operand:SI 4 "gpc_reg_operand" "r"))
9588 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9589 (match_operand:SI 5 "gpc_reg_operand" "r"))
9590 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9591 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9592 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9593 "{stsi|stswi} %2,%1,%O0"
9594 [(set_attr "type" "store_ux")])
9596 (define_insn "*stmsi3_power"
9597 [(match_parallel 0 "store_multiple_operation"
9598 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9599 (match_operand:SI 2 "gpc_reg_operand" "r"))
9600 (clobber (match_scratch:SI 3 "=q"))
9601 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9602 (match_operand:SI 4 "gpc_reg_operand" "r"))
9603 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9604 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9605 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9606 "{stsi|stswi} %2,%1,%O0"
9607 [(set_attr "type" "store_ux")])
9609 (define_expand "setmemsi"
9610 [(parallel [(set (match_operand:BLK 0 "" "")
9611 (match_operand 2 "const_int_operand" ""))
9612 (use (match_operand:SI 1 "" ""))
9613 (use (match_operand:SI 3 "" ""))])]
9617 /* If value to set is not zero, use the library routine. */
9618 if (operands[2] != const0_rtx)
9621 if (expand_block_clear (operands))
9627 ;; String/block move insn.
9628 ;; Argument 0 is the destination
9629 ;; Argument 1 is the source
9630 ;; Argument 2 is the length
9631 ;; Argument 3 is the alignment
9633 (define_expand "movmemsi"
9634 [(parallel [(set (match_operand:BLK 0 "" "")
9635 (match_operand:BLK 1 "" ""))
9636 (use (match_operand:SI 2 "" ""))
9637 (use (match_operand:SI 3 "" ""))])]
9641 if (expand_block_move (operands))
9647 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9648 ;; register allocator doesn't have a clue about allocating 8 word registers.
9649 ;; rD/rS = r5 is preferred, efficient form.
9650 (define_expand "movmemsi_8reg"
9651 [(parallel [(set (match_operand 0 "" "")
9652 (match_operand 1 "" ""))
9653 (use (match_operand 2 "" ""))
9654 (use (match_operand 3 "" ""))
9655 (clobber (reg:SI 5))
9656 (clobber (reg:SI 6))
9657 (clobber (reg:SI 7))
9658 (clobber (reg:SI 8))
9659 (clobber (reg:SI 9))
9660 (clobber (reg:SI 10))
9661 (clobber (reg:SI 11))
9662 (clobber (reg:SI 12))
9663 (clobber (match_scratch:SI 4 ""))])]
9668 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9669 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9670 (use (match_operand:SI 2 "immediate_operand" "i"))
9671 (use (match_operand:SI 3 "immediate_operand" "i"))
9672 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9673 (clobber (reg:SI 6))
9674 (clobber (reg:SI 7))
9675 (clobber (reg:SI 8))
9676 (clobber (reg:SI 9))
9677 (clobber (reg:SI 10))
9678 (clobber (reg:SI 11))
9679 (clobber (reg:SI 12))
9680 (clobber (match_scratch:SI 5 "=q"))]
9681 "TARGET_STRING && TARGET_POWER
9682 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9683 || INTVAL (operands[2]) == 0)
9684 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9685 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9686 && REGNO (operands[4]) == 5"
9687 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9688 [(set_attr "type" "store_ux")
9689 (set_attr "length" "8")])
9692 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9693 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9694 (use (match_operand:SI 2 "immediate_operand" "i"))
9695 (use (match_operand:SI 3 "immediate_operand" "i"))
9696 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9697 (clobber (reg:SI 6))
9698 (clobber (reg:SI 7))
9699 (clobber (reg:SI 8))
9700 (clobber (reg:SI 9))
9701 (clobber (reg:SI 10))
9702 (clobber (reg:SI 11))
9703 (clobber (reg:SI 12))
9704 (clobber (match_scratch:SI 5 "=X"))]
9705 "TARGET_STRING && ! TARGET_POWER
9706 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9707 || INTVAL (operands[2]) == 0)
9708 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9709 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9710 && REGNO (operands[4]) == 5"
9711 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9712 [(set_attr "type" "store_ux")
9713 (set_attr "length" "8")])
9715 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9716 ;; register allocator doesn't have a clue about allocating 6 word registers.
9717 ;; rD/rS = r5 is preferred, efficient form.
9718 (define_expand "movmemsi_6reg"
9719 [(parallel [(set (match_operand 0 "" "")
9720 (match_operand 1 "" ""))
9721 (use (match_operand 2 "" ""))
9722 (use (match_operand 3 "" ""))
9723 (clobber (reg:SI 5))
9724 (clobber (reg:SI 6))
9725 (clobber (reg:SI 7))
9726 (clobber (reg:SI 8))
9727 (clobber (reg:SI 9))
9728 (clobber (reg:SI 10))
9729 (clobber (match_scratch:SI 4 ""))])]
9734 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9735 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9736 (use (match_operand:SI 2 "immediate_operand" "i"))
9737 (use (match_operand:SI 3 "immediate_operand" "i"))
9738 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9739 (clobber (reg:SI 6))
9740 (clobber (reg:SI 7))
9741 (clobber (reg:SI 8))
9742 (clobber (reg:SI 9))
9743 (clobber (reg:SI 10))
9744 (clobber (match_scratch:SI 5 "=q"))]
9745 "TARGET_STRING && TARGET_POWER
9746 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9747 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9748 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9749 && REGNO (operands[4]) == 5"
9750 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9751 [(set_attr "type" "store_ux")
9752 (set_attr "length" "8")])
9755 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9756 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9757 (use (match_operand:SI 2 "immediate_operand" "i"))
9758 (use (match_operand:SI 3 "immediate_operand" "i"))
9759 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9760 (clobber (reg:SI 6))
9761 (clobber (reg:SI 7))
9762 (clobber (reg:SI 8))
9763 (clobber (reg:SI 9))
9764 (clobber (reg:SI 10))
9765 (clobber (match_scratch:SI 5 "=X"))]
9766 "TARGET_STRING && ! TARGET_POWER
9767 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9768 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9769 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9770 && REGNO (operands[4]) == 5"
9771 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9772 [(set_attr "type" "store_ux")
9773 (set_attr "length" "8")])
9775 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9776 ;; problems with TImode.
9777 ;; rD/rS = r5 is preferred, efficient form.
9778 (define_expand "movmemsi_4reg"
9779 [(parallel [(set (match_operand 0 "" "")
9780 (match_operand 1 "" ""))
9781 (use (match_operand 2 "" ""))
9782 (use (match_operand 3 "" ""))
9783 (clobber (reg:SI 5))
9784 (clobber (reg:SI 6))
9785 (clobber (reg:SI 7))
9786 (clobber (reg:SI 8))
9787 (clobber (match_scratch:SI 4 ""))])]
9792 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9793 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9794 (use (match_operand:SI 2 "immediate_operand" "i"))
9795 (use (match_operand:SI 3 "immediate_operand" "i"))
9796 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9797 (clobber (reg:SI 6))
9798 (clobber (reg:SI 7))
9799 (clobber (reg:SI 8))
9800 (clobber (match_scratch:SI 5 "=q"))]
9801 "TARGET_STRING && TARGET_POWER
9802 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9803 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9804 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9805 && REGNO (operands[4]) == 5"
9806 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9807 [(set_attr "type" "store_ux")
9808 (set_attr "length" "8")])
9811 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9812 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9813 (use (match_operand:SI 2 "immediate_operand" "i"))
9814 (use (match_operand:SI 3 "immediate_operand" "i"))
9815 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9816 (clobber (reg:SI 6))
9817 (clobber (reg:SI 7))
9818 (clobber (reg:SI 8))
9819 (clobber (match_scratch:SI 5 "=X"))]
9820 "TARGET_STRING && ! TARGET_POWER
9821 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9822 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9823 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9824 && REGNO (operands[4]) == 5"
9825 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9826 [(set_attr "type" "store_ux")
9827 (set_attr "length" "8")])
9829 ;; Move up to 8 bytes at a time.
9830 (define_expand "movmemsi_2reg"
9831 [(parallel [(set (match_operand 0 "" "")
9832 (match_operand 1 "" ""))
9833 (use (match_operand 2 "" ""))
9834 (use (match_operand 3 "" ""))
9835 (clobber (match_scratch:DI 4 ""))
9836 (clobber (match_scratch:SI 5 ""))])]
9837 "TARGET_STRING && ! TARGET_POWERPC64"
9841 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9842 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9843 (use (match_operand:SI 2 "immediate_operand" "i"))
9844 (use (match_operand:SI 3 "immediate_operand" "i"))
9845 (clobber (match_scratch:DI 4 "=&r"))
9846 (clobber (match_scratch:SI 5 "=q"))]
9847 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9848 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9849 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9850 [(set_attr "type" "store_ux")
9851 (set_attr "length" "8")])
9854 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9855 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9856 (use (match_operand:SI 2 "immediate_operand" "i"))
9857 (use (match_operand:SI 3 "immediate_operand" "i"))
9858 (clobber (match_scratch:DI 4 "=&r"))
9859 (clobber (match_scratch:SI 5 "=X"))]
9860 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9861 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9862 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9863 [(set_attr "type" "store_ux")
9864 (set_attr "length" "8")])
9866 ;; Move up to 4 bytes at a time.
9867 (define_expand "movmemsi_1reg"
9868 [(parallel [(set (match_operand 0 "" "")
9869 (match_operand 1 "" ""))
9870 (use (match_operand 2 "" ""))
9871 (use (match_operand 3 "" ""))
9872 (clobber (match_scratch:SI 4 ""))
9873 (clobber (match_scratch:SI 5 ""))])]
9878 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9879 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9880 (use (match_operand:SI 2 "immediate_operand" "i"))
9881 (use (match_operand:SI 3 "immediate_operand" "i"))
9882 (clobber (match_scratch:SI 4 "=&r"))
9883 (clobber (match_scratch:SI 5 "=q"))]
9884 "TARGET_STRING && TARGET_POWER
9885 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9886 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9887 [(set_attr "type" "store_ux")
9888 (set_attr "length" "8")])
9891 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9892 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9893 (use (match_operand:SI 2 "immediate_operand" "i"))
9894 (use (match_operand:SI 3 "immediate_operand" "i"))
9895 (clobber (match_scratch:SI 4 "=&r"))
9896 (clobber (match_scratch:SI 5 "=X"))]
9897 "TARGET_STRING && ! TARGET_POWER
9898 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9899 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9900 [(set_attr "type" "store_ux")
9901 (set_attr "length" "8")])
9903 ;; Define insns that do load or store with update. Some of these we can
9904 ;; get by using pre-decrement or pre-increment, but the hardware can also
9905 ;; do cases where the increment is not the size of the object.
9907 ;; In all these cases, we use operands 0 and 1 for the register being
9908 ;; incremented because those are the operands that local-alloc will
9909 ;; tie and these are the pair most likely to be tieable (and the ones
9910 ;; that will benefit the most).
9912 (define_insn "*movdi_update1"
9913 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9914 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9915 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9916 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9917 (plus:DI (match_dup 1) (match_dup 2)))]
9918 "TARGET_POWERPC64 && TARGET_UPDATE"
9922 [(set_attr "type" "load_ux,load_u")])
9924 (define_insn "movdi_<mode>_update"
9925 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9926 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9927 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9928 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9929 (plus:P (match_dup 1) (match_dup 2)))]
9930 "TARGET_POWERPC64 && TARGET_UPDATE"
9934 [(set_attr "type" "store_ux,store_u")])
9936 (define_insn "*movsi_update1"
9937 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9938 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9939 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9940 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9941 (plus:SI (match_dup 1) (match_dup 2)))]
9944 {lux|lwzux} %3,%0,%2
9945 {lu|lwzu} %3,%2(%0)"
9946 [(set_attr "type" "load_ux,load_u")])
9948 (define_insn "*movsi_update2"
9949 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9951 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9952 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9953 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9954 (plus:DI (match_dup 1) (match_dup 2)))]
9957 [(set_attr "type" "load_ext_ux")])
9959 (define_insn "movsi_update"
9960 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9961 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9962 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9963 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9964 (plus:SI (match_dup 1) (match_dup 2)))]
9967 {stux|stwux} %3,%0,%2
9968 {stu|stwu} %3,%2(%0)"
9969 [(set_attr "type" "store_ux,store_u")])
9971 (define_insn "*movhi_update1"
9972 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9973 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9974 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9975 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9976 (plus:SI (match_dup 1) (match_dup 2)))]
9981 [(set_attr "type" "load_ux,load_u")])
9983 (define_insn "*movhi_update2"
9984 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9986 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9987 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9988 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9989 (plus:SI (match_dup 1) (match_dup 2)))]
9994 [(set_attr "type" "load_ux,load_u")])
9996 (define_insn "*movhi_update3"
9997 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9999 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10000 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10001 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10002 (plus:SI (match_dup 1) (match_dup 2)))]
10007 [(set_attr "type" "load_ext_ux,load_ext_u")])
10009 (define_insn "*movhi_update4"
10010 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10011 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10012 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
10013 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10014 (plus:SI (match_dup 1) (match_dup 2)))]
10019 [(set_attr "type" "store_ux,store_u")])
10021 (define_insn "*movqi_update1"
10022 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
10023 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10024 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10025 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10026 (plus:SI (match_dup 1) (match_dup 2)))]
10031 [(set_attr "type" "load_ux,load_u")])
10033 (define_insn "*movqi_update2"
10034 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10036 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10037 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10038 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10039 (plus:SI (match_dup 1) (match_dup 2)))]
10044 [(set_attr "type" "load_ux,load_u")])
10046 (define_insn "*movqi_update3"
10047 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10048 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10049 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
10050 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10051 (plus:SI (match_dup 1) (match_dup 2)))]
10056 [(set_attr "type" "store_ux,store_u")])
10058 (define_insn "*movsf_update1"
10059 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
10060 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10061 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10062 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10063 (plus:SI (match_dup 1) (match_dup 2)))]
10064 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
10068 [(set_attr "type" "fpload_ux,fpload_u")])
10070 (define_insn "*movsf_update2"
10071 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10072 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10073 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10074 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10075 (plus:SI (match_dup 1) (match_dup 2)))]
10076 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
10080 [(set_attr "type" "fpstore_ux,fpstore_u")])
10082 (define_insn "*movsf_update3"
10083 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10084 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10085 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10086 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10087 (plus:SI (match_dup 1) (match_dup 2)))]
10088 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
10090 {lux|lwzux} %3,%0,%2
10091 {lu|lwzu} %3,%2(%0)"
10092 [(set_attr "type" "load_ux,load_u")])
10094 (define_insn "*movsf_update4"
10095 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10096 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10097 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10098 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10099 (plus:SI (match_dup 1) (match_dup 2)))]
10100 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
10102 {stux|stwux} %3,%0,%2
10103 {stu|stwu} %3,%2(%0)"
10104 [(set_attr "type" "store_ux,store_u")])
10106 (define_insn "*movdf_update1"
10107 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
10108 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10109 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10110 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10111 (plus:SI (match_dup 1) (match_dup 2)))]
10112 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
10116 [(set_attr "type" "fpload_ux,fpload_u")])
10118 (define_insn "*movdf_update2"
10119 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10120 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10121 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
10122 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10123 (plus:SI (match_dup 1) (match_dup 2)))]
10124 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
10128 [(set_attr "type" "fpstore_ux,fpstore_u")])
10130 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
10132 (define_insn "*lfq_power2"
10133 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
10134 (match_operand:V2DF 1 "memory_operand" ""))]
10136 && TARGET_HARD_FLOAT && TARGET_FPRS"
10140 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10141 (match_operand:DF 1 "memory_operand" ""))
10142 (set (match_operand:DF 2 "gpc_reg_operand" "")
10143 (match_operand:DF 3 "memory_operand" ""))]
10145 && TARGET_HARD_FLOAT && TARGET_FPRS
10146 && registers_ok_for_quad_peep (operands[0], operands[2])
10147 && mems_ok_for_quad_peep (operands[1], operands[3])"
10148 [(set (match_dup 0)
10150 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
10151 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
10153 (define_insn "*stfq_power2"
10154 [(set (match_operand:V2DF 0 "memory_operand" "")
10155 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
10157 && TARGET_HARD_FLOAT && TARGET_FPRS"
10158 "stfq%U0%X0 %1,%0")
10162 [(set (match_operand:DF 0 "memory_operand" "")
10163 (match_operand:DF 1 "gpc_reg_operand" ""))
10164 (set (match_operand:DF 2 "memory_operand" "")
10165 (match_operand:DF 3 "gpc_reg_operand" ""))]
10167 && TARGET_HARD_FLOAT && TARGET_FPRS
10168 && registers_ok_for_quad_peep (operands[1], operands[3])
10169 && mems_ok_for_quad_peep (operands[0], operands[2])"
10170 [(set (match_dup 0)
10172 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
10173 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
10175 ;; After inserting conditional returns we can sometimes have
10176 ;; unnecessary register moves. Unfortunately we cannot have a
10177 ;; modeless peephole here, because some single SImode sets have early
10178 ;; clobber outputs. Although those sets expand to multi-ppc-insn
10179 ;; sequences, using get_attr_length here will smash the operands
10180 ;; array. Neither is there an early_cobbler_p predicate.
10181 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
10183 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10184 (match_operand:DF 1 "any_operand" ""))
10185 (set (match_operand:DF 2 "gpc_reg_operand" "")
10187 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10188 && peep2_reg_dead_p (2, operands[0])"
10189 [(set (match_dup 2) (match_dup 1))])
10192 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10193 (match_operand:SF 1 "any_operand" ""))
10194 (set (match_operand:SF 2 "gpc_reg_operand" "")
10196 "peep2_reg_dead_p (2, operands[0])"
10197 [(set (match_dup 2) (match_dup 1))])
10202 ;; Mode attributes for different ABIs.
10203 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
10204 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
10205 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
10206 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
10208 (define_insn "tls_gd_aix<TLSmode:tls_abi_suffix>"
10209 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10210 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10211 (match_operand 4 "" "g")))
10212 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10213 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10215 (clobber (reg:SI LR_REGNO))]
10216 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10217 "addi %0,%1,%2@got@tlsgd\;bl %z3\;%."
10218 [(set_attr "type" "two")
10219 (set_attr "length" "12")])
10221 (define_insn "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
10222 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10223 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10224 (match_operand 4 "" "g")))
10225 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10226 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10228 (clobber (reg:SI LR_REGNO))]
10229 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10233 if (TARGET_SECURE_PLT && flag_pic == 2)
10234 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
10236 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
10239 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
10241 [(set_attr "type" "two")
10242 (set_attr "length" "8")])
10244 (define_insn "tls_ld_aix<TLSmode:tls_abi_suffix>"
10245 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10246 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10247 (match_operand 3 "" "g")))
10248 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10250 (clobber (reg:SI LR_REGNO))]
10251 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10252 "addi %0,%1,%&@got@tlsld\;bl %z2\;%."
10253 [(set_attr "length" "12")])
10255 (define_insn "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
10256 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10257 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10258 (match_operand 3 "" "g")))
10259 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10261 (clobber (reg:SI LR_REGNO))]
10262 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10266 if (TARGET_SECURE_PLT && flag_pic == 2)
10267 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
10269 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
10272 return "addi %0,%1,%&@got@tlsld\;bl %z2";
10274 [(set_attr "length" "8")])
10276 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
10277 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10278 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10279 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10280 UNSPEC_TLSDTPREL))]
10282 "addi %0,%1,%2@dtprel")
10284 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
10285 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10286 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10287 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10288 UNSPEC_TLSDTPRELHA))]
10290 "addis %0,%1,%2@dtprel@ha")
10292 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
10293 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10294 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10295 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10296 UNSPEC_TLSDTPRELLO))]
10298 "addi %0,%1,%2@dtprel@l")
10300 (define_insn "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
10301 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10302 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10303 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10304 UNSPEC_TLSGOTDTPREL))]
10306 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)")
10308 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
10309 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10310 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10311 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10314 "addi %0,%1,%2@tprel")
10316 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
10317 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10318 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10319 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10320 UNSPEC_TLSTPRELHA))]
10322 "addis %0,%1,%2@tprel@ha")
10324 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
10325 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10326 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10327 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10328 UNSPEC_TLSTPRELLO))]
10330 "addi %0,%1,%2@tprel@l")
10332 ;; "b" output constraint here and on tls_tls input to support linker tls
10333 ;; optimization. The linker may edit the instructions emitted by a
10334 ;; tls_got_tprel/tls_tls pair to addis,addi.
10335 (define_insn "tls_got_tprel_<TLSmode:tls_abi_suffix>"
10336 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10337 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10338 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10339 UNSPEC_TLSGOTTPREL))]
10341 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)")
10343 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
10344 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10345 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10346 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10349 "add %0,%1,%2@tls")
10352 ;; Next come insns related to the calling sequence.
10354 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
10355 ;; We move the back-chain and decrement the stack pointer.
10357 (define_expand "allocate_stack"
10358 [(set (match_operand 0 "gpc_reg_operand" "")
10359 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10361 (minus (reg 1) (match_dup 1)))]
10364 { rtx chain = gen_reg_rtx (Pmode);
10365 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
10368 emit_move_insn (chain, stack_bot);
10370 /* Check stack bounds if necessary. */
10371 if (crtl->limit_stack)
10374 available = expand_binop (Pmode, sub_optab,
10375 stack_pointer_rtx, stack_limit_rtx,
10376 NULL_RTX, 1, OPTAB_WIDEN);
10377 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10380 if (GET_CODE (operands[1]) != CONST_INT
10381 || INTVAL (operands[1]) < -32767
10382 || INTVAL (operands[1]) > 32768)
10384 neg_op0 = gen_reg_rtx (Pmode);
10386 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10388 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10391 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10394 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
10395 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
10399 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
10400 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
10401 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
10404 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10408 ;; These patterns say how to save and restore the stack pointer. We need not
10409 ;; save the stack pointer at function level since we are careful to
10410 ;; preserve the backchain. At block level, we have to restore the backchain
10411 ;; when we restore the stack pointer.
10413 ;; For nonlocal gotos, we must save both the stack pointer and its
10414 ;; backchain and restore both. Note that in the nonlocal case, the
10415 ;; save area is a memory location.
10417 (define_expand "save_stack_function"
10418 [(match_operand 0 "any_operand" "")
10419 (match_operand 1 "any_operand" "")]
10423 (define_expand "restore_stack_function"
10424 [(match_operand 0 "any_operand" "")
10425 (match_operand 1 "any_operand" "")]
10429 ;; Adjust stack pointer (op0) to a new value (op1).
10430 ;; First copy old stack backchain to new location, and ensure that the
10431 ;; scheduler won't reorder the sp assignment before the backchain write.
10432 (define_expand "restore_stack_block"
10433 [(set (match_dup 2) (match_dup 3))
10434 (set (match_dup 4) (match_dup 2))
10435 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
10436 (set (match_operand 0 "register_operand" "")
10437 (match_operand 1 "register_operand" ""))]
10441 operands[1] = force_reg (Pmode, operands[1]);
10442 operands[2] = gen_reg_rtx (Pmode);
10443 operands[3] = gen_frame_mem (Pmode, operands[0]);
10444 operands[4] = gen_frame_mem (Pmode, operands[1]);
10445 operands[5] = gen_frame_mem (BLKmode, operands[0]);
10448 (define_expand "save_stack_nonlocal"
10449 [(set (match_dup 3) (match_dup 4))
10450 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10451 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
10455 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10457 /* Copy the backchain to the first word, sp to the second. */
10458 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10459 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10460 operands[3] = gen_reg_rtx (Pmode);
10461 operands[4] = gen_frame_mem (Pmode, operands[1]);
10464 (define_expand "restore_stack_nonlocal"
10465 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10466 (set (match_dup 3) (match_dup 4))
10467 (set (match_dup 5) (match_dup 2))
10468 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
10469 (set (match_operand 0 "register_operand" "") (match_dup 3))]
10473 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10475 /* Restore the backchain from the first word, sp from the second. */
10476 operands[2] = gen_reg_rtx (Pmode);
10477 operands[3] = gen_reg_rtx (Pmode);
10478 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10479 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10480 operands[5] = gen_frame_mem (Pmode, operands[3]);
10481 operands[6] = gen_frame_mem (BLKmode, operands[0]);
10484 ;; TOC register handling.
10486 ;; Code to initialize the TOC register...
10488 (define_insn "load_toc_aix_si"
10489 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10490 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10491 (use (reg:SI 2))])]
10492 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10496 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10497 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10498 operands[2] = gen_rtx_REG (Pmode, 2);
10499 return \"{l|lwz} %0,%1(%2)\";
10501 [(set_attr "type" "load")])
10503 (define_insn "load_toc_aix_di"
10504 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10505 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10506 (use (reg:DI 2))])]
10507 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10511 #ifdef TARGET_RELOCATABLE
10512 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10513 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10515 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10518 strcat (buf, \"@toc\");
10519 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10520 operands[2] = gen_rtx_REG (Pmode, 2);
10521 return \"ld %0,%1(%2)\";
10523 [(set_attr "type" "load")])
10525 (define_insn "load_toc_v4_pic_si"
10526 [(set (reg:SI LR_REGNO)
10527 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10528 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10529 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10530 [(set_attr "type" "branch")
10531 (set_attr "length" "4")])
10533 (define_insn "load_toc_v4_PIC_1"
10534 [(set (reg:SI LR_REGNO)
10535 (match_operand:SI 0 "immediate_operand" "s"))
10536 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10537 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
10538 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10539 "bcl 20,31,%0\\n%0:"
10540 [(set_attr "type" "branch")
10541 (set_attr "length" "4")])
10543 (define_insn "load_toc_v4_PIC_1b"
10544 [(set (reg:SI LR_REGNO)
10545 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")]
10547 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10548 "bcl 20,31,$+8\\n\\t.long %0-$"
10549 [(set_attr "type" "branch")
10550 (set_attr "length" "8")])
10552 (define_insn "load_toc_v4_PIC_2"
10553 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10554 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10555 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10556 (match_operand:SI 3 "immediate_operand" "s")))))]
10557 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10558 "{l|lwz} %0,%2-%3(%1)"
10559 [(set_attr "type" "load")])
10561 (define_insn "load_toc_v4_PIC_3b"
10562 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10563 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10565 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10566 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10567 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10568 "{cau|addis} %0,%1,%2-%3@ha")
10570 (define_insn "load_toc_v4_PIC_3c"
10571 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10572 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10573 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10574 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10575 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10576 "{cal|addi} %0,%1,%2-%3@l")
10578 ;; If the TOC is shared over a translation unit, as happens with all
10579 ;; the kinds of PIC that we support, we need to restore the TOC
10580 ;; pointer only when jumping over units of translation.
10581 ;; On Darwin, we need to reload the picbase.
10583 (define_expand "builtin_setjmp_receiver"
10584 [(use (label_ref (match_operand 0 "" "")))]
10585 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10586 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10587 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10591 if (DEFAULT_ABI == ABI_DARWIN)
10593 const char *picbase = machopic_function_base_name ();
10594 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
10595 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10599 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10600 CODE_LABEL_NUMBER (operands[0]));
10601 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10603 emit_insn (gen_load_macho_picbase (tmplabrtx));
10604 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
10605 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10609 rs6000_emit_load_toc_table (FALSE);
10613 ;; Elf specific ways of loading addresses for non-PIC code.
10614 ;; The output of this could be r0, but we make a very strong
10615 ;; preference for a base register because it will usually
10616 ;; be needed there.
10617 (define_insn "elf_high"
10618 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10619 (high:SI (match_operand 1 "" "")))]
10620 "TARGET_ELF && ! TARGET_64BIT"
10621 "{liu|lis} %0,%1@ha")
10623 (define_insn "elf_low"
10624 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10625 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10626 (match_operand 2 "" "")))]
10627 "TARGET_ELF && ! TARGET_64BIT"
10629 {cal|la} %0,%2@l(%1)
10630 {ai|addic} %0,%1,%K2")
10632 ;; A function pointer under AIX is a pointer to a data area whose first word
10633 ;; contains the actual address of the function, whose second word contains a
10634 ;; pointer to its TOC, and whose third word contains a value to place in the
10635 ;; static chain register (r11). Note that if we load the static chain, our
10636 ;; "trampoline" need not have any executable code.
10638 (define_expand "call_indirect_aix32"
10639 [(set (match_dup 2)
10640 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10641 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10644 (mem:SI (plus:SI (match_dup 0)
10647 (mem:SI (plus:SI (match_dup 0)
10649 (parallel [(call (mem:SI (match_dup 2))
10650 (match_operand 1 "" ""))
10654 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10655 (clobber (reg:SI LR_REGNO))])]
10658 { operands[2] = gen_reg_rtx (SImode); }")
10660 (define_expand "call_indirect_aix64"
10661 [(set (match_dup 2)
10662 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10663 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10666 (mem:DI (plus:DI (match_dup 0)
10669 (mem:DI (plus:DI (match_dup 0)
10671 (parallel [(call (mem:SI (match_dup 2))
10672 (match_operand 1 "" ""))
10676 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10677 (clobber (reg:SI LR_REGNO))])]
10680 { operands[2] = gen_reg_rtx (DImode); }")
10682 (define_expand "call_value_indirect_aix32"
10683 [(set (match_dup 3)
10684 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10685 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10688 (mem:SI (plus:SI (match_dup 1)
10691 (mem:SI (plus:SI (match_dup 1)
10693 (parallel [(set (match_operand 0 "" "")
10694 (call (mem:SI (match_dup 3))
10695 (match_operand 2 "" "")))
10699 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10700 (clobber (reg:SI LR_REGNO))])]
10703 { operands[3] = gen_reg_rtx (SImode); }")
10705 (define_expand "call_value_indirect_aix64"
10706 [(set (match_dup 3)
10707 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10708 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10711 (mem:DI (plus:DI (match_dup 1)
10714 (mem:DI (plus:DI (match_dup 1)
10716 (parallel [(set (match_operand 0 "" "")
10717 (call (mem:SI (match_dup 3))
10718 (match_operand 2 "" "")))
10722 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10723 (clobber (reg:SI LR_REGNO))])]
10726 { operands[3] = gen_reg_rtx (DImode); }")
10728 ;; Now the definitions for the call and call_value insns
10729 (define_expand "call"
10730 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10731 (match_operand 1 "" ""))
10732 (use (match_operand 2 "" ""))
10733 (clobber (reg:SI LR_REGNO))])]
10738 if (MACHOPIC_INDIRECT)
10739 operands[0] = machopic_indirect_call_target (operands[0]);
10742 gcc_assert (GET_CODE (operands[0]) == MEM);
10743 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10745 operands[0] = XEXP (operands[0], 0);
10747 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10749 && GET_CODE (operands[0]) == SYMBOL_REF
10750 && !SYMBOL_REF_LOCAL_P (operands[0]))
10755 tmp = gen_rtvec (3,
10756 gen_rtx_CALL (VOIDmode,
10757 gen_rtx_MEM (SImode, operands[0]),
10759 gen_rtx_USE (VOIDmode, operands[2]),
10760 gen_rtx_CLOBBER (VOIDmode,
10761 gen_rtx_REG (Pmode, LR_REGNO)));
10762 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10763 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10767 if (GET_CODE (operands[0]) != SYMBOL_REF
10768 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10769 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10771 if (INTVAL (operands[2]) & CALL_LONG)
10772 operands[0] = rs6000_longcall_ref (operands[0]);
10774 switch (DEFAULT_ABI)
10778 operands[0] = force_reg (Pmode, operands[0]);
10782 /* AIX function pointers are really pointers to a three word
10784 emit_call_insn (TARGET_32BIT
10785 ? gen_call_indirect_aix32 (force_reg (SImode,
10788 : gen_call_indirect_aix64 (force_reg (DImode,
10794 gcc_unreachable ();
10799 (define_expand "call_value"
10800 [(parallel [(set (match_operand 0 "" "")
10801 (call (mem:SI (match_operand 1 "address_operand" ""))
10802 (match_operand 2 "" "")))
10803 (use (match_operand 3 "" ""))
10804 (clobber (reg:SI LR_REGNO))])]
10809 if (MACHOPIC_INDIRECT)
10810 operands[1] = machopic_indirect_call_target (operands[1]);
10813 gcc_assert (GET_CODE (operands[1]) == MEM);
10814 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10816 operands[1] = XEXP (operands[1], 0);
10818 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10820 && GET_CODE (operands[1]) == SYMBOL_REF
10821 && !SYMBOL_REF_LOCAL_P (operands[1]))
10826 tmp = gen_rtvec (3,
10827 gen_rtx_SET (VOIDmode,
10829 gen_rtx_CALL (VOIDmode,
10830 gen_rtx_MEM (SImode,
10833 gen_rtx_USE (VOIDmode, operands[3]),
10834 gen_rtx_CLOBBER (VOIDmode,
10835 gen_rtx_REG (Pmode, LR_REGNO)));
10836 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10837 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10841 if (GET_CODE (operands[1]) != SYMBOL_REF
10842 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10843 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10845 if (INTVAL (operands[3]) & CALL_LONG)
10846 operands[1] = rs6000_longcall_ref (operands[1]);
10848 switch (DEFAULT_ABI)
10852 operands[1] = force_reg (Pmode, operands[1]);
10856 /* AIX function pointers are really pointers to a three word
10858 emit_call_insn (TARGET_32BIT
10859 ? gen_call_value_indirect_aix32 (operands[0],
10863 : gen_call_value_indirect_aix64 (operands[0],
10870 gcc_unreachable ();
10875 ;; Call to function in current module. No TOC pointer reload needed.
10876 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10877 ;; either the function was not prototyped, or it was prototyped as a
10878 ;; variable argument function. It is > 0 if FP registers were passed
10879 ;; and < 0 if they were not.
10881 (define_insn "*call_local32"
10882 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10883 (match_operand 1 "" "g,g"))
10884 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10885 (clobber (reg:SI LR_REGNO))]
10886 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10889 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10890 output_asm_insn (\"crxor 6,6,6\", operands);
10892 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10893 output_asm_insn (\"creqv 6,6,6\", operands);
10895 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10897 [(set_attr "type" "branch")
10898 (set_attr "length" "4,8")])
10900 (define_insn "*call_local64"
10901 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10902 (match_operand 1 "" "g,g"))
10903 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10904 (clobber (reg:SI LR_REGNO))]
10905 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10908 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10909 output_asm_insn (\"crxor 6,6,6\", operands);
10911 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10912 output_asm_insn (\"creqv 6,6,6\", operands);
10914 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10916 [(set_attr "type" "branch")
10917 (set_attr "length" "4,8")])
10919 (define_insn "*call_value_local32"
10920 [(set (match_operand 0 "" "")
10921 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10922 (match_operand 2 "" "g,g")))
10923 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10924 (clobber (reg:SI LR_REGNO))]
10925 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10928 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10929 output_asm_insn (\"crxor 6,6,6\", operands);
10931 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10932 output_asm_insn (\"creqv 6,6,6\", operands);
10934 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10936 [(set_attr "type" "branch")
10937 (set_attr "length" "4,8")])
10940 (define_insn "*call_value_local64"
10941 [(set (match_operand 0 "" "")
10942 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10943 (match_operand 2 "" "g,g")))
10944 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10945 (clobber (reg:SI LR_REGNO))]
10946 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10949 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10950 output_asm_insn (\"crxor 6,6,6\", operands);
10952 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10953 output_asm_insn (\"creqv 6,6,6\", operands);
10955 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10957 [(set_attr "type" "branch")
10958 (set_attr "length" "4,8")])
10960 ;; Call to function which may be in another module. Restore the TOC
10961 ;; pointer (r2) after the call unless this is System V.
10962 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10963 ;; either the function was not prototyped, or it was prototyped as a
10964 ;; variable argument function. It is > 0 if FP registers were passed
10965 ;; and < 0 if they were not.
10967 (define_insn "*call_indirect_nonlocal_aix32"
10968 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
10969 (match_operand 1 "" "g,g"))
10973 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10974 (clobber (reg:SI LR_REGNO))]
10975 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10976 "b%T0l\;{l|lwz} 2,20(1)"
10977 [(set_attr "type" "jmpreg")
10978 (set_attr "length" "8")])
10980 (define_insn "*call_nonlocal_aix32"
10981 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10982 (match_operand 1 "" "g"))
10983 (use (match_operand:SI 2 "immediate_operand" "O"))
10984 (clobber (reg:SI LR_REGNO))]
10986 && DEFAULT_ABI == ABI_AIX
10987 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10989 [(set_attr "type" "branch")
10990 (set_attr "length" "8")])
10992 (define_insn "*call_indirect_nonlocal_aix64"
10993 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
10994 (match_operand 1 "" "g,g"))
10998 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10999 (clobber (reg:SI LR_REGNO))]
11000 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11001 "b%T0l\;ld 2,40(1)"
11002 [(set_attr "type" "jmpreg")
11003 (set_attr "length" "8")])
11005 (define_insn "*call_nonlocal_aix64"
11006 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11007 (match_operand 1 "" "g"))
11008 (use (match_operand:SI 2 "immediate_operand" "O"))
11009 (clobber (reg:SI LR_REGNO))]
11011 && DEFAULT_ABI == ABI_AIX
11012 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11014 [(set_attr "type" "branch")
11015 (set_attr "length" "8")])
11017 (define_insn "*call_value_indirect_nonlocal_aix32"
11018 [(set (match_operand 0 "" "")
11019 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
11020 (match_operand 2 "" "g,g")))
11024 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11025 (clobber (reg:SI LR_REGNO))]
11026 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11027 "b%T1l\;{l|lwz} 2,20(1)"
11028 [(set_attr "type" "jmpreg")
11029 (set_attr "length" "8")])
11031 (define_insn "*call_value_nonlocal_aix32"
11032 [(set (match_operand 0 "" "")
11033 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11034 (match_operand 2 "" "g")))
11035 (use (match_operand:SI 3 "immediate_operand" "O"))
11036 (clobber (reg:SI LR_REGNO))]
11038 && DEFAULT_ABI == ABI_AIX
11039 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11041 [(set_attr "type" "branch")
11042 (set_attr "length" "8")])
11044 (define_insn "*call_value_indirect_nonlocal_aix64"
11045 [(set (match_operand 0 "" "")
11046 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
11047 (match_operand 2 "" "g,g")))
11051 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11052 (clobber (reg:SI LR_REGNO))]
11053 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11054 "b%T1l\;ld 2,40(1)"
11055 [(set_attr "type" "jmpreg")
11056 (set_attr "length" "8")])
11058 (define_insn "*call_value_nonlocal_aix64"
11059 [(set (match_operand 0 "" "")
11060 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11061 (match_operand 2 "" "g")))
11062 (use (match_operand:SI 3 "immediate_operand" "O"))
11063 (clobber (reg:SI LR_REGNO))]
11065 && DEFAULT_ABI == ABI_AIX
11066 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11068 [(set_attr "type" "branch")
11069 (set_attr "length" "8")])
11071 ;; A function pointer under System V is just a normal pointer
11072 ;; operands[0] is the function pointer
11073 ;; operands[1] is the stack size to clean up
11074 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
11075 ;; which indicates how to set cr1
11077 (define_insn "*call_indirect_nonlocal_sysv<mode>"
11078 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
11079 (match_operand 1 "" "g,g,g,g"))
11080 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
11081 (clobber (reg:SI LR_REGNO))]
11082 "DEFAULT_ABI == ABI_V4
11083 || DEFAULT_ABI == ABI_DARWIN"
11085 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11086 output_asm_insn ("crxor 6,6,6", operands);
11088 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11089 output_asm_insn ("creqv 6,6,6", operands);
11093 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11094 (set_attr "length" "4,4,8,8")])
11096 (define_insn "*call_nonlocal_sysv<mode>"
11097 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11098 (match_operand 1 "" "g,g"))
11099 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11100 (clobber (reg:SI LR_REGNO))]
11101 "(DEFAULT_ABI == ABI_DARWIN
11102 || (DEFAULT_ABI == ABI_V4
11103 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
11105 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11106 output_asm_insn ("crxor 6,6,6", operands);
11108 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11109 output_asm_insn ("creqv 6,6,6", operands);
11112 return output_call(insn, operands, 0, 2);
11114 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11116 if (TARGET_SECURE_PLT && flag_pic == 2)
11117 /* The magic 32768 offset here and in the other sysv call insns
11118 corresponds to the offset of r30 in .got2, as given by LCTOC1.
11119 See sysv4.h:toc_section. */
11120 return "bl %z0+32768@plt";
11122 return "bl %z0@plt";
11128 [(set_attr "type" "branch,branch")
11129 (set_attr "length" "4,8")])
11131 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
11132 [(set (match_operand 0 "" "")
11133 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
11134 (match_operand 2 "" "g,g,g,g")))
11135 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
11136 (clobber (reg:SI LR_REGNO))]
11137 "DEFAULT_ABI == ABI_V4
11138 || DEFAULT_ABI == ABI_DARWIN"
11140 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11141 output_asm_insn ("crxor 6,6,6", operands);
11143 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11144 output_asm_insn ("creqv 6,6,6", operands);
11148 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11149 (set_attr "length" "4,4,8,8")])
11151 (define_insn "*call_value_nonlocal_sysv<mode>"
11152 [(set (match_operand 0 "" "")
11153 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11154 (match_operand 2 "" "g,g")))
11155 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11156 (clobber (reg:SI LR_REGNO))]
11157 "(DEFAULT_ABI == ABI_DARWIN
11158 || (DEFAULT_ABI == ABI_V4
11159 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
11161 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11162 output_asm_insn ("crxor 6,6,6", operands);
11164 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11165 output_asm_insn ("creqv 6,6,6", operands);
11168 return output_call(insn, operands, 1, 3);
11170 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11172 if (TARGET_SECURE_PLT && flag_pic == 2)
11173 return "bl %z1+32768@plt";
11175 return "bl %z1@plt";
11181 [(set_attr "type" "branch,branch")
11182 (set_attr "length" "4,8")])
11184 ;; Call subroutine returning any type.
11185 (define_expand "untyped_call"
11186 [(parallel [(call (match_operand 0 "" "")
11188 (match_operand 1 "" "")
11189 (match_operand 2 "" "")])]
11195 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
11197 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11199 rtx set = XVECEXP (operands[2], 0, i);
11200 emit_move_insn (SET_DEST (set), SET_SRC (set));
11203 /* The optimizer does not know that the call sets the function value
11204 registers we stored in the result block. We avoid problems by
11205 claiming that all hard registers are used and clobbered at this
11207 emit_insn (gen_blockage ());
11212 ;; sibling call patterns
11213 (define_expand "sibcall"
11214 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11215 (match_operand 1 "" ""))
11216 (use (match_operand 2 "" ""))
11217 (use (reg:SI LR_REGNO))
11223 if (MACHOPIC_INDIRECT)
11224 operands[0] = machopic_indirect_call_target (operands[0]);
11227 gcc_assert (GET_CODE (operands[0]) == MEM);
11228 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11230 operands[0] = XEXP (operands[0], 0);
11233 ;; this and similar patterns must be marked as using LR, otherwise
11234 ;; dataflow will try to delete the store into it. This is true
11235 ;; even when the actual reg to jump to is in CTR, when LR was
11236 ;; saved and restored around the PIC-setting BCL.
11237 (define_insn "*sibcall_local32"
11238 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11239 (match_operand 1 "" "g,g"))
11240 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11241 (use (reg:SI LR_REGNO))
11243 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11246 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11247 output_asm_insn (\"crxor 6,6,6\", operands);
11249 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11250 output_asm_insn (\"creqv 6,6,6\", operands);
11252 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11254 [(set_attr "type" "branch")
11255 (set_attr "length" "4,8")])
11257 (define_insn "*sibcall_local64"
11258 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11259 (match_operand 1 "" "g,g"))
11260 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11261 (use (reg:SI LR_REGNO))
11263 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11266 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11267 output_asm_insn (\"crxor 6,6,6\", operands);
11269 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11270 output_asm_insn (\"creqv 6,6,6\", operands);
11272 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11274 [(set_attr "type" "branch")
11275 (set_attr "length" "4,8")])
11277 (define_insn "*sibcall_value_local32"
11278 [(set (match_operand 0 "" "")
11279 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11280 (match_operand 2 "" "g,g")))
11281 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11282 (use (reg:SI LR_REGNO))
11284 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11287 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11288 output_asm_insn (\"crxor 6,6,6\", operands);
11290 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11291 output_asm_insn (\"creqv 6,6,6\", operands);
11293 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11295 [(set_attr "type" "branch")
11296 (set_attr "length" "4,8")])
11299 (define_insn "*sibcall_value_local64"
11300 [(set (match_operand 0 "" "")
11301 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11302 (match_operand 2 "" "g,g")))
11303 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11304 (use (reg:SI LR_REGNO))
11306 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11309 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11310 output_asm_insn (\"crxor 6,6,6\", operands);
11312 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11313 output_asm_insn (\"creqv 6,6,6\", operands);
11315 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11317 [(set_attr "type" "branch")
11318 (set_attr "length" "4,8")])
11320 (define_insn "*sibcall_nonlocal_aix32"
11321 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11322 (match_operand 1 "" "g"))
11323 (use (match_operand:SI 2 "immediate_operand" "O"))
11324 (use (reg:SI LR_REGNO))
11327 && DEFAULT_ABI == ABI_AIX
11328 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11330 [(set_attr "type" "branch")
11331 (set_attr "length" "4")])
11333 (define_insn "*sibcall_nonlocal_aix64"
11334 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11335 (match_operand 1 "" "g"))
11336 (use (match_operand:SI 2 "immediate_operand" "O"))
11337 (use (reg:SI LR_REGNO))
11340 && DEFAULT_ABI == ABI_AIX
11341 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11343 [(set_attr "type" "branch")
11344 (set_attr "length" "4")])
11346 (define_insn "*sibcall_value_nonlocal_aix32"
11347 [(set (match_operand 0 "" "")
11348 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11349 (match_operand 2 "" "g")))
11350 (use (match_operand:SI 3 "immediate_operand" "O"))
11351 (use (reg:SI LR_REGNO))
11354 && DEFAULT_ABI == ABI_AIX
11355 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11357 [(set_attr "type" "branch")
11358 (set_attr "length" "4")])
11360 (define_insn "*sibcall_value_nonlocal_aix64"
11361 [(set (match_operand 0 "" "")
11362 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11363 (match_operand 2 "" "g")))
11364 (use (match_operand:SI 3 "immediate_operand" "O"))
11365 (use (reg:SI LR_REGNO))
11368 && DEFAULT_ABI == ABI_AIX
11369 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11371 [(set_attr "type" "branch")
11372 (set_attr "length" "4")])
11374 (define_insn "*sibcall_nonlocal_sysv<mode>"
11375 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11376 (match_operand 1 "" ""))
11377 (use (match_operand 2 "immediate_operand" "O,n"))
11378 (use (reg:SI LR_REGNO))
11380 "(DEFAULT_ABI == ABI_DARWIN
11381 || DEFAULT_ABI == ABI_V4)
11382 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11385 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11386 output_asm_insn (\"crxor 6,6,6\", operands);
11388 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11389 output_asm_insn (\"creqv 6,6,6\", operands);
11391 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11393 if (TARGET_SECURE_PLT && flag_pic == 2)
11394 return \"b %z0+32768@plt\";
11396 return \"b %z0@plt\";
11401 [(set_attr "type" "branch,branch")
11402 (set_attr "length" "4,8")])
11404 (define_expand "sibcall_value"
11405 [(parallel [(set (match_operand 0 "register_operand" "")
11406 (call (mem:SI (match_operand 1 "address_operand" ""))
11407 (match_operand 2 "" "")))
11408 (use (match_operand 3 "" ""))
11409 (use (reg:SI LR_REGNO))
11415 if (MACHOPIC_INDIRECT)
11416 operands[1] = machopic_indirect_call_target (operands[1]);
11419 gcc_assert (GET_CODE (operands[1]) == MEM);
11420 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11422 operands[1] = XEXP (operands[1], 0);
11425 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
11426 [(set (match_operand 0 "" "")
11427 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11428 (match_operand 2 "" "")))
11429 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11430 (use (reg:SI LR_REGNO))
11432 "(DEFAULT_ABI == ABI_DARWIN
11433 || DEFAULT_ABI == ABI_V4)
11434 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11437 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11438 output_asm_insn (\"crxor 6,6,6\", operands);
11440 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11441 output_asm_insn (\"creqv 6,6,6\", operands);
11443 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11445 if (TARGET_SECURE_PLT && flag_pic == 2)
11446 return \"b %z1+32768@plt\";
11448 return \"b %z1@plt\";
11453 [(set_attr "type" "branch,branch")
11454 (set_attr "length" "4,8")])
11456 (define_expand "sibcall_epilogue"
11457 [(use (const_int 0))]
11458 "TARGET_SCHED_PROLOG"
11461 rs6000_emit_epilogue (TRUE);
11465 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11466 ;; all of memory. This blocks insns from being moved across this point.
11468 (define_insn "blockage"
11469 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
11473 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
11474 ;; signed & unsigned, and one type of branch.
11476 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11477 ;; insns, and branches. We store the operands of compares until we see
11479 (define_expand "cmp<mode>"
11481 (compare (match_operand:GPR 0 "gpc_reg_operand" "")
11482 (match_operand:GPR 1 "reg_or_short_operand" "")))]
11486 /* Take care of the possibility that operands[1] might be negative but
11487 this might be a logical operation. That insn doesn't exist. */
11488 if (GET_CODE (operands[1]) == CONST_INT
11489 && INTVAL (operands[1]) < 0)
11490 operands[1] = force_reg (<MODE>mode, operands[1]);
11492 rs6000_compare_op0 = operands[0];
11493 rs6000_compare_op1 = operands[1];
11494 rs6000_compare_fp_p = 0;
11498 (define_expand "cmp<mode>"
11499 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
11500 (match_operand:FP 1 "gpc_reg_operand" "")))]
11504 rs6000_compare_op0 = operands[0];
11505 rs6000_compare_op1 = operands[1];
11506 rs6000_compare_fp_p = 1;
11510 (define_expand "beq"
11511 [(use (match_operand 0 "" ""))]
11513 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
11515 (define_expand "bne"
11516 [(use (match_operand 0 "" ""))]
11518 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
11520 (define_expand "bge"
11521 [(use (match_operand 0 "" ""))]
11523 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
11525 (define_expand "bgt"
11526 [(use (match_operand 0 "" ""))]
11528 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
11530 (define_expand "ble"
11531 [(use (match_operand 0 "" ""))]
11533 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
11535 (define_expand "blt"
11536 [(use (match_operand 0 "" ""))]
11538 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
11540 (define_expand "bgeu"
11541 [(use (match_operand 0 "" ""))]
11543 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
11545 (define_expand "bgtu"
11546 [(use (match_operand 0 "" ""))]
11548 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
11550 (define_expand "bleu"
11551 [(use (match_operand 0 "" ""))]
11553 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
11555 (define_expand "bltu"
11556 [(use (match_operand 0 "" ""))]
11558 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
11560 (define_expand "bunordered"
11561 [(use (match_operand 0 "" ""))]
11562 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11563 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
11565 (define_expand "bordered"
11566 [(use (match_operand 0 "" ""))]
11567 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11568 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
11570 (define_expand "buneq"
11571 [(use (match_operand 0 "" ""))]
11572 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11573 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
11575 (define_expand "bunge"
11576 [(use (match_operand 0 "" ""))]
11577 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11578 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
11580 (define_expand "bungt"
11581 [(use (match_operand 0 "" ""))]
11582 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11583 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
11585 (define_expand "bunle"
11586 [(use (match_operand 0 "" ""))]
11587 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11588 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
11590 (define_expand "bunlt"
11591 [(use (match_operand 0 "" ""))]
11592 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11593 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
11595 (define_expand "bltgt"
11596 [(use (match_operand 0 "" ""))]
11598 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
11600 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11601 ;; For SEQ, likewise, except that comparisons with zero should be done
11602 ;; with an scc insns. However, due to the order that combine see the
11603 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11604 ;; the cases we don't want to handle.
11605 (define_expand "seq"
11606 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11608 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
11610 (define_expand "sne"
11611 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11615 if (! rs6000_compare_fp_p)
11618 rs6000_emit_sCOND (NE, operands[0]);
11622 ;; A >= 0 is best done the portable way for A an integer.
11623 (define_expand "sge"
11624 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11628 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11631 rs6000_emit_sCOND (GE, operands[0]);
11635 ;; A > 0 is best done using the portable sequence, so fail in that case.
11636 (define_expand "sgt"
11637 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11641 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11644 rs6000_emit_sCOND (GT, operands[0]);
11648 ;; A <= 0 is best done the portable way for A an integer.
11649 (define_expand "sle"
11650 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11654 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11657 rs6000_emit_sCOND (LE, operands[0]);
11661 ;; A < 0 is best done in the portable way for A an integer.
11662 (define_expand "slt"
11663 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11667 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11670 rs6000_emit_sCOND (LT, operands[0]);
11674 (define_expand "sgeu"
11675 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11677 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11679 (define_expand "sgtu"
11680 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11682 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
11684 (define_expand "sleu"
11685 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11687 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11689 (define_expand "sltu"
11690 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11692 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
11694 (define_expand "sunordered"
11695 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11696 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11697 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
11699 (define_expand "sordered"
11700 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11701 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11702 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11704 (define_expand "suneq"
11705 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11706 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11707 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11709 (define_expand "sunge"
11710 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11711 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11712 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11714 (define_expand "sungt"
11715 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11716 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11717 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11719 (define_expand "sunle"
11720 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11721 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11722 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11724 (define_expand "sunlt"
11725 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11726 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11727 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11729 (define_expand "sltgt"
11730 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11732 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11734 (define_expand "stack_protect_set"
11735 [(match_operand 0 "memory_operand" "")
11736 (match_operand 1 "memory_operand" "")]
11739 #ifdef TARGET_THREAD_SSP_OFFSET
11740 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11741 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11742 operands[1] = gen_rtx_MEM (Pmode, addr);
11745 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11747 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11751 (define_insn "stack_protect_setsi"
11752 [(set (match_operand:SI 0 "memory_operand" "=m")
11753 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11754 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11756 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
11757 [(set_attr "type" "three")
11758 (set_attr "length" "12")])
11760 (define_insn "stack_protect_setdi"
11761 [(set (match_operand:DI 0 "memory_operand" "=m")
11762 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11763 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11765 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
11766 [(set_attr "type" "three")
11767 (set_attr "length" "12")])
11769 (define_expand "stack_protect_test"
11770 [(match_operand 0 "memory_operand" "")
11771 (match_operand 1 "memory_operand" "")
11772 (match_operand 2 "" "")]
11775 #ifdef TARGET_THREAD_SSP_OFFSET
11776 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11777 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11778 operands[1] = gen_rtx_MEM (Pmode, addr);
11780 rs6000_compare_op0 = operands[0];
11781 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
11783 rs6000_compare_fp_p = 0;
11784 emit_jump_insn (gen_beq (operands[2]));
11788 (define_insn "stack_protect_testsi"
11789 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11790 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11791 (match_operand:SI 2 "memory_operand" "m,m")]
11793 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11794 (clobber (match_scratch:SI 3 "=&r,&r"))]
11797 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11798 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11799 [(set_attr "length" "16,20")])
11801 (define_insn "stack_protect_testdi"
11802 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11803 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
11804 (match_operand:DI 2 "memory_operand" "m,m")]
11806 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11807 (clobber (match_scratch:DI 3 "=&r,&r"))]
11810 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11811 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11812 [(set_attr "length" "16,20")])
11815 ;; Here are the actual compare insns.
11816 (define_insn "*cmp<mode>_internal1"
11817 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11818 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11819 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
11821 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
11822 [(set_attr "type" "cmp")])
11824 ;; If we are comparing a register for equality with a large constant,
11825 ;; we can do this with an XOR followed by a compare. But this is profitable
11826 ;; only if the large constant is only used for the comparison (and in this
11827 ;; case we already have a register to reuse as scratch).
11829 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11830 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
11833 [(set (match_operand:SI 0 "register_operand")
11834 (match_operand:SI 1 "logical_const_operand" ""))
11835 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
11837 (match_operand:SI 2 "logical_const_operand" "")]))
11838 (set (match_operand:CC 4 "cc_reg_operand" "")
11839 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
11842 (if_then_else (match_operator 6 "equality_operator"
11843 [(match_dup 4) (const_int 0)])
11844 (match_operand 7 "" "")
11845 (match_operand 8 "" "")))]
11846 "peep2_reg_dead_p (3, operands[0])
11847 && peep2_reg_dead_p (4, operands[4])"
11848 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
11849 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11850 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11853 /* Get the constant we are comparing against, and see what it looks like
11854 when sign-extended from 16 to 32 bits. Then see what constant we could
11855 XOR with SEXTC to get the sign-extended value. */
11856 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
11858 operands[1], operands[2]);
11859 HOST_WIDE_INT c = INTVAL (cnst);
11860 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11861 HOST_WIDE_INT xorv = c ^ sextc;
11863 operands[9] = GEN_INT (xorv);
11864 operands[10] = GEN_INT (sextc);
11867 (define_insn "*cmpsi_internal2"
11868 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11869 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11870 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11872 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
11873 [(set_attr "type" "cmp")])
11875 (define_insn "*cmpdi_internal2"
11876 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11877 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11878 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11880 "cmpld%I2 %0,%1,%b2"
11881 [(set_attr "type" "cmp")])
11883 ;; The following two insns don't exist as single insns, but if we provide
11884 ;; them, we can swap an add and compare, which will enable us to overlap more
11885 ;; of the required delay between a compare and branch. We generate code for
11886 ;; them by splitting.
11889 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11890 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11891 (match_operand:SI 2 "short_cint_operand" "i")))
11892 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11893 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11896 [(set_attr "length" "8")])
11899 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11900 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11901 (match_operand:SI 2 "u_short_cint_operand" "i")))
11902 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11903 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11906 [(set_attr "length" "8")])
11909 [(set (match_operand:CC 3 "cc_reg_operand" "")
11910 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11911 (match_operand:SI 2 "short_cint_operand" "")))
11912 (set (match_operand:SI 0 "gpc_reg_operand" "")
11913 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11915 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11916 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11919 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11920 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11921 (match_operand:SI 2 "u_short_cint_operand" "")))
11922 (set (match_operand:SI 0 "gpc_reg_operand" "")
11923 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11925 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11926 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11928 (define_insn "*cmpsf_internal1"
11929 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11930 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11931 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11932 "TARGET_HARD_FLOAT && TARGET_FPRS"
11934 [(set_attr "type" "fpcompare")])
11936 (define_insn "*cmpdf_internal1"
11937 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11938 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11939 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11940 "TARGET_HARD_FLOAT && TARGET_FPRS"
11942 [(set_attr "type" "fpcompare")])
11944 ;; Only need to compare second words if first words equal
11945 (define_insn "*cmptf_internal1"
11946 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11947 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11948 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11949 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
11950 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11951 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11952 [(set_attr "type" "fpcompare")
11953 (set_attr "length" "12")])
11955 (define_insn_and_split "*cmptf_internal2"
11956 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11957 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11958 (match_operand:TF 2 "gpc_reg_operand" "f")))
11959 (clobber (match_scratch:DF 3 "=f"))
11960 (clobber (match_scratch:DF 4 "=f"))
11961 (clobber (match_scratch:DF 5 "=f"))
11962 (clobber (match_scratch:DF 6 "=f"))
11963 (clobber (match_scratch:DF 7 "=f"))
11964 (clobber (match_scratch:DF 8 "=f"))
11965 (clobber (match_scratch:DF 9 "=f"))
11966 (clobber (match_scratch:DF 10 "=f"))]
11967 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
11968 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11970 "&& reload_completed"
11971 [(set (match_dup 3) (match_dup 13))
11972 (set (match_dup 4) (match_dup 14))
11973 (set (match_dup 9) (abs:DF (match_dup 5)))
11974 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11975 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11976 (label_ref (match_dup 11))
11978 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11979 (set (pc) (label_ref (match_dup 12)))
11981 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11982 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11983 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11984 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
11987 REAL_VALUE_TYPE rv;
11988 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
11989 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
11991 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11992 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11993 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11994 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11995 operands[11] = gen_label_rtx ();
11996 operands[12] = gen_label_rtx ();
11998 operands[13] = force_const_mem (DFmode,
11999 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
12000 operands[14] = force_const_mem (DFmode,
12001 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
12005 operands[13] = gen_const_mem (DFmode,
12006 create_TOC_reference (XEXP (operands[13], 0)));
12007 operands[14] = gen_const_mem (DFmode,
12008 create_TOC_reference (XEXP (operands[14], 0)));
12009 set_mem_alias_set (operands[13], get_TOC_alias_set ());
12010 set_mem_alias_set (operands[14], get_TOC_alias_set ());
12014 ;; Now we have the scc insns. We can do some combinations because of the
12015 ;; way the machine works.
12017 ;; Note that this is probably faster if we can put an insn between the
12018 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
12019 ;; cases the insns below which don't use an intermediate CR field will
12020 ;; be used instead.
12022 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12023 (match_operator:SI 1 "scc_comparison_operator"
12024 [(match_operand 2 "cc_reg_operand" "y")
12027 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12028 [(set (attr "type")
12029 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12030 (const_string "mfcrf")
12032 (const_string "mfcr")))
12033 (set_attr "length" "8")])
12035 ;; Same as above, but get the GT bit.
12036 (define_insn "move_from_CR_gt_bit"
12037 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12038 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
12040 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
12041 [(set_attr "type" "mfcr")
12042 (set_attr "length" "8")])
12044 ;; Same as above, but get the OV/ORDERED bit.
12045 (define_insn "move_from_CR_ov_bit"
12046 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12047 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
12049 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
12050 [(set_attr "type" "mfcr")
12051 (set_attr "length" "8")])
12054 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12055 (match_operator:DI 1 "scc_comparison_operator"
12056 [(match_operand 2 "cc_reg_operand" "y")
12059 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12060 [(set (attr "type")
12061 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12062 (const_string "mfcrf")
12064 (const_string "mfcr")))
12065 (set_attr "length" "8")])
12068 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12069 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12070 [(match_operand 2 "cc_reg_operand" "y,y")
12073 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
12074 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12077 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
12079 [(set_attr "type" "delayed_compare")
12080 (set_attr "length" "8,16")])
12083 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12084 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12085 [(match_operand 2 "cc_reg_operand" "")
12088 (set (match_operand:SI 3 "gpc_reg_operand" "")
12089 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12090 "TARGET_32BIT && reload_completed"
12091 [(set (match_dup 3)
12092 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12094 (compare:CC (match_dup 3)
12099 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12100 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12101 [(match_operand 2 "cc_reg_operand" "y")
12103 (match_operand:SI 3 "const_int_operand" "n")))]
12107 int is_bit = ccr_bit (operands[1], 1);
12108 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12111 if (is_bit >= put_bit)
12112 count = is_bit - put_bit;
12114 count = 32 - (put_bit - is_bit);
12116 operands[4] = GEN_INT (count);
12117 operands[5] = GEN_INT (put_bit);
12119 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
12121 [(set (attr "type")
12122 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12123 (const_string "mfcrf")
12125 (const_string "mfcr")))
12126 (set_attr "length" "8")])
12129 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12131 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12132 [(match_operand 2 "cc_reg_operand" "y,y")
12134 (match_operand:SI 3 "const_int_operand" "n,n"))
12136 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
12137 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12142 int is_bit = ccr_bit (operands[1], 1);
12143 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12146 /* Force split for non-cc0 compare. */
12147 if (which_alternative == 1)
12150 if (is_bit >= put_bit)
12151 count = is_bit - put_bit;
12153 count = 32 - (put_bit - is_bit);
12155 operands[5] = GEN_INT (count);
12156 operands[6] = GEN_INT (put_bit);
12158 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
12160 [(set_attr "type" "delayed_compare")
12161 (set_attr "length" "8,16")])
12164 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12166 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12167 [(match_operand 2 "cc_reg_operand" "")
12169 (match_operand:SI 3 "const_int_operand" ""))
12171 (set (match_operand:SI 4 "gpc_reg_operand" "")
12172 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12175 [(set (match_dup 4)
12176 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12179 (compare:CC (match_dup 4)
12183 ;; There is a 3 cycle delay between consecutive mfcr instructions
12184 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
12187 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12188 (match_operator:SI 1 "scc_comparison_operator"
12189 [(match_operand 2 "cc_reg_operand" "y")
12191 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
12192 (match_operator:SI 4 "scc_comparison_operator"
12193 [(match_operand 5 "cc_reg_operand" "y")
12195 "REGNO (operands[2]) != REGNO (operands[5])"
12196 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
12197 [(set_attr "type" "mfcr")
12198 (set_attr "length" "12")])
12201 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12202 (match_operator:DI 1 "scc_comparison_operator"
12203 [(match_operand 2 "cc_reg_operand" "y")
12205 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12206 (match_operator:DI 4 "scc_comparison_operator"
12207 [(match_operand 5 "cc_reg_operand" "y")
12209 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
12210 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
12211 [(set_attr "type" "mfcr")
12212 (set_attr "length" "12")])
12214 ;; There are some scc insns that can be done directly, without a compare.
12215 ;; These are faster because they don't involve the communications between
12216 ;; the FXU and branch units. In fact, we will be replacing all of the
12217 ;; integer scc insns here or in the portable methods in emit_store_flag.
12219 ;; Also support (neg (scc ..)) since that construct is used to replace
12220 ;; branches, (plus (scc ..) ..) since that construct is common and
12221 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12222 ;; cases where it is no more expensive than (neg (scc ..)).
12224 ;; Have reload force a constant into a register for the simple insns that
12225 ;; otherwise won't accept constants. We do this because it is faster than
12226 ;; the cmp/mfcr sequence we would otherwise generate.
12228 (define_mode_attr scc_eq_op2 [(SI "rKLI")
12231 (define_insn_and_split "*eq<mode>"
12232 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12233 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
12234 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
12238 [(set (match_dup 0)
12239 (clz:GPR (match_dup 3)))
12241 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
12243 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12245 /* Use output operand as intermediate. */
12246 operands[3] = operands[0];
12248 if (logical_operand (operands[2], <MODE>mode))
12249 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12250 gen_rtx_XOR (<MODE>mode,
12251 operands[1], operands[2])));
12253 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12254 gen_rtx_PLUS (<MODE>mode, operands[1],
12255 negate_rtx (<MODE>mode,
12259 operands[3] = operands[1];
12261 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12264 (define_insn_and_split "*eq<mode>_compare"
12265 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12267 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12268 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
12270 (set (match_operand:P 0 "gpc_reg_operand" "=r")
12271 (eq:P (match_dup 1) (match_dup 2)))]
12272 "!TARGET_POWER && optimize_size"
12274 "!TARGET_POWER && optimize_size"
12275 [(set (match_dup 0)
12276 (clz:P (match_dup 4)))
12277 (parallel [(set (match_dup 3)
12278 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
12281 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
12283 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12285 /* Use output operand as intermediate. */
12286 operands[4] = operands[0];
12288 if (logical_operand (operands[2], <MODE>mode))
12289 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12290 gen_rtx_XOR (<MODE>mode,
12291 operands[1], operands[2])));
12293 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12294 gen_rtx_PLUS (<MODE>mode, operands[1],
12295 negate_rtx (<MODE>mode,
12299 operands[4] = operands[1];
12301 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12304 (define_insn "*eqsi_power"
12305 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
12306 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12307 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
12308 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
12311 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12312 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
12313 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12314 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12315 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
12316 [(set_attr "type" "three,two,three,three,three")
12317 (set_attr "length" "12,8,12,12,12")])
12319 ;; We have insns of the form shown by the first define_insn below. If
12320 ;; there is something inside the comparison operation, we must split it.
12322 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12323 (plus:SI (match_operator 1 "comparison_operator"
12324 [(match_operand:SI 2 "" "")
12325 (match_operand:SI 3
12326 "reg_or_cint_operand" "")])
12327 (match_operand:SI 4 "gpc_reg_operand" "")))
12328 (clobber (match_operand:SI 5 "register_operand" ""))]
12329 "! gpc_reg_operand (operands[2], SImode)"
12330 [(set (match_dup 5) (match_dup 2))
12331 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
12334 (define_insn "*plus_eqsi"
12335 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
12336 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12337 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
12338 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
12341 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12342 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
12343 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12344 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12345 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12346 [(set_attr "type" "three,two,three,three,three")
12347 (set_attr "length" "12,8,12,12,12")])
12349 (define_insn "*compare_plus_eqsi"
12350 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12353 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12354 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12355 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12357 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
12358 "TARGET_32BIT && optimize_size"
12360 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12361 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
12362 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12363 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12364 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12370 [(set_attr "type" "compare")
12371 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12374 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12377 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12378 (match_operand:SI 2 "scc_eq_operand" ""))
12379 (match_operand:SI 3 "gpc_reg_operand" ""))
12381 (clobber (match_scratch:SI 4 ""))]
12382 "TARGET_32BIT && optimize_size && reload_completed"
12383 [(set (match_dup 4)
12384 (plus:SI (eq:SI (match_dup 1)
12388 (compare:CC (match_dup 4)
12392 (define_insn "*plus_eqsi_compare"
12393 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12396 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12397 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12398 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12400 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12401 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12402 "TARGET_32BIT && optimize_size"
12404 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12405 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
12406 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12407 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12408 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12414 [(set_attr "type" "compare")
12415 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12418 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12421 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12422 (match_operand:SI 2 "scc_eq_operand" ""))
12423 (match_operand:SI 3 "gpc_reg_operand" ""))
12425 (set (match_operand:SI 0 "gpc_reg_operand" "")
12426 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12427 "TARGET_32BIT && optimize_size && reload_completed"
12428 [(set (match_dup 0)
12429 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12431 (compare:CC (match_dup 0)
12435 (define_insn "*neg_eq0<mode>"
12436 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12437 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12440 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
12441 [(set_attr "type" "two")
12442 (set_attr "length" "8")])
12444 (define_insn_and_split "*neg_eq<mode>"
12445 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12446 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12447 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
12451 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12453 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12455 /* Use output operand as intermediate. */
12456 operands[3] = operands[0];
12458 if (logical_operand (operands[2], <MODE>mode))
12459 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12460 gen_rtx_XOR (<MODE>mode,
12461 operands[1], operands[2])));
12463 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12464 gen_rtx_PLUS (<MODE>mode, operands[1],
12465 negate_rtx (<MODE>mode,
12469 operands[3] = operands[1];
12472 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
12473 ;; since it nabs/sr is just as fast.
12474 (define_insn "*ne0si"
12475 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12476 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12478 (clobber (match_scratch:SI 2 "=&r"))]
12479 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
12480 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
12481 [(set_attr "type" "two")
12482 (set_attr "length" "8")])
12484 (define_insn "*ne0di"
12485 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12486 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12488 (clobber (match_scratch:DI 2 "=&r"))]
12490 "addic %2,%1,-1\;subfe %0,%2,%1"
12491 [(set_attr "type" "two")
12492 (set_attr "length" "8")])
12494 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
12495 (define_insn "*plus_ne0si"
12496 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12497 (plus:SI (lshiftrt:SI
12498 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12500 (match_operand:SI 2 "gpc_reg_operand" "r")))
12501 (clobber (match_scratch:SI 3 "=&r"))]
12503 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
12504 [(set_attr "type" "two")
12505 (set_attr "length" "8")])
12507 (define_insn "*plus_ne0di"
12508 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12509 (plus:DI (lshiftrt:DI
12510 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12512 (match_operand:DI 2 "gpc_reg_operand" "r")))
12513 (clobber (match_scratch:DI 3 "=&r"))]
12515 "addic %3,%1,-1\;addze %0,%2"
12516 [(set_attr "type" "two")
12517 (set_attr "length" "8")])
12519 (define_insn "*compare_plus_ne0si"
12520 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12522 (plus:SI (lshiftrt:SI
12523 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12525 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12527 (clobber (match_scratch:SI 3 "=&r,&r"))
12528 (clobber (match_scratch:SI 4 "=X,&r"))]
12531 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
12533 [(set_attr "type" "compare")
12534 (set_attr "length" "8,12")])
12537 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12539 (plus:SI (lshiftrt:SI
12540 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12542 (match_operand:SI 2 "gpc_reg_operand" ""))
12544 (clobber (match_scratch:SI 3 ""))
12545 (clobber (match_scratch:SI 4 ""))]
12546 "TARGET_32BIT && reload_completed"
12547 [(parallel [(set (match_dup 3)
12548 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
12551 (clobber (match_dup 4))])
12553 (compare:CC (match_dup 3)
12557 (define_insn "*compare_plus_ne0di"
12558 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12560 (plus:DI (lshiftrt:DI
12561 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12563 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12565 (clobber (match_scratch:DI 3 "=&r,&r"))]
12568 addic %3,%1,-1\;addze. %3,%2
12570 [(set_attr "type" "compare")
12571 (set_attr "length" "8,12")])
12574 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12576 (plus:DI (lshiftrt:DI
12577 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12579 (match_operand:DI 2 "gpc_reg_operand" ""))
12581 (clobber (match_scratch:DI 3 ""))]
12582 "TARGET_64BIT && reload_completed"
12583 [(set (match_dup 3)
12584 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12588 (compare:CC (match_dup 3)
12592 (define_insn "*plus_ne0si_compare"
12593 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12595 (plus:SI (lshiftrt:SI
12596 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12598 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12600 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12601 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12603 (clobber (match_scratch:SI 3 "=&r,&r"))]
12606 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
12608 [(set_attr "type" "compare")
12609 (set_attr "length" "8,12")])
12612 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12614 (plus:SI (lshiftrt:SI
12615 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12617 (match_operand:SI 2 "gpc_reg_operand" ""))
12619 (set (match_operand:SI 0 "gpc_reg_operand" "")
12620 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12622 (clobber (match_scratch:SI 3 ""))]
12623 "TARGET_32BIT && reload_completed"
12624 [(parallel [(set (match_dup 0)
12625 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12627 (clobber (match_dup 3))])
12629 (compare:CC (match_dup 0)
12633 (define_insn "*plus_ne0di_compare"
12634 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12636 (plus:DI (lshiftrt:DI
12637 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12639 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12641 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12642 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12644 (clobber (match_scratch:DI 3 "=&r,&r"))]
12647 addic %3,%1,-1\;addze. %0,%2
12649 [(set_attr "type" "compare")
12650 (set_attr "length" "8,12")])
12653 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12655 (plus:DI (lshiftrt:DI
12656 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12658 (match_operand:DI 2 "gpc_reg_operand" ""))
12660 (set (match_operand:DI 0 "gpc_reg_operand" "")
12661 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12663 (clobber (match_scratch:DI 3 ""))]
12664 "TARGET_64BIT && reload_completed"
12665 [(parallel [(set (match_dup 0)
12666 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12668 (clobber (match_dup 3))])
12670 (compare:CC (match_dup 0)
12675 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12676 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12677 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12678 (clobber (match_scratch:SI 3 "=r,X"))]
12681 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
12682 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
12683 [(set_attr "length" "12")])
12686 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12688 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12689 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12691 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12692 (le:SI (match_dup 1) (match_dup 2)))
12693 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
12696 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12697 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
12700 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
12701 (set_attr "length" "12,12,16,16")])
12704 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12706 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12707 (match_operand:SI 2 "reg_or_short_operand" ""))
12709 (set (match_operand:SI 0 "gpc_reg_operand" "")
12710 (le:SI (match_dup 1) (match_dup 2)))
12711 (clobber (match_scratch:SI 3 ""))]
12712 "TARGET_POWER && reload_completed"
12713 [(parallel [(set (match_dup 0)
12714 (le:SI (match_dup 1) (match_dup 2)))
12715 (clobber (match_dup 3))])
12717 (compare:CC (match_dup 0)
12722 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12723 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12724 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
12725 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12728 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12729 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
12730 [(set_attr "length" "12")])
12733 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12735 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12736 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12737 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12739 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12742 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12743 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12746 [(set_attr "type" "compare")
12747 (set_attr "length" "12,12,16,16")])
12750 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12752 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12753 (match_operand:SI 2 "reg_or_short_operand" ""))
12754 (match_operand:SI 3 "gpc_reg_operand" ""))
12756 (clobber (match_scratch:SI 4 ""))]
12757 "TARGET_POWER && reload_completed"
12758 [(set (match_dup 4)
12759 (plus:SI (le:SI (match_dup 1) (match_dup 2))
12762 (compare:CC (match_dup 4)
12767 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12769 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12770 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12771 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12773 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12774 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12777 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12778 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
12781 [(set_attr "type" "compare")
12782 (set_attr "length" "12,12,16,16")])
12785 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12787 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12788 (match_operand:SI 2 "reg_or_short_operand" ""))
12789 (match_operand:SI 3 "gpc_reg_operand" ""))
12791 (set (match_operand:SI 0 "gpc_reg_operand" "")
12792 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12793 "TARGET_POWER && reload_completed"
12794 [(set (match_dup 0)
12795 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12797 (compare:CC (match_dup 0)
12802 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12803 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12804 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
12807 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12808 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
12809 [(set_attr "length" "12")])
12811 (define_insn "*leu<mode>"
12812 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12813 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12814 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12816 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12817 [(set_attr "type" "three")
12818 (set_attr "length" "12")])
12820 (define_insn "*leu<mode>_compare"
12821 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12823 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12824 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12826 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12827 (leu:P (match_dup 1) (match_dup 2)))]
12830 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12832 [(set_attr "type" "compare")
12833 (set_attr "length" "12,16")])
12836 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12838 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12839 (match_operand:P 2 "reg_or_short_operand" ""))
12841 (set (match_operand:P 0 "gpc_reg_operand" "")
12842 (leu:P (match_dup 1) (match_dup 2)))]
12844 [(set (match_dup 0)
12845 (leu:P (match_dup 1) (match_dup 2)))
12847 (compare:CC (match_dup 0)
12851 (define_insn "*plus_leu<mode>"
12852 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12853 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12854 (match_operand:P 2 "reg_or_short_operand" "rI"))
12855 (match_operand:P 3 "gpc_reg_operand" "r")))]
12857 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12858 [(set_attr "type" "two")
12859 (set_attr "length" "8")])
12862 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12864 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12865 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12866 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12868 (clobber (match_scratch:SI 4 "=&r,&r"))]
12871 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12873 [(set_attr "type" "compare")
12874 (set_attr "length" "8,12")])
12877 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12879 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12880 (match_operand:SI 2 "reg_or_short_operand" ""))
12881 (match_operand:SI 3 "gpc_reg_operand" ""))
12883 (clobber (match_scratch:SI 4 ""))]
12884 "TARGET_32BIT && reload_completed"
12885 [(set (match_dup 4)
12886 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12889 (compare:CC (match_dup 4)
12894 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12896 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12897 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12898 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12900 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12901 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12904 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12906 [(set_attr "type" "compare")
12907 (set_attr "length" "8,12")])
12910 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12912 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12913 (match_operand:SI 2 "reg_or_short_operand" ""))
12914 (match_operand:SI 3 "gpc_reg_operand" ""))
12916 (set (match_operand:SI 0 "gpc_reg_operand" "")
12917 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12918 "TARGET_32BIT && reload_completed"
12919 [(set (match_dup 0)
12920 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12922 (compare:CC (match_dup 0)
12926 (define_insn "*neg_leu<mode>"
12927 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12928 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12929 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12931 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12932 [(set_attr "type" "three")
12933 (set_attr "length" "12")])
12935 (define_insn "*and_neg_leu<mode>"
12936 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12938 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12939 (match_operand:P 2 "reg_or_short_operand" "rI")))
12940 (match_operand:P 3 "gpc_reg_operand" "r")))]
12942 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12943 [(set_attr "type" "three")
12944 (set_attr "length" "12")])
12947 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12950 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12951 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12952 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12954 (clobber (match_scratch:SI 4 "=&r,&r"))]
12957 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12959 [(set_attr "type" "compare")
12960 (set_attr "length" "12,16")])
12963 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12966 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12967 (match_operand:SI 2 "reg_or_short_operand" "")))
12968 (match_operand:SI 3 "gpc_reg_operand" ""))
12970 (clobber (match_scratch:SI 4 ""))]
12971 "TARGET_32BIT && reload_completed"
12972 [(set (match_dup 4)
12973 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12976 (compare:CC (match_dup 4)
12981 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12984 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12985 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12986 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12988 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12989 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12992 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12994 [(set_attr "type" "compare")
12995 (set_attr "length" "12,16")])
12998 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13001 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13002 (match_operand:SI 2 "reg_or_short_operand" "")))
13003 (match_operand:SI 3 "gpc_reg_operand" ""))
13005 (set (match_operand:SI 0 "gpc_reg_operand" "")
13006 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13007 "TARGET_32BIT && reload_completed"
13008 [(set (match_dup 0)
13009 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13012 (compare:CC (match_dup 0)
13017 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13018 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13019 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13021 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13022 [(set_attr "length" "12")])
13025 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13027 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13028 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13030 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13031 (lt:SI (match_dup 1) (match_dup 2)))]
13034 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13036 [(set_attr "type" "delayed_compare")
13037 (set_attr "length" "12,16")])
13040 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13042 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13043 (match_operand:SI 2 "reg_or_short_operand" ""))
13045 (set (match_operand:SI 0 "gpc_reg_operand" "")
13046 (lt:SI (match_dup 1) (match_dup 2)))]
13047 "TARGET_POWER && reload_completed"
13048 [(set (match_dup 0)
13049 (lt:SI (match_dup 1) (match_dup 2)))
13051 (compare:CC (match_dup 0)
13056 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13057 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13058 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13059 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13061 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13062 [(set_attr "length" "12")])
13065 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13067 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13068 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13069 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13071 (clobber (match_scratch:SI 4 "=&r,&r"))]
13074 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13076 [(set_attr "type" "compare")
13077 (set_attr "length" "12,16")])
13080 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13082 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13083 (match_operand:SI 2 "reg_or_short_operand" ""))
13084 (match_operand:SI 3 "gpc_reg_operand" ""))
13086 (clobber (match_scratch:SI 4 ""))]
13087 "TARGET_POWER && reload_completed"
13088 [(set (match_dup 4)
13089 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
13092 (compare:CC (match_dup 4)
13097 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13099 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13100 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13101 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13103 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13104 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13107 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13109 [(set_attr "type" "compare")
13110 (set_attr "length" "12,16")])
13113 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13115 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13116 (match_operand:SI 2 "reg_or_short_operand" ""))
13117 (match_operand:SI 3 "gpc_reg_operand" ""))
13119 (set (match_operand:SI 0 "gpc_reg_operand" "")
13120 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13121 "TARGET_POWER && reload_completed"
13122 [(set (match_dup 0)
13123 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13125 (compare:CC (match_dup 0)
13130 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13131 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13132 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13134 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13135 [(set_attr "length" "12")])
13137 (define_insn_and_split "*ltu<mode>"
13138 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13139 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13140 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13144 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13145 (set (match_dup 0) (neg:P (match_dup 0)))]
13148 (define_insn_and_split "*ltu<mode>_compare"
13149 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13151 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13152 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13154 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13155 (ltu:P (match_dup 1) (match_dup 2)))]
13159 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13160 (parallel [(set (match_dup 3)
13161 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13162 (set (match_dup 0) (neg:P (match_dup 0)))])]
13165 (define_insn_and_split "*plus_ltu<mode>"
13166 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
13167 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13168 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13169 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
13172 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13173 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13174 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13177 (define_insn_and_split "*plus_ltu<mode>_compare"
13178 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13180 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13181 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13182 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13184 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13185 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13188 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13189 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13190 (parallel [(set (match_dup 4)
13191 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13193 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13196 (define_insn "*neg_ltu<mode>"
13197 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13198 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13199 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
13202 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
13203 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
13204 [(set_attr "type" "two")
13205 (set_attr "length" "8")])
13208 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13209 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13210 (match_operand:SI 2 "reg_or_short_operand" "rI")))
13211 (clobber (match_scratch:SI 3 "=r"))]
13213 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
13214 [(set_attr "length" "12")])
13217 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13219 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13220 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13222 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13223 (ge:SI (match_dup 1) (match_dup 2)))
13224 (clobber (match_scratch:SI 3 "=r,r"))]
13227 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13229 [(set_attr "type" "compare")
13230 (set_attr "length" "12,16")])
13233 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13235 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13236 (match_operand:SI 2 "reg_or_short_operand" ""))
13238 (set (match_operand:SI 0 "gpc_reg_operand" "")
13239 (ge:SI (match_dup 1) (match_dup 2)))
13240 (clobber (match_scratch:SI 3 ""))]
13241 "TARGET_POWER && reload_completed"
13242 [(parallel [(set (match_dup 0)
13243 (ge:SI (match_dup 1) (match_dup 2)))
13244 (clobber (match_dup 3))])
13246 (compare:CC (match_dup 0)
13251 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13252 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13253 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13254 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13256 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
13257 [(set_attr "length" "12")])
13260 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13262 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13263 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13264 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13266 (clobber (match_scratch:SI 4 "=&r,&r"))]
13269 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13271 [(set_attr "type" "compare")
13272 (set_attr "length" "12,16")])
13275 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13277 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13278 (match_operand:SI 2 "reg_or_short_operand" ""))
13279 (match_operand:SI 3 "gpc_reg_operand" ""))
13281 (clobber (match_scratch:SI 4 ""))]
13282 "TARGET_POWER && reload_completed"
13283 [(set (match_dup 4)
13284 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
13287 (compare:CC (match_dup 4)
13292 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13294 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13295 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13296 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13298 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13299 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13302 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13304 [(set_attr "type" "compare")
13305 (set_attr "length" "12,16")])
13308 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13310 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13311 (match_operand:SI 2 "reg_or_short_operand" ""))
13312 (match_operand:SI 3 "gpc_reg_operand" ""))
13314 (set (match_operand:SI 0 "gpc_reg_operand" "")
13315 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13316 "TARGET_POWER && reload_completed"
13317 [(set (match_dup 0)
13318 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13320 (compare:CC (match_dup 0)
13325 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13326 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13327 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13329 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
13330 [(set_attr "length" "12")])
13332 (define_insn "*geu<mode>"
13333 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13334 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13335 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13338 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
13339 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
13340 [(set_attr "type" "three")
13341 (set_attr "length" "12")])
13343 (define_insn "*geu<mode>_compare"
13344 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13346 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13347 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13349 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13350 (geu:P (match_dup 1) (match_dup 2)))]
13353 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13354 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13357 [(set_attr "type" "compare")
13358 (set_attr "length" "12,12,16,16")])
13361 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13363 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
13364 (match_operand:P 2 "reg_or_neg_short_operand" ""))
13366 (set (match_operand:P 0 "gpc_reg_operand" "")
13367 (geu:P (match_dup 1) (match_dup 2)))]
13369 [(set (match_dup 0)
13370 (geu:P (match_dup 1) (match_dup 2)))
13372 (compare:CC (match_dup 0)
13376 (define_insn "*plus_geu<mode>"
13377 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13378 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13379 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13380 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13383 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
13384 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
13385 [(set_attr "type" "two")
13386 (set_attr "length" "8")])
13389 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13391 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13392 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13393 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13395 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13398 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
13399 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
13402 [(set_attr "type" "compare")
13403 (set_attr "length" "8,8,12,12")])
13406 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13408 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13409 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13410 (match_operand:SI 3 "gpc_reg_operand" ""))
13412 (clobber (match_scratch:SI 4 ""))]
13413 "TARGET_32BIT && reload_completed"
13414 [(set (match_dup 4)
13415 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13418 (compare:CC (match_dup 4)
13423 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13425 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13426 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13427 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13429 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13430 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13433 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
13434 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
13437 [(set_attr "type" "compare")
13438 (set_attr "length" "8,8,12,12")])
13441 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13443 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13444 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13445 (match_operand:SI 3 "gpc_reg_operand" ""))
13447 (set (match_operand:SI 0 "gpc_reg_operand" "")
13448 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13449 "TARGET_32BIT && reload_completed"
13450 [(set (match_dup 0)
13451 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13453 (compare:CC (match_dup 0)
13457 (define_insn "*neg_geu<mode>"
13458 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13459 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13460 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13463 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
13464 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
13465 [(set_attr "type" "three")
13466 (set_attr "length" "12")])
13468 (define_insn "*and_neg_geu<mode>"
13469 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13471 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13472 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13473 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13476 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
13477 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13478 [(set_attr "type" "three")
13479 (set_attr "length" "12")])
13482 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13485 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13486 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13487 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13489 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13492 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13493 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13496 [(set_attr "type" "compare")
13497 (set_attr "length" "12,12,16,16")])
13500 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13503 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13504 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13505 (match_operand:SI 3 "gpc_reg_operand" ""))
13507 (clobber (match_scratch:SI 4 ""))]
13508 "TARGET_32BIT && reload_completed"
13509 [(set (match_dup 4)
13510 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13513 (compare:CC (match_dup 4)
13518 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13521 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13522 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13523 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13525 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13526 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13529 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13530 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13533 [(set_attr "type" "compare")
13534 (set_attr "length" "12,12,16,16")])
13537 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13540 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13541 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13542 (match_operand:SI 3 "gpc_reg_operand" ""))
13544 (set (match_operand:SI 0 "gpc_reg_operand" "")
13545 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13546 "TARGET_32BIT && reload_completed"
13547 [(set (match_dup 0)
13548 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13550 (compare:CC (match_dup 0)
13555 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13556 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13557 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13559 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13560 [(set_attr "length" "12")])
13563 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13565 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13566 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13568 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13569 (gt:SI (match_dup 1) (match_dup 2)))]
13572 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13574 [(set_attr "type" "delayed_compare")
13575 (set_attr "length" "12,16")])
13578 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13580 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13581 (match_operand:SI 2 "reg_or_short_operand" ""))
13583 (set (match_operand:SI 0 "gpc_reg_operand" "")
13584 (gt:SI (match_dup 1) (match_dup 2)))]
13585 "TARGET_POWER && reload_completed"
13586 [(set (match_dup 0)
13587 (gt:SI (match_dup 1) (match_dup 2)))
13589 (compare:CC (match_dup 0)
13593 (define_insn "*plus_gt0<mode>"
13594 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13595 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13597 (match_operand:P 2 "gpc_reg_operand" "r")))]
13599 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13600 [(set_attr "type" "three")
13601 (set_attr "length" "12")])
13604 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13606 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13608 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13610 (clobber (match_scratch:SI 3 "=&r,&r"))]
13613 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13615 [(set_attr "type" "compare")
13616 (set_attr "length" "12,16")])
13619 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13621 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13623 (match_operand:SI 2 "gpc_reg_operand" ""))
13625 (clobber (match_scratch:SI 3 ""))]
13626 "TARGET_32BIT && reload_completed"
13627 [(set (match_dup 3)
13628 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13631 (compare:CC (match_dup 3)
13636 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13638 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13640 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13642 (clobber (match_scratch:DI 3 "=&r,&r"))]
13645 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13647 [(set_attr "type" "compare")
13648 (set_attr "length" "12,16")])
13651 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13653 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13655 (match_operand:DI 2 "gpc_reg_operand" ""))
13657 (clobber (match_scratch:DI 3 ""))]
13658 "TARGET_64BIT && reload_completed"
13659 [(set (match_dup 3)
13660 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13663 (compare:CC (match_dup 3)
13668 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13670 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13672 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13674 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13675 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13678 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13680 [(set_attr "type" "compare")
13681 (set_attr "length" "12,16")])
13684 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13686 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13688 (match_operand:SI 2 "gpc_reg_operand" ""))
13690 (set (match_operand:SI 0 "gpc_reg_operand" "")
13691 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13692 "TARGET_32BIT && reload_completed"
13693 [(set (match_dup 0)
13694 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13696 (compare:CC (match_dup 0)
13701 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13703 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13705 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13707 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13708 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13711 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13713 [(set_attr "type" "compare")
13714 (set_attr "length" "12,16")])
13717 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13719 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13721 (match_operand:DI 2 "gpc_reg_operand" ""))
13723 (set (match_operand:DI 0 "gpc_reg_operand" "")
13724 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13725 "TARGET_64BIT && reload_completed"
13726 [(set (match_dup 0)
13727 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13729 (compare:CC (match_dup 0)
13734 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13735 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13736 (match_operand:SI 2 "reg_or_short_operand" "r"))
13737 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13739 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13740 [(set_attr "length" "12")])
13743 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13745 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13746 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13747 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13749 (clobber (match_scratch:SI 4 "=&r,&r"))]
13752 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13754 [(set_attr "type" "compare")
13755 (set_attr "length" "12,16")])
13758 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13760 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13761 (match_operand:SI 2 "reg_or_short_operand" ""))
13762 (match_operand:SI 3 "gpc_reg_operand" ""))
13764 (clobber (match_scratch:SI 4 ""))]
13765 "TARGET_POWER && reload_completed"
13766 [(set (match_dup 4)
13767 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13769 (compare:CC (match_dup 4)
13774 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13776 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13777 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13778 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13780 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13781 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13784 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13786 [(set_attr "type" "compare")
13787 (set_attr "length" "12,16")])
13790 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13792 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13793 (match_operand:SI 2 "reg_or_short_operand" ""))
13794 (match_operand:SI 3 "gpc_reg_operand" ""))
13796 (set (match_operand:SI 0 "gpc_reg_operand" "")
13797 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13798 "TARGET_POWER && reload_completed"
13799 [(set (match_dup 0)
13800 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13802 (compare:CC (match_dup 0)
13807 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13808 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13809 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13811 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13812 [(set_attr "length" "12")])
13814 (define_insn_and_split "*gtu<mode>"
13815 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13816 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13817 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13821 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13822 (set (match_dup 0) (neg:P (match_dup 0)))]
13825 (define_insn_and_split "*gtu<mode>_compare"
13826 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13828 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13829 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13831 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13832 (gtu:P (match_dup 1) (match_dup 2)))]
13836 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13837 (parallel [(set (match_dup 3)
13838 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13839 (set (match_dup 0) (neg:P (match_dup 0)))])]
13842 (define_insn_and_split "*plus_gtu<mode>"
13843 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13844 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13845 (match_operand:P 2 "reg_or_short_operand" "rI"))
13846 (match_operand:P 3 "reg_or_short_operand" "rI")))]
13849 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13850 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13851 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13854 (define_insn_and_split "*plus_gtu<mode>_compare"
13855 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13857 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13858 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13859 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13861 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13862 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13865 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13866 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13867 (parallel [(set (match_dup 4)
13868 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13870 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13873 (define_insn "*neg_gtu<mode>"
13874 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13875 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13876 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13878 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13879 [(set_attr "type" "two")
13880 (set_attr "length" "8")])
13883 ;; Define both directions of branch and return. If we need a reload
13884 ;; register, we'd rather use CR0 since it is much easier to copy a
13885 ;; register CC value to there.
13889 (if_then_else (match_operator 1 "branch_comparison_operator"
13891 "cc_reg_operand" "y")
13893 (label_ref (match_operand 0 "" ""))
13898 return output_cbranch (operands[1], \"%l0\", 0, insn);
13900 [(set_attr "type" "branch")])
13904 (if_then_else (match_operator 0 "branch_comparison_operator"
13906 "cc_reg_operand" "y")
13913 return output_cbranch (operands[0], NULL, 0, insn);
13915 [(set_attr "type" "jmpreg")
13916 (set_attr "length" "4")])
13920 (if_then_else (match_operator 1 "branch_comparison_operator"
13922 "cc_reg_operand" "y")
13925 (label_ref (match_operand 0 "" ""))))]
13929 return output_cbranch (operands[1], \"%l0\", 1, insn);
13931 [(set_attr "type" "branch")])
13935 (if_then_else (match_operator 0 "branch_comparison_operator"
13937 "cc_reg_operand" "y")
13944 return output_cbranch (operands[0], NULL, 1, insn);
13946 [(set_attr "type" "jmpreg")
13947 (set_attr "length" "4")])
13949 ;; Logic on condition register values.
13951 ; This pattern matches things like
13952 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13953 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13955 ; which are generated by the branch logic.
13956 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13958 (define_insn "*cceq_ior_compare"
13959 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13960 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13961 [(match_operator:SI 2
13962 "branch_positive_comparison_operator"
13964 "cc_reg_operand" "y,y")
13966 (match_operator:SI 4
13967 "branch_positive_comparison_operator"
13969 "cc_reg_operand" "0,y")
13973 "cr%q1 %E0,%j2,%j4"
13974 [(set_attr "type" "cr_logical,delayed_cr")])
13976 ; Why is the constant -1 here, but 1 in the previous pattern?
13977 ; Because ~1 has all but the low bit set.
13979 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13980 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13981 [(not:SI (match_operator:SI 2
13982 "branch_positive_comparison_operator"
13984 "cc_reg_operand" "y,y")
13986 (match_operator:SI 4
13987 "branch_positive_comparison_operator"
13989 "cc_reg_operand" "0,y")
13993 "cr%q1 %E0,%j2,%j4"
13994 [(set_attr "type" "cr_logical,delayed_cr")])
13996 (define_insn "*cceq_rev_compare"
13997 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13998 (compare:CCEQ (match_operator:SI 1
13999 "branch_positive_comparison_operator"
14001 "cc_reg_operand" "0,y")
14005 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
14006 [(set_attr "type" "cr_logical,delayed_cr")])
14008 ;; If we are comparing the result of two comparisons, this can be done
14009 ;; using creqv or crxor.
14011 (define_insn_and_split ""
14012 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14013 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
14014 [(match_operand 2 "cc_reg_operand" "y")
14016 (match_operator 3 "branch_comparison_operator"
14017 [(match_operand 4 "cc_reg_operand" "y")
14022 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14026 int positive_1, positive_2;
14028 positive_1 = branch_positive_comparison_operator (operands[1],
14029 GET_MODE (operands[1]));
14030 positive_2 = branch_positive_comparison_operator (operands[3],
14031 GET_MODE (operands[3]));
14034 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
14035 GET_CODE (operands[1])),
14037 operands[2], const0_rtx);
14038 else if (GET_MODE (operands[1]) != SImode)
14039 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14040 operands[2], const0_rtx);
14043 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
14044 GET_CODE (operands[3])),
14046 operands[4], const0_rtx);
14047 else if (GET_MODE (operands[3]) != SImode)
14048 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14049 operands[4], const0_rtx);
14051 if (positive_1 == positive_2)
14053 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14054 operands[5] = constm1_rtx;
14058 operands[5] = const1_rtx;
14062 ;; Unconditional branch and return.
14064 (define_insn "jump"
14066 (label_ref (match_operand 0 "" "")))]
14069 [(set_attr "type" "branch")])
14071 (define_insn "return"
14075 [(set_attr "type" "jmpreg")])
14077 (define_expand "indirect_jump"
14078 [(set (pc) (match_operand 0 "register_operand" ""))])
14080 (define_insn "*indirect_jump<mode>"
14081 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14086 [(set_attr "type" "jmpreg")])
14088 ;; Table jump for switch statements:
14089 (define_expand "tablejump"
14090 [(use (match_operand 0 "" ""))
14091 (use (label_ref (match_operand 1 "" "")))]
14096 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14098 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14102 (define_expand "tablejumpsi"
14103 [(set (match_dup 3)
14104 (plus:SI (match_operand:SI 0 "" "")
14106 (parallel [(set (pc) (match_dup 3))
14107 (use (label_ref (match_operand 1 "" "")))])]
14110 { operands[0] = force_reg (SImode, operands[0]);
14111 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
14112 operands[3] = gen_reg_rtx (SImode);
14115 (define_expand "tablejumpdi"
14116 [(set (match_dup 4)
14117 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
14119 (plus:DI (match_dup 4)
14121 (parallel [(set (pc) (match_dup 3))
14122 (use (label_ref (match_operand 1 "" "")))])]
14125 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
14126 operands[3] = gen_reg_rtx (DImode);
14127 operands[4] = gen_reg_rtx (DImode);
14130 (define_insn "*tablejump<mode>_internal1"
14132 (match_operand:P 0 "register_operand" "c,*l"))
14133 (use (label_ref (match_operand 1 "" "")))]
14138 [(set_attr "type" "jmpreg")])
14143 "{cror 0,0,0|nop}")
14145 ;; Define the subtract-one-and-jump insns, starting with the template
14146 ;; so loop.c knows what to generate.
14148 (define_expand "doloop_end"
14149 [(use (match_operand 0 "" "")) ; loop pseudo
14150 (use (match_operand 1 "" "")) ; iterations; zero if unknown
14151 (use (match_operand 2 "" "")) ; max iterations
14152 (use (match_operand 3 "" "")) ; loop level
14153 (use (match_operand 4 "" ""))] ; label
14157 /* Only use this on innermost loops. */
14158 if (INTVAL (operands[3]) > 1)
14162 if (GET_MODE (operands[0]) != DImode)
14164 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
14168 if (GET_MODE (operands[0]) != SImode)
14170 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
14175 (define_expand "ctr<mode>"
14176 [(parallel [(set (pc)
14177 (if_then_else (ne (match_operand:P 0 "register_operand" "")
14179 (label_ref (match_operand 1 "" ""))
14182 (plus:P (match_dup 0)
14184 (clobber (match_scratch:CC 2 ""))
14185 (clobber (match_scratch:P 3 ""))])]
14189 ;; We need to be able to do this for any operand, including MEM, or we
14190 ;; will cause reload to blow up since we don't allow output reloads on
14192 ;; For the length attribute to be calculated correctly, the
14193 ;; label MUST be operand 0.
14195 (define_insn "*ctr<mode>_internal1"
14197 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14199 (label_ref (match_operand 0 "" ""))
14201 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14202 (plus:P (match_dup 1)
14204 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14205 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14209 if (which_alternative != 0)
14211 else if (get_attr_length (insn) == 4)
14212 return \"{bdn|bdnz} %l0\";
14214 return \"bdz $+8\;b %l0\";
14216 [(set_attr "type" "branch")
14217 (set_attr "length" "*,12,16,16")])
14219 (define_insn "*ctr<mode>_internal2"
14221 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14224 (label_ref (match_operand 0 "" ""))))
14225 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14226 (plus:P (match_dup 1)
14228 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14229 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14233 if (which_alternative != 0)
14235 else if (get_attr_length (insn) == 4)
14236 return \"bdz %l0\";
14238 return \"{bdn|bdnz} $+8\;b %l0\";
14240 [(set_attr "type" "branch")
14241 (set_attr "length" "*,12,16,16")])
14243 ;; Similar but use EQ
14245 (define_insn "*ctr<mode>_internal5"
14247 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14249 (label_ref (match_operand 0 "" ""))
14251 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14252 (plus:P (match_dup 1)
14254 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14255 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14259 if (which_alternative != 0)
14261 else if (get_attr_length (insn) == 4)
14262 return \"bdz %l0\";
14264 return \"{bdn|bdnz} $+8\;b %l0\";
14266 [(set_attr "type" "branch")
14267 (set_attr "length" "*,12,16,16")])
14269 (define_insn "*ctr<mode>_internal6"
14271 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14274 (label_ref (match_operand 0 "" ""))))
14275 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14276 (plus:P (match_dup 1)
14278 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14279 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14283 if (which_alternative != 0)
14285 else if (get_attr_length (insn) == 4)
14286 return \"{bdn|bdnz} %l0\";
14288 return \"bdz $+8\;b %l0\";
14290 [(set_attr "type" "branch")
14291 (set_attr "length" "*,12,16,16")])
14293 ;; Now the splitters if we could not allocate the CTR register
14297 (if_then_else (match_operator 2 "comparison_operator"
14298 [(match_operand:P 1 "gpc_reg_operand" "")
14300 (match_operand 5 "" "")
14301 (match_operand 6 "" "")))
14302 (set (match_operand:P 0 "gpc_reg_operand" "")
14303 (plus:P (match_dup 1) (const_int -1)))
14304 (clobber (match_scratch:CC 3 ""))
14305 (clobber (match_scratch:P 4 ""))]
14307 [(parallel [(set (match_dup 3)
14308 (compare:CC (plus:P (match_dup 1)
14312 (plus:P (match_dup 1)
14314 (set (pc) (if_then_else (match_dup 7)
14318 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14319 operands[3], const0_rtx); }")
14323 (if_then_else (match_operator 2 "comparison_operator"
14324 [(match_operand:P 1 "gpc_reg_operand" "")
14326 (match_operand 5 "" "")
14327 (match_operand 6 "" "")))
14328 (set (match_operand:P 0 "nonimmediate_operand" "")
14329 (plus:P (match_dup 1) (const_int -1)))
14330 (clobber (match_scratch:CC 3 ""))
14331 (clobber (match_scratch:P 4 ""))]
14332 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
14333 [(parallel [(set (match_dup 3)
14334 (compare:CC (plus:P (match_dup 1)
14338 (plus:P (match_dup 1)
14342 (set (pc) (if_then_else (match_dup 7)
14346 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14347 operands[3], const0_rtx); }")
14349 (define_insn "trap"
14350 [(trap_if (const_int 1) (const_int 0))]
14353 [(set_attr "type" "trap")])
14355 (define_expand "conditional_trap"
14356 [(trap_if (match_operator 0 "trap_comparison_operator"
14357 [(match_dup 2) (match_dup 3)])
14358 (match_operand 1 "const_int_operand" ""))]
14360 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14361 operands[2] = rs6000_compare_op0;
14362 operands[3] = rs6000_compare_op1;")
14365 [(trap_if (match_operator 0 "trap_comparison_operator"
14366 [(match_operand:GPR 1 "register_operand" "r")
14367 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
14370 "{t|t<wd>}%V0%I2 %1,%2"
14371 [(set_attr "type" "trap")])
14373 ;; Insns related to generating the function prologue and epilogue.
14375 (define_expand "prologue"
14376 [(use (const_int 0))]
14377 "TARGET_SCHED_PROLOG"
14380 rs6000_emit_prologue ();
14384 (define_insn "*movesi_from_cr_one"
14385 [(match_parallel 0 "mfcr_operation"
14386 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14387 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14388 (match_operand 3 "immediate_operand" "n")]
14389 UNSPEC_MOVESI_FROM_CR))])]
14395 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14397 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14398 operands[4] = GEN_INT (mask);
14399 output_asm_insn (\"mfcr %1,%4\", operands);
14403 [(set_attr "type" "mfcrf")])
14405 (define_insn "movesi_from_cr"
14406 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14407 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
14408 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
14409 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
14410 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
14411 UNSPEC_MOVESI_FROM_CR))]
14414 [(set_attr "type" "mfcr")])
14416 (define_insn "*stmw"
14417 [(match_parallel 0 "stmw_operation"
14418 [(set (match_operand:SI 1 "memory_operand" "=m")
14419 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14422 [(set_attr "type" "store_ux")])
14424 (define_insn "*save_fpregs_<mode>"
14425 [(match_parallel 0 "any_parallel_operand"
14426 [(clobber (reg:P 65))
14427 (use (match_operand:P 1 "call_operand" "s"))
14428 (set (match_operand:DF 2 "memory_operand" "=m")
14429 (match_operand:DF 3 "gpc_reg_operand" "f"))])]
14432 [(set_attr "type" "branch")
14433 (set_attr "length" "4")])
14435 ; These are to explain that changes to the stack pointer should
14436 ; not be moved over stores to stack memory.
14437 (define_insn "stack_tie"
14438 [(set (match_operand:BLK 0 "memory_operand" "+m")
14439 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
14442 [(set_attr "length" "0")])
14445 (define_expand "epilogue"
14446 [(use (const_int 0))]
14447 "TARGET_SCHED_PROLOG"
14450 rs6000_emit_epilogue (FALSE);
14454 ; On some processors, doing the mtcrf one CC register at a time is
14455 ; faster (like on the 604e). On others, doing them all at once is
14456 ; faster; for instance, on the 601 and 750.
14458 (define_expand "movsi_to_cr_one"
14459 [(set (match_operand:CC 0 "cc_reg_operand" "")
14460 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
14461 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14463 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14465 (define_insn "*movsi_to_cr"
14466 [(match_parallel 0 "mtcrf_operation"
14467 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14468 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14469 (match_operand 3 "immediate_operand" "n")]
14470 UNSPEC_MOVESI_TO_CR))])]
14476 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14477 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14478 operands[4] = GEN_INT (mask);
14479 return \"mtcrf %4,%2\";
14481 [(set_attr "type" "mtcr")])
14483 (define_insn "*mtcrfsi"
14484 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14485 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14486 (match_operand 2 "immediate_operand" "n")]
14487 UNSPEC_MOVESI_TO_CR))]
14488 "GET_CODE (operands[0]) == REG
14489 && CR_REGNO_P (REGNO (operands[0]))
14490 && GET_CODE (operands[2]) == CONST_INT
14491 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14493 [(set_attr "type" "mtcr")])
14495 ; The load-multiple instructions have similar properties.
14496 ; Note that "load_multiple" is a name known to the machine-independent
14497 ; code that actually corresponds to the PowerPC load-string.
14499 (define_insn "*lmw"
14500 [(match_parallel 0 "lmw_operation"
14501 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14502 (match_operand:SI 2 "memory_operand" "m"))])]
14505 [(set_attr "type" "load_ux")])
14507 (define_insn "*return_internal_<mode>"
14509 (use (match_operand:P 0 "register_operand" "lc"))]
14512 [(set_attr "type" "jmpreg")])
14514 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14515 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14517 (define_insn "*return_and_restore_fpregs_<mode>"
14518 [(match_parallel 0 "any_parallel_operand"
14521 (use (match_operand:P 1 "call_operand" "s"))
14522 (set (match_operand:DF 2 "gpc_reg_operand" "=f")
14523 (match_operand:DF 3 "memory_operand" "m"))])]
14527 ; This is used in compiling the unwind routines.
14528 (define_expand "eh_return"
14529 [(use (match_operand 0 "general_operand" ""))]
14534 emit_insn (gen_eh_set_lr_si (operands[0]));
14536 emit_insn (gen_eh_set_lr_di (operands[0]));
14540 ; We can't expand this before we know where the link register is stored.
14541 (define_insn "eh_set_lr_<mode>"
14542 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
14544 (clobber (match_scratch:P 1 "=&b"))]
14549 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14550 (clobber (match_scratch 1 ""))]
14555 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14559 (define_insn "prefetch"
14560 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
14561 (match_operand:SI 1 "const_int_operand" "n")
14562 (match_operand:SI 2 "const_int_operand" "n"))]
14566 if (GET_CODE (operands[0]) == REG)
14567 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14568 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14570 [(set_attr "type" "load")])
14573 (include "sync.md")
14574 (include "altivec.md")
14577 (include "paired.md")