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invoke.texi: Add cpu_type power6x (RS/6000 and PowerPC Options): Add -mmfpgpr.
[thirdparty/gcc.git] / gcc / config / rs6000 / rs6000.md
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6
7 ;; This file is part of GCC.
8
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 2, or (at your
12 ;; option) any later version.
13
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
18
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the
21 ;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
22 ;; MA 02110-1301, USA.
23
24 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25
26 ;;
27 ;; UNSPEC usage
28 ;;
29
30 (define_constants
31 [(UNSPEC_FRSP 0) ; frsp for POWER machines
32 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
33 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
34 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
35 (UNSPEC_MOVSI_GOT 8)
36 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
37 (UNSPEC_FCTIWZ 10)
38 (UNSPEC_FRIM 11)
39 (UNSPEC_FRIN 12)
40 (UNSPEC_FRIP 13)
41 (UNSPEC_FRIZ 14)
42 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
43 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
44 (UNSPEC_TLSGD 17)
45 (UNSPEC_TLSLD 18)
46 (UNSPEC_MOVESI_FROM_CR 19)
47 (UNSPEC_MOVESI_TO_CR 20)
48 (UNSPEC_TLSDTPREL 21)
49 (UNSPEC_TLSDTPRELHA 22)
50 (UNSPEC_TLSDTPRELLO 23)
51 (UNSPEC_TLSGOTDTPREL 24)
52 (UNSPEC_TLSTPREL 25)
53 (UNSPEC_TLSTPRELHA 26)
54 (UNSPEC_TLSTPRELLO 27)
55 (UNSPEC_TLSGOTTPREL 28)
56 (UNSPEC_TLSTLS 29)
57 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
58 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
59 (UNSPEC_STFIWX 32)
60 (UNSPEC_POPCNTB 33)
61 (UNSPEC_FRES 34)
62 (UNSPEC_SP_SET 35)
63 (UNSPEC_SP_TEST 36)
64 (UNSPEC_SYNC 37)
65 (UNSPEC_LWSYNC 38)
66 (UNSPEC_ISYNC 39)
67 (UNSPEC_SYNC_OP 40)
68 (UNSPEC_ATOMIC 41)
69 (UNSPEC_CMPXCHG 42)
70 (UNSPEC_XCHG 43)
71 (UNSPEC_AND 44)
72 (UNSPEC_DLMZB 45)
73 (UNSPEC_DLMZB_CR 46)
74 (UNSPEC_DLMZB_STRLEN 47)
75 ])
76
77 ;;
78 ;; UNSPEC_VOLATILE usage
79 ;;
80
81 (define_constants
82 [(UNSPECV_BLOCK 0)
83 (UNSPECV_LL 1) ; load-locked
84 (UNSPECV_SC 2) ; store-conditional
85 (UNSPECV_EH_RR 9) ; eh_reg_restore
86 ])
87 \f
88 ;; Define an insn type attribute. This is used in function unit delay
89 ;; computations.
90 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr"
91 (const_string "integer"))
92
93 ;; Length (in bytes).
94 ; '(pc)' in the following doesn't include the instruction itself; it is
95 ; calculated as if the instruction had zero size.
96 (define_attr "length" ""
97 (if_then_else (eq_attr "type" "branch")
98 (if_then_else (and (ge (minus (match_dup 0) (pc))
99 (const_int -32768))
100 (lt (minus (match_dup 0) (pc))
101 (const_int 32764)))
102 (const_int 4)
103 (const_int 8))
104 (const_int 4)))
105
106 ;; Processor type -- this attribute must exactly match the processor_type
107 ;; enumeration in rs6000.h.
108
109 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5,power6"
110 (const (symbol_ref "rs6000_cpu_attr")))
111
112 (automata_option "ndfa")
113
114 (include "rios1.md")
115 (include "rios2.md")
116 (include "rs64.md")
117 (include "mpc.md")
118 (include "40x.md")
119 (include "440.md")
120 (include "603.md")
121 (include "6xx.md")
122 (include "7xx.md")
123 (include "7450.md")
124 (include "8540.md")
125 (include "power4.md")
126 (include "power5.md")
127 (include "power6.md")
128
129 (include "predicates.md")
130 (include "constraints.md")
131
132 (include "darwin.md")
133
134 \f
135 ;; Mode macros
136
137 ; This mode macro allows :GPR to be used to indicate the allowable size
138 ; of whole values in GPRs.
139 (define_mode_macro GPR [SI (DI "TARGET_POWERPC64")])
140
141 ; Any supported integer mode.
142 (define_mode_macro INT [QI HI SI DI TI])
143
144 ; Any supported integer mode that fits in one register.
145 (define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")])
146
147 ; extend modes for DImode
148 (define_mode_macro QHSI [QI HI SI])
149
150 ; SImode or DImode, even if DImode doesn't fit in GPRs.
151 (define_mode_macro SDI [SI DI])
152
153 ; The size of a pointer. Also, the size of the value that a record-condition
154 ; (one with a '.') will compare.
155 (define_mode_macro P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
156
157 ; Any hardware-supported floating-point mode
158 (define_mode_macro FP [(SF "TARGET_HARD_FLOAT")
159 (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
160 (TF "!TARGET_IEEEQUAD
161 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128")])
162
163 ; Various instructions that come in SI and DI forms.
164 ; A generic w/d attribute, for things like cmpw/cmpd.
165 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
166
167 ; DImode bits
168 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
169
170 \f
171 ;; Start with fixed-point load and store insns. Here we put only the more
172 ;; complex forms. Basic data transfer is done later.
173
174 (define_expand "zero_extend<mode>di2"
175 [(set (match_operand:DI 0 "gpc_reg_operand" "")
176 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
177 "TARGET_POWERPC64"
178 "")
179
180 (define_insn "*zero_extend<mode>di2_internal1"
181 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
182 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
183 "TARGET_POWERPC64"
184 "@
185 l<wd>z%U1%X1 %0,%1
186 rldicl %0,%1,0,<dbits>"
187 [(set_attr "type" "load,*")])
188
189 (define_insn "*zero_extend<mode>di2_internal2"
190 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
191 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
192 (const_int 0)))
193 (clobber (match_scratch:DI 2 "=r,r"))]
194 "TARGET_64BIT"
195 "@
196 rldicl. %2,%1,0,<dbits>
197 #"
198 [(set_attr "type" "compare")
199 (set_attr "length" "4,8")])
200
201 (define_split
202 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
203 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
204 (const_int 0)))
205 (clobber (match_scratch:DI 2 ""))]
206 "TARGET_POWERPC64 && reload_completed"
207 [(set (match_dup 2)
208 (zero_extend:DI (match_dup 1)))
209 (set (match_dup 0)
210 (compare:CC (match_dup 2)
211 (const_int 0)))]
212 "")
213
214 (define_insn "*zero_extend<mode>di2_internal3"
215 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
216 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
217 (const_int 0)))
218 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
219 (zero_extend:DI (match_dup 1)))]
220 "TARGET_64BIT"
221 "@
222 rldicl. %0,%1,0,<dbits>
223 #"
224 [(set_attr "type" "compare")
225 (set_attr "length" "4,8")])
226
227 (define_split
228 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
229 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
230 (const_int 0)))
231 (set (match_operand:DI 0 "gpc_reg_operand" "")
232 (zero_extend:DI (match_dup 1)))]
233 "TARGET_POWERPC64 && reload_completed"
234 [(set (match_dup 0)
235 (zero_extend:DI (match_dup 1)))
236 (set (match_dup 2)
237 (compare:CC (match_dup 0)
238 (const_int 0)))]
239 "")
240
241 (define_insn "extendqidi2"
242 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
243 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
244 "TARGET_POWERPC64"
245 "extsb %0,%1"
246 [(set_attr "type" "exts")])
247
248 (define_insn ""
249 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
250 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
251 (const_int 0)))
252 (clobber (match_scratch:DI 2 "=r,r"))]
253 "TARGET_64BIT"
254 "@
255 extsb. %2,%1
256 #"
257 [(set_attr "type" "compare")
258 (set_attr "length" "4,8")])
259
260 (define_split
261 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
262 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
263 (const_int 0)))
264 (clobber (match_scratch:DI 2 ""))]
265 "TARGET_POWERPC64 && reload_completed"
266 [(set (match_dup 2)
267 (sign_extend:DI (match_dup 1)))
268 (set (match_dup 0)
269 (compare:CC (match_dup 2)
270 (const_int 0)))]
271 "")
272
273 (define_insn ""
274 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
275 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
276 (const_int 0)))
277 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
278 (sign_extend:DI (match_dup 1)))]
279 "TARGET_64BIT"
280 "@
281 extsb. %0,%1
282 #"
283 [(set_attr "type" "compare")
284 (set_attr "length" "4,8")])
285
286 (define_split
287 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
288 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
289 (const_int 0)))
290 (set (match_operand:DI 0 "gpc_reg_operand" "")
291 (sign_extend:DI (match_dup 1)))]
292 "TARGET_POWERPC64 && reload_completed"
293 [(set (match_dup 0)
294 (sign_extend:DI (match_dup 1)))
295 (set (match_dup 2)
296 (compare:CC (match_dup 0)
297 (const_int 0)))]
298 "")
299
300 (define_expand "extendhidi2"
301 [(set (match_operand:DI 0 "gpc_reg_operand" "")
302 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
303 "TARGET_POWERPC64"
304 "")
305
306 (define_insn ""
307 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
308 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
309 "TARGET_POWERPC64"
310 "@
311 lha%U1%X1 %0,%1
312 extsh %0,%1"
313 [(set_attr "type" "load_ext,exts")])
314
315 (define_insn ""
316 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
317 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
318 (const_int 0)))
319 (clobber (match_scratch:DI 2 "=r,r"))]
320 "TARGET_64BIT"
321 "@
322 extsh. %2,%1
323 #"
324 [(set_attr "type" "compare")
325 (set_attr "length" "4,8")])
326
327 (define_split
328 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
329 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
330 (const_int 0)))
331 (clobber (match_scratch:DI 2 ""))]
332 "TARGET_POWERPC64 && reload_completed"
333 [(set (match_dup 2)
334 (sign_extend:DI (match_dup 1)))
335 (set (match_dup 0)
336 (compare:CC (match_dup 2)
337 (const_int 0)))]
338 "")
339
340 (define_insn ""
341 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
342 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
343 (const_int 0)))
344 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
345 (sign_extend:DI (match_dup 1)))]
346 "TARGET_64BIT"
347 "@
348 extsh. %0,%1
349 #"
350 [(set_attr "type" "compare")
351 (set_attr "length" "4,8")])
352
353 (define_split
354 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
355 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
356 (const_int 0)))
357 (set (match_operand:DI 0 "gpc_reg_operand" "")
358 (sign_extend:DI (match_dup 1)))]
359 "TARGET_POWERPC64 && reload_completed"
360 [(set (match_dup 0)
361 (sign_extend:DI (match_dup 1)))
362 (set (match_dup 2)
363 (compare:CC (match_dup 0)
364 (const_int 0)))]
365 "")
366
367 (define_expand "extendsidi2"
368 [(set (match_operand:DI 0 "gpc_reg_operand" "")
369 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
370 "TARGET_POWERPC64"
371 "")
372
373 (define_insn ""
374 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
375 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
376 "TARGET_POWERPC64"
377 "@
378 lwa%U1%X1 %0,%1
379 extsw %0,%1"
380 [(set_attr "type" "load_ext,exts")])
381
382 (define_insn ""
383 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
384 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
385 (const_int 0)))
386 (clobber (match_scratch:DI 2 "=r,r"))]
387 "TARGET_64BIT"
388 "@
389 extsw. %2,%1
390 #"
391 [(set_attr "type" "compare")
392 (set_attr "length" "4,8")])
393
394 (define_split
395 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
396 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
397 (const_int 0)))
398 (clobber (match_scratch:DI 2 ""))]
399 "TARGET_POWERPC64 && reload_completed"
400 [(set (match_dup 2)
401 (sign_extend:DI (match_dup 1)))
402 (set (match_dup 0)
403 (compare:CC (match_dup 2)
404 (const_int 0)))]
405 "")
406
407 (define_insn ""
408 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
409 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
410 (const_int 0)))
411 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
412 (sign_extend:DI (match_dup 1)))]
413 "TARGET_64BIT"
414 "@
415 extsw. %0,%1
416 #"
417 [(set_attr "type" "compare")
418 (set_attr "length" "4,8")])
419
420 (define_split
421 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
422 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
423 (const_int 0)))
424 (set (match_operand:DI 0 "gpc_reg_operand" "")
425 (sign_extend:DI (match_dup 1)))]
426 "TARGET_POWERPC64 && reload_completed"
427 [(set (match_dup 0)
428 (sign_extend:DI (match_dup 1)))
429 (set (match_dup 2)
430 (compare:CC (match_dup 0)
431 (const_int 0)))]
432 "")
433
434 (define_expand "zero_extendqisi2"
435 [(set (match_operand:SI 0 "gpc_reg_operand" "")
436 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
437 ""
438 "")
439
440 (define_insn ""
441 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
442 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
443 ""
444 "@
445 lbz%U1%X1 %0,%1
446 {rlinm|rlwinm} %0,%1,0,0xff"
447 [(set_attr "type" "load,*")])
448
449 (define_insn ""
450 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
451 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
452 (const_int 0)))
453 (clobber (match_scratch:SI 2 "=r,r"))]
454 ""
455 "@
456 {andil.|andi.} %2,%1,0xff
457 #"
458 [(set_attr "type" "compare")
459 (set_attr "length" "4,8")])
460
461 (define_split
462 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
463 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
464 (const_int 0)))
465 (clobber (match_scratch:SI 2 ""))]
466 "reload_completed"
467 [(set (match_dup 2)
468 (zero_extend:SI (match_dup 1)))
469 (set (match_dup 0)
470 (compare:CC (match_dup 2)
471 (const_int 0)))]
472 "")
473
474 (define_insn ""
475 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
476 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
477 (const_int 0)))
478 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
479 (zero_extend:SI (match_dup 1)))]
480 ""
481 "@
482 {andil.|andi.} %0,%1,0xff
483 #"
484 [(set_attr "type" "compare")
485 (set_attr "length" "4,8")])
486
487 (define_split
488 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
489 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
490 (const_int 0)))
491 (set (match_operand:SI 0 "gpc_reg_operand" "")
492 (zero_extend:SI (match_dup 1)))]
493 "reload_completed"
494 [(set (match_dup 0)
495 (zero_extend:SI (match_dup 1)))
496 (set (match_dup 2)
497 (compare:CC (match_dup 0)
498 (const_int 0)))]
499 "")
500
501 (define_expand "extendqisi2"
502 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
503 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
504 ""
505 "
506 {
507 if (TARGET_POWERPC)
508 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
509 else if (TARGET_POWER)
510 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
511 else
512 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
513 DONE;
514 }")
515
516 (define_insn "extendqisi2_ppc"
517 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
518 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
519 "TARGET_POWERPC"
520 "extsb %0,%1"
521 [(set_attr "type" "exts")])
522
523 (define_insn ""
524 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
525 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
526 (const_int 0)))
527 (clobber (match_scratch:SI 2 "=r,r"))]
528 "TARGET_POWERPC"
529 "@
530 extsb. %2,%1
531 #"
532 [(set_attr "type" "compare")
533 (set_attr "length" "4,8")])
534
535 (define_split
536 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
537 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
538 (const_int 0)))
539 (clobber (match_scratch:SI 2 ""))]
540 "TARGET_POWERPC && reload_completed"
541 [(set (match_dup 2)
542 (sign_extend:SI (match_dup 1)))
543 (set (match_dup 0)
544 (compare:CC (match_dup 2)
545 (const_int 0)))]
546 "")
547
548 (define_insn ""
549 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
550 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
551 (const_int 0)))
552 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
553 (sign_extend:SI (match_dup 1)))]
554 "TARGET_POWERPC"
555 "@
556 extsb. %0,%1
557 #"
558 [(set_attr "type" "compare")
559 (set_attr "length" "4,8")])
560
561 (define_split
562 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
563 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
564 (const_int 0)))
565 (set (match_operand:SI 0 "gpc_reg_operand" "")
566 (sign_extend:SI (match_dup 1)))]
567 "TARGET_POWERPC && reload_completed"
568 [(set (match_dup 0)
569 (sign_extend:SI (match_dup 1)))
570 (set (match_dup 2)
571 (compare:CC (match_dup 0)
572 (const_int 0)))]
573 "")
574
575 (define_expand "extendqisi2_power"
576 [(parallel [(set (match_dup 2)
577 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
578 (const_int 24)))
579 (clobber (scratch:SI))])
580 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
581 (ashiftrt:SI (match_dup 2)
582 (const_int 24)))
583 (clobber (scratch:SI))])]
584 "TARGET_POWER"
585 "
586 { operands[1] = gen_lowpart (SImode, operands[1]);
587 operands[2] = gen_reg_rtx (SImode); }")
588
589 (define_expand "extendqisi2_no_power"
590 [(set (match_dup 2)
591 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
592 (const_int 24)))
593 (set (match_operand:SI 0 "gpc_reg_operand" "")
594 (ashiftrt:SI (match_dup 2)
595 (const_int 24)))]
596 "! TARGET_POWER && ! TARGET_POWERPC"
597 "
598 { operands[1] = gen_lowpart (SImode, operands[1]);
599 operands[2] = gen_reg_rtx (SImode); }")
600
601 (define_expand "zero_extendqihi2"
602 [(set (match_operand:HI 0 "gpc_reg_operand" "")
603 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
604 ""
605 "")
606
607 (define_insn ""
608 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
609 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
610 ""
611 "@
612 lbz%U1%X1 %0,%1
613 {rlinm|rlwinm} %0,%1,0,0xff"
614 [(set_attr "type" "load,*")])
615
616 (define_insn ""
617 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
618 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
619 (const_int 0)))
620 (clobber (match_scratch:HI 2 "=r,r"))]
621 ""
622 "@
623 {andil.|andi.} %2,%1,0xff
624 #"
625 [(set_attr "type" "compare")
626 (set_attr "length" "4,8")])
627
628 (define_split
629 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
630 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
631 (const_int 0)))
632 (clobber (match_scratch:HI 2 ""))]
633 "reload_completed"
634 [(set (match_dup 2)
635 (zero_extend:HI (match_dup 1)))
636 (set (match_dup 0)
637 (compare:CC (match_dup 2)
638 (const_int 0)))]
639 "")
640
641 (define_insn ""
642 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
643 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
644 (const_int 0)))
645 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
646 (zero_extend:HI (match_dup 1)))]
647 ""
648 "@
649 {andil.|andi.} %0,%1,0xff
650 #"
651 [(set_attr "type" "compare")
652 (set_attr "length" "4,8")])
653
654 (define_split
655 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
656 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
657 (const_int 0)))
658 (set (match_operand:HI 0 "gpc_reg_operand" "")
659 (zero_extend:HI (match_dup 1)))]
660 "reload_completed"
661 [(set (match_dup 0)
662 (zero_extend:HI (match_dup 1)))
663 (set (match_dup 2)
664 (compare:CC (match_dup 0)
665 (const_int 0)))]
666 "")
667
668 (define_expand "extendqihi2"
669 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
670 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
671 ""
672 "
673 {
674 if (TARGET_POWERPC)
675 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
676 else if (TARGET_POWER)
677 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
678 else
679 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
680 DONE;
681 }")
682
683 (define_insn "extendqihi2_ppc"
684 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
685 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
686 "TARGET_POWERPC"
687 "extsb %0,%1"
688 [(set_attr "type" "exts")])
689
690 (define_insn ""
691 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
692 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
693 (const_int 0)))
694 (clobber (match_scratch:HI 2 "=r,r"))]
695 "TARGET_POWERPC"
696 "@
697 extsb. %2,%1
698 #"
699 [(set_attr "type" "compare")
700 (set_attr "length" "4,8")])
701
702 (define_split
703 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
704 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
705 (const_int 0)))
706 (clobber (match_scratch:HI 2 ""))]
707 "TARGET_POWERPC && reload_completed"
708 [(set (match_dup 2)
709 (sign_extend:HI (match_dup 1)))
710 (set (match_dup 0)
711 (compare:CC (match_dup 2)
712 (const_int 0)))]
713 "")
714
715 (define_insn ""
716 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
717 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
718 (const_int 0)))
719 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
720 (sign_extend:HI (match_dup 1)))]
721 "TARGET_POWERPC"
722 "@
723 extsb. %0,%1
724 #"
725 [(set_attr "type" "compare")
726 (set_attr "length" "4,8")])
727
728 (define_split
729 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
730 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
731 (const_int 0)))
732 (set (match_operand:HI 0 "gpc_reg_operand" "")
733 (sign_extend:HI (match_dup 1)))]
734 "TARGET_POWERPC && reload_completed"
735 [(set (match_dup 0)
736 (sign_extend:HI (match_dup 1)))
737 (set (match_dup 2)
738 (compare:CC (match_dup 0)
739 (const_int 0)))]
740 "")
741
742 (define_expand "extendqihi2_power"
743 [(parallel [(set (match_dup 2)
744 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
745 (const_int 24)))
746 (clobber (scratch:SI))])
747 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
748 (ashiftrt:SI (match_dup 2)
749 (const_int 24)))
750 (clobber (scratch:SI))])]
751 "TARGET_POWER"
752 "
753 { operands[0] = gen_lowpart (SImode, operands[0]);
754 operands[1] = gen_lowpart (SImode, operands[1]);
755 operands[2] = gen_reg_rtx (SImode); }")
756
757 (define_expand "extendqihi2_no_power"
758 [(set (match_dup 2)
759 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
760 (const_int 24)))
761 (set (match_operand:HI 0 "gpc_reg_operand" "")
762 (ashiftrt:SI (match_dup 2)
763 (const_int 24)))]
764 "! TARGET_POWER && ! TARGET_POWERPC"
765 "
766 { operands[0] = gen_lowpart (SImode, operands[0]);
767 operands[1] = gen_lowpart (SImode, operands[1]);
768 operands[2] = gen_reg_rtx (SImode); }")
769
770 (define_expand "zero_extendhisi2"
771 [(set (match_operand:SI 0 "gpc_reg_operand" "")
772 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
773 ""
774 "")
775
776 (define_insn ""
777 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
778 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
779 ""
780 "@
781 lhz%U1%X1 %0,%1
782 {rlinm|rlwinm} %0,%1,0,0xffff"
783 [(set_attr "type" "load,*")])
784
785 (define_insn ""
786 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
787 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
788 (const_int 0)))
789 (clobber (match_scratch:SI 2 "=r,r"))]
790 ""
791 "@
792 {andil.|andi.} %2,%1,0xffff
793 #"
794 [(set_attr "type" "compare")
795 (set_attr "length" "4,8")])
796
797 (define_split
798 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
799 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
800 (const_int 0)))
801 (clobber (match_scratch:SI 2 ""))]
802 "reload_completed"
803 [(set (match_dup 2)
804 (zero_extend:SI (match_dup 1)))
805 (set (match_dup 0)
806 (compare:CC (match_dup 2)
807 (const_int 0)))]
808 "")
809
810 (define_insn ""
811 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
812 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
813 (const_int 0)))
814 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
815 (zero_extend:SI (match_dup 1)))]
816 ""
817 "@
818 {andil.|andi.} %0,%1,0xffff
819 #"
820 [(set_attr "type" "compare")
821 (set_attr "length" "4,8")])
822
823 (define_split
824 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
825 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
826 (const_int 0)))
827 (set (match_operand:SI 0 "gpc_reg_operand" "")
828 (zero_extend:SI (match_dup 1)))]
829 "reload_completed"
830 [(set (match_dup 0)
831 (zero_extend:SI (match_dup 1)))
832 (set (match_dup 2)
833 (compare:CC (match_dup 0)
834 (const_int 0)))]
835 "")
836
837 (define_expand "extendhisi2"
838 [(set (match_operand:SI 0 "gpc_reg_operand" "")
839 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
840 ""
841 "")
842
843 (define_insn ""
844 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
845 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
846 ""
847 "@
848 lha%U1%X1 %0,%1
849 {exts|extsh} %0,%1"
850 [(set_attr "type" "load_ext,exts")])
851
852 (define_insn ""
853 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
854 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
855 (const_int 0)))
856 (clobber (match_scratch:SI 2 "=r,r"))]
857 ""
858 "@
859 {exts.|extsh.} %2,%1
860 #"
861 [(set_attr "type" "compare")
862 (set_attr "length" "4,8")])
863
864 (define_split
865 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
866 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
867 (const_int 0)))
868 (clobber (match_scratch:SI 2 ""))]
869 "reload_completed"
870 [(set (match_dup 2)
871 (sign_extend:SI (match_dup 1)))
872 (set (match_dup 0)
873 (compare:CC (match_dup 2)
874 (const_int 0)))]
875 "")
876
877 (define_insn ""
878 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
879 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
880 (const_int 0)))
881 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
882 (sign_extend:SI (match_dup 1)))]
883 ""
884 "@
885 {exts.|extsh.} %0,%1
886 #"
887 [(set_attr "type" "compare")
888 (set_attr "length" "4,8")])
889 \f
890 ;; IBM 405 and 440 half-word multiplication operations.
891
892 (define_insn "*macchwc"
893 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
894 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
895 (match_operand:SI 2 "gpc_reg_operand" "r")
896 (const_int 16))
897 (sign_extend:SI
898 (match_operand:HI 1 "gpc_reg_operand" "r")))
899 (match_operand:SI 4 "gpc_reg_operand" "0"))
900 (const_int 0)))
901 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
902 (plus:SI (mult:SI (ashiftrt:SI
903 (match_dup 2)
904 (const_int 16))
905 (sign_extend:SI
906 (match_dup 1)))
907 (match_dup 4)))]
908 "TARGET_MULHW"
909 "macchw. %0, %1, %2"
910 [(set_attr "type" "imul3")])
911
912 (define_insn "*macchw"
913 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
914 (plus:SI (mult:SI (ashiftrt:SI
915 (match_operand:SI 2 "gpc_reg_operand" "r")
916 (const_int 16))
917 (sign_extend:SI
918 (match_operand:HI 1 "gpc_reg_operand" "r")))
919 (match_operand:SI 3 "gpc_reg_operand" "0")))]
920 "TARGET_MULHW"
921 "macchw %0, %1, %2"
922 [(set_attr "type" "imul3")])
923
924 (define_insn "*macchwuc"
925 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
926 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
927 (match_operand:SI 2 "gpc_reg_operand" "r")
928 (const_int 16))
929 (zero_extend:SI
930 (match_operand:HI 1 "gpc_reg_operand" "r")))
931 (match_operand:SI 4 "gpc_reg_operand" "0"))
932 (const_int 0)))
933 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
934 (plus:SI (mult:SI (lshiftrt:SI
935 (match_dup 2)
936 (const_int 16))
937 (zero_extend:SI
938 (match_dup 1)))
939 (match_dup 4)))]
940 "TARGET_MULHW"
941 "macchwu. %0, %1, %2"
942 [(set_attr "type" "imul3")])
943
944 (define_insn "*macchwu"
945 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
946 (plus:SI (mult:SI (lshiftrt:SI
947 (match_operand:SI 2 "gpc_reg_operand" "r")
948 (const_int 16))
949 (zero_extend:SI
950 (match_operand:HI 1 "gpc_reg_operand" "r")))
951 (match_operand:SI 3 "gpc_reg_operand" "0")))]
952 "TARGET_MULHW"
953 "macchwu %0, %1, %2"
954 [(set_attr "type" "imul3")])
955
956 (define_insn "*machhwc"
957 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
958 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
959 (match_operand:SI 1 "gpc_reg_operand" "%r")
960 (const_int 16))
961 (ashiftrt:SI
962 (match_operand:SI 2 "gpc_reg_operand" "r")
963 (const_int 16)))
964 (match_operand:SI 4 "gpc_reg_operand" "0"))
965 (const_int 0)))
966 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
967 (plus:SI (mult:SI (ashiftrt:SI
968 (match_dup 1)
969 (const_int 16))
970 (ashiftrt:SI
971 (match_dup 2)
972 (const_int 16)))
973 (match_dup 4)))]
974 "TARGET_MULHW"
975 "machhw. %0, %1, %2"
976 [(set_attr "type" "imul3")])
977
978 (define_insn "*machhw"
979 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
980 (plus:SI (mult:SI (ashiftrt:SI
981 (match_operand:SI 1 "gpc_reg_operand" "%r")
982 (const_int 16))
983 (ashiftrt:SI
984 (match_operand:SI 2 "gpc_reg_operand" "r")
985 (const_int 16)))
986 (match_operand:SI 3 "gpc_reg_operand" "0")))]
987 "TARGET_MULHW"
988 "machhw %0, %1, %2"
989 [(set_attr "type" "imul3")])
990
991 (define_insn "*machhwuc"
992 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
993 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
994 (match_operand:SI 1 "gpc_reg_operand" "%r")
995 (const_int 16))
996 (lshiftrt:SI
997 (match_operand:SI 2 "gpc_reg_operand" "r")
998 (const_int 16)))
999 (match_operand:SI 4 "gpc_reg_operand" "0"))
1000 (const_int 0)))
1001 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1002 (plus:SI (mult:SI (lshiftrt:SI
1003 (match_dup 1)
1004 (const_int 16))
1005 (lshiftrt:SI
1006 (match_dup 2)
1007 (const_int 16)))
1008 (match_dup 4)))]
1009 "TARGET_MULHW"
1010 "machhwu. %0, %1, %2"
1011 [(set_attr "type" "imul3")])
1012
1013 (define_insn "*machhwu"
1014 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1015 (plus:SI (mult:SI (lshiftrt:SI
1016 (match_operand:SI 1 "gpc_reg_operand" "%r")
1017 (const_int 16))
1018 (lshiftrt:SI
1019 (match_operand:SI 2 "gpc_reg_operand" "r")
1020 (const_int 16)))
1021 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1022 "TARGET_MULHW"
1023 "machhwu %0, %1, %2"
1024 [(set_attr "type" "imul3")])
1025
1026 (define_insn "*maclhwc"
1027 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1028 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1029 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1030 (sign_extend:SI
1031 (match_operand:HI 2 "gpc_reg_operand" "r")))
1032 (match_operand:SI 4 "gpc_reg_operand" "0"))
1033 (const_int 0)))
1034 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1035 (plus:SI (mult:SI (sign_extend:SI
1036 (match_dup 1))
1037 (sign_extend:SI
1038 (match_dup 2)))
1039 (match_dup 4)))]
1040 "TARGET_MULHW"
1041 "maclhw. %0, %1, %2"
1042 [(set_attr "type" "imul3")])
1043
1044 (define_insn "*maclhw"
1045 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1046 (plus:SI (mult:SI (sign_extend:SI
1047 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1048 (sign_extend:SI
1049 (match_operand:HI 2 "gpc_reg_operand" "r")))
1050 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1051 "TARGET_MULHW"
1052 "maclhw %0, %1, %2"
1053 [(set_attr "type" "imul3")])
1054
1055 (define_insn "*maclhwuc"
1056 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1057 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1058 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1059 (zero_extend:SI
1060 (match_operand:HI 2 "gpc_reg_operand" "r")))
1061 (match_operand:SI 4 "gpc_reg_operand" "0"))
1062 (const_int 0)))
1063 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1064 (plus:SI (mult:SI (zero_extend:SI
1065 (match_dup 1))
1066 (zero_extend:SI
1067 (match_dup 2)))
1068 (match_dup 4)))]
1069 "TARGET_MULHW"
1070 "maclhwu. %0, %1, %2"
1071 [(set_attr "type" "imul3")])
1072
1073 (define_insn "*maclhwu"
1074 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1075 (plus:SI (mult:SI (zero_extend:SI
1076 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1077 (zero_extend:SI
1078 (match_operand:HI 2 "gpc_reg_operand" "r")))
1079 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1080 "TARGET_MULHW"
1081 "maclhwu %0, %1, %2"
1082 [(set_attr "type" "imul3")])
1083
1084 (define_insn "*nmacchwc"
1085 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1086 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1087 (mult:SI (ashiftrt:SI
1088 (match_operand:SI 2 "gpc_reg_operand" "r")
1089 (const_int 16))
1090 (sign_extend:SI
1091 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1092 (const_int 0)))
1093 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1094 (minus:SI (match_dup 4)
1095 (mult:SI (ashiftrt:SI
1096 (match_dup 2)
1097 (const_int 16))
1098 (sign_extend:SI
1099 (match_dup 1)))))]
1100 "TARGET_MULHW"
1101 "nmacchw. %0, %1, %2"
1102 [(set_attr "type" "imul3")])
1103
1104 (define_insn "*nmacchw"
1105 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1106 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1107 (mult:SI (ashiftrt:SI
1108 (match_operand:SI 2 "gpc_reg_operand" "r")
1109 (const_int 16))
1110 (sign_extend:SI
1111 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1112 "TARGET_MULHW"
1113 "nmacchw %0, %1, %2"
1114 [(set_attr "type" "imul3")])
1115
1116 (define_insn "*nmachhwc"
1117 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1118 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1119 (mult:SI (ashiftrt:SI
1120 (match_operand:SI 1 "gpc_reg_operand" "%r")
1121 (const_int 16))
1122 (ashiftrt:SI
1123 (match_operand:SI 2 "gpc_reg_operand" "r")
1124 (const_int 16))))
1125 (const_int 0)))
1126 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1127 (minus:SI (match_dup 4)
1128 (mult:SI (ashiftrt:SI
1129 (match_dup 1)
1130 (const_int 16))
1131 (ashiftrt:SI
1132 (match_dup 2)
1133 (const_int 16)))))]
1134 "TARGET_MULHW"
1135 "nmachhw. %0, %1, %2"
1136 [(set_attr "type" "imul3")])
1137
1138 (define_insn "*nmachhw"
1139 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1140 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1141 (mult:SI (ashiftrt:SI
1142 (match_operand:SI 1 "gpc_reg_operand" "%r")
1143 (const_int 16))
1144 (ashiftrt:SI
1145 (match_operand:SI 2 "gpc_reg_operand" "r")
1146 (const_int 16)))))]
1147 "TARGET_MULHW"
1148 "nmachhw %0, %1, %2"
1149 [(set_attr "type" "imul3")])
1150
1151 (define_insn "*nmaclhwc"
1152 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1153 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1154 (mult:SI (sign_extend:SI
1155 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1156 (sign_extend:SI
1157 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1158 (const_int 0)))
1159 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1160 (minus:SI (match_dup 4)
1161 (mult:SI (sign_extend:SI
1162 (match_dup 1))
1163 (sign_extend:SI
1164 (match_dup 2)))))]
1165 "TARGET_MULHW"
1166 "nmaclhw. %0, %1, %2"
1167 [(set_attr "type" "imul3")])
1168
1169 (define_insn "*nmaclhw"
1170 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1171 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1172 (mult:SI (sign_extend:SI
1173 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1174 (sign_extend:SI
1175 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1176 "TARGET_MULHW"
1177 "nmaclhw %0, %1, %2"
1178 [(set_attr "type" "imul3")])
1179
1180 (define_insn "*mulchwc"
1181 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1182 (compare:CC (mult:SI (ashiftrt:SI
1183 (match_operand:SI 2 "gpc_reg_operand" "r")
1184 (const_int 16))
1185 (sign_extend:SI
1186 (match_operand:HI 1 "gpc_reg_operand" "r")))
1187 (const_int 0)))
1188 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1189 (mult:SI (ashiftrt:SI
1190 (match_dup 2)
1191 (const_int 16))
1192 (sign_extend:SI
1193 (match_dup 1))))]
1194 "TARGET_MULHW"
1195 "mulchw. %0, %1, %2"
1196 [(set_attr "type" "imul3")])
1197
1198 (define_insn "*mulchw"
1199 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1200 (mult:SI (ashiftrt:SI
1201 (match_operand:SI 2 "gpc_reg_operand" "r")
1202 (const_int 16))
1203 (sign_extend:SI
1204 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1205 "TARGET_MULHW"
1206 "mulchw %0, %1, %2"
1207 [(set_attr "type" "imul3")])
1208
1209 (define_insn "*mulchwuc"
1210 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1211 (compare:CC (mult:SI (lshiftrt:SI
1212 (match_operand:SI 2 "gpc_reg_operand" "r")
1213 (const_int 16))
1214 (zero_extend:SI
1215 (match_operand:HI 1 "gpc_reg_operand" "r")))
1216 (const_int 0)))
1217 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1218 (mult:SI (lshiftrt:SI
1219 (match_dup 2)
1220 (const_int 16))
1221 (zero_extend:SI
1222 (match_dup 1))))]
1223 "TARGET_MULHW"
1224 "mulchwu. %0, %1, %2"
1225 [(set_attr "type" "imul3")])
1226
1227 (define_insn "*mulchwu"
1228 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1229 (mult:SI (lshiftrt:SI
1230 (match_operand:SI 2 "gpc_reg_operand" "r")
1231 (const_int 16))
1232 (zero_extend:SI
1233 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1234 "TARGET_MULHW"
1235 "mulchwu %0, %1, %2"
1236 [(set_attr "type" "imul3")])
1237
1238 (define_insn "*mulhhwc"
1239 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1240 (compare:CC (mult:SI (ashiftrt:SI
1241 (match_operand:SI 1 "gpc_reg_operand" "%r")
1242 (const_int 16))
1243 (ashiftrt:SI
1244 (match_operand:SI 2 "gpc_reg_operand" "r")
1245 (const_int 16)))
1246 (const_int 0)))
1247 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1248 (mult:SI (ashiftrt:SI
1249 (match_dup 1)
1250 (const_int 16))
1251 (ashiftrt:SI
1252 (match_dup 2)
1253 (const_int 16))))]
1254 "TARGET_MULHW"
1255 "mulhhw. %0, %1, %2"
1256 [(set_attr "type" "imul3")])
1257
1258 (define_insn "*mulhhw"
1259 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1260 (mult:SI (ashiftrt:SI
1261 (match_operand:SI 1 "gpc_reg_operand" "%r")
1262 (const_int 16))
1263 (ashiftrt:SI
1264 (match_operand:SI 2 "gpc_reg_operand" "r")
1265 (const_int 16))))]
1266 "TARGET_MULHW"
1267 "mulhhw %0, %1, %2"
1268 [(set_attr "type" "imul3")])
1269
1270 (define_insn "*mulhhwuc"
1271 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1272 (compare:CC (mult:SI (lshiftrt:SI
1273 (match_operand:SI 1 "gpc_reg_operand" "%r")
1274 (const_int 16))
1275 (lshiftrt:SI
1276 (match_operand:SI 2 "gpc_reg_operand" "r")
1277 (const_int 16)))
1278 (const_int 0)))
1279 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1280 (mult:SI (lshiftrt:SI
1281 (match_dup 1)
1282 (const_int 16))
1283 (lshiftrt:SI
1284 (match_dup 2)
1285 (const_int 16))))]
1286 "TARGET_MULHW"
1287 "mulhhwu. %0, %1, %2"
1288 [(set_attr "type" "imul3")])
1289
1290 (define_insn "*mulhhwu"
1291 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1292 (mult:SI (lshiftrt:SI
1293 (match_operand:SI 1 "gpc_reg_operand" "%r")
1294 (const_int 16))
1295 (lshiftrt:SI
1296 (match_operand:SI 2 "gpc_reg_operand" "r")
1297 (const_int 16))))]
1298 "TARGET_MULHW"
1299 "mulhhwu %0, %1, %2"
1300 [(set_attr "type" "imul3")])
1301
1302 (define_insn "*mullhwc"
1303 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1304 (compare:CC (mult:SI (sign_extend:SI
1305 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1306 (sign_extend:SI
1307 (match_operand:HI 2 "gpc_reg_operand" "r")))
1308 (const_int 0)))
1309 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1310 (mult:SI (sign_extend:SI
1311 (match_dup 1))
1312 (sign_extend:SI
1313 (match_dup 2))))]
1314 "TARGET_MULHW"
1315 "mullhw. %0, %1, %2"
1316 [(set_attr "type" "imul3")])
1317
1318 (define_insn "*mullhw"
1319 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1320 (mult:SI (sign_extend:SI
1321 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1322 (sign_extend:SI
1323 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1324 "TARGET_MULHW"
1325 "mullhw %0, %1, %2"
1326 [(set_attr "type" "imul3")])
1327
1328 (define_insn "*mullhwuc"
1329 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1330 (compare:CC (mult:SI (zero_extend:SI
1331 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1332 (zero_extend:SI
1333 (match_operand:HI 2 "gpc_reg_operand" "r")))
1334 (const_int 0)))
1335 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1336 (mult:SI (zero_extend:SI
1337 (match_dup 1))
1338 (zero_extend:SI
1339 (match_dup 2))))]
1340 "TARGET_MULHW"
1341 "mullhwu. %0, %1, %2"
1342 [(set_attr "type" "imul3")])
1343
1344 (define_insn "*mullhwu"
1345 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1346 (mult:SI (zero_extend:SI
1347 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1348 (zero_extend:SI
1349 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1350 "TARGET_MULHW"
1351 "mullhwu %0, %1, %2"
1352 [(set_attr "type" "imul3")])
1353 \f
1354 ;; IBM 405 and 440 string-search dlmzb instruction support.
1355 (define_insn "dlmzb"
1356 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1357 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1358 (match_operand:SI 2 "gpc_reg_operand" "r")]
1359 UNSPEC_DLMZB_CR))
1360 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1361 (unspec:SI [(match_dup 1)
1362 (match_dup 2)]
1363 UNSPEC_DLMZB))]
1364 "TARGET_DLMZB"
1365 "dlmzb. %0, %1, %2")
1366
1367 (define_expand "strlensi"
1368 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1369 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1370 (match_operand:QI 2 "const_int_operand" "")
1371 (match_operand 3 "const_int_operand" "")]
1372 UNSPEC_DLMZB_STRLEN))
1373 (clobber (match_scratch:CC 4 "=x"))]
1374 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1375 {
1376 rtx result = operands[0];
1377 rtx src = operands[1];
1378 rtx search_char = operands[2];
1379 rtx align = operands[3];
1380 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1381 rtx loop_label, end_label, mem, cr0, cond;
1382 if (search_char != const0_rtx
1383 || GET_CODE (align) != CONST_INT
1384 || INTVAL (align) < 8)
1385 FAIL;
1386 word1 = gen_reg_rtx (SImode);
1387 word2 = gen_reg_rtx (SImode);
1388 scratch_dlmzb = gen_reg_rtx (SImode);
1389 scratch_string = gen_reg_rtx (Pmode);
1390 loop_label = gen_label_rtx ();
1391 end_label = gen_label_rtx ();
1392 addr = force_reg (Pmode, XEXP (src, 0));
1393 emit_move_insn (scratch_string, addr);
1394 emit_label (loop_label);
1395 mem = change_address (src, SImode, scratch_string);
1396 emit_move_insn (word1, mem);
1397 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1398 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1399 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1400 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1401 emit_jump_insn (gen_rtx_SET (VOIDmode,
1402 pc_rtx,
1403 gen_rtx_IF_THEN_ELSE (VOIDmode,
1404 cond,
1405 gen_rtx_LABEL_REF
1406 (VOIDmode,
1407 end_label),
1408 pc_rtx)));
1409 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1410 emit_jump_insn (gen_rtx_SET (VOIDmode,
1411 pc_rtx,
1412 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1413 emit_barrier ();
1414 emit_label (end_label);
1415 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1416 emit_insn (gen_subsi3 (result, scratch_string, addr));
1417 emit_insn (gen_subsi3 (result, result, const1_rtx));
1418 DONE;
1419 })
1420 \f
1421 (define_split
1422 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1423 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1424 (const_int 0)))
1425 (set (match_operand:SI 0 "gpc_reg_operand" "")
1426 (sign_extend:SI (match_dup 1)))]
1427 "reload_completed"
1428 [(set (match_dup 0)
1429 (sign_extend:SI (match_dup 1)))
1430 (set (match_dup 2)
1431 (compare:CC (match_dup 0)
1432 (const_int 0)))]
1433 "")
1434
1435 ;; Fixed-point arithmetic insns.
1436
1437 (define_expand "add<mode>3"
1438 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1439 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1440 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1441 ""
1442 {
1443 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1444 {
1445 if (non_short_cint_operand (operands[2], DImode))
1446 FAIL;
1447 }
1448 else if (GET_CODE (operands[2]) == CONST_INT
1449 && ! add_operand (operands[2], <MODE>mode))
1450 {
1451 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
1452 ? operands[0] : gen_reg_rtx (<MODE>mode));
1453
1454 HOST_WIDE_INT val = INTVAL (operands[2]);
1455 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1456 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1457
1458 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1459 FAIL;
1460
1461 /* The ordering here is important for the prolog expander.
1462 When space is allocated from the stack, adding 'low' first may
1463 produce a temporary deallocation (which would be bad). */
1464 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1465 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1466 DONE;
1467 }
1468 })
1469
1470 ;; Discourage ai/addic because of carry but provide it in an alternative
1471 ;; allowing register zero as source.
1472 (define_insn "*add<mode>3_internal1"
1473 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1474 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1475 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1476 ""
1477 "@
1478 {cax|add} %0,%1,%2
1479 {cal %0,%2(%1)|addi %0,%1,%2}
1480 {ai|addic} %0,%1,%2
1481 {cau|addis} %0,%1,%v2"
1482 [(set_attr "length" "4,4,4,4")])
1483
1484 (define_insn "addsi3_high"
1485 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1486 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1487 (high:SI (match_operand 2 "" ""))))]
1488 "TARGET_MACHO && !TARGET_64BIT"
1489 "{cau|addis} %0,%1,ha16(%2)"
1490 [(set_attr "length" "4")])
1491
1492 (define_insn "*add<mode>3_internal2"
1493 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1494 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1495 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1496 (const_int 0)))
1497 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1498 ""
1499 "@
1500 {cax.|add.} %3,%1,%2
1501 {ai.|addic.} %3,%1,%2
1502 #
1503 #"
1504 [(set_attr "type" "fast_compare,compare,compare,compare")
1505 (set_attr "length" "4,4,8,8")])
1506
1507 (define_split
1508 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1509 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1510 (match_operand:GPR 2 "reg_or_short_operand" ""))
1511 (const_int 0)))
1512 (clobber (match_scratch:GPR 3 ""))]
1513 "reload_completed"
1514 [(set (match_dup 3)
1515 (plus:GPR (match_dup 1)
1516 (match_dup 2)))
1517 (set (match_dup 0)
1518 (compare:CC (match_dup 3)
1519 (const_int 0)))]
1520 "")
1521
1522 (define_insn "*add<mode>3_internal3"
1523 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1524 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1525 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1526 (const_int 0)))
1527 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1528 (plus:P (match_dup 1)
1529 (match_dup 2)))]
1530 ""
1531 "@
1532 {cax.|add.} %0,%1,%2
1533 {ai.|addic.} %0,%1,%2
1534 #
1535 #"
1536 [(set_attr "type" "fast_compare,compare,compare,compare")
1537 (set_attr "length" "4,4,8,8")])
1538
1539 (define_split
1540 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1541 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1542 (match_operand:P 2 "reg_or_short_operand" ""))
1543 (const_int 0)))
1544 (set (match_operand:P 0 "gpc_reg_operand" "")
1545 (plus:P (match_dup 1) (match_dup 2)))]
1546 "reload_completed"
1547 [(set (match_dup 0)
1548 (plus:P (match_dup 1)
1549 (match_dup 2)))
1550 (set (match_dup 3)
1551 (compare:CC (match_dup 0)
1552 (const_int 0)))]
1553 "")
1554
1555 ;; Split an add that we can't do in one insn into two insns, each of which
1556 ;; does one 16-bit part. This is used by combine. Note that the low-order
1557 ;; add should be last in case the result gets used in an address.
1558
1559 (define_split
1560 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1561 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1562 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1563 ""
1564 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1565 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1566 {
1567 HOST_WIDE_INT val = INTVAL (operands[2]);
1568 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1569 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1570
1571 operands[4] = GEN_INT (low);
1572 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1573 operands[3] = GEN_INT (rest);
1574 else if (! no_new_pseudos)
1575 {
1576 operands[3] = gen_reg_rtx (DImode);
1577 emit_move_insn (operands[3], operands[2]);
1578 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1579 DONE;
1580 }
1581 else
1582 FAIL;
1583 })
1584
1585 (define_insn "one_cmpl<mode>2"
1586 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1587 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1588 ""
1589 "nor %0,%1,%1")
1590
1591 (define_insn ""
1592 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1593 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1594 (const_int 0)))
1595 (clobber (match_scratch:P 2 "=r,r"))]
1596 ""
1597 "@
1598 nor. %2,%1,%1
1599 #"
1600 [(set_attr "type" "compare")
1601 (set_attr "length" "4,8")])
1602
1603 (define_split
1604 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1605 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1606 (const_int 0)))
1607 (clobber (match_scratch:P 2 ""))]
1608 "reload_completed"
1609 [(set (match_dup 2)
1610 (not:P (match_dup 1)))
1611 (set (match_dup 0)
1612 (compare:CC (match_dup 2)
1613 (const_int 0)))]
1614 "")
1615
1616 (define_insn ""
1617 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1618 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1619 (const_int 0)))
1620 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1621 (not:P (match_dup 1)))]
1622 ""
1623 "@
1624 nor. %0,%1,%1
1625 #"
1626 [(set_attr "type" "compare")
1627 (set_attr "length" "4,8")])
1628
1629 (define_split
1630 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1631 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1632 (const_int 0)))
1633 (set (match_operand:P 0 "gpc_reg_operand" "")
1634 (not:P (match_dup 1)))]
1635 "reload_completed"
1636 [(set (match_dup 0)
1637 (not:P (match_dup 1)))
1638 (set (match_dup 2)
1639 (compare:CC (match_dup 0)
1640 (const_int 0)))]
1641 "")
1642
1643 (define_insn ""
1644 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1645 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1646 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1647 "! TARGET_POWERPC"
1648 "{sf%I1|subf%I1c} %0,%2,%1")
1649
1650 (define_insn ""
1651 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1652 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1653 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1654 "TARGET_POWERPC"
1655 "@
1656 subf %0,%2,%1
1657 subfic %0,%2,%1")
1658
1659 (define_insn ""
1660 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1661 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1662 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1663 (const_int 0)))
1664 (clobber (match_scratch:SI 3 "=r,r"))]
1665 "! TARGET_POWERPC"
1666 "@
1667 {sf.|subfc.} %3,%2,%1
1668 #"
1669 [(set_attr "type" "compare")
1670 (set_attr "length" "4,8")])
1671
1672 (define_insn ""
1673 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1674 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1675 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1676 (const_int 0)))
1677 (clobber (match_scratch:P 3 "=r,r"))]
1678 "TARGET_POWERPC"
1679 "@
1680 subf. %3,%2,%1
1681 #"
1682 [(set_attr "type" "fast_compare")
1683 (set_attr "length" "4,8")])
1684
1685 (define_split
1686 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1687 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1688 (match_operand:P 2 "gpc_reg_operand" ""))
1689 (const_int 0)))
1690 (clobber (match_scratch:P 3 ""))]
1691 "reload_completed"
1692 [(set (match_dup 3)
1693 (minus:P (match_dup 1)
1694 (match_dup 2)))
1695 (set (match_dup 0)
1696 (compare:CC (match_dup 3)
1697 (const_int 0)))]
1698 "")
1699
1700 (define_insn ""
1701 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1702 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1703 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1704 (const_int 0)))
1705 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1706 (minus:SI (match_dup 1) (match_dup 2)))]
1707 "! TARGET_POWERPC"
1708 "@
1709 {sf.|subfc.} %0,%2,%1
1710 #"
1711 [(set_attr "type" "compare")
1712 (set_attr "length" "4,8")])
1713
1714 (define_insn ""
1715 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1716 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1717 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1718 (const_int 0)))
1719 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1720 (minus:P (match_dup 1)
1721 (match_dup 2)))]
1722 "TARGET_POWERPC"
1723 "@
1724 subf. %0,%2,%1
1725 #"
1726 [(set_attr "type" "fast_compare")
1727 (set_attr "length" "4,8")])
1728
1729 (define_split
1730 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1731 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1732 (match_operand:P 2 "gpc_reg_operand" ""))
1733 (const_int 0)))
1734 (set (match_operand:P 0 "gpc_reg_operand" "")
1735 (minus:P (match_dup 1)
1736 (match_dup 2)))]
1737 "reload_completed"
1738 [(set (match_dup 0)
1739 (minus:P (match_dup 1)
1740 (match_dup 2)))
1741 (set (match_dup 3)
1742 (compare:CC (match_dup 0)
1743 (const_int 0)))]
1744 "")
1745
1746 (define_expand "sub<mode>3"
1747 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1748 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1749 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1750 ""
1751 "
1752 {
1753 if (GET_CODE (operands[2]) == CONST_INT)
1754 {
1755 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1756 negate_rtx (<MODE>mode, operands[2])));
1757 DONE;
1758 }
1759 }")
1760
1761 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1762 ;; instruction and some auxiliary computations. Then we just have a single
1763 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1764 ;; combine.
1765
1766 (define_expand "sminsi3"
1767 [(set (match_dup 3)
1768 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1769 (match_operand:SI 2 "reg_or_short_operand" ""))
1770 (const_int 0)
1771 (minus:SI (match_dup 2) (match_dup 1))))
1772 (set (match_operand:SI 0 "gpc_reg_operand" "")
1773 (minus:SI (match_dup 2) (match_dup 3)))]
1774 "TARGET_POWER || TARGET_ISEL"
1775 "
1776 {
1777 if (TARGET_ISEL)
1778 {
1779 operands[2] = force_reg (SImode, operands[2]);
1780 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1781 DONE;
1782 }
1783
1784 operands[3] = gen_reg_rtx (SImode);
1785 }")
1786
1787 (define_split
1788 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1789 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1790 (match_operand:SI 2 "reg_or_short_operand" "")))
1791 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1792 "TARGET_POWER"
1793 [(set (match_dup 3)
1794 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1795 (const_int 0)
1796 (minus:SI (match_dup 2) (match_dup 1))))
1797 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1798 "")
1799
1800 (define_expand "smaxsi3"
1801 [(set (match_dup 3)
1802 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1803 (match_operand:SI 2 "reg_or_short_operand" ""))
1804 (const_int 0)
1805 (minus:SI (match_dup 2) (match_dup 1))))
1806 (set (match_operand:SI 0 "gpc_reg_operand" "")
1807 (plus:SI (match_dup 3) (match_dup 1)))]
1808 "TARGET_POWER || TARGET_ISEL"
1809 "
1810 {
1811 if (TARGET_ISEL)
1812 {
1813 operands[2] = force_reg (SImode, operands[2]);
1814 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1815 DONE;
1816 }
1817 operands[3] = gen_reg_rtx (SImode);
1818 }")
1819
1820 (define_split
1821 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1822 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1823 (match_operand:SI 2 "reg_or_short_operand" "")))
1824 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1825 "TARGET_POWER"
1826 [(set (match_dup 3)
1827 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1828 (const_int 0)
1829 (minus:SI (match_dup 2) (match_dup 1))))
1830 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1831 "")
1832
1833 (define_expand "uminsi3"
1834 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1835 (match_dup 5)))
1836 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1837 (match_dup 5)))
1838 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1839 (const_int 0)
1840 (minus:SI (match_dup 4) (match_dup 3))))
1841 (set (match_operand:SI 0 "gpc_reg_operand" "")
1842 (minus:SI (match_dup 2) (match_dup 3)))]
1843 "TARGET_POWER || TARGET_ISEL"
1844 "
1845 {
1846 if (TARGET_ISEL)
1847 {
1848 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1849 DONE;
1850 }
1851 operands[3] = gen_reg_rtx (SImode);
1852 operands[4] = gen_reg_rtx (SImode);
1853 operands[5] = GEN_INT (-2147483647 - 1);
1854 }")
1855
1856 (define_expand "umaxsi3"
1857 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1858 (match_dup 5)))
1859 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1860 (match_dup 5)))
1861 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1862 (const_int 0)
1863 (minus:SI (match_dup 4) (match_dup 3))))
1864 (set (match_operand:SI 0 "gpc_reg_operand" "")
1865 (plus:SI (match_dup 3) (match_dup 1)))]
1866 "TARGET_POWER || TARGET_ISEL"
1867 "
1868 {
1869 if (TARGET_ISEL)
1870 {
1871 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1872 DONE;
1873 }
1874 operands[3] = gen_reg_rtx (SImode);
1875 operands[4] = gen_reg_rtx (SImode);
1876 operands[5] = GEN_INT (-2147483647 - 1);
1877 }")
1878
1879 (define_insn ""
1880 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1881 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1882 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1883 (const_int 0)
1884 (minus:SI (match_dup 2) (match_dup 1))))]
1885 "TARGET_POWER"
1886 "doz%I2 %0,%1,%2")
1887
1888 (define_insn ""
1889 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1890 (compare:CC
1891 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1892 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1893 (const_int 0)
1894 (minus:SI (match_dup 2) (match_dup 1)))
1895 (const_int 0)))
1896 (clobber (match_scratch:SI 3 "=r,r"))]
1897 "TARGET_POWER"
1898 "@
1899 doz%I2. %3,%1,%2
1900 #"
1901 [(set_attr "type" "delayed_compare")
1902 (set_attr "length" "4,8")])
1903
1904 (define_split
1905 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1906 (compare:CC
1907 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1908 (match_operand:SI 2 "reg_or_short_operand" ""))
1909 (const_int 0)
1910 (minus:SI (match_dup 2) (match_dup 1)))
1911 (const_int 0)))
1912 (clobber (match_scratch:SI 3 ""))]
1913 "TARGET_POWER && reload_completed"
1914 [(set (match_dup 3)
1915 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1916 (const_int 0)
1917 (minus:SI (match_dup 2) (match_dup 1))))
1918 (set (match_dup 0)
1919 (compare:CC (match_dup 3)
1920 (const_int 0)))]
1921 "")
1922
1923 (define_insn ""
1924 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1925 (compare:CC
1926 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1927 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1928 (const_int 0)
1929 (minus:SI (match_dup 2) (match_dup 1)))
1930 (const_int 0)))
1931 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1932 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1933 (const_int 0)
1934 (minus:SI (match_dup 2) (match_dup 1))))]
1935 "TARGET_POWER"
1936 "@
1937 doz%I2. %0,%1,%2
1938 #"
1939 [(set_attr "type" "delayed_compare")
1940 (set_attr "length" "4,8")])
1941
1942 (define_split
1943 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1944 (compare:CC
1945 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1946 (match_operand:SI 2 "reg_or_short_operand" ""))
1947 (const_int 0)
1948 (minus:SI (match_dup 2) (match_dup 1)))
1949 (const_int 0)))
1950 (set (match_operand:SI 0 "gpc_reg_operand" "")
1951 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1952 (const_int 0)
1953 (minus:SI (match_dup 2) (match_dup 1))))]
1954 "TARGET_POWER && reload_completed"
1955 [(set (match_dup 0)
1956 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1957 (const_int 0)
1958 (minus:SI (match_dup 2) (match_dup 1))))
1959 (set (match_dup 3)
1960 (compare:CC (match_dup 0)
1961 (const_int 0)))]
1962 "")
1963
1964 ;; We don't need abs with condition code because such comparisons should
1965 ;; never be done.
1966 (define_expand "abssi2"
1967 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1968 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1969 ""
1970 "
1971 {
1972 if (TARGET_ISEL)
1973 {
1974 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1975 DONE;
1976 }
1977 else if (! TARGET_POWER)
1978 {
1979 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1980 DONE;
1981 }
1982 }")
1983
1984 (define_insn "*abssi2_power"
1985 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1986 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1987 "TARGET_POWER"
1988 "abs %0,%1")
1989
1990 (define_insn_and_split "abssi2_isel"
1991 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1992 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
1993 (clobber (match_scratch:SI 2 "=&b"))
1994 (clobber (match_scratch:CC 3 "=y"))]
1995 "TARGET_ISEL"
1996 "#"
1997 "&& reload_completed"
1998 [(set (match_dup 2) (neg:SI (match_dup 1)))
1999 (set (match_dup 3)
2000 (compare:CC (match_dup 1)
2001 (const_int 0)))
2002 (set (match_dup 0)
2003 (if_then_else:SI (ge (match_dup 3)
2004 (const_int 0))
2005 (match_dup 1)
2006 (match_dup 2)))]
2007 "")
2008
2009 (define_insn_and_split "abssi2_nopower"
2010 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2011 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2012 (clobber (match_scratch:SI 2 "=&r,&r"))]
2013 "! TARGET_POWER && ! TARGET_ISEL"
2014 "#"
2015 "&& reload_completed"
2016 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2017 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2018 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2019 "")
2020
2021 (define_insn "*nabs_power"
2022 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2023 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2024 "TARGET_POWER"
2025 "nabs %0,%1")
2026
2027 (define_insn_and_split "*nabs_nopower"
2028 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2029 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2030 (clobber (match_scratch:SI 2 "=&r,&r"))]
2031 "! TARGET_POWER"
2032 "#"
2033 "&& reload_completed"
2034 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2035 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2036 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2037 "")
2038
2039 (define_expand "neg<mode>2"
2040 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2041 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2042 ""
2043 "")
2044
2045 (define_insn "*neg<mode>2_internal"
2046 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2047 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2048 ""
2049 "neg %0,%1")
2050
2051 (define_insn ""
2052 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2053 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2054 (const_int 0)))
2055 (clobber (match_scratch:P 2 "=r,r"))]
2056 ""
2057 "@
2058 neg. %2,%1
2059 #"
2060 [(set_attr "type" "fast_compare")
2061 (set_attr "length" "4,8")])
2062
2063 (define_split
2064 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2065 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2066 (const_int 0)))
2067 (clobber (match_scratch:P 2 ""))]
2068 "reload_completed"
2069 [(set (match_dup 2)
2070 (neg:P (match_dup 1)))
2071 (set (match_dup 0)
2072 (compare:CC (match_dup 2)
2073 (const_int 0)))]
2074 "")
2075
2076 (define_insn ""
2077 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2078 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2079 (const_int 0)))
2080 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2081 (neg:P (match_dup 1)))]
2082 ""
2083 "@
2084 neg. %0,%1
2085 #"
2086 [(set_attr "type" "fast_compare")
2087 (set_attr "length" "4,8")])
2088
2089 (define_split
2090 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2091 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2092 (const_int 0)))
2093 (set (match_operand:P 0 "gpc_reg_operand" "")
2094 (neg:P (match_dup 1)))]
2095 "reload_completed"
2096 [(set (match_dup 0)
2097 (neg:P (match_dup 1)))
2098 (set (match_dup 2)
2099 (compare:CC (match_dup 0)
2100 (const_int 0)))]
2101 "")
2102
2103 (define_insn "clz<mode>2"
2104 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2105 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2106 ""
2107 "{cntlz|cntlz<wd>} %0,%1"
2108 [(set_attr "type" "cntlz")])
2109
2110 (define_expand "ctz<mode>2"
2111 [(set (match_dup 2)
2112 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
2113 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2114 (match_dup 2)))
2115 (clobber (scratch:CC))])
2116 (set (match_dup 4) (clz:GPR (match_dup 3)))
2117 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2118 (minus:GPR (match_dup 5) (match_dup 4)))]
2119 ""
2120 {
2121 operands[2] = gen_reg_rtx (<MODE>mode);
2122 operands[3] = gen_reg_rtx (<MODE>mode);
2123 operands[4] = gen_reg_rtx (<MODE>mode);
2124 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2125 })
2126
2127 (define_expand "ffs<mode>2"
2128 [(set (match_dup 2)
2129 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
2130 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2131 (match_dup 2)))
2132 (clobber (scratch:CC))])
2133 (set (match_dup 4) (clz:GPR (match_dup 3)))
2134 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2135 (minus:GPR (match_dup 5) (match_dup 4)))]
2136 ""
2137 {
2138 operands[2] = gen_reg_rtx (<MODE>mode);
2139 operands[3] = gen_reg_rtx (<MODE>mode);
2140 operands[4] = gen_reg_rtx (<MODE>mode);
2141 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2142 })
2143
2144 (define_expand "popcount<mode>2"
2145 [(set (match_dup 2)
2146 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2147 UNSPEC_POPCNTB))
2148 (set (match_dup 3)
2149 (mult:GPR (match_dup 2) (match_dup 4)))
2150 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2151 (lshiftrt:GPR (match_dup 3) (match_dup 5)))]
2152 "TARGET_POPCNTB"
2153 {
2154 operands[2] = gen_reg_rtx (<MODE>mode);
2155 operands[3] = gen_reg_rtx (<MODE>mode);
2156 operands[4] = force_reg (<MODE>mode,
2157 <MODE>mode == SImode
2158 ? GEN_INT (0x01010101)
2159 : GEN_INT ((HOST_WIDE_INT)
2160 0x01010101 << 32 | 0x01010101));
2161 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 8);
2162 })
2163
2164 (define_insn "popcntb<mode>2"
2165 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2166 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2167 UNSPEC_POPCNTB))]
2168 "TARGET_POPCNTB"
2169 "popcntb %0,%1")
2170
2171 (define_expand "mulsi3"
2172 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2173 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2174 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2175 ""
2176 "
2177 {
2178 if (TARGET_POWER)
2179 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2180 else
2181 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2182 DONE;
2183 }")
2184
2185 (define_insn "mulsi3_mq"
2186 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2187 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2188 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2189 (clobber (match_scratch:SI 3 "=q,q"))]
2190 "TARGET_POWER"
2191 "@
2192 {muls|mullw} %0,%1,%2
2193 {muli|mulli} %0,%1,%2"
2194 [(set (attr "type")
2195 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2196 (const_string "imul3")
2197 (match_operand:SI 2 "short_cint_operand" "")
2198 (const_string "imul2")]
2199 (const_string "imul")))])
2200
2201 (define_insn "mulsi3_no_mq"
2202 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2203 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2204 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2205 "! TARGET_POWER"
2206 "@
2207 {muls|mullw} %0,%1,%2
2208 {muli|mulli} %0,%1,%2"
2209 [(set (attr "type")
2210 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2211 (const_string "imul3")
2212 (match_operand:SI 2 "short_cint_operand" "")
2213 (const_string "imul2")]
2214 (const_string "imul")))])
2215
2216 (define_insn "*mulsi3_mq_internal1"
2217 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2218 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2219 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2220 (const_int 0)))
2221 (clobber (match_scratch:SI 3 "=r,r"))
2222 (clobber (match_scratch:SI 4 "=q,q"))]
2223 "TARGET_POWER"
2224 "@
2225 {muls.|mullw.} %3,%1,%2
2226 #"
2227 [(set_attr "type" "imul_compare")
2228 (set_attr "length" "4,8")])
2229
2230 (define_split
2231 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2232 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2233 (match_operand:SI 2 "gpc_reg_operand" ""))
2234 (const_int 0)))
2235 (clobber (match_scratch:SI 3 ""))
2236 (clobber (match_scratch:SI 4 ""))]
2237 "TARGET_POWER && reload_completed"
2238 [(parallel [(set (match_dup 3)
2239 (mult:SI (match_dup 1) (match_dup 2)))
2240 (clobber (match_dup 4))])
2241 (set (match_dup 0)
2242 (compare:CC (match_dup 3)
2243 (const_int 0)))]
2244 "")
2245
2246 (define_insn "*mulsi3_no_mq_internal1"
2247 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2248 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2249 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2250 (const_int 0)))
2251 (clobber (match_scratch:SI 3 "=r,r"))]
2252 "! TARGET_POWER"
2253 "@
2254 {muls.|mullw.} %3,%1,%2
2255 #"
2256 [(set_attr "type" "imul_compare")
2257 (set_attr "length" "4,8")])
2258
2259 (define_split
2260 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2261 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2262 (match_operand:SI 2 "gpc_reg_operand" ""))
2263 (const_int 0)))
2264 (clobber (match_scratch:SI 3 ""))]
2265 "! TARGET_POWER && reload_completed"
2266 [(set (match_dup 3)
2267 (mult:SI (match_dup 1) (match_dup 2)))
2268 (set (match_dup 0)
2269 (compare:CC (match_dup 3)
2270 (const_int 0)))]
2271 "")
2272
2273 (define_insn "*mulsi3_mq_internal2"
2274 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2275 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2276 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2277 (const_int 0)))
2278 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2279 (mult:SI (match_dup 1) (match_dup 2)))
2280 (clobber (match_scratch:SI 4 "=q,q"))]
2281 "TARGET_POWER"
2282 "@
2283 {muls.|mullw.} %0,%1,%2
2284 #"
2285 [(set_attr "type" "imul_compare")
2286 (set_attr "length" "4,8")])
2287
2288 (define_split
2289 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2290 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2291 (match_operand:SI 2 "gpc_reg_operand" ""))
2292 (const_int 0)))
2293 (set (match_operand:SI 0 "gpc_reg_operand" "")
2294 (mult:SI (match_dup 1) (match_dup 2)))
2295 (clobber (match_scratch:SI 4 ""))]
2296 "TARGET_POWER && reload_completed"
2297 [(parallel [(set (match_dup 0)
2298 (mult:SI (match_dup 1) (match_dup 2)))
2299 (clobber (match_dup 4))])
2300 (set (match_dup 3)
2301 (compare:CC (match_dup 0)
2302 (const_int 0)))]
2303 "")
2304
2305 (define_insn "*mulsi3_no_mq_internal2"
2306 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2307 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2308 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2309 (const_int 0)))
2310 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2311 (mult:SI (match_dup 1) (match_dup 2)))]
2312 "! TARGET_POWER"
2313 "@
2314 {muls.|mullw.} %0,%1,%2
2315 #"
2316 [(set_attr "type" "imul_compare")
2317 (set_attr "length" "4,8")])
2318
2319 (define_split
2320 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2321 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2322 (match_operand:SI 2 "gpc_reg_operand" ""))
2323 (const_int 0)))
2324 (set (match_operand:SI 0 "gpc_reg_operand" "")
2325 (mult:SI (match_dup 1) (match_dup 2)))]
2326 "! TARGET_POWER && reload_completed"
2327 [(set (match_dup 0)
2328 (mult:SI (match_dup 1) (match_dup 2)))
2329 (set (match_dup 3)
2330 (compare:CC (match_dup 0)
2331 (const_int 0)))]
2332 "")
2333
2334 ;; Operand 1 is divided by operand 2; quotient goes to operand
2335 ;; 0 and remainder to operand 3.
2336 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2337
2338 (define_expand "divmodsi4"
2339 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2340 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2341 (match_operand:SI 2 "gpc_reg_operand" "")))
2342 (set (match_operand:SI 3 "register_operand" "")
2343 (mod:SI (match_dup 1) (match_dup 2)))])]
2344 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2345 "
2346 {
2347 if (! TARGET_POWER && ! TARGET_POWERPC)
2348 {
2349 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2350 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2351 emit_insn (gen_divss_call ());
2352 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2353 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2354 DONE;
2355 }
2356 }")
2357
2358 (define_insn "*divmodsi4_internal"
2359 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2360 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2361 (match_operand:SI 2 "gpc_reg_operand" "r")))
2362 (set (match_operand:SI 3 "register_operand" "=q")
2363 (mod:SI (match_dup 1) (match_dup 2)))]
2364 "TARGET_POWER"
2365 "divs %0,%1,%2"
2366 [(set_attr "type" "idiv")])
2367
2368 (define_expand "udiv<mode>3"
2369 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2370 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2371 (match_operand:GPR 2 "gpc_reg_operand" "")))]
2372 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2373 "
2374 {
2375 if (! TARGET_POWER && ! TARGET_POWERPC)
2376 {
2377 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2378 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2379 emit_insn (gen_quous_call ());
2380 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2381 DONE;
2382 }
2383 else if (TARGET_POWER)
2384 {
2385 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2386 DONE;
2387 }
2388 }")
2389
2390 (define_insn "udivsi3_mq"
2391 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2392 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2393 (match_operand:SI 2 "gpc_reg_operand" "r")))
2394 (clobber (match_scratch:SI 3 "=q"))]
2395 "TARGET_POWERPC && TARGET_POWER"
2396 "divwu %0,%1,%2"
2397 [(set_attr "type" "idiv")])
2398
2399 (define_insn "*udivsi3_no_mq"
2400 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2401 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2402 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2403 "TARGET_POWERPC && ! TARGET_POWER"
2404 "div<wd>u %0,%1,%2"
2405 [(set (attr "type")
2406 (cond [(match_operand:SI 0 "" "")
2407 (const_string "idiv")]
2408 (const_string "ldiv")))])
2409
2410
2411 ;; For powers of two we can do srai/aze for divide and then adjust for
2412 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2413 ;; used; for PowerPC, force operands into register and do a normal divide;
2414 ;; for AIX common-mode, use quoss call on register operands.
2415 (define_expand "div<mode>3"
2416 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2417 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2418 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2419 ""
2420 "
2421 {
2422 if (GET_CODE (operands[2]) == CONST_INT
2423 && INTVAL (operands[2]) > 0
2424 && exact_log2 (INTVAL (operands[2])) >= 0)
2425 ;
2426 else if (TARGET_POWERPC)
2427 {
2428 operands[2] = force_reg (SImode, operands[2]);
2429 if (TARGET_POWER)
2430 {
2431 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2432 DONE;
2433 }
2434 }
2435 else if (TARGET_POWER)
2436 FAIL;
2437 else
2438 {
2439 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2440 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2441 emit_insn (gen_quoss_call ());
2442 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2443 DONE;
2444 }
2445 }")
2446
2447 (define_insn "divsi3_mq"
2448 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2449 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2450 (match_operand:SI 2 "gpc_reg_operand" "r")))
2451 (clobber (match_scratch:SI 3 "=q"))]
2452 "TARGET_POWERPC && TARGET_POWER"
2453 "divw %0,%1,%2"
2454 [(set_attr "type" "idiv")])
2455
2456 (define_insn "*div<mode>3_no_mq"
2457 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2458 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2459 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2460 "TARGET_POWERPC && ! TARGET_POWER"
2461 "div<wd> %0,%1,%2"
2462 [(set (attr "type")
2463 (cond [(match_operand:SI 0 "" "")
2464 (const_string "idiv")]
2465 (const_string "ldiv")))])
2466
2467 (define_expand "mod<mode>3"
2468 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2469 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2470 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2471 ""
2472 "
2473 {
2474 int i;
2475 rtx temp1;
2476 rtx temp2;
2477
2478 if (GET_CODE (operands[2]) != CONST_INT
2479 || INTVAL (operands[2]) <= 0
2480 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2481 FAIL;
2482
2483 temp1 = gen_reg_rtx (<MODE>mode);
2484 temp2 = gen_reg_rtx (<MODE>mode);
2485
2486 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2487 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2488 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2489 DONE;
2490 }")
2491
2492 (define_insn ""
2493 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2494 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2495 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2496 ""
2497 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
2498 [(set_attr "type" "two")
2499 (set_attr "length" "8")])
2500
2501 (define_insn ""
2502 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2503 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2504 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2505 (const_int 0)))
2506 (clobber (match_scratch:P 3 "=r,r"))]
2507 ""
2508 "@
2509 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
2510 #"
2511 [(set_attr "type" "compare")
2512 (set_attr "length" "8,12")])
2513
2514 (define_split
2515 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2516 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2517 (match_operand:GPR 2 "exact_log2_cint_operand"
2518 ""))
2519 (const_int 0)))
2520 (clobber (match_scratch:GPR 3 ""))]
2521 "reload_completed"
2522 [(set (match_dup 3)
2523 (div:<MODE> (match_dup 1) (match_dup 2)))
2524 (set (match_dup 0)
2525 (compare:CC (match_dup 3)
2526 (const_int 0)))]
2527 "")
2528
2529 (define_insn ""
2530 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2531 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2532 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2533 (const_int 0)))
2534 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2535 (div:P (match_dup 1) (match_dup 2)))]
2536 ""
2537 "@
2538 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
2539 #"
2540 [(set_attr "type" "compare")
2541 (set_attr "length" "8,12")])
2542
2543 (define_split
2544 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2545 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2546 (match_operand:GPR 2 "exact_log2_cint_operand"
2547 ""))
2548 (const_int 0)))
2549 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2550 (div:GPR (match_dup 1) (match_dup 2)))]
2551 "reload_completed"
2552 [(set (match_dup 0)
2553 (div:<MODE> (match_dup 1) (match_dup 2)))
2554 (set (match_dup 3)
2555 (compare:CC (match_dup 0)
2556 (const_int 0)))]
2557 "")
2558
2559 (define_insn ""
2560 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2561 (udiv:SI
2562 (plus:DI (ashift:DI
2563 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2564 (const_int 32))
2565 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2566 (match_operand:SI 3 "gpc_reg_operand" "r")))
2567 (set (match_operand:SI 2 "register_operand" "=*q")
2568 (umod:SI
2569 (plus:DI (ashift:DI
2570 (zero_extend:DI (match_dup 1)) (const_int 32))
2571 (zero_extend:DI (match_dup 4)))
2572 (match_dup 3)))]
2573 "TARGET_POWER"
2574 "div %0,%1,%3"
2575 [(set_attr "type" "idiv")])
2576
2577 ;; To do unsigned divide we handle the cases of the divisor looking like a
2578 ;; negative number. If it is a constant that is less than 2**31, we don't
2579 ;; have to worry about the branches. So make a few subroutines here.
2580 ;;
2581 ;; First comes the normal case.
2582 (define_expand "udivmodsi4_normal"
2583 [(set (match_dup 4) (const_int 0))
2584 (parallel [(set (match_operand:SI 0 "" "")
2585 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2586 (const_int 32))
2587 (zero_extend:DI (match_operand:SI 1 "" "")))
2588 (match_operand:SI 2 "" "")))
2589 (set (match_operand:SI 3 "" "")
2590 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2591 (const_int 32))
2592 (zero_extend:DI (match_dup 1)))
2593 (match_dup 2)))])]
2594 "TARGET_POWER"
2595 "
2596 { operands[4] = gen_reg_rtx (SImode); }")
2597
2598 ;; This handles the branches.
2599 (define_expand "udivmodsi4_tests"
2600 [(set (match_operand:SI 0 "" "") (const_int 0))
2601 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2602 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2603 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2604 (label_ref (match_operand:SI 4 "" "")) (pc)))
2605 (set (match_dup 0) (const_int 1))
2606 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2607 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2608 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2609 (label_ref (match_dup 4)) (pc)))]
2610 "TARGET_POWER"
2611 "
2612 { operands[5] = gen_reg_rtx (CCUNSmode);
2613 operands[6] = gen_reg_rtx (CCmode);
2614 }")
2615
2616 (define_expand "udivmodsi4"
2617 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2618 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2619 (match_operand:SI 2 "reg_or_cint_operand" "")))
2620 (set (match_operand:SI 3 "gpc_reg_operand" "")
2621 (umod:SI (match_dup 1) (match_dup 2)))])]
2622 ""
2623 "
2624 {
2625 rtx label = 0;
2626
2627 if (! TARGET_POWER)
2628 {
2629 if (! TARGET_POWERPC)
2630 {
2631 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2632 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2633 emit_insn (gen_divus_call ());
2634 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2635 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2636 DONE;
2637 }
2638 else
2639 FAIL;
2640 }
2641
2642 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2643 {
2644 operands[2] = force_reg (SImode, operands[2]);
2645 label = gen_label_rtx ();
2646 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2647 operands[3], label));
2648 }
2649 else
2650 operands[2] = force_reg (SImode, operands[2]);
2651
2652 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2653 operands[3]));
2654 if (label)
2655 emit_label (label);
2656
2657 DONE;
2658 }")
2659
2660 ;; AIX architecture-independent common-mode multiply (DImode),
2661 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2662 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2663 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2664 ;; assumed unused if generating common-mode, so ignore.
2665 (define_insn "mulh_call"
2666 [(set (reg:SI 3)
2667 (truncate:SI
2668 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2669 (sign_extend:DI (reg:SI 4)))
2670 (const_int 32))))
2671 (clobber (match_scratch:SI 0 "=l"))]
2672 "! TARGET_POWER && ! TARGET_POWERPC"
2673 "bla __mulh"
2674 [(set_attr "type" "imul")])
2675
2676 (define_insn "mull_call"
2677 [(set (reg:DI 3)
2678 (mult:DI (sign_extend:DI (reg:SI 3))
2679 (sign_extend:DI (reg:SI 4))))
2680 (clobber (match_scratch:SI 0 "=l"))
2681 (clobber (reg:SI 0))]
2682 "! TARGET_POWER && ! TARGET_POWERPC"
2683 "bla __mull"
2684 [(set_attr "type" "imul")])
2685
2686 (define_insn "divss_call"
2687 [(set (reg:SI 3)
2688 (div:SI (reg:SI 3) (reg:SI 4)))
2689 (set (reg:SI 4)
2690 (mod:SI (reg:SI 3) (reg:SI 4)))
2691 (clobber (match_scratch:SI 0 "=l"))
2692 (clobber (reg:SI 0))]
2693 "! TARGET_POWER && ! TARGET_POWERPC"
2694 "bla __divss"
2695 [(set_attr "type" "idiv")])
2696
2697 (define_insn "divus_call"
2698 [(set (reg:SI 3)
2699 (udiv:SI (reg:SI 3) (reg:SI 4)))
2700 (set (reg:SI 4)
2701 (umod:SI (reg:SI 3) (reg:SI 4)))
2702 (clobber (match_scratch:SI 0 "=l"))
2703 (clobber (reg:SI 0))
2704 (clobber (match_scratch:CC 1 "=x"))
2705 (clobber (reg:CC 69))]
2706 "! TARGET_POWER && ! TARGET_POWERPC"
2707 "bla __divus"
2708 [(set_attr "type" "idiv")])
2709
2710 (define_insn "quoss_call"
2711 [(set (reg:SI 3)
2712 (div:SI (reg:SI 3) (reg:SI 4)))
2713 (clobber (match_scratch:SI 0 "=l"))]
2714 "! TARGET_POWER && ! TARGET_POWERPC"
2715 "bla __quoss"
2716 [(set_attr "type" "idiv")])
2717
2718 (define_insn "quous_call"
2719 [(set (reg:SI 3)
2720 (udiv:SI (reg:SI 3) (reg:SI 4)))
2721 (clobber (match_scratch:SI 0 "=l"))
2722 (clobber (reg:SI 0))
2723 (clobber (match_scratch:CC 1 "=x"))
2724 (clobber (reg:CC 69))]
2725 "! TARGET_POWER && ! TARGET_POWERPC"
2726 "bla __quous"
2727 [(set_attr "type" "idiv")])
2728 \f
2729 ;; Logical instructions
2730 ;; The logical instructions are mostly combined by using match_operator,
2731 ;; but the plain AND insns are somewhat different because there is no
2732 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2733 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2734
2735 (define_insn "andsi3"
2736 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2737 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2738 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2739 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2740 ""
2741 "@
2742 and %0,%1,%2
2743 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2744 {andil.|andi.} %0,%1,%b2
2745 {andiu.|andis.} %0,%1,%u2"
2746 [(set_attr "type" "*,*,compare,compare")])
2747
2748 ;; Note to set cr's other than cr0 we do the and immediate and then
2749 ;; the test again -- this avoids a mfcr which on the higher end
2750 ;; machines causes an execution serialization
2751
2752 (define_insn "*andsi3_internal2"
2753 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2754 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2755 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2756 (const_int 0)))
2757 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2758 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2759 "TARGET_32BIT"
2760 "@
2761 and. %3,%1,%2
2762 {andil.|andi.} %3,%1,%b2
2763 {andiu.|andis.} %3,%1,%u2
2764 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2765 #
2766 #
2767 #
2768 #"
2769 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2770 (set_attr "length" "4,4,4,4,8,8,8,8")])
2771
2772 (define_insn "*andsi3_internal3"
2773 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2774 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2775 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2776 (const_int 0)))
2777 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2778 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2779 "TARGET_64BIT"
2780 "@
2781 #
2782 {andil.|andi.} %3,%1,%b2
2783 {andiu.|andis.} %3,%1,%u2
2784 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2785 #
2786 #
2787 #
2788 #"
2789 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2790 (set_attr "length" "8,4,4,4,8,8,8,8")])
2791
2792 (define_split
2793 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2794 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2795 (match_operand:GPR 2 "and_operand" ""))
2796 (const_int 0)))
2797 (clobber (match_scratch:GPR 3 ""))
2798 (clobber (match_scratch:CC 4 ""))]
2799 "reload_completed"
2800 [(parallel [(set (match_dup 3)
2801 (and:<MODE> (match_dup 1)
2802 (match_dup 2)))
2803 (clobber (match_dup 4))])
2804 (set (match_dup 0)
2805 (compare:CC (match_dup 3)
2806 (const_int 0)))]
2807 "")
2808
2809 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2810 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2811
2812 (define_split
2813 [(set (match_operand:CC 0 "cc_reg_operand" "")
2814 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2815 (match_operand:SI 2 "gpc_reg_operand" ""))
2816 (const_int 0)))
2817 (clobber (match_scratch:SI 3 ""))
2818 (clobber (match_scratch:CC 4 ""))]
2819 "TARGET_POWERPC64 && reload_completed"
2820 [(parallel [(set (match_dup 3)
2821 (and:SI (match_dup 1)
2822 (match_dup 2)))
2823 (clobber (match_dup 4))])
2824 (set (match_dup 0)
2825 (compare:CC (match_dup 3)
2826 (const_int 0)))]
2827 "")
2828
2829 (define_insn "*andsi3_internal4"
2830 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2831 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2832 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2833 (const_int 0)))
2834 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2835 (and:SI (match_dup 1)
2836 (match_dup 2)))
2837 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2838 "TARGET_32BIT"
2839 "@
2840 and. %0,%1,%2
2841 {andil.|andi.} %0,%1,%b2
2842 {andiu.|andis.} %0,%1,%u2
2843 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2844 #
2845 #
2846 #
2847 #"
2848 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2849 (set_attr "length" "4,4,4,4,8,8,8,8")])
2850
2851 (define_insn "*andsi3_internal5"
2852 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2853 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2854 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2855 (const_int 0)))
2856 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2857 (and:SI (match_dup 1)
2858 (match_dup 2)))
2859 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2860 "TARGET_64BIT"
2861 "@
2862 #
2863 {andil.|andi.} %0,%1,%b2
2864 {andiu.|andis.} %0,%1,%u2
2865 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2866 #
2867 #
2868 #
2869 #"
2870 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2871 (set_attr "length" "8,4,4,4,8,8,8,8")])
2872
2873 (define_split
2874 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2875 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2876 (match_operand:SI 2 "and_operand" ""))
2877 (const_int 0)))
2878 (set (match_operand:SI 0 "gpc_reg_operand" "")
2879 (and:SI (match_dup 1)
2880 (match_dup 2)))
2881 (clobber (match_scratch:CC 4 ""))]
2882 "reload_completed"
2883 [(parallel [(set (match_dup 0)
2884 (and:SI (match_dup 1)
2885 (match_dup 2)))
2886 (clobber (match_dup 4))])
2887 (set (match_dup 3)
2888 (compare:CC (match_dup 0)
2889 (const_int 0)))]
2890 "")
2891
2892 (define_split
2893 [(set (match_operand:CC 3 "cc_reg_operand" "")
2894 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2895 (match_operand:SI 2 "gpc_reg_operand" ""))
2896 (const_int 0)))
2897 (set (match_operand:SI 0 "gpc_reg_operand" "")
2898 (and:SI (match_dup 1)
2899 (match_dup 2)))
2900 (clobber (match_scratch:CC 4 ""))]
2901 "TARGET_POWERPC64 && reload_completed"
2902 [(parallel [(set (match_dup 0)
2903 (and:SI (match_dup 1)
2904 (match_dup 2)))
2905 (clobber (match_dup 4))])
2906 (set (match_dup 3)
2907 (compare:CC (match_dup 0)
2908 (const_int 0)))]
2909 "")
2910
2911 ;; Handle the PowerPC64 rlwinm corner case
2912
2913 (define_insn_and_split "*andsi3_internal6"
2914 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2915 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2916 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2917 "TARGET_POWERPC64"
2918 "#"
2919 "TARGET_POWERPC64"
2920 [(set (match_dup 0)
2921 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2922 (match_dup 4)))
2923 (set (match_dup 0)
2924 (rotate:SI (match_dup 0) (match_dup 5)))]
2925 "
2926 {
2927 int mb = extract_MB (operands[2]);
2928 int me = extract_ME (operands[2]);
2929 operands[3] = GEN_INT (me + 1);
2930 operands[5] = GEN_INT (32 - (me + 1));
2931 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2932 }"
2933 [(set_attr "length" "8")])
2934
2935 (define_expand "iorsi3"
2936 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2937 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2938 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2939 ""
2940 "
2941 {
2942 if (GET_CODE (operands[2]) == CONST_INT
2943 && ! logical_operand (operands[2], SImode))
2944 {
2945 HOST_WIDE_INT value = INTVAL (operands[2]);
2946 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2947 ? operands[0] : gen_reg_rtx (SImode));
2948
2949 emit_insn (gen_iorsi3 (tmp, operands[1],
2950 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2951 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2952 DONE;
2953 }
2954 }")
2955
2956 (define_expand "xorsi3"
2957 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2958 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2959 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2960 ""
2961 "
2962 {
2963 if (GET_CODE (operands[2]) == CONST_INT
2964 && ! logical_operand (operands[2], SImode))
2965 {
2966 HOST_WIDE_INT value = INTVAL (operands[2]);
2967 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2968 ? operands[0] : gen_reg_rtx (SImode));
2969
2970 emit_insn (gen_xorsi3 (tmp, operands[1],
2971 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2972 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2973 DONE;
2974 }
2975 }")
2976
2977 (define_insn "*boolsi3_internal1"
2978 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2979 (match_operator:SI 3 "boolean_or_operator"
2980 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2981 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2982 ""
2983 "@
2984 %q3 %0,%1,%2
2985 {%q3il|%q3i} %0,%1,%b2
2986 {%q3iu|%q3is} %0,%1,%u2")
2987
2988 (define_insn "*boolsi3_internal2"
2989 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2990 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2991 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2992 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2993 (const_int 0)))
2994 (clobber (match_scratch:SI 3 "=r,r"))]
2995 "TARGET_32BIT"
2996 "@
2997 %q4. %3,%1,%2
2998 #"
2999 [(set_attr "type" "compare")
3000 (set_attr "length" "4,8")])
3001
3002 (define_split
3003 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3004 (compare:CC (match_operator:SI 4 "boolean_operator"
3005 [(match_operand:SI 1 "gpc_reg_operand" "")
3006 (match_operand:SI 2 "gpc_reg_operand" "")])
3007 (const_int 0)))
3008 (clobber (match_scratch:SI 3 ""))]
3009 "TARGET_32BIT && reload_completed"
3010 [(set (match_dup 3) (match_dup 4))
3011 (set (match_dup 0)
3012 (compare:CC (match_dup 3)
3013 (const_int 0)))]
3014 "")
3015
3016 (define_insn "*boolsi3_internal3"
3017 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3018 (compare:CC (match_operator:SI 4 "boolean_operator"
3019 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3020 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3021 (const_int 0)))
3022 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3023 (match_dup 4))]
3024 "TARGET_32BIT"
3025 "@
3026 %q4. %0,%1,%2
3027 #"
3028 [(set_attr "type" "compare")
3029 (set_attr "length" "4,8")])
3030
3031 (define_split
3032 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3033 (compare:CC (match_operator:SI 4 "boolean_operator"
3034 [(match_operand:SI 1 "gpc_reg_operand" "")
3035 (match_operand:SI 2 "gpc_reg_operand" "")])
3036 (const_int 0)))
3037 (set (match_operand:SI 0 "gpc_reg_operand" "")
3038 (match_dup 4))]
3039 "TARGET_32BIT && reload_completed"
3040 [(set (match_dup 0) (match_dup 4))
3041 (set (match_dup 3)
3042 (compare:CC (match_dup 0)
3043 (const_int 0)))]
3044 "")
3045
3046 ;; Split a logical operation that we can't do in one insn into two insns,
3047 ;; each of which does one 16-bit part. This is used by combine.
3048
3049 (define_split
3050 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3051 (match_operator:SI 3 "boolean_or_operator"
3052 [(match_operand:SI 1 "gpc_reg_operand" "")
3053 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3054 ""
3055 [(set (match_dup 0) (match_dup 4))
3056 (set (match_dup 0) (match_dup 5))]
3057 "
3058 {
3059 rtx i;
3060 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3061 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3062 operands[1], i);
3063 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3064 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3065 operands[0], i);
3066 }")
3067
3068 (define_insn "*boolcsi3_internal1"
3069 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3070 (match_operator:SI 3 "boolean_operator"
3071 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3072 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3073 ""
3074 "%q3 %0,%2,%1")
3075
3076 (define_insn "*boolcsi3_internal2"
3077 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3078 (compare:CC (match_operator:SI 4 "boolean_operator"
3079 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3080 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3081 (const_int 0)))
3082 (clobber (match_scratch:SI 3 "=r,r"))]
3083 "TARGET_32BIT"
3084 "@
3085 %q4. %3,%2,%1
3086 #"
3087 [(set_attr "type" "compare")
3088 (set_attr "length" "4,8")])
3089
3090 (define_split
3091 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3092 (compare:CC (match_operator:SI 4 "boolean_operator"
3093 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3094 (match_operand:SI 2 "gpc_reg_operand" "")])
3095 (const_int 0)))
3096 (clobber (match_scratch:SI 3 ""))]
3097 "TARGET_32BIT && reload_completed"
3098 [(set (match_dup 3) (match_dup 4))
3099 (set (match_dup 0)
3100 (compare:CC (match_dup 3)
3101 (const_int 0)))]
3102 "")
3103
3104 (define_insn "*boolcsi3_internal3"
3105 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3106 (compare:CC (match_operator:SI 4 "boolean_operator"
3107 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3108 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3109 (const_int 0)))
3110 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3111 (match_dup 4))]
3112 "TARGET_32BIT"
3113 "@
3114 %q4. %0,%2,%1
3115 #"
3116 [(set_attr "type" "compare")
3117 (set_attr "length" "4,8")])
3118
3119 (define_split
3120 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3121 (compare:CC (match_operator:SI 4 "boolean_operator"
3122 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3123 (match_operand:SI 2 "gpc_reg_operand" "")])
3124 (const_int 0)))
3125 (set (match_operand:SI 0 "gpc_reg_operand" "")
3126 (match_dup 4))]
3127 "TARGET_32BIT && reload_completed"
3128 [(set (match_dup 0) (match_dup 4))
3129 (set (match_dup 3)
3130 (compare:CC (match_dup 0)
3131 (const_int 0)))]
3132 "")
3133
3134 (define_insn "*boolccsi3_internal1"
3135 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3136 (match_operator:SI 3 "boolean_operator"
3137 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3138 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3139 ""
3140 "%q3 %0,%1,%2")
3141
3142 (define_insn "*boolccsi3_internal2"
3143 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3144 (compare:CC (match_operator:SI 4 "boolean_operator"
3145 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3146 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3147 (const_int 0)))
3148 (clobber (match_scratch:SI 3 "=r,r"))]
3149 "TARGET_32BIT"
3150 "@
3151 %q4. %3,%1,%2
3152 #"
3153 [(set_attr "type" "compare")
3154 (set_attr "length" "4,8")])
3155
3156 (define_split
3157 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3158 (compare:CC (match_operator:SI 4 "boolean_operator"
3159 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3160 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3161 (const_int 0)))
3162 (clobber (match_scratch:SI 3 ""))]
3163 "TARGET_32BIT && reload_completed"
3164 [(set (match_dup 3) (match_dup 4))
3165 (set (match_dup 0)
3166 (compare:CC (match_dup 3)
3167 (const_int 0)))]
3168 "")
3169
3170 (define_insn "*boolccsi3_internal3"
3171 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3172 (compare:CC (match_operator:SI 4 "boolean_operator"
3173 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3174 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3175 (const_int 0)))
3176 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3177 (match_dup 4))]
3178 "TARGET_32BIT"
3179 "@
3180 %q4. %0,%1,%2
3181 #"
3182 [(set_attr "type" "compare")
3183 (set_attr "length" "4,8")])
3184
3185 (define_split
3186 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3187 (compare:CC (match_operator:SI 4 "boolean_operator"
3188 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3189 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3190 (const_int 0)))
3191 (set (match_operand:SI 0 "gpc_reg_operand" "")
3192 (match_dup 4))]
3193 "TARGET_32BIT && reload_completed"
3194 [(set (match_dup 0) (match_dup 4))
3195 (set (match_dup 3)
3196 (compare:CC (match_dup 0)
3197 (const_int 0)))]
3198 "")
3199
3200 ;; maskir insn. We need four forms because things might be in arbitrary
3201 ;; orders. Don't define forms that only set CR fields because these
3202 ;; would modify an input register.
3203
3204 (define_insn "*maskir_internal1"
3205 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3206 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3207 (match_operand:SI 1 "gpc_reg_operand" "0"))
3208 (and:SI (match_dup 2)
3209 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3210 "TARGET_POWER"
3211 "maskir %0,%3,%2")
3212
3213 (define_insn "*maskir_internal2"
3214 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3215 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3216 (match_operand:SI 1 "gpc_reg_operand" "0"))
3217 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3218 (match_dup 2))))]
3219 "TARGET_POWER"
3220 "maskir %0,%3,%2")
3221
3222 (define_insn "*maskir_internal3"
3223 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3224 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3225 (match_operand:SI 3 "gpc_reg_operand" "r"))
3226 (and:SI (not:SI (match_dup 2))
3227 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3228 "TARGET_POWER"
3229 "maskir %0,%3,%2")
3230
3231 (define_insn "*maskir_internal4"
3232 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3233 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3234 (match_operand:SI 2 "gpc_reg_operand" "r"))
3235 (and:SI (not:SI (match_dup 2))
3236 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3237 "TARGET_POWER"
3238 "maskir %0,%3,%2")
3239
3240 (define_insn "*maskir_internal5"
3241 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3242 (compare:CC
3243 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3244 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3245 (and:SI (match_dup 2)
3246 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3247 (const_int 0)))
3248 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3249 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3250 (and:SI (match_dup 2) (match_dup 3))))]
3251 "TARGET_POWER"
3252 "@
3253 maskir. %0,%3,%2
3254 #"
3255 [(set_attr "type" "compare")
3256 (set_attr "length" "4,8")])
3257
3258 (define_split
3259 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3260 (compare:CC
3261 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3262 (match_operand:SI 1 "gpc_reg_operand" ""))
3263 (and:SI (match_dup 2)
3264 (match_operand:SI 3 "gpc_reg_operand" "")))
3265 (const_int 0)))
3266 (set (match_operand:SI 0 "gpc_reg_operand" "")
3267 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3268 (and:SI (match_dup 2) (match_dup 3))))]
3269 "TARGET_POWER && reload_completed"
3270 [(set (match_dup 0)
3271 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3272 (and:SI (match_dup 2) (match_dup 3))))
3273 (set (match_dup 4)
3274 (compare:CC (match_dup 0)
3275 (const_int 0)))]
3276 "")
3277
3278 (define_insn "*maskir_internal6"
3279 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3280 (compare:CC
3281 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3282 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3283 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3284 (match_dup 2)))
3285 (const_int 0)))
3286 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3287 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3288 (and:SI (match_dup 3) (match_dup 2))))]
3289 "TARGET_POWER"
3290 "@
3291 maskir. %0,%3,%2
3292 #"
3293 [(set_attr "type" "compare")
3294 (set_attr "length" "4,8")])
3295
3296 (define_split
3297 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3298 (compare:CC
3299 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3300 (match_operand:SI 1 "gpc_reg_operand" ""))
3301 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3302 (match_dup 2)))
3303 (const_int 0)))
3304 (set (match_operand:SI 0 "gpc_reg_operand" "")
3305 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3306 (and:SI (match_dup 3) (match_dup 2))))]
3307 "TARGET_POWER && reload_completed"
3308 [(set (match_dup 0)
3309 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3310 (and:SI (match_dup 3) (match_dup 2))))
3311 (set (match_dup 4)
3312 (compare:CC (match_dup 0)
3313 (const_int 0)))]
3314 "")
3315
3316 (define_insn "*maskir_internal7"
3317 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3318 (compare:CC
3319 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3320 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3321 (and:SI (not:SI (match_dup 2))
3322 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3323 (const_int 0)))
3324 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3325 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3326 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3327 "TARGET_POWER"
3328 "@
3329 maskir. %0,%3,%2
3330 #"
3331 [(set_attr "type" "compare")
3332 (set_attr "length" "4,8")])
3333
3334 (define_split
3335 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3336 (compare:CC
3337 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3338 (match_operand:SI 3 "gpc_reg_operand" ""))
3339 (and:SI (not:SI (match_dup 2))
3340 (match_operand:SI 1 "gpc_reg_operand" "")))
3341 (const_int 0)))
3342 (set (match_operand:SI 0 "gpc_reg_operand" "")
3343 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3344 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3345 "TARGET_POWER && reload_completed"
3346 [(set (match_dup 0)
3347 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3348 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3349 (set (match_dup 4)
3350 (compare:CC (match_dup 0)
3351 (const_int 0)))]
3352 "")
3353
3354 (define_insn "*maskir_internal8"
3355 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3356 (compare:CC
3357 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3358 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3359 (and:SI (not:SI (match_dup 2))
3360 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3361 (const_int 0)))
3362 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3363 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3364 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3365 "TARGET_POWER"
3366 "@
3367 maskir. %0,%3,%2
3368 #"
3369 [(set_attr "type" "compare")
3370 (set_attr "length" "4,8")])
3371
3372 (define_split
3373 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3374 (compare:CC
3375 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3376 (match_operand:SI 2 "gpc_reg_operand" ""))
3377 (and:SI (not:SI (match_dup 2))
3378 (match_operand:SI 1 "gpc_reg_operand" "")))
3379 (const_int 0)))
3380 (set (match_operand:SI 0 "gpc_reg_operand" "")
3381 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3382 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3383 "TARGET_POWER && reload_completed"
3384 [(set (match_dup 0)
3385 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3386 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3387 (set (match_dup 4)
3388 (compare:CC (match_dup 0)
3389 (const_int 0)))]
3390 "")
3391 \f
3392 ;; Rotate and shift insns, in all their variants. These support shifts,
3393 ;; field inserts and extracts, and various combinations thereof.
3394 (define_expand "insv"
3395 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3396 (match_operand:SI 1 "const_int_operand" "")
3397 (match_operand:SI 2 "const_int_operand" ""))
3398 (match_operand 3 "gpc_reg_operand" ""))]
3399 ""
3400 "
3401 {
3402 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3403 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3404 compiler if the address of the structure is taken later. */
3405 if (GET_CODE (operands[0]) == SUBREG
3406 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3407 FAIL;
3408
3409 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3410 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3411 else
3412 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3413 DONE;
3414 }")
3415
3416 (define_insn "insvsi"
3417 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3418 (match_operand:SI 1 "const_int_operand" "i")
3419 (match_operand:SI 2 "const_int_operand" "i"))
3420 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3421 ""
3422 "*
3423 {
3424 int start = INTVAL (operands[2]) & 31;
3425 int size = INTVAL (operands[1]) & 31;
3426
3427 operands[4] = GEN_INT (32 - start - size);
3428 operands[1] = GEN_INT (start + size - 1);
3429 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3430 }"
3431 [(set_attr "type" "insert_word")])
3432
3433 (define_insn "*insvsi_internal1"
3434 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3435 (match_operand:SI 1 "const_int_operand" "i")
3436 (match_operand:SI 2 "const_int_operand" "i"))
3437 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3438 (match_operand:SI 4 "const_int_operand" "i")))]
3439 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3440 "*
3441 {
3442 int shift = INTVAL (operands[4]) & 31;
3443 int start = INTVAL (operands[2]) & 31;
3444 int size = INTVAL (operands[1]) & 31;
3445
3446 operands[4] = GEN_INT (shift - start - size);
3447 operands[1] = GEN_INT (start + size - 1);
3448 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3449 }"
3450 [(set_attr "type" "insert_word")])
3451
3452 (define_insn "*insvsi_internal2"
3453 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3454 (match_operand:SI 1 "const_int_operand" "i")
3455 (match_operand:SI 2 "const_int_operand" "i"))
3456 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3457 (match_operand:SI 4 "const_int_operand" "i")))]
3458 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3459 "*
3460 {
3461 int shift = INTVAL (operands[4]) & 31;
3462 int start = INTVAL (operands[2]) & 31;
3463 int size = INTVAL (operands[1]) & 31;
3464
3465 operands[4] = GEN_INT (32 - shift - start - size);
3466 operands[1] = GEN_INT (start + size - 1);
3467 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3468 }"
3469 [(set_attr "type" "insert_word")])
3470
3471 (define_insn "*insvsi_internal3"
3472 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3473 (match_operand:SI 1 "const_int_operand" "i")
3474 (match_operand:SI 2 "const_int_operand" "i"))
3475 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3476 (match_operand:SI 4 "const_int_operand" "i")))]
3477 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3478 "*
3479 {
3480 int shift = INTVAL (operands[4]) & 31;
3481 int start = INTVAL (operands[2]) & 31;
3482 int size = INTVAL (operands[1]) & 31;
3483
3484 operands[4] = GEN_INT (32 - shift - start - size);
3485 operands[1] = GEN_INT (start + size - 1);
3486 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3487 }"
3488 [(set_attr "type" "insert_word")])
3489
3490 (define_insn "*insvsi_internal4"
3491 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3492 (match_operand:SI 1 "const_int_operand" "i")
3493 (match_operand:SI 2 "const_int_operand" "i"))
3494 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3495 (match_operand:SI 4 "const_int_operand" "i")
3496 (match_operand:SI 5 "const_int_operand" "i")))]
3497 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3498 "*
3499 {
3500 int extract_start = INTVAL (operands[5]) & 31;
3501 int extract_size = INTVAL (operands[4]) & 31;
3502 int insert_start = INTVAL (operands[2]) & 31;
3503 int insert_size = INTVAL (operands[1]) & 31;
3504
3505 /* Align extract field with insert field */
3506 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3507 operands[1] = GEN_INT (insert_start + insert_size - 1);
3508 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3509 }"
3510 [(set_attr "type" "insert_word")])
3511
3512 ;; combine patterns for rlwimi
3513 (define_insn "*insvsi_internal5"
3514 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3515 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3516 (match_operand:SI 1 "mask_operand" "i"))
3517 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3518 (match_operand:SI 2 "const_int_operand" "i"))
3519 (match_operand:SI 5 "mask_operand" "i"))))]
3520 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3521 "*
3522 {
3523 int me = extract_ME(operands[5]);
3524 int mb = extract_MB(operands[5]);
3525 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3526 operands[2] = GEN_INT(mb);
3527 operands[1] = GEN_INT(me);
3528 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3529 }"
3530 [(set_attr "type" "insert_word")])
3531
3532 (define_insn "*insvsi_internal6"
3533 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3534 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3535 (match_operand:SI 2 "const_int_operand" "i"))
3536 (match_operand:SI 5 "mask_operand" "i"))
3537 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3538 (match_operand:SI 1 "mask_operand" "i"))))]
3539 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3540 "*
3541 {
3542 int me = extract_ME(operands[5]);
3543 int mb = extract_MB(operands[5]);
3544 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3545 operands[2] = GEN_INT(mb);
3546 operands[1] = GEN_INT(me);
3547 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3548 }"
3549 [(set_attr "type" "insert_word")])
3550
3551 (define_insn "insvdi"
3552 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3553 (match_operand:SI 1 "const_int_operand" "i")
3554 (match_operand:SI 2 "const_int_operand" "i"))
3555 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3556 "TARGET_POWERPC64"
3557 "*
3558 {
3559 int start = INTVAL (operands[2]) & 63;
3560 int size = INTVAL (operands[1]) & 63;
3561
3562 operands[1] = GEN_INT (64 - start - size);
3563 return \"rldimi %0,%3,%H1,%H2\";
3564 }"
3565 [(set_attr "type" "insert_dword")])
3566
3567 (define_insn "*insvdi_internal2"
3568 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3569 (match_operand:SI 1 "const_int_operand" "i")
3570 (match_operand:SI 2 "const_int_operand" "i"))
3571 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3572 (match_operand:SI 4 "const_int_operand" "i")))]
3573 "TARGET_POWERPC64
3574 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3575 "*
3576 {
3577 int shift = INTVAL (operands[4]) & 63;
3578 int start = (INTVAL (operands[2]) & 63) - 32;
3579 int size = INTVAL (operands[1]) & 63;
3580
3581 operands[4] = GEN_INT (64 - shift - start - size);
3582 operands[2] = GEN_INT (start);
3583 operands[1] = GEN_INT (start + size - 1);
3584 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3585 }")
3586
3587 (define_insn "*insvdi_internal3"
3588 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3589 (match_operand:SI 1 "const_int_operand" "i")
3590 (match_operand:SI 2 "const_int_operand" "i"))
3591 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3592 (match_operand:SI 4 "const_int_operand" "i")))]
3593 "TARGET_POWERPC64
3594 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3595 "*
3596 {
3597 int shift = INTVAL (operands[4]) & 63;
3598 int start = (INTVAL (operands[2]) & 63) - 32;
3599 int size = INTVAL (operands[1]) & 63;
3600
3601 operands[4] = GEN_INT (64 - shift - start - size);
3602 operands[2] = GEN_INT (start);
3603 operands[1] = GEN_INT (start + size - 1);
3604 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3605 }")
3606
3607 (define_expand "extzv"
3608 [(set (match_operand 0 "gpc_reg_operand" "")
3609 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3610 (match_operand:SI 2 "const_int_operand" "")
3611 (match_operand:SI 3 "const_int_operand" "")))]
3612 ""
3613 "
3614 {
3615 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3616 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3617 compiler if the address of the structure is taken later. */
3618 if (GET_CODE (operands[0]) == SUBREG
3619 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3620 FAIL;
3621
3622 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3623 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3624 else
3625 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3626 DONE;
3627 }")
3628
3629 (define_insn "extzvsi"
3630 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3631 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3632 (match_operand:SI 2 "const_int_operand" "i")
3633 (match_operand:SI 3 "const_int_operand" "i")))]
3634 ""
3635 "*
3636 {
3637 int start = INTVAL (operands[3]) & 31;
3638 int size = INTVAL (operands[2]) & 31;
3639
3640 if (start + size >= 32)
3641 operands[3] = const0_rtx;
3642 else
3643 operands[3] = GEN_INT (start + size);
3644 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3645 }")
3646
3647 (define_insn "*extzvsi_internal1"
3648 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3649 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3650 (match_operand:SI 2 "const_int_operand" "i,i")
3651 (match_operand:SI 3 "const_int_operand" "i,i"))
3652 (const_int 0)))
3653 (clobber (match_scratch:SI 4 "=r,r"))]
3654 ""
3655 "*
3656 {
3657 int start = INTVAL (operands[3]) & 31;
3658 int size = INTVAL (operands[2]) & 31;
3659
3660 /* Force split for non-cc0 compare. */
3661 if (which_alternative == 1)
3662 return \"#\";
3663
3664 /* If the bit-field being tested fits in the upper or lower half of a
3665 word, it is possible to use andiu. or andil. to test it. This is
3666 useful because the condition register set-use delay is smaller for
3667 andi[ul]. than for rlinm. This doesn't work when the starting bit
3668 position is 0 because the LT and GT bits may be set wrong. */
3669
3670 if ((start > 0 && start + size <= 16) || start >= 16)
3671 {
3672 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3673 - (1 << (16 - (start & 15) - size))));
3674 if (start < 16)
3675 return \"{andiu.|andis.} %4,%1,%3\";
3676 else
3677 return \"{andil.|andi.} %4,%1,%3\";
3678 }
3679
3680 if (start + size >= 32)
3681 operands[3] = const0_rtx;
3682 else
3683 operands[3] = GEN_INT (start + size);
3684 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3685 }"
3686 [(set_attr "type" "delayed_compare")
3687 (set_attr "length" "4,8")])
3688
3689 (define_split
3690 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3691 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3692 (match_operand:SI 2 "const_int_operand" "")
3693 (match_operand:SI 3 "const_int_operand" ""))
3694 (const_int 0)))
3695 (clobber (match_scratch:SI 4 ""))]
3696 "reload_completed"
3697 [(set (match_dup 4)
3698 (zero_extract:SI (match_dup 1) (match_dup 2)
3699 (match_dup 3)))
3700 (set (match_dup 0)
3701 (compare:CC (match_dup 4)
3702 (const_int 0)))]
3703 "")
3704
3705 (define_insn "*extzvsi_internal2"
3706 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3707 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3708 (match_operand:SI 2 "const_int_operand" "i,i")
3709 (match_operand:SI 3 "const_int_operand" "i,i"))
3710 (const_int 0)))
3711 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3712 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3713 ""
3714 "*
3715 {
3716 int start = INTVAL (operands[3]) & 31;
3717 int size = INTVAL (operands[2]) & 31;
3718
3719 /* Force split for non-cc0 compare. */
3720 if (which_alternative == 1)
3721 return \"#\";
3722
3723 /* Since we are using the output value, we can't ignore any need for
3724 a shift. The bit-field must end at the LSB. */
3725 if (start >= 16 && start + size == 32)
3726 {
3727 operands[3] = GEN_INT ((1 << size) - 1);
3728 return \"{andil.|andi.} %0,%1,%3\";
3729 }
3730
3731 if (start + size >= 32)
3732 operands[3] = const0_rtx;
3733 else
3734 operands[3] = GEN_INT (start + size);
3735 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3736 }"
3737 [(set_attr "type" "delayed_compare")
3738 (set_attr "length" "4,8")])
3739
3740 (define_split
3741 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3742 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3743 (match_operand:SI 2 "const_int_operand" "")
3744 (match_operand:SI 3 "const_int_operand" ""))
3745 (const_int 0)))
3746 (set (match_operand:SI 0 "gpc_reg_operand" "")
3747 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3748 "reload_completed"
3749 [(set (match_dup 0)
3750 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3751 (set (match_dup 4)
3752 (compare:CC (match_dup 0)
3753 (const_int 0)))]
3754 "")
3755
3756 (define_insn "extzvdi"
3757 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3758 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3759 (match_operand:SI 2 "const_int_operand" "i")
3760 (match_operand:SI 3 "const_int_operand" "i")))]
3761 "TARGET_POWERPC64"
3762 "*
3763 {
3764 int start = INTVAL (operands[3]) & 63;
3765 int size = INTVAL (operands[2]) & 63;
3766
3767 if (start + size >= 64)
3768 operands[3] = const0_rtx;
3769 else
3770 operands[3] = GEN_INT (start + size);
3771 operands[2] = GEN_INT (64 - size);
3772 return \"rldicl %0,%1,%3,%2\";
3773 }")
3774
3775 (define_insn "*extzvdi_internal1"
3776 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3777 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3778 (match_operand:SI 2 "const_int_operand" "i")
3779 (match_operand:SI 3 "const_int_operand" "i"))
3780 (const_int 0)))
3781 (clobber (match_scratch:DI 4 "=r"))]
3782 "TARGET_64BIT"
3783 "*
3784 {
3785 int start = INTVAL (operands[3]) & 63;
3786 int size = INTVAL (operands[2]) & 63;
3787
3788 if (start + size >= 64)
3789 operands[3] = const0_rtx;
3790 else
3791 operands[3] = GEN_INT (start + size);
3792 operands[2] = GEN_INT (64 - size);
3793 return \"rldicl. %4,%1,%3,%2\";
3794 }"
3795 [(set_attr "type" "compare")])
3796
3797 (define_insn "*extzvdi_internal2"
3798 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3799 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3800 (match_operand:SI 2 "const_int_operand" "i")
3801 (match_operand:SI 3 "const_int_operand" "i"))
3802 (const_int 0)))
3803 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3804 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3805 "TARGET_64BIT"
3806 "*
3807 {
3808 int start = INTVAL (operands[3]) & 63;
3809 int size = INTVAL (operands[2]) & 63;
3810
3811 if (start + size >= 64)
3812 operands[3] = const0_rtx;
3813 else
3814 operands[3] = GEN_INT (start + size);
3815 operands[2] = GEN_INT (64 - size);
3816 return \"rldicl. %0,%1,%3,%2\";
3817 }"
3818 [(set_attr "type" "compare")])
3819
3820 (define_insn "rotlsi3"
3821 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3822 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3823 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
3824 ""
3825 "@
3826 {rlnm|rlwnm} %0,%1,%2,0xffffffff
3827 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
3828 [(set_attr "type" "var_shift_rotate,integer")])
3829
3830 (define_insn "*rotlsi3_internal2"
3831 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3832 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3833 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3834 (const_int 0)))
3835 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3836 ""
3837 "@
3838 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
3839 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
3840 #
3841 #"
3842 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3843 (set_attr "length" "4,4,8,8")])
3844
3845 (define_split
3846 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3847 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3848 (match_operand:SI 2 "reg_or_cint_operand" ""))
3849 (const_int 0)))
3850 (clobber (match_scratch:SI 3 ""))]
3851 "reload_completed"
3852 [(set (match_dup 3)
3853 (rotate:SI (match_dup 1) (match_dup 2)))
3854 (set (match_dup 0)
3855 (compare:CC (match_dup 3)
3856 (const_int 0)))]
3857 "")
3858
3859 (define_insn "*rotlsi3_internal3"
3860 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3861 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3862 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3863 (const_int 0)))
3864 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3865 (rotate:SI (match_dup 1) (match_dup 2)))]
3866 ""
3867 "@
3868 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
3869 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
3870 #
3871 #"
3872 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3873 (set_attr "length" "4,4,8,8")])
3874
3875 (define_split
3876 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3877 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3878 (match_operand:SI 2 "reg_or_cint_operand" ""))
3879 (const_int 0)))
3880 (set (match_operand:SI 0 "gpc_reg_operand" "")
3881 (rotate:SI (match_dup 1) (match_dup 2)))]
3882 "reload_completed"
3883 [(set (match_dup 0)
3884 (rotate:SI (match_dup 1) (match_dup 2)))
3885 (set (match_dup 3)
3886 (compare:CC (match_dup 0)
3887 (const_int 0)))]
3888 "")
3889
3890 (define_insn "*rotlsi3_internal4"
3891 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3892 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3893 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
3894 (match_operand:SI 3 "mask_operand" "n,n")))]
3895 ""
3896 "@
3897 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
3898 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
3899 [(set_attr "type" "var_shift_rotate,integer")])
3900
3901 (define_insn "*rotlsi3_internal5"
3902 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3903 (compare:CC (and:SI
3904 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3905 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3906 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3907 (const_int 0)))
3908 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
3909 ""
3910 "@
3911 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
3912 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3913 #
3914 #"
3915 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3916 (set_attr "length" "4,4,8,8")])
3917
3918 (define_split
3919 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3920 (compare:CC (and:SI
3921 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3922 (match_operand:SI 2 "reg_or_cint_operand" ""))
3923 (match_operand:SI 3 "mask_operand" ""))
3924 (const_int 0)))
3925 (clobber (match_scratch:SI 4 ""))]
3926 "reload_completed"
3927 [(set (match_dup 4)
3928 (and:SI (rotate:SI (match_dup 1)
3929 (match_dup 2))
3930 (match_dup 3)))
3931 (set (match_dup 0)
3932 (compare:CC (match_dup 4)
3933 (const_int 0)))]
3934 "")
3935
3936 (define_insn "*rotlsi3_internal6"
3937 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
3938 (compare:CC (and:SI
3939 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3940 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3941 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3942 (const_int 0)))
3943 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3944 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3945 ""
3946 "@
3947 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
3948 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3949 #
3950 #"
3951 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3952 (set_attr "length" "4,4,8,8")])
3953
3954 (define_split
3955 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3956 (compare:CC (and:SI
3957 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3958 (match_operand:SI 2 "reg_or_cint_operand" ""))
3959 (match_operand:SI 3 "mask_operand" ""))
3960 (const_int 0)))
3961 (set (match_operand:SI 0 "gpc_reg_operand" "")
3962 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3963 "reload_completed"
3964 [(set (match_dup 0)
3965 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3966 (set (match_dup 4)
3967 (compare:CC (match_dup 0)
3968 (const_int 0)))]
3969 "")
3970
3971 (define_insn "*rotlsi3_internal7"
3972 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3973 (zero_extend:SI
3974 (subreg:QI
3975 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3976 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3977 ""
3978 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3979
3980 (define_insn "*rotlsi3_internal8"
3981 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3982 (compare:CC (zero_extend:SI
3983 (subreg:QI
3984 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3985 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
3986 (const_int 0)))
3987 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3988 ""
3989 "@
3990 {rlnm.|rlwnm.} %3,%1,%2,0xff
3991 {rlinm.|rlwinm.} %3,%1,%h2,0xff
3992 #
3993 #"
3994 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3995 (set_attr "length" "4,4,8,8")])
3996
3997 (define_split
3998 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3999 (compare:CC (zero_extend:SI
4000 (subreg:QI
4001 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4002 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4003 (const_int 0)))
4004 (clobber (match_scratch:SI 3 ""))]
4005 "reload_completed"
4006 [(set (match_dup 3)
4007 (zero_extend:SI (subreg:QI
4008 (rotate:SI (match_dup 1)
4009 (match_dup 2)) 0)))
4010 (set (match_dup 0)
4011 (compare:CC (match_dup 3)
4012 (const_int 0)))]
4013 "")
4014
4015 (define_insn "*rotlsi3_internal9"
4016 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4017 (compare:CC (zero_extend:SI
4018 (subreg:QI
4019 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4020 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4021 (const_int 0)))
4022 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4023 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4024 ""
4025 "@
4026 {rlnm.|rlwnm.} %0,%1,%2,0xff
4027 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4028 #
4029 #"
4030 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4031 (set_attr "length" "4,4,8,8")])
4032
4033 (define_split
4034 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4035 (compare:CC (zero_extend:SI
4036 (subreg:QI
4037 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4038 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4039 (const_int 0)))
4040 (set (match_operand:SI 0 "gpc_reg_operand" "")
4041 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4042 "reload_completed"
4043 [(set (match_dup 0)
4044 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4045 (set (match_dup 3)
4046 (compare:CC (match_dup 0)
4047 (const_int 0)))]
4048 "")
4049
4050 (define_insn "*rotlsi3_internal10"
4051 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4052 (zero_extend:SI
4053 (subreg:HI
4054 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4055 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4056 ""
4057 "@
4058 {rlnm|rlwnm} %0,%1,%2,0xffff
4059 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4060 [(set_attr "type" "var_shift_rotate,integer")])
4061
4062
4063 (define_insn "*rotlsi3_internal11"
4064 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4065 (compare:CC (zero_extend:SI
4066 (subreg:HI
4067 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4068 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4069 (const_int 0)))
4070 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4071 ""
4072 "@
4073 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4074 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4075 #
4076 #"
4077 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4078 (set_attr "length" "4,4,8,8")])
4079
4080 (define_split
4081 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4082 (compare:CC (zero_extend:SI
4083 (subreg:HI
4084 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4085 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4086 (const_int 0)))
4087 (clobber (match_scratch:SI 3 ""))]
4088 "reload_completed"
4089 [(set (match_dup 3)
4090 (zero_extend:SI (subreg:HI
4091 (rotate:SI (match_dup 1)
4092 (match_dup 2)) 0)))
4093 (set (match_dup 0)
4094 (compare:CC (match_dup 3)
4095 (const_int 0)))]
4096 "")
4097
4098 (define_insn "*rotlsi3_internal12"
4099 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4100 (compare:CC (zero_extend:SI
4101 (subreg:HI
4102 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4103 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4104 (const_int 0)))
4105 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4106 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4107 ""
4108 "@
4109 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4110 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4111 #
4112 #"
4113 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4114 (set_attr "length" "4,4,8,8")])
4115
4116 (define_split
4117 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4118 (compare:CC (zero_extend:SI
4119 (subreg:HI
4120 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4121 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4122 (const_int 0)))
4123 (set (match_operand:SI 0 "gpc_reg_operand" "")
4124 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4125 "reload_completed"
4126 [(set (match_dup 0)
4127 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4128 (set (match_dup 3)
4129 (compare:CC (match_dup 0)
4130 (const_int 0)))]
4131 "")
4132
4133 ;; Note that we use "sle." instead of "sl." so that we can set
4134 ;; SHIFT_COUNT_TRUNCATED.
4135
4136 (define_expand "ashlsi3"
4137 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4138 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4139 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4140 ""
4141 "
4142 {
4143 if (TARGET_POWER)
4144 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4145 else
4146 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4147 DONE;
4148 }")
4149
4150 (define_insn "ashlsi3_power"
4151 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4152 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4153 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4154 (clobber (match_scratch:SI 3 "=q,X"))]
4155 "TARGET_POWER"
4156 "@
4157 sle %0,%1,%2
4158 {sli|slwi} %0,%1,%h2")
4159
4160 (define_insn "ashlsi3_no_power"
4161 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4162 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4163 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4164 "! TARGET_POWER"
4165 "@
4166 {sl|slw} %0,%1,%2
4167 {sli|slwi} %0,%1,%h2"
4168 [(set_attr "type" "var_shift_rotate,shift")])
4169
4170 (define_insn ""
4171 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4172 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4173 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4174 (const_int 0)))
4175 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4176 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4177 "TARGET_POWER"
4178 "@
4179 sle. %3,%1,%2
4180 {sli.|slwi.} %3,%1,%h2
4181 #
4182 #"
4183 [(set_attr "type" "delayed_compare")
4184 (set_attr "length" "4,4,8,8")])
4185
4186 (define_split
4187 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4188 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4189 (match_operand:SI 2 "reg_or_cint_operand" ""))
4190 (const_int 0)))
4191 (clobber (match_scratch:SI 3 ""))
4192 (clobber (match_scratch:SI 4 ""))]
4193 "TARGET_POWER && reload_completed"
4194 [(parallel [(set (match_dup 3)
4195 (ashift:SI (match_dup 1) (match_dup 2)))
4196 (clobber (match_dup 4))])
4197 (set (match_dup 0)
4198 (compare:CC (match_dup 3)
4199 (const_int 0)))]
4200 "")
4201
4202 (define_insn ""
4203 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4204 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4205 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4206 (const_int 0)))
4207 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4208 "! TARGET_POWER && TARGET_32BIT"
4209 "@
4210 {sl.|slw.} %3,%1,%2
4211 {sli.|slwi.} %3,%1,%h2
4212 #
4213 #"
4214 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4215 (set_attr "length" "4,4,8,8")])
4216
4217 (define_split
4218 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4219 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4220 (match_operand:SI 2 "reg_or_cint_operand" ""))
4221 (const_int 0)))
4222 (clobber (match_scratch:SI 3 ""))]
4223 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4224 [(set (match_dup 3)
4225 (ashift:SI (match_dup 1) (match_dup 2)))
4226 (set (match_dup 0)
4227 (compare:CC (match_dup 3)
4228 (const_int 0)))]
4229 "")
4230
4231 (define_insn ""
4232 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4233 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4234 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4235 (const_int 0)))
4236 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4237 (ashift:SI (match_dup 1) (match_dup 2)))
4238 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4239 "TARGET_POWER"
4240 "@
4241 sle. %0,%1,%2
4242 {sli.|slwi.} %0,%1,%h2
4243 #
4244 #"
4245 [(set_attr "type" "delayed_compare")
4246 (set_attr "length" "4,4,8,8")])
4247
4248 (define_split
4249 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4250 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4251 (match_operand:SI 2 "reg_or_cint_operand" ""))
4252 (const_int 0)))
4253 (set (match_operand:SI 0 "gpc_reg_operand" "")
4254 (ashift:SI (match_dup 1) (match_dup 2)))
4255 (clobber (match_scratch:SI 4 ""))]
4256 "TARGET_POWER && reload_completed"
4257 [(parallel [(set (match_dup 0)
4258 (ashift:SI (match_dup 1) (match_dup 2)))
4259 (clobber (match_dup 4))])
4260 (set (match_dup 3)
4261 (compare:CC (match_dup 0)
4262 (const_int 0)))]
4263 "")
4264
4265 (define_insn ""
4266 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4267 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4268 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4269 (const_int 0)))
4270 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4271 (ashift:SI (match_dup 1) (match_dup 2)))]
4272 "! TARGET_POWER && TARGET_32BIT"
4273 "@
4274 {sl.|slw.} %0,%1,%2
4275 {sli.|slwi.} %0,%1,%h2
4276 #
4277 #"
4278 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4279 (set_attr "length" "4,4,8,8")])
4280
4281 (define_split
4282 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4283 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4284 (match_operand:SI 2 "reg_or_cint_operand" ""))
4285 (const_int 0)))
4286 (set (match_operand:SI 0 "gpc_reg_operand" "")
4287 (ashift:SI (match_dup 1) (match_dup 2)))]
4288 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4289 [(set (match_dup 0)
4290 (ashift:SI (match_dup 1) (match_dup 2)))
4291 (set (match_dup 3)
4292 (compare:CC (match_dup 0)
4293 (const_int 0)))]
4294 "")
4295
4296 (define_insn "rlwinm"
4297 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4298 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4299 (match_operand:SI 2 "const_int_operand" "i"))
4300 (match_operand:SI 3 "mask_operand" "n")))]
4301 "includes_lshift_p (operands[2], operands[3])"
4302 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4303
4304 (define_insn ""
4305 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4306 (compare:CC
4307 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4308 (match_operand:SI 2 "const_int_operand" "i,i"))
4309 (match_operand:SI 3 "mask_operand" "n,n"))
4310 (const_int 0)))
4311 (clobber (match_scratch:SI 4 "=r,r"))]
4312 "includes_lshift_p (operands[2], operands[3])"
4313 "@
4314 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4315 #"
4316 [(set_attr "type" "delayed_compare")
4317 (set_attr "length" "4,8")])
4318
4319 (define_split
4320 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4321 (compare:CC
4322 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4323 (match_operand:SI 2 "const_int_operand" ""))
4324 (match_operand:SI 3 "mask_operand" ""))
4325 (const_int 0)))
4326 (clobber (match_scratch:SI 4 ""))]
4327 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4328 [(set (match_dup 4)
4329 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4330 (match_dup 3)))
4331 (set (match_dup 0)
4332 (compare:CC (match_dup 4)
4333 (const_int 0)))]
4334 "")
4335
4336 (define_insn ""
4337 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4338 (compare:CC
4339 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4340 (match_operand:SI 2 "const_int_operand" "i,i"))
4341 (match_operand:SI 3 "mask_operand" "n,n"))
4342 (const_int 0)))
4343 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4344 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4345 "includes_lshift_p (operands[2], operands[3])"
4346 "@
4347 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4348 #"
4349 [(set_attr "type" "delayed_compare")
4350 (set_attr "length" "4,8")])
4351
4352 (define_split
4353 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4354 (compare:CC
4355 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4356 (match_operand:SI 2 "const_int_operand" ""))
4357 (match_operand:SI 3 "mask_operand" ""))
4358 (const_int 0)))
4359 (set (match_operand:SI 0 "gpc_reg_operand" "")
4360 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4361 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4362 [(set (match_dup 0)
4363 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4364 (set (match_dup 4)
4365 (compare:CC (match_dup 0)
4366 (const_int 0)))]
4367 "")
4368
4369 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
4370 ;; "sli x,x,0".
4371 (define_expand "lshrsi3"
4372 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4373 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4374 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4375 ""
4376 "
4377 {
4378 if (TARGET_POWER)
4379 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4380 else
4381 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
4382 DONE;
4383 }")
4384
4385 (define_insn "lshrsi3_power"
4386 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4387 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4388 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4389 (clobber (match_scratch:SI 3 "=q,X,X"))]
4390 "TARGET_POWER"
4391 "@
4392 sre %0,%1,%2
4393 mr %0,%1
4394 {s%A2i|s%A2wi} %0,%1,%h2")
4395
4396 (define_insn "lshrsi3_no_power"
4397 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4398 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4399 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
4400 "! TARGET_POWER"
4401 "@
4402 mr %0,%1
4403 {sr|srw} %0,%1,%2
4404 {sri|srwi} %0,%1,%h2"
4405 [(set_attr "type" "integer,var_shift_rotate,shift")])
4406
4407 (define_insn ""
4408 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4409 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4410 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4411 (const_int 0)))
4412 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4413 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4414 "TARGET_POWER"
4415 "@
4416 sre. %3,%1,%2
4417 mr. %1,%1
4418 {s%A2i.|s%A2wi.} %3,%1,%h2
4419 #
4420 #
4421 #"
4422 [(set_attr "type" "delayed_compare")
4423 (set_attr "length" "4,4,4,8,8,8")])
4424
4425 (define_split
4426 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4427 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4428 (match_operand:SI 2 "reg_or_cint_operand" ""))
4429 (const_int 0)))
4430 (clobber (match_scratch:SI 3 ""))
4431 (clobber (match_scratch:SI 4 ""))]
4432 "TARGET_POWER && reload_completed"
4433 [(parallel [(set (match_dup 3)
4434 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4435 (clobber (match_dup 4))])
4436 (set (match_dup 0)
4437 (compare:CC (match_dup 3)
4438 (const_int 0)))]
4439 "")
4440
4441 (define_insn ""
4442 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4443 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4444 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4445 (const_int 0)))
4446 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4447 "! TARGET_POWER && TARGET_32BIT"
4448 "@
4449 mr. %1,%1
4450 {sr.|srw.} %3,%1,%2
4451 {sri.|srwi.} %3,%1,%h2
4452 #
4453 #
4454 #"
4455 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4456 (set_attr "length" "4,4,4,8,8,8")])
4457
4458 (define_split
4459 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4460 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4461 (match_operand:SI 2 "reg_or_cint_operand" ""))
4462 (const_int 0)))
4463 (clobber (match_scratch:SI 3 ""))]
4464 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4465 [(set (match_dup 3)
4466 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4467 (set (match_dup 0)
4468 (compare:CC (match_dup 3)
4469 (const_int 0)))]
4470 "")
4471
4472 (define_insn ""
4473 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4474 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4475 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4476 (const_int 0)))
4477 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4478 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4479 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4480 "TARGET_POWER"
4481 "@
4482 sre. %0,%1,%2
4483 mr. %0,%1
4484 {s%A2i.|s%A2wi.} %0,%1,%h2
4485 #
4486 #
4487 #"
4488 [(set_attr "type" "delayed_compare")
4489 (set_attr "length" "4,4,4,8,8,8")])
4490
4491 (define_split
4492 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4493 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4494 (match_operand:SI 2 "reg_or_cint_operand" ""))
4495 (const_int 0)))
4496 (set (match_operand:SI 0 "gpc_reg_operand" "")
4497 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4498 (clobber (match_scratch:SI 4 ""))]
4499 "TARGET_POWER && reload_completed"
4500 [(parallel [(set (match_dup 0)
4501 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4502 (clobber (match_dup 4))])
4503 (set (match_dup 3)
4504 (compare:CC (match_dup 0)
4505 (const_int 0)))]
4506 "")
4507
4508 (define_insn ""
4509 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4510 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4511 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4512 (const_int 0)))
4513 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4514 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4515 "! TARGET_POWER && TARGET_32BIT"
4516 "@
4517 mr. %0,%1
4518 {sr.|srw.} %0,%1,%2
4519 {sri.|srwi.} %0,%1,%h2
4520 #
4521 #
4522 #"
4523 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4524 (set_attr "length" "4,4,4,8,8,8")])
4525
4526 (define_split
4527 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4528 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4529 (match_operand:SI 2 "reg_or_cint_operand" ""))
4530 (const_int 0)))
4531 (set (match_operand:SI 0 "gpc_reg_operand" "")
4532 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4533 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4534 [(set (match_dup 0)
4535 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4536 (set (match_dup 3)
4537 (compare:CC (match_dup 0)
4538 (const_int 0)))]
4539 "")
4540
4541 (define_insn ""
4542 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4543 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4544 (match_operand:SI 2 "const_int_operand" "i"))
4545 (match_operand:SI 3 "mask_operand" "n")))]
4546 "includes_rshift_p (operands[2], operands[3])"
4547 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4548
4549 (define_insn ""
4550 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4551 (compare:CC
4552 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4553 (match_operand:SI 2 "const_int_operand" "i,i"))
4554 (match_operand:SI 3 "mask_operand" "n,n"))
4555 (const_int 0)))
4556 (clobber (match_scratch:SI 4 "=r,r"))]
4557 "includes_rshift_p (operands[2], operands[3])"
4558 "@
4559 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4560 #"
4561 [(set_attr "type" "delayed_compare")
4562 (set_attr "length" "4,8")])
4563
4564 (define_split
4565 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4566 (compare:CC
4567 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4568 (match_operand:SI 2 "const_int_operand" ""))
4569 (match_operand:SI 3 "mask_operand" ""))
4570 (const_int 0)))
4571 (clobber (match_scratch:SI 4 ""))]
4572 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4573 [(set (match_dup 4)
4574 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4575 (match_dup 3)))
4576 (set (match_dup 0)
4577 (compare:CC (match_dup 4)
4578 (const_int 0)))]
4579 "")
4580
4581 (define_insn ""
4582 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4583 (compare:CC
4584 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4585 (match_operand:SI 2 "const_int_operand" "i,i"))
4586 (match_operand:SI 3 "mask_operand" "n,n"))
4587 (const_int 0)))
4588 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4589 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4590 "includes_rshift_p (operands[2], operands[3])"
4591 "@
4592 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4593 #"
4594 [(set_attr "type" "delayed_compare")
4595 (set_attr "length" "4,8")])
4596
4597 (define_split
4598 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4599 (compare:CC
4600 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4601 (match_operand:SI 2 "const_int_operand" ""))
4602 (match_operand:SI 3 "mask_operand" ""))
4603 (const_int 0)))
4604 (set (match_operand:SI 0 "gpc_reg_operand" "")
4605 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4606 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4607 [(set (match_dup 0)
4608 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4609 (set (match_dup 4)
4610 (compare:CC (match_dup 0)
4611 (const_int 0)))]
4612 "")
4613
4614 (define_insn ""
4615 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4616 (zero_extend:SI
4617 (subreg:QI
4618 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4619 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4620 "includes_rshift_p (operands[2], GEN_INT (255))"
4621 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4622
4623 (define_insn ""
4624 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4625 (compare:CC
4626 (zero_extend:SI
4627 (subreg:QI
4628 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4629 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4630 (const_int 0)))
4631 (clobber (match_scratch:SI 3 "=r,r"))]
4632 "includes_rshift_p (operands[2], GEN_INT (255))"
4633 "@
4634 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4635 #"
4636 [(set_attr "type" "delayed_compare")
4637 (set_attr "length" "4,8")])
4638
4639 (define_split
4640 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4641 (compare:CC
4642 (zero_extend:SI
4643 (subreg:QI
4644 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4645 (match_operand:SI 2 "const_int_operand" "")) 0))
4646 (const_int 0)))
4647 (clobber (match_scratch:SI 3 ""))]
4648 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4649 [(set (match_dup 3)
4650 (zero_extend:SI (subreg:QI
4651 (lshiftrt:SI (match_dup 1)
4652 (match_dup 2)) 0)))
4653 (set (match_dup 0)
4654 (compare:CC (match_dup 3)
4655 (const_int 0)))]
4656 "")
4657
4658 (define_insn ""
4659 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4660 (compare:CC
4661 (zero_extend:SI
4662 (subreg:QI
4663 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4664 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4665 (const_int 0)))
4666 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4667 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4668 "includes_rshift_p (operands[2], GEN_INT (255))"
4669 "@
4670 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4671 #"
4672 [(set_attr "type" "delayed_compare")
4673 (set_attr "length" "4,8")])
4674
4675 (define_split
4676 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4677 (compare:CC
4678 (zero_extend:SI
4679 (subreg:QI
4680 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4681 (match_operand:SI 2 "const_int_operand" "")) 0))
4682 (const_int 0)))
4683 (set (match_operand:SI 0 "gpc_reg_operand" "")
4684 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4685 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4686 [(set (match_dup 0)
4687 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4688 (set (match_dup 3)
4689 (compare:CC (match_dup 0)
4690 (const_int 0)))]
4691 "")
4692
4693 (define_insn ""
4694 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4695 (zero_extend:SI
4696 (subreg:HI
4697 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4698 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4699 "includes_rshift_p (operands[2], GEN_INT (65535))"
4700 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4701
4702 (define_insn ""
4703 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4704 (compare:CC
4705 (zero_extend:SI
4706 (subreg:HI
4707 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4708 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4709 (const_int 0)))
4710 (clobber (match_scratch:SI 3 "=r,r"))]
4711 "includes_rshift_p (operands[2], GEN_INT (65535))"
4712 "@
4713 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4714 #"
4715 [(set_attr "type" "delayed_compare")
4716 (set_attr "length" "4,8")])
4717
4718 (define_split
4719 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4720 (compare:CC
4721 (zero_extend:SI
4722 (subreg:HI
4723 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4724 (match_operand:SI 2 "const_int_operand" "")) 0))
4725 (const_int 0)))
4726 (clobber (match_scratch:SI 3 ""))]
4727 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4728 [(set (match_dup 3)
4729 (zero_extend:SI (subreg:HI
4730 (lshiftrt:SI (match_dup 1)
4731 (match_dup 2)) 0)))
4732 (set (match_dup 0)
4733 (compare:CC (match_dup 3)
4734 (const_int 0)))]
4735 "")
4736
4737 (define_insn ""
4738 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4739 (compare:CC
4740 (zero_extend:SI
4741 (subreg:HI
4742 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4743 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4744 (const_int 0)))
4745 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4746 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4747 "includes_rshift_p (operands[2], GEN_INT (65535))"
4748 "@
4749 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4750 #"
4751 [(set_attr "type" "delayed_compare")
4752 (set_attr "length" "4,8")])
4753
4754 (define_split
4755 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4756 (compare:CC
4757 (zero_extend:SI
4758 (subreg:HI
4759 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4760 (match_operand:SI 2 "const_int_operand" "")) 0))
4761 (const_int 0)))
4762 (set (match_operand:SI 0 "gpc_reg_operand" "")
4763 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4764 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4765 [(set (match_dup 0)
4766 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4767 (set (match_dup 3)
4768 (compare:CC (match_dup 0)
4769 (const_int 0)))]
4770 "")
4771
4772 (define_insn ""
4773 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4774 (const_int 1)
4775 (match_operand:SI 1 "gpc_reg_operand" "r"))
4776 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4777 (const_int 31)))]
4778 "TARGET_POWER"
4779 "rrib %0,%1,%2")
4780
4781 (define_insn ""
4782 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4783 (const_int 1)
4784 (match_operand:SI 1 "gpc_reg_operand" "r"))
4785 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4786 (const_int 31)))]
4787 "TARGET_POWER"
4788 "rrib %0,%1,%2")
4789
4790 (define_insn ""
4791 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4792 (const_int 1)
4793 (match_operand:SI 1 "gpc_reg_operand" "r"))
4794 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4795 (const_int 1)
4796 (const_int 0)))]
4797 "TARGET_POWER"
4798 "rrib %0,%1,%2")
4799
4800 (define_expand "ashrsi3"
4801 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4802 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4803 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4804 ""
4805 "
4806 {
4807 if (TARGET_POWER)
4808 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4809 else
4810 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4811 DONE;
4812 }")
4813
4814 (define_insn "ashrsi3_power"
4815 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4816 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4817 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4818 (clobber (match_scratch:SI 3 "=q,X"))]
4819 "TARGET_POWER"
4820 "@
4821 srea %0,%1,%2
4822 {srai|srawi} %0,%1,%h2"
4823 [(set_attr "type" "shift")])
4824
4825 (define_insn "ashrsi3_no_power"
4826 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4827 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4828 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4829 "! TARGET_POWER"
4830 "@
4831 {sra|sraw} %0,%1,%2
4832 {srai|srawi} %0,%1,%h2"
4833 [(set_attr "type" "var_shift_rotate,shift")])
4834
4835 (define_insn ""
4836 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4837 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4838 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4839 (const_int 0)))
4840 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4841 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4842 "TARGET_POWER"
4843 "@
4844 srea. %3,%1,%2
4845 {srai.|srawi.} %3,%1,%h2
4846 #
4847 #"
4848 [(set_attr "type" "delayed_compare")
4849 (set_attr "length" "4,4,8,8")])
4850
4851 (define_split
4852 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4853 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4854 (match_operand:SI 2 "reg_or_cint_operand" ""))
4855 (const_int 0)))
4856 (clobber (match_scratch:SI 3 ""))
4857 (clobber (match_scratch:SI 4 ""))]
4858 "TARGET_POWER && reload_completed"
4859 [(parallel [(set (match_dup 3)
4860 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4861 (clobber (match_dup 4))])
4862 (set (match_dup 0)
4863 (compare:CC (match_dup 3)
4864 (const_int 0)))]
4865 "")
4866
4867 (define_insn ""
4868 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4869 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4870 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4871 (const_int 0)))
4872 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4873 "! TARGET_POWER"
4874 "@
4875 {sra.|sraw.} %3,%1,%2
4876 {srai.|srawi.} %3,%1,%h2
4877 #
4878 #"
4879 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4880 (set_attr "length" "4,4,8,8")])
4881
4882 (define_split
4883 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4884 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4885 (match_operand:SI 2 "reg_or_cint_operand" ""))
4886 (const_int 0)))
4887 (clobber (match_scratch:SI 3 ""))]
4888 "! TARGET_POWER && reload_completed"
4889 [(set (match_dup 3)
4890 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4891 (set (match_dup 0)
4892 (compare:CC (match_dup 3)
4893 (const_int 0)))]
4894 "")
4895
4896 (define_insn ""
4897 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4898 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4899 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4900 (const_int 0)))
4901 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4902 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4903 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4904 "TARGET_POWER"
4905 "@
4906 srea. %0,%1,%2
4907 {srai.|srawi.} %0,%1,%h2
4908 #
4909 #"
4910 [(set_attr "type" "delayed_compare")
4911 (set_attr "length" "4,4,8,8")])
4912
4913 (define_split
4914 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4915 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4916 (match_operand:SI 2 "reg_or_cint_operand" ""))
4917 (const_int 0)))
4918 (set (match_operand:SI 0 "gpc_reg_operand" "")
4919 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4920 (clobber (match_scratch:SI 4 ""))]
4921 "TARGET_POWER && reload_completed"
4922 [(parallel [(set (match_dup 0)
4923 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4924 (clobber (match_dup 4))])
4925 (set (match_dup 3)
4926 (compare:CC (match_dup 0)
4927 (const_int 0)))]
4928 "")
4929
4930 (define_insn ""
4931 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4932 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4933 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4934 (const_int 0)))
4935 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4936 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4937 "! TARGET_POWER"
4938 "@
4939 {sra.|sraw.} %0,%1,%2
4940 {srai.|srawi.} %0,%1,%h2
4941 #
4942 #"
4943 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4944 (set_attr "length" "4,4,8,8")])
4945 \f
4946 (define_split
4947 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4948 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4949 (match_operand:SI 2 "reg_or_cint_operand" ""))
4950 (const_int 0)))
4951 (set (match_operand:SI 0 "gpc_reg_operand" "")
4952 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4953 "! TARGET_POWER && reload_completed"
4954 [(set (match_dup 0)
4955 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4956 (set (match_dup 3)
4957 (compare:CC (match_dup 0)
4958 (const_int 0)))]
4959 "")
4960
4961 ;; Floating-point insns, excluding normal data motion.
4962 ;;
4963 ;; PowerPC has a full set of single-precision floating point instructions.
4964 ;;
4965 ;; For the POWER architecture, we pretend that we have both SFmode and
4966 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4967 ;; The only conversions we will do will be when storing to memory. In that
4968 ;; case, we will use the "frsp" instruction before storing.
4969 ;;
4970 ;; Note that when we store into a single-precision memory location, we need to
4971 ;; use the frsp insn first. If the register being stored isn't dead, we
4972 ;; need a scratch register for the frsp. But this is difficult when the store
4973 ;; is done by reload. It is not incorrect to do the frsp on the register in
4974 ;; this case, we just lose precision that we would have otherwise gotten but
4975 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4976
4977 (define_expand "extendsfdf2"
4978 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4979 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4980 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4981 "")
4982
4983 (define_insn_and_split "*extendsfdf2_fpr"
4984 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
4985 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
4986 "TARGET_HARD_FLOAT && TARGET_FPRS"
4987 "@
4988 #
4989 fmr %0,%1
4990 lfs%U1%X1 %0,%1"
4991 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4992 [(const_int 0)]
4993 {
4994 emit_note (NOTE_INSN_DELETED);
4995 DONE;
4996 }
4997 [(set_attr "type" "fp,fp,fpload")])
4998
4999 (define_expand "truncdfsf2"
5000 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5001 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5002 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5003 "")
5004
5005 (define_insn "*truncdfsf2_fpr"
5006 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5007 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5008 "TARGET_HARD_FLOAT && TARGET_FPRS"
5009 "frsp %0,%1"
5010 [(set_attr "type" "fp")])
5011
5012 (define_insn "aux_truncdfsf2"
5013 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5014 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
5015 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5016 "frsp %0,%1"
5017 [(set_attr "type" "fp")])
5018
5019 (define_expand "negsf2"
5020 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5021 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5022 "TARGET_HARD_FLOAT"
5023 "")
5024
5025 (define_insn "*negsf2"
5026 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5027 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5028 "TARGET_HARD_FLOAT && TARGET_FPRS"
5029 "fneg %0,%1"
5030 [(set_attr "type" "fp")])
5031
5032 (define_expand "abssf2"
5033 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5034 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5035 "TARGET_HARD_FLOAT"
5036 "")
5037
5038 (define_insn "*abssf2"
5039 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5040 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5041 "TARGET_HARD_FLOAT && TARGET_FPRS"
5042 "fabs %0,%1"
5043 [(set_attr "type" "fp")])
5044
5045 (define_insn ""
5046 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5047 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
5048 "TARGET_HARD_FLOAT && TARGET_FPRS"
5049 "fnabs %0,%1"
5050 [(set_attr "type" "fp")])
5051
5052 (define_expand "addsf3"
5053 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5054 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5055 (match_operand:SF 2 "gpc_reg_operand" "")))]
5056 "TARGET_HARD_FLOAT"
5057 "")
5058
5059 (define_insn ""
5060 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5061 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5062 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5063 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5064 "fadds %0,%1,%2"
5065 [(set_attr "type" "fp")])
5066
5067 (define_insn ""
5068 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5069 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5070 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5071 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5072 "{fa|fadd} %0,%1,%2"
5073 [(set_attr "type" "fp")])
5074
5075 (define_expand "subsf3"
5076 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5077 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5078 (match_operand:SF 2 "gpc_reg_operand" "")))]
5079 "TARGET_HARD_FLOAT"
5080 "")
5081
5082 (define_insn ""
5083 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5084 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5085 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5086 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5087 "fsubs %0,%1,%2"
5088 [(set_attr "type" "fp")])
5089
5090 (define_insn ""
5091 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5092 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5093 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5094 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5095 "{fs|fsub} %0,%1,%2"
5096 [(set_attr "type" "fp")])
5097
5098 (define_expand "mulsf3"
5099 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5100 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5101 (match_operand:SF 2 "gpc_reg_operand" "")))]
5102 "TARGET_HARD_FLOAT"
5103 "")
5104
5105 (define_insn ""
5106 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5107 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5108 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5109 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5110 "fmuls %0,%1,%2"
5111 [(set_attr "type" "fp")])
5112
5113 (define_insn ""
5114 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5115 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5116 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5117 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5118 "{fm|fmul} %0,%1,%2"
5119 [(set_attr "type" "dmul")])
5120
5121 (define_insn "fres"
5122 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5123 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5124 "TARGET_PPC_GFXOPT && flag_finite_math_only"
5125 "fres %0,%1"
5126 [(set_attr "type" "fp")])
5127
5128 (define_expand "divsf3"
5129 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5130 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5131 (match_operand:SF 2 "gpc_reg_operand" "")))]
5132 "TARGET_HARD_FLOAT"
5133 {
5134 if (swdiv && !optimize_size && TARGET_PPC_GFXOPT
5135 && flag_finite_math_only && !flag_trapping_math)
5136 {
5137 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5138 DONE;
5139 }
5140 })
5141
5142 (define_insn ""
5143 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5144 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5145 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5146 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5147 "fdivs %0,%1,%2"
5148 [(set_attr "type" "sdiv")])
5149
5150 (define_insn ""
5151 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5152 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5153 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5154 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5155 "{fd|fdiv} %0,%1,%2"
5156 [(set_attr "type" "ddiv")])
5157
5158 (define_insn ""
5159 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5160 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5161 (match_operand:SF 2 "gpc_reg_operand" "f"))
5162 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5163 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5164 "fmadds %0,%1,%2,%3"
5165 [(set_attr "type" "fp")])
5166
5167 (define_insn ""
5168 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5169 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5170 (match_operand:SF 2 "gpc_reg_operand" "f"))
5171 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5172 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5173 "{fma|fmadd} %0,%1,%2,%3"
5174 [(set_attr "type" "dmul")])
5175
5176 (define_insn ""
5177 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5178 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5179 (match_operand:SF 2 "gpc_reg_operand" "f"))
5180 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5181 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5182 "fmsubs %0,%1,%2,%3"
5183 [(set_attr "type" "fp")])
5184
5185 (define_insn ""
5186 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5187 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5188 (match_operand:SF 2 "gpc_reg_operand" "f"))
5189 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5190 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5191 "{fms|fmsub} %0,%1,%2,%3"
5192 [(set_attr "type" "dmul")])
5193
5194 (define_insn ""
5195 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5196 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5197 (match_operand:SF 2 "gpc_reg_operand" "f"))
5198 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5199 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5200 && HONOR_SIGNED_ZEROS (SFmode)"
5201 "fnmadds %0,%1,%2,%3"
5202 [(set_attr "type" "fp")])
5203
5204 (define_insn ""
5205 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5206 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5207 (match_operand:SF 2 "gpc_reg_operand" "f"))
5208 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5209 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5210 && ! HONOR_SIGNED_ZEROS (SFmode)"
5211 "fnmadds %0,%1,%2,%3"
5212 [(set_attr "type" "fp")])
5213
5214 (define_insn ""
5215 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5216 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5217 (match_operand:SF 2 "gpc_reg_operand" "f"))
5218 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5219 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5220 "{fnma|fnmadd} %0,%1,%2,%3"
5221 [(set_attr "type" "dmul")])
5222
5223 (define_insn ""
5224 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5225 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5226 (match_operand:SF 2 "gpc_reg_operand" "f"))
5227 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5228 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5229 && ! HONOR_SIGNED_ZEROS (SFmode)"
5230 "{fnma|fnmadd} %0,%1,%2,%3"
5231 [(set_attr "type" "dmul")])
5232
5233 (define_insn ""
5234 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5235 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5236 (match_operand:SF 2 "gpc_reg_operand" "f"))
5237 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5238 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5239 && HONOR_SIGNED_ZEROS (SFmode)"
5240 "fnmsubs %0,%1,%2,%3"
5241 [(set_attr "type" "fp")])
5242
5243 (define_insn ""
5244 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5245 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5246 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5247 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5248 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5249 && ! HONOR_SIGNED_ZEROS (SFmode)"
5250 "fnmsubs %0,%1,%2,%3"
5251 [(set_attr "type" "fp")])
5252
5253 (define_insn ""
5254 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5255 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5256 (match_operand:SF 2 "gpc_reg_operand" "f"))
5257 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5258 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5259 "{fnms|fnmsub} %0,%1,%2,%3"
5260 [(set_attr "type" "dmul")])
5261
5262 (define_insn ""
5263 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5264 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5265 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5266 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5267 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5268 && ! HONOR_SIGNED_ZEROS (SFmode)"
5269 "{fnms|fnmsub} %0,%1,%2,%3"
5270 [(set_attr "type" "dmul")])
5271
5272 (define_expand "sqrtsf2"
5273 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5274 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5275 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5276 "")
5277
5278 (define_insn ""
5279 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5280 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5281 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5282 "fsqrts %0,%1"
5283 [(set_attr "type" "ssqrt")])
5284
5285 (define_insn ""
5286 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5287 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5288 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
5289 "fsqrt %0,%1"
5290 [(set_attr "type" "dsqrt")])
5291
5292 (define_expand "copysignsf3"
5293 [(set (match_dup 3)
5294 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5295 (set (match_dup 4)
5296 (neg:SF (abs:SF (match_dup 1))))
5297 (set (match_operand:SF 0 "gpc_reg_operand" "")
5298 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5299 (match_dup 5))
5300 (match_dup 3)
5301 (match_dup 4)))]
5302 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5303 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
5304 {
5305 operands[3] = gen_reg_rtx (SFmode);
5306 operands[4] = gen_reg_rtx (SFmode);
5307 operands[5] = CONST0_RTX (SFmode);
5308 })
5309
5310 (define_expand "copysigndf3"
5311 [(set (match_dup 3)
5312 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5313 (set (match_dup 4)
5314 (neg:DF (abs:DF (match_dup 1))))
5315 (set (match_operand:DF 0 "gpc_reg_operand" "")
5316 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5317 (match_dup 5))
5318 (match_dup 3)
5319 (match_dup 4)))]
5320 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5321 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
5322 {
5323 operands[3] = gen_reg_rtx (DFmode);
5324 operands[4] = gen_reg_rtx (DFmode);
5325 operands[5] = CONST0_RTX (DFmode);
5326 })
5327
5328 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5329 ;; fsel instruction and some auxiliary computations. Then we just have a
5330 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5331 ;; combine.
5332 (define_expand "smaxsf3"
5333 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5334 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5335 (match_operand:SF 2 "gpc_reg_operand" ""))
5336 (match_dup 1)
5337 (match_dup 2)))]
5338 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5339 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5340
5341 (define_expand "sminsf3"
5342 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5343 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5344 (match_operand:SF 2 "gpc_reg_operand" ""))
5345 (match_dup 2)
5346 (match_dup 1)))]
5347 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5348 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5349
5350 (define_split
5351 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5352 (match_operator:SF 3 "min_max_operator"
5353 [(match_operand:SF 1 "gpc_reg_operand" "")
5354 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5355 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5356 [(const_int 0)]
5357 "
5358 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5359 operands[1], operands[2]);
5360 DONE;
5361 }")
5362
5363 (define_expand "movsicc"
5364 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5365 (if_then_else:SI (match_operand 1 "comparison_operator" "")
5366 (match_operand:SI 2 "gpc_reg_operand" "")
5367 (match_operand:SI 3 "gpc_reg_operand" "")))]
5368 "TARGET_ISEL"
5369 "
5370 {
5371 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5372 DONE;
5373 else
5374 FAIL;
5375 }")
5376
5377 ;; We use the BASE_REGS for the isel input operands because, if rA is
5378 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5379 ;; because we may switch the operands and rB may end up being rA.
5380 ;;
5381 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5382 ;; leave out the mode in operand 4 and use one pattern, but reload can
5383 ;; change the mode underneath our feet and then gets confused trying
5384 ;; to reload the value.
5385 (define_insn "isel_signed"
5386 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5387 (if_then_else:SI
5388 (match_operator 1 "comparison_operator"
5389 [(match_operand:CC 4 "cc_reg_operand" "y")
5390 (const_int 0)])
5391 (match_operand:SI 2 "gpc_reg_operand" "b")
5392 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5393 "TARGET_ISEL"
5394 "*
5395 { return output_isel (operands); }"
5396 [(set_attr "length" "4")])
5397
5398 (define_insn "isel_unsigned"
5399 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5400 (if_then_else:SI
5401 (match_operator 1 "comparison_operator"
5402 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5403 (const_int 0)])
5404 (match_operand:SI 2 "gpc_reg_operand" "b")
5405 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5406 "TARGET_ISEL"
5407 "*
5408 { return output_isel (operands); }"
5409 [(set_attr "length" "4")])
5410
5411 (define_expand "movsfcc"
5412 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5413 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5414 (match_operand:SF 2 "gpc_reg_operand" "")
5415 (match_operand:SF 3 "gpc_reg_operand" "")))]
5416 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5417 "
5418 {
5419 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5420 DONE;
5421 else
5422 FAIL;
5423 }")
5424
5425 (define_insn "*fselsfsf4"
5426 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5427 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5428 (match_operand:SF 4 "zero_fp_constant" "F"))
5429 (match_operand:SF 2 "gpc_reg_operand" "f")
5430 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5431 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5432 "fsel %0,%1,%2,%3"
5433 [(set_attr "type" "fp")])
5434
5435 (define_insn "*fseldfsf4"
5436 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5437 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5438 (match_operand:DF 4 "zero_fp_constant" "F"))
5439 (match_operand:SF 2 "gpc_reg_operand" "f")
5440 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5441 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5442 "fsel %0,%1,%2,%3"
5443 [(set_attr "type" "fp")])
5444
5445 (define_expand "negdf2"
5446 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5447 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5448 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5449 "")
5450
5451 (define_insn "*negdf2_fpr"
5452 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5453 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5454 "TARGET_HARD_FLOAT && TARGET_FPRS"
5455 "fneg %0,%1"
5456 [(set_attr "type" "fp")])
5457
5458 (define_expand "absdf2"
5459 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5460 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5461 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5462 "")
5463
5464 (define_insn "*absdf2_fpr"
5465 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5466 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5467 "TARGET_HARD_FLOAT && TARGET_FPRS"
5468 "fabs %0,%1"
5469 [(set_attr "type" "fp")])
5470
5471 (define_insn "*nabsdf2_fpr"
5472 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5473 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
5474 "TARGET_HARD_FLOAT && TARGET_FPRS"
5475 "fnabs %0,%1"
5476 [(set_attr "type" "fp")])
5477
5478 (define_expand "adddf3"
5479 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5480 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5481 (match_operand:DF 2 "gpc_reg_operand" "")))]
5482 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5483 "")
5484
5485 (define_insn "*adddf3_fpr"
5486 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5487 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5488 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5489 "TARGET_HARD_FLOAT && TARGET_FPRS"
5490 "{fa|fadd} %0,%1,%2"
5491 [(set_attr "type" "fp")])
5492
5493 (define_expand "subdf3"
5494 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5495 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5496 (match_operand:DF 2 "gpc_reg_operand" "")))]
5497 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5498 "")
5499
5500 (define_insn "*subdf3_fpr"
5501 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5502 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5503 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5504 "TARGET_HARD_FLOAT && TARGET_FPRS"
5505 "{fs|fsub} %0,%1,%2"
5506 [(set_attr "type" "fp")])
5507
5508 (define_expand "muldf3"
5509 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5510 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5511 (match_operand:DF 2 "gpc_reg_operand" "")))]
5512 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5513 "")
5514
5515 (define_insn "*muldf3_fpr"
5516 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5517 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5518 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5519 "TARGET_HARD_FLOAT && TARGET_FPRS"
5520 "{fm|fmul} %0,%1,%2"
5521 [(set_attr "type" "dmul")])
5522
5523 (define_insn "fred"
5524 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5525 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5526 "TARGET_POPCNTB && flag_finite_math_only"
5527 "fre %0,%1"
5528 [(set_attr "type" "fp")])
5529
5530 (define_expand "divdf3"
5531 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5532 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5533 (match_operand:DF 2 "gpc_reg_operand" "")))]
5534 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5535 {
5536 if (swdiv && !optimize_size && TARGET_POPCNTB
5537 && flag_finite_math_only && !flag_trapping_math)
5538 {
5539 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5540 DONE;
5541 }
5542 })
5543
5544 (define_insn "*divdf3_fpr"
5545 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5546 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5547 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5548 "TARGET_HARD_FLOAT && TARGET_FPRS"
5549 "{fd|fdiv} %0,%1,%2"
5550 [(set_attr "type" "ddiv")])
5551
5552 (define_insn ""
5553 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5554 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5555 (match_operand:DF 2 "gpc_reg_operand" "f"))
5556 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5557 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5558 "{fma|fmadd} %0,%1,%2,%3"
5559 [(set_attr "type" "dmul")])
5560
5561 (define_insn ""
5562 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5563 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5564 (match_operand:DF 2 "gpc_reg_operand" "f"))
5565 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5566 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5567 "{fms|fmsub} %0,%1,%2,%3"
5568 [(set_attr "type" "dmul")])
5569
5570 (define_insn ""
5571 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5572 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5573 (match_operand:DF 2 "gpc_reg_operand" "f"))
5574 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5575 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5576 && HONOR_SIGNED_ZEROS (DFmode)"
5577 "{fnma|fnmadd} %0,%1,%2,%3"
5578 [(set_attr "type" "dmul")])
5579
5580 (define_insn ""
5581 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5582 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5583 (match_operand:DF 2 "gpc_reg_operand" "f"))
5584 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5585 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5586 && ! HONOR_SIGNED_ZEROS (DFmode)"
5587 "{fnma|fnmadd} %0,%1,%2,%3"
5588 [(set_attr "type" "dmul")])
5589
5590 (define_insn ""
5591 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5592 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5593 (match_operand:DF 2 "gpc_reg_operand" "f"))
5594 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5595 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5596 && HONOR_SIGNED_ZEROS (DFmode)"
5597 "{fnms|fnmsub} %0,%1,%2,%3"
5598 [(set_attr "type" "dmul")])
5599
5600 (define_insn ""
5601 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5602 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5603 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5604 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5605 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5606 && ! HONOR_SIGNED_ZEROS (DFmode)"
5607 "{fnms|fnmsub} %0,%1,%2,%3"
5608 [(set_attr "type" "dmul")])
5609
5610 (define_insn "sqrtdf2"
5611 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5612 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5613 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5614 "fsqrt %0,%1"
5615 [(set_attr "type" "dsqrt")])
5616
5617 ;; The conditional move instructions allow us to perform max and min
5618 ;; operations even when
5619
5620 (define_expand "smaxdf3"
5621 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5622 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5623 (match_operand:DF 2 "gpc_reg_operand" ""))
5624 (match_dup 1)
5625 (match_dup 2)))]
5626 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5627 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5628
5629 (define_expand "smindf3"
5630 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5631 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5632 (match_operand:DF 2 "gpc_reg_operand" ""))
5633 (match_dup 2)
5634 (match_dup 1)))]
5635 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5636 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5637
5638 (define_split
5639 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5640 (match_operator:DF 3 "min_max_operator"
5641 [(match_operand:DF 1 "gpc_reg_operand" "")
5642 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5643 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5644 [(const_int 0)]
5645 "
5646 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5647 operands[1], operands[2]);
5648 DONE;
5649 }")
5650
5651 (define_expand "movdfcc"
5652 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5653 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5654 (match_operand:DF 2 "gpc_reg_operand" "")
5655 (match_operand:DF 3 "gpc_reg_operand" "")))]
5656 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5657 "
5658 {
5659 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5660 DONE;
5661 else
5662 FAIL;
5663 }")
5664
5665 (define_insn "*fseldfdf4"
5666 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5667 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5668 (match_operand:DF 4 "zero_fp_constant" "F"))
5669 (match_operand:DF 2 "gpc_reg_operand" "f")
5670 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5671 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5672 "fsel %0,%1,%2,%3"
5673 [(set_attr "type" "fp")])
5674
5675 (define_insn "*fselsfdf4"
5676 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5677 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5678 (match_operand:SF 4 "zero_fp_constant" "F"))
5679 (match_operand:DF 2 "gpc_reg_operand" "f")
5680 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5681 "TARGET_PPC_GFXOPT"
5682 "fsel %0,%1,%2,%3"
5683 [(set_attr "type" "fp")])
5684 \f
5685 ;; Conversions to and from floating-point.
5686
5687 (define_expand "fixuns_truncsfsi2"
5688 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5689 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5690 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5691 "")
5692
5693 (define_expand "fix_truncsfsi2"
5694 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5695 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5696 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5697 "")
5698
5699 ; For each of these conversions, there is a define_expand, a define_insn
5700 ; with a '#' template, and a define_split (with C code). The idea is
5701 ; to allow constant folding with the template of the define_insn,
5702 ; then to have the insns split later (between sched1 and final).
5703
5704 (define_expand "floatsidf2"
5705 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5706 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5707 (use (match_dup 2))
5708 (use (match_dup 3))
5709 (clobber (match_dup 4))
5710 (clobber (match_dup 5))
5711 (clobber (match_dup 6))])]
5712 "TARGET_HARD_FLOAT && TARGET_FPRS"
5713 "
5714 {
5715 if (TARGET_E500_DOUBLE)
5716 {
5717 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5718 DONE;
5719 }
5720 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS)
5721 {
5722 rtx t1 = gen_reg_rtx (DImode);
5723 emit_insn (gen_floatsidf_ppc64_mfpgpr (operands[0], operands[1], t1));
5724 DONE;
5725 }
5726 if (TARGET_POWERPC64)
5727 {
5728 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5729 rtx t1 = gen_reg_rtx (DImode);
5730 rtx t2 = gen_reg_rtx (DImode);
5731 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5732 DONE;
5733 }
5734
5735 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5736 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5737 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5738 operands[5] = gen_reg_rtx (DFmode);
5739 operands[6] = gen_reg_rtx (SImode);
5740 }")
5741
5742 (define_insn_and_split "*floatsidf2_internal"
5743 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5744 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5745 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5746 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5747 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5748 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5749 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5750 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5751 "#"
5752 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5753 [(pc)]
5754 "
5755 {
5756 rtx lowword, highword;
5757 gcc_assert (MEM_P (operands[4]));
5758 highword = adjust_address (operands[4], SImode, 0);
5759 lowword = adjust_address (operands[4], SImode, 4);
5760 if (! WORDS_BIG_ENDIAN)
5761 {
5762 rtx tmp;
5763 tmp = highword; highword = lowword; lowword = tmp;
5764 }
5765
5766 emit_insn (gen_xorsi3 (operands[6], operands[1],
5767 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5768 emit_move_insn (lowword, operands[6]);
5769 emit_move_insn (highword, operands[2]);
5770 emit_move_insn (operands[5], operands[4]);
5771 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5772 DONE;
5773 }"
5774 [(set_attr "length" "24")])
5775
5776 (define_expand "floatunssisf2"
5777 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5778 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5779 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5780 "")
5781
5782 (define_expand "floatunssidf2"
5783 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5784 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5785 (use (match_dup 2))
5786 (use (match_dup 3))
5787 (clobber (match_dup 4))
5788 (clobber (match_dup 5))])]
5789 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5790 "
5791 {
5792 if (TARGET_E500_DOUBLE)
5793 {
5794 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5795 DONE;
5796 }
5797 if (TARGET_POWERPC64)
5798 {
5799 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5800 rtx t1 = gen_reg_rtx (DImode);
5801 rtx t2 = gen_reg_rtx (DImode);
5802 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5803 t1, t2));
5804 DONE;
5805 }
5806
5807 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5808 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5809 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5810 operands[5] = gen_reg_rtx (DFmode);
5811 }")
5812
5813 (define_insn_and_split "*floatunssidf2_internal"
5814 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5815 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5816 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5817 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5818 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5819 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5820 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5821 "#"
5822 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5823 [(pc)]
5824 "
5825 {
5826 rtx lowword, highword;
5827 gcc_assert (MEM_P (operands[4]));
5828 highword = adjust_address (operands[4], SImode, 0);
5829 lowword = adjust_address (operands[4], SImode, 4);
5830 if (! WORDS_BIG_ENDIAN)
5831 {
5832 rtx tmp;
5833 tmp = highword; highword = lowword; lowword = tmp;
5834 }
5835
5836 emit_move_insn (lowword, operands[1]);
5837 emit_move_insn (highword, operands[2]);
5838 emit_move_insn (operands[5], operands[4]);
5839 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5840 DONE;
5841 }"
5842 [(set_attr "length" "20")])
5843
5844 (define_expand "fix_truncdfsi2"
5845 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
5846 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5847 (clobber (match_dup 2))
5848 (clobber (match_dup 3))])]
5849 "(TARGET_POWER2 || TARGET_POWERPC)
5850 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5851 "
5852 {
5853 if (TARGET_E500_DOUBLE)
5854 {
5855 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5856 DONE;
5857 }
5858 operands[2] = gen_reg_rtx (DImode);
5859 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
5860 && gpc_reg_operand(operands[0], GET_MODE (operands[0])))
5861 {
5862 operands[3] = gen_reg_rtx (DImode);
5863 emit_insn (gen_fix_truncdfsi2_mfpgpr (operands[0], operands[1],
5864 operands[2], operands[3]));
5865 DONE;
5866 }
5867 if (TARGET_PPC_GFXOPT)
5868 {
5869 rtx orig_dest = operands[0];
5870 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
5871 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5872 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5873 operands[2]));
5874 if (operands[0] != orig_dest)
5875 emit_move_insn (orig_dest, operands[0]);
5876 DONE;
5877 }
5878 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5879 }")
5880
5881 (define_insn_and_split "*fix_truncdfsi2_internal"
5882 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5883 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5884 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5885 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5886 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5887 "#"
5888 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[3]))"
5889 [(pc)]
5890 "
5891 {
5892 rtx lowword;
5893 gcc_assert (MEM_P (operands[3]));
5894 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5895
5896 emit_insn (gen_fctiwz (operands[2], operands[1]));
5897 emit_move_insn (operands[3], operands[2]);
5898 emit_move_insn (operands[0], lowword);
5899 DONE;
5900 }"
5901 [(set_attr "length" "16")])
5902
5903 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
5904 [(set (match_operand:SI 0 "memory_operand" "=Z")
5905 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5906 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
5907 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
5908 && TARGET_PPC_GFXOPT"
5909 "#"
5910 "&& 1"
5911 [(pc)]
5912 "
5913 {
5914 emit_insn (gen_fctiwz (operands[2], operands[1]));
5915 emit_insn (gen_stfiwx (operands[0], operands[2]));
5916 DONE;
5917 }"
5918 [(set_attr "length" "16")])
5919
5920 (define_insn_and_split "fix_truncdfsi2_mfpgpr"
5921 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5922 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5923 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5924 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
5925 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
5926 "#"
5927 "&& 1"
5928 [(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
5929 (set (match_dup 3) (match_dup 2))
5930 (set (match_dup 0) (subreg:SI (match_dup 3) 4))]
5931 ""
5932 [(set_attr "length" "12")])
5933
5934 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5935 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5936 ; because the first makes it clear that operand 0 is not live
5937 ; before the instruction.
5938 (define_insn "fctiwz"
5939 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
5940 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5941 UNSPEC_FCTIWZ))]
5942 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5943 "{fcirz|fctiwz} %0,%1"
5944 [(set_attr "type" "fp")])
5945
5946 (define_insn "btruncdf2"
5947 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5948 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
5949 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5950 "friz %0,%1"
5951 [(set_attr "type" "fp")])
5952
5953 (define_insn "btruncsf2"
5954 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5955 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
5956 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5957 "friz %0,%1"
5958 [(set_attr "type" "fp")])
5959
5960 (define_insn "ceildf2"
5961 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5962 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
5963 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5964 "frip %0,%1"
5965 [(set_attr "type" "fp")])
5966
5967 (define_insn "ceilsf2"
5968 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5969 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
5970 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5971 "frip %0,%1"
5972 [(set_attr "type" "fp")])
5973
5974 (define_insn "floordf2"
5975 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5976 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
5977 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5978 "frim %0,%1"
5979 [(set_attr "type" "fp")])
5980
5981 (define_insn "floorsf2"
5982 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5983 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
5984 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5985 "frim %0,%1"
5986 [(set_attr "type" "fp")])
5987
5988 (define_insn "rounddf2"
5989 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5990 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
5991 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5992 "frin %0,%1"
5993 [(set_attr "type" "fp")])
5994
5995 (define_insn "roundsf2"
5996 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5997 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
5998 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5999 "frin %0,%1"
6000 [(set_attr "type" "fp")])
6001
6002 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6003 (define_insn "stfiwx"
6004 [(set (match_operand:SI 0 "memory_operand" "=Z")
6005 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
6006 UNSPEC_STFIWX))]
6007 "TARGET_PPC_GFXOPT"
6008 "stfiwx %1,%y0"
6009 [(set_attr "type" "fpstore")])
6010
6011 (define_expand "floatsisf2"
6012 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6013 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6014 "TARGET_HARD_FLOAT && !TARGET_FPRS"
6015 "")
6016
6017 (define_insn "floatdidf2"
6018 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6019 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
6020 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6021 "fcfid %0,%1"
6022 [(set_attr "type" "fp")])
6023
6024 (define_insn_and_split "floatsidf_ppc64_mfpgpr"
6025 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6026 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6027 (clobber (match_operand:DI 2 "gpc_reg_operand" "=r"))]
6028 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
6029 "#"
6030 "&& 1"
6031 [(set (match_dup 2) (sign_extend:DI (match_dup 1)))
6032 (set (match_dup 0) (float:DF (match_dup 2)))]
6033 "")
6034
6035 (define_insn_and_split "floatsidf_ppc64"
6036 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6037 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6038 (clobber (match_operand:DI 2 "memory_operand" "=o"))
6039 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
6040 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
6041 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
6042 "#"
6043 "&& 1"
6044 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
6045 (set (match_dup 2) (match_dup 3))
6046 (set (match_dup 4) (match_dup 2))
6047 (set (match_dup 0) (float:DF (match_dup 4)))]
6048 "")
6049
6050 (define_insn_and_split "floatunssidf_ppc64"
6051 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6052 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6053 (clobber (match_operand:DI 2 "memory_operand" "=o"))
6054 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
6055 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
6056 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6057 "#"
6058 "&& 1"
6059 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
6060 (set (match_dup 2) (match_dup 3))
6061 (set (match_dup 4) (match_dup 2))
6062 (set (match_dup 0) (float:DF (match_dup 4)))]
6063 "")
6064
6065 (define_insn "fix_truncdfdi2"
6066 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
6067 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
6068 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6069 "fctidz %0,%1"
6070 [(set_attr "type" "fp")])
6071
6072 (define_expand "floatdisf2"
6073 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6074 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6075 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6076 "
6077 {
6078 rtx val = operands[1];
6079 if (!flag_unsafe_math_optimizations)
6080 {
6081 rtx label = gen_label_rtx ();
6082 val = gen_reg_rtx (DImode);
6083 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6084 emit_label (label);
6085 }
6086 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6087 DONE;
6088 }")
6089
6090 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6091 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6092 ;; from double rounding.
6093 (define_insn_and_split "floatdisf2_internal1"
6094 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6095 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
6096 (clobber (match_scratch:DF 2 "=f"))]
6097 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6098 "#"
6099 "&& reload_completed"
6100 [(set (match_dup 2)
6101 (float:DF (match_dup 1)))
6102 (set (match_dup 0)
6103 (float_truncate:SF (match_dup 2)))]
6104 "")
6105
6106 ;; Twiddles bits to avoid double rounding.
6107 ;; Bits that might be truncated when converting to DFmode are replaced
6108 ;; by a bit that won't be lost at that stage, but is below the SFmode
6109 ;; rounding position.
6110 (define_expand "floatdisf2_internal2"
6111 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6112 (const_int 53)))
6113 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6114 (const_int 2047)))
6115 (clobber (scratch:CC))])
6116 (set (match_dup 3) (plus:DI (match_dup 3)
6117 (const_int 1)))
6118 (set (match_dup 0) (plus:DI (match_dup 0)
6119 (const_int 2047)))
6120 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6121 (const_int 2)))
6122 (set (match_dup 0) (ior:DI (match_dup 0)
6123 (match_dup 1)))
6124 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6125 (const_int -2048)))
6126 (clobber (scratch:CC))])
6127 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6128 (label_ref (match_operand:DI 2 "" ""))
6129 (pc)))
6130 (set (match_dup 0) (match_dup 1))]
6131 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6132 "
6133 {
6134 operands[3] = gen_reg_rtx (DImode);
6135 operands[4] = gen_reg_rtx (CCUNSmode);
6136 }")
6137 \f
6138 ;; Define the DImode operations that can be done in a small number
6139 ;; of instructions. The & constraints are to prevent the register
6140 ;; allocator from allocating registers that overlap with the inputs
6141 ;; (for example, having an input in 7,8 and an output in 6,7). We
6142 ;; also allow for the output being the same as one of the inputs.
6143
6144 (define_insn "*adddi3_noppc64"
6145 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6146 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6147 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6148 "! TARGET_POWERPC64"
6149 "*
6150 {
6151 if (WORDS_BIG_ENDIAN)
6152 return (GET_CODE (operands[2])) != CONST_INT
6153 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6154 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6155 else
6156 return (GET_CODE (operands[2])) != CONST_INT
6157 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6158 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6159 }"
6160 [(set_attr "type" "two")
6161 (set_attr "length" "8")])
6162
6163 (define_insn "*subdi3_noppc64"
6164 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6165 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6166 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6167 "! TARGET_POWERPC64"
6168 "*
6169 {
6170 if (WORDS_BIG_ENDIAN)
6171 return (GET_CODE (operands[1]) != CONST_INT)
6172 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6173 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6174 else
6175 return (GET_CODE (operands[1]) != CONST_INT)
6176 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6177 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
6178 }"
6179 [(set_attr "type" "two")
6180 (set_attr "length" "8")])
6181
6182 (define_insn "*negdi2_noppc64"
6183 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6184 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6185 "! TARGET_POWERPC64"
6186 "*
6187 {
6188 return (WORDS_BIG_ENDIAN)
6189 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6190 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6191 }"
6192 [(set_attr "type" "two")
6193 (set_attr "length" "8")])
6194
6195 (define_expand "mulsidi3"
6196 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6197 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6198 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6199 "! TARGET_POWERPC64"
6200 "
6201 {
6202 if (! TARGET_POWER && ! TARGET_POWERPC)
6203 {
6204 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6205 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6206 emit_insn (gen_mull_call ());
6207 if (WORDS_BIG_ENDIAN)
6208 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
6209 else
6210 {
6211 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
6212 gen_rtx_REG (SImode, 3));
6213 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
6214 gen_rtx_REG (SImode, 4));
6215 }
6216 DONE;
6217 }
6218 else if (TARGET_POWER)
6219 {
6220 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6221 DONE;
6222 }
6223 }")
6224
6225 (define_insn "mulsidi3_mq"
6226 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6227 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6228 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6229 (clobber (match_scratch:SI 3 "=q"))]
6230 "TARGET_POWER"
6231 "mul %0,%1,%2\;mfmq %L0"
6232 [(set_attr "type" "imul")
6233 (set_attr "length" "8")])
6234
6235 (define_insn "*mulsidi3_no_mq"
6236 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6237 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6238 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6239 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6240 "*
6241 {
6242 return (WORDS_BIG_ENDIAN)
6243 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6244 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6245 }"
6246 [(set_attr "type" "imul")
6247 (set_attr "length" "8")])
6248
6249 (define_split
6250 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6251 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6252 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6253 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6254 [(set (match_dup 3)
6255 (truncate:SI
6256 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6257 (sign_extend:DI (match_dup 2)))
6258 (const_int 32))))
6259 (set (match_dup 4)
6260 (mult:SI (match_dup 1)
6261 (match_dup 2)))]
6262 "
6263 {
6264 int endian = (WORDS_BIG_ENDIAN == 0);
6265 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6266 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6267 }")
6268
6269 (define_expand "umulsidi3"
6270 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6271 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6272 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6273 "TARGET_POWERPC && ! TARGET_POWERPC64"
6274 "
6275 {
6276 if (TARGET_POWER)
6277 {
6278 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6279 DONE;
6280 }
6281 }")
6282
6283 (define_insn "umulsidi3_mq"
6284 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6285 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6286 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6287 (clobber (match_scratch:SI 3 "=q"))]
6288 "TARGET_POWERPC && TARGET_POWER"
6289 "*
6290 {
6291 return (WORDS_BIG_ENDIAN)
6292 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6293 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6294 }"
6295 [(set_attr "type" "imul")
6296 (set_attr "length" "8")])
6297
6298 (define_insn "*umulsidi3_no_mq"
6299 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6300 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6301 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6302 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6303 "*
6304 {
6305 return (WORDS_BIG_ENDIAN)
6306 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6307 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6308 }"
6309 [(set_attr "type" "imul")
6310 (set_attr "length" "8")])
6311
6312 (define_split
6313 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6314 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6315 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6316 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6317 [(set (match_dup 3)
6318 (truncate:SI
6319 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6320 (zero_extend:DI (match_dup 2)))
6321 (const_int 32))))
6322 (set (match_dup 4)
6323 (mult:SI (match_dup 1)
6324 (match_dup 2)))]
6325 "
6326 {
6327 int endian = (WORDS_BIG_ENDIAN == 0);
6328 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6329 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6330 }")
6331
6332 (define_expand "smulsi3_highpart"
6333 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6334 (truncate:SI
6335 (lshiftrt:DI (mult:DI (sign_extend:DI
6336 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6337 (sign_extend:DI
6338 (match_operand:SI 2 "gpc_reg_operand" "r")))
6339 (const_int 32))))]
6340 ""
6341 "
6342 {
6343 if (! TARGET_POWER && ! TARGET_POWERPC)
6344 {
6345 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6346 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6347 emit_insn (gen_mulh_call ());
6348 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
6349 DONE;
6350 }
6351 else if (TARGET_POWER)
6352 {
6353 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6354 DONE;
6355 }
6356 }")
6357
6358 (define_insn "smulsi3_highpart_mq"
6359 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6360 (truncate:SI
6361 (lshiftrt:DI (mult:DI (sign_extend:DI
6362 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6363 (sign_extend:DI
6364 (match_operand:SI 2 "gpc_reg_operand" "r")))
6365 (const_int 32))))
6366 (clobber (match_scratch:SI 3 "=q"))]
6367 "TARGET_POWER"
6368 "mul %0,%1,%2"
6369 [(set_attr "type" "imul")])
6370
6371 (define_insn "*smulsi3_highpart_no_mq"
6372 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6373 (truncate:SI
6374 (lshiftrt:DI (mult:DI (sign_extend:DI
6375 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6376 (sign_extend:DI
6377 (match_operand:SI 2 "gpc_reg_operand" "r")))
6378 (const_int 32))))]
6379 "TARGET_POWERPC && ! TARGET_POWER"
6380 "mulhw %0,%1,%2"
6381 [(set_attr "type" "imul")])
6382
6383 (define_expand "umulsi3_highpart"
6384 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6385 (truncate:SI
6386 (lshiftrt:DI (mult:DI (zero_extend:DI
6387 (match_operand:SI 1 "gpc_reg_operand" ""))
6388 (zero_extend:DI
6389 (match_operand:SI 2 "gpc_reg_operand" "")))
6390 (const_int 32))))]
6391 "TARGET_POWERPC"
6392 "
6393 {
6394 if (TARGET_POWER)
6395 {
6396 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6397 DONE;
6398 }
6399 }")
6400
6401 (define_insn "umulsi3_highpart_mq"
6402 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6403 (truncate:SI
6404 (lshiftrt:DI (mult:DI (zero_extend:DI
6405 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6406 (zero_extend:DI
6407 (match_operand:SI 2 "gpc_reg_operand" "r")))
6408 (const_int 32))))
6409 (clobber (match_scratch:SI 3 "=q"))]
6410 "TARGET_POWERPC && TARGET_POWER"
6411 "mulhwu %0,%1,%2"
6412 [(set_attr "type" "imul")])
6413
6414 (define_insn "*umulsi3_highpart_no_mq"
6415 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6416 (truncate:SI
6417 (lshiftrt:DI (mult:DI (zero_extend:DI
6418 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6419 (zero_extend:DI
6420 (match_operand:SI 2 "gpc_reg_operand" "r")))
6421 (const_int 32))))]
6422 "TARGET_POWERPC && ! TARGET_POWER"
6423 "mulhwu %0,%1,%2"
6424 [(set_attr "type" "imul")])
6425
6426 ;; If operands 0 and 2 are in the same register, we have a problem. But
6427 ;; operands 0 and 1 (the usual case) can be in the same register. That's
6428 ;; why we have the strange constraints below.
6429 (define_insn "ashldi3_power"
6430 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6431 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6432 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6433 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6434 "TARGET_POWER"
6435 "@
6436 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
6437 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6438 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6439 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
6440 [(set_attr "length" "8")])
6441
6442 (define_insn "lshrdi3_power"
6443 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6444 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6445 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6446 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6447 "TARGET_POWER"
6448 "@
6449 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
6450 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6451 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6452 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
6453 [(set_attr "length" "8")])
6454
6455 ;; Shift by a variable amount is too complex to be worth open-coding. We
6456 ;; just handle shifts by constants.
6457 (define_insn "ashrdi3_power"
6458 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6459 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6460 (match_operand:SI 2 "const_int_operand" "M,i")))
6461 (clobber (match_scratch:SI 3 "=X,q"))]
6462 "TARGET_POWER"
6463 "@
6464 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6465 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
6466 [(set_attr "type" "shift")
6467 (set_attr "length" "8")])
6468
6469 (define_insn "ashrdi3_no_power"
6470 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6471 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6472 (match_operand:SI 2 "const_int_operand" "M,i")))]
6473 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
6474 "@
6475 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6476 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
6477 [(set_attr "type" "two,three")
6478 (set_attr "length" "8,12")])
6479
6480 (define_insn "*ashrdisi3_noppc64"
6481 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6482 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6483 (const_int 32)) 4))]
6484 "TARGET_32BIT && !TARGET_POWERPC64"
6485 "*
6486 {
6487 if (REGNO (operands[0]) == REGNO (operands[1]))
6488 return \"\";
6489 else
6490 return \"mr %0,%1\";
6491 }"
6492 [(set_attr "length" "4")])
6493
6494 \f
6495 ;; PowerPC64 DImode operations.
6496
6497 (define_insn_and_split "absdi2"
6498 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6499 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6500 (clobber (match_scratch:DI 2 "=&r,&r"))]
6501 "TARGET_POWERPC64"
6502 "#"
6503 "&& reload_completed"
6504 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6505 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6506 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6507 "")
6508
6509 (define_insn_and_split "*nabsdi2"
6510 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6511 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6512 (clobber (match_scratch:DI 2 "=&r,&r"))]
6513 "TARGET_POWERPC64"
6514 "#"
6515 "&& reload_completed"
6516 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6517 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6518 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
6519 "")
6520
6521 (define_insn "muldi3"
6522 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6523 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6524 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6525 "TARGET_POWERPC64"
6526 "@
6527 mulld %0,%1,%2
6528 mulli %0,%1,%2"
6529 [(set (attr "type")
6530 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6531 (const_string "imul3")
6532 (match_operand:SI 2 "short_cint_operand" "")
6533 (const_string "imul2")]
6534 (const_string "lmul")))])
6535
6536 (define_insn "*muldi3_internal1"
6537 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6538 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6539 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6540 (const_int 0)))
6541 (clobber (match_scratch:DI 3 "=r,r"))]
6542 "TARGET_POWERPC64"
6543 "@
6544 mulld. %3,%1,%2
6545 #"
6546 [(set_attr "type" "lmul_compare")
6547 (set_attr "length" "4,8")])
6548
6549 (define_split
6550 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6551 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6552 (match_operand:DI 2 "gpc_reg_operand" ""))
6553 (const_int 0)))
6554 (clobber (match_scratch:DI 3 ""))]
6555 "TARGET_POWERPC64 && reload_completed"
6556 [(set (match_dup 3)
6557 (mult:DI (match_dup 1) (match_dup 2)))
6558 (set (match_dup 0)
6559 (compare:CC (match_dup 3)
6560 (const_int 0)))]
6561 "")
6562
6563 (define_insn "*muldi3_internal2"
6564 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6565 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6566 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6567 (const_int 0)))
6568 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6569 (mult:DI (match_dup 1) (match_dup 2)))]
6570 "TARGET_POWERPC64"
6571 "@
6572 mulld. %0,%1,%2
6573 #"
6574 [(set_attr "type" "lmul_compare")
6575 (set_attr "length" "4,8")])
6576
6577 (define_split
6578 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6579 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6580 (match_operand:DI 2 "gpc_reg_operand" ""))
6581 (const_int 0)))
6582 (set (match_operand:DI 0 "gpc_reg_operand" "")
6583 (mult:DI (match_dup 1) (match_dup 2)))]
6584 "TARGET_POWERPC64 && reload_completed"
6585 [(set (match_dup 0)
6586 (mult:DI (match_dup 1) (match_dup 2)))
6587 (set (match_dup 3)
6588 (compare:CC (match_dup 0)
6589 (const_int 0)))]
6590 "")
6591
6592 (define_insn "smuldi3_highpart"
6593 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6594 (truncate:DI
6595 (lshiftrt:TI (mult:TI (sign_extend:TI
6596 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6597 (sign_extend:TI
6598 (match_operand:DI 2 "gpc_reg_operand" "r")))
6599 (const_int 64))))]
6600 "TARGET_POWERPC64"
6601 "mulhd %0,%1,%2"
6602 [(set_attr "type" "lmul")])
6603
6604 (define_insn "umuldi3_highpart"
6605 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6606 (truncate:DI
6607 (lshiftrt:TI (mult:TI (zero_extend:TI
6608 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6609 (zero_extend:TI
6610 (match_operand:DI 2 "gpc_reg_operand" "r")))
6611 (const_int 64))))]
6612 "TARGET_POWERPC64"
6613 "mulhdu %0,%1,%2"
6614 [(set_attr "type" "lmul")])
6615
6616 (define_insn "rotldi3"
6617 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6618 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6619 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
6620 "TARGET_POWERPC64"
6621 "@
6622 rldcl %0,%1,%2,0
6623 rldicl %0,%1,%H2,0"
6624 [(set_attr "type" "var_shift_rotate,integer")])
6625
6626 (define_insn "*rotldi3_internal2"
6627 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6628 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6629 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6630 (const_int 0)))
6631 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6632 "TARGET_64BIT"
6633 "@
6634 rldcl. %3,%1,%2,0
6635 rldicl. %3,%1,%H2,0
6636 #
6637 #"
6638 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6639 (set_attr "length" "4,4,8,8")])
6640
6641 (define_split
6642 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6643 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6644 (match_operand:DI 2 "reg_or_cint_operand" ""))
6645 (const_int 0)))
6646 (clobber (match_scratch:DI 3 ""))]
6647 "TARGET_POWERPC64 && reload_completed"
6648 [(set (match_dup 3)
6649 (rotate:DI (match_dup 1) (match_dup 2)))
6650 (set (match_dup 0)
6651 (compare:CC (match_dup 3)
6652 (const_int 0)))]
6653 "")
6654
6655 (define_insn "*rotldi3_internal3"
6656 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6657 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6658 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6659 (const_int 0)))
6660 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6661 (rotate:DI (match_dup 1) (match_dup 2)))]
6662 "TARGET_64BIT"
6663 "@
6664 rldcl. %0,%1,%2,0
6665 rldicl. %0,%1,%H2,0
6666 #
6667 #"
6668 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6669 (set_attr "length" "4,4,8,8")])
6670
6671 (define_split
6672 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6673 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6674 (match_operand:DI 2 "reg_or_cint_operand" ""))
6675 (const_int 0)))
6676 (set (match_operand:DI 0 "gpc_reg_operand" "")
6677 (rotate:DI (match_dup 1) (match_dup 2)))]
6678 "TARGET_POWERPC64 && reload_completed"
6679 [(set (match_dup 0)
6680 (rotate:DI (match_dup 1) (match_dup 2)))
6681 (set (match_dup 3)
6682 (compare:CC (match_dup 0)
6683 (const_int 0)))]
6684 "")
6685
6686 (define_insn "*rotldi3_internal4"
6687 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6688 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6689 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6690 (match_operand:DI 3 "mask64_operand" "n,n")))]
6691 "TARGET_POWERPC64"
6692 "@
6693 rldc%B3 %0,%1,%2,%S3
6694 rldic%B3 %0,%1,%H2,%S3"
6695 [(set_attr "type" "var_shift_rotate,integer")])
6696
6697 (define_insn "*rotldi3_internal5"
6698 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6699 (compare:CC (and:DI
6700 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6701 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6702 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6703 (const_int 0)))
6704 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
6705 "TARGET_64BIT"
6706 "@
6707 rldc%B3. %4,%1,%2,%S3
6708 rldic%B3. %4,%1,%H2,%S3
6709 #
6710 #"
6711 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6712 (set_attr "length" "4,4,8,8")])
6713
6714 (define_split
6715 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6716 (compare:CC (and:DI
6717 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6718 (match_operand:DI 2 "reg_or_cint_operand" ""))
6719 (match_operand:DI 3 "mask64_operand" ""))
6720 (const_int 0)))
6721 (clobber (match_scratch:DI 4 ""))]
6722 "TARGET_POWERPC64 && reload_completed"
6723 [(set (match_dup 4)
6724 (and:DI (rotate:DI (match_dup 1)
6725 (match_dup 2))
6726 (match_dup 3)))
6727 (set (match_dup 0)
6728 (compare:CC (match_dup 4)
6729 (const_int 0)))]
6730 "")
6731
6732 (define_insn "*rotldi3_internal6"
6733 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
6734 (compare:CC (and:DI
6735 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6736 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6737 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6738 (const_int 0)))
6739 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6740 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6741 "TARGET_64BIT"
6742 "@
6743 rldc%B3. %0,%1,%2,%S3
6744 rldic%B3. %0,%1,%H2,%S3
6745 #
6746 #"
6747 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6748 (set_attr "length" "4,4,8,8")])
6749
6750 (define_split
6751 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6752 (compare:CC (and:DI
6753 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6754 (match_operand:DI 2 "reg_or_cint_operand" ""))
6755 (match_operand:DI 3 "mask64_operand" ""))
6756 (const_int 0)))
6757 (set (match_operand:DI 0 "gpc_reg_operand" "")
6758 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6759 "TARGET_POWERPC64 && reload_completed"
6760 [(set (match_dup 0)
6761 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6762 (set (match_dup 4)
6763 (compare:CC (match_dup 0)
6764 (const_int 0)))]
6765 "")
6766
6767 (define_insn "*rotldi3_internal7"
6768 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6769 (zero_extend:DI
6770 (subreg:QI
6771 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6772 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6773 "TARGET_POWERPC64"
6774 "@
6775 rldcl %0,%1,%2,56
6776 rldicl %0,%1,%H2,56"
6777 [(set_attr "type" "var_shift_rotate,integer")])
6778
6779 (define_insn "*rotldi3_internal8"
6780 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6781 (compare:CC (zero_extend:DI
6782 (subreg:QI
6783 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6784 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6785 (const_int 0)))
6786 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6787 "TARGET_64BIT"
6788 "@
6789 rldcl. %3,%1,%2,56
6790 rldicl. %3,%1,%H2,56
6791 #
6792 #"
6793 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6794 (set_attr "length" "4,4,8,8")])
6795
6796 (define_split
6797 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6798 (compare:CC (zero_extend:DI
6799 (subreg:QI
6800 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6801 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6802 (const_int 0)))
6803 (clobber (match_scratch:DI 3 ""))]
6804 "TARGET_POWERPC64 && reload_completed"
6805 [(set (match_dup 3)
6806 (zero_extend:DI (subreg:QI
6807 (rotate:DI (match_dup 1)
6808 (match_dup 2)) 0)))
6809 (set (match_dup 0)
6810 (compare:CC (match_dup 3)
6811 (const_int 0)))]
6812 "")
6813
6814 (define_insn "*rotldi3_internal9"
6815 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6816 (compare:CC (zero_extend:DI
6817 (subreg:QI
6818 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6819 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6820 (const_int 0)))
6821 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6822 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6823 "TARGET_64BIT"
6824 "@
6825 rldcl. %0,%1,%2,56
6826 rldicl. %0,%1,%H2,56
6827 #
6828 #"
6829 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6830 (set_attr "length" "4,4,8,8")])
6831
6832 (define_split
6833 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6834 (compare:CC (zero_extend:DI
6835 (subreg:QI
6836 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6837 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6838 (const_int 0)))
6839 (set (match_operand:DI 0 "gpc_reg_operand" "")
6840 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6841 "TARGET_POWERPC64 && reload_completed"
6842 [(set (match_dup 0)
6843 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6844 (set (match_dup 3)
6845 (compare:CC (match_dup 0)
6846 (const_int 0)))]
6847 "")
6848
6849 (define_insn "*rotldi3_internal10"
6850 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6851 (zero_extend:DI
6852 (subreg:HI
6853 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6854 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6855 "TARGET_POWERPC64"
6856 "@
6857 rldcl %0,%1,%2,48
6858 rldicl %0,%1,%H2,48"
6859 [(set_attr "type" "var_shift_rotate,integer")])
6860
6861 (define_insn "*rotldi3_internal11"
6862 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6863 (compare:CC (zero_extend:DI
6864 (subreg:HI
6865 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6866 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6867 (const_int 0)))
6868 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6869 "TARGET_64BIT"
6870 "@
6871 rldcl. %3,%1,%2,48
6872 rldicl. %3,%1,%H2,48
6873 #
6874 #"
6875 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6876 (set_attr "length" "4,4,8,8")])
6877
6878 (define_split
6879 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6880 (compare:CC (zero_extend:DI
6881 (subreg:HI
6882 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6883 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6884 (const_int 0)))
6885 (clobber (match_scratch:DI 3 ""))]
6886 "TARGET_POWERPC64 && reload_completed"
6887 [(set (match_dup 3)
6888 (zero_extend:DI (subreg:HI
6889 (rotate:DI (match_dup 1)
6890 (match_dup 2)) 0)))
6891 (set (match_dup 0)
6892 (compare:CC (match_dup 3)
6893 (const_int 0)))]
6894 "")
6895
6896 (define_insn "*rotldi3_internal12"
6897 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6898 (compare:CC (zero_extend:DI
6899 (subreg:HI
6900 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6901 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6902 (const_int 0)))
6903 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6904 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6905 "TARGET_64BIT"
6906 "@
6907 rldcl. %0,%1,%2,48
6908 rldicl. %0,%1,%H2,48
6909 #
6910 #"
6911 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6912 (set_attr "length" "4,4,8,8")])
6913
6914 (define_split
6915 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6916 (compare:CC (zero_extend:DI
6917 (subreg:HI
6918 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6919 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6920 (const_int 0)))
6921 (set (match_operand:DI 0 "gpc_reg_operand" "")
6922 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6923 "TARGET_POWERPC64 && reload_completed"
6924 [(set (match_dup 0)
6925 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6926 (set (match_dup 3)
6927 (compare:CC (match_dup 0)
6928 (const_int 0)))]
6929 "")
6930
6931 (define_insn "*rotldi3_internal13"
6932 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6933 (zero_extend:DI
6934 (subreg:SI
6935 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6936 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6937 "TARGET_POWERPC64"
6938 "@
6939 rldcl %0,%1,%2,32
6940 rldicl %0,%1,%H2,32"
6941 [(set_attr "type" "var_shift_rotate,integer")])
6942
6943 (define_insn "*rotldi3_internal14"
6944 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6945 (compare:CC (zero_extend:DI
6946 (subreg:SI
6947 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6948 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6949 (const_int 0)))
6950 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6951 "TARGET_64BIT"
6952 "@
6953 rldcl. %3,%1,%2,32
6954 rldicl. %3,%1,%H2,32
6955 #
6956 #"
6957 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6958 (set_attr "length" "4,4,8,8")])
6959
6960 (define_split
6961 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6962 (compare:CC (zero_extend:DI
6963 (subreg:SI
6964 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6965 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6966 (const_int 0)))
6967 (clobber (match_scratch:DI 3 ""))]
6968 "TARGET_POWERPC64 && reload_completed"
6969 [(set (match_dup 3)
6970 (zero_extend:DI (subreg:SI
6971 (rotate:DI (match_dup 1)
6972 (match_dup 2)) 0)))
6973 (set (match_dup 0)
6974 (compare:CC (match_dup 3)
6975 (const_int 0)))]
6976 "")
6977
6978 (define_insn "*rotldi3_internal15"
6979 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6980 (compare:CC (zero_extend:DI
6981 (subreg:SI
6982 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6983 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6984 (const_int 0)))
6985 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6986 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6987 "TARGET_64BIT"
6988 "@
6989 rldcl. %0,%1,%2,32
6990 rldicl. %0,%1,%H2,32
6991 #
6992 #"
6993 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6994 (set_attr "length" "4,4,8,8")])
6995
6996 (define_split
6997 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6998 (compare:CC (zero_extend:DI
6999 (subreg:SI
7000 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7001 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7002 (const_int 0)))
7003 (set (match_operand:DI 0 "gpc_reg_operand" "")
7004 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7005 "TARGET_POWERPC64 && reload_completed"
7006 [(set (match_dup 0)
7007 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7008 (set (match_dup 3)
7009 (compare:CC (match_dup 0)
7010 (const_int 0)))]
7011 "")
7012
7013 (define_expand "ashldi3"
7014 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7015 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7016 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7017 "TARGET_POWERPC64 || TARGET_POWER"
7018 "
7019 {
7020 if (TARGET_POWERPC64)
7021 ;
7022 else if (TARGET_POWER)
7023 {
7024 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
7025 DONE;
7026 }
7027 else
7028 FAIL;
7029 }")
7030
7031 (define_insn "*ashldi3_internal1"
7032 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7033 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7034 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7035 "TARGET_POWERPC64"
7036 "@
7037 sld %0,%1,%2
7038 sldi %0,%1,%H2"
7039 [(set_attr "type" "var_shift_rotate,shift")])
7040
7041 (define_insn "*ashldi3_internal2"
7042 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7043 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7044 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7045 (const_int 0)))
7046 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7047 "TARGET_64BIT"
7048 "@
7049 sld. %3,%1,%2
7050 sldi. %3,%1,%H2
7051 #
7052 #"
7053 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7054 (set_attr "length" "4,4,8,8")])
7055
7056 (define_split
7057 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7058 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7059 (match_operand:SI 2 "reg_or_cint_operand" ""))
7060 (const_int 0)))
7061 (clobber (match_scratch:DI 3 ""))]
7062 "TARGET_POWERPC64 && reload_completed"
7063 [(set (match_dup 3)
7064 (ashift:DI (match_dup 1) (match_dup 2)))
7065 (set (match_dup 0)
7066 (compare:CC (match_dup 3)
7067 (const_int 0)))]
7068 "")
7069
7070 (define_insn "*ashldi3_internal3"
7071 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7072 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7073 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7074 (const_int 0)))
7075 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7076 (ashift:DI (match_dup 1) (match_dup 2)))]
7077 "TARGET_64BIT"
7078 "@
7079 sld. %0,%1,%2
7080 sldi. %0,%1,%H2
7081 #
7082 #"
7083 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7084 (set_attr "length" "4,4,8,8")])
7085
7086 (define_split
7087 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7088 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7089 (match_operand:SI 2 "reg_or_cint_operand" ""))
7090 (const_int 0)))
7091 (set (match_operand:DI 0 "gpc_reg_operand" "")
7092 (ashift:DI (match_dup 1) (match_dup 2)))]
7093 "TARGET_POWERPC64 && reload_completed"
7094 [(set (match_dup 0)
7095 (ashift:DI (match_dup 1) (match_dup 2)))
7096 (set (match_dup 3)
7097 (compare:CC (match_dup 0)
7098 (const_int 0)))]
7099 "")
7100
7101 (define_insn "*ashldi3_internal4"
7102 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7103 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7104 (match_operand:SI 2 "const_int_operand" "i"))
7105 (match_operand:DI 3 "const_int_operand" "n")))]
7106 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7107 "rldic %0,%1,%H2,%W3")
7108
7109 (define_insn "ashldi3_internal5"
7110 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7111 (compare:CC
7112 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7113 (match_operand:SI 2 "const_int_operand" "i,i"))
7114 (match_operand:DI 3 "const_int_operand" "n,n"))
7115 (const_int 0)))
7116 (clobber (match_scratch:DI 4 "=r,r"))]
7117 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7118 "@
7119 rldic. %4,%1,%H2,%W3
7120 #"
7121 [(set_attr "type" "compare")
7122 (set_attr "length" "4,8")])
7123
7124 (define_split
7125 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7126 (compare:CC
7127 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7128 (match_operand:SI 2 "const_int_operand" ""))
7129 (match_operand:DI 3 "const_int_operand" ""))
7130 (const_int 0)))
7131 (clobber (match_scratch:DI 4 ""))]
7132 "TARGET_POWERPC64 && reload_completed
7133 && includes_rldic_lshift_p (operands[2], operands[3])"
7134 [(set (match_dup 4)
7135 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7136 (match_dup 3)))
7137 (set (match_dup 0)
7138 (compare:CC (match_dup 4)
7139 (const_int 0)))]
7140 "")
7141
7142 (define_insn "*ashldi3_internal6"
7143 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7144 (compare:CC
7145 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7146 (match_operand:SI 2 "const_int_operand" "i,i"))
7147 (match_operand:DI 3 "const_int_operand" "n,n"))
7148 (const_int 0)))
7149 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7150 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7151 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7152 "@
7153 rldic. %0,%1,%H2,%W3
7154 #"
7155 [(set_attr "type" "compare")
7156 (set_attr "length" "4,8")])
7157
7158 (define_split
7159 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7160 (compare:CC
7161 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7162 (match_operand:SI 2 "const_int_operand" ""))
7163 (match_operand:DI 3 "const_int_operand" ""))
7164 (const_int 0)))
7165 (set (match_operand:DI 0 "gpc_reg_operand" "")
7166 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7167 "TARGET_POWERPC64 && reload_completed
7168 && includes_rldic_lshift_p (operands[2], operands[3])"
7169 [(set (match_dup 0)
7170 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7171 (match_dup 3)))
7172 (set (match_dup 4)
7173 (compare:CC (match_dup 0)
7174 (const_int 0)))]
7175 "")
7176
7177 (define_insn "*ashldi3_internal7"
7178 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7179 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7180 (match_operand:SI 2 "const_int_operand" "i"))
7181 (match_operand:DI 3 "mask64_operand" "n")))]
7182 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7183 "rldicr %0,%1,%H2,%S3")
7184
7185 (define_insn "ashldi3_internal8"
7186 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7187 (compare:CC
7188 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7189 (match_operand:SI 2 "const_int_operand" "i,i"))
7190 (match_operand:DI 3 "mask64_operand" "n,n"))
7191 (const_int 0)))
7192 (clobber (match_scratch:DI 4 "=r,r"))]
7193 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7194 "@
7195 rldicr. %4,%1,%H2,%S3
7196 #"
7197 [(set_attr "type" "compare")
7198 (set_attr "length" "4,8")])
7199
7200 (define_split
7201 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7202 (compare:CC
7203 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7204 (match_operand:SI 2 "const_int_operand" ""))
7205 (match_operand:DI 3 "mask64_operand" ""))
7206 (const_int 0)))
7207 (clobber (match_scratch:DI 4 ""))]
7208 "TARGET_POWERPC64 && reload_completed
7209 && includes_rldicr_lshift_p (operands[2], operands[3])"
7210 [(set (match_dup 4)
7211 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7212 (match_dup 3)))
7213 (set (match_dup 0)
7214 (compare:CC (match_dup 4)
7215 (const_int 0)))]
7216 "")
7217
7218 (define_insn "*ashldi3_internal9"
7219 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7220 (compare:CC
7221 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7222 (match_operand:SI 2 "const_int_operand" "i,i"))
7223 (match_operand:DI 3 "mask64_operand" "n,n"))
7224 (const_int 0)))
7225 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7226 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7227 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7228 "@
7229 rldicr. %0,%1,%H2,%S3
7230 #"
7231 [(set_attr "type" "compare")
7232 (set_attr "length" "4,8")])
7233
7234 (define_split
7235 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7236 (compare:CC
7237 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7238 (match_operand:SI 2 "const_int_operand" ""))
7239 (match_operand:DI 3 "mask64_operand" ""))
7240 (const_int 0)))
7241 (set (match_operand:DI 0 "gpc_reg_operand" "")
7242 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7243 "TARGET_POWERPC64 && reload_completed
7244 && includes_rldicr_lshift_p (operands[2], operands[3])"
7245 [(set (match_dup 0)
7246 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7247 (match_dup 3)))
7248 (set (match_dup 4)
7249 (compare:CC (match_dup 0)
7250 (const_int 0)))]
7251 "")
7252
7253 (define_expand "lshrdi3"
7254 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7255 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7256 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7257 "TARGET_POWERPC64 || TARGET_POWER"
7258 "
7259 {
7260 if (TARGET_POWERPC64)
7261 ;
7262 else if (TARGET_POWER)
7263 {
7264 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7265 DONE;
7266 }
7267 else
7268 FAIL;
7269 }")
7270
7271 (define_insn "*lshrdi3_internal1"
7272 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7273 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7274 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7275 "TARGET_POWERPC64"
7276 "@
7277 srd %0,%1,%2
7278 srdi %0,%1,%H2"
7279 [(set_attr "type" "var_shift_rotate,shift")])
7280
7281 (define_insn "*lshrdi3_internal2"
7282 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7283 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7284 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7285 (const_int 0)))
7286 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7287 "TARGET_64BIT "
7288 "@
7289 srd. %3,%1,%2
7290 srdi. %3,%1,%H2
7291 #
7292 #"
7293 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7294 (set_attr "length" "4,4,8,8")])
7295
7296 (define_split
7297 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7298 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7299 (match_operand:SI 2 "reg_or_cint_operand" ""))
7300 (const_int 0)))
7301 (clobber (match_scratch:DI 3 ""))]
7302 "TARGET_POWERPC64 && reload_completed"
7303 [(set (match_dup 3)
7304 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7305 (set (match_dup 0)
7306 (compare:CC (match_dup 3)
7307 (const_int 0)))]
7308 "")
7309
7310 (define_insn "*lshrdi3_internal3"
7311 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7312 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7313 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7314 (const_int 0)))
7315 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7316 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7317 "TARGET_64BIT"
7318 "@
7319 srd. %0,%1,%2
7320 srdi. %0,%1,%H2
7321 #
7322 #"
7323 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7324 (set_attr "length" "4,4,8,8")])
7325
7326 (define_split
7327 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7328 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7329 (match_operand:SI 2 "reg_or_cint_operand" ""))
7330 (const_int 0)))
7331 (set (match_operand:DI 0 "gpc_reg_operand" "")
7332 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7333 "TARGET_POWERPC64 && reload_completed"
7334 [(set (match_dup 0)
7335 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7336 (set (match_dup 3)
7337 (compare:CC (match_dup 0)
7338 (const_int 0)))]
7339 "")
7340
7341 (define_expand "ashrdi3"
7342 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7343 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7344 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7345 "WORDS_BIG_ENDIAN"
7346 "
7347 {
7348 if (TARGET_POWERPC64)
7349 ;
7350 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7351 {
7352 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7353 DONE;
7354 }
7355 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7356 && WORDS_BIG_ENDIAN)
7357 {
7358 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7359 DONE;
7360 }
7361 else
7362 FAIL;
7363 }")
7364
7365 (define_insn "*ashrdi3_internal1"
7366 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7367 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7368 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7369 "TARGET_POWERPC64"
7370 "@
7371 srad %0,%1,%2
7372 sradi %0,%1,%H2"
7373 [(set_attr "type" "var_shift_rotate,shift")])
7374
7375 (define_insn "*ashrdi3_internal2"
7376 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7377 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7378 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7379 (const_int 0)))
7380 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7381 "TARGET_64BIT"
7382 "@
7383 srad. %3,%1,%2
7384 sradi. %3,%1,%H2
7385 #
7386 #"
7387 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7388 (set_attr "length" "4,4,8,8")])
7389
7390 (define_split
7391 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7392 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7393 (match_operand:SI 2 "reg_or_cint_operand" ""))
7394 (const_int 0)))
7395 (clobber (match_scratch:DI 3 ""))]
7396 "TARGET_POWERPC64 && reload_completed"
7397 [(set (match_dup 3)
7398 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7399 (set (match_dup 0)
7400 (compare:CC (match_dup 3)
7401 (const_int 0)))]
7402 "")
7403
7404 (define_insn "*ashrdi3_internal3"
7405 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7406 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7407 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7408 (const_int 0)))
7409 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7410 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7411 "TARGET_64BIT"
7412 "@
7413 srad. %0,%1,%2
7414 sradi. %0,%1,%H2
7415 #
7416 #"
7417 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7418 (set_attr "length" "4,4,8,8")])
7419
7420 (define_split
7421 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7422 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7423 (match_operand:SI 2 "reg_or_cint_operand" ""))
7424 (const_int 0)))
7425 (set (match_operand:DI 0 "gpc_reg_operand" "")
7426 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7427 "TARGET_POWERPC64 && reload_completed"
7428 [(set (match_dup 0)
7429 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7430 (set (match_dup 3)
7431 (compare:CC (match_dup 0)
7432 (const_int 0)))]
7433 "")
7434
7435 (define_insn "anddi3"
7436 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7437 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7438 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7439 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7440 "TARGET_POWERPC64"
7441 "@
7442 and %0,%1,%2
7443 rldic%B2 %0,%1,0,%S2
7444 rlwinm %0,%1,0,%m2,%M2
7445 andi. %0,%1,%b2
7446 andis. %0,%1,%u2
7447 #"
7448 [(set_attr "type" "*,*,*,compare,compare,*")
7449 (set_attr "length" "4,4,4,4,4,8")])
7450
7451 (define_split
7452 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7453 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7454 (match_operand:DI 2 "mask64_2_operand" "")))
7455 (clobber (match_scratch:CC 3 ""))]
7456 "TARGET_POWERPC64
7457 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7458 && !mask_operand (operands[2], DImode)
7459 && !mask64_operand (operands[2], DImode)"
7460 [(set (match_dup 0)
7461 (and:DI (rotate:DI (match_dup 1)
7462 (match_dup 4))
7463 (match_dup 5)))
7464 (set (match_dup 0)
7465 (and:DI (rotate:DI (match_dup 0)
7466 (match_dup 6))
7467 (match_dup 7)))]
7468 {
7469 build_mask64_2_operands (operands[2], &operands[4]);
7470 })
7471
7472 (define_insn "*anddi3_internal2"
7473 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7474 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7475 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7476 (const_int 0)))
7477 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7478 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7479 "TARGET_64BIT"
7480 "@
7481 and. %3,%1,%2
7482 rldic%B2. %3,%1,0,%S2
7483 rlwinm. %3,%1,0,%m2,%M2
7484 andi. %3,%1,%b2
7485 andis. %3,%1,%u2
7486 #
7487 #
7488 #
7489 #
7490 #
7491 #
7492 #"
7493 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7494 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7495
7496 (define_split
7497 [(set (match_operand:CC 0 "cc_reg_operand" "")
7498 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7499 (match_operand:DI 2 "mask64_2_operand" ""))
7500 (const_int 0)))
7501 (clobber (match_scratch:DI 3 ""))
7502 (clobber (match_scratch:CC 4 ""))]
7503 "TARGET_64BIT && reload_completed
7504 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7505 && !mask_operand (operands[2], DImode)
7506 && !mask64_operand (operands[2], DImode)"
7507 [(set (match_dup 3)
7508 (and:DI (rotate:DI (match_dup 1)
7509 (match_dup 5))
7510 (match_dup 6)))
7511 (parallel [(set (match_dup 0)
7512 (compare:CC (and:DI (rotate:DI (match_dup 3)
7513 (match_dup 7))
7514 (match_dup 8))
7515 (const_int 0)))
7516 (clobber (match_dup 3))])]
7517 "
7518 {
7519 build_mask64_2_operands (operands[2], &operands[5]);
7520 }")
7521
7522 (define_insn "*anddi3_internal3"
7523 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7524 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7525 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7526 (const_int 0)))
7527 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
7528 (and:DI (match_dup 1) (match_dup 2)))
7529 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7530 "TARGET_64BIT"
7531 "@
7532 and. %0,%1,%2
7533 rldic%B2. %0,%1,0,%S2
7534 rlwinm. %0,%1,0,%m2,%M2
7535 andi. %0,%1,%b2
7536 andis. %0,%1,%u2
7537 #
7538 #
7539 #
7540 #
7541 #
7542 #
7543 #"
7544 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7545 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7546
7547 (define_split
7548 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7549 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7550 (match_operand:DI 2 "and64_2_operand" ""))
7551 (const_int 0)))
7552 (set (match_operand:DI 0 "gpc_reg_operand" "")
7553 (and:DI (match_dup 1) (match_dup 2)))
7554 (clobber (match_scratch:CC 4 ""))]
7555 "TARGET_64BIT && reload_completed"
7556 [(parallel [(set (match_dup 0)
7557 (and:DI (match_dup 1) (match_dup 2)))
7558 (clobber (match_dup 4))])
7559 (set (match_dup 3)
7560 (compare:CC (match_dup 0)
7561 (const_int 0)))]
7562 "")
7563
7564 (define_split
7565 [(set (match_operand:CC 3 "cc_reg_operand" "")
7566 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7567 (match_operand:DI 2 "mask64_2_operand" ""))
7568 (const_int 0)))
7569 (set (match_operand:DI 0 "gpc_reg_operand" "")
7570 (and:DI (match_dup 1) (match_dup 2)))
7571 (clobber (match_scratch:CC 4 ""))]
7572 "TARGET_64BIT && reload_completed
7573 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7574 && !mask_operand (operands[2], DImode)
7575 && !mask64_operand (operands[2], DImode)"
7576 [(set (match_dup 0)
7577 (and:DI (rotate:DI (match_dup 1)
7578 (match_dup 5))
7579 (match_dup 6)))
7580 (parallel [(set (match_dup 3)
7581 (compare:CC (and:DI (rotate:DI (match_dup 0)
7582 (match_dup 7))
7583 (match_dup 8))
7584 (const_int 0)))
7585 (set (match_dup 0)
7586 (and:DI (rotate:DI (match_dup 0)
7587 (match_dup 7))
7588 (match_dup 8)))])]
7589 "
7590 {
7591 build_mask64_2_operands (operands[2], &operands[5]);
7592 }")
7593
7594 (define_expand "iordi3"
7595 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7596 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7597 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7598 "TARGET_POWERPC64"
7599 "
7600 {
7601 if (non_logical_cint_operand (operands[2], DImode))
7602 {
7603 HOST_WIDE_INT value;
7604 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7605 ? operands[0] : gen_reg_rtx (DImode));
7606
7607 if (GET_CODE (operands[2]) == CONST_INT)
7608 {
7609 value = INTVAL (operands[2]);
7610 emit_insn (gen_iordi3 (tmp, operands[1],
7611 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7612 }
7613 else
7614 {
7615 value = CONST_DOUBLE_LOW (operands[2]);
7616 emit_insn (gen_iordi3 (tmp, operands[1],
7617 immed_double_const (value
7618 & (~ (HOST_WIDE_INT) 0xffff),
7619 0, DImode)));
7620 }
7621
7622 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7623 DONE;
7624 }
7625 }")
7626
7627 (define_expand "xordi3"
7628 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7629 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7630 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7631 "TARGET_POWERPC64"
7632 "
7633 {
7634 if (non_logical_cint_operand (operands[2], DImode))
7635 {
7636 HOST_WIDE_INT value;
7637 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7638 ? operands[0] : gen_reg_rtx (DImode));
7639
7640 if (GET_CODE (operands[2]) == CONST_INT)
7641 {
7642 value = INTVAL (operands[2]);
7643 emit_insn (gen_xordi3 (tmp, operands[1],
7644 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7645 }
7646 else
7647 {
7648 value = CONST_DOUBLE_LOW (operands[2]);
7649 emit_insn (gen_xordi3 (tmp, operands[1],
7650 immed_double_const (value
7651 & (~ (HOST_WIDE_INT) 0xffff),
7652 0, DImode)));
7653 }
7654
7655 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7656 DONE;
7657 }
7658 }")
7659
7660 (define_insn "*booldi3_internal1"
7661 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7662 (match_operator:DI 3 "boolean_or_operator"
7663 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7664 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7665 "TARGET_POWERPC64"
7666 "@
7667 %q3 %0,%1,%2
7668 %q3i %0,%1,%b2
7669 %q3is %0,%1,%u2")
7670
7671 (define_insn "*booldi3_internal2"
7672 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7673 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7674 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7675 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7676 (const_int 0)))
7677 (clobber (match_scratch:DI 3 "=r,r"))]
7678 "TARGET_64BIT"
7679 "@
7680 %q4. %3,%1,%2
7681 #"
7682 [(set_attr "type" "compare")
7683 (set_attr "length" "4,8")])
7684
7685 (define_split
7686 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7687 (compare:CC (match_operator:DI 4 "boolean_operator"
7688 [(match_operand:DI 1 "gpc_reg_operand" "")
7689 (match_operand:DI 2 "gpc_reg_operand" "")])
7690 (const_int 0)))
7691 (clobber (match_scratch:DI 3 ""))]
7692 "TARGET_POWERPC64 && reload_completed"
7693 [(set (match_dup 3) (match_dup 4))
7694 (set (match_dup 0)
7695 (compare:CC (match_dup 3)
7696 (const_int 0)))]
7697 "")
7698
7699 (define_insn "*booldi3_internal3"
7700 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7701 (compare:CC (match_operator:DI 4 "boolean_operator"
7702 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7703 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7704 (const_int 0)))
7705 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7706 (match_dup 4))]
7707 "TARGET_64BIT"
7708 "@
7709 %q4. %0,%1,%2
7710 #"
7711 [(set_attr "type" "compare")
7712 (set_attr "length" "4,8")])
7713
7714 (define_split
7715 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7716 (compare:CC (match_operator:DI 4 "boolean_operator"
7717 [(match_operand:DI 1 "gpc_reg_operand" "")
7718 (match_operand:DI 2 "gpc_reg_operand" "")])
7719 (const_int 0)))
7720 (set (match_operand:DI 0 "gpc_reg_operand" "")
7721 (match_dup 4))]
7722 "TARGET_POWERPC64 && reload_completed"
7723 [(set (match_dup 0) (match_dup 4))
7724 (set (match_dup 3)
7725 (compare:CC (match_dup 0)
7726 (const_int 0)))]
7727 "")
7728
7729 ;; Split a logical operation that we can't do in one insn into two insns,
7730 ;; each of which does one 16-bit part. This is used by combine.
7731
7732 (define_split
7733 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7734 (match_operator:DI 3 "boolean_or_operator"
7735 [(match_operand:DI 1 "gpc_reg_operand" "")
7736 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7737 "TARGET_POWERPC64"
7738 [(set (match_dup 0) (match_dup 4))
7739 (set (match_dup 0) (match_dup 5))]
7740 "
7741 {
7742 rtx i3,i4;
7743
7744 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7745 {
7746 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7747 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7748 0, DImode);
7749 i4 = GEN_INT (value & 0xffff);
7750 }
7751 else
7752 {
7753 i3 = GEN_INT (INTVAL (operands[2])
7754 & (~ (HOST_WIDE_INT) 0xffff));
7755 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7756 }
7757 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7758 operands[1], i3);
7759 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7760 operands[0], i4);
7761 }")
7762
7763 (define_insn "*boolcdi3_internal1"
7764 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7765 (match_operator:DI 3 "boolean_operator"
7766 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7767 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7768 "TARGET_POWERPC64"
7769 "%q3 %0,%2,%1")
7770
7771 (define_insn "*boolcdi3_internal2"
7772 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7773 (compare:CC (match_operator:DI 4 "boolean_operator"
7774 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7775 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7776 (const_int 0)))
7777 (clobber (match_scratch:DI 3 "=r,r"))]
7778 "TARGET_64BIT"
7779 "@
7780 %q4. %3,%2,%1
7781 #"
7782 [(set_attr "type" "compare")
7783 (set_attr "length" "4,8")])
7784
7785 (define_split
7786 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7787 (compare:CC (match_operator:DI 4 "boolean_operator"
7788 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7789 (match_operand:DI 2 "gpc_reg_operand" "")])
7790 (const_int 0)))
7791 (clobber (match_scratch:DI 3 ""))]
7792 "TARGET_POWERPC64 && reload_completed"
7793 [(set (match_dup 3) (match_dup 4))
7794 (set (match_dup 0)
7795 (compare:CC (match_dup 3)
7796 (const_int 0)))]
7797 "")
7798
7799 (define_insn "*boolcdi3_internal3"
7800 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7801 (compare:CC (match_operator:DI 4 "boolean_operator"
7802 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7803 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7804 (const_int 0)))
7805 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7806 (match_dup 4))]
7807 "TARGET_64BIT"
7808 "@
7809 %q4. %0,%2,%1
7810 #"
7811 [(set_attr "type" "compare")
7812 (set_attr "length" "4,8")])
7813
7814 (define_split
7815 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7816 (compare:CC (match_operator:DI 4 "boolean_operator"
7817 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7818 (match_operand:DI 2 "gpc_reg_operand" "")])
7819 (const_int 0)))
7820 (set (match_operand:DI 0 "gpc_reg_operand" "")
7821 (match_dup 4))]
7822 "TARGET_POWERPC64 && reload_completed"
7823 [(set (match_dup 0) (match_dup 4))
7824 (set (match_dup 3)
7825 (compare:CC (match_dup 0)
7826 (const_int 0)))]
7827 "")
7828
7829 (define_insn "*boolccdi3_internal1"
7830 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7831 (match_operator:DI 3 "boolean_operator"
7832 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7833 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7834 "TARGET_POWERPC64"
7835 "%q3 %0,%1,%2")
7836
7837 (define_insn "*boolccdi3_internal2"
7838 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7839 (compare:CC (match_operator:DI 4 "boolean_operator"
7840 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7841 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7842 (const_int 0)))
7843 (clobber (match_scratch:DI 3 "=r,r"))]
7844 "TARGET_64BIT"
7845 "@
7846 %q4. %3,%1,%2
7847 #"
7848 [(set_attr "type" "compare")
7849 (set_attr "length" "4,8")])
7850
7851 (define_split
7852 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7853 (compare:CC (match_operator:DI 4 "boolean_operator"
7854 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7855 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7856 (const_int 0)))
7857 (clobber (match_scratch:DI 3 ""))]
7858 "TARGET_POWERPC64 && reload_completed"
7859 [(set (match_dup 3) (match_dup 4))
7860 (set (match_dup 0)
7861 (compare:CC (match_dup 3)
7862 (const_int 0)))]
7863 "")
7864
7865 (define_insn "*boolccdi3_internal3"
7866 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7867 (compare:CC (match_operator:DI 4 "boolean_operator"
7868 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7869 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7870 (const_int 0)))
7871 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7872 (match_dup 4))]
7873 "TARGET_64BIT"
7874 "@
7875 %q4. %0,%1,%2
7876 #"
7877 [(set_attr "type" "compare")
7878 (set_attr "length" "4,8")])
7879
7880 (define_split
7881 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7882 (compare:CC (match_operator:DI 4 "boolean_operator"
7883 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7884 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7885 (const_int 0)))
7886 (set (match_operand:DI 0 "gpc_reg_operand" "")
7887 (match_dup 4))]
7888 "TARGET_POWERPC64 && reload_completed"
7889 [(set (match_dup 0) (match_dup 4))
7890 (set (match_dup 3)
7891 (compare:CC (match_dup 0)
7892 (const_int 0)))]
7893 "")
7894 \f
7895 ;; Now define ways of moving data around.
7896
7897 ;; Set up a register with a value from the GOT table
7898
7899 (define_expand "movsi_got"
7900 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7901 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7902 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7903 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7904 "
7905 {
7906 if (GET_CODE (operands[1]) == CONST)
7907 {
7908 rtx offset = const0_rtx;
7909 HOST_WIDE_INT value;
7910
7911 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7912 value = INTVAL (offset);
7913 if (value != 0)
7914 {
7915 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7916 emit_insn (gen_movsi_got (tmp, operands[1]));
7917 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7918 DONE;
7919 }
7920 }
7921
7922 operands[2] = rs6000_got_register (operands[1]);
7923 }")
7924
7925 (define_insn "*movsi_got_internal"
7926 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7927 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7928 (match_operand:SI 2 "gpc_reg_operand" "b")]
7929 UNSPEC_MOVSI_GOT))]
7930 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7931 "{l|lwz} %0,%a1@got(%2)"
7932 [(set_attr "type" "load")])
7933
7934 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7935 ;; didn't get allocated to a hard register.
7936 (define_split
7937 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7938 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7939 (match_operand:SI 2 "memory_operand" "")]
7940 UNSPEC_MOVSI_GOT))]
7941 "DEFAULT_ABI == ABI_V4
7942 && flag_pic == 1
7943 && (reload_in_progress || reload_completed)"
7944 [(set (match_dup 0) (match_dup 2))
7945 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7946 UNSPEC_MOVSI_GOT))]
7947 "")
7948
7949 ;; For SI, we special-case integers that can't be loaded in one insn. We
7950 ;; do the load 16-bits at a time. We could do this by loading from memory,
7951 ;; and this is even supposed to be faster, but it is simpler not to get
7952 ;; integers in the TOC.
7953 (define_insn "movsi_low"
7954 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7955 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7956 (match_operand 2 "" ""))))]
7957 "TARGET_MACHO && ! TARGET_64BIT"
7958 "{l|lwz} %0,lo16(%2)(%1)"
7959 [(set_attr "type" "load")
7960 (set_attr "length" "4")])
7961
7962 (define_insn "*movsi_internal1"
7963 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7964 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7965 "gpc_reg_operand (operands[0], SImode)
7966 || gpc_reg_operand (operands[1], SImode)"
7967 "@
7968 mr %0,%1
7969 {cal|la} %0,%a1
7970 {l%U1%X1|lwz%U1%X1} %0,%1
7971 {st%U0%X0|stw%U0%X0} %1,%0
7972 {lil|li} %0,%1
7973 {liu|lis} %0,%v1
7974 #
7975 {cal|la} %0,%a1
7976 mf%1 %0
7977 mt%0 %1
7978 mt%0 %1
7979 mt%0 %1
7980 {cror 0,0,0|nop}"
7981 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
7982 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7983
7984 ;; Split a load of a large constant into the appropriate two-insn
7985 ;; sequence.
7986
7987 (define_split
7988 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7989 (match_operand:SI 1 "const_int_operand" ""))]
7990 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7991 && (INTVAL (operands[1]) & 0xffff) != 0"
7992 [(set (match_dup 0)
7993 (match_dup 2))
7994 (set (match_dup 0)
7995 (ior:SI (match_dup 0)
7996 (match_dup 3)))]
7997 "
7998 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7999
8000 if (tem == operands[0])
8001 DONE;
8002 else
8003 FAIL;
8004 }")
8005
8006 (define_insn "*mov<mode>_internal2"
8007 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8008 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
8009 (const_int 0)))
8010 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8011 ""
8012 "@
8013 {cmpi|cmp<wd>i} %2,%0,0
8014 mr. %0,%1
8015 #"
8016 [(set_attr "type" "cmp,compare,cmp")
8017 (set_attr "length" "4,4,8")])
8018
8019 (define_split
8020 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8021 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
8022 (const_int 0)))
8023 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8024 "reload_completed"
8025 [(set (match_dup 0) (match_dup 1))
8026 (set (match_dup 2)
8027 (compare:CC (match_dup 0)
8028 (const_int 0)))]
8029 "")
8030 \f
8031 (define_insn "*movhi_internal"
8032 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8033 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8034 "gpc_reg_operand (operands[0], HImode)
8035 || gpc_reg_operand (operands[1], HImode)"
8036 "@
8037 mr %0,%1
8038 lhz%U1%X1 %0,%1
8039 sth%U0%X0 %1,%0
8040 {lil|li} %0,%w1
8041 mf%1 %0
8042 mt%0 %1
8043 mt%0 %1
8044 {cror 0,0,0|nop}"
8045 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8046
8047 (define_expand "mov<mode>"
8048 [(set (match_operand:INT 0 "general_operand" "")
8049 (match_operand:INT 1 "any_operand" ""))]
8050 ""
8051 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8052
8053 (define_insn "*movqi_internal"
8054 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8055 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8056 "gpc_reg_operand (operands[0], QImode)
8057 || gpc_reg_operand (operands[1], QImode)"
8058 "@
8059 mr %0,%1
8060 lbz%U1%X1 %0,%1
8061 stb%U0%X0 %1,%0
8062 {lil|li} %0,%1
8063 mf%1 %0
8064 mt%0 %1
8065 mt%0 %1
8066 {cror 0,0,0|nop}"
8067 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8068 \f
8069 ;; Here is how to move condition codes around. When we store CC data in
8070 ;; an integer register or memory, we store just the high-order 4 bits.
8071 ;; This lets us not shift in the most common case of CR0.
8072 (define_expand "movcc"
8073 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8074 (match_operand:CC 1 "nonimmediate_operand" ""))]
8075 ""
8076 "")
8077
8078 (define_insn "*movcc_internal1"
8079 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
8080 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
8081 "register_operand (operands[0], CCmode)
8082 || register_operand (operands[1], CCmode)"
8083 "@
8084 mcrf %0,%1
8085 mtcrf 128,%1
8086 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
8087 crxor %0,%0,%0
8088 mfcr %0%Q1
8089 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
8090 mr %0,%1
8091 {lil|li} %0,%1
8092 mf%1 %0
8093 mt%0 %1
8094 mt%0 %1
8095 {l%U1%X1|lwz%U1%X1} %0,%1
8096 {st%U0%U1|stw%U0%U1} %1,%0"
8097 [(set (attr "type")
8098 (cond [(eq_attr "alternative" "0,3")
8099 (const_string "cr_logical")
8100 (eq_attr "alternative" "1,2")
8101 (const_string "mtcr")
8102 (eq_attr "alternative" "6,7,9")
8103 (const_string "integer")
8104 (eq_attr "alternative" "8")
8105 (const_string "mfjmpr")
8106 (eq_attr "alternative" "10")
8107 (const_string "mtjmpr")
8108 (eq_attr "alternative" "11")
8109 (const_string "load")
8110 (eq_attr "alternative" "12")
8111 (const_string "store")
8112 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
8113 (const_string "mfcrf")
8114 ]
8115 (const_string "mfcr")))
8116 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
8117 \f
8118 ;; For floating-point, we normally deal with the floating-point registers
8119 ;; unless -msoft-float is used. The sole exception is that parameter passing
8120 ;; can produce floating-point values in fixed-point registers. Unless the
8121 ;; value is a simple constant or already in memory, we deal with this by
8122 ;; allocating memory and copying the value explicitly via that memory location.
8123 (define_expand "movsf"
8124 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8125 (match_operand:SF 1 "any_operand" ""))]
8126 ""
8127 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
8128
8129 (define_split
8130 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8131 (match_operand:SF 1 "const_double_operand" ""))]
8132 "reload_completed
8133 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8134 || (GET_CODE (operands[0]) == SUBREG
8135 && GET_CODE (SUBREG_REG (operands[0])) == REG
8136 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8137 [(set (match_dup 2) (match_dup 3))]
8138 "
8139 {
8140 long l;
8141 REAL_VALUE_TYPE rv;
8142
8143 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8144 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
8145
8146 if (! TARGET_POWERPC64)
8147 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
8148 else
8149 operands[2] = gen_lowpart (SImode, operands[0]);
8150
8151 operands[3] = gen_int_mode (l, SImode);
8152 }")
8153
8154 (define_insn "*movsf_hardfloat"
8155 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
8156 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
8157 "(gpc_reg_operand (operands[0], SFmode)
8158 || gpc_reg_operand (operands[1], SFmode))
8159 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
8160 "@
8161 mr %0,%1
8162 {l%U1%X1|lwz%U1%X1} %0,%1
8163 {st%U0%X0|stw%U0%X0} %1,%0
8164 fmr %0,%1
8165 lfs%U1%X1 %0,%1
8166 stfs%U0%X0 %1,%0
8167 mt%0 %1
8168 mt%0 %1
8169 mf%1 %0
8170 {cror 0,0,0|nop}
8171 #
8172 #"
8173 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
8174 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
8175
8176 (define_insn "*movsf_softfloat"
8177 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
8178 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
8179 "(gpc_reg_operand (operands[0], SFmode)
8180 || gpc_reg_operand (operands[1], SFmode))
8181 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
8182 "@
8183 mr %0,%1
8184 mt%0 %1
8185 mt%0 %1
8186 mf%1 %0
8187 {l%U1%X1|lwz%U1%X1} %0,%1
8188 {st%U0%X0|stw%U0%X0} %1,%0
8189 {lil|li} %0,%1
8190 {liu|lis} %0,%v1
8191 {cal|la} %0,%a1
8192 #
8193 #
8194 {cror 0,0,0|nop}"
8195 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
8196 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
8197
8198 \f
8199 (define_expand "movdf"
8200 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8201 (match_operand:DF 1 "any_operand" ""))]
8202 ""
8203 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
8204
8205 (define_split
8206 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8207 (match_operand:DF 1 "const_int_operand" ""))]
8208 "! TARGET_POWERPC64 && reload_completed
8209 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8210 || (GET_CODE (operands[0]) == SUBREG
8211 && GET_CODE (SUBREG_REG (operands[0])) == REG
8212 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8213 [(set (match_dup 2) (match_dup 4))
8214 (set (match_dup 3) (match_dup 1))]
8215 "
8216 {
8217 int endian = (WORDS_BIG_ENDIAN == 0);
8218 HOST_WIDE_INT value = INTVAL (operands[1]);
8219
8220 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8221 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8222 #if HOST_BITS_PER_WIDE_INT == 32
8223 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8224 #else
8225 operands[4] = GEN_INT (value >> 32);
8226 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8227 #endif
8228 }")
8229
8230 (define_split
8231 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8232 (match_operand:DF 1 "const_double_operand" ""))]
8233 "! TARGET_POWERPC64 && reload_completed
8234 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8235 || (GET_CODE (operands[0]) == SUBREG
8236 && GET_CODE (SUBREG_REG (operands[0])) == REG
8237 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8238 [(set (match_dup 2) (match_dup 4))
8239 (set (match_dup 3) (match_dup 5))]
8240 "
8241 {
8242 int endian = (WORDS_BIG_ENDIAN == 0);
8243 long l[2];
8244 REAL_VALUE_TYPE rv;
8245
8246 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8247 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8248
8249 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8250 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8251 operands[4] = gen_int_mode (l[endian], SImode);
8252 operands[5] = gen_int_mode (l[1 - endian], SImode);
8253 }")
8254
8255 (define_split
8256 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8257 (match_operand:DF 1 "const_double_operand" ""))]
8258 "TARGET_POWERPC64 && reload_completed
8259 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8260 || (GET_CODE (operands[0]) == SUBREG
8261 && GET_CODE (SUBREG_REG (operands[0])) == REG
8262 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8263 [(set (match_dup 2) (match_dup 3))]
8264 "
8265 {
8266 int endian = (WORDS_BIG_ENDIAN == 0);
8267 long l[2];
8268 REAL_VALUE_TYPE rv;
8269 #if HOST_BITS_PER_WIDE_INT >= 64
8270 HOST_WIDE_INT val;
8271 #endif
8272
8273 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8274 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8275
8276 operands[2] = gen_lowpart (DImode, operands[0]);
8277 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8278 #if HOST_BITS_PER_WIDE_INT >= 64
8279 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8280 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8281
8282 operands[3] = gen_int_mode (val, DImode);
8283 #else
8284 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8285 #endif
8286 }")
8287
8288 ;; Don't have reload use general registers to load a constant. First,
8289 ;; it might not work if the output operand is the equivalent of
8290 ;; a non-offsettable memref, but also it is less efficient than loading
8291 ;; the constant into an FP register, since it will probably be used there.
8292 ;; The "??" is a kludge until we can figure out a more reasonable way
8293 ;; of handling these non-offsettable values.
8294 (define_insn "*movdf_hardfloat32"
8295 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8296 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
8297 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8298 && (gpc_reg_operand (operands[0], DFmode)
8299 || gpc_reg_operand (operands[1], DFmode))"
8300 "*
8301 {
8302 switch (which_alternative)
8303 {
8304 default:
8305 gcc_unreachable ();
8306 case 0:
8307 /* We normally copy the low-numbered register first. However, if
8308 the first register operand 0 is the same as the second register
8309 of operand 1, we must copy in the opposite order. */
8310 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8311 return \"mr %L0,%L1\;mr %0,%1\";
8312 else
8313 return \"mr %0,%1\;mr %L0,%L1\";
8314 case 1:
8315 if (rs6000_offsettable_memref_p (operands[1])
8316 || (GET_CODE (operands[1]) == MEM
8317 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8318 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8319 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)))
8320 {
8321 /* If the low-address word is used in the address, we must load
8322 it last. Otherwise, load it first. Note that we cannot have
8323 auto-increment in that case since the address register is
8324 known to be dead. */
8325 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8326 operands[1], 0))
8327 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8328 else
8329 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8330 }
8331 else
8332 {
8333 rtx addreg;
8334
8335 addreg = find_addr_reg (XEXP (operands[1], 0));
8336 if (refers_to_regno_p (REGNO (operands[0]),
8337 REGNO (operands[0]) + 1,
8338 operands[1], 0))
8339 {
8340 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8341 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8342 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8343 return \"{lx|lwzx} %0,%1\";
8344 }
8345 else
8346 {
8347 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
8348 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8349 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8350 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8351 return \"\";
8352 }
8353 }
8354 case 2:
8355 if (rs6000_offsettable_memref_p (operands[0])
8356 || (GET_CODE (operands[0]) == MEM
8357 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8358 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8359 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)))
8360 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8361 else
8362 {
8363 rtx addreg;
8364
8365 addreg = find_addr_reg (XEXP (operands[0], 0));
8366 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
8367 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8368 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
8369 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8370 return \"\";
8371 }
8372 case 3:
8373 return \"fmr %0,%1\";
8374 case 4:
8375 return \"lfd%U1%X1 %0,%1\";
8376 case 5:
8377 return \"stfd%U0%X0 %1,%0\";
8378 case 6:
8379 case 7:
8380 case 8:
8381 return \"#\";
8382 }
8383 }"
8384 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
8385 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
8386
8387 (define_insn "*movdf_softfloat32"
8388 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8389 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8390 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8391 && (gpc_reg_operand (operands[0], DFmode)
8392 || gpc_reg_operand (operands[1], DFmode))"
8393 "*
8394 {
8395 switch (which_alternative)
8396 {
8397 default:
8398 gcc_unreachable ();
8399 case 0:
8400 /* We normally copy the low-numbered register first. However, if
8401 the first register operand 0 is the same as the second register of
8402 operand 1, we must copy in the opposite order. */
8403 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8404 return \"mr %L0,%L1\;mr %0,%1\";
8405 else
8406 return \"mr %0,%1\;mr %L0,%L1\";
8407 case 1:
8408 /* If the low-address word is used in the address, we must load
8409 it last. Otherwise, load it first. Note that we cannot have
8410 auto-increment in that case since the address register is
8411 known to be dead. */
8412 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8413 operands[1], 0))
8414 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8415 else
8416 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8417 case 2:
8418 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8419 case 3:
8420 case 4:
8421 case 5:
8422 return \"#\";
8423 }
8424 }"
8425 [(set_attr "type" "two,load,store,*,*,*")
8426 (set_attr "length" "8,8,8,8,12,16")])
8427
8428 ; ld/std require word-aligned displacements -> 'Y' constraint.
8429 ; List Y->r and r->Y before r->r for reload.
8430 (define_insn "*movdf_hardfloat64_mfpgpr"
8431 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f")
8432 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))]
8433 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8434 && (gpc_reg_operand (operands[0], DFmode)
8435 || gpc_reg_operand (operands[1], DFmode))"
8436 "@
8437 std%U0%X0 %1,%0
8438 ld%U1%X1 %0,%1
8439 mr %0,%1
8440 fmr %0,%1
8441 lfd%U1%X1 %0,%1
8442 stfd%U0%X0 %1,%0
8443 mt%0 %1
8444 mf%1 %0
8445 {cror 0,0,0|nop}
8446 #
8447 #
8448 #
8449 mftgpr %0,%1
8450 mffgpr %0,%1"
8451 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
8452 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
8453
8454 ; ld/std require word-aligned displacements -> 'Y' constraint.
8455 ; List Y->r and r->Y before r->r for reload.
8456 (define_insn "*movdf_hardfloat64"
8457 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
8458 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
8459 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8460 && (gpc_reg_operand (operands[0], DFmode)
8461 || gpc_reg_operand (operands[1], DFmode))"
8462 "@
8463 std%U0%X0 %1,%0
8464 ld%U1%X1 %0,%1
8465 mr %0,%1
8466 fmr %0,%1
8467 lfd%U1%X1 %0,%1
8468 stfd%U0%X0 %1,%0
8469 mt%0 %1
8470 mf%1 %0
8471 {cror 0,0,0|nop}
8472 #
8473 #
8474 #"
8475 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
8476 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
8477
8478 (define_insn "*movdf_softfloat64"
8479 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8480 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
8481 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8482 && (gpc_reg_operand (operands[0], DFmode)
8483 || gpc_reg_operand (operands[1], DFmode))"
8484 "@
8485 ld%U1%X1 %0,%1
8486 std%U0%X0 %1,%0
8487 mr %0,%1
8488 mt%0 %1
8489 mf%1 %0
8490 #
8491 #
8492 #
8493 {cror 0,0,0|nop}"
8494 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
8495 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8496 \f
8497 (define_expand "movtf"
8498 [(set (match_operand:TF 0 "general_operand" "")
8499 (match_operand:TF 1 "any_operand" ""))]
8500 "!TARGET_IEEEQUAD
8501 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8502 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8503
8504 ; It's important to list the o->f and f->o moves before f->f because
8505 ; otherwise reload, given m->f, will try to pick f->f and reload it,
8506 ; which doesn't make progress. Likewise r->Y must be before r->r.
8507 (define_insn_and_split "*movtf_internal"
8508 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
8509 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
8510 "!TARGET_IEEEQUAD
8511 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8512 && (gpc_reg_operand (operands[0], TFmode)
8513 || gpc_reg_operand (operands[1], TFmode))"
8514 "#"
8515 "&& reload_completed"
8516 [(pc)]
8517 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8518 [(set_attr "length" "8,8,8,20,20,16")])
8519
8520 (define_expand "extenddftf2"
8521 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8522 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8523 (use (match_dup 2))])]
8524 "!TARGET_IEEEQUAD
8525 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8526 {
8527 operands[2] = CONST0_RTX (DFmode);
8528 /* Generate GOT reference early for SVR4 PIC. */
8529 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8530 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8531 })
8532
8533 (define_insn_and_split "*extenddftf2_internal"
8534 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8535 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8536 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
8537 "!TARGET_IEEEQUAD
8538 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8539 "#"
8540 "&& reload_completed"
8541 [(pc)]
8542 {
8543 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8544 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8545 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8546 operands[1]);
8547 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8548 operands[2]);
8549 DONE;
8550 })
8551
8552 (define_expand "extendsftf2"
8553 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8554 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8555 "!TARGET_IEEEQUAD
8556 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8557 {
8558 rtx tmp = gen_reg_rtx (DFmode);
8559 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8560 emit_insn (gen_extenddftf2 (operands[0], tmp));
8561 DONE;
8562 })
8563
8564 (define_expand "trunctfdf2"
8565 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8566 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8567 "!TARGET_IEEEQUAD
8568 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8569 "")
8570
8571 (define_insn_and_split "trunctfdf2_internal1"
8572 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8573 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
8574 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8575 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8576 "@
8577 #
8578 fmr %0,%1"
8579 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8580 [(const_int 0)]
8581 {
8582 emit_note (NOTE_INSN_DELETED);
8583 DONE;
8584 }
8585 [(set_attr "type" "fp")])
8586
8587 (define_insn "trunctfdf2_internal2"
8588 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8589 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8590 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8591 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8592 "fadd %0,%1,%L1"
8593 [(set_attr "type" "fp")])
8594
8595 (define_insn_and_split "trunctfsf2"
8596 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8597 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8598 (clobber (match_scratch:DF 2 "=f"))]
8599 "!TARGET_IEEEQUAD
8600 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8601 "#"
8602 "&& reload_completed"
8603 [(set (match_dup 2)
8604 (float_truncate:DF (match_dup 1)))
8605 (set (match_dup 0)
8606 (float_truncate:SF (match_dup 2)))]
8607 "")
8608
8609 (define_expand "floatsitf2"
8610 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8611 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
8612 "!TARGET_IEEEQUAD
8613 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8614 {
8615 rtx tmp = gen_reg_rtx (DFmode);
8616 expand_float (tmp, operands[1], false);
8617 emit_insn (gen_extenddftf2 (operands[0], tmp));
8618 DONE;
8619 })
8620
8621 ; fadd, but rounding towards zero.
8622 ; This is probably not the optimal code sequence.
8623 (define_insn "fix_trunc_helper"
8624 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8625 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8626 UNSPEC_FIX_TRUNC_TF))
8627 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8628 "TARGET_HARD_FLOAT && TARGET_FPRS"
8629 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8630 [(set_attr "type" "fp")
8631 (set_attr "length" "20")])
8632
8633 (define_expand "fix_trunctfsi2"
8634 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8635 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8636 (clobber (match_dup 2))
8637 (clobber (match_dup 3))
8638 (clobber (match_dup 4))
8639 (clobber (match_dup 5))])]
8640 "!TARGET_IEEEQUAD
8641 && (TARGET_POWER2 || TARGET_POWERPC)
8642 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8643 {
8644 operands[2] = gen_reg_rtx (DFmode);
8645 operands[3] = gen_reg_rtx (DFmode);
8646 operands[4] = gen_reg_rtx (DImode);
8647 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8648 })
8649
8650 (define_insn_and_split "*fix_trunctfsi2_internal"
8651 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8652 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8653 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8654 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8655 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8656 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
8657 "!TARGET_IEEEQUAD
8658 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8659 "#"
8660 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[5]))"
8661 [(pc)]
8662 {
8663 rtx lowword;
8664 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8665
8666 gcc_assert (MEM_P (operands[5]));
8667 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8668
8669 emit_insn (gen_fctiwz (operands[4], operands[2]));
8670 emit_move_insn (operands[5], operands[4]);
8671 emit_move_insn (operands[0], lowword);
8672 DONE;
8673 })
8674
8675 (define_insn "negtf2"
8676 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8677 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8678 "!TARGET_IEEEQUAD
8679 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8680 "*
8681 {
8682 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8683 return \"fneg %L0,%L1\;fneg %0,%1\";
8684 else
8685 return \"fneg %0,%1\;fneg %L0,%L1\";
8686 }"
8687 [(set_attr "type" "fp")
8688 (set_attr "length" "8")])
8689
8690 (define_expand "abstf2"
8691 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8692 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8693 "!TARGET_IEEEQUAD
8694 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8695 "
8696 {
8697 rtx label = gen_label_rtx ();
8698 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8699 emit_label (label);
8700 DONE;
8701 }")
8702
8703 (define_expand "abstf2_internal"
8704 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8705 (match_operand:TF 1 "gpc_reg_operand" "f"))
8706 (set (match_dup 3) (match_dup 5))
8707 (set (match_dup 5) (abs:DF (match_dup 5)))
8708 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8709 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8710 (label_ref (match_operand 2 "" ""))
8711 (pc)))
8712 (set (match_dup 6) (neg:DF (match_dup 6)))]
8713 "!TARGET_IEEEQUAD
8714 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8715 "
8716 {
8717 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8718 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8719 operands[3] = gen_reg_rtx (DFmode);
8720 operands[4] = gen_reg_rtx (CCFPmode);
8721 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8722 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8723 }")
8724 \f
8725 ;; Next come the multi-word integer load and store and the load and store
8726 ;; multiple insns.
8727
8728 ; List r->r after r->"o<>", otherwise reload will try to reload a
8729 ; non-offsettable address by using r->r which won't make progress.
8730 (define_insn "*movdi_internal32"
8731 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
8732 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
8733 "! TARGET_POWERPC64
8734 && (gpc_reg_operand (operands[0], DImode)
8735 || gpc_reg_operand (operands[1], DImode))"
8736 "@
8737 #
8738 #
8739 #
8740 fmr %0,%1
8741 lfd%U1%X1 %0,%1
8742 stfd%U0%X0 %1,%0
8743 #"
8744 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
8745
8746 (define_split
8747 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8748 (match_operand:DI 1 "const_int_operand" ""))]
8749 "! TARGET_POWERPC64 && reload_completed"
8750 [(set (match_dup 2) (match_dup 4))
8751 (set (match_dup 3) (match_dup 1))]
8752 "
8753 {
8754 HOST_WIDE_INT value = INTVAL (operands[1]);
8755 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8756 DImode);
8757 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8758 DImode);
8759 #if HOST_BITS_PER_WIDE_INT == 32
8760 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8761 #else
8762 operands[4] = GEN_INT (value >> 32);
8763 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8764 #endif
8765 }")
8766
8767 (define_split
8768 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8769 (match_operand:DI 1 "input_operand" ""))]
8770 "reload_completed && !TARGET_POWERPC64
8771 && gpr_or_gpr_p (operands[0], operands[1])"
8772 [(pc)]
8773 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8774
8775 (define_insn "*movdi_mfpgpr"
8776 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h,r,*f")
8777 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0,*f,r"))]
8778 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8779 && (gpc_reg_operand (operands[0], DImode)
8780 || gpc_reg_operand (operands[1], DImode))"
8781 "@
8782 mr %0,%1
8783 ld%U1%X1 %0,%1
8784 std%U0%X0 %1,%0
8785 li %0,%1
8786 lis %0,%v1
8787 #
8788 {cal|la} %0,%a1
8789 fmr %0,%1
8790 lfd%U1%X1 %0,%1
8791 stfd%U0%X0 %1,%0
8792 mf%1 %0
8793 mt%0 %1
8794 {cror 0,0,0|nop}
8795 mftgpr %0,%1
8796 mffgpr %0,%1"
8797 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
8798 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
8799
8800 (define_insn "*movdi_internal64"
8801 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
8802 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8803 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
8804 && (gpc_reg_operand (operands[0], DImode)
8805 || gpc_reg_operand (operands[1], DImode))"
8806 "@
8807 mr %0,%1
8808 ld%U1%X1 %0,%1
8809 std%U0%X0 %1,%0
8810 li %0,%1
8811 lis %0,%v1
8812 #
8813 {cal|la} %0,%a1
8814 fmr %0,%1
8815 lfd%U1%X1 %0,%1
8816 stfd%U0%X0 %1,%0
8817 mf%1 %0
8818 mt%0 %1
8819 {cror 0,0,0|nop}"
8820 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
8821 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8822
8823 ;; immediate value valid for a single instruction hiding in a const_double
8824 (define_insn ""
8825 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8826 (match_operand:DI 1 "const_double_operand" "F"))]
8827 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8828 && GET_CODE (operands[1]) == CONST_DOUBLE
8829 && num_insns_constant (operands[1], DImode) == 1"
8830 "*
8831 {
8832 return ((unsigned HOST_WIDE_INT)
8833 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8834 ? \"li %0,%1\" : \"lis %0,%v1\";
8835 }")
8836
8837 ;; Generate all one-bits and clear left or right.
8838 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8839 (define_split
8840 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8841 (match_operand:DI 1 "mask64_operand" ""))]
8842 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8843 [(set (match_dup 0) (const_int -1))
8844 (set (match_dup 0)
8845 (and:DI (rotate:DI (match_dup 0)
8846 (const_int 0))
8847 (match_dup 1)))]
8848 "")
8849
8850 ;; Split a load of a large constant into the appropriate five-instruction
8851 ;; sequence. Handle anything in a constant number of insns.
8852 ;; When non-easy constants can go in the TOC, this should use
8853 ;; easy_fp_constant predicate.
8854 (define_split
8855 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8856 (match_operand:DI 1 "const_int_operand" ""))]
8857 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8858 [(set (match_dup 0) (match_dup 2))
8859 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8860 "
8861 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8862
8863 if (tem == operands[0])
8864 DONE;
8865 else
8866 FAIL;
8867 }")
8868
8869 (define_split
8870 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8871 (match_operand:DI 1 "const_double_operand" ""))]
8872 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8873 [(set (match_dup 0) (match_dup 2))
8874 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8875 "
8876 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8877
8878 if (tem == operands[0])
8879 DONE;
8880 else
8881 FAIL;
8882 }")
8883 \f
8884 ;; TImode is similar, except that we usually want to compute the address into
8885 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8886 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8887
8888 ;; We say that MQ is clobbered in the last alternative because the first
8889 ;; alternative would never get used otherwise since it would need a reload
8890 ;; while the 2nd alternative would not. We put memory cases first so they
8891 ;; are preferred. Otherwise, we'd try to reload the output instead of
8892 ;; giving the SCRATCH mq.
8893
8894 (define_insn "*movti_power"
8895 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
8896 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
8897 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
8898 "TARGET_POWER && ! TARGET_POWERPC64
8899 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8900 "*
8901 {
8902 switch (which_alternative)
8903 {
8904 default:
8905 gcc_unreachable ();
8906
8907 case 0:
8908 if (TARGET_STRING)
8909 return \"{stsi|stswi} %1,%P0,16\";
8910 case 1:
8911 case 2:
8912 return \"#\";
8913 case 3:
8914 /* If the address is not used in the output, we can use lsi. Otherwise,
8915 fall through to generating four loads. */
8916 if (TARGET_STRING
8917 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8918 return \"{lsi|lswi} %0,%P1,16\";
8919 /* ... fall through ... */
8920 case 4:
8921 case 5:
8922 return \"#\";
8923 }
8924 }"
8925 [(set_attr "type" "store,store,*,load,load,*")])
8926
8927 (define_insn "*movti_string"
8928 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
8929 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
8930 "! TARGET_POWER && ! TARGET_POWERPC64
8931 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8932 "*
8933 {
8934 switch (which_alternative)
8935 {
8936 default:
8937 gcc_unreachable ();
8938 case 0:
8939 if (TARGET_STRING)
8940 return \"{stsi|stswi} %1,%P0,16\";
8941 case 1:
8942 case 2:
8943 return \"#\";
8944 case 3:
8945 /* If the address is not used in the output, we can use lsi. Otherwise,
8946 fall through to generating four loads. */
8947 if (TARGET_STRING
8948 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8949 return \"{lsi|lswi} %0,%P1,16\";
8950 /* ... fall through ... */
8951 case 4:
8952 case 5:
8953 return \"#\";
8954 }
8955 }"
8956 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")])
8957
8958 (define_insn "*movti_ppc64"
8959 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
8960 (match_operand:TI 1 "input_operand" "r,r,m"))]
8961 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8962 || gpc_reg_operand (operands[1], TImode))"
8963 "#"
8964 [(set_attr "type" "*,load,store")])
8965
8966 (define_split
8967 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8968 (match_operand:TI 1 "const_double_operand" ""))]
8969 "TARGET_POWERPC64"
8970 [(set (match_dup 2) (match_dup 4))
8971 (set (match_dup 3) (match_dup 5))]
8972 "
8973 {
8974 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8975 TImode);
8976 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8977 TImode);
8978 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8979 {
8980 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8981 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8982 }
8983 else if (GET_CODE (operands[1]) == CONST_INT)
8984 {
8985 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8986 operands[5] = operands[1];
8987 }
8988 else
8989 FAIL;
8990 }")
8991
8992 (define_split
8993 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8994 (match_operand:TI 1 "input_operand" ""))]
8995 "reload_completed
8996 && gpr_or_gpr_p (operands[0], operands[1])"
8997 [(pc)]
8998 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8999 \f
9000 (define_expand "load_multiple"
9001 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9002 (match_operand:SI 1 "" ""))
9003 (use (match_operand:SI 2 "" ""))])]
9004 "TARGET_STRING && !TARGET_POWERPC64"
9005 "
9006 {
9007 int regno;
9008 int count;
9009 rtx op1;
9010 int i;
9011
9012 /* Support only loading a constant number of fixed-point registers from
9013 memory and only bother with this if more than two; the machine
9014 doesn't support more than eight. */
9015 if (GET_CODE (operands[2]) != CONST_INT
9016 || INTVAL (operands[2]) <= 2
9017 || INTVAL (operands[2]) > 8
9018 || GET_CODE (operands[1]) != MEM
9019 || GET_CODE (operands[0]) != REG
9020 || REGNO (operands[0]) >= 32)
9021 FAIL;
9022
9023 count = INTVAL (operands[2]);
9024 regno = REGNO (operands[0]);
9025
9026 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9027 op1 = replace_equiv_address (operands[1],
9028 force_reg (SImode, XEXP (operands[1], 0)));
9029
9030 for (i = 0; i < count; i++)
9031 XVECEXP (operands[3], 0, i)
9032 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
9033 adjust_address_nv (op1, SImode, i * 4));
9034 }")
9035
9036 (define_insn "*ldmsi8"
9037 [(match_parallel 0 "load_multiple_operation"
9038 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9039 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9040 (set (match_operand:SI 3 "gpc_reg_operand" "")
9041 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9042 (set (match_operand:SI 4 "gpc_reg_operand" "")
9043 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9044 (set (match_operand:SI 5 "gpc_reg_operand" "")
9045 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9046 (set (match_operand:SI 6 "gpc_reg_operand" "")
9047 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9048 (set (match_operand:SI 7 "gpc_reg_operand" "")
9049 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9050 (set (match_operand:SI 8 "gpc_reg_operand" "")
9051 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9052 (set (match_operand:SI 9 "gpc_reg_operand" "")
9053 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9054 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9055 "*
9056 { return rs6000_output_load_multiple (operands); }"
9057 [(set_attr "type" "load_ux")
9058 (set_attr "length" "32")])
9059
9060 (define_insn "*ldmsi7"
9061 [(match_parallel 0 "load_multiple_operation"
9062 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9063 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9064 (set (match_operand:SI 3 "gpc_reg_operand" "")
9065 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9066 (set (match_operand:SI 4 "gpc_reg_operand" "")
9067 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9068 (set (match_operand:SI 5 "gpc_reg_operand" "")
9069 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9070 (set (match_operand:SI 6 "gpc_reg_operand" "")
9071 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9072 (set (match_operand:SI 7 "gpc_reg_operand" "")
9073 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9074 (set (match_operand:SI 8 "gpc_reg_operand" "")
9075 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9076 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9077 "*
9078 { return rs6000_output_load_multiple (operands); }"
9079 [(set_attr "type" "load_ux")
9080 (set_attr "length" "32")])
9081
9082 (define_insn "*ldmsi6"
9083 [(match_parallel 0 "load_multiple_operation"
9084 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9085 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9086 (set (match_operand:SI 3 "gpc_reg_operand" "")
9087 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9088 (set (match_operand:SI 4 "gpc_reg_operand" "")
9089 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9090 (set (match_operand:SI 5 "gpc_reg_operand" "")
9091 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9092 (set (match_operand:SI 6 "gpc_reg_operand" "")
9093 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9094 (set (match_operand:SI 7 "gpc_reg_operand" "")
9095 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9096 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9097 "*
9098 { return rs6000_output_load_multiple (operands); }"
9099 [(set_attr "type" "load_ux")
9100 (set_attr "length" "32")])
9101
9102 (define_insn "*ldmsi5"
9103 [(match_parallel 0 "load_multiple_operation"
9104 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9105 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9106 (set (match_operand:SI 3 "gpc_reg_operand" "")
9107 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9108 (set (match_operand:SI 4 "gpc_reg_operand" "")
9109 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9110 (set (match_operand:SI 5 "gpc_reg_operand" "")
9111 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9112 (set (match_operand:SI 6 "gpc_reg_operand" "")
9113 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9114 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9115 "*
9116 { return rs6000_output_load_multiple (operands); }"
9117 [(set_attr "type" "load_ux")
9118 (set_attr "length" "32")])
9119
9120 (define_insn "*ldmsi4"
9121 [(match_parallel 0 "load_multiple_operation"
9122 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9123 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9124 (set (match_operand:SI 3 "gpc_reg_operand" "")
9125 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9126 (set (match_operand:SI 4 "gpc_reg_operand" "")
9127 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9128 (set (match_operand:SI 5 "gpc_reg_operand" "")
9129 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9130 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9131 "*
9132 { return rs6000_output_load_multiple (operands); }"
9133 [(set_attr "type" "load_ux")
9134 (set_attr "length" "32")])
9135
9136 (define_insn "*ldmsi3"
9137 [(match_parallel 0 "load_multiple_operation"
9138 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9139 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9140 (set (match_operand:SI 3 "gpc_reg_operand" "")
9141 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9142 (set (match_operand:SI 4 "gpc_reg_operand" "")
9143 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9144 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9145 "*
9146 { return rs6000_output_load_multiple (operands); }"
9147 [(set_attr "type" "load_ux")
9148 (set_attr "length" "32")])
9149
9150 (define_expand "store_multiple"
9151 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9152 (match_operand:SI 1 "" ""))
9153 (clobber (scratch:SI))
9154 (use (match_operand:SI 2 "" ""))])]
9155 "TARGET_STRING && !TARGET_POWERPC64"
9156 "
9157 {
9158 int regno;
9159 int count;
9160 rtx to;
9161 rtx op0;
9162 int i;
9163
9164 /* Support only storing a constant number of fixed-point registers to
9165 memory and only bother with this if more than two; the machine
9166 doesn't support more than eight. */
9167 if (GET_CODE (operands[2]) != CONST_INT
9168 || INTVAL (operands[2]) <= 2
9169 || INTVAL (operands[2]) > 8
9170 || GET_CODE (operands[0]) != MEM
9171 || GET_CODE (operands[1]) != REG
9172 || REGNO (operands[1]) >= 32)
9173 FAIL;
9174
9175 count = INTVAL (operands[2]);
9176 regno = REGNO (operands[1]);
9177
9178 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
9179 to = force_reg (SImode, XEXP (operands[0], 0));
9180 op0 = replace_equiv_address (operands[0], to);
9181
9182 XVECEXP (operands[3], 0, 0)
9183 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
9184 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
9185 gen_rtx_SCRATCH (SImode));
9186
9187 for (i = 1; i < count; i++)
9188 XVECEXP (operands[3], 0, i + 1)
9189 = gen_rtx_SET (VOIDmode,
9190 adjust_address_nv (op0, SImode, i * 4),
9191 gen_rtx_REG (SImode, regno + i));
9192 }")
9193
9194 (define_insn "*stmsi8"
9195 [(match_parallel 0 "store_multiple_operation"
9196 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9197 (match_operand:SI 2 "gpc_reg_operand" "r"))
9198 (clobber (match_scratch:SI 3 "=X"))
9199 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9200 (match_operand:SI 4 "gpc_reg_operand" "r"))
9201 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9202 (match_operand:SI 5 "gpc_reg_operand" "r"))
9203 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9204 (match_operand:SI 6 "gpc_reg_operand" "r"))
9205 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9206 (match_operand:SI 7 "gpc_reg_operand" "r"))
9207 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9208 (match_operand:SI 8 "gpc_reg_operand" "r"))
9209 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9210 (match_operand:SI 9 "gpc_reg_operand" "r"))
9211 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9212 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9213 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9214 "{stsi|stswi} %2,%1,%O0"
9215 [(set_attr "type" "store_ux")])
9216
9217 (define_insn "*stmsi7"
9218 [(match_parallel 0 "store_multiple_operation"
9219 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9220 (match_operand:SI 2 "gpc_reg_operand" "r"))
9221 (clobber (match_scratch:SI 3 "=X"))
9222 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9223 (match_operand:SI 4 "gpc_reg_operand" "r"))
9224 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9225 (match_operand:SI 5 "gpc_reg_operand" "r"))
9226 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9227 (match_operand:SI 6 "gpc_reg_operand" "r"))
9228 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9229 (match_operand:SI 7 "gpc_reg_operand" "r"))
9230 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9231 (match_operand:SI 8 "gpc_reg_operand" "r"))
9232 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9233 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9234 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9235 "{stsi|stswi} %2,%1,%O0"
9236 [(set_attr "type" "store_ux")])
9237
9238 (define_insn "*stmsi6"
9239 [(match_parallel 0 "store_multiple_operation"
9240 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9241 (match_operand:SI 2 "gpc_reg_operand" "r"))
9242 (clobber (match_scratch:SI 3 "=X"))
9243 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9244 (match_operand:SI 4 "gpc_reg_operand" "r"))
9245 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9246 (match_operand:SI 5 "gpc_reg_operand" "r"))
9247 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9248 (match_operand:SI 6 "gpc_reg_operand" "r"))
9249 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9250 (match_operand:SI 7 "gpc_reg_operand" "r"))
9251 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9252 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9253 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9254 "{stsi|stswi} %2,%1,%O0"
9255 [(set_attr "type" "store_ux")])
9256
9257 (define_insn "*stmsi5"
9258 [(match_parallel 0 "store_multiple_operation"
9259 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9260 (match_operand:SI 2 "gpc_reg_operand" "r"))
9261 (clobber (match_scratch:SI 3 "=X"))
9262 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9263 (match_operand:SI 4 "gpc_reg_operand" "r"))
9264 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9265 (match_operand:SI 5 "gpc_reg_operand" "r"))
9266 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9267 (match_operand:SI 6 "gpc_reg_operand" "r"))
9268 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9269 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9270 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9271 "{stsi|stswi} %2,%1,%O0"
9272 [(set_attr "type" "store_ux")])
9273
9274 (define_insn "*stmsi4"
9275 [(match_parallel 0 "store_multiple_operation"
9276 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9277 (match_operand:SI 2 "gpc_reg_operand" "r"))
9278 (clobber (match_scratch:SI 3 "=X"))
9279 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9280 (match_operand:SI 4 "gpc_reg_operand" "r"))
9281 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9282 (match_operand:SI 5 "gpc_reg_operand" "r"))
9283 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9284 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9285 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9286 "{stsi|stswi} %2,%1,%O0"
9287 [(set_attr "type" "store_ux")])
9288
9289 (define_insn "*stmsi3"
9290 [(match_parallel 0 "store_multiple_operation"
9291 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9292 (match_operand:SI 2 "gpc_reg_operand" "r"))
9293 (clobber (match_scratch:SI 3 "=X"))
9294 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9295 (match_operand:SI 4 "gpc_reg_operand" "r"))
9296 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9297 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9298 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9299 "{stsi|stswi} %2,%1,%O0"
9300 [(set_attr "type" "store_ux")])
9301
9302 (define_insn "*stmsi8_power"
9303 [(match_parallel 0 "store_multiple_operation"
9304 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9305 (match_operand:SI 2 "gpc_reg_operand" "r"))
9306 (clobber (match_scratch:SI 3 "=q"))
9307 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9308 (match_operand:SI 4 "gpc_reg_operand" "r"))
9309 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9310 (match_operand:SI 5 "gpc_reg_operand" "r"))
9311 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9312 (match_operand:SI 6 "gpc_reg_operand" "r"))
9313 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9314 (match_operand:SI 7 "gpc_reg_operand" "r"))
9315 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9316 (match_operand:SI 8 "gpc_reg_operand" "r"))
9317 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9318 (match_operand:SI 9 "gpc_reg_operand" "r"))
9319 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9320 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9321 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9322 "{stsi|stswi} %2,%1,%O0"
9323 [(set_attr "type" "store_ux")])
9324
9325 (define_insn "*stmsi7_power"
9326 [(match_parallel 0 "store_multiple_operation"
9327 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9328 (match_operand:SI 2 "gpc_reg_operand" "r"))
9329 (clobber (match_scratch:SI 3 "=q"))
9330 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9331 (match_operand:SI 4 "gpc_reg_operand" "r"))
9332 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9333 (match_operand:SI 5 "gpc_reg_operand" "r"))
9334 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9335 (match_operand:SI 6 "gpc_reg_operand" "r"))
9336 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9337 (match_operand:SI 7 "gpc_reg_operand" "r"))
9338 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9339 (match_operand:SI 8 "gpc_reg_operand" "r"))
9340 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9341 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9342 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9343 "{stsi|stswi} %2,%1,%O0"
9344 [(set_attr "type" "store_ux")])
9345
9346 (define_insn "*stmsi6_power"
9347 [(match_parallel 0 "store_multiple_operation"
9348 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9349 (match_operand:SI 2 "gpc_reg_operand" "r"))
9350 (clobber (match_scratch:SI 3 "=q"))
9351 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9352 (match_operand:SI 4 "gpc_reg_operand" "r"))
9353 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9354 (match_operand:SI 5 "gpc_reg_operand" "r"))
9355 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9356 (match_operand:SI 6 "gpc_reg_operand" "r"))
9357 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9358 (match_operand:SI 7 "gpc_reg_operand" "r"))
9359 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9360 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9361 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9362 "{stsi|stswi} %2,%1,%O0"
9363 [(set_attr "type" "store_ux")])
9364
9365 (define_insn "*stmsi5_power"
9366 [(match_parallel 0 "store_multiple_operation"
9367 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9368 (match_operand:SI 2 "gpc_reg_operand" "r"))
9369 (clobber (match_scratch:SI 3 "=q"))
9370 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9371 (match_operand:SI 4 "gpc_reg_operand" "r"))
9372 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9373 (match_operand:SI 5 "gpc_reg_operand" "r"))
9374 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9375 (match_operand:SI 6 "gpc_reg_operand" "r"))
9376 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9377 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9378 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9379 "{stsi|stswi} %2,%1,%O0"
9380 [(set_attr "type" "store_ux")])
9381
9382 (define_insn "*stmsi4_power"
9383 [(match_parallel 0 "store_multiple_operation"
9384 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9385 (match_operand:SI 2 "gpc_reg_operand" "r"))
9386 (clobber (match_scratch:SI 3 "=q"))
9387 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9388 (match_operand:SI 4 "gpc_reg_operand" "r"))
9389 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9390 (match_operand:SI 5 "gpc_reg_operand" "r"))
9391 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9392 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9393 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9394 "{stsi|stswi} %2,%1,%O0"
9395 [(set_attr "type" "store_ux")])
9396
9397 (define_insn "*stmsi3_power"
9398 [(match_parallel 0 "store_multiple_operation"
9399 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9400 (match_operand:SI 2 "gpc_reg_operand" "r"))
9401 (clobber (match_scratch:SI 3 "=q"))
9402 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9403 (match_operand:SI 4 "gpc_reg_operand" "r"))
9404 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9405 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9406 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9407 "{stsi|stswi} %2,%1,%O0"
9408 [(set_attr "type" "store_ux")])
9409 \f
9410 (define_expand "setmemsi"
9411 [(parallel [(set (match_operand:BLK 0 "" "")
9412 (match_operand 2 "const_int_operand" ""))
9413 (use (match_operand:SI 1 "" ""))
9414 (use (match_operand:SI 3 "" ""))])]
9415 ""
9416 "
9417 {
9418 /* If value to set is not zero, use the library routine. */
9419 if (operands[2] != const0_rtx)
9420 FAIL;
9421
9422 if (expand_block_clear (operands))
9423 DONE;
9424 else
9425 FAIL;
9426 }")
9427
9428 ;; String/block move insn.
9429 ;; Argument 0 is the destination
9430 ;; Argument 1 is the source
9431 ;; Argument 2 is the length
9432 ;; Argument 3 is the alignment
9433
9434 (define_expand "movmemsi"
9435 [(parallel [(set (match_operand:BLK 0 "" "")
9436 (match_operand:BLK 1 "" ""))
9437 (use (match_operand:SI 2 "" ""))
9438 (use (match_operand:SI 3 "" ""))])]
9439 ""
9440 "
9441 {
9442 if (expand_block_move (operands))
9443 DONE;
9444 else
9445 FAIL;
9446 }")
9447
9448 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9449 ;; register allocator doesn't have a clue about allocating 8 word registers.
9450 ;; rD/rS = r5 is preferred, efficient form.
9451 (define_expand "movmemsi_8reg"
9452 [(parallel [(set (match_operand 0 "" "")
9453 (match_operand 1 "" ""))
9454 (use (match_operand 2 "" ""))
9455 (use (match_operand 3 "" ""))
9456 (clobber (reg:SI 5))
9457 (clobber (reg:SI 6))
9458 (clobber (reg:SI 7))
9459 (clobber (reg:SI 8))
9460 (clobber (reg:SI 9))
9461 (clobber (reg:SI 10))
9462 (clobber (reg:SI 11))
9463 (clobber (reg:SI 12))
9464 (clobber (match_scratch:SI 4 ""))])]
9465 "TARGET_STRING"
9466 "")
9467
9468 (define_insn ""
9469 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9470 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9471 (use (match_operand:SI 2 "immediate_operand" "i"))
9472 (use (match_operand:SI 3 "immediate_operand" "i"))
9473 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9474 (clobber (reg:SI 6))
9475 (clobber (reg:SI 7))
9476 (clobber (reg:SI 8))
9477 (clobber (reg:SI 9))
9478 (clobber (reg:SI 10))
9479 (clobber (reg:SI 11))
9480 (clobber (reg:SI 12))
9481 (clobber (match_scratch:SI 5 "=q"))]
9482 "TARGET_STRING && TARGET_POWER
9483 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9484 || INTVAL (operands[2]) == 0)
9485 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9486 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9487 && REGNO (operands[4]) == 5"
9488 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9489 [(set_attr "type" "store_ux")
9490 (set_attr "length" "8")])
9491
9492 (define_insn ""
9493 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9494 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9495 (use (match_operand:SI 2 "immediate_operand" "i"))
9496 (use (match_operand:SI 3 "immediate_operand" "i"))
9497 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9498 (clobber (reg:SI 6))
9499 (clobber (reg:SI 7))
9500 (clobber (reg:SI 8))
9501 (clobber (reg:SI 9))
9502 (clobber (reg:SI 10))
9503 (clobber (reg:SI 11))
9504 (clobber (reg:SI 12))
9505 (clobber (match_scratch:SI 5 "=X"))]
9506 "TARGET_STRING && ! TARGET_POWER
9507 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9508 || INTVAL (operands[2]) == 0)
9509 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9510 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9511 && REGNO (operands[4]) == 5"
9512 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9513 [(set_attr "type" "store_ux")
9514 (set_attr "length" "8")])
9515
9516 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9517 ;; register allocator doesn't have a clue about allocating 6 word registers.
9518 ;; rD/rS = r5 is preferred, efficient form.
9519 (define_expand "movmemsi_6reg"
9520 [(parallel [(set (match_operand 0 "" "")
9521 (match_operand 1 "" ""))
9522 (use (match_operand 2 "" ""))
9523 (use (match_operand 3 "" ""))
9524 (clobber (reg:SI 5))
9525 (clobber (reg:SI 6))
9526 (clobber (reg:SI 7))
9527 (clobber (reg:SI 8))
9528 (clobber (reg:SI 9))
9529 (clobber (reg:SI 10))
9530 (clobber (match_scratch:SI 4 ""))])]
9531 "TARGET_STRING"
9532 "")
9533
9534 (define_insn ""
9535 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9536 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9537 (use (match_operand:SI 2 "immediate_operand" "i"))
9538 (use (match_operand:SI 3 "immediate_operand" "i"))
9539 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9540 (clobber (reg:SI 6))
9541 (clobber (reg:SI 7))
9542 (clobber (reg:SI 8))
9543 (clobber (reg:SI 9))
9544 (clobber (reg:SI 10))
9545 (clobber (match_scratch:SI 5 "=q"))]
9546 "TARGET_STRING && TARGET_POWER
9547 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9548 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9549 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9550 && REGNO (operands[4]) == 5"
9551 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9552 [(set_attr "type" "store_ux")
9553 (set_attr "length" "8")])
9554
9555 (define_insn ""
9556 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9557 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9558 (use (match_operand:SI 2 "immediate_operand" "i"))
9559 (use (match_operand:SI 3 "immediate_operand" "i"))
9560 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9561 (clobber (reg:SI 6))
9562 (clobber (reg:SI 7))
9563 (clobber (reg:SI 8))
9564 (clobber (reg:SI 9))
9565 (clobber (reg:SI 10))
9566 (clobber (match_scratch:SI 5 "=X"))]
9567 "TARGET_STRING && ! TARGET_POWER
9568 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9569 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9570 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9571 && REGNO (operands[4]) == 5"
9572 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9573 [(set_attr "type" "store_ux")
9574 (set_attr "length" "8")])
9575
9576 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9577 ;; problems with TImode.
9578 ;; rD/rS = r5 is preferred, efficient form.
9579 (define_expand "movmemsi_4reg"
9580 [(parallel [(set (match_operand 0 "" "")
9581 (match_operand 1 "" ""))
9582 (use (match_operand 2 "" ""))
9583 (use (match_operand 3 "" ""))
9584 (clobber (reg:SI 5))
9585 (clobber (reg:SI 6))
9586 (clobber (reg:SI 7))
9587 (clobber (reg:SI 8))
9588 (clobber (match_scratch:SI 4 ""))])]
9589 "TARGET_STRING"
9590 "")
9591
9592 (define_insn ""
9593 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9594 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9595 (use (match_operand:SI 2 "immediate_operand" "i"))
9596 (use (match_operand:SI 3 "immediate_operand" "i"))
9597 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9598 (clobber (reg:SI 6))
9599 (clobber (reg:SI 7))
9600 (clobber (reg:SI 8))
9601 (clobber (match_scratch:SI 5 "=q"))]
9602 "TARGET_STRING && TARGET_POWER
9603 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9604 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9605 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9606 && REGNO (operands[4]) == 5"
9607 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9608 [(set_attr "type" "store_ux")
9609 (set_attr "length" "8")])
9610
9611 (define_insn ""
9612 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9613 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9614 (use (match_operand:SI 2 "immediate_operand" "i"))
9615 (use (match_operand:SI 3 "immediate_operand" "i"))
9616 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9617 (clobber (reg:SI 6))
9618 (clobber (reg:SI 7))
9619 (clobber (reg:SI 8))
9620 (clobber (match_scratch:SI 5 "=X"))]
9621 "TARGET_STRING && ! TARGET_POWER
9622 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9623 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9624 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9625 && REGNO (operands[4]) == 5"
9626 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9627 [(set_attr "type" "store_ux")
9628 (set_attr "length" "8")])
9629
9630 ;; Move up to 8 bytes at a time.
9631 (define_expand "movmemsi_2reg"
9632 [(parallel [(set (match_operand 0 "" "")
9633 (match_operand 1 "" ""))
9634 (use (match_operand 2 "" ""))
9635 (use (match_operand 3 "" ""))
9636 (clobber (match_scratch:DI 4 ""))
9637 (clobber (match_scratch:SI 5 ""))])]
9638 "TARGET_STRING && ! TARGET_POWERPC64"
9639 "")
9640
9641 (define_insn ""
9642 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9643 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9644 (use (match_operand:SI 2 "immediate_operand" "i"))
9645 (use (match_operand:SI 3 "immediate_operand" "i"))
9646 (clobber (match_scratch:DI 4 "=&r"))
9647 (clobber (match_scratch:SI 5 "=q"))]
9648 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9649 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9650 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9651 [(set_attr "type" "store_ux")
9652 (set_attr "length" "8")])
9653
9654 (define_insn ""
9655 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9656 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9657 (use (match_operand:SI 2 "immediate_operand" "i"))
9658 (use (match_operand:SI 3 "immediate_operand" "i"))
9659 (clobber (match_scratch:DI 4 "=&r"))
9660 (clobber (match_scratch:SI 5 "=X"))]
9661 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9662 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9663 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9664 [(set_attr "type" "store_ux")
9665 (set_attr "length" "8")])
9666
9667 ;; Move up to 4 bytes at a time.
9668 (define_expand "movmemsi_1reg"
9669 [(parallel [(set (match_operand 0 "" "")
9670 (match_operand 1 "" ""))
9671 (use (match_operand 2 "" ""))
9672 (use (match_operand 3 "" ""))
9673 (clobber (match_scratch:SI 4 ""))
9674 (clobber (match_scratch:SI 5 ""))])]
9675 "TARGET_STRING"
9676 "")
9677
9678 (define_insn ""
9679 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9680 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9681 (use (match_operand:SI 2 "immediate_operand" "i"))
9682 (use (match_operand:SI 3 "immediate_operand" "i"))
9683 (clobber (match_scratch:SI 4 "=&r"))
9684 (clobber (match_scratch:SI 5 "=q"))]
9685 "TARGET_STRING && TARGET_POWER
9686 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9687 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9688 [(set_attr "type" "store_ux")
9689 (set_attr "length" "8")])
9690
9691 (define_insn ""
9692 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9693 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9694 (use (match_operand:SI 2 "immediate_operand" "i"))
9695 (use (match_operand:SI 3 "immediate_operand" "i"))
9696 (clobber (match_scratch:SI 4 "=&r"))
9697 (clobber (match_scratch:SI 5 "=X"))]
9698 "TARGET_STRING && ! TARGET_POWER
9699 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9700 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9701 [(set_attr "type" "store_ux")
9702 (set_attr "length" "8")])
9703 \f
9704 ;; Define insns that do load or store with update. Some of these we can
9705 ;; get by using pre-decrement or pre-increment, but the hardware can also
9706 ;; do cases where the increment is not the size of the object.
9707 ;;
9708 ;; In all these cases, we use operands 0 and 1 for the register being
9709 ;; incremented because those are the operands that local-alloc will
9710 ;; tie and these are the pair most likely to be tieable (and the ones
9711 ;; that will benefit the most).
9712
9713 (define_insn "*movdi_update1"
9714 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9715 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9716 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9717 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9718 (plus:DI (match_dup 1) (match_dup 2)))]
9719 "TARGET_POWERPC64 && TARGET_UPDATE"
9720 "@
9721 ldux %3,%0,%2
9722 ldu %3,%2(%0)"
9723 [(set_attr "type" "load_ux,load_u")])
9724
9725 (define_insn "movdi_<mode>_update"
9726 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9727 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9728 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9729 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9730 (plus:P (match_dup 1) (match_dup 2)))]
9731 "TARGET_POWERPC64 && TARGET_UPDATE"
9732 "@
9733 stdux %3,%0,%2
9734 stdu %3,%2(%0)"
9735 [(set_attr "type" "store_ux,store_u")])
9736
9737 (define_insn "*movsi_update1"
9738 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9739 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9740 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9741 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9742 (plus:SI (match_dup 1) (match_dup 2)))]
9743 "TARGET_UPDATE"
9744 "@
9745 {lux|lwzux} %3,%0,%2
9746 {lu|lwzu} %3,%2(%0)"
9747 [(set_attr "type" "load_ux,load_u")])
9748
9749 (define_insn "*movsi_update2"
9750 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9751 (sign_extend:DI
9752 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9753 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9754 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9755 (plus:DI (match_dup 1) (match_dup 2)))]
9756 "TARGET_POWERPC64"
9757 "lwaux %3,%0,%2"
9758 [(set_attr "type" "load_ext_ux")])
9759
9760 (define_insn "movsi_update"
9761 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9762 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9763 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9764 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9765 (plus:SI (match_dup 1) (match_dup 2)))]
9766 "TARGET_UPDATE"
9767 "@
9768 {stux|stwux} %3,%0,%2
9769 {stu|stwu} %3,%2(%0)"
9770 [(set_attr "type" "store_ux,store_u")])
9771
9772 (define_insn "*movhi_update1"
9773 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9774 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9775 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9776 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9777 (plus:SI (match_dup 1) (match_dup 2)))]
9778 "TARGET_UPDATE"
9779 "@
9780 lhzux %3,%0,%2
9781 lhzu %3,%2(%0)"
9782 [(set_attr "type" "load_ux,load_u")])
9783
9784 (define_insn "*movhi_update2"
9785 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9786 (zero_extend:SI
9787 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9788 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9789 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9790 (plus:SI (match_dup 1) (match_dup 2)))]
9791 "TARGET_UPDATE"
9792 "@
9793 lhzux %3,%0,%2
9794 lhzu %3,%2(%0)"
9795 [(set_attr "type" "load_ux,load_u")])
9796
9797 (define_insn "*movhi_update3"
9798 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9799 (sign_extend:SI
9800 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9801 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9802 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9803 (plus:SI (match_dup 1) (match_dup 2)))]
9804 "TARGET_UPDATE"
9805 "@
9806 lhaux %3,%0,%2
9807 lhau %3,%2(%0)"
9808 [(set_attr "type" "load_ext_ux,load_ext_u")])
9809
9810 (define_insn "*movhi_update4"
9811 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9812 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9813 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9814 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9815 (plus:SI (match_dup 1) (match_dup 2)))]
9816 "TARGET_UPDATE"
9817 "@
9818 sthux %3,%0,%2
9819 sthu %3,%2(%0)"
9820 [(set_attr "type" "store_ux,store_u")])
9821
9822 (define_insn "*movqi_update1"
9823 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9824 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9825 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9826 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9827 (plus:SI (match_dup 1) (match_dup 2)))]
9828 "TARGET_UPDATE"
9829 "@
9830 lbzux %3,%0,%2
9831 lbzu %3,%2(%0)"
9832 [(set_attr "type" "load_ux,load_u")])
9833
9834 (define_insn "*movqi_update2"
9835 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9836 (zero_extend:SI
9837 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9838 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9839 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9840 (plus:SI (match_dup 1) (match_dup 2)))]
9841 "TARGET_UPDATE"
9842 "@
9843 lbzux %3,%0,%2
9844 lbzu %3,%2(%0)"
9845 [(set_attr "type" "load_ux,load_u")])
9846
9847 (define_insn "*movqi_update3"
9848 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9849 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9850 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9851 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9852 (plus:SI (match_dup 1) (match_dup 2)))]
9853 "TARGET_UPDATE"
9854 "@
9855 stbux %3,%0,%2
9856 stbu %3,%2(%0)"
9857 [(set_attr "type" "store_ux,store_u")])
9858
9859 (define_insn "*movsf_update1"
9860 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9861 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9862 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9863 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9864 (plus:SI (match_dup 1) (match_dup 2)))]
9865 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9866 "@
9867 lfsux %3,%0,%2
9868 lfsu %3,%2(%0)"
9869 [(set_attr "type" "fpload_ux,fpload_u")])
9870
9871 (define_insn "*movsf_update2"
9872 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9873 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9874 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9875 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9876 (plus:SI (match_dup 1) (match_dup 2)))]
9877 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9878 "@
9879 stfsux %3,%0,%2
9880 stfsu %3,%2(%0)"
9881 [(set_attr "type" "fpstore_ux,fpstore_u")])
9882
9883 (define_insn "*movsf_update3"
9884 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9885 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9886 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9887 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9888 (plus:SI (match_dup 1) (match_dup 2)))]
9889 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9890 "@
9891 {lux|lwzux} %3,%0,%2
9892 {lu|lwzu} %3,%2(%0)"
9893 [(set_attr "type" "load_ux,load_u")])
9894
9895 (define_insn "*movsf_update4"
9896 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9897 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9898 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9899 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9900 (plus:SI (match_dup 1) (match_dup 2)))]
9901 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9902 "@
9903 {stux|stwux} %3,%0,%2
9904 {stu|stwu} %3,%2(%0)"
9905 [(set_attr "type" "store_ux,store_u")])
9906
9907 (define_insn "*movdf_update1"
9908 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9909 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9910 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9911 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9912 (plus:SI (match_dup 1) (match_dup 2)))]
9913 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9914 "@
9915 lfdux %3,%0,%2
9916 lfdu %3,%2(%0)"
9917 [(set_attr "type" "fpload_ux,fpload_u")])
9918
9919 (define_insn "*movdf_update2"
9920 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9921 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9922 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9923 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9924 (plus:SI (match_dup 1) (match_dup 2)))]
9925 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9926 "@
9927 stfdux %3,%0,%2
9928 stfdu %3,%2(%0)"
9929 [(set_attr "type" "fpstore_ux,fpstore_u")])
9930
9931 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9932
9933 (define_insn "*lfq_power2"
9934 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
9935 (match_operand:V2DF 1 "memory_operand" ""))]
9936 "TARGET_POWER2
9937 && TARGET_HARD_FLOAT && TARGET_FPRS"
9938 "lfq%U1%X1 %0,%1")
9939
9940 (define_peephole2
9941 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9942 (match_operand:DF 1 "memory_operand" ""))
9943 (set (match_operand:DF 2 "gpc_reg_operand" "")
9944 (match_operand:DF 3 "memory_operand" ""))]
9945 "TARGET_POWER2
9946 && TARGET_HARD_FLOAT && TARGET_FPRS
9947 && registers_ok_for_quad_peep (operands[0], operands[2])
9948 && mems_ok_for_quad_peep (operands[1], operands[3])"
9949 [(set (match_dup 0)
9950 (match_dup 1))]
9951 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
9952 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
9953
9954 (define_insn "*stfq_power2"
9955 [(set (match_operand:V2DF 0 "memory_operand" "")
9956 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
9957 "TARGET_POWER2
9958 && TARGET_HARD_FLOAT && TARGET_FPRS"
9959 "stfq%U0%X0 %1,%0")
9960
9961
9962 (define_peephole2
9963 [(set (match_operand:DF 0 "memory_operand" "")
9964 (match_operand:DF 1 "gpc_reg_operand" ""))
9965 (set (match_operand:DF 2 "memory_operand" "")
9966 (match_operand:DF 3 "gpc_reg_operand" ""))]
9967 "TARGET_POWER2
9968 && TARGET_HARD_FLOAT && TARGET_FPRS
9969 && registers_ok_for_quad_peep (operands[1], operands[3])
9970 && mems_ok_for_quad_peep (operands[0], operands[2])"
9971 [(set (match_dup 0)
9972 (match_dup 1))]
9973 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
9974 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
9975
9976 ;; After inserting conditional returns we can sometimes have
9977 ;; unnecessary register moves. Unfortunately we cannot have a
9978 ;; modeless peephole here, because some single SImode sets have early
9979 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9980 ;; sequences, using get_attr_length here will smash the operands
9981 ;; array. Neither is there an early_cobbler_p predicate.
9982 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
9983 (define_peephole2
9984 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9985 (match_operand:DF 1 "any_operand" ""))
9986 (set (match_operand:DF 2 "gpc_reg_operand" "")
9987 (match_dup 0))]
9988 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
9989 && peep2_reg_dead_p (2, operands[0])"
9990 [(set (match_dup 2) (match_dup 1))])
9991
9992 (define_peephole2
9993 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9994 (match_operand:SF 1 "any_operand" ""))
9995 (set (match_operand:SF 2 "gpc_reg_operand" "")
9996 (match_dup 0))]
9997 "peep2_reg_dead_p (2, operands[0])"
9998 [(set (match_dup 2) (match_dup 1))])
9999
10000 \f
10001 ;; TLS support.
10002
10003 ;; "b" output constraint here and on tls_ld to support tls linker optimization.
10004 (define_insn "tls_gd_32"
10005 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10006 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10007 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10008 UNSPEC_TLSGD))]
10009 "HAVE_AS_TLS && !TARGET_64BIT"
10010 "addi %0,%1,%2@got@tlsgd")
10011
10012 (define_insn "tls_gd_64"
10013 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10014 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10015 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10016 UNSPEC_TLSGD))]
10017 "HAVE_AS_TLS && TARGET_64BIT"
10018 "addi %0,%1,%2@got@tlsgd")
10019
10020 (define_insn "tls_ld_32"
10021 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10022 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
10023 UNSPEC_TLSLD))]
10024 "HAVE_AS_TLS && !TARGET_64BIT"
10025 "addi %0,%1,%&@got@tlsld")
10026
10027 (define_insn "tls_ld_64"
10028 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10029 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
10030 UNSPEC_TLSLD))]
10031 "HAVE_AS_TLS && TARGET_64BIT"
10032 "addi %0,%1,%&@got@tlsld")
10033
10034 (define_insn "tls_dtprel_32"
10035 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10036 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10037 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10038 UNSPEC_TLSDTPREL))]
10039 "HAVE_AS_TLS && !TARGET_64BIT"
10040 "addi %0,%1,%2@dtprel")
10041
10042 (define_insn "tls_dtprel_64"
10043 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10044 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10045 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10046 UNSPEC_TLSDTPREL))]
10047 "HAVE_AS_TLS && TARGET_64BIT"
10048 "addi %0,%1,%2@dtprel")
10049
10050 (define_insn "tls_dtprel_ha_32"
10051 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10052 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10053 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10054 UNSPEC_TLSDTPRELHA))]
10055 "HAVE_AS_TLS && !TARGET_64BIT"
10056 "addis %0,%1,%2@dtprel@ha")
10057
10058 (define_insn "tls_dtprel_ha_64"
10059 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10060 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10061 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10062 UNSPEC_TLSDTPRELHA))]
10063 "HAVE_AS_TLS && TARGET_64BIT"
10064 "addis %0,%1,%2@dtprel@ha")
10065
10066 (define_insn "tls_dtprel_lo_32"
10067 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10068 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10069 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10070 UNSPEC_TLSDTPRELLO))]
10071 "HAVE_AS_TLS && !TARGET_64BIT"
10072 "addi %0,%1,%2@dtprel@l")
10073
10074 (define_insn "tls_dtprel_lo_64"
10075 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10076 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10077 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10078 UNSPEC_TLSDTPRELLO))]
10079 "HAVE_AS_TLS && TARGET_64BIT"
10080 "addi %0,%1,%2@dtprel@l")
10081
10082 (define_insn "tls_got_dtprel_32"
10083 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10084 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10085 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10086 UNSPEC_TLSGOTDTPREL))]
10087 "HAVE_AS_TLS && !TARGET_64BIT"
10088 "lwz %0,%2@got@dtprel(%1)")
10089
10090 (define_insn "tls_got_dtprel_64"
10091 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10092 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10093 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10094 UNSPEC_TLSGOTDTPREL))]
10095 "HAVE_AS_TLS && TARGET_64BIT"
10096 "ld %0,%2@got@dtprel(%1)")
10097
10098 (define_insn "tls_tprel_32"
10099 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10100 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10101 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10102 UNSPEC_TLSTPREL))]
10103 "HAVE_AS_TLS && !TARGET_64BIT"
10104 "addi %0,%1,%2@tprel")
10105
10106 (define_insn "tls_tprel_64"
10107 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10108 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10109 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10110 UNSPEC_TLSTPREL))]
10111 "HAVE_AS_TLS && TARGET_64BIT"
10112 "addi %0,%1,%2@tprel")
10113
10114 (define_insn "tls_tprel_ha_32"
10115 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10116 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10117 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10118 UNSPEC_TLSTPRELHA))]
10119 "HAVE_AS_TLS && !TARGET_64BIT"
10120 "addis %0,%1,%2@tprel@ha")
10121
10122 (define_insn "tls_tprel_ha_64"
10123 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10124 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10125 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10126 UNSPEC_TLSTPRELHA))]
10127 "HAVE_AS_TLS && TARGET_64BIT"
10128 "addis %0,%1,%2@tprel@ha")
10129
10130 (define_insn "tls_tprel_lo_32"
10131 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10132 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10133 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10134 UNSPEC_TLSTPRELLO))]
10135 "HAVE_AS_TLS && !TARGET_64BIT"
10136 "addi %0,%1,%2@tprel@l")
10137
10138 (define_insn "tls_tprel_lo_64"
10139 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10140 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10141 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10142 UNSPEC_TLSTPRELLO))]
10143 "HAVE_AS_TLS && TARGET_64BIT"
10144 "addi %0,%1,%2@tprel@l")
10145
10146 ;; "b" output constraint here and on tls_tls input to support linker tls
10147 ;; optimization. The linker may edit the instructions emitted by a
10148 ;; tls_got_tprel/tls_tls pair to addis,addi.
10149 (define_insn "tls_got_tprel_32"
10150 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10151 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10152 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10153 UNSPEC_TLSGOTTPREL))]
10154 "HAVE_AS_TLS && !TARGET_64BIT"
10155 "lwz %0,%2@got@tprel(%1)")
10156
10157 (define_insn "tls_got_tprel_64"
10158 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10159 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10160 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10161 UNSPEC_TLSGOTTPREL))]
10162 "HAVE_AS_TLS && TARGET_64BIT"
10163 "ld %0,%2@got@tprel(%1)")
10164
10165 (define_insn "tls_tls_32"
10166 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10167 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10168 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10169 UNSPEC_TLSTLS))]
10170 "HAVE_AS_TLS && !TARGET_64BIT"
10171 "add %0,%1,%2@tls")
10172
10173 (define_insn "tls_tls_64"
10174 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10175 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10176 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10177 UNSPEC_TLSTLS))]
10178 "HAVE_AS_TLS && TARGET_64BIT"
10179 "add %0,%1,%2@tls")
10180 \f
10181 ;; Next come insns related to the calling sequence.
10182 ;;
10183 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
10184 ;; We move the back-chain and decrement the stack pointer.
10185
10186 (define_expand "allocate_stack"
10187 [(set (match_operand 0 "gpc_reg_operand" "=r")
10188 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10189 (set (reg 1)
10190 (minus (reg 1) (match_dup 1)))]
10191 ""
10192 "
10193 { rtx chain = gen_reg_rtx (Pmode);
10194 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
10195 rtx neg_op0;
10196
10197 emit_move_insn (chain, stack_bot);
10198
10199 /* Check stack bounds if necessary. */
10200 if (current_function_limit_stack)
10201 {
10202 rtx available;
10203 available = expand_binop (Pmode, sub_optab,
10204 stack_pointer_rtx, stack_limit_rtx,
10205 NULL_RTX, 1, OPTAB_WIDEN);
10206 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10207 }
10208
10209 if (GET_CODE (operands[1]) != CONST_INT
10210 || INTVAL (operands[1]) < -32767
10211 || INTVAL (operands[1]) > 32768)
10212 {
10213 neg_op0 = gen_reg_rtx (Pmode);
10214 if (TARGET_32BIT)
10215 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10216 else
10217 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10218 }
10219 else
10220 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10221
10222 if (TARGET_UPDATE)
10223 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
10224 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
10225
10226 else
10227 {
10228 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
10229 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
10230 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
10231 }
10232
10233 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10234 DONE;
10235 }")
10236
10237 ;; These patterns say how to save and restore the stack pointer. We need not
10238 ;; save the stack pointer at function level since we are careful to
10239 ;; preserve the backchain. At block level, we have to restore the backchain
10240 ;; when we restore the stack pointer.
10241 ;;
10242 ;; For nonlocal gotos, we must save both the stack pointer and its
10243 ;; backchain and restore both. Note that in the nonlocal case, the
10244 ;; save area is a memory location.
10245
10246 (define_expand "save_stack_function"
10247 [(match_operand 0 "any_operand" "")
10248 (match_operand 1 "any_operand" "")]
10249 ""
10250 "DONE;")
10251
10252 (define_expand "restore_stack_function"
10253 [(match_operand 0 "any_operand" "")
10254 (match_operand 1 "any_operand" "")]
10255 ""
10256 "DONE;")
10257
10258 ;; Adjust stack pointer (op0) to a new value (op1).
10259 ;; First copy old stack backchain to new location, and ensure that the
10260 ;; scheduler won't reorder the sp assignment before the backchain write.
10261 (define_expand "restore_stack_block"
10262 [(set (match_dup 2) (match_dup 3))
10263 (set (match_dup 4) (match_dup 2))
10264 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
10265 (set (match_operand 0 "register_operand" "")
10266 (match_operand 1 "register_operand" ""))]
10267 ""
10268 "
10269 {
10270 operands[2] = gen_reg_rtx (Pmode);
10271 operands[3] = gen_frame_mem (Pmode, operands[0]);
10272 operands[4] = gen_frame_mem (Pmode, operands[1]);
10273 operands[5] = gen_frame_mem (BLKmode, operands[0]);
10274 }")
10275
10276 (define_expand "save_stack_nonlocal"
10277 [(set (match_dup 3) (match_dup 4))
10278 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10279 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
10280 ""
10281 "
10282 {
10283 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10284
10285 /* Copy the backchain to the first word, sp to the second. */
10286 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10287 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10288 operands[3] = gen_reg_rtx (Pmode);
10289 operands[4] = gen_frame_mem (Pmode, operands[1]);
10290 }")
10291
10292 (define_expand "restore_stack_nonlocal"
10293 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10294 (set (match_dup 3) (match_dup 4))
10295 (set (match_dup 5) (match_dup 2))
10296 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
10297 (set (match_operand 0 "register_operand" "") (match_dup 3))]
10298 ""
10299 "
10300 {
10301 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10302
10303 /* Restore the backchain from the first word, sp from the second. */
10304 operands[2] = gen_reg_rtx (Pmode);
10305 operands[3] = gen_reg_rtx (Pmode);
10306 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10307 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10308 operands[5] = gen_frame_mem (Pmode, operands[3]);
10309 operands[6] = gen_frame_mem (BLKmode, operands[0]);
10310 }")
10311 \f
10312 ;; TOC register handling.
10313
10314 ;; Code to initialize the TOC register...
10315
10316 (define_insn "load_toc_aix_si"
10317 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10318 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10319 (use (reg:SI 2))])]
10320 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10321 "*
10322 {
10323 char buf[30];
10324 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10325 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10326 operands[2] = gen_rtx_REG (Pmode, 2);
10327 return \"{l|lwz} %0,%1(%2)\";
10328 }"
10329 [(set_attr "type" "load")])
10330
10331 (define_insn "load_toc_aix_di"
10332 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10333 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10334 (use (reg:DI 2))])]
10335 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10336 "*
10337 {
10338 char buf[30];
10339 #ifdef TARGET_RELOCATABLE
10340 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10341 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10342 #else
10343 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10344 #endif
10345 if (TARGET_ELF)
10346 strcat (buf, \"@toc\");
10347 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10348 operands[2] = gen_rtx_REG (Pmode, 2);
10349 return \"ld %0,%1(%2)\";
10350 }"
10351 [(set_attr "type" "load")])
10352
10353 (define_insn "load_toc_v4_pic_si"
10354 [(set (match_operand:SI 0 "register_operand" "=l")
10355 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10356 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10357 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10358 [(set_attr "type" "branch")
10359 (set_attr "length" "4")])
10360
10361 (define_insn "load_toc_v4_PIC_1"
10362 [(set (match_operand:SI 0 "register_operand" "=l")
10363 (match_operand:SI 1 "immediate_operand" "s"))
10364 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
10365 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
10366 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10367 "bcl 20,31,%1\\n%1:"
10368 [(set_attr "type" "branch")
10369 (set_attr "length" "4")])
10370
10371 (define_insn "load_toc_v4_PIC_1b"
10372 [(set (match_operand:SI 0 "register_operand" "=l")
10373 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
10374 UNSPEC_TOCPTR))]
10375 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10376 "bcl 20,31,$+8\\n\\t.long %1-$"
10377 [(set_attr "type" "branch")
10378 (set_attr "length" "8")])
10379
10380 (define_insn "load_toc_v4_PIC_2"
10381 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10382 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10383 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10384 (match_operand:SI 3 "immediate_operand" "s")))))]
10385 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10386 "{l|lwz} %0,%2-%3(%1)"
10387 [(set_attr "type" "load")])
10388
10389 (define_insn "load_toc_v4_PIC_3b"
10390 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10391 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10392 (high:SI
10393 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10394 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10395 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10396 "{cau|addis} %0,%1,%2-%3@ha")
10397
10398 (define_insn "load_toc_v4_PIC_3c"
10399 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10400 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10401 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10402 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10403 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10404 "{cal|addi} %0,%1,%2-%3@l")
10405
10406 ;; If the TOC is shared over a translation unit, as happens with all
10407 ;; the kinds of PIC that we support, we need to restore the TOC
10408 ;; pointer only when jumping over units of translation.
10409 ;; On Darwin, we need to reload the picbase.
10410
10411 (define_expand "builtin_setjmp_receiver"
10412 [(use (label_ref (match_operand 0 "" "")))]
10413 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10414 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10415 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10416 "
10417 {
10418 #if TARGET_MACHO
10419 if (DEFAULT_ABI == ABI_DARWIN)
10420 {
10421 const char *picbase = machopic_function_base_name ();
10422 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
10423 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10424 rtx tmplabrtx;
10425 char tmplab[20];
10426
10427 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10428 CODE_LABEL_NUMBER (operands[0]));
10429 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10430
10431 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
10432 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10433 }
10434 else
10435 #endif
10436 rs6000_emit_load_toc_table (FALSE);
10437 DONE;
10438 }")
10439
10440 ;; Elf specific ways of loading addresses for non-PIC code.
10441 ;; The output of this could be r0, but we make a very strong
10442 ;; preference for a base register because it will usually
10443 ;; be needed there.
10444 (define_insn "elf_high"
10445 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10446 (high:SI (match_operand 1 "" "")))]
10447 "TARGET_ELF && ! TARGET_64BIT"
10448 "{liu|lis} %0,%1@ha")
10449
10450 (define_insn "elf_low"
10451 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10452 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10453 (match_operand 2 "" "")))]
10454 "TARGET_ELF && ! TARGET_64BIT"
10455 "@
10456 {cal|la} %0,%2@l(%1)
10457 {ai|addic} %0,%1,%K2")
10458 \f
10459 ;; A function pointer under AIX is a pointer to a data area whose first word
10460 ;; contains the actual address of the function, whose second word contains a
10461 ;; pointer to its TOC, and whose third word contains a value to place in the
10462 ;; static chain register (r11). Note that if we load the static chain, our
10463 ;; "trampoline" need not have any executable code.
10464
10465 (define_expand "call_indirect_aix32"
10466 [(set (match_dup 2)
10467 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10468 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10469 (reg:SI 2))
10470 (set (reg:SI 2)
10471 (mem:SI (plus:SI (match_dup 0)
10472 (const_int 4))))
10473 (set (reg:SI 11)
10474 (mem:SI (plus:SI (match_dup 0)
10475 (const_int 8))))
10476 (parallel [(call (mem:SI (match_dup 2))
10477 (match_operand 1 "" ""))
10478 (use (reg:SI 2))
10479 (use (reg:SI 11))
10480 (set (reg:SI 2)
10481 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10482 (clobber (scratch:SI))])]
10483 "TARGET_32BIT"
10484 "
10485 { operands[2] = gen_reg_rtx (SImode); }")
10486
10487 (define_expand "call_indirect_aix64"
10488 [(set (match_dup 2)
10489 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10490 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10491 (reg:DI 2))
10492 (set (reg:DI 2)
10493 (mem:DI (plus:DI (match_dup 0)
10494 (const_int 8))))
10495 (set (reg:DI 11)
10496 (mem:DI (plus:DI (match_dup 0)
10497 (const_int 16))))
10498 (parallel [(call (mem:SI (match_dup 2))
10499 (match_operand 1 "" ""))
10500 (use (reg:DI 2))
10501 (use (reg:DI 11))
10502 (set (reg:DI 2)
10503 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10504 (clobber (scratch:SI))])]
10505 "TARGET_64BIT"
10506 "
10507 { operands[2] = gen_reg_rtx (DImode); }")
10508
10509 (define_expand "call_value_indirect_aix32"
10510 [(set (match_dup 3)
10511 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10512 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10513 (reg:SI 2))
10514 (set (reg:SI 2)
10515 (mem:SI (plus:SI (match_dup 1)
10516 (const_int 4))))
10517 (set (reg:SI 11)
10518 (mem:SI (plus:SI (match_dup 1)
10519 (const_int 8))))
10520 (parallel [(set (match_operand 0 "" "")
10521 (call (mem:SI (match_dup 3))
10522 (match_operand 2 "" "")))
10523 (use (reg:SI 2))
10524 (use (reg:SI 11))
10525 (set (reg:SI 2)
10526 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10527 (clobber (scratch:SI))])]
10528 "TARGET_32BIT"
10529 "
10530 { operands[3] = gen_reg_rtx (SImode); }")
10531
10532 (define_expand "call_value_indirect_aix64"
10533 [(set (match_dup 3)
10534 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10535 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10536 (reg:DI 2))
10537 (set (reg:DI 2)
10538 (mem:DI (plus:DI (match_dup 1)
10539 (const_int 8))))
10540 (set (reg:DI 11)
10541 (mem:DI (plus:DI (match_dup 1)
10542 (const_int 16))))
10543 (parallel [(set (match_operand 0 "" "")
10544 (call (mem:SI (match_dup 3))
10545 (match_operand 2 "" "")))
10546 (use (reg:DI 2))
10547 (use (reg:DI 11))
10548 (set (reg:DI 2)
10549 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10550 (clobber (scratch:SI))])]
10551 "TARGET_64BIT"
10552 "
10553 { operands[3] = gen_reg_rtx (DImode); }")
10554
10555 ;; Now the definitions for the call and call_value insns
10556 (define_expand "call"
10557 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10558 (match_operand 1 "" ""))
10559 (use (match_operand 2 "" ""))
10560 (clobber (scratch:SI))])]
10561 ""
10562 "
10563 {
10564 #if TARGET_MACHO
10565 if (MACHOPIC_INDIRECT)
10566 operands[0] = machopic_indirect_call_target (operands[0]);
10567 #endif
10568
10569 gcc_assert (GET_CODE (operands[0]) == MEM);
10570 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10571
10572 operands[0] = XEXP (operands[0], 0);
10573
10574 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10575 && flag_pic
10576 && GET_CODE (operands[0]) == SYMBOL_REF
10577 && !SYMBOL_REF_LOCAL_P (operands[0]))
10578 {
10579 rtx call;
10580 rtvec tmp;
10581
10582 tmp = gen_rtvec (3,
10583 gen_rtx_CALL (VOIDmode,
10584 gen_rtx_MEM (SImode, operands[0]),
10585 operands[1]),
10586 gen_rtx_USE (VOIDmode, operands[2]),
10587 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
10588 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10589 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10590 DONE;
10591 }
10592
10593 if (GET_CODE (operands[0]) != SYMBOL_REF
10594 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10595 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10596 {
10597 if (INTVAL (operands[2]) & CALL_LONG)
10598 operands[0] = rs6000_longcall_ref (operands[0]);
10599
10600 switch (DEFAULT_ABI)
10601 {
10602 case ABI_V4:
10603 case ABI_DARWIN:
10604 operands[0] = force_reg (Pmode, operands[0]);
10605 break;
10606
10607 case ABI_AIX:
10608 /* AIX function pointers are really pointers to a three word
10609 area. */
10610 emit_call_insn (TARGET_32BIT
10611 ? gen_call_indirect_aix32 (force_reg (SImode,
10612 operands[0]),
10613 operands[1])
10614 : gen_call_indirect_aix64 (force_reg (DImode,
10615 operands[0]),
10616 operands[1]));
10617 DONE;
10618
10619 default:
10620 gcc_unreachable ();
10621 }
10622 }
10623 }")
10624
10625 (define_expand "call_value"
10626 [(parallel [(set (match_operand 0 "" "")
10627 (call (mem:SI (match_operand 1 "address_operand" ""))
10628 (match_operand 2 "" "")))
10629 (use (match_operand 3 "" ""))
10630 (clobber (scratch:SI))])]
10631 ""
10632 "
10633 {
10634 #if TARGET_MACHO
10635 if (MACHOPIC_INDIRECT)
10636 operands[1] = machopic_indirect_call_target (operands[1]);
10637 #endif
10638
10639 gcc_assert (GET_CODE (operands[1]) == MEM);
10640 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10641
10642 operands[1] = XEXP (operands[1], 0);
10643
10644 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10645 && flag_pic
10646 && GET_CODE (operands[1]) == SYMBOL_REF
10647 && !SYMBOL_REF_LOCAL_P (operands[1]))
10648 {
10649 rtx call;
10650 rtvec tmp;
10651
10652 tmp = gen_rtvec (3,
10653 gen_rtx_SET (VOIDmode,
10654 operands[0],
10655 gen_rtx_CALL (VOIDmode,
10656 gen_rtx_MEM (SImode,
10657 operands[1]),
10658 operands[2])),
10659 gen_rtx_USE (VOIDmode, operands[3]),
10660 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
10661 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10662 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10663 DONE;
10664 }
10665
10666 if (GET_CODE (operands[1]) != SYMBOL_REF
10667 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10668 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10669 {
10670 if (INTVAL (operands[3]) & CALL_LONG)
10671 operands[1] = rs6000_longcall_ref (operands[1]);
10672
10673 switch (DEFAULT_ABI)
10674 {
10675 case ABI_V4:
10676 case ABI_DARWIN:
10677 operands[1] = force_reg (Pmode, operands[1]);
10678 break;
10679
10680 case ABI_AIX:
10681 /* AIX function pointers are really pointers to a three word
10682 area. */
10683 emit_call_insn (TARGET_32BIT
10684 ? gen_call_value_indirect_aix32 (operands[0],
10685 force_reg (SImode,
10686 operands[1]),
10687 operands[2])
10688 : gen_call_value_indirect_aix64 (operands[0],
10689 force_reg (DImode,
10690 operands[1]),
10691 operands[2]));
10692 DONE;
10693
10694 default:
10695 gcc_unreachable ();
10696 }
10697 }
10698 }")
10699
10700 ;; Call to function in current module. No TOC pointer reload needed.
10701 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10702 ;; either the function was not prototyped, or it was prototyped as a
10703 ;; variable argument function. It is > 0 if FP registers were passed
10704 ;; and < 0 if they were not.
10705
10706 (define_insn "*call_local32"
10707 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10708 (match_operand 1 "" "g,g"))
10709 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10710 (clobber (match_scratch:SI 3 "=l,l"))]
10711 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10712 "*
10713 {
10714 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10715 output_asm_insn (\"crxor 6,6,6\", operands);
10716
10717 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10718 output_asm_insn (\"creqv 6,6,6\", operands);
10719
10720 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10721 }"
10722 [(set_attr "type" "branch")
10723 (set_attr "length" "4,8")])
10724
10725 (define_insn "*call_local64"
10726 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10727 (match_operand 1 "" "g,g"))
10728 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10729 (clobber (match_scratch:SI 3 "=l,l"))]
10730 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10731 "*
10732 {
10733 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10734 output_asm_insn (\"crxor 6,6,6\", operands);
10735
10736 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10737 output_asm_insn (\"creqv 6,6,6\", operands);
10738
10739 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10740 }"
10741 [(set_attr "type" "branch")
10742 (set_attr "length" "4,8")])
10743
10744 (define_insn "*call_value_local32"
10745 [(set (match_operand 0 "" "")
10746 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10747 (match_operand 2 "" "g,g")))
10748 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10749 (clobber (match_scratch:SI 4 "=l,l"))]
10750 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10751 "*
10752 {
10753 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10754 output_asm_insn (\"crxor 6,6,6\", operands);
10755
10756 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10757 output_asm_insn (\"creqv 6,6,6\", operands);
10758
10759 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10760 }"
10761 [(set_attr "type" "branch")
10762 (set_attr "length" "4,8")])
10763
10764
10765 (define_insn "*call_value_local64"
10766 [(set (match_operand 0 "" "")
10767 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10768 (match_operand 2 "" "g,g")))
10769 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10770 (clobber (match_scratch:SI 4 "=l,l"))]
10771 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10772 "*
10773 {
10774 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10775 output_asm_insn (\"crxor 6,6,6\", operands);
10776
10777 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10778 output_asm_insn (\"creqv 6,6,6\", operands);
10779
10780 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10781 }"
10782 [(set_attr "type" "branch")
10783 (set_attr "length" "4,8")])
10784
10785 ;; Call to function which may be in another module. Restore the TOC
10786 ;; pointer (r2) after the call unless this is System V.
10787 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10788 ;; either the function was not prototyped, or it was prototyped as a
10789 ;; variable argument function. It is > 0 if FP registers were passed
10790 ;; and < 0 if they were not.
10791
10792 (define_insn "*call_indirect_nonlocal_aix32"
10793 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
10794 (match_operand 1 "" "g,g"))
10795 (use (reg:SI 2))
10796 (use (reg:SI 11))
10797 (set (reg:SI 2)
10798 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10799 (clobber (match_scratch:SI 2 "=l,l"))]
10800 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10801 "b%T0l\;{l|lwz} 2,20(1)"
10802 [(set_attr "type" "jmpreg")
10803 (set_attr "length" "8")])
10804
10805 (define_insn "*call_nonlocal_aix32"
10806 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10807 (match_operand 1 "" "g"))
10808 (use (match_operand:SI 2 "immediate_operand" "O"))
10809 (clobber (match_scratch:SI 3 "=l"))]
10810 "TARGET_32BIT
10811 && DEFAULT_ABI == ABI_AIX
10812 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10813 "bl %z0\;%."
10814 [(set_attr "type" "branch")
10815 (set_attr "length" "8")])
10816
10817 (define_insn "*call_indirect_nonlocal_aix64"
10818 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
10819 (match_operand 1 "" "g,g"))
10820 (use (reg:DI 2))
10821 (use (reg:DI 11))
10822 (set (reg:DI 2)
10823 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10824 (clobber (match_scratch:SI 2 "=l,l"))]
10825 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10826 "b%T0l\;ld 2,40(1)"
10827 [(set_attr "type" "jmpreg")
10828 (set_attr "length" "8")])
10829
10830 (define_insn "*call_nonlocal_aix64"
10831 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10832 (match_operand 1 "" "g"))
10833 (use (match_operand:SI 2 "immediate_operand" "O"))
10834 (clobber (match_scratch:SI 3 "=l"))]
10835 "TARGET_64BIT
10836 && DEFAULT_ABI == ABI_AIX
10837 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10838 "bl %z0\;%."
10839 [(set_attr "type" "branch")
10840 (set_attr "length" "8")])
10841
10842 (define_insn "*call_value_indirect_nonlocal_aix32"
10843 [(set (match_operand 0 "" "")
10844 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
10845 (match_operand 2 "" "g,g")))
10846 (use (reg:SI 2))
10847 (use (reg:SI 11))
10848 (set (reg:SI 2)
10849 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10850 (clobber (match_scratch:SI 3 "=l,l"))]
10851 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10852 "b%T1l\;{l|lwz} 2,20(1)"
10853 [(set_attr "type" "jmpreg")
10854 (set_attr "length" "8")])
10855
10856 (define_insn "*call_value_nonlocal_aix32"
10857 [(set (match_operand 0 "" "")
10858 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10859 (match_operand 2 "" "g")))
10860 (use (match_operand:SI 3 "immediate_operand" "O"))
10861 (clobber (match_scratch:SI 4 "=l"))]
10862 "TARGET_32BIT
10863 && DEFAULT_ABI == ABI_AIX
10864 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10865 "bl %z1\;%."
10866 [(set_attr "type" "branch")
10867 (set_attr "length" "8")])
10868
10869 (define_insn "*call_value_indirect_nonlocal_aix64"
10870 [(set (match_operand 0 "" "")
10871 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
10872 (match_operand 2 "" "g,g")))
10873 (use (reg:DI 2))
10874 (use (reg:DI 11))
10875 (set (reg:DI 2)
10876 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10877 (clobber (match_scratch:SI 3 "=l,l"))]
10878 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10879 "b%T1l\;ld 2,40(1)"
10880 [(set_attr "type" "jmpreg")
10881 (set_attr "length" "8")])
10882
10883 (define_insn "*call_value_nonlocal_aix64"
10884 [(set (match_operand 0 "" "")
10885 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10886 (match_operand 2 "" "g")))
10887 (use (match_operand:SI 3 "immediate_operand" "O"))
10888 (clobber (match_scratch:SI 4 "=l"))]
10889 "TARGET_64BIT
10890 && DEFAULT_ABI == ABI_AIX
10891 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10892 "bl %z1\;%."
10893 [(set_attr "type" "branch")
10894 (set_attr "length" "8")])
10895
10896 ;; A function pointer under System V is just a normal pointer
10897 ;; operands[0] is the function pointer
10898 ;; operands[1] is the stack size to clean up
10899 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10900 ;; which indicates how to set cr1
10901
10902 (define_insn "*call_indirect_nonlocal_sysv<mode>"
10903 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
10904 (match_operand 1 "" "g,g,g,g"))
10905 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
10906 (clobber (match_scratch:SI 3 "=l,l,l,l"))]
10907 "DEFAULT_ABI == ABI_V4
10908 || DEFAULT_ABI == ABI_DARWIN"
10909 {
10910 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10911 output_asm_insn ("crxor 6,6,6", operands);
10912
10913 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10914 output_asm_insn ("creqv 6,6,6", operands);
10915
10916 return "b%T0l";
10917 }
10918 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10919 (set_attr "length" "4,4,8,8")])
10920
10921 (define_insn "*call_nonlocal_sysv<mode>"
10922 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
10923 (match_operand 1 "" "g,g"))
10924 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10925 (clobber (match_scratch:SI 3 "=l,l"))]
10926 "(DEFAULT_ABI == ABI_DARWIN
10927 || (DEFAULT_ABI == ABI_V4
10928 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10929 {
10930 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10931 output_asm_insn ("crxor 6,6,6", operands);
10932
10933 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10934 output_asm_insn ("creqv 6,6,6", operands);
10935
10936 #if TARGET_MACHO
10937 return output_call(insn, operands, 0, 2);
10938 #else
10939 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10940 {
10941 if (TARGET_SECURE_PLT && flag_pic == 2)
10942 /* The magic 32768 offset here and in the other sysv call insns
10943 corresponds to the offset of r30 in .got2, as given by LCTOC1.
10944 See sysv4.h:toc_section. */
10945 return "bl %z0+32768@plt";
10946 else
10947 return "bl %z0@plt";
10948 }
10949 else
10950 return "bl %z0";
10951 #endif
10952 }
10953 [(set_attr "type" "branch,branch")
10954 (set_attr "length" "4,8")])
10955
10956 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
10957 [(set (match_operand 0 "" "")
10958 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
10959 (match_operand 2 "" "g,g,g,g")))
10960 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
10961 (clobber (match_scratch:SI 4 "=l,l,l,l"))]
10962 "DEFAULT_ABI == ABI_V4
10963 || DEFAULT_ABI == ABI_DARWIN"
10964 {
10965 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10966 output_asm_insn ("crxor 6,6,6", operands);
10967
10968 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10969 output_asm_insn ("creqv 6,6,6", operands);
10970
10971 return "b%T1l";
10972 }
10973 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10974 (set_attr "length" "4,4,8,8")])
10975
10976 (define_insn "*call_value_nonlocal_sysv<mode>"
10977 [(set (match_operand 0 "" "")
10978 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
10979 (match_operand 2 "" "g,g")))
10980 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10981 (clobber (match_scratch:SI 4 "=l,l"))]
10982 "(DEFAULT_ABI == ABI_DARWIN
10983 || (DEFAULT_ABI == ABI_V4
10984 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10985 {
10986 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10987 output_asm_insn ("crxor 6,6,6", operands);
10988
10989 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10990 output_asm_insn ("creqv 6,6,6", operands);
10991
10992 #if TARGET_MACHO
10993 return output_call(insn, operands, 1, 3);
10994 #else
10995 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10996 {
10997 if (TARGET_SECURE_PLT && flag_pic == 2)
10998 return "bl %z1+32768@plt";
10999 else
11000 return "bl %z1@plt";
11001 }
11002 else
11003 return "bl %z1";
11004 #endif
11005 }
11006 [(set_attr "type" "branch,branch")
11007 (set_attr "length" "4,8")])
11008
11009 ;; Call subroutine returning any type.
11010 (define_expand "untyped_call"
11011 [(parallel [(call (match_operand 0 "" "")
11012 (const_int 0))
11013 (match_operand 1 "" "")
11014 (match_operand 2 "" "")])]
11015 ""
11016 "
11017 {
11018 int i;
11019
11020 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
11021
11022 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11023 {
11024 rtx set = XVECEXP (operands[2], 0, i);
11025 emit_move_insn (SET_DEST (set), SET_SRC (set));
11026 }
11027
11028 /* The optimizer does not know that the call sets the function value
11029 registers we stored in the result block. We avoid problems by
11030 claiming that all hard registers are used and clobbered at this
11031 point. */
11032 emit_insn (gen_blockage ());
11033
11034 DONE;
11035 }")
11036
11037 ;; sibling call patterns
11038 (define_expand "sibcall"
11039 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11040 (match_operand 1 "" ""))
11041 (use (match_operand 2 "" ""))
11042 (use (match_operand 3 "" ""))
11043 (return)])]
11044 ""
11045 "
11046 {
11047 #if TARGET_MACHO
11048 if (MACHOPIC_INDIRECT)
11049 operands[0] = machopic_indirect_call_target (operands[0]);
11050 #endif
11051
11052 gcc_assert (GET_CODE (operands[0]) == MEM);
11053 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11054
11055 operands[0] = XEXP (operands[0], 0);
11056 operands[3] = gen_reg_rtx (SImode);
11057
11058 }")
11059
11060 ;; this and similar patterns must be marked as using LR, otherwise
11061 ;; dataflow will try to delete the store into it. This is true
11062 ;; even when the actual reg to jump to is in CTR, when LR was
11063 ;; saved and restored around the PIC-setting BCL.
11064 (define_insn "*sibcall_local32"
11065 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11066 (match_operand 1 "" "g,g"))
11067 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11068 (use (match_operand:SI 3 "register_operand" "l,l"))
11069 (return)]
11070 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11071 "*
11072 {
11073 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11074 output_asm_insn (\"crxor 6,6,6\", operands);
11075
11076 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11077 output_asm_insn (\"creqv 6,6,6\", operands);
11078
11079 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11080 }"
11081 [(set_attr "type" "branch")
11082 (set_attr "length" "4,8")])
11083
11084 (define_insn "*sibcall_local64"
11085 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11086 (match_operand 1 "" "g,g"))
11087 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11088 (use (match_operand:SI 3 "register_operand" "l,l"))
11089 (return)]
11090 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11091 "*
11092 {
11093 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11094 output_asm_insn (\"crxor 6,6,6\", operands);
11095
11096 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11097 output_asm_insn (\"creqv 6,6,6\", operands);
11098
11099 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11100 }"
11101 [(set_attr "type" "branch")
11102 (set_attr "length" "4,8")])
11103
11104 (define_insn "*sibcall_value_local32"
11105 [(set (match_operand 0 "" "")
11106 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11107 (match_operand 2 "" "g,g")))
11108 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11109 (use (match_operand:SI 4 "register_operand" "l,l"))
11110 (return)]
11111 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11112 "*
11113 {
11114 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11115 output_asm_insn (\"crxor 6,6,6\", operands);
11116
11117 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11118 output_asm_insn (\"creqv 6,6,6\", operands);
11119
11120 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11121 }"
11122 [(set_attr "type" "branch")
11123 (set_attr "length" "4,8")])
11124
11125
11126 (define_insn "*sibcall_value_local64"
11127 [(set (match_operand 0 "" "")
11128 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11129 (match_operand 2 "" "g,g")))
11130 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11131 (use (match_operand:SI 4 "register_operand" "l,l"))
11132 (return)]
11133 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11134 "*
11135 {
11136 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11137 output_asm_insn (\"crxor 6,6,6\", operands);
11138
11139 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11140 output_asm_insn (\"creqv 6,6,6\", operands);
11141
11142 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11143 }"
11144 [(set_attr "type" "branch")
11145 (set_attr "length" "4,8")])
11146
11147 (define_insn "*sibcall_nonlocal_aix32"
11148 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11149 (match_operand 1 "" "g"))
11150 (use (match_operand:SI 2 "immediate_operand" "O"))
11151 (use (match_operand:SI 3 "register_operand" "l"))
11152 (return)]
11153 "TARGET_32BIT
11154 && DEFAULT_ABI == ABI_AIX
11155 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11156 "b %z0"
11157 [(set_attr "type" "branch")
11158 (set_attr "length" "4")])
11159
11160 (define_insn "*sibcall_nonlocal_aix64"
11161 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11162 (match_operand 1 "" "g"))
11163 (use (match_operand:SI 2 "immediate_operand" "O"))
11164 (use (match_operand:SI 3 "register_operand" "l"))
11165 (return)]
11166 "TARGET_64BIT
11167 && DEFAULT_ABI == ABI_AIX
11168 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11169 "b %z0"
11170 [(set_attr "type" "branch")
11171 (set_attr "length" "4")])
11172
11173 (define_insn "*sibcall_value_nonlocal_aix32"
11174 [(set (match_operand 0 "" "")
11175 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11176 (match_operand 2 "" "g")))
11177 (use (match_operand:SI 3 "immediate_operand" "O"))
11178 (use (match_operand:SI 4 "register_operand" "l"))
11179 (return)]
11180 "TARGET_32BIT
11181 && DEFAULT_ABI == ABI_AIX
11182 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11183 "b %z1"
11184 [(set_attr "type" "branch")
11185 (set_attr "length" "4")])
11186
11187 (define_insn "*sibcall_value_nonlocal_aix64"
11188 [(set (match_operand 0 "" "")
11189 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11190 (match_operand 2 "" "g")))
11191 (use (match_operand:SI 3 "immediate_operand" "O"))
11192 (use (match_operand:SI 4 "register_operand" "l"))
11193 (return)]
11194 "TARGET_64BIT
11195 && DEFAULT_ABI == ABI_AIX
11196 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11197 "b %z1"
11198 [(set_attr "type" "branch")
11199 (set_attr "length" "4")])
11200
11201 (define_insn "*sibcall_nonlocal_sysv<mode>"
11202 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11203 (match_operand 1 "" ""))
11204 (use (match_operand 2 "immediate_operand" "O,n"))
11205 (use (match_operand:SI 3 "register_operand" "l,l"))
11206 (return)]
11207 "(DEFAULT_ABI == ABI_DARWIN
11208 || DEFAULT_ABI == ABI_V4)
11209 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11210 "*
11211 {
11212 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11213 output_asm_insn (\"crxor 6,6,6\", operands);
11214
11215 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11216 output_asm_insn (\"creqv 6,6,6\", operands);
11217
11218 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11219 {
11220 if (TARGET_SECURE_PLT && flag_pic == 2)
11221 return \"b %z0+32768@plt\";
11222 else
11223 return \"b %z0@plt\";
11224 }
11225 else
11226 return \"b %z0\";
11227 }"
11228 [(set_attr "type" "branch,branch")
11229 (set_attr "length" "4,8")])
11230
11231 (define_expand "sibcall_value"
11232 [(parallel [(set (match_operand 0 "register_operand" "")
11233 (call (mem:SI (match_operand 1 "address_operand" ""))
11234 (match_operand 2 "" "")))
11235 (use (match_operand 3 "" ""))
11236 (use (match_operand 4 "" ""))
11237 (return)])]
11238 ""
11239 "
11240 {
11241 #if TARGET_MACHO
11242 if (MACHOPIC_INDIRECT)
11243 operands[1] = machopic_indirect_call_target (operands[1]);
11244 #endif
11245
11246 gcc_assert (GET_CODE (operands[1]) == MEM);
11247 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11248
11249 operands[1] = XEXP (operands[1], 0);
11250 operands[4] = gen_reg_rtx (SImode);
11251
11252 }")
11253
11254 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
11255 [(set (match_operand 0 "" "")
11256 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11257 (match_operand 2 "" "")))
11258 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11259 (use (match_operand:SI 4 "register_operand" "l,l"))
11260 (return)]
11261 "(DEFAULT_ABI == ABI_DARWIN
11262 || DEFAULT_ABI == ABI_V4)
11263 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11264 "*
11265 {
11266 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11267 output_asm_insn (\"crxor 6,6,6\", operands);
11268
11269 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11270 output_asm_insn (\"creqv 6,6,6\", operands);
11271
11272 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11273 {
11274 if (TARGET_SECURE_PLT && flag_pic == 2)
11275 return \"b %z1+32768@plt\";
11276 else
11277 return \"b %z1@plt\";
11278 }
11279 else
11280 return \"b %z1\";
11281 }"
11282 [(set_attr "type" "branch,branch")
11283 (set_attr "length" "4,8")])
11284
11285 (define_expand "sibcall_epilogue"
11286 [(use (const_int 0))]
11287 "TARGET_SCHED_PROLOG"
11288 "
11289 {
11290 rs6000_emit_epilogue (TRUE);
11291 DONE;
11292 }")
11293
11294 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11295 ;; all of memory. This blocks insns from being moved across this point.
11296
11297 (define_insn "blockage"
11298 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
11299 ""
11300 "")
11301 \f
11302 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
11303 ;; signed & unsigned, and one type of branch.
11304 ;;
11305 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11306 ;; insns, and branches. We store the operands of compares until we see
11307 ;; how it is used.
11308 (define_expand "cmp<mode>"
11309 [(set (cc0)
11310 (compare (match_operand:GPR 0 "gpc_reg_operand" "")
11311 (match_operand:GPR 1 "reg_or_short_operand" "")))]
11312 ""
11313 "
11314 {
11315 /* Take care of the possibility that operands[1] might be negative but
11316 this might be a logical operation. That insn doesn't exist. */
11317 if (GET_CODE (operands[1]) == CONST_INT
11318 && INTVAL (operands[1]) < 0)
11319 operands[1] = force_reg (<MODE>mode, operands[1]);
11320
11321 rs6000_compare_op0 = operands[0];
11322 rs6000_compare_op1 = operands[1];
11323 rs6000_compare_fp_p = 0;
11324 DONE;
11325 }")
11326
11327 (define_expand "cmp<mode>"
11328 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
11329 (match_operand:FP 1 "gpc_reg_operand" "")))]
11330 ""
11331 "
11332 {
11333 rs6000_compare_op0 = operands[0];
11334 rs6000_compare_op1 = operands[1];
11335 rs6000_compare_fp_p = 1;
11336 DONE;
11337 }")
11338
11339 (define_expand "beq"
11340 [(use (match_operand 0 "" ""))]
11341 ""
11342 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
11343
11344 (define_expand "bne"
11345 [(use (match_operand 0 "" ""))]
11346 ""
11347 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
11348
11349 (define_expand "bge"
11350 [(use (match_operand 0 "" ""))]
11351 ""
11352 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
11353
11354 (define_expand "bgt"
11355 [(use (match_operand 0 "" ""))]
11356 ""
11357 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
11358
11359 (define_expand "ble"
11360 [(use (match_operand 0 "" ""))]
11361 ""
11362 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
11363
11364 (define_expand "blt"
11365 [(use (match_operand 0 "" ""))]
11366 ""
11367 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
11368
11369 (define_expand "bgeu"
11370 [(use (match_operand 0 "" ""))]
11371 ""
11372 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
11373
11374 (define_expand "bgtu"
11375 [(use (match_operand 0 "" ""))]
11376 ""
11377 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
11378
11379 (define_expand "bleu"
11380 [(use (match_operand 0 "" ""))]
11381 ""
11382 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
11383
11384 (define_expand "bltu"
11385 [(use (match_operand 0 "" ""))]
11386 ""
11387 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
11388
11389 (define_expand "bunordered"
11390 [(use (match_operand 0 "" ""))]
11391 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11392 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
11393
11394 (define_expand "bordered"
11395 [(use (match_operand 0 "" ""))]
11396 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11397 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
11398
11399 (define_expand "buneq"
11400 [(use (match_operand 0 "" ""))]
11401 ""
11402 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
11403
11404 (define_expand "bunge"
11405 [(use (match_operand 0 "" ""))]
11406 ""
11407 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
11408
11409 (define_expand "bungt"
11410 [(use (match_operand 0 "" ""))]
11411 ""
11412 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
11413
11414 (define_expand "bunle"
11415 [(use (match_operand 0 "" ""))]
11416 ""
11417 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
11418
11419 (define_expand "bunlt"
11420 [(use (match_operand 0 "" ""))]
11421 ""
11422 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
11423
11424 (define_expand "bltgt"
11425 [(use (match_operand 0 "" ""))]
11426 ""
11427 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
11428
11429 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11430 ;; For SEQ, likewise, except that comparisons with zero should be done
11431 ;; with an scc insns. However, due to the order that combine see the
11432 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11433 ;; the cases we don't want to handle.
11434 (define_expand "seq"
11435 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11436 ""
11437 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
11438
11439 (define_expand "sne"
11440 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11441 ""
11442 "
11443 {
11444 if (! rs6000_compare_fp_p)
11445 FAIL;
11446
11447 rs6000_emit_sCOND (NE, operands[0]);
11448 DONE;
11449 }")
11450
11451 ;; A >= 0 is best done the portable way for A an integer.
11452 (define_expand "sge"
11453 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11454 ""
11455 "
11456 {
11457 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11458 FAIL;
11459
11460 rs6000_emit_sCOND (GE, operands[0]);
11461 DONE;
11462 }")
11463
11464 ;; A > 0 is best done using the portable sequence, so fail in that case.
11465 (define_expand "sgt"
11466 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11467 ""
11468 "
11469 {
11470 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11471 FAIL;
11472
11473 rs6000_emit_sCOND (GT, operands[0]);
11474 DONE;
11475 }")
11476
11477 ;; A <= 0 is best done the portable way for A an integer.
11478 (define_expand "sle"
11479 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11480 ""
11481 "
11482 {
11483 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11484 FAIL;
11485
11486 rs6000_emit_sCOND (LE, operands[0]);
11487 DONE;
11488 }")
11489
11490 ;; A < 0 is best done in the portable way for A an integer.
11491 (define_expand "slt"
11492 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11493 ""
11494 "
11495 {
11496 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11497 FAIL;
11498
11499 rs6000_emit_sCOND (LT, operands[0]);
11500 DONE;
11501 }")
11502
11503 (define_expand "sgeu"
11504 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11505 ""
11506 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11507
11508 (define_expand "sgtu"
11509 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11510 ""
11511 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
11512
11513 (define_expand "sleu"
11514 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11515 ""
11516 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11517
11518 (define_expand "sltu"
11519 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11520 ""
11521 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
11522
11523 (define_expand "sunordered"
11524 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11525 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11526 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
11527
11528 (define_expand "sordered"
11529 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11530 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11531 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11532
11533 (define_expand "suneq"
11534 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11535 ""
11536 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11537
11538 (define_expand "sunge"
11539 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11540 ""
11541 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11542
11543 (define_expand "sungt"
11544 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11545 ""
11546 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11547
11548 (define_expand "sunle"
11549 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11550 ""
11551 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11552
11553 (define_expand "sunlt"
11554 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11555 ""
11556 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11557
11558 (define_expand "sltgt"
11559 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11560 ""
11561 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11562
11563 (define_expand "stack_protect_set"
11564 [(match_operand 0 "memory_operand" "")
11565 (match_operand 1 "memory_operand" "")]
11566 ""
11567 {
11568 #ifdef TARGET_THREAD_SSP_OFFSET
11569 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11570 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11571 operands[1] = gen_rtx_MEM (Pmode, addr);
11572 #endif
11573 if (TARGET_64BIT)
11574 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11575 else
11576 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11577 DONE;
11578 })
11579
11580 (define_insn "stack_protect_setsi"
11581 [(set (match_operand:SI 0 "memory_operand" "=m")
11582 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11583 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11584 "TARGET_32BIT"
11585 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
11586 [(set_attr "type" "three")
11587 (set_attr "length" "12")])
11588
11589 (define_insn "stack_protect_setdi"
11590 [(set (match_operand:DI 0 "memory_operand" "=m")
11591 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11592 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11593 "TARGET_64BIT"
11594 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
11595 [(set_attr "type" "three")
11596 (set_attr "length" "12")])
11597
11598 (define_expand "stack_protect_test"
11599 [(match_operand 0 "memory_operand" "")
11600 (match_operand 1 "memory_operand" "")
11601 (match_operand 2 "" "")]
11602 ""
11603 {
11604 #ifdef TARGET_THREAD_SSP_OFFSET
11605 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11606 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11607 operands[1] = gen_rtx_MEM (Pmode, addr);
11608 #endif
11609 rs6000_compare_op0 = operands[0];
11610 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
11611 UNSPEC_SP_TEST);
11612 rs6000_compare_fp_p = 0;
11613 emit_jump_insn (gen_beq (operands[2]));
11614 DONE;
11615 })
11616
11617 (define_insn "stack_protect_testsi"
11618 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11619 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11620 (match_operand:SI 2 "memory_operand" "m,m")]
11621 UNSPEC_SP_TEST))
11622 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11623 (clobber (match_scratch:SI 3 "=&r,&r"))]
11624 "TARGET_32BIT"
11625 "@
11626 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11627 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11628 [(set_attr "length" "16,20")])
11629
11630 (define_insn "stack_protect_testdi"
11631 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11632 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
11633 (match_operand:DI 2 "memory_operand" "m,m")]
11634 UNSPEC_SP_TEST))
11635 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11636 (clobber (match_scratch:DI 3 "=&r,&r"))]
11637 "TARGET_64BIT"
11638 "@
11639 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11640 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11641 [(set_attr "length" "16,20")])
11642
11643 \f
11644 ;; Here are the actual compare insns.
11645 (define_insn "*cmp<mode>_internal1"
11646 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11647 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11648 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
11649 ""
11650 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
11651 [(set_attr "type" "cmp")])
11652
11653 ;; If we are comparing a register for equality with a large constant,
11654 ;; we can do this with an XOR followed by a compare. But this is profitable
11655 ;; only if the large constant is only used for the comparison (and in this
11656 ;; case we already have a register to reuse as scratch).
11657 ;;
11658 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11659 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
11660
11661 (define_peephole2
11662 [(set (match_operand:SI 0 "register_operand")
11663 (match_operand:SI 1 "logical_const_operand" ""))
11664 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
11665 [(match_dup 0)
11666 (match_operand:SI 2 "logical_const_operand" "")]))
11667 (set (match_operand:CC 4 "cc_reg_operand" "")
11668 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
11669 (match_dup 0)))
11670 (set (pc)
11671 (if_then_else (match_operator 6 "equality_operator"
11672 [(match_dup 4) (const_int 0)])
11673 (match_operand 7 "" "")
11674 (match_operand 8 "" "")))]
11675 "peep2_reg_dead_p (3, operands[0])
11676 && peep2_reg_dead_p (4, operands[4])"
11677 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
11678 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11679 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11680
11681 {
11682 /* Get the constant we are comparing against, and see what it looks like
11683 when sign-extended from 16 to 32 bits. Then see what constant we could
11684 XOR with SEXTC to get the sign-extended value. */
11685 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
11686 SImode,
11687 operands[1], operands[2]);
11688 HOST_WIDE_INT c = INTVAL (cnst);
11689 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11690 HOST_WIDE_INT xorv = c ^ sextc;
11691
11692 operands[9] = GEN_INT (xorv);
11693 operands[10] = GEN_INT (sextc);
11694 })
11695
11696 (define_insn "*cmpsi_internal2"
11697 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11698 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11699 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11700 ""
11701 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
11702 [(set_attr "type" "cmp")])
11703
11704 (define_insn "*cmpdi_internal2"
11705 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11706 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11707 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11708 ""
11709 "cmpld%I2 %0,%1,%b2"
11710 [(set_attr "type" "cmp")])
11711
11712 ;; The following two insns don't exist as single insns, but if we provide
11713 ;; them, we can swap an add and compare, which will enable us to overlap more
11714 ;; of the required delay between a compare and branch. We generate code for
11715 ;; them by splitting.
11716
11717 (define_insn ""
11718 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11719 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11720 (match_operand:SI 2 "short_cint_operand" "i")))
11721 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11722 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11723 ""
11724 "#"
11725 [(set_attr "length" "8")])
11726
11727 (define_insn ""
11728 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11729 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11730 (match_operand:SI 2 "u_short_cint_operand" "i")))
11731 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11732 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11733 ""
11734 "#"
11735 [(set_attr "length" "8")])
11736
11737 (define_split
11738 [(set (match_operand:CC 3 "cc_reg_operand" "")
11739 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11740 (match_operand:SI 2 "short_cint_operand" "")))
11741 (set (match_operand:SI 0 "gpc_reg_operand" "")
11742 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11743 ""
11744 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11745 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11746
11747 (define_split
11748 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11749 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11750 (match_operand:SI 2 "u_short_cint_operand" "")))
11751 (set (match_operand:SI 0 "gpc_reg_operand" "")
11752 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11753 ""
11754 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11755 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11756
11757 (define_insn "*cmpsf_internal1"
11758 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11759 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11760 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11761 "TARGET_HARD_FLOAT && TARGET_FPRS"
11762 "fcmpu %0,%1,%2"
11763 [(set_attr "type" "fpcompare")])
11764
11765 (define_insn "*cmpdf_internal1"
11766 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11767 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11768 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11769 "TARGET_HARD_FLOAT && TARGET_FPRS"
11770 "fcmpu %0,%1,%2"
11771 [(set_attr "type" "fpcompare")])
11772
11773 ;; Only need to compare second words if first words equal
11774 (define_insn "*cmptf_internal1"
11775 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11776 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11777 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11778 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
11779 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11780 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11781 [(set_attr "type" "fpcompare")
11782 (set_attr "length" "12")])
11783
11784 (define_insn_and_split "*cmptf_internal2"
11785 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11786 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11787 (match_operand:TF 2 "gpc_reg_operand" "f")))
11788 (clobber (match_scratch:DF 3 "=f"))
11789 (clobber (match_scratch:DF 4 "=f"))
11790 (clobber (match_scratch:DF 5 "=f"))
11791 (clobber (match_scratch:DF 6 "=f"))
11792 (clobber (match_scratch:DF 7 "=f"))
11793 (clobber (match_scratch:DF 8 "=f"))
11794 (clobber (match_scratch:DF 9 "=f"))
11795 (clobber (match_scratch:DF 10 "=f"))]
11796 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
11797 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11798 "#"
11799 "&& reload_completed"
11800 [(set (match_dup 3) (match_dup 13))
11801 (set (match_dup 4) (match_dup 14))
11802 (set (match_dup 9) (abs:DF (match_dup 5)))
11803 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11804 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11805 (label_ref (match_dup 11))
11806 (pc)))
11807 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11808 (set (pc) (label_ref (match_dup 12)))
11809 (match_dup 11)
11810 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11811 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11812 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11813 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
11814 (match_dup 12)]
11815 {
11816 REAL_VALUE_TYPE rv;
11817 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
11818 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
11819
11820 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11821 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11822 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11823 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11824 operands[11] = gen_label_rtx ();
11825 operands[12] = gen_label_rtx ();
11826 real_inf (&rv);
11827 operands[13] = force_const_mem (DFmode,
11828 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11829 operands[14] = force_const_mem (DFmode,
11830 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11831 DFmode));
11832 if (TARGET_TOC)
11833 {
11834 operands[13] = gen_const_mem (DFmode,
11835 create_TOC_reference (XEXP (operands[13], 0)));
11836 operands[14] = gen_const_mem (DFmode,
11837 create_TOC_reference (XEXP (operands[14], 0)));
11838 set_mem_alias_set (operands[13], get_TOC_alias_set ());
11839 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11840 }
11841 })
11842 \f
11843 ;; Now we have the scc insns. We can do some combinations because of the
11844 ;; way the machine works.
11845 ;;
11846 ;; Note that this is probably faster if we can put an insn between the
11847 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11848 ;; cases the insns below which don't use an intermediate CR field will
11849 ;; be used instead.
11850 (define_insn ""
11851 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11852 (match_operator:SI 1 "scc_comparison_operator"
11853 [(match_operand 2 "cc_reg_operand" "y")
11854 (const_int 0)]))]
11855 ""
11856 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11857 [(set (attr "type")
11858 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11859 (const_string "mfcrf")
11860 ]
11861 (const_string "mfcr")))
11862 (set_attr "length" "8")])
11863
11864 ;; Same as above, but get the GT bit.
11865 (define_insn "move_from_CR_gt_bit"
11866 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11867 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
11868 "TARGET_E500"
11869 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
11870 [(set_attr "type" "mfcr")
11871 (set_attr "length" "8")])
11872
11873 ;; Same as above, but get the OV/ORDERED bit.
11874 (define_insn "move_from_CR_ov_bit"
11875 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11876 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
11877 "TARGET_ISEL"
11878 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
11879 [(set_attr "type" "mfcr")
11880 (set_attr "length" "8")])
11881
11882 (define_insn ""
11883 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11884 (match_operator:DI 1 "scc_comparison_operator"
11885 [(match_operand 2 "cc_reg_operand" "y")
11886 (const_int 0)]))]
11887 "TARGET_POWERPC64"
11888 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11889 [(set (attr "type")
11890 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11891 (const_string "mfcrf")
11892 ]
11893 (const_string "mfcr")))
11894 (set_attr "length" "8")])
11895
11896 (define_insn ""
11897 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11898 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11899 [(match_operand 2 "cc_reg_operand" "y,y")
11900 (const_int 0)])
11901 (const_int 0)))
11902 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11903 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11904 "TARGET_32BIT"
11905 "@
11906 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
11907 #"
11908 [(set_attr "type" "delayed_compare")
11909 (set_attr "length" "8,16")])
11910
11911 (define_split
11912 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11913 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11914 [(match_operand 2 "cc_reg_operand" "")
11915 (const_int 0)])
11916 (const_int 0)))
11917 (set (match_operand:SI 3 "gpc_reg_operand" "")
11918 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11919 "TARGET_32BIT && reload_completed"
11920 [(set (match_dup 3)
11921 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11922 (set (match_dup 0)
11923 (compare:CC (match_dup 3)
11924 (const_int 0)))]
11925 "")
11926
11927 (define_insn ""
11928 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11929 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11930 [(match_operand 2 "cc_reg_operand" "y")
11931 (const_int 0)])
11932 (match_operand:SI 3 "const_int_operand" "n")))]
11933 ""
11934 "*
11935 {
11936 int is_bit = ccr_bit (operands[1], 1);
11937 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11938 int count;
11939
11940 if (is_bit >= put_bit)
11941 count = is_bit - put_bit;
11942 else
11943 count = 32 - (put_bit - is_bit);
11944
11945 operands[4] = GEN_INT (count);
11946 operands[5] = GEN_INT (put_bit);
11947
11948 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11949 }"
11950 [(set (attr "type")
11951 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11952 (const_string "mfcrf")
11953 ]
11954 (const_string "mfcr")))
11955 (set_attr "length" "8")])
11956
11957 (define_insn ""
11958 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11959 (compare:CC
11960 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11961 [(match_operand 2 "cc_reg_operand" "y,y")
11962 (const_int 0)])
11963 (match_operand:SI 3 "const_int_operand" "n,n"))
11964 (const_int 0)))
11965 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11966 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11967 (match_dup 3)))]
11968 ""
11969 "*
11970 {
11971 int is_bit = ccr_bit (operands[1], 1);
11972 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11973 int count;
11974
11975 /* Force split for non-cc0 compare. */
11976 if (which_alternative == 1)
11977 return \"#\";
11978
11979 if (is_bit >= put_bit)
11980 count = is_bit - put_bit;
11981 else
11982 count = 32 - (put_bit - is_bit);
11983
11984 operands[5] = GEN_INT (count);
11985 operands[6] = GEN_INT (put_bit);
11986
11987 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
11988 }"
11989 [(set_attr "type" "delayed_compare")
11990 (set_attr "length" "8,16")])
11991
11992 (define_split
11993 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11994 (compare:CC
11995 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11996 [(match_operand 2 "cc_reg_operand" "")
11997 (const_int 0)])
11998 (match_operand:SI 3 "const_int_operand" ""))
11999 (const_int 0)))
12000 (set (match_operand:SI 4 "gpc_reg_operand" "")
12001 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12002 (match_dup 3)))]
12003 "reload_completed"
12004 [(set (match_dup 4)
12005 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12006 (match_dup 3)))
12007 (set (match_dup 0)
12008 (compare:CC (match_dup 4)
12009 (const_int 0)))]
12010 "")
12011
12012 ;; There is a 3 cycle delay between consecutive mfcr instructions
12013 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
12014
12015 (define_peephole
12016 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12017 (match_operator:SI 1 "scc_comparison_operator"
12018 [(match_operand 2 "cc_reg_operand" "y")
12019 (const_int 0)]))
12020 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
12021 (match_operator:SI 4 "scc_comparison_operator"
12022 [(match_operand 5 "cc_reg_operand" "y")
12023 (const_int 0)]))]
12024 "REGNO (operands[2]) != REGNO (operands[5])"
12025 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
12026 [(set_attr "type" "mfcr")
12027 (set_attr "length" "12")])
12028
12029 (define_peephole
12030 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12031 (match_operator:DI 1 "scc_comparison_operator"
12032 [(match_operand 2 "cc_reg_operand" "y")
12033 (const_int 0)]))
12034 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12035 (match_operator:DI 4 "scc_comparison_operator"
12036 [(match_operand 5 "cc_reg_operand" "y")
12037 (const_int 0)]))]
12038 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
12039 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
12040 [(set_attr "type" "mfcr")
12041 (set_attr "length" "12")])
12042
12043 ;; There are some scc insns that can be done directly, without a compare.
12044 ;; These are faster because they don't involve the communications between
12045 ;; the FXU and branch units. In fact, we will be replacing all of the
12046 ;; integer scc insns here or in the portable methods in emit_store_flag.
12047 ;;
12048 ;; Also support (neg (scc ..)) since that construct is used to replace
12049 ;; branches, (plus (scc ..) ..) since that construct is common and
12050 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12051 ;; cases where it is no more expensive than (neg (scc ..)).
12052
12053 ;; Have reload force a constant into a register for the simple insns that
12054 ;; otherwise won't accept constants. We do this because it is faster than
12055 ;; the cmp/mfcr sequence we would otherwise generate.
12056
12057 (define_mode_attr scc_eq_op2 [(SI "rKLI")
12058 (DI "rKJI")])
12059
12060 (define_insn_and_split "*eq<mode>"
12061 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12062 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
12063 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
12064 "!TARGET_POWER"
12065 "#"
12066 "!TARGET_POWER"
12067 [(set (match_dup 0)
12068 (clz:GPR (match_dup 3)))
12069 (set (match_dup 0)
12070 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
12071 {
12072 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12073 {
12074 /* Use output operand as intermediate. */
12075 operands[3] = operands[0];
12076
12077 if (logical_operand (operands[2], <MODE>mode))
12078 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12079 gen_rtx_XOR (<MODE>mode,
12080 operands[1], operands[2])));
12081 else
12082 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12083 gen_rtx_PLUS (<MODE>mode, operands[1],
12084 negate_rtx (<MODE>mode,
12085 operands[2]))));
12086 }
12087 else
12088 operands[3] = operands[1];
12089
12090 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12091 })
12092
12093 (define_insn_and_split "*eq<mode>_compare"
12094 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12095 (compare:CC
12096 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12097 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
12098 (const_int 0)))
12099 (set (match_operand:P 0 "gpc_reg_operand" "=r")
12100 (eq:P (match_dup 1) (match_dup 2)))]
12101 "!TARGET_POWER && optimize_size"
12102 "#"
12103 "!TARGET_POWER && optimize_size"
12104 [(set (match_dup 0)
12105 (clz:P (match_dup 4)))
12106 (parallel [(set (match_dup 3)
12107 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
12108 (const_int 0)))
12109 (set (match_dup 0)
12110 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
12111 {
12112 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12113 {
12114 /* Use output operand as intermediate. */
12115 operands[4] = operands[0];
12116
12117 if (logical_operand (operands[2], <MODE>mode))
12118 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12119 gen_rtx_XOR (<MODE>mode,
12120 operands[1], operands[2])));
12121 else
12122 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12123 gen_rtx_PLUS (<MODE>mode, operands[1],
12124 negate_rtx (<MODE>mode,
12125 operands[2]))));
12126 }
12127 else
12128 operands[4] = operands[1];
12129
12130 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12131 })
12132
12133 (define_insn "*eqsi_power"
12134 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
12135 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12136 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
12137 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
12138 "TARGET_POWER"
12139 "@
12140 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12141 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
12142 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12143 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12144 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
12145 [(set_attr "type" "three,two,three,three,three")
12146 (set_attr "length" "12,8,12,12,12")])
12147
12148 ;; We have insns of the form shown by the first define_insn below. If
12149 ;; there is something inside the comparison operation, we must split it.
12150 (define_split
12151 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12152 (plus:SI (match_operator 1 "comparison_operator"
12153 [(match_operand:SI 2 "" "")
12154 (match_operand:SI 3
12155 "reg_or_cint_operand" "")])
12156 (match_operand:SI 4 "gpc_reg_operand" "")))
12157 (clobber (match_operand:SI 5 "register_operand" ""))]
12158 "! gpc_reg_operand (operands[2], SImode)"
12159 [(set (match_dup 5) (match_dup 2))
12160 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
12161 (match_dup 4)))])
12162
12163 (define_insn "*plus_eqsi"
12164 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
12165 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12166 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
12167 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
12168 "TARGET_32BIT"
12169 "@
12170 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12171 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
12172 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12173 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12174 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12175 [(set_attr "type" "three,two,three,three,three")
12176 (set_attr "length" "12,8,12,12,12")])
12177
12178 (define_insn "*compare_plus_eqsi"
12179 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12180 (compare:CC
12181 (plus:SI
12182 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12183 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12184 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12185 (const_int 0)))
12186 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
12187 "TARGET_32BIT && optimize_size"
12188 "@
12189 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12190 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
12191 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12192 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12193 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12194 #
12195 #
12196 #
12197 #
12198 #"
12199 [(set_attr "type" "compare")
12200 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12201
12202 (define_split
12203 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12204 (compare:CC
12205 (plus:SI
12206 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12207 (match_operand:SI 2 "scc_eq_operand" ""))
12208 (match_operand:SI 3 "gpc_reg_operand" ""))
12209 (const_int 0)))
12210 (clobber (match_scratch:SI 4 ""))]
12211 "TARGET_32BIT && optimize_size && reload_completed"
12212 [(set (match_dup 4)
12213 (plus:SI (eq:SI (match_dup 1)
12214 (match_dup 2))
12215 (match_dup 3)))
12216 (set (match_dup 0)
12217 (compare:CC (match_dup 4)
12218 (const_int 0)))]
12219 "")
12220
12221 (define_insn "*plus_eqsi_compare"
12222 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12223 (compare:CC
12224 (plus:SI
12225 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12226 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12227 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12228 (const_int 0)))
12229 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12230 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12231 "TARGET_32BIT && optimize_size"
12232 "@
12233 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12234 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
12235 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12236 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12237 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12238 #
12239 #
12240 #
12241 #
12242 #"
12243 [(set_attr "type" "compare")
12244 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12245
12246 (define_split
12247 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12248 (compare:CC
12249 (plus:SI
12250 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12251 (match_operand:SI 2 "scc_eq_operand" ""))
12252 (match_operand:SI 3 "gpc_reg_operand" ""))
12253 (const_int 0)))
12254 (set (match_operand:SI 0 "gpc_reg_operand" "")
12255 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12256 "TARGET_32BIT && optimize_size && reload_completed"
12257 [(set (match_dup 0)
12258 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12259 (set (match_dup 4)
12260 (compare:CC (match_dup 0)
12261 (const_int 0)))]
12262 "")
12263
12264 (define_insn "*neg_eq0<mode>"
12265 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12266 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12267 (const_int 0))))]
12268 ""
12269 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
12270 [(set_attr "type" "two")
12271 (set_attr "length" "8")])
12272
12273 (define_insn_and_split "*neg_eq<mode>"
12274 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12275 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12276 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
12277 ""
12278 "#"
12279 ""
12280 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12281 {
12282 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12283 {
12284 /* Use output operand as intermediate. */
12285 operands[3] = operands[0];
12286
12287 if (logical_operand (operands[2], <MODE>mode))
12288 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12289 gen_rtx_XOR (<MODE>mode,
12290 operands[1], operands[2])));
12291 else
12292 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12293 gen_rtx_PLUS (<MODE>mode, operands[1],
12294 negate_rtx (<MODE>mode,
12295 operands[2]))));
12296 }
12297 else
12298 operands[3] = operands[1];
12299 })
12300
12301 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
12302 ;; since it nabs/sr is just as fast.
12303 (define_insn "*ne0si"
12304 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12305 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12306 (const_int 31)))
12307 (clobber (match_scratch:SI 2 "=&r"))]
12308 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
12309 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
12310 [(set_attr "type" "two")
12311 (set_attr "length" "8")])
12312
12313 (define_insn "*ne0di"
12314 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12315 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12316 (const_int 63)))
12317 (clobber (match_scratch:DI 2 "=&r"))]
12318 "TARGET_64BIT"
12319 "addic %2,%1,-1\;subfe %0,%2,%1"
12320 [(set_attr "type" "two")
12321 (set_attr "length" "8")])
12322
12323 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
12324 (define_insn "*plus_ne0si"
12325 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12326 (plus:SI (lshiftrt:SI
12327 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12328 (const_int 31))
12329 (match_operand:SI 2 "gpc_reg_operand" "r")))
12330 (clobber (match_scratch:SI 3 "=&r"))]
12331 "TARGET_32BIT"
12332 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
12333 [(set_attr "type" "two")
12334 (set_attr "length" "8")])
12335
12336 (define_insn "*plus_ne0di"
12337 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12338 (plus:DI (lshiftrt:DI
12339 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12340 (const_int 63))
12341 (match_operand:DI 2 "gpc_reg_operand" "r")))
12342 (clobber (match_scratch:DI 3 "=&r"))]
12343 "TARGET_64BIT"
12344 "addic %3,%1,-1\;addze %0,%2"
12345 [(set_attr "type" "two")
12346 (set_attr "length" "8")])
12347
12348 (define_insn "*compare_plus_ne0si"
12349 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12350 (compare:CC
12351 (plus:SI (lshiftrt:SI
12352 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12353 (const_int 31))
12354 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12355 (const_int 0)))
12356 (clobber (match_scratch:SI 3 "=&r,&r"))
12357 (clobber (match_scratch:SI 4 "=X,&r"))]
12358 "TARGET_32BIT"
12359 "@
12360 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
12361 #"
12362 [(set_attr "type" "compare")
12363 (set_attr "length" "8,12")])
12364
12365 (define_split
12366 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12367 (compare:CC
12368 (plus:SI (lshiftrt:SI
12369 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12370 (const_int 31))
12371 (match_operand:SI 2 "gpc_reg_operand" ""))
12372 (const_int 0)))
12373 (clobber (match_scratch:SI 3 ""))
12374 (clobber (match_scratch:SI 4 ""))]
12375 "TARGET_32BIT && reload_completed"
12376 [(parallel [(set (match_dup 3)
12377 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
12378 (const_int 31))
12379 (match_dup 2)))
12380 (clobber (match_dup 4))])
12381 (set (match_dup 0)
12382 (compare:CC (match_dup 3)
12383 (const_int 0)))]
12384 "")
12385
12386 (define_insn "*compare_plus_ne0di"
12387 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12388 (compare:CC
12389 (plus:DI (lshiftrt:DI
12390 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12391 (const_int 63))
12392 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12393 (const_int 0)))
12394 (clobber (match_scratch:DI 3 "=&r,&r"))]
12395 "TARGET_64BIT"
12396 "@
12397 addic %3,%1,-1\;addze. %3,%2
12398 #"
12399 [(set_attr "type" "compare")
12400 (set_attr "length" "8,12")])
12401
12402 (define_split
12403 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12404 (compare:CC
12405 (plus:DI (lshiftrt:DI
12406 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12407 (const_int 63))
12408 (match_operand:DI 2 "gpc_reg_operand" ""))
12409 (const_int 0)))
12410 (clobber (match_scratch:DI 3 ""))]
12411 "TARGET_64BIT && reload_completed"
12412 [(set (match_dup 3)
12413 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12414 (const_int 63))
12415 (match_dup 2)))
12416 (set (match_dup 0)
12417 (compare:CC (match_dup 3)
12418 (const_int 0)))]
12419 "")
12420
12421 (define_insn "*plus_ne0si_compare"
12422 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12423 (compare:CC
12424 (plus:SI (lshiftrt:SI
12425 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12426 (const_int 31))
12427 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12428 (const_int 0)))
12429 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12430 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12431 (match_dup 2)))
12432 (clobber (match_scratch:SI 3 "=&r,&r"))]
12433 "TARGET_32BIT"
12434 "@
12435 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
12436 #"
12437 [(set_attr "type" "compare")
12438 (set_attr "length" "8,12")])
12439
12440 (define_split
12441 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12442 (compare:CC
12443 (plus:SI (lshiftrt:SI
12444 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12445 (const_int 31))
12446 (match_operand:SI 2 "gpc_reg_operand" ""))
12447 (const_int 0)))
12448 (set (match_operand:SI 0 "gpc_reg_operand" "")
12449 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12450 (match_dup 2)))
12451 (clobber (match_scratch:SI 3 ""))]
12452 "TARGET_32BIT && reload_completed"
12453 [(parallel [(set (match_dup 0)
12454 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12455 (match_dup 2)))
12456 (clobber (match_dup 3))])
12457 (set (match_dup 4)
12458 (compare:CC (match_dup 0)
12459 (const_int 0)))]
12460 "")
12461
12462 (define_insn "*plus_ne0di_compare"
12463 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12464 (compare:CC
12465 (plus:DI (lshiftrt:DI
12466 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12467 (const_int 63))
12468 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12469 (const_int 0)))
12470 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12471 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12472 (match_dup 2)))
12473 (clobber (match_scratch:DI 3 "=&r,&r"))]
12474 "TARGET_64BIT"
12475 "@
12476 addic %3,%1,-1\;addze. %0,%2
12477 #"
12478 [(set_attr "type" "compare")
12479 (set_attr "length" "8,12")])
12480
12481 (define_split
12482 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12483 (compare:CC
12484 (plus:DI (lshiftrt:DI
12485 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12486 (const_int 63))
12487 (match_operand:DI 2 "gpc_reg_operand" ""))
12488 (const_int 0)))
12489 (set (match_operand:DI 0 "gpc_reg_operand" "")
12490 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12491 (match_dup 2)))
12492 (clobber (match_scratch:DI 3 ""))]
12493 "TARGET_64BIT && reload_completed"
12494 [(parallel [(set (match_dup 0)
12495 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12496 (match_dup 2)))
12497 (clobber (match_dup 3))])
12498 (set (match_dup 4)
12499 (compare:CC (match_dup 0)
12500 (const_int 0)))]
12501 "")
12502
12503 (define_insn ""
12504 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12505 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12506 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12507 (clobber (match_scratch:SI 3 "=r,X"))]
12508 "TARGET_POWER"
12509 "@
12510 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
12511 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
12512 [(set_attr "length" "12")])
12513
12514 (define_insn ""
12515 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12516 (compare:CC
12517 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12518 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12519 (const_int 0)))
12520 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12521 (le:SI (match_dup 1) (match_dup 2)))
12522 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
12523 "TARGET_POWER"
12524 "@
12525 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12526 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
12527 #
12528 #"
12529 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
12530 (set_attr "length" "12,12,16,16")])
12531
12532 (define_split
12533 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12534 (compare:CC
12535 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12536 (match_operand:SI 2 "reg_or_short_operand" ""))
12537 (const_int 0)))
12538 (set (match_operand:SI 0 "gpc_reg_operand" "")
12539 (le:SI (match_dup 1) (match_dup 2)))
12540 (clobber (match_scratch:SI 3 ""))]
12541 "TARGET_POWER && reload_completed"
12542 [(parallel [(set (match_dup 0)
12543 (le:SI (match_dup 1) (match_dup 2)))
12544 (clobber (match_dup 3))])
12545 (set (match_dup 4)
12546 (compare:CC (match_dup 0)
12547 (const_int 0)))]
12548 "")
12549
12550 (define_insn ""
12551 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12552 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12553 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
12554 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12555 "TARGET_POWER"
12556 "@
12557 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12558 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
12559 [(set_attr "length" "12")])
12560
12561 (define_insn ""
12562 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12563 (compare:CC
12564 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12565 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12566 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12567 (const_int 0)))
12568 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12569 "TARGET_POWER"
12570 "@
12571 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12572 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12573 #
12574 #"
12575 [(set_attr "type" "compare")
12576 (set_attr "length" "12,12,16,16")])
12577
12578 (define_split
12579 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12580 (compare:CC
12581 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12582 (match_operand:SI 2 "reg_or_short_operand" ""))
12583 (match_operand:SI 3 "gpc_reg_operand" ""))
12584 (const_int 0)))
12585 (clobber (match_scratch:SI 4 ""))]
12586 "TARGET_POWER && reload_completed"
12587 [(set (match_dup 4)
12588 (plus:SI (le:SI (match_dup 1) (match_dup 2))
12589 (match_dup 3)))
12590 (set (match_dup 0)
12591 (compare:CC (match_dup 4)
12592 (const_int 0)))]
12593 "")
12594
12595 (define_insn ""
12596 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12597 (compare:CC
12598 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12599 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12600 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12601 (const_int 0)))
12602 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12603 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12604 "TARGET_POWER"
12605 "@
12606 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12607 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
12608 #
12609 #"
12610 [(set_attr "type" "compare")
12611 (set_attr "length" "12,12,16,16")])
12612
12613 (define_split
12614 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12615 (compare:CC
12616 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12617 (match_operand:SI 2 "reg_or_short_operand" ""))
12618 (match_operand:SI 3 "gpc_reg_operand" ""))
12619 (const_int 0)))
12620 (set (match_operand:SI 0 "gpc_reg_operand" "")
12621 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12622 "TARGET_POWER && reload_completed"
12623 [(set (match_dup 0)
12624 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12625 (set (match_dup 4)
12626 (compare:CC (match_dup 0)
12627 (const_int 0)))]
12628 "")
12629
12630 (define_insn ""
12631 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12632 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12633 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
12634 "TARGET_POWER"
12635 "@
12636 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12637 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
12638 [(set_attr "length" "12")])
12639
12640 (define_insn "*leu<mode>"
12641 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12642 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12643 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12644 ""
12645 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12646 [(set_attr "type" "three")
12647 (set_attr "length" "12")])
12648
12649 (define_insn "*leu<mode>_compare"
12650 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12651 (compare:CC
12652 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12653 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12654 (const_int 0)))
12655 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12656 (leu:P (match_dup 1) (match_dup 2)))]
12657 ""
12658 "@
12659 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12660 #"
12661 [(set_attr "type" "compare")
12662 (set_attr "length" "12,16")])
12663
12664 (define_split
12665 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12666 (compare:CC
12667 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12668 (match_operand:P 2 "reg_or_short_operand" ""))
12669 (const_int 0)))
12670 (set (match_operand:P 0 "gpc_reg_operand" "")
12671 (leu:P (match_dup 1) (match_dup 2)))]
12672 "reload_completed"
12673 [(set (match_dup 0)
12674 (leu:P (match_dup 1) (match_dup 2)))
12675 (set (match_dup 3)
12676 (compare:CC (match_dup 0)
12677 (const_int 0)))]
12678 "")
12679
12680 (define_insn "*plus_leu<mode>"
12681 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12682 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12683 (match_operand:P 2 "reg_or_short_operand" "rI"))
12684 (match_operand:P 3 "gpc_reg_operand" "r")))]
12685 ""
12686 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12687 [(set_attr "type" "two")
12688 (set_attr "length" "8")])
12689
12690 (define_insn ""
12691 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12692 (compare:CC
12693 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12694 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12695 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12696 (const_int 0)))
12697 (clobber (match_scratch:SI 4 "=&r,&r"))]
12698 "TARGET_32BIT"
12699 "@
12700 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12701 #"
12702 [(set_attr "type" "compare")
12703 (set_attr "length" "8,12")])
12704
12705 (define_split
12706 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12707 (compare:CC
12708 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12709 (match_operand:SI 2 "reg_or_short_operand" ""))
12710 (match_operand:SI 3 "gpc_reg_operand" ""))
12711 (const_int 0)))
12712 (clobber (match_scratch:SI 4 ""))]
12713 "TARGET_32BIT && reload_completed"
12714 [(set (match_dup 4)
12715 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12716 (match_dup 3)))
12717 (set (match_dup 0)
12718 (compare:CC (match_dup 4)
12719 (const_int 0)))]
12720 "")
12721
12722 (define_insn ""
12723 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12724 (compare:CC
12725 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12726 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12727 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12728 (const_int 0)))
12729 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12730 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12731 "TARGET_32BIT"
12732 "@
12733 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12734 #"
12735 [(set_attr "type" "compare")
12736 (set_attr "length" "8,12")])
12737
12738 (define_split
12739 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12740 (compare:CC
12741 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12742 (match_operand:SI 2 "reg_or_short_operand" ""))
12743 (match_operand:SI 3 "gpc_reg_operand" ""))
12744 (const_int 0)))
12745 (set (match_operand:SI 0 "gpc_reg_operand" "")
12746 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12747 "TARGET_32BIT && reload_completed"
12748 [(set (match_dup 0)
12749 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12750 (set (match_dup 4)
12751 (compare:CC (match_dup 0)
12752 (const_int 0)))]
12753 "")
12754
12755 (define_insn "*neg_leu<mode>"
12756 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12757 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12758 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12759 ""
12760 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12761 [(set_attr "type" "three")
12762 (set_attr "length" "12")])
12763
12764 (define_insn "*and_neg_leu<mode>"
12765 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12766 (and:P (neg:P
12767 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12768 (match_operand:P 2 "reg_or_short_operand" "rI")))
12769 (match_operand:P 3 "gpc_reg_operand" "r")))]
12770 ""
12771 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12772 [(set_attr "type" "three")
12773 (set_attr "length" "12")])
12774
12775 (define_insn ""
12776 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12777 (compare:CC
12778 (and:SI (neg:SI
12779 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12780 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12781 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12782 (const_int 0)))
12783 (clobber (match_scratch:SI 4 "=&r,&r"))]
12784 "TARGET_32BIT"
12785 "@
12786 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12787 #"
12788 [(set_attr "type" "compare")
12789 (set_attr "length" "12,16")])
12790
12791 (define_split
12792 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12793 (compare:CC
12794 (and:SI (neg:SI
12795 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12796 (match_operand:SI 2 "reg_or_short_operand" "")))
12797 (match_operand:SI 3 "gpc_reg_operand" ""))
12798 (const_int 0)))
12799 (clobber (match_scratch:SI 4 ""))]
12800 "TARGET_32BIT && reload_completed"
12801 [(set (match_dup 4)
12802 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12803 (match_dup 3)))
12804 (set (match_dup 0)
12805 (compare:CC (match_dup 4)
12806 (const_int 0)))]
12807 "")
12808
12809 (define_insn ""
12810 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12811 (compare:CC
12812 (and:SI (neg:SI
12813 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12814 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12815 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12816 (const_int 0)))
12817 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12818 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12819 "TARGET_32BIT"
12820 "@
12821 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12822 #"
12823 [(set_attr "type" "compare")
12824 (set_attr "length" "12,16")])
12825
12826 (define_split
12827 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12828 (compare:CC
12829 (and:SI (neg:SI
12830 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12831 (match_operand:SI 2 "reg_or_short_operand" "")))
12832 (match_operand:SI 3 "gpc_reg_operand" ""))
12833 (const_int 0)))
12834 (set (match_operand:SI 0 "gpc_reg_operand" "")
12835 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12836 "TARGET_32BIT && reload_completed"
12837 [(set (match_dup 0)
12838 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12839 (match_dup 3)))
12840 (set (match_dup 4)
12841 (compare:CC (match_dup 0)
12842 (const_int 0)))]
12843 "")
12844
12845 (define_insn ""
12846 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12847 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12848 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12849 "TARGET_POWER"
12850 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12851 [(set_attr "length" "12")])
12852
12853 (define_insn ""
12854 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12855 (compare:CC
12856 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12857 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12858 (const_int 0)))
12859 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12860 (lt:SI (match_dup 1) (match_dup 2)))]
12861 "TARGET_POWER"
12862 "@
12863 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12864 #"
12865 [(set_attr "type" "delayed_compare")
12866 (set_attr "length" "12,16")])
12867
12868 (define_split
12869 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12870 (compare:CC
12871 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12872 (match_operand:SI 2 "reg_or_short_operand" ""))
12873 (const_int 0)))
12874 (set (match_operand:SI 0 "gpc_reg_operand" "")
12875 (lt:SI (match_dup 1) (match_dup 2)))]
12876 "TARGET_POWER && reload_completed"
12877 [(set (match_dup 0)
12878 (lt:SI (match_dup 1) (match_dup 2)))
12879 (set (match_dup 3)
12880 (compare:CC (match_dup 0)
12881 (const_int 0)))]
12882 "")
12883
12884 (define_insn ""
12885 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12886 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12887 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12888 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12889 "TARGET_POWER"
12890 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12891 [(set_attr "length" "12")])
12892
12893 (define_insn ""
12894 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12895 (compare:CC
12896 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12897 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12898 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12899 (const_int 0)))
12900 (clobber (match_scratch:SI 4 "=&r,&r"))]
12901 "TARGET_POWER"
12902 "@
12903 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12904 #"
12905 [(set_attr "type" "compare")
12906 (set_attr "length" "12,16")])
12907
12908 (define_split
12909 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12910 (compare:CC
12911 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12912 (match_operand:SI 2 "reg_or_short_operand" ""))
12913 (match_operand:SI 3 "gpc_reg_operand" ""))
12914 (const_int 0)))
12915 (clobber (match_scratch:SI 4 ""))]
12916 "TARGET_POWER && reload_completed"
12917 [(set (match_dup 4)
12918 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
12919 (match_dup 3)))
12920 (set (match_dup 0)
12921 (compare:CC (match_dup 4)
12922 (const_int 0)))]
12923 "")
12924
12925 (define_insn ""
12926 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12927 (compare:CC
12928 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12929 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12930 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12931 (const_int 0)))
12932 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12933 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12934 "TARGET_POWER"
12935 "@
12936 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12937 #"
12938 [(set_attr "type" "compare")
12939 (set_attr "length" "12,16")])
12940
12941 (define_split
12942 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12943 (compare:CC
12944 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12945 (match_operand:SI 2 "reg_or_short_operand" ""))
12946 (match_operand:SI 3 "gpc_reg_operand" ""))
12947 (const_int 0)))
12948 (set (match_operand:SI 0 "gpc_reg_operand" "")
12949 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12950 "TARGET_POWER && reload_completed"
12951 [(set (match_dup 0)
12952 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12953 (set (match_dup 4)
12954 (compare:CC (match_dup 0)
12955 (const_int 0)))]
12956 "")
12957
12958 (define_insn ""
12959 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12960 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12961 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12962 "TARGET_POWER"
12963 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12964 [(set_attr "length" "12")])
12965
12966 (define_insn_and_split "*ltu<mode>"
12967 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12968 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12969 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12970 ""
12971 "#"
12972 ""
12973 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12974 (set (match_dup 0) (neg:P (match_dup 0)))]
12975 "")
12976
12977 (define_insn_and_split "*ltu<mode>_compare"
12978 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12979 (compare:CC
12980 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12981 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12982 (const_int 0)))
12983 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12984 (ltu:P (match_dup 1) (match_dup 2)))]
12985 ""
12986 "#"
12987 ""
12988 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12989 (parallel [(set (match_dup 3)
12990 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12991 (set (match_dup 0) (neg:P (match_dup 0)))])]
12992 "")
12993
12994 (define_insn_and_split "*plus_ltu<mode>"
12995 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
12996 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12997 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12998 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
12999 ""
13000 "#"
13001 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13002 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13003 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13004 "")
13005
13006 (define_insn_and_split "*plus_ltu<mode>_compare"
13007 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13008 (compare:CC
13009 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13010 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13011 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13012 (const_int 0)))
13013 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13014 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13015 ""
13016 "#"
13017 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13018 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13019 (parallel [(set (match_dup 4)
13020 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13021 (const_int 0)))
13022 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13023 "")
13024
13025 (define_insn "*neg_ltu<mode>"
13026 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13027 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13028 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
13029 ""
13030 "@
13031 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
13032 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
13033 [(set_attr "type" "two")
13034 (set_attr "length" "8")])
13035
13036 (define_insn ""
13037 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13038 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13039 (match_operand:SI 2 "reg_or_short_operand" "rI")))
13040 (clobber (match_scratch:SI 3 "=r"))]
13041 "TARGET_POWER"
13042 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
13043 [(set_attr "length" "12")])
13044
13045 (define_insn ""
13046 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13047 (compare:CC
13048 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13049 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13050 (const_int 0)))
13051 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13052 (ge:SI (match_dup 1) (match_dup 2)))
13053 (clobber (match_scratch:SI 3 "=r,r"))]
13054 "TARGET_POWER"
13055 "@
13056 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13057 #"
13058 [(set_attr "type" "compare")
13059 (set_attr "length" "12,16")])
13060
13061 (define_split
13062 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13063 (compare:CC
13064 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13065 (match_operand:SI 2 "reg_or_short_operand" ""))
13066 (const_int 0)))
13067 (set (match_operand:SI 0 "gpc_reg_operand" "")
13068 (ge:SI (match_dup 1) (match_dup 2)))
13069 (clobber (match_scratch:SI 3 ""))]
13070 "TARGET_POWER && reload_completed"
13071 [(parallel [(set (match_dup 0)
13072 (ge:SI (match_dup 1) (match_dup 2)))
13073 (clobber (match_dup 3))])
13074 (set (match_dup 4)
13075 (compare:CC (match_dup 0)
13076 (const_int 0)))]
13077 "")
13078
13079 (define_insn ""
13080 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13081 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13082 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13083 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13084 "TARGET_POWER"
13085 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
13086 [(set_attr "length" "12")])
13087
13088 (define_insn ""
13089 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13090 (compare:CC
13091 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13092 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13093 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13094 (const_int 0)))
13095 (clobber (match_scratch:SI 4 "=&r,&r"))]
13096 "TARGET_POWER"
13097 "@
13098 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13099 #"
13100 [(set_attr "type" "compare")
13101 (set_attr "length" "12,16")])
13102
13103 (define_split
13104 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13105 (compare:CC
13106 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13107 (match_operand:SI 2 "reg_or_short_operand" ""))
13108 (match_operand:SI 3 "gpc_reg_operand" ""))
13109 (const_int 0)))
13110 (clobber (match_scratch:SI 4 ""))]
13111 "TARGET_POWER && reload_completed"
13112 [(set (match_dup 4)
13113 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
13114 (match_dup 3)))
13115 (set (match_dup 0)
13116 (compare:CC (match_dup 4)
13117 (const_int 0)))]
13118 "")
13119
13120 (define_insn ""
13121 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13122 (compare:CC
13123 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13124 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13125 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13126 (const_int 0)))
13127 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13128 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13129 "TARGET_POWER"
13130 "@
13131 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13132 #"
13133 [(set_attr "type" "compare")
13134 (set_attr "length" "12,16")])
13135
13136 (define_split
13137 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13138 (compare:CC
13139 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13140 (match_operand:SI 2 "reg_or_short_operand" ""))
13141 (match_operand:SI 3 "gpc_reg_operand" ""))
13142 (const_int 0)))
13143 (set (match_operand:SI 0 "gpc_reg_operand" "")
13144 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13145 "TARGET_POWER && reload_completed"
13146 [(set (match_dup 0)
13147 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13148 (set (match_dup 4)
13149 (compare:CC (match_dup 0)
13150 (const_int 0)))]
13151 "")
13152
13153 (define_insn ""
13154 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13155 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13156 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13157 "TARGET_POWER"
13158 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
13159 [(set_attr "length" "12")])
13160
13161 (define_insn "*geu<mode>"
13162 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13163 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13164 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13165 ""
13166 "@
13167 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
13168 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
13169 [(set_attr "type" "three")
13170 (set_attr "length" "12")])
13171
13172 (define_insn "*geu<mode>_compare"
13173 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13174 (compare:CC
13175 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13176 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13177 (const_int 0)))
13178 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13179 (geu:P (match_dup 1) (match_dup 2)))]
13180 ""
13181 "@
13182 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13183 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13184 #
13185 #"
13186 [(set_attr "type" "compare")
13187 (set_attr "length" "12,12,16,16")])
13188
13189 (define_split
13190 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13191 (compare:CC
13192 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
13193 (match_operand:P 2 "reg_or_neg_short_operand" ""))
13194 (const_int 0)))
13195 (set (match_operand:P 0 "gpc_reg_operand" "")
13196 (geu:P (match_dup 1) (match_dup 2)))]
13197 "reload_completed"
13198 [(set (match_dup 0)
13199 (geu:P (match_dup 1) (match_dup 2)))
13200 (set (match_dup 3)
13201 (compare:CC (match_dup 0)
13202 (const_int 0)))]
13203 "")
13204
13205 (define_insn "*plus_geu<mode>"
13206 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13207 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13208 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13209 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13210 ""
13211 "@
13212 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
13213 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
13214 [(set_attr "type" "two")
13215 (set_attr "length" "8")])
13216
13217 (define_insn ""
13218 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13219 (compare:CC
13220 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13221 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13222 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13223 (const_int 0)))
13224 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13225 "TARGET_32BIT"
13226 "@
13227 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
13228 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
13229 #
13230 #"
13231 [(set_attr "type" "compare")
13232 (set_attr "length" "8,8,12,12")])
13233
13234 (define_split
13235 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13236 (compare:CC
13237 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13238 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13239 (match_operand:SI 3 "gpc_reg_operand" ""))
13240 (const_int 0)))
13241 (clobber (match_scratch:SI 4 ""))]
13242 "TARGET_32BIT && reload_completed"
13243 [(set (match_dup 4)
13244 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13245 (match_dup 3)))
13246 (set (match_dup 0)
13247 (compare:CC (match_dup 4)
13248 (const_int 0)))]
13249 "")
13250
13251 (define_insn ""
13252 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13253 (compare:CC
13254 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13255 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13256 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13257 (const_int 0)))
13258 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13259 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13260 "TARGET_32BIT"
13261 "@
13262 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
13263 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
13264 #
13265 #"
13266 [(set_attr "type" "compare")
13267 (set_attr "length" "8,8,12,12")])
13268
13269 (define_split
13270 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13271 (compare:CC
13272 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13273 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13274 (match_operand:SI 3 "gpc_reg_operand" ""))
13275 (const_int 0)))
13276 (set (match_operand:SI 0 "gpc_reg_operand" "")
13277 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13278 "TARGET_32BIT && reload_completed"
13279 [(set (match_dup 0)
13280 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13281 (set (match_dup 4)
13282 (compare:CC (match_dup 0)
13283 (const_int 0)))]
13284 "")
13285
13286 (define_insn "*neg_geu<mode>"
13287 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13288 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13289 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13290 ""
13291 "@
13292 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
13293 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
13294 [(set_attr "type" "three")
13295 (set_attr "length" "12")])
13296
13297 (define_insn "*and_neg_geu<mode>"
13298 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13299 (and:P (neg:P
13300 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13301 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13302 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13303 ""
13304 "@
13305 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
13306 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13307 [(set_attr "type" "three")
13308 (set_attr "length" "12")])
13309
13310 (define_insn ""
13311 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13312 (compare:CC
13313 (and:SI (neg:SI
13314 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13315 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13316 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13317 (const_int 0)))
13318 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13319 "TARGET_32BIT"
13320 "@
13321 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13322 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13323 #
13324 #"
13325 [(set_attr "type" "compare")
13326 (set_attr "length" "12,12,16,16")])
13327
13328 (define_split
13329 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13330 (compare:CC
13331 (and:SI (neg:SI
13332 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13333 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13334 (match_operand:SI 3 "gpc_reg_operand" ""))
13335 (const_int 0)))
13336 (clobber (match_scratch:SI 4 ""))]
13337 "TARGET_32BIT && reload_completed"
13338 [(set (match_dup 4)
13339 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13340 (match_dup 3)))
13341 (set (match_dup 0)
13342 (compare:CC (match_dup 4)
13343 (const_int 0)))]
13344 "")
13345
13346 (define_insn ""
13347 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13348 (compare:CC
13349 (and:SI (neg:SI
13350 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13351 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13352 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13353 (const_int 0)))
13354 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13355 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13356 "TARGET_32BIT"
13357 "@
13358 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13359 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13360 #
13361 #"
13362 [(set_attr "type" "compare")
13363 (set_attr "length" "12,12,16,16")])
13364
13365 (define_split
13366 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13367 (compare:CC
13368 (and:SI (neg:SI
13369 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13370 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13371 (match_operand:SI 3 "gpc_reg_operand" ""))
13372 (const_int 0)))
13373 (set (match_operand:SI 0 "gpc_reg_operand" "")
13374 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13375 "TARGET_32BIT && reload_completed"
13376 [(set (match_dup 0)
13377 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13378 (set (match_dup 4)
13379 (compare:CC (match_dup 0)
13380 (const_int 0)))]
13381 "")
13382
13383 (define_insn ""
13384 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13385 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13386 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13387 "TARGET_POWER"
13388 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13389 [(set_attr "length" "12")])
13390
13391 (define_insn ""
13392 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13393 (compare:CC
13394 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13395 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13396 (const_int 0)))
13397 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13398 (gt:SI (match_dup 1) (match_dup 2)))]
13399 "TARGET_POWER"
13400 "@
13401 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13402 #"
13403 [(set_attr "type" "delayed_compare")
13404 (set_attr "length" "12,16")])
13405
13406 (define_split
13407 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13408 (compare:CC
13409 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13410 (match_operand:SI 2 "reg_or_short_operand" ""))
13411 (const_int 0)))
13412 (set (match_operand:SI 0 "gpc_reg_operand" "")
13413 (gt:SI (match_dup 1) (match_dup 2)))]
13414 "TARGET_POWER && reload_completed"
13415 [(set (match_dup 0)
13416 (gt:SI (match_dup 1) (match_dup 2)))
13417 (set (match_dup 3)
13418 (compare:CC (match_dup 0)
13419 (const_int 0)))]
13420 "")
13421
13422 (define_insn "*plus_gt0<mode>"
13423 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13424 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13425 (const_int 0))
13426 (match_operand:P 2 "gpc_reg_operand" "r")))]
13427 ""
13428 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13429 [(set_attr "type" "three")
13430 (set_attr "length" "12")])
13431
13432 (define_insn ""
13433 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13434 (compare:CC
13435 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13436 (const_int 0))
13437 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13438 (const_int 0)))
13439 (clobber (match_scratch:SI 3 "=&r,&r"))]
13440 "TARGET_32BIT"
13441 "@
13442 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13443 #"
13444 [(set_attr "type" "compare")
13445 (set_attr "length" "12,16")])
13446
13447 (define_split
13448 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13449 (compare:CC
13450 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13451 (const_int 0))
13452 (match_operand:SI 2 "gpc_reg_operand" ""))
13453 (const_int 0)))
13454 (clobber (match_scratch:SI 3 ""))]
13455 "TARGET_32BIT && reload_completed"
13456 [(set (match_dup 3)
13457 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13458 (match_dup 2)))
13459 (set (match_dup 0)
13460 (compare:CC (match_dup 3)
13461 (const_int 0)))]
13462 "")
13463
13464 (define_insn ""
13465 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13466 (compare:CC
13467 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13468 (const_int 0))
13469 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13470 (const_int 0)))
13471 (clobber (match_scratch:DI 3 "=&r,&r"))]
13472 "TARGET_64BIT"
13473 "@
13474 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13475 #"
13476 [(set_attr "type" "compare")
13477 (set_attr "length" "12,16")])
13478
13479 (define_split
13480 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13481 (compare:CC
13482 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13483 (const_int 0))
13484 (match_operand:DI 2 "gpc_reg_operand" ""))
13485 (const_int 0)))
13486 (clobber (match_scratch:DI 3 ""))]
13487 "TARGET_64BIT && reload_completed"
13488 [(set (match_dup 3)
13489 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13490 (match_dup 2)))
13491 (set (match_dup 0)
13492 (compare:CC (match_dup 3)
13493 (const_int 0)))]
13494 "")
13495
13496 (define_insn ""
13497 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13498 (compare:CC
13499 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13500 (const_int 0))
13501 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13502 (const_int 0)))
13503 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13504 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13505 "TARGET_32BIT"
13506 "@
13507 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13508 #"
13509 [(set_attr "type" "compare")
13510 (set_attr "length" "12,16")])
13511
13512 (define_split
13513 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13514 (compare:CC
13515 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13516 (const_int 0))
13517 (match_operand:SI 2 "gpc_reg_operand" ""))
13518 (const_int 0)))
13519 (set (match_operand:SI 0 "gpc_reg_operand" "")
13520 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13521 "TARGET_32BIT && reload_completed"
13522 [(set (match_dup 0)
13523 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13524 (set (match_dup 3)
13525 (compare:CC (match_dup 0)
13526 (const_int 0)))]
13527 "")
13528
13529 (define_insn ""
13530 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13531 (compare:CC
13532 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13533 (const_int 0))
13534 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13535 (const_int 0)))
13536 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13537 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13538 "TARGET_64BIT"
13539 "@
13540 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13541 #"
13542 [(set_attr "type" "compare")
13543 (set_attr "length" "12,16")])
13544
13545 (define_split
13546 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13547 (compare:CC
13548 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13549 (const_int 0))
13550 (match_operand:DI 2 "gpc_reg_operand" ""))
13551 (const_int 0)))
13552 (set (match_operand:DI 0 "gpc_reg_operand" "")
13553 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13554 "TARGET_64BIT && reload_completed"
13555 [(set (match_dup 0)
13556 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13557 (set (match_dup 3)
13558 (compare:CC (match_dup 0)
13559 (const_int 0)))]
13560 "")
13561
13562 (define_insn ""
13563 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13564 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13565 (match_operand:SI 2 "reg_or_short_operand" "r"))
13566 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13567 "TARGET_POWER"
13568 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13569 [(set_attr "length" "12")])
13570
13571 (define_insn ""
13572 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13573 (compare:CC
13574 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13575 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13576 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13577 (const_int 0)))
13578 (clobber (match_scratch:SI 4 "=&r,&r"))]
13579 "TARGET_POWER"
13580 "@
13581 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13582 #"
13583 [(set_attr "type" "compare")
13584 (set_attr "length" "12,16")])
13585
13586 (define_split
13587 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13588 (compare:CC
13589 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13590 (match_operand:SI 2 "reg_or_short_operand" ""))
13591 (match_operand:SI 3 "gpc_reg_operand" ""))
13592 (const_int 0)))
13593 (clobber (match_scratch:SI 4 ""))]
13594 "TARGET_POWER && reload_completed"
13595 [(set (match_dup 4)
13596 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13597 (set (match_dup 0)
13598 (compare:CC (match_dup 4)
13599 (const_int 0)))]
13600 "")
13601
13602 (define_insn ""
13603 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13604 (compare:CC
13605 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13606 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13607 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13608 (const_int 0)))
13609 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13610 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13611 "TARGET_POWER"
13612 "@
13613 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13614 #"
13615 [(set_attr "type" "compare")
13616 (set_attr "length" "12,16")])
13617
13618 (define_split
13619 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13620 (compare:CC
13621 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13622 (match_operand:SI 2 "reg_or_short_operand" ""))
13623 (match_operand:SI 3 "gpc_reg_operand" ""))
13624 (const_int 0)))
13625 (set (match_operand:SI 0 "gpc_reg_operand" "")
13626 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13627 "TARGET_POWER && reload_completed"
13628 [(set (match_dup 0)
13629 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13630 (set (match_dup 4)
13631 (compare:CC (match_dup 0)
13632 (const_int 0)))]
13633 "")
13634
13635 (define_insn ""
13636 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13637 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13638 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13639 "TARGET_POWER"
13640 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13641 [(set_attr "length" "12")])
13642
13643 (define_insn_and_split "*gtu<mode>"
13644 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13645 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13646 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13647 ""
13648 "#"
13649 ""
13650 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13651 (set (match_dup 0) (neg:P (match_dup 0)))]
13652 "")
13653
13654 (define_insn_and_split "*gtu<mode>_compare"
13655 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13656 (compare:CC
13657 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13658 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13659 (const_int 0)))
13660 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13661 (gtu:P (match_dup 1) (match_dup 2)))]
13662 ""
13663 "#"
13664 ""
13665 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13666 (parallel [(set (match_dup 3)
13667 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13668 (set (match_dup 0) (neg:P (match_dup 0)))])]
13669 "")
13670
13671 (define_insn_and_split "*plus_gtu<mode>"
13672 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13673 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13674 (match_operand:P 2 "reg_or_short_operand" "rI"))
13675 (match_operand:P 3 "reg_or_short_operand" "rI")))]
13676 ""
13677 "#"
13678 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13679 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13680 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13681 "")
13682
13683 (define_insn_and_split "*plus_gtu<mode>_compare"
13684 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13685 (compare:CC
13686 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13687 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13688 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13689 (const_int 0)))
13690 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13691 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13692 ""
13693 "#"
13694 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13695 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13696 (parallel [(set (match_dup 4)
13697 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13698 (const_int 0)))
13699 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13700 "")
13701
13702 (define_insn "*neg_gtu<mode>"
13703 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13704 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13705 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13706 ""
13707 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13708 [(set_attr "type" "two")
13709 (set_attr "length" "8")])
13710
13711 \f
13712 ;; Define both directions of branch and return. If we need a reload
13713 ;; register, we'd rather use CR0 since it is much easier to copy a
13714 ;; register CC value to there.
13715
13716 (define_insn ""
13717 [(set (pc)
13718 (if_then_else (match_operator 1 "branch_comparison_operator"
13719 [(match_operand 2
13720 "cc_reg_operand" "y")
13721 (const_int 0)])
13722 (label_ref (match_operand 0 "" ""))
13723 (pc)))]
13724 ""
13725 "*
13726 {
13727 return output_cbranch (operands[1], \"%l0\", 0, insn);
13728 }"
13729 [(set_attr "type" "branch")])
13730
13731 (define_insn ""
13732 [(set (pc)
13733 (if_then_else (match_operator 0 "branch_comparison_operator"
13734 [(match_operand 1
13735 "cc_reg_operand" "y")
13736 (const_int 0)])
13737 (return)
13738 (pc)))]
13739 "direct_return ()"
13740 "*
13741 {
13742 return output_cbranch (operands[0], NULL, 0, insn);
13743 }"
13744 [(set_attr "type" "jmpreg")
13745 (set_attr "length" "4")])
13746
13747 (define_insn ""
13748 [(set (pc)
13749 (if_then_else (match_operator 1 "branch_comparison_operator"
13750 [(match_operand 2
13751 "cc_reg_operand" "y")
13752 (const_int 0)])
13753 (pc)
13754 (label_ref (match_operand 0 "" ""))))]
13755 ""
13756 "*
13757 {
13758 return output_cbranch (operands[1], \"%l0\", 1, insn);
13759 }"
13760 [(set_attr "type" "branch")])
13761
13762 (define_insn ""
13763 [(set (pc)
13764 (if_then_else (match_operator 0 "branch_comparison_operator"
13765 [(match_operand 1
13766 "cc_reg_operand" "y")
13767 (const_int 0)])
13768 (pc)
13769 (return)))]
13770 "direct_return ()"
13771 "*
13772 {
13773 return output_cbranch (operands[0], NULL, 1, insn);
13774 }"
13775 [(set_attr "type" "jmpreg")
13776 (set_attr "length" "4")])
13777
13778 ;; Logic on condition register values.
13779
13780 ; This pattern matches things like
13781 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13782 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13783 ; (const_int 1)))
13784 ; which are generated by the branch logic.
13785 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13786
13787 (define_insn "*cceq_ior_compare"
13788 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13789 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13790 [(match_operator:SI 2
13791 "branch_positive_comparison_operator"
13792 [(match_operand 3
13793 "cc_reg_operand" "y,y")
13794 (const_int 0)])
13795 (match_operator:SI 4
13796 "branch_positive_comparison_operator"
13797 [(match_operand 5
13798 "cc_reg_operand" "0,y")
13799 (const_int 0)])])
13800 (const_int 1)))]
13801 ""
13802 "cr%q1 %E0,%j2,%j4"
13803 [(set_attr "type" "cr_logical,delayed_cr")])
13804
13805 ; Why is the constant -1 here, but 1 in the previous pattern?
13806 ; Because ~1 has all but the low bit set.
13807 (define_insn ""
13808 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13809 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13810 [(not:SI (match_operator:SI 2
13811 "branch_positive_comparison_operator"
13812 [(match_operand 3
13813 "cc_reg_operand" "y,y")
13814 (const_int 0)]))
13815 (match_operator:SI 4
13816 "branch_positive_comparison_operator"
13817 [(match_operand 5
13818 "cc_reg_operand" "0,y")
13819 (const_int 0)])])
13820 (const_int -1)))]
13821 ""
13822 "cr%q1 %E0,%j2,%j4"
13823 [(set_attr "type" "cr_logical,delayed_cr")])
13824
13825 (define_insn "*cceq_rev_compare"
13826 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13827 (compare:CCEQ (match_operator:SI 1
13828 "branch_positive_comparison_operator"
13829 [(match_operand 2
13830 "cc_reg_operand" "0,y")
13831 (const_int 0)])
13832 (const_int 0)))]
13833 ""
13834 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
13835 [(set_attr "type" "cr_logical,delayed_cr")])
13836
13837 ;; If we are comparing the result of two comparisons, this can be done
13838 ;; using creqv or crxor.
13839
13840 (define_insn_and_split ""
13841 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13842 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13843 [(match_operand 2 "cc_reg_operand" "y")
13844 (const_int 0)])
13845 (match_operator 3 "branch_comparison_operator"
13846 [(match_operand 4 "cc_reg_operand" "y")
13847 (const_int 0)])))]
13848 ""
13849 "#"
13850 ""
13851 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13852 (match_dup 5)))]
13853 "
13854 {
13855 int positive_1, positive_2;
13856
13857 positive_1 = branch_positive_comparison_operator (operands[1],
13858 GET_MODE (operands[1]));
13859 positive_2 = branch_positive_comparison_operator (operands[3],
13860 GET_MODE (operands[3]));
13861
13862 if (! positive_1)
13863 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13864 GET_CODE (operands[1])),
13865 SImode,
13866 operands[2], const0_rtx);
13867 else if (GET_MODE (operands[1]) != SImode)
13868 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13869 operands[2], const0_rtx);
13870
13871 if (! positive_2)
13872 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13873 GET_CODE (operands[3])),
13874 SImode,
13875 operands[4], const0_rtx);
13876 else if (GET_MODE (operands[3]) != SImode)
13877 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13878 operands[4], const0_rtx);
13879
13880 if (positive_1 == positive_2)
13881 {
13882 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13883 operands[5] = constm1_rtx;
13884 }
13885 else
13886 {
13887 operands[5] = const1_rtx;
13888 }
13889 }")
13890
13891 ;; Unconditional branch and return.
13892
13893 (define_insn "jump"
13894 [(set (pc)
13895 (label_ref (match_operand 0 "" "")))]
13896 ""
13897 "b %l0"
13898 [(set_attr "type" "branch")])
13899
13900 (define_insn "return"
13901 [(return)]
13902 "direct_return ()"
13903 "{br|blr}"
13904 [(set_attr "type" "jmpreg")])
13905
13906 (define_expand "indirect_jump"
13907 [(set (pc) (match_operand 0 "register_operand" ""))])
13908
13909 (define_insn "*indirect_jump<mode>"
13910 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
13911 ""
13912 "@
13913 bctr
13914 {br|blr}"
13915 [(set_attr "type" "jmpreg")])
13916
13917 ;; Table jump for switch statements:
13918 (define_expand "tablejump"
13919 [(use (match_operand 0 "" ""))
13920 (use (label_ref (match_operand 1 "" "")))]
13921 ""
13922 "
13923 {
13924 if (TARGET_32BIT)
13925 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13926 else
13927 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13928 DONE;
13929 }")
13930
13931 (define_expand "tablejumpsi"
13932 [(set (match_dup 3)
13933 (plus:SI (match_operand:SI 0 "" "")
13934 (match_dup 2)))
13935 (parallel [(set (pc) (match_dup 3))
13936 (use (label_ref (match_operand 1 "" "")))])]
13937 "TARGET_32BIT"
13938 "
13939 { operands[0] = force_reg (SImode, operands[0]);
13940 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13941 operands[3] = gen_reg_rtx (SImode);
13942 }")
13943
13944 (define_expand "tablejumpdi"
13945 [(set (match_dup 4)
13946 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
13947 (set (match_dup 3)
13948 (plus:DI (match_dup 4)
13949 (match_dup 2)))
13950 (parallel [(set (pc) (match_dup 3))
13951 (use (label_ref (match_operand 1 "" "")))])]
13952 "TARGET_64BIT"
13953 "
13954 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13955 operands[3] = gen_reg_rtx (DImode);
13956 operands[4] = gen_reg_rtx (DImode);
13957 }")
13958
13959 (define_insn "*tablejump<mode>_internal1"
13960 [(set (pc)
13961 (match_operand:P 0 "register_operand" "c,*l"))
13962 (use (label_ref (match_operand 1 "" "")))]
13963 ""
13964 "@
13965 bctr
13966 {br|blr}"
13967 [(set_attr "type" "jmpreg")])
13968
13969 (define_insn "nop"
13970 [(const_int 0)]
13971 ""
13972 "{cror 0,0,0|nop}")
13973 \f
13974 ;; Define the subtract-one-and-jump insns, starting with the template
13975 ;; so loop.c knows what to generate.
13976
13977 (define_expand "doloop_end"
13978 [(use (match_operand 0 "" "")) ; loop pseudo
13979 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13980 (use (match_operand 2 "" "")) ; max iterations
13981 (use (match_operand 3 "" "")) ; loop level
13982 (use (match_operand 4 "" ""))] ; label
13983 ""
13984 "
13985 {
13986 /* Only use this on innermost loops. */
13987 if (INTVAL (operands[3]) > 1)
13988 FAIL;
13989 if (TARGET_64BIT)
13990 {
13991 if (GET_MODE (operands[0]) != DImode)
13992 FAIL;
13993 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13994 }
13995 else
13996 {
13997 if (GET_MODE (operands[0]) != SImode)
13998 FAIL;
13999 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
14000 }
14001 DONE;
14002 }")
14003
14004 (define_expand "ctr<mode>"
14005 [(parallel [(set (pc)
14006 (if_then_else (ne (match_operand:P 0 "register_operand" "")
14007 (const_int 1))
14008 (label_ref (match_operand 1 "" ""))
14009 (pc)))
14010 (set (match_dup 0)
14011 (plus:P (match_dup 0)
14012 (const_int -1)))
14013 (clobber (match_scratch:CC 2 ""))
14014 (clobber (match_scratch:P 3 ""))])]
14015 ""
14016 "")
14017
14018 ;; We need to be able to do this for any operand, including MEM, or we
14019 ;; will cause reload to blow up since we don't allow output reloads on
14020 ;; JUMP_INSNs.
14021 ;; For the length attribute to be calculated correctly, the
14022 ;; label MUST be operand 0.
14023
14024 (define_insn "*ctr<mode>_internal1"
14025 [(set (pc)
14026 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14027 (const_int 1))
14028 (label_ref (match_operand 0 "" ""))
14029 (pc)))
14030 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14031 (plus:P (match_dup 1)
14032 (const_int -1)))
14033 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14034 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14035 ""
14036 "*
14037 {
14038 if (which_alternative != 0)
14039 return \"#\";
14040 else if (get_attr_length (insn) == 4)
14041 return \"{bdn|bdnz} %l0\";
14042 else
14043 return \"bdz $+8\;b %l0\";
14044 }"
14045 [(set_attr "type" "branch")
14046 (set_attr "length" "*,12,16,16")])
14047
14048 (define_insn "*ctr<mode>_internal2"
14049 [(set (pc)
14050 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14051 (const_int 1))
14052 (pc)
14053 (label_ref (match_operand 0 "" ""))))
14054 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14055 (plus:P (match_dup 1)
14056 (const_int -1)))
14057 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14058 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14059 ""
14060 "*
14061 {
14062 if (which_alternative != 0)
14063 return \"#\";
14064 else if (get_attr_length (insn) == 4)
14065 return \"bdz %l0\";
14066 else
14067 return \"{bdn|bdnz} $+8\;b %l0\";
14068 }"
14069 [(set_attr "type" "branch")
14070 (set_attr "length" "*,12,16,16")])
14071
14072 ;; Similar but use EQ
14073
14074 (define_insn "*ctr<mode>_internal5"
14075 [(set (pc)
14076 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14077 (const_int 1))
14078 (label_ref (match_operand 0 "" ""))
14079 (pc)))
14080 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14081 (plus:P (match_dup 1)
14082 (const_int -1)))
14083 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14084 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14085 ""
14086 "*
14087 {
14088 if (which_alternative != 0)
14089 return \"#\";
14090 else if (get_attr_length (insn) == 4)
14091 return \"bdz %l0\";
14092 else
14093 return \"{bdn|bdnz} $+8\;b %l0\";
14094 }"
14095 [(set_attr "type" "branch")
14096 (set_attr "length" "*,12,16,16")])
14097
14098 (define_insn "*ctr<mode>_internal6"
14099 [(set (pc)
14100 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14101 (const_int 1))
14102 (pc)
14103 (label_ref (match_operand 0 "" ""))))
14104 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14105 (plus:P (match_dup 1)
14106 (const_int -1)))
14107 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14108 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14109 ""
14110 "*
14111 {
14112 if (which_alternative != 0)
14113 return \"#\";
14114 else if (get_attr_length (insn) == 4)
14115 return \"{bdn|bdnz} %l0\";
14116 else
14117 return \"bdz $+8\;b %l0\";
14118 }"
14119 [(set_attr "type" "branch")
14120 (set_attr "length" "*,12,16,16")])
14121
14122 ;; Now the splitters if we could not allocate the CTR register
14123
14124 (define_split
14125 [(set (pc)
14126 (if_then_else (match_operator 2 "comparison_operator"
14127 [(match_operand:P 1 "gpc_reg_operand" "")
14128 (const_int 1)])
14129 (match_operand 5 "" "")
14130 (match_operand 6 "" "")))
14131 (set (match_operand:P 0 "gpc_reg_operand" "")
14132 (plus:P (match_dup 1) (const_int -1)))
14133 (clobber (match_scratch:CC 3 ""))
14134 (clobber (match_scratch:P 4 ""))]
14135 "reload_completed"
14136 [(parallel [(set (match_dup 3)
14137 (compare:CC (plus:P (match_dup 1)
14138 (const_int -1))
14139 (const_int 0)))
14140 (set (match_dup 0)
14141 (plus:P (match_dup 1)
14142 (const_int -1)))])
14143 (set (pc) (if_then_else (match_dup 7)
14144 (match_dup 5)
14145 (match_dup 6)))]
14146 "
14147 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14148 operands[3], const0_rtx); }")
14149
14150 (define_split
14151 [(set (pc)
14152 (if_then_else (match_operator 2 "comparison_operator"
14153 [(match_operand:P 1 "gpc_reg_operand" "")
14154 (const_int 1)])
14155 (match_operand 5 "" "")
14156 (match_operand 6 "" "")))
14157 (set (match_operand:P 0 "nonimmediate_operand" "")
14158 (plus:P (match_dup 1) (const_int -1)))
14159 (clobber (match_scratch:CC 3 ""))
14160 (clobber (match_scratch:P 4 ""))]
14161 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
14162 [(parallel [(set (match_dup 3)
14163 (compare:CC (plus:P (match_dup 1)
14164 (const_int -1))
14165 (const_int 0)))
14166 (set (match_dup 4)
14167 (plus:P (match_dup 1)
14168 (const_int -1)))])
14169 (set (match_dup 0)
14170 (match_dup 4))
14171 (set (pc) (if_then_else (match_dup 7)
14172 (match_dup 5)
14173 (match_dup 6)))]
14174 "
14175 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14176 operands[3], const0_rtx); }")
14177 \f
14178 (define_insn "trap"
14179 [(trap_if (const_int 1) (const_int 0))]
14180 ""
14181 "{t 31,0,0|trap}"
14182 [(set_attr "type" "trap")])
14183
14184 (define_expand "conditional_trap"
14185 [(trap_if (match_operator 0 "trap_comparison_operator"
14186 [(match_dup 2) (match_dup 3)])
14187 (match_operand 1 "const_int_operand" ""))]
14188 ""
14189 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14190 operands[2] = rs6000_compare_op0;
14191 operands[3] = rs6000_compare_op1;")
14192
14193 (define_insn ""
14194 [(trap_if (match_operator 0 "trap_comparison_operator"
14195 [(match_operand:GPR 1 "register_operand" "r")
14196 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
14197 (const_int 0))]
14198 ""
14199 "{t|t<wd>}%V0%I2 %1,%2"
14200 [(set_attr "type" "trap")])
14201 \f
14202 ;; Insns related to generating the function prologue and epilogue.
14203
14204 (define_expand "prologue"
14205 [(use (const_int 0))]
14206 "TARGET_SCHED_PROLOG"
14207 "
14208 {
14209 rs6000_emit_prologue ();
14210 DONE;
14211 }")
14212
14213 (define_insn "*movesi_from_cr_one"
14214 [(match_parallel 0 "mfcr_operation"
14215 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14216 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14217 (match_operand 3 "immediate_operand" "n")]
14218 UNSPEC_MOVESI_FROM_CR))])]
14219 "TARGET_MFCRF"
14220 "*
14221 {
14222 int mask = 0;
14223 int i;
14224 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14225 {
14226 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14227 operands[4] = GEN_INT (mask);
14228 output_asm_insn (\"mfcr %1,%4\", operands);
14229 }
14230 return \"\";
14231 }"
14232 [(set_attr "type" "mfcrf")])
14233
14234 (define_insn "movesi_from_cr"
14235 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14236 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
14237 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
14238 UNSPEC_MOVESI_FROM_CR))]
14239 ""
14240 "mfcr %0"
14241 [(set_attr "type" "mfcr")])
14242
14243 (define_insn "*stmw"
14244 [(match_parallel 0 "stmw_operation"
14245 [(set (match_operand:SI 1 "memory_operand" "=m")
14246 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14247 "TARGET_MULTIPLE"
14248 "{stm|stmw} %2,%1"
14249 [(set_attr "type" "store_ux")])
14250
14251 (define_insn "*save_fpregs_<mode>"
14252 [(match_parallel 0 "any_parallel_operand"
14253 [(clobber (match_operand:P 1 "register_operand" "=l"))
14254 (use (match_operand:P 2 "call_operand" "s"))
14255 (set (match_operand:DF 3 "memory_operand" "=m")
14256 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14257 ""
14258 "bl %z2"
14259 [(set_attr "type" "branch")
14260 (set_attr "length" "4")])
14261
14262 ; These are to explain that changes to the stack pointer should
14263 ; not be moved over stores to stack memory.
14264 (define_insn "stack_tie"
14265 [(set (match_operand:BLK 0 "memory_operand" "+m")
14266 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
14267 ""
14268 ""
14269 [(set_attr "length" "0")])
14270
14271
14272 (define_expand "epilogue"
14273 [(use (const_int 0))]
14274 "TARGET_SCHED_PROLOG"
14275 "
14276 {
14277 rs6000_emit_epilogue (FALSE);
14278 DONE;
14279 }")
14280
14281 ; On some processors, doing the mtcrf one CC register at a time is
14282 ; faster (like on the 604e). On others, doing them all at once is
14283 ; faster; for instance, on the 601 and 750.
14284
14285 (define_expand "movsi_to_cr_one"
14286 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14287 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14288 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14289 ""
14290 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14291
14292 (define_insn "*movsi_to_cr"
14293 [(match_parallel 0 "mtcrf_operation"
14294 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14295 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14296 (match_operand 3 "immediate_operand" "n")]
14297 UNSPEC_MOVESI_TO_CR))])]
14298 ""
14299 "*
14300 {
14301 int mask = 0;
14302 int i;
14303 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14304 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14305 operands[4] = GEN_INT (mask);
14306 return \"mtcrf %4,%2\";
14307 }"
14308 [(set_attr "type" "mtcr")])
14309
14310 (define_insn "*mtcrfsi"
14311 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14312 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14313 (match_operand 2 "immediate_operand" "n")]
14314 UNSPEC_MOVESI_TO_CR))]
14315 "GET_CODE (operands[0]) == REG
14316 && CR_REGNO_P (REGNO (operands[0]))
14317 && GET_CODE (operands[2]) == CONST_INT
14318 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14319 "mtcrf %R0,%1"
14320 [(set_attr "type" "mtcr")])
14321
14322 ; The load-multiple instructions have similar properties.
14323 ; Note that "load_multiple" is a name known to the machine-independent
14324 ; code that actually corresponds to the PowerPC load-string.
14325
14326 (define_insn "*lmw"
14327 [(match_parallel 0 "lmw_operation"
14328 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14329 (match_operand:SI 2 "memory_operand" "m"))])]
14330 "TARGET_MULTIPLE"
14331 "{lm|lmw} %1,%2"
14332 [(set_attr "type" "load_ux")])
14333
14334 (define_insn "*return_internal_<mode>"
14335 [(return)
14336 (use (match_operand:P 0 "register_operand" "lc"))]
14337 ""
14338 "b%T0"
14339 [(set_attr "type" "jmpreg")])
14340
14341 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14342 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14343
14344 (define_insn "*return_and_restore_fpregs_<mode>"
14345 [(match_parallel 0 "any_parallel_operand"
14346 [(return)
14347 (use (match_operand:P 1 "register_operand" "l"))
14348 (use (match_operand:P 2 "call_operand" "s"))
14349 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14350 (match_operand:DF 4 "memory_operand" "m"))])]
14351 ""
14352 "b %z2")
14353
14354 ; This is used in compiling the unwind routines.
14355 (define_expand "eh_return"
14356 [(use (match_operand 0 "general_operand" ""))]
14357 ""
14358 "
14359 {
14360 if (TARGET_32BIT)
14361 emit_insn (gen_eh_set_lr_si (operands[0]));
14362 else
14363 emit_insn (gen_eh_set_lr_di (operands[0]));
14364 DONE;
14365 }")
14366
14367 ; We can't expand this before we know where the link register is stored.
14368 (define_insn "eh_set_lr_<mode>"
14369 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
14370 UNSPECV_EH_RR)
14371 (clobber (match_scratch:P 1 "=&b"))]
14372 ""
14373 "#")
14374
14375 (define_split
14376 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14377 (clobber (match_scratch 1 ""))]
14378 "reload_completed"
14379 [(const_int 0)]
14380 "
14381 {
14382 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14383 DONE;
14384 }")
14385
14386 (define_insn "prefetch"
14387 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
14388 (match_operand:SI 1 "const_int_operand" "n")
14389 (match_operand:SI 2 "const_int_operand" "n"))]
14390 "TARGET_POWERPC"
14391 "*
14392 {
14393 if (GET_CODE (operands[0]) == REG)
14394 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14395 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14396 }"
14397 [(set_attr "type" "load")])
14398 \f
14399
14400 (include "sync.md")
14401 (include "altivec.md")
14402 (include "spe.md")
Mirror of https://gcc.gnu.org/git/gcc.git