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predicates.md (easy_fp_constant): Single FP consts are easy.
[thirdparty/gcc.git] / gcc / config / rs6000 / rs6000.md
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6
7 ;; This file is part of GCC.
8
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 3, or (at your
12 ;; option) any later version.
13
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
18
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
22
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
24
25 ;;
26 ;; REGNOS
27 ;;
28
29 (define_constants
30 [(MQ_REGNO 64)
31 (LR_REGNO 65)
32 (CTR_REGNO 66)
33 (CR0_REGNO 68)
34 (CR1_REGNO 69)
35 (CR2_REGNO 70)
36 (CR3_REGNO 71)
37 (CR4_REGNO 72)
38 (CR5_REGNO 73)
39 (CR6_REGNO 74)
40 (CR7_REGNO 75)
41 (MAX_CR_REGNO 75)
42 (XER_REGNO 76)
43 (FIRST_ALTIVEC_REGNO 77)
44 (LAST_ALTIVEC_REGNO 108)
45 (VRSAVE_REGNO 109)
46 (VSCR_REGNO 110)
47 (SPE_ACC_REGNO 111)
48 (SPEFSCR_REGNO 112)
49 (SFP_REGNO 113)
50 ])
51
52 ;;
53 ;; UNSPEC usage
54 ;;
55
56 (define_constants
57 [(UNSPEC_FRSP 0) ; frsp for POWER machines
58 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
59 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
60 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
61 (UNSPEC_MOVSI_GOT 8)
62 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
63 (UNSPEC_FCTIWZ 10)
64 (UNSPEC_FRIM 11)
65 (UNSPEC_FRIN 12)
66 (UNSPEC_FRIP 13)
67 (UNSPEC_FRIZ 14)
68 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
69 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
70 (UNSPEC_TLSGD 17)
71 (UNSPEC_TLSLD 18)
72 (UNSPEC_MOVESI_FROM_CR 19)
73 (UNSPEC_MOVESI_TO_CR 20)
74 (UNSPEC_TLSDTPREL 21)
75 (UNSPEC_TLSDTPRELHA 22)
76 (UNSPEC_TLSDTPRELLO 23)
77 (UNSPEC_TLSGOTDTPREL 24)
78 (UNSPEC_TLSTPREL 25)
79 (UNSPEC_TLSTPRELHA 26)
80 (UNSPEC_TLSTPRELLO 27)
81 (UNSPEC_TLSGOTTPREL 28)
82 (UNSPEC_TLSTLS 29)
83 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
84 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
85 (UNSPEC_STFIWX 32)
86 (UNSPEC_POPCNTB 33)
87 (UNSPEC_FRES 34)
88 (UNSPEC_SP_SET 35)
89 (UNSPEC_SP_TEST 36)
90 (UNSPEC_SYNC 37)
91 (UNSPEC_LWSYNC 38)
92 (UNSPEC_ISYNC 39)
93 (UNSPEC_SYNC_OP 40)
94 (UNSPEC_ATOMIC 41)
95 (UNSPEC_CMPXCHG 42)
96 (UNSPEC_XCHG 43)
97 (UNSPEC_AND 44)
98 (UNSPEC_DLMZB 45)
99 (UNSPEC_DLMZB_CR 46)
100 (UNSPEC_DLMZB_STRLEN 47)
101 (UNSPEC_RSQRT 48)
102 ])
103
104 ;;
105 ;; UNSPEC_VOLATILE usage
106 ;;
107
108 (define_constants
109 [(UNSPECV_BLOCK 0)
110 (UNSPECV_LL 1) ; load-locked
111 (UNSPECV_SC 2) ; store-conditional
112 (UNSPECV_EH_RR 9) ; eh_reg_restore
113 ])
114 \f
115 ;; Define an insn type attribute. This is used in function unit delay
116 ;; computations.
117 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr"
118 (const_string "integer"))
119
120 ;; Length (in bytes).
121 ; '(pc)' in the following doesn't include the instruction itself; it is
122 ; calculated as if the instruction had zero size.
123 (define_attr "length" ""
124 (if_then_else (eq_attr "type" "branch")
125 (if_then_else (and (ge (minus (match_dup 0) (pc))
126 (const_int -32768))
127 (lt (minus (match_dup 0) (pc))
128 (const_int 32764)))
129 (const_int 4)
130 (const_int 8))
131 (const_int 4)))
132
133 ;; Processor type -- this attribute must exactly match the processor_type
134 ;; enumeration in rs6000.h.
135
136 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,power4,power5,power6,cell"
137 (const (symbol_ref "rs6000_cpu_attr")))
138
139
140 ;; If this instruction is microcoded on the CELL processor
141 ; The default for load and stores is conditional
142 ; The default for load extended and the recorded instructions is always microcoded
143 (define_attr "cell_micro" "not,conditional,always"
144 (if_then_else (ior (ior (eq_attr "type" "load")
145 (eq_attr "type" "store"))
146 (ior (eq_attr "type" "fpload")
147 (eq_attr "type" "fpstore")))
148 (const_string "conditional")
149 (if_then_else (ior (eq_attr "type" "load_ext")
150 (ior (eq_attr "type" "compare")
151 (eq_attr "type" "delayed_compare")))
152 (const_string "always")
153 (const_string "not"))))
154
155
156 (automata_option "ndfa")
157
158 (include "rios1.md")
159 (include "rios2.md")
160 (include "rs64.md")
161 (include "mpc.md")
162 (include "40x.md")
163 (include "440.md")
164 (include "603.md")
165 (include "6xx.md")
166 (include "7xx.md")
167 (include "7450.md")
168 (include "8540.md")
169 (include "e300c2c3.md")
170 (include "e500mc.md")
171 (include "power4.md")
172 (include "power5.md")
173 (include "power6.md")
174 (include "cell.md")
175
176 (include "predicates.md")
177 (include "constraints.md")
178
179 (include "darwin.md")
180
181 \f
182 ;; Mode iterators
183
184 ; This mode iterator allows :GPR to be used to indicate the allowable size
185 ; of whole values in GPRs.
186 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
187
188 ; Any supported integer mode.
189 (define_mode_iterator INT [QI HI SI DI TI])
190
191 ; Any supported integer mode that fits in one register.
192 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
193
194 ; extend modes for DImode
195 (define_mode_iterator QHSI [QI HI SI])
196
197 ; SImode or DImode, even if DImode doesn't fit in GPRs.
198 (define_mode_iterator SDI [SI DI])
199
200 ; The size of a pointer. Also, the size of the value that a record-condition
201 ; (one with a '.') will compare.
202 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
203
204 ; Any hardware-supported floating-point mode
205 (define_mode_iterator FP [
206 (SF "TARGET_HARD_FLOAT
207 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
208 (DF "TARGET_HARD_FLOAT
209 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
210 (TF "!TARGET_IEEEQUAD
211 && TARGET_HARD_FLOAT
212 && (TARGET_FPRS || TARGET_E500_DOUBLE)
213 && TARGET_LONG_DOUBLE_128")
214 (DD "TARGET_DFP")
215 (TD "TARGET_DFP")])
216
217 ; Various instructions that come in SI and DI forms.
218 ; A generic w/d attribute, for things like cmpw/cmpd.
219 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
220
221 ; DImode bits
222 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
223
224 \f
225 ;; Start with fixed-point load and store insns. Here we put only the more
226 ;; complex forms. Basic data transfer is done later.
227
228 (define_expand "zero_extend<mode>di2"
229 [(set (match_operand:DI 0 "gpc_reg_operand" "")
230 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
231 "TARGET_POWERPC64"
232 "")
233
234 (define_insn "*zero_extend<mode>di2_internal1"
235 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
236 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
237 "TARGET_POWERPC64"
238 "@
239 l<wd>z%U1%X1 %0,%1
240 rldicl %0,%1,0,<dbits>"
241 [(set_attr "type" "load,*")])
242
243 (define_insn "*zero_extend<mode>di2_internal2"
244 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
245 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
246 (const_int 0)))
247 (clobber (match_scratch:DI 2 "=r,r"))]
248 "TARGET_64BIT"
249 "@
250 rldicl. %2,%1,0,<dbits>
251 #"
252 [(set_attr "type" "compare")
253 (set_attr "length" "4,8")])
254
255 (define_split
256 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
257 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
258 (const_int 0)))
259 (clobber (match_scratch:DI 2 ""))]
260 "TARGET_POWERPC64 && reload_completed"
261 [(set (match_dup 2)
262 (zero_extend:DI (match_dup 1)))
263 (set (match_dup 0)
264 (compare:CC (match_dup 2)
265 (const_int 0)))]
266 "")
267
268 (define_insn "*zero_extend<mode>di2_internal3"
269 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
270 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
271 (const_int 0)))
272 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
273 (zero_extend:DI (match_dup 1)))]
274 "TARGET_64BIT"
275 "@
276 rldicl. %0,%1,0,<dbits>
277 #"
278 [(set_attr "type" "compare")
279 (set_attr "length" "4,8")])
280
281 (define_split
282 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
283 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
284 (const_int 0)))
285 (set (match_operand:DI 0 "gpc_reg_operand" "")
286 (zero_extend:DI (match_dup 1)))]
287 "TARGET_POWERPC64 && reload_completed"
288 [(set (match_dup 0)
289 (zero_extend:DI (match_dup 1)))
290 (set (match_dup 2)
291 (compare:CC (match_dup 0)
292 (const_int 0)))]
293 "")
294
295 (define_insn "extendqidi2"
296 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
297 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
298 "TARGET_POWERPC64"
299 "extsb %0,%1"
300 [(set_attr "type" "exts")])
301
302 (define_insn ""
303 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
304 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
305 (const_int 0)))
306 (clobber (match_scratch:DI 2 "=r,r"))]
307 "TARGET_64BIT"
308 "@
309 extsb. %2,%1
310 #"
311 [(set_attr "type" "compare")
312 (set_attr "length" "4,8")])
313
314 (define_split
315 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
316 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
317 (const_int 0)))
318 (clobber (match_scratch:DI 2 ""))]
319 "TARGET_POWERPC64 && reload_completed"
320 [(set (match_dup 2)
321 (sign_extend:DI (match_dup 1)))
322 (set (match_dup 0)
323 (compare:CC (match_dup 2)
324 (const_int 0)))]
325 "")
326
327 (define_insn ""
328 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
329 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
330 (const_int 0)))
331 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
332 (sign_extend:DI (match_dup 1)))]
333 "TARGET_64BIT"
334 "@
335 extsb. %0,%1
336 #"
337 [(set_attr "type" "compare")
338 (set_attr "length" "4,8")])
339
340 (define_split
341 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
342 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
343 (const_int 0)))
344 (set (match_operand:DI 0 "gpc_reg_operand" "")
345 (sign_extend:DI (match_dup 1)))]
346 "TARGET_POWERPC64 && reload_completed"
347 [(set (match_dup 0)
348 (sign_extend:DI (match_dup 1)))
349 (set (match_dup 2)
350 (compare:CC (match_dup 0)
351 (const_int 0)))]
352 "")
353
354 (define_expand "extendhidi2"
355 [(set (match_operand:DI 0 "gpc_reg_operand" "")
356 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
357 "TARGET_POWERPC64"
358 "")
359
360 (define_insn ""
361 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
362 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
363 "TARGET_POWERPC64"
364 "@
365 lha%U1%X1 %0,%1
366 extsh %0,%1"
367 [(set_attr "type" "load_ext,exts")])
368
369 (define_insn ""
370 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
371 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
372 (const_int 0)))
373 (clobber (match_scratch:DI 2 "=r,r"))]
374 "TARGET_64BIT"
375 "@
376 extsh. %2,%1
377 #"
378 [(set_attr "type" "compare")
379 (set_attr "length" "4,8")])
380
381 (define_split
382 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
383 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
384 (const_int 0)))
385 (clobber (match_scratch:DI 2 ""))]
386 "TARGET_POWERPC64 && reload_completed"
387 [(set (match_dup 2)
388 (sign_extend:DI (match_dup 1)))
389 (set (match_dup 0)
390 (compare:CC (match_dup 2)
391 (const_int 0)))]
392 "")
393
394 (define_insn ""
395 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
396 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
397 (const_int 0)))
398 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
399 (sign_extend:DI (match_dup 1)))]
400 "TARGET_64BIT"
401 "@
402 extsh. %0,%1
403 #"
404 [(set_attr "type" "compare")
405 (set_attr "length" "4,8")])
406
407 (define_split
408 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
409 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
410 (const_int 0)))
411 (set (match_operand:DI 0 "gpc_reg_operand" "")
412 (sign_extend:DI (match_dup 1)))]
413 "TARGET_POWERPC64 && reload_completed"
414 [(set (match_dup 0)
415 (sign_extend:DI (match_dup 1)))
416 (set (match_dup 2)
417 (compare:CC (match_dup 0)
418 (const_int 0)))]
419 "")
420
421 (define_expand "extendsidi2"
422 [(set (match_operand:DI 0 "gpc_reg_operand" "")
423 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
424 "TARGET_POWERPC64"
425 "")
426
427 (define_insn ""
428 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
429 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
430 "TARGET_POWERPC64"
431 "@
432 lwa%U1%X1 %0,%1
433 extsw %0,%1"
434 [(set_attr "type" "load_ext,exts")])
435
436 (define_insn ""
437 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
438 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
439 (const_int 0)))
440 (clobber (match_scratch:DI 2 "=r,r"))]
441 "TARGET_64BIT"
442 "@
443 extsw. %2,%1
444 #"
445 [(set_attr "type" "compare")
446 (set_attr "length" "4,8")])
447
448 (define_split
449 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
450 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
451 (const_int 0)))
452 (clobber (match_scratch:DI 2 ""))]
453 "TARGET_POWERPC64 && reload_completed"
454 [(set (match_dup 2)
455 (sign_extend:DI (match_dup 1)))
456 (set (match_dup 0)
457 (compare:CC (match_dup 2)
458 (const_int 0)))]
459 "")
460
461 (define_insn ""
462 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
463 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
464 (const_int 0)))
465 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
466 (sign_extend:DI (match_dup 1)))]
467 "TARGET_64BIT"
468 "@
469 extsw. %0,%1
470 #"
471 [(set_attr "type" "compare")
472 (set_attr "length" "4,8")])
473
474 (define_split
475 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
476 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
477 (const_int 0)))
478 (set (match_operand:DI 0 "gpc_reg_operand" "")
479 (sign_extend:DI (match_dup 1)))]
480 "TARGET_POWERPC64 && reload_completed"
481 [(set (match_dup 0)
482 (sign_extend:DI (match_dup 1)))
483 (set (match_dup 2)
484 (compare:CC (match_dup 0)
485 (const_int 0)))]
486 "")
487
488 (define_expand "zero_extendqisi2"
489 [(set (match_operand:SI 0 "gpc_reg_operand" "")
490 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
491 ""
492 "")
493
494 (define_insn ""
495 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
496 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
497 ""
498 "@
499 lbz%U1%X1 %0,%1
500 {rlinm|rlwinm} %0,%1,0,0xff"
501 [(set_attr "type" "load,*")])
502
503 (define_insn ""
504 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
505 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
506 (const_int 0)))
507 (clobber (match_scratch:SI 2 "=r,r"))]
508 ""
509 "@
510 {andil.|andi.} %2,%1,0xff
511 #"
512 [(set_attr "type" "compare")
513 (set_attr "length" "4,8")])
514
515 (define_split
516 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
517 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
518 (const_int 0)))
519 (clobber (match_scratch:SI 2 ""))]
520 "reload_completed"
521 [(set (match_dup 2)
522 (zero_extend:SI (match_dup 1)))
523 (set (match_dup 0)
524 (compare:CC (match_dup 2)
525 (const_int 0)))]
526 "")
527
528 (define_insn ""
529 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
530 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
531 (const_int 0)))
532 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
533 (zero_extend:SI (match_dup 1)))]
534 ""
535 "@
536 {andil.|andi.} %0,%1,0xff
537 #"
538 [(set_attr "type" "compare")
539 (set_attr "length" "4,8")])
540
541 (define_split
542 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
543 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
544 (const_int 0)))
545 (set (match_operand:SI 0 "gpc_reg_operand" "")
546 (zero_extend:SI (match_dup 1)))]
547 "reload_completed"
548 [(set (match_dup 0)
549 (zero_extend:SI (match_dup 1)))
550 (set (match_dup 2)
551 (compare:CC (match_dup 0)
552 (const_int 0)))]
553 "")
554
555 (define_expand "extendqisi2"
556 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
557 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
558 ""
559 "
560 {
561 if (TARGET_POWERPC)
562 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
563 else if (TARGET_POWER)
564 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
565 else
566 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
567 DONE;
568 }")
569
570 (define_insn "extendqisi2_ppc"
571 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
572 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
573 "TARGET_POWERPC"
574 "extsb %0,%1"
575 [(set_attr "type" "exts")])
576
577 (define_insn ""
578 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
579 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
580 (const_int 0)))
581 (clobber (match_scratch:SI 2 "=r,r"))]
582 "TARGET_POWERPC"
583 "@
584 extsb. %2,%1
585 #"
586 [(set_attr "type" "compare")
587 (set_attr "length" "4,8")])
588
589 (define_split
590 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
591 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
592 (const_int 0)))
593 (clobber (match_scratch:SI 2 ""))]
594 "TARGET_POWERPC && reload_completed"
595 [(set (match_dup 2)
596 (sign_extend:SI (match_dup 1)))
597 (set (match_dup 0)
598 (compare:CC (match_dup 2)
599 (const_int 0)))]
600 "")
601
602 (define_insn ""
603 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
604 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
605 (const_int 0)))
606 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
607 (sign_extend:SI (match_dup 1)))]
608 "TARGET_POWERPC"
609 "@
610 extsb. %0,%1
611 #"
612 [(set_attr "type" "compare")
613 (set_attr "length" "4,8")])
614
615 (define_split
616 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
617 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
618 (const_int 0)))
619 (set (match_operand:SI 0 "gpc_reg_operand" "")
620 (sign_extend:SI (match_dup 1)))]
621 "TARGET_POWERPC && reload_completed"
622 [(set (match_dup 0)
623 (sign_extend:SI (match_dup 1)))
624 (set (match_dup 2)
625 (compare:CC (match_dup 0)
626 (const_int 0)))]
627 "")
628
629 (define_expand "extendqisi2_power"
630 [(parallel [(set (match_dup 2)
631 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
632 (const_int 24)))
633 (clobber (scratch:SI))])
634 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
635 (ashiftrt:SI (match_dup 2)
636 (const_int 24)))
637 (clobber (scratch:SI))])]
638 "TARGET_POWER"
639 "
640 { operands[1] = gen_lowpart (SImode, operands[1]);
641 operands[2] = gen_reg_rtx (SImode); }")
642
643 (define_expand "extendqisi2_no_power"
644 [(set (match_dup 2)
645 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
646 (const_int 24)))
647 (set (match_operand:SI 0 "gpc_reg_operand" "")
648 (ashiftrt:SI (match_dup 2)
649 (const_int 24)))]
650 "! TARGET_POWER && ! TARGET_POWERPC"
651 "
652 { operands[1] = gen_lowpart (SImode, operands[1]);
653 operands[2] = gen_reg_rtx (SImode); }")
654
655 (define_expand "zero_extendqihi2"
656 [(set (match_operand:HI 0 "gpc_reg_operand" "")
657 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
658 ""
659 "")
660
661 (define_insn ""
662 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
663 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
664 ""
665 "@
666 lbz%U1%X1 %0,%1
667 {rlinm|rlwinm} %0,%1,0,0xff"
668 [(set_attr "type" "load,*")])
669
670 (define_insn ""
671 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
672 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
673 (const_int 0)))
674 (clobber (match_scratch:HI 2 "=r,r"))]
675 ""
676 "@
677 {andil.|andi.} %2,%1,0xff
678 #"
679 [(set_attr "type" "compare")
680 (set_attr "length" "4,8")])
681
682 (define_split
683 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
684 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
685 (const_int 0)))
686 (clobber (match_scratch:HI 2 ""))]
687 "reload_completed"
688 [(set (match_dup 2)
689 (zero_extend:HI (match_dup 1)))
690 (set (match_dup 0)
691 (compare:CC (match_dup 2)
692 (const_int 0)))]
693 "")
694
695 (define_insn ""
696 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
697 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
698 (const_int 0)))
699 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
700 (zero_extend:HI (match_dup 1)))]
701 ""
702 "@
703 {andil.|andi.} %0,%1,0xff
704 #"
705 [(set_attr "type" "compare")
706 (set_attr "length" "4,8")])
707
708 (define_split
709 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
710 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
711 (const_int 0)))
712 (set (match_operand:HI 0 "gpc_reg_operand" "")
713 (zero_extend:HI (match_dup 1)))]
714 "reload_completed"
715 [(set (match_dup 0)
716 (zero_extend:HI (match_dup 1)))
717 (set (match_dup 2)
718 (compare:CC (match_dup 0)
719 (const_int 0)))]
720 "")
721
722 (define_expand "extendqihi2"
723 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
724 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
725 ""
726 "
727 {
728 if (TARGET_POWERPC)
729 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
730 else if (TARGET_POWER)
731 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
732 else
733 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
734 DONE;
735 }")
736
737 (define_insn "extendqihi2_ppc"
738 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
739 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
740 "TARGET_POWERPC"
741 "extsb %0,%1"
742 [(set_attr "type" "exts")])
743
744 (define_insn ""
745 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
746 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
747 (const_int 0)))
748 (clobber (match_scratch:HI 2 "=r,r"))]
749 "TARGET_POWERPC"
750 "@
751 extsb. %2,%1
752 #"
753 [(set_attr "type" "compare")
754 (set_attr "length" "4,8")])
755
756 (define_split
757 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
758 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
759 (const_int 0)))
760 (clobber (match_scratch:HI 2 ""))]
761 "TARGET_POWERPC && reload_completed"
762 [(set (match_dup 2)
763 (sign_extend:HI (match_dup 1)))
764 (set (match_dup 0)
765 (compare:CC (match_dup 2)
766 (const_int 0)))]
767 "")
768
769 (define_insn ""
770 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
771 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
772 (const_int 0)))
773 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
774 (sign_extend:HI (match_dup 1)))]
775 "TARGET_POWERPC"
776 "@
777 extsb. %0,%1
778 #"
779 [(set_attr "type" "compare")
780 (set_attr "length" "4,8")])
781
782 (define_split
783 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
784 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
785 (const_int 0)))
786 (set (match_operand:HI 0 "gpc_reg_operand" "")
787 (sign_extend:HI (match_dup 1)))]
788 "TARGET_POWERPC && reload_completed"
789 [(set (match_dup 0)
790 (sign_extend:HI (match_dup 1)))
791 (set (match_dup 2)
792 (compare:CC (match_dup 0)
793 (const_int 0)))]
794 "")
795
796 (define_expand "extendqihi2_power"
797 [(parallel [(set (match_dup 2)
798 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
799 (const_int 24)))
800 (clobber (scratch:SI))])
801 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
802 (ashiftrt:SI (match_dup 2)
803 (const_int 24)))
804 (clobber (scratch:SI))])]
805 "TARGET_POWER"
806 "
807 { operands[0] = gen_lowpart (SImode, operands[0]);
808 operands[1] = gen_lowpart (SImode, operands[1]);
809 operands[2] = gen_reg_rtx (SImode); }")
810
811 (define_expand "extendqihi2_no_power"
812 [(set (match_dup 2)
813 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
814 (const_int 24)))
815 (set (match_operand:HI 0 "gpc_reg_operand" "")
816 (ashiftrt:SI (match_dup 2)
817 (const_int 24)))]
818 "! TARGET_POWER && ! TARGET_POWERPC"
819 "
820 { operands[0] = gen_lowpart (SImode, operands[0]);
821 operands[1] = gen_lowpart (SImode, operands[1]);
822 operands[2] = gen_reg_rtx (SImode); }")
823
824 (define_expand "zero_extendhisi2"
825 [(set (match_operand:SI 0 "gpc_reg_operand" "")
826 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
827 ""
828 "")
829
830 (define_insn ""
831 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
832 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
833 ""
834 "@
835 lhz%U1%X1 %0,%1
836 {rlinm|rlwinm} %0,%1,0,0xffff"
837 [(set_attr "type" "load,*")])
838
839 (define_insn ""
840 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
841 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
842 (const_int 0)))
843 (clobber (match_scratch:SI 2 "=r,r"))]
844 ""
845 "@
846 {andil.|andi.} %2,%1,0xffff
847 #"
848 [(set_attr "type" "compare")
849 (set_attr "length" "4,8")])
850
851 (define_split
852 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
853 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
854 (const_int 0)))
855 (clobber (match_scratch:SI 2 ""))]
856 "reload_completed"
857 [(set (match_dup 2)
858 (zero_extend:SI (match_dup 1)))
859 (set (match_dup 0)
860 (compare:CC (match_dup 2)
861 (const_int 0)))]
862 "")
863
864 (define_insn ""
865 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
866 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
867 (const_int 0)))
868 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
869 (zero_extend:SI (match_dup 1)))]
870 ""
871 "@
872 {andil.|andi.} %0,%1,0xffff
873 #"
874 [(set_attr "type" "compare")
875 (set_attr "length" "4,8")])
876
877 (define_split
878 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
879 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
880 (const_int 0)))
881 (set (match_operand:SI 0 "gpc_reg_operand" "")
882 (zero_extend:SI (match_dup 1)))]
883 "reload_completed"
884 [(set (match_dup 0)
885 (zero_extend:SI (match_dup 1)))
886 (set (match_dup 2)
887 (compare:CC (match_dup 0)
888 (const_int 0)))]
889 "")
890
891 (define_expand "extendhisi2"
892 [(set (match_operand:SI 0 "gpc_reg_operand" "")
893 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
894 ""
895 "")
896
897 (define_insn ""
898 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
899 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
900 ""
901 "@
902 lha%U1%X1 %0,%1
903 {exts|extsh} %0,%1"
904 [(set_attr "type" "load_ext,exts")])
905
906 (define_insn ""
907 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
908 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
909 (const_int 0)))
910 (clobber (match_scratch:SI 2 "=r,r"))]
911 ""
912 "@
913 {exts.|extsh.} %2,%1
914 #"
915 [(set_attr "type" "compare")
916 (set_attr "length" "4,8")])
917
918 (define_split
919 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
920 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
921 (const_int 0)))
922 (clobber (match_scratch:SI 2 ""))]
923 "reload_completed"
924 [(set (match_dup 2)
925 (sign_extend:SI (match_dup 1)))
926 (set (match_dup 0)
927 (compare:CC (match_dup 2)
928 (const_int 0)))]
929 "")
930
931 (define_insn ""
932 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
933 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
934 (const_int 0)))
935 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
936 (sign_extend:SI (match_dup 1)))]
937 ""
938 "@
939 {exts.|extsh.} %0,%1
940 #"
941 [(set_attr "type" "compare")
942 (set_attr "length" "4,8")])
943 \f
944 ;; IBM 405, 440 and 464 half-word multiplication operations.
945
946 (define_insn "*macchwc"
947 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
948 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
949 (match_operand:SI 2 "gpc_reg_operand" "r")
950 (const_int 16))
951 (sign_extend:SI
952 (match_operand:HI 1 "gpc_reg_operand" "r")))
953 (match_operand:SI 4 "gpc_reg_operand" "0"))
954 (const_int 0)))
955 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
956 (plus:SI (mult:SI (ashiftrt:SI
957 (match_dup 2)
958 (const_int 16))
959 (sign_extend:SI
960 (match_dup 1)))
961 (match_dup 4)))]
962 "TARGET_MULHW"
963 "macchw. %0, %1, %2"
964 [(set_attr "type" "imul3")])
965
966 (define_insn "*macchw"
967 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
968 (plus:SI (mult:SI (ashiftrt:SI
969 (match_operand:SI 2 "gpc_reg_operand" "r")
970 (const_int 16))
971 (sign_extend:SI
972 (match_operand:HI 1 "gpc_reg_operand" "r")))
973 (match_operand:SI 3 "gpc_reg_operand" "0")))]
974 "TARGET_MULHW"
975 "macchw %0, %1, %2"
976 [(set_attr "type" "imul3")])
977
978 (define_insn "*macchwuc"
979 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
980 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
981 (match_operand:SI 2 "gpc_reg_operand" "r")
982 (const_int 16))
983 (zero_extend:SI
984 (match_operand:HI 1 "gpc_reg_operand" "r")))
985 (match_operand:SI 4 "gpc_reg_operand" "0"))
986 (const_int 0)))
987 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
988 (plus:SI (mult:SI (lshiftrt:SI
989 (match_dup 2)
990 (const_int 16))
991 (zero_extend:SI
992 (match_dup 1)))
993 (match_dup 4)))]
994 "TARGET_MULHW"
995 "macchwu. %0, %1, %2"
996 [(set_attr "type" "imul3")])
997
998 (define_insn "*macchwu"
999 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1000 (plus:SI (mult:SI (lshiftrt:SI
1001 (match_operand:SI 2 "gpc_reg_operand" "r")
1002 (const_int 16))
1003 (zero_extend:SI
1004 (match_operand:HI 1 "gpc_reg_operand" "r")))
1005 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1006 "TARGET_MULHW"
1007 "macchwu %0, %1, %2"
1008 [(set_attr "type" "imul3")])
1009
1010 (define_insn "*machhwc"
1011 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1012 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1013 (match_operand:SI 1 "gpc_reg_operand" "%r")
1014 (const_int 16))
1015 (ashiftrt:SI
1016 (match_operand:SI 2 "gpc_reg_operand" "r")
1017 (const_int 16)))
1018 (match_operand:SI 4 "gpc_reg_operand" "0"))
1019 (const_int 0)))
1020 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1021 (plus:SI (mult:SI (ashiftrt:SI
1022 (match_dup 1)
1023 (const_int 16))
1024 (ashiftrt:SI
1025 (match_dup 2)
1026 (const_int 16)))
1027 (match_dup 4)))]
1028 "TARGET_MULHW"
1029 "machhw. %0, %1, %2"
1030 [(set_attr "type" "imul3")])
1031
1032 (define_insn "*machhw"
1033 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1034 (plus:SI (mult:SI (ashiftrt:SI
1035 (match_operand:SI 1 "gpc_reg_operand" "%r")
1036 (const_int 16))
1037 (ashiftrt:SI
1038 (match_operand:SI 2 "gpc_reg_operand" "r")
1039 (const_int 16)))
1040 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1041 "TARGET_MULHW"
1042 "machhw %0, %1, %2"
1043 [(set_attr "type" "imul3")])
1044
1045 (define_insn "*machhwuc"
1046 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1047 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1048 (match_operand:SI 1 "gpc_reg_operand" "%r")
1049 (const_int 16))
1050 (lshiftrt:SI
1051 (match_operand:SI 2 "gpc_reg_operand" "r")
1052 (const_int 16)))
1053 (match_operand:SI 4 "gpc_reg_operand" "0"))
1054 (const_int 0)))
1055 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1056 (plus:SI (mult:SI (lshiftrt:SI
1057 (match_dup 1)
1058 (const_int 16))
1059 (lshiftrt:SI
1060 (match_dup 2)
1061 (const_int 16)))
1062 (match_dup 4)))]
1063 "TARGET_MULHW"
1064 "machhwu. %0, %1, %2"
1065 [(set_attr "type" "imul3")])
1066
1067 (define_insn "*machhwu"
1068 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1069 (plus:SI (mult:SI (lshiftrt:SI
1070 (match_operand:SI 1 "gpc_reg_operand" "%r")
1071 (const_int 16))
1072 (lshiftrt:SI
1073 (match_operand:SI 2 "gpc_reg_operand" "r")
1074 (const_int 16)))
1075 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1076 "TARGET_MULHW"
1077 "machhwu %0, %1, %2"
1078 [(set_attr "type" "imul3")])
1079
1080 (define_insn "*maclhwc"
1081 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1082 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1083 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1084 (sign_extend:SI
1085 (match_operand:HI 2 "gpc_reg_operand" "r")))
1086 (match_operand:SI 4 "gpc_reg_operand" "0"))
1087 (const_int 0)))
1088 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1089 (plus:SI (mult:SI (sign_extend:SI
1090 (match_dup 1))
1091 (sign_extend:SI
1092 (match_dup 2)))
1093 (match_dup 4)))]
1094 "TARGET_MULHW"
1095 "maclhw. %0, %1, %2"
1096 [(set_attr "type" "imul3")])
1097
1098 (define_insn "*maclhw"
1099 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1100 (plus:SI (mult:SI (sign_extend:SI
1101 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1102 (sign_extend:SI
1103 (match_operand:HI 2 "gpc_reg_operand" "r")))
1104 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1105 "TARGET_MULHW"
1106 "maclhw %0, %1, %2"
1107 [(set_attr "type" "imul3")])
1108
1109 (define_insn "*maclhwuc"
1110 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1111 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1112 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1113 (zero_extend:SI
1114 (match_operand:HI 2 "gpc_reg_operand" "r")))
1115 (match_operand:SI 4 "gpc_reg_operand" "0"))
1116 (const_int 0)))
1117 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1118 (plus:SI (mult:SI (zero_extend:SI
1119 (match_dup 1))
1120 (zero_extend:SI
1121 (match_dup 2)))
1122 (match_dup 4)))]
1123 "TARGET_MULHW"
1124 "maclhwu. %0, %1, %2"
1125 [(set_attr "type" "imul3")])
1126
1127 (define_insn "*maclhwu"
1128 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1129 (plus:SI (mult:SI (zero_extend:SI
1130 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1131 (zero_extend:SI
1132 (match_operand:HI 2 "gpc_reg_operand" "r")))
1133 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1134 "TARGET_MULHW"
1135 "maclhwu %0, %1, %2"
1136 [(set_attr "type" "imul3")])
1137
1138 (define_insn "*nmacchwc"
1139 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1140 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1141 (mult:SI (ashiftrt:SI
1142 (match_operand:SI 2 "gpc_reg_operand" "r")
1143 (const_int 16))
1144 (sign_extend:SI
1145 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1146 (const_int 0)))
1147 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1148 (minus:SI (match_dup 4)
1149 (mult:SI (ashiftrt:SI
1150 (match_dup 2)
1151 (const_int 16))
1152 (sign_extend:SI
1153 (match_dup 1)))))]
1154 "TARGET_MULHW"
1155 "nmacchw. %0, %1, %2"
1156 [(set_attr "type" "imul3")])
1157
1158 (define_insn "*nmacchw"
1159 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1160 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1161 (mult:SI (ashiftrt:SI
1162 (match_operand:SI 2 "gpc_reg_operand" "r")
1163 (const_int 16))
1164 (sign_extend:SI
1165 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1166 "TARGET_MULHW"
1167 "nmacchw %0, %1, %2"
1168 [(set_attr "type" "imul3")])
1169
1170 (define_insn "*nmachhwc"
1171 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1172 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1173 (mult:SI (ashiftrt:SI
1174 (match_operand:SI 1 "gpc_reg_operand" "%r")
1175 (const_int 16))
1176 (ashiftrt:SI
1177 (match_operand:SI 2 "gpc_reg_operand" "r")
1178 (const_int 16))))
1179 (const_int 0)))
1180 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1181 (minus:SI (match_dup 4)
1182 (mult:SI (ashiftrt:SI
1183 (match_dup 1)
1184 (const_int 16))
1185 (ashiftrt:SI
1186 (match_dup 2)
1187 (const_int 16)))))]
1188 "TARGET_MULHW"
1189 "nmachhw. %0, %1, %2"
1190 [(set_attr "type" "imul3")])
1191
1192 (define_insn "*nmachhw"
1193 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1194 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1195 (mult:SI (ashiftrt:SI
1196 (match_operand:SI 1 "gpc_reg_operand" "%r")
1197 (const_int 16))
1198 (ashiftrt:SI
1199 (match_operand:SI 2 "gpc_reg_operand" "r")
1200 (const_int 16)))))]
1201 "TARGET_MULHW"
1202 "nmachhw %0, %1, %2"
1203 [(set_attr "type" "imul3")])
1204
1205 (define_insn "*nmaclhwc"
1206 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1207 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1208 (mult:SI (sign_extend:SI
1209 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1210 (sign_extend:SI
1211 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1212 (const_int 0)))
1213 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1214 (minus:SI (match_dup 4)
1215 (mult:SI (sign_extend:SI
1216 (match_dup 1))
1217 (sign_extend:SI
1218 (match_dup 2)))))]
1219 "TARGET_MULHW"
1220 "nmaclhw. %0, %1, %2"
1221 [(set_attr "type" "imul3")])
1222
1223 (define_insn "*nmaclhw"
1224 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1225 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1226 (mult:SI (sign_extend:SI
1227 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1228 (sign_extend:SI
1229 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1230 "TARGET_MULHW"
1231 "nmaclhw %0, %1, %2"
1232 [(set_attr "type" "imul3")])
1233
1234 (define_insn "*mulchwc"
1235 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1236 (compare:CC (mult:SI (ashiftrt:SI
1237 (match_operand:SI 2 "gpc_reg_operand" "r")
1238 (const_int 16))
1239 (sign_extend:SI
1240 (match_operand:HI 1 "gpc_reg_operand" "r")))
1241 (const_int 0)))
1242 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1243 (mult:SI (ashiftrt:SI
1244 (match_dup 2)
1245 (const_int 16))
1246 (sign_extend:SI
1247 (match_dup 1))))]
1248 "TARGET_MULHW"
1249 "mulchw. %0, %1, %2"
1250 [(set_attr "type" "imul3")])
1251
1252 (define_insn "*mulchw"
1253 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1254 (mult:SI (ashiftrt:SI
1255 (match_operand:SI 2 "gpc_reg_operand" "r")
1256 (const_int 16))
1257 (sign_extend:SI
1258 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1259 "TARGET_MULHW"
1260 "mulchw %0, %1, %2"
1261 [(set_attr "type" "imul3")])
1262
1263 (define_insn "*mulchwuc"
1264 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1265 (compare:CC (mult:SI (lshiftrt:SI
1266 (match_operand:SI 2 "gpc_reg_operand" "r")
1267 (const_int 16))
1268 (zero_extend:SI
1269 (match_operand:HI 1 "gpc_reg_operand" "r")))
1270 (const_int 0)))
1271 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1272 (mult:SI (lshiftrt:SI
1273 (match_dup 2)
1274 (const_int 16))
1275 (zero_extend:SI
1276 (match_dup 1))))]
1277 "TARGET_MULHW"
1278 "mulchwu. %0, %1, %2"
1279 [(set_attr "type" "imul3")])
1280
1281 (define_insn "*mulchwu"
1282 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1283 (mult:SI (lshiftrt:SI
1284 (match_operand:SI 2 "gpc_reg_operand" "r")
1285 (const_int 16))
1286 (zero_extend:SI
1287 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1288 "TARGET_MULHW"
1289 "mulchwu %0, %1, %2"
1290 [(set_attr "type" "imul3")])
1291
1292 (define_insn "*mulhhwc"
1293 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1294 (compare:CC (mult:SI (ashiftrt:SI
1295 (match_operand:SI 1 "gpc_reg_operand" "%r")
1296 (const_int 16))
1297 (ashiftrt:SI
1298 (match_operand:SI 2 "gpc_reg_operand" "r")
1299 (const_int 16)))
1300 (const_int 0)))
1301 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1302 (mult:SI (ashiftrt:SI
1303 (match_dup 1)
1304 (const_int 16))
1305 (ashiftrt:SI
1306 (match_dup 2)
1307 (const_int 16))))]
1308 "TARGET_MULHW"
1309 "mulhhw. %0, %1, %2"
1310 [(set_attr "type" "imul3")])
1311
1312 (define_insn "*mulhhw"
1313 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1314 (mult:SI (ashiftrt:SI
1315 (match_operand:SI 1 "gpc_reg_operand" "%r")
1316 (const_int 16))
1317 (ashiftrt:SI
1318 (match_operand:SI 2 "gpc_reg_operand" "r")
1319 (const_int 16))))]
1320 "TARGET_MULHW"
1321 "mulhhw %0, %1, %2"
1322 [(set_attr "type" "imul3")])
1323
1324 (define_insn "*mulhhwuc"
1325 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1326 (compare:CC (mult:SI (lshiftrt:SI
1327 (match_operand:SI 1 "gpc_reg_operand" "%r")
1328 (const_int 16))
1329 (lshiftrt:SI
1330 (match_operand:SI 2 "gpc_reg_operand" "r")
1331 (const_int 16)))
1332 (const_int 0)))
1333 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1334 (mult:SI (lshiftrt:SI
1335 (match_dup 1)
1336 (const_int 16))
1337 (lshiftrt:SI
1338 (match_dup 2)
1339 (const_int 16))))]
1340 "TARGET_MULHW"
1341 "mulhhwu. %0, %1, %2"
1342 [(set_attr "type" "imul3")])
1343
1344 (define_insn "*mulhhwu"
1345 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1346 (mult:SI (lshiftrt:SI
1347 (match_operand:SI 1 "gpc_reg_operand" "%r")
1348 (const_int 16))
1349 (lshiftrt:SI
1350 (match_operand:SI 2 "gpc_reg_operand" "r")
1351 (const_int 16))))]
1352 "TARGET_MULHW"
1353 "mulhhwu %0, %1, %2"
1354 [(set_attr "type" "imul3")])
1355
1356 (define_insn "*mullhwc"
1357 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1358 (compare:CC (mult:SI (sign_extend:SI
1359 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1360 (sign_extend:SI
1361 (match_operand:HI 2 "gpc_reg_operand" "r")))
1362 (const_int 0)))
1363 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1364 (mult:SI (sign_extend:SI
1365 (match_dup 1))
1366 (sign_extend:SI
1367 (match_dup 2))))]
1368 "TARGET_MULHW"
1369 "mullhw. %0, %1, %2"
1370 [(set_attr "type" "imul3")])
1371
1372 (define_insn "*mullhw"
1373 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1374 (mult:SI (sign_extend:SI
1375 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1376 (sign_extend:SI
1377 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1378 "TARGET_MULHW"
1379 "mullhw %0, %1, %2"
1380 [(set_attr "type" "imul3")])
1381
1382 (define_insn "*mullhwuc"
1383 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1384 (compare:CC (mult:SI (zero_extend:SI
1385 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1386 (zero_extend:SI
1387 (match_operand:HI 2 "gpc_reg_operand" "r")))
1388 (const_int 0)))
1389 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1390 (mult:SI (zero_extend:SI
1391 (match_dup 1))
1392 (zero_extend:SI
1393 (match_dup 2))))]
1394 "TARGET_MULHW"
1395 "mullhwu. %0, %1, %2"
1396 [(set_attr "type" "imul3")])
1397
1398 (define_insn "*mullhwu"
1399 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1400 (mult:SI (zero_extend:SI
1401 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1402 (zero_extend:SI
1403 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1404 "TARGET_MULHW"
1405 "mullhwu %0, %1, %2"
1406 [(set_attr "type" "imul3")])
1407 \f
1408 ;; IBM 405, 440 and 464 string-search dlmzb instruction support.
1409 (define_insn "dlmzb"
1410 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1411 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1412 (match_operand:SI 2 "gpc_reg_operand" "r")]
1413 UNSPEC_DLMZB_CR))
1414 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1415 (unspec:SI [(match_dup 1)
1416 (match_dup 2)]
1417 UNSPEC_DLMZB))]
1418 "TARGET_DLMZB"
1419 "dlmzb. %0, %1, %2")
1420
1421 (define_expand "strlensi"
1422 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1423 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1424 (match_operand:QI 2 "const_int_operand" "")
1425 (match_operand 3 "const_int_operand" "")]
1426 UNSPEC_DLMZB_STRLEN))
1427 (clobber (match_scratch:CC 4 "=x"))]
1428 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1429 {
1430 rtx result = operands[0];
1431 rtx src = operands[1];
1432 rtx search_char = operands[2];
1433 rtx align = operands[3];
1434 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1435 rtx loop_label, end_label, mem, cr0, cond;
1436 if (search_char != const0_rtx
1437 || GET_CODE (align) != CONST_INT
1438 || INTVAL (align) < 8)
1439 FAIL;
1440 word1 = gen_reg_rtx (SImode);
1441 word2 = gen_reg_rtx (SImode);
1442 scratch_dlmzb = gen_reg_rtx (SImode);
1443 scratch_string = gen_reg_rtx (Pmode);
1444 loop_label = gen_label_rtx ();
1445 end_label = gen_label_rtx ();
1446 addr = force_reg (Pmode, XEXP (src, 0));
1447 emit_move_insn (scratch_string, addr);
1448 emit_label (loop_label);
1449 mem = change_address (src, SImode, scratch_string);
1450 emit_move_insn (word1, mem);
1451 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1452 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1453 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1454 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1455 emit_jump_insn (gen_rtx_SET (VOIDmode,
1456 pc_rtx,
1457 gen_rtx_IF_THEN_ELSE (VOIDmode,
1458 cond,
1459 gen_rtx_LABEL_REF
1460 (VOIDmode,
1461 end_label),
1462 pc_rtx)));
1463 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1464 emit_jump_insn (gen_rtx_SET (VOIDmode,
1465 pc_rtx,
1466 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1467 emit_barrier ();
1468 emit_label (end_label);
1469 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1470 emit_insn (gen_subsi3 (result, scratch_string, addr));
1471 emit_insn (gen_subsi3 (result, result, const1_rtx));
1472 DONE;
1473 })
1474 \f
1475 (define_split
1476 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1477 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1478 (const_int 0)))
1479 (set (match_operand:SI 0 "gpc_reg_operand" "")
1480 (sign_extend:SI (match_dup 1)))]
1481 "reload_completed"
1482 [(set (match_dup 0)
1483 (sign_extend:SI (match_dup 1)))
1484 (set (match_dup 2)
1485 (compare:CC (match_dup 0)
1486 (const_int 0)))]
1487 "")
1488
1489 ;; Fixed-point arithmetic insns.
1490
1491 (define_expand "add<mode>3"
1492 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1493 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1494 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1495 ""
1496 {
1497 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1498 {
1499 if (non_short_cint_operand (operands[2], DImode))
1500 FAIL;
1501 }
1502 else if (GET_CODE (operands[2]) == CONST_INT
1503 && ! add_operand (operands[2], <MODE>mode))
1504 {
1505 rtx tmp = ((!can_create_pseudo_p ()
1506 || rtx_equal_p (operands[0], operands[1]))
1507 ? operands[0] : gen_reg_rtx (<MODE>mode));
1508
1509 HOST_WIDE_INT val = INTVAL (operands[2]);
1510 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1511 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1512
1513 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1514 FAIL;
1515
1516 /* The ordering here is important for the prolog expander.
1517 When space is allocated from the stack, adding 'low' first may
1518 produce a temporary deallocation (which would be bad). */
1519 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1520 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1521 DONE;
1522 }
1523 })
1524
1525 ;; Discourage ai/addic because of carry but provide it in an alternative
1526 ;; allowing register zero as source.
1527 (define_insn "*add<mode>3_internal1"
1528 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1529 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1530 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1531 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1532 "@
1533 {cax|add} %0,%1,%2
1534 {cal %0,%2(%1)|addi %0,%1,%2}
1535 {ai|addic} %0,%1,%2
1536 {cau|addis} %0,%1,%v2"
1537 [(set_attr "length" "4,4,4,4")])
1538
1539 (define_insn "addsi3_high"
1540 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1541 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1542 (high:SI (match_operand 2 "" ""))))]
1543 "TARGET_MACHO && !TARGET_64BIT"
1544 "{cau|addis} %0,%1,ha16(%2)"
1545 [(set_attr "length" "4")])
1546
1547 (define_insn "*add<mode>3_internal2"
1548 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1549 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1550 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1551 (const_int 0)))
1552 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1553 ""
1554 "@
1555 {cax.|add.} %3,%1,%2
1556 {ai.|addic.} %3,%1,%2
1557 #
1558 #"
1559 [(set_attr "type" "fast_compare,compare,compare,compare")
1560 (set_attr "length" "4,4,8,8")])
1561
1562 (define_split
1563 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1564 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1565 (match_operand:GPR 2 "reg_or_short_operand" ""))
1566 (const_int 0)))
1567 (clobber (match_scratch:GPR 3 ""))]
1568 "reload_completed"
1569 [(set (match_dup 3)
1570 (plus:GPR (match_dup 1)
1571 (match_dup 2)))
1572 (set (match_dup 0)
1573 (compare:CC (match_dup 3)
1574 (const_int 0)))]
1575 "")
1576
1577 (define_insn "*add<mode>3_internal3"
1578 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1579 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1580 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1581 (const_int 0)))
1582 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1583 (plus:P (match_dup 1)
1584 (match_dup 2)))]
1585 ""
1586 "@
1587 {cax.|add.} %0,%1,%2
1588 {ai.|addic.} %0,%1,%2
1589 #
1590 #"
1591 [(set_attr "type" "fast_compare,compare,compare,compare")
1592 (set_attr "length" "4,4,8,8")])
1593
1594 (define_split
1595 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1596 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1597 (match_operand:P 2 "reg_or_short_operand" ""))
1598 (const_int 0)))
1599 (set (match_operand:P 0 "gpc_reg_operand" "")
1600 (plus:P (match_dup 1) (match_dup 2)))]
1601 "reload_completed"
1602 [(set (match_dup 0)
1603 (plus:P (match_dup 1)
1604 (match_dup 2)))
1605 (set (match_dup 3)
1606 (compare:CC (match_dup 0)
1607 (const_int 0)))]
1608 "")
1609
1610 ;; Split an add that we can't do in one insn into two insns, each of which
1611 ;; does one 16-bit part. This is used by combine. Note that the low-order
1612 ;; add should be last in case the result gets used in an address.
1613
1614 (define_split
1615 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1616 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1617 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1618 ""
1619 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1620 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1621 {
1622 HOST_WIDE_INT val = INTVAL (operands[2]);
1623 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1624 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1625
1626 operands[4] = GEN_INT (low);
1627 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1628 operands[3] = GEN_INT (rest);
1629 else if (can_create_pseudo_p ())
1630 {
1631 operands[3] = gen_reg_rtx (DImode);
1632 emit_move_insn (operands[3], operands[2]);
1633 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1634 DONE;
1635 }
1636 else
1637 FAIL;
1638 })
1639
1640 (define_insn "one_cmpl<mode>2"
1641 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1642 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1643 ""
1644 "nor %0,%1,%1")
1645
1646 (define_insn ""
1647 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1648 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1649 (const_int 0)))
1650 (clobber (match_scratch:P 2 "=r,r"))]
1651 ""
1652 "@
1653 nor. %2,%1,%1
1654 #"
1655 [(set_attr "type" "compare")
1656 (set_attr "length" "4,8")])
1657
1658 (define_split
1659 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1660 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1661 (const_int 0)))
1662 (clobber (match_scratch:P 2 ""))]
1663 "reload_completed"
1664 [(set (match_dup 2)
1665 (not:P (match_dup 1)))
1666 (set (match_dup 0)
1667 (compare:CC (match_dup 2)
1668 (const_int 0)))]
1669 "")
1670
1671 (define_insn ""
1672 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1673 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1674 (const_int 0)))
1675 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1676 (not:P (match_dup 1)))]
1677 ""
1678 "@
1679 nor. %0,%1,%1
1680 #"
1681 [(set_attr "type" "compare")
1682 (set_attr "length" "4,8")])
1683
1684 (define_split
1685 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1686 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1687 (const_int 0)))
1688 (set (match_operand:P 0 "gpc_reg_operand" "")
1689 (not:P (match_dup 1)))]
1690 "reload_completed"
1691 [(set (match_dup 0)
1692 (not:P (match_dup 1)))
1693 (set (match_dup 2)
1694 (compare:CC (match_dup 0)
1695 (const_int 0)))]
1696 "")
1697
1698 (define_insn ""
1699 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1700 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1701 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1702 "! TARGET_POWERPC"
1703 "{sf%I1|subf%I1c} %0,%2,%1")
1704
1705 (define_insn ""
1706 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1707 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1708 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1709 "TARGET_POWERPC"
1710 "@
1711 subf %0,%2,%1
1712 subfic %0,%2,%1")
1713
1714 (define_insn ""
1715 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1716 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1717 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1718 (const_int 0)))
1719 (clobber (match_scratch:SI 3 "=r,r"))]
1720 "! TARGET_POWERPC"
1721 "@
1722 {sf.|subfc.} %3,%2,%1
1723 #"
1724 [(set_attr "type" "compare")
1725 (set_attr "length" "4,8")])
1726
1727 (define_insn ""
1728 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1729 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1730 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1731 (const_int 0)))
1732 (clobber (match_scratch:P 3 "=r,r"))]
1733 "TARGET_POWERPC"
1734 "@
1735 subf. %3,%2,%1
1736 #"
1737 [(set_attr "type" "fast_compare")
1738 (set_attr "length" "4,8")])
1739
1740 (define_split
1741 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1742 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1743 (match_operand:P 2 "gpc_reg_operand" ""))
1744 (const_int 0)))
1745 (clobber (match_scratch:P 3 ""))]
1746 "reload_completed"
1747 [(set (match_dup 3)
1748 (minus:P (match_dup 1)
1749 (match_dup 2)))
1750 (set (match_dup 0)
1751 (compare:CC (match_dup 3)
1752 (const_int 0)))]
1753 "")
1754
1755 (define_insn ""
1756 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1757 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1758 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1759 (const_int 0)))
1760 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1761 (minus:SI (match_dup 1) (match_dup 2)))]
1762 "! TARGET_POWERPC"
1763 "@
1764 {sf.|subfc.} %0,%2,%1
1765 #"
1766 [(set_attr "type" "compare")
1767 (set_attr "length" "4,8")])
1768
1769 (define_insn ""
1770 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1771 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1772 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1773 (const_int 0)))
1774 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1775 (minus:P (match_dup 1)
1776 (match_dup 2)))]
1777 "TARGET_POWERPC"
1778 "@
1779 subf. %0,%2,%1
1780 #"
1781 [(set_attr "type" "fast_compare")
1782 (set_attr "length" "4,8")])
1783
1784 (define_split
1785 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1786 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1787 (match_operand:P 2 "gpc_reg_operand" ""))
1788 (const_int 0)))
1789 (set (match_operand:P 0 "gpc_reg_operand" "")
1790 (minus:P (match_dup 1)
1791 (match_dup 2)))]
1792 "reload_completed"
1793 [(set (match_dup 0)
1794 (minus:P (match_dup 1)
1795 (match_dup 2)))
1796 (set (match_dup 3)
1797 (compare:CC (match_dup 0)
1798 (const_int 0)))]
1799 "")
1800
1801 (define_expand "sub<mode>3"
1802 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1803 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1804 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1805 ""
1806 "
1807 {
1808 if (GET_CODE (operands[2]) == CONST_INT)
1809 {
1810 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1811 negate_rtx (<MODE>mode, operands[2])));
1812 DONE;
1813 }
1814 }")
1815
1816 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1817 ;; instruction and some auxiliary computations. Then we just have a single
1818 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1819 ;; combine.
1820
1821 (define_expand "sminsi3"
1822 [(set (match_dup 3)
1823 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1824 (match_operand:SI 2 "reg_or_short_operand" ""))
1825 (const_int 0)
1826 (minus:SI (match_dup 2) (match_dup 1))))
1827 (set (match_operand:SI 0 "gpc_reg_operand" "")
1828 (minus:SI (match_dup 2) (match_dup 3)))]
1829 "TARGET_POWER || TARGET_ISEL"
1830 "
1831 {
1832 if (TARGET_ISEL)
1833 {
1834 operands[2] = force_reg (SImode, operands[2]);
1835 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1836 DONE;
1837 }
1838
1839 operands[3] = gen_reg_rtx (SImode);
1840 }")
1841
1842 (define_split
1843 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1844 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1845 (match_operand:SI 2 "reg_or_short_operand" "")))
1846 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1847 "TARGET_POWER"
1848 [(set (match_dup 3)
1849 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1850 (const_int 0)
1851 (minus:SI (match_dup 2) (match_dup 1))))
1852 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1853 "")
1854
1855 (define_expand "smaxsi3"
1856 [(set (match_dup 3)
1857 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1858 (match_operand:SI 2 "reg_or_short_operand" ""))
1859 (const_int 0)
1860 (minus:SI (match_dup 2) (match_dup 1))))
1861 (set (match_operand:SI 0 "gpc_reg_operand" "")
1862 (plus:SI (match_dup 3) (match_dup 1)))]
1863 "TARGET_POWER || TARGET_ISEL"
1864 "
1865 {
1866 if (TARGET_ISEL)
1867 {
1868 operands[2] = force_reg (SImode, operands[2]);
1869 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1870 DONE;
1871 }
1872 operands[3] = gen_reg_rtx (SImode);
1873 }")
1874
1875 (define_split
1876 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1877 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1878 (match_operand:SI 2 "reg_or_short_operand" "")))
1879 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1880 "TARGET_POWER"
1881 [(set (match_dup 3)
1882 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1883 (const_int 0)
1884 (minus:SI (match_dup 2) (match_dup 1))))
1885 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1886 "")
1887
1888 (define_expand "uminsi3"
1889 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1890 (match_dup 5)))
1891 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1892 (match_dup 5)))
1893 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1894 (const_int 0)
1895 (minus:SI (match_dup 4) (match_dup 3))))
1896 (set (match_operand:SI 0 "gpc_reg_operand" "")
1897 (minus:SI (match_dup 2) (match_dup 3)))]
1898 "TARGET_POWER || TARGET_ISEL"
1899 "
1900 {
1901 if (TARGET_ISEL)
1902 {
1903 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1904 DONE;
1905 }
1906 operands[3] = gen_reg_rtx (SImode);
1907 operands[4] = gen_reg_rtx (SImode);
1908 operands[5] = GEN_INT (-2147483647 - 1);
1909 }")
1910
1911 (define_expand "umaxsi3"
1912 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1913 (match_dup 5)))
1914 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1915 (match_dup 5)))
1916 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1917 (const_int 0)
1918 (minus:SI (match_dup 4) (match_dup 3))))
1919 (set (match_operand:SI 0 "gpc_reg_operand" "")
1920 (plus:SI (match_dup 3) (match_dup 1)))]
1921 "TARGET_POWER || TARGET_ISEL"
1922 "
1923 {
1924 if (TARGET_ISEL)
1925 {
1926 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1927 DONE;
1928 }
1929 operands[3] = gen_reg_rtx (SImode);
1930 operands[4] = gen_reg_rtx (SImode);
1931 operands[5] = GEN_INT (-2147483647 - 1);
1932 }")
1933
1934 (define_insn ""
1935 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1936 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1937 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1938 (const_int 0)
1939 (minus:SI (match_dup 2) (match_dup 1))))]
1940 "TARGET_POWER"
1941 "doz%I2 %0,%1,%2")
1942
1943 (define_insn ""
1944 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1945 (compare:CC
1946 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1947 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1948 (const_int 0)
1949 (minus:SI (match_dup 2) (match_dup 1)))
1950 (const_int 0)))
1951 (clobber (match_scratch:SI 3 "=r,r"))]
1952 "TARGET_POWER"
1953 "@
1954 doz%I2. %3,%1,%2
1955 #"
1956 [(set_attr "type" "delayed_compare")
1957 (set_attr "length" "4,8")])
1958
1959 (define_split
1960 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1961 (compare:CC
1962 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1963 (match_operand:SI 2 "reg_or_short_operand" ""))
1964 (const_int 0)
1965 (minus:SI (match_dup 2) (match_dup 1)))
1966 (const_int 0)))
1967 (clobber (match_scratch:SI 3 ""))]
1968 "TARGET_POWER && reload_completed"
1969 [(set (match_dup 3)
1970 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1971 (const_int 0)
1972 (minus:SI (match_dup 2) (match_dup 1))))
1973 (set (match_dup 0)
1974 (compare:CC (match_dup 3)
1975 (const_int 0)))]
1976 "")
1977
1978 (define_insn ""
1979 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1980 (compare:CC
1981 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1982 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1983 (const_int 0)
1984 (minus:SI (match_dup 2) (match_dup 1)))
1985 (const_int 0)))
1986 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1987 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1988 (const_int 0)
1989 (minus:SI (match_dup 2) (match_dup 1))))]
1990 "TARGET_POWER"
1991 "@
1992 doz%I2. %0,%1,%2
1993 #"
1994 [(set_attr "type" "delayed_compare")
1995 (set_attr "length" "4,8")])
1996
1997 (define_split
1998 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1999 (compare:CC
2000 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2001 (match_operand:SI 2 "reg_or_short_operand" ""))
2002 (const_int 0)
2003 (minus:SI (match_dup 2) (match_dup 1)))
2004 (const_int 0)))
2005 (set (match_operand:SI 0 "gpc_reg_operand" "")
2006 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2007 (const_int 0)
2008 (minus:SI (match_dup 2) (match_dup 1))))]
2009 "TARGET_POWER && reload_completed"
2010 [(set (match_dup 0)
2011 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2012 (const_int 0)
2013 (minus:SI (match_dup 2) (match_dup 1))))
2014 (set (match_dup 3)
2015 (compare:CC (match_dup 0)
2016 (const_int 0)))]
2017 "")
2018
2019 ;; We don't need abs with condition code because such comparisons should
2020 ;; never be done.
2021 (define_expand "abssi2"
2022 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2023 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2024 ""
2025 "
2026 {
2027 if (TARGET_ISEL)
2028 {
2029 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
2030 DONE;
2031 }
2032 else if (! TARGET_POWER)
2033 {
2034 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2035 DONE;
2036 }
2037 }")
2038
2039 (define_insn "*abssi2_power"
2040 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2041 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2042 "TARGET_POWER"
2043 "abs %0,%1")
2044
2045 (define_insn_and_split "abssi2_isel"
2046 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2047 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
2048 (clobber (match_scratch:SI 2 "=&b"))
2049 (clobber (match_scratch:CC 3 "=y"))]
2050 "TARGET_ISEL"
2051 "#"
2052 "&& reload_completed"
2053 [(set (match_dup 2) (neg:SI (match_dup 1)))
2054 (set (match_dup 3)
2055 (compare:CC (match_dup 1)
2056 (const_int 0)))
2057 (set (match_dup 0)
2058 (if_then_else:SI (ge (match_dup 3)
2059 (const_int 0))
2060 (match_dup 1)
2061 (match_dup 2)))]
2062 "")
2063
2064 (define_insn_and_split "abssi2_nopower"
2065 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2066 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2067 (clobber (match_scratch:SI 2 "=&r,&r"))]
2068 "! TARGET_POWER && ! TARGET_ISEL"
2069 "#"
2070 "&& reload_completed"
2071 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2072 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2073 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2074 "")
2075
2076 (define_insn "*nabs_power"
2077 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2078 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2079 "TARGET_POWER"
2080 "nabs %0,%1")
2081
2082 (define_insn_and_split "*nabs_nopower"
2083 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2084 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2085 (clobber (match_scratch:SI 2 "=&r,&r"))]
2086 "! TARGET_POWER"
2087 "#"
2088 "&& reload_completed"
2089 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2090 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2091 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2092 "")
2093
2094 (define_expand "neg<mode>2"
2095 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2096 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2097 ""
2098 "")
2099
2100 (define_insn "*neg<mode>2_internal"
2101 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2102 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2103 ""
2104 "neg %0,%1")
2105
2106 (define_insn ""
2107 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2108 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2109 (const_int 0)))
2110 (clobber (match_scratch:P 2 "=r,r"))]
2111 ""
2112 "@
2113 neg. %2,%1
2114 #"
2115 [(set_attr "type" "fast_compare")
2116 (set_attr "length" "4,8")])
2117
2118 (define_split
2119 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2120 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2121 (const_int 0)))
2122 (clobber (match_scratch:P 2 ""))]
2123 "reload_completed"
2124 [(set (match_dup 2)
2125 (neg:P (match_dup 1)))
2126 (set (match_dup 0)
2127 (compare:CC (match_dup 2)
2128 (const_int 0)))]
2129 "")
2130
2131 (define_insn ""
2132 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2133 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2134 (const_int 0)))
2135 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2136 (neg:P (match_dup 1)))]
2137 ""
2138 "@
2139 neg. %0,%1
2140 #"
2141 [(set_attr "type" "fast_compare")
2142 (set_attr "length" "4,8")])
2143
2144 (define_split
2145 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2146 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2147 (const_int 0)))
2148 (set (match_operand:P 0 "gpc_reg_operand" "")
2149 (neg:P (match_dup 1)))]
2150 "reload_completed"
2151 [(set (match_dup 0)
2152 (neg:P (match_dup 1)))
2153 (set (match_dup 2)
2154 (compare:CC (match_dup 0)
2155 (const_int 0)))]
2156 "")
2157
2158 (define_insn "clz<mode>2"
2159 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2160 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2161 ""
2162 "{cntlz|cntlz<wd>} %0,%1"
2163 [(set_attr "type" "cntlz")])
2164
2165 (define_expand "ctz<mode>2"
2166 [(set (match_dup 2)
2167 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2168 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2169 (match_dup 2)))
2170 (clobber (scratch:CC))])
2171 (set (match_dup 4) (clz:GPR (match_dup 3)))
2172 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2173 (minus:GPR (match_dup 5) (match_dup 4)))]
2174 ""
2175 {
2176 operands[2] = gen_reg_rtx (<MODE>mode);
2177 operands[3] = gen_reg_rtx (<MODE>mode);
2178 operands[4] = gen_reg_rtx (<MODE>mode);
2179 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2180 })
2181
2182 (define_expand "ffs<mode>2"
2183 [(set (match_dup 2)
2184 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2185 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2186 (match_dup 2)))
2187 (clobber (scratch:CC))])
2188 (set (match_dup 4) (clz:GPR (match_dup 3)))
2189 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2190 (minus:GPR (match_dup 5) (match_dup 4)))]
2191 ""
2192 {
2193 operands[2] = gen_reg_rtx (<MODE>mode);
2194 operands[3] = gen_reg_rtx (<MODE>mode);
2195 operands[4] = gen_reg_rtx (<MODE>mode);
2196 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2197 })
2198
2199 (define_insn "popcntb<mode>2"
2200 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2201 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2202 UNSPEC_POPCNTB))]
2203 "TARGET_POPCNTB"
2204 "popcntb %0,%1")
2205
2206 (define_expand "popcount<mode>2"
2207 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2208 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2209 "TARGET_POPCNTB"
2210 {
2211 rs6000_emit_popcount (operands[0], operands[1]);
2212 DONE;
2213 })
2214
2215 (define_expand "parity<mode>2"
2216 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2217 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2218 "TARGET_POPCNTB"
2219 {
2220 rs6000_emit_parity (operands[0], operands[1]);
2221 DONE;
2222 })
2223
2224 (define_insn "bswapsi2"
2225 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2226 (bswap:SI (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2227 ""
2228 "@
2229 {lbrx|lwbrx} %0,%y1
2230 {stbrx|stwbrx} %1,%y0
2231 #"
2232 [(set_attr "length" "4,4,12")])
2233
2234 (define_split
2235 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2236 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2237 "reload_completed"
2238 [(set (match_dup 0)
2239 (rotate:SI (match_dup 1) (const_int 8)))
2240 (set (zero_extract:SI (match_dup 0)
2241 (const_int 8)
2242 (const_int 0))
2243 (match_dup 1))
2244 (set (zero_extract:SI (match_dup 0)
2245 (const_int 8)
2246 (const_int 16))
2247 (rotate:SI (match_dup 1)
2248 (const_int 16)))]
2249 "")
2250
2251 (define_expand "mulsi3"
2252 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2253 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2254 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2255 ""
2256 "
2257 {
2258 if (TARGET_POWER)
2259 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2260 else
2261 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2262 DONE;
2263 }")
2264
2265 (define_insn "mulsi3_mq"
2266 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2267 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2268 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2269 (clobber (match_scratch:SI 3 "=q,q"))]
2270 "TARGET_POWER"
2271 "@
2272 {muls|mullw} %0,%1,%2
2273 {muli|mulli} %0,%1,%2"
2274 [(set (attr "type")
2275 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2276 (const_string "imul3")
2277 (match_operand:SI 2 "short_cint_operand" "")
2278 (const_string "imul2")]
2279 (const_string "imul")))])
2280
2281 (define_insn "mulsi3_no_mq"
2282 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2283 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2284 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2285 "! TARGET_POWER"
2286 "@
2287 {muls|mullw} %0,%1,%2
2288 {muli|mulli} %0,%1,%2"
2289 [(set (attr "type")
2290 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2291 (const_string "imul3")
2292 (match_operand:SI 2 "short_cint_operand" "")
2293 (const_string "imul2")]
2294 (const_string "imul")))])
2295
2296 (define_insn "*mulsi3_mq_internal1"
2297 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2298 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2299 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2300 (const_int 0)))
2301 (clobber (match_scratch:SI 3 "=r,r"))
2302 (clobber (match_scratch:SI 4 "=q,q"))]
2303 "TARGET_POWER"
2304 "@
2305 {muls.|mullw.} %3,%1,%2
2306 #"
2307 [(set_attr "type" "imul_compare")
2308 (set_attr "length" "4,8")])
2309
2310 (define_split
2311 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2312 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2313 (match_operand:SI 2 "gpc_reg_operand" ""))
2314 (const_int 0)))
2315 (clobber (match_scratch:SI 3 ""))
2316 (clobber (match_scratch:SI 4 ""))]
2317 "TARGET_POWER && reload_completed"
2318 [(parallel [(set (match_dup 3)
2319 (mult:SI (match_dup 1) (match_dup 2)))
2320 (clobber (match_dup 4))])
2321 (set (match_dup 0)
2322 (compare:CC (match_dup 3)
2323 (const_int 0)))]
2324 "")
2325
2326 (define_insn "*mulsi3_no_mq_internal1"
2327 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2328 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2329 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2330 (const_int 0)))
2331 (clobber (match_scratch:SI 3 "=r,r"))]
2332 "! TARGET_POWER"
2333 "@
2334 {muls.|mullw.} %3,%1,%2
2335 #"
2336 [(set_attr "type" "imul_compare")
2337 (set_attr "length" "4,8")])
2338
2339 (define_split
2340 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2341 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2342 (match_operand:SI 2 "gpc_reg_operand" ""))
2343 (const_int 0)))
2344 (clobber (match_scratch:SI 3 ""))]
2345 "! TARGET_POWER && reload_completed"
2346 [(set (match_dup 3)
2347 (mult:SI (match_dup 1) (match_dup 2)))
2348 (set (match_dup 0)
2349 (compare:CC (match_dup 3)
2350 (const_int 0)))]
2351 "")
2352
2353 (define_insn "*mulsi3_mq_internal2"
2354 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2355 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2356 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2357 (const_int 0)))
2358 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2359 (mult:SI (match_dup 1) (match_dup 2)))
2360 (clobber (match_scratch:SI 4 "=q,q"))]
2361 "TARGET_POWER"
2362 "@
2363 {muls.|mullw.} %0,%1,%2
2364 #"
2365 [(set_attr "type" "imul_compare")
2366 (set_attr "length" "4,8")])
2367
2368 (define_split
2369 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2370 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2371 (match_operand:SI 2 "gpc_reg_operand" ""))
2372 (const_int 0)))
2373 (set (match_operand:SI 0 "gpc_reg_operand" "")
2374 (mult:SI (match_dup 1) (match_dup 2)))
2375 (clobber (match_scratch:SI 4 ""))]
2376 "TARGET_POWER && reload_completed"
2377 [(parallel [(set (match_dup 0)
2378 (mult:SI (match_dup 1) (match_dup 2)))
2379 (clobber (match_dup 4))])
2380 (set (match_dup 3)
2381 (compare:CC (match_dup 0)
2382 (const_int 0)))]
2383 "")
2384
2385 (define_insn "*mulsi3_no_mq_internal2"
2386 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2387 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2388 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2389 (const_int 0)))
2390 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2391 (mult:SI (match_dup 1) (match_dup 2)))]
2392 "! TARGET_POWER"
2393 "@
2394 {muls.|mullw.} %0,%1,%2
2395 #"
2396 [(set_attr "type" "imul_compare")
2397 (set_attr "length" "4,8")])
2398
2399 (define_split
2400 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2401 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2402 (match_operand:SI 2 "gpc_reg_operand" ""))
2403 (const_int 0)))
2404 (set (match_operand:SI 0 "gpc_reg_operand" "")
2405 (mult:SI (match_dup 1) (match_dup 2)))]
2406 "! TARGET_POWER && reload_completed"
2407 [(set (match_dup 0)
2408 (mult:SI (match_dup 1) (match_dup 2)))
2409 (set (match_dup 3)
2410 (compare:CC (match_dup 0)
2411 (const_int 0)))]
2412 "")
2413
2414 ;; Operand 1 is divided by operand 2; quotient goes to operand
2415 ;; 0 and remainder to operand 3.
2416 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2417
2418 (define_expand "divmodsi4"
2419 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2420 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2421 (match_operand:SI 2 "gpc_reg_operand" "")))
2422 (set (match_operand:SI 3 "register_operand" "")
2423 (mod:SI (match_dup 1) (match_dup 2)))])]
2424 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2425 "
2426 {
2427 if (! TARGET_POWER && ! TARGET_POWERPC)
2428 {
2429 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2430 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2431 emit_insn (gen_divss_call ());
2432 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2433 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2434 DONE;
2435 }
2436 }")
2437
2438 (define_insn "*divmodsi4_internal"
2439 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2440 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2441 (match_operand:SI 2 "gpc_reg_operand" "r")))
2442 (set (match_operand:SI 3 "register_operand" "=q")
2443 (mod:SI (match_dup 1) (match_dup 2)))]
2444 "TARGET_POWER"
2445 "divs %0,%1,%2"
2446 [(set_attr "type" "idiv")])
2447
2448 (define_expand "udiv<mode>3"
2449 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2450 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2451 (match_operand:GPR 2 "gpc_reg_operand" "")))]
2452 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2453 "
2454 {
2455 if (! TARGET_POWER && ! TARGET_POWERPC)
2456 {
2457 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2458 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2459 emit_insn (gen_quous_call ());
2460 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2461 DONE;
2462 }
2463 else if (TARGET_POWER)
2464 {
2465 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2466 DONE;
2467 }
2468 }")
2469
2470 (define_insn "udivsi3_mq"
2471 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2472 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2473 (match_operand:SI 2 "gpc_reg_operand" "r")))
2474 (clobber (match_scratch:SI 3 "=q"))]
2475 "TARGET_POWERPC && TARGET_POWER"
2476 "divwu %0,%1,%2"
2477 [(set_attr "type" "idiv")])
2478
2479 (define_insn "*udivsi3_no_mq"
2480 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2481 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2482 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2483 "TARGET_POWERPC && ! TARGET_POWER"
2484 "div<wd>u %0,%1,%2"
2485 [(set (attr "type")
2486 (cond [(match_operand:SI 0 "" "")
2487 (const_string "idiv")]
2488 (const_string "ldiv")))])
2489
2490
2491 ;; For powers of two we can do srai/aze for divide and then adjust for
2492 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2493 ;; used; for PowerPC, force operands into register and do a normal divide;
2494 ;; for AIX common-mode, use quoss call on register operands.
2495 (define_expand "div<mode>3"
2496 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2497 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2498 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2499 ""
2500 "
2501 {
2502 if (GET_CODE (operands[2]) == CONST_INT
2503 && INTVAL (operands[2]) > 0
2504 && exact_log2 (INTVAL (operands[2])) >= 0)
2505 ;
2506 else if (TARGET_POWERPC)
2507 {
2508 operands[2] = force_reg (<MODE>mode, operands[2]);
2509 if (TARGET_POWER)
2510 {
2511 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2512 DONE;
2513 }
2514 }
2515 else if (TARGET_POWER)
2516 FAIL;
2517 else
2518 {
2519 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2520 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2521 emit_insn (gen_quoss_call ());
2522 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2523 DONE;
2524 }
2525 }")
2526
2527 (define_insn "divsi3_mq"
2528 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2529 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2530 (match_operand:SI 2 "gpc_reg_operand" "r")))
2531 (clobber (match_scratch:SI 3 "=q"))]
2532 "TARGET_POWERPC && TARGET_POWER"
2533 "divw %0,%1,%2"
2534 [(set_attr "type" "idiv")])
2535
2536 (define_insn "*div<mode>3_no_mq"
2537 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2538 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2539 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2540 "TARGET_POWERPC && ! TARGET_POWER"
2541 "div<wd> %0,%1,%2"
2542 [(set (attr "type")
2543 (cond [(match_operand:SI 0 "" "")
2544 (const_string "idiv")]
2545 (const_string "ldiv")))])
2546
2547 (define_expand "mod<mode>3"
2548 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2549 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2550 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2551 ""
2552 "
2553 {
2554 int i;
2555 rtx temp1;
2556 rtx temp2;
2557
2558 if (GET_CODE (operands[2]) != CONST_INT
2559 || INTVAL (operands[2]) <= 0
2560 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2561 FAIL;
2562
2563 temp1 = gen_reg_rtx (<MODE>mode);
2564 temp2 = gen_reg_rtx (<MODE>mode);
2565
2566 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2567 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2568 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2569 DONE;
2570 }")
2571
2572 (define_insn ""
2573 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2574 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2575 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2576 ""
2577 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
2578 [(set_attr "type" "two")
2579 (set_attr "length" "8")])
2580
2581 (define_insn ""
2582 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2583 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2584 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2585 (const_int 0)))
2586 (clobber (match_scratch:P 3 "=r,r"))]
2587 ""
2588 "@
2589 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
2590 #"
2591 [(set_attr "type" "compare")
2592 (set_attr "length" "8,12")])
2593
2594 (define_split
2595 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2596 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2597 (match_operand:GPR 2 "exact_log2_cint_operand"
2598 ""))
2599 (const_int 0)))
2600 (clobber (match_scratch:GPR 3 ""))]
2601 "reload_completed"
2602 [(set (match_dup 3)
2603 (div:<MODE> (match_dup 1) (match_dup 2)))
2604 (set (match_dup 0)
2605 (compare:CC (match_dup 3)
2606 (const_int 0)))]
2607 "")
2608
2609 (define_insn ""
2610 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2611 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2612 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2613 (const_int 0)))
2614 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2615 (div:P (match_dup 1) (match_dup 2)))]
2616 ""
2617 "@
2618 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
2619 #"
2620 [(set_attr "type" "compare")
2621 (set_attr "length" "8,12")])
2622
2623 (define_split
2624 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2625 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2626 (match_operand:GPR 2 "exact_log2_cint_operand"
2627 ""))
2628 (const_int 0)))
2629 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2630 (div:GPR (match_dup 1) (match_dup 2)))]
2631 "reload_completed"
2632 [(set (match_dup 0)
2633 (div:<MODE> (match_dup 1) (match_dup 2)))
2634 (set (match_dup 3)
2635 (compare:CC (match_dup 0)
2636 (const_int 0)))]
2637 "")
2638
2639 (define_insn ""
2640 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2641 (udiv:SI
2642 (plus:DI (ashift:DI
2643 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2644 (const_int 32))
2645 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2646 (match_operand:SI 3 "gpc_reg_operand" "r")))
2647 (set (match_operand:SI 2 "register_operand" "=*q")
2648 (umod:SI
2649 (plus:DI (ashift:DI
2650 (zero_extend:DI (match_dup 1)) (const_int 32))
2651 (zero_extend:DI (match_dup 4)))
2652 (match_dup 3)))]
2653 "TARGET_POWER"
2654 "div %0,%1,%3"
2655 [(set_attr "type" "idiv")])
2656
2657 ;; To do unsigned divide we handle the cases of the divisor looking like a
2658 ;; negative number. If it is a constant that is less than 2**31, we don't
2659 ;; have to worry about the branches. So make a few subroutines here.
2660 ;;
2661 ;; First comes the normal case.
2662 (define_expand "udivmodsi4_normal"
2663 [(set (match_dup 4) (const_int 0))
2664 (parallel [(set (match_operand:SI 0 "" "")
2665 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2666 (const_int 32))
2667 (zero_extend:DI (match_operand:SI 1 "" "")))
2668 (match_operand:SI 2 "" "")))
2669 (set (match_operand:SI 3 "" "")
2670 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2671 (const_int 32))
2672 (zero_extend:DI (match_dup 1)))
2673 (match_dup 2)))])]
2674 "TARGET_POWER"
2675 "
2676 { operands[4] = gen_reg_rtx (SImode); }")
2677
2678 ;; This handles the branches.
2679 (define_expand "udivmodsi4_tests"
2680 [(set (match_operand:SI 0 "" "") (const_int 0))
2681 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2682 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2683 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2684 (label_ref (match_operand:SI 4 "" "")) (pc)))
2685 (set (match_dup 0) (const_int 1))
2686 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2687 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2688 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2689 (label_ref (match_dup 4)) (pc)))]
2690 "TARGET_POWER"
2691 "
2692 { operands[5] = gen_reg_rtx (CCUNSmode);
2693 operands[6] = gen_reg_rtx (CCmode);
2694 }")
2695
2696 (define_expand "udivmodsi4"
2697 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2698 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2699 (match_operand:SI 2 "reg_or_cint_operand" "")))
2700 (set (match_operand:SI 3 "gpc_reg_operand" "")
2701 (umod:SI (match_dup 1) (match_dup 2)))])]
2702 ""
2703 "
2704 {
2705 rtx label = 0;
2706
2707 if (! TARGET_POWER)
2708 {
2709 if (! TARGET_POWERPC)
2710 {
2711 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2712 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2713 emit_insn (gen_divus_call ());
2714 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2715 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2716 DONE;
2717 }
2718 else
2719 FAIL;
2720 }
2721
2722 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2723 {
2724 operands[2] = force_reg (SImode, operands[2]);
2725 label = gen_label_rtx ();
2726 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2727 operands[3], label));
2728 }
2729 else
2730 operands[2] = force_reg (SImode, operands[2]);
2731
2732 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2733 operands[3]));
2734 if (label)
2735 emit_label (label);
2736
2737 DONE;
2738 }")
2739
2740 ;; AIX architecture-independent common-mode multiply (DImode),
2741 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2742 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2743 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2744 ;; assumed unused if generating common-mode, so ignore.
2745 (define_insn "mulh_call"
2746 [(set (reg:SI 3)
2747 (truncate:SI
2748 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2749 (sign_extend:DI (reg:SI 4)))
2750 (const_int 32))))
2751 (clobber (reg:SI LR_REGNO))]
2752 "! TARGET_POWER && ! TARGET_POWERPC"
2753 "bla __mulh"
2754 [(set_attr "type" "imul")])
2755
2756 (define_insn "mull_call"
2757 [(set (reg:DI 3)
2758 (mult:DI (sign_extend:DI (reg:SI 3))
2759 (sign_extend:DI (reg:SI 4))))
2760 (clobber (reg:SI LR_REGNO))
2761 (clobber (reg:SI 0))]
2762 "! TARGET_POWER && ! TARGET_POWERPC"
2763 "bla __mull"
2764 [(set_attr "type" "imul")])
2765
2766 (define_insn "divss_call"
2767 [(set (reg:SI 3)
2768 (div:SI (reg:SI 3) (reg:SI 4)))
2769 (set (reg:SI 4)
2770 (mod:SI (reg:SI 3) (reg:SI 4)))
2771 (clobber (reg:SI LR_REGNO))
2772 (clobber (reg:SI 0))]
2773 "! TARGET_POWER && ! TARGET_POWERPC"
2774 "bla __divss"
2775 [(set_attr "type" "idiv")])
2776
2777 (define_insn "divus_call"
2778 [(set (reg:SI 3)
2779 (udiv:SI (reg:SI 3) (reg:SI 4)))
2780 (set (reg:SI 4)
2781 (umod:SI (reg:SI 3) (reg:SI 4)))
2782 (clobber (reg:SI LR_REGNO))
2783 (clobber (reg:SI 0))
2784 (clobber (match_scratch:CC 0 "=x"))
2785 (clobber (reg:CC CR1_REGNO))]
2786 "! TARGET_POWER && ! TARGET_POWERPC"
2787 "bla __divus"
2788 [(set_attr "type" "idiv")])
2789
2790 (define_insn "quoss_call"
2791 [(set (reg:SI 3)
2792 (div:SI (reg:SI 3) (reg:SI 4)))
2793 (clobber (reg:SI LR_REGNO))]
2794 "! TARGET_POWER && ! TARGET_POWERPC"
2795 "bla __quoss"
2796 [(set_attr "type" "idiv")])
2797
2798 (define_insn "quous_call"
2799 [(set (reg:SI 3)
2800 (udiv:SI (reg:SI 3) (reg:SI 4)))
2801 (clobber (reg:SI LR_REGNO))
2802 (clobber (reg:SI 0))
2803 (clobber (match_scratch:CC 0 "=x"))
2804 (clobber (reg:CC CR1_REGNO))]
2805 "! TARGET_POWER && ! TARGET_POWERPC"
2806 "bla __quous"
2807 [(set_attr "type" "idiv")])
2808 \f
2809 ;; Logical instructions
2810 ;; The logical instructions are mostly combined by using match_operator,
2811 ;; but the plain AND insns are somewhat different because there is no
2812 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2813 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2814
2815 (define_insn "andsi3"
2816 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2817 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2818 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2819 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2820 ""
2821 "@
2822 and %0,%1,%2
2823 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2824 {andil.|andi.} %0,%1,%b2
2825 {andiu.|andis.} %0,%1,%u2"
2826 [(set_attr "type" "*,*,compare,compare")])
2827
2828 ;; Note to set cr's other than cr0 we do the and immediate and then
2829 ;; the test again -- this avoids a mfcr which on the higher end
2830 ;; machines causes an execution serialization
2831
2832 (define_insn "*andsi3_internal2"
2833 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2834 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2835 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2836 (const_int 0)))
2837 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2838 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2839 "TARGET_32BIT"
2840 "@
2841 and. %3,%1,%2
2842 {andil.|andi.} %3,%1,%b2
2843 {andiu.|andis.} %3,%1,%u2
2844 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2845 #
2846 #
2847 #
2848 #"
2849 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2850 (set_attr "length" "4,4,4,4,8,8,8,8")])
2851
2852 (define_insn "*andsi3_internal3"
2853 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2854 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2855 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2856 (const_int 0)))
2857 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2858 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2859 "TARGET_64BIT"
2860 "@
2861 #
2862 {andil.|andi.} %3,%1,%b2
2863 {andiu.|andis.} %3,%1,%u2
2864 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2865 #
2866 #
2867 #
2868 #"
2869 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2870 (set_attr "length" "8,4,4,4,8,8,8,8")])
2871
2872 (define_split
2873 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2874 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2875 (match_operand:GPR 2 "and_operand" ""))
2876 (const_int 0)))
2877 (clobber (match_scratch:GPR 3 ""))
2878 (clobber (match_scratch:CC 4 ""))]
2879 "reload_completed"
2880 [(parallel [(set (match_dup 3)
2881 (and:<MODE> (match_dup 1)
2882 (match_dup 2)))
2883 (clobber (match_dup 4))])
2884 (set (match_dup 0)
2885 (compare:CC (match_dup 3)
2886 (const_int 0)))]
2887 "")
2888
2889 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2890 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2891
2892 (define_split
2893 [(set (match_operand:CC 0 "cc_reg_operand" "")
2894 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2895 (match_operand:SI 2 "gpc_reg_operand" ""))
2896 (const_int 0)))
2897 (clobber (match_scratch:SI 3 ""))
2898 (clobber (match_scratch:CC 4 ""))]
2899 "TARGET_POWERPC64 && reload_completed"
2900 [(parallel [(set (match_dup 3)
2901 (and:SI (match_dup 1)
2902 (match_dup 2)))
2903 (clobber (match_dup 4))])
2904 (set (match_dup 0)
2905 (compare:CC (match_dup 3)
2906 (const_int 0)))]
2907 "")
2908
2909 (define_insn "*andsi3_internal4"
2910 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2911 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2912 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2913 (const_int 0)))
2914 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2915 (and:SI (match_dup 1)
2916 (match_dup 2)))
2917 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2918 "TARGET_32BIT"
2919 "@
2920 and. %0,%1,%2
2921 {andil.|andi.} %0,%1,%b2
2922 {andiu.|andis.} %0,%1,%u2
2923 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2924 #
2925 #
2926 #
2927 #"
2928 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2929 (set_attr "length" "4,4,4,4,8,8,8,8")])
2930
2931 (define_insn "*andsi3_internal5"
2932 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2933 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2934 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2935 (const_int 0)))
2936 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2937 (and:SI (match_dup 1)
2938 (match_dup 2)))
2939 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2940 "TARGET_64BIT"
2941 "@
2942 #
2943 {andil.|andi.} %0,%1,%b2
2944 {andiu.|andis.} %0,%1,%u2
2945 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2946 #
2947 #
2948 #
2949 #"
2950 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2951 (set_attr "length" "8,4,4,4,8,8,8,8")])
2952
2953 (define_split
2954 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2955 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2956 (match_operand:SI 2 "and_operand" ""))
2957 (const_int 0)))
2958 (set (match_operand:SI 0 "gpc_reg_operand" "")
2959 (and:SI (match_dup 1)
2960 (match_dup 2)))
2961 (clobber (match_scratch:CC 4 ""))]
2962 "reload_completed"
2963 [(parallel [(set (match_dup 0)
2964 (and:SI (match_dup 1)
2965 (match_dup 2)))
2966 (clobber (match_dup 4))])
2967 (set (match_dup 3)
2968 (compare:CC (match_dup 0)
2969 (const_int 0)))]
2970 "")
2971
2972 (define_split
2973 [(set (match_operand:CC 3 "cc_reg_operand" "")
2974 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2975 (match_operand:SI 2 "gpc_reg_operand" ""))
2976 (const_int 0)))
2977 (set (match_operand:SI 0 "gpc_reg_operand" "")
2978 (and:SI (match_dup 1)
2979 (match_dup 2)))
2980 (clobber (match_scratch:CC 4 ""))]
2981 "TARGET_POWERPC64 && reload_completed"
2982 [(parallel [(set (match_dup 0)
2983 (and:SI (match_dup 1)
2984 (match_dup 2)))
2985 (clobber (match_dup 4))])
2986 (set (match_dup 3)
2987 (compare:CC (match_dup 0)
2988 (const_int 0)))]
2989 "")
2990
2991 ;; Handle the PowerPC64 rlwinm corner case
2992
2993 (define_insn_and_split "*andsi3_internal6"
2994 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2995 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2996 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2997 "TARGET_POWERPC64"
2998 "#"
2999 "TARGET_POWERPC64"
3000 [(set (match_dup 0)
3001 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3002 (match_dup 4)))
3003 (set (match_dup 0)
3004 (rotate:SI (match_dup 0) (match_dup 5)))]
3005 "
3006 {
3007 int mb = extract_MB (operands[2]);
3008 int me = extract_ME (operands[2]);
3009 operands[3] = GEN_INT (me + 1);
3010 operands[5] = GEN_INT (32 - (me + 1));
3011 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3012 }"
3013 [(set_attr "length" "8")])
3014
3015 (define_expand "iorsi3"
3016 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3017 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
3018 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3019 ""
3020 "
3021 {
3022 if (GET_CODE (operands[2]) == CONST_INT
3023 && ! logical_operand (operands[2], SImode))
3024 {
3025 HOST_WIDE_INT value = INTVAL (operands[2]);
3026 rtx tmp = ((!can_create_pseudo_p ()
3027 || rtx_equal_p (operands[0], operands[1]))
3028 ? operands[0] : gen_reg_rtx (SImode));
3029
3030 emit_insn (gen_iorsi3 (tmp, operands[1],
3031 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3032 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3033 DONE;
3034 }
3035 }")
3036
3037 (define_expand "xorsi3"
3038 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3039 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3040 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3041 ""
3042 "
3043 {
3044 if (GET_CODE (operands[2]) == CONST_INT
3045 && ! logical_operand (operands[2], SImode))
3046 {
3047 HOST_WIDE_INT value = INTVAL (operands[2]);
3048 rtx tmp = ((!can_create_pseudo_p ()
3049 || rtx_equal_p (operands[0], operands[1]))
3050 ? operands[0] : gen_reg_rtx (SImode));
3051
3052 emit_insn (gen_xorsi3 (tmp, operands[1],
3053 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3054 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3055 DONE;
3056 }
3057 }")
3058
3059 (define_insn "*boolsi3_internal1"
3060 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3061 (match_operator:SI 3 "boolean_or_operator"
3062 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3063 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3064 ""
3065 "@
3066 %q3 %0,%1,%2
3067 {%q3il|%q3i} %0,%1,%b2
3068 {%q3iu|%q3is} %0,%1,%u2")
3069
3070 (define_insn "*boolsi3_internal2"
3071 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3072 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3073 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3074 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3075 (const_int 0)))
3076 (clobber (match_scratch:SI 3 "=r,r"))]
3077 "TARGET_32BIT"
3078 "@
3079 %q4. %3,%1,%2
3080 #"
3081 [(set_attr "type" "compare")
3082 (set_attr "length" "4,8")])
3083
3084 (define_split
3085 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3086 (compare:CC (match_operator:SI 4 "boolean_operator"
3087 [(match_operand:SI 1 "gpc_reg_operand" "")
3088 (match_operand:SI 2 "gpc_reg_operand" "")])
3089 (const_int 0)))
3090 (clobber (match_scratch:SI 3 ""))]
3091 "TARGET_32BIT && reload_completed"
3092 [(set (match_dup 3) (match_dup 4))
3093 (set (match_dup 0)
3094 (compare:CC (match_dup 3)
3095 (const_int 0)))]
3096 "")
3097
3098 (define_insn "*boolsi3_internal3"
3099 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3100 (compare:CC (match_operator:SI 4 "boolean_operator"
3101 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3102 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3103 (const_int 0)))
3104 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3105 (match_dup 4))]
3106 "TARGET_32BIT"
3107 "@
3108 %q4. %0,%1,%2
3109 #"
3110 [(set_attr "type" "compare")
3111 (set_attr "length" "4,8")])
3112
3113 (define_split
3114 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3115 (compare:CC (match_operator:SI 4 "boolean_operator"
3116 [(match_operand:SI 1 "gpc_reg_operand" "")
3117 (match_operand:SI 2 "gpc_reg_operand" "")])
3118 (const_int 0)))
3119 (set (match_operand:SI 0 "gpc_reg_operand" "")
3120 (match_dup 4))]
3121 "TARGET_32BIT && reload_completed"
3122 [(set (match_dup 0) (match_dup 4))
3123 (set (match_dup 3)
3124 (compare:CC (match_dup 0)
3125 (const_int 0)))]
3126 "")
3127
3128 ;; Split a logical operation that we can't do in one insn into two insns,
3129 ;; each of which does one 16-bit part. This is used by combine.
3130
3131 (define_split
3132 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3133 (match_operator:SI 3 "boolean_or_operator"
3134 [(match_operand:SI 1 "gpc_reg_operand" "")
3135 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3136 ""
3137 [(set (match_dup 0) (match_dup 4))
3138 (set (match_dup 0) (match_dup 5))]
3139 "
3140 {
3141 rtx i;
3142 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3143 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3144 operands[1], i);
3145 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3146 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3147 operands[0], i);
3148 }")
3149
3150 (define_insn "*boolcsi3_internal1"
3151 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3152 (match_operator:SI 3 "boolean_operator"
3153 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3154 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3155 ""
3156 "%q3 %0,%2,%1")
3157
3158 (define_insn "*boolcsi3_internal2"
3159 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3160 (compare:CC (match_operator:SI 4 "boolean_operator"
3161 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3162 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3163 (const_int 0)))
3164 (clobber (match_scratch:SI 3 "=r,r"))]
3165 "TARGET_32BIT"
3166 "@
3167 %q4. %3,%2,%1
3168 #"
3169 [(set_attr "type" "compare")
3170 (set_attr "length" "4,8")])
3171
3172 (define_split
3173 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3174 (compare:CC (match_operator:SI 4 "boolean_operator"
3175 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3176 (match_operand:SI 2 "gpc_reg_operand" "")])
3177 (const_int 0)))
3178 (clobber (match_scratch:SI 3 ""))]
3179 "TARGET_32BIT && reload_completed"
3180 [(set (match_dup 3) (match_dup 4))
3181 (set (match_dup 0)
3182 (compare:CC (match_dup 3)
3183 (const_int 0)))]
3184 "")
3185
3186 (define_insn "*boolcsi3_internal3"
3187 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3188 (compare:CC (match_operator:SI 4 "boolean_operator"
3189 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3190 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3191 (const_int 0)))
3192 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3193 (match_dup 4))]
3194 "TARGET_32BIT"
3195 "@
3196 %q4. %0,%2,%1
3197 #"
3198 [(set_attr "type" "compare")
3199 (set_attr "length" "4,8")])
3200
3201 (define_split
3202 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3203 (compare:CC (match_operator:SI 4 "boolean_operator"
3204 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3205 (match_operand:SI 2 "gpc_reg_operand" "")])
3206 (const_int 0)))
3207 (set (match_operand:SI 0 "gpc_reg_operand" "")
3208 (match_dup 4))]
3209 "TARGET_32BIT && reload_completed"
3210 [(set (match_dup 0) (match_dup 4))
3211 (set (match_dup 3)
3212 (compare:CC (match_dup 0)
3213 (const_int 0)))]
3214 "")
3215
3216 (define_insn "*boolccsi3_internal1"
3217 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3218 (match_operator:SI 3 "boolean_operator"
3219 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3220 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3221 ""
3222 "%q3 %0,%1,%2")
3223
3224 (define_insn "*boolccsi3_internal2"
3225 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3226 (compare:CC (match_operator:SI 4 "boolean_operator"
3227 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3228 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3229 (const_int 0)))
3230 (clobber (match_scratch:SI 3 "=r,r"))]
3231 "TARGET_32BIT"
3232 "@
3233 %q4. %3,%1,%2
3234 #"
3235 [(set_attr "type" "compare")
3236 (set_attr "length" "4,8")])
3237
3238 (define_split
3239 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3240 (compare:CC (match_operator:SI 4 "boolean_operator"
3241 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3242 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3243 (const_int 0)))
3244 (clobber (match_scratch:SI 3 ""))]
3245 "TARGET_32BIT && reload_completed"
3246 [(set (match_dup 3) (match_dup 4))
3247 (set (match_dup 0)
3248 (compare:CC (match_dup 3)
3249 (const_int 0)))]
3250 "")
3251
3252 (define_insn "*boolccsi3_internal3"
3253 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3254 (compare:CC (match_operator:SI 4 "boolean_operator"
3255 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3256 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3257 (const_int 0)))
3258 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3259 (match_dup 4))]
3260 "TARGET_32BIT"
3261 "@
3262 %q4. %0,%1,%2
3263 #"
3264 [(set_attr "type" "compare")
3265 (set_attr "length" "4,8")])
3266
3267 (define_split
3268 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3269 (compare:CC (match_operator:SI 4 "boolean_operator"
3270 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3271 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3272 (const_int 0)))
3273 (set (match_operand:SI 0 "gpc_reg_operand" "")
3274 (match_dup 4))]
3275 "TARGET_32BIT && reload_completed"
3276 [(set (match_dup 0) (match_dup 4))
3277 (set (match_dup 3)
3278 (compare:CC (match_dup 0)
3279 (const_int 0)))]
3280 "")
3281
3282 ;; maskir insn. We need four forms because things might be in arbitrary
3283 ;; orders. Don't define forms that only set CR fields because these
3284 ;; would modify an input register.
3285
3286 (define_insn "*maskir_internal1"
3287 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3288 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3289 (match_operand:SI 1 "gpc_reg_operand" "0"))
3290 (and:SI (match_dup 2)
3291 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3292 "TARGET_POWER"
3293 "maskir %0,%3,%2")
3294
3295 (define_insn "*maskir_internal2"
3296 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3297 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3298 (match_operand:SI 1 "gpc_reg_operand" "0"))
3299 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3300 (match_dup 2))))]
3301 "TARGET_POWER"
3302 "maskir %0,%3,%2")
3303
3304 (define_insn "*maskir_internal3"
3305 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3306 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3307 (match_operand:SI 3 "gpc_reg_operand" "r"))
3308 (and:SI (not:SI (match_dup 2))
3309 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3310 "TARGET_POWER"
3311 "maskir %0,%3,%2")
3312
3313 (define_insn "*maskir_internal4"
3314 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3315 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3316 (match_operand:SI 2 "gpc_reg_operand" "r"))
3317 (and:SI (not:SI (match_dup 2))
3318 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3319 "TARGET_POWER"
3320 "maskir %0,%3,%2")
3321
3322 (define_insn "*maskir_internal5"
3323 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3324 (compare:CC
3325 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3326 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3327 (and:SI (match_dup 2)
3328 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3329 (const_int 0)))
3330 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3331 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3332 (and:SI (match_dup 2) (match_dup 3))))]
3333 "TARGET_POWER"
3334 "@
3335 maskir. %0,%3,%2
3336 #"
3337 [(set_attr "type" "compare")
3338 (set_attr "length" "4,8")])
3339
3340 (define_split
3341 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3342 (compare:CC
3343 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3344 (match_operand:SI 1 "gpc_reg_operand" ""))
3345 (and:SI (match_dup 2)
3346 (match_operand:SI 3 "gpc_reg_operand" "")))
3347 (const_int 0)))
3348 (set (match_operand:SI 0 "gpc_reg_operand" "")
3349 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3350 (and:SI (match_dup 2) (match_dup 3))))]
3351 "TARGET_POWER && reload_completed"
3352 [(set (match_dup 0)
3353 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3354 (and:SI (match_dup 2) (match_dup 3))))
3355 (set (match_dup 4)
3356 (compare:CC (match_dup 0)
3357 (const_int 0)))]
3358 "")
3359
3360 (define_insn "*maskir_internal6"
3361 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3362 (compare:CC
3363 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3364 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3365 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3366 (match_dup 2)))
3367 (const_int 0)))
3368 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3369 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3370 (and:SI (match_dup 3) (match_dup 2))))]
3371 "TARGET_POWER"
3372 "@
3373 maskir. %0,%3,%2
3374 #"
3375 [(set_attr "type" "compare")
3376 (set_attr "length" "4,8")])
3377
3378 (define_split
3379 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3380 (compare:CC
3381 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3382 (match_operand:SI 1 "gpc_reg_operand" ""))
3383 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3384 (match_dup 2)))
3385 (const_int 0)))
3386 (set (match_operand:SI 0 "gpc_reg_operand" "")
3387 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3388 (and:SI (match_dup 3) (match_dup 2))))]
3389 "TARGET_POWER && reload_completed"
3390 [(set (match_dup 0)
3391 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3392 (and:SI (match_dup 3) (match_dup 2))))
3393 (set (match_dup 4)
3394 (compare:CC (match_dup 0)
3395 (const_int 0)))]
3396 "")
3397
3398 (define_insn "*maskir_internal7"
3399 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3400 (compare:CC
3401 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3402 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3403 (and:SI (not:SI (match_dup 2))
3404 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3405 (const_int 0)))
3406 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3407 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3408 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3409 "TARGET_POWER"
3410 "@
3411 maskir. %0,%3,%2
3412 #"
3413 [(set_attr "type" "compare")
3414 (set_attr "length" "4,8")])
3415
3416 (define_split
3417 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3418 (compare:CC
3419 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3420 (match_operand:SI 3 "gpc_reg_operand" ""))
3421 (and:SI (not:SI (match_dup 2))
3422 (match_operand:SI 1 "gpc_reg_operand" "")))
3423 (const_int 0)))
3424 (set (match_operand:SI 0 "gpc_reg_operand" "")
3425 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3426 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3427 "TARGET_POWER && reload_completed"
3428 [(set (match_dup 0)
3429 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3430 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3431 (set (match_dup 4)
3432 (compare:CC (match_dup 0)
3433 (const_int 0)))]
3434 "")
3435
3436 (define_insn "*maskir_internal8"
3437 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3438 (compare:CC
3439 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3440 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3441 (and:SI (not:SI (match_dup 2))
3442 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3443 (const_int 0)))
3444 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3445 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3446 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3447 "TARGET_POWER"
3448 "@
3449 maskir. %0,%3,%2
3450 #"
3451 [(set_attr "type" "compare")
3452 (set_attr "length" "4,8")])
3453
3454 (define_split
3455 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3456 (compare:CC
3457 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3458 (match_operand:SI 2 "gpc_reg_operand" ""))
3459 (and:SI (not:SI (match_dup 2))
3460 (match_operand:SI 1 "gpc_reg_operand" "")))
3461 (const_int 0)))
3462 (set (match_operand:SI 0 "gpc_reg_operand" "")
3463 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3464 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3465 "TARGET_POWER && reload_completed"
3466 [(set (match_dup 0)
3467 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3468 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3469 (set (match_dup 4)
3470 (compare:CC (match_dup 0)
3471 (const_int 0)))]
3472 "")
3473 \f
3474 ;; Rotate and shift insns, in all their variants. These support shifts,
3475 ;; field inserts and extracts, and various combinations thereof.
3476 (define_expand "insv"
3477 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3478 (match_operand:SI 1 "const_int_operand" "")
3479 (match_operand:SI 2 "const_int_operand" ""))
3480 (match_operand 3 "gpc_reg_operand" ""))]
3481 ""
3482 "
3483 {
3484 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3485 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3486 compiler if the address of the structure is taken later. Likewise, do
3487 not handle invalid E500 subregs. */
3488 if (GET_CODE (operands[0]) == SUBREG
3489 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3490 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3491 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3492 FAIL;
3493
3494 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3495 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3496 else
3497 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3498 DONE;
3499 }")
3500
3501 (define_insn "insvsi"
3502 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3503 (match_operand:SI 1 "const_int_operand" "i")
3504 (match_operand:SI 2 "const_int_operand" "i"))
3505 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3506 ""
3507 "*
3508 {
3509 int start = INTVAL (operands[2]) & 31;
3510 int size = INTVAL (operands[1]) & 31;
3511
3512 operands[4] = GEN_INT (32 - start - size);
3513 operands[1] = GEN_INT (start + size - 1);
3514 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3515 }"
3516 [(set_attr "type" "insert_word")])
3517
3518 (define_insn "*insvsi_internal1"
3519 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3520 (match_operand:SI 1 "const_int_operand" "i")
3521 (match_operand:SI 2 "const_int_operand" "i"))
3522 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3523 (match_operand:SI 4 "const_int_operand" "i")))]
3524 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3525 "*
3526 {
3527 int shift = INTVAL (operands[4]) & 31;
3528 int start = INTVAL (operands[2]) & 31;
3529 int size = INTVAL (operands[1]) & 31;
3530
3531 operands[4] = GEN_INT (shift - start - size);
3532 operands[1] = GEN_INT (start + size - 1);
3533 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3534 }"
3535 [(set_attr "type" "insert_word")])
3536
3537 (define_insn "*insvsi_internal2"
3538 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3539 (match_operand:SI 1 "const_int_operand" "i")
3540 (match_operand:SI 2 "const_int_operand" "i"))
3541 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3542 (match_operand:SI 4 "const_int_operand" "i")))]
3543 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3544 "*
3545 {
3546 int shift = INTVAL (operands[4]) & 31;
3547 int start = INTVAL (operands[2]) & 31;
3548 int size = INTVAL (operands[1]) & 31;
3549
3550 operands[4] = GEN_INT (32 - shift - start - size);
3551 operands[1] = GEN_INT (start + size - 1);
3552 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3553 }"
3554 [(set_attr "type" "insert_word")])
3555
3556 (define_insn "*insvsi_internal3"
3557 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3558 (match_operand:SI 1 "const_int_operand" "i")
3559 (match_operand:SI 2 "const_int_operand" "i"))
3560 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3561 (match_operand:SI 4 "const_int_operand" "i")))]
3562 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3563 "*
3564 {
3565 int shift = INTVAL (operands[4]) & 31;
3566 int start = INTVAL (operands[2]) & 31;
3567 int size = INTVAL (operands[1]) & 31;
3568
3569 operands[4] = GEN_INT (32 - shift - start - size);
3570 operands[1] = GEN_INT (start + size - 1);
3571 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3572 }"
3573 [(set_attr "type" "insert_word")])
3574
3575 (define_insn "*insvsi_internal4"
3576 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3577 (match_operand:SI 1 "const_int_operand" "i")
3578 (match_operand:SI 2 "const_int_operand" "i"))
3579 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3580 (match_operand:SI 4 "const_int_operand" "i")
3581 (match_operand:SI 5 "const_int_operand" "i")))]
3582 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3583 "*
3584 {
3585 int extract_start = INTVAL (operands[5]) & 31;
3586 int extract_size = INTVAL (operands[4]) & 31;
3587 int insert_start = INTVAL (operands[2]) & 31;
3588 int insert_size = INTVAL (operands[1]) & 31;
3589
3590 /* Align extract field with insert field */
3591 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3592 operands[1] = GEN_INT (insert_start + insert_size - 1);
3593 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3594 }"
3595 [(set_attr "type" "insert_word")])
3596
3597 ;; combine patterns for rlwimi
3598 (define_insn "*insvsi_internal5"
3599 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3600 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3601 (match_operand:SI 1 "mask_operand" "i"))
3602 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3603 (match_operand:SI 2 "const_int_operand" "i"))
3604 (match_operand:SI 5 "mask_operand" "i"))))]
3605 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3606 "*
3607 {
3608 int me = extract_ME(operands[5]);
3609 int mb = extract_MB(operands[5]);
3610 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3611 operands[2] = GEN_INT(mb);
3612 operands[1] = GEN_INT(me);
3613 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3614 }"
3615 [(set_attr "type" "insert_word")])
3616
3617 (define_insn "*insvsi_internal6"
3618 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3619 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3620 (match_operand:SI 2 "const_int_operand" "i"))
3621 (match_operand:SI 5 "mask_operand" "i"))
3622 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3623 (match_operand:SI 1 "mask_operand" "i"))))]
3624 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3625 "*
3626 {
3627 int me = extract_ME(operands[5]);
3628 int mb = extract_MB(operands[5]);
3629 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3630 operands[2] = GEN_INT(mb);
3631 operands[1] = GEN_INT(me);
3632 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3633 }"
3634 [(set_attr "type" "insert_word")])
3635
3636 (define_insn "insvdi"
3637 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3638 (match_operand:SI 1 "const_int_operand" "i")
3639 (match_operand:SI 2 "const_int_operand" "i"))
3640 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3641 "TARGET_POWERPC64"
3642 "*
3643 {
3644 int start = INTVAL (operands[2]) & 63;
3645 int size = INTVAL (operands[1]) & 63;
3646
3647 operands[1] = GEN_INT (64 - start - size);
3648 return \"rldimi %0,%3,%H1,%H2\";
3649 }"
3650 [(set_attr "type" "insert_dword")])
3651
3652 (define_insn "*insvdi_internal2"
3653 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3654 (match_operand:SI 1 "const_int_operand" "i")
3655 (match_operand:SI 2 "const_int_operand" "i"))
3656 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3657 (match_operand:SI 4 "const_int_operand" "i")))]
3658 "TARGET_POWERPC64
3659 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3660 "*
3661 {
3662 int shift = INTVAL (operands[4]) & 63;
3663 int start = (INTVAL (operands[2]) & 63) - 32;
3664 int size = INTVAL (operands[1]) & 63;
3665
3666 operands[4] = GEN_INT (64 - shift - start - size);
3667 operands[2] = GEN_INT (start);
3668 operands[1] = GEN_INT (start + size - 1);
3669 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3670 }")
3671
3672 (define_insn "*insvdi_internal3"
3673 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3674 (match_operand:SI 1 "const_int_operand" "i")
3675 (match_operand:SI 2 "const_int_operand" "i"))
3676 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3677 (match_operand:SI 4 "const_int_operand" "i")))]
3678 "TARGET_POWERPC64
3679 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3680 "*
3681 {
3682 int shift = INTVAL (operands[4]) & 63;
3683 int start = (INTVAL (operands[2]) & 63) - 32;
3684 int size = INTVAL (operands[1]) & 63;
3685
3686 operands[4] = GEN_INT (64 - shift - start - size);
3687 operands[2] = GEN_INT (start);
3688 operands[1] = GEN_INT (start + size - 1);
3689 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3690 }")
3691
3692 (define_expand "extzv"
3693 [(set (match_operand 0 "gpc_reg_operand" "")
3694 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3695 (match_operand:SI 2 "const_int_operand" "")
3696 (match_operand:SI 3 "const_int_operand" "")))]
3697 ""
3698 "
3699 {
3700 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3701 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3702 compiler if the address of the structure is taken later. */
3703 if (GET_CODE (operands[0]) == SUBREG
3704 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3705 FAIL;
3706
3707 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3708 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3709 else
3710 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3711 DONE;
3712 }")
3713
3714 (define_insn "extzvsi"
3715 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3716 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3717 (match_operand:SI 2 "const_int_operand" "i")
3718 (match_operand:SI 3 "const_int_operand" "i")))]
3719 ""
3720 "*
3721 {
3722 int start = INTVAL (operands[3]) & 31;
3723 int size = INTVAL (operands[2]) & 31;
3724
3725 if (start + size >= 32)
3726 operands[3] = const0_rtx;
3727 else
3728 operands[3] = GEN_INT (start + size);
3729 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3730 }")
3731
3732 (define_insn "*extzvsi_internal1"
3733 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3734 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3735 (match_operand:SI 2 "const_int_operand" "i,i")
3736 (match_operand:SI 3 "const_int_operand" "i,i"))
3737 (const_int 0)))
3738 (clobber (match_scratch:SI 4 "=r,r"))]
3739 ""
3740 "*
3741 {
3742 int start = INTVAL (operands[3]) & 31;
3743 int size = INTVAL (operands[2]) & 31;
3744
3745 /* Force split for non-cc0 compare. */
3746 if (which_alternative == 1)
3747 return \"#\";
3748
3749 /* If the bit-field being tested fits in the upper or lower half of a
3750 word, it is possible to use andiu. or andil. to test it. This is
3751 useful because the condition register set-use delay is smaller for
3752 andi[ul]. than for rlinm. This doesn't work when the starting bit
3753 position is 0 because the LT and GT bits may be set wrong. */
3754
3755 if ((start > 0 && start + size <= 16) || start >= 16)
3756 {
3757 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3758 - (1 << (16 - (start & 15) - size))));
3759 if (start < 16)
3760 return \"{andiu.|andis.} %4,%1,%3\";
3761 else
3762 return \"{andil.|andi.} %4,%1,%3\";
3763 }
3764
3765 if (start + size >= 32)
3766 operands[3] = const0_rtx;
3767 else
3768 operands[3] = GEN_INT (start + size);
3769 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3770 }"
3771 [(set_attr "type" "delayed_compare")
3772 (set_attr "length" "4,8")])
3773
3774 (define_split
3775 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3776 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3777 (match_operand:SI 2 "const_int_operand" "")
3778 (match_operand:SI 3 "const_int_operand" ""))
3779 (const_int 0)))
3780 (clobber (match_scratch:SI 4 ""))]
3781 "reload_completed"
3782 [(set (match_dup 4)
3783 (zero_extract:SI (match_dup 1) (match_dup 2)
3784 (match_dup 3)))
3785 (set (match_dup 0)
3786 (compare:CC (match_dup 4)
3787 (const_int 0)))]
3788 "")
3789
3790 (define_insn "*extzvsi_internal2"
3791 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3792 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3793 (match_operand:SI 2 "const_int_operand" "i,i")
3794 (match_operand:SI 3 "const_int_operand" "i,i"))
3795 (const_int 0)))
3796 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3797 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3798 ""
3799 "*
3800 {
3801 int start = INTVAL (operands[3]) & 31;
3802 int size = INTVAL (operands[2]) & 31;
3803
3804 /* Force split for non-cc0 compare. */
3805 if (which_alternative == 1)
3806 return \"#\";
3807
3808 /* Since we are using the output value, we can't ignore any need for
3809 a shift. The bit-field must end at the LSB. */
3810 if (start >= 16 && start + size == 32)
3811 {
3812 operands[3] = GEN_INT ((1 << size) - 1);
3813 return \"{andil.|andi.} %0,%1,%3\";
3814 }
3815
3816 if (start + size >= 32)
3817 operands[3] = const0_rtx;
3818 else
3819 operands[3] = GEN_INT (start + size);
3820 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3821 }"
3822 [(set_attr "type" "delayed_compare")
3823 (set_attr "length" "4,8")])
3824
3825 (define_split
3826 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3827 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3828 (match_operand:SI 2 "const_int_operand" "")
3829 (match_operand:SI 3 "const_int_operand" ""))
3830 (const_int 0)))
3831 (set (match_operand:SI 0 "gpc_reg_operand" "")
3832 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3833 "reload_completed"
3834 [(set (match_dup 0)
3835 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3836 (set (match_dup 4)
3837 (compare:CC (match_dup 0)
3838 (const_int 0)))]
3839 "")
3840
3841 (define_insn "extzvdi"
3842 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3843 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3844 (match_operand:SI 2 "const_int_operand" "i")
3845 (match_operand:SI 3 "const_int_operand" "i")))]
3846 "TARGET_POWERPC64"
3847 "*
3848 {
3849 int start = INTVAL (operands[3]) & 63;
3850 int size = INTVAL (operands[2]) & 63;
3851
3852 if (start + size >= 64)
3853 operands[3] = const0_rtx;
3854 else
3855 operands[3] = GEN_INT (start + size);
3856 operands[2] = GEN_INT (64 - size);
3857 return \"rldicl %0,%1,%3,%2\";
3858 }")
3859
3860 (define_insn "*extzvdi_internal1"
3861 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3862 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3863 (match_operand:SI 2 "const_int_operand" "i")
3864 (match_operand:SI 3 "const_int_operand" "i"))
3865 (const_int 0)))
3866 (clobber (match_scratch:DI 4 "=r"))]
3867 "TARGET_64BIT"
3868 "*
3869 {
3870 int start = INTVAL (operands[3]) & 63;
3871 int size = INTVAL (operands[2]) & 63;
3872
3873 if (start + size >= 64)
3874 operands[3] = const0_rtx;
3875 else
3876 operands[3] = GEN_INT (start + size);
3877 operands[2] = GEN_INT (64 - size);
3878 return \"rldicl. %4,%1,%3,%2\";
3879 }"
3880 [(set_attr "type" "compare")])
3881
3882 (define_insn "*extzvdi_internal2"
3883 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3884 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3885 (match_operand:SI 2 "const_int_operand" "i")
3886 (match_operand:SI 3 "const_int_operand" "i"))
3887 (const_int 0)))
3888 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3889 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3890 "TARGET_64BIT"
3891 "*
3892 {
3893 int start = INTVAL (operands[3]) & 63;
3894 int size = INTVAL (operands[2]) & 63;
3895
3896 if (start + size >= 64)
3897 operands[3] = const0_rtx;
3898 else
3899 operands[3] = GEN_INT (start + size);
3900 operands[2] = GEN_INT (64 - size);
3901 return \"rldicl. %0,%1,%3,%2\";
3902 }"
3903 [(set_attr "type" "compare")])
3904
3905 (define_insn "rotlsi3"
3906 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3907 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3908 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
3909 ""
3910 "@
3911 {rlnm|rlwnm} %0,%1,%2,0xffffffff
3912 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
3913 [(set_attr "type" "var_shift_rotate,integer")])
3914
3915 (define_insn "*rotlsi3_internal2"
3916 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3917 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3918 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3919 (const_int 0)))
3920 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3921 ""
3922 "@
3923 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
3924 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
3925 #
3926 #"
3927 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3928 (set_attr "length" "4,4,8,8")])
3929
3930 (define_split
3931 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3932 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3933 (match_operand:SI 2 "reg_or_cint_operand" ""))
3934 (const_int 0)))
3935 (clobber (match_scratch:SI 3 ""))]
3936 "reload_completed"
3937 [(set (match_dup 3)
3938 (rotate:SI (match_dup 1) (match_dup 2)))
3939 (set (match_dup 0)
3940 (compare:CC (match_dup 3)
3941 (const_int 0)))]
3942 "")
3943
3944 (define_insn "*rotlsi3_internal3"
3945 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3946 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3947 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3948 (const_int 0)))
3949 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3950 (rotate:SI (match_dup 1) (match_dup 2)))]
3951 ""
3952 "@
3953 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
3954 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
3955 #
3956 #"
3957 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3958 (set_attr "length" "4,4,8,8")])
3959
3960 (define_split
3961 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3962 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3963 (match_operand:SI 2 "reg_or_cint_operand" ""))
3964 (const_int 0)))
3965 (set (match_operand:SI 0 "gpc_reg_operand" "")
3966 (rotate:SI (match_dup 1) (match_dup 2)))]
3967 "reload_completed"
3968 [(set (match_dup 0)
3969 (rotate:SI (match_dup 1) (match_dup 2)))
3970 (set (match_dup 3)
3971 (compare:CC (match_dup 0)
3972 (const_int 0)))]
3973 "")
3974
3975 (define_insn "*rotlsi3_internal4"
3976 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3977 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3978 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
3979 (match_operand:SI 3 "mask_operand" "n,n")))]
3980 ""
3981 "@
3982 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
3983 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
3984 [(set_attr "type" "var_shift_rotate,integer")])
3985
3986 (define_insn "*rotlsi3_internal5"
3987 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3988 (compare:CC (and:SI
3989 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3990 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3991 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3992 (const_int 0)))
3993 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
3994 ""
3995 "@
3996 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
3997 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3998 #
3999 #"
4000 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4001 (set_attr "length" "4,4,8,8")])
4002
4003 (define_split
4004 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4005 (compare:CC (and:SI
4006 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4007 (match_operand:SI 2 "reg_or_cint_operand" ""))
4008 (match_operand:SI 3 "mask_operand" ""))
4009 (const_int 0)))
4010 (clobber (match_scratch:SI 4 ""))]
4011 "reload_completed"
4012 [(set (match_dup 4)
4013 (and:SI (rotate:SI (match_dup 1)
4014 (match_dup 2))
4015 (match_dup 3)))
4016 (set (match_dup 0)
4017 (compare:CC (match_dup 4)
4018 (const_int 0)))]
4019 "")
4020
4021 (define_insn "*rotlsi3_internal6"
4022 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
4023 (compare:CC (and:SI
4024 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4025 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4026 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4027 (const_int 0)))
4028 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4029 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4030 ""
4031 "@
4032 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
4033 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4034 #
4035 #"
4036 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4037 (set_attr "length" "4,4,8,8")])
4038
4039 (define_split
4040 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4041 (compare:CC (and:SI
4042 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4043 (match_operand:SI 2 "reg_or_cint_operand" ""))
4044 (match_operand:SI 3 "mask_operand" ""))
4045 (const_int 0)))
4046 (set (match_operand:SI 0 "gpc_reg_operand" "")
4047 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4048 "reload_completed"
4049 [(set (match_dup 0)
4050 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4051 (set (match_dup 4)
4052 (compare:CC (match_dup 0)
4053 (const_int 0)))]
4054 "")
4055
4056 (define_insn "*rotlsi3_internal7"
4057 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4058 (zero_extend:SI
4059 (subreg:QI
4060 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4061 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4062 ""
4063 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
4064
4065 (define_insn "*rotlsi3_internal8"
4066 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4067 (compare:CC (zero_extend:SI
4068 (subreg:QI
4069 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4070 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4071 (const_int 0)))
4072 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4073 ""
4074 "@
4075 {rlnm.|rlwnm.} %3,%1,%2,0xff
4076 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4077 #
4078 #"
4079 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4080 (set_attr "length" "4,4,8,8")])
4081
4082 (define_split
4083 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4084 (compare:CC (zero_extend:SI
4085 (subreg:QI
4086 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4087 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4088 (const_int 0)))
4089 (clobber (match_scratch:SI 3 ""))]
4090 "reload_completed"
4091 [(set (match_dup 3)
4092 (zero_extend:SI (subreg:QI
4093 (rotate:SI (match_dup 1)
4094 (match_dup 2)) 0)))
4095 (set (match_dup 0)
4096 (compare:CC (match_dup 3)
4097 (const_int 0)))]
4098 "")
4099
4100 (define_insn "*rotlsi3_internal9"
4101 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4102 (compare:CC (zero_extend:SI
4103 (subreg:QI
4104 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4105 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4106 (const_int 0)))
4107 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4108 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4109 ""
4110 "@
4111 {rlnm.|rlwnm.} %0,%1,%2,0xff
4112 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4113 #
4114 #"
4115 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4116 (set_attr "length" "4,4,8,8")])
4117
4118 (define_split
4119 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4120 (compare:CC (zero_extend:SI
4121 (subreg:QI
4122 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4123 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4124 (const_int 0)))
4125 (set (match_operand:SI 0 "gpc_reg_operand" "")
4126 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4127 "reload_completed"
4128 [(set (match_dup 0)
4129 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4130 (set (match_dup 3)
4131 (compare:CC (match_dup 0)
4132 (const_int 0)))]
4133 "")
4134
4135 (define_insn "*rotlsi3_internal10"
4136 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4137 (zero_extend:SI
4138 (subreg:HI
4139 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4140 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4141 ""
4142 "@
4143 {rlnm|rlwnm} %0,%1,%2,0xffff
4144 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4145 [(set_attr "type" "var_shift_rotate,integer")])
4146
4147
4148 (define_insn "*rotlsi3_internal11"
4149 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4150 (compare:CC (zero_extend:SI
4151 (subreg:HI
4152 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4153 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4154 (const_int 0)))
4155 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4156 ""
4157 "@
4158 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4159 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4160 #
4161 #"
4162 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4163 (set_attr "length" "4,4,8,8")])
4164
4165 (define_split
4166 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4167 (compare:CC (zero_extend:SI
4168 (subreg:HI
4169 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4170 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4171 (const_int 0)))
4172 (clobber (match_scratch:SI 3 ""))]
4173 "reload_completed"
4174 [(set (match_dup 3)
4175 (zero_extend:SI (subreg:HI
4176 (rotate:SI (match_dup 1)
4177 (match_dup 2)) 0)))
4178 (set (match_dup 0)
4179 (compare:CC (match_dup 3)
4180 (const_int 0)))]
4181 "")
4182
4183 (define_insn "*rotlsi3_internal12"
4184 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4185 (compare:CC (zero_extend:SI
4186 (subreg:HI
4187 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4188 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4189 (const_int 0)))
4190 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4191 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4192 ""
4193 "@
4194 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4195 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4196 #
4197 #"
4198 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4199 (set_attr "length" "4,4,8,8")])
4200
4201 (define_split
4202 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4203 (compare:CC (zero_extend:SI
4204 (subreg:HI
4205 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4206 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4207 (const_int 0)))
4208 (set (match_operand:SI 0 "gpc_reg_operand" "")
4209 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4210 "reload_completed"
4211 [(set (match_dup 0)
4212 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4213 (set (match_dup 3)
4214 (compare:CC (match_dup 0)
4215 (const_int 0)))]
4216 "")
4217
4218 ;; Note that we use "sle." instead of "sl." so that we can set
4219 ;; SHIFT_COUNT_TRUNCATED.
4220
4221 (define_expand "ashlsi3"
4222 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4223 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4224 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4225 ""
4226 "
4227 {
4228 if (TARGET_POWER)
4229 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4230 else
4231 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4232 DONE;
4233 }")
4234
4235 (define_insn "ashlsi3_power"
4236 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4237 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4238 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4239 (clobber (match_scratch:SI 3 "=q,X"))]
4240 "TARGET_POWER"
4241 "@
4242 sle %0,%1,%2
4243 {sli|slwi} %0,%1,%h2")
4244
4245 (define_insn "ashlsi3_no_power"
4246 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4247 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4248 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4249 "! TARGET_POWER"
4250 "@
4251 {sl|slw} %0,%1,%2
4252 {sli|slwi} %0,%1,%h2"
4253 [(set_attr "type" "var_shift_rotate,shift")])
4254
4255 (define_insn ""
4256 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4257 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4258 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4259 (const_int 0)))
4260 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4261 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4262 "TARGET_POWER"
4263 "@
4264 sle. %3,%1,%2
4265 {sli.|slwi.} %3,%1,%h2
4266 #
4267 #"
4268 [(set_attr "type" "delayed_compare")
4269 (set_attr "length" "4,4,8,8")])
4270
4271 (define_split
4272 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4273 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4274 (match_operand:SI 2 "reg_or_cint_operand" ""))
4275 (const_int 0)))
4276 (clobber (match_scratch:SI 3 ""))
4277 (clobber (match_scratch:SI 4 ""))]
4278 "TARGET_POWER && reload_completed"
4279 [(parallel [(set (match_dup 3)
4280 (ashift:SI (match_dup 1) (match_dup 2)))
4281 (clobber (match_dup 4))])
4282 (set (match_dup 0)
4283 (compare:CC (match_dup 3)
4284 (const_int 0)))]
4285 "")
4286
4287 (define_insn ""
4288 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4289 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4290 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4291 (const_int 0)))
4292 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4293 "! TARGET_POWER && TARGET_32BIT"
4294 "@
4295 {sl.|slw.} %3,%1,%2
4296 {sli.|slwi.} %3,%1,%h2
4297 #
4298 #"
4299 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4300 (set_attr "length" "4,4,8,8")])
4301
4302 (define_split
4303 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4304 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4305 (match_operand:SI 2 "reg_or_cint_operand" ""))
4306 (const_int 0)))
4307 (clobber (match_scratch:SI 3 ""))]
4308 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4309 [(set (match_dup 3)
4310 (ashift:SI (match_dup 1) (match_dup 2)))
4311 (set (match_dup 0)
4312 (compare:CC (match_dup 3)
4313 (const_int 0)))]
4314 "")
4315
4316 (define_insn ""
4317 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4318 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4319 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4320 (const_int 0)))
4321 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4322 (ashift:SI (match_dup 1) (match_dup 2)))
4323 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4324 "TARGET_POWER"
4325 "@
4326 sle. %0,%1,%2
4327 {sli.|slwi.} %0,%1,%h2
4328 #
4329 #"
4330 [(set_attr "type" "delayed_compare")
4331 (set_attr "length" "4,4,8,8")])
4332
4333 (define_split
4334 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4335 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4336 (match_operand:SI 2 "reg_or_cint_operand" ""))
4337 (const_int 0)))
4338 (set (match_operand:SI 0 "gpc_reg_operand" "")
4339 (ashift:SI (match_dup 1) (match_dup 2)))
4340 (clobber (match_scratch:SI 4 ""))]
4341 "TARGET_POWER && reload_completed"
4342 [(parallel [(set (match_dup 0)
4343 (ashift:SI (match_dup 1) (match_dup 2)))
4344 (clobber (match_dup 4))])
4345 (set (match_dup 3)
4346 (compare:CC (match_dup 0)
4347 (const_int 0)))]
4348 "")
4349
4350 (define_insn ""
4351 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4352 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4353 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4354 (const_int 0)))
4355 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4356 (ashift:SI (match_dup 1) (match_dup 2)))]
4357 "! TARGET_POWER && TARGET_32BIT"
4358 "@
4359 {sl.|slw.} %0,%1,%2
4360 {sli.|slwi.} %0,%1,%h2
4361 #
4362 #"
4363 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4364 (set_attr "length" "4,4,8,8")])
4365
4366 (define_split
4367 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4368 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4369 (match_operand:SI 2 "reg_or_cint_operand" ""))
4370 (const_int 0)))
4371 (set (match_operand:SI 0 "gpc_reg_operand" "")
4372 (ashift:SI (match_dup 1) (match_dup 2)))]
4373 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4374 [(set (match_dup 0)
4375 (ashift:SI (match_dup 1) (match_dup 2)))
4376 (set (match_dup 3)
4377 (compare:CC (match_dup 0)
4378 (const_int 0)))]
4379 "")
4380
4381 (define_insn "rlwinm"
4382 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4383 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4384 (match_operand:SI 2 "const_int_operand" "i"))
4385 (match_operand:SI 3 "mask_operand" "n")))]
4386 "includes_lshift_p (operands[2], operands[3])"
4387 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4388
4389 (define_insn ""
4390 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4391 (compare:CC
4392 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4393 (match_operand:SI 2 "const_int_operand" "i,i"))
4394 (match_operand:SI 3 "mask_operand" "n,n"))
4395 (const_int 0)))
4396 (clobber (match_scratch:SI 4 "=r,r"))]
4397 "includes_lshift_p (operands[2], operands[3])"
4398 "@
4399 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4400 #"
4401 [(set_attr "type" "delayed_compare")
4402 (set_attr "length" "4,8")])
4403
4404 (define_split
4405 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4406 (compare:CC
4407 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4408 (match_operand:SI 2 "const_int_operand" ""))
4409 (match_operand:SI 3 "mask_operand" ""))
4410 (const_int 0)))
4411 (clobber (match_scratch:SI 4 ""))]
4412 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4413 [(set (match_dup 4)
4414 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4415 (match_dup 3)))
4416 (set (match_dup 0)
4417 (compare:CC (match_dup 4)
4418 (const_int 0)))]
4419 "")
4420
4421 (define_insn ""
4422 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4423 (compare:CC
4424 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4425 (match_operand:SI 2 "const_int_operand" "i,i"))
4426 (match_operand:SI 3 "mask_operand" "n,n"))
4427 (const_int 0)))
4428 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4429 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4430 "includes_lshift_p (operands[2], operands[3])"
4431 "@
4432 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4433 #"
4434 [(set_attr "type" "delayed_compare")
4435 (set_attr "length" "4,8")])
4436
4437 (define_split
4438 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4439 (compare:CC
4440 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4441 (match_operand:SI 2 "const_int_operand" ""))
4442 (match_operand:SI 3 "mask_operand" ""))
4443 (const_int 0)))
4444 (set (match_operand:SI 0 "gpc_reg_operand" "")
4445 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4446 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4447 [(set (match_dup 0)
4448 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4449 (set (match_dup 4)
4450 (compare:CC (match_dup 0)
4451 (const_int 0)))]
4452 "")
4453
4454 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
4455 ;; "sli x,x,0".
4456 (define_expand "lshrsi3"
4457 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4458 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4459 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4460 ""
4461 "
4462 {
4463 if (TARGET_POWER)
4464 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4465 else
4466 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
4467 DONE;
4468 }")
4469
4470 (define_insn "lshrsi3_power"
4471 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4472 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4473 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4474 (clobber (match_scratch:SI 3 "=q,X,X"))]
4475 "TARGET_POWER"
4476 "@
4477 sre %0,%1,%2
4478 mr %0,%1
4479 {s%A2i|s%A2wi} %0,%1,%h2")
4480
4481 (define_insn "lshrsi3_no_power"
4482 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4483 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4484 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
4485 "! TARGET_POWER"
4486 "@
4487 mr %0,%1
4488 {sr|srw} %0,%1,%2
4489 {sri|srwi} %0,%1,%h2"
4490 [(set_attr "type" "integer,var_shift_rotate,shift")])
4491
4492 (define_insn ""
4493 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4494 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4495 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4496 (const_int 0)))
4497 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4498 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4499 "TARGET_POWER"
4500 "@
4501 sre. %3,%1,%2
4502 mr. %1,%1
4503 {s%A2i.|s%A2wi.} %3,%1,%h2
4504 #
4505 #
4506 #"
4507 [(set_attr "type" "delayed_compare")
4508 (set_attr "length" "4,4,4,8,8,8")])
4509
4510 (define_split
4511 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4512 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4513 (match_operand:SI 2 "reg_or_cint_operand" ""))
4514 (const_int 0)))
4515 (clobber (match_scratch:SI 3 ""))
4516 (clobber (match_scratch:SI 4 ""))]
4517 "TARGET_POWER && reload_completed"
4518 [(parallel [(set (match_dup 3)
4519 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4520 (clobber (match_dup 4))])
4521 (set (match_dup 0)
4522 (compare:CC (match_dup 3)
4523 (const_int 0)))]
4524 "")
4525
4526 (define_insn ""
4527 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4528 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4529 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4530 (const_int 0)))
4531 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4532 "! TARGET_POWER && TARGET_32BIT"
4533 "@
4534 mr. %1,%1
4535 {sr.|srw.} %3,%1,%2
4536 {sri.|srwi.} %3,%1,%h2
4537 #
4538 #
4539 #"
4540 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4541 (set_attr "length" "4,4,4,8,8,8")])
4542
4543 (define_split
4544 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4545 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4546 (match_operand:SI 2 "reg_or_cint_operand" ""))
4547 (const_int 0)))
4548 (clobber (match_scratch:SI 3 ""))]
4549 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4550 [(set (match_dup 3)
4551 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4552 (set (match_dup 0)
4553 (compare:CC (match_dup 3)
4554 (const_int 0)))]
4555 "")
4556
4557 (define_insn ""
4558 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4559 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4560 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4561 (const_int 0)))
4562 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4563 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4564 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4565 "TARGET_POWER"
4566 "@
4567 sre. %0,%1,%2
4568 mr. %0,%1
4569 {s%A2i.|s%A2wi.} %0,%1,%h2
4570 #
4571 #
4572 #"
4573 [(set_attr "type" "delayed_compare")
4574 (set_attr "length" "4,4,4,8,8,8")])
4575
4576 (define_split
4577 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4578 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4579 (match_operand:SI 2 "reg_or_cint_operand" ""))
4580 (const_int 0)))
4581 (set (match_operand:SI 0 "gpc_reg_operand" "")
4582 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4583 (clobber (match_scratch:SI 4 ""))]
4584 "TARGET_POWER && reload_completed"
4585 [(parallel [(set (match_dup 0)
4586 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4587 (clobber (match_dup 4))])
4588 (set (match_dup 3)
4589 (compare:CC (match_dup 0)
4590 (const_int 0)))]
4591 "")
4592
4593 (define_insn ""
4594 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4595 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4596 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4597 (const_int 0)))
4598 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4599 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4600 "! TARGET_POWER && TARGET_32BIT"
4601 "@
4602 mr. %0,%1
4603 {sr.|srw.} %0,%1,%2
4604 {sri.|srwi.} %0,%1,%h2
4605 #
4606 #
4607 #"
4608 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4609 (set_attr "length" "4,4,4,8,8,8")])
4610
4611 (define_split
4612 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4613 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4614 (match_operand:SI 2 "reg_or_cint_operand" ""))
4615 (const_int 0)))
4616 (set (match_operand:SI 0 "gpc_reg_operand" "")
4617 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4618 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4619 [(set (match_dup 0)
4620 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4621 (set (match_dup 3)
4622 (compare:CC (match_dup 0)
4623 (const_int 0)))]
4624 "")
4625
4626 (define_insn ""
4627 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4628 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4629 (match_operand:SI 2 "const_int_operand" "i"))
4630 (match_operand:SI 3 "mask_operand" "n")))]
4631 "includes_rshift_p (operands[2], operands[3])"
4632 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4633
4634 (define_insn ""
4635 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4636 (compare:CC
4637 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4638 (match_operand:SI 2 "const_int_operand" "i,i"))
4639 (match_operand:SI 3 "mask_operand" "n,n"))
4640 (const_int 0)))
4641 (clobber (match_scratch:SI 4 "=r,r"))]
4642 "includes_rshift_p (operands[2], operands[3])"
4643 "@
4644 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4645 #"
4646 [(set_attr "type" "delayed_compare")
4647 (set_attr "length" "4,8")])
4648
4649 (define_split
4650 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4651 (compare:CC
4652 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4653 (match_operand:SI 2 "const_int_operand" ""))
4654 (match_operand:SI 3 "mask_operand" ""))
4655 (const_int 0)))
4656 (clobber (match_scratch:SI 4 ""))]
4657 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4658 [(set (match_dup 4)
4659 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4660 (match_dup 3)))
4661 (set (match_dup 0)
4662 (compare:CC (match_dup 4)
4663 (const_int 0)))]
4664 "")
4665
4666 (define_insn ""
4667 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4668 (compare:CC
4669 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4670 (match_operand:SI 2 "const_int_operand" "i,i"))
4671 (match_operand:SI 3 "mask_operand" "n,n"))
4672 (const_int 0)))
4673 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4674 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4675 "includes_rshift_p (operands[2], operands[3])"
4676 "@
4677 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4678 #"
4679 [(set_attr "type" "delayed_compare")
4680 (set_attr "length" "4,8")])
4681
4682 (define_split
4683 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4684 (compare:CC
4685 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4686 (match_operand:SI 2 "const_int_operand" ""))
4687 (match_operand:SI 3 "mask_operand" ""))
4688 (const_int 0)))
4689 (set (match_operand:SI 0 "gpc_reg_operand" "")
4690 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4691 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4692 [(set (match_dup 0)
4693 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4694 (set (match_dup 4)
4695 (compare:CC (match_dup 0)
4696 (const_int 0)))]
4697 "")
4698
4699 (define_insn ""
4700 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4701 (zero_extend:SI
4702 (subreg:QI
4703 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4704 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4705 "includes_rshift_p (operands[2], GEN_INT (255))"
4706 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4707
4708 (define_insn ""
4709 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4710 (compare:CC
4711 (zero_extend:SI
4712 (subreg:QI
4713 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4714 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4715 (const_int 0)))
4716 (clobber (match_scratch:SI 3 "=r,r"))]
4717 "includes_rshift_p (operands[2], GEN_INT (255))"
4718 "@
4719 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4720 #"
4721 [(set_attr "type" "delayed_compare")
4722 (set_attr "length" "4,8")])
4723
4724 (define_split
4725 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4726 (compare:CC
4727 (zero_extend:SI
4728 (subreg:QI
4729 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4730 (match_operand:SI 2 "const_int_operand" "")) 0))
4731 (const_int 0)))
4732 (clobber (match_scratch:SI 3 ""))]
4733 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4734 [(set (match_dup 3)
4735 (zero_extend:SI (subreg:QI
4736 (lshiftrt:SI (match_dup 1)
4737 (match_dup 2)) 0)))
4738 (set (match_dup 0)
4739 (compare:CC (match_dup 3)
4740 (const_int 0)))]
4741 "")
4742
4743 (define_insn ""
4744 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4745 (compare:CC
4746 (zero_extend:SI
4747 (subreg:QI
4748 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4749 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4750 (const_int 0)))
4751 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4752 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4753 "includes_rshift_p (operands[2], GEN_INT (255))"
4754 "@
4755 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4756 #"
4757 [(set_attr "type" "delayed_compare")
4758 (set_attr "length" "4,8")])
4759
4760 (define_split
4761 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4762 (compare:CC
4763 (zero_extend:SI
4764 (subreg:QI
4765 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4766 (match_operand:SI 2 "const_int_operand" "")) 0))
4767 (const_int 0)))
4768 (set (match_operand:SI 0 "gpc_reg_operand" "")
4769 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4770 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4771 [(set (match_dup 0)
4772 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4773 (set (match_dup 3)
4774 (compare:CC (match_dup 0)
4775 (const_int 0)))]
4776 "")
4777
4778 (define_insn ""
4779 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4780 (zero_extend:SI
4781 (subreg:HI
4782 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4783 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4784 "includes_rshift_p (operands[2], GEN_INT (65535))"
4785 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4786
4787 (define_insn ""
4788 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4789 (compare:CC
4790 (zero_extend:SI
4791 (subreg:HI
4792 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4793 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4794 (const_int 0)))
4795 (clobber (match_scratch:SI 3 "=r,r"))]
4796 "includes_rshift_p (operands[2], GEN_INT (65535))"
4797 "@
4798 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4799 #"
4800 [(set_attr "type" "delayed_compare")
4801 (set_attr "length" "4,8")])
4802
4803 (define_split
4804 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4805 (compare:CC
4806 (zero_extend:SI
4807 (subreg:HI
4808 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4809 (match_operand:SI 2 "const_int_operand" "")) 0))
4810 (const_int 0)))
4811 (clobber (match_scratch:SI 3 ""))]
4812 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4813 [(set (match_dup 3)
4814 (zero_extend:SI (subreg:HI
4815 (lshiftrt:SI (match_dup 1)
4816 (match_dup 2)) 0)))
4817 (set (match_dup 0)
4818 (compare:CC (match_dup 3)
4819 (const_int 0)))]
4820 "")
4821
4822 (define_insn ""
4823 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4824 (compare:CC
4825 (zero_extend:SI
4826 (subreg:HI
4827 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4828 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4829 (const_int 0)))
4830 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4831 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4832 "includes_rshift_p (operands[2], GEN_INT (65535))"
4833 "@
4834 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4835 #"
4836 [(set_attr "type" "delayed_compare")
4837 (set_attr "length" "4,8")])
4838
4839 (define_split
4840 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4841 (compare:CC
4842 (zero_extend:SI
4843 (subreg:HI
4844 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4845 (match_operand:SI 2 "const_int_operand" "")) 0))
4846 (const_int 0)))
4847 (set (match_operand:SI 0 "gpc_reg_operand" "")
4848 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4849 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4850 [(set (match_dup 0)
4851 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4852 (set (match_dup 3)
4853 (compare:CC (match_dup 0)
4854 (const_int 0)))]
4855 "")
4856
4857 (define_insn ""
4858 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4859 (const_int 1)
4860 (match_operand:SI 1 "gpc_reg_operand" "r"))
4861 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4862 (const_int 31)))]
4863 "TARGET_POWER"
4864 "rrib %0,%1,%2")
4865
4866 (define_insn ""
4867 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4868 (const_int 1)
4869 (match_operand:SI 1 "gpc_reg_operand" "r"))
4870 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4871 (const_int 31)))]
4872 "TARGET_POWER"
4873 "rrib %0,%1,%2")
4874
4875 (define_insn ""
4876 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4877 (const_int 1)
4878 (match_operand:SI 1 "gpc_reg_operand" "r"))
4879 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4880 (const_int 1)
4881 (const_int 0)))]
4882 "TARGET_POWER"
4883 "rrib %0,%1,%2")
4884
4885 (define_expand "ashrsi3"
4886 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4887 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4888 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4889 ""
4890 "
4891 {
4892 if (TARGET_POWER)
4893 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4894 else
4895 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4896 DONE;
4897 }")
4898
4899 (define_insn "ashrsi3_power"
4900 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4901 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4902 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4903 (clobber (match_scratch:SI 3 "=q,X"))]
4904 "TARGET_POWER"
4905 "@
4906 srea %0,%1,%2
4907 {srai|srawi} %0,%1,%h2"
4908 [(set_attr "type" "shift")])
4909
4910 (define_insn "ashrsi3_no_power"
4911 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4912 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4913 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4914 "! TARGET_POWER"
4915 "@
4916 {sra|sraw} %0,%1,%2
4917 {srai|srawi} %0,%1,%h2"
4918 [(set_attr "type" "var_shift_rotate,shift")])
4919
4920 (define_insn ""
4921 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4922 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4923 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4924 (const_int 0)))
4925 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4926 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4927 "TARGET_POWER"
4928 "@
4929 srea. %3,%1,%2
4930 {srai.|srawi.} %3,%1,%h2
4931 #
4932 #"
4933 [(set_attr "type" "delayed_compare")
4934 (set_attr "length" "4,4,8,8")])
4935
4936 (define_split
4937 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4938 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4939 (match_operand:SI 2 "reg_or_cint_operand" ""))
4940 (const_int 0)))
4941 (clobber (match_scratch:SI 3 ""))
4942 (clobber (match_scratch:SI 4 ""))]
4943 "TARGET_POWER && reload_completed"
4944 [(parallel [(set (match_dup 3)
4945 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4946 (clobber (match_dup 4))])
4947 (set (match_dup 0)
4948 (compare:CC (match_dup 3)
4949 (const_int 0)))]
4950 "")
4951
4952 (define_insn ""
4953 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4954 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4955 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4956 (const_int 0)))
4957 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4958 "! TARGET_POWER"
4959 "@
4960 {sra.|sraw.} %3,%1,%2
4961 {srai.|srawi.} %3,%1,%h2
4962 #
4963 #"
4964 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4965 (set_attr "length" "4,4,8,8")])
4966
4967 (define_split
4968 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4969 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4970 (match_operand:SI 2 "reg_or_cint_operand" ""))
4971 (const_int 0)))
4972 (clobber (match_scratch:SI 3 ""))]
4973 "! TARGET_POWER && reload_completed"
4974 [(set (match_dup 3)
4975 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4976 (set (match_dup 0)
4977 (compare:CC (match_dup 3)
4978 (const_int 0)))]
4979 "")
4980
4981 (define_insn ""
4982 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4983 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4984 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4985 (const_int 0)))
4986 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4987 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4988 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4989 "TARGET_POWER"
4990 "@
4991 srea. %0,%1,%2
4992 {srai.|srawi.} %0,%1,%h2
4993 #
4994 #"
4995 [(set_attr "type" "delayed_compare")
4996 (set_attr "length" "4,4,8,8")])
4997
4998 (define_split
4999 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5000 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5001 (match_operand:SI 2 "reg_or_cint_operand" ""))
5002 (const_int 0)))
5003 (set (match_operand:SI 0 "gpc_reg_operand" "")
5004 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5005 (clobber (match_scratch:SI 4 ""))]
5006 "TARGET_POWER && reload_completed"
5007 [(parallel [(set (match_dup 0)
5008 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5009 (clobber (match_dup 4))])
5010 (set (match_dup 3)
5011 (compare:CC (match_dup 0)
5012 (const_int 0)))]
5013 "")
5014
5015 (define_insn ""
5016 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5017 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5018 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5019 (const_int 0)))
5020 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5021 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5022 "! TARGET_POWER"
5023 "@
5024 {sra.|sraw.} %0,%1,%2
5025 {srai.|srawi.} %0,%1,%h2
5026 #
5027 #"
5028 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5029 (set_attr "length" "4,4,8,8")])
5030 \f
5031 (define_split
5032 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5033 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5034 (match_operand:SI 2 "reg_or_cint_operand" ""))
5035 (const_int 0)))
5036 (set (match_operand:SI 0 "gpc_reg_operand" "")
5037 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5038 "! TARGET_POWER && reload_completed"
5039 [(set (match_dup 0)
5040 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5041 (set (match_dup 3)
5042 (compare:CC (match_dup 0)
5043 (const_int 0)))]
5044 "")
5045
5046 ;; Floating-point insns, excluding normal data motion.
5047 ;;
5048 ;; PowerPC has a full set of single-precision floating point instructions.
5049 ;;
5050 ;; For the POWER architecture, we pretend that we have both SFmode and
5051 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
5052 ;; The only conversions we will do will be when storing to memory. In that
5053 ;; case, we will use the "frsp" instruction before storing.
5054 ;;
5055 ;; Note that when we store into a single-precision memory location, we need to
5056 ;; use the frsp insn first. If the register being stored isn't dead, we
5057 ;; need a scratch register for the frsp. But this is difficult when the store
5058 ;; is done by reload. It is not incorrect to do the frsp on the register in
5059 ;; this case, we just lose precision that we would have otherwise gotten but
5060 ;; is not guaranteed. Perhaps this should be tightened up at some point.
5061
5062 (define_expand "extendsfdf2"
5063 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5064 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5065 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5066 "")
5067
5068 (define_insn_and_split "*extendsfdf2_fpr"
5069 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
5070 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
5071 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5072 "@
5073 #
5074 fmr %0,%1
5075 lfs%U1%X1 %0,%1"
5076 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5077 [(const_int 0)]
5078 {
5079 emit_note (NOTE_INSN_DELETED);
5080 DONE;
5081 }
5082 [(set_attr "type" "fp,fp,fpload")])
5083
5084 (define_expand "truncdfsf2"
5085 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5086 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5087 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5088 "")
5089
5090 (define_insn "*truncdfsf2_fpr"
5091 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5092 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5093 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5094 "frsp %0,%1"
5095 [(set_attr "type" "fp")])
5096
5097 (define_insn "aux_truncdfsf2"
5098 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5099 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
5100 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5101 "frsp %0,%1"
5102 [(set_attr "type" "fp")])
5103
5104 (define_expand "negsf2"
5105 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5106 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5107 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5108 "")
5109
5110 (define_insn "*negsf2"
5111 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5112 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5113 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5114 "fneg %0,%1"
5115 [(set_attr "type" "fp")])
5116
5117 (define_expand "abssf2"
5118 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5119 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5120 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5121 "")
5122
5123 (define_insn "*abssf2"
5124 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5125 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5126 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5127 "fabs %0,%1"
5128 [(set_attr "type" "fp")])
5129
5130 (define_insn ""
5131 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5132 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
5133 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5134 "fnabs %0,%1"
5135 [(set_attr "type" "fp")])
5136
5137 (define_expand "addsf3"
5138 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5139 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5140 (match_operand:SF 2 "gpc_reg_operand" "")))]
5141 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5142 "")
5143
5144 (define_insn ""
5145 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5146 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5147 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5148 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5149 "fadds %0,%1,%2"
5150 [(set_attr "type" "fp")])
5151
5152 (define_insn ""
5153 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5154 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5155 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5156 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5157 "{fa|fadd} %0,%1,%2"
5158 [(set_attr "type" "fp")])
5159
5160 (define_expand "subsf3"
5161 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5162 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5163 (match_operand:SF 2 "gpc_reg_operand" "")))]
5164 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5165 "")
5166
5167 (define_insn ""
5168 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5169 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5170 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5171 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5172 "fsubs %0,%1,%2"
5173 [(set_attr "type" "fp")])
5174
5175 (define_insn ""
5176 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5177 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5178 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5179 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5180 "{fs|fsub} %0,%1,%2"
5181 [(set_attr "type" "fp")])
5182
5183 (define_expand "mulsf3"
5184 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5185 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5186 (match_operand:SF 2 "gpc_reg_operand" "")))]
5187 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5188 "")
5189
5190 (define_insn ""
5191 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5192 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5193 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5194 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5195 "fmuls %0,%1,%2"
5196 [(set_attr "type" "fp")])
5197
5198 (define_insn ""
5199 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5200 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5201 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5202 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5203 "{fm|fmul} %0,%1,%2"
5204 [(set_attr "type" "dmul")])
5205
5206 (define_expand "divsf3"
5207 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5208 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5209 (match_operand:SF 2 "gpc_reg_operand" "")))]
5210 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5211 "")
5212
5213 (define_insn ""
5214 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5215 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5216 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5217 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5218 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5219 "fdivs %0,%1,%2"
5220 [(set_attr "type" "sdiv")])
5221
5222 (define_insn ""
5223 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5224 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5225 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5226 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5227 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5228 "{fd|fdiv} %0,%1,%2"
5229 [(set_attr "type" "ddiv")])
5230
5231 (define_expand "recipsf3"
5232 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5233 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")
5234 (match_operand:SF 2 "gpc_reg_operand" "f")]
5235 UNSPEC_FRES))]
5236 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5237 && flag_finite_math_only && !flag_trapping_math"
5238 {
5239 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5240 DONE;
5241 })
5242
5243 (define_insn "fres"
5244 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5245 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5246 "TARGET_PPC_GFXOPT && flag_finite_math_only"
5247 "fres %0,%1"
5248 [(set_attr "type" "fp")])
5249
5250 (define_insn ""
5251 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5252 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5253 (match_operand:SF 2 "gpc_reg_operand" "f"))
5254 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5255 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5256 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5257 "fmadds %0,%1,%2,%3"
5258 [(set_attr "type" "fp")])
5259
5260 (define_insn ""
5261 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5262 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5263 (match_operand:SF 2 "gpc_reg_operand" "f"))
5264 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5265 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5266 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5267 "{fma|fmadd} %0,%1,%2,%3"
5268 [(set_attr "type" "dmul")])
5269
5270 (define_insn ""
5271 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5272 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5273 (match_operand:SF 2 "gpc_reg_operand" "f"))
5274 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5275 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5276 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5277 "fmsubs %0,%1,%2,%3"
5278 [(set_attr "type" "fp")])
5279
5280 (define_insn ""
5281 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5282 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5283 (match_operand:SF 2 "gpc_reg_operand" "f"))
5284 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5285 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5286 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5287 "{fms|fmsub} %0,%1,%2,%3"
5288 [(set_attr "type" "dmul")])
5289
5290 (define_insn ""
5291 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5292 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5293 (match_operand:SF 2 "gpc_reg_operand" "f"))
5294 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5295 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5296 && TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)"
5297 "fnmadds %0,%1,%2,%3"
5298 [(set_attr "type" "fp")])
5299
5300 (define_insn ""
5301 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5302 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5303 (match_operand:SF 2 "gpc_reg_operand" "f"))
5304 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5305 "TARGET_POWERPC && TARGET_SINGLE_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5306 && ! HONOR_SIGNED_ZEROS (SFmode)"
5307 "fnmadds %0,%1,%2,%3"
5308 [(set_attr "type" "fp")])
5309
5310 (define_insn ""
5311 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5312 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5313 (match_operand:SF 2 "gpc_reg_operand" "f"))
5314 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5315 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5316 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5317 "{fnma|fnmadd} %0,%1,%2,%3"
5318 [(set_attr "type" "dmul")])
5319
5320 (define_insn ""
5321 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5322 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5323 (match_operand:SF 2 "gpc_reg_operand" "f"))
5324 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5325 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5326 && TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)"
5327 "{fnma|fnmadd} %0,%1,%2,%3"
5328 [(set_attr "type" "dmul")])
5329
5330 (define_insn ""
5331 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5332 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5333 (match_operand:SF 2 "gpc_reg_operand" "f"))
5334 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5335 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5336 && TARGET_SINGLE_FLOAT && HONOR_SIGNED_ZEROS (SFmode)"
5337 "fnmsubs %0,%1,%2,%3"
5338 [(set_attr "type" "fp")])
5339
5340 (define_insn ""
5341 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5342 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5343 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5344 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5345 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5346 && TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)"
5347 "fnmsubs %0,%1,%2,%3"
5348 [(set_attr "type" "fp")])
5349
5350 (define_insn ""
5351 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5352 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5353 (match_operand:SF 2 "gpc_reg_operand" "f"))
5354 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5355 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5356 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5357 "{fnms|fnmsub} %0,%1,%2,%3"
5358 [(set_attr "type" "dmul")])
5359
5360 (define_insn ""
5361 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5362 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5363 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5364 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5365 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5366 && TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)"
5367 "{fnms|fnmsub} %0,%1,%2,%3"
5368 [(set_attr "type" "dmul")])
5369
5370 (define_expand "sqrtsf2"
5371 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5372 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5373 "(TARGET_PPC_GPOPT || TARGET_POWER2)
5374 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5375 && !TARGET_SIMPLE_FPU"
5376 "")
5377
5378 (define_insn ""
5379 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5380 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5381 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT
5382 && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5383 "fsqrts %0,%1"
5384 [(set_attr "type" "ssqrt")])
5385
5386 (define_insn ""
5387 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5388 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5389 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS
5390 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5391 "fsqrt %0,%1"
5392 [(set_attr "type" "dsqrt")])
5393
5394 (define_expand "rsqrtsf2"
5395 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5396 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5397 UNSPEC_RSQRT))]
5398 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5399 && flag_finite_math_only && !flag_trapping_math"
5400 {
5401 rs6000_emit_swrsqrtsf (operands[0], operands[1]);
5402 DONE;
5403 })
5404
5405 (define_insn "*rsqrt_internal1"
5406 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5407 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5408 UNSPEC_RSQRT))]
5409 "TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT"
5410 "frsqrte %0,%1"
5411 [(set_attr "type" "fp")])
5412
5413 (define_expand "copysignsf3"
5414 [(set (match_dup 3)
5415 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5416 (set (match_dup 4)
5417 (neg:SF (abs:SF (match_dup 1))))
5418 (set (match_operand:SF 0 "gpc_reg_operand" "")
5419 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5420 (match_dup 5))
5421 (match_dup 3)
5422 (match_dup 4)))]
5423 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5424 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
5425 {
5426 operands[3] = gen_reg_rtx (SFmode);
5427 operands[4] = gen_reg_rtx (SFmode);
5428 operands[5] = CONST0_RTX (SFmode);
5429 })
5430
5431 (define_expand "copysigndf3"
5432 [(set (match_dup 3)
5433 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5434 (set (match_dup 4)
5435 (neg:DF (abs:DF (match_dup 1))))
5436 (set (match_operand:DF 0 "gpc_reg_operand" "")
5437 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5438 (match_dup 5))
5439 (match_dup 3)
5440 (match_dup 4)))]
5441 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5442 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
5443 {
5444 operands[3] = gen_reg_rtx (DFmode);
5445 operands[4] = gen_reg_rtx (DFmode);
5446 operands[5] = CONST0_RTX (DFmode);
5447 })
5448
5449 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5450 ;; fsel instruction and some auxiliary computations. Then we just have a
5451 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5452 ;; combine.
5453 (define_expand "smaxsf3"
5454 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5455 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5456 (match_operand:SF 2 "gpc_reg_operand" ""))
5457 (match_dup 1)
5458 (match_dup 2)))]
5459 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5460 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5461 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5462
5463 (define_expand "sminsf3"
5464 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5465 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5466 (match_operand:SF 2 "gpc_reg_operand" ""))
5467 (match_dup 2)
5468 (match_dup 1)))]
5469 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5470 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5471 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5472
5473 (define_split
5474 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5475 (match_operator:SF 3 "min_max_operator"
5476 [(match_operand:SF 1 "gpc_reg_operand" "")
5477 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5478 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5479 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5480 [(const_int 0)]
5481 "
5482 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5483 operands[1], operands[2]);
5484 DONE;
5485 }")
5486
5487 (define_expand "movsicc"
5488 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5489 (if_then_else:SI (match_operand 1 "comparison_operator" "")
5490 (match_operand:SI 2 "gpc_reg_operand" "")
5491 (match_operand:SI 3 "gpc_reg_operand" "")))]
5492 "TARGET_ISEL"
5493 "
5494 {
5495 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5496 DONE;
5497 else
5498 FAIL;
5499 }")
5500
5501 ;; We use the BASE_REGS for the isel input operands because, if rA is
5502 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5503 ;; because we may switch the operands and rB may end up being rA.
5504 ;;
5505 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5506 ;; leave out the mode in operand 4 and use one pattern, but reload can
5507 ;; change the mode underneath our feet and then gets confused trying
5508 ;; to reload the value.
5509 (define_insn "isel_signed"
5510 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5511 (if_then_else:SI
5512 (match_operator 1 "comparison_operator"
5513 [(match_operand:CC 4 "cc_reg_operand" "y")
5514 (const_int 0)])
5515 (match_operand:SI 2 "gpc_reg_operand" "b")
5516 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5517 "TARGET_ISEL"
5518 "*
5519 { return output_isel (operands); }"
5520 [(set_attr "length" "4")])
5521
5522 (define_insn "isel_unsigned"
5523 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5524 (if_then_else:SI
5525 (match_operator 1 "comparison_operator"
5526 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5527 (const_int 0)])
5528 (match_operand:SI 2 "gpc_reg_operand" "b")
5529 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5530 "TARGET_ISEL"
5531 "*
5532 { return output_isel (operands); }"
5533 [(set_attr "length" "4")])
5534
5535 (define_expand "movsfcc"
5536 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5537 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5538 (match_operand:SF 2 "gpc_reg_operand" "")
5539 (match_operand:SF 3 "gpc_reg_operand" "")))]
5540 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5541 "
5542 {
5543 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5544 DONE;
5545 else
5546 FAIL;
5547 }")
5548
5549 (define_insn "*fselsfsf4"
5550 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5551 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5552 (match_operand:SF 4 "zero_fp_constant" "F"))
5553 (match_operand:SF 2 "gpc_reg_operand" "f")
5554 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5555 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5556 "fsel %0,%1,%2,%3"
5557 [(set_attr "type" "fp")])
5558
5559 (define_insn "*fseldfsf4"
5560 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5561 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5562 (match_operand:DF 4 "zero_fp_constant" "F"))
5563 (match_operand:SF 2 "gpc_reg_operand" "f")
5564 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5565 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5566 "fsel %0,%1,%2,%3"
5567 [(set_attr "type" "fp")])
5568
5569 (define_expand "negdf2"
5570 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5571 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5572 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5573 "")
5574
5575 (define_insn "*negdf2_fpr"
5576 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5577 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5578 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5579 "fneg %0,%1"
5580 [(set_attr "type" "fp")])
5581
5582 (define_expand "absdf2"
5583 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5584 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5585 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5586 "")
5587
5588 (define_insn "*absdf2_fpr"
5589 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5590 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5591 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5592 "fabs %0,%1"
5593 [(set_attr "type" "fp")])
5594
5595 (define_insn "*nabsdf2_fpr"
5596 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5597 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
5598 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5599 "fnabs %0,%1"
5600 [(set_attr "type" "fp")])
5601
5602 (define_expand "adddf3"
5603 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5604 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5605 (match_operand:DF 2 "gpc_reg_operand" "")))]
5606 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5607 "")
5608
5609 (define_insn "*adddf3_fpr"
5610 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5611 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5612 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5613 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5614 "{fa|fadd} %0,%1,%2"
5615 [(set_attr "type" "fp")])
5616
5617 (define_expand "subdf3"
5618 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5619 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5620 (match_operand:DF 2 "gpc_reg_operand" "")))]
5621 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5622 "")
5623
5624 (define_insn "*subdf3_fpr"
5625 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5626 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5627 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5628 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5629 "{fs|fsub} %0,%1,%2"
5630 [(set_attr "type" "fp")])
5631
5632 (define_expand "muldf3"
5633 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5634 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5635 (match_operand:DF 2 "gpc_reg_operand" "")))]
5636 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5637 "")
5638
5639 (define_insn "*muldf3_fpr"
5640 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5641 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5642 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5643 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5644 "{fm|fmul} %0,%1,%2"
5645 [(set_attr "type" "dmul")])
5646
5647 (define_expand "divdf3"
5648 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5649 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5650 (match_operand:DF 2 "gpc_reg_operand" "")))]
5651 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE) && !TARGET_SIMPLE_FPU"
5652 "")
5653
5654 (define_insn "*divdf3_fpr"
5655 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5656 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5657 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5658 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU"
5659 "{fd|fdiv} %0,%1,%2"
5660 [(set_attr "type" "ddiv")])
5661
5662 (define_expand "recipdf3"
5663 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5664 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")
5665 (match_operand:DF 2 "gpc_reg_operand" "f")]
5666 UNSPEC_FRES))]
5667 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_POPCNTB && !optimize_size
5668 && flag_finite_math_only && !flag_trapping_math"
5669 {
5670 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5671 DONE;
5672 })
5673
5674 (define_insn "fred"
5675 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5676 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5677 "TARGET_POPCNTB && flag_finite_math_only"
5678 "fre %0,%1"
5679 [(set_attr "type" "fp")])
5680
5681 (define_insn ""
5682 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5683 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5684 (match_operand:DF 2 "gpc_reg_operand" "f"))
5685 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5686 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT"
5687 "{fma|fmadd} %0,%1,%2,%3"
5688 [(set_attr "type" "dmul")])
5689
5690 (define_insn ""
5691 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5692 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5693 (match_operand:DF 2 "gpc_reg_operand" "f"))
5694 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5695 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT"
5696 "{fms|fmsub} %0,%1,%2,%3"
5697 [(set_attr "type" "dmul")])
5698
5699 (define_insn ""
5700 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5701 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5702 (match_operand:DF 2 "gpc_reg_operand" "f"))
5703 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5704 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
5705 && HONOR_SIGNED_ZEROS (DFmode)"
5706 "{fnma|fnmadd} %0,%1,%2,%3"
5707 [(set_attr "type" "dmul")])
5708
5709 (define_insn ""
5710 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5711 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5712 (match_operand:DF 2 "gpc_reg_operand" "f"))
5713 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5714 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
5715 && ! HONOR_SIGNED_ZEROS (DFmode)"
5716 "{fnma|fnmadd} %0,%1,%2,%3"
5717 [(set_attr "type" "dmul")])
5718
5719 (define_insn ""
5720 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5721 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5722 (match_operand:DF 2 "gpc_reg_operand" "f"))
5723 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5724 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
5725 && HONOR_SIGNED_ZEROS (DFmode)"
5726 "{fnms|fnmsub} %0,%1,%2,%3"
5727 [(set_attr "type" "dmul")])
5728
5729 (define_insn ""
5730 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5731 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5732 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5733 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5734 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
5735 && ! HONOR_SIGNED_ZEROS (DFmode)"
5736 "{fnms|fnmsub} %0,%1,%2,%3"
5737 [(set_attr "type" "dmul")])
5738
5739 (define_insn "sqrtdf2"
5740 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5741 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5742 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
5743 && TARGET_DOUBLE_FLOAT"
5744 "fsqrt %0,%1"
5745 [(set_attr "type" "dsqrt")])
5746
5747 ;; The conditional move instructions allow us to perform max and min
5748 ;; operations even when
5749
5750 (define_expand "smaxdf3"
5751 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5752 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5753 (match_operand:DF 2 "gpc_reg_operand" ""))
5754 (match_dup 1)
5755 (match_dup 2)))]
5756 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5757 && !flag_trapping_math"
5758 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5759
5760 (define_expand "smindf3"
5761 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5762 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5763 (match_operand:DF 2 "gpc_reg_operand" ""))
5764 (match_dup 2)
5765 (match_dup 1)))]
5766 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5767 && !flag_trapping_math"
5768 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5769
5770 (define_split
5771 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5772 (match_operator:DF 3 "min_max_operator"
5773 [(match_operand:DF 1 "gpc_reg_operand" "")
5774 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5775 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5776 && !flag_trapping_math"
5777 [(const_int 0)]
5778 "
5779 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5780 operands[1], operands[2]);
5781 DONE;
5782 }")
5783
5784 (define_expand "movdfcc"
5785 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5786 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5787 (match_operand:DF 2 "gpc_reg_operand" "")
5788 (match_operand:DF 3 "gpc_reg_operand" "")))]
5789 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5790 "
5791 {
5792 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5793 DONE;
5794 else
5795 FAIL;
5796 }")
5797
5798 (define_insn "*fseldfdf4"
5799 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5800 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5801 (match_operand:DF 4 "zero_fp_constant" "F"))
5802 (match_operand:DF 2 "gpc_reg_operand" "f")
5803 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5804 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5805 "fsel %0,%1,%2,%3"
5806 [(set_attr "type" "fp")])
5807
5808 (define_insn "*fselsfdf4"
5809 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5810 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5811 (match_operand:SF 4 "zero_fp_constant" "F"))
5812 (match_operand:DF 2 "gpc_reg_operand" "f")
5813 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5814 "TARGET_PPC_GFXOPT"
5815 "fsel %0,%1,%2,%3"
5816 [(set_attr "type" "fp")])
5817 \f
5818 ;; Conversions to and from floating-point.
5819
5820 (define_expand "fixuns_truncsfsi2"
5821 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5822 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5823 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
5824 "")
5825
5826 (define_expand "fix_truncsfsi2"
5827 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5828 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5829 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
5830 "")
5831
5832 ; For each of these conversions, there is a define_expand, a define_insn
5833 ; with a '#' template, and a define_split (with C code). The idea is
5834 ; to allow constant folding with the template of the define_insn,
5835 ; then to have the insns split later (between sched1 and final).
5836
5837 (define_expand "floatsidf2"
5838 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5839 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5840 (use (match_dup 2))
5841 (use (match_dup 3))
5842 (clobber (match_dup 4))
5843 (clobber (match_dup 5))
5844 (clobber (match_dup 6))])]
5845 "TARGET_HARD_FLOAT
5846 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5847 "
5848 {
5849 if (TARGET_E500_DOUBLE)
5850 {
5851 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5852 DONE;
5853 }
5854 if (TARGET_POWERPC64)
5855 {
5856 rtx x = convert_to_mode (DImode, operands[1], 0);
5857 emit_insn (gen_floatdidf2 (operands[0], x));
5858 DONE;
5859 }
5860
5861 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5862 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5863 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5864 operands[5] = gen_reg_rtx (DFmode);
5865 operands[6] = gen_reg_rtx (SImode);
5866 }")
5867
5868 (define_insn_and_split "*floatsidf2_internal"
5869 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5870 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5871 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5872 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5873 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5874 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5875 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5876 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5877 "#"
5878 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
5879 [(pc)]
5880 "
5881 {
5882 rtx lowword, highword;
5883 gcc_assert (MEM_P (operands[4]));
5884 highword = adjust_address (operands[4], SImode, 0);
5885 lowword = adjust_address (operands[4], SImode, 4);
5886 if (! WORDS_BIG_ENDIAN)
5887 {
5888 rtx tmp;
5889 tmp = highword; highword = lowword; lowword = tmp;
5890 }
5891
5892 emit_insn (gen_xorsi3 (operands[6], operands[1],
5893 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5894 emit_move_insn (lowword, operands[6]);
5895 emit_move_insn (highword, operands[2]);
5896 emit_move_insn (operands[5], operands[4]);
5897 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5898 DONE;
5899 }"
5900 [(set_attr "length" "24")])
5901
5902 (define_expand "floatunssisf2"
5903 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5904 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5905 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
5906 "")
5907
5908 (define_expand "floatunssidf2"
5909 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5910 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5911 (use (match_dup 2))
5912 (use (match_dup 3))
5913 (clobber (match_dup 4))
5914 (clobber (match_dup 5))])]
5915 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5916 "
5917 {
5918 if (TARGET_E500_DOUBLE)
5919 {
5920 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5921 DONE;
5922 }
5923 if (TARGET_POWERPC64)
5924 {
5925 rtx x = convert_to_mode (DImode, operands[1], 1);
5926 emit_insn (gen_floatdidf2 (operands[0], x));
5927 DONE;
5928 }
5929
5930 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5931 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5932 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5933 operands[5] = gen_reg_rtx (DFmode);
5934 }")
5935
5936 (define_insn_and_split "*floatunssidf2_internal"
5937 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5938 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5939 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5940 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5941 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5942 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5943 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5944 "#"
5945 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
5946 [(pc)]
5947 "
5948 {
5949 rtx lowword, highword;
5950 gcc_assert (MEM_P (operands[4]));
5951 highword = adjust_address (operands[4], SImode, 0);
5952 lowword = adjust_address (operands[4], SImode, 4);
5953 if (! WORDS_BIG_ENDIAN)
5954 {
5955 rtx tmp;
5956 tmp = highword; highword = lowword; lowword = tmp;
5957 }
5958
5959 emit_move_insn (lowword, operands[1]);
5960 emit_move_insn (highword, operands[2]);
5961 emit_move_insn (operands[5], operands[4]);
5962 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5963 DONE;
5964 }"
5965 [(set_attr "length" "20")])
5966
5967 (define_expand "fix_truncdfsi2"
5968 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
5969 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5970 (clobber (match_dup 2))
5971 (clobber (match_dup 3))])]
5972 "(TARGET_POWER2 || TARGET_POWERPC)
5973 && TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5974 "
5975 {
5976 if (TARGET_E500_DOUBLE)
5977 {
5978 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5979 DONE;
5980 }
5981 operands[2] = gen_reg_rtx (DImode);
5982 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
5983 && gpc_reg_operand(operands[0], GET_MODE (operands[0])))
5984 {
5985 operands[3] = gen_reg_rtx (DImode);
5986 emit_insn (gen_fix_truncdfsi2_mfpgpr (operands[0], operands[1],
5987 operands[2], operands[3]));
5988 DONE;
5989 }
5990 if (TARGET_PPC_GFXOPT)
5991 {
5992 rtx orig_dest = operands[0];
5993 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
5994 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5995 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5996 operands[2]));
5997 if (operands[0] != orig_dest)
5998 emit_move_insn (orig_dest, operands[0]);
5999 DONE;
6000 }
6001 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
6002 }")
6003
6004 (define_insn_and_split "*fix_truncdfsi2_internal"
6005 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6006 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
6007 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
6008 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))]
6009 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6010 && TARGET_DOUBLE_FLOAT"
6011 "#"
6012 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[3]))"
6013 [(pc)]
6014 "
6015 {
6016 rtx lowword;
6017 gcc_assert (MEM_P (operands[3]));
6018 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
6019
6020 emit_insn (gen_fctiwz (operands[2], operands[1]));
6021 emit_move_insn (operands[3], operands[2]);
6022 emit_move_insn (operands[0], lowword);
6023 DONE;
6024 }"
6025 [(set_attr "length" "16")])
6026
6027 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
6028 [(set (match_operand:SI 0 "memory_operand" "=Z")
6029 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
6030 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
6031 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6032 && TARGET_DOUBLE_FLOAT
6033 && TARGET_PPC_GFXOPT"
6034 "#"
6035 "&& 1"
6036 [(pc)]
6037 "
6038 {
6039 emit_insn (gen_fctiwz (operands[2], operands[1]));
6040 emit_insn (gen_stfiwx (operands[0], operands[2]));
6041 DONE;
6042 }"
6043 [(set_attr "length" "16")])
6044
6045 (define_insn_and_split "fix_truncdfsi2_mfpgpr"
6046 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6047 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
6048 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
6049 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
6050 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
6051 && TARGET_DOUBLE_FLOAT"
6052 "#"
6053 "&& 1"
6054 [(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
6055 (set (match_dup 3) (match_dup 2))
6056 (set (match_dup 0) (subreg:SI (match_dup 3) 4))]
6057 ""
6058 [(set_attr "length" "12")])
6059
6060 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6061 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6062 ; because the first makes it clear that operand 0 is not live
6063 ; before the instruction.
6064 (define_insn "fctiwz"
6065 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
6066 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
6067 UNSPEC_FCTIWZ))]
6068 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6069 && TARGET_DOUBLE_FLOAT"
6070 "{fcirz|fctiwz} %0,%1"
6071 [(set_attr "type" "fp")])
6072
6073 (define_insn "btruncdf2"
6074 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6075 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6076 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6077 "friz %0,%1"
6078 [(set_attr "type" "fp")])
6079
6080 (define_insn "btruncsf2"
6081 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6082 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6083 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6084 "friz %0,%1"
6085 [(set_attr "type" "fp")])
6086
6087 (define_insn "ceildf2"
6088 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6089 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6090 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6091 "frip %0,%1"
6092 [(set_attr "type" "fp")])
6093
6094 (define_insn "ceilsf2"
6095 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6096 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6097 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6098 "frip %0,%1"
6099 [(set_attr "type" "fp")])
6100
6101 (define_insn "floordf2"
6102 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6103 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6104 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6105 "frim %0,%1"
6106 [(set_attr "type" "fp")])
6107
6108 (define_insn "floorsf2"
6109 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6110 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6111 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6112 "frim %0,%1"
6113 [(set_attr "type" "fp")])
6114
6115 (define_insn "rounddf2"
6116 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6117 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6118 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6119 "frin %0,%1"
6120 [(set_attr "type" "fp")])
6121
6122 (define_insn "roundsf2"
6123 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6124 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6125 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6126 "frin %0,%1"
6127 [(set_attr "type" "fp")])
6128
6129 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6130 (define_insn "stfiwx"
6131 [(set (match_operand:SI 0 "memory_operand" "=Z")
6132 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
6133 UNSPEC_STFIWX))]
6134 "TARGET_PPC_GFXOPT"
6135 "stfiwx %1,%y0"
6136 [(set_attr "type" "fpstore")])
6137
6138 (define_expand "floatsisf2"
6139 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6140 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6141 "TARGET_HARD_FLOAT && (!TARGET_FPRS || TARGET_SINGLE_FPU)"
6142 "")
6143
6144 (define_insn "floatdidf2"
6145 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6146 (float:DF (match_operand:DI 1 "gpc_reg_operand" "!f#r")))]
6147 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6148 "fcfid %0,%1"
6149 [(set_attr "type" "fp")])
6150
6151 (define_insn "fix_truncdfdi2"
6152 [(set (match_operand:DI 0 "gpc_reg_operand" "=!f#r")
6153 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
6154 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6155 "fctidz %0,%1"
6156 [(set_attr "type" "fp")])
6157
6158 (define_expand "floatdisf2"
6159 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6160 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6161 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6162 "
6163 {
6164 rtx val = operands[1];
6165 if (!flag_unsafe_math_optimizations)
6166 {
6167 rtx label = gen_label_rtx ();
6168 val = gen_reg_rtx (DImode);
6169 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6170 emit_label (label);
6171 }
6172 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6173 DONE;
6174 }")
6175
6176 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6177 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6178 ;; from double rounding.
6179 (define_insn_and_split "floatdisf2_internal1"
6180 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6181 (float:SF (match_operand:DI 1 "gpc_reg_operand" "!f#r")))
6182 (clobber (match_scratch:DF 2 "=f"))]
6183 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6184 "#"
6185 "&& reload_completed"
6186 [(set (match_dup 2)
6187 (float:DF (match_dup 1)))
6188 (set (match_dup 0)
6189 (float_truncate:SF (match_dup 2)))]
6190 "")
6191
6192 ;; Twiddles bits to avoid double rounding.
6193 ;; Bits that might be truncated when converting to DFmode are replaced
6194 ;; by a bit that won't be lost at that stage, but is below the SFmode
6195 ;; rounding position.
6196 (define_expand "floatdisf2_internal2"
6197 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6198 (const_int 53)))
6199 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6200 (const_int 2047)))
6201 (clobber (scratch:CC))])
6202 (set (match_dup 3) (plus:DI (match_dup 3)
6203 (const_int 1)))
6204 (set (match_dup 0) (plus:DI (match_dup 0)
6205 (const_int 2047)))
6206 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6207 (const_int 2)))
6208 (set (match_dup 0) (ior:DI (match_dup 0)
6209 (match_dup 1)))
6210 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6211 (const_int -2048)))
6212 (clobber (scratch:CC))])
6213 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6214 (label_ref (match_operand:DI 2 "" ""))
6215 (pc)))
6216 (set (match_dup 0) (match_dup 1))]
6217 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6218 "
6219 {
6220 operands[3] = gen_reg_rtx (DImode);
6221 operands[4] = gen_reg_rtx (CCUNSmode);
6222 }")
6223 \f
6224 ;; Define the DImode operations that can be done in a small number
6225 ;; of instructions. The & constraints are to prevent the register
6226 ;; allocator from allocating registers that overlap with the inputs
6227 ;; (for example, having an input in 7,8 and an output in 6,7). We
6228 ;; also allow for the output being the same as one of the inputs.
6229
6230 (define_insn "*adddi3_noppc64"
6231 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6232 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6233 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6234 "! TARGET_POWERPC64"
6235 "*
6236 {
6237 if (WORDS_BIG_ENDIAN)
6238 return (GET_CODE (operands[2])) != CONST_INT
6239 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6240 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6241 else
6242 return (GET_CODE (operands[2])) != CONST_INT
6243 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6244 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6245 }"
6246 [(set_attr "type" "two")
6247 (set_attr "length" "8")])
6248
6249 (define_insn "*subdi3_noppc64"
6250 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6251 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6252 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6253 "! TARGET_POWERPC64"
6254 "*
6255 {
6256 if (WORDS_BIG_ENDIAN)
6257 return (GET_CODE (operands[1]) != CONST_INT)
6258 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6259 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6260 else
6261 return (GET_CODE (operands[1]) != CONST_INT)
6262 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6263 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
6264 }"
6265 [(set_attr "type" "two")
6266 (set_attr "length" "8")])
6267
6268 (define_insn "*negdi2_noppc64"
6269 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6270 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6271 "! TARGET_POWERPC64"
6272 "*
6273 {
6274 return (WORDS_BIG_ENDIAN)
6275 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6276 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6277 }"
6278 [(set_attr "type" "two")
6279 (set_attr "length" "8")])
6280
6281 (define_expand "mulsidi3"
6282 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6283 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6284 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6285 "! TARGET_POWERPC64"
6286 "
6287 {
6288 if (! TARGET_POWER && ! TARGET_POWERPC)
6289 {
6290 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6291 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6292 emit_insn (gen_mull_call ());
6293 if (WORDS_BIG_ENDIAN)
6294 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
6295 else
6296 {
6297 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
6298 gen_rtx_REG (SImode, 3));
6299 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
6300 gen_rtx_REG (SImode, 4));
6301 }
6302 DONE;
6303 }
6304 else if (TARGET_POWER)
6305 {
6306 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6307 DONE;
6308 }
6309 }")
6310
6311 (define_insn "mulsidi3_mq"
6312 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6313 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6314 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6315 (clobber (match_scratch:SI 3 "=q"))]
6316 "TARGET_POWER"
6317 "mul %0,%1,%2\;mfmq %L0"
6318 [(set_attr "type" "imul")
6319 (set_attr "length" "8")])
6320
6321 (define_insn "*mulsidi3_no_mq"
6322 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6323 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6324 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6325 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6326 "*
6327 {
6328 return (WORDS_BIG_ENDIAN)
6329 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6330 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6331 }"
6332 [(set_attr "type" "imul")
6333 (set_attr "length" "8")])
6334
6335 (define_split
6336 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6337 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6338 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6339 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6340 [(set (match_dup 3)
6341 (truncate:SI
6342 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6343 (sign_extend:DI (match_dup 2)))
6344 (const_int 32))))
6345 (set (match_dup 4)
6346 (mult:SI (match_dup 1)
6347 (match_dup 2)))]
6348 "
6349 {
6350 int endian = (WORDS_BIG_ENDIAN == 0);
6351 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6352 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6353 }")
6354
6355 (define_expand "umulsidi3"
6356 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6357 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6358 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6359 "TARGET_POWERPC && ! TARGET_POWERPC64"
6360 "
6361 {
6362 if (TARGET_POWER)
6363 {
6364 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6365 DONE;
6366 }
6367 }")
6368
6369 (define_insn "umulsidi3_mq"
6370 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6371 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6372 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6373 (clobber (match_scratch:SI 3 "=q"))]
6374 "TARGET_POWERPC && TARGET_POWER"
6375 "*
6376 {
6377 return (WORDS_BIG_ENDIAN)
6378 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6379 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6380 }"
6381 [(set_attr "type" "imul")
6382 (set_attr "length" "8")])
6383
6384 (define_insn "*umulsidi3_no_mq"
6385 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6386 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6387 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6388 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6389 "*
6390 {
6391 return (WORDS_BIG_ENDIAN)
6392 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6393 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6394 }"
6395 [(set_attr "type" "imul")
6396 (set_attr "length" "8")])
6397
6398 (define_split
6399 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6400 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6401 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6402 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6403 [(set (match_dup 3)
6404 (truncate:SI
6405 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6406 (zero_extend:DI (match_dup 2)))
6407 (const_int 32))))
6408 (set (match_dup 4)
6409 (mult:SI (match_dup 1)
6410 (match_dup 2)))]
6411 "
6412 {
6413 int endian = (WORDS_BIG_ENDIAN == 0);
6414 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6415 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6416 }")
6417
6418 (define_expand "smulsi3_highpart"
6419 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6420 (truncate:SI
6421 (lshiftrt:DI (mult:DI (sign_extend:DI
6422 (match_operand:SI 1 "gpc_reg_operand" ""))
6423 (sign_extend:DI
6424 (match_operand:SI 2 "gpc_reg_operand" "")))
6425 (const_int 32))))]
6426 ""
6427 "
6428 {
6429 if (! TARGET_POWER && ! TARGET_POWERPC)
6430 {
6431 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6432 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6433 emit_insn (gen_mulh_call ());
6434 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
6435 DONE;
6436 }
6437 else if (TARGET_POWER)
6438 {
6439 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6440 DONE;
6441 }
6442 }")
6443
6444 (define_insn "smulsi3_highpart_mq"
6445 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6446 (truncate:SI
6447 (lshiftrt:DI (mult:DI (sign_extend:DI
6448 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6449 (sign_extend:DI
6450 (match_operand:SI 2 "gpc_reg_operand" "r")))
6451 (const_int 32))))
6452 (clobber (match_scratch:SI 3 "=q"))]
6453 "TARGET_POWER"
6454 "mul %0,%1,%2"
6455 [(set_attr "type" "imul")])
6456
6457 (define_insn "*smulsi3_highpart_no_mq"
6458 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6459 (truncate:SI
6460 (lshiftrt:DI (mult:DI (sign_extend:DI
6461 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6462 (sign_extend:DI
6463 (match_operand:SI 2 "gpc_reg_operand" "r")))
6464 (const_int 32))))]
6465 "TARGET_POWERPC && ! TARGET_POWER"
6466 "mulhw %0,%1,%2"
6467 [(set_attr "type" "imul")])
6468
6469 (define_expand "umulsi3_highpart"
6470 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6471 (truncate:SI
6472 (lshiftrt:DI (mult:DI (zero_extend:DI
6473 (match_operand:SI 1 "gpc_reg_operand" ""))
6474 (zero_extend:DI
6475 (match_operand:SI 2 "gpc_reg_operand" "")))
6476 (const_int 32))))]
6477 "TARGET_POWERPC"
6478 "
6479 {
6480 if (TARGET_POWER)
6481 {
6482 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6483 DONE;
6484 }
6485 }")
6486
6487 (define_insn "umulsi3_highpart_mq"
6488 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6489 (truncate:SI
6490 (lshiftrt:DI (mult:DI (zero_extend:DI
6491 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6492 (zero_extend:DI
6493 (match_operand:SI 2 "gpc_reg_operand" "r")))
6494 (const_int 32))))
6495 (clobber (match_scratch:SI 3 "=q"))]
6496 "TARGET_POWERPC && TARGET_POWER"
6497 "mulhwu %0,%1,%2"
6498 [(set_attr "type" "imul")])
6499
6500 (define_insn "*umulsi3_highpart_no_mq"
6501 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6502 (truncate:SI
6503 (lshiftrt:DI (mult:DI (zero_extend:DI
6504 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6505 (zero_extend:DI
6506 (match_operand:SI 2 "gpc_reg_operand" "r")))
6507 (const_int 32))))]
6508 "TARGET_POWERPC && ! TARGET_POWER"
6509 "mulhwu %0,%1,%2"
6510 [(set_attr "type" "imul")])
6511
6512 ;; If operands 0 and 2 are in the same register, we have a problem. But
6513 ;; operands 0 and 1 (the usual case) can be in the same register. That's
6514 ;; why we have the strange constraints below.
6515 (define_insn "ashldi3_power"
6516 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6517 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6518 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6519 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6520 "TARGET_POWER"
6521 "@
6522 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
6523 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6524 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6525 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
6526 [(set_attr "length" "8")])
6527
6528 (define_insn "lshrdi3_power"
6529 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6530 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6531 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6532 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6533 "TARGET_POWER"
6534 "@
6535 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
6536 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6537 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6538 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
6539 [(set_attr "length" "8")])
6540
6541 ;; Shift by a variable amount is too complex to be worth open-coding. We
6542 ;; just handle shifts by constants.
6543 (define_insn "ashrdi3_power"
6544 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6545 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6546 (match_operand:SI 2 "const_int_operand" "M,i")))
6547 (clobber (match_scratch:SI 3 "=X,q"))]
6548 "TARGET_POWER"
6549 "@
6550 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6551 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
6552 [(set_attr "type" "shift")
6553 (set_attr "length" "8")])
6554
6555 (define_insn "ashrdi3_no_power"
6556 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6557 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6558 (match_operand:SI 2 "const_int_operand" "M,i")))]
6559 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
6560 "@
6561 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6562 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
6563 [(set_attr "type" "two,three")
6564 (set_attr "length" "8,12")])
6565
6566 (define_insn "*ashrdisi3_noppc64"
6567 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6568 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6569 (const_int 32)) 4))]
6570 "TARGET_32BIT && !TARGET_POWERPC64"
6571 "*
6572 {
6573 if (REGNO (operands[0]) == REGNO (operands[1]))
6574 return \"\";
6575 else
6576 return \"mr %0,%1\";
6577 }"
6578 [(set_attr "length" "4")])
6579
6580 \f
6581 ;; PowerPC64 DImode operations.
6582
6583 (define_insn_and_split "absdi2"
6584 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6585 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6586 (clobber (match_scratch:DI 2 "=&r,&r"))]
6587 "TARGET_POWERPC64"
6588 "#"
6589 "&& reload_completed"
6590 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6591 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6592 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6593 "")
6594
6595 (define_insn_and_split "*nabsdi2"
6596 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6597 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6598 (clobber (match_scratch:DI 2 "=&r,&r"))]
6599 "TARGET_POWERPC64"
6600 "#"
6601 "&& reload_completed"
6602 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6603 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6604 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
6605 "")
6606
6607 (define_insn "muldi3"
6608 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6609 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6610 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6611 "TARGET_POWERPC64"
6612 "@
6613 mulld %0,%1,%2
6614 mulli %0,%1,%2"
6615 [(set (attr "type")
6616 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6617 (const_string "imul3")
6618 (match_operand:SI 2 "short_cint_operand" "")
6619 (const_string "imul2")]
6620 (const_string "lmul")))])
6621
6622 (define_insn "*muldi3_internal1"
6623 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6624 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6625 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6626 (const_int 0)))
6627 (clobber (match_scratch:DI 3 "=r,r"))]
6628 "TARGET_POWERPC64"
6629 "@
6630 mulld. %3,%1,%2
6631 #"
6632 [(set_attr "type" "lmul_compare")
6633 (set_attr "length" "4,8")])
6634
6635 (define_split
6636 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6637 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6638 (match_operand:DI 2 "gpc_reg_operand" ""))
6639 (const_int 0)))
6640 (clobber (match_scratch:DI 3 ""))]
6641 "TARGET_POWERPC64 && reload_completed"
6642 [(set (match_dup 3)
6643 (mult:DI (match_dup 1) (match_dup 2)))
6644 (set (match_dup 0)
6645 (compare:CC (match_dup 3)
6646 (const_int 0)))]
6647 "")
6648
6649 (define_insn "*muldi3_internal2"
6650 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6651 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6652 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6653 (const_int 0)))
6654 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6655 (mult:DI (match_dup 1) (match_dup 2)))]
6656 "TARGET_POWERPC64"
6657 "@
6658 mulld. %0,%1,%2
6659 #"
6660 [(set_attr "type" "lmul_compare")
6661 (set_attr "length" "4,8")])
6662
6663 (define_split
6664 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6665 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6666 (match_operand:DI 2 "gpc_reg_operand" ""))
6667 (const_int 0)))
6668 (set (match_operand:DI 0 "gpc_reg_operand" "")
6669 (mult:DI (match_dup 1) (match_dup 2)))]
6670 "TARGET_POWERPC64 && reload_completed"
6671 [(set (match_dup 0)
6672 (mult:DI (match_dup 1) (match_dup 2)))
6673 (set (match_dup 3)
6674 (compare:CC (match_dup 0)
6675 (const_int 0)))]
6676 "")
6677
6678 (define_insn "smuldi3_highpart"
6679 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6680 (truncate:DI
6681 (lshiftrt:TI (mult:TI (sign_extend:TI
6682 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6683 (sign_extend:TI
6684 (match_operand:DI 2 "gpc_reg_operand" "r")))
6685 (const_int 64))))]
6686 "TARGET_POWERPC64"
6687 "mulhd %0,%1,%2"
6688 [(set_attr "type" "lmul")])
6689
6690 (define_insn "umuldi3_highpart"
6691 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6692 (truncate:DI
6693 (lshiftrt:TI (mult:TI (zero_extend:TI
6694 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6695 (zero_extend:TI
6696 (match_operand:DI 2 "gpc_reg_operand" "r")))
6697 (const_int 64))))]
6698 "TARGET_POWERPC64"
6699 "mulhdu %0,%1,%2"
6700 [(set_attr "type" "lmul")])
6701
6702 (define_insn "rotldi3"
6703 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6704 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6705 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
6706 "TARGET_POWERPC64"
6707 "@
6708 rldcl %0,%1,%2,0
6709 rldicl %0,%1,%H2,0"
6710 [(set_attr "type" "var_shift_rotate,integer")])
6711
6712 (define_insn "*rotldi3_internal2"
6713 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6714 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6715 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6716 (const_int 0)))
6717 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6718 "TARGET_64BIT"
6719 "@
6720 rldcl. %3,%1,%2,0
6721 rldicl. %3,%1,%H2,0
6722 #
6723 #"
6724 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6725 (set_attr "length" "4,4,8,8")])
6726
6727 (define_split
6728 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6729 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6730 (match_operand:DI 2 "reg_or_cint_operand" ""))
6731 (const_int 0)))
6732 (clobber (match_scratch:DI 3 ""))]
6733 "TARGET_POWERPC64 && reload_completed"
6734 [(set (match_dup 3)
6735 (rotate:DI (match_dup 1) (match_dup 2)))
6736 (set (match_dup 0)
6737 (compare:CC (match_dup 3)
6738 (const_int 0)))]
6739 "")
6740
6741 (define_insn "*rotldi3_internal3"
6742 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6743 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6744 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6745 (const_int 0)))
6746 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6747 (rotate:DI (match_dup 1) (match_dup 2)))]
6748 "TARGET_64BIT"
6749 "@
6750 rldcl. %0,%1,%2,0
6751 rldicl. %0,%1,%H2,0
6752 #
6753 #"
6754 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6755 (set_attr "length" "4,4,8,8")])
6756
6757 (define_split
6758 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6759 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6760 (match_operand:DI 2 "reg_or_cint_operand" ""))
6761 (const_int 0)))
6762 (set (match_operand:DI 0 "gpc_reg_operand" "")
6763 (rotate:DI (match_dup 1) (match_dup 2)))]
6764 "TARGET_POWERPC64 && reload_completed"
6765 [(set (match_dup 0)
6766 (rotate:DI (match_dup 1) (match_dup 2)))
6767 (set (match_dup 3)
6768 (compare:CC (match_dup 0)
6769 (const_int 0)))]
6770 "")
6771
6772 (define_insn "*rotldi3_internal4"
6773 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6774 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6775 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6776 (match_operand:DI 3 "mask64_operand" "n,n")))]
6777 "TARGET_POWERPC64"
6778 "@
6779 rldc%B3 %0,%1,%2,%S3
6780 rldic%B3 %0,%1,%H2,%S3"
6781 [(set_attr "type" "var_shift_rotate,integer")])
6782
6783 (define_insn "*rotldi3_internal5"
6784 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6785 (compare:CC (and:DI
6786 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6787 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6788 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6789 (const_int 0)))
6790 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
6791 "TARGET_64BIT"
6792 "@
6793 rldc%B3. %4,%1,%2,%S3
6794 rldic%B3. %4,%1,%H2,%S3
6795 #
6796 #"
6797 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6798 (set_attr "length" "4,4,8,8")])
6799
6800 (define_split
6801 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6802 (compare:CC (and:DI
6803 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6804 (match_operand:DI 2 "reg_or_cint_operand" ""))
6805 (match_operand:DI 3 "mask64_operand" ""))
6806 (const_int 0)))
6807 (clobber (match_scratch:DI 4 ""))]
6808 "TARGET_POWERPC64 && reload_completed"
6809 [(set (match_dup 4)
6810 (and:DI (rotate:DI (match_dup 1)
6811 (match_dup 2))
6812 (match_dup 3)))
6813 (set (match_dup 0)
6814 (compare:CC (match_dup 4)
6815 (const_int 0)))]
6816 "")
6817
6818 (define_insn "*rotldi3_internal6"
6819 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
6820 (compare:CC (and:DI
6821 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6822 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6823 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6824 (const_int 0)))
6825 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6826 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6827 "TARGET_64BIT"
6828 "@
6829 rldc%B3. %0,%1,%2,%S3
6830 rldic%B3. %0,%1,%H2,%S3
6831 #
6832 #"
6833 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6834 (set_attr "length" "4,4,8,8")])
6835
6836 (define_split
6837 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6838 (compare:CC (and:DI
6839 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6840 (match_operand:DI 2 "reg_or_cint_operand" ""))
6841 (match_operand:DI 3 "mask64_operand" ""))
6842 (const_int 0)))
6843 (set (match_operand:DI 0 "gpc_reg_operand" "")
6844 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6845 "TARGET_POWERPC64 && reload_completed"
6846 [(set (match_dup 0)
6847 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6848 (set (match_dup 4)
6849 (compare:CC (match_dup 0)
6850 (const_int 0)))]
6851 "")
6852
6853 (define_insn "*rotldi3_internal7"
6854 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6855 (zero_extend:DI
6856 (subreg:QI
6857 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6858 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6859 "TARGET_POWERPC64"
6860 "@
6861 rldcl %0,%1,%2,56
6862 rldicl %0,%1,%H2,56"
6863 [(set_attr "type" "var_shift_rotate,integer")])
6864
6865 (define_insn "*rotldi3_internal8"
6866 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6867 (compare:CC (zero_extend:DI
6868 (subreg:QI
6869 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6870 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6871 (const_int 0)))
6872 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6873 "TARGET_64BIT"
6874 "@
6875 rldcl. %3,%1,%2,56
6876 rldicl. %3,%1,%H2,56
6877 #
6878 #"
6879 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6880 (set_attr "length" "4,4,8,8")])
6881
6882 (define_split
6883 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6884 (compare:CC (zero_extend:DI
6885 (subreg:QI
6886 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6887 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6888 (const_int 0)))
6889 (clobber (match_scratch:DI 3 ""))]
6890 "TARGET_POWERPC64 && reload_completed"
6891 [(set (match_dup 3)
6892 (zero_extend:DI (subreg:QI
6893 (rotate:DI (match_dup 1)
6894 (match_dup 2)) 0)))
6895 (set (match_dup 0)
6896 (compare:CC (match_dup 3)
6897 (const_int 0)))]
6898 "")
6899
6900 (define_insn "*rotldi3_internal9"
6901 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6902 (compare:CC (zero_extend:DI
6903 (subreg:QI
6904 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6905 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6906 (const_int 0)))
6907 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6908 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6909 "TARGET_64BIT"
6910 "@
6911 rldcl. %0,%1,%2,56
6912 rldicl. %0,%1,%H2,56
6913 #
6914 #"
6915 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6916 (set_attr "length" "4,4,8,8")])
6917
6918 (define_split
6919 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6920 (compare:CC (zero_extend:DI
6921 (subreg:QI
6922 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6923 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6924 (const_int 0)))
6925 (set (match_operand:DI 0 "gpc_reg_operand" "")
6926 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6927 "TARGET_POWERPC64 && reload_completed"
6928 [(set (match_dup 0)
6929 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6930 (set (match_dup 3)
6931 (compare:CC (match_dup 0)
6932 (const_int 0)))]
6933 "")
6934
6935 (define_insn "*rotldi3_internal10"
6936 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6937 (zero_extend:DI
6938 (subreg:HI
6939 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6940 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6941 "TARGET_POWERPC64"
6942 "@
6943 rldcl %0,%1,%2,48
6944 rldicl %0,%1,%H2,48"
6945 [(set_attr "type" "var_shift_rotate,integer")])
6946
6947 (define_insn "*rotldi3_internal11"
6948 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6949 (compare:CC (zero_extend:DI
6950 (subreg:HI
6951 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6952 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6953 (const_int 0)))
6954 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6955 "TARGET_64BIT"
6956 "@
6957 rldcl. %3,%1,%2,48
6958 rldicl. %3,%1,%H2,48
6959 #
6960 #"
6961 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6962 (set_attr "length" "4,4,8,8")])
6963
6964 (define_split
6965 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6966 (compare:CC (zero_extend:DI
6967 (subreg:HI
6968 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6969 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6970 (const_int 0)))
6971 (clobber (match_scratch:DI 3 ""))]
6972 "TARGET_POWERPC64 && reload_completed"
6973 [(set (match_dup 3)
6974 (zero_extend:DI (subreg:HI
6975 (rotate:DI (match_dup 1)
6976 (match_dup 2)) 0)))
6977 (set (match_dup 0)
6978 (compare:CC (match_dup 3)
6979 (const_int 0)))]
6980 "")
6981
6982 (define_insn "*rotldi3_internal12"
6983 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6984 (compare:CC (zero_extend:DI
6985 (subreg:HI
6986 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6987 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6988 (const_int 0)))
6989 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6990 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6991 "TARGET_64BIT"
6992 "@
6993 rldcl. %0,%1,%2,48
6994 rldicl. %0,%1,%H2,48
6995 #
6996 #"
6997 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6998 (set_attr "length" "4,4,8,8")])
6999
7000 (define_split
7001 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7002 (compare:CC (zero_extend:DI
7003 (subreg:HI
7004 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7005 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7006 (const_int 0)))
7007 (set (match_operand:DI 0 "gpc_reg_operand" "")
7008 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7009 "TARGET_POWERPC64 && reload_completed"
7010 [(set (match_dup 0)
7011 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7012 (set (match_dup 3)
7013 (compare:CC (match_dup 0)
7014 (const_int 0)))]
7015 "")
7016
7017 (define_insn "*rotldi3_internal13"
7018 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7019 (zero_extend:DI
7020 (subreg:SI
7021 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7022 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7023 "TARGET_POWERPC64"
7024 "@
7025 rldcl %0,%1,%2,32
7026 rldicl %0,%1,%H2,32"
7027 [(set_attr "type" "var_shift_rotate,integer")])
7028
7029 (define_insn "*rotldi3_internal14"
7030 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7031 (compare:CC (zero_extend:DI
7032 (subreg:SI
7033 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7034 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7035 (const_int 0)))
7036 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7037 "TARGET_64BIT"
7038 "@
7039 rldcl. %3,%1,%2,32
7040 rldicl. %3,%1,%H2,32
7041 #
7042 #"
7043 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7044 (set_attr "length" "4,4,8,8")])
7045
7046 (define_split
7047 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7048 (compare:CC (zero_extend:DI
7049 (subreg:SI
7050 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7051 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7052 (const_int 0)))
7053 (clobber (match_scratch:DI 3 ""))]
7054 "TARGET_POWERPC64 && reload_completed"
7055 [(set (match_dup 3)
7056 (zero_extend:DI (subreg:SI
7057 (rotate:DI (match_dup 1)
7058 (match_dup 2)) 0)))
7059 (set (match_dup 0)
7060 (compare:CC (match_dup 3)
7061 (const_int 0)))]
7062 "")
7063
7064 (define_insn "*rotldi3_internal15"
7065 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7066 (compare:CC (zero_extend:DI
7067 (subreg:SI
7068 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7069 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7070 (const_int 0)))
7071 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7072 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7073 "TARGET_64BIT"
7074 "@
7075 rldcl. %0,%1,%2,32
7076 rldicl. %0,%1,%H2,32
7077 #
7078 #"
7079 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7080 (set_attr "length" "4,4,8,8")])
7081
7082 (define_split
7083 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7084 (compare:CC (zero_extend:DI
7085 (subreg:SI
7086 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7087 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7088 (const_int 0)))
7089 (set (match_operand:DI 0 "gpc_reg_operand" "")
7090 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7091 "TARGET_POWERPC64 && reload_completed"
7092 [(set (match_dup 0)
7093 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7094 (set (match_dup 3)
7095 (compare:CC (match_dup 0)
7096 (const_int 0)))]
7097 "")
7098
7099 (define_expand "ashldi3"
7100 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7101 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7102 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7103 "TARGET_POWERPC64 || TARGET_POWER"
7104 "
7105 {
7106 if (TARGET_POWERPC64)
7107 ;
7108 else if (TARGET_POWER)
7109 {
7110 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
7111 DONE;
7112 }
7113 else
7114 FAIL;
7115 }")
7116
7117 (define_insn "*ashldi3_internal1"
7118 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7119 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7120 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7121 "TARGET_POWERPC64"
7122 "@
7123 sld %0,%1,%2
7124 sldi %0,%1,%H2"
7125 [(set_attr "type" "var_shift_rotate,shift")])
7126
7127 (define_insn "*ashldi3_internal2"
7128 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7129 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7130 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7131 (const_int 0)))
7132 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7133 "TARGET_64BIT"
7134 "@
7135 sld. %3,%1,%2
7136 sldi. %3,%1,%H2
7137 #
7138 #"
7139 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7140 (set_attr "length" "4,4,8,8")])
7141
7142 (define_split
7143 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7144 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7145 (match_operand:SI 2 "reg_or_cint_operand" ""))
7146 (const_int 0)))
7147 (clobber (match_scratch:DI 3 ""))]
7148 "TARGET_POWERPC64 && reload_completed"
7149 [(set (match_dup 3)
7150 (ashift:DI (match_dup 1) (match_dup 2)))
7151 (set (match_dup 0)
7152 (compare:CC (match_dup 3)
7153 (const_int 0)))]
7154 "")
7155
7156 (define_insn "*ashldi3_internal3"
7157 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7158 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7159 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7160 (const_int 0)))
7161 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7162 (ashift:DI (match_dup 1) (match_dup 2)))]
7163 "TARGET_64BIT"
7164 "@
7165 sld. %0,%1,%2
7166 sldi. %0,%1,%H2
7167 #
7168 #"
7169 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7170 (set_attr "length" "4,4,8,8")])
7171
7172 (define_split
7173 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7174 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7175 (match_operand:SI 2 "reg_or_cint_operand" ""))
7176 (const_int 0)))
7177 (set (match_operand:DI 0 "gpc_reg_operand" "")
7178 (ashift:DI (match_dup 1) (match_dup 2)))]
7179 "TARGET_POWERPC64 && reload_completed"
7180 [(set (match_dup 0)
7181 (ashift:DI (match_dup 1) (match_dup 2)))
7182 (set (match_dup 3)
7183 (compare:CC (match_dup 0)
7184 (const_int 0)))]
7185 "")
7186
7187 (define_insn "*ashldi3_internal4"
7188 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7189 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7190 (match_operand:SI 2 "const_int_operand" "i"))
7191 (match_operand:DI 3 "const_int_operand" "n")))]
7192 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7193 "rldic %0,%1,%H2,%W3")
7194
7195 (define_insn "ashldi3_internal5"
7196 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7197 (compare:CC
7198 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7199 (match_operand:SI 2 "const_int_operand" "i,i"))
7200 (match_operand:DI 3 "const_int_operand" "n,n"))
7201 (const_int 0)))
7202 (clobber (match_scratch:DI 4 "=r,r"))]
7203 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7204 "@
7205 rldic. %4,%1,%H2,%W3
7206 #"
7207 [(set_attr "type" "compare")
7208 (set_attr "length" "4,8")])
7209
7210 (define_split
7211 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7212 (compare:CC
7213 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7214 (match_operand:SI 2 "const_int_operand" ""))
7215 (match_operand:DI 3 "const_int_operand" ""))
7216 (const_int 0)))
7217 (clobber (match_scratch:DI 4 ""))]
7218 "TARGET_POWERPC64 && reload_completed
7219 && includes_rldic_lshift_p (operands[2], operands[3])"
7220 [(set (match_dup 4)
7221 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7222 (match_dup 3)))
7223 (set (match_dup 0)
7224 (compare:CC (match_dup 4)
7225 (const_int 0)))]
7226 "")
7227
7228 (define_insn "*ashldi3_internal6"
7229 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7230 (compare:CC
7231 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7232 (match_operand:SI 2 "const_int_operand" "i,i"))
7233 (match_operand:DI 3 "const_int_operand" "n,n"))
7234 (const_int 0)))
7235 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7236 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7237 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7238 "@
7239 rldic. %0,%1,%H2,%W3
7240 #"
7241 [(set_attr "type" "compare")
7242 (set_attr "length" "4,8")])
7243
7244 (define_split
7245 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7246 (compare:CC
7247 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7248 (match_operand:SI 2 "const_int_operand" ""))
7249 (match_operand:DI 3 "const_int_operand" ""))
7250 (const_int 0)))
7251 (set (match_operand:DI 0 "gpc_reg_operand" "")
7252 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7253 "TARGET_POWERPC64 && reload_completed
7254 && includes_rldic_lshift_p (operands[2], operands[3])"
7255 [(set (match_dup 0)
7256 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7257 (match_dup 3)))
7258 (set (match_dup 4)
7259 (compare:CC (match_dup 0)
7260 (const_int 0)))]
7261 "")
7262
7263 (define_insn "*ashldi3_internal7"
7264 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7265 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7266 (match_operand:SI 2 "const_int_operand" "i"))
7267 (match_operand:DI 3 "mask64_operand" "n")))]
7268 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7269 "rldicr %0,%1,%H2,%S3")
7270
7271 (define_insn "ashldi3_internal8"
7272 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7273 (compare:CC
7274 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7275 (match_operand:SI 2 "const_int_operand" "i,i"))
7276 (match_operand:DI 3 "mask64_operand" "n,n"))
7277 (const_int 0)))
7278 (clobber (match_scratch:DI 4 "=r,r"))]
7279 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7280 "@
7281 rldicr. %4,%1,%H2,%S3
7282 #"
7283 [(set_attr "type" "compare")
7284 (set_attr "length" "4,8")])
7285
7286 (define_split
7287 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7288 (compare:CC
7289 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7290 (match_operand:SI 2 "const_int_operand" ""))
7291 (match_operand:DI 3 "mask64_operand" ""))
7292 (const_int 0)))
7293 (clobber (match_scratch:DI 4 ""))]
7294 "TARGET_POWERPC64 && reload_completed
7295 && includes_rldicr_lshift_p (operands[2], operands[3])"
7296 [(set (match_dup 4)
7297 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7298 (match_dup 3)))
7299 (set (match_dup 0)
7300 (compare:CC (match_dup 4)
7301 (const_int 0)))]
7302 "")
7303
7304 (define_insn "*ashldi3_internal9"
7305 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7306 (compare:CC
7307 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7308 (match_operand:SI 2 "const_int_operand" "i,i"))
7309 (match_operand:DI 3 "mask64_operand" "n,n"))
7310 (const_int 0)))
7311 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7312 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7313 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7314 "@
7315 rldicr. %0,%1,%H2,%S3
7316 #"
7317 [(set_attr "type" "compare")
7318 (set_attr "length" "4,8")])
7319
7320 (define_split
7321 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7322 (compare:CC
7323 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7324 (match_operand:SI 2 "const_int_operand" ""))
7325 (match_operand:DI 3 "mask64_operand" ""))
7326 (const_int 0)))
7327 (set (match_operand:DI 0 "gpc_reg_operand" "")
7328 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7329 "TARGET_POWERPC64 && reload_completed
7330 && includes_rldicr_lshift_p (operands[2], operands[3])"
7331 [(set (match_dup 0)
7332 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7333 (match_dup 3)))
7334 (set (match_dup 4)
7335 (compare:CC (match_dup 0)
7336 (const_int 0)))]
7337 "")
7338
7339 (define_expand "lshrdi3"
7340 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7341 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7342 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7343 "TARGET_POWERPC64 || TARGET_POWER"
7344 "
7345 {
7346 if (TARGET_POWERPC64)
7347 ;
7348 else if (TARGET_POWER)
7349 {
7350 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7351 DONE;
7352 }
7353 else
7354 FAIL;
7355 }")
7356
7357 (define_insn "*lshrdi3_internal1"
7358 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7359 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7360 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7361 "TARGET_POWERPC64"
7362 "@
7363 srd %0,%1,%2
7364 srdi %0,%1,%H2"
7365 [(set_attr "type" "var_shift_rotate,shift")])
7366
7367 (define_insn "*lshrdi3_internal2"
7368 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7369 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7370 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7371 (const_int 0)))
7372 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7373 "TARGET_64BIT "
7374 "@
7375 srd. %3,%1,%2
7376 srdi. %3,%1,%H2
7377 #
7378 #"
7379 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7380 (set_attr "length" "4,4,8,8")])
7381
7382 (define_split
7383 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7384 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7385 (match_operand:SI 2 "reg_or_cint_operand" ""))
7386 (const_int 0)))
7387 (clobber (match_scratch:DI 3 ""))]
7388 "TARGET_POWERPC64 && reload_completed"
7389 [(set (match_dup 3)
7390 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7391 (set (match_dup 0)
7392 (compare:CC (match_dup 3)
7393 (const_int 0)))]
7394 "")
7395
7396 (define_insn "*lshrdi3_internal3"
7397 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7398 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7399 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7400 (const_int 0)))
7401 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7402 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7403 "TARGET_64BIT"
7404 "@
7405 srd. %0,%1,%2
7406 srdi. %0,%1,%H2
7407 #
7408 #"
7409 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7410 (set_attr "length" "4,4,8,8")])
7411
7412 (define_split
7413 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7414 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7415 (match_operand:SI 2 "reg_or_cint_operand" ""))
7416 (const_int 0)))
7417 (set (match_operand:DI 0 "gpc_reg_operand" "")
7418 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7419 "TARGET_POWERPC64 && reload_completed"
7420 [(set (match_dup 0)
7421 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7422 (set (match_dup 3)
7423 (compare:CC (match_dup 0)
7424 (const_int 0)))]
7425 "")
7426
7427 (define_expand "ashrdi3"
7428 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7429 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7430 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7431 "WORDS_BIG_ENDIAN"
7432 "
7433 {
7434 if (TARGET_POWERPC64)
7435 ;
7436 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7437 {
7438 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7439 DONE;
7440 }
7441 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7442 && WORDS_BIG_ENDIAN)
7443 {
7444 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7445 DONE;
7446 }
7447 else
7448 FAIL;
7449 }")
7450
7451 (define_insn "*ashrdi3_internal1"
7452 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7453 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7454 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7455 "TARGET_POWERPC64"
7456 "@
7457 srad %0,%1,%2
7458 sradi %0,%1,%H2"
7459 [(set_attr "type" "var_shift_rotate,shift")])
7460
7461 (define_insn "*ashrdi3_internal2"
7462 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7463 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7464 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7465 (const_int 0)))
7466 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7467 "TARGET_64BIT"
7468 "@
7469 srad. %3,%1,%2
7470 sradi. %3,%1,%H2
7471 #
7472 #"
7473 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7474 (set_attr "length" "4,4,8,8")])
7475
7476 (define_split
7477 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7478 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7479 (match_operand:SI 2 "reg_or_cint_operand" ""))
7480 (const_int 0)))
7481 (clobber (match_scratch:DI 3 ""))]
7482 "TARGET_POWERPC64 && reload_completed"
7483 [(set (match_dup 3)
7484 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7485 (set (match_dup 0)
7486 (compare:CC (match_dup 3)
7487 (const_int 0)))]
7488 "")
7489
7490 (define_insn "*ashrdi3_internal3"
7491 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7492 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7493 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7494 (const_int 0)))
7495 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7496 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7497 "TARGET_64BIT"
7498 "@
7499 srad. %0,%1,%2
7500 sradi. %0,%1,%H2
7501 #
7502 #"
7503 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7504 (set_attr "length" "4,4,8,8")])
7505
7506 (define_split
7507 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7508 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7509 (match_operand:SI 2 "reg_or_cint_operand" ""))
7510 (const_int 0)))
7511 (set (match_operand:DI 0 "gpc_reg_operand" "")
7512 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7513 "TARGET_POWERPC64 && reload_completed"
7514 [(set (match_dup 0)
7515 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7516 (set (match_dup 3)
7517 (compare:CC (match_dup 0)
7518 (const_int 0)))]
7519 "")
7520
7521 (define_insn "anddi3"
7522 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7523 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7524 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7525 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7526 "TARGET_POWERPC64"
7527 "@
7528 and %0,%1,%2
7529 rldic%B2 %0,%1,0,%S2
7530 rlwinm %0,%1,0,%m2,%M2
7531 andi. %0,%1,%b2
7532 andis. %0,%1,%u2
7533 #"
7534 [(set_attr "type" "*,*,*,compare,compare,*")
7535 (set_attr "length" "4,4,4,4,4,8")])
7536
7537 (define_split
7538 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7539 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7540 (match_operand:DI 2 "mask64_2_operand" "")))
7541 (clobber (match_scratch:CC 3 ""))]
7542 "TARGET_POWERPC64
7543 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7544 && !mask_operand (operands[2], DImode)
7545 && !mask64_operand (operands[2], DImode)"
7546 [(set (match_dup 0)
7547 (and:DI (rotate:DI (match_dup 1)
7548 (match_dup 4))
7549 (match_dup 5)))
7550 (set (match_dup 0)
7551 (and:DI (rotate:DI (match_dup 0)
7552 (match_dup 6))
7553 (match_dup 7)))]
7554 {
7555 build_mask64_2_operands (operands[2], &operands[4]);
7556 })
7557
7558 (define_insn "*anddi3_internal2"
7559 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7560 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7561 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7562 (const_int 0)))
7563 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7564 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7565 "TARGET_64BIT"
7566 "@
7567 and. %3,%1,%2
7568 rldic%B2. %3,%1,0,%S2
7569 rlwinm. %3,%1,0,%m2,%M2
7570 andi. %3,%1,%b2
7571 andis. %3,%1,%u2
7572 #
7573 #
7574 #
7575 #
7576 #
7577 #
7578 #"
7579 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7580 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7581
7582 (define_split
7583 [(set (match_operand:CC 0 "cc_reg_operand" "")
7584 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7585 (match_operand:DI 2 "mask64_2_operand" ""))
7586 (const_int 0)))
7587 (clobber (match_scratch:DI 3 ""))
7588 (clobber (match_scratch:CC 4 ""))]
7589 "TARGET_64BIT && reload_completed
7590 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7591 && !mask_operand (operands[2], DImode)
7592 && !mask64_operand (operands[2], DImode)"
7593 [(set (match_dup 3)
7594 (and:DI (rotate:DI (match_dup 1)
7595 (match_dup 5))
7596 (match_dup 6)))
7597 (parallel [(set (match_dup 0)
7598 (compare:CC (and:DI (rotate:DI (match_dup 3)
7599 (match_dup 7))
7600 (match_dup 8))
7601 (const_int 0)))
7602 (clobber (match_dup 3))])]
7603 "
7604 {
7605 build_mask64_2_operands (operands[2], &operands[5]);
7606 }")
7607
7608 (define_insn "*anddi3_internal3"
7609 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7610 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7611 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7612 (const_int 0)))
7613 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
7614 (and:DI (match_dup 1) (match_dup 2)))
7615 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7616 "TARGET_64BIT"
7617 "@
7618 and. %0,%1,%2
7619 rldic%B2. %0,%1,0,%S2
7620 rlwinm. %0,%1,0,%m2,%M2
7621 andi. %0,%1,%b2
7622 andis. %0,%1,%u2
7623 #
7624 #
7625 #
7626 #
7627 #
7628 #
7629 #"
7630 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7631 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7632
7633 (define_split
7634 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7635 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7636 (match_operand:DI 2 "and64_2_operand" ""))
7637 (const_int 0)))
7638 (set (match_operand:DI 0 "gpc_reg_operand" "")
7639 (and:DI (match_dup 1) (match_dup 2)))
7640 (clobber (match_scratch:CC 4 ""))]
7641 "TARGET_64BIT && reload_completed"
7642 [(parallel [(set (match_dup 0)
7643 (and:DI (match_dup 1) (match_dup 2)))
7644 (clobber (match_dup 4))])
7645 (set (match_dup 3)
7646 (compare:CC (match_dup 0)
7647 (const_int 0)))]
7648 "")
7649
7650 (define_split
7651 [(set (match_operand:CC 3 "cc_reg_operand" "")
7652 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7653 (match_operand:DI 2 "mask64_2_operand" ""))
7654 (const_int 0)))
7655 (set (match_operand:DI 0 "gpc_reg_operand" "")
7656 (and:DI (match_dup 1) (match_dup 2)))
7657 (clobber (match_scratch:CC 4 ""))]
7658 "TARGET_64BIT && reload_completed
7659 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7660 && !mask_operand (operands[2], DImode)
7661 && !mask64_operand (operands[2], DImode)"
7662 [(set (match_dup 0)
7663 (and:DI (rotate:DI (match_dup 1)
7664 (match_dup 5))
7665 (match_dup 6)))
7666 (parallel [(set (match_dup 3)
7667 (compare:CC (and:DI (rotate:DI (match_dup 0)
7668 (match_dup 7))
7669 (match_dup 8))
7670 (const_int 0)))
7671 (set (match_dup 0)
7672 (and:DI (rotate:DI (match_dup 0)
7673 (match_dup 7))
7674 (match_dup 8)))])]
7675 "
7676 {
7677 build_mask64_2_operands (operands[2], &operands[5]);
7678 }")
7679
7680 (define_expand "iordi3"
7681 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7682 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7683 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7684 "TARGET_POWERPC64"
7685 "
7686 {
7687 if (non_logical_cint_operand (operands[2], DImode))
7688 {
7689 HOST_WIDE_INT value;
7690 rtx tmp = ((!can_create_pseudo_p ()
7691 || rtx_equal_p (operands[0], operands[1]))
7692 ? operands[0] : gen_reg_rtx (DImode));
7693
7694 if (GET_CODE (operands[2]) == CONST_INT)
7695 {
7696 value = INTVAL (operands[2]);
7697 emit_insn (gen_iordi3 (tmp, operands[1],
7698 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7699 }
7700 else
7701 {
7702 value = CONST_DOUBLE_LOW (operands[2]);
7703 emit_insn (gen_iordi3 (tmp, operands[1],
7704 immed_double_const (value
7705 & (~ (HOST_WIDE_INT) 0xffff),
7706 0, DImode)));
7707 }
7708
7709 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7710 DONE;
7711 }
7712 }")
7713
7714 (define_expand "xordi3"
7715 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7716 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7717 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7718 "TARGET_POWERPC64"
7719 "
7720 {
7721 if (non_logical_cint_operand (operands[2], DImode))
7722 {
7723 HOST_WIDE_INT value;
7724 rtx tmp = ((!can_create_pseudo_p ()
7725 || rtx_equal_p (operands[0], operands[1]))
7726 ? operands[0] : gen_reg_rtx (DImode));
7727
7728 if (GET_CODE (operands[2]) == CONST_INT)
7729 {
7730 value = INTVAL (operands[2]);
7731 emit_insn (gen_xordi3 (tmp, operands[1],
7732 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7733 }
7734 else
7735 {
7736 value = CONST_DOUBLE_LOW (operands[2]);
7737 emit_insn (gen_xordi3 (tmp, operands[1],
7738 immed_double_const (value
7739 & (~ (HOST_WIDE_INT) 0xffff),
7740 0, DImode)));
7741 }
7742
7743 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7744 DONE;
7745 }
7746 }")
7747
7748 (define_insn "*booldi3_internal1"
7749 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7750 (match_operator:DI 3 "boolean_or_operator"
7751 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7752 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7753 "TARGET_POWERPC64"
7754 "@
7755 %q3 %0,%1,%2
7756 %q3i %0,%1,%b2
7757 %q3is %0,%1,%u2")
7758
7759 (define_insn "*booldi3_internal2"
7760 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7761 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7762 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7763 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7764 (const_int 0)))
7765 (clobber (match_scratch:DI 3 "=r,r"))]
7766 "TARGET_64BIT"
7767 "@
7768 %q4. %3,%1,%2
7769 #"
7770 [(set_attr "type" "compare")
7771 (set_attr "length" "4,8")])
7772
7773 (define_split
7774 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7775 (compare:CC (match_operator:DI 4 "boolean_operator"
7776 [(match_operand:DI 1 "gpc_reg_operand" "")
7777 (match_operand:DI 2 "gpc_reg_operand" "")])
7778 (const_int 0)))
7779 (clobber (match_scratch:DI 3 ""))]
7780 "TARGET_POWERPC64 && reload_completed"
7781 [(set (match_dup 3) (match_dup 4))
7782 (set (match_dup 0)
7783 (compare:CC (match_dup 3)
7784 (const_int 0)))]
7785 "")
7786
7787 (define_insn "*booldi3_internal3"
7788 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7789 (compare:CC (match_operator:DI 4 "boolean_operator"
7790 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7791 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7792 (const_int 0)))
7793 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7794 (match_dup 4))]
7795 "TARGET_64BIT"
7796 "@
7797 %q4. %0,%1,%2
7798 #"
7799 [(set_attr "type" "compare")
7800 (set_attr "length" "4,8")])
7801
7802 (define_split
7803 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7804 (compare:CC (match_operator:DI 4 "boolean_operator"
7805 [(match_operand:DI 1 "gpc_reg_operand" "")
7806 (match_operand:DI 2 "gpc_reg_operand" "")])
7807 (const_int 0)))
7808 (set (match_operand:DI 0 "gpc_reg_operand" "")
7809 (match_dup 4))]
7810 "TARGET_POWERPC64 && reload_completed"
7811 [(set (match_dup 0) (match_dup 4))
7812 (set (match_dup 3)
7813 (compare:CC (match_dup 0)
7814 (const_int 0)))]
7815 "")
7816
7817 ;; Split a logical operation that we can't do in one insn into two insns,
7818 ;; each of which does one 16-bit part. This is used by combine.
7819
7820 (define_split
7821 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7822 (match_operator:DI 3 "boolean_or_operator"
7823 [(match_operand:DI 1 "gpc_reg_operand" "")
7824 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7825 "TARGET_POWERPC64"
7826 [(set (match_dup 0) (match_dup 4))
7827 (set (match_dup 0) (match_dup 5))]
7828 "
7829 {
7830 rtx i3,i4;
7831
7832 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7833 {
7834 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7835 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7836 0, DImode);
7837 i4 = GEN_INT (value & 0xffff);
7838 }
7839 else
7840 {
7841 i3 = GEN_INT (INTVAL (operands[2])
7842 & (~ (HOST_WIDE_INT) 0xffff));
7843 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7844 }
7845 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7846 operands[1], i3);
7847 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7848 operands[0], i4);
7849 }")
7850
7851 (define_insn "*boolcdi3_internal1"
7852 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7853 (match_operator:DI 3 "boolean_operator"
7854 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7855 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7856 "TARGET_POWERPC64"
7857 "%q3 %0,%2,%1")
7858
7859 (define_insn "*boolcdi3_internal2"
7860 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7861 (compare:CC (match_operator:DI 4 "boolean_operator"
7862 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7863 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7864 (const_int 0)))
7865 (clobber (match_scratch:DI 3 "=r,r"))]
7866 "TARGET_64BIT"
7867 "@
7868 %q4. %3,%2,%1
7869 #"
7870 [(set_attr "type" "compare")
7871 (set_attr "length" "4,8")])
7872
7873 (define_split
7874 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7875 (compare:CC (match_operator:DI 4 "boolean_operator"
7876 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7877 (match_operand:DI 2 "gpc_reg_operand" "")])
7878 (const_int 0)))
7879 (clobber (match_scratch:DI 3 ""))]
7880 "TARGET_POWERPC64 && reload_completed"
7881 [(set (match_dup 3) (match_dup 4))
7882 (set (match_dup 0)
7883 (compare:CC (match_dup 3)
7884 (const_int 0)))]
7885 "")
7886
7887 (define_insn "*boolcdi3_internal3"
7888 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7889 (compare:CC (match_operator:DI 4 "boolean_operator"
7890 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7891 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7892 (const_int 0)))
7893 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7894 (match_dup 4))]
7895 "TARGET_64BIT"
7896 "@
7897 %q4. %0,%2,%1
7898 #"
7899 [(set_attr "type" "compare")
7900 (set_attr "length" "4,8")])
7901
7902 (define_split
7903 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7904 (compare:CC (match_operator:DI 4 "boolean_operator"
7905 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7906 (match_operand:DI 2 "gpc_reg_operand" "")])
7907 (const_int 0)))
7908 (set (match_operand:DI 0 "gpc_reg_operand" "")
7909 (match_dup 4))]
7910 "TARGET_POWERPC64 && reload_completed"
7911 [(set (match_dup 0) (match_dup 4))
7912 (set (match_dup 3)
7913 (compare:CC (match_dup 0)
7914 (const_int 0)))]
7915 "")
7916
7917 (define_insn "*boolccdi3_internal1"
7918 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7919 (match_operator:DI 3 "boolean_operator"
7920 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7921 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7922 "TARGET_POWERPC64"
7923 "%q3 %0,%1,%2")
7924
7925 (define_insn "*boolccdi3_internal2"
7926 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7927 (compare:CC (match_operator:DI 4 "boolean_operator"
7928 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7929 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7930 (const_int 0)))
7931 (clobber (match_scratch:DI 3 "=r,r"))]
7932 "TARGET_64BIT"
7933 "@
7934 %q4. %3,%1,%2
7935 #"
7936 [(set_attr "type" "compare")
7937 (set_attr "length" "4,8")])
7938
7939 (define_split
7940 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7941 (compare:CC (match_operator:DI 4 "boolean_operator"
7942 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7943 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7944 (const_int 0)))
7945 (clobber (match_scratch:DI 3 ""))]
7946 "TARGET_POWERPC64 && reload_completed"
7947 [(set (match_dup 3) (match_dup 4))
7948 (set (match_dup 0)
7949 (compare:CC (match_dup 3)
7950 (const_int 0)))]
7951 "")
7952
7953 (define_insn "*boolccdi3_internal3"
7954 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7955 (compare:CC (match_operator:DI 4 "boolean_operator"
7956 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7957 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7958 (const_int 0)))
7959 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7960 (match_dup 4))]
7961 "TARGET_64BIT"
7962 "@
7963 %q4. %0,%1,%2
7964 #"
7965 [(set_attr "type" "compare")
7966 (set_attr "length" "4,8")])
7967
7968 (define_split
7969 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7970 (compare:CC (match_operator:DI 4 "boolean_operator"
7971 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7972 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7973 (const_int 0)))
7974 (set (match_operand:DI 0 "gpc_reg_operand" "")
7975 (match_dup 4))]
7976 "TARGET_POWERPC64 && reload_completed"
7977 [(set (match_dup 0) (match_dup 4))
7978 (set (match_dup 3)
7979 (compare:CC (match_dup 0)
7980 (const_int 0)))]
7981 "")
7982 \f
7983 ;; Now define ways of moving data around.
7984
7985 ;; Set up a register with a value from the GOT table
7986
7987 (define_expand "movsi_got"
7988 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7989 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7990 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7991 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7992 "
7993 {
7994 if (GET_CODE (operands[1]) == CONST)
7995 {
7996 rtx offset = const0_rtx;
7997 HOST_WIDE_INT value;
7998
7999 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8000 value = INTVAL (offset);
8001 if (value != 0)
8002 {
8003 rtx tmp = (!can_create_pseudo_p ()
8004 ? operands[0]
8005 : gen_reg_rtx (Pmode));
8006 emit_insn (gen_movsi_got (tmp, operands[1]));
8007 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8008 DONE;
8009 }
8010 }
8011
8012 operands[2] = rs6000_got_register (operands[1]);
8013 }")
8014
8015 (define_insn "*movsi_got_internal"
8016 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8017 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8018 (match_operand:SI 2 "gpc_reg_operand" "b")]
8019 UNSPEC_MOVSI_GOT))]
8020 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8021 "{l|lwz} %0,%a1@got(%2)"
8022 [(set_attr "type" "load")])
8023
8024 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
8025 ;; didn't get allocated to a hard register.
8026 (define_split
8027 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8028 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8029 (match_operand:SI 2 "memory_operand" "")]
8030 UNSPEC_MOVSI_GOT))]
8031 "DEFAULT_ABI == ABI_V4
8032 && flag_pic == 1
8033 && (reload_in_progress || reload_completed)"
8034 [(set (match_dup 0) (match_dup 2))
8035 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8036 UNSPEC_MOVSI_GOT))]
8037 "")
8038
8039 ;; For SI, we special-case integers that can't be loaded in one insn. We
8040 ;; do the load 16-bits at a time. We could do this by loading from memory,
8041 ;; and this is even supposed to be faster, but it is simpler not to get
8042 ;; integers in the TOC.
8043 (define_insn "movsi_low"
8044 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8045 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
8046 (match_operand 2 "" ""))))]
8047 "TARGET_MACHO && ! TARGET_64BIT"
8048 "{l|lwz} %0,lo16(%2)(%1)"
8049 [(set_attr "type" "load")
8050 (set_attr "length" "4")])
8051
8052 (define_insn "*movsi_internal1"
8053 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
8054 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
8055 "gpc_reg_operand (operands[0], SImode)
8056 || gpc_reg_operand (operands[1], SImode)"
8057 "@
8058 mr %0,%1
8059 {cal|la} %0,%a1
8060 {l%U1%X1|lwz%U1%X1} %0,%1
8061 {st%U0%X0|stw%U0%X0} %1,%0
8062 {lil|li} %0,%1
8063 {liu|lis} %0,%v1
8064 #
8065 {cal|la} %0,%a1
8066 mf%1 %0
8067 mt%0 %1
8068 mt%0 %1
8069 mt%0 %1
8070 {cror 0,0,0|nop}"
8071 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
8072 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
8073
8074 ;; Split a load of a large constant into the appropriate two-insn
8075 ;; sequence.
8076
8077 (define_split
8078 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8079 (match_operand:SI 1 "const_int_operand" ""))]
8080 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
8081 && (INTVAL (operands[1]) & 0xffff) != 0"
8082 [(set (match_dup 0)
8083 (match_dup 2))
8084 (set (match_dup 0)
8085 (ior:SI (match_dup 0)
8086 (match_dup 3)))]
8087 "
8088 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8089
8090 if (tem == operands[0])
8091 DONE;
8092 else
8093 FAIL;
8094 }")
8095
8096 (define_insn "*mov<mode>_internal2"
8097 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8098 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
8099 (const_int 0)))
8100 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8101 ""
8102 "@
8103 {cmpi|cmp<wd>i} %2,%0,0
8104 mr. %0,%1
8105 #"
8106 [(set_attr "type" "cmp,compare,cmp")
8107 (set_attr "length" "4,4,8")])
8108
8109 (define_split
8110 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8111 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
8112 (const_int 0)))
8113 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8114 "reload_completed"
8115 [(set (match_dup 0) (match_dup 1))
8116 (set (match_dup 2)
8117 (compare:CC (match_dup 0)
8118 (const_int 0)))]
8119 "")
8120 \f
8121 (define_insn "*movhi_internal"
8122 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8123 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8124 "gpc_reg_operand (operands[0], HImode)
8125 || gpc_reg_operand (operands[1], HImode)"
8126 "@
8127 mr %0,%1
8128 lhz%U1%X1 %0,%1
8129 sth%U0%X0 %1,%0
8130 {lil|li} %0,%w1
8131 mf%1 %0
8132 mt%0 %1
8133 mt%0 %1
8134 {cror 0,0,0|nop}"
8135 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8136
8137 (define_expand "mov<mode>"
8138 [(set (match_operand:INT 0 "general_operand" "")
8139 (match_operand:INT 1 "any_operand" ""))]
8140 ""
8141 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8142
8143 (define_insn "*movqi_internal"
8144 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8145 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8146 "gpc_reg_operand (operands[0], QImode)
8147 || gpc_reg_operand (operands[1], QImode)"
8148 "@
8149 mr %0,%1
8150 lbz%U1%X1 %0,%1
8151 stb%U0%X0 %1,%0
8152 {lil|li} %0,%1
8153 mf%1 %0
8154 mt%0 %1
8155 mt%0 %1
8156 {cror 0,0,0|nop}"
8157 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8158 \f
8159 ;; Here is how to move condition codes around. When we store CC data in
8160 ;; an integer register or memory, we store just the high-order 4 bits.
8161 ;; This lets us not shift in the most common case of CR0.
8162 (define_expand "movcc"
8163 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8164 (match_operand:CC 1 "nonimmediate_operand" ""))]
8165 ""
8166 "")
8167
8168 (define_insn "*movcc_internal1"
8169 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
8170 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
8171 "register_operand (operands[0], CCmode)
8172 || register_operand (operands[1], CCmode)"
8173 "@
8174 mcrf %0,%1
8175 mtcrf 128,%1
8176 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
8177 crxor %0,%0,%0
8178 mfcr %0%Q1
8179 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
8180 mr %0,%1
8181 {lil|li} %0,%1
8182 mf%1 %0
8183 mt%0 %1
8184 mt%0 %1
8185 {l%U1%X1|lwz%U1%X1} %0,%1
8186 {st%U0%U1|stw%U0%U1} %1,%0"
8187 [(set (attr "type")
8188 (cond [(eq_attr "alternative" "0,3")
8189 (const_string "cr_logical")
8190 (eq_attr "alternative" "1,2")
8191 (const_string "mtcr")
8192 (eq_attr "alternative" "6,7,9")
8193 (const_string "integer")
8194 (eq_attr "alternative" "8")
8195 (const_string "mfjmpr")
8196 (eq_attr "alternative" "10")
8197 (const_string "mtjmpr")
8198 (eq_attr "alternative" "11")
8199 (const_string "load")
8200 (eq_attr "alternative" "12")
8201 (const_string "store")
8202 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
8203 (const_string "mfcrf")
8204 ]
8205 (const_string "mfcr")))
8206 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
8207 \f
8208 ;; For floating-point, we normally deal with the floating-point registers
8209 ;; unless -msoft-float is used. The sole exception is that parameter passing
8210 ;; can produce floating-point values in fixed-point registers. Unless the
8211 ;; value is a simple constant or already in memory, we deal with this by
8212 ;; allocating memory and copying the value explicitly via that memory location.
8213 (define_expand "movsf"
8214 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8215 (match_operand:SF 1 "any_operand" ""))]
8216 ""
8217 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
8218
8219 (define_split
8220 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8221 (match_operand:SF 1 "const_double_operand" ""))]
8222 "reload_completed
8223 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8224 || (GET_CODE (operands[0]) == SUBREG
8225 && GET_CODE (SUBREG_REG (operands[0])) == REG
8226 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8227 [(set (match_dup 2) (match_dup 3))]
8228 "
8229 {
8230 long l;
8231 REAL_VALUE_TYPE rv;
8232
8233 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8234 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
8235
8236 if (! TARGET_POWERPC64)
8237 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
8238 else
8239 operands[2] = gen_lowpart (SImode, operands[0]);
8240
8241 operands[3] = gen_int_mode (l, SImode);
8242 }")
8243
8244 (define_insn "*movsf_hardfloat"
8245 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
8246 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
8247 "(gpc_reg_operand (operands[0], SFmode)
8248 || gpc_reg_operand (operands[1], SFmode))
8249 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
8250 "@
8251 mr %0,%1
8252 {l%U1%X1|lwz%U1%X1} %0,%1
8253 {st%U0%X0|stw%U0%X0} %1,%0
8254 fmr %0,%1
8255 lfs%U1%X1 %0,%1
8256 stfs%U0%X0 %1,%0
8257 mt%0 %1
8258 mt%0 %1
8259 mf%1 %0
8260 {cror 0,0,0|nop}
8261 #
8262 #"
8263 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
8264 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
8265
8266 (define_insn "*movsf_softfloat"
8267 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
8268 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
8269 "(gpc_reg_operand (operands[0], SFmode)
8270 || gpc_reg_operand (operands[1], SFmode))
8271 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
8272 "@
8273 mr %0,%1
8274 mt%0 %1
8275 mt%0 %1
8276 mf%1 %0
8277 {l%U1%X1|lwz%U1%X1} %0,%1
8278 {st%U0%X0|stw%U0%X0} %1,%0
8279 {lil|li} %0,%1
8280 {liu|lis} %0,%v1
8281 {cal|la} %0,%a1
8282 #
8283 #
8284 {cror 0,0,0|nop}"
8285 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
8286 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
8287
8288 \f
8289 (define_expand "movdf"
8290 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8291 (match_operand:DF 1 "any_operand" ""))]
8292 ""
8293 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
8294
8295 (define_split
8296 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8297 (match_operand:DF 1 "const_int_operand" ""))]
8298 "! TARGET_POWERPC64 && reload_completed
8299 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8300 || (GET_CODE (operands[0]) == SUBREG
8301 && GET_CODE (SUBREG_REG (operands[0])) == REG
8302 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8303 [(set (match_dup 2) (match_dup 4))
8304 (set (match_dup 3) (match_dup 1))]
8305 "
8306 {
8307 int endian = (WORDS_BIG_ENDIAN == 0);
8308 HOST_WIDE_INT value = INTVAL (operands[1]);
8309
8310 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8311 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8312 #if HOST_BITS_PER_WIDE_INT == 32
8313 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8314 #else
8315 operands[4] = GEN_INT (value >> 32);
8316 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8317 #endif
8318 }")
8319
8320 (define_split
8321 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8322 (match_operand:DF 1 "const_double_operand" ""))]
8323 "! TARGET_POWERPC64 && reload_completed
8324 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8325 || (GET_CODE (operands[0]) == SUBREG
8326 && GET_CODE (SUBREG_REG (operands[0])) == REG
8327 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8328 [(set (match_dup 2) (match_dup 4))
8329 (set (match_dup 3) (match_dup 5))]
8330 "
8331 {
8332 int endian = (WORDS_BIG_ENDIAN == 0);
8333 long l[2];
8334 REAL_VALUE_TYPE rv;
8335
8336 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8337 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8338
8339 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8340 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8341 operands[4] = gen_int_mode (l[endian], SImode);
8342 operands[5] = gen_int_mode (l[1 - endian], SImode);
8343 }")
8344
8345 (define_split
8346 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8347 (match_operand:DF 1 "const_double_operand" ""))]
8348 "TARGET_POWERPC64 && reload_completed
8349 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8350 || (GET_CODE (operands[0]) == SUBREG
8351 && GET_CODE (SUBREG_REG (operands[0])) == REG
8352 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8353 [(set (match_dup 2) (match_dup 3))]
8354 "
8355 {
8356 int endian = (WORDS_BIG_ENDIAN == 0);
8357 long l[2];
8358 REAL_VALUE_TYPE rv;
8359 #if HOST_BITS_PER_WIDE_INT >= 64
8360 HOST_WIDE_INT val;
8361 #endif
8362
8363 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8364 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8365
8366 operands[2] = gen_lowpart (DImode, operands[0]);
8367 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8368 #if HOST_BITS_PER_WIDE_INT >= 64
8369 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8370 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8371
8372 operands[3] = gen_int_mode (val, DImode);
8373 #else
8374 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8375 #endif
8376 }")
8377
8378 ;; Don't have reload use general registers to load a constant. First,
8379 ;; it might not work if the output operand is the equivalent of
8380 ;; a non-offsettable memref, but also it is less efficient than loading
8381 ;; the constant into an FP register, since it will probably be used there.
8382 ;; The "??" is a kludge until we can figure out a more reasonable way
8383 ;; of handling these non-offsettable values.
8384 (define_insn "*movdf_hardfloat32"
8385 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8386 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
8387 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8388 && (gpc_reg_operand (operands[0], DFmode)
8389 || gpc_reg_operand (operands[1], DFmode))"
8390 "*
8391 {
8392 switch (which_alternative)
8393 {
8394 default:
8395 gcc_unreachable ();
8396 case 0:
8397 /* We normally copy the low-numbered register first. However, if
8398 the first register operand 0 is the same as the second register
8399 of operand 1, we must copy in the opposite order. */
8400 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8401 return \"mr %L0,%L1\;mr %0,%1\";
8402 else
8403 return \"mr %0,%1\;mr %L0,%L1\";
8404 case 1:
8405 if (rs6000_offsettable_memref_p (operands[1])
8406 || (GET_CODE (operands[1]) == MEM
8407 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8408 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8409 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC
8410 || GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)))
8411 {
8412 /* If the low-address word is used in the address, we must load
8413 it last. Otherwise, load it first. Note that we cannot have
8414 auto-increment in that case since the address register is
8415 known to be dead. */
8416 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8417 operands[1], 0))
8418 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8419 else
8420 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
8421 }
8422 else
8423 {
8424 rtx addreg;
8425
8426 addreg = find_addr_reg (XEXP (operands[1], 0));
8427 if (refers_to_regno_p (REGNO (operands[0]),
8428 REGNO (operands[0]) + 1,
8429 operands[1], 0))
8430 {
8431 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8432 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
8433 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8434 return \"{l%X1|lwz%X1} %0,%1\";
8435 }
8436 else
8437 {
8438 output_asm_insn (\"{l%X1|lwz%X1} %0,%1\", operands);
8439 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8440 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
8441 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8442 return \"\";
8443 }
8444 }
8445 case 2:
8446 if (rs6000_offsettable_memref_p (operands[0])
8447 || (GET_CODE (operands[0]) == MEM
8448 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8449 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8450 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
8451 || GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)))
8452 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
8453 else
8454 {
8455 rtx addreg;
8456
8457 addreg = find_addr_reg (XEXP (operands[0], 0));
8458 output_asm_insn (\"{st%X0|stw%X0} %1,%0\", operands);
8459 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8460 output_asm_insn (\"{st%X0|stw%X0} %L1,%0\", operands);
8461 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8462 return \"\";
8463 }
8464 case 3:
8465 return \"fmr %0,%1\";
8466 case 4:
8467 return \"lfd%U1%X1 %0,%1\";
8468 case 5:
8469 return \"stfd%U0%X0 %1,%0\";
8470 case 6:
8471 case 7:
8472 case 8:
8473 return \"#\";
8474 }
8475 }"
8476 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
8477 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
8478
8479 (define_insn "*movdf_softfloat32"
8480 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8481 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8482 "! TARGET_POWERPC64
8483 && ((TARGET_FPRS && !TARGET_DOUBLE_FLOAT)
8484 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8485 && (gpc_reg_operand (operands[0], DFmode)
8486 || gpc_reg_operand (operands[1], DFmode))"
8487 "*
8488 {
8489 switch (which_alternative)
8490 {
8491 default:
8492 gcc_unreachable ();
8493 case 0:
8494 /* We normally copy the low-numbered register first. However, if
8495 the first register operand 0 is the same as the second register of
8496 operand 1, we must copy in the opposite order. */
8497 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8498 return \"mr %L0,%L1\;mr %0,%1\";
8499 else
8500 return \"mr %0,%1\;mr %L0,%L1\";
8501 case 1:
8502 /* If the low-address word is used in the address, we must load
8503 it last. Otherwise, load it first. Note that we cannot have
8504 auto-increment in that case since the address register is
8505 known to be dead. */
8506 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8507 operands[1], 0))
8508 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8509 else
8510 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
8511 case 2:
8512 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
8513 case 3:
8514 case 4:
8515 case 5:
8516 return \"#\";
8517 }
8518 }"
8519 [(set_attr "type" "two,load,store,*,*,*")
8520 (set_attr "length" "8,8,8,8,12,16")])
8521
8522 ; ld/std require word-aligned displacements -> 'Y' constraint.
8523 ; List Y->r and r->Y before r->r for reload.
8524 (define_insn "*movdf_hardfloat64_mfpgpr"
8525 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f")
8526 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))]
8527 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8528 && TARGET_DOUBLE_FLOAT
8529 && (gpc_reg_operand (operands[0], DFmode)
8530 || gpc_reg_operand (operands[1], DFmode))"
8531 "@
8532 std%U0%X0 %1,%0
8533 ld%U1%X1 %0,%1
8534 mr %0,%1
8535 fmr %0,%1
8536 lfd%U1%X1 %0,%1
8537 stfd%U0%X0 %1,%0
8538 mt%0 %1
8539 mf%1 %0
8540 {cror 0,0,0|nop}
8541 #
8542 #
8543 #
8544 mftgpr %0,%1
8545 mffgpr %0,%1"
8546 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
8547 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
8548
8549 ; ld/std require word-aligned displacements -> 'Y' constraint.
8550 ; List Y->r and r->Y before r->r for reload.
8551 (define_insn "*movdf_hardfloat64"
8552 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
8553 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
8554 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8555 && TARGET_DOUBLE_FLOAT
8556 && (gpc_reg_operand (operands[0], DFmode)
8557 || gpc_reg_operand (operands[1], DFmode))"
8558 "@
8559 std%U0%X0 %1,%0
8560 ld%U1%X1 %0,%1
8561 mr %0,%1
8562 fmr %0,%1
8563 lfd%U1%X1 %0,%1
8564 stfd%U0%X0 %1,%0
8565 mt%0 %1
8566 mf%1 %0
8567 {cror 0,0,0|nop}
8568 #
8569 #
8570 #"
8571 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
8572 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
8573
8574 (define_insn "*movdf_softfloat64"
8575 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8576 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
8577 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8578 && (gpc_reg_operand (operands[0], DFmode)
8579 || gpc_reg_operand (operands[1], DFmode))"
8580 "@
8581 ld%U1%X1 %0,%1
8582 std%U0%X0 %1,%0
8583 mr %0,%1
8584 mt%0 %1
8585 mf%1 %0
8586 #
8587 #
8588 #
8589 {cror 0,0,0|nop}"
8590 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
8591 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8592 \f
8593 (define_expand "movtf"
8594 [(set (match_operand:TF 0 "general_operand" "")
8595 (match_operand:TF 1 "any_operand" ""))]
8596 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
8597 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8598
8599 ; It's important to list the o->f and f->o moves before f->f because
8600 ; otherwise reload, given m->f, will try to pick f->f and reload it,
8601 ; which doesn't make progress. Likewise r->Y must be before r->r.
8602 (define_insn_and_split "*movtf_internal"
8603 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
8604 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
8605 "!TARGET_IEEEQUAD
8606 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8607 && (gpc_reg_operand (operands[0], TFmode)
8608 || gpc_reg_operand (operands[1], TFmode))"
8609 "#"
8610 "&& reload_completed"
8611 [(pc)]
8612 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8613 [(set_attr "length" "8,8,8,20,20,16")])
8614
8615 (define_insn_and_split "*movtf_softfloat"
8616 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
8617 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
8618 "!TARGET_IEEEQUAD
8619 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
8620 && (gpc_reg_operand (operands[0], TFmode)
8621 || gpc_reg_operand (operands[1], TFmode))"
8622 "#"
8623 "&& reload_completed"
8624 [(pc)]
8625 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8626 [(set_attr "length" "20,20,16")])
8627
8628 (define_expand "extenddftf2"
8629 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8630 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8631 "!TARGET_IEEEQUAD
8632 && TARGET_HARD_FLOAT
8633 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8634 && TARGET_LONG_DOUBLE_128"
8635 {
8636 if (TARGET_E500_DOUBLE)
8637 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8638 else
8639 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8640 DONE;
8641 })
8642
8643 (define_expand "extenddftf2_fprs"
8644 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8645 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8646 (use (match_dup 2))])]
8647 "!TARGET_IEEEQUAD
8648 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8649 && TARGET_LONG_DOUBLE_128"
8650 {
8651 operands[2] = CONST0_RTX (DFmode);
8652 /* Generate GOT reference early for SVR4 PIC. */
8653 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8654 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8655 })
8656
8657 (define_insn_and_split "*extenddftf2_internal"
8658 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8659 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8660 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
8661 "!TARGET_IEEEQUAD
8662 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8663 && TARGET_LONG_DOUBLE_128"
8664 "#"
8665 "&& reload_completed"
8666 [(pc)]
8667 {
8668 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8669 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8670 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8671 operands[1]);
8672 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8673 operands[2]);
8674 DONE;
8675 })
8676
8677 (define_expand "extendsftf2"
8678 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8679 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8680 "!TARGET_IEEEQUAD
8681 && TARGET_HARD_FLOAT
8682 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8683 && TARGET_LONG_DOUBLE_128"
8684 {
8685 rtx tmp = gen_reg_rtx (DFmode);
8686 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8687 emit_insn (gen_extenddftf2 (operands[0], tmp));
8688 DONE;
8689 })
8690
8691 (define_expand "trunctfdf2"
8692 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8693 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8694 "!TARGET_IEEEQUAD
8695 && TARGET_HARD_FLOAT
8696 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8697 && TARGET_LONG_DOUBLE_128"
8698 "")
8699
8700 (define_insn_and_split "trunctfdf2_internal1"
8701 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8702 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
8703 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8704 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8705 "@
8706 #
8707 fmr %0,%1"
8708 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8709 [(const_int 0)]
8710 {
8711 emit_note (NOTE_INSN_DELETED);
8712 DONE;
8713 }
8714 [(set_attr "type" "fp")])
8715
8716 (define_insn "trunctfdf2_internal2"
8717 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8718 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8719 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8720 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8721 && TARGET_LONG_DOUBLE_128"
8722 "fadd %0,%1,%L1"
8723 [(set_attr "type" "fp")])
8724
8725 (define_expand "trunctfsf2"
8726 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8727 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8728 "!TARGET_IEEEQUAD
8729 && TARGET_HARD_FLOAT
8730 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8731 && TARGET_LONG_DOUBLE_128"
8732 {
8733 if (TARGET_E500_DOUBLE)
8734 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8735 else
8736 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8737 DONE;
8738 })
8739
8740 (define_insn_and_split "trunctfsf2_fprs"
8741 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8742 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8743 (clobber (match_scratch:DF 2 "=f"))]
8744 "!TARGET_IEEEQUAD
8745 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
8746 && TARGET_LONG_DOUBLE_128"
8747 "#"
8748 "&& reload_completed"
8749 [(set (match_dup 2)
8750 (float_truncate:DF (match_dup 1)))
8751 (set (match_dup 0)
8752 (float_truncate:SF (match_dup 2)))]
8753 "")
8754
8755 (define_expand "floatsitf2"
8756 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8757 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
8758 "!TARGET_IEEEQUAD
8759 && TARGET_HARD_FLOAT
8760 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8761 && TARGET_LONG_DOUBLE_128"
8762 {
8763 rtx tmp = gen_reg_rtx (DFmode);
8764 expand_float (tmp, operands[1], false);
8765 emit_insn (gen_extenddftf2 (operands[0], tmp));
8766 DONE;
8767 })
8768
8769 ; fadd, but rounding towards zero.
8770 ; This is probably not the optimal code sequence.
8771 (define_insn "fix_trunc_helper"
8772 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8773 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8774 UNSPEC_FIX_TRUNC_TF))
8775 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8776 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
8777 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8778 [(set_attr "type" "fp")
8779 (set_attr "length" "20")])
8780
8781 (define_expand "fix_trunctfsi2"
8782 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8783 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8784 "!TARGET_IEEEQUAD
8785 && (TARGET_POWER2 || TARGET_POWERPC)
8786 && TARGET_HARD_FLOAT
8787 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8788 && TARGET_LONG_DOUBLE_128"
8789 {
8790 if (TARGET_E500_DOUBLE)
8791 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8792 else
8793 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8794 DONE;
8795 })
8796
8797 (define_expand "fix_trunctfsi2_fprs"
8798 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8799 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8800 (clobber (match_dup 2))
8801 (clobber (match_dup 3))
8802 (clobber (match_dup 4))
8803 (clobber (match_dup 5))])]
8804 "!TARGET_IEEEQUAD
8805 && (TARGET_POWER2 || TARGET_POWERPC)
8806 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8807 {
8808 operands[2] = gen_reg_rtx (DFmode);
8809 operands[3] = gen_reg_rtx (DFmode);
8810 operands[4] = gen_reg_rtx (DImode);
8811 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8812 })
8813
8814 (define_insn_and_split "*fix_trunctfsi2_internal"
8815 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8816 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8817 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8818 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8819 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8820 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
8821 "!TARGET_IEEEQUAD
8822 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8823 "#"
8824 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[5]))"
8825 [(pc)]
8826 {
8827 rtx lowword;
8828 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8829
8830 gcc_assert (MEM_P (operands[5]));
8831 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8832
8833 emit_insn (gen_fctiwz (operands[4], operands[2]));
8834 emit_move_insn (operands[5], operands[4]);
8835 emit_move_insn (operands[0], lowword);
8836 DONE;
8837 })
8838
8839 (define_expand "negtf2"
8840 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8841 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8842 "!TARGET_IEEEQUAD
8843 && TARGET_HARD_FLOAT
8844 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8845 && TARGET_LONG_DOUBLE_128"
8846 "")
8847
8848 (define_insn "negtf2_internal"
8849 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8850 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8851 "!TARGET_IEEEQUAD
8852 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8853 "*
8854 {
8855 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8856 return \"fneg %L0,%L1\;fneg %0,%1\";
8857 else
8858 return \"fneg %0,%1\;fneg %L0,%L1\";
8859 }"
8860 [(set_attr "type" "fp")
8861 (set_attr "length" "8")])
8862
8863 (define_expand "abstf2"
8864 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8865 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8866 "!TARGET_IEEEQUAD
8867 && TARGET_HARD_FLOAT
8868 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8869 && TARGET_LONG_DOUBLE_128"
8870 "
8871 {
8872 rtx label = gen_label_rtx ();
8873 if (TARGET_E500_DOUBLE)
8874 {
8875 if (flag_unsafe_math_optimizations)
8876 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
8877 else
8878 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
8879 }
8880 else
8881 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8882 emit_label (label);
8883 DONE;
8884 }")
8885
8886 (define_expand "abstf2_internal"
8887 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8888 (match_operand:TF 1 "gpc_reg_operand" ""))
8889 (set (match_dup 3) (match_dup 5))
8890 (set (match_dup 5) (abs:DF (match_dup 5)))
8891 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8892 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8893 (label_ref (match_operand 2 "" ""))
8894 (pc)))
8895 (set (match_dup 6) (neg:DF (match_dup 6)))]
8896 "!TARGET_IEEEQUAD
8897 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8898 && TARGET_LONG_DOUBLE_128"
8899 "
8900 {
8901 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8902 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8903 operands[3] = gen_reg_rtx (DFmode);
8904 operands[4] = gen_reg_rtx (CCFPmode);
8905 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8906 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8907 }")
8908 \f
8909 ;; Next come the multi-word integer load and store and the load and store
8910 ;; multiple insns.
8911
8912 ; List r->r after r->"o<>", otherwise reload will try to reload a
8913 ; non-offsettable address by using r->r which won't make progress.
8914 (define_insn "*movdi_internal32"
8915 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
8916 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
8917 "! TARGET_POWERPC64
8918 && (gpc_reg_operand (operands[0], DImode)
8919 || gpc_reg_operand (operands[1], DImode))"
8920 "@
8921 #
8922 #
8923 #
8924 fmr %0,%1
8925 lfd%U1%X1 %0,%1
8926 stfd%U0%X0 %1,%0
8927 #"
8928 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
8929
8930 (define_split
8931 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8932 (match_operand:DI 1 "const_int_operand" ""))]
8933 "! TARGET_POWERPC64 && reload_completed"
8934 [(set (match_dup 2) (match_dup 4))
8935 (set (match_dup 3) (match_dup 1))]
8936 "
8937 {
8938 HOST_WIDE_INT value = INTVAL (operands[1]);
8939 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8940 DImode);
8941 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8942 DImode);
8943 #if HOST_BITS_PER_WIDE_INT == 32
8944 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8945 #else
8946 operands[4] = GEN_INT (value >> 32);
8947 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8948 #endif
8949 }")
8950
8951 (define_split
8952 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "")
8953 (match_operand:DI 1 "input_operand" ""))]
8954 "reload_completed && !TARGET_POWERPC64
8955 && gpr_or_gpr_p (operands[0], operands[1])"
8956 [(pc)]
8957 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8958
8959 (define_insn "*movdi_mfpgpr"
8960 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h,r,*f")
8961 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0,*f,r"))]
8962 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8963 && (gpc_reg_operand (operands[0], DImode)
8964 || gpc_reg_operand (operands[1], DImode))"
8965 "@
8966 mr %0,%1
8967 ld%U1%X1 %0,%1
8968 std%U0%X0 %1,%0
8969 li %0,%1
8970 lis %0,%v1
8971 #
8972 {cal|la} %0,%a1
8973 fmr %0,%1
8974 lfd%U1%X1 %0,%1
8975 stfd%U0%X0 %1,%0
8976 mf%1 %0
8977 mt%0 %1
8978 {cror 0,0,0|nop}
8979 mftgpr %0,%1
8980 mffgpr %0,%1"
8981 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
8982 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
8983
8984 (define_insn "*movdi_internal64"
8985 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
8986 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8987 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
8988 && (gpc_reg_operand (operands[0], DImode)
8989 || gpc_reg_operand (operands[1], DImode))"
8990 "@
8991 mr %0,%1
8992 ld%U1%X1 %0,%1
8993 std%U0%X0 %1,%0
8994 li %0,%1
8995 lis %0,%v1
8996 #
8997 {cal|la} %0,%a1
8998 fmr %0,%1
8999 lfd%U1%X1 %0,%1
9000 stfd%U0%X0 %1,%0
9001 mf%1 %0
9002 mt%0 %1
9003 {cror 0,0,0|nop}"
9004 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
9005 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
9006
9007 ;; immediate value valid for a single instruction hiding in a const_double
9008 (define_insn ""
9009 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9010 (match_operand:DI 1 "const_double_operand" "F"))]
9011 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
9012 && GET_CODE (operands[1]) == CONST_DOUBLE
9013 && num_insns_constant (operands[1], DImode) == 1"
9014 "*
9015 {
9016 return ((unsigned HOST_WIDE_INT)
9017 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
9018 ? \"li %0,%1\" : \"lis %0,%v1\";
9019 }")
9020
9021 ;; Generate all one-bits and clear left or right.
9022 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9023 (define_split
9024 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9025 (match_operand:DI 1 "mask64_operand" ""))]
9026 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9027 [(set (match_dup 0) (const_int -1))
9028 (set (match_dup 0)
9029 (and:DI (rotate:DI (match_dup 0)
9030 (const_int 0))
9031 (match_dup 1)))]
9032 "")
9033
9034 ;; Split a load of a large constant into the appropriate five-instruction
9035 ;; sequence. Handle anything in a constant number of insns.
9036 ;; When non-easy constants can go in the TOC, this should use
9037 ;; easy_fp_constant predicate.
9038 (define_split
9039 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9040 (match_operand:DI 1 "const_int_operand" ""))]
9041 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9042 [(set (match_dup 0) (match_dup 2))
9043 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9044 "
9045 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9046
9047 if (tem == operands[0])
9048 DONE;
9049 else
9050 FAIL;
9051 }")
9052
9053 (define_split
9054 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9055 (match_operand:DI 1 "const_double_operand" ""))]
9056 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9057 [(set (match_dup 0) (match_dup 2))
9058 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9059 "
9060 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9061
9062 if (tem == operands[0])
9063 DONE;
9064 else
9065 FAIL;
9066 }")
9067 \f
9068 ;; TImode is similar, except that we usually want to compute the address into
9069 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
9070 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
9071
9072 ;; We say that MQ is clobbered in the last alternative because the first
9073 ;; alternative would never get used otherwise since it would need a reload
9074 ;; while the 2nd alternative would not. We put memory cases first so they
9075 ;; are preferred. Otherwise, we'd try to reload the output instead of
9076 ;; giving the SCRATCH mq.
9077
9078 (define_insn "*movti_power"
9079 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
9080 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
9081 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
9082 "TARGET_POWER && ! TARGET_POWERPC64
9083 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9084 "*
9085 {
9086 switch (which_alternative)
9087 {
9088 default:
9089 gcc_unreachable ();
9090
9091 case 0:
9092 if (TARGET_STRING)
9093 return \"{stsi|stswi} %1,%P0,16\";
9094 case 1:
9095 case 2:
9096 return \"#\";
9097 case 3:
9098 /* If the address is not used in the output, we can use lsi. Otherwise,
9099 fall through to generating four loads. */
9100 if (TARGET_STRING
9101 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9102 return \"{lsi|lswi} %0,%P1,16\";
9103 /* ... fall through ... */
9104 case 4:
9105 case 5:
9106 return \"#\";
9107 }
9108 }"
9109 [(set_attr "type" "store,store,*,load,load,*")])
9110
9111 (define_insn "*movti_string"
9112 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
9113 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
9114 "! TARGET_POWER && ! TARGET_POWERPC64
9115 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9116 "*
9117 {
9118 switch (which_alternative)
9119 {
9120 default:
9121 gcc_unreachable ();
9122 case 0:
9123 if (TARGET_STRING)
9124 return \"{stsi|stswi} %1,%P0,16\";
9125 case 1:
9126 case 2:
9127 return \"#\";
9128 case 3:
9129 /* If the address is not used in the output, we can use lsi. Otherwise,
9130 fall through to generating four loads. */
9131 if (TARGET_STRING
9132 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9133 return \"{lsi|lswi} %0,%P1,16\";
9134 /* ... fall through ... */
9135 case 4:
9136 case 5:
9137 return \"#\";
9138 }
9139 }"
9140 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")])
9141
9142 (define_insn "*movti_ppc64"
9143 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
9144 (match_operand:TI 1 "input_operand" "r,r,m"))]
9145 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
9146 || gpc_reg_operand (operands[1], TImode))"
9147 "#"
9148 [(set_attr "type" "*,load,store")])
9149
9150 (define_split
9151 [(set (match_operand:TI 0 "gpc_reg_operand" "")
9152 (match_operand:TI 1 "const_double_operand" ""))]
9153 "TARGET_POWERPC64"
9154 [(set (match_dup 2) (match_dup 4))
9155 (set (match_dup 3) (match_dup 5))]
9156 "
9157 {
9158 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9159 TImode);
9160 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9161 TImode);
9162 if (GET_CODE (operands[1]) == CONST_DOUBLE)
9163 {
9164 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9165 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9166 }
9167 else if (GET_CODE (operands[1]) == CONST_INT)
9168 {
9169 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9170 operands[5] = operands[1];
9171 }
9172 else
9173 FAIL;
9174 }")
9175
9176 (define_split
9177 [(set (match_operand:TI 0 "nonimmediate_operand" "")
9178 (match_operand:TI 1 "input_operand" ""))]
9179 "reload_completed
9180 && gpr_or_gpr_p (operands[0], operands[1])"
9181 [(pc)]
9182 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9183 \f
9184 (define_expand "load_multiple"
9185 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9186 (match_operand:SI 1 "" ""))
9187 (use (match_operand:SI 2 "" ""))])]
9188 "TARGET_STRING && !TARGET_POWERPC64"
9189 "
9190 {
9191 int regno;
9192 int count;
9193 rtx op1;
9194 int i;
9195
9196 /* Support only loading a constant number of fixed-point registers from
9197 memory and only bother with this if more than two; the machine
9198 doesn't support more than eight. */
9199 if (GET_CODE (operands[2]) != CONST_INT
9200 || INTVAL (operands[2]) <= 2
9201 || INTVAL (operands[2]) > 8
9202 || GET_CODE (operands[1]) != MEM
9203 || GET_CODE (operands[0]) != REG
9204 || REGNO (operands[0]) >= 32)
9205 FAIL;
9206
9207 count = INTVAL (operands[2]);
9208 regno = REGNO (operands[0]);
9209
9210 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9211 op1 = replace_equiv_address (operands[1],
9212 force_reg (SImode, XEXP (operands[1], 0)));
9213
9214 for (i = 0; i < count; i++)
9215 XVECEXP (operands[3], 0, i)
9216 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
9217 adjust_address_nv (op1, SImode, i * 4));
9218 }")
9219
9220 (define_insn "*ldmsi8"
9221 [(match_parallel 0 "load_multiple_operation"
9222 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9223 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9224 (set (match_operand:SI 3 "gpc_reg_operand" "")
9225 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9226 (set (match_operand:SI 4 "gpc_reg_operand" "")
9227 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9228 (set (match_operand:SI 5 "gpc_reg_operand" "")
9229 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9230 (set (match_operand:SI 6 "gpc_reg_operand" "")
9231 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9232 (set (match_operand:SI 7 "gpc_reg_operand" "")
9233 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9234 (set (match_operand:SI 8 "gpc_reg_operand" "")
9235 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9236 (set (match_operand:SI 9 "gpc_reg_operand" "")
9237 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9238 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9239 "*
9240 { return rs6000_output_load_multiple (operands); }"
9241 [(set_attr "type" "load_ux")
9242 (set_attr "length" "32")])
9243
9244 (define_insn "*ldmsi7"
9245 [(match_parallel 0 "load_multiple_operation"
9246 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9247 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9248 (set (match_operand:SI 3 "gpc_reg_operand" "")
9249 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9250 (set (match_operand:SI 4 "gpc_reg_operand" "")
9251 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9252 (set (match_operand:SI 5 "gpc_reg_operand" "")
9253 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9254 (set (match_operand:SI 6 "gpc_reg_operand" "")
9255 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9256 (set (match_operand:SI 7 "gpc_reg_operand" "")
9257 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9258 (set (match_operand:SI 8 "gpc_reg_operand" "")
9259 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9260 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9261 "*
9262 { return rs6000_output_load_multiple (operands); }"
9263 [(set_attr "type" "load_ux")
9264 (set_attr "length" "32")])
9265
9266 (define_insn "*ldmsi6"
9267 [(match_parallel 0 "load_multiple_operation"
9268 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9269 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9270 (set (match_operand:SI 3 "gpc_reg_operand" "")
9271 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9272 (set (match_operand:SI 4 "gpc_reg_operand" "")
9273 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9274 (set (match_operand:SI 5 "gpc_reg_operand" "")
9275 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9276 (set (match_operand:SI 6 "gpc_reg_operand" "")
9277 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9278 (set (match_operand:SI 7 "gpc_reg_operand" "")
9279 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9280 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9281 "*
9282 { return rs6000_output_load_multiple (operands); }"
9283 [(set_attr "type" "load_ux")
9284 (set_attr "length" "32")])
9285
9286 (define_insn "*ldmsi5"
9287 [(match_parallel 0 "load_multiple_operation"
9288 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9289 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9290 (set (match_operand:SI 3 "gpc_reg_operand" "")
9291 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9292 (set (match_operand:SI 4 "gpc_reg_operand" "")
9293 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9294 (set (match_operand:SI 5 "gpc_reg_operand" "")
9295 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9296 (set (match_operand:SI 6 "gpc_reg_operand" "")
9297 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9298 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9299 "*
9300 { return rs6000_output_load_multiple (operands); }"
9301 [(set_attr "type" "load_ux")
9302 (set_attr "length" "32")])
9303
9304 (define_insn "*ldmsi4"
9305 [(match_parallel 0 "load_multiple_operation"
9306 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9307 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9308 (set (match_operand:SI 3 "gpc_reg_operand" "")
9309 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9310 (set (match_operand:SI 4 "gpc_reg_operand" "")
9311 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9312 (set (match_operand:SI 5 "gpc_reg_operand" "")
9313 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9314 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9315 "*
9316 { return rs6000_output_load_multiple (operands); }"
9317 [(set_attr "type" "load_ux")
9318 (set_attr "length" "32")])
9319
9320 (define_insn "*ldmsi3"
9321 [(match_parallel 0 "load_multiple_operation"
9322 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9323 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9324 (set (match_operand:SI 3 "gpc_reg_operand" "")
9325 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9326 (set (match_operand:SI 4 "gpc_reg_operand" "")
9327 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9328 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9329 "*
9330 { return rs6000_output_load_multiple (operands); }"
9331 [(set_attr "type" "load_ux")
9332 (set_attr "length" "32")])
9333
9334 (define_expand "store_multiple"
9335 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9336 (match_operand:SI 1 "" ""))
9337 (clobber (scratch:SI))
9338 (use (match_operand:SI 2 "" ""))])]
9339 "TARGET_STRING && !TARGET_POWERPC64"
9340 "
9341 {
9342 int regno;
9343 int count;
9344 rtx to;
9345 rtx op0;
9346 int i;
9347
9348 /* Support only storing a constant number of fixed-point registers to
9349 memory and only bother with this if more than two; the machine
9350 doesn't support more than eight. */
9351 if (GET_CODE (operands[2]) != CONST_INT
9352 || INTVAL (operands[2]) <= 2
9353 || INTVAL (operands[2]) > 8
9354 || GET_CODE (operands[0]) != MEM
9355 || GET_CODE (operands[1]) != REG
9356 || REGNO (operands[1]) >= 32)
9357 FAIL;
9358
9359 count = INTVAL (operands[2]);
9360 regno = REGNO (operands[1]);
9361
9362 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
9363 to = force_reg (SImode, XEXP (operands[0], 0));
9364 op0 = replace_equiv_address (operands[0], to);
9365
9366 XVECEXP (operands[3], 0, 0)
9367 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
9368 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
9369 gen_rtx_SCRATCH (SImode));
9370
9371 for (i = 1; i < count; i++)
9372 XVECEXP (operands[3], 0, i + 1)
9373 = gen_rtx_SET (VOIDmode,
9374 adjust_address_nv (op0, SImode, i * 4),
9375 gen_rtx_REG (SImode, regno + i));
9376 }")
9377
9378 (define_insn "*stmsi8"
9379 [(match_parallel 0 "store_multiple_operation"
9380 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9381 (match_operand:SI 2 "gpc_reg_operand" "r"))
9382 (clobber (match_scratch:SI 3 "=X"))
9383 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9384 (match_operand:SI 4 "gpc_reg_operand" "r"))
9385 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9386 (match_operand:SI 5 "gpc_reg_operand" "r"))
9387 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9388 (match_operand:SI 6 "gpc_reg_operand" "r"))
9389 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9390 (match_operand:SI 7 "gpc_reg_operand" "r"))
9391 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9392 (match_operand:SI 8 "gpc_reg_operand" "r"))
9393 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9394 (match_operand:SI 9 "gpc_reg_operand" "r"))
9395 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9396 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9397 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9398 "{stsi|stswi} %2,%1,%O0"
9399 [(set_attr "type" "store_ux")])
9400
9401 (define_insn "*stmsi7"
9402 [(match_parallel 0 "store_multiple_operation"
9403 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9404 (match_operand:SI 2 "gpc_reg_operand" "r"))
9405 (clobber (match_scratch:SI 3 "=X"))
9406 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9407 (match_operand:SI 4 "gpc_reg_operand" "r"))
9408 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9409 (match_operand:SI 5 "gpc_reg_operand" "r"))
9410 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9411 (match_operand:SI 6 "gpc_reg_operand" "r"))
9412 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9413 (match_operand:SI 7 "gpc_reg_operand" "r"))
9414 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9415 (match_operand:SI 8 "gpc_reg_operand" "r"))
9416 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9417 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9418 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9419 "{stsi|stswi} %2,%1,%O0"
9420 [(set_attr "type" "store_ux")])
9421
9422 (define_insn "*stmsi6"
9423 [(match_parallel 0 "store_multiple_operation"
9424 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9425 (match_operand:SI 2 "gpc_reg_operand" "r"))
9426 (clobber (match_scratch:SI 3 "=X"))
9427 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9428 (match_operand:SI 4 "gpc_reg_operand" "r"))
9429 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9430 (match_operand:SI 5 "gpc_reg_operand" "r"))
9431 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9432 (match_operand:SI 6 "gpc_reg_operand" "r"))
9433 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9434 (match_operand:SI 7 "gpc_reg_operand" "r"))
9435 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9436 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9437 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9438 "{stsi|stswi} %2,%1,%O0"
9439 [(set_attr "type" "store_ux")])
9440
9441 (define_insn "*stmsi5"
9442 [(match_parallel 0 "store_multiple_operation"
9443 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9444 (match_operand:SI 2 "gpc_reg_operand" "r"))
9445 (clobber (match_scratch:SI 3 "=X"))
9446 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9447 (match_operand:SI 4 "gpc_reg_operand" "r"))
9448 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9449 (match_operand:SI 5 "gpc_reg_operand" "r"))
9450 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9451 (match_operand:SI 6 "gpc_reg_operand" "r"))
9452 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9453 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9454 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9455 "{stsi|stswi} %2,%1,%O0"
9456 [(set_attr "type" "store_ux")])
9457
9458 (define_insn "*stmsi4"
9459 [(match_parallel 0 "store_multiple_operation"
9460 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9461 (match_operand:SI 2 "gpc_reg_operand" "r"))
9462 (clobber (match_scratch:SI 3 "=X"))
9463 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9464 (match_operand:SI 4 "gpc_reg_operand" "r"))
9465 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9466 (match_operand:SI 5 "gpc_reg_operand" "r"))
9467 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9468 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9469 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9470 "{stsi|stswi} %2,%1,%O0"
9471 [(set_attr "type" "store_ux")])
9472
9473 (define_insn "*stmsi3"
9474 [(match_parallel 0 "store_multiple_operation"
9475 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9476 (match_operand:SI 2 "gpc_reg_operand" "r"))
9477 (clobber (match_scratch:SI 3 "=X"))
9478 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9479 (match_operand:SI 4 "gpc_reg_operand" "r"))
9480 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9481 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9482 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9483 "{stsi|stswi} %2,%1,%O0"
9484 [(set_attr "type" "store_ux")])
9485
9486 (define_insn "*stmsi8_power"
9487 [(match_parallel 0 "store_multiple_operation"
9488 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9489 (match_operand:SI 2 "gpc_reg_operand" "r"))
9490 (clobber (match_scratch:SI 3 "=q"))
9491 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9492 (match_operand:SI 4 "gpc_reg_operand" "r"))
9493 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9494 (match_operand:SI 5 "gpc_reg_operand" "r"))
9495 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9496 (match_operand:SI 6 "gpc_reg_operand" "r"))
9497 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9498 (match_operand:SI 7 "gpc_reg_operand" "r"))
9499 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9500 (match_operand:SI 8 "gpc_reg_operand" "r"))
9501 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9502 (match_operand:SI 9 "gpc_reg_operand" "r"))
9503 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9504 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9505 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9506 "{stsi|stswi} %2,%1,%O0"
9507 [(set_attr "type" "store_ux")])
9508
9509 (define_insn "*stmsi7_power"
9510 [(match_parallel 0 "store_multiple_operation"
9511 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9512 (match_operand:SI 2 "gpc_reg_operand" "r"))
9513 (clobber (match_scratch:SI 3 "=q"))
9514 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9515 (match_operand:SI 4 "gpc_reg_operand" "r"))
9516 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9517 (match_operand:SI 5 "gpc_reg_operand" "r"))
9518 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9519 (match_operand:SI 6 "gpc_reg_operand" "r"))
9520 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9521 (match_operand:SI 7 "gpc_reg_operand" "r"))
9522 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9523 (match_operand:SI 8 "gpc_reg_operand" "r"))
9524 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9525 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9526 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9527 "{stsi|stswi} %2,%1,%O0"
9528 [(set_attr "type" "store_ux")])
9529
9530 (define_insn "*stmsi6_power"
9531 [(match_parallel 0 "store_multiple_operation"
9532 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9533 (match_operand:SI 2 "gpc_reg_operand" "r"))
9534 (clobber (match_scratch:SI 3 "=q"))
9535 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9536 (match_operand:SI 4 "gpc_reg_operand" "r"))
9537 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9538 (match_operand:SI 5 "gpc_reg_operand" "r"))
9539 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9540 (match_operand:SI 6 "gpc_reg_operand" "r"))
9541 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9542 (match_operand:SI 7 "gpc_reg_operand" "r"))
9543 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9544 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9545 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9546 "{stsi|stswi} %2,%1,%O0"
9547 [(set_attr "type" "store_ux")])
9548
9549 (define_insn "*stmsi5_power"
9550 [(match_parallel 0 "store_multiple_operation"
9551 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9552 (match_operand:SI 2 "gpc_reg_operand" "r"))
9553 (clobber (match_scratch:SI 3 "=q"))
9554 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9555 (match_operand:SI 4 "gpc_reg_operand" "r"))
9556 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9557 (match_operand:SI 5 "gpc_reg_operand" "r"))
9558 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9559 (match_operand:SI 6 "gpc_reg_operand" "r"))
9560 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9561 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9562 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9563 "{stsi|stswi} %2,%1,%O0"
9564 [(set_attr "type" "store_ux")])
9565
9566 (define_insn "*stmsi4_power"
9567 [(match_parallel 0 "store_multiple_operation"
9568 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9569 (match_operand:SI 2 "gpc_reg_operand" "r"))
9570 (clobber (match_scratch:SI 3 "=q"))
9571 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9572 (match_operand:SI 4 "gpc_reg_operand" "r"))
9573 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9574 (match_operand:SI 5 "gpc_reg_operand" "r"))
9575 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9576 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9577 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9578 "{stsi|stswi} %2,%1,%O0"
9579 [(set_attr "type" "store_ux")])
9580
9581 (define_insn "*stmsi3_power"
9582 [(match_parallel 0 "store_multiple_operation"
9583 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9584 (match_operand:SI 2 "gpc_reg_operand" "r"))
9585 (clobber (match_scratch:SI 3 "=q"))
9586 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9587 (match_operand:SI 4 "gpc_reg_operand" "r"))
9588 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9589 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9590 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9591 "{stsi|stswi} %2,%1,%O0"
9592 [(set_attr "type" "store_ux")])
9593 \f
9594 (define_expand "setmemsi"
9595 [(parallel [(set (match_operand:BLK 0 "" "")
9596 (match_operand 2 "const_int_operand" ""))
9597 (use (match_operand:SI 1 "" ""))
9598 (use (match_operand:SI 3 "" ""))])]
9599 ""
9600 "
9601 {
9602 /* If value to set is not zero, use the library routine. */
9603 if (operands[2] != const0_rtx)
9604 FAIL;
9605
9606 if (expand_block_clear (operands))
9607 DONE;
9608 else
9609 FAIL;
9610 }")
9611
9612 ;; String/block move insn.
9613 ;; Argument 0 is the destination
9614 ;; Argument 1 is the source
9615 ;; Argument 2 is the length
9616 ;; Argument 3 is the alignment
9617
9618 (define_expand "movmemsi"
9619 [(parallel [(set (match_operand:BLK 0 "" "")
9620 (match_operand:BLK 1 "" ""))
9621 (use (match_operand:SI 2 "" ""))
9622 (use (match_operand:SI 3 "" ""))])]
9623 ""
9624 "
9625 {
9626 if (expand_block_move (operands))
9627 DONE;
9628 else
9629 FAIL;
9630 }")
9631
9632 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9633 ;; register allocator doesn't have a clue about allocating 8 word registers.
9634 ;; rD/rS = r5 is preferred, efficient form.
9635 (define_expand "movmemsi_8reg"
9636 [(parallel [(set (match_operand 0 "" "")
9637 (match_operand 1 "" ""))
9638 (use (match_operand 2 "" ""))
9639 (use (match_operand 3 "" ""))
9640 (clobber (reg:SI 5))
9641 (clobber (reg:SI 6))
9642 (clobber (reg:SI 7))
9643 (clobber (reg:SI 8))
9644 (clobber (reg:SI 9))
9645 (clobber (reg:SI 10))
9646 (clobber (reg:SI 11))
9647 (clobber (reg:SI 12))
9648 (clobber (match_scratch:SI 4 ""))])]
9649 "TARGET_STRING"
9650 "")
9651
9652 (define_insn ""
9653 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9654 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9655 (use (match_operand:SI 2 "immediate_operand" "i"))
9656 (use (match_operand:SI 3 "immediate_operand" "i"))
9657 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9658 (clobber (reg:SI 6))
9659 (clobber (reg:SI 7))
9660 (clobber (reg:SI 8))
9661 (clobber (reg:SI 9))
9662 (clobber (reg:SI 10))
9663 (clobber (reg:SI 11))
9664 (clobber (reg:SI 12))
9665 (clobber (match_scratch:SI 5 "=q"))]
9666 "TARGET_STRING && TARGET_POWER
9667 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9668 || INTVAL (operands[2]) == 0)
9669 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9670 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9671 && REGNO (operands[4]) == 5"
9672 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9673 [(set_attr "type" "store_ux")
9674 (set_attr "length" "8")])
9675
9676 (define_insn ""
9677 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9678 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9679 (use (match_operand:SI 2 "immediate_operand" "i"))
9680 (use (match_operand:SI 3 "immediate_operand" "i"))
9681 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9682 (clobber (reg:SI 6))
9683 (clobber (reg:SI 7))
9684 (clobber (reg:SI 8))
9685 (clobber (reg:SI 9))
9686 (clobber (reg:SI 10))
9687 (clobber (reg:SI 11))
9688 (clobber (reg:SI 12))
9689 (clobber (match_scratch:SI 5 "=X"))]
9690 "TARGET_STRING && ! TARGET_POWER
9691 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9692 || INTVAL (operands[2]) == 0)
9693 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9694 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9695 && REGNO (operands[4]) == 5"
9696 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9697 [(set_attr "type" "store_ux")
9698 (set_attr "length" "8")])
9699
9700 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9701 ;; register allocator doesn't have a clue about allocating 6 word registers.
9702 ;; rD/rS = r5 is preferred, efficient form.
9703 (define_expand "movmemsi_6reg"
9704 [(parallel [(set (match_operand 0 "" "")
9705 (match_operand 1 "" ""))
9706 (use (match_operand 2 "" ""))
9707 (use (match_operand 3 "" ""))
9708 (clobber (reg:SI 5))
9709 (clobber (reg:SI 6))
9710 (clobber (reg:SI 7))
9711 (clobber (reg:SI 8))
9712 (clobber (reg:SI 9))
9713 (clobber (reg:SI 10))
9714 (clobber (match_scratch:SI 4 ""))])]
9715 "TARGET_STRING"
9716 "")
9717
9718 (define_insn ""
9719 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9720 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9721 (use (match_operand:SI 2 "immediate_operand" "i"))
9722 (use (match_operand:SI 3 "immediate_operand" "i"))
9723 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9724 (clobber (reg:SI 6))
9725 (clobber (reg:SI 7))
9726 (clobber (reg:SI 8))
9727 (clobber (reg:SI 9))
9728 (clobber (reg:SI 10))
9729 (clobber (match_scratch:SI 5 "=q"))]
9730 "TARGET_STRING && TARGET_POWER
9731 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9732 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9733 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9734 && REGNO (operands[4]) == 5"
9735 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9736 [(set_attr "type" "store_ux")
9737 (set_attr "length" "8")])
9738
9739 (define_insn ""
9740 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9741 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9742 (use (match_operand:SI 2 "immediate_operand" "i"))
9743 (use (match_operand:SI 3 "immediate_operand" "i"))
9744 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9745 (clobber (reg:SI 6))
9746 (clobber (reg:SI 7))
9747 (clobber (reg:SI 8))
9748 (clobber (reg:SI 9))
9749 (clobber (reg:SI 10))
9750 (clobber (match_scratch:SI 5 "=X"))]
9751 "TARGET_STRING && ! TARGET_POWER
9752 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9753 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9754 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9755 && REGNO (operands[4]) == 5"
9756 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9757 [(set_attr "type" "store_ux")
9758 (set_attr "length" "8")])
9759
9760 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9761 ;; problems with TImode.
9762 ;; rD/rS = r5 is preferred, efficient form.
9763 (define_expand "movmemsi_4reg"
9764 [(parallel [(set (match_operand 0 "" "")
9765 (match_operand 1 "" ""))
9766 (use (match_operand 2 "" ""))
9767 (use (match_operand 3 "" ""))
9768 (clobber (reg:SI 5))
9769 (clobber (reg:SI 6))
9770 (clobber (reg:SI 7))
9771 (clobber (reg:SI 8))
9772 (clobber (match_scratch:SI 4 ""))])]
9773 "TARGET_STRING"
9774 "")
9775
9776 (define_insn ""
9777 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9778 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9779 (use (match_operand:SI 2 "immediate_operand" "i"))
9780 (use (match_operand:SI 3 "immediate_operand" "i"))
9781 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9782 (clobber (reg:SI 6))
9783 (clobber (reg:SI 7))
9784 (clobber (reg:SI 8))
9785 (clobber (match_scratch:SI 5 "=q"))]
9786 "TARGET_STRING && TARGET_POWER
9787 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9788 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9789 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9790 && REGNO (operands[4]) == 5"
9791 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9792 [(set_attr "type" "store_ux")
9793 (set_attr "length" "8")])
9794
9795 (define_insn ""
9796 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9797 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9798 (use (match_operand:SI 2 "immediate_operand" "i"))
9799 (use (match_operand:SI 3 "immediate_operand" "i"))
9800 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9801 (clobber (reg:SI 6))
9802 (clobber (reg:SI 7))
9803 (clobber (reg:SI 8))
9804 (clobber (match_scratch:SI 5 "=X"))]
9805 "TARGET_STRING && ! TARGET_POWER
9806 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9807 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9808 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9809 && REGNO (operands[4]) == 5"
9810 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9811 [(set_attr "type" "store_ux")
9812 (set_attr "length" "8")])
9813
9814 ;; Move up to 8 bytes at a time.
9815 (define_expand "movmemsi_2reg"
9816 [(parallel [(set (match_operand 0 "" "")
9817 (match_operand 1 "" ""))
9818 (use (match_operand 2 "" ""))
9819 (use (match_operand 3 "" ""))
9820 (clobber (match_scratch:DI 4 ""))
9821 (clobber (match_scratch:SI 5 ""))])]
9822 "TARGET_STRING && ! TARGET_POWERPC64"
9823 "")
9824
9825 (define_insn ""
9826 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9827 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9828 (use (match_operand:SI 2 "immediate_operand" "i"))
9829 (use (match_operand:SI 3 "immediate_operand" "i"))
9830 (clobber (match_scratch:DI 4 "=&r"))
9831 (clobber (match_scratch:SI 5 "=q"))]
9832 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9833 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9834 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9835 [(set_attr "type" "store_ux")
9836 (set_attr "length" "8")])
9837
9838 (define_insn ""
9839 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9840 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9841 (use (match_operand:SI 2 "immediate_operand" "i"))
9842 (use (match_operand:SI 3 "immediate_operand" "i"))
9843 (clobber (match_scratch:DI 4 "=&r"))
9844 (clobber (match_scratch:SI 5 "=X"))]
9845 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9846 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9847 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9848 [(set_attr "type" "store_ux")
9849 (set_attr "length" "8")])
9850
9851 ;; Move up to 4 bytes at a time.
9852 (define_expand "movmemsi_1reg"
9853 [(parallel [(set (match_operand 0 "" "")
9854 (match_operand 1 "" ""))
9855 (use (match_operand 2 "" ""))
9856 (use (match_operand 3 "" ""))
9857 (clobber (match_scratch:SI 4 ""))
9858 (clobber (match_scratch:SI 5 ""))])]
9859 "TARGET_STRING"
9860 "")
9861
9862 (define_insn ""
9863 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9864 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9865 (use (match_operand:SI 2 "immediate_operand" "i"))
9866 (use (match_operand:SI 3 "immediate_operand" "i"))
9867 (clobber (match_scratch:SI 4 "=&r"))
9868 (clobber (match_scratch:SI 5 "=q"))]
9869 "TARGET_STRING && TARGET_POWER
9870 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9871 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9872 [(set_attr "type" "store_ux")
9873 (set_attr "length" "8")])
9874
9875 (define_insn ""
9876 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9877 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9878 (use (match_operand:SI 2 "immediate_operand" "i"))
9879 (use (match_operand:SI 3 "immediate_operand" "i"))
9880 (clobber (match_scratch:SI 4 "=&r"))
9881 (clobber (match_scratch:SI 5 "=X"))]
9882 "TARGET_STRING && ! TARGET_POWER
9883 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9884 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9885 [(set_attr "type" "store_ux")
9886 (set_attr "length" "8")])
9887 \f
9888 ;; Define insns that do load or store with update. Some of these we can
9889 ;; get by using pre-decrement or pre-increment, but the hardware can also
9890 ;; do cases where the increment is not the size of the object.
9891 ;;
9892 ;; In all these cases, we use operands 0 and 1 for the register being
9893 ;; incremented because those are the operands that local-alloc will
9894 ;; tie and these are the pair most likely to be tieable (and the ones
9895 ;; that will benefit the most).
9896
9897 (define_insn "*movdi_update1"
9898 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9899 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9900 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9901 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9902 (plus:DI (match_dup 1) (match_dup 2)))]
9903 "TARGET_POWERPC64 && TARGET_UPDATE"
9904 "@
9905 ldux %3,%0,%2
9906 ldu %3,%2(%0)"
9907 [(set_attr "type" "load_ux,load_u")])
9908
9909 (define_insn "movdi_<mode>_update"
9910 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9911 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9912 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9913 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9914 (plus:P (match_dup 1) (match_dup 2)))]
9915 "TARGET_POWERPC64 && TARGET_UPDATE"
9916 "@
9917 stdux %3,%0,%2
9918 stdu %3,%2(%0)"
9919 [(set_attr "type" "store_ux,store_u")])
9920
9921 (define_insn "*movsi_update1"
9922 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9923 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9924 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9925 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9926 (plus:SI (match_dup 1) (match_dup 2)))]
9927 "TARGET_UPDATE"
9928 "@
9929 {lux|lwzux} %3,%0,%2
9930 {lu|lwzu} %3,%2(%0)"
9931 [(set_attr "type" "load_ux,load_u")])
9932
9933 (define_insn "*movsi_update2"
9934 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9935 (sign_extend:DI
9936 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9937 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9938 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9939 (plus:DI (match_dup 1) (match_dup 2)))]
9940 "TARGET_POWERPC64"
9941 "lwaux %3,%0,%2"
9942 [(set_attr "type" "load_ext_ux")])
9943
9944 (define_insn "movsi_update"
9945 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9946 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9947 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9948 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9949 (plus:SI (match_dup 1) (match_dup 2)))]
9950 "TARGET_UPDATE"
9951 "@
9952 {stux|stwux} %3,%0,%2
9953 {stu|stwu} %3,%2(%0)"
9954 [(set_attr "type" "store_ux,store_u")])
9955
9956 (define_insn "*movhi_update1"
9957 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9958 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9959 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9960 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9961 (plus:SI (match_dup 1) (match_dup 2)))]
9962 "TARGET_UPDATE"
9963 "@
9964 lhzux %3,%0,%2
9965 lhzu %3,%2(%0)"
9966 [(set_attr "type" "load_ux,load_u")])
9967
9968 (define_insn "*movhi_update2"
9969 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9970 (zero_extend:SI
9971 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9972 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9973 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9974 (plus:SI (match_dup 1) (match_dup 2)))]
9975 "TARGET_UPDATE"
9976 "@
9977 lhzux %3,%0,%2
9978 lhzu %3,%2(%0)"
9979 [(set_attr "type" "load_ux,load_u")])
9980
9981 (define_insn "*movhi_update3"
9982 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9983 (sign_extend:SI
9984 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9985 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9986 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9987 (plus:SI (match_dup 1) (match_dup 2)))]
9988 "TARGET_UPDATE"
9989 "@
9990 lhaux %3,%0,%2
9991 lhau %3,%2(%0)"
9992 [(set_attr "type" "load_ext_ux,load_ext_u")])
9993
9994 (define_insn "*movhi_update4"
9995 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9996 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9997 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9998 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9999 (plus:SI (match_dup 1) (match_dup 2)))]
10000 "TARGET_UPDATE"
10001 "@
10002 sthux %3,%0,%2
10003 sthu %3,%2(%0)"
10004 [(set_attr "type" "store_ux,store_u")])
10005
10006 (define_insn "*movqi_update1"
10007 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
10008 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10009 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10010 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10011 (plus:SI (match_dup 1) (match_dup 2)))]
10012 "TARGET_UPDATE"
10013 "@
10014 lbzux %3,%0,%2
10015 lbzu %3,%2(%0)"
10016 [(set_attr "type" "load_ux,load_u")])
10017
10018 (define_insn "*movqi_update2"
10019 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10020 (zero_extend:SI
10021 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10022 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10023 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10024 (plus:SI (match_dup 1) (match_dup 2)))]
10025 "TARGET_UPDATE"
10026 "@
10027 lbzux %3,%0,%2
10028 lbzu %3,%2(%0)"
10029 [(set_attr "type" "load_ux,load_u")])
10030
10031 (define_insn "*movqi_update3"
10032 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10033 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10034 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
10035 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10036 (plus:SI (match_dup 1) (match_dup 2)))]
10037 "TARGET_UPDATE"
10038 "@
10039 stbux %3,%0,%2
10040 stbu %3,%2(%0)"
10041 [(set_attr "type" "store_ux,store_u")])
10042
10043 (define_insn "*movsf_update1"
10044 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
10045 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10046 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10047 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10048 (plus:SI (match_dup 1) (match_dup 2)))]
10049 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE"
10050 "@
10051 lfsux %3,%0,%2
10052 lfsu %3,%2(%0)"
10053 [(set_attr "type" "fpload_ux,fpload_u")])
10054
10055 (define_insn "*movsf_update2"
10056 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10057 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10058 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10059 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10060 (plus:SI (match_dup 1) (match_dup 2)))]
10061 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE"
10062 "@
10063 stfsux %3,%0,%2
10064 stfsu %3,%2(%0)"
10065 [(set_attr "type" "fpstore_ux,fpstore_u")])
10066
10067 (define_insn "*movsf_update3"
10068 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10069 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10070 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10071 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10072 (plus:SI (match_dup 1) (match_dup 2)))]
10073 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
10074 "@
10075 {lux|lwzux} %3,%0,%2
10076 {lu|lwzu} %3,%2(%0)"
10077 [(set_attr "type" "load_ux,load_u")])
10078
10079 (define_insn "*movsf_update4"
10080 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10081 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10082 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10083 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10084 (plus:SI (match_dup 1) (match_dup 2)))]
10085 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
10086 "@
10087 {stux|stwux} %3,%0,%2
10088 {stu|stwu} %3,%2(%0)"
10089 [(set_attr "type" "store_ux,store_u")])
10090
10091 (define_insn "*movdf_update1"
10092 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
10093 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10094 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10095 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10096 (plus:SI (match_dup 1) (match_dup 2)))]
10097 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE"
10098 "@
10099 lfdux %3,%0,%2
10100 lfdu %3,%2(%0)"
10101 [(set_attr "type" "fpload_ux,fpload_u")])
10102
10103 (define_insn "*movdf_update2"
10104 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10105 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10106 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
10107 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10108 (plus:SI (match_dup 1) (match_dup 2)))]
10109 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE"
10110 "@
10111 stfdux %3,%0,%2
10112 stfdu %3,%2(%0)"
10113 [(set_attr "type" "fpstore_ux,fpstore_u")])
10114
10115 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
10116
10117 (define_insn "*lfq_power2"
10118 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
10119 (match_operand:V2DF 1 "memory_operand" ""))]
10120 "TARGET_POWER2
10121 && TARGET_HARD_FLOAT && TARGET_FPRS"
10122 "lfq%U1%X1 %0,%1")
10123
10124 (define_peephole2
10125 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10126 (match_operand:DF 1 "memory_operand" ""))
10127 (set (match_operand:DF 2 "gpc_reg_operand" "")
10128 (match_operand:DF 3 "memory_operand" ""))]
10129 "TARGET_POWER2
10130 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
10131 && registers_ok_for_quad_peep (operands[0], operands[2])
10132 && mems_ok_for_quad_peep (operands[1], operands[3])"
10133 [(set (match_dup 0)
10134 (match_dup 1))]
10135 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
10136 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
10137
10138 (define_insn "*stfq_power2"
10139 [(set (match_operand:V2DF 0 "memory_operand" "")
10140 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
10141 "TARGET_POWER2
10142 && TARGET_HARD_FLOAT && TARGET_FPRS"
10143 "stfq%U0%X0 %1,%0")
10144
10145
10146 (define_peephole2
10147 [(set (match_operand:DF 0 "memory_operand" "")
10148 (match_operand:DF 1 "gpc_reg_operand" ""))
10149 (set (match_operand:DF 2 "memory_operand" "")
10150 (match_operand:DF 3 "gpc_reg_operand" ""))]
10151 "TARGET_POWER2
10152 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
10153 && registers_ok_for_quad_peep (operands[1], operands[3])
10154 && mems_ok_for_quad_peep (operands[0], operands[2])"
10155 [(set (match_dup 0)
10156 (match_dup 1))]
10157 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
10158 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
10159
10160 ;; After inserting conditional returns we can sometimes have
10161 ;; unnecessary register moves. Unfortunately we cannot have a
10162 ;; modeless peephole here, because some single SImode sets have early
10163 ;; clobber outputs. Although those sets expand to multi-ppc-insn
10164 ;; sequences, using get_attr_length here will smash the operands
10165 ;; array. Neither is there an early_cobbler_p predicate.
10166 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
10167 (define_peephole2
10168 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10169 (match_operand:DF 1 "any_operand" ""))
10170 (set (match_operand:DF 2 "gpc_reg_operand" "")
10171 (match_dup 0))]
10172 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10173 && peep2_reg_dead_p (2, operands[0])"
10174 [(set (match_dup 2) (match_dup 1))])
10175
10176 (define_peephole2
10177 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10178 (match_operand:SF 1 "any_operand" ""))
10179 (set (match_operand:SF 2 "gpc_reg_operand" "")
10180 (match_dup 0))]
10181 "peep2_reg_dead_p (2, operands[0])"
10182 [(set (match_dup 2) (match_dup 1))])
10183
10184 \f
10185 ;; TLS support.
10186
10187 ;; Mode attributes for different ABIs.
10188 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
10189 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
10190 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
10191 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
10192
10193 (define_insn "tls_gd_aix<TLSmode:tls_abi_suffix>"
10194 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10195 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10196 (match_operand 4 "" "g")))
10197 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10198 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10199 UNSPEC_TLSGD)
10200 (clobber (reg:SI LR_REGNO))]
10201 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10202 "addi %0,%1,%2@got@tlsgd\;bl %z3\;%."
10203 [(set_attr "type" "two")
10204 (set_attr "length" "12")])
10205
10206 (define_insn "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
10207 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10208 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10209 (match_operand 4 "" "g")))
10210 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10211 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10212 UNSPEC_TLSGD)
10213 (clobber (reg:SI LR_REGNO))]
10214 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10215 {
10216 if (flag_pic)
10217 {
10218 if (TARGET_SECURE_PLT && flag_pic == 2)
10219 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
10220 else
10221 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
10222 }
10223 else
10224 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
10225 }
10226 [(set_attr "type" "two")
10227 (set_attr "length" "8")])
10228
10229 (define_insn "tls_ld_aix<TLSmode:tls_abi_suffix>"
10230 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10231 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10232 (match_operand 3 "" "g")))
10233 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10234 UNSPEC_TLSLD)
10235 (clobber (reg:SI LR_REGNO))]
10236 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10237 "addi %0,%1,%&@got@tlsld\;bl %z2\;%."
10238 [(set_attr "length" "12")])
10239
10240 (define_insn "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
10241 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10242 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10243 (match_operand 3 "" "g")))
10244 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10245 UNSPEC_TLSLD)
10246 (clobber (reg:SI LR_REGNO))]
10247 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10248 {
10249 if (flag_pic)
10250 {
10251 if (TARGET_SECURE_PLT && flag_pic == 2)
10252 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
10253 else
10254 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
10255 }
10256 else
10257 return "addi %0,%1,%&@got@tlsld\;bl %z2";
10258 }
10259 [(set_attr "length" "8")])
10260
10261 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
10262 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10263 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10264 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10265 UNSPEC_TLSDTPREL))]
10266 "HAVE_AS_TLS"
10267 "addi %0,%1,%2@dtprel")
10268
10269 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
10270 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10271 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10272 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10273 UNSPEC_TLSDTPRELHA))]
10274 "HAVE_AS_TLS"
10275 "addis %0,%1,%2@dtprel@ha")
10276
10277 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
10278 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10279 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10280 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10281 UNSPEC_TLSDTPRELLO))]
10282 "HAVE_AS_TLS"
10283 "addi %0,%1,%2@dtprel@l")
10284
10285 (define_insn "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
10286 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10287 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10288 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10289 UNSPEC_TLSGOTDTPREL))]
10290 "HAVE_AS_TLS"
10291 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)")
10292
10293 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
10294 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10295 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10296 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10297 UNSPEC_TLSTPREL))]
10298 "HAVE_AS_TLS"
10299 "addi %0,%1,%2@tprel")
10300
10301 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
10302 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10303 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10304 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10305 UNSPEC_TLSTPRELHA))]
10306 "HAVE_AS_TLS"
10307 "addis %0,%1,%2@tprel@ha")
10308
10309 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
10310 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10311 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10312 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10313 UNSPEC_TLSTPRELLO))]
10314 "HAVE_AS_TLS"
10315 "addi %0,%1,%2@tprel@l")
10316
10317 ;; "b" output constraint here and on tls_tls input to support linker tls
10318 ;; optimization. The linker may edit the instructions emitted by a
10319 ;; tls_got_tprel/tls_tls pair to addis,addi.
10320 (define_insn "tls_got_tprel_<TLSmode:tls_abi_suffix>"
10321 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10322 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10323 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10324 UNSPEC_TLSGOTTPREL))]
10325 "HAVE_AS_TLS"
10326 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)")
10327
10328 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
10329 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10330 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10331 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10332 UNSPEC_TLSTLS))]
10333 "HAVE_AS_TLS"
10334 "add %0,%1,%2@tls")
10335
10336 \f
10337 ;; Next come insns related to the calling sequence.
10338 ;;
10339 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
10340 ;; We move the back-chain and decrement the stack pointer.
10341
10342 (define_expand "allocate_stack"
10343 [(set (match_operand 0 "gpc_reg_operand" "")
10344 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10345 (set (reg 1)
10346 (minus (reg 1) (match_dup 1)))]
10347 ""
10348 "
10349 { rtx chain = gen_reg_rtx (Pmode);
10350 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
10351 rtx neg_op0;
10352
10353 emit_move_insn (chain, stack_bot);
10354
10355 /* Check stack bounds if necessary. */
10356 if (crtl->limit_stack)
10357 {
10358 rtx available;
10359 available = expand_binop (Pmode, sub_optab,
10360 stack_pointer_rtx, stack_limit_rtx,
10361 NULL_RTX, 1, OPTAB_WIDEN);
10362 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10363 }
10364
10365 if (GET_CODE (operands[1]) != CONST_INT
10366 || INTVAL (operands[1]) < -32767
10367 || INTVAL (operands[1]) > 32768)
10368 {
10369 neg_op0 = gen_reg_rtx (Pmode);
10370 if (TARGET_32BIT)
10371 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10372 else
10373 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10374 }
10375 else
10376 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10377
10378 if (TARGET_UPDATE)
10379 {
10380 rtx insn, par, set, mem;
10381
10382 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update
10383 : gen_movdi_di_update))
10384 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
10385 chain));
10386 /* Since we didn't use gen_frame_mem to generate the MEM, grab
10387 it now and set the alias set/attributes. The above gen_*_update
10388 calls will generate a PARALLEL with the MEM set being the first
10389 operation. */
10390 par = PATTERN (insn);
10391 gcc_assert (GET_CODE (par) == PARALLEL);
10392 set = XVECEXP (par, 0, 0);
10393 gcc_assert (GET_CODE (set) == SET);
10394 mem = SET_DEST (set);
10395 gcc_assert (MEM_P (mem));
10396 MEM_NOTRAP_P (mem) = 1;
10397 set_mem_alias_set (mem, get_frame_alias_set ());
10398 }
10399
10400 else
10401 {
10402 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
10403 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
10404 emit_move_insn (gen_frame_mem (Pmode, stack_pointer_rtx), chain);
10405 }
10406
10407 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10408 DONE;
10409 }")
10410
10411 ;; These patterns say how to save and restore the stack pointer. We need not
10412 ;; save the stack pointer at function level since we are careful to
10413 ;; preserve the backchain. At block level, we have to restore the backchain
10414 ;; when we restore the stack pointer.
10415 ;;
10416 ;; For nonlocal gotos, we must save both the stack pointer and its
10417 ;; backchain and restore both. Note that in the nonlocal case, the
10418 ;; save area is a memory location.
10419
10420 (define_expand "save_stack_function"
10421 [(match_operand 0 "any_operand" "")
10422 (match_operand 1 "any_operand" "")]
10423 ""
10424 "DONE;")
10425
10426 (define_expand "restore_stack_function"
10427 [(match_operand 0 "any_operand" "")
10428 (match_operand 1 "any_operand" "")]
10429 ""
10430 "DONE;")
10431
10432 ;; Adjust stack pointer (op0) to a new value (op1).
10433 ;; First copy old stack backchain to new location, and ensure that the
10434 ;; scheduler won't reorder the sp assignment before the backchain write.
10435 (define_expand "restore_stack_block"
10436 [(set (match_dup 2) (match_dup 3))
10437 (set (match_dup 4) (match_dup 2))
10438 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
10439 (set (match_operand 0 "register_operand" "")
10440 (match_operand 1 "register_operand" ""))]
10441 ""
10442 "
10443 {
10444 operands[1] = force_reg (Pmode, operands[1]);
10445 operands[2] = gen_reg_rtx (Pmode);
10446 operands[3] = gen_frame_mem (Pmode, operands[0]);
10447 operands[4] = gen_frame_mem (Pmode, operands[1]);
10448 operands[5] = gen_frame_mem (BLKmode, operands[0]);
10449 }")
10450
10451 (define_expand "save_stack_nonlocal"
10452 [(set (match_dup 3) (match_dup 4))
10453 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10454 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
10455 ""
10456 "
10457 {
10458 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10459
10460 /* Copy the backchain to the first word, sp to the second. */
10461 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10462 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10463 operands[3] = gen_reg_rtx (Pmode);
10464 operands[4] = gen_frame_mem (Pmode, operands[1]);
10465 }")
10466
10467 (define_expand "restore_stack_nonlocal"
10468 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10469 (set (match_dup 3) (match_dup 4))
10470 (set (match_dup 5) (match_dup 2))
10471 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
10472 (set (match_operand 0 "register_operand" "") (match_dup 3))]
10473 ""
10474 "
10475 {
10476 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10477
10478 /* Restore the backchain from the first word, sp from the second. */
10479 operands[2] = gen_reg_rtx (Pmode);
10480 operands[3] = gen_reg_rtx (Pmode);
10481 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10482 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10483 operands[5] = gen_frame_mem (Pmode, operands[3]);
10484 operands[6] = gen_frame_mem (BLKmode, operands[0]);
10485 }")
10486 \f
10487 ;; TOC register handling.
10488
10489 ;; Code to initialize the TOC register...
10490
10491 (define_insn "load_toc_aix_si"
10492 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10493 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10494 (use (reg:SI 2))])]
10495 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10496 "*
10497 {
10498 char buf[30];
10499 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10500 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10501 operands[2] = gen_rtx_REG (Pmode, 2);
10502 return \"{l|lwz} %0,%1(%2)\";
10503 }"
10504 [(set_attr "type" "load")])
10505
10506 (define_insn "load_toc_aix_di"
10507 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10508 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10509 (use (reg:DI 2))])]
10510 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10511 "*
10512 {
10513 char buf[30];
10514 #ifdef TARGET_RELOCATABLE
10515 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10516 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10517 #else
10518 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10519 #endif
10520 if (TARGET_ELF)
10521 strcat (buf, \"@toc\");
10522 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10523 operands[2] = gen_rtx_REG (Pmode, 2);
10524 return \"ld %0,%1(%2)\";
10525 }"
10526 [(set_attr "type" "load")])
10527
10528 (define_insn "load_toc_v4_pic_si"
10529 [(set (reg:SI LR_REGNO)
10530 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10531 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10532 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10533 [(set_attr "type" "branch")
10534 (set_attr "length" "4")])
10535
10536 (define_insn "load_toc_v4_PIC_1"
10537 [(set (reg:SI LR_REGNO)
10538 (match_operand:SI 0 "immediate_operand" "s"))
10539 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10540 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
10541 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10542 "bcl 20,31,%0\\n%0:"
10543 [(set_attr "type" "branch")
10544 (set_attr "length" "4")])
10545
10546 (define_insn "load_toc_v4_PIC_1b"
10547 [(set (reg:SI LR_REGNO)
10548 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")]
10549 UNSPEC_TOCPTR))]
10550 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10551 "bcl 20,31,$+8\\n\\t.long %0-$"
10552 [(set_attr "type" "branch")
10553 (set_attr "length" "8")])
10554
10555 (define_insn "load_toc_v4_PIC_2"
10556 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10557 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10558 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10559 (match_operand:SI 3 "immediate_operand" "s")))))]
10560 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10561 "{l|lwz} %0,%2-%3(%1)"
10562 [(set_attr "type" "load")])
10563
10564 (define_insn "load_toc_v4_PIC_3b"
10565 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10566 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10567 (high:SI
10568 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10569 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10570 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10571 "{cau|addis} %0,%1,%2-%3@ha")
10572
10573 (define_insn "load_toc_v4_PIC_3c"
10574 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10575 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10576 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10577 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10578 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10579 "{cal|addi} %0,%1,%2-%3@l")
10580
10581 ;; If the TOC is shared over a translation unit, as happens with all
10582 ;; the kinds of PIC that we support, we need to restore the TOC
10583 ;; pointer only when jumping over units of translation.
10584 ;; On Darwin, we need to reload the picbase.
10585
10586 (define_expand "builtin_setjmp_receiver"
10587 [(use (label_ref (match_operand 0 "" "")))]
10588 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10589 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10590 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10591 "
10592 {
10593 #if TARGET_MACHO
10594 if (DEFAULT_ABI == ABI_DARWIN)
10595 {
10596 const char *picbase = machopic_function_base_name ();
10597 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
10598 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10599 rtx tmplabrtx;
10600 char tmplab[20];
10601
10602 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10603 CODE_LABEL_NUMBER (operands[0]));
10604 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10605
10606 emit_insn (gen_load_macho_picbase (tmplabrtx));
10607 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
10608 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10609 }
10610 else
10611 #endif
10612 rs6000_emit_load_toc_table (FALSE);
10613 DONE;
10614 }")
10615
10616 ;; Elf specific ways of loading addresses for non-PIC code.
10617 ;; The output of this could be r0, but we make a very strong
10618 ;; preference for a base register because it will usually
10619 ;; be needed there.
10620 (define_insn "elf_high"
10621 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10622 (high:SI (match_operand 1 "" "")))]
10623 "TARGET_ELF && ! TARGET_64BIT"
10624 "{liu|lis} %0,%1@ha")
10625
10626 (define_insn "elf_low"
10627 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10628 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10629 (match_operand 2 "" "")))]
10630 "TARGET_ELF && ! TARGET_64BIT"
10631 "@
10632 {cal|la} %0,%2@l(%1)
10633 {ai|addic} %0,%1,%K2")
10634 \f
10635 ;; A function pointer under AIX is a pointer to a data area whose first word
10636 ;; contains the actual address of the function, whose second word contains a
10637 ;; pointer to its TOC, and whose third word contains a value to place in the
10638 ;; static chain register (r11). Note that if we load the static chain, our
10639 ;; "trampoline" need not have any executable code.
10640
10641 (define_expand "call_indirect_aix32"
10642 [(set (match_dup 2)
10643 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10644 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10645 (reg:SI 2))
10646 (set (reg:SI 2)
10647 (mem:SI (plus:SI (match_dup 0)
10648 (const_int 4))))
10649 (set (reg:SI 11)
10650 (mem:SI (plus:SI (match_dup 0)
10651 (const_int 8))))
10652 (parallel [(call (mem:SI (match_dup 2))
10653 (match_operand 1 "" ""))
10654 (use (reg:SI 2))
10655 (use (reg:SI 11))
10656 (set (reg:SI 2)
10657 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10658 (clobber (reg:SI LR_REGNO))])]
10659 "TARGET_32BIT"
10660 "
10661 { operands[2] = gen_reg_rtx (SImode); }")
10662
10663 (define_expand "call_indirect_aix64"
10664 [(set (match_dup 2)
10665 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10666 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10667 (reg:DI 2))
10668 (set (reg:DI 2)
10669 (mem:DI (plus:DI (match_dup 0)
10670 (const_int 8))))
10671 (set (reg:DI 11)
10672 (mem:DI (plus:DI (match_dup 0)
10673 (const_int 16))))
10674 (parallel [(call (mem:SI (match_dup 2))
10675 (match_operand 1 "" ""))
10676 (use (reg:DI 2))
10677 (use (reg:DI 11))
10678 (set (reg:DI 2)
10679 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10680 (clobber (reg:SI LR_REGNO))])]
10681 "TARGET_64BIT"
10682 "
10683 { operands[2] = gen_reg_rtx (DImode); }")
10684
10685 (define_expand "call_value_indirect_aix32"
10686 [(set (match_dup 3)
10687 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10688 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10689 (reg:SI 2))
10690 (set (reg:SI 2)
10691 (mem:SI (plus:SI (match_dup 1)
10692 (const_int 4))))
10693 (set (reg:SI 11)
10694 (mem:SI (plus:SI (match_dup 1)
10695 (const_int 8))))
10696 (parallel [(set (match_operand 0 "" "")
10697 (call (mem:SI (match_dup 3))
10698 (match_operand 2 "" "")))
10699 (use (reg:SI 2))
10700 (use (reg:SI 11))
10701 (set (reg:SI 2)
10702 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10703 (clobber (reg:SI LR_REGNO))])]
10704 "TARGET_32BIT"
10705 "
10706 { operands[3] = gen_reg_rtx (SImode); }")
10707
10708 (define_expand "call_value_indirect_aix64"
10709 [(set (match_dup 3)
10710 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10711 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10712 (reg:DI 2))
10713 (set (reg:DI 2)
10714 (mem:DI (plus:DI (match_dup 1)
10715 (const_int 8))))
10716 (set (reg:DI 11)
10717 (mem:DI (plus:DI (match_dup 1)
10718 (const_int 16))))
10719 (parallel [(set (match_operand 0 "" "")
10720 (call (mem:SI (match_dup 3))
10721 (match_operand 2 "" "")))
10722 (use (reg:DI 2))
10723 (use (reg:DI 11))
10724 (set (reg:DI 2)
10725 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10726 (clobber (reg:SI LR_REGNO))])]
10727 "TARGET_64BIT"
10728 "
10729 { operands[3] = gen_reg_rtx (DImode); }")
10730
10731 ;; Now the definitions for the call and call_value insns
10732 (define_expand "call"
10733 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10734 (match_operand 1 "" ""))
10735 (use (match_operand 2 "" ""))
10736 (clobber (reg:SI LR_REGNO))])]
10737 ""
10738 "
10739 {
10740 #if TARGET_MACHO
10741 if (MACHOPIC_INDIRECT)
10742 operands[0] = machopic_indirect_call_target (operands[0]);
10743 #endif
10744
10745 gcc_assert (GET_CODE (operands[0]) == MEM);
10746 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10747
10748 operands[0] = XEXP (operands[0], 0);
10749
10750 if (GET_CODE (operands[0]) != SYMBOL_REF
10751 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10752 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10753 {
10754 if (INTVAL (operands[2]) & CALL_LONG)
10755 operands[0] = rs6000_longcall_ref (operands[0]);
10756
10757 switch (DEFAULT_ABI)
10758 {
10759 case ABI_V4:
10760 case ABI_DARWIN:
10761 operands[0] = force_reg (Pmode, operands[0]);
10762 break;
10763
10764 case ABI_AIX:
10765 /* AIX function pointers are really pointers to a three word
10766 area. */
10767 emit_call_insn (TARGET_32BIT
10768 ? gen_call_indirect_aix32 (force_reg (SImode,
10769 operands[0]),
10770 operands[1])
10771 : gen_call_indirect_aix64 (force_reg (DImode,
10772 operands[0]),
10773 operands[1]));
10774 DONE;
10775
10776 default:
10777 gcc_unreachable ();
10778 }
10779 }
10780 }")
10781
10782 (define_expand "call_value"
10783 [(parallel [(set (match_operand 0 "" "")
10784 (call (mem:SI (match_operand 1 "address_operand" ""))
10785 (match_operand 2 "" "")))
10786 (use (match_operand 3 "" ""))
10787 (clobber (reg:SI LR_REGNO))])]
10788 ""
10789 "
10790 {
10791 #if TARGET_MACHO
10792 if (MACHOPIC_INDIRECT)
10793 operands[1] = machopic_indirect_call_target (operands[1]);
10794 #endif
10795
10796 gcc_assert (GET_CODE (operands[1]) == MEM);
10797 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10798
10799 operands[1] = XEXP (operands[1], 0);
10800
10801 if (GET_CODE (operands[1]) != SYMBOL_REF
10802 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10803 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10804 {
10805 if (INTVAL (operands[3]) & CALL_LONG)
10806 operands[1] = rs6000_longcall_ref (operands[1]);
10807
10808 switch (DEFAULT_ABI)
10809 {
10810 case ABI_V4:
10811 case ABI_DARWIN:
10812 operands[1] = force_reg (Pmode, operands[1]);
10813 break;
10814
10815 case ABI_AIX:
10816 /* AIX function pointers are really pointers to a three word
10817 area. */
10818 emit_call_insn (TARGET_32BIT
10819 ? gen_call_value_indirect_aix32 (operands[0],
10820 force_reg (SImode,
10821 operands[1]),
10822 operands[2])
10823 : gen_call_value_indirect_aix64 (operands[0],
10824 force_reg (DImode,
10825 operands[1]),
10826 operands[2]));
10827 DONE;
10828
10829 default:
10830 gcc_unreachable ();
10831 }
10832 }
10833 }")
10834
10835 ;; Call to function in current module. No TOC pointer reload needed.
10836 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10837 ;; either the function was not prototyped, or it was prototyped as a
10838 ;; variable argument function. It is > 0 if FP registers were passed
10839 ;; and < 0 if they were not.
10840
10841 (define_insn "*call_local32"
10842 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10843 (match_operand 1 "" "g,g"))
10844 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10845 (clobber (reg:SI LR_REGNO))]
10846 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10847 "*
10848 {
10849 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10850 output_asm_insn (\"crxor 6,6,6\", operands);
10851
10852 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10853 output_asm_insn (\"creqv 6,6,6\", operands);
10854
10855 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10856 }"
10857 [(set_attr "type" "branch")
10858 (set_attr "length" "4,8")])
10859
10860 (define_insn "*call_local64"
10861 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10862 (match_operand 1 "" "g,g"))
10863 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10864 (clobber (reg:SI LR_REGNO))]
10865 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10866 "*
10867 {
10868 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10869 output_asm_insn (\"crxor 6,6,6\", operands);
10870
10871 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10872 output_asm_insn (\"creqv 6,6,6\", operands);
10873
10874 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10875 }"
10876 [(set_attr "type" "branch")
10877 (set_attr "length" "4,8")])
10878
10879 (define_insn "*call_value_local32"
10880 [(set (match_operand 0 "" "")
10881 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10882 (match_operand 2 "" "g,g")))
10883 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10884 (clobber (reg:SI LR_REGNO))]
10885 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10886 "*
10887 {
10888 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10889 output_asm_insn (\"crxor 6,6,6\", operands);
10890
10891 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10892 output_asm_insn (\"creqv 6,6,6\", operands);
10893
10894 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10895 }"
10896 [(set_attr "type" "branch")
10897 (set_attr "length" "4,8")])
10898
10899
10900 (define_insn "*call_value_local64"
10901 [(set (match_operand 0 "" "")
10902 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10903 (match_operand 2 "" "g,g")))
10904 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10905 (clobber (reg:SI LR_REGNO))]
10906 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10907 "*
10908 {
10909 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10910 output_asm_insn (\"crxor 6,6,6\", operands);
10911
10912 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10913 output_asm_insn (\"creqv 6,6,6\", operands);
10914
10915 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10916 }"
10917 [(set_attr "type" "branch")
10918 (set_attr "length" "4,8")])
10919
10920 ;; Call to function which may be in another module. Restore the TOC
10921 ;; pointer (r2) after the call unless this is System V.
10922 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10923 ;; either the function was not prototyped, or it was prototyped as a
10924 ;; variable argument function. It is > 0 if FP registers were passed
10925 ;; and < 0 if they were not.
10926
10927 (define_insn "*call_indirect_nonlocal_aix32"
10928 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
10929 (match_operand 1 "" "g,g"))
10930 (use (reg:SI 2))
10931 (use (reg:SI 11))
10932 (set (reg:SI 2)
10933 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10934 (clobber (reg:SI LR_REGNO))]
10935 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10936 "b%T0l\;{l|lwz} 2,20(1)"
10937 [(set_attr "type" "jmpreg")
10938 (set_attr "length" "8")])
10939
10940 (define_insn "*call_nonlocal_aix32"
10941 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10942 (match_operand 1 "" "g"))
10943 (use (match_operand:SI 2 "immediate_operand" "O"))
10944 (clobber (reg:SI LR_REGNO))]
10945 "TARGET_32BIT
10946 && DEFAULT_ABI == ABI_AIX
10947 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10948 "bl %z0\;%."
10949 [(set_attr "type" "branch")
10950 (set_attr "length" "8")])
10951
10952 (define_insn "*call_indirect_nonlocal_aix64"
10953 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
10954 (match_operand 1 "" "g,g"))
10955 (use (reg:DI 2))
10956 (use (reg:DI 11))
10957 (set (reg:DI 2)
10958 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10959 (clobber (reg:SI LR_REGNO))]
10960 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10961 "b%T0l\;ld 2,40(1)"
10962 [(set_attr "type" "jmpreg")
10963 (set_attr "length" "8")])
10964
10965 (define_insn "*call_nonlocal_aix64"
10966 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10967 (match_operand 1 "" "g"))
10968 (use (match_operand:SI 2 "immediate_operand" "O"))
10969 (clobber (reg:SI LR_REGNO))]
10970 "TARGET_64BIT
10971 && DEFAULT_ABI == ABI_AIX
10972 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10973 "bl %z0\;%."
10974 [(set_attr "type" "branch")
10975 (set_attr "length" "8")])
10976
10977 (define_insn "*call_value_indirect_nonlocal_aix32"
10978 [(set (match_operand 0 "" "")
10979 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
10980 (match_operand 2 "" "g,g")))
10981 (use (reg:SI 2))
10982 (use (reg:SI 11))
10983 (set (reg:SI 2)
10984 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10985 (clobber (reg:SI LR_REGNO))]
10986 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10987 "b%T1l\;{l|lwz} 2,20(1)"
10988 [(set_attr "type" "jmpreg")
10989 (set_attr "length" "8")])
10990
10991 (define_insn "*call_value_nonlocal_aix32"
10992 [(set (match_operand 0 "" "")
10993 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10994 (match_operand 2 "" "g")))
10995 (use (match_operand:SI 3 "immediate_operand" "O"))
10996 (clobber (reg:SI LR_REGNO))]
10997 "TARGET_32BIT
10998 && DEFAULT_ABI == ABI_AIX
10999 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11000 "bl %z1\;%."
11001 [(set_attr "type" "branch")
11002 (set_attr "length" "8")])
11003
11004 (define_insn "*call_value_indirect_nonlocal_aix64"
11005 [(set (match_operand 0 "" "")
11006 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
11007 (match_operand 2 "" "g,g")))
11008 (use (reg:DI 2))
11009 (use (reg:DI 11))
11010 (set (reg:DI 2)
11011 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11012 (clobber (reg:SI LR_REGNO))]
11013 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11014 "b%T1l\;ld 2,40(1)"
11015 [(set_attr "type" "jmpreg")
11016 (set_attr "length" "8")])
11017
11018 (define_insn "*call_value_nonlocal_aix64"
11019 [(set (match_operand 0 "" "")
11020 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11021 (match_operand 2 "" "g")))
11022 (use (match_operand:SI 3 "immediate_operand" "O"))
11023 (clobber (reg:SI LR_REGNO))]
11024 "TARGET_64BIT
11025 && DEFAULT_ABI == ABI_AIX
11026 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11027 "bl %z1\;%."
11028 [(set_attr "type" "branch")
11029 (set_attr "length" "8")])
11030
11031 ;; A function pointer under System V is just a normal pointer
11032 ;; operands[0] is the function pointer
11033 ;; operands[1] is the stack size to clean up
11034 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
11035 ;; which indicates how to set cr1
11036
11037 (define_insn "*call_indirect_nonlocal_sysv<mode>"
11038 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
11039 (match_operand 1 "" "g,g,g,g"))
11040 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
11041 (clobber (reg:SI LR_REGNO))]
11042 "DEFAULT_ABI == ABI_V4
11043 || DEFAULT_ABI == ABI_DARWIN"
11044 {
11045 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11046 output_asm_insn ("crxor 6,6,6", operands);
11047
11048 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11049 output_asm_insn ("creqv 6,6,6", operands);
11050
11051 return "b%T0l";
11052 }
11053 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11054 (set_attr "length" "4,4,8,8")])
11055
11056 (define_insn_and_split "*call_nonlocal_sysv<mode>"
11057 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11058 (match_operand 1 "" "g,g"))
11059 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11060 (clobber (reg:SI LR_REGNO))]
11061 "(DEFAULT_ABI == ABI_DARWIN
11062 || (DEFAULT_ABI == ABI_V4
11063 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
11064 {
11065 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11066 output_asm_insn ("crxor 6,6,6", operands);
11067
11068 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11069 output_asm_insn ("creqv 6,6,6", operands);
11070
11071 #if TARGET_MACHO
11072 return output_call(insn, operands, 0, 2);
11073 #else
11074 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11075 {
11076 gcc_assert (!TARGET_SECURE_PLT);
11077 return "bl %z0@plt";
11078 }
11079 else
11080 return "bl %z0";
11081 #endif
11082 }
11083 "DEFAULT_ABI == ABI_V4
11084 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11085 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11086 [(parallel [(call (mem:SI (match_dup 0))
11087 (match_dup 1))
11088 (use (match_dup 2))
11089 (use (match_dup 3))
11090 (clobber (reg:SI LR_REGNO))])]
11091 {
11092 operands[3] = pic_offset_table_rtx;
11093 }
11094 [(set_attr "type" "branch,branch")
11095 (set_attr "length" "4,8")])
11096
11097 (define_insn "*call_nonlocal_sysv_secure<mode>"
11098 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11099 (match_operand 1 "" "g,g"))
11100 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11101 (use (match_operand:SI 3 "register_operand" "r,r"))
11102 (clobber (reg:SI LR_REGNO))]
11103 "(DEFAULT_ABI == ABI_V4
11104 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11105 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
11106 {
11107 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11108 output_asm_insn ("crxor 6,6,6", operands);
11109
11110 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11111 output_asm_insn ("creqv 6,6,6", operands);
11112
11113 if (flag_pic == 2)
11114 /* The magic 32768 offset here and in the other sysv call insns
11115 corresponds to the offset of r30 in .got2, as given by LCTOC1.
11116 See sysv4.h:toc_section. */
11117 return "bl %z0+32768@plt";
11118 else
11119 return "bl %z0@plt";
11120 }
11121 [(set_attr "type" "branch,branch")
11122 (set_attr "length" "4,8")])
11123
11124 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
11125 [(set (match_operand 0 "" "")
11126 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
11127 (match_operand 2 "" "g,g,g,g")))
11128 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
11129 (clobber (reg:SI LR_REGNO))]
11130 "DEFAULT_ABI == ABI_V4
11131 || DEFAULT_ABI == ABI_DARWIN"
11132 {
11133 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11134 output_asm_insn ("crxor 6,6,6", operands);
11135
11136 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11137 output_asm_insn ("creqv 6,6,6", operands);
11138
11139 return "b%T1l";
11140 }
11141 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11142 (set_attr "length" "4,4,8,8")])
11143
11144 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
11145 [(set (match_operand 0 "" "")
11146 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11147 (match_operand 2 "" "g,g")))
11148 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11149 (clobber (reg:SI LR_REGNO))]
11150 "(DEFAULT_ABI == ABI_DARWIN
11151 || (DEFAULT_ABI == ABI_V4
11152 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
11153 {
11154 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11155 output_asm_insn ("crxor 6,6,6", operands);
11156
11157 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11158 output_asm_insn ("creqv 6,6,6", operands);
11159
11160 #if TARGET_MACHO
11161 return output_call(insn, operands, 1, 3);
11162 #else
11163 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11164 {
11165 gcc_assert (!TARGET_SECURE_PLT);
11166 return "bl %z1@plt";
11167 }
11168 else
11169 return "bl %z1";
11170 #endif
11171 }
11172 "DEFAULT_ABI == ABI_V4
11173 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11174 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11175 [(parallel [(set (match_dup 0)
11176 (call (mem:SI (match_dup 1))
11177 (match_dup 2)))
11178 (use (match_dup 3))
11179 (use (match_dup 4))
11180 (clobber (reg:SI LR_REGNO))])]
11181 {
11182 operands[4] = pic_offset_table_rtx;
11183 }
11184 [(set_attr "type" "branch,branch")
11185 (set_attr "length" "4,8")])
11186
11187 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
11188 [(set (match_operand 0 "" "")
11189 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11190 (match_operand 2 "" "g,g")))
11191 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11192 (use (match_operand:SI 4 "register_operand" "r,r"))
11193 (clobber (reg:SI LR_REGNO))]
11194 "(DEFAULT_ABI == ABI_V4
11195 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11196 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
11197 {
11198 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11199 output_asm_insn ("crxor 6,6,6", operands);
11200
11201 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11202 output_asm_insn ("creqv 6,6,6", operands);
11203
11204 if (flag_pic == 2)
11205 return "bl %z1+32768@plt";
11206 else
11207 return "bl %z1@plt";
11208 }
11209 [(set_attr "type" "branch,branch")
11210 (set_attr "length" "4,8")])
11211
11212 ;; Call subroutine returning any type.
11213 (define_expand "untyped_call"
11214 [(parallel [(call (match_operand 0 "" "")
11215 (const_int 0))
11216 (match_operand 1 "" "")
11217 (match_operand 2 "" "")])]
11218 ""
11219 "
11220 {
11221 int i;
11222
11223 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
11224
11225 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11226 {
11227 rtx set = XVECEXP (operands[2], 0, i);
11228 emit_move_insn (SET_DEST (set), SET_SRC (set));
11229 }
11230
11231 /* The optimizer does not know that the call sets the function value
11232 registers we stored in the result block. We avoid problems by
11233 claiming that all hard registers are used and clobbered at this
11234 point. */
11235 emit_insn (gen_blockage ());
11236
11237 DONE;
11238 }")
11239
11240 ;; sibling call patterns
11241 (define_expand "sibcall"
11242 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11243 (match_operand 1 "" ""))
11244 (use (match_operand 2 "" ""))
11245 (use (reg:SI LR_REGNO))
11246 (return)])]
11247 ""
11248 "
11249 {
11250 #if TARGET_MACHO
11251 if (MACHOPIC_INDIRECT)
11252 operands[0] = machopic_indirect_call_target (operands[0]);
11253 #endif
11254
11255 gcc_assert (GET_CODE (operands[0]) == MEM);
11256 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11257
11258 operands[0] = XEXP (operands[0], 0);
11259 }")
11260
11261 ;; this and similar patterns must be marked as using LR, otherwise
11262 ;; dataflow will try to delete the store into it. This is true
11263 ;; even when the actual reg to jump to is in CTR, when LR was
11264 ;; saved and restored around the PIC-setting BCL.
11265 (define_insn "*sibcall_local32"
11266 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11267 (match_operand 1 "" "g,g"))
11268 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11269 (use (reg:SI LR_REGNO))
11270 (return)]
11271 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11272 "*
11273 {
11274 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11275 output_asm_insn (\"crxor 6,6,6\", operands);
11276
11277 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11278 output_asm_insn (\"creqv 6,6,6\", operands);
11279
11280 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11281 }"
11282 [(set_attr "type" "branch")
11283 (set_attr "length" "4,8")])
11284
11285 (define_insn "*sibcall_local64"
11286 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11287 (match_operand 1 "" "g,g"))
11288 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11289 (use (reg:SI LR_REGNO))
11290 (return)]
11291 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11292 "*
11293 {
11294 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11295 output_asm_insn (\"crxor 6,6,6\", operands);
11296
11297 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11298 output_asm_insn (\"creqv 6,6,6\", operands);
11299
11300 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11301 }"
11302 [(set_attr "type" "branch")
11303 (set_attr "length" "4,8")])
11304
11305 (define_insn "*sibcall_value_local32"
11306 [(set (match_operand 0 "" "")
11307 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11308 (match_operand 2 "" "g,g")))
11309 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11310 (use (reg:SI LR_REGNO))
11311 (return)]
11312 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11313 "*
11314 {
11315 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11316 output_asm_insn (\"crxor 6,6,6\", operands);
11317
11318 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11319 output_asm_insn (\"creqv 6,6,6\", operands);
11320
11321 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11322 }"
11323 [(set_attr "type" "branch")
11324 (set_attr "length" "4,8")])
11325
11326
11327 (define_insn "*sibcall_value_local64"
11328 [(set (match_operand 0 "" "")
11329 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11330 (match_operand 2 "" "g,g")))
11331 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11332 (use (reg:SI LR_REGNO))
11333 (return)]
11334 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11335 "*
11336 {
11337 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11338 output_asm_insn (\"crxor 6,6,6\", operands);
11339
11340 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11341 output_asm_insn (\"creqv 6,6,6\", operands);
11342
11343 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11344 }"
11345 [(set_attr "type" "branch")
11346 (set_attr "length" "4,8")])
11347
11348 (define_insn "*sibcall_nonlocal_aix32"
11349 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11350 (match_operand 1 "" "g"))
11351 (use (match_operand:SI 2 "immediate_operand" "O"))
11352 (use (reg:SI LR_REGNO))
11353 (return)]
11354 "TARGET_32BIT
11355 && DEFAULT_ABI == ABI_AIX
11356 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11357 "b %z0"
11358 [(set_attr "type" "branch")
11359 (set_attr "length" "4")])
11360
11361 (define_insn "*sibcall_nonlocal_aix64"
11362 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11363 (match_operand 1 "" "g"))
11364 (use (match_operand:SI 2 "immediate_operand" "O"))
11365 (use (reg:SI LR_REGNO))
11366 (return)]
11367 "TARGET_64BIT
11368 && DEFAULT_ABI == ABI_AIX
11369 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11370 "b %z0"
11371 [(set_attr "type" "branch")
11372 (set_attr "length" "4")])
11373
11374 (define_insn "*sibcall_value_nonlocal_aix32"
11375 [(set (match_operand 0 "" "")
11376 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11377 (match_operand 2 "" "g")))
11378 (use (match_operand:SI 3 "immediate_operand" "O"))
11379 (use (reg:SI LR_REGNO))
11380 (return)]
11381 "TARGET_32BIT
11382 && DEFAULT_ABI == ABI_AIX
11383 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11384 "b %z1"
11385 [(set_attr "type" "branch")
11386 (set_attr "length" "4")])
11387
11388 (define_insn "*sibcall_value_nonlocal_aix64"
11389 [(set (match_operand 0 "" "")
11390 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11391 (match_operand 2 "" "g")))
11392 (use (match_operand:SI 3 "immediate_operand" "O"))
11393 (use (reg:SI LR_REGNO))
11394 (return)]
11395 "TARGET_64BIT
11396 && DEFAULT_ABI == ABI_AIX
11397 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11398 "b %z1"
11399 [(set_attr "type" "branch")
11400 (set_attr "length" "4")])
11401
11402 (define_insn "*sibcall_nonlocal_sysv<mode>"
11403 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11404 (match_operand 1 "" ""))
11405 (use (match_operand 2 "immediate_operand" "O,n"))
11406 (use (reg:SI LR_REGNO))
11407 (return)]
11408 "(DEFAULT_ABI == ABI_DARWIN
11409 || DEFAULT_ABI == ABI_V4)
11410 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11411 "*
11412 {
11413 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11414 output_asm_insn (\"crxor 6,6,6\", operands);
11415
11416 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11417 output_asm_insn (\"creqv 6,6,6\", operands);
11418
11419 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11420 {
11421 gcc_assert (!TARGET_SECURE_PLT);
11422 return \"b %z0@plt\";
11423 }
11424 else
11425 return \"b %z0\";
11426 }"
11427 [(set_attr "type" "branch,branch")
11428 (set_attr "length" "4,8")])
11429
11430 (define_expand "sibcall_value"
11431 [(parallel [(set (match_operand 0 "register_operand" "")
11432 (call (mem:SI (match_operand 1 "address_operand" ""))
11433 (match_operand 2 "" "")))
11434 (use (match_operand 3 "" ""))
11435 (use (reg:SI LR_REGNO))
11436 (return)])]
11437 ""
11438 "
11439 {
11440 #if TARGET_MACHO
11441 if (MACHOPIC_INDIRECT)
11442 operands[1] = machopic_indirect_call_target (operands[1]);
11443 #endif
11444
11445 gcc_assert (GET_CODE (operands[1]) == MEM);
11446 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11447
11448 operands[1] = XEXP (operands[1], 0);
11449 }")
11450
11451 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
11452 [(set (match_operand 0 "" "")
11453 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11454 (match_operand 2 "" "")))
11455 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11456 (use (reg:SI LR_REGNO))
11457 (return)]
11458 "(DEFAULT_ABI == ABI_DARWIN
11459 || DEFAULT_ABI == ABI_V4)
11460 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11461 "*
11462 {
11463 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11464 output_asm_insn (\"crxor 6,6,6\", operands);
11465
11466 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11467 output_asm_insn (\"creqv 6,6,6\", operands);
11468
11469 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11470 {
11471 gcc_assert (!TARGET_SECURE_PLT);
11472 return \"b %z1@plt\";
11473 }
11474 else
11475 return \"b %z1\";
11476 }"
11477 [(set_attr "type" "branch,branch")
11478 (set_attr "length" "4,8")])
11479
11480 (define_expand "sibcall_epilogue"
11481 [(use (const_int 0))]
11482 "TARGET_SCHED_PROLOG"
11483 "
11484 {
11485 rs6000_emit_epilogue (TRUE);
11486 DONE;
11487 }")
11488
11489 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11490 ;; all of memory. This blocks insns from being moved across this point.
11491
11492 (define_insn "blockage"
11493 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
11494 ""
11495 "")
11496 \f
11497 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
11498 ;; signed & unsigned, and one type of branch.
11499 ;;
11500 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11501 ;; insns, and branches. We store the operands of compares until we see
11502 ;; how it is used.
11503 (define_expand "cmp<mode>"
11504 [(set (cc0)
11505 (compare (match_operand:GPR 0 "gpc_reg_operand" "")
11506 (match_operand:GPR 1 "reg_or_short_operand" "")))]
11507 ""
11508 "
11509 {
11510 /* Take care of the possibility that operands[1] might be negative but
11511 this might be a logical operation. That insn doesn't exist. */
11512 if (GET_CODE (operands[1]) == CONST_INT
11513 && INTVAL (operands[1]) < 0)
11514 operands[1] = force_reg (<MODE>mode, operands[1]);
11515
11516 rs6000_compare_op0 = operands[0];
11517 rs6000_compare_op1 = operands[1];
11518 rs6000_compare_fp_p = 0;
11519 DONE;
11520 }")
11521
11522 (define_expand "cmp<mode>"
11523 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
11524 (match_operand:FP 1 "gpc_reg_operand" "")))]
11525 ""
11526 "
11527 {
11528 rs6000_compare_op0 = operands[0];
11529 rs6000_compare_op1 = operands[1];
11530 rs6000_compare_fp_p = 1;
11531 DONE;
11532 }")
11533
11534 (define_expand "beq"
11535 [(use (match_operand 0 "" ""))]
11536 ""
11537 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
11538
11539 (define_expand "bne"
11540 [(use (match_operand 0 "" ""))]
11541 ""
11542 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
11543
11544 (define_expand "bge"
11545 [(use (match_operand 0 "" ""))]
11546 ""
11547 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
11548
11549 (define_expand "bgt"
11550 [(use (match_operand 0 "" ""))]
11551 ""
11552 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
11553
11554 (define_expand "ble"
11555 [(use (match_operand 0 "" ""))]
11556 ""
11557 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
11558
11559 (define_expand "blt"
11560 [(use (match_operand 0 "" ""))]
11561 ""
11562 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
11563
11564 (define_expand "bgeu"
11565 [(use (match_operand 0 "" ""))]
11566 ""
11567 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
11568
11569 (define_expand "bgtu"
11570 [(use (match_operand 0 "" ""))]
11571 ""
11572 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
11573
11574 (define_expand "bleu"
11575 [(use (match_operand 0 "" ""))]
11576 ""
11577 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
11578
11579 (define_expand "bltu"
11580 [(use (match_operand 0 "" ""))]
11581 ""
11582 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
11583
11584 (define_expand "bunordered"
11585 [(use (match_operand 0 "" ""))]
11586 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11587 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
11588
11589 (define_expand "bordered"
11590 [(use (match_operand 0 "" ""))]
11591 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11592 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
11593
11594 (define_expand "buneq"
11595 [(use (match_operand 0 "" ""))]
11596 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11597 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
11598
11599 (define_expand "bunge"
11600 [(use (match_operand 0 "" ""))]
11601 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11602 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
11603
11604 (define_expand "bungt"
11605 [(use (match_operand 0 "" ""))]
11606 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11607 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
11608
11609 (define_expand "bunle"
11610 [(use (match_operand 0 "" ""))]
11611 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11612 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
11613
11614 (define_expand "bunlt"
11615 [(use (match_operand 0 "" ""))]
11616 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11617 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
11618
11619 (define_expand "bltgt"
11620 [(use (match_operand 0 "" ""))]
11621 ""
11622 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
11623
11624 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11625 ;; For SEQ, likewise, except that comparisons with zero should be done
11626 ;; with an scc insns. However, due to the order that combine see the
11627 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11628 ;; the cases we don't want to handle.
11629 (define_expand "seq"
11630 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11631 ""
11632 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
11633
11634 (define_expand "sne"
11635 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11636 ""
11637 "
11638 {
11639 if (! rs6000_compare_fp_p)
11640 FAIL;
11641
11642 rs6000_emit_sCOND (NE, operands[0]);
11643 DONE;
11644 }")
11645
11646 ;; A >= 0 is best done the portable way for A an integer.
11647 (define_expand "sge"
11648 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11649 ""
11650 "
11651 {
11652 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11653 FAIL;
11654
11655 rs6000_emit_sCOND (GE, operands[0]);
11656 DONE;
11657 }")
11658
11659 ;; A > 0 is best done using the portable sequence, so fail in that case.
11660 (define_expand "sgt"
11661 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11662 ""
11663 "
11664 {
11665 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11666 FAIL;
11667
11668 rs6000_emit_sCOND (GT, operands[0]);
11669 DONE;
11670 }")
11671
11672 ;; A <= 0 is best done the portable way for A an integer.
11673 (define_expand "sle"
11674 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11675 ""
11676 "
11677 {
11678 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11679 FAIL;
11680
11681 rs6000_emit_sCOND (LE, operands[0]);
11682 DONE;
11683 }")
11684
11685 ;; A < 0 is best done in the portable way for A an integer.
11686 (define_expand "slt"
11687 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11688 ""
11689 "
11690 {
11691 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11692 FAIL;
11693
11694 rs6000_emit_sCOND (LT, operands[0]);
11695 DONE;
11696 }")
11697
11698 (define_expand "sgeu"
11699 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11700 ""
11701 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11702
11703 (define_expand "sgtu"
11704 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11705 ""
11706 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
11707
11708 (define_expand "sleu"
11709 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11710 ""
11711 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11712
11713 (define_expand "sltu"
11714 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11715 ""
11716 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
11717
11718 (define_expand "sunordered"
11719 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11720 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11721 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
11722
11723 (define_expand "sordered"
11724 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11725 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11726 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11727
11728 (define_expand "suneq"
11729 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11730 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11731 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11732
11733 (define_expand "sunge"
11734 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11735 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11736 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11737
11738 (define_expand "sungt"
11739 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11740 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11741 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11742
11743 (define_expand "sunle"
11744 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11745 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11746 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11747
11748 (define_expand "sunlt"
11749 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11750 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11751 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11752
11753 (define_expand "sltgt"
11754 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11755 ""
11756 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11757
11758 (define_expand "stack_protect_set"
11759 [(match_operand 0 "memory_operand" "")
11760 (match_operand 1 "memory_operand" "")]
11761 ""
11762 {
11763 #ifdef TARGET_THREAD_SSP_OFFSET
11764 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11765 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11766 operands[1] = gen_rtx_MEM (Pmode, addr);
11767 #endif
11768 if (TARGET_64BIT)
11769 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11770 else
11771 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11772 DONE;
11773 })
11774
11775 (define_insn "stack_protect_setsi"
11776 [(set (match_operand:SI 0 "memory_operand" "=m")
11777 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11778 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11779 "TARGET_32BIT"
11780 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
11781 [(set_attr "type" "three")
11782 (set_attr "length" "12")])
11783
11784 (define_insn "stack_protect_setdi"
11785 [(set (match_operand:DI 0 "memory_operand" "=m")
11786 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11787 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11788 "TARGET_64BIT"
11789 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
11790 [(set_attr "type" "three")
11791 (set_attr "length" "12")])
11792
11793 (define_expand "stack_protect_test"
11794 [(match_operand 0 "memory_operand" "")
11795 (match_operand 1 "memory_operand" "")
11796 (match_operand 2 "" "")]
11797 ""
11798 {
11799 #ifdef TARGET_THREAD_SSP_OFFSET
11800 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11801 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11802 operands[1] = gen_rtx_MEM (Pmode, addr);
11803 #endif
11804 rs6000_compare_op0 = operands[0];
11805 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
11806 UNSPEC_SP_TEST);
11807 rs6000_compare_fp_p = 0;
11808 emit_jump_insn (gen_beq (operands[2]));
11809 DONE;
11810 })
11811
11812 (define_insn "stack_protect_testsi"
11813 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11814 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11815 (match_operand:SI 2 "memory_operand" "m,m")]
11816 UNSPEC_SP_TEST))
11817 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11818 (clobber (match_scratch:SI 3 "=&r,&r"))]
11819 "TARGET_32BIT"
11820 "@
11821 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11822 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11823 [(set_attr "length" "16,20")])
11824
11825 (define_insn "stack_protect_testdi"
11826 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11827 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
11828 (match_operand:DI 2 "memory_operand" "m,m")]
11829 UNSPEC_SP_TEST))
11830 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11831 (clobber (match_scratch:DI 3 "=&r,&r"))]
11832 "TARGET_64BIT"
11833 "@
11834 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11835 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11836 [(set_attr "length" "16,20")])
11837
11838 \f
11839 ;; Here are the actual compare insns.
11840 (define_insn "*cmp<mode>_internal1"
11841 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11842 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11843 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
11844 ""
11845 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
11846 [(set_attr "type" "cmp")])
11847
11848 ;; If we are comparing a register for equality with a large constant,
11849 ;; we can do this with an XOR followed by a compare. But this is profitable
11850 ;; only if the large constant is only used for the comparison (and in this
11851 ;; case we already have a register to reuse as scratch).
11852 ;;
11853 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11854 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
11855
11856 (define_peephole2
11857 [(set (match_operand:SI 0 "register_operand")
11858 (match_operand:SI 1 "logical_const_operand" ""))
11859 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
11860 [(match_dup 0)
11861 (match_operand:SI 2 "logical_const_operand" "")]))
11862 (set (match_operand:CC 4 "cc_reg_operand" "")
11863 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
11864 (match_dup 0)))
11865 (set (pc)
11866 (if_then_else (match_operator 6 "equality_operator"
11867 [(match_dup 4) (const_int 0)])
11868 (match_operand 7 "" "")
11869 (match_operand 8 "" "")))]
11870 "peep2_reg_dead_p (3, operands[0])
11871 && peep2_reg_dead_p (4, operands[4])"
11872 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
11873 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11874 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11875
11876 {
11877 /* Get the constant we are comparing against, and see what it looks like
11878 when sign-extended from 16 to 32 bits. Then see what constant we could
11879 XOR with SEXTC to get the sign-extended value. */
11880 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
11881 SImode,
11882 operands[1], operands[2]);
11883 HOST_WIDE_INT c = INTVAL (cnst);
11884 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11885 HOST_WIDE_INT xorv = c ^ sextc;
11886
11887 operands[9] = GEN_INT (xorv);
11888 operands[10] = GEN_INT (sextc);
11889 })
11890
11891 (define_insn "*cmpsi_internal2"
11892 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11893 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11894 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11895 ""
11896 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
11897 [(set_attr "type" "cmp")])
11898
11899 (define_insn "*cmpdi_internal2"
11900 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11901 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11902 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11903 ""
11904 "cmpld%I2 %0,%1,%b2"
11905 [(set_attr "type" "cmp")])
11906
11907 ;; The following two insns don't exist as single insns, but if we provide
11908 ;; them, we can swap an add and compare, which will enable us to overlap more
11909 ;; of the required delay between a compare and branch. We generate code for
11910 ;; them by splitting.
11911
11912 (define_insn ""
11913 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11914 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11915 (match_operand:SI 2 "short_cint_operand" "i")))
11916 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11917 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11918 ""
11919 "#"
11920 [(set_attr "length" "8")])
11921
11922 (define_insn ""
11923 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11924 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11925 (match_operand:SI 2 "u_short_cint_operand" "i")))
11926 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11927 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11928 ""
11929 "#"
11930 [(set_attr "length" "8")])
11931
11932 (define_split
11933 [(set (match_operand:CC 3 "cc_reg_operand" "")
11934 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11935 (match_operand:SI 2 "short_cint_operand" "")))
11936 (set (match_operand:SI 0 "gpc_reg_operand" "")
11937 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11938 ""
11939 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11940 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11941
11942 (define_split
11943 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11944 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11945 (match_operand:SI 2 "u_short_cint_operand" "")))
11946 (set (match_operand:SI 0 "gpc_reg_operand" "")
11947 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11948 ""
11949 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11950 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11951
11952 (define_insn "*cmpsf_internal1"
11953 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11954 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11955 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11956 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
11957 "fcmpu %0,%1,%2"
11958 [(set_attr "type" "fpcompare")])
11959
11960 (define_insn "*cmpdf_internal1"
11961 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11962 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11963 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11964 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
11965 "fcmpu %0,%1,%2"
11966 [(set_attr "type" "fpcompare")])
11967
11968 ;; Only need to compare second words if first words equal
11969 (define_insn "*cmptf_internal1"
11970 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11971 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11972 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11973 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
11974 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
11975 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11976 [(set_attr "type" "fpcompare")
11977 (set_attr "length" "12")])
11978
11979 (define_insn_and_split "*cmptf_internal2"
11980 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11981 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11982 (match_operand:TF 2 "gpc_reg_operand" "f")))
11983 (clobber (match_scratch:DF 3 "=f"))
11984 (clobber (match_scratch:DF 4 "=f"))
11985 (clobber (match_scratch:DF 5 "=f"))
11986 (clobber (match_scratch:DF 6 "=f"))
11987 (clobber (match_scratch:DF 7 "=f"))
11988 (clobber (match_scratch:DF 8 "=f"))
11989 (clobber (match_scratch:DF 9 "=f"))
11990 (clobber (match_scratch:DF 10 "=f"))]
11991 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
11992 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
11993 "#"
11994 "&& reload_completed"
11995 [(set (match_dup 3) (match_dup 13))
11996 (set (match_dup 4) (match_dup 14))
11997 (set (match_dup 9) (abs:DF (match_dup 5)))
11998 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11999 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
12000 (label_ref (match_dup 11))
12001 (pc)))
12002 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
12003 (set (pc) (label_ref (match_dup 12)))
12004 (match_dup 11)
12005 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
12006 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
12007 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
12008 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
12009 (match_dup 12)]
12010 {
12011 REAL_VALUE_TYPE rv;
12012 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
12013 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
12014
12015 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
12016 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
12017 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
12018 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
12019 operands[11] = gen_label_rtx ();
12020 operands[12] = gen_label_rtx ();
12021 real_inf (&rv);
12022 operands[13] = force_const_mem (DFmode,
12023 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
12024 operands[14] = force_const_mem (DFmode,
12025 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
12026 DFmode));
12027 if (TARGET_TOC)
12028 {
12029 operands[13] = gen_const_mem (DFmode,
12030 create_TOC_reference (XEXP (operands[13], 0)));
12031 operands[14] = gen_const_mem (DFmode,
12032 create_TOC_reference (XEXP (operands[14], 0)));
12033 set_mem_alias_set (operands[13], get_TOC_alias_set ());
12034 set_mem_alias_set (operands[14], get_TOC_alias_set ());
12035 }
12036 })
12037 \f
12038 ;; Now we have the scc insns. We can do some combinations because of the
12039 ;; way the machine works.
12040 ;;
12041 ;; Note that this is probably faster if we can put an insn between the
12042 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
12043 ;; cases the insns below which don't use an intermediate CR field will
12044 ;; be used instead.
12045 (define_insn ""
12046 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12047 (match_operator:SI 1 "scc_comparison_operator"
12048 [(match_operand 2 "cc_reg_operand" "y")
12049 (const_int 0)]))]
12050 ""
12051 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12052 [(set (attr "type")
12053 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12054 (const_string "mfcrf")
12055 ]
12056 (const_string "mfcr")))
12057 (set_attr "length" "8")])
12058
12059 ;; Same as above, but get the GT bit.
12060 (define_insn "move_from_CR_gt_bit"
12061 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12062 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
12063 "TARGET_E500"
12064 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
12065 [(set_attr "type" "mfcr")
12066 (set_attr "length" "8")])
12067
12068 ;; Same as above, but get the OV/ORDERED bit.
12069 (define_insn "move_from_CR_ov_bit"
12070 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12071 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
12072 "TARGET_ISEL"
12073 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
12074 [(set_attr "type" "mfcr")
12075 (set_attr "length" "8")])
12076
12077 (define_insn ""
12078 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12079 (match_operator:DI 1 "scc_comparison_operator"
12080 [(match_operand 2 "cc_reg_operand" "y")
12081 (const_int 0)]))]
12082 "TARGET_POWERPC64"
12083 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12084 [(set (attr "type")
12085 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12086 (const_string "mfcrf")
12087 ]
12088 (const_string "mfcr")))
12089 (set_attr "length" "8")])
12090
12091 (define_insn ""
12092 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12093 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12094 [(match_operand 2 "cc_reg_operand" "y,y")
12095 (const_int 0)])
12096 (const_int 0)))
12097 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
12098 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12099 "TARGET_32BIT"
12100 "@
12101 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
12102 #"
12103 [(set_attr "type" "delayed_compare")
12104 (set_attr "length" "8,16")])
12105
12106 (define_split
12107 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12108 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12109 [(match_operand 2 "cc_reg_operand" "")
12110 (const_int 0)])
12111 (const_int 0)))
12112 (set (match_operand:SI 3 "gpc_reg_operand" "")
12113 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12114 "TARGET_32BIT && reload_completed"
12115 [(set (match_dup 3)
12116 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12117 (set (match_dup 0)
12118 (compare:CC (match_dup 3)
12119 (const_int 0)))]
12120 "")
12121
12122 (define_insn ""
12123 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12124 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12125 [(match_operand 2 "cc_reg_operand" "y")
12126 (const_int 0)])
12127 (match_operand:SI 3 "const_int_operand" "n")))]
12128 ""
12129 "*
12130 {
12131 int is_bit = ccr_bit (operands[1], 1);
12132 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12133 int count;
12134
12135 if (is_bit >= put_bit)
12136 count = is_bit - put_bit;
12137 else
12138 count = 32 - (put_bit - is_bit);
12139
12140 operands[4] = GEN_INT (count);
12141 operands[5] = GEN_INT (put_bit);
12142
12143 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
12144 }"
12145 [(set (attr "type")
12146 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12147 (const_string "mfcrf")
12148 ]
12149 (const_string "mfcr")))
12150 (set_attr "length" "8")])
12151
12152 (define_insn ""
12153 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12154 (compare:CC
12155 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12156 [(match_operand 2 "cc_reg_operand" "y,y")
12157 (const_int 0)])
12158 (match_operand:SI 3 "const_int_operand" "n,n"))
12159 (const_int 0)))
12160 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
12161 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12162 (match_dup 3)))]
12163 ""
12164 "*
12165 {
12166 int is_bit = ccr_bit (operands[1], 1);
12167 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12168 int count;
12169
12170 /* Force split for non-cc0 compare. */
12171 if (which_alternative == 1)
12172 return \"#\";
12173
12174 if (is_bit >= put_bit)
12175 count = is_bit - put_bit;
12176 else
12177 count = 32 - (put_bit - is_bit);
12178
12179 operands[5] = GEN_INT (count);
12180 operands[6] = GEN_INT (put_bit);
12181
12182 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
12183 }"
12184 [(set_attr "type" "delayed_compare")
12185 (set_attr "length" "8,16")])
12186
12187 (define_split
12188 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12189 (compare:CC
12190 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12191 [(match_operand 2 "cc_reg_operand" "")
12192 (const_int 0)])
12193 (match_operand:SI 3 "const_int_operand" ""))
12194 (const_int 0)))
12195 (set (match_operand:SI 4 "gpc_reg_operand" "")
12196 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12197 (match_dup 3)))]
12198 "reload_completed"
12199 [(set (match_dup 4)
12200 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12201 (match_dup 3)))
12202 (set (match_dup 0)
12203 (compare:CC (match_dup 4)
12204 (const_int 0)))]
12205 "")
12206
12207 ;; There is a 3 cycle delay between consecutive mfcr instructions
12208 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
12209
12210 (define_peephole
12211 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12212 (match_operator:SI 1 "scc_comparison_operator"
12213 [(match_operand 2 "cc_reg_operand" "y")
12214 (const_int 0)]))
12215 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
12216 (match_operator:SI 4 "scc_comparison_operator"
12217 [(match_operand 5 "cc_reg_operand" "y")
12218 (const_int 0)]))]
12219 "REGNO (operands[2]) != REGNO (operands[5])"
12220 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
12221 [(set_attr "type" "mfcr")
12222 (set_attr "length" "12")])
12223
12224 (define_peephole
12225 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12226 (match_operator:DI 1 "scc_comparison_operator"
12227 [(match_operand 2 "cc_reg_operand" "y")
12228 (const_int 0)]))
12229 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12230 (match_operator:DI 4 "scc_comparison_operator"
12231 [(match_operand 5 "cc_reg_operand" "y")
12232 (const_int 0)]))]
12233 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
12234 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
12235 [(set_attr "type" "mfcr")
12236 (set_attr "length" "12")])
12237
12238 ;; There are some scc insns that can be done directly, without a compare.
12239 ;; These are faster because they don't involve the communications between
12240 ;; the FXU and branch units. In fact, we will be replacing all of the
12241 ;; integer scc insns here or in the portable methods in emit_store_flag.
12242 ;;
12243 ;; Also support (neg (scc ..)) since that construct is used to replace
12244 ;; branches, (plus (scc ..) ..) since that construct is common and
12245 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12246 ;; cases where it is no more expensive than (neg (scc ..)).
12247
12248 ;; Have reload force a constant into a register for the simple insns that
12249 ;; otherwise won't accept constants. We do this because it is faster than
12250 ;; the cmp/mfcr sequence we would otherwise generate.
12251
12252 (define_mode_attr scc_eq_op2 [(SI "rKLI")
12253 (DI "rKJI")])
12254
12255 (define_insn_and_split "*eq<mode>"
12256 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12257 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
12258 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
12259 "!TARGET_POWER"
12260 "#"
12261 "!TARGET_POWER"
12262 [(set (match_dup 0)
12263 (clz:GPR (match_dup 3)))
12264 (set (match_dup 0)
12265 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
12266 {
12267 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12268 {
12269 /* Use output operand as intermediate. */
12270 operands[3] = operands[0];
12271
12272 if (logical_operand (operands[2], <MODE>mode))
12273 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12274 gen_rtx_XOR (<MODE>mode,
12275 operands[1], operands[2])));
12276 else
12277 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12278 gen_rtx_PLUS (<MODE>mode, operands[1],
12279 negate_rtx (<MODE>mode,
12280 operands[2]))));
12281 }
12282 else
12283 operands[3] = operands[1];
12284
12285 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12286 })
12287
12288 (define_insn_and_split "*eq<mode>_compare"
12289 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12290 (compare:CC
12291 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12292 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
12293 (const_int 0)))
12294 (set (match_operand:P 0 "gpc_reg_operand" "=r")
12295 (eq:P (match_dup 1) (match_dup 2)))]
12296 "!TARGET_POWER && optimize_size"
12297 "#"
12298 "!TARGET_POWER && optimize_size"
12299 [(set (match_dup 0)
12300 (clz:P (match_dup 4)))
12301 (parallel [(set (match_dup 3)
12302 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
12303 (const_int 0)))
12304 (set (match_dup 0)
12305 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
12306 {
12307 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12308 {
12309 /* Use output operand as intermediate. */
12310 operands[4] = operands[0];
12311
12312 if (logical_operand (operands[2], <MODE>mode))
12313 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12314 gen_rtx_XOR (<MODE>mode,
12315 operands[1], operands[2])));
12316 else
12317 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12318 gen_rtx_PLUS (<MODE>mode, operands[1],
12319 negate_rtx (<MODE>mode,
12320 operands[2]))));
12321 }
12322 else
12323 operands[4] = operands[1];
12324
12325 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12326 })
12327
12328 (define_insn "*eqsi_power"
12329 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
12330 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12331 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
12332 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
12333 "TARGET_POWER"
12334 "@
12335 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12336 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
12337 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12338 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12339 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
12340 [(set_attr "type" "three,two,three,three,three")
12341 (set_attr "length" "12,8,12,12,12")])
12342
12343 ;; We have insns of the form shown by the first define_insn below. If
12344 ;; there is something inside the comparison operation, we must split it.
12345 (define_split
12346 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12347 (plus:SI (match_operator 1 "comparison_operator"
12348 [(match_operand:SI 2 "" "")
12349 (match_operand:SI 3
12350 "reg_or_cint_operand" "")])
12351 (match_operand:SI 4 "gpc_reg_operand" "")))
12352 (clobber (match_operand:SI 5 "register_operand" ""))]
12353 "! gpc_reg_operand (operands[2], SImode)"
12354 [(set (match_dup 5) (match_dup 2))
12355 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
12356 (match_dup 4)))])
12357
12358 (define_insn "*plus_eqsi"
12359 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
12360 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12361 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
12362 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
12363 "TARGET_32BIT"
12364 "@
12365 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12366 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
12367 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12368 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12369 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12370 [(set_attr "type" "three,two,three,three,three")
12371 (set_attr "length" "12,8,12,12,12")])
12372
12373 (define_insn "*compare_plus_eqsi"
12374 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12375 (compare:CC
12376 (plus:SI
12377 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12378 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12379 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12380 (const_int 0)))
12381 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
12382 "TARGET_32BIT && optimize_size"
12383 "@
12384 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12385 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
12386 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12387 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12388 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12389 #
12390 #
12391 #
12392 #
12393 #"
12394 [(set_attr "type" "compare")
12395 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12396
12397 (define_split
12398 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12399 (compare:CC
12400 (plus:SI
12401 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12402 (match_operand:SI 2 "scc_eq_operand" ""))
12403 (match_operand:SI 3 "gpc_reg_operand" ""))
12404 (const_int 0)))
12405 (clobber (match_scratch:SI 4 ""))]
12406 "TARGET_32BIT && optimize_size && reload_completed"
12407 [(set (match_dup 4)
12408 (plus:SI (eq:SI (match_dup 1)
12409 (match_dup 2))
12410 (match_dup 3)))
12411 (set (match_dup 0)
12412 (compare:CC (match_dup 4)
12413 (const_int 0)))]
12414 "")
12415
12416 (define_insn "*plus_eqsi_compare"
12417 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12418 (compare:CC
12419 (plus:SI
12420 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12421 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12422 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12423 (const_int 0)))
12424 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12425 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12426 "TARGET_32BIT && optimize_size"
12427 "@
12428 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12429 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
12430 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12431 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12432 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12433 #
12434 #
12435 #
12436 #
12437 #"
12438 [(set_attr "type" "compare")
12439 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12440
12441 (define_split
12442 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12443 (compare:CC
12444 (plus:SI
12445 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12446 (match_operand:SI 2 "scc_eq_operand" ""))
12447 (match_operand:SI 3 "gpc_reg_operand" ""))
12448 (const_int 0)))
12449 (set (match_operand:SI 0 "gpc_reg_operand" "")
12450 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12451 "TARGET_32BIT && optimize_size && reload_completed"
12452 [(set (match_dup 0)
12453 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12454 (set (match_dup 4)
12455 (compare:CC (match_dup 0)
12456 (const_int 0)))]
12457 "")
12458
12459 (define_insn "*neg_eq0<mode>"
12460 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12461 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12462 (const_int 0))))]
12463 ""
12464 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
12465 [(set_attr "type" "two")
12466 (set_attr "length" "8")])
12467
12468 (define_insn_and_split "*neg_eq<mode>"
12469 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12470 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12471 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
12472 ""
12473 "#"
12474 ""
12475 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12476 {
12477 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12478 {
12479 /* Use output operand as intermediate. */
12480 operands[3] = operands[0];
12481
12482 if (logical_operand (operands[2], <MODE>mode))
12483 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12484 gen_rtx_XOR (<MODE>mode,
12485 operands[1], operands[2])));
12486 else
12487 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12488 gen_rtx_PLUS (<MODE>mode, operands[1],
12489 negate_rtx (<MODE>mode,
12490 operands[2]))));
12491 }
12492 else
12493 operands[3] = operands[1];
12494 })
12495
12496 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
12497 ;; since it nabs/sr is just as fast.
12498 (define_insn "*ne0si"
12499 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12500 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12501 (const_int 31)))
12502 (clobber (match_scratch:SI 2 "=&r"))]
12503 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
12504 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
12505 [(set_attr "type" "two")
12506 (set_attr "length" "8")])
12507
12508 (define_insn "*ne0di"
12509 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12510 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12511 (const_int 63)))
12512 (clobber (match_scratch:DI 2 "=&r"))]
12513 "TARGET_64BIT"
12514 "addic %2,%1,-1\;subfe %0,%2,%1"
12515 [(set_attr "type" "two")
12516 (set_attr "length" "8")])
12517
12518 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
12519 (define_insn "*plus_ne0si"
12520 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12521 (plus:SI (lshiftrt:SI
12522 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12523 (const_int 31))
12524 (match_operand:SI 2 "gpc_reg_operand" "r")))
12525 (clobber (match_scratch:SI 3 "=&r"))]
12526 "TARGET_32BIT"
12527 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
12528 [(set_attr "type" "two")
12529 (set_attr "length" "8")])
12530
12531 (define_insn "*plus_ne0di"
12532 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12533 (plus:DI (lshiftrt:DI
12534 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12535 (const_int 63))
12536 (match_operand:DI 2 "gpc_reg_operand" "r")))
12537 (clobber (match_scratch:DI 3 "=&r"))]
12538 "TARGET_64BIT"
12539 "addic %3,%1,-1\;addze %0,%2"
12540 [(set_attr "type" "two")
12541 (set_attr "length" "8")])
12542
12543 (define_insn "*compare_plus_ne0si"
12544 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12545 (compare:CC
12546 (plus:SI (lshiftrt:SI
12547 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12548 (const_int 31))
12549 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12550 (const_int 0)))
12551 (clobber (match_scratch:SI 3 "=&r,&r"))
12552 (clobber (match_scratch:SI 4 "=X,&r"))]
12553 "TARGET_32BIT"
12554 "@
12555 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
12556 #"
12557 [(set_attr "type" "compare")
12558 (set_attr "length" "8,12")])
12559
12560 (define_split
12561 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12562 (compare:CC
12563 (plus:SI (lshiftrt:SI
12564 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12565 (const_int 31))
12566 (match_operand:SI 2 "gpc_reg_operand" ""))
12567 (const_int 0)))
12568 (clobber (match_scratch:SI 3 ""))
12569 (clobber (match_scratch:SI 4 ""))]
12570 "TARGET_32BIT && reload_completed"
12571 [(parallel [(set (match_dup 3)
12572 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
12573 (const_int 31))
12574 (match_dup 2)))
12575 (clobber (match_dup 4))])
12576 (set (match_dup 0)
12577 (compare:CC (match_dup 3)
12578 (const_int 0)))]
12579 "")
12580
12581 (define_insn "*compare_plus_ne0di"
12582 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12583 (compare:CC
12584 (plus:DI (lshiftrt:DI
12585 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12586 (const_int 63))
12587 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12588 (const_int 0)))
12589 (clobber (match_scratch:DI 3 "=&r,&r"))]
12590 "TARGET_64BIT"
12591 "@
12592 addic %3,%1,-1\;addze. %3,%2
12593 #"
12594 [(set_attr "type" "compare")
12595 (set_attr "length" "8,12")])
12596
12597 (define_split
12598 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12599 (compare:CC
12600 (plus:DI (lshiftrt:DI
12601 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12602 (const_int 63))
12603 (match_operand:DI 2 "gpc_reg_operand" ""))
12604 (const_int 0)))
12605 (clobber (match_scratch:DI 3 ""))]
12606 "TARGET_64BIT && reload_completed"
12607 [(set (match_dup 3)
12608 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12609 (const_int 63))
12610 (match_dup 2)))
12611 (set (match_dup 0)
12612 (compare:CC (match_dup 3)
12613 (const_int 0)))]
12614 "")
12615
12616 (define_insn "*plus_ne0si_compare"
12617 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12618 (compare:CC
12619 (plus:SI (lshiftrt:SI
12620 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12621 (const_int 31))
12622 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12623 (const_int 0)))
12624 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12625 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12626 (match_dup 2)))
12627 (clobber (match_scratch:SI 3 "=&r,&r"))]
12628 "TARGET_32BIT"
12629 "@
12630 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
12631 #"
12632 [(set_attr "type" "compare")
12633 (set_attr "length" "8,12")])
12634
12635 (define_split
12636 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12637 (compare:CC
12638 (plus:SI (lshiftrt:SI
12639 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12640 (const_int 31))
12641 (match_operand:SI 2 "gpc_reg_operand" ""))
12642 (const_int 0)))
12643 (set (match_operand:SI 0 "gpc_reg_operand" "")
12644 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12645 (match_dup 2)))
12646 (clobber (match_scratch:SI 3 ""))]
12647 "TARGET_32BIT && reload_completed"
12648 [(parallel [(set (match_dup 0)
12649 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12650 (match_dup 2)))
12651 (clobber (match_dup 3))])
12652 (set (match_dup 4)
12653 (compare:CC (match_dup 0)
12654 (const_int 0)))]
12655 "")
12656
12657 (define_insn "*plus_ne0di_compare"
12658 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12659 (compare:CC
12660 (plus:DI (lshiftrt:DI
12661 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12662 (const_int 63))
12663 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12664 (const_int 0)))
12665 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12666 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12667 (match_dup 2)))
12668 (clobber (match_scratch:DI 3 "=&r,&r"))]
12669 "TARGET_64BIT"
12670 "@
12671 addic %3,%1,-1\;addze. %0,%2
12672 #"
12673 [(set_attr "type" "compare")
12674 (set_attr "length" "8,12")])
12675
12676 (define_split
12677 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12678 (compare:CC
12679 (plus:DI (lshiftrt:DI
12680 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12681 (const_int 63))
12682 (match_operand:DI 2 "gpc_reg_operand" ""))
12683 (const_int 0)))
12684 (set (match_operand:DI 0 "gpc_reg_operand" "")
12685 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12686 (match_dup 2)))
12687 (clobber (match_scratch:DI 3 ""))]
12688 "TARGET_64BIT && reload_completed"
12689 [(parallel [(set (match_dup 0)
12690 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12691 (match_dup 2)))
12692 (clobber (match_dup 3))])
12693 (set (match_dup 4)
12694 (compare:CC (match_dup 0)
12695 (const_int 0)))]
12696 "")
12697
12698 (define_insn ""
12699 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12700 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12701 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12702 (clobber (match_scratch:SI 3 "=r,X"))]
12703 "TARGET_POWER"
12704 "@
12705 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
12706 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
12707 [(set_attr "length" "12")])
12708
12709 (define_insn ""
12710 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12711 (compare:CC
12712 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12713 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12714 (const_int 0)))
12715 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12716 (le:SI (match_dup 1) (match_dup 2)))
12717 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
12718 "TARGET_POWER"
12719 "@
12720 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12721 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
12722 #
12723 #"
12724 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
12725 (set_attr "length" "12,12,16,16")])
12726
12727 (define_split
12728 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12729 (compare:CC
12730 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12731 (match_operand:SI 2 "reg_or_short_operand" ""))
12732 (const_int 0)))
12733 (set (match_operand:SI 0 "gpc_reg_operand" "")
12734 (le:SI (match_dup 1) (match_dup 2)))
12735 (clobber (match_scratch:SI 3 ""))]
12736 "TARGET_POWER && reload_completed"
12737 [(parallel [(set (match_dup 0)
12738 (le:SI (match_dup 1) (match_dup 2)))
12739 (clobber (match_dup 3))])
12740 (set (match_dup 4)
12741 (compare:CC (match_dup 0)
12742 (const_int 0)))]
12743 "")
12744
12745 (define_insn ""
12746 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12747 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12748 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
12749 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12750 "TARGET_POWER"
12751 "@
12752 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12753 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
12754 [(set_attr "length" "12")])
12755
12756 (define_insn ""
12757 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12758 (compare:CC
12759 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12760 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12761 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12762 (const_int 0)))
12763 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12764 "TARGET_POWER"
12765 "@
12766 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12767 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12768 #
12769 #"
12770 [(set_attr "type" "compare")
12771 (set_attr "length" "12,12,16,16")])
12772
12773 (define_split
12774 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12775 (compare:CC
12776 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12777 (match_operand:SI 2 "reg_or_short_operand" ""))
12778 (match_operand:SI 3 "gpc_reg_operand" ""))
12779 (const_int 0)))
12780 (clobber (match_scratch:SI 4 ""))]
12781 "TARGET_POWER && reload_completed"
12782 [(set (match_dup 4)
12783 (plus:SI (le:SI (match_dup 1) (match_dup 2))
12784 (match_dup 3)))
12785 (set (match_dup 0)
12786 (compare:CC (match_dup 4)
12787 (const_int 0)))]
12788 "")
12789
12790 (define_insn ""
12791 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12792 (compare:CC
12793 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12794 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12795 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12796 (const_int 0)))
12797 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12798 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12799 "TARGET_POWER"
12800 "@
12801 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12802 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
12803 #
12804 #"
12805 [(set_attr "type" "compare")
12806 (set_attr "length" "12,12,16,16")])
12807
12808 (define_split
12809 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12810 (compare:CC
12811 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12812 (match_operand:SI 2 "reg_or_short_operand" ""))
12813 (match_operand:SI 3 "gpc_reg_operand" ""))
12814 (const_int 0)))
12815 (set (match_operand:SI 0 "gpc_reg_operand" "")
12816 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12817 "TARGET_POWER && reload_completed"
12818 [(set (match_dup 0)
12819 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12820 (set (match_dup 4)
12821 (compare:CC (match_dup 0)
12822 (const_int 0)))]
12823 "")
12824
12825 (define_insn ""
12826 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12827 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12828 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
12829 "TARGET_POWER"
12830 "@
12831 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12832 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
12833 [(set_attr "length" "12")])
12834
12835 (define_insn "*leu<mode>"
12836 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12837 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12838 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12839 ""
12840 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12841 [(set_attr "type" "three")
12842 (set_attr "length" "12")])
12843
12844 (define_insn "*leu<mode>_compare"
12845 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12846 (compare:CC
12847 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12848 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12849 (const_int 0)))
12850 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12851 (leu:P (match_dup 1) (match_dup 2)))]
12852 ""
12853 "@
12854 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12855 #"
12856 [(set_attr "type" "compare")
12857 (set_attr "length" "12,16")])
12858
12859 (define_split
12860 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12861 (compare:CC
12862 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12863 (match_operand:P 2 "reg_or_short_operand" ""))
12864 (const_int 0)))
12865 (set (match_operand:P 0 "gpc_reg_operand" "")
12866 (leu:P (match_dup 1) (match_dup 2)))]
12867 "reload_completed"
12868 [(set (match_dup 0)
12869 (leu:P (match_dup 1) (match_dup 2)))
12870 (set (match_dup 3)
12871 (compare:CC (match_dup 0)
12872 (const_int 0)))]
12873 "")
12874
12875 (define_insn "*plus_leu<mode>"
12876 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12877 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12878 (match_operand:P 2 "reg_or_short_operand" "rI"))
12879 (match_operand:P 3 "gpc_reg_operand" "r")))]
12880 ""
12881 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12882 [(set_attr "type" "two")
12883 (set_attr "length" "8")])
12884
12885 (define_insn ""
12886 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12887 (compare:CC
12888 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12889 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12890 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12891 (const_int 0)))
12892 (clobber (match_scratch:SI 4 "=&r,&r"))]
12893 "TARGET_32BIT"
12894 "@
12895 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12896 #"
12897 [(set_attr "type" "compare")
12898 (set_attr "length" "8,12")])
12899
12900 (define_split
12901 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12902 (compare:CC
12903 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12904 (match_operand:SI 2 "reg_or_short_operand" ""))
12905 (match_operand:SI 3 "gpc_reg_operand" ""))
12906 (const_int 0)))
12907 (clobber (match_scratch:SI 4 ""))]
12908 "TARGET_32BIT && reload_completed"
12909 [(set (match_dup 4)
12910 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12911 (match_dup 3)))
12912 (set (match_dup 0)
12913 (compare:CC (match_dup 4)
12914 (const_int 0)))]
12915 "")
12916
12917 (define_insn ""
12918 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12919 (compare:CC
12920 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12921 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12922 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12923 (const_int 0)))
12924 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12925 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12926 "TARGET_32BIT"
12927 "@
12928 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12929 #"
12930 [(set_attr "type" "compare")
12931 (set_attr "length" "8,12")])
12932
12933 (define_split
12934 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12935 (compare:CC
12936 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12937 (match_operand:SI 2 "reg_or_short_operand" ""))
12938 (match_operand:SI 3 "gpc_reg_operand" ""))
12939 (const_int 0)))
12940 (set (match_operand:SI 0 "gpc_reg_operand" "")
12941 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12942 "TARGET_32BIT && reload_completed"
12943 [(set (match_dup 0)
12944 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12945 (set (match_dup 4)
12946 (compare:CC (match_dup 0)
12947 (const_int 0)))]
12948 "")
12949
12950 (define_insn "*neg_leu<mode>"
12951 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12952 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12953 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12954 ""
12955 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12956 [(set_attr "type" "three")
12957 (set_attr "length" "12")])
12958
12959 (define_insn "*and_neg_leu<mode>"
12960 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12961 (and:P (neg:P
12962 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12963 (match_operand:P 2 "reg_or_short_operand" "rI")))
12964 (match_operand:P 3 "gpc_reg_operand" "r")))]
12965 ""
12966 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12967 [(set_attr "type" "three")
12968 (set_attr "length" "12")])
12969
12970 (define_insn ""
12971 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12972 (compare:CC
12973 (and:SI (neg:SI
12974 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12975 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12976 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12977 (const_int 0)))
12978 (clobber (match_scratch:SI 4 "=&r,&r"))]
12979 "TARGET_32BIT"
12980 "@
12981 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12982 #"
12983 [(set_attr "type" "compare")
12984 (set_attr "length" "12,16")])
12985
12986 (define_split
12987 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12988 (compare:CC
12989 (and:SI (neg:SI
12990 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12991 (match_operand:SI 2 "reg_or_short_operand" "")))
12992 (match_operand:SI 3 "gpc_reg_operand" ""))
12993 (const_int 0)))
12994 (clobber (match_scratch:SI 4 ""))]
12995 "TARGET_32BIT && reload_completed"
12996 [(set (match_dup 4)
12997 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12998 (match_dup 3)))
12999 (set (match_dup 0)
13000 (compare:CC (match_dup 4)
13001 (const_int 0)))]
13002 "")
13003
13004 (define_insn ""
13005 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13006 (compare:CC
13007 (and:SI (neg:SI
13008 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13009 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13010 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13011 (const_int 0)))
13012 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13013 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13014 "TARGET_32BIT"
13015 "@
13016 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13017 #"
13018 [(set_attr "type" "compare")
13019 (set_attr "length" "12,16")])
13020
13021 (define_split
13022 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13023 (compare:CC
13024 (and:SI (neg:SI
13025 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13026 (match_operand:SI 2 "reg_or_short_operand" "")))
13027 (match_operand:SI 3 "gpc_reg_operand" ""))
13028 (const_int 0)))
13029 (set (match_operand:SI 0 "gpc_reg_operand" "")
13030 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13031 "TARGET_32BIT && reload_completed"
13032 [(set (match_dup 0)
13033 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13034 (match_dup 3)))
13035 (set (match_dup 4)
13036 (compare:CC (match_dup 0)
13037 (const_int 0)))]
13038 "")
13039
13040 (define_insn ""
13041 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13042 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13043 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13044 "TARGET_POWER"
13045 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13046 [(set_attr "length" "12")])
13047
13048 (define_insn ""
13049 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13050 (compare:CC
13051 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13052 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13053 (const_int 0)))
13054 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13055 (lt:SI (match_dup 1) (match_dup 2)))]
13056 "TARGET_POWER"
13057 "@
13058 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13059 #"
13060 [(set_attr "type" "delayed_compare")
13061 (set_attr "length" "12,16")])
13062
13063 (define_split
13064 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13065 (compare:CC
13066 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13067 (match_operand:SI 2 "reg_or_short_operand" ""))
13068 (const_int 0)))
13069 (set (match_operand:SI 0 "gpc_reg_operand" "")
13070 (lt:SI (match_dup 1) (match_dup 2)))]
13071 "TARGET_POWER && reload_completed"
13072 [(set (match_dup 0)
13073 (lt:SI (match_dup 1) (match_dup 2)))
13074 (set (match_dup 3)
13075 (compare:CC (match_dup 0)
13076 (const_int 0)))]
13077 "")
13078
13079 (define_insn ""
13080 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13081 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13082 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13083 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13084 "TARGET_POWER"
13085 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13086 [(set_attr "length" "12")])
13087
13088 (define_insn ""
13089 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13090 (compare:CC
13091 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13092 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13093 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13094 (const_int 0)))
13095 (clobber (match_scratch:SI 4 "=&r,&r"))]
13096 "TARGET_POWER"
13097 "@
13098 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13099 #"
13100 [(set_attr "type" "compare")
13101 (set_attr "length" "12,16")])
13102
13103 (define_split
13104 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13105 (compare:CC
13106 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13107 (match_operand:SI 2 "reg_or_short_operand" ""))
13108 (match_operand:SI 3 "gpc_reg_operand" ""))
13109 (const_int 0)))
13110 (clobber (match_scratch:SI 4 ""))]
13111 "TARGET_POWER && reload_completed"
13112 [(set (match_dup 4)
13113 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
13114 (match_dup 3)))
13115 (set (match_dup 0)
13116 (compare:CC (match_dup 4)
13117 (const_int 0)))]
13118 "")
13119
13120 (define_insn ""
13121 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13122 (compare:CC
13123 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13124 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13125 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13126 (const_int 0)))
13127 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13128 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13129 "TARGET_POWER"
13130 "@
13131 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13132 #"
13133 [(set_attr "type" "compare")
13134 (set_attr "length" "12,16")])
13135
13136 (define_split
13137 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13138 (compare:CC
13139 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13140 (match_operand:SI 2 "reg_or_short_operand" ""))
13141 (match_operand:SI 3 "gpc_reg_operand" ""))
13142 (const_int 0)))
13143 (set (match_operand:SI 0 "gpc_reg_operand" "")
13144 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13145 "TARGET_POWER && reload_completed"
13146 [(set (match_dup 0)
13147 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13148 (set (match_dup 4)
13149 (compare:CC (match_dup 0)
13150 (const_int 0)))]
13151 "")
13152
13153 (define_insn ""
13154 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13155 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13156 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13157 "TARGET_POWER"
13158 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13159 [(set_attr "length" "12")])
13160
13161 (define_insn_and_split "*ltu<mode>"
13162 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13163 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13164 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13165 ""
13166 "#"
13167 ""
13168 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13169 (set (match_dup 0) (neg:P (match_dup 0)))]
13170 "")
13171
13172 (define_insn_and_split "*ltu<mode>_compare"
13173 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13174 (compare:CC
13175 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13176 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13177 (const_int 0)))
13178 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13179 (ltu:P (match_dup 1) (match_dup 2)))]
13180 ""
13181 "#"
13182 ""
13183 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13184 (parallel [(set (match_dup 3)
13185 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13186 (set (match_dup 0) (neg:P (match_dup 0)))])]
13187 "")
13188
13189 (define_insn_and_split "*plus_ltu<mode>"
13190 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
13191 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13192 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13193 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
13194 ""
13195 "#"
13196 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13197 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13198 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13199 "")
13200
13201 (define_insn_and_split "*plus_ltu<mode>_compare"
13202 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13203 (compare:CC
13204 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13205 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13206 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13207 (const_int 0)))
13208 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13209 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13210 ""
13211 "#"
13212 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13213 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13214 (parallel [(set (match_dup 4)
13215 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13216 (const_int 0)))
13217 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13218 "")
13219
13220 (define_insn "*neg_ltu<mode>"
13221 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13222 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13223 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
13224 ""
13225 "@
13226 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
13227 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
13228 [(set_attr "type" "two")
13229 (set_attr "length" "8")])
13230
13231 (define_insn ""
13232 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13233 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13234 (match_operand:SI 2 "reg_or_short_operand" "rI")))
13235 (clobber (match_scratch:SI 3 "=r"))]
13236 "TARGET_POWER"
13237 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
13238 [(set_attr "length" "12")])
13239
13240 (define_insn ""
13241 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13242 (compare:CC
13243 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13244 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13245 (const_int 0)))
13246 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13247 (ge:SI (match_dup 1) (match_dup 2)))
13248 (clobber (match_scratch:SI 3 "=r,r"))]
13249 "TARGET_POWER"
13250 "@
13251 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13252 #"
13253 [(set_attr "type" "compare")
13254 (set_attr "length" "12,16")])
13255
13256 (define_split
13257 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13258 (compare:CC
13259 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13260 (match_operand:SI 2 "reg_or_short_operand" ""))
13261 (const_int 0)))
13262 (set (match_operand:SI 0 "gpc_reg_operand" "")
13263 (ge:SI (match_dup 1) (match_dup 2)))
13264 (clobber (match_scratch:SI 3 ""))]
13265 "TARGET_POWER && reload_completed"
13266 [(parallel [(set (match_dup 0)
13267 (ge:SI (match_dup 1) (match_dup 2)))
13268 (clobber (match_dup 3))])
13269 (set (match_dup 4)
13270 (compare:CC (match_dup 0)
13271 (const_int 0)))]
13272 "")
13273
13274 (define_insn ""
13275 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13276 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13277 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13278 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13279 "TARGET_POWER"
13280 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
13281 [(set_attr "length" "12")])
13282
13283 (define_insn ""
13284 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13285 (compare:CC
13286 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13287 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13288 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13289 (const_int 0)))
13290 (clobber (match_scratch:SI 4 "=&r,&r"))]
13291 "TARGET_POWER"
13292 "@
13293 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13294 #"
13295 [(set_attr "type" "compare")
13296 (set_attr "length" "12,16")])
13297
13298 (define_split
13299 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13300 (compare:CC
13301 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13302 (match_operand:SI 2 "reg_or_short_operand" ""))
13303 (match_operand:SI 3 "gpc_reg_operand" ""))
13304 (const_int 0)))
13305 (clobber (match_scratch:SI 4 ""))]
13306 "TARGET_POWER && reload_completed"
13307 [(set (match_dup 4)
13308 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
13309 (match_dup 3)))
13310 (set (match_dup 0)
13311 (compare:CC (match_dup 4)
13312 (const_int 0)))]
13313 "")
13314
13315 (define_insn ""
13316 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13317 (compare:CC
13318 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13319 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13320 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13321 (const_int 0)))
13322 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13323 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13324 "TARGET_POWER"
13325 "@
13326 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13327 #"
13328 [(set_attr "type" "compare")
13329 (set_attr "length" "12,16")])
13330
13331 (define_split
13332 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13333 (compare:CC
13334 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13335 (match_operand:SI 2 "reg_or_short_operand" ""))
13336 (match_operand:SI 3 "gpc_reg_operand" ""))
13337 (const_int 0)))
13338 (set (match_operand:SI 0 "gpc_reg_operand" "")
13339 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13340 "TARGET_POWER && reload_completed"
13341 [(set (match_dup 0)
13342 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13343 (set (match_dup 4)
13344 (compare:CC (match_dup 0)
13345 (const_int 0)))]
13346 "")
13347
13348 (define_insn ""
13349 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13350 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13351 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13352 "TARGET_POWER"
13353 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
13354 [(set_attr "length" "12")])
13355
13356 (define_insn "*geu<mode>"
13357 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13358 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13359 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13360 ""
13361 "@
13362 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
13363 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
13364 [(set_attr "type" "three")
13365 (set_attr "length" "12")])
13366
13367 (define_insn "*geu<mode>_compare"
13368 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13369 (compare:CC
13370 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13371 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13372 (const_int 0)))
13373 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13374 (geu:P (match_dup 1) (match_dup 2)))]
13375 ""
13376 "@
13377 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13378 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13379 #
13380 #"
13381 [(set_attr "type" "compare")
13382 (set_attr "length" "12,12,16,16")])
13383
13384 (define_split
13385 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13386 (compare:CC
13387 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
13388 (match_operand:P 2 "reg_or_neg_short_operand" ""))
13389 (const_int 0)))
13390 (set (match_operand:P 0 "gpc_reg_operand" "")
13391 (geu:P (match_dup 1) (match_dup 2)))]
13392 "reload_completed"
13393 [(set (match_dup 0)
13394 (geu:P (match_dup 1) (match_dup 2)))
13395 (set (match_dup 3)
13396 (compare:CC (match_dup 0)
13397 (const_int 0)))]
13398 "")
13399
13400 (define_insn "*plus_geu<mode>"
13401 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13402 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13403 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13404 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13405 ""
13406 "@
13407 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
13408 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
13409 [(set_attr "type" "two")
13410 (set_attr "length" "8")])
13411
13412 (define_insn ""
13413 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13414 (compare:CC
13415 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13416 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13417 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13418 (const_int 0)))
13419 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13420 "TARGET_32BIT"
13421 "@
13422 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
13423 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
13424 #
13425 #"
13426 [(set_attr "type" "compare")
13427 (set_attr "length" "8,8,12,12")])
13428
13429 (define_split
13430 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13431 (compare:CC
13432 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13433 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13434 (match_operand:SI 3 "gpc_reg_operand" ""))
13435 (const_int 0)))
13436 (clobber (match_scratch:SI 4 ""))]
13437 "TARGET_32BIT && reload_completed"
13438 [(set (match_dup 4)
13439 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13440 (match_dup 3)))
13441 (set (match_dup 0)
13442 (compare:CC (match_dup 4)
13443 (const_int 0)))]
13444 "")
13445
13446 (define_insn ""
13447 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13448 (compare:CC
13449 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13450 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13451 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13452 (const_int 0)))
13453 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13454 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13455 "TARGET_32BIT"
13456 "@
13457 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
13458 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
13459 #
13460 #"
13461 [(set_attr "type" "compare")
13462 (set_attr "length" "8,8,12,12")])
13463
13464 (define_split
13465 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13466 (compare:CC
13467 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13468 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13469 (match_operand:SI 3 "gpc_reg_operand" ""))
13470 (const_int 0)))
13471 (set (match_operand:SI 0 "gpc_reg_operand" "")
13472 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13473 "TARGET_32BIT && reload_completed"
13474 [(set (match_dup 0)
13475 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13476 (set (match_dup 4)
13477 (compare:CC (match_dup 0)
13478 (const_int 0)))]
13479 "")
13480
13481 (define_insn "*neg_geu<mode>"
13482 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13483 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13484 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13485 ""
13486 "@
13487 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
13488 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
13489 [(set_attr "type" "three")
13490 (set_attr "length" "12")])
13491
13492 (define_insn "*and_neg_geu<mode>"
13493 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13494 (and:P (neg:P
13495 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13496 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13497 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13498 ""
13499 "@
13500 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
13501 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13502 [(set_attr "type" "three")
13503 (set_attr "length" "12")])
13504
13505 (define_insn ""
13506 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13507 (compare:CC
13508 (and:SI (neg:SI
13509 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13510 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13511 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13512 (const_int 0)))
13513 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13514 "TARGET_32BIT"
13515 "@
13516 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13517 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13518 #
13519 #"
13520 [(set_attr "type" "compare")
13521 (set_attr "length" "12,12,16,16")])
13522
13523 (define_split
13524 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13525 (compare:CC
13526 (and:SI (neg:SI
13527 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13528 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13529 (match_operand:SI 3 "gpc_reg_operand" ""))
13530 (const_int 0)))
13531 (clobber (match_scratch:SI 4 ""))]
13532 "TARGET_32BIT && reload_completed"
13533 [(set (match_dup 4)
13534 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13535 (match_dup 3)))
13536 (set (match_dup 0)
13537 (compare:CC (match_dup 4)
13538 (const_int 0)))]
13539 "")
13540
13541 (define_insn ""
13542 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13543 (compare:CC
13544 (and:SI (neg:SI
13545 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13546 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13547 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13548 (const_int 0)))
13549 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13550 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13551 "TARGET_32BIT"
13552 "@
13553 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13554 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13555 #
13556 #"
13557 [(set_attr "type" "compare")
13558 (set_attr "length" "12,12,16,16")])
13559
13560 (define_split
13561 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13562 (compare:CC
13563 (and:SI (neg:SI
13564 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13565 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13566 (match_operand:SI 3 "gpc_reg_operand" ""))
13567 (const_int 0)))
13568 (set (match_operand:SI 0 "gpc_reg_operand" "")
13569 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13570 "TARGET_32BIT && reload_completed"
13571 [(set (match_dup 0)
13572 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13573 (set (match_dup 4)
13574 (compare:CC (match_dup 0)
13575 (const_int 0)))]
13576 "")
13577
13578 (define_insn ""
13579 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13580 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13581 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13582 "TARGET_POWER"
13583 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13584 [(set_attr "length" "12")])
13585
13586 (define_insn ""
13587 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13588 (compare:CC
13589 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13590 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13591 (const_int 0)))
13592 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13593 (gt:SI (match_dup 1) (match_dup 2)))]
13594 "TARGET_POWER"
13595 "@
13596 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13597 #"
13598 [(set_attr "type" "delayed_compare")
13599 (set_attr "length" "12,16")])
13600
13601 (define_split
13602 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13603 (compare:CC
13604 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13605 (match_operand:SI 2 "reg_or_short_operand" ""))
13606 (const_int 0)))
13607 (set (match_operand:SI 0 "gpc_reg_operand" "")
13608 (gt:SI (match_dup 1) (match_dup 2)))]
13609 "TARGET_POWER && reload_completed"
13610 [(set (match_dup 0)
13611 (gt:SI (match_dup 1) (match_dup 2)))
13612 (set (match_dup 3)
13613 (compare:CC (match_dup 0)
13614 (const_int 0)))]
13615 "")
13616
13617 (define_insn "*plus_gt0<mode>"
13618 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13619 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13620 (const_int 0))
13621 (match_operand:P 2 "gpc_reg_operand" "r")))]
13622 ""
13623 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13624 [(set_attr "type" "three")
13625 (set_attr "length" "12")])
13626
13627 (define_insn ""
13628 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13629 (compare:CC
13630 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13631 (const_int 0))
13632 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13633 (const_int 0)))
13634 (clobber (match_scratch:SI 3 "=&r,&r"))]
13635 "TARGET_32BIT"
13636 "@
13637 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13638 #"
13639 [(set_attr "type" "compare")
13640 (set_attr "length" "12,16")])
13641
13642 (define_split
13643 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13644 (compare:CC
13645 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13646 (const_int 0))
13647 (match_operand:SI 2 "gpc_reg_operand" ""))
13648 (const_int 0)))
13649 (clobber (match_scratch:SI 3 ""))]
13650 "TARGET_32BIT && reload_completed"
13651 [(set (match_dup 3)
13652 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13653 (match_dup 2)))
13654 (set (match_dup 0)
13655 (compare:CC (match_dup 3)
13656 (const_int 0)))]
13657 "")
13658
13659 (define_insn ""
13660 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13661 (compare:CC
13662 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13663 (const_int 0))
13664 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13665 (const_int 0)))
13666 (clobber (match_scratch:DI 3 "=&r,&r"))]
13667 "TARGET_64BIT"
13668 "@
13669 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13670 #"
13671 [(set_attr "type" "compare")
13672 (set_attr "length" "12,16")])
13673
13674 (define_split
13675 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13676 (compare:CC
13677 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13678 (const_int 0))
13679 (match_operand:DI 2 "gpc_reg_operand" ""))
13680 (const_int 0)))
13681 (clobber (match_scratch:DI 3 ""))]
13682 "TARGET_64BIT && reload_completed"
13683 [(set (match_dup 3)
13684 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13685 (match_dup 2)))
13686 (set (match_dup 0)
13687 (compare:CC (match_dup 3)
13688 (const_int 0)))]
13689 "")
13690
13691 (define_insn ""
13692 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13693 (compare:CC
13694 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13695 (const_int 0))
13696 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13697 (const_int 0)))
13698 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13699 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13700 "TARGET_32BIT"
13701 "@
13702 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13703 #"
13704 [(set_attr "type" "compare")
13705 (set_attr "length" "12,16")])
13706
13707 (define_split
13708 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13709 (compare:CC
13710 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13711 (const_int 0))
13712 (match_operand:SI 2 "gpc_reg_operand" ""))
13713 (const_int 0)))
13714 (set (match_operand:SI 0 "gpc_reg_operand" "")
13715 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13716 "TARGET_32BIT && reload_completed"
13717 [(set (match_dup 0)
13718 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13719 (set (match_dup 3)
13720 (compare:CC (match_dup 0)
13721 (const_int 0)))]
13722 "")
13723
13724 (define_insn ""
13725 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13726 (compare:CC
13727 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13728 (const_int 0))
13729 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13730 (const_int 0)))
13731 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13732 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13733 "TARGET_64BIT"
13734 "@
13735 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13736 #"
13737 [(set_attr "type" "compare")
13738 (set_attr "length" "12,16")])
13739
13740 (define_split
13741 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13742 (compare:CC
13743 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13744 (const_int 0))
13745 (match_operand:DI 2 "gpc_reg_operand" ""))
13746 (const_int 0)))
13747 (set (match_operand:DI 0 "gpc_reg_operand" "")
13748 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13749 "TARGET_64BIT && reload_completed"
13750 [(set (match_dup 0)
13751 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13752 (set (match_dup 3)
13753 (compare:CC (match_dup 0)
13754 (const_int 0)))]
13755 "")
13756
13757 (define_insn ""
13758 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13759 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13760 (match_operand:SI 2 "reg_or_short_operand" "r"))
13761 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13762 "TARGET_POWER"
13763 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13764 [(set_attr "length" "12")])
13765
13766 (define_insn ""
13767 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13768 (compare:CC
13769 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13770 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13771 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13772 (const_int 0)))
13773 (clobber (match_scratch:SI 4 "=&r,&r"))]
13774 "TARGET_POWER"
13775 "@
13776 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13777 #"
13778 [(set_attr "type" "compare")
13779 (set_attr "length" "12,16")])
13780
13781 (define_split
13782 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13783 (compare:CC
13784 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13785 (match_operand:SI 2 "reg_or_short_operand" ""))
13786 (match_operand:SI 3 "gpc_reg_operand" ""))
13787 (const_int 0)))
13788 (clobber (match_scratch:SI 4 ""))]
13789 "TARGET_POWER && reload_completed"
13790 [(set (match_dup 4)
13791 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13792 (set (match_dup 0)
13793 (compare:CC (match_dup 4)
13794 (const_int 0)))]
13795 "")
13796
13797 (define_insn ""
13798 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13799 (compare:CC
13800 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13801 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13802 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13803 (const_int 0)))
13804 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13805 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13806 "TARGET_POWER"
13807 "@
13808 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13809 #"
13810 [(set_attr "type" "compare")
13811 (set_attr "length" "12,16")])
13812
13813 (define_split
13814 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13815 (compare:CC
13816 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13817 (match_operand:SI 2 "reg_or_short_operand" ""))
13818 (match_operand:SI 3 "gpc_reg_operand" ""))
13819 (const_int 0)))
13820 (set (match_operand:SI 0 "gpc_reg_operand" "")
13821 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13822 "TARGET_POWER && reload_completed"
13823 [(set (match_dup 0)
13824 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13825 (set (match_dup 4)
13826 (compare:CC (match_dup 0)
13827 (const_int 0)))]
13828 "")
13829
13830 (define_insn ""
13831 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13832 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13833 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13834 "TARGET_POWER"
13835 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13836 [(set_attr "length" "12")])
13837
13838 (define_insn_and_split "*gtu<mode>"
13839 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13840 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13841 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13842 ""
13843 "#"
13844 ""
13845 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13846 (set (match_dup 0) (neg:P (match_dup 0)))]
13847 "")
13848
13849 (define_insn_and_split "*gtu<mode>_compare"
13850 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13851 (compare:CC
13852 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13853 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13854 (const_int 0)))
13855 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13856 (gtu:P (match_dup 1) (match_dup 2)))]
13857 ""
13858 "#"
13859 ""
13860 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13861 (parallel [(set (match_dup 3)
13862 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13863 (set (match_dup 0) (neg:P (match_dup 0)))])]
13864 "")
13865
13866 (define_insn_and_split "*plus_gtu<mode>"
13867 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13868 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13869 (match_operand:P 2 "reg_or_short_operand" "rI"))
13870 (match_operand:P 3 "reg_or_short_operand" "rI")))]
13871 ""
13872 "#"
13873 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13874 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13875 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13876 "")
13877
13878 (define_insn_and_split "*plus_gtu<mode>_compare"
13879 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13880 (compare:CC
13881 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13882 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13883 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13884 (const_int 0)))
13885 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13886 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13887 ""
13888 "#"
13889 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13890 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13891 (parallel [(set (match_dup 4)
13892 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13893 (const_int 0)))
13894 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13895 "")
13896
13897 (define_insn "*neg_gtu<mode>"
13898 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13899 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13900 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13901 ""
13902 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13903 [(set_attr "type" "two")
13904 (set_attr "length" "8")])
13905
13906 \f
13907 ;; Define both directions of branch and return. If we need a reload
13908 ;; register, we'd rather use CR0 since it is much easier to copy a
13909 ;; register CC value to there.
13910
13911 (define_insn ""
13912 [(set (pc)
13913 (if_then_else (match_operator 1 "branch_comparison_operator"
13914 [(match_operand 2
13915 "cc_reg_operand" "y")
13916 (const_int 0)])
13917 (label_ref (match_operand 0 "" ""))
13918 (pc)))]
13919 ""
13920 "*
13921 {
13922 return output_cbranch (operands[1], \"%l0\", 0, insn);
13923 }"
13924 [(set_attr "type" "branch")])
13925
13926 (define_insn ""
13927 [(set (pc)
13928 (if_then_else (match_operator 0 "branch_comparison_operator"
13929 [(match_operand 1
13930 "cc_reg_operand" "y")
13931 (const_int 0)])
13932 (return)
13933 (pc)))]
13934 "direct_return ()"
13935 "*
13936 {
13937 return output_cbranch (operands[0], NULL, 0, insn);
13938 }"
13939 [(set_attr "type" "jmpreg")
13940 (set_attr "length" "4")])
13941
13942 (define_insn ""
13943 [(set (pc)
13944 (if_then_else (match_operator 1 "branch_comparison_operator"
13945 [(match_operand 2
13946 "cc_reg_operand" "y")
13947 (const_int 0)])
13948 (pc)
13949 (label_ref (match_operand 0 "" ""))))]
13950 ""
13951 "*
13952 {
13953 return output_cbranch (operands[1], \"%l0\", 1, insn);
13954 }"
13955 [(set_attr "type" "branch")])
13956
13957 (define_insn ""
13958 [(set (pc)
13959 (if_then_else (match_operator 0 "branch_comparison_operator"
13960 [(match_operand 1
13961 "cc_reg_operand" "y")
13962 (const_int 0)])
13963 (pc)
13964 (return)))]
13965 "direct_return ()"
13966 "*
13967 {
13968 return output_cbranch (operands[0], NULL, 1, insn);
13969 }"
13970 [(set_attr "type" "jmpreg")
13971 (set_attr "length" "4")])
13972
13973 ;; Logic on condition register values.
13974
13975 ; This pattern matches things like
13976 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13977 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13978 ; (const_int 1)))
13979 ; which are generated by the branch logic.
13980 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13981
13982 (define_insn "*cceq_ior_compare"
13983 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13984 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13985 [(match_operator:SI 2
13986 "branch_positive_comparison_operator"
13987 [(match_operand 3
13988 "cc_reg_operand" "y,y")
13989 (const_int 0)])
13990 (match_operator:SI 4
13991 "branch_positive_comparison_operator"
13992 [(match_operand 5
13993 "cc_reg_operand" "0,y")
13994 (const_int 0)])])
13995 (const_int 1)))]
13996 ""
13997 "cr%q1 %E0,%j2,%j4"
13998 [(set_attr "type" "cr_logical,delayed_cr")])
13999
14000 ; Why is the constant -1 here, but 1 in the previous pattern?
14001 ; Because ~1 has all but the low bit set.
14002 (define_insn ""
14003 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14004 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
14005 [(not:SI (match_operator:SI 2
14006 "branch_positive_comparison_operator"
14007 [(match_operand 3
14008 "cc_reg_operand" "y,y")
14009 (const_int 0)]))
14010 (match_operator:SI 4
14011 "branch_positive_comparison_operator"
14012 [(match_operand 5
14013 "cc_reg_operand" "0,y")
14014 (const_int 0)])])
14015 (const_int -1)))]
14016 ""
14017 "cr%q1 %E0,%j2,%j4"
14018 [(set_attr "type" "cr_logical,delayed_cr")])
14019
14020 (define_insn "*cceq_rev_compare"
14021 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14022 (compare:CCEQ (match_operator:SI 1
14023 "branch_positive_comparison_operator"
14024 [(match_operand 2
14025 "cc_reg_operand" "0,y")
14026 (const_int 0)])
14027 (const_int 0)))]
14028 ""
14029 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
14030 [(set_attr "type" "cr_logical,delayed_cr")])
14031
14032 ;; If we are comparing the result of two comparisons, this can be done
14033 ;; using creqv or crxor.
14034
14035 (define_insn_and_split ""
14036 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14037 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
14038 [(match_operand 2 "cc_reg_operand" "y")
14039 (const_int 0)])
14040 (match_operator 3 "branch_comparison_operator"
14041 [(match_operand 4 "cc_reg_operand" "y")
14042 (const_int 0)])))]
14043 ""
14044 "#"
14045 ""
14046 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14047 (match_dup 5)))]
14048 "
14049 {
14050 int positive_1, positive_2;
14051
14052 positive_1 = branch_positive_comparison_operator (operands[1],
14053 GET_MODE (operands[1]));
14054 positive_2 = branch_positive_comparison_operator (operands[3],
14055 GET_MODE (operands[3]));
14056
14057 if (! positive_1)
14058 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
14059 GET_CODE (operands[1])),
14060 SImode,
14061 operands[2], const0_rtx);
14062 else if (GET_MODE (operands[1]) != SImode)
14063 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14064 operands[2], const0_rtx);
14065
14066 if (! positive_2)
14067 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
14068 GET_CODE (operands[3])),
14069 SImode,
14070 operands[4], const0_rtx);
14071 else if (GET_MODE (operands[3]) != SImode)
14072 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14073 operands[4], const0_rtx);
14074
14075 if (positive_1 == positive_2)
14076 {
14077 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14078 operands[5] = constm1_rtx;
14079 }
14080 else
14081 {
14082 operands[5] = const1_rtx;
14083 }
14084 }")
14085
14086 ;; Unconditional branch and return.
14087
14088 (define_insn "jump"
14089 [(set (pc)
14090 (label_ref (match_operand 0 "" "")))]
14091 ""
14092 "b %l0"
14093 [(set_attr "type" "branch")])
14094
14095 (define_insn "return"
14096 [(return)]
14097 "direct_return ()"
14098 "{br|blr}"
14099 [(set_attr "type" "jmpreg")])
14100
14101 (define_expand "indirect_jump"
14102 [(set (pc) (match_operand 0 "register_operand" ""))])
14103
14104 (define_insn "*indirect_jump<mode>"
14105 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14106 ""
14107 "@
14108 bctr
14109 {br|blr}"
14110 [(set_attr "type" "jmpreg")])
14111
14112 ;; Table jump for switch statements:
14113 (define_expand "tablejump"
14114 [(use (match_operand 0 "" ""))
14115 (use (label_ref (match_operand 1 "" "")))]
14116 ""
14117 "
14118 {
14119 if (TARGET_32BIT)
14120 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14121 else
14122 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14123 DONE;
14124 }")
14125
14126 (define_expand "tablejumpsi"
14127 [(set (match_dup 3)
14128 (plus:SI (match_operand:SI 0 "" "")
14129 (match_dup 2)))
14130 (parallel [(set (pc) (match_dup 3))
14131 (use (label_ref (match_operand 1 "" "")))])]
14132 "TARGET_32BIT"
14133 "
14134 { operands[0] = force_reg (SImode, operands[0]);
14135 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
14136 operands[3] = gen_reg_rtx (SImode);
14137 }")
14138
14139 (define_expand "tablejumpdi"
14140 [(set (match_dup 4)
14141 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
14142 (set (match_dup 3)
14143 (plus:DI (match_dup 4)
14144 (match_dup 2)))
14145 (parallel [(set (pc) (match_dup 3))
14146 (use (label_ref (match_operand 1 "" "")))])]
14147 "TARGET_64BIT"
14148 "
14149 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
14150 operands[3] = gen_reg_rtx (DImode);
14151 operands[4] = gen_reg_rtx (DImode);
14152 }")
14153
14154 (define_insn "*tablejump<mode>_internal1"
14155 [(set (pc)
14156 (match_operand:P 0 "register_operand" "c,*l"))
14157 (use (label_ref (match_operand 1 "" "")))]
14158 ""
14159 "@
14160 bctr
14161 {br|blr}"
14162 [(set_attr "type" "jmpreg")])
14163
14164 (define_insn "nop"
14165 [(const_int 0)]
14166 ""
14167 "{cror 0,0,0|nop}")
14168 \f
14169 ;; Define the subtract-one-and-jump insns, starting with the template
14170 ;; so loop.c knows what to generate.
14171
14172 (define_expand "doloop_end"
14173 [(use (match_operand 0 "" "")) ; loop pseudo
14174 (use (match_operand 1 "" "")) ; iterations; zero if unknown
14175 (use (match_operand 2 "" "")) ; max iterations
14176 (use (match_operand 3 "" "")) ; loop level
14177 (use (match_operand 4 "" ""))] ; label
14178 ""
14179 "
14180 {
14181 /* Only use this on innermost loops. */
14182 if (INTVAL (operands[3]) > 1)
14183 FAIL;
14184 if (TARGET_64BIT)
14185 {
14186 if (GET_MODE (operands[0]) != DImode)
14187 FAIL;
14188 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
14189 }
14190 else
14191 {
14192 if (GET_MODE (operands[0]) != SImode)
14193 FAIL;
14194 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
14195 }
14196 DONE;
14197 }")
14198
14199 (define_expand "ctr<mode>"
14200 [(parallel [(set (pc)
14201 (if_then_else (ne (match_operand:P 0 "register_operand" "")
14202 (const_int 1))
14203 (label_ref (match_operand 1 "" ""))
14204 (pc)))
14205 (set (match_dup 0)
14206 (plus:P (match_dup 0)
14207 (const_int -1)))
14208 (clobber (match_scratch:CC 2 ""))
14209 (clobber (match_scratch:P 3 ""))])]
14210 ""
14211 "")
14212
14213 ;; We need to be able to do this for any operand, including MEM, or we
14214 ;; will cause reload to blow up since we don't allow output reloads on
14215 ;; JUMP_INSNs.
14216 ;; For the length attribute to be calculated correctly, the
14217 ;; label MUST be operand 0.
14218
14219 (define_insn "*ctr<mode>_internal1"
14220 [(set (pc)
14221 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14222 (const_int 1))
14223 (label_ref (match_operand 0 "" ""))
14224 (pc)))
14225 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14226 (plus:P (match_dup 1)
14227 (const_int -1)))
14228 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14229 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14230 ""
14231 "*
14232 {
14233 if (which_alternative != 0)
14234 return \"#\";
14235 else if (get_attr_length (insn) == 4)
14236 return \"{bdn|bdnz} %l0\";
14237 else
14238 return \"bdz $+8\;b %l0\";
14239 }"
14240 [(set_attr "type" "branch")
14241 (set_attr "length" "*,12,16,16")])
14242
14243 (define_insn "*ctr<mode>_internal2"
14244 [(set (pc)
14245 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14246 (const_int 1))
14247 (pc)
14248 (label_ref (match_operand 0 "" ""))))
14249 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14250 (plus:P (match_dup 1)
14251 (const_int -1)))
14252 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14253 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14254 ""
14255 "*
14256 {
14257 if (which_alternative != 0)
14258 return \"#\";
14259 else if (get_attr_length (insn) == 4)
14260 return \"bdz %l0\";
14261 else
14262 return \"{bdn|bdnz} $+8\;b %l0\";
14263 }"
14264 [(set_attr "type" "branch")
14265 (set_attr "length" "*,12,16,16")])
14266
14267 ;; Similar but use EQ
14268
14269 (define_insn "*ctr<mode>_internal5"
14270 [(set (pc)
14271 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14272 (const_int 1))
14273 (label_ref (match_operand 0 "" ""))
14274 (pc)))
14275 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14276 (plus:P (match_dup 1)
14277 (const_int -1)))
14278 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14279 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14280 ""
14281 "*
14282 {
14283 if (which_alternative != 0)
14284 return \"#\";
14285 else if (get_attr_length (insn) == 4)
14286 return \"bdz %l0\";
14287 else
14288 return \"{bdn|bdnz} $+8\;b %l0\";
14289 }"
14290 [(set_attr "type" "branch")
14291 (set_attr "length" "*,12,16,16")])
14292
14293 (define_insn "*ctr<mode>_internal6"
14294 [(set (pc)
14295 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14296 (const_int 1))
14297 (pc)
14298 (label_ref (match_operand 0 "" ""))))
14299 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14300 (plus:P (match_dup 1)
14301 (const_int -1)))
14302 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14303 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14304 ""
14305 "*
14306 {
14307 if (which_alternative != 0)
14308 return \"#\";
14309 else if (get_attr_length (insn) == 4)
14310 return \"{bdn|bdnz} %l0\";
14311 else
14312 return \"bdz $+8\;b %l0\";
14313 }"
14314 [(set_attr "type" "branch")
14315 (set_attr "length" "*,12,16,16")])
14316
14317 ;; Now the splitters if we could not allocate the CTR register
14318
14319 (define_split
14320 [(set (pc)
14321 (if_then_else (match_operator 2 "comparison_operator"
14322 [(match_operand:P 1 "gpc_reg_operand" "")
14323 (const_int 1)])
14324 (match_operand 5 "" "")
14325 (match_operand 6 "" "")))
14326 (set (match_operand:P 0 "gpc_reg_operand" "")
14327 (plus:P (match_dup 1) (const_int -1)))
14328 (clobber (match_scratch:CC 3 ""))
14329 (clobber (match_scratch:P 4 ""))]
14330 "reload_completed"
14331 [(parallel [(set (match_dup 3)
14332 (compare:CC (plus:P (match_dup 1)
14333 (const_int -1))
14334 (const_int 0)))
14335 (set (match_dup 0)
14336 (plus:P (match_dup 1)
14337 (const_int -1)))])
14338 (set (pc) (if_then_else (match_dup 7)
14339 (match_dup 5)
14340 (match_dup 6)))]
14341 "
14342 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14343 operands[3], const0_rtx); }")
14344
14345 (define_split
14346 [(set (pc)
14347 (if_then_else (match_operator 2 "comparison_operator"
14348 [(match_operand:P 1 "gpc_reg_operand" "")
14349 (const_int 1)])
14350 (match_operand 5 "" "")
14351 (match_operand 6 "" "")))
14352 (set (match_operand:P 0 "nonimmediate_operand" "")
14353 (plus:P (match_dup 1) (const_int -1)))
14354 (clobber (match_scratch:CC 3 ""))
14355 (clobber (match_scratch:P 4 ""))]
14356 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
14357 [(parallel [(set (match_dup 3)
14358 (compare:CC (plus:P (match_dup 1)
14359 (const_int -1))
14360 (const_int 0)))
14361 (set (match_dup 4)
14362 (plus:P (match_dup 1)
14363 (const_int -1)))])
14364 (set (match_dup 0)
14365 (match_dup 4))
14366 (set (pc) (if_then_else (match_dup 7)
14367 (match_dup 5)
14368 (match_dup 6)))]
14369 "
14370 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14371 operands[3], const0_rtx); }")
14372 \f
14373 (define_insn "trap"
14374 [(trap_if (const_int 1) (const_int 0))]
14375 ""
14376 "{t 31,0,0|trap}"
14377 [(set_attr "type" "trap")])
14378
14379 (define_expand "conditional_trap"
14380 [(trap_if (match_operator 0 "trap_comparison_operator"
14381 [(match_dup 2) (match_dup 3)])
14382 (match_operand 1 "const_int_operand" ""))]
14383 ""
14384 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14385 operands[2] = rs6000_compare_op0;
14386 operands[3] = rs6000_compare_op1;")
14387
14388 (define_insn ""
14389 [(trap_if (match_operator 0 "trap_comparison_operator"
14390 [(match_operand:GPR 1 "register_operand" "r")
14391 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
14392 (const_int 0))]
14393 ""
14394 "{t|t<wd>}%V0%I2 %1,%2"
14395 [(set_attr "type" "trap")])
14396 \f
14397 ;; Insns related to generating the function prologue and epilogue.
14398
14399 (define_expand "prologue"
14400 [(use (const_int 0))]
14401 "TARGET_SCHED_PROLOG"
14402 "
14403 {
14404 rs6000_emit_prologue ();
14405 DONE;
14406 }")
14407
14408 (define_insn "*movesi_from_cr_one"
14409 [(match_parallel 0 "mfcr_operation"
14410 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14411 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14412 (match_operand 3 "immediate_operand" "n")]
14413 UNSPEC_MOVESI_FROM_CR))])]
14414 "TARGET_MFCRF"
14415 "*
14416 {
14417 int mask = 0;
14418 int i;
14419 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14420 {
14421 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14422 operands[4] = GEN_INT (mask);
14423 output_asm_insn (\"mfcr %1,%4\", operands);
14424 }
14425 return \"\";
14426 }"
14427 [(set_attr "type" "mfcrf")])
14428
14429 (define_insn "movesi_from_cr"
14430 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14431 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
14432 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
14433 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
14434 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
14435 UNSPEC_MOVESI_FROM_CR))]
14436 ""
14437 "mfcr %0"
14438 [(set_attr "type" "mfcr")])
14439
14440 (define_insn "*stmw"
14441 [(match_parallel 0 "stmw_operation"
14442 [(set (match_operand:SI 1 "memory_operand" "=m")
14443 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14444 "TARGET_MULTIPLE"
14445 "{stm|stmw} %2,%1"
14446 [(set_attr "type" "store_ux")])
14447
14448 (define_insn "*save_gpregs_<mode>"
14449 [(match_parallel 0 "any_parallel_operand"
14450 [(clobber (reg:P 65))
14451 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14452 (use (match_operand:P 2 "gpc_reg_operand" "r"))
14453 (set (match_operand:P 3 "memory_operand" "=m")
14454 (match_operand:P 4 "gpc_reg_operand" "r"))])]
14455 ""
14456 "bl %z1"
14457 [(set_attr "type" "branch")
14458 (set_attr "length" "4")])
14459
14460 (define_insn "*save_fpregs_<mode>"
14461 [(match_parallel 0 "any_parallel_operand"
14462 [(clobber (reg:P 65))
14463 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14464 (use (match_operand:P 2 "gpc_reg_operand" "r"))
14465 (set (match_operand:DF 3 "memory_operand" "=m")
14466 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14467 ""
14468 "bl %z1"
14469 [(set_attr "type" "branch")
14470 (set_attr "length" "4")])
14471
14472 ; These are to explain that changes to the stack pointer should
14473 ; not be moved over stores to stack memory.
14474 (define_insn "stack_tie"
14475 [(set (match_operand:BLK 0 "memory_operand" "+m")
14476 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
14477 ""
14478 ""
14479 [(set_attr "length" "0")])
14480
14481
14482 (define_expand "epilogue"
14483 [(use (const_int 0))]
14484 "TARGET_SCHED_PROLOG"
14485 "
14486 {
14487 rs6000_emit_epilogue (FALSE);
14488 DONE;
14489 }")
14490
14491 ; On some processors, doing the mtcrf one CC register at a time is
14492 ; faster (like on the 604e). On others, doing them all at once is
14493 ; faster; for instance, on the 601 and 750.
14494
14495 (define_expand "movsi_to_cr_one"
14496 [(set (match_operand:CC 0 "cc_reg_operand" "")
14497 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
14498 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14499 ""
14500 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14501
14502 (define_insn "*movsi_to_cr"
14503 [(match_parallel 0 "mtcrf_operation"
14504 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14505 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14506 (match_operand 3 "immediate_operand" "n")]
14507 UNSPEC_MOVESI_TO_CR))])]
14508 ""
14509 "*
14510 {
14511 int mask = 0;
14512 int i;
14513 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14514 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14515 operands[4] = GEN_INT (mask);
14516 return \"mtcrf %4,%2\";
14517 }"
14518 [(set_attr "type" "mtcr")])
14519
14520 (define_insn "*mtcrfsi"
14521 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14522 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14523 (match_operand 2 "immediate_operand" "n")]
14524 UNSPEC_MOVESI_TO_CR))]
14525 "GET_CODE (operands[0]) == REG
14526 && CR_REGNO_P (REGNO (operands[0]))
14527 && GET_CODE (operands[2]) == CONST_INT
14528 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14529 "mtcrf %R0,%1"
14530 [(set_attr "type" "mtcr")])
14531
14532 ; The load-multiple instructions have similar properties.
14533 ; Note that "load_multiple" is a name known to the machine-independent
14534 ; code that actually corresponds to the PowerPC load-string.
14535
14536 (define_insn "*lmw"
14537 [(match_parallel 0 "lmw_operation"
14538 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14539 (match_operand:SI 2 "memory_operand" "m"))])]
14540 "TARGET_MULTIPLE"
14541 "{lm|lmw} %1,%2"
14542 [(set_attr "type" "load_ux")])
14543
14544 (define_insn "*return_internal_<mode>"
14545 [(return)
14546 (use (match_operand:P 0 "register_operand" "lc"))]
14547 ""
14548 "b%T0"
14549 [(set_attr "type" "jmpreg")])
14550
14551 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14552 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14553
14554 (define_insn "*restore_gpregs_<mode>"
14555 [(match_parallel 0 "any_parallel_operand"
14556 [(clobber (match_operand:P 1 "register_operand" "=l"))
14557 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14558 (use (match_operand:P 3 "gpc_reg_operand" "r"))
14559 (set (match_operand:P 4 "gpc_reg_operand" "=r")
14560 (match_operand:P 5 "memory_operand" "m"))])]
14561 ""
14562 "bl %z2"
14563 [(set_attr "type" "branch")
14564 (set_attr "length" "4")])
14565
14566 (define_insn "*return_and_restore_gpregs_<mode>"
14567 [(match_parallel 0 "any_parallel_operand"
14568 [(return)
14569 (clobber (match_operand:P 1 "register_operand" "=l"))
14570 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14571 (use (match_operand:P 3 "gpc_reg_operand" "r"))
14572 (set (match_operand:P 4 "gpc_reg_operand" "=r")
14573 (match_operand:P 5 "memory_operand" "m"))])]
14574 ""
14575 "b %z2"
14576 [(set_attr "type" "branch")
14577 (set_attr "length" "4")])
14578
14579 (define_insn "*return_and_restore_fpregs_<mode>"
14580 [(match_parallel 0 "any_parallel_operand"
14581 [(return)
14582 (clobber (match_operand:P 1 "register_operand" "=l"))
14583 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14584 (use (match_operand:P 3 "gpc_reg_operand" "r"))
14585 (set (match_operand:DF 4 "gpc_reg_operand" "=f")
14586 (match_operand:DF 5 "memory_operand" "m"))])]
14587 ""
14588 "b %z2"
14589 [(set_attr "type" "branch")
14590 (set_attr "length" "4")])
14591
14592 ; This is used in compiling the unwind routines.
14593 (define_expand "eh_return"
14594 [(use (match_operand 0 "general_operand" ""))]
14595 ""
14596 "
14597 {
14598 if (TARGET_32BIT)
14599 emit_insn (gen_eh_set_lr_si (operands[0]));
14600 else
14601 emit_insn (gen_eh_set_lr_di (operands[0]));
14602 DONE;
14603 }")
14604
14605 ; We can't expand this before we know where the link register is stored.
14606 (define_insn "eh_set_lr_<mode>"
14607 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
14608 UNSPECV_EH_RR)
14609 (clobber (match_scratch:P 1 "=&b"))]
14610 ""
14611 "#")
14612
14613 (define_split
14614 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14615 (clobber (match_scratch 1 ""))]
14616 "reload_completed"
14617 [(const_int 0)]
14618 "
14619 {
14620 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14621 DONE;
14622 }")
14623
14624 (define_insn "prefetch"
14625 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
14626 (match_operand:SI 1 "const_int_operand" "n")
14627 (match_operand:SI 2 "const_int_operand" "n"))]
14628 "TARGET_POWERPC"
14629 "*
14630 {
14631 if (GET_CODE (operands[0]) == REG)
14632 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14633 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14634 }"
14635 [(set_attr "type" "load")])
14636 \f
14637
14638 (include "sync.md")
14639 (include "altivec.md")
14640 (include "spe.md")
14641 (include "dfp.md")
14642 (include "paired.md")
Mirror of https://gcc.gnu.org/git/gcc.git