]> git.ipfire.org Git - thirdparty/gcc.git/blob - gcc/config/rs6000/rs6000.md
projects / thirdparty / gcc.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
rs6000.opt (mdlmzb): New option.
[thirdparty/gcc.git] / gcc / config / rs6000 / rs6000.md
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6
7 ;; This file is part of GCC.
8
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 2, or (at your
12 ;; option) any later version.
13
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
18
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the
21 ;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
22 ;; MA 02110-1301, USA.
23
24 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25
26 ;;
27 ;; UNSPEC usage
28 ;;
29
30 (define_constants
31 [(UNSPEC_FRSP 0) ; frsp for POWER machines
32 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
33 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
34 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
35 (UNSPEC_MOVSI_GOT 8)
36 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
37 (UNSPEC_FCTIWZ 10)
38 (UNSPEC_FRIM 11)
39 (UNSPEC_FRIN 12)
40 (UNSPEC_FRIP 13)
41 (UNSPEC_FRIZ 14)
42 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
43 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
44 (UNSPEC_TLSGD 17)
45 (UNSPEC_TLSLD 18)
46 (UNSPEC_MOVESI_FROM_CR 19)
47 (UNSPEC_MOVESI_TO_CR 20)
48 (UNSPEC_TLSDTPREL 21)
49 (UNSPEC_TLSDTPRELHA 22)
50 (UNSPEC_TLSDTPRELLO 23)
51 (UNSPEC_TLSGOTDTPREL 24)
52 (UNSPEC_TLSTPREL 25)
53 (UNSPEC_TLSTPRELHA 26)
54 (UNSPEC_TLSTPRELLO 27)
55 (UNSPEC_TLSGOTTPREL 28)
56 (UNSPEC_TLSTLS 29)
57 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
58 (UNSPEC_MV_CR_GT 31) ; move_from_CR_eq_bit
59 (UNSPEC_STFIWX 32)
60 (UNSPEC_POPCNTB 33)
61 (UNSPEC_FRES 34)
62 (UNSPEC_SP_SET 35)
63 (UNSPEC_SP_TEST 36)
64 (UNSPEC_SYNC 37)
65 (UNSPEC_LWSYNC 38)
66 (UNSPEC_ISYNC 39)
67 (UNSPEC_SYNC_OP 40)
68 (UNSPEC_ATOMIC 41)
69 (UNSPEC_CMPXCHG 42)
70 (UNSPEC_XCHG 43)
71 (UNSPEC_AND 44)
72 (UNSPEC_DLMZB 45)
73 (UNSPEC_DLMZB_CR 46)
74 (UNSPEC_DLMZB_STRLEN 47)
75 ])
76
77 ;;
78 ;; UNSPEC_VOLATILE usage
79 ;;
80
81 (define_constants
82 [(UNSPECV_BLOCK 0)
83 (UNSPECV_LL 1) ; load-locked
84 (UNSPECV_SC 2) ; store-conditional
85 (UNSPECV_EH_RR 9) ; eh_reg_restore
86 ])
87 \f
88 ;; Define an insn type attribute. This is used in function unit delay
89 ;; computations.
90 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c"
91 (const_string "integer"))
92
93 ;; Length (in bytes).
94 ; '(pc)' in the following doesn't include the instruction itself; it is
95 ; calculated as if the instruction had zero size.
96 (define_attr "length" ""
97 (if_then_else (eq_attr "type" "branch")
98 (if_then_else (and (ge (minus (match_dup 0) (pc))
99 (const_int -32768))
100 (lt (minus (match_dup 0) (pc))
101 (const_int 32764)))
102 (const_int 4)
103 (const_int 8))
104 (const_int 4)))
105
106 ;; Processor type -- this attribute must exactly match the processor_type
107 ;; enumeration in rs6000.h.
108
109 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5"
110 (const (symbol_ref "rs6000_cpu_attr")))
111
112 (automata_option "ndfa")
113
114 (include "rios1.md")
115 (include "rios2.md")
116 (include "rs64.md")
117 (include "mpc.md")
118 (include "40x.md")
119 (include "440.md")
120 (include "603.md")
121 (include "6xx.md")
122 (include "7xx.md")
123 (include "7450.md")
124 (include "8540.md")
125 (include "power4.md")
126 (include "power5.md")
127
128 (include "predicates.md")
129
130 (include "darwin.md")
131
132 \f
133 ;; Mode macros
134
135 ; This mode macro allows :GPR to be used to indicate the allowable size
136 ; of whole values in GPRs.
137 (define_mode_macro GPR [SI (DI "TARGET_POWERPC64")])
138
139 ; Any supported integer mode.
140 (define_mode_macro INT [QI HI SI DI TI])
141
142 ; Any supported integer mode that fits in one register.
143 (define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")])
144
145 ; extend modes for DImode
146 (define_mode_macro QHSI [QI HI SI])
147
148 ; SImode or DImode, even if DImode doesn't fit in GPRs.
149 (define_mode_macro SDI [SI DI])
150
151 ; The size of a pointer. Also, the size of the value that a record-condition
152 ; (one with a '.') will compare.
153 (define_mode_macro P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
154
155 ; Any hardware-supported floating-point mode
156 (define_mode_macro FP [(SF "TARGET_HARD_FLOAT")
157 (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
158 (TF "!TARGET_IEEEQUAD
159 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128")])
160
161 ; Various instructions that come in SI and DI forms.
162 ; A generic w/d attribute, for things like cmpw/cmpd.
163 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
164
165 ; DImode bits
166 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
167
168 \f
169 ;; Start with fixed-point load and store insns. Here we put only the more
170 ;; complex forms. Basic data transfer is done later.
171
172 (define_expand "zero_extend<mode>di2"
173 [(set (match_operand:DI 0 "gpc_reg_operand" "")
174 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
175 "TARGET_POWERPC64"
176 "")
177
178 (define_insn "*zero_extend<mode>di2_internal1"
179 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
180 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
181 "TARGET_POWERPC64"
182 "@
183 l<wd>z%U1%X1 %0,%1
184 rldicl %0,%1,0,<dbits>"
185 [(set_attr "type" "load,*")])
186
187 (define_insn "*zero_extend<mode>di2_internal2"
188 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
189 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
190 (const_int 0)))
191 (clobber (match_scratch:DI 2 "=r,r"))]
192 "TARGET_64BIT"
193 "@
194 rldicl. %2,%1,0,<dbits>
195 #"
196 [(set_attr "type" "compare")
197 (set_attr "length" "4,8")])
198
199 (define_split
200 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
201 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
202 (const_int 0)))
203 (clobber (match_scratch:DI 2 ""))]
204 "TARGET_POWERPC64 && reload_completed"
205 [(set (match_dup 2)
206 (zero_extend:DI (match_dup 1)))
207 (set (match_dup 0)
208 (compare:CC (match_dup 2)
209 (const_int 0)))]
210 "")
211
212 (define_insn "*zero_extend<mode>di2_internal3"
213 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
214 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
215 (const_int 0)))
216 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
217 (zero_extend:DI (match_dup 1)))]
218 "TARGET_64BIT"
219 "@
220 rldicl. %0,%1,0,<dbits>
221 #"
222 [(set_attr "type" "compare")
223 (set_attr "length" "4,8")])
224
225 (define_split
226 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
227 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
228 (const_int 0)))
229 (set (match_operand:DI 0 "gpc_reg_operand" "")
230 (zero_extend:DI (match_dup 1)))]
231 "TARGET_POWERPC64 && reload_completed"
232 [(set (match_dup 0)
233 (zero_extend:DI (match_dup 1)))
234 (set (match_dup 2)
235 (compare:CC (match_dup 0)
236 (const_int 0)))]
237 "")
238
239 (define_insn "extendqidi2"
240 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
241 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
242 "TARGET_POWERPC64"
243 "extsb %0,%1")
244
245 (define_insn ""
246 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
247 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
248 (const_int 0)))
249 (clobber (match_scratch:DI 2 "=r,r"))]
250 "TARGET_64BIT"
251 "@
252 extsb. %2,%1
253 #"
254 [(set_attr "type" "compare")
255 (set_attr "length" "4,8")])
256
257 (define_split
258 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
259 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
260 (const_int 0)))
261 (clobber (match_scratch:DI 2 ""))]
262 "TARGET_POWERPC64 && reload_completed"
263 [(set (match_dup 2)
264 (sign_extend:DI (match_dup 1)))
265 (set (match_dup 0)
266 (compare:CC (match_dup 2)
267 (const_int 0)))]
268 "")
269
270 (define_insn ""
271 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
272 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
273 (const_int 0)))
274 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
275 (sign_extend:DI (match_dup 1)))]
276 "TARGET_64BIT"
277 "@
278 extsb. %0,%1
279 #"
280 [(set_attr "type" "compare")
281 (set_attr "length" "4,8")])
282
283 (define_split
284 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
285 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
286 (const_int 0)))
287 (set (match_operand:DI 0 "gpc_reg_operand" "")
288 (sign_extend:DI (match_dup 1)))]
289 "TARGET_POWERPC64 && reload_completed"
290 [(set (match_dup 0)
291 (sign_extend:DI (match_dup 1)))
292 (set (match_dup 2)
293 (compare:CC (match_dup 0)
294 (const_int 0)))]
295 "")
296
297 (define_expand "extendhidi2"
298 [(set (match_operand:DI 0 "gpc_reg_operand" "")
299 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
300 "TARGET_POWERPC64"
301 "")
302
303 (define_insn ""
304 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
305 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
306 "TARGET_POWERPC64"
307 "@
308 lha%U1%X1 %0,%1
309 extsh %0,%1"
310 [(set_attr "type" "load_ext,*")])
311
312 (define_insn ""
313 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
314 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
315 (const_int 0)))
316 (clobber (match_scratch:DI 2 "=r,r"))]
317 "TARGET_64BIT"
318 "@
319 extsh. %2,%1
320 #"
321 [(set_attr "type" "compare")
322 (set_attr "length" "4,8")])
323
324 (define_split
325 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
326 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
327 (const_int 0)))
328 (clobber (match_scratch:DI 2 ""))]
329 "TARGET_POWERPC64 && reload_completed"
330 [(set (match_dup 2)
331 (sign_extend:DI (match_dup 1)))
332 (set (match_dup 0)
333 (compare:CC (match_dup 2)
334 (const_int 0)))]
335 "")
336
337 (define_insn ""
338 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
339 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
340 (const_int 0)))
341 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
342 (sign_extend:DI (match_dup 1)))]
343 "TARGET_64BIT"
344 "@
345 extsh. %0,%1
346 #"
347 [(set_attr "type" "compare")
348 (set_attr "length" "4,8")])
349
350 (define_split
351 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
352 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
353 (const_int 0)))
354 (set (match_operand:DI 0 "gpc_reg_operand" "")
355 (sign_extend:DI (match_dup 1)))]
356 "TARGET_POWERPC64 && reload_completed"
357 [(set (match_dup 0)
358 (sign_extend:DI (match_dup 1)))
359 (set (match_dup 2)
360 (compare:CC (match_dup 0)
361 (const_int 0)))]
362 "")
363
364 (define_expand "extendsidi2"
365 [(set (match_operand:DI 0 "gpc_reg_operand" "")
366 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
367 "TARGET_POWERPC64"
368 "")
369
370 (define_insn ""
371 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
372 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
373 "TARGET_POWERPC64"
374 "@
375 lwa%U1%X1 %0,%1
376 extsw %0,%1"
377 [(set_attr "type" "load_ext,*")])
378
379 (define_insn ""
380 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
381 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
382 (const_int 0)))
383 (clobber (match_scratch:DI 2 "=r,r"))]
384 "TARGET_64BIT"
385 "@
386 extsw. %2,%1
387 #"
388 [(set_attr "type" "compare")
389 (set_attr "length" "4,8")])
390
391 (define_split
392 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
393 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
394 (const_int 0)))
395 (clobber (match_scratch:DI 2 ""))]
396 "TARGET_POWERPC64 && reload_completed"
397 [(set (match_dup 2)
398 (sign_extend:DI (match_dup 1)))
399 (set (match_dup 0)
400 (compare:CC (match_dup 2)
401 (const_int 0)))]
402 "")
403
404 (define_insn ""
405 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
406 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
407 (const_int 0)))
408 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
409 (sign_extend:DI (match_dup 1)))]
410 "TARGET_64BIT"
411 "@
412 extsw. %0,%1
413 #"
414 [(set_attr "type" "compare")
415 (set_attr "length" "4,8")])
416
417 (define_split
418 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
419 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
420 (const_int 0)))
421 (set (match_operand:DI 0 "gpc_reg_operand" "")
422 (sign_extend:DI (match_dup 1)))]
423 "TARGET_POWERPC64 && reload_completed"
424 [(set (match_dup 0)
425 (sign_extend:DI (match_dup 1)))
426 (set (match_dup 2)
427 (compare:CC (match_dup 0)
428 (const_int 0)))]
429 "")
430
431 (define_expand "zero_extendqisi2"
432 [(set (match_operand:SI 0 "gpc_reg_operand" "")
433 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
434 ""
435 "")
436
437 (define_insn ""
438 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
439 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
440 ""
441 "@
442 lbz%U1%X1 %0,%1
443 {rlinm|rlwinm} %0,%1,0,0xff"
444 [(set_attr "type" "load,*")])
445
446 (define_insn ""
447 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
448 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
449 (const_int 0)))
450 (clobber (match_scratch:SI 2 "=r,r"))]
451 ""
452 "@
453 {andil.|andi.} %2,%1,0xff
454 #"
455 [(set_attr "type" "compare")
456 (set_attr "length" "4,8")])
457
458 (define_split
459 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
460 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
461 (const_int 0)))
462 (clobber (match_scratch:SI 2 ""))]
463 "reload_completed"
464 [(set (match_dup 2)
465 (zero_extend:SI (match_dup 1)))
466 (set (match_dup 0)
467 (compare:CC (match_dup 2)
468 (const_int 0)))]
469 "")
470
471 (define_insn ""
472 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
473 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
474 (const_int 0)))
475 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
476 (zero_extend:SI (match_dup 1)))]
477 ""
478 "@
479 {andil.|andi.} %0,%1,0xff
480 #"
481 [(set_attr "type" "compare")
482 (set_attr "length" "4,8")])
483
484 (define_split
485 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
486 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
487 (const_int 0)))
488 (set (match_operand:SI 0 "gpc_reg_operand" "")
489 (zero_extend:SI (match_dup 1)))]
490 "reload_completed"
491 [(set (match_dup 0)
492 (zero_extend:SI (match_dup 1)))
493 (set (match_dup 2)
494 (compare:CC (match_dup 0)
495 (const_int 0)))]
496 "")
497
498 (define_expand "extendqisi2"
499 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
500 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
501 ""
502 "
503 {
504 if (TARGET_POWERPC)
505 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
506 else if (TARGET_POWER)
507 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
508 else
509 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
510 DONE;
511 }")
512
513 (define_insn "extendqisi2_ppc"
514 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
515 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
516 "TARGET_POWERPC"
517 "extsb %0,%1")
518
519 (define_insn ""
520 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
521 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
522 (const_int 0)))
523 (clobber (match_scratch:SI 2 "=r,r"))]
524 "TARGET_POWERPC"
525 "@
526 extsb. %2,%1
527 #"
528 [(set_attr "type" "compare")
529 (set_attr "length" "4,8")])
530
531 (define_split
532 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
533 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
534 (const_int 0)))
535 (clobber (match_scratch:SI 2 ""))]
536 "TARGET_POWERPC && reload_completed"
537 [(set (match_dup 2)
538 (sign_extend:SI (match_dup 1)))
539 (set (match_dup 0)
540 (compare:CC (match_dup 2)
541 (const_int 0)))]
542 "")
543
544 (define_insn ""
545 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
546 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
547 (const_int 0)))
548 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
549 (sign_extend:SI (match_dup 1)))]
550 "TARGET_POWERPC"
551 "@
552 extsb. %0,%1
553 #"
554 [(set_attr "type" "compare")
555 (set_attr "length" "4,8")])
556
557 (define_split
558 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
559 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
560 (const_int 0)))
561 (set (match_operand:SI 0 "gpc_reg_operand" "")
562 (sign_extend:SI (match_dup 1)))]
563 "TARGET_POWERPC && reload_completed"
564 [(set (match_dup 0)
565 (sign_extend:SI (match_dup 1)))
566 (set (match_dup 2)
567 (compare:CC (match_dup 0)
568 (const_int 0)))]
569 "")
570
571 (define_expand "extendqisi2_power"
572 [(parallel [(set (match_dup 2)
573 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
574 (const_int 24)))
575 (clobber (scratch:SI))])
576 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
577 (ashiftrt:SI (match_dup 2)
578 (const_int 24)))
579 (clobber (scratch:SI))])]
580 "TARGET_POWER"
581 "
582 { operands[1] = gen_lowpart (SImode, operands[1]);
583 operands[2] = gen_reg_rtx (SImode); }")
584
585 (define_expand "extendqisi2_no_power"
586 [(set (match_dup 2)
587 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
588 (const_int 24)))
589 (set (match_operand:SI 0 "gpc_reg_operand" "")
590 (ashiftrt:SI (match_dup 2)
591 (const_int 24)))]
592 "! TARGET_POWER && ! TARGET_POWERPC"
593 "
594 { operands[1] = gen_lowpart (SImode, operands[1]);
595 operands[2] = gen_reg_rtx (SImode); }")
596
597 (define_expand "zero_extendqihi2"
598 [(set (match_operand:HI 0 "gpc_reg_operand" "")
599 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
600 ""
601 "")
602
603 (define_insn ""
604 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
605 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
606 ""
607 "@
608 lbz%U1%X1 %0,%1
609 {rlinm|rlwinm} %0,%1,0,0xff"
610 [(set_attr "type" "load,*")])
611
612 (define_insn ""
613 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
614 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
615 (const_int 0)))
616 (clobber (match_scratch:HI 2 "=r,r"))]
617 ""
618 "@
619 {andil.|andi.} %2,%1,0xff
620 #"
621 [(set_attr "type" "compare")
622 (set_attr "length" "4,8")])
623
624 (define_split
625 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
626 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
627 (const_int 0)))
628 (clobber (match_scratch:HI 2 ""))]
629 "reload_completed"
630 [(set (match_dup 2)
631 (zero_extend:HI (match_dup 1)))
632 (set (match_dup 0)
633 (compare:CC (match_dup 2)
634 (const_int 0)))]
635 "")
636
637 (define_insn ""
638 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
639 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
640 (const_int 0)))
641 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
642 (zero_extend:HI (match_dup 1)))]
643 ""
644 "@
645 {andil.|andi.} %0,%1,0xff
646 #"
647 [(set_attr "type" "compare")
648 (set_attr "length" "4,8")])
649
650 (define_split
651 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
652 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
653 (const_int 0)))
654 (set (match_operand:HI 0 "gpc_reg_operand" "")
655 (zero_extend:HI (match_dup 1)))]
656 "reload_completed"
657 [(set (match_dup 0)
658 (zero_extend:HI (match_dup 1)))
659 (set (match_dup 2)
660 (compare:CC (match_dup 0)
661 (const_int 0)))]
662 "")
663
664 (define_expand "extendqihi2"
665 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
666 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
667 ""
668 "
669 {
670 if (TARGET_POWERPC)
671 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
672 else if (TARGET_POWER)
673 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
674 else
675 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
676 DONE;
677 }")
678
679 (define_insn "extendqihi2_ppc"
680 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
681 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
682 "TARGET_POWERPC"
683 "extsb %0,%1")
684
685 (define_insn ""
686 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
687 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
688 (const_int 0)))
689 (clobber (match_scratch:HI 2 "=r,r"))]
690 "TARGET_POWERPC"
691 "@
692 extsb. %2,%1
693 #"
694 [(set_attr "type" "compare")
695 (set_attr "length" "4,8")])
696
697 (define_split
698 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
699 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
700 (const_int 0)))
701 (clobber (match_scratch:HI 2 ""))]
702 "TARGET_POWERPC && reload_completed"
703 [(set (match_dup 2)
704 (sign_extend:HI (match_dup 1)))
705 (set (match_dup 0)
706 (compare:CC (match_dup 2)
707 (const_int 0)))]
708 "")
709
710 (define_insn ""
711 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
712 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
713 (const_int 0)))
714 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
715 (sign_extend:HI (match_dup 1)))]
716 "TARGET_POWERPC"
717 "@
718 extsb. %0,%1
719 #"
720 [(set_attr "type" "compare")
721 (set_attr "length" "4,8")])
722
723 (define_split
724 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
725 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
726 (const_int 0)))
727 (set (match_operand:HI 0 "gpc_reg_operand" "")
728 (sign_extend:HI (match_dup 1)))]
729 "TARGET_POWERPC && reload_completed"
730 [(set (match_dup 0)
731 (sign_extend:HI (match_dup 1)))
732 (set (match_dup 2)
733 (compare:CC (match_dup 0)
734 (const_int 0)))]
735 "")
736
737 (define_expand "extendqihi2_power"
738 [(parallel [(set (match_dup 2)
739 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
740 (const_int 24)))
741 (clobber (scratch:SI))])
742 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
743 (ashiftrt:SI (match_dup 2)
744 (const_int 24)))
745 (clobber (scratch:SI))])]
746 "TARGET_POWER"
747 "
748 { operands[0] = gen_lowpart (SImode, operands[0]);
749 operands[1] = gen_lowpart (SImode, operands[1]);
750 operands[2] = gen_reg_rtx (SImode); }")
751
752 (define_expand "extendqihi2_no_power"
753 [(set (match_dup 2)
754 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
755 (const_int 24)))
756 (set (match_operand:HI 0 "gpc_reg_operand" "")
757 (ashiftrt:SI (match_dup 2)
758 (const_int 24)))]
759 "! TARGET_POWER && ! TARGET_POWERPC"
760 "
761 { operands[0] = gen_lowpart (SImode, operands[0]);
762 operands[1] = gen_lowpart (SImode, operands[1]);
763 operands[2] = gen_reg_rtx (SImode); }")
764
765 (define_expand "zero_extendhisi2"
766 [(set (match_operand:SI 0 "gpc_reg_operand" "")
767 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
768 ""
769 "")
770
771 (define_insn ""
772 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
773 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
774 ""
775 "@
776 lhz%U1%X1 %0,%1
777 {rlinm|rlwinm} %0,%1,0,0xffff"
778 [(set_attr "type" "load,*")])
779
780 (define_insn ""
781 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
782 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
783 (const_int 0)))
784 (clobber (match_scratch:SI 2 "=r,r"))]
785 ""
786 "@
787 {andil.|andi.} %2,%1,0xffff
788 #"
789 [(set_attr "type" "compare")
790 (set_attr "length" "4,8")])
791
792 (define_split
793 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
794 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
795 (const_int 0)))
796 (clobber (match_scratch:SI 2 ""))]
797 "reload_completed"
798 [(set (match_dup 2)
799 (zero_extend:SI (match_dup 1)))
800 (set (match_dup 0)
801 (compare:CC (match_dup 2)
802 (const_int 0)))]
803 "")
804
805 (define_insn ""
806 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
807 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
808 (const_int 0)))
809 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
810 (zero_extend:SI (match_dup 1)))]
811 ""
812 "@
813 {andil.|andi.} %0,%1,0xffff
814 #"
815 [(set_attr "type" "compare")
816 (set_attr "length" "4,8")])
817
818 (define_split
819 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
820 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
821 (const_int 0)))
822 (set (match_operand:SI 0 "gpc_reg_operand" "")
823 (zero_extend:SI (match_dup 1)))]
824 "reload_completed"
825 [(set (match_dup 0)
826 (zero_extend:SI (match_dup 1)))
827 (set (match_dup 2)
828 (compare:CC (match_dup 0)
829 (const_int 0)))]
830 "")
831
832 (define_expand "extendhisi2"
833 [(set (match_operand:SI 0 "gpc_reg_operand" "")
834 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
835 ""
836 "")
837
838 (define_insn ""
839 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
840 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
841 ""
842 "@
843 lha%U1%X1 %0,%1
844 {exts|extsh} %0,%1"
845 [(set_attr "type" "load_ext,*")])
846
847 (define_insn ""
848 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
849 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
850 (const_int 0)))
851 (clobber (match_scratch:SI 2 "=r,r"))]
852 ""
853 "@
854 {exts.|extsh.} %2,%1
855 #"
856 [(set_attr "type" "compare")
857 (set_attr "length" "4,8")])
858
859 (define_split
860 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
861 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
862 (const_int 0)))
863 (clobber (match_scratch:SI 2 ""))]
864 "reload_completed"
865 [(set (match_dup 2)
866 (sign_extend:SI (match_dup 1)))
867 (set (match_dup 0)
868 (compare:CC (match_dup 2)
869 (const_int 0)))]
870 "")
871
872 (define_insn ""
873 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
874 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
875 (const_int 0)))
876 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
877 (sign_extend:SI (match_dup 1)))]
878 ""
879 "@
880 {exts.|extsh.} %0,%1
881 #"
882 [(set_attr "type" "compare")
883 (set_attr "length" "4,8")])
884 \f
885 ;; IBM 405 and 440 half-word multiplication operations.
886
887 (define_insn "*macchwc"
888 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
889 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
890 (match_operand:SI 2 "gpc_reg_operand" "r")
891 (const_int 16))
892 (sign_extend:SI
893 (match_operand:HI 1 "gpc_reg_operand" "r")))
894 (match_operand:SI 4 "gpc_reg_operand" "0"))
895 (const_int 0)))
896 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
897 (plus:SI (mult:SI (ashiftrt:SI
898 (match_dup 2)
899 (const_int 16))
900 (sign_extend:SI
901 (match_dup 1)))
902 (match_dup 4)))]
903 "TARGET_MULHW"
904 "macchw. %0, %1, %2"
905 [(set_attr "type" "imul3")])
906
907 (define_insn "*macchw"
908 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
909 (plus:SI (mult:SI (ashiftrt:SI
910 (match_operand:SI 2 "gpc_reg_operand" "r")
911 (const_int 16))
912 (sign_extend:SI
913 (match_operand:HI 1 "gpc_reg_operand" "r")))
914 (match_operand:SI 3 "gpc_reg_operand" "0")))]
915 "TARGET_MULHW"
916 "macchw %0, %1, %2"
917 [(set_attr "type" "imul3")])
918
919 (define_insn "*macchwuc"
920 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
921 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
922 (match_operand:SI 2 "gpc_reg_operand" "r")
923 (const_int 16))
924 (zero_extend:SI
925 (match_operand:HI 1 "gpc_reg_operand" "r")))
926 (match_operand:SI 4 "gpc_reg_operand" "0"))
927 (const_int 0)))
928 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
929 (plus:SI (mult:SI (lshiftrt:SI
930 (match_dup 2)
931 (const_int 16))
932 (zero_extend:SI
933 (match_dup 1)))
934 (match_dup 4)))]
935 "TARGET_MULHW"
936 "macchwu. %0, %1, %2"
937 [(set_attr "type" "imul3")])
938
939 (define_insn "*macchwu"
940 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
941 (plus:SI (mult:SI (lshiftrt:SI
942 (match_operand:SI 2 "gpc_reg_operand" "r")
943 (const_int 16))
944 (zero_extend:SI
945 (match_operand:HI 1 "gpc_reg_operand" "r")))
946 (match_operand:SI 3 "gpc_reg_operand" "0")))]
947 "TARGET_MULHW"
948 "macchwu %0, %1, %2"
949 [(set_attr "type" "imul3")])
950
951 (define_insn "*machhwc"
952 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
953 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
954 (match_operand:SI 1 "gpc_reg_operand" "%r")
955 (const_int 16))
956 (ashiftrt:SI
957 (match_operand:SI 2 "gpc_reg_operand" "r")
958 (const_int 16)))
959 (match_operand:SI 4 "gpc_reg_operand" "0"))
960 (const_int 0)))
961 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
962 (plus:SI (mult:SI (ashiftrt:SI
963 (match_dup 1)
964 (const_int 16))
965 (ashiftrt:SI
966 (match_dup 2)
967 (const_int 16)))
968 (match_dup 4)))]
969 "TARGET_MULHW"
970 "machhw. %0, %1, %2"
971 [(set_attr "type" "imul3")])
972
973 (define_insn "*machhw"
974 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
975 (plus:SI (mult:SI (ashiftrt:SI
976 (match_operand:SI 1 "gpc_reg_operand" "%r")
977 (const_int 16))
978 (ashiftrt:SI
979 (match_operand:SI 2 "gpc_reg_operand" "r")
980 (const_int 16)))
981 (match_operand:SI 3 "gpc_reg_operand" "0")))]
982 "TARGET_MULHW"
983 "machhw %0, %1, %2"
984 [(set_attr "type" "imul3")])
985
986 (define_insn "*machhwuc"
987 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
988 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
989 (match_operand:SI 1 "gpc_reg_operand" "%r")
990 (const_int 16))
991 (lshiftrt:SI
992 (match_operand:SI 2 "gpc_reg_operand" "r")
993 (const_int 16)))
994 (match_operand:SI 4 "gpc_reg_operand" "0"))
995 (const_int 0)))
996 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
997 (plus:SI (mult:SI (lshiftrt:SI
998 (match_dup 1)
999 (const_int 16))
1000 (lshiftrt:SI
1001 (match_dup 2)
1002 (const_int 16)))
1003 (match_dup 4)))]
1004 "TARGET_MULHW"
1005 "machhwu. %0, %1, %2"
1006 [(set_attr "type" "imul3")])
1007
1008 (define_insn "*machhwu"
1009 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1010 (plus:SI (mult:SI (lshiftrt:SI
1011 (match_operand:SI 1 "gpc_reg_operand" "%r")
1012 (const_int 16))
1013 (lshiftrt:SI
1014 (match_operand:SI 2 "gpc_reg_operand" "r")
1015 (const_int 16)))
1016 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1017 "TARGET_MULHW"
1018 "machhwu %0, %1, %2"
1019 [(set_attr "type" "imul3")])
1020
1021 (define_insn "*maclhwc"
1022 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1023 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1024 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1025 (sign_extend:SI
1026 (match_operand:HI 2 "gpc_reg_operand" "r")))
1027 (match_operand:SI 4 "gpc_reg_operand" "0"))
1028 (const_int 0)))
1029 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1030 (plus:SI (mult:SI (sign_extend:SI
1031 (match_dup 1))
1032 (sign_extend:SI
1033 (match_dup 2)))
1034 (match_dup 4)))]
1035 "TARGET_MULHW"
1036 "maclhw. %0, %1, %2"
1037 [(set_attr "type" "imul3")])
1038
1039 (define_insn "*maclhw"
1040 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1041 (plus:SI (mult:SI (sign_extend:SI
1042 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1043 (sign_extend:SI
1044 (match_operand:HI 2 "gpc_reg_operand" "r")))
1045 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1046 "TARGET_MULHW"
1047 "maclhw %0, %1, %2"
1048 [(set_attr "type" "imul3")])
1049
1050 (define_insn "*maclhwuc"
1051 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1052 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1053 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1054 (zero_extend:SI
1055 (match_operand:HI 2 "gpc_reg_operand" "r")))
1056 (match_operand:SI 4 "gpc_reg_operand" "0"))
1057 (const_int 0)))
1058 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1059 (plus:SI (mult:SI (zero_extend:SI
1060 (match_dup 1))
1061 (zero_extend:SI
1062 (match_dup 2)))
1063 (match_dup 4)))]
1064 "TARGET_MULHW"
1065 "maclhwu. %0, %1, %2"
1066 [(set_attr "type" "imul3")])
1067
1068 (define_insn "*maclhwu"
1069 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1070 (plus:SI (mult:SI (zero_extend:SI
1071 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1072 (zero_extend:SI
1073 (match_operand:HI 2 "gpc_reg_operand" "r")))
1074 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1075 "TARGET_MULHW"
1076 "maclhwu %0, %1, %2"
1077 [(set_attr "type" "imul3")])
1078
1079 (define_insn "*nmacchwc"
1080 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1081 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1082 (mult:SI (ashiftrt:SI
1083 (match_operand:SI 2 "gpc_reg_operand" "r")
1084 (const_int 16))
1085 (sign_extend:SI
1086 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1087 (const_int 0)))
1088 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1089 (minus:SI (match_dup 4)
1090 (mult:SI (ashiftrt:SI
1091 (match_dup 2)
1092 (const_int 16))
1093 (sign_extend:SI
1094 (match_dup 1)))))]
1095 "TARGET_MULHW"
1096 "nmacchw. %0, %1, %2"
1097 [(set_attr "type" "imul3")])
1098
1099 (define_insn "*nmacchw"
1100 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1101 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1102 (mult:SI (ashiftrt:SI
1103 (match_operand:SI 2 "gpc_reg_operand" "r")
1104 (const_int 16))
1105 (sign_extend:SI
1106 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1107 "TARGET_MULHW"
1108 "nmacchw %0, %1, %2"
1109 [(set_attr "type" "imul3")])
1110
1111 (define_insn "*nmachhwc"
1112 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1113 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1114 (mult:SI (ashiftrt:SI
1115 (match_operand:SI 1 "gpc_reg_operand" "%r")
1116 (const_int 16))
1117 (ashiftrt:SI
1118 (match_operand:SI 2 "gpc_reg_operand" "r")
1119 (const_int 16))))
1120 (const_int 0)))
1121 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1122 (minus:SI (match_dup 4)
1123 (mult:SI (ashiftrt:SI
1124 (match_dup 1)
1125 (const_int 16))
1126 (ashiftrt:SI
1127 (match_dup 2)
1128 (const_int 16)))))]
1129 "TARGET_MULHW"
1130 "nmachhw. %0, %1, %2"
1131 [(set_attr "type" "imul3")])
1132
1133 (define_insn "*nmachhw"
1134 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1135 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1136 (mult:SI (ashiftrt:SI
1137 (match_operand:SI 1 "gpc_reg_operand" "%r")
1138 (const_int 16))
1139 (ashiftrt:SI
1140 (match_operand:SI 2 "gpc_reg_operand" "r")
1141 (const_int 16)))))]
1142 "TARGET_MULHW"
1143 "nmachhw %0, %1, %2"
1144 [(set_attr "type" "imul3")])
1145
1146 (define_insn "*nmaclhwc"
1147 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1148 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1149 (mult:SI (sign_extend:SI
1150 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1151 (sign_extend:SI
1152 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1153 (const_int 0)))
1154 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1155 (minus:SI (match_dup 4)
1156 (mult:SI (sign_extend:SI
1157 (match_dup 1))
1158 (sign_extend:SI
1159 (match_dup 2)))))]
1160 "TARGET_MULHW"
1161 "nmaclhw. %0, %1, %2"
1162 [(set_attr "type" "imul3")])
1163
1164 (define_insn "*nmaclhw"
1165 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1166 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1167 (mult:SI (sign_extend:SI
1168 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1169 (sign_extend:SI
1170 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1171 "TARGET_MULHW"
1172 "nmaclhw %0, %1, %2"
1173 [(set_attr "type" "imul3")])
1174
1175 (define_insn "*mulchwc"
1176 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1177 (compare:CC (mult:SI (ashiftrt:SI
1178 (match_operand:SI 2 "gpc_reg_operand" "r")
1179 (const_int 16))
1180 (sign_extend:SI
1181 (match_operand:HI 1 "gpc_reg_operand" "r")))
1182 (const_int 0)))
1183 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1184 (mult:SI (ashiftrt:SI
1185 (match_dup 2)
1186 (const_int 16))
1187 (sign_extend:SI
1188 (match_dup 1))))]
1189 "TARGET_MULHW"
1190 "mulchw. %0, %1, %2"
1191 [(set_attr "type" "imul3")])
1192
1193 (define_insn "*mulchw"
1194 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1195 (mult:SI (ashiftrt:SI
1196 (match_operand:SI 2 "gpc_reg_operand" "r")
1197 (const_int 16))
1198 (sign_extend:SI
1199 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1200 "TARGET_MULHW"
1201 "mulchw %0, %1, %2"
1202 [(set_attr "type" "imul3")])
1203
1204 (define_insn "*mulchwuc"
1205 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1206 (compare:CC (mult:SI (lshiftrt:SI
1207 (match_operand:SI 2 "gpc_reg_operand" "r")
1208 (const_int 16))
1209 (zero_extend:SI
1210 (match_operand:HI 1 "gpc_reg_operand" "r")))
1211 (const_int 0)))
1212 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1213 (mult:SI (lshiftrt:SI
1214 (match_dup 2)
1215 (const_int 16))
1216 (zero_extend:SI
1217 (match_dup 1))))]
1218 "TARGET_MULHW"
1219 "mulchwu. %0, %1, %2"
1220 [(set_attr "type" "imul3")])
1221
1222 (define_insn "*mulchwu"
1223 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1224 (mult:SI (lshiftrt:SI
1225 (match_operand:SI 2 "gpc_reg_operand" "r")
1226 (const_int 16))
1227 (zero_extend:SI
1228 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1229 "TARGET_MULHW"
1230 "mulchwu %0, %1, %2"
1231 [(set_attr "type" "imul3")])
1232
1233 (define_insn "*mulhhwc"
1234 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1235 (compare:CC (mult:SI (ashiftrt:SI
1236 (match_operand:SI 1 "gpc_reg_operand" "%r")
1237 (const_int 16))
1238 (ashiftrt:SI
1239 (match_operand:SI 2 "gpc_reg_operand" "r")
1240 (const_int 16)))
1241 (const_int 0)))
1242 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1243 (mult:SI (ashiftrt:SI
1244 (match_dup 1)
1245 (const_int 16))
1246 (ashiftrt:SI
1247 (match_dup 2)
1248 (const_int 16))))]
1249 "TARGET_MULHW"
1250 "mulhhw. %0, %1, %2"
1251 [(set_attr "type" "imul3")])
1252
1253 (define_insn "*mulhhw"
1254 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1255 (mult:SI (ashiftrt:SI
1256 (match_operand:SI 1 "gpc_reg_operand" "%r")
1257 (const_int 16))
1258 (ashiftrt:SI
1259 (match_operand:SI 2 "gpc_reg_operand" "r")
1260 (const_int 16))))]
1261 "TARGET_MULHW"
1262 "mulhhw %0, %1, %2"
1263 [(set_attr "type" "imul3")])
1264
1265 (define_insn "*mulhhwuc"
1266 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1267 (compare:CC (mult:SI (lshiftrt:SI
1268 (match_operand:SI 1 "gpc_reg_operand" "%r")
1269 (const_int 16))
1270 (lshiftrt:SI
1271 (match_operand:SI 2 "gpc_reg_operand" "r")
1272 (const_int 16)))
1273 (const_int 0)))
1274 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1275 (mult:SI (lshiftrt:SI
1276 (match_dup 1)
1277 (const_int 16))
1278 (lshiftrt:SI
1279 (match_dup 2)
1280 (const_int 16))))]
1281 "TARGET_MULHW"
1282 "mulhhwu. %0, %1, %2"
1283 [(set_attr "type" "imul3")])
1284
1285 (define_insn "*mulhhwu"
1286 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1287 (mult:SI (lshiftrt:SI
1288 (match_operand:SI 1 "gpc_reg_operand" "%r")
1289 (const_int 16))
1290 (lshiftrt:SI
1291 (match_operand:SI 2 "gpc_reg_operand" "r")
1292 (const_int 16))))]
1293 "TARGET_MULHW"
1294 "mulhhwu %0, %1, %2"
1295 [(set_attr "type" "imul3")])
1296
1297 (define_insn "*mullhwc"
1298 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1299 (compare:CC (mult:SI (sign_extend:SI
1300 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1301 (sign_extend:SI
1302 (match_operand:HI 2 "gpc_reg_operand" "r")))
1303 (const_int 0)))
1304 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1305 (mult:SI (sign_extend:SI
1306 (match_dup 1))
1307 (sign_extend:SI
1308 (match_dup 2))))]
1309 "TARGET_MULHW"
1310 "mullhw. %0, %1, %2"
1311 [(set_attr "type" "imul3")])
1312
1313 (define_insn "*mullhw"
1314 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1315 (mult:SI (sign_extend:SI
1316 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1317 (sign_extend:SI
1318 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1319 "TARGET_MULHW"
1320 "mullhw %0, %1, %2"
1321 [(set_attr "type" "imul3")])
1322
1323 (define_insn "*mullhwuc"
1324 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1325 (compare:CC (mult:SI (zero_extend:SI
1326 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1327 (zero_extend:SI
1328 (match_operand:HI 2 "gpc_reg_operand" "r")))
1329 (const_int 0)))
1330 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1331 (mult:SI (zero_extend:SI
1332 (match_dup 1))
1333 (zero_extend:SI
1334 (match_dup 2))))]
1335 "TARGET_MULHW"
1336 "mullhwu. %0, %1, %2"
1337 [(set_attr "type" "imul3")])
1338
1339 (define_insn "*mullhwu"
1340 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1341 (mult:SI (zero_extend:SI
1342 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1343 (zero_extend:SI
1344 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1345 "TARGET_MULHW"
1346 "mullhwu %0, %1, %2"
1347 [(set_attr "type" "imul3")])
1348 \f
1349 ;; IBM 405 and 440 string-search dlmzb instruction support.
1350 (define_insn "dlmzb"
1351 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1352 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1353 (match_operand:SI 2 "gpc_reg_operand" "r")]
1354 UNSPEC_DLMZB_CR))
1355 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1356 (unspec:SI [(match_dup 1)
1357 (match_dup 2)]
1358 UNSPEC_DLMZB))]
1359 "TARGET_DLMZB"
1360 "dlmzb. %0, %1, %2")
1361
1362 (define_expand "strlensi"
1363 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1364 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1365 (match_operand:QI 2 "const_int_operand" "")
1366 (match_operand 3 "const_int_operand" "")]
1367 UNSPEC_DLMZB_STRLEN))
1368 (clobber (match_scratch:CC 4 "=x"))]
1369 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1370 {
1371 rtx result = operands[0];
1372 rtx src = operands[1];
1373 rtx search_char = operands[2];
1374 rtx align = operands[3];
1375 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1376 rtx loop_label, end_label, mem, cr0, cond;
1377 if (search_char != const0_rtx
1378 || GET_CODE (align) != CONST_INT
1379 || INTVAL (align) < 8)
1380 FAIL;
1381 word1 = gen_reg_rtx (SImode);
1382 word2 = gen_reg_rtx (SImode);
1383 scratch_dlmzb = gen_reg_rtx (SImode);
1384 scratch_string = gen_reg_rtx (Pmode);
1385 loop_label = gen_label_rtx ();
1386 end_label = gen_label_rtx ();
1387 addr = force_reg (Pmode, XEXP (src, 0));
1388 emit_move_insn (scratch_string, addr);
1389 emit_label (loop_label);
1390 mem = change_address (src, SImode, scratch_string);
1391 emit_move_insn (word1, mem);
1392 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1393 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1394 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1395 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1396 emit_jump_insn (gen_rtx_SET (VOIDmode,
1397 pc_rtx,
1398 gen_rtx_IF_THEN_ELSE (VOIDmode,
1399 cond,
1400 gen_rtx_LABEL_REF
1401 (VOIDmode,
1402 end_label),
1403 pc_rtx)));
1404 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1405 emit_jump_insn (gen_rtx_SET (VOIDmode,
1406 pc_rtx,
1407 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1408 emit_label (end_label);
1409 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1410 emit_insn (gen_subsi3 (result, scratch_string, addr));
1411 emit_insn (gen_subsi3 (result, result, const1_rtx));
1412 DONE;
1413 })
1414 \f
1415 (define_split
1416 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1417 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1418 (const_int 0)))
1419 (set (match_operand:SI 0 "gpc_reg_operand" "")
1420 (sign_extend:SI (match_dup 1)))]
1421 "reload_completed"
1422 [(set (match_dup 0)
1423 (sign_extend:SI (match_dup 1)))
1424 (set (match_dup 2)
1425 (compare:CC (match_dup 0)
1426 (const_int 0)))]
1427 "")
1428
1429 ;; Fixed-point arithmetic insns.
1430
1431 (define_expand "add<mode>3"
1432 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1433 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1434 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1435 ""
1436 "
1437 {
1438 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1439 {
1440 if (non_short_cint_operand (operands[2], DImode))
1441 FAIL;
1442 }
1443 else if (GET_CODE (operands[2]) == CONST_INT
1444 && ! add_operand (operands[2], <MODE>mode))
1445 {
1446 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
1447 ? operands[0] : gen_reg_rtx (<MODE>mode));
1448
1449 HOST_WIDE_INT val = INTVAL (operands[2]);
1450 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1451 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1452
1453 if (<MODE>mode == DImode && !CONST_OK_FOR_LETTER_P (rest, 'L'))
1454 FAIL;
1455
1456 /* The ordering here is important for the prolog expander.
1457 When space is allocated from the stack, adding 'low' first may
1458 produce a temporary deallocation (which would be bad). */
1459 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1460 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1461 DONE;
1462 }
1463 }")
1464
1465 ;; Discourage ai/addic because of carry but provide it in an alternative
1466 ;; allowing register zero as source.
1467 (define_insn "*add<mode>3_internal1"
1468 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1469 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1470 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1471 ""
1472 "@
1473 {cax|add} %0,%1,%2
1474 {cal %0,%2(%1)|addi %0,%1,%2}
1475 {ai|addic} %0,%1,%2
1476 {cau|addis} %0,%1,%v2"
1477 [(set_attr "length" "4,4,4,4")])
1478
1479 (define_insn "addsi3_high"
1480 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1481 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1482 (high:SI (match_operand 2 "" ""))))]
1483 "TARGET_MACHO && !TARGET_64BIT"
1484 "{cau|addis} %0,%1,ha16(%2)"
1485 [(set_attr "length" "4")])
1486
1487 (define_insn "*add<mode>3_internal2"
1488 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1489 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1490 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1491 (const_int 0)))
1492 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1493 ""
1494 "@
1495 {cax.|add.} %3,%1,%2
1496 {ai.|addic.} %3,%1,%2
1497 #
1498 #"
1499 [(set_attr "type" "fast_compare,compare,compare,compare")
1500 (set_attr "length" "4,4,8,8")])
1501
1502 (define_split
1503 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1504 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1505 (match_operand:GPR 2 "reg_or_short_operand" ""))
1506 (const_int 0)))
1507 (clobber (match_scratch:GPR 3 ""))]
1508 "reload_completed"
1509 [(set (match_dup 3)
1510 (plus:GPR (match_dup 1)
1511 (match_dup 2)))
1512 (set (match_dup 0)
1513 (compare:CC (match_dup 3)
1514 (const_int 0)))]
1515 "")
1516
1517 (define_insn "*add<mode>3_internal3"
1518 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1519 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1520 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1521 (const_int 0)))
1522 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1523 (plus:P (match_dup 1)
1524 (match_dup 2)))]
1525 ""
1526 "@
1527 {cax.|add.} %0,%1,%2
1528 {ai.|addic.} %0,%1,%2
1529 #
1530 #"
1531 [(set_attr "type" "fast_compare,compare,compare,compare")
1532 (set_attr "length" "4,4,8,8")])
1533
1534 (define_split
1535 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1536 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1537 (match_operand:P 2 "reg_or_short_operand" ""))
1538 (const_int 0)))
1539 (set (match_operand:P 0 "gpc_reg_operand" "")
1540 (plus:P (match_dup 1) (match_dup 2)))]
1541 "reload_completed"
1542 [(set (match_dup 0)
1543 (plus:P (match_dup 1)
1544 (match_dup 2)))
1545 (set (match_dup 3)
1546 (compare:CC (match_dup 0)
1547 (const_int 0)))]
1548 "")
1549
1550 ;; Split an add that we can't do in one insn into two insns, each of which
1551 ;; does one 16-bit part. This is used by combine. Note that the low-order
1552 ;; add should be last in case the result gets used in an address.
1553
1554 (define_split
1555 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1556 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1557 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1558 ""
1559 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1560 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1561 "
1562 {
1563 HOST_WIDE_INT val = INTVAL (operands[2]);
1564 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1565 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1566
1567 operands[4] = GEN_INT (low);
1568 if (<MODE>mode == SImode || CONST_OK_FOR_LETTER_P (rest, 'L'))
1569 operands[3] = GEN_INT (rest);
1570 else if (! no_new_pseudos)
1571 {
1572 operands[3] = gen_reg_rtx (DImode);
1573 emit_move_insn (operands[3], operands[2]);
1574 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1575 DONE;
1576 }
1577 else
1578 FAIL;
1579 }")
1580
1581 (define_insn "one_cmpl<mode>2"
1582 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1583 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1584 ""
1585 "nor %0,%1,%1")
1586
1587 (define_insn ""
1588 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1589 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1590 (const_int 0)))
1591 (clobber (match_scratch:P 2 "=r,r"))]
1592 ""
1593 "@
1594 nor. %2,%1,%1
1595 #"
1596 [(set_attr "type" "compare")
1597 (set_attr "length" "4,8")])
1598
1599 (define_split
1600 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1601 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1602 (const_int 0)))
1603 (clobber (match_scratch:P 2 ""))]
1604 "reload_completed"
1605 [(set (match_dup 2)
1606 (not:P (match_dup 1)))
1607 (set (match_dup 0)
1608 (compare:CC (match_dup 2)
1609 (const_int 0)))]
1610 "")
1611
1612 (define_insn ""
1613 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1614 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1615 (const_int 0)))
1616 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1617 (not:P (match_dup 1)))]
1618 ""
1619 "@
1620 nor. %0,%1,%1
1621 #"
1622 [(set_attr "type" "compare")
1623 (set_attr "length" "4,8")])
1624
1625 (define_split
1626 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1627 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1628 (const_int 0)))
1629 (set (match_operand:P 0 "gpc_reg_operand" "")
1630 (not:P (match_dup 1)))]
1631 "reload_completed"
1632 [(set (match_dup 0)
1633 (not:P (match_dup 1)))
1634 (set (match_dup 2)
1635 (compare:CC (match_dup 0)
1636 (const_int 0)))]
1637 "")
1638
1639 (define_insn ""
1640 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1641 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1642 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1643 "! TARGET_POWERPC"
1644 "{sf%I1|subf%I1c} %0,%2,%1")
1645
1646 (define_insn ""
1647 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1648 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1649 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1650 "TARGET_POWERPC"
1651 "@
1652 subf %0,%2,%1
1653 subfic %0,%2,%1")
1654
1655 (define_insn ""
1656 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1657 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1658 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1659 (const_int 0)))
1660 (clobber (match_scratch:SI 3 "=r,r"))]
1661 "! TARGET_POWERPC"
1662 "@
1663 {sf.|subfc.} %3,%2,%1
1664 #"
1665 [(set_attr "type" "compare")
1666 (set_attr "length" "4,8")])
1667
1668 (define_insn ""
1669 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1670 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1671 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1672 (const_int 0)))
1673 (clobber (match_scratch:P 3 "=r,r"))]
1674 "TARGET_POWERPC"
1675 "@
1676 subf. %3,%2,%1
1677 #"
1678 [(set_attr "type" "fast_compare")
1679 (set_attr "length" "4,8")])
1680
1681 (define_split
1682 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1683 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1684 (match_operand:P 2 "gpc_reg_operand" ""))
1685 (const_int 0)))
1686 (clobber (match_scratch:P 3 ""))]
1687 "reload_completed"
1688 [(set (match_dup 3)
1689 (minus:P (match_dup 1)
1690 (match_dup 2)))
1691 (set (match_dup 0)
1692 (compare:CC (match_dup 3)
1693 (const_int 0)))]
1694 "")
1695
1696 (define_insn ""
1697 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1698 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1699 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1700 (const_int 0)))
1701 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1702 (minus:SI (match_dup 1) (match_dup 2)))]
1703 "! TARGET_POWERPC"
1704 "@
1705 {sf.|subfc.} %0,%2,%1
1706 #"
1707 [(set_attr "type" "compare")
1708 (set_attr "length" "4,8")])
1709
1710 (define_insn ""
1711 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1712 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1713 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1714 (const_int 0)))
1715 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1716 (minus:P (match_dup 1)
1717 (match_dup 2)))]
1718 "TARGET_POWERPC"
1719 "@
1720 subf. %0,%2,%1
1721 #"
1722 [(set_attr "type" "fast_compare")
1723 (set_attr "length" "4,8")])
1724
1725 (define_split
1726 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1727 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1728 (match_operand:P 2 "gpc_reg_operand" ""))
1729 (const_int 0)))
1730 (set (match_operand:P 0 "gpc_reg_operand" "")
1731 (minus:P (match_dup 1)
1732 (match_dup 2)))]
1733 "reload_completed"
1734 [(set (match_dup 0)
1735 (minus:P (match_dup 1)
1736 (match_dup 2)))
1737 (set (match_dup 3)
1738 (compare:CC (match_dup 0)
1739 (const_int 0)))]
1740 "")
1741
1742 (define_expand "sub<mode>3"
1743 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1744 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1745 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1746 ""
1747 "
1748 {
1749 if (GET_CODE (operands[2]) == CONST_INT)
1750 {
1751 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1752 negate_rtx (<MODE>mode, operands[2])));
1753 DONE;
1754 }
1755 }")
1756
1757 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1758 ;; instruction and some auxiliary computations. Then we just have a single
1759 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1760 ;; combine.
1761
1762 (define_expand "sminsi3"
1763 [(set (match_dup 3)
1764 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1765 (match_operand:SI 2 "reg_or_short_operand" ""))
1766 (const_int 0)
1767 (minus:SI (match_dup 2) (match_dup 1))))
1768 (set (match_operand:SI 0 "gpc_reg_operand" "")
1769 (minus:SI (match_dup 2) (match_dup 3)))]
1770 "TARGET_POWER || TARGET_ISEL"
1771 "
1772 {
1773 if (TARGET_ISEL)
1774 {
1775 operands[2] = force_reg (SImode, operands[2]);
1776 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1777 DONE;
1778 }
1779
1780 operands[3] = gen_reg_rtx (SImode);
1781 }")
1782
1783 (define_split
1784 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1785 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1786 (match_operand:SI 2 "reg_or_short_operand" "")))
1787 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1788 "TARGET_POWER"
1789 [(set (match_dup 3)
1790 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1791 (const_int 0)
1792 (minus:SI (match_dup 2) (match_dup 1))))
1793 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1794 "")
1795
1796 (define_expand "smaxsi3"
1797 [(set (match_dup 3)
1798 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1799 (match_operand:SI 2 "reg_or_short_operand" ""))
1800 (const_int 0)
1801 (minus:SI (match_dup 2) (match_dup 1))))
1802 (set (match_operand:SI 0 "gpc_reg_operand" "")
1803 (plus:SI (match_dup 3) (match_dup 1)))]
1804 "TARGET_POWER || TARGET_ISEL"
1805 "
1806 {
1807 if (TARGET_ISEL)
1808 {
1809 operands[2] = force_reg (SImode, operands[2]);
1810 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1811 DONE;
1812 }
1813 operands[3] = gen_reg_rtx (SImode);
1814 }")
1815
1816 (define_split
1817 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1818 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1819 (match_operand:SI 2 "reg_or_short_operand" "")))
1820 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1821 "TARGET_POWER"
1822 [(set (match_dup 3)
1823 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1824 (const_int 0)
1825 (minus:SI (match_dup 2) (match_dup 1))))
1826 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1827 "")
1828
1829 (define_expand "uminsi3"
1830 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1831 (match_dup 5)))
1832 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1833 (match_dup 5)))
1834 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1835 (const_int 0)
1836 (minus:SI (match_dup 4) (match_dup 3))))
1837 (set (match_operand:SI 0 "gpc_reg_operand" "")
1838 (minus:SI (match_dup 2) (match_dup 3)))]
1839 "TARGET_POWER || TARGET_ISEL"
1840 "
1841 {
1842 if (TARGET_ISEL)
1843 {
1844 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1845 DONE;
1846 }
1847 operands[3] = gen_reg_rtx (SImode);
1848 operands[4] = gen_reg_rtx (SImode);
1849 operands[5] = GEN_INT (-2147483647 - 1);
1850 }")
1851
1852 (define_expand "umaxsi3"
1853 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1854 (match_dup 5)))
1855 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1856 (match_dup 5)))
1857 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1858 (const_int 0)
1859 (minus:SI (match_dup 4) (match_dup 3))))
1860 (set (match_operand:SI 0 "gpc_reg_operand" "")
1861 (plus:SI (match_dup 3) (match_dup 1)))]
1862 "TARGET_POWER || TARGET_ISEL"
1863 "
1864 {
1865 if (TARGET_ISEL)
1866 {
1867 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1868 DONE;
1869 }
1870 operands[3] = gen_reg_rtx (SImode);
1871 operands[4] = gen_reg_rtx (SImode);
1872 operands[5] = GEN_INT (-2147483647 - 1);
1873 }")
1874
1875 (define_insn ""
1876 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1877 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1878 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1879 (const_int 0)
1880 (minus:SI (match_dup 2) (match_dup 1))))]
1881 "TARGET_POWER"
1882 "doz%I2 %0,%1,%2")
1883
1884 (define_insn ""
1885 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1886 (compare:CC
1887 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1888 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1889 (const_int 0)
1890 (minus:SI (match_dup 2) (match_dup 1)))
1891 (const_int 0)))
1892 (clobber (match_scratch:SI 3 "=r,r"))]
1893 "TARGET_POWER"
1894 "@
1895 doz%I2. %3,%1,%2
1896 #"
1897 [(set_attr "type" "delayed_compare")
1898 (set_attr "length" "4,8")])
1899
1900 (define_split
1901 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1902 (compare:CC
1903 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1904 (match_operand:SI 2 "reg_or_short_operand" ""))
1905 (const_int 0)
1906 (minus:SI (match_dup 2) (match_dup 1)))
1907 (const_int 0)))
1908 (clobber (match_scratch:SI 3 ""))]
1909 "TARGET_POWER && reload_completed"
1910 [(set (match_dup 3)
1911 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1912 (const_int 0)
1913 (minus:SI (match_dup 2) (match_dup 1))))
1914 (set (match_dup 0)
1915 (compare:CC (match_dup 3)
1916 (const_int 0)))]
1917 "")
1918
1919 (define_insn ""
1920 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1921 (compare:CC
1922 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1923 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1924 (const_int 0)
1925 (minus:SI (match_dup 2) (match_dup 1)))
1926 (const_int 0)))
1927 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1928 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1929 (const_int 0)
1930 (minus:SI (match_dup 2) (match_dup 1))))]
1931 "TARGET_POWER"
1932 "@
1933 doz%I2. %0,%1,%2
1934 #"
1935 [(set_attr "type" "delayed_compare")
1936 (set_attr "length" "4,8")])
1937
1938 (define_split
1939 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1940 (compare:CC
1941 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1942 (match_operand:SI 2 "reg_or_short_operand" ""))
1943 (const_int 0)
1944 (minus:SI (match_dup 2) (match_dup 1)))
1945 (const_int 0)))
1946 (set (match_operand:SI 0 "gpc_reg_operand" "")
1947 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1948 (const_int 0)
1949 (minus:SI (match_dup 2) (match_dup 1))))]
1950 "TARGET_POWER && reload_completed"
1951 [(set (match_dup 0)
1952 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1953 (const_int 0)
1954 (minus:SI (match_dup 2) (match_dup 1))))
1955 (set (match_dup 3)
1956 (compare:CC (match_dup 0)
1957 (const_int 0)))]
1958 "")
1959
1960 ;; We don't need abs with condition code because such comparisons should
1961 ;; never be done.
1962 (define_expand "abssi2"
1963 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1964 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1965 ""
1966 "
1967 {
1968 if (TARGET_ISEL)
1969 {
1970 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1971 DONE;
1972 }
1973 else if (! TARGET_POWER)
1974 {
1975 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1976 DONE;
1977 }
1978 }")
1979
1980 (define_insn "*abssi2_power"
1981 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1982 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1983 "TARGET_POWER"
1984 "abs %0,%1")
1985
1986 (define_insn_and_split "abssi2_isel"
1987 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1988 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
1989 (clobber (match_scratch:SI 2 "=&b"))
1990 (clobber (match_scratch:CC 3 "=y"))]
1991 "TARGET_ISEL"
1992 "#"
1993 "&& reload_completed"
1994 [(set (match_dup 2) (neg:SI (match_dup 1)))
1995 (set (match_dup 3)
1996 (compare:CC (match_dup 1)
1997 (const_int 0)))
1998 (set (match_dup 0)
1999 (if_then_else:SI (ge (match_dup 3)
2000 (const_int 0))
2001 (match_dup 1)
2002 (match_dup 2)))]
2003 "")
2004
2005 (define_insn_and_split "abssi2_nopower"
2006 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2007 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2008 (clobber (match_scratch:SI 2 "=&r,&r"))]
2009 "! TARGET_POWER && ! TARGET_ISEL"
2010 "#"
2011 "&& reload_completed"
2012 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2013 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2014 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2015 "")
2016
2017 (define_insn "*nabs_power"
2018 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2019 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2020 "TARGET_POWER"
2021 "nabs %0,%1")
2022
2023 (define_insn_and_split "*nabs_nopower"
2024 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2025 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2026 (clobber (match_scratch:SI 2 "=&r,&r"))]
2027 "! TARGET_POWER"
2028 "#"
2029 "&& reload_completed"
2030 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2031 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2032 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2033 "")
2034
2035 (define_expand "neg<mode>2"
2036 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2037 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2038 ""
2039 "")
2040
2041 (define_insn "*neg<mode>2_internal"
2042 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2043 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2044 ""
2045 "neg %0,%1")
2046
2047 (define_insn ""
2048 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2049 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2050 (const_int 0)))
2051 (clobber (match_scratch:P 2 "=r,r"))]
2052 ""
2053 "@
2054 neg. %2,%1
2055 #"
2056 [(set_attr "type" "fast_compare")
2057 (set_attr "length" "4,8")])
2058
2059 (define_split
2060 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2061 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2062 (const_int 0)))
2063 (clobber (match_scratch:P 2 ""))]
2064 "reload_completed"
2065 [(set (match_dup 2)
2066 (neg:P (match_dup 1)))
2067 (set (match_dup 0)
2068 (compare:CC (match_dup 2)
2069 (const_int 0)))]
2070 "")
2071
2072 (define_insn ""
2073 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2074 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2075 (const_int 0)))
2076 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2077 (neg:P (match_dup 1)))]
2078 ""
2079 "@
2080 neg. %0,%1
2081 #"
2082 [(set_attr "type" "fast_compare")
2083 (set_attr "length" "4,8")])
2084
2085 (define_split
2086 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2087 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2088 (const_int 0)))
2089 (set (match_operand:P 0 "gpc_reg_operand" "")
2090 (neg:P (match_dup 1)))]
2091 "reload_completed"
2092 [(set (match_dup 0)
2093 (neg:P (match_dup 1)))
2094 (set (match_dup 2)
2095 (compare:CC (match_dup 0)
2096 (const_int 0)))]
2097 "")
2098
2099 (define_insn "clz<mode>2"
2100 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2101 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2102 ""
2103 "{cntlz|cntlz<wd>} %0,%1")
2104
2105 (define_expand "ctz<mode>2"
2106 [(set (match_dup 2)
2107 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
2108 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2109 (match_dup 2)))
2110 (clobber (scratch:CC))])
2111 (set (match_dup 4) (clz:GPR (match_dup 3)))
2112 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2113 (minus:GPR (match_dup 5) (match_dup 4)))]
2114 ""
2115 {
2116 operands[2] = gen_reg_rtx (<MODE>mode);
2117 operands[3] = gen_reg_rtx (<MODE>mode);
2118 operands[4] = gen_reg_rtx (<MODE>mode);
2119 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2120 })
2121
2122 (define_expand "ffs<mode>2"
2123 [(set (match_dup 2)
2124 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
2125 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2126 (match_dup 2)))
2127 (clobber (scratch:CC))])
2128 (set (match_dup 4) (clz:GPR (match_dup 3)))
2129 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2130 (minus:GPR (match_dup 5) (match_dup 4)))]
2131 ""
2132 {
2133 operands[2] = gen_reg_rtx (<MODE>mode);
2134 operands[3] = gen_reg_rtx (<MODE>mode);
2135 operands[4] = gen_reg_rtx (<MODE>mode);
2136 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2137 })
2138
2139 (define_expand "popcount<mode>2"
2140 [(set (match_dup 2)
2141 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2142 UNSPEC_POPCNTB))
2143 (set (match_dup 3)
2144 (mult:GPR (match_dup 2) (match_dup 4)))
2145 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2146 (lshiftrt:GPR (match_dup 3) (match_dup 5)))]
2147 "TARGET_POPCNTB"
2148 {
2149 operands[2] = gen_reg_rtx (<MODE>mode);
2150 operands[3] = gen_reg_rtx (<MODE>mode);
2151 operands[4] = force_reg (<MODE>mode,
2152 <MODE>mode == SImode
2153 ? GEN_INT (0x01010101)
2154 : GEN_INT ((HOST_WIDE_INT)
2155 0x01010101 << 32 | 0x01010101));
2156 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 8);
2157 })
2158
2159 (define_insn "popcntb<mode>2"
2160 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2161 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2162 UNSPEC_POPCNTB))]
2163 "TARGET_POPCNTB"
2164 "popcntb %0,%1")
2165
2166 (define_expand "mulsi3"
2167 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2168 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2169 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2170 ""
2171 "
2172 {
2173 if (TARGET_POWER)
2174 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2175 else
2176 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2177 DONE;
2178 }")
2179
2180 (define_insn "mulsi3_mq"
2181 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2182 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2183 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2184 (clobber (match_scratch:SI 3 "=q,q"))]
2185 "TARGET_POWER"
2186 "@
2187 {muls|mullw} %0,%1,%2
2188 {muli|mulli} %0,%1,%2"
2189 [(set (attr "type")
2190 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2191 (const_string "imul3")
2192 (match_operand:SI 2 "short_cint_operand" "")
2193 (const_string "imul2")]
2194 (const_string "imul")))])
2195
2196 (define_insn "mulsi3_no_mq"
2197 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2198 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2199 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2200 "! TARGET_POWER"
2201 "@
2202 {muls|mullw} %0,%1,%2
2203 {muli|mulli} %0,%1,%2"
2204 [(set (attr "type")
2205 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2206 (const_string "imul3")
2207 (match_operand:SI 2 "short_cint_operand" "")
2208 (const_string "imul2")]
2209 (const_string "imul")))])
2210
2211 (define_insn "*mulsi3_mq_internal1"
2212 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2213 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2214 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2215 (const_int 0)))
2216 (clobber (match_scratch:SI 3 "=r,r"))
2217 (clobber (match_scratch:SI 4 "=q,q"))]
2218 "TARGET_POWER"
2219 "@
2220 {muls.|mullw.} %3,%1,%2
2221 #"
2222 [(set_attr "type" "imul_compare")
2223 (set_attr "length" "4,8")])
2224
2225 (define_split
2226 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2227 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2228 (match_operand:SI 2 "gpc_reg_operand" ""))
2229 (const_int 0)))
2230 (clobber (match_scratch:SI 3 ""))
2231 (clobber (match_scratch:SI 4 ""))]
2232 "TARGET_POWER && reload_completed"
2233 [(parallel [(set (match_dup 3)
2234 (mult:SI (match_dup 1) (match_dup 2)))
2235 (clobber (match_dup 4))])
2236 (set (match_dup 0)
2237 (compare:CC (match_dup 3)
2238 (const_int 0)))]
2239 "")
2240
2241 (define_insn "*mulsi3_no_mq_internal1"
2242 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2243 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2244 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2245 (const_int 0)))
2246 (clobber (match_scratch:SI 3 "=r,r"))]
2247 "! TARGET_POWER"
2248 "@
2249 {muls.|mullw.} %3,%1,%2
2250 #"
2251 [(set_attr "type" "imul_compare")
2252 (set_attr "length" "4,8")])
2253
2254 (define_split
2255 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2256 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2257 (match_operand:SI 2 "gpc_reg_operand" ""))
2258 (const_int 0)))
2259 (clobber (match_scratch:SI 3 ""))]
2260 "! TARGET_POWER && reload_completed"
2261 [(set (match_dup 3)
2262 (mult:SI (match_dup 1) (match_dup 2)))
2263 (set (match_dup 0)
2264 (compare:CC (match_dup 3)
2265 (const_int 0)))]
2266 "")
2267
2268 (define_insn "*mulsi3_mq_internal2"
2269 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2270 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2271 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2272 (const_int 0)))
2273 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2274 (mult:SI (match_dup 1) (match_dup 2)))
2275 (clobber (match_scratch:SI 4 "=q,q"))]
2276 "TARGET_POWER"
2277 "@
2278 {muls.|mullw.} %0,%1,%2
2279 #"
2280 [(set_attr "type" "imul_compare")
2281 (set_attr "length" "4,8")])
2282
2283 (define_split
2284 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2285 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2286 (match_operand:SI 2 "gpc_reg_operand" ""))
2287 (const_int 0)))
2288 (set (match_operand:SI 0 "gpc_reg_operand" "")
2289 (mult:SI (match_dup 1) (match_dup 2)))
2290 (clobber (match_scratch:SI 4 ""))]
2291 "TARGET_POWER && reload_completed"
2292 [(parallel [(set (match_dup 0)
2293 (mult:SI (match_dup 1) (match_dup 2)))
2294 (clobber (match_dup 4))])
2295 (set (match_dup 3)
2296 (compare:CC (match_dup 0)
2297 (const_int 0)))]
2298 "")
2299
2300 (define_insn "*mulsi3_no_mq_internal2"
2301 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2302 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2303 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2304 (const_int 0)))
2305 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2306 (mult:SI (match_dup 1) (match_dup 2)))]
2307 "! TARGET_POWER"
2308 "@
2309 {muls.|mullw.} %0,%1,%2
2310 #"
2311 [(set_attr "type" "imul_compare")
2312 (set_attr "length" "4,8")])
2313
2314 (define_split
2315 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2316 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2317 (match_operand:SI 2 "gpc_reg_operand" ""))
2318 (const_int 0)))
2319 (set (match_operand:SI 0 "gpc_reg_operand" "")
2320 (mult:SI (match_dup 1) (match_dup 2)))]
2321 "! TARGET_POWER && reload_completed"
2322 [(set (match_dup 0)
2323 (mult:SI (match_dup 1) (match_dup 2)))
2324 (set (match_dup 3)
2325 (compare:CC (match_dup 0)
2326 (const_int 0)))]
2327 "")
2328
2329 ;; Operand 1 is divided by operand 2; quotient goes to operand
2330 ;; 0 and remainder to operand 3.
2331 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2332
2333 (define_expand "divmodsi4"
2334 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2335 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2336 (match_operand:SI 2 "gpc_reg_operand" "")))
2337 (set (match_operand:SI 3 "register_operand" "")
2338 (mod:SI (match_dup 1) (match_dup 2)))])]
2339 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2340 "
2341 {
2342 if (! TARGET_POWER && ! TARGET_POWERPC)
2343 {
2344 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2345 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2346 emit_insn (gen_divss_call ());
2347 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2348 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2349 DONE;
2350 }
2351 }")
2352
2353 (define_insn "*divmodsi4_internal"
2354 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2355 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2356 (match_operand:SI 2 "gpc_reg_operand" "r")))
2357 (set (match_operand:SI 3 "register_operand" "=q")
2358 (mod:SI (match_dup 1) (match_dup 2)))]
2359 "TARGET_POWER"
2360 "divs %0,%1,%2"
2361 [(set_attr "type" "idiv")])
2362
2363 (define_expand "udiv<mode>3"
2364 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2365 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2366 (match_operand:GPR 2 "gpc_reg_operand" "")))]
2367 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2368 "
2369 {
2370 if (! TARGET_POWER && ! TARGET_POWERPC)
2371 {
2372 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2373 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2374 emit_insn (gen_quous_call ());
2375 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2376 DONE;
2377 }
2378 else if (TARGET_POWER)
2379 {
2380 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2381 DONE;
2382 }
2383 }")
2384
2385 (define_insn "udivsi3_mq"
2386 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2387 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2388 (match_operand:SI 2 "gpc_reg_operand" "r")))
2389 (clobber (match_scratch:SI 3 "=q"))]
2390 "TARGET_POWERPC && TARGET_POWER"
2391 "divwu %0,%1,%2"
2392 [(set_attr "type" "idiv")])
2393
2394 (define_insn "*udivsi3_no_mq"
2395 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2396 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2397 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2398 "TARGET_POWERPC && ! TARGET_POWER"
2399 "div<wd>u %0,%1,%2"
2400 [(set_attr "type" "idiv")])
2401
2402 ;; For powers of two we can do srai/aze for divide and then adjust for
2403 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2404 ;; used; for PowerPC, force operands into register and do a normal divide;
2405 ;; for AIX common-mode, use quoss call on register operands.
2406 (define_expand "div<mode>3"
2407 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2408 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2409 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2410 ""
2411 "
2412 {
2413 if (GET_CODE (operands[2]) == CONST_INT
2414 && INTVAL (operands[2]) > 0
2415 && exact_log2 (INTVAL (operands[2])) >= 0)
2416 ;
2417 else if (TARGET_POWERPC)
2418 {
2419 operands[2] = force_reg (SImode, operands[2]);
2420 if (TARGET_POWER)
2421 {
2422 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2423 DONE;
2424 }
2425 }
2426 else if (TARGET_POWER)
2427 FAIL;
2428 else
2429 {
2430 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2431 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2432 emit_insn (gen_quoss_call ());
2433 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2434 DONE;
2435 }
2436 }")
2437
2438 (define_insn "divsi3_mq"
2439 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2440 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2441 (match_operand:SI 2 "gpc_reg_operand" "r")))
2442 (clobber (match_scratch:SI 3 "=q"))]
2443 "TARGET_POWERPC && TARGET_POWER"
2444 "divw %0,%1,%2"
2445 [(set_attr "type" "idiv")])
2446
2447 (define_insn "*div<mode>3_no_mq"
2448 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2449 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2450 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2451 "TARGET_POWERPC && ! TARGET_POWER"
2452 "div<wd> %0,%1,%2"
2453 [(set_attr "type" "idiv")])
2454
2455 (define_expand "mod<mode>3"
2456 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2457 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2458 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2459 ""
2460 "
2461 {
2462 int i;
2463 rtx temp1;
2464 rtx temp2;
2465
2466 if (GET_CODE (operands[2]) != CONST_INT
2467 || INTVAL (operands[2]) <= 0
2468 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2469 FAIL;
2470
2471 temp1 = gen_reg_rtx (<MODE>mode);
2472 temp2 = gen_reg_rtx (<MODE>mode);
2473
2474 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2475 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2476 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2477 DONE;
2478 }")
2479
2480 (define_insn ""
2481 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2482 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2483 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2484 ""
2485 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
2486 [(set_attr "type" "two")
2487 (set_attr "length" "8")])
2488
2489 (define_insn ""
2490 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2491 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2492 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2493 (const_int 0)))
2494 (clobber (match_scratch:P 3 "=r,r"))]
2495 ""
2496 "@
2497 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
2498 #"
2499 [(set_attr "type" "compare")
2500 (set_attr "length" "8,12")])
2501
2502 (define_split
2503 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2504 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2505 (match_operand:GPR 2 "exact_log2_cint_operand"
2506 ""))
2507 (const_int 0)))
2508 (clobber (match_scratch:GPR 3 ""))]
2509 "reload_completed"
2510 [(set (match_dup 3)
2511 (div:<MODE> (match_dup 1) (match_dup 2)))
2512 (set (match_dup 0)
2513 (compare:CC (match_dup 3)
2514 (const_int 0)))]
2515 "")
2516
2517 (define_insn ""
2518 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2519 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2520 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2521 (const_int 0)))
2522 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2523 (div:P (match_dup 1) (match_dup 2)))]
2524 ""
2525 "@
2526 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
2527 #"
2528 [(set_attr "type" "compare")
2529 (set_attr "length" "8,12")])
2530
2531 (define_split
2532 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2533 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2534 (match_operand:GPR 2 "exact_log2_cint_operand"
2535 ""))
2536 (const_int 0)))
2537 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2538 (div:GPR (match_dup 1) (match_dup 2)))]
2539 "reload_completed"
2540 [(set (match_dup 0)
2541 (div:<MODE> (match_dup 1) (match_dup 2)))
2542 (set (match_dup 3)
2543 (compare:CC (match_dup 0)
2544 (const_int 0)))]
2545 "")
2546
2547 (define_insn ""
2548 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2549 (udiv:SI
2550 (plus:DI (ashift:DI
2551 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2552 (const_int 32))
2553 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2554 (match_operand:SI 3 "gpc_reg_operand" "r")))
2555 (set (match_operand:SI 2 "register_operand" "=*q")
2556 (umod:SI
2557 (plus:DI (ashift:DI
2558 (zero_extend:DI (match_dup 1)) (const_int 32))
2559 (zero_extend:DI (match_dup 4)))
2560 (match_dup 3)))]
2561 "TARGET_POWER"
2562 "div %0,%1,%3"
2563 [(set_attr "type" "idiv")])
2564
2565 ;; To do unsigned divide we handle the cases of the divisor looking like a
2566 ;; negative number. If it is a constant that is less than 2**31, we don't
2567 ;; have to worry about the branches. So make a few subroutines here.
2568 ;;
2569 ;; First comes the normal case.
2570 (define_expand "udivmodsi4_normal"
2571 [(set (match_dup 4) (const_int 0))
2572 (parallel [(set (match_operand:SI 0 "" "")
2573 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2574 (const_int 32))
2575 (zero_extend:DI (match_operand:SI 1 "" "")))
2576 (match_operand:SI 2 "" "")))
2577 (set (match_operand:SI 3 "" "")
2578 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2579 (const_int 32))
2580 (zero_extend:DI (match_dup 1)))
2581 (match_dup 2)))])]
2582 "TARGET_POWER"
2583 "
2584 { operands[4] = gen_reg_rtx (SImode); }")
2585
2586 ;; This handles the branches.
2587 (define_expand "udivmodsi4_tests"
2588 [(set (match_operand:SI 0 "" "") (const_int 0))
2589 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2590 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2591 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2592 (label_ref (match_operand:SI 4 "" "")) (pc)))
2593 (set (match_dup 0) (const_int 1))
2594 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2595 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2596 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2597 (label_ref (match_dup 4)) (pc)))]
2598 "TARGET_POWER"
2599 "
2600 { operands[5] = gen_reg_rtx (CCUNSmode);
2601 operands[6] = gen_reg_rtx (CCmode);
2602 }")
2603
2604 (define_expand "udivmodsi4"
2605 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2606 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2607 (match_operand:SI 2 "reg_or_cint_operand" "")))
2608 (set (match_operand:SI 3 "gpc_reg_operand" "")
2609 (umod:SI (match_dup 1) (match_dup 2)))])]
2610 ""
2611 "
2612 {
2613 rtx label = 0;
2614
2615 if (! TARGET_POWER)
2616 {
2617 if (! TARGET_POWERPC)
2618 {
2619 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2620 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2621 emit_insn (gen_divus_call ());
2622 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2623 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2624 DONE;
2625 }
2626 else
2627 FAIL;
2628 }
2629
2630 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2631 {
2632 operands[2] = force_reg (SImode, operands[2]);
2633 label = gen_label_rtx ();
2634 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2635 operands[3], label));
2636 }
2637 else
2638 operands[2] = force_reg (SImode, operands[2]);
2639
2640 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2641 operands[3]));
2642 if (label)
2643 emit_label (label);
2644
2645 DONE;
2646 }")
2647
2648 ;; AIX architecture-independent common-mode multiply (DImode),
2649 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2650 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2651 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2652 ;; assumed unused if generating common-mode, so ignore.
2653 (define_insn "mulh_call"
2654 [(set (reg:SI 3)
2655 (truncate:SI
2656 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2657 (sign_extend:DI (reg:SI 4)))
2658 (const_int 32))))
2659 (clobber (match_scratch:SI 0 "=l"))]
2660 "! TARGET_POWER && ! TARGET_POWERPC"
2661 "bla __mulh"
2662 [(set_attr "type" "imul")])
2663
2664 (define_insn "mull_call"
2665 [(set (reg:DI 3)
2666 (mult:DI (sign_extend:DI (reg:SI 3))
2667 (sign_extend:DI (reg:SI 4))))
2668 (clobber (match_scratch:SI 0 "=l"))
2669 (clobber (reg:SI 0))]
2670 "! TARGET_POWER && ! TARGET_POWERPC"
2671 "bla __mull"
2672 [(set_attr "type" "imul")])
2673
2674 (define_insn "divss_call"
2675 [(set (reg:SI 3)
2676 (div:SI (reg:SI 3) (reg:SI 4)))
2677 (set (reg:SI 4)
2678 (mod:SI (reg:SI 3) (reg:SI 4)))
2679 (clobber (match_scratch:SI 0 "=l"))
2680 (clobber (reg:SI 0))]
2681 "! TARGET_POWER && ! TARGET_POWERPC"
2682 "bla __divss"
2683 [(set_attr "type" "idiv")])
2684
2685 (define_insn "divus_call"
2686 [(set (reg:SI 3)
2687 (udiv:SI (reg:SI 3) (reg:SI 4)))
2688 (set (reg:SI 4)
2689 (umod:SI (reg:SI 3) (reg:SI 4)))
2690 (clobber (match_scratch:SI 0 "=l"))
2691 (clobber (reg:SI 0))
2692 (clobber (match_scratch:CC 1 "=x"))
2693 (clobber (reg:CC 69))]
2694 "! TARGET_POWER && ! TARGET_POWERPC"
2695 "bla __divus"
2696 [(set_attr "type" "idiv")])
2697
2698 (define_insn "quoss_call"
2699 [(set (reg:SI 3)
2700 (div:SI (reg:SI 3) (reg:SI 4)))
2701 (clobber (match_scratch:SI 0 "=l"))]
2702 "! TARGET_POWER && ! TARGET_POWERPC"
2703 "bla __quoss"
2704 [(set_attr "type" "idiv")])
2705
2706 (define_insn "quous_call"
2707 [(set (reg:SI 3)
2708 (udiv:SI (reg:SI 3) (reg:SI 4)))
2709 (clobber (match_scratch:SI 0 "=l"))
2710 (clobber (reg:SI 0))
2711 (clobber (match_scratch:CC 1 "=x"))
2712 (clobber (reg:CC 69))]
2713 "! TARGET_POWER && ! TARGET_POWERPC"
2714 "bla __quous"
2715 [(set_attr "type" "idiv")])
2716 \f
2717 ;; Logical instructions
2718 ;; The logical instructions are mostly combined by using match_operator,
2719 ;; but the plain AND insns are somewhat different because there is no
2720 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2721 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2722
2723 (define_insn "andsi3"
2724 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2725 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2726 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2727 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2728 ""
2729 "@
2730 and %0,%1,%2
2731 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2732 {andil.|andi.} %0,%1,%b2
2733 {andiu.|andis.} %0,%1,%u2"
2734 [(set_attr "type" "*,*,compare,compare")])
2735
2736 ;; Note to set cr's other than cr0 we do the and immediate and then
2737 ;; the test again -- this avoids a mfcr which on the higher end
2738 ;; machines causes an execution serialization
2739
2740 (define_insn "*andsi3_internal2"
2741 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2742 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2743 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2744 (const_int 0)))
2745 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2746 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2747 "TARGET_32BIT"
2748 "@
2749 and. %3,%1,%2
2750 {andil.|andi.} %3,%1,%b2
2751 {andiu.|andis.} %3,%1,%u2
2752 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2753 #
2754 #
2755 #
2756 #"
2757 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2758 (set_attr "length" "4,4,4,4,8,8,8,8")])
2759
2760 (define_insn "*andsi3_internal3"
2761 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2762 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2763 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2764 (const_int 0)))
2765 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2766 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2767 "TARGET_64BIT"
2768 "@
2769 #
2770 {andil.|andi.} %3,%1,%b2
2771 {andiu.|andis.} %3,%1,%u2
2772 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2773 #
2774 #
2775 #
2776 #"
2777 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2778 (set_attr "length" "8,4,4,4,8,8,8,8")])
2779
2780 (define_split
2781 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2782 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2783 (match_operand:GPR 2 "and_operand" ""))
2784 (const_int 0)))
2785 (clobber (match_scratch:GPR 3 ""))
2786 (clobber (match_scratch:CC 4 ""))]
2787 "reload_completed"
2788 [(parallel [(set (match_dup 3)
2789 (and:<MODE> (match_dup 1)
2790 (match_dup 2)))
2791 (clobber (match_dup 4))])
2792 (set (match_dup 0)
2793 (compare:CC (match_dup 3)
2794 (const_int 0)))]
2795 "")
2796
2797 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2798 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2799
2800 (define_split
2801 [(set (match_operand:CC 0 "cc_reg_operand" "")
2802 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2803 (match_operand:SI 2 "gpc_reg_operand" ""))
2804 (const_int 0)))
2805 (clobber (match_scratch:SI 3 ""))
2806 (clobber (match_scratch:CC 4 ""))]
2807 "TARGET_POWERPC64 && reload_completed"
2808 [(parallel [(set (match_dup 3)
2809 (and:SI (match_dup 1)
2810 (match_dup 2)))
2811 (clobber (match_dup 4))])
2812 (set (match_dup 0)
2813 (compare:CC (match_dup 3)
2814 (const_int 0)))]
2815 "")
2816
2817 (define_insn "*andsi3_internal4"
2818 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2819 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2820 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2821 (const_int 0)))
2822 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2823 (and:SI (match_dup 1)
2824 (match_dup 2)))
2825 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2826 "TARGET_32BIT"
2827 "@
2828 and. %0,%1,%2
2829 {andil.|andi.} %0,%1,%b2
2830 {andiu.|andis.} %0,%1,%u2
2831 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2832 #
2833 #
2834 #
2835 #"
2836 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2837 (set_attr "length" "4,4,4,4,8,8,8,8")])
2838
2839 (define_insn "*andsi3_internal5"
2840 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2841 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2842 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2843 (const_int 0)))
2844 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2845 (and:SI (match_dup 1)
2846 (match_dup 2)))
2847 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2848 "TARGET_64BIT"
2849 "@
2850 #
2851 {andil.|andi.} %0,%1,%b2
2852 {andiu.|andis.} %0,%1,%u2
2853 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2854 #
2855 #
2856 #
2857 #"
2858 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2859 (set_attr "length" "8,4,4,4,8,8,8,8")])
2860
2861 (define_split
2862 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2863 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2864 (match_operand:SI 2 "and_operand" ""))
2865 (const_int 0)))
2866 (set (match_operand:SI 0 "gpc_reg_operand" "")
2867 (and:SI (match_dup 1)
2868 (match_dup 2)))
2869 (clobber (match_scratch:CC 4 ""))]
2870 "reload_completed"
2871 [(parallel [(set (match_dup 0)
2872 (and:SI (match_dup 1)
2873 (match_dup 2)))
2874 (clobber (match_dup 4))])
2875 (set (match_dup 3)
2876 (compare:CC (match_dup 0)
2877 (const_int 0)))]
2878 "")
2879
2880 (define_split
2881 [(set (match_operand:CC 3 "cc_reg_operand" "")
2882 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2883 (match_operand:SI 2 "gpc_reg_operand" ""))
2884 (const_int 0)))
2885 (set (match_operand:SI 0 "gpc_reg_operand" "")
2886 (and:SI (match_dup 1)
2887 (match_dup 2)))
2888 (clobber (match_scratch:CC 4 ""))]
2889 "TARGET_POWERPC64 && reload_completed"
2890 [(parallel [(set (match_dup 0)
2891 (and:SI (match_dup 1)
2892 (match_dup 2)))
2893 (clobber (match_dup 4))])
2894 (set (match_dup 3)
2895 (compare:CC (match_dup 0)
2896 (const_int 0)))]
2897 "")
2898
2899 ;; Handle the PowerPC64 rlwinm corner case
2900
2901 (define_insn_and_split "*andsi3_internal6"
2902 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2903 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2904 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2905 "TARGET_POWERPC64"
2906 "#"
2907 "TARGET_POWERPC64"
2908 [(set (match_dup 0)
2909 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2910 (match_dup 4)))
2911 (set (match_dup 0)
2912 (rotate:SI (match_dup 0) (match_dup 5)))]
2913 "
2914 {
2915 int mb = extract_MB (operands[2]);
2916 int me = extract_ME (operands[2]);
2917 operands[3] = GEN_INT (me + 1);
2918 operands[5] = GEN_INT (32 - (me + 1));
2919 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2920 }"
2921 [(set_attr "length" "8")])
2922
2923 (define_expand "iorsi3"
2924 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2925 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2926 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2927 ""
2928 "
2929 {
2930 if (GET_CODE (operands[2]) == CONST_INT
2931 && ! logical_operand (operands[2], SImode))
2932 {
2933 HOST_WIDE_INT value = INTVAL (operands[2]);
2934 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2935 ? operands[0] : gen_reg_rtx (SImode));
2936
2937 emit_insn (gen_iorsi3 (tmp, operands[1],
2938 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2939 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2940 DONE;
2941 }
2942 }")
2943
2944 (define_expand "xorsi3"
2945 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2946 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2947 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2948 ""
2949 "
2950 {
2951 if (GET_CODE (operands[2]) == CONST_INT
2952 && ! logical_operand (operands[2], SImode))
2953 {
2954 HOST_WIDE_INT value = INTVAL (operands[2]);
2955 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2956 ? operands[0] : gen_reg_rtx (SImode));
2957
2958 emit_insn (gen_xorsi3 (tmp, operands[1],
2959 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2960 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2961 DONE;
2962 }
2963 }")
2964
2965 (define_insn "*boolsi3_internal1"
2966 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2967 (match_operator:SI 3 "boolean_or_operator"
2968 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2969 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2970 ""
2971 "@
2972 %q3 %0,%1,%2
2973 {%q3il|%q3i} %0,%1,%b2
2974 {%q3iu|%q3is} %0,%1,%u2")
2975
2976 (define_insn "*boolsi3_internal2"
2977 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2978 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2979 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2980 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2981 (const_int 0)))
2982 (clobber (match_scratch:SI 3 "=r,r"))]
2983 "TARGET_32BIT"
2984 "@
2985 %q4. %3,%1,%2
2986 #"
2987 [(set_attr "type" "compare")
2988 (set_attr "length" "4,8")])
2989
2990 (define_split
2991 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2992 (compare:CC (match_operator:SI 4 "boolean_operator"
2993 [(match_operand:SI 1 "gpc_reg_operand" "")
2994 (match_operand:SI 2 "gpc_reg_operand" "")])
2995 (const_int 0)))
2996 (clobber (match_scratch:SI 3 ""))]
2997 "TARGET_32BIT && reload_completed"
2998 [(set (match_dup 3) (match_dup 4))
2999 (set (match_dup 0)
3000 (compare:CC (match_dup 3)
3001 (const_int 0)))]
3002 "")
3003
3004 (define_insn "*boolsi3_internal3"
3005 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3006 (compare:CC (match_operator:SI 4 "boolean_operator"
3007 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3008 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3009 (const_int 0)))
3010 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3011 (match_dup 4))]
3012 "TARGET_32BIT"
3013 "@
3014 %q4. %0,%1,%2
3015 #"
3016 [(set_attr "type" "compare")
3017 (set_attr "length" "4,8")])
3018
3019 (define_split
3020 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3021 (compare:CC (match_operator:SI 4 "boolean_operator"
3022 [(match_operand:SI 1 "gpc_reg_operand" "")
3023 (match_operand:SI 2 "gpc_reg_operand" "")])
3024 (const_int 0)))
3025 (set (match_operand:SI 0 "gpc_reg_operand" "")
3026 (match_dup 4))]
3027 "TARGET_32BIT && reload_completed"
3028 [(set (match_dup 0) (match_dup 4))
3029 (set (match_dup 3)
3030 (compare:CC (match_dup 0)
3031 (const_int 0)))]
3032 "")
3033
3034 ;; Split a logical operation that we can't do in one insn into two insns,
3035 ;; each of which does one 16-bit part. This is used by combine.
3036
3037 (define_split
3038 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3039 (match_operator:SI 3 "boolean_or_operator"
3040 [(match_operand:SI 1 "gpc_reg_operand" "")
3041 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3042 ""
3043 [(set (match_dup 0) (match_dup 4))
3044 (set (match_dup 0) (match_dup 5))]
3045 "
3046 {
3047 rtx i;
3048 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3049 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3050 operands[1], i);
3051 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3052 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3053 operands[0], i);
3054 }")
3055
3056 (define_insn "*boolcsi3_internal1"
3057 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3058 (match_operator:SI 3 "boolean_operator"
3059 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3060 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3061 ""
3062 "%q3 %0,%2,%1")
3063
3064 (define_insn "*boolcsi3_internal2"
3065 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3066 (compare:CC (match_operator:SI 4 "boolean_operator"
3067 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3068 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3069 (const_int 0)))
3070 (clobber (match_scratch:SI 3 "=r,r"))]
3071 "TARGET_32BIT"
3072 "@
3073 %q4. %3,%2,%1
3074 #"
3075 [(set_attr "type" "compare")
3076 (set_attr "length" "4,8")])
3077
3078 (define_split
3079 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3080 (compare:CC (match_operator:SI 4 "boolean_operator"
3081 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3082 (match_operand:SI 2 "gpc_reg_operand" "")])
3083 (const_int 0)))
3084 (clobber (match_scratch:SI 3 ""))]
3085 "TARGET_32BIT && reload_completed"
3086 [(set (match_dup 3) (match_dup 4))
3087 (set (match_dup 0)
3088 (compare:CC (match_dup 3)
3089 (const_int 0)))]
3090 "")
3091
3092 (define_insn "*boolcsi3_internal3"
3093 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3094 (compare:CC (match_operator:SI 4 "boolean_operator"
3095 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3096 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3097 (const_int 0)))
3098 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3099 (match_dup 4))]
3100 "TARGET_32BIT"
3101 "@
3102 %q4. %0,%2,%1
3103 #"
3104 [(set_attr "type" "compare")
3105 (set_attr "length" "4,8")])
3106
3107 (define_split
3108 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3109 (compare:CC (match_operator:SI 4 "boolean_operator"
3110 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3111 (match_operand:SI 2 "gpc_reg_operand" "")])
3112 (const_int 0)))
3113 (set (match_operand:SI 0 "gpc_reg_operand" "")
3114 (match_dup 4))]
3115 "TARGET_32BIT && reload_completed"
3116 [(set (match_dup 0) (match_dup 4))
3117 (set (match_dup 3)
3118 (compare:CC (match_dup 0)
3119 (const_int 0)))]
3120 "")
3121
3122 (define_insn "*boolccsi3_internal1"
3123 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3124 (match_operator:SI 3 "boolean_operator"
3125 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3126 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3127 ""
3128 "%q3 %0,%1,%2")
3129
3130 (define_insn "*boolccsi3_internal2"
3131 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3132 (compare:CC (match_operator:SI 4 "boolean_operator"
3133 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3134 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3135 (const_int 0)))
3136 (clobber (match_scratch:SI 3 "=r,r"))]
3137 "TARGET_32BIT"
3138 "@
3139 %q4. %3,%1,%2
3140 #"
3141 [(set_attr "type" "compare")
3142 (set_attr "length" "4,8")])
3143
3144 (define_split
3145 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3146 (compare:CC (match_operator:SI 4 "boolean_operator"
3147 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3148 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3149 (const_int 0)))
3150 (clobber (match_scratch:SI 3 ""))]
3151 "TARGET_32BIT && reload_completed"
3152 [(set (match_dup 3) (match_dup 4))
3153 (set (match_dup 0)
3154 (compare:CC (match_dup 3)
3155 (const_int 0)))]
3156 "")
3157
3158 (define_insn "*boolccsi3_internal3"
3159 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3160 (compare:CC (match_operator:SI 4 "boolean_operator"
3161 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3162 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3163 (const_int 0)))
3164 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3165 (match_dup 4))]
3166 "TARGET_32BIT"
3167 "@
3168 %q4. %0,%1,%2
3169 #"
3170 [(set_attr "type" "compare")
3171 (set_attr "length" "4,8")])
3172
3173 (define_split
3174 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3175 (compare:CC (match_operator:SI 4 "boolean_operator"
3176 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3177 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3178 (const_int 0)))
3179 (set (match_operand:SI 0 "gpc_reg_operand" "")
3180 (match_dup 4))]
3181 "TARGET_32BIT && reload_completed"
3182 [(set (match_dup 0) (match_dup 4))
3183 (set (match_dup 3)
3184 (compare:CC (match_dup 0)
3185 (const_int 0)))]
3186 "")
3187
3188 ;; maskir insn. We need four forms because things might be in arbitrary
3189 ;; orders. Don't define forms that only set CR fields because these
3190 ;; would modify an input register.
3191
3192 (define_insn "*maskir_internal1"
3193 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3194 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3195 (match_operand:SI 1 "gpc_reg_operand" "0"))
3196 (and:SI (match_dup 2)
3197 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3198 "TARGET_POWER"
3199 "maskir %0,%3,%2")
3200
3201 (define_insn "*maskir_internal2"
3202 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3203 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3204 (match_operand:SI 1 "gpc_reg_operand" "0"))
3205 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3206 (match_dup 2))))]
3207 "TARGET_POWER"
3208 "maskir %0,%3,%2")
3209
3210 (define_insn "*maskir_internal3"
3211 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3212 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3213 (match_operand:SI 3 "gpc_reg_operand" "r"))
3214 (and:SI (not:SI (match_dup 2))
3215 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3216 "TARGET_POWER"
3217 "maskir %0,%3,%2")
3218
3219 (define_insn "*maskir_internal4"
3220 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3221 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3222 (match_operand:SI 2 "gpc_reg_operand" "r"))
3223 (and:SI (not:SI (match_dup 2))
3224 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3225 "TARGET_POWER"
3226 "maskir %0,%3,%2")
3227
3228 (define_insn "*maskir_internal5"
3229 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3230 (compare:CC
3231 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3232 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3233 (and:SI (match_dup 2)
3234 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3235 (const_int 0)))
3236 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3237 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3238 (and:SI (match_dup 2) (match_dup 3))))]
3239 "TARGET_POWER"
3240 "@
3241 maskir. %0,%3,%2
3242 #"
3243 [(set_attr "type" "compare")
3244 (set_attr "length" "4,8")])
3245
3246 (define_split
3247 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3248 (compare:CC
3249 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3250 (match_operand:SI 1 "gpc_reg_operand" ""))
3251 (and:SI (match_dup 2)
3252 (match_operand:SI 3 "gpc_reg_operand" "")))
3253 (const_int 0)))
3254 (set (match_operand:SI 0 "gpc_reg_operand" "")
3255 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3256 (and:SI (match_dup 2) (match_dup 3))))]
3257 "TARGET_POWER && reload_completed"
3258 [(set (match_dup 0)
3259 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3260 (and:SI (match_dup 2) (match_dup 3))))
3261 (set (match_dup 4)
3262 (compare:CC (match_dup 0)
3263 (const_int 0)))]
3264 "")
3265
3266 (define_insn "*maskir_internal6"
3267 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3268 (compare:CC
3269 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3270 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3271 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3272 (match_dup 2)))
3273 (const_int 0)))
3274 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3275 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3276 (and:SI (match_dup 3) (match_dup 2))))]
3277 "TARGET_POWER"
3278 "@
3279 maskir. %0,%3,%2
3280 #"
3281 [(set_attr "type" "compare")
3282 (set_attr "length" "4,8")])
3283
3284 (define_split
3285 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3286 (compare:CC
3287 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3288 (match_operand:SI 1 "gpc_reg_operand" ""))
3289 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3290 (match_dup 2)))
3291 (const_int 0)))
3292 (set (match_operand:SI 0 "gpc_reg_operand" "")
3293 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3294 (and:SI (match_dup 3) (match_dup 2))))]
3295 "TARGET_POWER && reload_completed"
3296 [(set (match_dup 0)
3297 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3298 (and:SI (match_dup 3) (match_dup 2))))
3299 (set (match_dup 4)
3300 (compare:CC (match_dup 0)
3301 (const_int 0)))]
3302 "")
3303
3304 (define_insn "*maskir_internal7"
3305 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3306 (compare:CC
3307 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3308 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3309 (and:SI (not:SI (match_dup 2))
3310 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3311 (const_int 0)))
3312 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3313 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3314 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3315 "TARGET_POWER"
3316 "@
3317 maskir. %0,%3,%2
3318 #"
3319 [(set_attr "type" "compare")
3320 (set_attr "length" "4,8")])
3321
3322 (define_split
3323 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3324 (compare:CC
3325 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3326 (match_operand:SI 3 "gpc_reg_operand" ""))
3327 (and:SI (not:SI (match_dup 2))
3328 (match_operand:SI 1 "gpc_reg_operand" "")))
3329 (const_int 0)))
3330 (set (match_operand:SI 0 "gpc_reg_operand" "")
3331 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3332 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3333 "TARGET_POWER && reload_completed"
3334 [(set (match_dup 0)
3335 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3336 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3337 (set (match_dup 4)
3338 (compare:CC (match_dup 0)
3339 (const_int 0)))]
3340 "")
3341
3342 (define_insn "*maskir_internal8"
3343 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3344 (compare:CC
3345 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3346 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3347 (and:SI (not:SI (match_dup 2))
3348 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3349 (const_int 0)))
3350 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3351 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3352 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3353 "TARGET_POWER"
3354 "@
3355 maskir. %0,%3,%2
3356 #"
3357 [(set_attr "type" "compare")
3358 (set_attr "length" "4,8")])
3359
3360 (define_split
3361 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3362 (compare:CC
3363 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3364 (match_operand:SI 2 "gpc_reg_operand" ""))
3365 (and:SI (not:SI (match_dup 2))
3366 (match_operand:SI 1 "gpc_reg_operand" "")))
3367 (const_int 0)))
3368 (set (match_operand:SI 0 "gpc_reg_operand" "")
3369 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3370 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3371 "TARGET_POWER && reload_completed"
3372 [(set (match_dup 0)
3373 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3374 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3375 (set (match_dup 4)
3376 (compare:CC (match_dup 0)
3377 (const_int 0)))]
3378 "")
3379 \f
3380 ;; Rotate and shift insns, in all their variants. These support shifts,
3381 ;; field inserts and extracts, and various combinations thereof.
3382 (define_expand "insv"
3383 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3384 (match_operand:SI 1 "const_int_operand" "")
3385 (match_operand:SI 2 "const_int_operand" ""))
3386 (match_operand 3 "gpc_reg_operand" ""))]
3387 ""
3388 "
3389 {
3390 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3391 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3392 compiler if the address of the structure is taken later. */
3393 if (GET_CODE (operands[0]) == SUBREG
3394 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3395 FAIL;
3396
3397 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3398 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3399 else
3400 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3401 DONE;
3402 }")
3403
3404 (define_insn "insvsi"
3405 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3406 (match_operand:SI 1 "const_int_operand" "i")
3407 (match_operand:SI 2 "const_int_operand" "i"))
3408 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3409 ""
3410 "*
3411 {
3412 int start = INTVAL (operands[2]) & 31;
3413 int size = INTVAL (operands[1]) & 31;
3414
3415 operands[4] = GEN_INT (32 - start - size);
3416 operands[1] = GEN_INT (start + size - 1);
3417 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3418 }"
3419 [(set_attr "type" "insert_word")])
3420
3421 (define_insn "*insvsi_internal1"
3422 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3423 (match_operand:SI 1 "const_int_operand" "i")
3424 (match_operand:SI 2 "const_int_operand" "i"))
3425 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3426 (match_operand:SI 4 "const_int_operand" "i")))]
3427 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3428 "*
3429 {
3430 int shift = INTVAL (operands[4]) & 31;
3431 int start = INTVAL (operands[2]) & 31;
3432 int size = INTVAL (operands[1]) & 31;
3433
3434 operands[4] = GEN_INT (shift - start - size);
3435 operands[1] = GEN_INT (start + size - 1);
3436 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3437 }"
3438 [(set_attr "type" "insert_word")])
3439
3440 (define_insn "*insvsi_internal2"
3441 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3442 (match_operand:SI 1 "const_int_operand" "i")
3443 (match_operand:SI 2 "const_int_operand" "i"))
3444 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3445 (match_operand:SI 4 "const_int_operand" "i")))]
3446 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3447 "*
3448 {
3449 int shift = INTVAL (operands[4]) & 31;
3450 int start = INTVAL (operands[2]) & 31;
3451 int size = INTVAL (operands[1]) & 31;
3452
3453 operands[4] = GEN_INT (32 - shift - start - size);
3454 operands[1] = GEN_INT (start + size - 1);
3455 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3456 }"
3457 [(set_attr "type" "insert_word")])
3458
3459 (define_insn "*insvsi_internal3"
3460 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3461 (match_operand:SI 1 "const_int_operand" "i")
3462 (match_operand:SI 2 "const_int_operand" "i"))
3463 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3464 (match_operand:SI 4 "const_int_operand" "i")))]
3465 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3466 "*
3467 {
3468 int shift = INTVAL (operands[4]) & 31;
3469 int start = INTVAL (operands[2]) & 31;
3470 int size = INTVAL (operands[1]) & 31;
3471
3472 operands[4] = GEN_INT (32 - shift - start - size);
3473 operands[1] = GEN_INT (start + size - 1);
3474 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3475 }"
3476 [(set_attr "type" "insert_word")])
3477
3478 (define_insn "*insvsi_internal4"
3479 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3480 (match_operand:SI 1 "const_int_operand" "i")
3481 (match_operand:SI 2 "const_int_operand" "i"))
3482 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3483 (match_operand:SI 4 "const_int_operand" "i")
3484 (match_operand:SI 5 "const_int_operand" "i")))]
3485 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3486 "*
3487 {
3488 int extract_start = INTVAL (operands[5]) & 31;
3489 int extract_size = INTVAL (operands[4]) & 31;
3490 int insert_start = INTVAL (operands[2]) & 31;
3491 int insert_size = INTVAL (operands[1]) & 31;
3492
3493 /* Align extract field with insert field */
3494 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3495 operands[1] = GEN_INT (insert_start + insert_size - 1);
3496 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3497 }"
3498 [(set_attr "type" "insert_word")])
3499
3500 ;; combine patterns for rlwimi
3501 (define_insn "*insvsi_internal5"
3502 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3503 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3504 (match_operand:SI 1 "mask_operand" "i"))
3505 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3506 (match_operand:SI 2 "const_int_operand" "i"))
3507 (match_operand:SI 5 "mask_operand" "i"))))]
3508 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3509 "*
3510 {
3511 int me = extract_ME(operands[5]);
3512 int mb = extract_MB(operands[5]);
3513 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3514 operands[2] = GEN_INT(mb);
3515 operands[1] = GEN_INT(me);
3516 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3517 }"
3518 [(set_attr "type" "insert_word")])
3519
3520 (define_insn "*insvsi_internal6"
3521 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3522 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3523 (match_operand:SI 2 "const_int_operand" "i"))
3524 (match_operand:SI 5 "mask_operand" "i"))
3525 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3526 (match_operand:SI 1 "mask_operand" "i"))))]
3527 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3528 "*
3529 {
3530 int me = extract_ME(operands[5]);
3531 int mb = extract_MB(operands[5]);
3532 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3533 operands[2] = GEN_INT(mb);
3534 operands[1] = GEN_INT(me);
3535 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3536 }"
3537 [(set_attr "type" "insert_word")])
3538
3539 (define_insn "insvdi"
3540 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3541 (match_operand:SI 1 "const_int_operand" "i")
3542 (match_operand:SI 2 "const_int_operand" "i"))
3543 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3544 "TARGET_POWERPC64"
3545 "*
3546 {
3547 int start = INTVAL (operands[2]) & 63;
3548 int size = INTVAL (operands[1]) & 63;
3549
3550 operands[1] = GEN_INT (64 - start - size);
3551 return \"rldimi %0,%3,%H1,%H2\";
3552 }")
3553
3554 (define_insn "*insvdi_internal2"
3555 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3556 (match_operand:SI 1 "const_int_operand" "i")
3557 (match_operand:SI 2 "const_int_operand" "i"))
3558 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3559 (match_operand:SI 4 "const_int_operand" "i")))]
3560 "TARGET_POWERPC64
3561 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3562 "*
3563 {
3564 int shift = INTVAL (operands[4]) & 63;
3565 int start = (INTVAL (operands[2]) & 63) - 32;
3566 int size = INTVAL (operands[1]) & 63;
3567
3568 operands[4] = GEN_INT (64 - shift - start - size);
3569 operands[2] = GEN_INT (start);
3570 operands[1] = GEN_INT (start + size - 1);
3571 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3572 }")
3573
3574 (define_insn "*insvdi_internal3"
3575 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3576 (match_operand:SI 1 "const_int_operand" "i")
3577 (match_operand:SI 2 "const_int_operand" "i"))
3578 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3579 (match_operand:SI 4 "const_int_operand" "i")))]
3580 "TARGET_POWERPC64
3581 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3582 "*
3583 {
3584 int shift = INTVAL (operands[4]) & 63;
3585 int start = (INTVAL (operands[2]) & 63) - 32;
3586 int size = INTVAL (operands[1]) & 63;
3587
3588 operands[4] = GEN_INT (64 - shift - start - size);
3589 operands[2] = GEN_INT (start);
3590 operands[1] = GEN_INT (start + size - 1);
3591 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3592 }")
3593
3594 (define_expand "extzv"
3595 [(set (match_operand 0 "gpc_reg_operand" "")
3596 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3597 (match_operand:SI 2 "const_int_operand" "")
3598 (match_operand:SI 3 "const_int_operand" "")))]
3599 ""
3600 "
3601 {
3602 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3603 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3604 compiler if the address of the structure is taken later. */
3605 if (GET_CODE (operands[0]) == SUBREG
3606 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3607 FAIL;
3608
3609 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3610 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3611 else
3612 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3613 DONE;
3614 }")
3615
3616 (define_insn "extzvsi"
3617 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3618 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3619 (match_operand:SI 2 "const_int_operand" "i")
3620 (match_operand:SI 3 "const_int_operand" "i")))]
3621 ""
3622 "*
3623 {
3624 int start = INTVAL (operands[3]) & 31;
3625 int size = INTVAL (operands[2]) & 31;
3626
3627 if (start + size >= 32)
3628 operands[3] = const0_rtx;
3629 else
3630 operands[3] = GEN_INT (start + size);
3631 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3632 }")
3633
3634 (define_insn "*extzvsi_internal1"
3635 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3636 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3637 (match_operand:SI 2 "const_int_operand" "i,i")
3638 (match_operand:SI 3 "const_int_operand" "i,i"))
3639 (const_int 0)))
3640 (clobber (match_scratch:SI 4 "=r,r"))]
3641 ""
3642 "*
3643 {
3644 int start = INTVAL (operands[3]) & 31;
3645 int size = INTVAL (operands[2]) & 31;
3646
3647 /* Force split for non-cc0 compare. */
3648 if (which_alternative == 1)
3649 return \"#\";
3650
3651 /* If the bit-field being tested fits in the upper or lower half of a
3652 word, it is possible to use andiu. or andil. to test it. This is
3653 useful because the condition register set-use delay is smaller for
3654 andi[ul]. than for rlinm. This doesn't work when the starting bit
3655 position is 0 because the LT and GT bits may be set wrong. */
3656
3657 if ((start > 0 && start + size <= 16) || start >= 16)
3658 {
3659 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3660 - (1 << (16 - (start & 15) - size))));
3661 if (start < 16)
3662 return \"{andiu.|andis.} %4,%1,%3\";
3663 else
3664 return \"{andil.|andi.} %4,%1,%3\";
3665 }
3666
3667 if (start + size >= 32)
3668 operands[3] = const0_rtx;
3669 else
3670 operands[3] = GEN_INT (start + size);
3671 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3672 }"
3673 [(set_attr "type" "compare")
3674 (set_attr "length" "4,8")])
3675
3676 (define_split
3677 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3678 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3679 (match_operand:SI 2 "const_int_operand" "")
3680 (match_operand:SI 3 "const_int_operand" ""))
3681 (const_int 0)))
3682 (clobber (match_scratch:SI 4 ""))]
3683 "reload_completed"
3684 [(set (match_dup 4)
3685 (zero_extract:SI (match_dup 1) (match_dup 2)
3686 (match_dup 3)))
3687 (set (match_dup 0)
3688 (compare:CC (match_dup 4)
3689 (const_int 0)))]
3690 "")
3691
3692 (define_insn "*extzvsi_internal2"
3693 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3694 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3695 (match_operand:SI 2 "const_int_operand" "i,i")
3696 (match_operand:SI 3 "const_int_operand" "i,i"))
3697 (const_int 0)))
3698 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3699 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3700 ""
3701 "*
3702 {
3703 int start = INTVAL (operands[3]) & 31;
3704 int size = INTVAL (operands[2]) & 31;
3705
3706 /* Force split for non-cc0 compare. */
3707 if (which_alternative == 1)
3708 return \"#\";
3709
3710 /* Since we are using the output value, we can't ignore any need for
3711 a shift. The bit-field must end at the LSB. */
3712 if (start >= 16 && start + size == 32)
3713 {
3714 operands[3] = GEN_INT ((1 << size) - 1);
3715 return \"{andil.|andi.} %0,%1,%3\";
3716 }
3717
3718 if (start + size >= 32)
3719 operands[3] = const0_rtx;
3720 else
3721 operands[3] = GEN_INT (start + size);
3722 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3723 }"
3724 [(set_attr "type" "compare")
3725 (set_attr "length" "4,8")])
3726
3727 (define_split
3728 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3729 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3730 (match_operand:SI 2 "const_int_operand" "")
3731 (match_operand:SI 3 "const_int_operand" ""))
3732 (const_int 0)))
3733 (set (match_operand:SI 0 "gpc_reg_operand" "")
3734 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3735 "reload_completed"
3736 [(set (match_dup 0)
3737 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3738 (set (match_dup 4)
3739 (compare:CC (match_dup 0)
3740 (const_int 0)))]
3741 "")
3742
3743 (define_insn "extzvdi"
3744 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3745 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3746 (match_operand:SI 2 "const_int_operand" "i")
3747 (match_operand:SI 3 "const_int_operand" "i")))]
3748 "TARGET_POWERPC64"
3749 "*
3750 {
3751 int start = INTVAL (operands[3]) & 63;
3752 int size = INTVAL (operands[2]) & 63;
3753
3754 if (start + size >= 64)
3755 operands[3] = const0_rtx;
3756 else
3757 operands[3] = GEN_INT (start + size);
3758 operands[2] = GEN_INT (64 - size);
3759 return \"rldicl %0,%1,%3,%2\";
3760 }")
3761
3762 (define_insn "*extzvdi_internal1"
3763 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3764 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3765 (match_operand:SI 2 "const_int_operand" "i")
3766 (match_operand:SI 3 "const_int_operand" "i"))
3767 (const_int 0)))
3768 (clobber (match_scratch:DI 4 "=r"))]
3769 "TARGET_64BIT"
3770 "*
3771 {
3772 int start = INTVAL (operands[3]) & 63;
3773 int size = INTVAL (operands[2]) & 63;
3774
3775 if (start + size >= 64)
3776 operands[3] = const0_rtx;
3777 else
3778 operands[3] = GEN_INT (start + size);
3779 operands[2] = GEN_INT (64 - size);
3780 return \"rldicl. %4,%1,%3,%2\";
3781 }"
3782 [(set_attr "type" "compare")])
3783
3784 (define_insn "*extzvdi_internal2"
3785 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3786 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3787 (match_operand:SI 2 "const_int_operand" "i")
3788 (match_operand:SI 3 "const_int_operand" "i"))
3789 (const_int 0)))
3790 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3791 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3792 "TARGET_64BIT"
3793 "*
3794 {
3795 int start = INTVAL (operands[3]) & 63;
3796 int size = INTVAL (operands[2]) & 63;
3797
3798 if (start + size >= 64)
3799 operands[3] = const0_rtx;
3800 else
3801 operands[3] = GEN_INT (start + size);
3802 operands[2] = GEN_INT (64 - size);
3803 return \"rldicl. %0,%1,%3,%2\";
3804 }"
3805 [(set_attr "type" "compare")])
3806
3807 (define_insn "rotlsi3"
3808 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3809 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3810 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3811 ""
3812 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3813
3814 (define_insn "*rotlsi3_internal2"
3815 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3816 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3817 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3818 (const_int 0)))
3819 (clobber (match_scratch:SI 3 "=r,r"))]
3820 ""
3821 "@
3822 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3823 #"
3824 [(set_attr "type" "delayed_compare")
3825 (set_attr "length" "4,8")])
3826
3827 (define_split
3828 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3829 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3830 (match_operand:SI 2 "reg_or_cint_operand" ""))
3831 (const_int 0)))
3832 (clobber (match_scratch:SI 3 ""))]
3833 "reload_completed"
3834 [(set (match_dup 3)
3835 (rotate:SI (match_dup 1) (match_dup 2)))
3836 (set (match_dup 0)
3837 (compare:CC (match_dup 3)
3838 (const_int 0)))]
3839 "")
3840
3841 (define_insn "*rotlsi3_internal3"
3842 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3843 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3844 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3845 (const_int 0)))
3846 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3847 (rotate:SI (match_dup 1) (match_dup 2)))]
3848 ""
3849 "@
3850 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3851 #"
3852 [(set_attr "type" "delayed_compare")
3853 (set_attr "length" "4,8")])
3854
3855 (define_split
3856 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3857 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3858 (match_operand:SI 2 "reg_or_cint_operand" ""))
3859 (const_int 0)))
3860 (set (match_operand:SI 0 "gpc_reg_operand" "")
3861 (rotate:SI (match_dup 1) (match_dup 2)))]
3862 "reload_completed"
3863 [(set (match_dup 0)
3864 (rotate:SI (match_dup 1) (match_dup 2)))
3865 (set (match_dup 3)
3866 (compare:CC (match_dup 0)
3867 (const_int 0)))]
3868 "")
3869
3870 (define_insn "*rotlsi3_internal4"
3871 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3872 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3873 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3874 (match_operand:SI 3 "mask_operand" "n")))]
3875 ""
3876 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3877
3878 (define_insn "*rotlsi3_internal5"
3879 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3880 (compare:CC (and:SI
3881 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3882 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3883 (match_operand:SI 3 "mask_operand" "n,n"))
3884 (const_int 0)))
3885 (clobber (match_scratch:SI 4 "=r,r"))]
3886 ""
3887 "@
3888 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3889 #"
3890 [(set_attr "type" "delayed_compare")
3891 (set_attr "length" "4,8")])
3892
3893 (define_split
3894 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3895 (compare:CC (and:SI
3896 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3897 (match_operand:SI 2 "reg_or_cint_operand" ""))
3898 (match_operand:SI 3 "mask_operand" ""))
3899 (const_int 0)))
3900 (clobber (match_scratch:SI 4 ""))]
3901 "reload_completed"
3902 [(set (match_dup 4)
3903 (and:SI (rotate:SI (match_dup 1)
3904 (match_dup 2))
3905 (match_dup 3)))
3906 (set (match_dup 0)
3907 (compare:CC (match_dup 4)
3908 (const_int 0)))]
3909 "")
3910
3911 (define_insn "*rotlsi3_internal6"
3912 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3913 (compare:CC (and:SI
3914 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3915 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3916 (match_operand:SI 3 "mask_operand" "n,n"))
3917 (const_int 0)))
3918 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3919 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3920 ""
3921 "@
3922 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3923 #"
3924 [(set_attr "type" "delayed_compare")
3925 (set_attr "length" "4,8")])
3926
3927 (define_split
3928 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3929 (compare:CC (and:SI
3930 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3931 (match_operand:SI 2 "reg_or_cint_operand" ""))
3932 (match_operand:SI 3 "mask_operand" ""))
3933 (const_int 0)))
3934 (set (match_operand:SI 0 "gpc_reg_operand" "")
3935 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3936 "reload_completed"
3937 [(set (match_dup 0)
3938 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3939 (set (match_dup 4)
3940 (compare:CC (match_dup 0)
3941 (const_int 0)))]
3942 "")
3943
3944 (define_insn "*rotlsi3_internal7"
3945 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3946 (zero_extend:SI
3947 (subreg:QI
3948 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3949 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3950 ""
3951 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3952
3953 (define_insn "*rotlsi3_internal8"
3954 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3955 (compare:CC (zero_extend:SI
3956 (subreg:QI
3957 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3958 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3959 (const_int 0)))
3960 (clobber (match_scratch:SI 3 "=r,r"))]
3961 ""
3962 "@
3963 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3964 #"
3965 [(set_attr "type" "delayed_compare")
3966 (set_attr "length" "4,8")])
3967
3968 (define_split
3969 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3970 (compare:CC (zero_extend:SI
3971 (subreg:QI
3972 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3973 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3974 (const_int 0)))
3975 (clobber (match_scratch:SI 3 ""))]
3976 "reload_completed"
3977 [(set (match_dup 3)
3978 (zero_extend:SI (subreg:QI
3979 (rotate:SI (match_dup 1)
3980 (match_dup 2)) 0)))
3981 (set (match_dup 0)
3982 (compare:CC (match_dup 3)
3983 (const_int 0)))]
3984 "")
3985
3986 (define_insn "*rotlsi3_internal9"
3987 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3988 (compare:CC (zero_extend:SI
3989 (subreg:QI
3990 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3991 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3992 (const_int 0)))
3993 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3994 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3995 ""
3996 "@
3997 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3998 #"
3999 [(set_attr "type" "delayed_compare")
4000 (set_attr "length" "4,8")])
4001
4002 (define_split
4003 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4004 (compare:CC (zero_extend:SI
4005 (subreg:QI
4006 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4007 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4008 (const_int 0)))
4009 (set (match_operand:SI 0 "gpc_reg_operand" "")
4010 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4011 "reload_completed"
4012 [(set (match_dup 0)
4013 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4014 (set (match_dup 3)
4015 (compare:CC (match_dup 0)
4016 (const_int 0)))]
4017 "")
4018
4019 (define_insn "*rotlsi3_internal10"
4020 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4021 (zero_extend:SI
4022 (subreg:HI
4023 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4024 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4025 ""
4026 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
4027
4028 (define_insn "*rotlsi3_internal11"
4029 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4030 (compare:CC (zero_extend:SI
4031 (subreg:HI
4032 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4033 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
4034 (const_int 0)))
4035 (clobber (match_scratch:SI 3 "=r,r"))]
4036 ""
4037 "@
4038 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
4039 #"
4040 [(set_attr "type" "delayed_compare")
4041 (set_attr "length" "4,8")])
4042
4043 (define_split
4044 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4045 (compare:CC (zero_extend:SI
4046 (subreg:HI
4047 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4048 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4049 (const_int 0)))
4050 (clobber (match_scratch:SI 3 ""))]
4051 "reload_completed"
4052 [(set (match_dup 3)
4053 (zero_extend:SI (subreg:HI
4054 (rotate:SI (match_dup 1)
4055 (match_dup 2)) 0)))
4056 (set (match_dup 0)
4057 (compare:CC (match_dup 3)
4058 (const_int 0)))]
4059 "")
4060
4061 (define_insn "*rotlsi3_internal12"
4062 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4063 (compare:CC (zero_extend:SI
4064 (subreg:HI
4065 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4066 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
4067 (const_int 0)))
4068 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4069 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4070 ""
4071 "@
4072 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
4073 #"
4074 [(set_attr "type" "delayed_compare")
4075 (set_attr "length" "4,8")])
4076
4077 (define_split
4078 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4079 (compare:CC (zero_extend:SI
4080 (subreg:HI
4081 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4082 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4083 (const_int 0)))
4084 (set (match_operand:SI 0 "gpc_reg_operand" "")
4085 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4086 "reload_completed"
4087 [(set (match_dup 0)
4088 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4089 (set (match_dup 3)
4090 (compare:CC (match_dup 0)
4091 (const_int 0)))]
4092 "")
4093
4094 ;; Note that we use "sle." instead of "sl." so that we can set
4095 ;; SHIFT_COUNT_TRUNCATED.
4096
4097 (define_expand "ashlsi3"
4098 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4099 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4100 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4101 ""
4102 "
4103 {
4104 if (TARGET_POWER)
4105 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4106 else
4107 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4108 DONE;
4109 }")
4110
4111 (define_insn "ashlsi3_power"
4112 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4113 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4114 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4115 (clobber (match_scratch:SI 3 "=q,X"))]
4116 "TARGET_POWER"
4117 "@
4118 sle %0,%1,%2
4119 {sli|slwi} %0,%1,%h2")
4120
4121 (define_insn "ashlsi3_no_power"
4122 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4123 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4124 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4125 "! TARGET_POWER"
4126 "{sl|slw}%I2 %0,%1,%h2")
4127
4128 (define_insn ""
4129 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4130 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4131 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4132 (const_int 0)))
4133 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4134 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4135 "TARGET_POWER"
4136 "@
4137 sle. %3,%1,%2
4138 {sli.|slwi.} %3,%1,%h2
4139 #
4140 #"
4141 [(set_attr "type" "delayed_compare")
4142 (set_attr "length" "4,4,8,8")])
4143
4144 (define_split
4145 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4146 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4147 (match_operand:SI 2 "reg_or_cint_operand" ""))
4148 (const_int 0)))
4149 (clobber (match_scratch:SI 3 ""))
4150 (clobber (match_scratch:SI 4 ""))]
4151 "TARGET_POWER && reload_completed"
4152 [(parallel [(set (match_dup 3)
4153 (ashift:SI (match_dup 1) (match_dup 2)))
4154 (clobber (match_dup 4))])
4155 (set (match_dup 0)
4156 (compare:CC (match_dup 3)
4157 (const_int 0)))]
4158 "")
4159
4160 (define_insn ""
4161 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4162 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4163 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4164 (const_int 0)))
4165 (clobber (match_scratch:SI 3 "=r,r"))]
4166 "! TARGET_POWER && TARGET_32BIT"
4167 "@
4168 {sl|slw}%I2. %3,%1,%h2
4169 #"
4170 [(set_attr "type" "delayed_compare")
4171 (set_attr "length" "4,8")])
4172
4173 (define_split
4174 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4175 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4176 (match_operand:SI 2 "reg_or_cint_operand" ""))
4177 (const_int 0)))
4178 (clobber (match_scratch:SI 3 ""))]
4179 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4180 [(set (match_dup 3)
4181 (ashift:SI (match_dup 1) (match_dup 2)))
4182 (set (match_dup 0)
4183 (compare:CC (match_dup 3)
4184 (const_int 0)))]
4185 "")
4186
4187 (define_insn ""
4188 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4189 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4190 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4191 (const_int 0)))
4192 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4193 (ashift:SI (match_dup 1) (match_dup 2)))
4194 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4195 "TARGET_POWER"
4196 "@
4197 sle. %0,%1,%2
4198 {sli.|slwi.} %0,%1,%h2
4199 #
4200 #"
4201 [(set_attr "type" "delayed_compare")
4202 (set_attr "length" "4,4,8,8")])
4203
4204 (define_split
4205 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4206 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4207 (match_operand:SI 2 "reg_or_cint_operand" ""))
4208 (const_int 0)))
4209 (set (match_operand:SI 0 "gpc_reg_operand" "")
4210 (ashift:SI (match_dup 1) (match_dup 2)))
4211 (clobber (match_scratch:SI 4 ""))]
4212 "TARGET_POWER && reload_completed"
4213 [(parallel [(set (match_dup 0)
4214 (ashift:SI (match_dup 1) (match_dup 2)))
4215 (clobber (match_dup 4))])
4216 (set (match_dup 3)
4217 (compare:CC (match_dup 0)
4218 (const_int 0)))]
4219 "")
4220
4221 (define_insn ""
4222 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4223 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4224 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4225 (const_int 0)))
4226 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4227 (ashift:SI (match_dup 1) (match_dup 2)))]
4228 "! TARGET_POWER && TARGET_32BIT"
4229 "@
4230 {sl|slw}%I2. %0,%1,%h2
4231 #"
4232 [(set_attr "type" "delayed_compare")
4233 (set_attr "length" "4,8")])
4234
4235 (define_split
4236 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4237 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4238 (match_operand:SI 2 "reg_or_cint_operand" ""))
4239 (const_int 0)))
4240 (set (match_operand:SI 0 "gpc_reg_operand" "")
4241 (ashift:SI (match_dup 1) (match_dup 2)))]
4242 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4243 [(set (match_dup 0)
4244 (ashift:SI (match_dup 1) (match_dup 2)))
4245 (set (match_dup 3)
4246 (compare:CC (match_dup 0)
4247 (const_int 0)))]
4248 "")
4249
4250 (define_insn "rlwinm"
4251 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4252 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4253 (match_operand:SI 2 "const_int_operand" "i"))
4254 (match_operand:SI 3 "mask_operand" "n")))]
4255 "includes_lshift_p (operands[2], operands[3])"
4256 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4257
4258 (define_insn ""
4259 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4260 (compare:CC
4261 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4262 (match_operand:SI 2 "const_int_operand" "i,i"))
4263 (match_operand:SI 3 "mask_operand" "n,n"))
4264 (const_int 0)))
4265 (clobber (match_scratch:SI 4 "=r,r"))]
4266 "includes_lshift_p (operands[2], operands[3])"
4267 "@
4268 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4269 #"
4270 [(set_attr "type" "delayed_compare")
4271 (set_attr "length" "4,8")])
4272
4273 (define_split
4274 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4275 (compare:CC
4276 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4277 (match_operand:SI 2 "const_int_operand" ""))
4278 (match_operand:SI 3 "mask_operand" ""))
4279 (const_int 0)))
4280 (clobber (match_scratch:SI 4 ""))]
4281 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4282 [(set (match_dup 4)
4283 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4284 (match_dup 3)))
4285 (set (match_dup 0)
4286 (compare:CC (match_dup 4)
4287 (const_int 0)))]
4288 "")
4289
4290 (define_insn ""
4291 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4292 (compare:CC
4293 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4294 (match_operand:SI 2 "const_int_operand" "i,i"))
4295 (match_operand:SI 3 "mask_operand" "n,n"))
4296 (const_int 0)))
4297 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4298 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4299 "includes_lshift_p (operands[2], operands[3])"
4300 "@
4301 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4302 #"
4303 [(set_attr "type" "delayed_compare")
4304 (set_attr "length" "4,8")])
4305
4306 (define_split
4307 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4308 (compare:CC
4309 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4310 (match_operand:SI 2 "const_int_operand" ""))
4311 (match_operand:SI 3 "mask_operand" ""))
4312 (const_int 0)))
4313 (set (match_operand:SI 0 "gpc_reg_operand" "")
4314 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4315 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4316 [(set (match_dup 0)
4317 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4318 (set (match_dup 4)
4319 (compare:CC (match_dup 0)
4320 (const_int 0)))]
4321 "")
4322
4323 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
4324 ;; "sli x,x,0".
4325 (define_expand "lshrsi3"
4326 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4327 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4328 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4329 ""
4330 "
4331 {
4332 if (TARGET_POWER)
4333 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4334 else
4335 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
4336 DONE;
4337 }")
4338
4339 (define_insn "lshrsi3_power"
4340 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4341 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4342 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4343 (clobber (match_scratch:SI 3 "=q,X,X"))]
4344 "TARGET_POWER"
4345 "@
4346 sre %0,%1,%2
4347 mr %0,%1
4348 {s%A2i|s%A2wi} %0,%1,%h2")
4349
4350 (define_insn "lshrsi3_no_power"
4351 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4352 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4353 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
4354 "! TARGET_POWER"
4355 "@
4356 mr %0,%1
4357 {sr|srw}%I2 %0,%1,%h2")
4358
4359 (define_insn ""
4360 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4361 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4362 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4363 (const_int 0)))
4364 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4365 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4366 "TARGET_POWER"
4367 "@
4368 sre. %3,%1,%2
4369 mr. %1,%1
4370 {s%A2i.|s%A2wi.} %3,%1,%h2
4371 #
4372 #
4373 #"
4374 [(set_attr "type" "delayed_compare")
4375 (set_attr "length" "4,4,4,8,8,8")])
4376
4377 (define_split
4378 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4379 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4380 (match_operand:SI 2 "reg_or_cint_operand" ""))
4381 (const_int 0)))
4382 (clobber (match_scratch:SI 3 ""))
4383 (clobber (match_scratch:SI 4 ""))]
4384 "TARGET_POWER && reload_completed"
4385 [(parallel [(set (match_dup 3)
4386 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4387 (clobber (match_dup 4))])
4388 (set (match_dup 0)
4389 (compare:CC (match_dup 3)
4390 (const_int 0)))]
4391 "")
4392
4393 (define_insn ""
4394 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4395 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4396 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
4397 (const_int 0)))
4398 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
4399 "! TARGET_POWER && TARGET_32BIT"
4400 "@
4401 mr. %1,%1
4402 {sr|srw}%I2. %3,%1,%h2
4403 #
4404 #"
4405 [(set_attr "type" "delayed_compare")
4406 (set_attr "length" "4,4,8,8")])
4407
4408 (define_split
4409 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4410 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4411 (match_operand:SI 2 "reg_or_cint_operand" ""))
4412 (const_int 0)))
4413 (clobber (match_scratch:SI 3 ""))]
4414 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4415 [(set (match_dup 3)
4416 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4417 (set (match_dup 0)
4418 (compare:CC (match_dup 3)
4419 (const_int 0)))]
4420 "")
4421
4422 (define_insn ""
4423 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4424 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4425 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4426 (const_int 0)))
4427 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4428 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4429 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4430 "TARGET_POWER"
4431 "@
4432 sre. %0,%1,%2
4433 mr. %0,%1
4434 {s%A2i.|s%A2wi.} %0,%1,%h2
4435 #
4436 #
4437 #"
4438 [(set_attr "type" "delayed_compare")
4439 (set_attr "length" "4,4,4,8,8,8")])
4440
4441 (define_split
4442 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4443 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4444 (match_operand:SI 2 "reg_or_cint_operand" ""))
4445 (const_int 0)))
4446 (set (match_operand:SI 0 "gpc_reg_operand" "")
4447 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4448 (clobber (match_scratch:SI 4 ""))]
4449 "TARGET_POWER && reload_completed"
4450 [(parallel [(set (match_dup 0)
4451 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4452 (clobber (match_dup 4))])
4453 (set (match_dup 3)
4454 (compare:CC (match_dup 0)
4455 (const_int 0)))]
4456 "")
4457
4458 (define_insn ""
4459 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4460 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4461 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
4462 (const_int 0)))
4463 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4464 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4465 "! TARGET_POWER && TARGET_32BIT"
4466 "@
4467 mr. %0,%1
4468 {sr|srw}%I2. %0,%1,%h2
4469 #
4470 #"
4471 [(set_attr "type" "delayed_compare")
4472 (set_attr "length" "4,4,8,8")])
4473
4474 (define_split
4475 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4476 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4477 (match_operand:SI 2 "reg_or_cint_operand" ""))
4478 (const_int 0)))
4479 (set (match_operand:SI 0 "gpc_reg_operand" "")
4480 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4481 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4482 [(set (match_dup 0)
4483 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4484 (set (match_dup 3)
4485 (compare:CC (match_dup 0)
4486 (const_int 0)))]
4487 "")
4488
4489 (define_insn ""
4490 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4491 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4492 (match_operand:SI 2 "const_int_operand" "i"))
4493 (match_operand:SI 3 "mask_operand" "n")))]
4494 "includes_rshift_p (operands[2], operands[3])"
4495 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4496
4497 (define_insn ""
4498 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4499 (compare:CC
4500 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4501 (match_operand:SI 2 "const_int_operand" "i,i"))
4502 (match_operand:SI 3 "mask_operand" "n,n"))
4503 (const_int 0)))
4504 (clobber (match_scratch:SI 4 "=r,r"))]
4505 "includes_rshift_p (operands[2], operands[3])"
4506 "@
4507 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4508 #"
4509 [(set_attr "type" "delayed_compare")
4510 (set_attr "length" "4,8")])
4511
4512 (define_split
4513 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4514 (compare:CC
4515 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4516 (match_operand:SI 2 "const_int_operand" ""))
4517 (match_operand:SI 3 "mask_operand" ""))
4518 (const_int 0)))
4519 (clobber (match_scratch:SI 4 ""))]
4520 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4521 [(set (match_dup 4)
4522 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4523 (match_dup 3)))
4524 (set (match_dup 0)
4525 (compare:CC (match_dup 4)
4526 (const_int 0)))]
4527 "")
4528
4529 (define_insn ""
4530 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4531 (compare:CC
4532 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4533 (match_operand:SI 2 "const_int_operand" "i,i"))
4534 (match_operand:SI 3 "mask_operand" "n,n"))
4535 (const_int 0)))
4536 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4537 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4538 "includes_rshift_p (operands[2], operands[3])"
4539 "@
4540 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4541 #"
4542 [(set_attr "type" "delayed_compare")
4543 (set_attr "length" "4,8")])
4544
4545 (define_split
4546 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4547 (compare:CC
4548 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4549 (match_operand:SI 2 "const_int_operand" ""))
4550 (match_operand:SI 3 "mask_operand" ""))
4551 (const_int 0)))
4552 (set (match_operand:SI 0 "gpc_reg_operand" "")
4553 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4554 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4555 [(set (match_dup 0)
4556 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4557 (set (match_dup 4)
4558 (compare:CC (match_dup 0)
4559 (const_int 0)))]
4560 "")
4561
4562 (define_insn ""
4563 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4564 (zero_extend:SI
4565 (subreg:QI
4566 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4567 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4568 "includes_rshift_p (operands[2], GEN_INT (255))"
4569 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4570
4571 (define_insn ""
4572 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4573 (compare:CC
4574 (zero_extend:SI
4575 (subreg:QI
4576 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4577 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4578 (const_int 0)))
4579 (clobber (match_scratch:SI 3 "=r,r"))]
4580 "includes_rshift_p (operands[2], GEN_INT (255))"
4581 "@
4582 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4583 #"
4584 [(set_attr "type" "delayed_compare")
4585 (set_attr "length" "4,8")])
4586
4587 (define_split
4588 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4589 (compare:CC
4590 (zero_extend:SI
4591 (subreg:QI
4592 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4593 (match_operand:SI 2 "const_int_operand" "")) 0))
4594 (const_int 0)))
4595 (clobber (match_scratch:SI 3 ""))]
4596 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4597 [(set (match_dup 3)
4598 (zero_extend:SI (subreg:QI
4599 (lshiftrt:SI (match_dup 1)
4600 (match_dup 2)) 0)))
4601 (set (match_dup 0)
4602 (compare:CC (match_dup 3)
4603 (const_int 0)))]
4604 "")
4605
4606 (define_insn ""
4607 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4608 (compare:CC
4609 (zero_extend:SI
4610 (subreg:QI
4611 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4612 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4613 (const_int 0)))
4614 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4615 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4616 "includes_rshift_p (operands[2], GEN_INT (255))"
4617 "@
4618 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4619 #"
4620 [(set_attr "type" "delayed_compare")
4621 (set_attr "length" "4,8")])
4622
4623 (define_split
4624 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4625 (compare:CC
4626 (zero_extend:SI
4627 (subreg:QI
4628 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4629 (match_operand:SI 2 "const_int_operand" "")) 0))
4630 (const_int 0)))
4631 (set (match_operand:SI 0 "gpc_reg_operand" "")
4632 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4633 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4634 [(set (match_dup 0)
4635 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4636 (set (match_dup 3)
4637 (compare:CC (match_dup 0)
4638 (const_int 0)))]
4639 "")
4640
4641 (define_insn ""
4642 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4643 (zero_extend:SI
4644 (subreg:HI
4645 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4646 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4647 "includes_rshift_p (operands[2], GEN_INT (65535))"
4648 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4649
4650 (define_insn ""
4651 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4652 (compare:CC
4653 (zero_extend:SI
4654 (subreg:HI
4655 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4656 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4657 (const_int 0)))
4658 (clobber (match_scratch:SI 3 "=r,r"))]
4659 "includes_rshift_p (operands[2], GEN_INT (65535))"
4660 "@
4661 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4662 #"
4663 [(set_attr "type" "delayed_compare")
4664 (set_attr "length" "4,8")])
4665
4666 (define_split
4667 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4668 (compare:CC
4669 (zero_extend:SI
4670 (subreg:HI
4671 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4672 (match_operand:SI 2 "const_int_operand" "")) 0))
4673 (const_int 0)))
4674 (clobber (match_scratch:SI 3 ""))]
4675 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4676 [(set (match_dup 3)
4677 (zero_extend:SI (subreg:HI
4678 (lshiftrt:SI (match_dup 1)
4679 (match_dup 2)) 0)))
4680 (set (match_dup 0)
4681 (compare:CC (match_dup 3)
4682 (const_int 0)))]
4683 "")
4684
4685 (define_insn ""
4686 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4687 (compare:CC
4688 (zero_extend:SI
4689 (subreg:HI
4690 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4691 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4692 (const_int 0)))
4693 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4694 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4695 "includes_rshift_p (operands[2], GEN_INT (65535))"
4696 "@
4697 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4698 #"
4699 [(set_attr "type" "delayed_compare")
4700 (set_attr "length" "4,8")])
4701
4702 (define_split
4703 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4704 (compare:CC
4705 (zero_extend:SI
4706 (subreg:HI
4707 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4708 (match_operand:SI 2 "const_int_operand" "")) 0))
4709 (const_int 0)))
4710 (set (match_operand:SI 0 "gpc_reg_operand" "")
4711 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4712 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4713 [(set (match_dup 0)
4714 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4715 (set (match_dup 3)
4716 (compare:CC (match_dup 0)
4717 (const_int 0)))]
4718 "")
4719
4720 (define_insn ""
4721 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4722 (const_int 1)
4723 (match_operand:SI 1 "gpc_reg_operand" "r"))
4724 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4725 (const_int 31)))]
4726 "TARGET_POWER"
4727 "rrib %0,%1,%2")
4728
4729 (define_insn ""
4730 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4731 (const_int 1)
4732 (match_operand:SI 1 "gpc_reg_operand" "r"))
4733 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4734 (const_int 31)))]
4735 "TARGET_POWER"
4736 "rrib %0,%1,%2")
4737
4738 (define_insn ""
4739 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4740 (const_int 1)
4741 (match_operand:SI 1 "gpc_reg_operand" "r"))
4742 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4743 (const_int 1)
4744 (const_int 0)))]
4745 "TARGET_POWER"
4746 "rrib %0,%1,%2")
4747
4748 (define_expand "ashrsi3"
4749 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4750 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4751 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4752 ""
4753 "
4754 {
4755 if (TARGET_POWER)
4756 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4757 else
4758 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4759 DONE;
4760 }")
4761
4762 (define_insn "ashrsi3_power"
4763 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4764 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4765 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4766 (clobber (match_scratch:SI 3 "=q,X"))]
4767 "TARGET_POWER"
4768 "@
4769 srea %0,%1,%2
4770 {srai|srawi} %0,%1,%h2")
4771
4772 (define_insn "ashrsi3_no_power"
4773 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4774 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4775 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4776 "! TARGET_POWER"
4777 "{sra|sraw}%I2 %0,%1,%h2")
4778
4779 (define_insn ""
4780 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4781 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4782 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4783 (const_int 0)))
4784 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4785 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4786 "TARGET_POWER"
4787 "@
4788 srea. %3,%1,%2
4789 {srai.|srawi.} %3,%1,%h2
4790 #
4791 #"
4792 [(set_attr "type" "delayed_compare")
4793 (set_attr "length" "4,4,8,8")])
4794
4795 (define_split
4796 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4797 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4798 (match_operand:SI 2 "reg_or_cint_operand" ""))
4799 (const_int 0)))
4800 (clobber (match_scratch:SI 3 ""))
4801 (clobber (match_scratch:SI 4 ""))]
4802 "TARGET_POWER && reload_completed"
4803 [(parallel [(set (match_dup 3)
4804 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4805 (clobber (match_dup 4))])
4806 (set (match_dup 0)
4807 (compare:CC (match_dup 3)
4808 (const_int 0)))]
4809 "")
4810
4811 (define_insn ""
4812 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4813 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4814 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4815 (const_int 0)))
4816 (clobber (match_scratch:SI 3 "=r,r"))]
4817 "! TARGET_POWER"
4818 "@
4819 {sra|sraw}%I2. %3,%1,%h2
4820 #"
4821 [(set_attr "type" "delayed_compare")
4822 (set_attr "length" "4,8")])
4823
4824 (define_split
4825 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4826 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4827 (match_operand:SI 2 "reg_or_cint_operand" ""))
4828 (const_int 0)))
4829 (clobber (match_scratch:SI 3 ""))]
4830 "! TARGET_POWER && reload_completed"
4831 [(set (match_dup 3)
4832 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4833 (set (match_dup 0)
4834 (compare:CC (match_dup 3)
4835 (const_int 0)))]
4836 "")
4837
4838 (define_insn ""
4839 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4840 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4841 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4842 (const_int 0)))
4843 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4844 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4845 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4846 "TARGET_POWER"
4847 "@
4848 srea. %0,%1,%2
4849 {srai.|srawi.} %0,%1,%h2
4850 #
4851 #"
4852 [(set_attr "type" "delayed_compare")
4853 (set_attr "length" "4,4,8,8")])
4854
4855 (define_split
4856 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4857 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4858 (match_operand:SI 2 "reg_or_cint_operand" ""))
4859 (const_int 0)))
4860 (set (match_operand:SI 0 "gpc_reg_operand" "")
4861 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4862 (clobber (match_scratch:SI 4 ""))]
4863 "TARGET_POWER && reload_completed"
4864 [(parallel [(set (match_dup 0)
4865 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4866 (clobber (match_dup 4))])
4867 (set (match_dup 3)
4868 (compare:CC (match_dup 0)
4869 (const_int 0)))]
4870 "")
4871
4872 (define_insn ""
4873 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4874 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4875 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4876 (const_int 0)))
4877 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4878 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4879 "! TARGET_POWER"
4880 "@
4881 {sra|sraw}%I2. %0,%1,%h2
4882 #"
4883 [(set_attr "type" "delayed_compare")
4884 (set_attr "length" "4,8")])
4885 \f
4886 (define_split
4887 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4888 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4889 (match_operand:SI 2 "reg_or_cint_operand" ""))
4890 (const_int 0)))
4891 (set (match_operand:SI 0 "gpc_reg_operand" "")
4892 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4893 "! TARGET_POWER && reload_completed"
4894 [(set (match_dup 0)
4895 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4896 (set (match_dup 3)
4897 (compare:CC (match_dup 0)
4898 (const_int 0)))]
4899 "")
4900
4901 ;; Floating-point insns, excluding normal data motion.
4902 ;;
4903 ;; PowerPC has a full set of single-precision floating point instructions.
4904 ;;
4905 ;; For the POWER architecture, we pretend that we have both SFmode and
4906 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4907 ;; The only conversions we will do will be when storing to memory. In that
4908 ;; case, we will use the "frsp" instruction before storing.
4909 ;;
4910 ;; Note that when we store into a single-precision memory location, we need to
4911 ;; use the frsp insn first. If the register being stored isn't dead, we
4912 ;; need a scratch register for the frsp. But this is difficult when the store
4913 ;; is done by reload. It is not incorrect to do the frsp on the register in
4914 ;; this case, we just lose precision that we would have otherwise gotten but
4915 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4916
4917 (define_expand "extendsfdf2"
4918 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4919 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4920 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4921 "")
4922
4923 (define_insn_and_split "*extendsfdf2_fpr"
4924 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
4925 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
4926 "TARGET_HARD_FLOAT && TARGET_FPRS"
4927 "@
4928 #
4929 fmr %0,%1
4930 lfs%U1%X1 %0,%1"
4931 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4932 [(const_int 0)]
4933 {
4934 emit_note (NOTE_INSN_DELETED);
4935 DONE;
4936 }
4937 [(set_attr "type" "fp,fp,fpload")])
4938
4939 (define_expand "truncdfsf2"
4940 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4941 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4942 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4943 "")
4944
4945 (define_insn "*truncdfsf2_fpr"
4946 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4947 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4948 "TARGET_HARD_FLOAT && TARGET_FPRS"
4949 "frsp %0,%1"
4950 [(set_attr "type" "fp")])
4951
4952 (define_insn "aux_truncdfsf2"
4953 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4954 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
4955 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4956 "frsp %0,%1"
4957 [(set_attr "type" "fp")])
4958
4959 (define_expand "negsf2"
4960 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4961 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4962 "TARGET_HARD_FLOAT"
4963 "")
4964
4965 (define_insn "*negsf2"
4966 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4967 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4968 "TARGET_HARD_FLOAT && TARGET_FPRS"
4969 "fneg %0,%1"
4970 [(set_attr "type" "fp")])
4971
4972 (define_expand "abssf2"
4973 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4974 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4975 "TARGET_HARD_FLOAT"
4976 "")
4977
4978 (define_insn "*abssf2"
4979 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4980 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4981 "TARGET_HARD_FLOAT && TARGET_FPRS"
4982 "fabs %0,%1"
4983 [(set_attr "type" "fp")])
4984
4985 (define_insn ""
4986 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4987 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4988 "TARGET_HARD_FLOAT && TARGET_FPRS"
4989 "fnabs %0,%1"
4990 [(set_attr "type" "fp")])
4991
4992 (define_expand "addsf3"
4993 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4994 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4995 (match_operand:SF 2 "gpc_reg_operand" "")))]
4996 "TARGET_HARD_FLOAT"
4997 "")
4998
4999 (define_insn ""
5000 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5001 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5002 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5003 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5004 "fadds %0,%1,%2"
5005 [(set_attr "type" "fp")])
5006
5007 (define_insn ""
5008 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5009 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5010 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5011 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5012 "{fa|fadd} %0,%1,%2"
5013 [(set_attr "type" "fp")])
5014
5015 (define_expand "subsf3"
5016 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5017 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5018 (match_operand:SF 2 "gpc_reg_operand" "")))]
5019 "TARGET_HARD_FLOAT"
5020 "")
5021
5022 (define_insn ""
5023 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5024 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5025 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5026 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5027 "fsubs %0,%1,%2"
5028 [(set_attr "type" "fp")])
5029
5030 (define_insn ""
5031 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5032 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5033 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5034 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5035 "{fs|fsub} %0,%1,%2"
5036 [(set_attr "type" "fp")])
5037
5038 (define_expand "mulsf3"
5039 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5040 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5041 (match_operand:SF 2 "gpc_reg_operand" "")))]
5042 "TARGET_HARD_FLOAT"
5043 "")
5044
5045 (define_insn ""
5046 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5047 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5048 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5049 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5050 "fmuls %0,%1,%2"
5051 [(set_attr "type" "fp")])
5052
5053 (define_insn ""
5054 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5055 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5056 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5057 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5058 "{fm|fmul} %0,%1,%2"
5059 [(set_attr "type" "dmul")])
5060
5061 (define_insn "fres"
5062 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5063 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5064 "TARGET_PPC_GFXOPT && flag_finite_math_only"
5065 "fres %0,%1"
5066 [(set_attr "type" "fp")])
5067
5068 (define_expand "divsf3"
5069 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5070 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5071 (match_operand:SF 2 "gpc_reg_operand" "")))]
5072 "TARGET_HARD_FLOAT"
5073 {
5074 if (swdiv && !optimize_size && TARGET_PPC_GFXOPT
5075 && flag_finite_math_only && !flag_trapping_math)
5076 {
5077 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5078 DONE;
5079 }
5080 })
5081
5082 (define_insn ""
5083 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5084 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5085 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5086 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5087 "fdivs %0,%1,%2"
5088 [(set_attr "type" "sdiv")])
5089
5090 (define_insn ""
5091 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5092 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5093 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5094 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5095 "{fd|fdiv} %0,%1,%2"
5096 [(set_attr "type" "ddiv")])
5097
5098 (define_insn ""
5099 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5100 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5101 (match_operand:SF 2 "gpc_reg_operand" "f"))
5102 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5103 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5104 "fmadds %0,%1,%2,%3"
5105 [(set_attr "type" "fp")])
5106
5107 (define_insn ""
5108 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5109 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5110 (match_operand:SF 2 "gpc_reg_operand" "f"))
5111 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5112 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5113 "{fma|fmadd} %0,%1,%2,%3"
5114 [(set_attr "type" "dmul")])
5115
5116 (define_insn ""
5117 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5118 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5119 (match_operand:SF 2 "gpc_reg_operand" "f"))
5120 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5121 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5122 "fmsubs %0,%1,%2,%3"
5123 [(set_attr "type" "fp")])
5124
5125 (define_insn ""
5126 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5127 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5128 (match_operand:SF 2 "gpc_reg_operand" "f"))
5129 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5130 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5131 "{fms|fmsub} %0,%1,%2,%3"
5132 [(set_attr "type" "dmul")])
5133
5134 (define_insn ""
5135 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5136 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5137 (match_operand:SF 2 "gpc_reg_operand" "f"))
5138 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5139 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5140 && HONOR_SIGNED_ZEROS (SFmode)"
5141 "fnmadds %0,%1,%2,%3"
5142 [(set_attr "type" "fp")])
5143
5144 (define_insn ""
5145 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5146 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5147 (match_operand:SF 2 "gpc_reg_operand" "f"))
5148 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5149 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5150 && ! HONOR_SIGNED_ZEROS (SFmode)"
5151 "fnmadds %0,%1,%2,%3"
5152 [(set_attr "type" "fp")])
5153
5154 (define_insn ""
5155 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5156 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5157 (match_operand:SF 2 "gpc_reg_operand" "f"))
5158 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5159 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5160 "{fnma|fnmadd} %0,%1,%2,%3"
5161 [(set_attr "type" "dmul")])
5162
5163 (define_insn ""
5164 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5165 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5166 (match_operand:SF 2 "gpc_reg_operand" "f"))
5167 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5168 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5169 && ! HONOR_SIGNED_ZEROS (SFmode)"
5170 "{fnma|fnmadd} %0,%1,%2,%3"
5171 [(set_attr "type" "dmul")])
5172
5173 (define_insn ""
5174 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5175 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5176 (match_operand:SF 2 "gpc_reg_operand" "f"))
5177 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5178 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5179 && HONOR_SIGNED_ZEROS (SFmode)"
5180 "fnmsubs %0,%1,%2,%3"
5181 [(set_attr "type" "fp")])
5182
5183 (define_insn ""
5184 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5185 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5186 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5187 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5188 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5189 && ! HONOR_SIGNED_ZEROS (SFmode)"
5190 "fnmsubs %0,%1,%2,%3"
5191 [(set_attr "type" "fp")])
5192
5193 (define_insn ""
5194 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5195 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5196 (match_operand:SF 2 "gpc_reg_operand" "f"))
5197 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5198 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5199 "{fnms|fnmsub} %0,%1,%2,%3"
5200 [(set_attr "type" "dmul")])
5201
5202 (define_insn ""
5203 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5204 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5205 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5206 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5207 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5208 && ! HONOR_SIGNED_ZEROS (SFmode)"
5209 "{fnms|fnmsub} %0,%1,%2,%3"
5210 [(set_attr "type" "dmul")])
5211
5212 (define_expand "sqrtsf2"
5213 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5214 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5215 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5216 "")
5217
5218 (define_insn ""
5219 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5220 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5221 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5222 "fsqrts %0,%1"
5223 [(set_attr "type" "ssqrt")])
5224
5225 (define_insn ""
5226 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5227 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5228 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
5229 "fsqrt %0,%1"
5230 [(set_attr "type" "dsqrt")])
5231
5232 (define_expand "copysignsf3"
5233 [(set (match_dup 3)
5234 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5235 (set (match_dup 4)
5236 (neg:SF (abs:SF (match_dup 1))))
5237 (set (match_operand:SF 0 "gpc_reg_operand" "")
5238 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5239 (match_dup 5))
5240 (match_dup 3)
5241 (match_dup 4)))]
5242 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5243 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
5244 {
5245 operands[3] = gen_reg_rtx (SFmode);
5246 operands[4] = gen_reg_rtx (SFmode);
5247 operands[5] = CONST0_RTX (SFmode);
5248 })
5249
5250 (define_expand "copysigndf3"
5251 [(set (match_dup 3)
5252 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5253 (set (match_dup 4)
5254 (neg:DF (abs:DF (match_dup 1))))
5255 (set (match_operand:DF 0 "gpc_reg_operand" "")
5256 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5257 (match_dup 5))
5258 (match_dup 3)
5259 (match_dup 4)))]
5260 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5261 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
5262 {
5263 operands[3] = gen_reg_rtx (DFmode);
5264 operands[4] = gen_reg_rtx (DFmode);
5265 operands[5] = CONST0_RTX (DFmode);
5266 })
5267
5268 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5269 ;; fsel instruction and some auxiliary computations. Then we just have a
5270 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5271 ;; combine.
5272 (define_expand "smaxsf3"
5273 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5274 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5275 (match_operand:SF 2 "gpc_reg_operand" ""))
5276 (match_dup 1)
5277 (match_dup 2)))]
5278 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5279 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5280
5281 (define_expand "sminsf3"
5282 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5283 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5284 (match_operand:SF 2 "gpc_reg_operand" ""))
5285 (match_dup 2)
5286 (match_dup 1)))]
5287 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5288 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5289
5290 (define_split
5291 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5292 (match_operator:SF 3 "min_max_operator"
5293 [(match_operand:SF 1 "gpc_reg_operand" "")
5294 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5295 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5296 [(const_int 0)]
5297 "
5298 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5299 operands[1], operands[2]);
5300 DONE;
5301 }")
5302
5303 (define_expand "movsicc"
5304 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5305 (if_then_else:SI (match_operand 1 "comparison_operator" "")
5306 (match_operand:SI 2 "gpc_reg_operand" "")
5307 (match_operand:SI 3 "gpc_reg_operand" "")))]
5308 "TARGET_ISEL"
5309 "
5310 {
5311 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5312 DONE;
5313 else
5314 FAIL;
5315 }")
5316
5317 ;; We use the BASE_REGS for the isel input operands because, if rA is
5318 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5319 ;; because we may switch the operands and rB may end up being rA.
5320 ;;
5321 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5322 ;; leave out the mode in operand 4 and use one pattern, but reload can
5323 ;; change the mode underneath our feet and then gets confused trying
5324 ;; to reload the value.
5325 (define_insn "isel_signed"
5326 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5327 (if_then_else:SI
5328 (match_operator 1 "comparison_operator"
5329 [(match_operand:CC 4 "cc_reg_operand" "y")
5330 (const_int 0)])
5331 (match_operand:SI 2 "gpc_reg_operand" "b")
5332 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5333 "TARGET_ISEL"
5334 "*
5335 { return output_isel (operands); }"
5336 [(set_attr "length" "4")])
5337
5338 (define_insn "isel_unsigned"
5339 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5340 (if_then_else:SI
5341 (match_operator 1 "comparison_operator"
5342 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5343 (const_int 0)])
5344 (match_operand:SI 2 "gpc_reg_operand" "b")
5345 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5346 "TARGET_ISEL"
5347 "*
5348 { return output_isel (operands); }"
5349 [(set_attr "length" "4")])
5350
5351 (define_expand "movsfcc"
5352 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5353 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5354 (match_operand:SF 2 "gpc_reg_operand" "")
5355 (match_operand:SF 3 "gpc_reg_operand" "")))]
5356 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5357 "
5358 {
5359 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5360 DONE;
5361 else
5362 FAIL;
5363 }")
5364
5365 (define_insn "*fselsfsf4"
5366 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5367 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5368 (match_operand:SF 4 "zero_fp_constant" "F"))
5369 (match_operand:SF 2 "gpc_reg_operand" "f")
5370 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5371 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5372 "fsel %0,%1,%2,%3"
5373 [(set_attr "type" "fp")])
5374
5375 (define_insn "*fseldfsf4"
5376 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5377 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5378 (match_operand:DF 4 "zero_fp_constant" "F"))
5379 (match_operand:SF 2 "gpc_reg_operand" "f")
5380 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5381 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5382 "fsel %0,%1,%2,%3"
5383 [(set_attr "type" "fp")])
5384
5385 (define_expand "negdf2"
5386 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5387 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5388 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5389 "")
5390
5391 (define_insn "*negdf2_fpr"
5392 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5393 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5394 "TARGET_HARD_FLOAT && TARGET_FPRS"
5395 "fneg %0,%1"
5396 [(set_attr "type" "fp")])
5397
5398 (define_expand "absdf2"
5399 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5400 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5401 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5402 "")
5403
5404 (define_insn "*absdf2_fpr"
5405 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5406 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5407 "TARGET_HARD_FLOAT && TARGET_FPRS"
5408 "fabs %0,%1"
5409 [(set_attr "type" "fp")])
5410
5411 (define_insn "*nabsdf2_fpr"
5412 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5413 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
5414 "TARGET_HARD_FLOAT && TARGET_FPRS"
5415 "fnabs %0,%1"
5416 [(set_attr "type" "fp")])
5417
5418 (define_expand "adddf3"
5419 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5420 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5421 (match_operand:DF 2 "gpc_reg_operand" "")))]
5422 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5423 "")
5424
5425 (define_insn "*adddf3_fpr"
5426 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5427 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5428 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5429 "TARGET_HARD_FLOAT && TARGET_FPRS"
5430 "{fa|fadd} %0,%1,%2"
5431 [(set_attr "type" "fp")])
5432
5433 (define_expand "subdf3"
5434 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5435 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5436 (match_operand:DF 2 "gpc_reg_operand" "")))]
5437 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5438 "")
5439
5440 (define_insn "*subdf3_fpr"
5441 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5442 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5443 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5444 "TARGET_HARD_FLOAT && TARGET_FPRS"
5445 "{fs|fsub} %0,%1,%2"
5446 [(set_attr "type" "fp")])
5447
5448 (define_expand "muldf3"
5449 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5450 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5451 (match_operand:DF 2 "gpc_reg_operand" "")))]
5452 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5453 "")
5454
5455 (define_insn "*muldf3_fpr"
5456 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5457 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5458 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5459 "TARGET_HARD_FLOAT && TARGET_FPRS"
5460 "{fm|fmul} %0,%1,%2"
5461 [(set_attr "type" "dmul")])
5462
5463 (define_insn "fred"
5464 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5465 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5466 "TARGET_POPCNTB && flag_finite_math_only"
5467 "fre %0,%1"
5468 [(set_attr "type" "fp")])
5469
5470 (define_expand "divdf3"
5471 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5472 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5473 (match_operand:DF 2 "gpc_reg_operand" "")))]
5474 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5475 {
5476 if (swdiv && !optimize_size && TARGET_POPCNTB
5477 && flag_finite_math_only && !flag_trapping_math)
5478 {
5479 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5480 DONE;
5481 }
5482 })
5483
5484 (define_insn "*divdf3_fpr"
5485 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5486 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5487 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5488 "TARGET_HARD_FLOAT && TARGET_FPRS"
5489 "{fd|fdiv} %0,%1,%2"
5490 [(set_attr "type" "ddiv")])
5491
5492 (define_insn ""
5493 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5494 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5495 (match_operand:DF 2 "gpc_reg_operand" "f"))
5496 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5497 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5498 "{fma|fmadd} %0,%1,%2,%3"
5499 [(set_attr "type" "dmul")])
5500
5501 (define_insn ""
5502 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5503 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5504 (match_operand:DF 2 "gpc_reg_operand" "f"))
5505 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5506 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5507 "{fms|fmsub} %0,%1,%2,%3"
5508 [(set_attr "type" "dmul")])
5509
5510 (define_insn ""
5511 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5512 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5513 (match_operand:DF 2 "gpc_reg_operand" "f"))
5514 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5515 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5516 && HONOR_SIGNED_ZEROS (DFmode)"
5517 "{fnma|fnmadd} %0,%1,%2,%3"
5518 [(set_attr "type" "dmul")])
5519
5520 (define_insn ""
5521 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5522 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5523 (match_operand:DF 2 "gpc_reg_operand" "f"))
5524 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5525 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5526 && ! HONOR_SIGNED_ZEROS (DFmode)"
5527 "{fnma|fnmadd} %0,%1,%2,%3"
5528 [(set_attr "type" "dmul")])
5529
5530 (define_insn ""
5531 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5532 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5533 (match_operand:DF 2 "gpc_reg_operand" "f"))
5534 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5535 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5536 && HONOR_SIGNED_ZEROS (DFmode)"
5537 "{fnms|fnmsub} %0,%1,%2,%3"
5538 [(set_attr "type" "dmul")])
5539
5540 (define_insn ""
5541 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5542 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5543 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5544 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5545 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5546 && ! HONOR_SIGNED_ZEROS (DFmode)"
5547 "{fnms|fnmsub} %0,%1,%2,%3"
5548 [(set_attr "type" "dmul")])
5549
5550 (define_insn "sqrtdf2"
5551 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5552 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5553 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5554 "fsqrt %0,%1"
5555 [(set_attr "type" "dsqrt")])
5556
5557 ;; The conditional move instructions allow us to perform max and min
5558 ;; operations even when
5559
5560 (define_expand "smaxdf3"
5561 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5562 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5563 (match_operand:DF 2 "gpc_reg_operand" ""))
5564 (match_dup 1)
5565 (match_dup 2)))]
5566 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5567 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5568
5569 (define_expand "smindf3"
5570 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5571 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5572 (match_operand:DF 2 "gpc_reg_operand" ""))
5573 (match_dup 2)
5574 (match_dup 1)))]
5575 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5576 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5577
5578 (define_split
5579 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5580 (match_operator:DF 3 "min_max_operator"
5581 [(match_operand:DF 1 "gpc_reg_operand" "")
5582 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5583 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5584 [(const_int 0)]
5585 "
5586 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5587 operands[1], operands[2]);
5588 DONE;
5589 }")
5590
5591 (define_expand "movdfcc"
5592 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5593 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5594 (match_operand:DF 2 "gpc_reg_operand" "")
5595 (match_operand:DF 3 "gpc_reg_operand" "")))]
5596 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5597 "
5598 {
5599 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5600 DONE;
5601 else
5602 FAIL;
5603 }")
5604
5605 (define_insn "*fseldfdf4"
5606 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5607 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5608 (match_operand:DF 4 "zero_fp_constant" "F"))
5609 (match_operand:DF 2 "gpc_reg_operand" "f")
5610 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5611 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5612 "fsel %0,%1,%2,%3"
5613 [(set_attr "type" "fp")])
5614
5615 (define_insn "*fselsfdf4"
5616 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5617 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5618 (match_operand:SF 4 "zero_fp_constant" "F"))
5619 (match_operand:DF 2 "gpc_reg_operand" "f")
5620 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5621 "TARGET_PPC_GFXOPT"
5622 "fsel %0,%1,%2,%3"
5623 [(set_attr "type" "fp")])
5624 \f
5625 ;; Conversions to and from floating-point.
5626
5627 (define_expand "fixuns_truncsfsi2"
5628 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5629 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5630 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5631 "")
5632
5633 (define_expand "fix_truncsfsi2"
5634 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5635 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5636 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5637 "")
5638
5639 ; For each of these conversions, there is a define_expand, a define_insn
5640 ; with a '#' template, and a define_split (with C code). The idea is
5641 ; to allow constant folding with the template of the define_insn,
5642 ; then to have the insns split later (between sched1 and final).
5643
5644 (define_expand "floatsidf2"
5645 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5646 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5647 (use (match_dup 2))
5648 (use (match_dup 3))
5649 (clobber (match_dup 4))
5650 (clobber (match_dup 5))
5651 (clobber (match_dup 6))])]
5652 "TARGET_HARD_FLOAT && TARGET_FPRS"
5653 "
5654 {
5655 if (TARGET_E500_DOUBLE)
5656 {
5657 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5658 DONE;
5659 }
5660 if (TARGET_POWERPC64)
5661 {
5662 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5663 rtx t1 = gen_reg_rtx (DImode);
5664 rtx t2 = gen_reg_rtx (DImode);
5665 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5666 DONE;
5667 }
5668
5669 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5670 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5671 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5672 operands[5] = gen_reg_rtx (DFmode);
5673 operands[6] = gen_reg_rtx (SImode);
5674 }")
5675
5676 (define_insn_and_split "*floatsidf2_internal"
5677 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5678 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5679 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5680 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5681 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5682 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5683 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5684 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5685 "#"
5686 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5687 [(pc)]
5688 "
5689 {
5690 rtx lowword, highword;
5691 gcc_assert (MEM_P (operands[4]));
5692 highword = adjust_address (operands[4], SImode, 0);
5693 lowword = adjust_address (operands[4], SImode, 4);
5694 if (! WORDS_BIG_ENDIAN)
5695 {
5696 rtx tmp;
5697 tmp = highword; highword = lowword; lowword = tmp;
5698 }
5699
5700 emit_insn (gen_xorsi3 (operands[6], operands[1],
5701 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5702 emit_move_insn (lowword, operands[6]);
5703 emit_move_insn (highword, operands[2]);
5704 emit_move_insn (operands[5], operands[4]);
5705 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5706 DONE;
5707 }"
5708 [(set_attr "length" "24")])
5709
5710 (define_expand "floatunssisf2"
5711 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5712 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5713 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5714 "")
5715
5716 (define_expand "floatunssidf2"
5717 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5718 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5719 (use (match_dup 2))
5720 (use (match_dup 3))
5721 (clobber (match_dup 4))
5722 (clobber (match_dup 5))])]
5723 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5724 "
5725 {
5726 if (TARGET_E500_DOUBLE)
5727 {
5728 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5729 DONE;
5730 }
5731 if (TARGET_POWERPC64)
5732 {
5733 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5734 rtx t1 = gen_reg_rtx (DImode);
5735 rtx t2 = gen_reg_rtx (DImode);
5736 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5737 t1, t2));
5738 DONE;
5739 }
5740
5741 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5742 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5743 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5744 operands[5] = gen_reg_rtx (DFmode);
5745 }")
5746
5747 (define_insn_and_split "*floatunssidf2_internal"
5748 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5749 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5750 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5751 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5752 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5753 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5754 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5755 "#"
5756 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5757 [(pc)]
5758 "
5759 {
5760 rtx lowword, highword;
5761 gcc_assert (MEM_P (operands[4]));
5762 highword = adjust_address (operands[4], SImode, 0);
5763 lowword = adjust_address (operands[4], SImode, 4);
5764 if (! WORDS_BIG_ENDIAN)
5765 {
5766 rtx tmp;
5767 tmp = highword; highword = lowword; lowword = tmp;
5768 }
5769
5770 emit_move_insn (lowword, operands[1]);
5771 emit_move_insn (highword, operands[2]);
5772 emit_move_insn (operands[5], operands[4]);
5773 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5774 DONE;
5775 }"
5776 [(set_attr "length" "20")])
5777
5778 (define_expand "fix_truncdfsi2"
5779 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
5780 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5781 (clobber (match_dup 2))
5782 (clobber (match_dup 3))])]
5783 "(TARGET_POWER2 || TARGET_POWERPC)
5784 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5785 "
5786 {
5787 if (TARGET_E500_DOUBLE)
5788 {
5789 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5790 DONE;
5791 }
5792 operands[2] = gen_reg_rtx (DImode);
5793 if (TARGET_PPC_GFXOPT)
5794 {
5795 rtx orig_dest = operands[0];
5796 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
5797 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5798 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5799 operands[2]));
5800 if (operands[0] != orig_dest)
5801 emit_move_insn (orig_dest, operands[0]);
5802 DONE;
5803 }
5804 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5805 }")
5806
5807 (define_insn_and_split "*fix_truncdfsi2_internal"
5808 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5809 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5810 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5811 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5812 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5813 "#"
5814 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[3]))"
5815 [(pc)]
5816 "
5817 {
5818 rtx lowword;
5819 gcc_assert (MEM_P (operands[3]));
5820 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5821
5822 emit_insn (gen_fctiwz (operands[2], operands[1]));
5823 emit_move_insn (operands[3], operands[2]);
5824 emit_move_insn (operands[0], lowword);
5825 DONE;
5826 }"
5827 [(set_attr "length" "16")])
5828
5829 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
5830 [(set (match_operand:SI 0 "memory_operand" "=Z")
5831 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5832 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
5833 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
5834 && TARGET_PPC_GFXOPT"
5835 "#"
5836 "&& 1"
5837 [(pc)]
5838 "
5839 {
5840 emit_insn (gen_fctiwz (operands[2], operands[1]));
5841 emit_insn (gen_stfiwx (operands[0], operands[2]));
5842 DONE;
5843 }"
5844 [(set_attr "length" "16")])
5845
5846 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5847 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5848 ; because the first makes it clear that operand 0 is not live
5849 ; before the instruction.
5850 (define_insn "fctiwz"
5851 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
5852 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5853 UNSPEC_FCTIWZ))]
5854 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5855 "{fcirz|fctiwz} %0,%1"
5856 [(set_attr "type" "fp")])
5857
5858 (define_insn "btruncdf2"
5859 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5860 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
5861 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5862 "friz %0,%1"
5863 [(set_attr "type" "fp")])
5864
5865 (define_insn "btruncsf2"
5866 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5867 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
5868 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5869 "friz %0,%1"
5870 [(set_attr "type" "fp")])
5871
5872 (define_insn "ceildf2"
5873 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5874 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
5875 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5876 "frip %0,%1"
5877 [(set_attr "type" "fp")])
5878
5879 (define_insn "ceilsf2"
5880 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5881 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
5882 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5883 "frip %0,%1"
5884 [(set_attr "type" "fp")])
5885
5886 (define_insn "floordf2"
5887 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5888 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
5889 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5890 "frim %0,%1"
5891 [(set_attr "type" "fp")])
5892
5893 (define_insn "floorsf2"
5894 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5895 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
5896 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5897 "frim %0,%1"
5898 [(set_attr "type" "fp")])
5899
5900 (define_insn "rounddf2"
5901 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5902 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
5903 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5904 "frin %0,%1"
5905 [(set_attr "type" "fp")])
5906
5907 (define_insn "roundsf2"
5908 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5909 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
5910 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5911 "frin %0,%1"
5912 [(set_attr "type" "fp")])
5913
5914 ; An UNSPEC is used so we don't have to support SImode in FP registers.
5915 (define_insn "stfiwx"
5916 [(set (match_operand:SI 0 "memory_operand" "=Z")
5917 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
5918 UNSPEC_STFIWX))]
5919 "TARGET_PPC_GFXOPT"
5920 "stfiwx %1,%y0"
5921 [(set_attr "type" "fpstore")])
5922
5923 (define_expand "floatsisf2"
5924 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5925 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5926 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5927 "")
5928
5929 (define_insn "floatdidf2"
5930 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5931 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
5932 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5933 "fcfid %0,%1"
5934 [(set_attr "type" "fp")])
5935
5936 (define_insn_and_split "floatsidf_ppc64"
5937 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5938 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5939 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5940 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5941 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5942 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5943 "#"
5944 "&& 1"
5945 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5946 (set (match_dup 2) (match_dup 3))
5947 (set (match_dup 4) (match_dup 2))
5948 (set (match_dup 0) (float:DF (match_dup 4)))]
5949 "")
5950
5951 (define_insn_and_split "floatunssidf_ppc64"
5952 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5953 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5954 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5955 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5956 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5957 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5958 "#"
5959 "&& 1"
5960 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5961 (set (match_dup 2) (match_dup 3))
5962 (set (match_dup 4) (match_dup 2))
5963 (set (match_dup 0) (float:DF (match_dup 4)))]
5964 "")
5965
5966 (define_insn "fix_truncdfdi2"
5967 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5968 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5969 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5970 "fctidz %0,%1"
5971 [(set_attr "type" "fp")])
5972
5973 (define_expand "floatdisf2"
5974 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5975 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5976 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5977 "
5978 {
5979 rtx val = operands[1];
5980 if (!flag_unsafe_math_optimizations)
5981 {
5982 rtx label = gen_label_rtx ();
5983 val = gen_reg_rtx (DImode);
5984 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
5985 emit_label (label);
5986 }
5987 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
5988 DONE;
5989 }")
5990
5991 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5992 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5993 ;; from double rounding.
5994 (define_insn_and_split "floatdisf2_internal1"
5995 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5996 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
5997 (clobber (match_scratch:DF 2 "=f"))]
5998 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5999 "#"
6000 "&& reload_completed"
6001 [(set (match_dup 2)
6002 (float:DF (match_dup 1)))
6003 (set (match_dup 0)
6004 (float_truncate:SF (match_dup 2)))]
6005 "")
6006
6007 ;; Twiddles bits to avoid double rounding.
6008 ;; Bits that might be truncated when converting to DFmode are replaced
6009 ;; by a bit that won't be lost at that stage, but is below the SFmode
6010 ;; rounding position.
6011 (define_expand "floatdisf2_internal2"
6012 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6013 (const_int 53)))
6014 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6015 (const_int 2047)))
6016 (clobber (scratch:CC))])
6017 (set (match_dup 3) (plus:DI (match_dup 3)
6018 (const_int 1)))
6019 (set (match_dup 0) (plus:DI (match_dup 0)
6020 (const_int 2047)))
6021 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6022 (const_int 2)))
6023 (set (match_dup 0) (ior:DI (match_dup 0)
6024 (match_dup 1)))
6025 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6026 (const_int -2048)))
6027 (clobber (scratch:CC))])
6028 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6029 (label_ref (match_operand:DI 2 "" ""))
6030 (pc)))
6031 (set (match_dup 0) (match_dup 1))]
6032 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6033 "
6034 {
6035 operands[3] = gen_reg_rtx (DImode);
6036 operands[4] = gen_reg_rtx (CCUNSmode);
6037 }")
6038 \f
6039 ;; Define the DImode operations that can be done in a small number
6040 ;; of instructions. The & constraints are to prevent the register
6041 ;; allocator from allocating registers that overlap with the inputs
6042 ;; (for example, having an input in 7,8 and an output in 6,7). We
6043 ;; also allow for the output being the same as one of the inputs.
6044
6045 (define_insn "*adddi3_noppc64"
6046 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6047 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6048 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6049 "! TARGET_POWERPC64"
6050 "*
6051 {
6052 if (WORDS_BIG_ENDIAN)
6053 return (GET_CODE (operands[2])) != CONST_INT
6054 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6055 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6056 else
6057 return (GET_CODE (operands[2])) != CONST_INT
6058 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6059 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6060 }"
6061 [(set_attr "type" "two")
6062 (set_attr "length" "8")])
6063
6064 (define_insn "*subdi3_noppc64"
6065 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6066 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6067 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6068 "! TARGET_POWERPC64"
6069 "*
6070 {
6071 if (WORDS_BIG_ENDIAN)
6072 return (GET_CODE (operands[1]) != CONST_INT)
6073 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6074 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6075 else
6076 return (GET_CODE (operands[1]) != CONST_INT)
6077 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6078 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
6079 }"
6080 [(set_attr "type" "two")
6081 (set_attr "length" "8")])
6082
6083 (define_insn "*negdi2_noppc64"
6084 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6085 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6086 "! TARGET_POWERPC64"
6087 "*
6088 {
6089 return (WORDS_BIG_ENDIAN)
6090 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6091 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6092 }"
6093 [(set_attr "type" "two")
6094 (set_attr "length" "8")])
6095
6096 (define_expand "mulsidi3"
6097 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6098 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6099 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6100 "! TARGET_POWERPC64"
6101 "
6102 {
6103 if (! TARGET_POWER && ! TARGET_POWERPC)
6104 {
6105 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6106 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6107 emit_insn (gen_mull_call ());
6108 if (WORDS_BIG_ENDIAN)
6109 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
6110 else
6111 {
6112 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
6113 gen_rtx_REG (SImode, 3));
6114 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
6115 gen_rtx_REG (SImode, 4));
6116 }
6117 DONE;
6118 }
6119 else if (TARGET_POWER)
6120 {
6121 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6122 DONE;
6123 }
6124 }")
6125
6126 (define_insn "mulsidi3_mq"
6127 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6128 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6129 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6130 (clobber (match_scratch:SI 3 "=q"))]
6131 "TARGET_POWER"
6132 "mul %0,%1,%2\;mfmq %L0"
6133 [(set_attr "type" "imul")
6134 (set_attr "length" "8")])
6135
6136 (define_insn "*mulsidi3_no_mq"
6137 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6138 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6139 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6140 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6141 "*
6142 {
6143 return (WORDS_BIG_ENDIAN)
6144 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6145 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6146 }"
6147 [(set_attr "type" "imul")
6148 (set_attr "length" "8")])
6149
6150 (define_split
6151 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6152 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6153 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6154 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6155 [(set (match_dup 3)
6156 (truncate:SI
6157 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6158 (sign_extend:DI (match_dup 2)))
6159 (const_int 32))))
6160 (set (match_dup 4)
6161 (mult:SI (match_dup 1)
6162 (match_dup 2)))]
6163 "
6164 {
6165 int endian = (WORDS_BIG_ENDIAN == 0);
6166 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6167 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6168 }")
6169
6170 (define_expand "umulsidi3"
6171 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6172 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6173 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6174 "TARGET_POWERPC && ! TARGET_POWERPC64"
6175 "
6176 {
6177 if (TARGET_POWER)
6178 {
6179 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6180 DONE;
6181 }
6182 }")
6183
6184 (define_insn "umulsidi3_mq"
6185 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6186 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6187 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6188 (clobber (match_scratch:SI 3 "=q"))]
6189 "TARGET_POWERPC && TARGET_POWER"
6190 "*
6191 {
6192 return (WORDS_BIG_ENDIAN)
6193 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6194 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6195 }"
6196 [(set_attr "type" "imul")
6197 (set_attr "length" "8")])
6198
6199 (define_insn "*umulsidi3_no_mq"
6200 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6201 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6202 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6203 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6204 "*
6205 {
6206 return (WORDS_BIG_ENDIAN)
6207 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6208 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6209 }"
6210 [(set_attr "type" "imul")
6211 (set_attr "length" "8")])
6212
6213 (define_split
6214 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6215 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6216 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6217 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6218 [(set (match_dup 3)
6219 (truncate:SI
6220 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6221 (zero_extend:DI (match_dup 2)))
6222 (const_int 32))))
6223 (set (match_dup 4)
6224 (mult:SI (match_dup 1)
6225 (match_dup 2)))]
6226 "
6227 {
6228 int endian = (WORDS_BIG_ENDIAN == 0);
6229 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6230 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6231 }")
6232
6233 (define_expand "smulsi3_highpart"
6234 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6235 (truncate:SI
6236 (lshiftrt:DI (mult:DI (sign_extend:DI
6237 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6238 (sign_extend:DI
6239 (match_operand:SI 2 "gpc_reg_operand" "r")))
6240 (const_int 32))))]
6241 ""
6242 "
6243 {
6244 if (! TARGET_POWER && ! TARGET_POWERPC)
6245 {
6246 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6247 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6248 emit_insn (gen_mulh_call ());
6249 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
6250 DONE;
6251 }
6252 else if (TARGET_POWER)
6253 {
6254 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6255 DONE;
6256 }
6257 }")
6258
6259 (define_insn "smulsi3_highpart_mq"
6260 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6261 (truncate:SI
6262 (lshiftrt:DI (mult:DI (sign_extend:DI
6263 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6264 (sign_extend:DI
6265 (match_operand:SI 2 "gpc_reg_operand" "r")))
6266 (const_int 32))))
6267 (clobber (match_scratch:SI 3 "=q"))]
6268 "TARGET_POWER"
6269 "mul %0,%1,%2"
6270 [(set_attr "type" "imul")])
6271
6272 (define_insn "*smulsi3_highpart_no_mq"
6273 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6274 (truncate:SI
6275 (lshiftrt:DI (mult:DI (sign_extend:DI
6276 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6277 (sign_extend:DI
6278 (match_operand:SI 2 "gpc_reg_operand" "r")))
6279 (const_int 32))))]
6280 "TARGET_POWERPC && ! TARGET_POWER"
6281 "mulhw %0,%1,%2"
6282 [(set_attr "type" "imul")])
6283
6284 (define_expand "umulsi3_highpart"
6285 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6286 (truncate:SI
6287 (lshiftrt:DI (mult:DI (zero_extend:DI
6288 (match_operand:SI 1 "gpc_reg_operand" ""))
6289 (zero_extend:DI
6290 (match_operand:SI 2 "gpc_reg_operand" "")))
6291 (const_int 32))))]
6292 "TARGET_POWERPC"
6293 "
6294 {
6295 if (TARGET_POWER)
6296 {
6297 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6298 DONE;
6299 }
6300 }")
6301
6302 (define_insn "umulsi3_highpart_mq"
6303 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6304 (truncate:SI
6305 (lshiftrt:DI (mult:DI (zero_extend:DI
6306 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6307 (zero_extend:DI
6308 (match_operand:SI 2 "gpc_reg_operand" "r")))
6309 (const_int 32))))
6310 (clobber (match_scratch:SI 3 "=q"))]
6311 "TARGET_POWERPC && TARGET_POWER"
6312 "mulhwu %0,%1,%2"
6313 [(set_attr "type" "imul")])
6314
6315 (define_insn "*umulsi3_highpart_no_mq"
6316 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6317 (truncate:SI
6318 (lshiftrt:DI (mult:DI (zero_extend:DI
6319 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6320 (zero_extend:DI
6321 (match_operand:SI 2 "gpc_reg_operand" "r")))
6322 (const_int 32))))]
6323 "TARGET_POWERPC && ! TARGET_POWER"
6324 "mulhwu %0,%1,%2"
6325 [(set_attr "type" "imul")])
6326
6327 ;; If operands 0 and 2 are in the same register, we have a problem. But
6328 ;; operands 0 and 1 (the usual case) can be in the same register. That's
6329 ;; why we have the strange constraints below.
6330 (define_insn "ashldi3_power"
6331 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6332 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6333 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6334 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6335 "TARGET_POWER"
6336 "@
6337 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
6338 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6339 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6340 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
6341 [(set_attr "length" "8")])
6342
6343 (define_insn "lshrdi3_power"
6344 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6345 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6346 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6347 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6348 "TARGET_POWER"
6349 "@
6350 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
6351 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6352 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6353 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
6354 [(set_attr "length" "8")])
6355
6356 ;; Shift by a variable amount is too complex to be worth open-coding. We
6357 ;; just handle shifts by constants.
6358 (define_insn "ashrdi3_power"
6359 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6360 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6361 (match_operand:SI 2 "const_int_operand" "M,i")))
6362 (clobber (match_scratch:SI 3 "=X,q"))]
6363 "TARGET_POWER"
6364 "@
6365 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6366 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
6367 [(set_attr "length" "8")])
6368
6369 (define_insn "ashrdi3_no_power"
6370 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6371 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6372 (match_operand:SI 2 "const_int_operand" "M,i")))]
6373 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
6374 "@
6375 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6376 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
6377 [(set_attr "type" "two,three")
6378 (set_attr "length" "8,12")])
6379
6380 (define_insn "*ashrdisi3_noppc64"
6381 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6382 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6383 (const_int 32)) 4))]
6384 "TARGET_32BIT && !TARGET_POWERPC64"
6385 "*
6386 {
6387 if (REGNO (operands[0]) == REGNO (operands[1]))
6388 return \"\";
6389 else
6390 return \"mr %0,%1\";
6391 }"
6392 [(set_attr "length" "4")])
6393
6394 \f
6395 ;; PowerPC64 DImode operations.
6396
6397 (define_insn_and_split "absdi2"
6398 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6399 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6400 (clobber (match_scratch:DI 2 "=&r,&r"))]
6401 "TARGET_POWERPC64"
6402 "#"
6403 "&& reload_completed"
6404 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6405 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6406 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6407 "")
6408
6409 (define_insn_and_split "*nabsdi2"
6410 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6411 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6412 (clobber (match_scratch:DI 2 "=&r,&r"))]
6413 "TARGET_POWERPC64"
6414 "#"
6415 "&& reload_completed"
6416 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6417 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6418 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
6419 "")
6420
6421 (define_insn "muldi3"
6422 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6423 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6424 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6425 "TARGET_POWERPC64"
6426 "@
6427 mulld %0,%1,%2
6428 mulli %0,%1,%2"
6429 [(set (attr "type")
6430 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6431 (const_string "imul3")
6432 (match_operand:SI 2 "short_cint_operand" "")
6433 (const_string "imul2")]
6434 (const_string "lmul")))])
6435
6436 (define_insn "*muldi3_internal1"
6437 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6438 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6439 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6440 (const_int 0)))
6441 (clobber (match_scratch:DI 3 "=r,r"))]
6442 "TARGET_POWERPC64"
6443 "@
6444 mulld. %3,%1,%2
6445 #"
6446 [(set_attr "type" "lmul_compare")
6447 (set_attr "length" "4,8")])
6448
6449 (define_split
6450 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6451 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6452 (match_operand:DI 2 "gpc_reg_operand" ""))
6453 (const_int 0)))
6454 (clobber (match_scratch:DI 3 ""))]
6455 "TARGET_POWERPC64 && reload_completed"
6456 [(set (match_dup 3)
6457 (mult:DI (match_dup 1) (match_dup 2)))
6458 (set (match_dup 0)
6459 (compare:CC (match_dup 3)
6460 (const_int 0)))]
6461 "")
6462
6463 (define_insn "*muldi3_internal2"
6464 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6465 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6466 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6467 (const_int 0)))
6468 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6469 (mult:DI (match_dup 1) (match_dup 2)))]
6470 "TARGET_POWERPC64"
6471 "@
6472 mulld. %0,%1,%2
6473 #"
6474 [(set_attr "type" "lmul_compare")
6475 (set_attr "length" "4,8")])
6476
6477 (define_split
6478 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6479 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6480 (match_operand:DI 2 "gpc_reg_operand" ""))
6481 (const_int 0)))
6482 (set (match_operand:DI 0 "gpc_reg_operand" "")
6483 (mult:DI (match_dup 1) (match_dup 2)))]
6484 "TARGET_POWERPC64 && reload_completed"
6485 [(set (match_dup 0)
6486 (mult:DI (match_dup 1) (match_dup 2)))
6487 (set (match_dup 3)
6488 (compare:CC (match_dup 0)
6489 (const_int 0)))]
6490 "")
6491
6492 (define_insn "smuldi3_highpart"
6493 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6494 (truncate:DI
6495 (lshiftrt:TI (mult:TI (sign_extend:TI
6496 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6497 (sign_extend:TI
6498 (match_operand:DI 2 "gpc_reg_operand" "r")))
6499 (const_int 64))))]
6500 "TARGET_POWERPC64"
6501 "mulhd %0,%1,%2"
6502 [(set_attr "type" "lmul")])
6503
6504 (define_insn "umuldi3_highpart"
6505 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6506 (truncate:DI
6507 (lshiftrt:TI (mult:TI (zero_extend:TI
6508 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6509 (zero_extend:TI
6510 (match_operand:DI 2 "gpc_reg_operand" "r")))
6511 (const_int 64))))]
6512 "TARGET_POWERPC64"
6513 "mulhdu %0,%1,%2"
6514 [(set_attr "type" "lmul")])
6515
6516 (define_insn "rotldi3"
6517 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6518 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6519 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6520 "TARGET_POWERPC64"
6521 "rld%I2cl %0,%1,%H2,0")
6522
6523 (define_insn "*rotldi3_internal2"
6524 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6525 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6526 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6527 (const_int 0)))
6528 (clobber (match_scratch:DI 3 "=r,r"))]
6529 "TARGET_64BIT"
6530 "@
6531 rld%I2cl. %3,%1,%H2,0
6532 #"
6533 [(set_attr "type" "delayed_compare")
6534 (set_attr "length" "4,8")])
6535
6536 (define_split
6537 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6538 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6539 (match_operand:DI 2 "reg_or_cint_operand" ""))
6540 (const_int 0)))
6541 (clobber (match_scratch:DI 3 ""))]
6542 "TARGET_POWERPC64 && reload_completed"
6543 [(set (match_dup 3)
6544 (rotate:DI (match_dup 1) (match_dup 2)))
6545 (set (match_dup 0)
6546 (compare:CC (match_dup 3)
6547 (const_int 0)))]
6548 "")
6549
6550 (define_insn "*rotldi3_internal3"
6551 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6552 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6553 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6554 (const_int 0)))
6555 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6556 (rotate:DI (match_dup 1) (match_dup 2)))]
6557 "TARGET_64BIT"
6558 "@
6559 rld%I2cl. %0,%1,%H2,0
6560 #"
6561 [(set_attr "type" "delayed_compare")
6562 (set_attr "length" "4,8")])
6563
6564 (define_split
6565 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6566 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6567 (match_operand:DI 2 "reg_or_cint_operand" ""))
6568 (const_int 0)))
6569 (set (match_operand:DI 0 "gpc_reg_operand" "")
6570 (rotate:DI (match_dup 1) (match_dup 2)))]
6571 "TARGET_POWERPC64 && reload_completed"
6572 [(set (match_dup 0)
6573 (rotate:DI (match_dup 1) (match_dup 2)))
6574 (set (match_dup 3)
6575 (compare:CC (match_dup 0)
6576 (const_int 0)))]
6577 "")
6578
6579 (define_insn "*rotldi3_internal4"
6580 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6581 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6582 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
6583 (match_operand:DI 3 "mask64_operand" "n")))]
6584 "TARGET_POWERPC64"
6585 "rld%I2c%B3 %0,%1,%H2,%S3")
6586
6587 (define_insn "*rotldi3_internal5"
6588 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6589 (compare:CC (and:DI
6590 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6591 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6592 (match_operand:DI 3 "mask64_operand" "n,n"))
6593 (const_int 0)))
6594 (clobber (match_scratch:DI 4 "=r,r"))]
6595 "TARGET_64BIT"
6596 "@
6597 rld%I2c%B3. %4,%1,%H2,%S3
6598 #"
6599 [(set_attr "type" "delayed_compare")
6600 (set_attr "length" "4,8")])
6601
6602 (define_split
6603 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6604 (compare:CC (and:DI
6605 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6606 (match_operand:DI 2 "reg_or_cint_operand" ""))
6607 (match_operand:DI 3 "mask64_operand" ""))
6608 (const_int 0)))
6609 (clobber (match_scratch:DI 4 ""))]
6610 "TARGET_POWERPC64 && reload_completed"
6611 [(set (match_dup 4)
6612 (and:DI (rotate:DI (match_dup 1)
6613 (match_dup 2))
6614 (match_dup 3)))
6615 (set (match_dup 0)
6616 (compare:CC (match_dup 4)
6617 (const_int 0)))]
6618 "")
6619
6620 (define_insn "*rotldi3_internal6"
6621 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6622 (compare:CC (and:DI
6623 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6624 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6625 (match_operand:DI 3 "mask64_operand" "n,n"))
6626 (const_int 0)))
6627 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6628 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6629 "TARGET_64BIT"
6630 "@
6631 rld%I2c%B3. %0,%1,%H2,%S3
6632 #"
6633 [(set_attr "type" "delayed_compare")
6634 (set_attr "length" "4,8")])
6635
6636 (define_split
6637 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6638 (compare:CC (and:DI
6639 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6640 (match_operand:DI 2 "reg_or_cint_operand" ""))
6641 (match_operand:DI 3 "mask64_operand" ""))
6642 (const_int 0)))
6643 (set (match_operand:DI 0 "gpc_reg_operand" "")
6644 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6645 "TARGET_POWERPC64 && reload_completed"
6646 [(set (match_dup 0)
6647 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6648 (set (match_dup 4)
6649 (compare:CC (match_dup 0)
6650 (const_int 0)))]
6651 "")
6652
6653 (define_insn "*rotldi3_internal7"
6654 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6655 (zero_extend:DI
6656 (subreg:QI
6657 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6658 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6659 "TARGET_POWERPC64"
6660 "rld%I2cl %0,%1,%H2,56")
6661
6662 (define_insn "*rotldi3_internal8"
6663 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6664 (compare:CC (zero_extend:DI
6665 (subreg:QI
6666 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6667 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6668 (const_int 0)))
6669 (clobber (match_scratch:DI 3 "=r,r"))]
6670 "TARGET_64BIT"
6671 "@
6672 rld%I2cl. %3,%1,%H2,56
6673 #"
6674 [(set_attr "type" "delayed_compare")
6675 (set_attr "length" "4,8")])
6676
6677 (define_split
6678 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6679 (compare:CC (zero_extend:DI
6680 (subreg:QI
6681 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6682 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6683 (const_int 0)))
6684 (clobber (match_scratch:DI 3 ""))]
6685 "TARGET_POWERPC64 && reload_completed"
6686 [(set (match_dup 3)
6687 (zero_extend:DI (subreg:QI
6688 (rotate:DI (match_dup 1)
6689 (match_dup 2)) 0)))
6690 (set (match_dup 0)
6691 (compare:CC (match_dup 3)
6692 (const_int 0)))]
6693 "")
6694
6695 (define_insn "*rotldi3_internal9"
6696 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6697 (compare:CC (zero_extend:DI
6698 (subreg:QI
6699 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6700 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6701 (const_int 0)))
6702 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6703 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6704 "TARGET_64BIT"
6705 "@
6706 rld%I2cl. %0,%1,%H2,56
6707 #"
6708 [(set_attr "type" "delayed_compare")
6709 (set_attr "length" "4,8")])
6710
6711 (define_split
6712 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6713 (compare:CC (zero_extend:DI
6714 (subreg:QI
6715 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6716 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6717 (const_int 0)))
6718 (set (match_operand:DI 0 "gpc_reg_operand" "")
6719 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6720 "TARGET_POWERPC64 && reload_completed"
6721 [(set (match_dup 0)
6722 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6723 (set (match_dup 3)
6724 (compare:CC (match_dup 0)
6725 (const_int 0)))]
6726 "")
6727
6728 (define_insn "*rotldi3_internal10"
6729 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6730 (zero_extend:DI
6731 (subreg:HI
6732 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6733 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6734 "TARGET_POWERPC64"
6735 "rld%I2cl %0,%1,%H2,48")
6736
6737 (define_insn "*rotldi3_internal11"
6738 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6739 (compare:CC (zero_extend:DI
6740 (subreg:HI
6741 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6742 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6743 (const_int 0)))
6744 (clobber (match_scratch:DI 3 "=r,r"))]
6745 "TARGET_64BIT"
6746 "@
6747 rld%I2cl. %3,%1,%H2,48
6748 #"
6749 [(set_attr "type" "delayed_compare")
6750 (set_attr "length" "4,8")])
6751
6752 (define_split
6753 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6754 (compare:CC (zero_extend:DI
6755 (subreg:HI
6756 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6757 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6758 (const_int 0)))
6759 (clobber (match_scratch:DI 3 ""))]
6760 "TARGET_POWERPC64 && reload_completed"
6761 [(set (match_dup 3)
6762 (zero_extend:DI (subreg:HI
6763 (rotate:DI (match_dup 1)
6764 (match_dup 2)) 0)))
6765 (set (match_dup 0)
6766 (compare:CC (match_dup 3)
6767 (const_int 0)))]
6768 "")
6769
6770 (define_insn "*rotldi3_internal12"
6771 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6772 (compare:CC (zero_extend:DI
6773 (subreg:HI
6774 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6775 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6776 (const_int 0)))
6777 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6778 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6779 "TARGET_64BIT"
6780 "@
6781 rld%I2cl. %0,%1,%H2,48
6782 #"
6783 [(set_attr "type" "delayed_compare")
6784 (set_attr "length" "4,8")])
6785
6786 (define_split
6787 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6788 (compare:CC (zero_extend:DI
6789 (subreg:HI
6790 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6791 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6792 (const_int 0)))
6793 (set (match_operand:DI 0 "gpc_reg_operand" "")
6794 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6795 "TARGET_POWERPC64 && reload_completed"
6796 [(set (match_dup 0)
6797 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6798 (set (match_dup 3)
6799 (compare:CC (match_dup 0)
6800 (const_int 0)))]
6801 "")
6802
6803 (define_insn "*rotldi3_internal13"
6804 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6805 (zero_extend:DI
6806 (subreg:SI
6807 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6808 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6809 "TARGET_POWERPC64"
6810 "rld%I2cl %0,%1,%H2,32")
6811
6812 (define_insn "*rotldi3_internal14"
6813 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6814 (compare:CC (zero_extend:DI
6815 (subreg:SI
6816 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6817 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6818 (const_int 0)))
6819 (clobber (match_scratch:DI 3 "=r,r"))]
6820 "TARGET_64BIT"
6821 "@
6822 rld%I2cl. %3,%1,%H2,32
6823 #"
6824 [(set_attr "type" "delayed_compare")
6825 (set_attr "length" "4,8")])
6826
6827 (define_split
6828 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6829 (compare:CC (zero_extend:DI
6830 (subreg:SI
6831 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6832 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6833 (const_int 0)))
6834 (clobber (match_scratch:DI 3 ""))]
6835 "TARGET_POWERPC64 && reload_completed"
6836 [(set (match_dup 3)
6837 (zero_extend:DI (subreg:SI
6838 (rotate:DI (match_dup 1)
6839 (match_dup 2)) 0)))
6840 (set (match_dup 0)
6841 (compare:CC (match_dup 3)
6842 (const_int 0)))]
6843 "")
6844
6845 (define_insn "*rotldi3_internal15"
6846 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6847 (compare:CC (zero_extend:DI
6848 (subreg:SI
6849 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6850 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6851 (const_int 0)))
6852 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6853 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6854 "TARGET_64BIT"
6855 "@
6856 rld%I2cl. %0,%1,%H2,32
6857 #"
6858 [(set_attr "type" "delayed_compare")
6859 (set_attr "length" "4,8")])
6860
6861 (define_split
6862 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6863 (compare:CC (zero_extend:DI
6864 (subreg:SI
6865 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6866 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6867 (const_int 0)))
6868 (set (match_operand:DI 0 "gpc_reg_operand" "")
6869 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6870 "TARGET_POWERPC64 && reload_completed"
6871 [(set (match_dup 0)
6872 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6873 (set (match_dup 3)
6874 (compare:CC (match_dup 0)
6875 (const_int 0)))]
6876 "")
6877
6878 (define_expand "ashldi3"
6879 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6880 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6881 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6882 "TARGET_POWERPC64 || TARGET_POWER"
6883 "
6884 {
6885 if (TARGET_POWERPC64)
6886 ;
6887 else if (TARGET_POWER)
6888 {
6889 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6890 DONE;
6891 }
6892 else
6893 FAIL;
6894 }")
6895
6896 (define_insn "*ashldi3_internal1"
6897 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6898 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6899 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6900 "TARGET_POWERPC64"
6901 "sld%I2 %0,%1,%H2")
6902
6903 (define_insn "*ashldi3_internal2"
6904 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6905 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6906 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6907 (const_int 0)))
6908 (clobber (match_scratch:DI 3 "=r,r"))]
6909 "TARGET_64BIT"
6910 "@
6911 sld%I2. %3,%1,%H2
6912 #"
6913 [(set_attr "type" "delayed_compare")
6914 (set_attr "length" "4,8")])
6915
6916 (define_split
6917 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6918 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6919 (match_operand:SI 2 "reg_or_cint_operand" ""))
6920 (const_int 0)))
6921 (clobber (match_scratch:DI 3 ""))]
6922 "TARGET_POWERPC64 && reload_completed"
6923 [(set (match_dup 3)
6924 (ashift:DI (match_dup 1) (match_dup 2)))
6925 (set (match_dup 0)
6926 (compare:CC (match_dup 3)
6927 (const_int 0)))]
6928 "")
6929
6930 (define_insn "*ashldi3_internal3"
6931 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6932 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6933 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6934 (const_int 0)))
6935 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6936 (ashift:DI (match_dup 1) (match_dup 2)))]
6937 "TARGET_64BIT"
6938 "@
6939 sld%I2. %0,%1,%H2
6940 #"
6941 [(set_attr "type" "delayed_compare")
6942 (set_attr "length" "4,8")])
6943
6944 (define_split
6945 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6946 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6947 (match_operand:SI 2 "reg_or_cint_operand" ""))
6948 (const_int 0)))
6949 (set (match_operand:DI 0 "gpc_reg_operand" "")
6950 (ashift:DI (match_dup 1) (match_dup 2)))]
6951 "TARGET_POWERPC64 && reload_completed"
6952 [(set (match_dup 0)
6953 (ashift:DI (match_dup 1) (match_dup 2)))
6954 (set (match_dup 3)
6955 (compare:CC (match_dup 0)
6956 (const_int 0)))]
6957 "")
6958
6959 (define_insn "*ashldi3_internal4"
6960 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6961 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6962 (match_operand:SI 2 "const_int_operand" "i"))
6963 (match_operand:DI 3 "const_int_operand" "n")))]
6964 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6965 "rldic %0,%1,%H2,%W3")
6966
6967 (define_insn "ashldi3_internal5"
6968 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6969 (compare:CC
6970 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6971 (match_operand:SI 2 "const_int_operand" "i,i"))
6972 (match_operand:DI 3 "const_int_operand" "n,n"))
6973 (const_int 0)))
6974 (clobber (match_scratch:DI 4 "=r,r"))]
6975 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6976 "@
6977 rldic. %4,%1,%H2,%W3
6978 #"
6979 [(set_attr "type" "compare")
6980 (set_attr "length" "4,8")])
6981
6982 (define_split
6983 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6984 (compare:CC
6985 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6986 (match_operand:SI 2 "const_int_operand" ""))
6987 (match_operand:DI 3 "const_int_operand" ""))
6988 (const_int 0)))
6989 (clobber (match_scratch:DI 4 ""))]
6990 "TARGET_POWERPC64 && reload_completed
6991 && includes_rldic_lshift_p (operands[2], operands[3])"
6992 [(set (match_dup 4)
6993 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6994 (match_dup 3)))
6995 (set (match_dup 0)
6996 (compare:CC (match_dup 4)
6997 (const_int 0)))]
6998 "")
6999
7000 (define_insn "*ashldi3_internal6"
7001 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7002 (compare:CC
7003 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7004 (match_operand:SI 2 "const_int_operand" "i,i"))
7005 (match_operand:DI 3 "const_int_operand" "n,n"))
7006 (const_int 0)))
7007 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7008 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7009 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7010 "@
7011 rldic. %0,%1,%H2,%W3
7012 #"
7013 [(set_attr "type" "compare")
7014 (set_attr "length" "4,8")])
7015
7016 (define_split
7017 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7018 (compare:CC
7019 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7020 (match_operand:SI 2 "const_int_operand" ""))
7021 (match_operand:DI 3 "const_int_operand" ""))
7022 (const_int 0)))
7023 (set (match_operand:DI 0 "gpc_reg_operand" "")
7024 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7025 "TARGET_POWERPC64 && reload_completed
7026 && includes_rldic_lshift_p (operands[2], operands[3])"
7027 [(set (match_dup 0)
7028 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7029 (match_dup 3)))
7030 (set (match_dup 4)
7031 (compare:CC (match_dup 0)
7032 (const_int 0)))]
7033 "")
7034
7035 (define_insn "*ashldi3_internal7"
7036 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7037 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7038 (match_operand:SI 2 "const_int_operand" "i"))
7039 (match_operand:DI 3 "mask64_operand" "n")))]
7040 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7041 "rldicr %0,%1,%H2,%S3")
7042
7043 (define_insn "ashldi3_internal8"
7044 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7045 (compare:CC
7046 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7047 (match_operand:SI 2 "const_int_operand" "i,i"))
7048 (match_operand:DI 3 "mask64_operand" "n,n"))
7049 (const_int 0)))
7050 (clobber (match_scratch:DI 4 "=r,r"))]
7051 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7052 "@
7053 rldicr. %4,%1,%H2,%S3
7054 #"
7055 [(set_attr "type" "compare")
7056 (set_attr "length" "4,8")])
7057
7058 (define_split
7059 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7060 (compare:CC
7061 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7062 (match_operand:SI 2 "const_int_operand" ""))
7063 (match_operand:DI 3 "mask64_operand" ""))
7064 (const_int 0)))
7065 (clobber (match_scratch:DI 4 ""))]
7066 "TARGET_POWERPC64 && reload_completed
7067 && includes_rldicr_lshift_p (operands[2], operands[3])"
7068 [(set (match_dup 4)
7069 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7070 (match_dup 3)))
7071 (set (match_dup 0)
7072 (compare:CC (match_dup 4)
7073 (const_int 0)))]
7074 "")
7075
7076 (define_insn "*ashldi3_internal9"
7077 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7078 (compare:CC
7079 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7080 (match_operand:SI 2 "const_int_operand" "i,i"))
7081 (match_operand:DI 3 "mask64_operand" "n,n"))
7082 (const_int 0)))
7083 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7084 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7085 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7086 "@
7087 rldicr. %0,%1,%H2,%S3
7088 #"
7089 [(set_attr "type" "compare")
7090 (set_attr "length" "4,8")])
7091
7092 (define_split
7093 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7094 (compare:CC
7095 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7096 (match_operand:SI 2 "const_int_operand" ""))
7097 (match_operand:DI 3 "mask64_operand" ""))
7098 (const_int 0)))
7099 (set (match_operand:DI 0 "gpc_reg_operand" "")
7100 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7101 "TARGET_POWERPC64 && reload_completed
7102 && includes_rldicr_lshift_p (operands[2], operands[3])"
7103 [(set (match_dup 0)
7104 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7105 (match_dup 3)))
7106 (set (match_dup 4)
7107 (compare:CC (match_dup 0)
7108 (const_int 0)))]
7109 "")
7110
7111 (define_expand "lshrdi3"
7112 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7113 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7114 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7115 "TARGET_POWERPC64 || TARGET_POWER"
7116 "
7117 {
7118 if (TARGET_POWERPC64)
7119 ;
7120 else if (TARGET_POWER)
7121 {
7122 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7123 DONE;
7124 }
7125 else
7126 FAIL;
7127 }")
7128
7129 (define_insn "*lshrdi3_internal1"
7130 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7131 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7132 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
7133 "TARGET_POWERPC64"
7134 "srd%I2 %0,%1,%H2")
7135
7136 (define_insn "*lshrdi3_internal2"
7137 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7138 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7139 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7140 (const_int 0)))
7141 (clobber (match_scratch:DI 3 "=r,r"))]
7142 "TARGET_64BIT "
7143 "@
7144 srd%I2. %3,%1,%H2
7145 #"
7146 [(set_attr "type" "delayed_compare")
7147 (set_attr "length" "4,8")])
7148
7149 (define_split
7150 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7151 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7152 (match_operand:SI 2 "reg_or_cint_operand" ""))
7153 (const_int 0)))
7154 (clobber (match_scratch:DI 3 ""))]
7155 "TARGET_POWERPC64 && reload_completed"
7156 [(set (match_dup 3)
7157 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7158 (set (match_dup 0)
7159 (compare:CC (match_dup 3)
7160 (const_int 0)))]
7161 "")
7162
7163 (define_insn "*lshrdi3_internal3"
7164 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7165 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7166 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7167 (const_int 0)))
7168 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7169 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7170 "TARGET_64BIT"
7171 "@
7172 srd%I2. %0,%1,%H2
7173 #"
7174 [(set_attr "type" "delayed_compare")
7175 (set_attr "length" "4,8")])
7176
7177 (define_split
7178 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7179 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7180 (match_operand:SI 2 "reg_or_cint_operand" ""))
7181 (const_int 0)))
7182 (set (match_operand:DI 0 "gpc_reg_operand" "")
7183 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7184 "TARGET_POWERPC64 && reload_completed"
7185 [(set (match_dup 0)
7186 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7187 (set (match_dup 3)
7188 (compare:CC (match_dup 0)
7189 (const_int 0)))]
7190 "")
7191
7192 (define_expand "ashrdi3"
7193 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7194 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7195 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7196 "WORDS_BIG_ENDIAN"
7197 "
7198 {
7199 if (TARGET_POWERPC64)
7200 ;
7201 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7202 {
7203 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7204 DONE;
7205 }
7206 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7207 && WORDS_BIG_ENDIAN)
7208 {
7209 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7210 DONE;
7211 }
7212 else
7213 FAIL;
7214 }")
7215
7216 (define_insn "*ashrdi3_internal1"
7217 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7218 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7219 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
7220 "TARGET_POWERPC64"
7221 "srad%I2 %0,%1,%H2")
7222
7223 (define_insn "*ashrdi3_internal2"
7224 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7225 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7226 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7227 (const_int 0)))
7228 (clobber (match_scratch:DI 3 "=r,r"))]
7229 "TARGET_64BIT"
7230 "@
7231 srad%I2. %3,%1,%H2
7232 #"
7233 [(set_attr "type" "delayed_compare")
7234 (set_attr "length" "4,8")])
7235
7236 (define_split
7237 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7238 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7239 (match_operand:SI 2 "reg_or_cint_operand" ""))
7240 (const_int 0)))
7241 (clobber (match_scratch:DI 3 ""))]
7242 "TARGET_POWERPC64 && reload_completed"
7243 [(set (match_dup 3)
7244 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7245 (set (match_dup 0)
7246 (compare:CC (match_dup 3)
7247 (const_int 0)))]
7248 "")
7249
7250 (define_insn "*ashrdi3_internal3"
7251 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7252 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7253 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7254 (const_int 0)))
7255 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7256 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7257 "TARGET_64BIT"
7258 "@
7259 srad%I2. %0,%1,%H2
7260 #"
7261 [(set_attr "type" "delayed_compare")
7262 (set_attr "length" "4,8")])
7263
7264 (define_split
7265 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7266 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7267 (match_operand:SI 2 "reg_or_cint_operand" ""))
7268 (const_int 0)))
7269 (set (match_operand:DI 0 "gpc_reg_operand" "")
7270 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7271 "TARGET_POWERPC64 && reload_completed"
7272 [(set (match_dup 0)
7273 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7274 (set (match_dup 3)
7275 (compare:CC (match_dup 0)
7276 (const_int 0)))]
7277 "")
7278
7279 (define_insn "anddi3"
7280 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7281 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7282 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7283 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7284 "TARGET_POWERPC64"
7285 "@
7286 and %0,%1,%2
7287 rldic%B2 %0,%1,0,%S2
7288 rlwinm %0,%1,0,%m2,%M2
7289 andi. %0,%1,%b2
7290 andis. %0,%1,%u2
7291 #"
7292 [(set_attr "type" "*,*,*,compare,compare,*")
7293 (set_attr "length" "4,4,4,4,4,8")])
7294
7295 (define_split
7296 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7297 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7298 (match_operand:DI 2 "mask64_2_operand" "")))
7299 (clobber (match_scratch:CC 3 ""))]
7300 "TARGET_POWERPC64
7301 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7302 && !mask_operand (operands[2], DImode)
7303 && !mask64_operand (operands[2], DImode)"
7304 [(set (match_dup 0)
7305 (and:DI (rotate:DI (match_dup 1)
7306 (match_dup 4))
7307 (match_dup 5)))
7308 (set (match_dup 0)
7309 (and:DI (rotate:DI (match_dup 0)
7310 (match_dup 6))
7311 (match_dup 7)))]
7312 {
7313 build_mask64_2_operands (operands[2], &operands[4]);
7314 })
7315
7316 (define_insn "*anddi3_internal2"
7317 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7318 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7319 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7320 (const_int 0)))
7321 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7322 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7323 "TARGET_64BIT"
7324 "@
7325 and. %3,%1,%2
7326 rldic%B2. %3,%1,0,%S2
7327 rlwinm. %3,%1,0,%m2,%M2
7328 andi. %3,%1,%b2
7329 andis. %3,%1,%u2
7330 #
7331 #
7332 #
7333 #
7334 #
7335 #
7336 #"
7337 [(set_attr "type" "compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7338 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7339
7340 (define_split
7341 [(set (match_operand:CC 0 "cc_reg_operand" "")
7342 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7343 (match_operand:DI 2 "mask64_2_operand" ""))
7344 (const_int 0)))
7345 (clobber (match_scratch:DI 3 ""))
7346 (clobber (match_scratch:CC 4 ""))]
7347 "TARGET_64BIT && reload_completed
7348 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7349 && !mask_operand (operands[2], DImode)
7350 && !mask64_operand (operands[2], DImode)"
7351 [(set (match_dup 3)
7352 (and:DI (rotate:DI (match_dup 1)
7353 (match_dup 5))
7354 (match_dup 6)))
7355 (parallel [(set (match_dup 0)
7356 (compare:CC (and:DI (rotate:DI (match_dup 3)
7357 (match_dup 7))
7358 (match_dup 8))
7359 (const_int 0)))
7360 (clobber (match_dup 3))])]
7361 "
7362 {
7363 build_mask64_2_operands (operands[2], &operands[5]);
7364 }")
7365
7366 (define_insn "*anddi3_internal3"
7367 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7368 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7369 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7370 (const_int 0)))
7371 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
7372 (and:DI (match_dup 1) (match_dup 2)))
7373 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7374 "TARGET_64BIT"
7375 "@
7376 and. %0,%1,%2
7377 rldic%B2. %0,%1,0,%S2
7378 rlwinm. %0,%1,0,%m2,%M2
7379 andi. %0,%1,%b2
7380 andis. %0,%1,%u2
7381 #
7382 #
7383 #
7384 #
7385 #
7386 #
7387 #"
7388 [(set_attr "type" "compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7389 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7390
7391 (define_split
7392 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7393 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7394 (match_operand:DI 2 "and64_2_operand" ""))
7395 (const_int 0)))
7396 (set (match_operand:DI 0 "gpc_reg_operand" "")
7397 (and:DI (match_dup 1) (match_dup 2)))
7398 (clobber (match_scratch:CC 4 ""))]
7399 "TARGET_64BIT && reload_completed"
7400 [(parallel [(set (match_dup 0)
7401 (and:DI (match_dup 1) (match_dup 2)))
7402 (clobber (match_dup 4))])
7403 (set (match_dup 3)
7404 (compare:CC (match_dup 0)
7405 (const_int 0)))]
7406 "")
7407
7408 (define_split
7409 [(set (match_operand:CC 3 "cc_reg_operand" "")
7410 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7411 (match_operand:DI 2 "mask64_2_operand" ""))
7412 (const_int 0)))
7413 (set (match_operand:DI 0 "gpc_reg_operand" "")
7414 (and:DI (match_dup 1) (match_dup 2)))
7415 (clobber (match_scratch:CC 4 ""))]
7416 "TARGET_64BIT && reload_completed
7417 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7418 && !mask_operand (operands[2], DImode)
7419 && !mask64_operand (operands[2], DImode)"
7420 [(set (match_dup 0)
7421 (and:DI (rotate:DI (match_dup 1)
7422 (match_dup 5))
7423 (match_dup 6)))
7424 (parallel [(set (match_dup 3)
7425 (compare:CC (and:DI (rotate:DI (match_dup 0)
7426 (match_dup 7))
7427 (match_dup 8))
7428 (const_int 0)))
7429 (set (match_dup 0)
7430 (and:DI (rotate:DI (match_dup 0)
7431 (match_dup 7))
7432 (match_dup 8)))])]
7433 "
7434 {
7435 build_mask64_2_operands (operands[2], &operands[5]);
7436 }")
7437
7438 (define_expand "iordi3"
7439 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7440 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7441 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7442 "TARGET_POWERPC64"
7443 "
7444 {
7445 if (non_logical_cint_operand (operands[2], DImode))
7446 {
7447 HOST_WIDE_INT value;
7448 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7449 ? operands[0] : gen_reg_rtx (DImode));
7450
7451 if (GET_CODE (operands[2]) == CONST_INT)
7452 {
7453 value = INTVAL (operands[2]);
7454 emit_insn (gen_iordi3 (tmp, operands[1],
7455 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7456 }
7457 else
7458 {
7459 value = CONST_DOUBLE_LOW (operands[2]);
7460 emit_insn (gen_iordi3 (tmp, operands[1],
7461 immed_double_const (value
7462 & (~ (HOST_WIDE_INT) 0xffff),
7463 0, DImode)));
7464 }
7465
7466 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7467 DONE;
7468 }
7469 }")
7470
7471 (define_expand "xordi3"
7472 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7473 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7474 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7475 "TARGET_POWERPC64"
7476 "
7477 {
7478 if (non_logical_cint_operand (operands[2], DImode))
7479 {
7480 HOST_WIDE_INT value;
7481 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7482 ? operands[0] : gen_reg_rtx (DImode));
7483
7484 if (GET_CODE (operands[2]) == CONST_INT)
7485 {
7486 value = INTVAL (operands[2]);
7487 emit_insn (gen_xordi3 (tmp, operands[1],
7488 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7489 }
7490 else
7491 {
7492 value = CONST_DOUBLE_LOW (operands[2]);
7493 emit_insn (gen_xordi3 (tmp, operands[1],
7494 immed_double_const (value
7495 & (~ (HOST_WIDE_INT) 0xffff),
7496 0, DImode)));
7497 }
7498
7499 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7500 DONE;
7501 }
7502 }")
7503
7504 (define_insn "*booldi3_internal1"
7505 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7506 (match_operator:DI 3 "boolean_or_operator"
7507 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7508 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7509 "TARGET_POWERPC64"
7510 "@
7511 %q3 %0,%1,%2
7512 %q3i %0,%1,%b2
7513 %q3is %0,%1,%u2")
7514
7515 (define_insn "*booldi3_internal2"
7516 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7517 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7518 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7519 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7520 (const_int 0)))
7521 (clobber (match_scratch:DI 3 "=r,r"))]
7522 "TARGET_64BIT"
7523 "@
7524 %q4. %3,%1,%2
7525 #"
7526 [(set_attr "type" "compare")
7527 (set_attr "length" "4,8")])
7528
7529 (define_split
7530 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7531 (compare:CC (match_operator:DI 4 "boolean_operator"
7532 [(match_operand:DI 1 "gpc_reg_operand" "")
7533 (match_operand:DI 2 "gpc_reg_operand" "")])
7534 (const_int 0)))
7535 (clobber (match_scratch:DI 3 ""))]
7536 "TARGET_POWERPC64 && reload_completed"
7537 [(set (match_dup 3) (match_dup 4))
7538 (set (match_dup 0)
7539 (compare:CC (match_dup 3)
7540 (const_int 0)))]
7541 "")
7542
7543 (define_insn "*booldi3_internal3"
7544 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7545 (compare:CC (match_operator:DI 4 "boolean_operator"
7546 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7547 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7548 (const_int 0)))
7549 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7550 (match_dup 4))]
7551 "TARGET_64BIT"
7552 "@
7553 %q4. %0,%1,%2
7554 #"
7555 [(set_attr "type" "compare")
7556 (set_attr "length" "4,8")])
7557
7558 (define_split
7559 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7560 (compare:CC (match_operator:DI 4 "boolean_operator"
7561 [(match_operand:DI 1 "gpc_reg_operand" "")
7562 (match_operand:DI 2 "gpc_reg_operand" "")])
7563 (const_int 0)))
7564 (set (match_operand:DI 0 "gpc_reg_operand" "")
7565 (match_dup 4))]
7566 "TARGET_POWERPC64 && reload_completed"
7567 [(set (match_dup 0) (match_dup 4))
7568 (set (match_dup 3)
7569 (compare:CC (match_dup 0)
7570 (const_int 0)))]
7571 "")
7572
7573 ;; Split a logical operation that we can't do in one insn into two insns,
7574 ;; each of which does one 16-bit part. This is used by combine.
7575
7576 (define_split
7577 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7578 (match_operator:DI 3 "boolean_or_operator"
7579 [(match_operand:DI 1 "gpc_reg_operand" "")
7580 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7581 "TARGET_POWERPC64"
7582 [(set (match_dup 0) (match_dup 4))
7583 (set (match_dup 0) (match_dup 5))]
7584 "
7585 {
7586 rtx i3,i4;
7587
7588 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7589 {
7590 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7591 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7592 0, DImode);
7593 i4 = GEN_INT (value & 0xffff);
7594 }
7595 else
7596 {
7597 i3 = GEN_INT (INTVAL (operands[2])
7598 & (~ (HOST_WIDE_INT) 0xffff));
7599 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7600 }
7601 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7602 operands[1], i3);
7603 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7604 operands[0], i4);
7605 }")
7606
7607 (define_insn "*boolcdi3_internal1"
7608 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7609 (match_operator:DI 3 "boolean_operator"
7610 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7611 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7612 "TARGET_POWERPC64"
7613 "%q3 %0,%2,%1")
7614
7615 (define_insn "*boolcdi3_internal2"
7616 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7617 (compare:CC (match_operator:DI 4 "boolean_operator"
7618 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7619 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7620 (const_int 0)))
7621 (clobber (match_scratch:DI 3 "=r,r"))]
7622 "TARGET_64BIT"
7623 "@
7624 %q4. %3,%2,%1
7625 #"
7626 [(set_attr "type" "compare")
7627 (set_attr "length" "4,8")])
7628
7629 (define_split
7630 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7631 (compare:CC (match_operator:DI 4 "boolean_operator"
7632 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7633 (match_operand:DI 2 "gpc_reg_operand" "")])
7634 (const_int 0)))
7635 (clobber (match_scratch:DI 3 ""))]
7636 "TARGET_POWERPC64 && reload_completed"
7637 [(set (match_dup 3) (match_dup 4))
7638 (set (match_dup 0)
7639 (compare:CC (match_dup 3)
7640 (const_int 0)))]
7641 "")
7642
7643 (define_insn "*boolcdi3_internal3"
7644 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7645 (compare:CC (match_operator:DI 4 "boolean_operator"
7646 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7647 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7648 (const_int 0)))
7649 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7650 (match_dup 4))]
7651 "TARGET_64BIT"
7652 "@
7653 %q4. %0,%2,%1
7654 #"
7655 [(set_attr "type" "compare")
7656 (set_attr "length" "4,8")])
7657
7658 (define_split
7659 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7660 (compare:CC (match_operator:DI 4 "boolean_operator"
7661 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7662 (match_operand:DI 2 "gpc_reg_operand" "")])
7663 (const_int 0)))
7664 (set (match_operand:DI 0 "gpc_reg_operand" "")
7665 (match_dup 4))]
7666 "TARGET_POWERPC64 && reload_completed"
7667 [(set (match_dup 0) (match_dup 4))
7668 (set (match_dup 3)
7669 (compare:CC (match_dup 0)
7670 (const_int 0)))]
7671 "")
7672
7673 (define_insn "*boolccdi3_internal1"
7674 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7675 (match_operator:DI 3 "boolean_operator"
7676 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7677 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7678 "TARGET_POWERPC64"
7679 "%q3 %0,%1,%2")
7680
7681 (define_insn "*boolccdi3_internal2"
7682 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7683 (compare:CC (match_operator:DI 4 "boolean_operator"
7684 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7685 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7686 (const_int 0)))
7687 (clobber (match_scratch:DI 3 "=r,r"))]
7688 "TARGET_64BIT"
7689 "@
7690 %q4. %3,%1,%2
7691 #"
7692 [(set_attr "type" "compare")
7693 (set_attr "length" "4,8")])
7694
7695 (define_split
7696 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7697 (compare:CC (match_operator:DI 4 "boolean_operator"
7698 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7699 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7700 (const_int 0)))
7701 (clobber (match_scratch:DI 3 ""))]
7702 "TARGET_POWERPC64 && reload_completed"
7703 [(set (match_dup 3) (match_dup 4))
7704 (set (match_dup 0)
7705 (compare:CC (match_dup 3)
7706 (const_int 0)))]
7707 "")
7708
7709 (define_insn "*boolccdi3_internal3"
7710 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7711 (compare:CC (match_operator:DI 4 "boolean_operator"
7712 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7713 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7714 (const_int 0)))
7715 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7716 (match_dup 4))]
7717 "TARGET_64BIT"
7718 "@
7719 %q4. %0,%1,%2
7720 #"
7721 [(set_attr "type" "compare")
7722 (set_attr "length" "4,8")])
7723
7724 (define_split
7725 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7726 (compare:CC (match_operator:DI 4 "boolean_operator"
7727 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7728 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7729 (const_int 0)))
7730 (set (match_operand:DI 0 "gpc_reg_operand" "")
7731 (match_dup 4))]
7732 "TARGET_POWERPC64 && reload_completed"
7733 [(set (match_dup 0) (match_dup 4))
7734 (set (match_dup 3)
7735 (compare:CC (match_dup 0)
7736 (const_int 0)))]
7737 "")
7738 \f
7739 ;; Now define ways of moving data around.
7740
7741 ;; Set up a register with a value from the GOT table
7742
7743 (define_expand "movsi_got"
7744 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7745 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7746 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7747 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7748 "
7749 {
7750 if (GET_CODE (operands[1]) == CONST)
7751 {
7752 rtx offset = const0_rtx;
7753 HOST_WIDE_INT value;
7754
7755 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7756 value = INTVAL (offset);
7757 if (value != 0)
7758 {
7759 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7760 emit_insn (gen_movsi_got (tmp, operands[1]));
7761 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7762 DONE;
7763 }
7764 }
7765
7766 operands[2] = rs6000_got_register (operands[1]);
7767 }")
7768
7769 (define_insn "*movsi_got_internal"
7770 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7771 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7772 (match_operand:SI 2 "gpc_reg_operand" "b")]
7773 UNSPEC_MOVSI_GOT))]
7774 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7775 "{l|lwz} %0,%a1@got(%2)"
7776 [(set_attr "type" "load")])
7777
7778 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7779 ;; didn't get allocated to a hard register.
7780 (define_split
7781 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7782 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7783 (match_operand:SI 2 "memory_operand" "")]
7784 UNSPEC_MOVSI_GOT))]
7785 "DEFAULT_ABI == ABI_V4
7786 && flag_pic == 1
7787 && (reload_in_progress || reload_completed)"
7788 [(set (match_dup 0) (match_dup 2))
7789 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7790 UNSPEC_MOVSI_GOT))]
7791 "")
7792
7793 ;; For SI, we special-case integers that can't be loaded in one insn. We
7794 ;; do the load 16-bits at a time. We could do this by loading from memory,
7795 ;; and this is even supposed to be faster, but it is simpler not to get
7796 ;; integers in the TOC.
7797 (define_insn "movsi_low"
7798 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7799 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7800 (match_operand 2 "" ""))))]
7801 "TARGET_MACHO && ! TARGET_64BIT"
7802 "{l|lwz} %0,lo16(%2)(%1)"
7803 [(set_attr "type" "load")
7804 (set_attr "length" "4")])
7805
7806 (define_insn "*movsi_internal1"
7807 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7808 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7809 "gpc_reg_operand (operands[0], SImode)
7810 || gpc_reg_operand (operands[1], SImode)"
7811 "@
7812 mr %0,%1
7813 {cal|la} %0,%a1
7814 {l%U1%X1|lwz%U1%X1} %0,%1
7815 {st%U0%X0|stw%U0%X0} %1,%0
7816 {lil|li} %0,%1
7817 {liu|lis} %0,%v1
7818 #
7819 {cal|la} %0,%a1
7820 mf%1 %0
7821 mt%0 %1
7822 mt%0 %1
7823 mt%0 %1
7824 {cror 0,0,0|nop}"
7825 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
7826 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7827
7828 ;; Split a load of a large constant into the appropriate two-insn
7829 ;; sequence.
7830
7831 (define_split
7832 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7833 (match_operand:SI 1 "const_int_operand" ""))]
7834 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7835 && (INTVAL (operands[1]) & 0xffff) != 0"
7836 [(set (match_dup 0)
7837 (match_dup 2))
7838 (set (match_dup 0)
7839 (ior:SI (match_dup 0)
7840 (match_dup 3)))]
7841 "
7842 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7843
7844 if (tem == operands[0])
7845 DONE;
7846 else
7847 FAIL;
7848 }")
7849
7850 (define_insn "*mov<mode>_internal2"
7851 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7852 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
7853 (const_int 0)))
7854 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7855 ""
7856 "@
7857 {cmpi|cmp<wd>i} %2,%0,0
7858 mr. %0,%1
7859 #"
7860 [(set_attr "type" "cmp,compare,cmp")
7861 (set_attr "length" "4,4,8")])
7862
7863 (define_split
7864 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7865 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
7866 (const_int 0)))
7867 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
7868 "reload_completed"
7869 [(set (match_dup 0) (match_dup 1))
7870 (set (match_dup 2)
7871 (compare:CC (match_dup 0)
7872 (const_int 0)))]
7873 "")
7874 \f
7875 (define_insn "*movhi_internal"
7876 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7877 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7878 "gpc_reg_operand (operands[0], HImode)
7879 || gpc_reg_operand (operands[1], HImode)"
7880 "@
7881 mr %0,%1
7882 lhz%U1%X1 %0,%1
7883 sth%U0%X0 %1,%0
7884 {lil|li} %0,%w1
7885 mf%1 %0
7886 mt%0 %1
7887 mt%0 %1
7888 {cror 0,0,0|nop}"
7889 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7890
7891 (define_expand "mov<mode>"
7892 [(set (match_operand:INT 0 "general_operand" "")
7893 (match_operand:INT 1 "any_operand" ""))]
7894 ""
7895 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7896
7897 (define_insn "*movqi_internal"
7898 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7899 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7900 "gpc_reg_operand (operands[0], QImode)
7901 || gpc_reg_operand (operands[1], QImode)"
7902 "@
7903 mr %0,%1
7904 lbz%U1%X1 %0,%1
7905 stb%U0%X0 %1,%0
7906 {lil|li} %0,%1
7907 mf%1 %0
7908 mt%0 %1
7909 mt%0 %1
7910 {cror 0,0,0|nop}"
7911 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7912 \f
7913 ;; Here is how to move condition codes around. When we store CC data in
7914 ;; an integer register or memory, we store just the high-order 4 bits.
7915 ;; This lets us not shift in the most common case of CR0.
7916 (define_expand "movcc"
7917 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7918 (match_operand:CC 1 "nonimmediate_operand" ""))]
7919 ""
7920 "")
7921
7922 (define_insn "*movcc_internal1"
7923 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m")
7924 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))]
7925 "register_operand (operands[0], CCmode)
7926 || register_operand (operands[1], CCmode)"
7927 "@
7928 mcrf %0,%1
7929 mtcrf 128,%1
7930 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7931 mfcr %0%Q1
7932 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7933 mr %0,%1
7934 mf%1 %0
7935 mt%0 %1
7936 mt%0 %1
7937 {l%U1%X1|lwz%U1%X1} %0,%1
7938 {st%U0%U1|stw%U0%U1} %1,%0"
7939 [(set (attr "type")
7940 (cond [(eq_attr "alternative" "0")
7941 (const_string "cr_logical")
7942 (eq_attr "alternative" "1,2")
7943 (const_string "mtcr")
7944 (eq_attr "alternative" "5,7")
7945 (const_string "integer")
7946 (eq_attr "alternative" "6")
7947 (const_string "mfjmpr")
7948 (eq_attr "alternative" "8")
7949 (const_string "mtjmpr")
7950 (eq_attr "alternative" "9")
7951 (const_string "load")
7952 (eq_attr "alternative" "10")
7953 (const_string "store")
7954 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
7955 (const_string "mfcrf")
7956 ]
7957 (const_string "mfcr")))
7958 (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
7959 \f
7960 ;; For floating-point, we normally deal with the floating-point registers
7961 ;; unless -msoft-float is used. The sole exception is that parameter passing
7962 ;; can produce floating-point values in fixed-point registers. Unless the
7963 ;; value is a simple constant or already in memory, we deal with this by
7964 ;; allocating memory and copying the value explicitly via that memory location.
7965 (define_expand "movsf"
7966 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7967 (match_operand:SF 1 "any_operand" ""))]
7968 ""
7969 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7970
7971 (define_split
7972 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7973 (match_operand:SF 1 "const_double_operand" ""))]
7974 "reload_completed
7975 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7976 || (GET_CODE (operands[0]) == SUBREG
7977 && GET_CODE (SUBREG_REG (operands[0])) == REG
7978 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7979 [(set (match_dup 2) (match_dup 3))]
7980 "
7981 {
7982 long l;
7983 REAL_VALUE_TYPE rv;
7984
7985 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7986 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7987
7988 if (! TARGET_POWERPC64)
7989 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7990 else
7991 operands[2] = gen_lowpart (SImode, operands[0]);
7992
7993 operands[3] = gen_int_mode (l, SImode);
7994 }")
7995
7996 (define_insn "*movsf_hardfloat"
7997 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
7998 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
7999 "(gpc_reg_operand (operands[0], SFmode)
8000 || gpc_reg_operand (operands[1], SFmode))
8001 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
8002 "@
8003 mr %0,%1
8004 {l%U1%X1|lwz%U1%X1} %0,%1
8005 {st%U0%X0|stw%U0%X0} %1,%0
8006 fmr %0,%1
8007 lfs%U1%X1 %0,%1
8008 stfs%U0%X0 %1,%0
8009 mt%0 %1
8010 mt%0 %1
8011 mf%1 %0
8012 {cror 0,0,0|nop}
8013 #
8014 #"
8015 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
8016 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
8017
8018 (define_insn "*movsf_softfloat"
8019 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
8020 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
8021 "(gpc_reg_operand (operands[0], SFmode)
8022 || gpc_reg_operand (operands[1], SFmode))
8023 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
8024 "@
8025 mr %0,%1
8026 mt%0 %1
8027 mt%0 %1
8028 mf%1 %0
8029 {l%U1%X1|lwz%U1%X1} %0,%1
8030 {st%U0%X0|stw%U0%X0} %1,%0
8031 {lil|li} %0,%1
8032 {liu|lis} %0,%v1
8033 {cal|la} %0,%a1
8034 #
8035 #
8036 {cror 0,0,0|nop}"
8037 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
8038 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
8039
8040 \f
8041 (define_expand "movdf"
8042 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8043 (match_operand:DF 1 "any_operand" ""))]
8044 ""
8045 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
8046
8047 (define_split
8048 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8049 (match_operand:DF 1 "const_int_operand" ""))]
8050 "! TARGET_POWERPC64 && reload_completed
8051 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8052 || (GET_CODE (operands[0]) == SUBREG
8053 && GET_CODE (SUBREG_REG (operands[0])) == REG
8054 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8055 [(set (match_dup 2) (match_dup 4))
8056 (set (match_dup 3) (match_dup 1))]
8057 "
8058 {
8059 int endian = (WORDS_BIG_ENDIAN == 0);
8060 HOST_WIDE_INT value = INTVAL (operands[1]);
8061
8062 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8063 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8064 #if HOST_BITS_PER_WIDE_INT == 32
8065 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8066 #else
8067 operands[4] = GEN_INT (value >> 32);
8068 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8069 #endif
8070 }")
8071
8072 (define_split
8073 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8074 (match_operand:DF 1 "const_double_operand" ""))]
8075 "! TARGET_POWERPC64 && reload_completed
8076 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8077 || (GET_CODE (operands[0]) == SUBREG
8078 && GET_CODE (SUBREG_REG (operands[0])) == REG
8079 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8080 [(set (match_dup 2) (match_dup 4))
8081 (set (match_dup 3) (match_dup 5))]
8082 "
8083 {
8084 int endian = (WORDS_BIG_ENDIAN == 0);
8085 long l[2];
8086 REAL_VALUE_TYPE rv;
8087
8088 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8089 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8090
8091 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8092 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8093 operands[4] = gen_int_mode (l[endian], SImode);
8094 operands[5] = gen_int_mode (l[1 - endian], SImode);
8095 }")
8096
8097 (define_split
8098 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8099 (match_operand:DF 1 "const_double_operand" ""))]
8100 "TARGET_POWERPC64 && reload_completed
8101 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8102 || (GET_CODE (operands[0]) == SUBREG
8103 && GET_CODE (SUBREG_REG (operands[0])) == REG
8104 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8105 [(set (match_dup 2) (match_dup 3))]
8106 "
8107 {
8108 int endian = (WORDS_BIG_ENDIAN == 0);
8109 long l[2];
8110 REAL_VALUE_TYPE rv;
8111 #if HOST_BITS_PER_WIDE_INT >= 64
8112 HOST_WIDE_INT val;
8113 #endif
8114
8115 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8116 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8117
8118 operands[2] = gen_lowpart (DImode, operands[0]);
8119 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8120 #if HOST_BITS_PER_WIDE_INT >= 64
8121 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8122 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8123
8124 operands[3] = gen_int_mode (val, DImode);
8125 #else
8126 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8127 #endif
8128 }")
8129
8130 ;; Don't have reload use general registers to load a constant. First,
8131 ;; it might not work if the output operand is the equivalent of
8132 ;; a non-offsettable memref, but also it is less efficient than loading
8133 ;; the constant into an FP register, since it will probably be used there.
8134 ;; The "??" is a kludge until we can figure out a more reasonable way
8135 ;; of handling these non-offsettable values.
8136 (define_insn "*movdf_hardfloat32"
8137 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8138 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
8139 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8140 && (gpc_reg_operand (operands[0], DFmode)
8141 || gpc_reg_operand (operands[1], DFmode))"
8142 "*
8143 {
8144 switch (which_alternative)
8145 {
8146 default:
8147 gcc_unreachable ();
8148 case 0:
8149 /* We normally copy the low-numbered register first. However, if
8150 the first register operand 0 is the same as the second register
8151 of operand 1, we must copy in the opposite order. */
8152 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8153 return \"mr %L0,%L1\;mr %0,%1\";
8154 else
8155 return \"mr %0,%1\;mr %L0,%L1\";
8156 case 1:
8157 if (GET_CODE (operands[1]) == MEM
8158 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[1], 0),
8159 reload_completed || reload_in_progress)
8160 || rs6000_legitimate_small_data_p (DFmode, XEXP (operands[1], 0))
8161 || GET_CODE (XEXP (operands[1], 0)) == REG
8162 || GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8163 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8164 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))
8165 {
8166 /* If the low-address word is used in the address, we must load
8167 it last. Otherwise, load it first. Note that we cannot have
8168 auto-increment in that case since the address register is
8169 known to be dead. */
8170 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8171 operands[1], 0))
8172 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8173 else
8174 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8175 }
8176 else
8177 {
8178 rtx addreg;
8179
8180 addreg = find_addr_reg (XEXP (operands[1], 0));
8181 if (refers_to_regno_p (REGNO (operands[0]),
8182 REGNO (operands[0]) + 1,
8183 operands[1], 0))
8184 {
8185 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8186 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8187 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8188 return \"{lx|lwzx} %0,%1\";
8189 }
8190 else
8191 {
8192 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
8193 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8194 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8195 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8196 return \"\";
8197 }
8198 }
8199 case 2:
8200 if (GET_CODE (operands[0]) == MEM
8201 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[0], 0),
8202 reload_completed || reload_in_progress)
8203 || rs6000_legitimate_small_data_p (DFmode, XEXP (operands[0], 0))
8204 || GET_CODE (XEXP (operands[0], 0)) == REG
8205 || GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8206 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8207 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))
8208 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8209 else
8210 {
8211 rtx addreg;
8212
8213 addreg = find_addr_reg (XEXP (operands[0], 0));
8214 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
8215 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8216 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
8217 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8218 return \"\";
8219 }
8220 case 3:
8221 return \"fmr %0,%1\";
8222 case 4:
8223 return \"lfd%U1%X1 %0,%1\";
8224 case 5:
8225 return \"stfd%U0%X0 %1,%0\";
8226 case 6:
8227 case 7:
8228 case 8:
8229 return \"#\";
8230 }
8231 }"
8232 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
8233 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
8234
8235 (define_insn "*movdf_softfloat32"
8236 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8237 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8238 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8239 && (gpc_reg_operand (operands[0], DFmode)
8240 || gpc_reg_operand (operands[1], DFmode))"
8241 "*
8242 {
8243 switch (which_alternative)
8244 {
8245 default:
8246 gcc_unreachable ();
8247 case 0:
8248 /* We normally copy the low-numbered register first. However, if
8249 the first register operand 0 is the same as the second register of
8250 operand 1, we must copy in the opposite order. */
8251 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8252 return \"mr %L0,%L1\;mr %0,%1\";
8253 else
8254 return \"mr %0,%1\;mr %L0,%L1\";
8255 case 1:
8256 /* If the low-address word is used in the address, we must load
8257 it last. Otherwise, load it first. Note that we cannot have
8258 auto-increment in that case since the address register is
8259 known to be dead. */
8260 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8261 operands[1], 0))
8262 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8263 else
8264 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8265 case 2:
8266 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8267 case 3:
8268 case 4:
8269 case 5:
8270 return \"#\";
8271 }
8272 }"
8273 [(set_attr "type" "two,load,store,*,*,*")
8274 (set_attr "length" "8,8,8,8,12,16")])
8275
8276 ; ld/std require word-aligned displacements -> 'Y' constraint.
8277 ; List Y->r and r->Y before r->r for reload.
8278 (define_insn "*movdf_hardfloat64"
8279 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
8280 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
8281 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8282 && (gpc_reg_operand (operands[0], DFmode)
8283 || gpc_reg_operand (operands[1], DFmode))"
8284 "@
8285 std%U0%X0 %1,%0
8286 ld%U1%X1 %0,%1
8287 mr %0,%1
8288 fmr %0,%1
8289 lfd%U1%X1 %0,%1
8290 stfd%U0%X0 %1,%0
8291 mt%0 %1
8292 mf%1 %0
8293 {cror 0,0,0|nop}
8294 #
8295 #
8296 #"
8297 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
8298 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
8299
8300 (define_insn "*movdf_softfloat64"
8301 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8302 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
8303 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8304 && (gpc_reg_operand (operands[0], DFmode)
8305 || gpc_reg_operand (operands[1], DFmode))"
8306 "@
8307 ld%U1%X1 %0,%1
8308 std%U0%X0 %1,%0
8309 mr %0,%1
8310 mt%0 %1
8311 mf%1 %0
8312 #
8313 #
8314 #
8315 {cror 0,0,0|nop}"
8316 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
8317 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8318 \f
8319 (define_expand "movtf"
8320 [(set (match_operand:TF 0 "general_operand" "")
8321 (match_operand:TF 1 "any_operand" ""))]
8322 "!TARGET_IEEEQUAD
8323 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8324 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8325
8326 ; It's important to list the o->f and f->o moves before f->f because
8327 ; otherwise reload, given m->f, will try to pick f->f and reload it,
8328 ; which doesn't make progress. Likewise r->Y must be before r->r.
8329 (define_insn_and_split "*movtf_internal"
8330 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
8331 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
8332 "!TARGET_IEEEQUAD
8333 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8334 && (gpc_reg_operand (operands[0], TFmode)
8335 || gpc_reg_operand (operands[1], TFmode))"
8336 "#"
8337 "&& reload_completed"
8338 [(pc)]
8339 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8340 [(set_attr "length" "8,8,8,20,20,16")])
8341
8342 (define_expand "extenddftf2"
8343 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8344 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8345 (use (match_dup 2))])]
8346 "!TARGET_IEEEQUAD
8347 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8348 {
8349 operands[2] = CONST0_RTX (DFmode);
8350 /* Generate GOT reference early for SVR4 PIC. */
8351 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8352 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8353 })
8354
8355 (define_insn_and_split "*extenddftf2_internal"
8356 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8357 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8358 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
8359 "!TARGET_IEEEQUAD
8360 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8361 "#"
8362 "&& reload_completed"
8363 [(pc)]
8364 {
8365 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8366 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8367 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8368 operands[1]);
8369 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8370 operands[2]);
8371 DONE;
8372 })
8373
8374 (define_expand "extendsftf2"
8375 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8376 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8377 "!TARGET_IEEEQUAD
8378 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8379 {
8380 rtx tmp = gen_reg_rtx (DFmode);
8381 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8382 emit_insn (gen_extenddftf2 (operands[0], tmp));
8383 DONE;
8384 })
8385
8386 (define_expand "trunctfdf2"
8387 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8388 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8389 "!TARGET_IEEEQUAD
8390 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8391 "")
8392
8393 (define_insn_and_split "trunctfdf2_internal1"
8394 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8395 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
8396 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8397 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8398 "@
8399 #
8400 fmr %0,%1"
8401 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8402 [(const_int 0)]
8403 {
8404 emit_note (NOTE_INSN_DELETED);
8405 DONE;
8406 }
8407 [(set_attr "type" "fp")])
8408
8409 (define_insn "trunctfdf2_internal2"
8410 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8411 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8412 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8413 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8414 "fadd %0,%1,%L1"
8415 [(set_attr "type" "fp")])
8416
8417 (define_insn_and_split "trunctfsf2"
8418 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8419 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8420 (clobber (match_scratch:DF 2 "=f"))]
8421 "!TARGET_IEEEQUAD
8422 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8423 "#"
8424 "&& reload_completed"
8425 [(set (match_dup 2)
8426 (float_truncate:DF (match_dup 1)))
8427 (set (match_dup 0)
8428 (float_truncate:SF (match_dup 2)))]
8429 "")
8430
8431 (define_expand "floatsitf2"
8432 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8433 (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))]
8434 "!TARGET_IEEEQUAD
8435 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8436 {
8437 rtx tmp = gen_reg_rtx (DFmode);
8438 expand_float (tmp, operands[1], false);
8439 emit_insn (gen_extenddftf2 (operands[0], tmp));
8440 DONE;
8441 })
8442
8443 ; fadd, but rounding towards zero.
8444 ; This is probably not the optimal code sequence.
8445 (define_insn "fix_trunc_helper"
8446 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8447 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8448 UNSPEC_FIX_TRUNC_TF))
8449 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8450 "TARGET_HARD_FLOAT && TARGET_FPRS"
8451 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8452 [(set_attr "type" "fp")
8453 (set_attr "length" "20")])
8454
8455 (define_expand "fix_trunctfsi2"
8456 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8457 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8458 (clobber (match_dup 2))
8459 (clobber (match_dup 3))
8460 (clobber (match_dup 4))
8461 (clobber (match_dup 5))])]
8462 "!TARGET_IEEEQUAD
8463 && (TARGET_POWER2 || TARGET_POWERPC)
8464 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8465 {
8466 operands[2] = gen_reg_rtx (DFmode);
8467 operands[3] = gen_reg_rtx (DFmode);
8468 operands[4] = gen_reg_rtx (DImode);
8469 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8470 })
8471
8472 (define_insn_and_split "*fix_trunctfsi2_internal"
8473 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8474 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8475 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8476 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8477 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8478 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
8479 "!TARGET_IEEEQUAD
8480 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8481 "#"
8482 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[5]))"
8483 [(pc)]
8484 {
8485 rtx lowword;
8486 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8487
8488 gcc_assert (MEM_P (operands[5]));
8489 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8490
8491 emit_insn (gen_fctiwz (operands[4], operands[2]));
8492 emit_move_insn (operands[5], operands[4]);
8493 emit_move_insn (operands[0], lowword);
8494 DONE;
8495 })
8496
8497 (define_insn "negtf2"
8498 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8499 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8500 "!TARGET_IEEEQUAD
8501 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8502 "*
8503 {
8504 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8505 return \"fneg %L0,%L1\;fneg %0,%1\";
8506 else
8507 return \"fneg %0,%1\;fneg %L0,%L1\";
8508 }"
8509 [(set_attr "type" "fp")
8510 (set_attr "length" "8")])
8511
8512 (define_expand "abstf2"
8513 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8514 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8515 "!TARGET_IEEEQUAD
8516 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8517 "
8518 {
8519 rtx label = gen_label_rtx ();
8520 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8521 emit_label (label);
8522 DONE;
8523 }")
8524
8525 (define_expand "abstf2_internal"
8526 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8527 (match_operand:TF 1 "gpc_reg_operand" "f"))
8528 (set (match_dup 3) (match_dup 5))
8529 (set (match_dup 5) (abs:DF (match_dup 5)))
8530 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8531 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8532 (label_ref (match_operand 2 "" ""))
8533 (pc)))
8534 (set (match_dup 6) (neg:DF (match_dup 6)))]
8535 "!TARGET_IEEEQUAD
8536 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8537 "
8538 {
8539 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8540 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8541 operands[3] = gen_reg_rtx (DFmode);
8542 operands[4] = gen_reg_rtx (CCFPmode);
8543 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8544 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8545 }")
8546 \f
8547 ;; Next come the multi-word integer load and store and the load and store
8548 ;; multiple insns.
8549
8550 ; List r->r after r->"o<>", otherwise reload will try to reload a
8551 ; non-offsettable address by using r->r which won't make progress.
8552 (define_insn "*movdi_internal32"
8553 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
8554 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
8555 "! TARGET_POWERPC64
8556 && (gpc_reg_operand (operands[0], DImode)
8557 || gpc_reg_operand (operands[1], DImode))"
8558 "@
8559 #
8560 #
8561 #
8562 fmr %0,%1
8563 lfd%U1%X1 %0,%1
8564 stfd%U0%X0 %1,%0
8565 #"
8566 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
8567
8568 (define_split
8569 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8570 (match_operand:DI 1 "const_int_operand" ""))]
8571 "! TARGET_POWERPC64 && reload_completed"
8572 [(set (match_dup 2) (match_dup 4))
8573 (set (match_dup 3) (match_dup 1))]
8574 "
8575 {
8576 HOST_WIDE_INT value = INTVAL (operands[1]);
8577 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8578 DImode);
8579 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8580 DImode);
8581 #if HOST_BITS_PER_WIDE_INT == 32
8582 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8583 #else
8584 operands[4] = GEN_INT (value >> 32);
8585 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8586 #endif
8587 }")
8588
8589 (define_split
8590 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8591 (match_operand:DI 1 "input_operand" ""))]
8592 "reload_completed && !TARGET_POWERPC64
8593 && gpr_or_gpr_p (operands[0], operands[1])"
8594 [(pc)]
8595 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8596
8597 (define_insn "*movdi_internal64"
8598 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
8599 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8600 "TARGET_POWERPC64
8601 && (gpc_reg_operand (operands[0], DImode)
8602 || gpc_reg_operand (operands[1], DImode))"
8603 "@
8604 mr %0,%1
8605 ld%U1%X1 %0,%1
8606 std%U0%X0 %1,%0
8607 li %0,%1
8608 lis %0,%v1
8609 #
8610 {cal|la} %0,%a1
8611 fmr %0,%1
8612 lfd%U1%X1 %0,%1
8613 stfd%U0%X0 %1,%0
8614 mf%1 %0
8615 mt%0 %1
8616 {cror 0,0,0|nop}"
8617 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
8618 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8619
8620 ;; immediate value valid for a single instruction hiding in a const_double
8621 (define_insn ""
8622 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8623 (match_operand:DI 1 "const_double_operand" "F"))]
8624 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8625 && GET_CODE (operands[1]) == CONST_DOUBLE
8626 && num_insns_constant (operands[1], DImode) == 1"
8627 "*
8628 {
8629 return ((unsigned HOST_WIDE_INT)
8630 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8631 ? \"li %0,%1\" : \"lis %0,%v1\";
8632 }")
8633
8634 ;; Generate all one-bits and clear left or right.
8635 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8636 (define_split
8637 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8638 (match_operand:DI 1 "mask64_operand" ""))]
8639 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8640 [(set (match_dup 0) (const_int -1))
8641 (set (match_dup 0)
8642 (and:DI (rotate:DI (match_dup 0)
8643 (const_int 0))
8644 (match_dup 1)))]
8645 "")
8646
8647 ;; Split a load of a large constant into the appropriate five-instruction
8648 ;; sequence. Handle anything in a constant number of insns.
8649 ;; When non-easy constants can go in the TOC, this should use
8650 ;; easy_fp_constant predicate.
8651 (define_split
8652 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8653 (match_operand:DI 1 "const_int_operand" ""))]
8654 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8655 [(set (match_dup 0) (match_dup 2))
8656 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8657 "
8658 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8659
8660 if (tem == operands[0])
8661 DONE;
8662 else
8663 FAIL;
8664 }")
8665
8666 (define_split
8667 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8668 (match_operand:DI 1 "const_double_operand" ""))]
8669 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8670 [(set (match_dup 0) (match_dup 2))
8671 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8672 "
8673 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8674
8675 if (tem == operands[0])
8676 DONE;
8677 else
8678 FAIL;
8679 }")
8680 \f
8681 ;; TImode is similar, except that we usually want to compute the address into
8682 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8683 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8684
8685 ;; We say that MQ is clobbered in the last alternative because the first
8686 ;; alternative would never get used otherwise since it would need a reload
8687 ;; while the 2nd alternative would not. We put memory cases first so they
8688 ;; are preferred. Otherwise, we'd try to reload the output instead of
8689 ;; giving the SCRATCH mq.
8690
8691 (define_insn "*movti_power"
8692 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
8693 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
8694 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
8695 "TARGET_POWER && ! TARGET_POWERPC64
8696 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8697 "*
8698 {
8699 switch (which_alternative)
8700 {
8701 default:
8702 gcc_unreachable ();
8703
8704 case 0:
8705 if (TARGET_STRING)
8706 return \"{stsi|stswi} %1,%P0,16\";
8707 case 1:
8708 case 2:
8709 return \"#\";
8710 case 3:
8711 /* If the address is not used in the output, we can use lsi. Otherwise,
8712 fall through to generating four loads. */
8713 if (TARGET_STRING
8714 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8715 return \"{lsi|lswi} %0,%P1,16\";
8716 /* ... fall through ... */
8717 case 4:
8718 case 5:
8719 return \"#\";
8720 }
8721 }"
8722 [(set_attr "type" "store,store,*,load,load,*")])
8723
8724 (define_insn "*movti_string"
8725 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
8726 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
8727 "! TARGET_POWER && ! TARGET_POWERPC64
8728 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8729 "*
8730 {
8731 switch (which_alternative)
8732 {
8733 default:
8734 gcc_unreachable ();
8735 case 0:
8736 if (TARGET_STRING)
8737 return \"{stsi|stswi} %1,%P0,16\";
8738 case 1:
8739 case 2:
8740 return \"#\";
8741 case 3:
8742 /* If the address is not used in the output, we can use lsi. Otherwise,
8743 fall through to generating four loads. */
8744 if (TARGET_STRING
8745 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8746 return \"{lsi|lswi} %0,%P1,16\";
8747 /* ... fall through ... */
8748 case 4:
8749 case 5:
8750 return \"#\";
8751 }
8752 }"
8753 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")])
8754
8755 (define_insn "*movti_ppc64"
8756 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
8757 (match_operand:TI 1 "input_operand" "r,r,m"))]
8758 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8759 || gpc_reg_operand (operands[1], TImode))"
8760 "#"
8761 [(set_attr "type" "*,load,store")])
8762
8763 (define_split
8764 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8765 (match_operand:TI 1 "const_double_operand" ""))]
8766 "TARGET_POWERPC64"
8767 [(set (match_dup 2) (match_dup 4))
8768 (set (match_dup 3) (match_dup 5))]
8769 "
8770 {
8771 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8772 TImode);
8773 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8774 TImode);
8775 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8776 {
8777 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8778 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8779 }
8780 else if (GET_CODE (operands[1]) == CONST_INT)
8781 {
8782 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8783 operands[5] = operands[1];
8784 }
8785 else
8786 FAIL;
8787 }")
8788
8789 (define_split
8790 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8791 (match_operand:TI 1 "input_operand" ""))]
8792 "reload_completed
8793 && gpr_or_gpr_p (operands[0], operands[1])"
8794 [(pc)]
8795 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8796 \f
8797 (define_expand "load_multiple"
8798 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8799 (match_operand:SI 1 "" ""))
8800 (use (match_operand:SI 2 "" ""))])]
8801 "TARGET_STRING && !TARGET_POWERPC64"
8802 "
8803 {
8804 int regno;
8805 int count;
8806 rtx op1;
8807 int i;
8808
8809 /* Support only loading a constant number of fixed-point registers from
8810 memory and only bother with this if more than two; the machine
8811 doesn't support more than eight. */
8812 if (GET_CODE (operands[2]) != CONST_INT
8813 || INTVAL (operands[2]) <= 2
8814 || INTVAL (operands[2]) > 8
8815 || GET_CODE (operands[1]) != MEM
8816 || GET_CODE (operands[0]) != REG
8817 || REGNO (operands[0]) >= 32)
8818 FAIL;
8819
8820 count = INTVAL (operands[2]);
8821 regno = REGNO (operands[0]);
8822
8823 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8824 op1 = replace_equiv_address (operands[1],
8825 force_reg (SImode, XEXP (operands[1], 0)));
8826
8827 for (i = 0; i < count; i++)
8828 XVECEXP (operands[3], 0, i)
8829 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8830 adjust_address_nv (op1, SImode, i * 4));
8831 }")
8832
8833 (define_insn "*ldmsi8"
8834 [(match_parallel 0 "load_multiple_operation"
8835 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8836 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8837 (set (match_operand:SI 3 "gpc_reg_operand" "")
8838 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8839 (set (match_operand:SI 4 "gpc_reg_operand" "")
8840 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8841 (set (match_operand:SI 5 "gpc_reg_operand" "")
8842 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8843 (set (match_operand:SI 6 "gpc_reg_operand" "")
8844 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8845 (set (match_operand:SI 7 "gpc_reg_operand" "")
8846 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8847 (set (match_operand:SI 8 "gpc_reg_operand" "")
8848 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8849 (set (match_operand:SI 9 "gpc_reg_operand" "")
8850 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8851 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8852 "*
8853 { return rs6000_output_load_multiple (operands); }"
8854 [(set_attr "type" "load_ux")
8855 (set_attr "length" "32")])
8856
8857 (define_insn "*ldmsi7"
8858 [(match_parallel 0 "load_multiple_operation"
8859 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8860 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8861 (set (match_operand:SI 3 "gpc_reg_operand" "")
8862 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8863 (set (match_operand:SI 4 "gpc_reg_operand" "")
8864 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8865 (set (match_operand:SI 5 "gpc_reg_operand" "")
8866 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8867 (set (match_operand:SI 6 "gpc_reg_operand" "")
8868 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8869 (set (match_operand:SI 7 "gpc_reg_operand" "")
8870 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8871 (set (match_operand:SI 8 "gpc_reg_operand" "")
8872 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8873 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8874 "*
8875 { return rs6000_output_load_multiple (operands); }"
8876 [(set_attr "type" "load_ux")
8877 (set_attr "length" "32")])
8878
8879 (define_insn "*ldmsi6"
8880 [(match_parallel 0 "load_multiple_operation"
8881 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8882 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8883 (set (match_operand:SI 3 "gpc_reg_operand" "")
8884 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8885 (set (match_operand:SI 4 "gpc_reg_operand" "")
8886 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8887 (set (match_operand:SI 5 "gpc_reg_operand" "")
8888 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8889 (set (match_operand:SI 6 "gpc_reg_operand" "")
8890 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8891 (set (match_operand:SI 7 "gpc_reg_operand" "")
8892 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8893 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8894 "*
8895 { return rs6000_output_load_multiple (operands); }"
8896 [(set_attr "type" "load_ux")
8897 (set_attr "length" "32")])
8898
8899 (define_insn "*ldmsi5"
8900 [(match_parallel 0 "load_multiple_operation"
8901 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8902 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8903 (set (match_operand:SI 3 "gpc_reg_operand" "")
8904 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8905 (set (match_operand:SI 4 "gpc_reg_operand" "")
8906 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8907 (set (match_operand:SI 5 "gpc_reg_operand" "")
8908 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8909 (set (match_operand:SI 6 "gpc_reg_operand" "")
8910 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8911 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8912 "*
8913 { return rs6000_output_load_multiple (operands); }"
8914 [(set_attr "type" "load_ux")
8915 (set_attr "length" "32")])
8916
8917 (define_insn "*ldmsi4"
8918 [(match_parallel 0 "load_multiple_operation"
8919 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8920 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8921 (set (match_operand:SI 3 "gpc_reg_operand" "")
8922 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8923 (set (match_operand:SI 4 "gpc_reg_operand" "")
8924 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8925 (set (match_operand:SI 5 "gpc_reg_operand" "")
8926 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8927 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8928 "*
8929 { return rs6000_output_load_multiple (operands); }"
8930 [(set_attr "type" "load_ux")
8931 (set_attr "length" "32")])
8932
8933 (define_insn "*ldmsi3"
8934 [(match_parallel 0 "load_multiple_operation"
8935 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8936 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8937 (set (match_operand:SI 3 "gpc_reg_operand" "")
8938 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8939 (set (match_operand:SI 4 "gpc_reg_operand" "")
8940 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8941 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8942 "*
8943 { return rs6000_output_load_multiple (operands); }"
8944 [(set_attr "type" "load_ux")
8945 (set_attr "length" "32")])
8946
8947 (define_expand "store_multiple"
8948 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8949 (match_operand:SI 1 "" ""))
8950 (clobber (scratch:SI))
8951 (use (match_operand:SI 2 "" ""))])]
8952 "TARGET_STRING && !TARGET_POWERPC64"
8953 "
8954 {
8955 int regno;
8956 int count;
8957 rtx to;
8958 rtx op0;
8959 int i;
8960
8961 /* Support only storing a constant number of fixed-point registers to
8962 memory and only bother with this if more than two; the machine
8963 doesn't support more than eight. */
8964 if (GET_CODE (operands[2]) != CONST_INT
8965 || INTVAL (operands[2]) <= 2
8966 || INTVAL (operands[2]) > 8
8967 || GET_CODE (operands[0]) != MEM
8968 || GET_CODE (operands[1]) != REG
8969 || REGNO (operands[1]) >= 32)
8970 FAIL;
8971
8972 count = INTVAL (operands[2]);
8973 regno = REGNO (operands[1]);
8974
8975 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8976 to = force_reg (SImode, XEXP (operands[0], 0));
8977 op0 = replace_equiv_address (operands[0], to);
8978
8979 XVECEXP (operands[3], 0, 0)
8980 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
8981 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8982 gen_rtx_SCRATCH (SImode));
8983
8984 for (i = 1; i < count; i++)
8985 XVECEXP (operands[3], 0, i + 1)
8986 = gen_rtx_SET (VOIDmode,
8987 adjust_address_nv (op0, SImode, i * 4),
8988 gen_rtx_REG (SImode, regno + i));
8989 }")
8990
8991 (define_insn "*store_multiple_power"
8992 [(match_parallel 0 "store_multiple_operation"
8993 [(set (match_operand:SI 1 "indirect_operand" "=Q")
8994 (match_operand:SI 2 "gpc_reg_operand" "r"))
8995 (clobber (match_scratch:SI 3 "=q"))])]
8996 "TARGET_STRING && TARGET_POWER"
8997 "{stsi|stswi} %2,%P1,%O0"
8998 [(set_attr "type" "store")])
8999
9000 (define_insn "*stmsi8"
9001 [(match_parallel 0 "store_multiple_operation"
9002 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9003 (match_operand:SI 2 "gpc_reg_operand" "r"))
9004 (clobber (match_scratch:SI 3 "X"))
9005 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9006 (match_operand:SI 4 "gpc_reg_operand" "r"))
9007 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9008 (match_operand:SI 5 "gpc_reg_operand" "r"))
9009 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9010 (match_operand:SI 6 "gpc_reg_operand" "r"))
9011 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9012 (match_operand:SI 7 "gpc_reg_operand" "r"))
9013 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9014 (match_operand:SI 8 "gpc_reg_operand" "r"))
9015 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9016 (match_operand:SI 9 "gpc_reg_operand" "r"))
9017 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9018 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9019 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9020 "{stsi|stswi} %2,%1,%O0"
9021 [(set_attr "type" "store_ux")])
9022
9023 (define_insn "*stmsi7"
9024 [(match_parallel 0 "store_multiple_operation"
9025 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9026 (match_operand:SI 2 "gpc_reg_operand" "r"))
9027 (clobber (match_scratch:SI 3 "X"))
9028 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9029 (match_operand:SI 4 "gpc_reg_operand" "r"))
9030 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9031 (match_operand:SI 5 "gpc_reg_operand" "r"))
9032 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9033 (match_operand:SI 6 "gpc_reg_operand" "r"))
9034 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9035 (match_operand:SI 7 "gpc_reg_operand" "r"))
9036 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9037 (match_operand:SI 8 "gpc_reg_operand" "r"))
9038 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9039 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9040 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9041 "{stsi|stswi} %2,%1,%O0"
9042 [(set_attr "type" "store_ux")])
9043
9044 (define_insn "*stmsi6"
9045 [(match_parallel 0 "store_multiple_operation"
9046 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9047 (match_operand:SI 2 "gpc_reg_operand" "r"))
9048 (clobber (match_scratch:SI 3 "X"))
9049 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9050 (match_operand:SI 4 "gpc_reg_operand" "r"))
9051 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9052 (match_operand:SI 5 "gpc_reg_operand" "r"))
9053 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9054 (match_operand:SI 6 "gpc_reg_operand" "r"))
9055 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9056 (match_operand:SI 7 "gpc_reg_operand" "r"))
9057 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9058 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9059 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9060 "{stsi|stswi} %2,%1,%O0"
9061 [(set_attr "type" "store_ux")])
9062
9063 (define_insn "*stmsi5"
9064 [(match_parallel 0 "store_multiple_operation"
9065 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9066 (match_operand:SI 2 "gpc_reg_operand" "r"))
9067 (clobber (match_scratch:SI 3 "X"))
9068 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9069 (match_operand:SI 4 "gpc_reg_operand" "r"))
9070 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9071 (match_operand:SI 5 "gpc_reg_operand" "r"))
9072 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9073 (match_operand:SI 6 "gpc_reg_operand" "r"))
9074 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9075 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9076 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9077 "{stsi|stswi} %2,%1,%O0"
9078 [(set_attr "type" "store_ux")])
9079
9080 (define_insn "*stmsi4"
9081 [(match_parallel 0 "store_multiple_operation"
9082 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9083 (match_operand:SI 2 "gpc_reg_operand" "r"))
9084 (clobber (match_scratch:SI 3 "X"))
9085 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9086 (match_operand:SI 4 "gpc_reg_operand" "r"))
9087 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9088 (match_operand:SI 5 "gpc_reg_operand" "r"))
9089 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9090 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9091 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9092 "{stsi|stswi} %2,%1,%O0"
9093 [(set_attr "type" "store_ux")])
9094
9095 (define_insn "*stmsi3"
9096 [(match_parallel 0 "store_multiple_operation"
9097 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9098 (match_operand:SI 2 "gpc_reg_operand" "r"))
9099 (clobber (match_scratch:SI 3 "X"))
9100 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9101 (match_operand:SI 4 "gpc_reg_operand" "r"))
9102 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9103 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9104 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9105 "{stsi|stswi} %2,%1,%O0"
9106 [(set_attr "type" "store_ux")])
9107 \f
9108 (define_expand "setmemsi"
9109 [(parallel [(set (match_operand:BLK 0 "" "")
9110 (match_operand 2 "const_int_operand" ""))
9111 (use (match_operand:SI 1 "" ""))
9112 (use (match_operand:SI 3 "" ""))])]
9113 ""
9114 "
9115 {
9116 /* If value to set is not zero, use the library routine. */
9117 if (operands[2] != const0_rtx)
9118 FAIL;
9119
9120 if (expand_block_clear (operands))
9121 DONE;
9122 else
9123 FAIL;
9124 }")
9125
9126 ;; String/block move insn.
9127 ;; Argument 0 is the destination
9128 ;; Argument 1 is the source
9129 ;; Argument 2 is the length
9130 ;; Argument 3 is the alignment
9131
9132 (define_expand "movmemsi"
9133 [(parallel [(set (match_operand:BLK 0 "" "")
9134 (match_operand:BLK 1 "" ""))
9135 (use (match_operand:SI 2 "" ""))
9136 (use (match_operand:SI 3 "" ""))])]
9137 ""
9138 "
9139 {
9140 if (expand_block_move (operands))
9141 DONE;
9142 else
9143 FAIL;
9144 }")
9145
9146 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9147 ;; register allocator doesn't have a clue about allocating 8 word registers.
9148 ;; rD/rS = r5 is preferred, efficient form.
9149 (define_expand "movmemsi_8reg"
9150 [(parallel [(set (match_operand 0 "" "")
9151 (match_operand 1 "" ""))
9152 (use (match_operand 2 "" ""))
9153 (use (match_operand 3 "" ""))
9154 (clobber (reg:SI 5))
9155 (clobber (reg:SI 6))
9156 (clobber (reg:SI 7))
9157 (clobber (reg:SI 8))
9158 (clobber (reg:SI 9))
9159 (clobber (reg:SI 10))
9160 (clobber (reg:SI 11))
9161 (clobber (reg:SI 12))
9162 (clobber (match_scratch:SI 4 ""))])]
9163 "TARGET_STRING"
9164 "")
9165
9166 (define_insn ""
9167 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9168 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9169 (use (match_operand:SI 2 "immediate_operand" "i"))
9170 (use (match_operand:SI 3 "immediate_operand" "i"))
9171 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9172 (clobber (reg:SI 6))
9173 (clobber (reg:SI 7))
9174 (clobber (reg:SI 8))
9175 (clobber (reg:SI 9))
9176 (clobber (reg:SI 10))
9177 (clobber (reg:SI 11))
9178 (clobber (reg:SI 12))
9179 (clobber (match_scratch:SI 5 "=q"))]
9180 "TARGET_STRING && TARGET_POWER
9181 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9182 || INTVAL (operands[2]) == 0)
9183 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9184 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9185 && REGNO (operands[4]) == 5"
9186 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9187 [(set_attr "type" "store_ux")
9188 (set_attr "length" "8")])
9189
9190 (define_insn ""
9191 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9192 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9193 (use (match_operand:SI 2 "immediate_operand" "i"))
9194 (use (match_operand:SI 3 "immediate_operand" "i"))
9195 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9196 (clobber (reg:SI 6))
9197 (clobber (reg:SI 7))
9198 (clobber (reg:SI 8))
9199 (clobber (reg:SI 9))
9200 (clobber (reg:SI 10))
9201 (clobber (reg:SI 11))
9202 (clobber (reg:SI 12))
9203 (clobber (match_scratch:SI 5 "X"))]
9204 "TARGET_STRING && ! TARGET_POWER
9205 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9206 || INTVAL (operands[2]) == 0)
9207 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9208 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9209 && REGNO (operands[4]) == 5"
9210 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9211 [(set_attr "type" "store_ux")
9212 (set_attr "length" "8")])
9213
9214 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9215 ;; register allocator doesn't have a clue about allocating 6 word registers.
9216 ;; rD/rS = r5 is preferred, efficient form.
9217 (define_expand "movmemsi_6reg"
9218 [(parallel [(set (match_operand 0 "" "")
9219 (match_operand 1 "" ""))
9220 (use (match_operand 2 "" ""))
9221 (use (match_operand 3 "" ""))
9222 (clobber (reg:SI 5))
9223 (clobber (reg:SI 6))
9224 (clobber (reg:SI 7))
9225 (clobber (reg:SI 8))
9226 (clobber (reg:SI 9))
9227 (clobber (reg:SI 10))
9228 (clobber (match_scratch:SI 4 ""))])]
9229 "TARGET_STRING"
9230 "")
9231
9232 (define_insn ""
9233 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9234 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9235 (use (match_operand:SI 2 "immediate_operand" "i"))
9236 (use (match_operand:SI 3 "immediate_operand" "i"))
9237 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9238 (clobber (reg:SI 6))
9239 (clobber (reg:SI 7))
9240 (clobber (reg:SI 8))
9241 (clobber (reg:SI 9))
9242 (clobber (reg:SI 10))
9243 (clobber (match_scratch:SI 5 "=q"))]
9244 "TARGET_STRING && TARGET_POWER
9245 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9246 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9247 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9248 && REGNO (operands[4]) == 5"
9249 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9250 [(set_attr "type" "store_ux")
9251 (set_attr "length" "8")])
9252
9253 (define_insn ""
9254 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9255 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9256 (use (match_operand:SI 2 "immediate_operand" "i"))
9257 (use (match_operand:SI 3 "immediate_operand" "i"))
9258 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9259 (clobber (reg:SI 6))
9260 (clobber (reg:SI 7))
9261 (clobber (reg:SI 8))
9262 (clobber (reg:SI 9))
9263 (clobber (reg:SI 10))
9264 (clobber (match_scratch:SI 5 "X"))]
9265 "TARGET_STRING && ! TARGET_POWER
9266 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9267 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9268 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9269 && REGNO (operands[4]) == 5"
9270 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9271 [(set_attr "type" "store_ux")
9272 (set_attr "length" "8")])
9273
9274 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9275 ;; problems with TImode.
9276 ;; rD/rS = r5 is preferred, efficient form.
9277 (define_expand "movmemsi_4reg"
9278 [(parallel [(set (match_operand 0 "" "")
9279 (match_operand 1 "" ""))
9280 (use (match_operand 2 "" ""))
9281 (use (match_operand 3 "" ""))
9282 (clobber (reg:SI 5))
9283 (clobber (reg:SI 6))
9284 (clobber (reg:SI 7))
9285 (clobber (reg:SI 8))
9286 (clobber (match_scratch:SI 4 ""))])]
9287 "TARGET_STRING"
9288 "")
9289
9290 (define_insn ""
9291 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9292 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9293 (use (match_operand:SI 2 "immediate_operand" "i"))
9294 (use (match_operand:SI 3 "immediate_operand" "i"))
9295 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9296 (clobber (reg:SI 6))
9297 (clobber (reg:SI 7))
9298 (clobber (reg:SI 8))
9299 (clobber (match_scratch:SI 5 "=q"))]
9300 "TARGET_STRING && TARGET_POWER
9301 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9302 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9303 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9304 && REGNO (operands[4]) == 5"
9305 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9306 [(set_attr "type" "store_ux")
9307 (set_attr "length" "8")])
9308
9309 (define_insn ""
9310 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9311 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9312 (use (match_operand:SI 2 "immediate_operand" "i"))
9313 (use (match_operand:SI 3 "immediate_operand" "i"))
9314 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9315 (clobber (reg:SI 6))
9316 (clobber (reg:SI 7))
9317 (clobber (reg:SI 8))
9318 (clobber (match_scratch:SI 5 "X"))]
9319 "TARGET_STRING && ! TARGET_POWER
9320 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9321 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9322 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9323 && REGNO (operands[4]) == 5"
9324 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9325 [(set_attr "type" "store_ux")
9326 (set_attr "length" "8")])
9327
9328 ;; Move up to 8 bytes at a time.
9329 (define_expand "movmemsi_2reg"
9330 [(parallel [(set (match_operand 0 "" "")
9331 (match_operand 1 "" ""))
9332 (use (match_operand 2 "" ""))
9333 (use (match_operand 3 "" ""))
9334 (clobber (match_scratch:DI 4 ""))
9335 (clobber (match_scratch:SI 5 ""))])]
9336 "TARGET_STRING && ! TARGET_POWERPC64"
9337 "")
9338
9339 (define_insn ""
9340 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9341 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9342 (use (match_operand:SI 2 "immediate_operand" "i"))
9343 (use (match_operand:SI 3 "immediate_operand" "i"))
9344 (clobber (match_scratch:DI 4 "=&r"))
9345 (clobber (match_scratch:SI 5 "=q"))]
9346 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9347 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9348 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9349 [(set_attr "type" "store_ux")
9350 (set_attr "length" "8")])
9351
9352 (define_insn ""
9353 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9354 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9355 (use (match_operand:SI 2 "immediate_operand" "i"))
9356 (use (match_operand:SI 3 "immediate_operand" "i"))
9357 (clobber (match_scratch:DI 4 "=&r"))
9358 (clobber (match_scratch:SI 5 "X"))]
9359 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9360 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9361 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9362 [(set_attr "type" "store_ux")
9363 (set_attr "length" "8")])
9364
9365 ;; Move up to 4 bytes at a time.
9366 (define_expand "movmemsi_1reg"
9367 [(parallel [(set (match_operand 0 "" "")
9368 (match_operand 1 "" ""))
9369 (use (match_operand 2 "" ""))
9370 (use (match_operand 3 "" ""))
9371 (clobber (match_scratch:SI 4 ""))
9372 (clobber (match_scratch:SI 5 ""))])]
9373 "TARGET_STRING"
9374 "")
9375
9376 (define_insn ""
9377 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9378 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9379 (use (match_operand:SI 2 "immediate_operand" "i"))
9380 (use (match_operand:SI 3 "immediate_operand" "i"))
9381 (clobber (match_scratch:SI 4 "=&r"))
9382 (clobber (match_scratch:SI 5 "=q"))]
9383 "TARGET_STRING && TARGET_POWER
9384 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9385 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9386 [(set_attr "type" "store_ux")
9387 (set_attr "length" "8")])
9388
9389 (define_insn ""
9390 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9391 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9392 (use (match_operand:SI 2 "immediate_operand" "i"))
9393 (use (match_operand:SI 3 "immediate_operand" "i"))
9394 (clobber (match_scratch:SI 4 "=&r"))
9395 (clobber (match_scratch:SI 5 "X"))]
9396 "TARGET_STRING && ! TARGET_POWER
9397 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9398 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9399 [(set_attr "type" "store_ux")
9400 (set_attr "length" "8")])
9401 \f
9402 ;; Define insns that do load or store with update. Some of these we can
9403 ;; get by using pre-decrement or pre-increment, but the hardware can also
9404 ;; do cases where the increment is not the size of the object.
9405 ;;
9406 ;; In all these cases, we use operands 0 and 1 for the register being
9407 ;; incremented because those are the operands that local-alloc will
9408 ;; tie and these are the pair most likely to be tieable (and the ones
9409 ;; that will benefit the most).
9410
9411 (define_insn "*movdi_update1"
9412 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9413 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9414 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9415 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9416 (plus:DI (match_dup 1) (match_dup 2)))]
9417 "TARGET_POWERPC64 && TARGET_UPDATE"
9418 "@
9419 ldux %3,%0,%2
9420 ldu %3,%2(%0)"
9421 [(set_attr "type" "load_ux,load_u")])
9422
9423 (define_insn "movdi_<mode>_update"
9424 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9425 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9426 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9427 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9428 (plus:P (match_dup 1) (match_dup 2)))]
9429 "TARGET_POWERPC64 && TARGET_UPDATE"
9430 "@
9431 stdux %3,%0,%2
9432 stdu %3,%2(%0)"
9433 [(set_attr "type" "store_ux,store_u")])
9434
9435 (define_insn "*movsi_update1"
9436 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9437 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9438 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9439 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9440 (plus:SI (match_dup 1) (match_dup 2)))]
9441 "TARGET_UPDATE"
9442 "@
9443 {lux|lwzux} %3,%0,%2
9444 {lu|lwzu} %3,%2(%0)"
9445 [(set_attr "type" "load_ux,load_u")])
9446
9447 (define_insn "*movsi_update2"
9448 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9449 (sign_extend:DI
9450 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9451 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9452 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9453 (plus:DI (match_dup 1) (match_dup 2)))]
9454 "TARGET_POWERPC64"
9455 "lwaux %3,%0,%2"
9456 [(set_attr "type" "load_ext_ux")])
9457
9458 (define_insn "movsi_update"
9459 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9460 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9461 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9462 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9463 (plus:SI (match_dup 1) (match_dup 2)))]
9464 "TARGET_UPDATE"
9465 "@
9466 {stux|stwux} %3,%0,%2
9467 {stu|stwu} %3,%2(%0)"
9468 [(set_attr "type" "store_ux,store_u")])
9469
9470 (define_insn "*movhi_update1"
9471 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9472 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9473 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9474 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9475 (plus:SI (match_dup 1) (match_dup 2)))]
9476 "TARGET_UPDATE"
9477 "@
9478 lhzux %3,%0,%2
9479 lhzu %3,%2(%0)"
9480 [(set_attr "type" "load_ux,load_u")])
9481
9482 (define_insn "*movhi_update2"
9483 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9484 (zero_extend:SI
9485 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9486 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9487 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9488 (plus:SI (match_dup 1) (match_dup 2)))]
9489 "TARGET_UPDATE"
9490 "@
9491 lhzux %3,%0,%2
9492 lhzu %3,%2(%0)"
9493 [(set_attr "type" "load_ux,load_u")])
9494
9495 (define_insn "*movhi_update3"
9496 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9497 (sign_extend:SI
9498 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9499 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9500 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9501 (plus:SI (match_dup 1) (match_dup 2)))]
9502 "TARGET_UPDATE"
9503 "@
9504 lhaux %3,%0,%2
9505 lhau %3,%2(%0)"
9506 [(set_attr "type" "load_ext_ux,load_ext_u")])
9507
9508 (define_insn "*movhi_update4"
9509 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9510 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9511 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9512 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9513 (plus:SI (match_dup 1) (match_dup 2)))]
9514 "TARGET_UPDATE"
9515 "@
9516 sthux %3,%0,%2
9517 sthu %3,%2(%0)"
9518 [(set_attr "type" "store_ux,store_u")])
9519
9520 (define_insn "*movqi_update1"
9521 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9522 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9523 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9524 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9525 (plus:SI (match_dup 1) (match_dup 2)))]
9526 "TARGET_UPDATE"
9527 "@
9528 lbzux %3,%0,%2
9529 lbzu %3,%2(%0)"
9530 [(set_attr "type" "load_ux,load_u")])
9531
9532 (define_insn "*movqi_update2"
9533 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9534 (zero_extend:SI
9535 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9536 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9537 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9538 (plus:SI (match_dup 1) (match_dup 2)))]
9539 "TARGET_UPDATE"
9540 "@
9541 lbzux %3,%0,%2
9542 lbzu %3,%2(%0)"
9543 [(set_attr "type" "load_ux,load_u")])
9544
9545 (define_insn "*movqi_update3"
9546 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9547 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9548 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9549 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9550 (plus:SI (match_dup 1) (match_dup 2)))]
9551 "TARGET_UPDATE"
9552 "@
9553 stbux %3,%0,%2
9554 stbu %3,%2(%0)"
9555 [(set_attr "type" "store_ux,store_u")])
9556
9557 (define_insn "*movsf_update1"
9558 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9559 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9560 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9561 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9562 (plus:SI (match_dup 1) (match_dup 2)))]
9563 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9564 "@
9565 lfsux %3,%0,%2
9566 lfsu %3,%2(%0)"
9567 [(set_attr "type" "fpload_ux,fpload_u")])
9568
9569 (define_insn "*movsf_update2"
9570 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9571 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9572 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9573 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9574 (plus:SI (match_dup 1) (match_dup 2)))]
9575 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9576 "@
9577 stfsux %3,%0,%2
9578 stfsu %3,%2(%0)"
9579 [(set_attr "type" "fpstore_ux,fpstore_u")])
9580
9581 (define_insn "*movsf_update3"
9582 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9583 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9584 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9585 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9586 (plus:SI (match_dup 1) (match_dup 2)))]
9587 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9588 "@
9589 {lux|lwzux} %3,%0,%2
9590 {lu|lwzu} %3,%2(%0)"
9591 [(set_attr "type" "load_ux,load_u")])
9592
9593 (define_insn "*movsf_update4"
9594 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9595 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9596 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9597 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9598 (plus:SI (match_dup 1) (match_dup 2)))]
9599 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9600 "@
9601 {stux|stwux} %3,%0,%2
9602 {stu|stwu} %3,%2(%0)"
9603 [(set_attr "type" "store_ux,store_u")])
9604
9605 (define_insn "*movdf_update1"
9606 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9607 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9608 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9609 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9610 (plus:SI (match_dup 1) (match_dup 2)))]
9611 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9612 "@
9613 lfdux %3,%0,%2
9614 lfdu %3,%2(%0)"
9615 [(set_attr "type" "fpload_ux,fpload_u")])
9616
9617 (define_insn "*movdf_update2"
9618 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9619 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9620 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9621 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9622 (plus:SI (match_dup 1) (match_dup 2)))]
9623 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9624 "@
9625 stfdux %3,%0,%2
9626 stfdu %3,%2(%0)"
9627 [(set_attr "type" "fpstore_ux,fpstore_u")])
9628
9629 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9630
9631 (define_insn "*lfq_power2"
9632 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
9633 (match_operand:V2DF 1 "memory_operand" ""))]
9634 "TARGET_POWER2
9635 && TARGET_HARD_FLOAT && TARGET_FPRS"
9636 "lfq%U1%X1 %0,%1")
9637
9638 (define_peephole2
9639 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9640 (match_operand:DF 1 "memory_operand" ""))
9641 (set (match_operand:DF 2 "gpc_reg_operand" "")
9642 (match_operand:DF 3 "memory_operand" ""))]
9643 "TARGET_POWER2
9644 && TARGET_HARD_FLOAT && TARGET_FPRS
9645 && registers_ok_for_quad_peep (operands[0], operands[2])
9646 && mems_ok_for_quad_peep (operands[1], operands[3])"
9647 [(set (match_dup 0)
9648 (match_dup 1))]
9649 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
9650 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
9651
9652 (define_insn "*stfq_power2"
9653 [(set (match_operand:V2DF 0 "memory_operand" "")
9654 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
9655 "TARGET_POWER2
9656 && TARGET_HARD_FLOAT && TARGET_FPRS"
9657 "stfq%U0%X0 %1,%0")
9658
9659
9660 (define_peephole2
9661 [(set (match_operand:DF 0 "memory_operand" "")
9662 (match_operand:DF 1 "gpc_reg_operand" ""))
9663 (set (match_operand:DF 2 "memory_operand" "")
9664 (match_operand:DF 3 "gpc_reg_operand" ""))]
9665 "TARGET_POWER2
9666 && TARGET_HARD_FLOAT && TARGET_FPRS
9667 && registers_ok_for_quad_peep (operands[1], operands[3])
9668 && mems_ok_for_quad_peep (operands[0], operands[2])"
9669 [(set (match_dup 0)
9670 (match_dup 1))]
9671 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
9672 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
9673
9674 ;; after inserting conditional returns we can sometimes have
9675 ;; unnecessary register moves. Unfortunately we cannot have a
9676 ;; modeless peephole here, because some single SImode sets have early
9677 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9678 ;; sequences, using get_attr_length here will smash the operands
9679 ;; array. Neither is there an early_cobbler_p predicate.
9680 (define_peephole2
9681 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9682 (match_operand:DF 1 "any_operand" ""))
9683 (set (match_operand:DF 2 "gpc_reg_operand" "")
9684 (match_dup 0))]
9685 "peep2_reg_dead_p (2, operands[0])"
9686 [(set (match_dup 2) (match_dup 1))])
9687
9688 (define_peephole2
9689 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9690 (match_operand:SF 1 "any_operand" ""))
9691 (set (match_operand:SF 2 "gpc_reg_operand" "")
9692 (match_dup 0))]
9693 "peep2_reg_dead_p (2, operands[0])"
9694 [(set (match_dup 2) (match_dup 1))])
9695
9696 \f
9697 ;; TLS support.
9698
9699 ;; "b" output constraint here and on tls_ld to support tls linker optimization.
9700 (define_insn "tls_gd_32"
9701 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9702 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9703 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9704 UNSPEC_TLSGD))]
9705 "HAVE_AS_TLS && !TARGET_64BIT"
9706 "addi %0,%1,%2@got@tlsgd")
9707
9708 (define_insn "tls_gd_64"
9709 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9710 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9711 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9712 UNSPEC_TLSGD))]
9713 "HAVE_AS_TLS && TARGET_64BIT"
9714 "addi %0,%1,%2@got@tlsgd")
9715
9716 (define_insn "tls_ld_32"
9717 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9718 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
9719 UNSPEC_TLSLD))]
9720 "HAVE_AS_TLS && !TARGET_64BIT"
9721 "addi %0,%1,%&@got@tlsld")
9722
9723 (define_insn "tls_ld_64"
9724 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9725 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
9726 UNSPEC_TLSLD))]
9727 "HAVE_AS_TLS && TARGET_64BIT"
9728 "addi %0,%1,%&@got@tlsld")
9729
9730 (define_insn "tls_dtprel_32"
9731 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9732 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9733 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9734 UNSPEC_TLSDTPREL))]
9735 "HAVE_AS_TLS && !TARGET_64BIT"
9736 "addi %0,%1,%2@dtprel")
9737
9738 (define_insn "tls_dtprel_64"
9739 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9740 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9741 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9742 UNSPEC_TLSDTPREL))]
9743 "HAVE_AS_TLS && TARGET_64BIT"
9744 "addi %0,%1,%2@dtprel")
9745
9746 (define_insn "tls_dtprel_ha_32"
9747 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9748 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9749 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9750 UNSPEC_TLSDTPRELHA))]
9751 "HAVE_AS_TLS && !TARGET_64BIT"
9752 "addis %0,%1,%2@dtprel@ha")
9753
9754 (define_insn "tls_dtprel_ha_64"
9755 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9756 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9757 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9758 UNSPEC_TLSDTPRELHA))]
9759 "HAVE_AS_TLS && TARGET_64BIT"
9760 "addis %0,%1,%2@dtprel@ha")
9761
9762 (define_insn "tls_dtprel_lo_32"
9763 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9764 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9765 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9766 UNSPEC_TLSDTPRELLO))]
9767 "HAVE_AS_TLS && !TARGET_64BIT"
9768 "addi %0,%1,%2@dtprel@l")
9769
9770 (define_insn "tls_dtprel_lo_64"
9771 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9772 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9773 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9774 UNSPEC_TLSDTPRELLO))]
9775 "HAVE_AS_TLS && TARGET_64BIT"
9776 "addi %0,%1,%2@dtprel@l")
9777
9778 (define_insn "tls_got_dtprel_32"
9779 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9780 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9781 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9782 UNSPEC_TLSGOTDTPREL))]
9783 "HAVE_AS_TLS && !TARGET_64BIT"
9784 "lwz %0,%2@got@dtprel(%1)")
9785
9786 (define_insn "tls_got_dtprel_64"
9787 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9788 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9789 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9790 UNSPEC_TLSGOTDTPREL))]
9791 "HAVE_AS_TLS && TARGET_64BIT"
9792 "ld %0,%2@got@dtprel(%1)")
9793
9794 (define_insn "tls_tprel_32"
9795 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9796 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9797 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9798 UNSPEC_TLSTPREL))]
9799 "HAVE_AS_TLS && !TARGET_64BIT"
9800 "addi %0,%1,%2@tprel")
9801
9802 (define_insn "tls_tprel_64"
9803 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9804 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9805 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9806 UNSPEC_TLSTPREL))]
9807 "HAVE_AS_TLS && TARGET_64BIT"
9808 "addi %0,%1,%2@tprel")
9809
9810 (define_insn "tls_tprel_ha_32"
9811 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9812 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9813 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9814 UNSPEC_TLSTPRELHA))]
9815 "HAVE_AS_TLS && !TARGET_64BIT"
9816 "addis %0,%1,%2@tprel@ha")
9817
9818 (define_insn "tls_tprel_ha_64"
9819 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9820 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9821 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9822 UNSPEC_TLSTPRELHA))]
9823 "HAVE_AS_TLS && TARGET_64BIT"
9824 "addis %0,%1,%2@tprel@ha")
9825
9826 (define_insn "tls_tprel_lo_32"
9827 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9828 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9829 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9830 UNSPEC_TLSTPRELLO))]
9831 "HAVE_AS_TLS && !TARGET_64BIT"
9832 "addi %0,%1,%2@tprel@l")
9833
9834 (define_insn "tls_tprel_lo_64"
9835 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9836 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9837 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9838 UNSPEC_TLSTPRELLO))]
9839 "HAVE_AS_TLS && TARGET_64BIT"
9840 "addi %0,%1,%2@tprel@l")
9841
9842 ;; "b" output constraint here and on tls_tls input to support linker tls
9843 ;; optimization. The linker may edit the instructions emitted by a
9844 ;; tls_got_tprel/tls_tls pair to addis,addi.
9845 (define_insn "tls_got_tprel_32"
9846 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9847 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9848 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9849 UNSPEC_TLSGOTTPREL))]
9850 "HAVE_AS_TLS && !TARGET_64BIT"
9851 "lwz %0,%2@got@tprel(%1)")
9852
9853 (define_insn "tls_got_tprel_64"
9854 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9855 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9856 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9857 UNSPEC_TLSGOTTPREL))]
9858 "HAVE_AS_TLS && TARGET_64BIT"
9859 "ld %0,%2@got@tprel(%1)")
9860
9861 (define_insn "tls_tls_32"
9862 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9863 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9864 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9865 UNSPEC_TLSTLS))]
9866 "HAVE_AS_TLS && !TARGET_64BIT"
9867 "add %0,%1,%2@tls")
9868
9869 (define_insn "tls_tls_64"
9870 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9871 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9872 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9873 UNSPEC_TLSTLS))]
9874 "HAVE_AS_TLS && TARGET_64BIT"
9875 "add %0,%1,%2@tls")
9876 \f
9877 ;; Next come insns related to the calling sequence.
9878 ;;
9879 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9880 ;; We move the back-chain and decrement the stack pointer.
9881
9882 (define_expand "allocate_stack"
9883 [(set (match_operand 0 "gpc_reg_operand" "=r")
9884 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9885 (set (reg 1)
9886 (minus (reg 1) (match_dup 1)))]
9887 ""
9888 "
9889 { rtx chain = gen_reg_rtx (Pmode);
9890 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
9891 rtx neg_op0;
9892
9893 emit_move_insn (chain, stack_bot);
9894
9895 /* Check stack bounds if necessary. */
9896 if (current_function_limit_stack)
9897 {
9898 rtx available;
9899 available = expand_binop (Pmode, sub_optab,
9900 stack_pointer_rtx, stack_limit_rtx,
9901 NULL_RTX, 1, OPTAB_WIDEN);
9902 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
9903 }
9904
9905 if (GET_CODE (operands[1]) != CONST_INT
9906 || INTVAL (operands[1]) < -32767
9907 || INTVAL (operands[1]) > 32768)
9908 {
9909 neg_op0 = gen_reg_rtx (Pmode);
9910 if (TARGET_32BIT)
9911 emit_insn (gen_negsi2 (neg_op0, operands[1]));
9912 else
9913 emit_insn (gen_negdi2 (neg_op0, operands[1]));
9914 }
9915 else
9916 neg_op0 = GEN_INT (- INTVAL (operands[1]));
9917
9918 if (TARGET_UPDATE)
9919 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
9920 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
9921
9922 else
9923 {
9924 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
9925 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
9926 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
9927 }
9928
9929 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9930 DONE;
9931 }")
9932
9933 ;; These patterns say how to save and restore the stack pointer. We need not
9934 ;; save the stack pointer at function level since we are careful to
9935 ;; preserve the backchain. At block level, we have to restore the backchain
9936 ;; when we restore the stack pointer.
9937 ;;
9938 ;; For nonlocal gotos, we must save both the stack pointer and its
9939 ;; backchain and restore both. Note that in the nonlocal case, the
9940 ;; save area is a memory location.
9941
9942 (define_expand "save_stack_function"
9943 [(match_operand 0 "any_operand" "")
9944 (match_operand 1 "any_operand" "")]
9945 ""
9946 "DONE;")
9947
9948 (define_expand "restore_stack_function"
9949 [(match_operand 0 "any_operand" "")
9950 (match_operand 1 "any_operand" "")]
9951 ""
9952 "DONE;")
9953
9954 ;; Adjust stack pointer (op0) to a new value (op1).
9955 ;; First copy old stack backchain to new location, and ensure that the
9956 ;; scheduler won't reorder the sp assignment before the backchain write.
9957 (define_expand "restore_stack_block"
9958 [(set (match_dup 2) (match_dup 3))
9959 (set (match_dup 4) (match_dup 2))
9960 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
9961 (set (match_operand 0 "register_operand" "")
9962 (match_operand 1 "register_operand" ""))]
9963 ""
9964 "
9965 {
9966 operands[2] = gen_reg_rtx (Pmode);
9967 operands[3] = gen_frame_mem (Pmode, operands[0]);
9968 operands[4] = gen_frame_mem (Pmode, operands[1]);
9969 operands[5] = gen_frame_mem (BLKmode, operands[0]);
9970 }")
9971
9972 (define_expand "save_stack_nonlocal"
9973 [(set (match_dup 3) (match_dup 4))
9974 (set (match_operand 0 "memory_operand" "") (match_dup 3))
9975 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
9976 ""
9977 "
9978 {
9979 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9980
9981 /* Copy the backchain to the first word, sp to the second. */
9982 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
9983 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
9984 operands[3] = gen_reg_rtx (Pmode);
9985 operands[4] = gen_frame_mem (Pmode, operands[1]);
9986 }")
9987
9988 (define_expand "restore_stack_nonlocal"
9989 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
9990 (set (match_dup 3) (match_dup 4))
9991 (set (match_dup 5) (match_dup 2))
9992 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
9993 (set (match_operand 0 "register_operand" "") (match_dup 3))]
9994 ""
9995 "
9996 {
9997 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9998
9999 /* Restore the backchain from the first word, sp from the second. */
10000 operands[2] = gen_reg_rtx (Pmode);
10001 operands[3] = gen_reg_rtx (Pmode);
10002 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10003 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10004 operands[5] = gen_frame_mem (Pmode, operands[3]);
10005 operands[6] = gen_frame_mem (BLKmode, operands[0]);
10006 }")
10007 \f
10008 ;; TOC register handling.
10009
10010 ;; Code to initialize the TOC register...
10011
10012 (define_insn "load_toc_aix_si"
10013 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10014 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10015 (use (reg:SI 2))])]
10016 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10017 "*
10018 {
10019 char buf[30];
10020 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10021 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10022 operands[2] = gen_rtx_REG (Pmode, 2);
10023 return \"{l|lwz} %0,%1(%2)\";
10024 }"
10025 [(set_attr "type" "load")])
10026
10027 (define_insn "load_toc_aix_di"
10028 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10029 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10030 (use (reg:DI 2))])]
10031 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10032 "*
10033 {
10034 char buf[30];
10035 #ifdef TARGET_RELOCATABLE
10036 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10037 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10038 #else
10039 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10040 #endif
10041 if (TARGET_ELF)
10042 strcat (buf, \"@toc\");
10043 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10044 operands[2] = gen_rtx_REG (Pmode, 2);
10045 return \"ld %0,%1(%2)\";
10046 }"
10047 [(set_attr "type" "load")])
10048
10049 (define_insn "load_toc_v4_pic_si"
10050 [(set (match_operand:SI 0 "register_operand" "=l")
10051 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10052 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10053 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10054 [(set_attr "type" "branch")
10055 (set_attr "length" "4")])
10056
10057 (define_insn "load_toc_v4_PIC_1"
10058 [(set (match_operand:SI 0 "register_operand" "=l")
10059 (match_operand:SI 1 "immediate_operand" "s"))
10060 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
10061 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
10062 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10063 "bcl 20,31,%1\\n%1:"
10064 [(set_attr "type" "branch")
10065 (set_attr "length" "4")])
10066
10067 (define_insn "load_toc_v4_PIC_1b"
10068 [(set (match_operand:SI 0 "register_operand" "=l")
10069 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
10070 UNSPEC_TOCPTR))]
10071 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10072 "bcl 20,31,$+8\\n\\t.long %1-$"
10073 [(set_attr "type" "branch")
10074 (set_attr "length" "8")])
10075
10076 (define_insn "load_toc_v4_PIC_2"
10077 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10078 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10079 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10080 (match_operand:SI 3 "immediate_operand" "s")))))]
10081 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10082 "{l|lwz} %0,%2-%3(%1)"
10083 [(set_attr "type" "load")])
10084
10085 (define_insn "load_toc_v4_PIC_3b"
10086 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10087 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10088 (high:SI
10089 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10090 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10091 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10092 "{cau|addis} %0,%1,%2-%3@ha")
10093
10094 (define_insn "load_toc_v4_PIC_3c"
10095 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10096 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10097 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10098 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10099 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10100 "{cal|addi} %0,%1,%2-%3@l")
10101
10102 ;; If the TOC is shared over a translation unit, as happens with all
10103 ;; the kinds of PIC that we support, we need to restore the TOC
10104 ;; pointer only when jumping over units of translation.
10105 ;; On Darwin, we need to reload the picbase.
10106
10107 (define_expand "builtin_setjmp_receiver"
10108 [(use (label_ref (match_operand 0 "" "")))]
10109 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10110 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10111 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10112 "
10113 {
10114 #if TARGET_MACHO
10115 if (DEFAULT_ABI == ABI_DARWIN)
10116 {
10117 const char *picbase = machopic_function_base_name ();
10118 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
10119 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10120 rtx tmplabrtx;
10121 char tmplab[20];
10122
10123 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10124 CODE_LABEL_NUMBER (operands[0]));
10125 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10126
10127 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
10128 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10129 }
10130 else
10131 #endif
10132 rs6000_emit_load_toc_table (FALSE);
10133 DONE;
10134 }")
10135
10136 ;; Elf specific ways of loading addresses for non-PIC code.
10137 ;; The output of this could be r0, but we make a very strong
10138 ;; preference for a base register because it will usually
10139 ;; be needed there.
10140 (define_insn "elf_high"
10141 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10142 (high:SI (match_operand 1 "" "")))]
10143 "TARGET_ELF && ! TARGET_64BIT"
10144 "{liu|lis} %0,%1@ha")
10145
10146 (define_insn "elf_low"
10147 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10148 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10149 (match_operand 2 "" "")))]
10150 "TARGET_ELF && ! TARGET_64BIT"
10151 "@
10152 {cal|la} %0,%2@l(%1)
10153 {ai|addic} %0,%1,%K2")
10154 \f
10155 ;; A function pointer under AIX is a pointer to a data area whose first word
10156 ;; contains the actual address of the function, whose second word contains a
10157 ;; pointer to its TOC, and whose third word contains a value to place in the
10158 ;; static chain register (r11). Note that if we load the static chain, our
10159 ;; "trampoline" need not have any executable code.
10160
10161 (define_expand "call_indirect_aix32"
10162 [(set (match_dup 2)
10163 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10164 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10165 (reg:SI 2))
10166 (set (reg:SI 2)
10167 (mem:SI (plus:SI (match_dup 0)
10168 (const_int 4))))
10169 (set (reg:SI 11)
10170 (mem:SI (plus:SI (match_dup 0)
10171 (const_int 8))))
10172 (parallel [(call (mem:SI (match_dup 2))
10173 (match_operand 1 "" ""))
10174 (use (reg:SI 2))
10175 (use (reg:SI 11))
10176 (set (reg:SI 2)
10177 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10178 (clobber (scratch:SI))])]
10179 "TARGET_32BIT"
10180 "
10181 { operands[2] = gen_reg_rtx (SImode); }")
10182
10183 (define_expand "call_indirect_aix64"
10184 [(set (match_dup 2)
10185 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10186 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10187 (reg:DI 2))
10188 (set (reg:DI 2)
10189 (mem:DI (plus:DI (match_dup 0)
10190 (const_int 8))))
10191 (set (reg:DI 11)
10192 (mem:DI (plus:DI (match_dup 0)
10193 (const_int 16))))
10194 (parallel [(call (mem:SI (match_dup 2))
10195 (match_operand 1 "" ""))
10196 (use (reg:DI 2))
10197 (use (reg:DI 11))
10198 (set (reg:DI 2)
10199 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10200 (clobber (scratch:SI))])]
10201 "TARGET_64BIT"
10202 "
10203 { operands[2] = gen_reg_rtx (DImode); }")
10204
10205 (define_expand "call_value_indirect_aix32"
10206 [(set (match_dup 3)
10207 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10208 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10209 (reg:SI 2))
10210 (set (reg:SI 2)
10211 (mem:SI (plus:SI (match_dup 1)
10212 (const_int 4))))
10213 (set (reg:SI 11)
10214 (mem:SI (plus:SI (match_dup 1)
10215 (const_int 8))))
10216 (parallel [(set (match_operand 0 "" "")
10217 (call (mem:SI (match_dup 3))
10218 (match_operand 2 "" "")))
10219 (use (reg:SI 2))
10220 (use (reg:SI 11))
10221 (set (reg:SI 2)
10222 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10223 (clobber (scratch:SI))])]
10224 "TARGET_32BIT"
10225 "
10226 { operands[3] = gen_reg_rtx (SImode); }")
10227
10228 (define_expand "call_value_indirect_aix64"
10229 [(set (match_dup 3)
10230 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10231 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10232 (reg:DI 2))
10233 (set (reg:DI 2)
10234 (mem:DI (plus:DI (match_dup 1)
10235 (const_int 8))))
10236 (set (reg:DI 11)
10237 (mem:DI (plus:DI (match_dup 1)
10238 (const_int 16))))
10239 (parallel [(set (match_operand 0 "" "")
10240 (call (mem:SI (match_dup 3))
10241 (match_operand 2 "" "")))
10242 (use (reg:DI 2))
10243 (use (reg:DI 11))
10244 (set (reg:DI 2)
10245 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10246 (clobber (scratch:SI))])]
10247 "TARGET_64BIT"
10248 "
10249 { operands[3] = gen_reg_rtx (DImode); }")
10250
10251 ;; Now the definitions for the call and call_value insns
10252 (define_expand "call"
10253 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10254 (match_operand 1 "" ""))
10255 (use (match_operand 2 "" ""))
10256 (clobber (scratch:SI))])]
10257 ""
10258 "
10259 {
10260 #if TARGET_MACHO
10261 if (MACHOPIC_INDIRECT)
10262 operands[0] = machopic_indirect_call_target (operands[0]);
10263 #endif
10264
10265 gcc_assert (GET_CODE (operands[0]) == MEM);
10266 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10267
10268 operands[0] = XEXP (operands[0], 0);
10269
10270 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10271 && flag_pic
10272 && GET_CODE (operands[0]) == SYMBOL_REF
10273 && !SYMBOL_REF_LOCAL_P (operands[0]))
10274 {
10275 rtx call;
10276 rtvec tmp;
10277
10278 tmp = gen_rtvec (3,
10279 gen_rtx_CALL (VOIDmode,
10280 gen_rtx_MEM (SImode, operands[0]),
10281 operands[1]),
10282 gen_rtx_USE (VOIDmode, operands[2]),
10283 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
10284 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10285 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10286 DONE;
10287 }
10288
10289 if (GET_CODE (operands[0]) != SYMBOL_REF
10290 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10291 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10292 {
10293 if (INTVAL (operands[2]) & CALL_LONG)
10294 operands[0] = rs6000_longcall_ref (operands[0]);
10295
10296 switch (DEFAULT_ABI)
10297 {
10298 case ABI_V4:
10299 case ABI_DARWIN:
10300 operands[0] = force_reg (Pmode, operands[0]);
10301 break;
10302
10303 case ABI_AIX:
10304 /* AIX function pointers are really pointers to a three word
10305 area. */
10306 emit_call_insn (TARGET_32BIT
10307 ? gen_call_indirect_aix32 (force_reg (SImode,
10308 operands[0]),
10309 operands[1])
10310 : gen_call_indirect_aix64 (force_reg (DImode,
10311 operands[0]),
10312 operands[1]));
10313 DONE;
10314
10315 default:
10316 gcc_unreachable ();
10317 }
10318 }
10319 }")
10320
10321 (define_expand "call_value"
10322 [(parallel [(set (match_operand 0 "" "")
10323 (call (mem:SI (match_operand 1 "address_operand" ""))
10324 (match_operand 2 "" "")))
10325 (use (match_operand 3 "" ""))
10326 (clobber (scratch:SI))])]
10327 ""
10328 "
10329 {
10330 #if TARGET_MACHO
10331 if (MACHOPIC_INDIRECT)
10332 operands[1] = machopic_indirect_call_target (operands[1]);
10333 #endif
10334
10335 gcc_assert (GET_CODE (operands[1]) == MEM);
10336 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10337
10338 operands[1] = XEXP (operands[1], 0);
10339
10340 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10341 && flag_pic
10342 && GET_CODE (operands[1]) == SYMBOL_REF
10343 && !SYMBOL_REF_LOCAL_P (operands[1]))
10344 {
10345 rtx call;
10346 rtvec tmp;
10347
10348 tmp = gen_rtvec (3,
10349 gen_rtx_SET (VOIDmode,
10350 operands[0],
10351 gen_rtx_CALL (VOIDmode,
10352 gen_rtx_MEM (SImode,
10353 operands[1]),
10354 operands[2])),
10355 gen_rtx_USE (VOIDmode, operands[3]),
10356 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
10357 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10358 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10359 DONE;
10360 }
10361
10362 if (GET_CODE (operands[1]) != SYMBOL_REF
10363 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10364 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10365 {
10366 if (INTVAL (operands[3]) & CALL_LONG)
10367 operands[1] = rs6000_longcall_ref (operands[1]);
10368
10369 switch (DEFAULT_ABI)
10370 {
10371 case ABI_V4:
10372 case ABI_DARWIN:
10373 operands[1] = force_reg (Pmode, operands[1]);
10374 break;
10375
10376 case ABI_AIX:
10377 /* AIX function pointers are really pointers to a three word
10378 area. */
10379 emit_call_insn (TARGET_32BIT
10380 ? gen_call_value_indirect_aix32 (operands[0],
10381 force_reg (SImode,
10382 operands[1]),
10383 operands[2])
10384 : gen_call_value_indirect_aix64 (operands[0],
10385 force_reg (DImode,
10386 operands[1]),
10387 operands[2]));
10388 DONE;
10389
10390 default:
10391 gcc_unreachable ();
10392 }
10393 }
10394 }")
10395
10396 ;; Call to function in current module. No TOC pointer reload needed.
10397 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10398 ;; either the function was not prototyped, or it was prototyped as a
10399 ;; variable argument function. It is > 0 if FP registers were passed
10400 ;; and < 0 if they were not.
10401
10402 (define_insn "*call_local32"
10403 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10404 (match_operand 1 "" "g,g"))
10405 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10406 (clobber (match_scratch:SI 3 "=l,l"))]
10407 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10408 "*
10409 {
10410 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10411 output_asm_insn (\"crxor 6,6,6\", operands);
10412
10413 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10414 output_asm_insn (\"creqv 6,6,6\", operands);
10415
10416 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10417 }"
10418 [(set_attr "type" "branch")
10419 (set_attr "length" "4,8")])
10420
10421 (define_insn "*call_local64"
10422 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10423 (match_operand 1 "" "g,g"))
10424 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10425 (clobber (match_scratch:SI 3 "=l,l"))]
10426 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10427 "*
10428 {
10429 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10430 output_asm_insn (\"crxor 6,6,6\", operands);
10431
10432 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10433 output_asm_insn (\"creqv 6,6,6\", operands);
10434
10435 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10436 }"
10437 [(set_attr "type" "branch")
10438 (set_attr "length" "4,8")])
10439
10440 (define_insn "*call_value_local32"
10441 [(set (match_operand 0 "" "")
10442 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10443 (match_operand 2 "" "g,g")))
10444 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10445 (clobber (match_scratch:SI 4 "=l,l"))]
10446 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10447 "*
10448 {
10449 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10450 output_asm_insn (\"crxor 6,6,6\", operands);
10451
10452 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10453 output_asm_insn (\"creqv 6,6,6\", operands);
10454
10455 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10456 }"
10457 [(set_attr "type" "branch")
10458 (set_attr "length" "4,8")])
10459
10460
10461 (define_insn "*call_value_local64"
10462 [(set (match_operand 0 "" "")
10463 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10464 (match_operand 2 "" "g,g")))
10465 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10466 (clobber (match_scratch:SI 4 "=l,l"))]
10467 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10468 "*
10469 {
10470 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10471 output_asm_insn (\"crxor 6,6,6\", operands);
10472
10473 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10474 output_asm_insn (\"creqv 6,6,6\", operands);
10475
10476 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10477 }"
10478 [(set_attr "type" "branch")
10479 (set_attr "length" "4,8")])
10480
10481 ;; Call to function which may be in another module. Restore the TOC
10482 ;; pointer (r2) after the call unless this is System V.
10483 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10484 ;; either the function was not prototyped, or it was prototyped as a
10485 ;; variable argument function. It is > 0 if FP registers were passed
10486 ;; and < 0 if they were not.
10487
10488 (define_insn "*call_indirect_nonlocal_aix32"
10489 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
10490 (match_operand 1 "" "g,g"))
10491 (use (reg:SI 2))
10492 (use (reg:SI 11))
10493 (set (reg:SI 2)
10494 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10495 (clobber (match_scratch:SI 2 "=l,l"))]
10496 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10497 "b%T0l\;{l|lwz} 2,20(1)"
10498 [(set_attr "type" "jmpreg")
10499 (set_attr "length" "8")])
10500
10501 (define_insn "*call_nonlocal_aix32"
10502 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10503 (match_operand 1 "" "g"))
10504 (use (match_operand:SI 2 "immediate_operand" "O"))
10505 (clobber (match_scratch:SI 3 "=l"))]
10506 "TARGET_32BIT
10507 && DEFAULT_ABI == ABI_AIX
10508 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10509 "bl %z0\;%."
10510 [(set_attr "type" "branch")
10511 (set_attr "length" "8")])
10512
10513 (define_insn "*call_indirect_nonlocal_aix64"
10514 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
10515 (match_operand 1 "" "g,g"))
10516 (use (reg:DI 2))
10517 (use (reg:DI 11))
10518 (set (reg:DI 2)
10519 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10520 (clobber (match_scratch:SI 2 "=l,l"))]
10521 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10522 "b%T0l\;ld 2,40(1)"
10523 [(set_attr "type" "jmpreg")
10524 (set_attr "length" "8")])
10525
10526 (define_insn "*call_nonlocal_aix64"
10527 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10528 (match_operand 1 "" "g"))
10529 (use (match_operand:SI 2 "immediate_operand" "O"))
10530 (clobber (match_scratch:SI 3 "=l"))]
10531 "TARGET_64BIT
10532 && DEFAULT_ABI == ABI_AIX
10533 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10534 "bl %z0\;%."
10535 [(set_attr "type" "branch")
10536 (set_attr "length" "8")])
10537
10538 (define_insn "*call_value_indirect_nonlocal_aix32"
10539 [(set (match_operand 0 "" "")
10540 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
10541 (match_operand 2 "" "g,g")))
10542 (use (reg:SI 2))
10543 (use (reg:SI 11))
10544 (set (reg:SI 2)
10545 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10546 (clobber (match_scratch:SI 3 "=l,l"))]
10547 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10548 "b%T1l\;{l|lwz} 2,20(1)"
10549 [(set_attr "type" "jmpreg")
10550 (set_attr "length" "8")])
10551
10552 (define_insn "*call_value_nonlocal_aix32"
10553 [(set (match_operand 0 "" "")
10554 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10555 (match_operand 2 "" "g")))
10556 (use (match_operand:SI 3 "immediate_operand" "O"))
10557 (clobber (match_scratch:SI 4 "=l"))]
10558 "TARGET_32BIT
10559 && DEFAULT_ABI == ABI_AIX
10560 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10561 "bl %z1\;%."
10562 [(set_attr "type" "branch")
10563 (set_attr "length" "8")])
10564
10565 (define_insn "*call_value_indirect_nonlocal_aix64"
10566 [(set (match_operand 0 "" "")
10567 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
10568 (match_operand 2 "" "g,g")))
10569 (use (reg:DI 2))
10570 (use (reg:DI 11))
10571 (set (reg:DI 2)
10572 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10573 (clobber (match_scratch:SI 3 "=l,l"))]
10574 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10575 "b%T1l\;ld 2,40(1)"
10576 [(set_attr "type" "jmpreg")
10577 (set_attr "length" "8")])
10578
10579 (define_insn "*call_value_nonlocal_aix64"
10580 [(set (match_operand 0 "" "")
10581 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10582 (match_operand 2 "" "g")))
10583 (use (match_operand:SI 3 "immediate_operand" "O"))
10584 (clobber (match_scratch:SI 4 "=l"))]
10585 "TARGET_64BIT
10586 && DEFAULT_ABI == ABI_AIX
10587 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10588 "bl %z1\;%."
10589 [(set_attr "type" "branch")
10590 (set_attr "length" "8")])
10591
10592 ;; A function pointer under System V is just a normal pointer
10593 ;; operands[0] is the function pointer
10594 ;; operands[1] is the stack size to clean up
10595 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10596 ;; which indicates how to set cr1
10597
10598 (define_insn "*call_indirect_nonlocal_sysv"
10599 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l,c,*l"))
10600 (match_operand 1 "" "g,g,g,g"))
10601 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
10602 (clobber (match_scratch:SI 3 "=l,l,l,l"))]
10603 "DEFAULT_ABI == ABI_V4
10604 || DEFAULT_ABI == ABI_DARWIN"
10605 {
10606 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10607 output_asm_insn ("crxor 6,6,6", operands);
10608
10609 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10610 output_asm_insn ("creqv 6,6,6", operands);
10611
10612 return "b%T0l";
10613 }
10614 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10615 (set_attr "length" "4,4,8,8")])
10616
10617 (define_insn "*call_nonlocal_sysv"
10618 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10619 (match_operand 1 "" "g,g"))
10620 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10621 (clobber (match_scratch:SI 3 "=l,l"))]
10622 "(DEFAULT_ABI == ABI_DARWIN
10623 || (DEFAULT_ABI == ABI_V4
10624 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10625 {
10626 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10627 output_asm_insn ("crxor 6,6,6", operands);
10628
10629 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10630 output_asm_insn ("creqv 6,6,6", operands);
10631
10632 #if TARGET_MACHO
10633 return output_call(insn, operands, 0, 2);
10634 #else
10635 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10636 {
10637 if (TARGET_SECURE_PLT && flag_pic == 2)
10638 /* The magic 32768 offset here and in the other sysv call insns
10639 corresponds to the offset of r30 in .got2, as given by LCTOC1.
10640 See sysv4.h:toc_section. */
10641 return "bl %z0+32768@plt";
10642 else
10643 return "bl %z0@plt";
10644 }
10645 else
10646 return "bl %z0";
10647 #endif
10648 }
10649 [(set_attr "type" "branch,branch")
10650 (set_attr "length" "4,8")])
10651
10652 (define_insn "*call_value_indirect_nonlocal_sysv"
10653 [(set (match_operand 0 "" "")
10654 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l,c,*l"))
10655 (match_operand 2 "" "g,g,g,g")))
10656 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
10657 (clobber (match_scratch:SI 4 "=l,l,l,l"))]
10658 "DEFAULT_ABI == ABI_V4
10659 || DEFAULT_ABI == ABI_DARWIN"
10660 {
10661 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10662 output_asm_insn ("crxor 6,6,6", operands);
10663
10664 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10665 output_asm_insn ("creqv 6,6,6", operands);
10666
10667 return "b%T1l";
10668 }
10669 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10670 (set_attr "length" "4,4,8,8")])
10671
10672 (define_insn "*call_value_nonlocal_sysv"
10673 [(set (match_operand 0 "" "")
10674 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10675 (match_operand 2 "" "g,g")))
10676 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10677 (clobber (match_scratch:SI 4 "=l,l"))]
10678 "(DEFAULT_ABI == ABI_DARWIN
10679 || (DEFAULT_ABI == ABI_V4
10680 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10681 {
10682 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10683 output_asm_insn ("crxor 6,6,6", operands);
10684
10685 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10686 output_asm_insn ("creqv 6,6,6", operands);
10687
10688 #if TARGET_MACHO
10689 return output_call(insn, operands, 1, 3);
10690 #else
10691 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10692 {
10693 if (TARGET_SECURE_PLT && flag_pic == 2)
10694 return "bl %z1+32768@plt";
10695 else
10696 return "bl %z1@plt";
10697 }
10698 else
10699 return "bl %z1";
10700 #endif
10701 }
10702 [(set_attr "type" "branch,branch")
10703 (set_attr "length" "4,8")])
10704
10705 ;; Call subroutine returning any type.
10706 (define_expand "untyped_call"
10707 [(parallel [(call (match_operand 0 "" "")
10708 (const_int 0))
10709 (match_operand 1 "" "")
10710 (match_operand 2 "" "")])]
10711 ""
10712 "
10713 {
10714 int i;
10715
10716 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10717
10718 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10719 {
10720 rtx set = XVECEXP (operands[2], 0, i);
10721 emit_move_insn (SET_DEST (set), SET_SRC (set));
10722 }
10723
10724 /* The optimizer does not know that the call sets the function value
10725 registers we stored in the result block. We avoid problems by
10726 claiming that all hard registers are used and clobbered at this
10727 point. */
10728 emit_insn (gen_blockage ());
10729
10730 DONE;
10731 }")
10732
10733 ;; sibling call patterns
10734 (define_expand "sibcall"
10735 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10736 (match_operand 1 "" ""))
10737 (use (match_operand 2 "" ""))
10738 (use (match_operand 3 "" ""))
10739 (return)])]
10740 ""
10741 "
10742 {
10743 #if TARGET_MACHO
10744 if (MACHOPIC_INDIRECT)
10745 operands[0] = machopic_indirect_call_target (operands[0]);
10746 #endif
10747
10748 gcc_assert (GET_CODE (operands[0]) == MEM);
10749 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10750
10751 operands[0] = XEXP (operands[0], 0);
10752 operands[3] = gen_reg_rtx (SImode);
10753
10754 }")
10755
10756 ;; this and similar patterns must be marked as using LR, otherwise
10757 ;; dataflow will try to delete the store into it. This is true
10758 ;; even when the actual reg to jump to is in CTR, when LR was
10759 ;; saved and restored around the PIC-setting BCL.
10760 (define_insn "*sibcall_local32"
10761 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10762 (match_operand 1 "" "g,g"))
10763 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10764 (use (match_operand:SI 3 "register_operand" "l,l"))
10765 (return)]
10766 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10767 "*
10768 {
10769 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10770 output_asm_insn (\"crxor 6,6,6\", operands);
10771
10772 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10773 output_asm_insn (\"creqv 6,6,6\", operands);
10774
10775 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10776 }"
10777 [(set_attr "type" "branch")
10778 (set_attr "length" "4,8")])
10779
10780 (define_insn "*sibcall_local64"
10781 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10782 (match_operand 1 "" "g,g"))
10783 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10784 (use (match_operand:SI 3 "register_operand" "l,l"))
10785 (return)]
10786 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10787 "*
10788 {
10789 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10790 output_asm_insn (\"crxor 6,6,6\", operands);
10791
10792 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10793 output_asm_insn (\"creqv 6,6,6\", operands);
10794
10795 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10796 }"
10797 [(set_attr "type" "branch")
10798 (set_attr "length" "4,8")])
10799
10800 (define_insn "*sibcall_value_local32"
10801 [(set (match_operand 0 "" "")
10802 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10803 (match_operand 2 "" "g,g")))
10804 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10805 (use (match_operand:SI 4 "register_operand" "l,l"))
10806 (return)]
10807 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10808 "*
10809 {
10810 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10811 output_asm_insn (\"crxor 6,6,6\", operands);
10812
10813 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10814 output_asm_insn (\"creqv 6,6,6\", operands);
10815
10816 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10817 }"
10818 [(set_attr "type" "branch")
10819 (set_attr "length" "4,8")])
10820
10821
10822 (define_insn "*sibcall_value_local64"
10823 [(set (match_operand 0 "" "")
10824 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10825 (match_operand 2 "" "g,g")))
10826 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10827 (use (match_operand:SI 4 "register_operand" "l,l"))
10828 (return)]
10829 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10830 "*
10831 {
10832 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10833 output_asm_insn (\"crxor 6,6,6\", operands);
10834
10835 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10836 output_asm_insn (\"creqv 6,6,6\", operands);
10837
10838 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10839 }"
10840 [(set_attr "type" "branch")
10841 (set_attr "length" "4,8")])
10842
10843 (define_insn "*sibcall_nonlocal_aix32"
10844 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10845 (match_operand 1 "" "g"))
10846 (use (match_operand:SI 2 "immediate_operand" "O"))
10847 (use (match_operand:SI 3 "register_operand" "l"))
10848 (return)]
10849 "TARGET_32BIT
10850 && DEFAULT_ABI == ABI_AIX
10851 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10852 "b %z0"
10853 [(set_attr "type" "branch")
10854 (set_attr "length" "4")])
10855
10856 (define_insn "*sibcall_nonlocal_aix64"
10857 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10858 (match_operand 1 "" "g"))
10859 (use (match_operand:SI 2 "immediate_operand" "O"))
10860 (use (match_operand:SI 3 "register_operand" "l"))
10861 (return)]
10862 "TARGET_64BIT
10863 && DEFAULT_ABI == ABI_AIX
10864 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10865 "b %z0"
10866 [(set_attr "type" "branch")
10867 (set_attr "length" "4")])
10868
10869 (define_insn "*sibcall_value_nonlocal_aix32"
10870 [(set (match_operand 0 "" "")
10871 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10872 (match_operand 2 "" "g")))
10873 (use (match_operand:SI 3 "immediate_operand" "O"))
10874 (use (match_operand:SI 4 "register_operand" "l"))
10875 (return)]
10876 "TARGET_32BIT
10877 && DEFAULT_ABI == ABI_AIX
10878 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10879 "b %z1"
10880 [(set_attr "type" "branch")
10881 (set_attr "length" "4")])
10882
10883 (define_insn "*sibcall_value_nonlocal_aix64"
10884 [(set (match_operand 0 "" "")
10885 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10886 (match_operand 2 "" "g")))
10887 (use (match_operand:SI 3 "immediate_operand" "O"))
10888 (use (match_operand:SI 4 "register_operand" "l"))
10889 (return)]
10890 "TARGET_64BIT
10891 && DEFAULT_ABI == ABI_AIX
10892 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10893 "b %z1"
10894 [(set_attr "type" "branch")
10895 (set_attr "length" "4")])
10896
10897 (define_insn "*sibcall_nonlocal_sysv"
10898 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10899 (match_operand 1 "" ""))
10900 (use (match_operand 2 "immediate_operand" "O,n"))
10901 (use (match_operand:SI 3 "register_operand" "l,l"))
10902 (return)]
10903 "(DEFAULT_ABI == ABI_DARWIN
10904 || DEFAULT_ABI == ABI_V4)
10905 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10906 "*
10907 {
10908 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10909 output_asm_insn (\"crxor 6,6,6\", operands);
10910
10911 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10912 output_asm_insn (\"creqv 6,6,6\", operands);
10913
10914 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10915 {
10916 if (TARGET_SECURE_PLT && flag_pic == 2)
10917 return \"b %z0+32768@plt\";
10918 else
10919 return \"b %z0@plt\";
10920 }
10921 else
10922 return \"b %z0\";
10923 }"
10924 [(set_attr "type" "branch,branch")
10925 (set_attr "length" "4,8")])
10926
10927 (define_expand "sibcall_value"
10928 [(parallel [(set (match_operand 0 "register_operand" "")
10929 (call (mem:SI (match_operand 1 "address_operand" ""))
10930 (match_operand 2 "" "")))
10931 (use (match_operand 3 "" ""))
10932 (use (match_operand 4 "" ""))
10933 (return)])]
10934 ""
10935 "
10936 {
10937 #if TARGET_MACHO
10938 if (MACHOPIC_INDIRECT)
10939 operands[1] = machopic_indirect_call_target (operands[1]);
10940 #endif
10941
10942 gcc_assert (GET_CODE (operands[1]) == MEM);
10943 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10944
10945 operands[1] = XEXP (operands[1], 0);
10946 operands[4] = gen_reg_rtx (SImode);
10947
10948 }")
10949
10950 (define_insn "*sibcall_value_nonlocal_sysv"
10951 [(set (match_operand 0 "" "")
10952 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10953 (match_operand 2 "" "")))
10954 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10955 (use (match_operand:SI 4 "register_operand" "l,l"))
10956 (return)]
10957 "(DEFAULT_ABI == ABI_DARWIN
10958 || DEFAULT_ABI == ABI_V4)
10959 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10960 "*
10961 {
10962 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10963 output_asm_insn (\"crxor 6,6,6\", operands);
10964
10965 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10966 output_asm_insn (\"creqv 6,6,6\", operands);
10967
10968 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10969 {
10970 if (TARGET_SECURE_PLT && flag_pic == 2)
10971 return \"b %z1+32768@plt\";
10972 else
10973 return \"b %z1@plt\";
10974 }
10975 else
10976 return \"b %z1\";
10977 }"
10978 [(set_attr "type" "branch,branch")
10979 (set_attr "length" "4,8")])
10980
10981 (define_expand "sibcall_epilogue"
10982 [(use (const_int 0))]
10983 "TARGET_SCHED_PROLOG"
10984 "
10985 {
10986 rs6000_emit_epilogue (TRUE);
10987 DONE;
10988 }")
10989
10990 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10991 ;; all of memory. This blocks insns from being moved across this point.
10992
10993 (define_insn "blockage"
10994 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
10995 ""
10996 "")
10997 \f
10998 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
10999 ;; signed & unsigned, and one type of branch.
11000 ;;
11001 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11002 ;; insns, and branches. We store the operands of compares until we see
11003 ;; how it is used.
11004 (define_expand "cmp<mode>"
11005 [(set (cc0)
11006 (compare (match_operand:GPR 0 "gpc_reg_operand" "")
11007 (match_operand:GPR 1 "reg_or_short_operand" "")))]
11008 ""
11009 "
11010 {
11011 /* Take care of the possibility that operands[1] might be negative but
11012 this might be a logical operation. That insn doesn't exist. */
11013 if (GET_CODE (operands[1]) == CONST_INT
11014 && INTVAL (operands[1]) < 0)
11015 operands[1] = force_reg (<MODE>mode, operands[1]);
11016
11017 rs6000_compare_op0 = operands[0];
11018 rs6000_compare_op1 = operands[1];
11019 rs6000_compare_fp_p = 0;
11020 DONE;
11021 }")
11022
11023 (define_expand "cmp<mode>"
11024 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
11025 (match_operand:FP 1 "gpc_reg_operand" "")))]
11026 ""
11027 "
11028 {
11029 rs6000_compare_op0 = operands[0];
11030 rs6000_compare_op1 = operands[1];
11031 rs6000_compare_fp_p = 1;
11032 DONE;
11033 }")
11034
11035 (define_expand "beq"
11036 [(use (match_operand 0 "" ""))]
11037 ""
11038 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
11039
11040 (define_expand "bne"
11041 [(use (match_operand 0 "" ""))]
11042 ""
11043 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
11044
11045 (define_expand "bge"
11046 [(use (match_operand 0 "" ""))]
11047 ""
11048 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
11049
11050 (define_expand "bgt"
11051 [(use (match_operand 0 "" ""))]
11052 ""
11053 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
11054
11055 (define_expand "ble"
11056 [(use (match_operand 0 "" ""))]
11057 ""
11058 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
11059
11060 (define_expand "blt"
11061 [(use (match_operand 0 "" ""))]
11062 ""
11063 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
11064
11065 (define_expand "bgeu"
11066 [(use (match_operand 0 "" ""))]
11067 ""
11068 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
11069
11070 (define_expand "bgtu"
11071 [(use (match_operand 0 "" ""))]
11072 ""
11073 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
11074
11075 (define_expand "bleu"
11076 [(use (match_operand 0 "" ""))]
11077 ""
11078 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
11079
11080 (define_expand "bltu"
11081 [(use (match_operand 0 "" ""))]
11082 ""
11083 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
11084
11085 (define_expand "bunordered"
11086 [(use (match_operand 0 "" ""))]
11087 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11088 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
11089
11090 (define_expand "bordered"
11091 [(use (match_operand 0 "" ""))]
11092 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11093 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
11094
11095 (define_expand "buneq"
11096 [(use (match_operand 0 "" ""))]
11097 ""
11098 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
11099
11100 (define_expand "bunge"
11101 [(use (match_operand 0 "" ""))]
11102 ""
11103 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
11104
11105 (define_expand "bungt"
11106 [(use (match_operand 0 "" ""))]
11107 ""
11108 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
11109
11110 (define_expand "bunle"
11111 [(use (match_operand 0 "" ""))]
11112 ""
11113 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
11114
11115 (define_expand "bunlt"
11116 [(use (match_operand 0 "" ""))]
11117 ""
11118 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
11119
11120 (define_expand "bltgt"
11121 [(use (match_operand 0 "" ""))]
11122 ""
11123 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
11124
11125 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11126 ;; For SEQ, likewise, except that comparisons with zero should be done
11127 ;; with an scc insns. However, due to the order that combine see the
11128 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11129 ;; the cases we don't want to handle.
11130 (define_expand "seq"
11131 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11132 ""
11133 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
11134
11135 (define_expand "sne"
11136 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11137 ""
11138 "
11139 {
11140 if (! rs6000_compare_fp_p)
11141 FAIL;
11142
11143 rs6000_emit_sCOND (NE, operands[0]);
11144 DONE;
11145 }")
11146
11147 ;; A >= 0 is best done the portable way for A an integer.
11148 (define_expand "sge"
11149 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11150 ""
11151 "
11152 {
11153 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11154 FAIL;
11155
11156 rs6000_emit_sCOND (GE, operands[0]);
11157 DONE;
11158 }")
11159
11160 ;; A > 0 is best done using the portable sequence, so fail in that case.
11161 (define_expand "sgt"
11162 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11163 ""
11164 "
11165 {
11166 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11167 FAIL;
11168
11169 rs6000_emit_sCOND (GT, operands[0]);
11170 DONE;
11171 }")
11172
11173 ;; A <= 0 is best done the portable way for A an integer.
11174 (define_expand "sle"
11175 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11176 ""
11177 "
11178 {
11179 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11180 FAIL;
11181
11182 rs6000_emit_sCOND (LE, operands[0]);
11183 DONE;
11184 }")
11185
11186 ;; A < 0 is best done in the portable way for A an integer.
11187 (define_expand "slt"
11188 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11189 ""
11190 "
11191 {
11192 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11193 FAIL;
11194
11195 rs6000_emit_sCOND (LT, operands[0]);
11196 DONE;
11197 }")
11198
11199 (define_expand "sgeu"
11200 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11201 ""
11202 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11203
11204 (define_expand "sgtu"
11205 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11206 ""
11207 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
11208
11209 (define_expand "sleu"
11210 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11211 ""
11212 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11213
11214 (define_expand "sltu"
11215 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11216 ""
11217 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
11218
11219 (define_expand "sunordered"
11220 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11221 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11222 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
11223
11224 (define_expand "sordered"
11225 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11226 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11227 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11228
11229 (define_expand "suneq"
11230 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11231 ""
11232 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11233
11234 (define_expand "sunge"
11235 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11236 ""
11237 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11238
11239 (define_expand "sungt"
11240 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11241 ""
11242 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11243
11244 (define_expand "sunle"
11245 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11246 ""
11247 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11248
11249 (define_expand "sunlt"
11250 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11251 ""
11252 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11253
11254 (define_expand "sltgt"
11255 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11256 ""
11257 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11258
11259 (define_expand "stack_protect_set"
11260 [(match_operand 0 "memory_operand" "")
11261 (match_operand 1 "memory_operand" "")]
11262 ""
11263 {
11264 #ifdef TARGET_THREAD_SSP_OFFSET
11265 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11266 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11267 operands[1] = gen_rtx_MEM (Pmode, addr);
11268 #endif
11269 if (TARGET_64BIT)
11270 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11271 else
11272 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11273 DONE;
11274 })
11275
11276 (define_insn "stack_protect_setsi"
11277 [(set (match_operand:SI 0 "memory_operand" "=m")
11278 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11279 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11280 "TARGET_32BIT"
11281 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
11282 [(set_attr "type" "three")
11283 (set_attr "length" "12")])
11284
11285 (define_insn "stack_protect_setdi"
11286 [(set (match_operand:DI 0 "memory_operand" "=m")
11287 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11288 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11289 "TARGET_64BIT"
11290 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
11291 [(set_attr "type" "three")
11292 (set_attr "length" "12")])
11293
11294 (define_expand "stack_protect_test"
11295 [(match_operand 0 "memory_operand" "")
11296 (match_operand 1 "memory_operand" "")
11297 (match_operand 2 "" "")]
11298 ""
11299 {
11300 #ifdef TARGET_THREAD_SSP_OFFSET
11301 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11302 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11303 operands[1] = gen_rtx_MEM (Pmode, addr);
11304 #endif
11305 rs6000_compare_op0 = operands[0];
11306 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
11307 UNSPEC_SP_TEST);
11308 rs6000_compare_fp_p = 0;
11309 emit_jump_insn (gen_beq (operands[2]));
11310 DONE;
11311 })
11312
11313 (define_insn "stack_protect_testsi"
11314 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11315 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11316 (match_operand:SI 2 "memory_operand" "m,m")]
11317 UNSPEC_SP_TEST))
11318 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11319 (clobber (match_scratch:SI 3 "=&r,&r"))]
11320 "TARGET_32BIT"
11321 "@
11322 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11323 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11324 [(set_attr "length" "16,20")])
11325
11326 (define_insn "stack_protect_testdi"
11327 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11328 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
11329 (match_operand:DI 2 "memory_operand" "m,m")]
11330 UNSPEC_SP_TEST))
11331 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11332 (clobber (match_scratch:DI 3 "=&r,&r"))]
11333 "TARGET_64BIT"
11334 "@
11335 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11336 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11337 [(set_attr "length" "16,20")])
11338
11339 \f
11340 ;; Here are the actual compare insns.
11341 (define_insn "*cmp<mode>_internal1"
11342 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11343 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11344 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
11345 ""
11346 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
11347 [(set_attr "type" "cmp")])
11348
11349 ;; If we are comparing a register for equality with a large constant,
11350 ;; we can do this with an XOR followed by a compare. But this is profitable
11351 ;; only if the large constant is only used for the comparison (and in this
11352 ;; case we already have a register to reuse as scratch).
11353 ;;
11354 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11355 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
11356
11357 (define_peephole2
11358 [(set (match_operand:SI 0 "register_operand")
11359 (match_operand:SI 1 "logical_const_operand" ""))
11360 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
11361 [(match_dup 0)
11362 (match_operand:SI 2 "logical_const_operand" "")]))
11363 (set (match_operand:CC 4 "cc_reg_operand" "")
11364 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
11365 (match_dup 0)))
11366 (set (pc)
11367 (if_then_else (match_operator 6 "equality_operator"
11368 [(match_dup 4) (const_int 0)])
11369 (match_operand 7 "" "")
11370 (match_operand 8 "" "")))]
11371 "peep2_reg_dead_p (3, operands[0])
11372 && peep2_reg_dead_p (4, operands[4])"
11373 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
11374 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11375 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11376
11377 {
11378 /* Get the constant we are comparing against, and see what it looks like
11379 when sign-extended from 16 to 32 bits. Then see what constant we could
11380 XOR with SEXTC to get the sign-extended value. */
11381 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
11382 SImode,
11383 operands[1], operands[2]);
11384 HOST_WIDE_INT c = INTVAL (cnst);
11385 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11386 HOST_WIDE_INT xorv = c ^ sextc;
11387
11388 operands[9] = GEN_INT (xorv);
11389 operands[10] = GEN_INT (sextc);
11390 })
11391
11392 (define_insn "*cmpsi_internal2"
11393 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11394 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11395 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11396 ""
11397 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
11398 [(set_attr "type" "cmp")])
11399
11400 (define_insn "*cmpdi_internal2"
11401 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11402 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11403 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11404 ""
11405 "cmpld%I2 %0,%1,%b2"
11406 [(set_attr "type" "cmp")])
11407
11408 ;; The following two insns don't exist as single insns, but if we provide
11409 ;; them, we can swap an add and compare, which will enable us to overlap more
11410 ;; of the required delay between a compare and branch. We generate code for
11411 ;; them by splitting.
11412
11413 (define_insn ""
11414 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11415 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11416 (match_operand:SI 2 "short_cint_operand" "i")))
11417 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11418 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11419 ""
11420 "#"
11421 [(set_attr "length" "8")])
11422
11423 (define_insn ""
11424 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11425 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11426 (match_operand:SI 2 "u_short_cint_operand" "i")))
11427 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11428 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11429 ""
11430 "#"
11431 [(set_attr "length" "8")])
11432
11433 (define_split
11434 [(set (match_operand:CC 3 "cc_reg_operand" "")
11435 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11436 (match_operand:SI 2 "short_cint_operand" "")))
11437 (set (match_operand:SI 0 "gpc_reg_operand" "")
11438 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11439 ""
11440 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11441 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11442
11443 (define_split
11444 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11445 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11446 (match_operand:SI 2 "u_short_cint_operand" "")))
11447 (set (match_operand:SI 0 "gpc_reg_operand" "")
11448 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11449 ""
11450 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11451 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11452
11453 (define_insn "*cmpsf_internal1"
11454 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11455 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11456 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11457 "TARGET_HARD_FLOAT && TARGET_FPRS"
11458 "fcmpu %0,%1,%2"
11459 [(set_attr "type" "fpcompare")])
11460
11461 (define_insn "*cmpdf_internal1"
11462 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11463 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11464 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11465 "TARGET_HARD_FLOAT && TARGET_FPRS"
11466 "fcmpu %0,%1,%2"
11467 [(set_attr "type" "fpcompare")])
11468
11469 ;; Only need to compare second words if first words equal
11470 (define_insn "*cmptf_internal1"
11471 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11472 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11473 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11474 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
11475 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11476 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11477 [(set_attr "type" "fpcompare")
11478 (set_attr "length" "12")])
11479
11480 (define_insn_and_split "*cmptf_internal2"
11481 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11482 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11483 (match_operand:TF 2 "gpc_reg_operand" "f")))
11484 (clobber (match_scratch:DF 3 "=f"))
11485 (clobber (match_scratch:DF 4 "=f"))
11486 (clobber (match_scratch:DF 5 "=f"))
11487 (clobber (match_scratch:DF 6 "=f"))
11488 (clobber (match_scratch:DF 7 "=f"))
11489 (clobber (match_scratch:DF 8 "=f"))
11490 (clobber (match_scratch:DF 9 "=f"))
11491 (clobber (match_scratch:DF 10 "=f"))]
11492 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
11493 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11494 "#"
11495 "&& reload_completed"
11496 [(set (match_dup 3) (match_dup 13))
11497 (set (match_dup 4) (match_dup 14))
11498 (set (match_dup 9) (abs:DF (match_dup 5)))
11499 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11500 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11501 (label_ref (match_dup 11))
11502 (pc)))
11503 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11504 (set (pc) (label_ref (match_dup 12)))
11505 (match_dup 11)
11506 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11507 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11508 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11509 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
11510 (match_dup 12)]
11511 {
11512 REAL_VALUE_TYPE rv;
11513 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
11514 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
11515
11516 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11517 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11518 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11519 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11520 operands[11] = gen_label_rtx ();
11521 operands[12] = gen_label_rtx ();
11522 real_inf (&rv);
11523 operands[13] = force_const_mem (DFmode,
11524 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11525 operands[14] = force_const_mem (DFmode,
11526 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11527 DFmode));
11528 if (TARGET_TOC)
11529 {
11530 operands[13] = gen_const_mem (DFmode,
11531 create_TOC_reference (XEXP (operands[13], 0)));
11532 operands[14] = gen_const_mem (DFmode,
11533 create_TOC_reference (XEXP (operands[14], 0)));
11534 set_mem_alias_set (operands[13], get_TOC_alias_set ());
11535 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11536 }
11537 })
11538 \f
11539 ;; Now we have the scc insns. We can do some combinations because of the
11540 ;; way the machine works.
11541 ;;
11542 ;; Note that this is probably faster if we can put an insn between the
11543 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11544 ;; cases the insns below which don't use an intermediate CR field will
11545 ;; be used instead.
11546 (define_insn ""
11547 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11548 (match_operator:SI 1 "scc_comparison_operator"
11549 [(match_operand 2 "cc_reg_operand" "y")
11550 (const_int 0)]))]
11551 ""
11552 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11553 [(set (attr "type")
11554 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11555 (const_string "mfcrf")
11556 ]
11557 (const_string "mfcr")))
11558 (set_attr "length" "8")])
11559
11560 ;; Same as above, but get the GT bit.
11561 (define_insn "move_from_CR_gt_bit"
11562 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11563 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
11564 "TARGET_E500"
11565 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
11566 [(set_attr "type" "mfcr")
11567 (set_attr "length" "8")])
11568
11569 ;; Same as above, but get the OV/ORDERED bit.
11570 (define_insn "move_from_CR_ov_bit"
11571 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11572 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
11573 "TARGET_ISEL"
11574 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
11575 [(set_attr "type" "mfcr")
11576 (set_attr "length" "8")])
11577
11578 (define_insn ""
11579 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11580 (match_operator:DI 1 "scc_comparison_operator"
11581 [(match_operand 2 "cc_reg_operand" "y")
11582 (const_int 0)]))]
11583 "TARGET_POWERPC64"
11584 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11585 [(set (attr "type")
11586 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11587 (const_string "mfcrf")
11588 ]
11589 (const_string "mfcr")))
11590 (set_attr "length" "8")])
11591
11592 (define_insn ""
11593 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11594 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11595 [(match_operand 2 "cc_reg_operand" "y,y")
11596 (const_int 0)])
11597 (const_int 0)))
11598 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11599 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11600 "TARGET_32BIT"
11601 "@
11602 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
11603 #"
11604 [(set_attr "type" "delayed_compare")
11605 (set_attr "length" "8,16")])
11606
11607 (define_split
11608 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11609 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11610 [(match_operand 2 "cc_reg_operand" "")
11611 (const_int 0)])
11612 (const_int 0)))
11613 (set (match_operand:SI 3 "gpc_reg_operand" "")
11614 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11615 "TARGET_32BIT && reload_completed"
11616 [(set (match_dup 3)
11617 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11618 (set (match_dup 0)
11619 (compare:CC (match_dup 3)
11620 (const_int 0)))]
11621 "")
11622
11623 (define_insn ""
11624 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11625 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11626 [(match_operand 2 "cc_reg_operand" "y")
11627 (const_int 0)])
11628 (match_operand:SI 3 "const_int_operand" "n")))]
11629 ""
11630 "*
11631 {
11632 int is_bit = ccr_bit (operands[1], 1);
11633 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11634 int count;
11635
11636 if (is_bit >= put_bit)
11637 count = is_bit - put_bit;
11638 else
11639 count = 32 - (put_bit - is_bit);
11640
11641 operands[4] = GEN_INT (count);
11642 operands[5] = GEN_INT (put_bit);
11643
11644 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11645 }"
11646 [(set (attr "type")
11647 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11648 (const_string "mfcrf")
11649 ]
11650 (const_string "mfcr")))
11651 (set_attr "length" "8")])
11652
11653 (define_insn ""
11654 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11655 (compare:CC
11656 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11657 [(match_operand 2 "cc_reg_operand" "y,y")
11658 (const_int 0)])
11659 (match_operand:SI 3 "const_int_operand" "n,n"))
11660 (const_int 0)))
11661 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11662 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11663 (match_dup 3)))]
11664 ""
11665 "*
11666 {
11667 int is_bit = ccr_bit (operands[1], 1);
11668 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11669 int count;
11670
11671 /* Force split for non-cc0 compare. */
11672 if (which_alternative == 1)
11673 return \"#\";
11674
11675 if (is_bit >= put_bit)
11676 count = is_bit - put_bit;
11677 else
11678 count = 32 - (put_bit - is_bit);
11679
11680 operands[5] = GEN_INT (count);
11681 operands[6] = GEN_INT (put_bit);
11682
11683 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
11684 }"
11685 [(set_attr "type" "delayed_compare")
11686 (set_attr "length" "8,16")])
11687
11688 (define_split
11689 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11690 (compare:CC
11691 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11692 [(match_operand 2 "cc_reg_operand" "")
11693 (const_int 0)])
11694 (match_operand:SI 3 "const_int_operand" ""))
11695 (const_int 0)))
11696 (set (match_operand:SI 4 "gpc_reg_operand" "")
11697 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11698 (match_dup 3)))]
11699 "reload_completed"
11700 [(set (match_dup 4)
11701 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11702 (match_dup 3)))
11703 (set (match_dup 0)
11704 (compare:CC (match_dup 4)
11705 (const_int 0)))]
11706 "")
11707
11708 ;; There is a 3 cycle delay between consecutive mfcr instructions
11709 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11710
11711 (define_peephole
11712 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11713 (match_operator:SI 1 "scc_comparison_operator"
11714 [(match_operand 2 "cc_reg_operand" "y")
11715 (const_int 0)]))
11716 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11717 (match_operator:SI 4 "scc_comparison_operator"
11718 [(match_operand 5 "cc_reg_operand" "y")
11719 (const_int 0)]))]
11720 "REGNO (operands[2]) != REGNO (operands[5])"
11721 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11722 [(set_attr "type" "mfcr")
11723 (set_attr "length" "12")])
11724
11725 (define_peephole
11726 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11727 (match_operator:DI 1 "scc_comparison_operator"
11728 [(match_operand 2 "cc_reg_operand" "y")
11729 (const_int 0)]))
11730 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11731 (match_operator:DI 4 "scc_comparison_operator"
11732 [(match_operand 5 "cc_reg_operand" "y")
11733 (const_int 0)]))]
11734 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11735 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11736 [(set_attr "type" "mfcr")
11737 (set_attr "length" "12")])
11738
11739 ;; There are some scc insns that can be done directly, without a compare.
11740 ;; These are faster because they don't involve the communications between
11741 ;; the FXU and branch units. In fact, we will be replacing all of the
11742 ;; integer scc insns here or in the portable methods in emit_store_flag.
11743 ;;
11744 ;; Also support (neg (scc ..)) since that construct is used to replace
11745 ;; branches, (plus (scc ..) ..) since that construct is common and
11746 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11747 ;; cases where it is no more expensive than (neg (scc ..)).
11748
11749 ;; Have reload force a constant into a register for the simple insns that
11750 ;; otherwise won't accept constants. We do this because it is faster than
11751 ;; the cmp/mfcr sequence we would otherwise generate.
11752
11753 (define_mode_attr scc_eq_op2 [(SI "rKLI")
11754 (DI "rKJI")])
11755
11756 (define_insn_and_split "*eq<mode>"
11757 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
11758 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
11759 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
11760 "!TARGET_POWER"
11761 "#"
11762 "!TARGET_POWER"
11763 [(set (match_dup 0)
11764 (clz:GPR (match_dup 3)))
11765 (set (match_dup 0)
11766 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
11767 {
11768 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11769 {
11770 /* Use output operand as intermediate. */
11771 operands[3] = operands[0];
11772
11773 if (logical_operand (operands[2], <MODE>mode))
11774 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11775 gen_rtx_XOR (<MODE>mode,
11776 operands[1], operands[2])));
11777 else
11778 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11779 gen_rtx_PLUS (<MODE>mode, operands[1],
11780 negate_rtx (<MODE>mode,
11781 operands[2]))));
11782 }
11783 else
11784 operands[3] = operands[1];
11785
11786 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11787 })
11788
11789 (define_insn_and_split "*eq<mode>_compare"
11790 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11791 (compare:CC
11792 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
11793 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
11794 (const_int 0)))
11795 (set (match_operand:P 0 "gpc_reg_operand" "=r")
11796 (eq:P (match_dup 1) (match_dup 2)))]
11797 "!TARGET_POWER && optimize_size"
11798 "#"
11799 "!TARGET_POWER && optimize_size"
11800 [(set (match_dup 0)
11801 (clz:P (match_dup 4)))
11802 (parallel [(set (match_dup 3)
11803 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
11804 (const_int 0)))
11805 (set (match_dup 0)
11806 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
11807 {
11808 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11809 {
11810 /* Use output operand as intermediate. */
11811 operands[4] = operands[0];
11812
11813 if (logical_operand (operands[2], <MODE>mode))
11814 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11815 gen_rtx_XOR (<MODE>mode,
11816 operands[1], operands[2])));
11817 else
11818 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11819 gen_rtx_PLUS (<MODE>mode, operands[1],
11820 negate_rtx (<MODE>mode,
11821 operands[2]))));
11822 }
11823 else
11824 operands[4] = operands[1];
11825
11826 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11827 })
11828
11829 (define_insn "*eqsi_power"
11830 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11831 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11832 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
11833 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
11834 "TARGET_POWER"
11835 "@
11836 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11837 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
11838 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11839 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11840 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
11841 [(set_attr "type" "three,two,three,three,three")
11842 (set_attr "length" "12,8,12,12,12")])
11843
11844 ;; We have insns of the form shown by the first define_insn below. If
11845 ;; there is something inside the comparison operation, we must split it.
11846 (define_split
11847 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11848 (plus:SI (match_operator 1 "comparison_operator"
11849 [(match_operand:SI 2 "" "")
11850 (match_operand:SI 3
11851 "reg_or_cint_operand" "")])
11852 (match_operand:SI 4 "gpc_reg_operand" "")))
11853 (clobber (match_operand:SI 5 "register_operand" ""))]
11854 "! gpc_reg_operand (operands[2], SImode)"
11855 [(set (match_dup 5) (match_dup 2))
11856 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11857 (match_dup 4)))])
11858
11859 (define_insn "*plus_eqsi"
11860 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11861 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11862 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
11863 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11864 "TARGET_32BIT"
11865 "@
11866 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11867 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11868 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11869 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11870 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
11871 [(set_attr "type" "three,two,three,three,three")
11872 (set_attr "length" "12,8,12,12,12")])
11873
11874 (define_insn "*compare_plus_eqsi"
11875 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11876 (compare:CC
11877 (plus:SI
11878 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11879 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
11880 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11881 (const_int 0)))
11882 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11883 "TARGET_32BIT && optimize_size"
11884 "@
11885 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11886 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
11887 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11888 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11889 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11890 #
11891 #
11892 #
11893 #
11894 #"
11895 [(set_attr "type" "compare")
11896 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11897
11898 (define_split
11899 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11900 (compare:CC
11901 (plus:SI
11902 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11903 (match_operand:SI 2 "scc_eq_operand" ""))
11904 (match_operand:SI 3 "gpc_reg_operand" ""))
11905 (const_int 0)))
11906 (clobber (match_scratch:SI 4 ""))]
11907 "TARGET_32BIT && optimize_size && reload_completed"
11908 [(set (match_dup 4)
11909 (plus:SI (eq:SI (match_dup 1)
11910 (match_dup 2))
11911 (match_dup 3)))
11912 (set (match_dup 0)
11913 (compare:CC (match_dup 4)
11914 (const_int 0)))]
11915 "")
11916
11917 (define_insn "*plus_eqsi_compare"
11918 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11919 (compare:CC
11920 (plus:SI
11921 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11922 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
11923 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11924 (const_int 0)))
11925 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11926 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11927 "TARGET_32BIT && optimize_size"
11928 "@
11929 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11930 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
11931 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11932 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11933 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11934 #
11935 #
11936 #
11937 #
11938 #"
11939 [(set_attr "type" "compare")
11940 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11941
11942 (define_split
11943 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11944 (compare:CC
11945 (plus:SI
11946 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11947 (match_operand:SI 2 "scc_eq_operand" ""))
11948 (match_operand:SI 3 "gpc_reg_operand" ""))
11949 (const_int 0)))
11950 (set (match_operand:SI 0 "gpc_reg_operand" "")
11951 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11952 "TARGET_32BIT && optimize_size && reload_completed"
11953 [(set (match_dup 0)
11954 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11955 (set (match_dup 4)
11956 (compare:CC (match_dup 0)
11957 (const_int 0)))]
11958 "")
11959
11960 (define_insn "*neg_eq0<mode>"
11961 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11962 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
11963 (const_int 0))))]
11964 ""
11965 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
11966 [(set_attr "type" "two")
11967 (set_attr "length" "8")])
11968
11969 (define_insn_and_split "*neg_eq<mode>"
11970 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11971 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
11972 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
11973 ""
11974 "#"
11975 ""
11976 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
11977 {
11978 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11979 {
11980 /* Use output operand as intermediate. */
11981 operands[3] = operands[0];
11982
11983 if (logical_operand (operands[2], <MODE>mode))
11984 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11985 gen_rtx_XOR (<MODE>mode,
11986 operands[1], operands[2])));
11987 else
11988 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11989 gen_rtx_PLUS (<MODE>mode, operands[1],
11990 negate_rtx (<MODE>mode,
11991 operands[2]))));
11992 }
11993 else
11994 operands[3] = operands[1];
11995 })
11996
11997 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
11998 ;; since it nabs/sr is just as fast.
11999 (define_insn "*ne0si"
12000 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12001 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12002 (const_int 31)))
12003 (clobber (match_scratch:SI 2 "=&r"))]
12004 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
12005 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
12006 [(set_attr "type" "two")
12007 (set_attr "length" "8")])
12008
12009 (define_insn "*ne0di"
12010 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12011 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12012 (const_int 63)))
12013 (clobber (match_scratch:DI 2 "=&r"))]
12014 "TARGET_64BIT"
12015 "addic %2,%1,-1\;subfe %0,%2,%1"
12016 [(set_attr "type" "two")
12017 (set_attr "length" "8")])
12018
12019 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
12020 (define_insn "*plus_ne0si"
12021 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12022 (plus:SI (lshiftrt:SI
12023 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12024 (const_int 31))
12025 (match_operand:SI 2 "gpc_reg_operand" "r")))
12026 (clobber (match_scratch:SI 3 "=&r"))]
12027 "TARGET_32BIT"
12028 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
12029 [(set_attr "type" "two")
12030 (set_attr "length" "8")])
12031
12032 (define_insn "*plus_ne0di"
12033 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12034 (plus:DI (lshiftrt:DI
12035 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12036 (const_int 63))
12037 (match_operand:DI 2 "gpc_reg_operand" "r")))
12038 (clobber (match_scratch:DI 3 "=&r"))]
12039 "TARGET_64BIT"
12040 "addic %3,%1,-1\;addze %0,%2"
12041 [(set_attr "type" "two")
12042 (set_attr "length" "8")])
12043
12044 (define_insn "*compare_plus_ne0si"
12045 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12046 (compare:CC
12047 (plus:SI (lshiftrt:SI
12048 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12049 (const_int 31))
12050 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12051 (const_int 0)))
12052 (clobber (match_scratch:SI 3 "=&r,&r"))
12053 (clobber (match_scratch:SI 4 "=X,&r"))]
12054 "TARGET_32BIT"
12055 "@
12056 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
12057 #"
12058 [(set_attr "type" "compare")
12059 (set_attr "length" "8,12")])
12060
12061 (define_split
12062 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12063 (compare:CC
12064 (plus:SI (lshiftrt:SI
12065 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12066 (const_int 31))
12067 (match_operand:SI 2 "gpc_reg_operand" ""))
12068 (const_int 0)))
12069 (clobber (match_scratch:SI 3 ""))
12070 (clobber (match_scratch:SI 4 ""))]
12071 "TARGET_32BIT && reload_completed"
12072 [(parallel [(set (match_dup 3)
12073 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
12074 (const_int 31))
12075 (match_dup 2)))
12076 (clobber (match_dup 4))])
12077 (set (match_dup 0)
12078 (compare:CC (match_dup 3)
12079 (const_int 0)))]
12080 "")
12081
12082 (define_insn "*compare_plus_ne0di"
12083 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12084 (compare:CC
12085 (plus:DI (lshiftrt:DI
12086 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12087 (const_int 63))
12088 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12089 (const_int 0)))
12090 (clobber (match_scratch:DI 3 "=&r,&r"))]
12091 "TARGET_64BIT"
12092 "@
12093 addic %3,%1,-1\;addze. %3,%2
12094 #"
12095 [(set_attr "type" "compare")
12096 (set_attr "length" "8,12")])
12097
12098 (define_split
12099 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12100 (compare:CC
12101 (plus:DI (lshiftrt:DI
12102 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12103 (const_int 63))
12104 (match_operand:DI 2 "gpc_reg_operand" ""))
12105 (const_int 0)))
12106 (clobber (match_scratch:DI 3 ""))]
12107 "TARGET_64BIT && reload_completed"
12108 [(set (match_dup 3)
12109 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12110 (const_int 63))
12111 (match_dup 2)))
12112 (set (match_dup 0)
12113 (compare:CC (match_dup 3)
12114 (const_int 0)))]
12115 "")
12116
12117 (define_insn "*plus_ne0si_compare"
12118 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12119 (compare:CC
12120 (plus:SI (lshiftrt:SI
12121 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12122 (const_int 31))
12123 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12124 (const_int 0)))
12125 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12126 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12127 (match_dup 2)))
12128 (clobber (match_scratch:SI 3 "=&r,&r"))]
12129 "TARGET_32BIT"
12130 "@
12131 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
12132 #"
12133 [(set_attr "type" "compare")
12134 (set_attr "length" "8,12")])
12135
12136 (define_split
12137 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12138 (compare:CC
12139 (plus:SI (lshiftrt:SI
12140 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12141 (const_int 31))
12142 (match_operand:SI 2 "gpc_reg_operand" ""))
12143 (const_int 0)))
12144 (set (match_operand:SI 0 "gpc_reg_operand" "")
12145 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12146 (match_dup 2)))
12147 (clobber (match_scratch:SI 3 ""))]
12148 "TARGET_32BIT && reload_completed"
12149 [(parallel [(set (match_dup 0)
12150 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12151 (match_dup 2)))
12152 (clobber (match_dup 3))])
12153 (set (match_dup 4)
12154 (compare:CC (match_dup 0)
12155 (const_int 0)))]
12156 "")
12157
12158 (define_insn "*plus_ne0di_compare"
12159 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12160 (compare:CC
12161 (plus:DI (lshiftrt:DI
12162 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12163 (const_int 63))
12164 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12165 (const_int 0)))
12166 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12167 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12168 (match_dup 2)))
12169 (clobber (match_scratch:DI 3 "=&r,&r"))]
12170 "TARGET_64BIT"
12171 "@
12172 addic %3,%1,-1\;addze. %0,%2
12173 #"
12174 [(set_attr "type" "compare")
12175 (set_attr "length" "8,12")])
12176
12177 (define_split
12178 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12179 (compare:CC
12180 (plus:DI (lshiftrt:DI
12181 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12182 (const_int 63))
12183 (match_operand:DI 2 "gpc_reg_operand" ""))
12184 (const_int 0)))
12185 (set (match_operand:DI 0 "gpc_reg_operand" "")
12186 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12187 (match_dup 2)))
12188 (clobber (match_scratch:DI 3 ""))]
12189 "TARGET_64BIT && reload_completed"
12190 [(parallel [(set (match_dup 0)
12191 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12192 (match_dup 2)))
12193 (clobber (match_dup 3))])
12194 (set (match_dup 4)
12195 (compare:CC (match_dup 0)
12196 (const_int 0)))]
12197 "")
12198
12199 (define_insn ""
12200 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12201 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12202 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12203 (clobber (match_scratch:SI 3 "=r,X"))]
12204 "TARGET_POWER"
12205 "@
12206 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
12207 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
12208 [(set_attr "length" "12")])
12209
12210 (define_insn ""
12211 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12212 (compare:CC
12213 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12214 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12215 (const_int 0)))
12216 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12217 (le:SI (match_dup 1) (match_dup 2)))
12218 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
12219 "TARGET_POWER"
12220 "@
12221 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12222 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
12223 #
12224 #"
12225 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
12226 (set_attr "length" "12,12,16,16")])
12227
12228 (define_split
12229 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12230 (compare:CC
12231 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12232 (match_operand:SI 2 "reg_or_short_operand" ""))
12233 (const_int 0)))
12234 (set (match_operand:SI 0 "gpc_reg_operand" "")
12235 (le:SI (match_dup 1) (match_dup 2)))
12236 (clobber (match_scratch:SI 3 ""))]
12237 "TARGET_POWER && reload_completed"
12238 [(parallel [(set (match_dup 0)
12239 (le:SI (match_dup 1) (match_dup 2)))
12240 (clobber (match_dup 3))])
12241 (set (match_dup 4)
12242 (compare:CC (match_dup 0)
12243 (const_int 0)))]
12244 "")
12245
12246 (define_insn ""
12247 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12248 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12249 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
12250 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12251 "TARGET_POWER"
12252 "@
12253 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12254 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
12255 [(set_attr "length" "12")])
12256
12257 (define_insn ""
12258 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12259 (compare:CC
12260 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12261 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12262 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12263 (const_int 0)))
12264 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12265 "TARGET_POWER"
12266 "@
12267 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12268 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12269 #
12270 #"
12271 [(set_attr "type" "compare")
12272 (set_attr "length" "12,12,16,16")])
12273
12274 (define_split
12275 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12276 (compare:CC
12277 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12278 (match_operand:SI 2 "reg_or_short_operand" ""))
12279 (match_operand:SI 3 "gpc_reg_operand" ""))
12280 (const_int 0)))
12281 (clobber (match_scratch:SI 4 ""))]
12282 "TARGET_POWER && reload_completed"
12283 [(set (match_dup 4)
12284 (plus:SI (le:SI (match_dup 1) (match_dup 2))
12285 (match_dup 3)))
12286 (set (match_dup 0)
12287 (compare:CC (match_dup 4)
12288 (const_int 0)))]
12289 "")
12290
12291 (define_insn ""
12292 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12293 (compare:CC
12294 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12295 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12296 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12297 (const_int 0)))
12298 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12299 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12300 "TARGET_POWER"
12301 "@
12302 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12303 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
12304 #
12305 #"
12306 [(set_attr "type" "compare")
12307 (set_attr "length" "12,12,16,16")])
12308
12309 (define_split
12310 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12311 (compare:CC
12312 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12313 (match_operand:SI 2 "reg_or_short_operand" ""))
12314 (match_operand:SI 3 "gpc_reg_operand" ""))
12315 (const_int 0)))
12316 (set (match_operand:SI 0 "gpc_reg_operand" "")
12317 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12318 "TARGET_POWER && reload_completed"
12319 [(set (match_dup 0)
12320 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12321 (set (match_dup 4)
12322 (compare:CC (match_dup 0)
12323 (const_int 0)))]
12324 "")
12325
12326 (define_insn ""
12327 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12328 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12329 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
12330 "TARGET_POWER"
12331 "@
12332 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12333 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
12334 [(set_attr "length" "12")])
12335
12336 (define_insn "*leu<mode>"
12337 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12338 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12339 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12340 ""
12341 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12342 [(set_attr "type" "three")
12343 (set_attr "length" "12")])
12344
12345 (define_insn "*leu<mode>_compare"
12346 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12347 (compare:CC
12348 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12349 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12350 (const_int 0)))
12351 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12352 (leu:P (match_dup 1) (match_dup 2)))]
12353 ""
12354 "@
12355 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12356 #"
12357 [(set_attr "type" "compare")
12358 (set_attr "length" "12,16")])
12359
12360 (define_split
12361 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12362 (compare:CC
12363 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12364 (match_operand:P 2 "reg_or_short_operand" ""))
12365 (const_int 0)))
12366 (set (match_operand:P 0 "gpc_reg_operand" "")
12367 (leu:P (match_dup 1) (match_dup 2)))]
12368 "reload_completed"
12369 [(set (match_dup 0)
12370 (leu:P (match_dup 1) (match_dup 2)))
12371 (set (match_dup 3)
12372 (compare:CC (match_dup 0)
12373 (const_int 0)))]
12374 "")
12375
12376 (define_insn "*plus_leu<mode>"
12377 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12378 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12379 (match_operand:P 2 "reg_or_short_operand" "rI"))
12380 (match_operand:P 3 "gpc_reg_operand" "r")))]
12381 ""
12382 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12383 [(set_attr "type" "two")
12384 (set_attr "length" "8")])
12385
12386 (define_insn ""
12387 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12388 (compare:CC
12389 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12390 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12391 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12392 (const_int 0)))
12393 (clobber (match_scratch:SI 4 "=&r,&r"))]
12394 "TARGET_32BIT"
12395 "@
12396 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12397 #"
12398 [(set_attr "type" "compare")
12399 (set_attr "length" "8,12")])
12400
12401 (define_split
12402 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12403 (compare:CC
12404 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12405 (match_operand:SI 2 "reg_or_short_operand" ""))
12406 (match_operand:SI 3 "gpc_reg_operand" ""))
12407 (const_int 0)))
12408 (clobber (match_scratch:SI 4 ""))]
12409 "TARGET_32BIT && reload_completed"
12410 [(set (match_dup 4)
12411 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12412 (match_dup 3)))
12413 (set (match_dup 0)
12414 (compare:CC (match_dup 4)
12415 (const_int 0)))]
12416 "")
12417
12418 (define_insn ""
12419 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12420 (compare:CC
12421 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12422 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12423 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12424 (const_int 0)))
12425 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12426 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12427 "TARGET_32BIT"
12428 "@
12429 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12430 #"
12431 [(set_attr "type" "compare")
12432 (set_attr "length" "8,12")])
12433
12434 (define_split
12435 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12436 (compare:CC
12437 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12438 (match_operand:SI 2 "reg_or_short_operand" ""))
12439 (match_operand:SI 3 "gpc_reg_operand" ""))
12440 (const_int 0)))
12441 (set (match_operand:SI 0 "gpc_reg_operand" "")
12442 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12443 "TARGET_32BIT && reload_completed"
12444 [(set (match_dup 0)
12445 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12446 (set (match_dup 4)
12447 (compare:CC (match_dup 0)
12448 (const_int 0)))]
12449 "")
12450
12451 (define_insn "*neg_leu<mode>"
12452 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12453 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12454 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12455 ""
12456 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12457 [(set_attr "type" "three")
12458 (set_attr "length" "12")])
12459
12460 (define_insn "*and_neg_leu<mode>"
12461 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12462 (and:P (neg:P
12463 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12464 (match_operand:P 2 "reg_or_short_operand" "rI")))
12465 (match_operand:P 3 "gpc_reg_operand" "r")))]
12466 ""
12467 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12468 [(set_attr "type" "three")
12469 (set_attr "length" "12")])
12470
12471 (define_insn ""
12472 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12473 (compare:CC
12474 (and:SI (neg:SI
12475 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12476 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12477 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12478 (const_int 0)))
12479 (clobber (match_scratch:SI 4 "=&r,&r"))]
12480 "TARGET_32BIT"
12481 "@
12482 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12483 #"
12484 [(set_attr "type" "compare")
12485 (set_attr "length" "12,16")])
12486
12487 (define_split
12488 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12489 (compare:CC
12490 (and:SI (neg:SI
12491 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12492 (match_operand:SI 2 "reg_or_short_operand" "")))
12493 (match_operand:SI 3 "gpc_reg_operand" ""))
12494 (const_int 0)))
12495 (clobber (match_scratch:SI 4 ""))]
12496 "TARGET_32BIT && reload_completed"
12497 [(set (match_dup 4)
12498 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12499 (match_dup 3)))
12500 (set (match_dup 0)
12501 (compare:CC (match_dup 4)
12502 (const_int 0)))]
12503 "")
12504
12505 (define_insn ""
12506 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12507 (compare:CC
12508 (and:SI (neg:SI
12509 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12510 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12511 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12512 (const_int 0)))
12513 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12514 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12515 "TARGET_32BIT"
12516 "@
12517 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12518 #"
12519 [(set_attr "type" "compare")
12520 (set_attr "length" "12,16")])
12521
12522 (define_split
12523 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12524 (compare:CC
12525 (and:SI (neg:SI
12526 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12527 (match_operand:SI 2 "reg_or_short_operand" "")))
12528 (match_operand:SI 3 "gpc_reg_operand" ""))
12529 (const_int 0)))
12530 (set (match_operand:SI 0 "gpc_reg_operand" "")
12531 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12532 "TARGET_32BIT && reload_completed"
12533 [(set (match_dup 0)
12534 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12535 (match_dup 3)))
12536 (set (match_dup 4)
12537 (compare:CC (match_dup 0)
12538 (const_int 0)))]
12539 "")
12540
12541 (define_insn ""
12542 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12543 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12544 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12545 "TARGET_POWER"
12546 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12547 [(set_attr "length" "12")])
12548
12549 (define_insn ""
12550 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12551 (compare:CC
12552 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12553 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12554 (const_int 0)))
12555 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12556 (lt:SI (match_dup 1) (match_dup 2)))]
12557 "TARGET_POWER"
12558 "@
12559 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12560 #"
12561 [(set_attr "type" "delayed_compare")
12562 (set_attr "length" "12,16")])
12563
12564 (define_split
12565 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12566 (compare:CC
12567 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12568 (match_operand:SI 2 "reg_or_short_operand" ""))
12569 (const_int 0)))
12570 (set (match_operand:SI 0 "gpc_reg_operand" "")
12571 (lt:SI (match_dup 1) (match_dup 2)))]
12572 "TARGET_POWER && reload_completed"
12573 [(set (match_dup 0)
12574 (lt:SI (match_dup 1) (match_dup 2)))
12575 (set (match_dup 3)
12576 (compare:CC (match_dup 0)
12577 (const_int 0)))]
12578 "")
12579
12580 (define_insn ""
12581 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12582 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12583 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12584 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12585 "TARGET_POWER"
12586 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12587 [(set_attr "length" "12")])
12588
12589 (define_insn ""
12590 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12591 (compare:CC
12592 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12593 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12594 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12595 (const_int 0)))
12596 (clobber (match_scratch:SI 4 "=&r,&r"))]
12597 "TARGET_POWER"
12598 "@
12599 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12600 #"
12601 [(set_attr "type" "compare")
12602 (set_attr "length" "12,16")])
12603
12604 (define_split
12605 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12606 (compare:CC
12607 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12608 (match_operand:SI 2 "reg_or_short_operand" ""))
12609 (match_operand:SI 3 "gpc_reg_operand" ""))
12610 (const_int 0)))
12611 (clobber (match_scratch:SI 4 ""))]
12612 "TARGET_POWER && reload_completed"
12613 [(set (match_dup 4)
12614 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
12615 (match_dup 3)))
12616 (set (match_dup 0)
12617 (compare:CC (match_dup 4)
12618 (const_int 0)))]
12619 "")
12620
12621 (define_insn ""
12622 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12623 (compare:CC
12624 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12625 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12626 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12627 (const_int 0)))
12628 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12629 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12630 "TARGET_POWER"
12631 "@
12632 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12633 #"
12634 [(set_attr "type" "compare")
12635 (set_attr "length" "12,16")])
12636
12637 (define_split
12638 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12639 (compare:CC
12640 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12641 (match_operand:SI 2 "reg_or_short_operand" ""))
12642 (match_operand:SI 3 "gpc_reg_operand" ""))
12643 (const_int 0)))
12644 (set (match_operand:SI 0 "gpc_reg_operand" "")
12645 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12646 "TARGET_POWER && reload_completed"
12647 [(set (match_dup 0)
12648 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12649 (set (match_dup 4)
12650 (compare:CC (match_dup 0)
12651 (const_int 0)))]
12652 "")
12653
12654 (define_insn ""
12655 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12656 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12657 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12658 "TARGET_POWER"
12659 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12660 [(set_attr "length" "12")])
12661
12662 (define_insn_and_split "*ltu<mode>"
12663 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12664 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12665 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12666 ""
12667 "#"
12668 ""
12669 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12670 (set (match_dup 0) (neg:P (match_dup 0)))]
12671 "")
12672
12673 (define_insn_and_split "*ltu<mode>_compare"
12674 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12675 (compare:CC
12676 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12677 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12678 (const_int 0)))
12679 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12680 (ltu:P (match_dup 1) (match_dup 2)))]
12681 ""
12682 "#"
12683 ""
12684 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12685 (parallel [(set (match_dup 3)
12686 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12687 (set (match_dup 0) (neg:P (match_dup 0)))])]
12688 "")
12689
12690 (define_insn_and_split "*plus_ltu<mode>"
12691 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
12692 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12693 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12694 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
12695 ""
12696 "#"
12697 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12698 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12699 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
12700 "")
12701
12702 (define_insn_and_split "*plus_ltu<mode>_compare"
12703 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12704 (compare:CC
12705 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12706 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12707 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
12708 (const_int 0)))
12709 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12710 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
12711 ""
12712 "#"
12713 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12714 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12715 (parallel [(set (match_dup 4)
12716 (compare:CC (minus:P (match_dup 3) (match_dup 0))
12717 (const_int 0)))
12718 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
12719 "")
12720
12721 (define_insn "*neg_ltu<mode>"
12722 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12723 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12724 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
12725 ""
12726 "@
12727 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12728 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12729 [(set_attr "type" "two")
12730 (set_attr "length" "8")])
12731
12732 (define_insn ""
12733 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12734 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12735 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12736 (clobber (match_scratch:SI 3 "=r"))]
12737 "TARGET_POWER"
12738 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
12739 [(set_attr "length" "12")])
12740
12741 (define_insn ""
12742 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12743 (compare:CC
12744 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12745 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12746 (const_int 0)))
12747 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12748 (ge:SI (match_dup 1) (match_dup 2)))
12749 (clobber (match_scratch:SI 3 "=r,r"))]
12750 "TARGET_POWER"
12751 "@
12752 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12753 #"
12754 [(set_attr "type" "compare")
12755 (set_attr "length" "12,16")])
12756
12757 (define_split
12758 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12759 (compare:CC
12760 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12761 (match_operand:SI 2 "reg_or_short_operand" ""))
12762 (const_int 0)))
12763 (set (match_operand:SI 0 "gpc_reg_operand" "")
12764 (ge:SI (match_dup 1) (match_dup 2)))
12765 (clobber (match_scratch:SI 3 ""))]
12766 "TARGET_POWER && reload_completed"
12767 [(parallel [(set (match_dup 0)
12768 (ge:SI (match_dup 1) (match_dup 2)))
12769 (clobber (match_dup 3))])
12770 (set (match_dup 4)
12771 (compare:CC (match_dup 0)
12772 (const_int 0)))]
12773 "")
12774
12775 (define_insn ""
12776 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12777 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12778 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12779 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12780 "TARGET_POWER"
12781 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12782 [(set_attr "length" "12")])
12783
12784 (define_insn ""
12785 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12786 (compare:CC
12787 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12788 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12789 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12790 (const_int 0)))
12791 (clobber (match_scratch:SI 4 "=&r,&r"))]
12792 "TARGET_POWER"
12793 "@
12794 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12795 #"
12796 [(set_attr "type" "compare")
12797 (set_attr "length" "12,16")])
12798
12799 (define_split
12800 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12801 (compare:CC
12802 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12803 (match_operand:SI 2 "reg_or_short_operand" ""))
12804 (match_operand:SI 3 "gpc_reg_operand" ""))
12805 (const_int 0)))
12806 (clobber (match_scratch:SI 4 ""))]
12807 "TARGET_POWER && reload_completed"
12808 [(set (match_dup 4)
12809 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
12810 (match_dup 3)))
12811 (set (match_dup 0)
12812 (compare:CC (match_dup 4)
12813 (const_int 0)))]
12814 "")
12815
12816 (define_insn ""
12817 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12818 (compare:CC
12819 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12820 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12821 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12822 (const_int 0)))
12823 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12824 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12825 "TARGET_POWER"
12826 "@
12827 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12828 #"
12829 [(set_attr "type" "compare")
12830 (set_attr "length" "12,16")])
12831
12832 (define_split
12833 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12834 (compare:CC
12835 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12836 (match_operand:SI 2 "reg_or_short_operand" ""))
12837 (match_operand:SI 3 "gpc_reg_operand" ""))
12838 (const_int 0)))
12839 (set (match_operand:SI 0 "gpc_reg_operand" "")
12840 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12841 "TARGET_POWER && reload_completed"
12842 [(set (match_dup 0)
12843 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12844 (set (match_dup 4)
12845 (compare:CC (match_dup 0)
12846 (const_int 0)))]
12847 "")
12848
12849 (define_insn ""
12850 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12851 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12852 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12853 "TARGET_POWER"
12854 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
12855 [(set_attr "length" "12")])
12856
12857 (define_insn "*geu<mode>"
12858 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12859 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12860 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12861 ""
12862 "@
12863 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12864 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12865 [(set_attr "type" "three")
12866 (set_attr "length" "12")])
12867
12868 (define_insn "*geu<mode>_compare"
12869 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12870 (compare:CC
12871 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12872 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12873 (const_int 0)))
12874 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12875 (geu:P (match_dup 1) (match_dup 2)))]
12876 ""
12877 "@
12878 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12879 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12880 #
12881 #"
12882 [(set_attr "type" "compare")
12883 (set_attr "length" "12,12,16,16")])
12884
12885 (define_split
12886 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12887 (compare:CC
12888 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
12889 (match_operand:P 2 "reg_or_neg_short_operand" ""))
12890 (const_int 0)))
12891 (set (match_operand:P 0 "gpc_reg_operand" "")
12892 (geu:P (match_dup 1) (match_dup 2)))]
12893 "reload_completed"
12894 [(set (match_dup 0)
12895 (geu:P (match_dup 1) (match_dup 2)))
12896 (set (match_dup 3)
12897 (compare:CC (match_dup 0)
12898 (const_int 0)))]
12899 "")
12900
12901 (define_insn "*plus_geu<mode>"
12902 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12903 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12904 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12905 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12906 ""
12907 "@
12908 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
12909 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
12910 [(set_attr "type" "two")
12911 (set_attr "length" "8")])
12912
12913 (define_insn ""
12914 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12915 (compare:CC
12916 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12917 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12918 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12919 (const_int 0)))
12920 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12921 "TARGET_32BIT"
12922 "@
12923 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
12924 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
12925 #
12926 #"
12927 [(set_attr "type" "compare")
12928 (set_attr "length" "8,8,12,12")])
12929
12930 (define_split
12931 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12932 (compare:CC
12933 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12934 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12935 (match_operand:SI 3 "gpc_reg_operand" ""))
12936 (const_int 0)))
12937 (clobber (match_scratch:SI 4 ""))]
12938 "TARGET_32BIT && reload_completed"
12939 [(set (match_dup 4)
12940 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12941 (match_dup 3)))
12942 (set (match_dup 0)
12943 (compare:CC (match_dup 4)
12944 (const_int 0)))]
12945 "")
12946
12947 (define_insn ""
12948 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12949 (compare:CC
12950 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12951 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12952 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12953 (const_int 0)))
12954 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12955 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12956 "TARGET_32BIT"
12957 "@
12958 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
12959 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
12960 #
12961 #"
12962 [(set_attr "type" "compare")
12963 (set_attr "length" "8,8,12,12")])
12964
12965 (define_split
12966 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12967 (compare:CC
12968 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12969 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12970 (match_operand:SI 3 "gpc_reg_operand" ""))
12971 (const_int 0)))
12972 (set (match_operand:SI 0 "gpc_reg_operand" "")
12973 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12974 "TARGET_32BIT && reload_completed"
12975 [(set (match_dup 0)
12976 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12977 (set (match_dup 4)
12978 (compare:CC (match_dup 0)
12979 (const_int 0)))]
12980 "")
12981
12982 (define_insn "*neg_geu<mode>"
12983 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12984 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12985 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
12986 ""
12987 "@
12988 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
12989 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
12990 [(set_attr "type" "three")
12991 (set_attr "length" "12")])
12992
12993 (define_insn "*and_neg_geu<mode>"
12994 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12995 (and:P (neg:P
12996 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12997 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
12998 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12999 ""
13000 "@
13001 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
13002 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13003 [(set_attr "type" "three")
13004 (set_attr "length" "12")])
13005
13006 (define_insn ""
13007 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13008 (compare:CC
13009 (and:SI (neg:SI
13010 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13011 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13012 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13013 (const_int 0)))
13014 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13015 "TARGET_32BIT"
13016 "@
13017 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13018 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13019 #
13020 #"
13021 [(set_attr "type" "compare")
13022 (set_attr "length" "12,12,16,16")])
13023
13024 (define_split
13025 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13026 (compare:CC
13027 (and:SI (neg:SI
13028 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13029 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13030 (match_operand:SI 3 "gpc_reg_operand" ""))
13031 (const_int 0)))
13032 (clobber (match_scratch:SI 4 ""))]
13033 "TARGET_32BIT && reload_completed"
13034 [(set (match_dup 4)
13035 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13036 (match_dup 3)))
13037 (set (match_dup 0)
13038 (compare:CC (match_dup 4)
13039 (const_int 0)))]
13040 "")
13041
13042 (define_insn ""
13043 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13044 (compare:CC
13045 (and:SI (neg:SI
13046 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13047 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13048 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13049 (const_int 0)))
13050 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13051 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13052 "TARGET_32BIT"
13053 "@
13054 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13055 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13056 #
13057 #"
13058 [(set_attr "type" "compare")
13059 (set_attr "length" "12,12,16,16")])
13060
13061 (define_split
13062 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13063 (compare:CC
13064 (and:SI (neg:SI
13065 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13066 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13067 (match_operand:SI 3 "gpc_reg_operand" ""))
13068 (const_int 0)))
13069 (set (match_operand:SI 0 "gpc_reg_operand" "")
13070 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13071 "TARGET_32BIT && reload_completed"
13072 [(set (match_dup 0)
13073 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13074 (set (match_dup 4)
13075 (compare:CC (match_dup 0)
13076 (const_int 0)))]
13077 "")
13078
13079 (define_insn ""
13080 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13081 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13082 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13083 "TARGET_POWER"
13084 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13085 [(set_attr "length" "12")])
13086
13087 (define_insn ""
13088 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13089 (compare:CC
13090 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13091 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13092 (const_int 0)))
13093 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13094 (gt:SI (match_dup 1) (match_dup 2)))]
13095 "TARGET_POWER"
13096 "@
13097 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13098 #"
13099 [(set_attr "type" "delayed_compare")
13100 (set_attr "length" "12,16")])
13101
13102 (define_split
13103 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13104 (compare:CC
13105 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13106 (match_operand:SI 2 "reg_or_short_operand" ""))
13107 (const_int 0)))
13108 (set (match_operand:SI 0 "gpc_reg_operand" "")
13109 (gt:SI (match_dup 1) (match_dup 2)))]
13110 "TARGET_POWER && reload_completed"
13111 [(set (match_dup 0)
13112 (gt:SI (match_dup 1) (match_dup 2)))
13113 (set (match_dup 3)
13114 (compare:CC (match_dup 0)
13115 (const_int 0)))]
13116 "")
13117
13118 (define_insn "*plus_gt0<mode>"
13119 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13120 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13121 (const_int 0))
13122 (match_operand:P 2 "gpc_reg_operand" "r")))]
13123 ""
13124 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13125 [(set_attr "type" "three")
13126 (set_attr "length" "12")])
13127
13128 (define_insn ""
13129 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13130 (compare:CC
13131 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13132 (const_int 0))
13133 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13134 (const_int 0)))
13135 (clobber (match_scratch:SI 3 "=&r,&r"))]
13136 "TARGET_32BIT"
13137 "@
13138 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13139 #"
13140 [(set_attr "type" "compare")
13141 (set_attr "length" "12,16")])
13142
13143 (define_split
13144 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13145 (compare:CC
13146 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13147 (const_int 0))
13148 (match_operand:SI 2 "gpc_reg_operand" ""))
13149 (const_int 0)))
13150 (clobber (match_scratch:SI 3 ""))]
13151 "TARGET_32BIT && reload_completed"
13152 [(set (match_dup 3)
13153 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13154 (match_dup 2)))
13155 (set (match_dup 0)
13156 (compare:CC (match_dup 3)
13157 (const_int 0)))]
13158 "")
13159
13160 (define_insn ""
13161 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13162 (compare:CC
13163 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13164 (const_int 0))
13165 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13166 (const_int 0)))
13167 (clobber (match_scratch:DI 3 "=&r,&r"))]
13168 "TARGET_64BIT"
13169 "@
13170 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13171 #"
13172 [(set_attr "type" "compare")
13173 (set_attr "length" "12,16")])
13174
13175 (define_split
13176 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13177 (compare:CC
13178 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13179 (const_int 0))
13180 (match_operand:DI 2 "gpc_reg_operand" ""))
13181 (const_int 0)))
13182 (clobber (match_scratch:DI 3 ""))]
13183 "TARGET_64BIT && reload_completed"
13184 [(set (match_dup 3)
13185 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13186 (match_dup 2)))
13187 (set (match_dup 0)
13188 (compare:CC (match_dup 3)
13189 (const_int 0)))]
13190 "")
13191
13192 (define_insn ""
13193 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13194 (compare:CC
13195 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13196 (const_int 0))
13197 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13198 (const_int 0)))
13199 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13200 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13201 "TARGET_32BIT"
13202 "@
13203 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13204 #"
13205 [(set_attr "type" "compare")
13206 (set_attr "length" "12,16")])
13207
13208 (define_split
13209 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13210 (compare:CC
13211 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13212 (const_int 0))
13213 (match_operand:SI 2 "gpc_reg_operand" ""))
13214 (const_int 0)))
13215 (set (match_operand:SI 0 "gpc_reg_operand" "")
13216 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13217 "TARGET_32BIT && reload_completed"
13218 [(set (match_dup 0)
13219 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13220 (set (match_dup 3)
13221 (compare:CC (match_dup 0)
13222 (const_int 0)))]
13223 "")
13224
13225 (define_insn ""
13226 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13227 (compare:CC
13228 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13229 (const_int 0))
13230 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13231 (const_int 0)))
13232 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13233 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13234 "TARGET_64BIT"
13235 "@
13236 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13237 #"
13238 [(set_attr "type" "compare")
13239 (set_attr "length" "12,16")])
13240
13241 (define_split
13242 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13243 (compare:CC
13244 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13245 (const_int 0))
13246 (match_operand:DI 2 "gpc_reg_operand" ""))
13247 (const_int 0)))
13248 (set (match_operand:DI 0 "gpc_reg_operand" "")
13249 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13250 "TARGET_64BIT && reload_completed"
13251 [(set (match_dup 0)
13252 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13253 (set (match_dup 3)
13254 (compare:CC (match_dup 0)
13255 (const_int 0)))]
13256 "")
13257
13258 (define_insn ""
13259 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13260 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13261 (match_operand:SI 2 "reg_or_short_operand" "r"))
13262 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13263 "TARGET_POWER"
13264 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13265 [(set_attr "length" "12")])
13266
13267 (define_insn ""
13268 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13269 (compare:CC
13270 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13271 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13272 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13273 (const_int 0)))
13274 (clobber (match_scratch:SI 4 "=&r,&r"))]
13275 "TARGET_POWER"
13276 "@
13277 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13278 #"
13279 [(set_attr "type" "compare")
13280 (set_attr "length" "12,16")])
13281
13282 (define_split
13283 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13284 (compare:CC
13285 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13286 (match_operand:SI 2 "reg_or_short_operand" ""))
13287 (match_operand:SI 3 "gpc_reg_operand" ""))
13288 (const_int 0)))
13289 (clobber (match_scratch:SI 4 ""))]
13290 "TARGET_POWER && reload_completed"
13291 [(set (match_dup 4)
13292 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13293 (set (match_dup 0)
13294 (compare:CC (match_dup 4)
13295 (const_int 0)))]
13296 "")
13297
13298 (define_insn ""
13299 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13300 (compare:CC
13301 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13302 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13303 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13304 (const_int 0)))
13305 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13306 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13307 "TARGET_POWER"
13308 "@
13309 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13310 #"
13311 [(set_attr "type" "compare")
13312 (set_attr "length" "12,16")])
13313
13314 (define_split
13315 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13316 (compare:CC
13317 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13318 (match_operand:SI 2 "reg_or_short_operand" ""))
13319 (match_operand:SI 3 "gpc_reg_operand" ""))
13320 (const_int 0)))
13321 (set (match_operand:SI 0 "gpc_reg_operand" "")
13322 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13323 "TARGET_POWER && reload_completed"
13324 [(set (match_dup 0)
13325 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13326 (set (match_dup 4)
13327 (compare:CC (match_dup 0)
13328 (const_int 0)))]
13329 "")
13330
13331 (define_insn ""
13332 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13333 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13334 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13335 "TARGET_POWER"
13336 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13337 [(set_attr "length" "12")])
13338
13339 (define_insn_and_split "*gtu<mode>"
13340 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13341 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13342 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13343 ""
13344 "#"
13345 ""
13346 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13347 (set (match_dup 0) (neg:P (match_dup 0)))]
13348 "")
13349
13350 (define_insn_and_split "*gtu<mode>_compare"
13351 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13352 (compare:CC
13353 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13354 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13355 (const_int 0)))
13356 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13357 (gtu:P (match_dup 1) (match_dup 2)))]
13358 ""
13359 "#"
13360 ""
13361 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13362 (parallel [(set (match_dup 3)
13363 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13364 (set (match_dup 0) (neg:P (match_dup 0)))])]
13365 "")
13366
13367 (define_insn_and_split "*plus_gtu<mode>"
13368 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13369 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13370 (match_operand:P 2 "reg_or_short_operand" "rI"))
13371 (match_operand:P 3 "reg_or_short_operand" "rI")))]
13372 ""
13373 "#"
13374 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13375 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13376 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13377 "")
13378
13379 (define_insn_and_split "*plus_gtu<mode>_compare"
13380 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13381 (compare:CC
13382 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13383 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13384 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13385 (const_int 0)))
13386 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13387 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13388 ""
13389 "#"
13390 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13391 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13392 (parallel [(set (match_dup 4)
13393 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13394 (const_int 0)))
13395 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13396 "")
13397
13398 (define_insn "*neg_gtu<mode>"
13399 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13400 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13401 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13402 ""
13403 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13404 [(set_attr "type" "two")
13405 (set_attr "length" "8")])
13406
13407 \f
13408 ;; Define both directions of branch and return. If we need a reload
13409 ;; register, we'd rather use CR0 since it is much easier to copy a
13410 ;; register CC value to there.
13411
13412 (define_insn ""
13413 [(set (pc)
13414 (if_then_else (match_operator 1 "branch_comparison_operator"
13415 [(match_operand 2
13416 "cc_reg_operand" "y")
13417 (const_int 0)])
13418 (label_ref (match_operand 0 "" ""))
13419 (pc)))]
13420 ""
13421 "*
13422 {
13423 return output_cbranch (operands[1], \"%l0\", 0, insn);
13424 }"
13425 [(set_attr "type" "branch")])
13426
13427 (define_insn ""
13428 [(set (pc)
13429 (if_then_else (match_operator 0 "branch_comparison_operator"
13430 [(match_operand 1
13431 "cc_reg_operand" "y")
13432 (const_int 0)])
13433 (return)
13434 (pc)))]
13435 "direct_return ()"
13436 "*
13437 {
13438 return output_cbranch (operands[0], NULL, 0, insn);
13439 }"
13440 [(set_attr "type" "jmpreg")
13441 (set_attr "length" "4")])
13442
13443 (define_insn ""
13444 [(set (pc)
13445 (if_then_else (match_operator 1 "branch_comparison_operator"
13446 [(match_operand 2
13447 "cc_reg_operand" "y")
13448 (const_int 0)])
13449 (pc)
13450 (label_ref (match_operand 0 "" ""))))]
13451 ""
13452 "*
13453 {
13454 return output_cbranch (operands[1], \"%l0\", 1, insn);
13455 }"
13456 [(set_attr "type" "branch")])
13457
13458 (define_insn ""
13459 [(set (pc)
13460 (if_then_else (match_operator 0 "branch_comparison_operator"
13461 [(match_operand 1
13462 "cc_reg_operand" "y")
13463 (const_int 0)])
13464 (pc)
13465 (return)))]
13466 "direct_return ()"
13467 "*
13468 {
13469 return output_cbranch (operands[0], NULL, 1, insn);
13470 }"
13471 [(set_attr "type" "jmpreg")
13472 (set_attr "length" "4")])
13473
13474 ;; Logic on condition register values.
13475
13476 ; This pattern matches things like
13477 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13478 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13479 ; (const_int 1)))
13480 ; which are generated by the branch logic.
13481 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13482
13483 (define_insn "*cceq_ior_compare"
13484 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13485 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13486 [(match_operator:SI 2
13487 "branch_positive_comparison_operator"
13488 [(match_operand 3
13489 "cc_reg_operand" "y,y")
13490 (const_int 0)])
13491 (match_operator:SI 4
13492 "branch_positive_comparison_operator"
13493 [(match_operand 5
13494 "cc_reg_operand" "0,y")
13495 (const_int 0)])])
13496 (const_int 1)))]
13497 ""
13498 "cr%q1 %E0,%j2,%j4"
13499 [(set_attr "type" "cr_logical,delayed_cr")])
13500
13501 ; Why is the constant -1 here, but 1 in the previous pattern?
13502 ; Because ~1 has all but the low bit set.
13503 (define_insn ""
13504 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13505 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13506 [(not:SI (match_operator:SI 2
13507 "branch_positive_comparison_operator"
13508 [(match_operand 3
13509 "cc_reg_operand" "y,y")
13510 (const_int 0)]))
13511 (match_operator:SI 4
13512 "branch_positive_comparison_operator"
13513 [(match_operand 5
13514 "cc_reg_operand" "0,y")
13515 (const_int 0)])])
13516 (const_int -1)))]
13517 ""
13518 "cr%q1 %E0,%j2,%j4"
13519 [(set_attr "type" "cr_logical,delayed_cr")])
13520
13521 (define_insn "*cceq_rev_compare"
13522 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13523 (compare:CCEQ (match_operator:SI 1
13524 "branch_positive_comparison_operator"
13525 [(match_operand 2
13526 "cc_reg_operand" "0,y")
13527 (const_int 0)])
13528 (const_int 0)))]
13529 ""
13530 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
13531 [(set_attr "type" "cr_logical,delayed_cr")])
13532
13533 ;; If we are comparing the result of two comparisons, this can be done
13534 ;; using creqv or crxor.
13535
13536 (define_insn_and_split ""
13537 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13538 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13539 [(match_operand 2 "cc_reg_operand" "y")
13540 (const_int 0)])
13541 (match_operator 3 "branch_comparison_operator"
13542 [(match_operand 4 "cc_reg_operand" "y")
13543 (const_int 0)])))]
13544 ""
13545 "#"
13546 ""
13547 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13548 (match_dup 5)))]
13549 "
13550 {
13551 int positive_1, positive_2;
13552
13553 positive_1 = branch_positive_comparison_operator (operands[1],
13554 GET_MODE (operands[1]));
13555 positive_2 = branch_positive_comparison_operator (operands[3],
13556 GET_MODE (operands[3]));
13557
13558 if (! positive_1)
13559 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13560 GET_CODE (operands[1])),
13561 SImode,
13562 operands[2], const0_rtx);
13563 else if (GET_MODE (operands[1]) != SImode)
13564 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13565 operands[2], const0_rtx);
13566
13567 if (! positive_2)
13568 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13569 GET_CODE (operands[3])),
13570 SImode,
13571 operands[4], const0_rtx);
13572 else if (GET_MODE (operands[3]) != SImode)
13573 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13574 operands[4], const0_rtx);
13575
13576 if (positive_1 == positive_2)
13577 {
13578 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13579 operands[5] = constm1_rtx;
13580 }
13581 else
13582 {
13583 operands[5] = const1_rtx;
13584 }
13585 }")
13586
13587 ;; Unconditional branch and return.
13588
13589 (define_insn "jump"
13590 [(set (pc)
13591 (label_ref (match_operand 0 "" "")))]
13592 ""
13593 "b %l0"
13594 [(set_attr "type" "branch")])
13595
13596 (define_insn "return"
13597 [(return)]
13598 "direct_return ()"
13599 "{br|blr}"
13600 [(set_attr "type" "jmpreg")])
13601
13602 (define_expand "indirect_jump"
13603 [(set (pc) (match_operand 0 "register_operand" ""))])
13604
13605 (define_insn "*indirect_jump<mode>"
13606 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
13607 ""
13608 "@
13609 bctr
13610 {br|blr}"
13611 [(set_attr "type" "jmpreg")])
13612
13613 ;; Table jump for switch statements:
13614 (define_expand "tablejump"
13615 [(use (match_operand 0 "" ""))
13616 (use (label_ref (match_operand 1 "" "")))]
13617 ""
13618 "
13619 {
13620 if (TARGET_32BIT)
13621 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13622 else
13623 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13624 DONE;
13625 }")
13626
13627 (define_expand "tablejumpsi"
13628 [(set (match_dup 3)
13629 (plus:SI (match_operand:SI 0 "" "")
13630 (match_dup 2)))
13631 (parallel [(set (pc) (match_dup 3))
13632 (use (label_ref (match_operand 1 "" "")))])]
13633 "TARGET_32BIT"
13634 "
13635 { operands[0] = force_reg (SImode, operands[0]);
13636 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13637 operands[3] = gen_reg_rtx (SImode);
13638 }")
13639
13640 (define_expand "tablejumpdi"
13641 [(set (match_dup 4)
13642 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
13643 (set (match_dup 3)
13644 (plus:DI (match_dup 4)
13645 (match_dup 2)))
13646 (parallel [(set (pc) (match_dup 3))
13647 (use (label_ref (match_operand 1 "" "")))])]
13648 "TARGET_64BIT"
13649 "
13650 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13651 operands[3] = gen_reg_rtx (DImode);
13652 operands[4] = gen_reg_rtx (DImode);
13653 }")
13654
13655 (define_insn "*tablejump<mode>_internal1"
13656 [(set (pc)
13657 (match_operand:P 0 "register_operand" "c,*l"))
13658 (use (label_ref (match_operand 1 "" "")))]
13659 ""
13660 "@
13661 bctr
13662 {br|blr}"
13663 [(set_attr "type" "jmpreg")])
13664
13665 (define_insn "nop"
13666 [(const_int 0)]
13667 ""
13668 "{cror 0,0,0|nop}")
13669 \f
13670 ;; Define the subtract-one-and-jump insns, starting with the template
13671 ;; so loop.c knows what to generate.
13672
13673 (define_expand "doloop_end"
13674 [(use (match_operand 0 "" "")) ; loop pseudo
13675 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13676 (use (match_operand 2 "" "")) ; max iterations
13677 (use (match_operand 3 "" "")) ; loop level
13678 (use (match_operand 4 "" ""))] ; label
13679 ""
13680 "
13681 {
13682 /* Only use this on innermost loops. */
13683 if (INTVAL (operands[3]) > 1)
13684 FAIL;
13685 if (TARGET_64BIT)
13686 {
13687 if (GET_MODE (operands[0]) != DImode)
13688 FAIL;
13689 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13690 }
13691 else
13692 {
13693 if (GET_MODE (operands[0]) != SImode)
13694 FAIL;
13695 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13696 }
13697 DONE;
13698 }")
13699
13700 (define_expand "ctr<mode>"
13701 [(parallel [(set (pc)
13702 (if_then_else (ne (match_operand:P 0 "register_operand" "")
13703 (const_int 1))
13704 (label_ref (match_operand 1 "" ""))
13705 (pc)))
13706 (set (match_dup 0)
13707 (plus:P (match_dup 0)
13708 (const_int -1)))
13709 (clobber (match_scratch:CC 2 ""))
13710 (clobber (match_scratch:P 3 ""))])]
13711 ""
13712 "")
13713
13714 ;; We need to be able to do this for any operand, including MEM, or we
13715 ;; will cause reload to blow up since we don't allow output reloads on
13716 ;; JUMP_INSNs.
13717 ;; For the length attribute to be calculated correctly, the
13718 ;; label MUST be operand 0.
13719
13720 (define_insn "*ctr<mode>_internal1"
13721 [(set (pc)
13722 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13723 (const_int 1))
13724 (label_ref (match_operand 0 "" ""))
13725 (pc)))
13726 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13727 (plus:P (match_dup 1)
13728 (const_int -1)))
13729 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13730 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13731 ""
13732 "*
13733 {
13734 if (which_alternative != 0)
13735 return \"#\";
13736 else if (get_attr_length (insn) == 4)
13737 return \"{bdn|bdnz} %l0\";
13738 else
13739 return \"bdz $+8\;b %l0\";
13740 }"
13741 [(set_attr "type" "branch")
13742 (set_attr "length" "*,12,16,16")])
13743
13744 (define_insn "*ctr<mode>_internal2"
13745 [(set (pc)
13746 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13747 (const_int 1))
13748 (pc)
13749 (label_ref (match_operand 0 "" ""))))
13750 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13751 (plus:P (match_dup 1)
13752 (const_int -1)))
13753 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13754 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13755 ""
13756 "*
13757 {
13758 if (which_alternative != 0)
13759 return \"#\";
13760 else if (get_attr_length (insn) == 4)
13761 return \"bdz %l0\";
13762 else
13763 return \"{bdn|bdnz} $+8\;b %l0\";
13764 }"
13765 [(set_attr "type" "branch")
13766 (set_attr "length" "*,12,16,16")])
13767
13768 ;; Similar but use EQ
13769
13770 (define_insn "*ctr<mode>_internal5"
13771 [(set (pc)
13772 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13773 (const_int 1))
13774 (label_ref (match_operand 0 "" ""))
13775 (pc)))
13776 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13777 (plus:P (match_dup 1)
13778 (const_int -1)))
13779 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13780 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13781 ""
13782 "*
13783 {
13784 if (which_alternative != 0)
13785 return \"#\";
13786 else if (get_attr_length (insn) == 4)
13787 return \"bdz %l0\";
13788 else
13789 return \"{bdn|bdnz} $+8\;b %l0\";
13790 }"
13791 [(set_attr "type" "branch")
13792 (set_attr "length" "*,12,16,16")])
13793
13794 (define_insn "*ctr<mode>_internal6"
13795 [(set (pc)
13796 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13797 (const_int 1))
13798 (pc)
13799 (label_ref (match_operand 0 "" ""))))
13800 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13801 (plus:P (match_dup 1)
13802 (const_int -1)))
13803 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13804 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13805 ""
13806 "*
13807 {
13808 if (which_alternative != 0)
13809 return \"#\";
13810 else if (get_attr_length (insn) == 4)
13811 return \"{bdn|bdnz} %l0\";
13812 else
13813 return \"bdz $+8\;b %l0\";
13814 }"
13815 [(set_attr "type" "branch")
13816 (set_attr "length" "*,12,16,16")])
13817
13818 ;; Now the splitters if we could not allocate the CTR register
13819
13820 (define_split
13821 [(set (pc)
13822 (if_then_else (match_operator 2 "comparison_operator"
13823 [(match_operand:P 1 "gpc_reg_operand" "")
13824 (const_int 1)])
13825 (match_operand 5 "" "")
13826 (match_operand 6 "" "")))
13827 (set (match_operand:P 0 "gpc_reg_operand" "")
13828 (plus:P (match_dup 1) (const_int -1)))
13829 (clobber (match_scratch:CC 3 ""))
13830 (clobber (match_scratch:P 4 ""))]
13831 "reload_completed"
13832 [(parallel [(set (match_dup 3)
13833 (compare:CC (plus:P (match_dup 1)
13834 (const_int -1))
13835 (const_int 0)))
13836 (set (match_dup 0)
13837 (plus:P (match_dup 1)
13838 (const_int -1)))])
13839 (set (pc) (if_then_else (match_dup 7)
13840 (match_dup 5)
13841 (match_dup 6)))]
13842 "
13843 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13844 operands[3], const0_rtx); }")
13845
13846 (define_split
13847 [(set (pc)
13848 (if_then_else (match_operator 2 "comparison_operator"
13849 [(match_operand:P 1 "gpc_reg_operand" "")
13850 (const_int 1)])
13851 (match_operand 5 "" "")
13852 (match_operand 6 "" "")))
13853 (set (match_operand:P 0 "nonimmediate_operand" "")
13854 (plus:P (match_dup 1) (const_int -1)))
13855 (clobber (match_scratch:CC 3 ""))
13856 (clobber (match_scratch:P 4 ""))]
13857 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
13858 [(parallel [(set (match_dup 3)
13859 (compare:CC (plus:P (match_dup 1)
13860 (const_int -1))
13861 (const_int 0)))
13862 (set (match_dup 4)
13863 (plus:P (match_dup 1)
13864 (const_int -1)))])
13865 (set (match_dup 0)
13866 (match_dup 4))
13867 (set (pc) (if_then_else (match_dup 7)
13868 (match_dup 5)
13869 (match_dup 6)))]
13870 "
13871 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13872 operands[3], const0_rtx); }")
13873 \f
13874 (define_insn "trap"
13875 [(trap_if (const_int 1) (const_int 0))]
13876 ""
13877 "{t 31,0,0|trap}")
13878
13879 (define_expand "conditional_trap"
13880 [(trap_if (match_operator 0 "trap_comparison_operator"
13881 [(match_dup 2) (match_dup 3)])
13882 (match_operand 1 "const_int_operand" ""))]
13883 ""
13884 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
13885 operands[2] = rs6000_compare_op0;
13886 operands[3] = rs6000_compare_op1;")
13887
13888 (define_insn ""
13889 [(trap_if (match_operator 0 "trap_comparison_operator"
13890 [(match_operand:GPR 1 "register_operand" "r")
13891 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
13892 (const_int 0))]
13893 ""
13894 "{t|t<wd>}%V0%I2 %1,%2")
13895 \f
13896 ;; Insns related to generating the function prologue and epilogue.
13897
13898 (define_expand "prologue"
13899 [(use (const_int 0))]
13900 "TARGET_SCHED_PROLOG"
13901 "
13902 {
13903 rs6000_emit_prologue ();
13904 DONE;
13905 }")
13906
13907 (define_insn "*movesi_from_cr_one"
13908 [(match_parallel 0 "mfcr_operation"
13909 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13910 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
13911 (match_operand 3 "immediate_operand" "n")]
13912 UNSPEC_MOVESI_FROM_CR))])]
13913 "TARGET_MFCRF"
13914 "*
13915 {
13916 int mask = 0;
13917 int i;
13918 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13919 {
13920 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13921 operands[4] = GEN_INT (mask);
13922 output_asm_insn (\"mfcr %1,%4\", operands);
13923 }
13924 return \"\";
13925 }"
13926 [(set_attr "type" "mfcrf")])
13927
13928 (define_insn "movesi_from_cr"
13929 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13930 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
13931 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
13932 UNSPEC_MOVESI_FROM_CR))]
13933 ""
13934 "mfcr %0"
13935 [(set_attr "type" "mfcr")])
13936
13937 (define_insn "*stmw"
13938 [(match_parallel 0 "stmw_operation"
13939 [(set (match_operand:SI 1 "memory_operand" "=m")
13940 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13941 "TARGET_MULTIPLE"
13942 "{stm|stmw} %2,%1"
13943 [(set_attr "type" "store_ux")])
13944
13945 (define_insn "*save_fpregs_<mode>"
13946 [(match_parallel 0 "any_parallel_operand"
13947 [(clobber (match_operand:P 1 "register_operand" "=l"))
13948 (use (match_operand:P 2 "call_operand" "s"))
13949 (set (match_operand:DF 3 "memory_operand" "=m")
13950 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
13951 ""
13952 "bl %z2"
13953 [(set_attr "type" "branch")
13954 (set_attr "length" "4")])
13955
13956 ; These are to explain that changes to the stack pointer should
13957 ; not be moved over stores to stack memory.
13958 (define_insn "stack_tie"
13959 [(set (match_operand:BLK 0 "memory_operand" "+m")
13960 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
13961 ""
13962 ""
13963 [(set_attr "length" "0")])
13964
13965
13966 (define_expand "epilogue"
13967 [(use (const_int 0))]
13968 "TARGET_SCHED_PROLOG"
13969 "
13970 {
13971 rs6000_emit_epilogue (FALSE);
13972 DONE;
13973 }")
13974
13975 ; On some processors, doing the mtcrf one CC register at a time is
13976 ; faster (like on the 604e). On others, doing them all at once is
13977 ; faster; for instance, on the 601 and 750.
13978
13979 (define_expand "movsi_to_cr_one"
13980 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13981 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13982 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
13983 ""
13984 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
13985
13986 (define_insn "*movsi_to_cr"
13987 [(match_parallel 0 "mtcrf_operation"
13988 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
13989 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
13990 (match_operand 3 "immediate_operand" "n")]
13991 UNSPEC_MOVESI_TO_CR))])]
13992 ""
13993 "*
13994 {
13995 int mask = 0;
13996 int i;
13997 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13998 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13999 operands[4] = GEN_INT (mask);
14000 return \"mtcrf %4,%2\";
14001 }"
14002 [(set_attr "type" "mtcr")])
14003
14004 (define_insn "*mtcrfsi"
14005 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14006 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14007 (match_operand 2 "immediate_operand" "n")]
14008 UNSPEC_MOVESI_TO_CR))]
14009 "GET_CODE (operands[0]) == REG
14010 && CR_REGNO_P (REGNO (operands[0]))
14011 && GET_CODE (operands[2]) == CONST_INT
14012 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14013 "mtcrf %R0,%1"
14014 [(set_attr "type" "mtcr")])
14015
14016 ; The load-multiple instructions have similar properties.
14017 ; Note that "load_multiple" is a name known to the machine-independent
14018 ; code that actually corresponds to the PowerPC load-string.
14019
14020 (define_insn "*lmw"
14021 [(match_parallel 0 "lmw_operation"
14022 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14023 (match_operand:SI 2 "memory_operand" "m"))])]
14024 "TARGET_MULTIPLE"
14025 "{lm|lmw} %1,%2"
14026 [(set_attr "type" "load_ux")])
14027
14028 (define_insn "*return_internal_<mode>"
14029 [(return)
14030 (use (match_operand:P 0 "register_operand" "lc"))]
14031 ""
14032 "b%T0"
14033 [(set_attr "type" "jmpreg")])
14034
14035 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14036 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14037
14038 (define_insn "*return_and_restore_fpregs_<mode>"
14039 [(match_parallel 0 "any_parallel_operand"
14040 [(return)
14041 (use (match_operand:P 1 "register_operand" "l"))
14042 (use (match_operand:P 2 "call_operand" "s"))
14043 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14044 (match_operand:DF 4 "memory_operand" "m"))])]
14045 ""
14046 "b %z2")
14047
14048 ; This is used in compiling the unwind routines.
14049 (define_expand "eh_return"
14050 [(use (match_operand 0 "general_operand" ""))]
14051 ""
14052 "
14053 {
14054 if (TARGET_32BIT)
14055 emit_insn (gen_eh_set_lr_si (operands[0]));
14056 else
14057 emit_insn (gen_eh_set_lr_di (operands[0]));
14058 DONE;
14059 }")
14060
14061 ; We can't expand this before we know where the link register is stored.
14062 (define_insn "eh_set_lr_<mode>"
14063 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
14064 UNSPECV_EH_RR)
14065 (clobber (match_scratch:P 1 "=&b"))]
14066 ""
14067 "#")
14068
14069 (define_split
14070 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14071 (clobber (match_scratch 1 ""))]
14072 "reload_completed"
14073 [(const_int 0)]
14074 "
14075 {
14076 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14077 DONE;
14078 }")
14079
14080 (define_insn "prefetch"
14081 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
14082 (match_operand:SI 1 "const_int_operand" "n")
14083 (match_operand:SI 2 "const_int_operand" "n"))]
14084 "TARGET_POWERPC"
14085 "*
14086 {
14087 if (GET_CODE (operands[0]) == REG)
14088 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14089 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14090 }"
14091 [(set_attr "type" "load")])
14092 \f
14093
14094 (include "sync.md")
14095 (include "altivec.md")
14096 (include "spe.md")
Mirror of https://gcc.gnu.org/git/gcc.git