1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 3, or (at your
12 ;; option) any later version.
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
43 (FIRST_ALTIVEC_REGNO 77)
44 (LAST_ALTIVEC_REGNO 108)
57 [(UNSPEC_FRSP 0) ; frsp for POWER machines
58 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
59 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
60 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
62 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
68 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
69 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
72 (UNSPEC_MOVESI_FROM_CR 19)
73 (UNSPEC_MOVESI_TO_CR 20)
75 (UNSPEC_TLSDTPRELHA 22)
76 (UNSPEC_TLSDTPRELLO 23)
77 (UNSPEC_TLSGOTDTPREL 24)
79 (UNSPEC_TLSTPRELHA 26)
80 (UNSPEC_TLSTPRELLO 27)
81 (UNSPEC_TLSGOTTPREL 28)
83 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
84 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
100 (UNSPEC_DLMZB_STRLEN 47)
103 (UNSPEC_MACHOPIC_OFFSET 50)
107 ;; UNSPEC_VOLATILE usage
112 (UNSPECV_LL 1) ; load-locked
113 (UNSPECV_SC 2) ; store-conditional
114 (UNSPECV_EH_RR 9) ; eh_reg_restore
117 ;; Define an insn type attribute. This is used in function unit delay
119 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr"
120 (const_string "integer"))
122 ;; Define floating point instruction sub-types for use with Xfpu.md
123 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
125 ;; Length (in bytes).
126 ; '(pc)' in the following doesn't include the instruction itself; it is
127 ; calculated as if the instruction had zero size.
128 (define_attr "length" ""
129 (if_then_else (eq_attr "type" "branch")
130 (if_then_else (and (ge (minus (match_dup 0) (pc))
132 (lt (minus (match_dup 0) (pc))
138 ;; Processor type -- this attribute must exactly match the processor_type
139 ;; enumeration in rs6000.h.
141 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,power4,power5,power6,cell"
142 (const (symbol_ref "rs6000_cpu_attr")))
145 ;; If this instruction is microcoded on the CELL processor
146 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
147 (define_attr "cell_micro" "not,conditional,always"
148 (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
149 (const_string "always")
150 (const_string "not")))
152 (automata_option "ndfa")
165 (include "e300c2c3.md")
166 (include "e500mc.md")
167 (include "power4.md")
168 (include "power5.md")
169 (include "power6.md")
173 (include "predicates.md")
174 (include "constraints.md")
176 (include "darwin.md")
181 ; This mode iterator allows :GPR to be used to indicate the allowable size
182 ; of whole values in GPRs.
183 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
185 ; Any supported integer mode.
186 (define_mode_iterator INT [QI HI SI DI TI])
188 ; Any supported integer mode that fits in one register.
189 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
191 ; extend modes for DImode
192 (define_mode_iterator QHSI [QI HI SI])
194 ; SImode or DImode, even if DImode doesn't fit in GPRs.
195 (define_mode_iterator SDI [SI DI])
197 ; The size of a pointer. Also, the size of the value that a record-condition
198 ; (one with a '.') will compare.
199 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
201 ; Any hardware-supported floating-point mode
202 (define_mode_iterator FP [
203 (SF "TARGET_HARD_FLOAT
204 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
205 (DF "TARGET_HARD_FLOAT
206 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
207 (TF "!TARGET_IEEEQUAD
209 && (TARGET_FPRS || TARGET_E500_DOUBLE)
210 && TARGET_LONG_DOUBLE_128")
214 ; Various instructions that come in SI and DI forms.
215 ; A generic w/d attribute, for things like cmpw/cmpd.
216 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
219 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
222 ;; Start with fixed-point load and store insns. Here we put only the more
223 ;; complex forms. Basic data transfer is done later.
225 (define_expand "zero_extend<mode>di2"
226 [(set (match_operand:DI 0 "gpc_reg_operand" "")
227 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
231 (define_insn "*zero_extend<mode>di2_internal1"
232 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
233 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
237 rldicl %0,%1,0,<dbits>"
238 [(set_attr "type" "load,*")])
240 (define_insn "*zero_extend<mode>di2_internal2"
241 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
242 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
244 (clobber (match_scratch:DI 2 "=r,r"))]
247 rldicl. %2,%1,0,<dbits>
249 [(set_attr "type" "compare")
250 (set_attr "length" "4,8")])
253 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
254 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
256 (clobber (match_scratch:DI 2 ""))]
257 "TARGET_POWERPC64 && reload_completed"
259 (zero_extend:DI (match_dup 1)))
261 (compare:CC (match_dup 2)
265 (define_insn "*zero_extend<mode>di2_internal3"
266 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
267 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
269 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
270 (zero_extend:DI (match_dup 1)))]
273 rldicl. %0,%1,0,<dbits>
275 [(set_attr "type" "compare")
276 (set_attr "length" "4,8")])
279 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
280 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
282 (set (match_operand:DI 0 "gpc_reg_operand" "")
283 (zero_extend:DI (match_dup 1)))]
284 "TARGET_POWERPC64 && reload_completed"
286 (zero_extend:DI (match_dup 1)))
288 (compare:CC (match_dup 0)
292 (define_insn "extendqidi2"
293 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
294 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
297 [(set_attr "type" "exts")])
300 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
301 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
303 (clobber (match_scratch:DI 2 "=r,r"))]
308 [(set_attr "type" "compare")
309 (set_attr "length" "4,8")])
312 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
313 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
315 (clobber (match_scratch:DI 2 ""))]
316 "TARGET_POWERPC64 && reload_completed"
318 (sign_extend:DI (match_dup 1)))
320 (compare:CC (match_dup 2)
325 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
326 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
328 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
329 (sign_extend:DI (match_dup 1)))]
334 [(set_attr "type" "compare")
335 (set_attr "length" "4,8")])
338 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
339 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
341 (set (match_operand:DI 0 "gpc_reg_operand" "")
342 (sign_extend:DI (match_dup 1)))]
343 "TARGET_POWERPC64 && reload_completed"
345 (sign_extend:DI (match_dup 1)))
347 (compare:CC (match_dup 0)
351 (define_expand "extendhidi2"
352 [(set (match_operand:DI 0 "gpc_reg_operand" "")
353 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
358 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
359 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
360 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
364 [(set_attr "type" "load_ext,exts")])
367 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
368 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
369 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
371 [(set_attr "type" "exts")])
374 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
375 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
377 (clobber (match_scratch:DI 2 "=r,r"))]
382 [(set_attr "type" "compare")
383 (set_attr "length" "4,8")])
386 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
387 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
389 (clobber (match_scratch:DI 2 ""))]
390 "TARGET_POWERPC64 && reload_completed"
392 (sign_extend:DI (match_dup 1)))
394 (compare:CC (match_dup 2)
399 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
400 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
402 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
403 (sign_extend:DI (match_dup 1)))]
408 [(set_attr "type" "compare")
409 (set_attr "length" "4,8")])
412 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
413 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
415 (set (match_operand:DI 0 "gpc_reg_operand" "")
416 (sign_extend:DI (match_dup 1)))]
417 "TARGET_POWERPC64 && reload_completed"
419 (sign_extend:DI (match_dup 1)))
421 (compare:CC (match_dup 0)
425 (define_expand "extendsidi2"
426 [(set (match_operand:DI 0 "gpc_reg_operand" "")
427 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
432 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
433 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
434 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
438 [(set_attr "type" "load_ext,exts")])
441 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
442 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
443 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
445 [(set_attr "type" "exts")])
448 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
449 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
451 (clobber (match_scratch:DI 2 "=r,r"))]
456 [(set_attr "type" "compare")
457 (set_attr "length" "4,8")])
460 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
461 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
463 (clobber (match_scratch:DI 2 ""))]
464 "TARGET_POWERPC64 && reload_completed"
466 (sign_extend:DI (match_dup 1)))
468 (compare:CC (match_dup 2)
473 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
474 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
476 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
477 (sign_extend:DI (match_dup 1)))]
482 [(set_attr "type" "compare")
483 (set_attr "length" "4,8")])
486 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
487 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
489 (set (match_operand:DI 0 "gpc_reg_operand" "")
490 (sign_extend:DI (match_dup 1)))]
491 "TARGET_POWERPC64 && reload_completed"
493 (sign_extend:DI (match_dup 1)))
495 (compare:CC (match_dup 0)
499 (define_expand "zero_extendqisi2"
500 [(set (match_operand:SI 0 "gpc_reg_operand" "")
501 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
506 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
507 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
511 {rlinm|rlwinm} %0,%1,0,0xff"
512 [(set_attr "type" "load,*")])
515 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
516 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
518 (clobber (match_scratch:SI 2 "=r,r"))]
521 {andil.|andi.} %2,%1,0xff
523 [(set_attr "type" "compare")
524 (set_attr "length" "4,8")])
527 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
528 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
530 (clobber (match_scratch:SI 2 ""))]
533 (zero_extend:SI (match_dup 1)))
535 (compare:CC (match_dup 2)
540 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
541 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
543 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
544 (zero_extend:SI (match_dup 1)))]
547 {andil.|andi.} %0,%1,0xff
549 [(set_attr "type" "compare")
550 (set_attr "length" "4,8")])
553 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
554 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
556 (set (match_operand:SI 0 "gpc_reg_operand" "")
557 (zero_extend:SI (match_dup 1)))]
560 (zero_extend:SI (match_dup 1)))
562 (compare:CC (match_dup 0)
566 (define_expand "extendqisi2"
567 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
568 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
573 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
574 else if (TARGET_POWER)
575 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
577 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
581 (define_insn "extendqisi2_ppc"
582 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
583 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
586 [(set_attr "type" "exts")])
589 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
590 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
592 (clobber (match_scratch:SI 2 "=r,r"))]
597 [(set_attr "type" "compare")
598 (set_attr "length" "4,8")])
601 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
602 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
604 (clobber (match_scratch:SI 2 ""))]
605 "TARGET_POWERPC && reload_completed"
607 (sign_extend:SI (match_dup 1)))
609 (compare:CC (match_dup 2)
614 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
615 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
617 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
618 (sign_extend:SI (match_dup 1)))]
623 [(set_attr "type" "compare")
624 (set_attr "length" "4,8")])
627 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
628 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
630 (set (match_operand:SI 0 "gpc_reg_operand" "")
631 (sign_extend:SI (match_dup 1)))]
632 "TARGET_POWERPC && reload_completed"
634 (sign_extend:SI (match_dup 1)))
636 (compare:CC (match_dup 0)
640 (define_expand "extendqisi2_power"
641 [(parallel [(set (match_dup 2)
642 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
644 (clobber (scratch:SI))])
645 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
646 (ashiftrt:SI (match_dup 2)
648 (clobber (scratch:SI))])]
651 { operands[1] = gen_lowpart (SImode, operands[1]);
652 operands[2] = gen_reg_rtx (SImode); }")
654 (define_expand "extendqisi2_no_power"
656 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
658 (set (match_operand:SI 0 "gpc_reg_operand" "")
659 (ashiftrt:SI (match_dup 2)
661 "! TARGET_POWER && ! TARGET_POWERPC"
663 { operands[1] = gen_lowpart (SImode, operands[1]);
664 operands[2] = gen_reg_rtx (SImode); }")
666 (define_expand "zero_extendqihi2"
667 [(set (match_operand:HI 0 "gpc_reg_operand" "")
668 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
673 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
674 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
678 {rlinm|rlwinm} %0,%1,0,0xff"
679 [(set_attr "type" "load,*")])
682 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
683 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
685 (clobber (match_scratch:HI 2 "=r,r"))]
688 {andil.|andi.} %2,%1,0xff
690 [(set_attr "type" "compare")
691 (set_attr "length" "4,8")])
694 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
695 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
697 (clobber (match_scratch:HI 2 ""))]
700 (zero_extend:HI (match_dup 1)))
702 (compare:CC (match_dup 2)
707 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
708 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
710 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
711 (zero_extend:HI (match_dup 1)))]
714 {andil.|andi.} %0,%1,0xff
716 [(set_attr "type" "compare")
717 (set_attr "length" "4,8")])
720 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
721 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
723 (set (match_operand:HI 0 "gpc_reg_operand" "")
724 (zero_extend:HI (match_dup 1)))]
727 (zero_extend:HI (match_dup 1)))
729 (compare:CC (match_dup 0)
733 (define_expand "extendqihi2"
734 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
735 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
740 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
741 else if (TARGET_POWER)
742 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
744 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
748 (define_insn "extendqihi2_ppc"
749 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
750 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
753 [(set_attr "type" "exts")])
756 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
757 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
759 (clobber (match_scratch:HI 2 "=r,r"))]
764 [(set_attr "type" "compare")
765 (set_attr "length" "4,8")])
768 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
769 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
771 (clobber (match_scratch:HI 2 ""))]
772 "TARGET_POWERPC && reload_completed"
774 (sign_extend:HI (match_dup 1)))
776 (compare:CC (match_dup 2)
781 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
782 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
784 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
785 (sign_extend:HI (match_dup 1)))]
790 [(set_attr "type" "compare")
791 (set_attr "length" "4,8")])
794 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
795 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
797 (set (match_operand:HI 0 "gpc_reg_operand" "")
798 (sign_extend:HI (match_dup 1)))]
799 "TARGET_POWERPC && reload_completed"
801 (sign_extend:HI (match_dup 1)))
803 (compare:CC (match_dup 0)
807 (define_expand "extendqihi2_power"
808 [(parallel [(set (match_dup 2)
809 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
811 (clobber (scratch:SI))])
812 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
813 (ashiftrt:SI (match_dup 2)
815 (clobber (scratch:SI))])]
818 { operands[0] = gen_lowpart (SImode, operands[0]);
819 operands[1] = gen_lowpart (SImode, operands[1]);
820 operands[2] = gen_reg_rtx (SImode); }")
822 (define_expand "extendqihi2_no_power"
824 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
826 (set (match_operand:HI 0 "gpc_reg_operand" "")
827 (ashiftrt:SI (match_dup 2)
829 "! TARGET_POWER && ! TARGET_POWERPC"
831 { operands[0] = gen_lowpart (SImode, operands[0]);
832 operands[1] = gen_lowpart (SImode, operands[1]);
833 operands[2] = gen_reg_rtx (SImode); }")
835 (define_expand "zero_extendhisi2"
836 [(set (match_operand:SI 0 "gpc_reg_operand" "")
837 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
842 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
843 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
847 {rlinm|rlwinm} %0,%1,0,0xffff"
848 [(set_attr "type" "load,*")])
851 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
852 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
854 (clobber (match_scratch:SI 2 "=r,r"))]
857 {andil.|andi.} %2,%1,0xffff
859 [(set_attr "type" "compare")
860 (set_attr "length" "4,8")])
863 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
864 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
866 (clobber (match_scratch:SI 2 ""))]
869 (zero_extend:SI (match_dup 1)))
871 (compare:CC (match_dup 2)
876 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
877 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
879 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
880 (zero_extend:SI (match_dup 1)))]
883 {andil.|andi.} %0,%1,0xffff
885 [(set_attr "type" "compare")
886 (set_attr "length" "4,8")])
889 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
890 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
892 (set (match_operand:SI 0 "gpc_reg_operand" "")
893 (zero_extend:SI (match_dup 1)))]
896 (zero_extend:SI (match_dup 1)))
898 (compare:CC (match_dup 0)
902 (define_expand "extendhisi2"
903 [(set (match_operand:SI 0 "gpc_reg_operand" "")
904 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
909 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
910 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
911 "rs6000_gen_cell_microcode"
915 [(set_attr "type" "load_ext,exts")])
918 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
919 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
920 "!rs6000_gen_cell_microcode"
922 [(set_attr "type" "exts")])
925 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
926 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
928 (clobber (match_scratch:SI 2 "=r,r"))]
933 [(set_attr "type" "compare")
934 (set_attr "length" "4,8")])
937 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
938 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
940 (clobber (match_scratch:SI 2 ""))]
943 (sign_extend:SI (match_dup 1)))
945 (compare:CC (match_dup 2)
950 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
951 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
953 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
954 (sign_extend:SI (match_dup 1)))]
959 [(set_attr "type" "compare")
960 (set_attr "length" "4,8")])
962 ;; IBM 405, 440 and 464 half-word multiplication operations.
964 (define_insn "*macchwc"
965 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
966 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
967 (match_operand:SI 2 "gpc_reg_operand" "r")
970 (match_operand:HI 1 "gpc_reg_operand" "r")))
971 (match_operand:SI 4 "gpc_reg_operand" "0"))
973 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
974 (plus:SI (mult:SI (ashiftrt:SI
982 [(set_attr "type" "imul3")])
984 (define_insn "*macchw"
985 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
986 (plus:SI (mult:SI (ashiftrt:SI
987 (match_operand:SI 2 "gpc_reg_operand" "r")
990 (match_operand:HI 1 "gpc_reg_operand" "r")))
991 (match_operand:SI 3 "gpc_reg_operand" "0")))]
994 [(set_attr "type" "imul3")])
996 (define_insn "*macchwuc"
997 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
998 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
999 (match_operand:SI 2 "gpc_reg_operand" "r")
1002 (match_operand:HI 1 "gpc_reg_operand" "r")))
1003 (match_operand:SI 4 "gpc_reg_operand" "0"))
1005 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1006 (plus:SI (mult:SI (lshiftrt:SI
1013 "macchwu. %0, %1, %2"
1014 [(set_attr "type" "imul3")])
1016 (define_insn "*macchwu"
1017 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1018 (plus:SI (mult:SI (lshiftrt:SI
1019 (match_operand:SI 2 "gpc_reg_operand" "r")
1022 (match_operand:HI 1 "gpc_reg_operand" "r")))
1023 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1025 "macchwu %0, %1, %2"
1026 [(set_attr "type" "imul3")])
1028 (define_insn "*machhwc"
1029 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1030 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1031 (match_operand:SI 1 "gpc_reg_operand" "%r")
1034 (match_operand:SI 2 "gpc_reg_operand" "r")
1036 (match_operand:SI 4 "gpc_reg_operand" "0"))
1038 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1039 (plus:SI (mult:SI (ashiftrt:SI
1047 "machhw. %0, %1, %2"
1048 [(set_attr "type" "imul3")])
1050 (define_insn "*machhw"
1051 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1052 (plus:SI (mult:SI (ashiftrt:SI
1053 (match_operand:SI 1 "gpc_reg_operand" "%r")
1056 (match_operand:SI 2 "gpc_reg_operand" "r")
1058 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1061 [(set_attr "type" "imul3")])
1063 (define_insn "*machhwuc"
1064 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1065 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1066 (match_operand:SI 1 "gpc_reg_operand" "%r")
1069 (match_operand:SI 2 "gpc_reg_operand" "r")
1071 (match_operand:SI 4 "gpc_reg_operand" "0"))
1073 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1074 (plus:SI (mult:SI (lshiftrt:SI
1082 "machhwu. %0, %1, %2"
1083 [(set_attr "type" "imul3")])
1085 (define_insn "*machhwu"
1086 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1087 (plus:SI (mult:SI (lshiftrt:SI
1088 (match_operand:SI 1 "gpc_reg_operand" "%r")
1091 (match_operand:SI 2 "gpc_reg_operand" "r")
1093 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1095 "machhwu %0, %1, %2"
1096 [(set_attr "type" "imul3")])
1098 (define_insn "*maclhwc"
1099 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1100 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1101 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1103 (match_operand:HI 2 "gpc_reg_operand" "r")))
1104 (match_operand:SI 4 "gpc_reg_operand" "0"))
1106 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1107 (plus:SI (mult:SI (sign_extend:SI
1113 "maclhw. %0, %1, %2"
1114 [(set_attr "type" "imul3")])
1116 (define_insn "*maclhw"
1117 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1118 (plus:SI (mult:SI (sign_extend:SI
1119 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1121 (match_operand:HI 2 "gpc_reg_operand" "r")))
1122 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1125 [(set_attr "type" "imul3")])
1127 (define_insn "*maclhwuc"
1128 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1129 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1130 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1132 (match_operand:HI 2 "gpc_reg_operand" "r")))
1133 (match_operand:SI 4 "gpc_reg_operand" "0"))
1135 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1136 (plus:SI (mult:SI (zero_extend:SI
1142 "maclhwu. %0, %1, %2"
1143 [(set_attr "type" "imul3")])
1145 (define_insn "*maclhwu"
1146 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1147 (plus:SI (mult:SI (zero_extend:SI
1148 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1150 (match_operand:HI 2 "gpc_reg_operand" "r")))
1151 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1153 "maclhwu %0, %1, %2"
1154 [(set_attr "type" "imul3")])
1156 (define_insn "*nmacchwc"
1157 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1158 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1159 (mult:SI (ashiftrt:SI
1160 (match_operand:SI 2 "gpc_reg_operand" "r")
1163 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1165 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1166 (minus:SI (match_dup 4)
1167 (mult:SI (ashiftrt:SI
1173 "nmacchw. %0, %1, %2"
1174 [(set_attr "type" "imul3")])
1176 (define_insn "*nmacchw"
1177 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1178 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1179 (mult:SI (ashiftrt:SI
1180 (match_operand:SI 2 "gpc_reg_operand" "r")
1183 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1185 "nmacchw %0, %1, %2"
1186 [(set_attr "type" "imul3")])
1188 (define_insn "*nmachhwc"
1189 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1190 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1191 (mult:SI (ashiftrt:SI
1192 (match_operand:SI 1 "gpc_reg_operand" "%r")
1195 (match_operand:SI 2 "gpc_reg_operand" "r")
1198 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1199 (minus:SI (match_dup 4)
1200 (mult:SI (ashiftrt:SI
1207 "nmachhw. %0, %1, %2"
1208 [(set_attr "type" "imul3")])
1210 (define_insn "*nmachhw"
1211 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1212 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1213 (mult:SI (ashiftrt:SI
1214 (match_operand:SI 1 "gpc_reg_operand" "%r")
1217 (match_operand:SI 2 "gpc_reg_operand" "r")
1220 "nmachhw %0, %1, %2"
1221 [(set_attr "type" "imul3")])
1223 (define_insn "*nmaclhwc"
1224 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1225 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1226 (mult:SI (sign_extend:SI
1227 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1229 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1231 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1232 (minus:SI (match_dup 4)
1233 (mult:SI (sign_extend:SI
1238 "nmaclhw. %0, %1, %2"
1239 [(set_attr "type" "imul3")])
1241 (define_insn "*nmaclhw"
1242 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1243 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1244 (mult:SI (sign_extend:SI
1245 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1247 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1249 "nmaclhw %0, %1, %2"
1250 [(set_attr "type" "imul3")])
1252 (define_insn "*mulchwc"
1253 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1254 (compare:CC (mult:SI (ashiftrt:SI
1255 (match_operand:SI 2 "gpc_reg_operand" "r")
1258 (match_operand:HI 1 "gpc_reg_operand" "r")))
1260 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1261 (mult:SI (ashiftrt:SI
1267 "mulchw. %0, %1, %2"
1268 [(set_attr "type" "imul3")])
1270 (define_insn "*mulchw"
1271 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1272 (mult:SI (ashiftrt:SI
1273 (match_operand:SI 2 "gpc_reg_operand" "r")
1276 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1279 [(set_attr "type" "imul3")])
1281 (define_insn "*mulchwuc"
1282 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1283 (compare:CC (mult:SI (lshiftrt:SI
1284 (match_operand:SI 2 "gpc_reg_operand" "r")
1287 (match_operand:HI 1 "gpc_reg_operand" "r")))
1289 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1290 (mult:SI (lshiftrt:SI
1296 "mulchwu. %0, %1, %2"
1297 [(set_attr "type" "imul3")])
1299 (define_insn "*mulchwu"
1300 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1301 (mult:SI (lshiftrt:SI
1302 (match_operand:SI 2 "gpc_reg_operand" "r")
1305 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1307 "mulchwu %0, %1, %2"
1308 [(set_attr "type" "imul3")])
1310 (define_insn "*mulhhwc"
1311 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1312 (compare:CC (mult:SI (ashiftrt:SI
1313 (match_operand:SI 1 "gpc_reg_operand" "%r")
1316 (match_operand:SI 2 "gpc_reg_operand" "r")
1319 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1320 (mult:SI (ashiftrt:SI
1327 "mulhhw. %0, %1, %2"
1328 [(set_attr "type" "imul3")])
1330 (define_insn "*mulhhw"
1331 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1332 (mult:SI (ashiftrt:SI
1333 (match_operand:SI 1 "gpc_reg_operand" "%r")
1336 (match_operand:SI 2 "gpc_reg_operand" "r")
1340 [(set_attr "type" "imul3")])
1342 (define_insn "*mulhhwuc"
1343 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1344 (compare:CC (mult:SI (lshiftrt:SI
1345 (match_operand:SI 1 "gpc_reg_operand" "%r")
1348 (match_operand:SI 2 "gpc_reg_operand" "r")
1351 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1352 (mult:SI (lshiftrt:SI
1359 "mulhhwu. %0, %1, %2"
1360 [(set_attr "type" "imul3")])
1362 (define_insn "*mulhhwu"
1363 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1364 (mult:SI (lshiftrt:SI
1365 (match_operand:SI 1 "gpc_reg_operand" "%r")
1368 (match_operand:SI 2 "gpc_reg_operand" "r")
1371 "mulhhwu %0, %1, %2"
1372 [(set_attr "type" "imul3")])
1374 (define_insn "*mullhwc"
1375 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1376 (compare:CC (mult:SI (sign_extend:SI
1377 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1379 (match_operand:HI 2 "gpc_reg_operand" "r")))
1381 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1382 (mult:SI (sign_extend:SI
1387 "mullhw. %0, %1, %2"
1388 [(set_attr "type" "imul3")])
1390 (define_insn "*mullhw"
1391 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1392 (mult:SI (sign_extend:SI
1393 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1395 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1398 [(set_attr "type" "imul3")])
1400 (define_insn "*mullhwuc"
1401 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1402 (compare:CC (mult:SI (zero_extend:SI
1403 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1405 (match_operand:HI 2 "gpc_reg_operand" "r")))
1407 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1408 (mult:SI (zero_extend:SI
1413 "mullhwu. %0, %1, %2"
1414 [(set_attr "type" "imul3")])
1416 (define_insn "*mullhwu"
1417 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1418 (mult:SI (zero_extend:SI
1419 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1421 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1423 "mullhwu %0, %1, %2"
1424 [(set_attr "type" "imul3")])
1426 ;; IBM 405, 440 and 464 string-search dlmzb instruction support.
1427 (define_insn "dlmzb"
1428 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1429 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1430 (match_operand:SI 2 "gpc_reg_operand" "r")]
1432 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1433 (unspec:SI [(match_dup 1)
1437 "dlmzb. %0, %1, %2")
1439 (define_expand "strlensi"
1440 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1441 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1442 (match_operand:QI 2 "const_int_operand" "")
1443 (match_operand 3 "const_int_operand" "")]
1444 UNSPEC_DLMZB_STRLEN))
1445 (clobber (match_scratch:CC 4 "=x"))]
1446 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1448 rtx result = operands[0];
1449 rtx src = operands[1];
1450 rtx search_char = operands[2];
1451 rtx align = operands[3];
1452 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1453 rtx loop_label, end_label, mem, cr0, cond;
1454 if (search_char != const0_rtx
1455 || GET_CODE (align) != CONST_INT
1456 || INTVAL (align) < 8)
1458 word1 = gen_reg_rtx (SImode);
1459 word2 = gen_reg_rtx (SImode);
1460 scratch_dlmzb = gen_reg_rtx (SImode);
1461 scratch_string = gen_reg_rtx (Pmode);
1462 loop_label = gen_label_rtx ();
1463 end_label = gen_label_rtx ();
1464 addr = force_reg (Pmode, XEXP (src, 0));
1465 emit_move_insn (scratch_string, addr);
1466 emit_label (loop_label);
1467 mem = change_address (src, SImode, scratch_string);
1468 emit_move_insn (word1, mem);
1469 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1470 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1471 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1472 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1473 emit_jump_insn (gen_rtx_SET (VOIDmode,
1475 gen_rtx_IF_THEN_ELSE (VOIDmode,
1481 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1482 emit_jump_insn (gen_rtx_SET (VOIDmode,
1484 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1486 emit_label (end_label);
1487 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1488 emit_insn (gen_subsi3 (result, scratch_string, addr));
1489 emit_insn (gen_subsi3 (result, result, const1_rtx));
1494 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1495 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1497 (set (match_operand:SI 0 "gpc_reg_operand" "")
1498 (sign_extend:SI (match_dup 1)))]
1501 (sign_extend:SI (match_dup 1)))
1503 (compare:CC (match_dup 0)
1507 ;; Fixed-point arithmetic insns.
1509 (define_expand "add<mode>3"
1510 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1511 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1512 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1515 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1517 if (non_short_cint_operand (operands[2], DImode))
1520 else if (GET_CODE (operands[2]) == CONST_INT
1521 && ! add_operand (operands[2], <MODE>mode))
1523 rtx tmp = ((!can_create_pseudo_p ()
1524 || rtx_equal_p (operands[0], operands[1]))
1525 ? operands[0] : gen_reg_rtx (<MODE>mode));
1527 HOST_WIDE_INT val = INTVAL (operands[2]);
1528 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1529 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1531 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1534 /* The ordering here is important for the prolog expander.
1535 When space is allocated from the stack, adding 'low' first may
1536 produce a temporary deallocation (which would be bad). */
1537 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1538 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1543 ;; Discourage ai/addic because of carry but provide it in an alternative
1544 ;; allowing register zero as source.
1545 (define_insn "*add<mode>3_internal1"
1546 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1547 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1548 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1549 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1552 {cal %0,%2(%1)|addi %0,%1,%2}
1554 {cau|addis} %0,%1,%v2"
1555 [(set_attr "length" "4,4,4,4")])
1557 (define_insn "addsi3_high"
1558 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1559 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1560 (high:SI (match_operand 2 "" ""))))]
1561 "TARGET_MACHO && !TARGET_64BIT"
1562 "{cau|addis} %0,%1,ha16(%2)"
1563 [(set_attr "length" "4")])
1565 (define_insn "*add<mode>3_internal2"
1566 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1567 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1568 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1570 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1573 {cax.|add.} %3,%1,%2
1574 {ai.|addic.} %3,%1,%2
1577 [(set_attr "type" "fast_compare,compare,compare,compare")
1578 (set_attr "length" "4,4,8,8")])
1581 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1582 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1583 (match_operand:GPR 2 "reg_or_short_operand" ""))
1585 (clobber (match_scratch:GPR 3 ""))]
1588 (plus:GPR (match_dup 1)
1591 (compare:CC (match_dup 3)
1595 (define_insn "*add<mode>3_internal3"
1596 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1597 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1598 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1600 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1601 (plus:P (match_dup 1)
1605 {cax.|add.} %0,%1,%2
1606 {ai.|addic.} %0,%1,%2
1609 [(set_attr "type" "fast_compare,compare,compare,compare")
1610 (set_attr "length" "4,4,8,8")])
1613 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1614 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1615 (match_operand:P 2 "reg_or_short_operand" ""))
1617 (set (match_operand:P 0 "gpc_reg_operand" "")
1618 (plus:P (match_dup 1) (match_dup 2)))]
1621 (plus:P (match_dup 1)
1624 (compare:CC (match_dup 0)
1628 ;; Split an add that we can't do in one insn into two insns, each of which
1629 ;; does one 16-bit part. This is used by combine. Note that the low-order
1630 ;; add should be last in case the result gets used in an address.
1633 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1634 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1635 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1637 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1638 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1640 HOST_WIDE_INT val = INTVAL (operands[2]);
1641 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1642 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1644 operands[4] = GEN_INT (low);
1645 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1646 operands[3] = GEN_INT (rest);
1647 else if (can_create_pseudo_p ())
1649 operands[3] = gen_reg_rtx (DImode);
1650 emit_move_insn (operands[3], operands[2]);
1651 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1658 (define_insn "one_cmpl<mode>2"
1659 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1660 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1665 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1666 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1668 (clobber (match_scratch:P 2 "=r,r"))]
1673 [(set_attr "type" "compare")
1674 (set_attr "length" "4,8")])
1677 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1678 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1680 (clobber (match_scratch:P 2 ""))]
1683 (not:P (match_dup 1)))
1685 (compare:CC (match_dup 2)
1690 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1691 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1693 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1694 (not:P (match_dup 1)))]
1699 [(set_attr "type" "compare")
1700 (set_attr "length" "4,8")])
1703 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1704 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1706 (set (match_operand:P 0 "gpc_reg_operand" "")
1707 (not:P (match_dup 1)))]
1710 (not:P (match_dup 1)))
1712 (compare:CC (match_dup 0)
1717 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1718 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1719 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1721 "{sf%I1|subf%I1c} %0,%2,%1")
1724 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1725 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1726 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1733 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1734 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1735 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1737 (clobber (match_scratch:SI 3 "=r,r"))]
1740 {sf.|subfc.} %3,%2,%1
1742 [(set_attr "type" "compare")
1743 (set_attr "length" "4,8")])
1746 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1747 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1748 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1750 (clobber (match_scratch:P 3 "=r,r"))]
1755 [(set_attr "type" "fast_compare")
1756 (set_attr "length" "4,8")])
1759 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1760 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1761 (match_operand:P 2 "gpc_reg_operand" ""))
1763 (clobber (match_scratch:P 3 ""))]
1766 (minus:P (match_dup 1)
1769 (compare:CC (match_dup 3)
1774 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1775 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1776 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1778 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1779 (minus:SI (match_dup 1) (match_dup 2)))]
1782 {sf.|subfc.} %0,%2,%1
1784 [(set_attr "type" "compare")
1785 (set_attr "length" "4,8")])
1788 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1789 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1790 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1792 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1793 (minus:P (match_dup 1)
1799 [(set_attr "type" "fast_compare")
1800 (set_attr "length" "4,8")])
1803 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1804 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1805 (match_operand:P 2 "gpc_reg_operand" ""))
1807 (set (match_operand:P 0 "gpc_reg_operand" "")
1808 (minus:P (match_dup 1)
1812 (minus:P (match_dup 1)
1815 (compare:CC (match_dup 0)
1819 (define_expand "sub<mode>3"
1820 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1821 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1822 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1826 if (GET_CODE (operands[2]) == CONST_INT)
1828 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1829 negate_rtx (<MODE>mode, operands[2])));
1834 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1835 ;; instruction and some auxiliary computations. Then we just have a single
1836 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1839 (define_expand "sminsi3"
1841 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1842 (match_operand:SI 2 "reg_or_short_operand" ""))
1844 (minus:SI (match_dup 2) (match_dup 1))))
1845 (set (match_operand:SI 0 "gpc_reg_operand" "")
1846 (minus:SI (match_dup 2) (match_dup 3)))]
1847 "TARGET_POWER || TARGET_ISEL"
1852 operands[2] = force_reg (SImode, operands[2]);
1853 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1857 operands[3] = gen_reg_rtx (SImode);
1861 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1862 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1863 (match_operand:SI 2 "reg_or_short_operand" "")))
1864 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1867 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1869 (minus:SI (match_dup 2) (match_dup 1))))
1870 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1873 (define_expand "smaxsi3"
1875 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1876 (match_operand:SI 2 "reg_or_short_operand" ""))
1878 (minus:SI (match_dup 2) (match_dup 1))))
1879 (set (match_operand:SI 0 "gpc_reg_operand" "")
1880 (plus:SI (match_dup 3) (match_dup 1)))]
1881 "TARGET_POWER || TARGET_ISEL"
1886 operands[2] = force_reg (SImode, operands[2]);
1887 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1890 operands[3] = gen_reg_rtx (SImode);
1894 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1895 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1896 (match_operand:SI 2 "reg_or_short_operand" "")))
1897 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1900 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1902 (minus:SI (match_dup 2) (match_dup 1))))
1903 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1906 (define_expand "uminsi3"
1907 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1909 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1911 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1913 (minus:SI (match_dup 4) (match_dup 3))))
1914 (set (match_operand:SI 0 "gpc_reg_operand" "")
1915 (minus:SI (match_dup 2) (match_dup 3)))]
1916 "TARGET_POWER || TARGET_ISEL"
1921 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1924 operands[3] = gen_reg_rtx (SImode);
1925 operands[4] = gen_reg_rtx (SImode);
1926 operands[5] = GEN_INT (-2147483647 - 1);
1929 (define_expand "umaxsi3"
1930 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1932 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1934 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1936 (minus:SI (match_dup 4) (match_dup 3))))
1937 (set (match_operand:SI 0 "gpc_reg_operand" "")
1938 (plus:SI (match_dup 3) (match_dup 1)))]
1939 "TARGET_POWER || TARGET_ISEL"
1944 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1947 operands[3] = gen_reg_rtx (SImode);
1948 operands[4] = gen_reg_rtx (SImode);
1949 operands[5] = GEN_INT (-2147483647 - 1);
1953 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1954 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1955 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1957 (minus:SI (match_dup 2) (match_dup 1))))]
1962 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1964 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1965 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1967 (minus:SI (match_dup 2) (match_dup 1)))
1969 (clobber (match_scratch:SI 3 "=r,r"))]
1974 [(set_attr "type" "delayed_compare")
1975 (set_attr "length" "4,8")])
1978 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1980 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1981 (match_operand:SI 2 "reg_or_short_operand" ""))
1983 (minus:SI (match_dup 2) (match_dup 1)))
1985 (clobber (match_scratch:SI 3 ""))]
1986 "TARGET_POWER && reload_completed"
1988 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1990 (minus:SI (match_dup 2) (match_dup 1))))
1992 (compare:CC (match_dup 3)
1997 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1999 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
2000 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
2002 (minus:SI (match_dup 2) (match_dup 1)))
2004 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2005 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2007 (minus:SI (match_dup 2) (match_dup 1))))]
2012 [(set_attr "type" "delayed_compare")
2013 (set_attr "length" "4,8")])
2016 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2018 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2019 (match_operand:SI 2 "reg_or_short_operand" ""))
2021 (minus:SI (match_dup 2) (match_dup 1)))
2023 (set (match_operand:SI 0 "gpc_reg_operand" "")
2024 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2026 (minus:SI (match_dup 2) (match_dup 1))))]
2027 "TARGET_POWER && reload_completed"
2029 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2031 (minus:SI (match_dup 2) (match_dup 1))))
2033 (compare:CC (match_dup 0)
2037 ;; We don't need abs with condition code because such comparisons should
2039 (define_expand "abssi2"
2040 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2041 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2047 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
2050 else if (! TARGET_POWER)
2052 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2057 (define_insn "*abssi2_power"
2058 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2059 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2063 (define_insn_and_split "abssi2_isel"
2064 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2065 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
2066 (clobber (match_scratch:SI 2 "=&b"))
2067 (clobber (match_scratch:CC 3 "=y"))]
2070 "&& reload_completed"
2071 [(set (match_dup 2) (neg:SI (match_dup 1)))
2073 (compare:CC (match_dup 1)
2076 (if_then_else:SI (ge (match_dup 3)
2082 (define_insn_and_split "abssi2_nopower"
2083 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2084 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2085 (clobber (match_scratch:SI 2 "=&r,&r"))]
2086 "! TARGET_POWER && ! TARGET_ISEL"
2088 "&& reload_completed"
2089 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2090 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2091 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2094 (define_insn "*nabs_power"
2095 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2096 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2100 (define_insn_and_split "*nabs_nopower"
2101 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2102 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2103 (clobber (match_scratch:SI 2 "=&r,&r"))]
2106 "&& reload_completed"
2107 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2108 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2109 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2112 (define_expand "neg<mode>2"
2113 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2114 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2118 (define_insn "*neg<mode>2_internal"
2119 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2120 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2125 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2126 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2128 (clobber (match_scratch:P 2 "=r,r"))]
2133 [(set_attr "type" "fast_compare")
2134 (set_attr "length" "4,8")])
2137 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2138 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2140 (clobber (match_scratch:P 2 ""))]
2143 (neg:P (match_dup 1)))
2145 (compare:CC (match_dup 2)
2150 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2151 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2153 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2154 (neg:P (match_dup 1)))]
2159 [(set_attr "type" "fast_compare")
2160 (set_attr "length" "4,8")])
2163 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2164 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2166 (set (match_operand:P 0 "gpc_reg_operand" "")
2167 (neg:P (match_dup 1)))]
2170 (neg:P (match_dup 1)))
2172 (compare:CC (match_dup 0)
2176 (define_insn "clz<mode>2"
2177 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2178 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2180 "{cntlz|cntlz<wd>} %0,%1"
2181 [(set_attr "type" "cntlz")])
2183 (define_expand "ctz<mode>2"
2185 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2186 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2188 (clobber (scratch:CC))])
2189 (set (match_dup 4) (clz:GPR (match_dup 3)))
2190 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2191 (minus:GPR (match_dup 5) (match_dup 4)))]
2194 operands[2] = gen_reg_rtx (<MODE>mode);
2195 operands[3] = gen_reg_rtx (<MODE>mode);
2196 operands[4] = gen_reg_rtx (<MODE>mode);
2197 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2200 (define_expand "ffs<mode>2"
2202 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2203 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2205 (clobber (scratch:CC))])
2206 (set (match_dup 4) (clz:GPR (match_dup 3)))
2207 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2208 (minus:GPR (match_dup 5) (match_dup 4)))]
2211 operands[2] = gen_reg_rtx (<MODE>mode);
2212 operands[3] = gen_reg_rtx (<MODE>mode);
2213 operands[4] = gen_reg_rtx (<MODE>mode);
2214 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2217 (define_insn "popcntb<mode>2"
2218 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2219 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2224 (define_expand "popcount<mode>2"
2225 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2226 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2229 rs6000_emit_popcount (operands[0], operands[1]);
2233 (define_expand "parity<mode>2"
2234 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2235 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2238 rs6000_emit_parity (operands[0], operands[1]);
2242 (define_insn "bswapsi2"
2243 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2244 (bswap:SI (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2248 {stbrx|stwbrx} %1,%y0
2250 [(set_attr "length" "4,4,12")])
2253 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2254 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2257 (rotate:SI (match_dup 1) (const_int 8)))
2258 (set (zero_extract:SI (match_dup 0)
2262 (set (zero_extract:SI (match_dup 0)
2265 (rotate:SI (match_dup 1)
2269 (define_expand "mulsi3"
2270 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2271 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2272 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2277 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2279 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2283 (define_insn "mulsi3_mq"
2284 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2285 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2286 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2287 (clobber (match_scratch:SI 3 "=q,q"))]
2290 {muls|mullw} %0,%1,%2
2291 {muli|mulli} %0,%1,%2"
2293 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2294 (const_string "imul3")
2295 (match_operand:SI 2 "short_cint_operand" "")
2296 (const_string "imul2")]
2297 (const_string "imul")))])
2299 (define_insn "mulsi3_no_mq"
2300 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2301 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2302 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2305 {muls|mullw} %0,%1,%2
2306 {muli|mulli} %0,%1,%2"
2308 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2309 (const_string "imul3")
2310 (match_operand:SI 2 "short_cint_operand" "")
2311 (const_string "imul2")]
2312 (const_string "imul")))])
2314 (define_insn "*mulsi3_mq_internal1"
2315 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2316 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2317 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2319 (clobber (match_scratch:SI 3 "=r,r"))
2320 (clobber (match_scratch:SI 4 "=q,q"))]
2323 {muls.|mullw.} %3,%1,%2
2325 [(set_attr "type" "imul_compare")
2326 (set_attr "length" "4,8")])
2329 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2330 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2331 (match_operand:SI 2 "gpc_reg_operand" ""))
2333 (clobber (match_scratch:SI 3 ""))
2334 (clobber (match_scratch:SI 4 ""))]
2335 "TARGET_POWER && reload_completed"
2336 [(parallel [(set (match_dup 3)
2337 (mult:SI (match_dup 1) (match_dup 2)))
2338 (clobber (match_dup 4))])
2340 (compare:CC (match_dup 3)
2344 (define_insn "*mulsi3_no_mq_internal1"
2345 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2346 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2347 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2349 (clobber (match_scratch:SI 3 "=r,r"))]
2352 {muls.|mullw.} %3,%1,%2
2354 [(set_attr "type" "imul_compare")
2355 (set_attr "length" "4,8")])
2358 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2359 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2360 (match_operand:SI 2 "gpc_reg_operand" ""))
2362 (clobber (match_scratch:SI 3 ""))]
2363 "! TARGET_POWER && reload_completed"
2365 (mult:SI (match_dup 1) (match_dup 2)))
2367 (compare:CC (match_dup 3)
2371 (define_insn "*mulsi3_mq_internal2"
2372 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2373 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2374 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2376 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2377 (mult:SI (match_dup 1) (match_dup 2)))
2378 (clobber (match_scratch:SI 4 "=q,q"))]
2381 {muls.|mullw.} %0,%1,%2
2383 [(set_attr "type" "imul_compare")
2384 (set_attr "length" "4,8")])
2387 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2388 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2389 (match_operand:SI 2 "gpc_reg_operand" ""))
2391 (set (match_operand:SI 0 "gpc_reg_operand" "")
2392 (mult:SI (match_dup 1) (match_dup 2)))
2393 (clobber (match_scratch:SI 4 ""))]
2394 "TARGET_POWER && reload_completed"
2395 [(parallel [(set (match_dup 0)
2396 (mult:SI (match_dup 1) (match_dup 2)))
2397 (clobber (match_dup 4))])
2399 (compare:CC (match_dup 0)
2403 (define_insn "*mulsi3_no_mq_internal2"
2404 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2405 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2406 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2408 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2409 (mult:SI (match_dup 1) (match_dup 2)))]
2412 {muls.|mullw.} %0,%1,%2
2414 [(set_attr "type" "imul_compare")
2415 (set_attr "length" "4,8")])
2418 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2419 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2420 (match_operand:SI 2 "gpc_reg_operand" ""))
2422 (set (match_operand:SI 0 "gpc_reg_operand" "")
2423 (mult:SI (match_dup 1) (match_dup 2)))]
2424 "! TARGET_POWER && reload_completed"
2426 (mult:SI (match_dup 1) (match_dup 2)))
2428 (compare:CC (match_dup 0)
2432 ;; Operand 1 is divided by operand 2; quotient goes to operand
2433 ;; 0 and remainder to operand 3.
2434 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2436 (define_expand "divmodsi4"
2437 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2438 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2439 (match_operand:SI 2 "gpc_reg_operand" "")))
2440 (set (match_operand:SI 3 "register_operand" "")
2441 (mod:SI (match_dup 1) (match_dup 2)))])]
2442 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2445 if (! TARGET_POWER && ! TARGET_POWERPC)
2447 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2448 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2449 emit_insn (gen_divss_call ());
2450 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2451 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2456 (define_insn "*divmodsi4_internal"
2457 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2458 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2459 (match_operand:SI 2 "gpc_reg_operand" "r")))
2460 (set (match_operand:SI 3 "register_operand" "=q")
2461 (mod:SI (match_dup 1) (match_dup 2)))]
2464 [(set_attr "type" "idiv")])
2466 (define_expand "udiv<mode>3"
2467 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2468 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2469 (match_operand:GPR 2 "gpc_reg_operand" "")))]
2470 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2473 if (! TARGET_POWER && ! TARGET_POWERPC)
2475 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2476 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2477 emit_insn (gen_quous_call ());
2478 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2481 else if (TARGET_POWER)
2483 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2488 (define_insn "udivsi3_mq"
2489 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2490 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2491 (match_operand:SI 2 "gpc_reg_operand" "r")))
2492 (clobber (match_scratch:SI 3 "=q"))]
2493 "TARGET_POWERPC && TARGET_POWER"
2495 [(set_attr "type" "idiv")])
2497 (define_insn "*udivsi3_no_mq"
2498 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2499 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2500 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2501 "TARGET_POWERPC && ! TARGET_POWER"
2504 (cond [(match_operand:SI 0 "" "")
2505 (const_string "idiv")]
2506 (const_string "ldiv")))])
2509 ;; For powers of two we can do srai/aze for divide and then adjust for
2510 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2511 ;; used; for PowerPC, force operands into register and do a normal divide;
2512 ;; for AIX common-mode, use quoss call on register operands.
2513 (define_expand "div<mode>3"
2514 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2515 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2516 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2520 if (GET_CODE (operands[2]) == CONST_INT
2521 && INTVAL (operands[2]) > 0
2522 && exact_log2 (INTVAL (operands[2])) >= 0)
2524 else if (TARGET_POWERPC)
2526 operands[2] = force_reg (<MODE>mode, operands[2]);
2529 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2533 else if (TARGET_POWER)
2537 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2538 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2539 emit_insn (gen_quoss_call ());
2540 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2545 (define_insn "divsi3_mq"
2546 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2547 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2548 (match_operand:SI 2 "gpc_reg_operand" "r")))
2549 (clobber (match_scratch:SI 3 "=q"))]
2550 "TARGET_POWERPC && TARGET_POWER"
2552 [(set_attr "type" "idiv")])
2554 (define_insn "*div<mode>3_no_mq"
2555 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2556 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2557 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2558 "TARGET_POWERPC && ! TARGET_POWER"
2561 (cond [(match_operand:SI 0 "" "")
2562 (const_string "idiv")]
2563 (const_string "ldiv")))])
2565 (define_expand "mod<mode>3"
2566 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2567 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2568 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2576 if (GET_CODE (operands[2]) != CONST_INT
2577 || INTVAL (operands[2]) <= 0
2578 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2581 temp1 = gen_reg_rtx (<MODE>mode);
2582 temp2 = gen_reg_rtx (<MODE>mode);
2584 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2585 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2586 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2591 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2592 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2593 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2595 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
2596 [(set_attr "type" "two")
2597 (set_attr "length" "8")])
2600 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2601 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2602 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2604 (clobber (match_scratch:P 3 "=r,r"))]
2607 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
2609 [(set_attr "type" "compare")
2610 (set_attr "length" "8,12")
2611 (set_attr "cell_micro" "not")])
2614 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2615 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2616 (match_operand:GPR 2 "exact_log2_cint_operand"
2619 (clobber (match_scratch:GPR 3 ""))]
2622 (div:<MODE> (match_dup 1) (match_dup 2)))
2624 (compare:CC (match_dup 3)
2629 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2630 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2631 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2633 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2634 (div:P (match_dup 1) (match_dup 2)))]
2637 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
2639 [(set_attr "type" "compare")
2640 (set_attr "length" "8,12")
2641 (set_attr "cell_micro" "not")])
2644 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2645 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2646 (match_operand:GPR 2 "exact_log2_cint_operand"
2649 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2650 (div:GPR (match_dup 1) (match_dup 2)))]
2653 (div:<MODE> (match_dup 1) (match_dup 2)))
2655 (compare:CC (match_dup 0)
2660 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2663 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2665 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2666 (match_operand:SI 3 "gpc_reg_operand" "r")))
2667 (set (match_operand:SI 2 "register_operand" "=*q")
2670 (zero_extend:DI (match_dup 1)) (const_int 32))
2671 (zero_extend:DI (match_dup 4)))
2675 [(set_attr "type" "idiv")])
2677 ;; To do unsigned divide we handle the cases of the divisor looking like a
2678 ;; negative number. If it is a constant that is less than 2**31, we don't
2679 ;; have to worry about the branches. So make a few subroutines here.
2681 ;; First comes the normal case.
2682 (define_expand "udivmodsi4_normal"
2683 [(set (match_dup 4) (const_int 0))
2684 (parallel [(set (match_operand:SI 0 "" "")
2685 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2687 (zero_extend:DI (match_operand:SI 1 "" "")))
2688 (match_operand:SI 2 "" "")))
2689 (set (match_operand:SI 3 "" "")
2690 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2692 (zero_extend:DI (match_dup 1)))
2696 { operands[4] = gen_reg_rtx (SImode); }")
2698 ;; This handles the branches.
2699 (define_expand "udivmodsi4_tests"
2700 [(set (match_operand:SI 0 "" "") (const_int 0))
2701 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2702 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2703 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2704 (label_ref (match_operand:SI 4 "" "")) (pc)))
2705 (set (match_dup 0) (const_int 1))
2706 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2707 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2708 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2709 (label_ref (match_dup 4)) (pc)))]
2712 { operands[5] = gen_reg_rtx (CCUNSmode);
2713 operands[6] = gen_reg_rtx (CCmode);
2716 (define_expand "udivmodsi4"
2717 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2718 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2719 (match_operand:SI 2 "reg_or_cint_operand" "")))
2720 (set (match_operand:SI 3 "gpc_reg_operand" "")
2721 (umod:SI (match_dup 1) (match_dup 2)))])]
2729 if (! TARGET_POWERPC)
2731 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2732 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2733 emit_insn (gen_divus_call ());
2734 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2735 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2742 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2744 operands[2] = force_reg (SImode, operands[2]);
2745 label = gen_label_rtx ();
2746 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2747 operands[3], label));
2750 operands[2] = force_reg (SImode, operands[2]);
2752 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2760 ;; AIX architecture-independent common-mode multiply (DImode),
2761 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2762 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2763 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2764 ;; assumed unused if generating common-mode, so ignore.
2765 (define_insn "mulh_call"
2768 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2769 (sign_extend:DI (reg:SI 4)))
2771 (clobber (reg:SI LR_REGNO))]
2772 "! TARGET_POWER && ! TARGET_POWERPC"
2774 [(set_attr "type" "imul")])
2776 (define_insn "mull_call"
2778 (mult:DI (sign_extend:DI (reg:SI 3))
2779 (sign_extend:DI (reg:SI 4))))
2780 (clobber (reg:SI LR_REGNO))
2781 (clobber (reg:SI 0))]
2782 "! TARGET_POWER && ! TARGET_POWERPC"
2784 [(set_attr "type" "imul")])
2786 (define_insn "divss_call"
2788 (div:SI (reg:SI 3) (reg:SI 4)))
2790 (mod:SI (reg:SI 3) (reg:SI 4)))
2791 (clobber (reg:SI LR_REGNO))
2792 (clobber (reg:SI 0))]
2793 "! TARGET_POWER && ! TARGET_POWERPC"
2795 [(set_attr "type" "idiv")])
2797 (define_insn "divus_call"
2799 (udiv:SI (reg:SI 3) (reg:SI 4)))
2801 (umod:SI (reg:SI 3) (reg:SI 4)))
2802 (clobber (reg:SI LR_REGNO))
2803 (clobber (reg:SI 0))
2804 (clobber (match_scratch:CC 0 "=x"))
2805 (clobber (reg:CC CR1_REGNO))]
2806 "! TARGET_POWER && ! TARGET_POWERPC"
2808 [(set_attr "type" "idiv")])
2810 (define_insn "quoss_call"
2812 (div:SI (reg:SI 3) (reg:SI 4)))
2813 (clobber (reg:SI LR_REGNO))]
2814 "! TARGET_POWER && ! TARGET_POWERPC"
2816 [(set_attr "type" "idiv")])
2818 (define_insn "quous_call"
2820 (udiv:SI (reg:SI 3) (reg:SI 4)))
2821 (clobber (reg:SI LR_REGNO))
2822 (clobber (reg:SI 0))
2823 (clobber (match_scratch:CC 0 "=x"))
2824 (clobber (reg:CC CR1_REGNO))]
2825 "! TARGET_POWER && ! TARGET_POWERPC"
2827 [(set_attr "type" "idiv")])
2829 ;; Logical instructions
2830 ;; The logical instructions are mostly combined by using match_operator,
2831 ;; but the plain AND insns are somewhat different because there is no
2832 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2833 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2835 (define_expand "andsi3"
2837 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2838 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2839 (match_operand:SI 2 "and_operand" "")))
2840 (clobber (match_scratch:CC 3 ""))])]
2844 (define_insn "andsi3_mc"
2845 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2846 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2847 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2848 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2849 "rs6000_gen_cell_microcode"
2852 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2853 {andil.|andi.} %0,%1,%b2
2854 {andiu.|andis.} %0,%1,%u2"
2855 [(set_attr "type" "*,*,compare,compare")])
2857 (define_insn "andsi3_nomc"
2858 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2859 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2860 (match_operand:SI 2 "and_operand" "?r,T")))
2861 (clobber (match_scratch:CC 3 "=X,X"))]
2862 "!rs6000_gen_cell_microcode"
2865 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
2867 (define_insn "andsi3_internal0_nomc"
2868 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2869 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2870 (match_operand:SI 2 "and_operand" "?r,T")))]
2871 "!rs6000_gen_cell_microcode"
2874 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
2877 ;; Note to set cr's other than cr0 we do the and immediate and then
2878 ;; the test again -- this avoids a mfcr which on the higher end
2879 ;; machines causes an execution serialization
2881 (define_insn "*andsi3_internal2_mc"
2882 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2883 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2884 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2886 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2887 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2888 "TARGET_32BIT && rs6000_gen_cell_microcode"
2891 {andil.|andi.} %3,%1,%b2
2892 {andiu.|andis.} %3,%1,%u2
2893 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2898 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2899 (set_attr "length" "4,4,4,4,8,8,8,8")])
2901 (define_insn "*andsi3_internal3_mc"
2902 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2903 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2904 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2906 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2907 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2908 "TARGET_64BIT && rs6000_gen_cell_microcode"
2911 {andil.|andi.} %3,%1,%b2
2912 {andiu.|andis.} %3,%1,%u2
2913 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2918 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2919 (set_attr "length" "8,4,4,4,8,8,8,8")])
2922 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2923 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2924 (match_operand:GPR 2 "and_operand" ""))
2926 (clobber (match_scratch:GPR 3 ""))
2927 (clobber (match_scratch:CC 4 ""))]
2929 [(parallel [(set (match_dup 3)
2930 (and:<MODE> (match_dup 1)
2932 (clobber (match_dup 4))])
2934 (compare:CC (match_dup 3)
2938 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2939 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2942 [(set (match_operand:CC 0 "cc_reg_operand" "")
2943 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2944 (match_operand:SI 2 "gpc_reg_operand" ""))
2946 (clobber (match_scratch:SI 3 ""))
2947 (clobber (match_scratch:CC 4 ""))]
2948 "TARGET_POWERPC64 && reload_completed"
2949 [(parallel [(set (match_dup 3)
2950 (and:SI (match_dup 1)
2952 (clobber (match_dup 4))])
2954 (compare:CC (match_dup 3)
2958 (define_insn "*andsi3_internal4"
2959 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2960 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2961 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2963 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2964 (and:SI (match_dup 1)
2966 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2967 "TARGET_32BIT && rs6000_gen_cell_microcode"
2970 {andil.|andi.} %0,%1,%b2
2971 {andiu.|andis.} %0,%1,%u2
2972 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2977 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2978 (set_attr "length" "4,4,4,4,8,8,8,8")])
2980 (define_insn "*andsi3_internal5_mc"
2981 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2982 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2983 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2985 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2986 (and:SI (match_dup 1)
2988 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2989 "TARGET_64BIT && rs6000_gen_cell_microcode"
2992 {andil.|andi.} %0,%1,%b2
2993 {andiu.|andis.} %0,%1,%u2
2994 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2999 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
3000 (set_attr "length" "8,4,4,4,8,8,8,8")])
3003 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3004 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3005 (match_operand:SI 2 "and_operand" ""))
3007 (set (match_operand:SI 0 "gpc_reg_operand" "")
3008 (and:SI (match_dup 1)
3010 (clobber (match_scratch:CC 4 ""))]
3012 [(parallel [(set (match_dup 0)
3013 (and:SI (match_dup 1)
3015 (clobber (match_dup 4))])
3017 (compare:CC (match_dup 0)
3022 [(set (match_operand:CC 3 "cc_reg_operand" "")
3023 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3024 (match_operand:SI 2 "gpc_reg_operand" ""))
3026 (set (match_operand:SI 0 "gpc_reg_operand" "")
3027 (and:SI (match_dup 1)
3029 (clobber (match_scratch:CC 4 ""))]
3030 "TARGET_POWERPC64 && reload_completed"
3031 [(parallel [(set (match_dup 0)
3032 (and:SI (match_dup 1)
3034 (clobber (match_dup 4))])
3036 (compare:CC (match_dup 0)
3040 ;; Handle the PowerPC64 rlwinm corner case
3042 (define_insn_and_split "*andsi3_internal6"
3043 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3044 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3045 (match_operand:SI 2 "mask_operand_wrap" "i")))]
3050 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3053 (rotate:SI (match_dup 0) (match_dup 5)))]
3056 int mb = extract_MB (operands[2]);
3057 int me = extract_ME (operands[2]);
3058 operands[3] = GEN_INT (me + 1);
3059 operands[5] = GEN_INT (32 - (me + 1));
3060 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3062 [(set_attr "length" "8")])
3064 (define_expand "iorsi3"
3065 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3066 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
3067 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3071 if (GET_CODE (operands[2]) == CONST_INT
3072 && ! logical_operand (operands[2], SImode))
3074 HOST_WIDE_INT value = INTVAL (operands[2]);
3075 rtx tmp = ((!can_create_pseudo_p ()
3076 || rtx_equal_p (operands[0], operands[1]))
3077 ? operands[0] : gen_reg_rtx (SImode));
3079 emit_insn (gen_iorsi3 (tmp, operands[1],
3080 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3081 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3086 (define_expand "xorsi3"
3087 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3088 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3089 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3093 if (GET_CODE (operands[2]) == CONST_INT
3094 && ! logical_operand (operands[2], SImode))
3096 HOST_WIDE_INT value = INTVAL (operands[2]);
3097 rtx tmp = ((!can_create_pseudo_p ()
3098 || rtx_equal_p (operands[0], operands[1]))
3099 ? operands[0] : gen_reg_rtx (SImode));
3101 emit_insn (gen_xorsi3 (tmp, operands[1],
3102 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3103 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3108 (define_insn "*boolsi3_internal1"
3109 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3110 (match_operator:SI 3 "boolean_or_operator"
3111 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3112 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3116 {%q3il|%q3i} %0,%1,%b2
3117 {%q3iu|%q3is} %0,%1,%u2")
3119 (define_insn "*boolsi3_internal2"
3120 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3121 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3122 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3123 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3125 (clobber (match_scratch:SI 3 "=r,r"))]
3130 [(set_attr "type" "compare")
3131 (set_attr "length" "4,8")])
3134 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3135 (compare:CC (match_operator:SI 4 "boolean_operator"
3136 [(match_operand:SI 1 "gpc_reg_operand" "")
3137 (match_operand:SI 2 "gpc_reg_operand" "")])
3139 (clobber (match_scratch:SI 3 ""))]
3140 "TARGET_32BIT && reload_completed"
3141 [(set (match_dup 3) (match_dup 4))
3143 (compare:CC (match_dup 3)
3147 (define_insn "*boolsi3_internal3"
3148 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3149 (compare:CC (match_operator:SI 4 "boolean_operator"
3150 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3151 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3153 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3159 [(set_attr "type" "compare")
3160 (set_attr "length" "4,8")])
3163 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3164 (compare:CC (match_operator:SI 4 "boolean_operator"
3165 [(match_operand:SI 1 "gpc_reg_operand" "")
3166 (match_operand:SI 2 "gpc_reg_operand" "")])
3168 (set (match_operand:SI 0 "gpc_reg_operand" "")
3170 "TARGET_32BIT && reload_completed"
3171 [(set (match_dup 0) (match_dup 4))
3173 (compare:CC (match_dup 0)
3177 ;; Split a logical operation that we can't do in one insn into two insns,
3178 ;; each of which does one 16-bit part. This is used by combine.
3181 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3182 (match_operator:SI 3 "boolean_or_operator"
3183 [(match_operand:SI 1 "gpc_reg_operand" "")
3184 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3186 [(set (match_dup 0) (match_dup 4))
3187 (set (match_dup 0) (match_dup 5))]
3191 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3192 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3194 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3195 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3199 (define_insn "*boolcsi3_internal1"
3200 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3201 (match_operator:SI 3 "boolean_operator"
3202 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3203 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3207 (define_insn "*boolcsi3_internal2"
3208 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3209 (compare:CC (match_operator:SI 4 "boolean_operator"
3210 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3211 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3213 (clobber (match_scratch:SI 3 "=r,r"))]
3218 [(set_attr "type" "compare")
3219 (set_attr "length" "4,8")])
3222 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3223 (compare:CC (match_operator:SI 4 "boolean_operator"
3224 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3225 (match_operand:SI 2 "gpc_reg_operand" "")])
3227 (clobber (match_scratch:SI 3 ""))]
3228 "TARGET_32BIT && reload_completed"
3229 [(set (match_dup 3) (match_dup 4))
3231 (compare:CC (match_dup 3)
3235 (define_insn "*boolcsi3_internal3"
3236 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3237 (compare:CC (match_operator:SI 4 "boolean_operator"
3238 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3239 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3241 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3247 [(set_attr "type" "compare")
3248 (set_attr "length" "4,8")])
3251 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3252 (compare:CC (match_operator:SI 4 "boolean_operator"
3253 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3254 (match_operand:SI 2 "gpc_reg_operand" "")])
3256 (set (match_operand:SI 0 "gpc_reg_operand" "")
3258 "TARGET_32BIT && reload_completed"
3259 [(set (match_dup 0) (match_dup 4))
3261 (compare:CC (match_dup 0)
3265 (define_insn "*boolccsi3_internal1"
3266 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3267 (match_operator:SI 3 "boolean_operator"
3268 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3269 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3273 (define_insn "*boolccsi3_internal2"
3274 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3275 (compare:CC (match_operator:SI 4 "boolean_operator"
3276 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3277 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3279 (clobber (match_scratch:SI 3 "=r,r"))]
3284 [(set_attr "type" "compare")
3285 (set_attr "length" "4,8")])
3288 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3289 (compare:CC (match_operator:SI 4 "boolean_operator"
3290 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3291 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3293 (clobber (match_scratch:SI 3 ""))]
3294 "TARGET_32BIT && reload_completed"
3295 [(set (match_dup 3) (match_dup 4))
3297 (compare:CC (match_dup 3)
3301 (define_insn "*boolccsi3_internal3"
3302 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3303 (compare:CC (match_operator:SI 4 "boolean_operator"
3304 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3305 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3307 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3313 [(set_attr "type" "compare")
3314 (set_attr "length" "4,8")])
3317 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3318 (compare:CC (match_operator:SI 4 "boolean_operator"
3319 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3320 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3322 (set (match_operand:SI 0 "gpc_reg_operand" "")
3324 "TARGET_32BIT && reload_completed"
3325 [(set (match_dup 0) (match_dup 4))
3327 (compare:CC (match_dup 0)
3331 ;; maskir insn. We need four forms because things might be in arbitrary
3332 ;; orders. Don't define forms that only set CR fields because these
3333 ;; would modify an input register.
3335 (define_insn "*maskir_internal1"
3336 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3337 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3338 (match_operand:SI 1 "gpc_reg_operand" "0"))
3339 (and:SI (match_dup 2)
3340 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3344 (define_insn "*maskir_internal2"
3345 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3346 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3347 (match_operand:SI 1 "gpc_reg_operand" "0"))
3348 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3353 (define_insn "*maskir_internal3"
3354 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3355 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3356 (match_operand:SI 3 "gpc_reg_operand" "r"))
3357 (and:SI (not:SI (match_dup 2))
3358 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3362 (define_insn "*maskir_internal4"
3363 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3364 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3365 (match_operand:SI 2 "gpc_reg_operand" "r"))
3366 (and:SI (not:SI (match_dup 2))
3367 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3371 (define_insn "*maskir_internal5"
3372 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3374 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3375 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3376 (and:SI (match_dup 2)
3377 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3379 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3380 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3381 (and:SI (match_dup 2) (match_dup 3))))]
3386 [(set_attr "type" "compare")
3387 (set_attr "length" "4,8")])
3390 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3392 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3393 (match_operand:SI 1 "gpc_reg_operand" ""))
3394 (and:SI (match_dup 2)
3395 (match_operand:SI 3 "gpc_reg_operand" "")))
3397 (set (match_operand:SI 0 "gpc_reg_operand" "")
3398 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3399 (and:SI (match_dup 2) (match_dup 3))))]
3400 "TARGET_POWER && reload_completed"
3402 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3403 (and:SI (match_dup 2) (match_dup 3))))
3405 (compare:CC (match_dup 0)
3409 (define_insn "*maskir_internal6"
3410 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3412 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3413 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3414 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3417 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3418 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3419 (and:SI (match_dup 3) (match_dup 2))))]
3424 [(set_attr "type" "compare")
3425 (set_attr "length" "4,8")])
3428 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3430 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3431 (match_operand:SI 1 "gpc_reg_operand" ""))
3432 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3435 (set (match_operand:SI 0 "gpc_reg_operand" "")
3436 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3437 (and:SI (match_dup 3) (match_dup 2))))]
3438 "TARGET_POWER && reload_completed"
3440 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3441 (and:SI (match_dup 3) (match_dup 2))))
3443 (compare:CC (match_dup 0)
3447 (define_insn "*maskir_internal7"
3448 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3450 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3451 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3452 (and:SI (not:SI (match_dup 2))
3453 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3455 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3456 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3457 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3462 [(set_attr "type" "compare")
3463 (set_attr "length" "4,8")])
3466 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3468 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3469 (match_operand:SI 3 "gpc_reg_operand" ""))
3470 (and:SI (not:SI (match_dup 2))
3471 (match_operand:SI 1 "gpc_reg_operand" "")))
3473 (set (match_operand:SI 0 "gpc_reg_operand" "")
3474 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3475 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3476 "TARGET_POWER && reload_completed"
3478 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3479 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3481 (compare:CC (match_dup 0)
3485 (define_insn "*maskir_internal8"
3486 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3488 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3489 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3490 (and:SI (not:SI (match_dup 2))
3491 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3493 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3494 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3495 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3500 [(set_attr "type" "compare")
3501 (set_attr "length" "4,8")])
3504 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3506 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3507 (match_operand:SI 2 "gpc_reg_operand" ""))
3508 (and:SI (not:SI (match_dup 2))
3509 (match_operand:SI 1 "gpc_reg_operand" "")))
3511 (set (match_operand:SI 0 "gpc_reg_operand" "")
3512 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3513 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3514 "TARGET_POWER && reload_completed"
3516 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3517 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3519 (compare:CC (match_dup 0)
3523 ;; Rotate and shift insns, in all their variants. These support shifts,
3524 ;; field inserts and extracts, and various combinations thereof.
3525 (define_expand "insv"
3526 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3527 (match_operand:SI 1 "const_int_operand" "")
3528 (match_operand:SI 2 "const_int_operand" ""))
3529 (match_operand 3 "gpc_reg_operand" ""))]
3533 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3534 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3535 compiler if the address of the structure is taken later. Likewise, do
3536 not handle invalid E500 subregs. */
3537 if (GET_CODE (operands[0]) == SUBREG
3538 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3539 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3540 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3543 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3544 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3546 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3550 (define_insn "insvsi"
3551 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3552 (match_operand:SI 1 "const_int_operand" "i")
3553 (match_operand:SI 2 "const_int_operand" "i"))
3554 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3558 int start = INTVAL (operands[2]) & 31;
3559 int size = INTVAL (operands[1]) & 31;
3561 operands[4] = GEN_INT (32 - start - size);
3562 operands[1] = GEN_INT (start + size - 1);
3563 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3565 [(set_attr "type" "insert_word")])
3567 (define_insn "*insvsi_internal1"
3568 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3569 (match_operand:SI 1 "const_int_operand" "i")
3570 (match_operand:SI 2 "const_int_operand" "i"))
3571 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3572 (match_operand:SI 4 "const_int_operand" "i")))]
3573 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3576 int shift = INTVAL (operands[4]) & 31;
3577 int start = INTVAL (operands[2]) & 31;
3578 int size = INTVAL (operands[1]) & 31;
3580 operands[4] = GEN_INT (shift - start - size);
3581 operands[1] = GEN_INT (start + size - 1);
3582 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3584 [(set_attr "type" "insert_word")])
3586 (define_insn "*insvsi_internal2"
3587 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3588 (match_operand:SI 1 "const_int_operand" "i")
3589 (match_operand:SI 2 "const_int_operand" "i"))
3590 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3591 (match_operand:SI 4 "const_int_operand" "i")))]
3592 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3595 int shift = INTVAL (operands[4]) & 31;
3596 int start = INTVAL (operands[2]) & 31;
3597 int size = INTVAL (operands[1]) & 31;
3599 operands[4] = GEN_INT (32 - shift - start - size);
3600 operands[1] = GEN_INT (start + size - 1);
3601 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3603 [(set_attr "type" "insert_word")])
3605 (define_insn "*insvsi_internal3"
3606 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3607 (match_operand:SI 1 "const_int_operand" "i")
3608 (match_operand:SI 2 "const_int_operand" "i"))
3609 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3610 (match_operand:SI 4 "const_int_operand" "i")))]
3611 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3614 int shift = INTVAL (operands[4]) & 31;
3615 int start = INTVAL (operands[2]) & 31;
3616 int size = INTVAL (operands[1]) & 31;
3618 operands[4] = GEN_INT (32 - shift - start - size);
3619 operands[1] = GEN_INT (start + size - 1);
3620 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3622 [(set_attr "type" "insert_word")])
3624 (define_insn "*insvsi_internal4"
3625 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3626 (match_operand:SI 1 "const_int_operand" "i")
3627 (match_operand:SI 2 "const_int_operand" "i"))
3628 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3629 (match_operand:SI 4 "const_int_operand" "i")
3630 (match_operand:SI 5 "const_int_operand" "i")))]
3631 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3634 int extract_start = INTVAL (operands[5]) & 31;
3635 int extract_size = INTVAL (operands[4]) & 31;
3636 int insert_start = INTVAL (operands[2]) & 31;
3637 int insert_size = INTVAL (operands[1]) & 31;
3639 /* Align extract field with insert field */
3640 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3641 operands[1] = GEN_INT (insert_start + insert_size - 1);
3642 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3644 [(set_attr "type" "insert_word")])
3646 ;; combine patterns for rlwimi
3647 (define_insn "*insvsi_internal5"
3648 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3649 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3650 (match_operand:SI 1 "mask_operand" "i"))
3651 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3652 (match_operand:SI 2 "const_int_operand" "i"))
3653 (match_operand:SI 5 "mask_operand" "i"))))]
3654 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3657 int me = extract_ME(operands[5]);
3658 int mb = extract_MB(operands[5]);
3659 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3660 operands[2] = GEN_INT(mb);
3661 operands[1] = GEN_INT(me);
3662 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3664 [(set_attr "type" "insert_word")])
3666 (define_insn "*insvsi_internal6"
3667 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3668 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3669 (match_operand:SI 2 "const_int_operand" "i"))
3670 (match_operand:SI 5 "mask_operand" "i"))
3671 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3672 (match_operand:SI 1 "mask_operand" "i"))))]
3673 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3676 int me = extract_ME(operands[5]);
3677 int mb = extract_MB(operands[5]);
3678 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3679 operands[2] = GEN_INT(mb);
3680 operands[1] = GEN_INT(me);
3681 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3683 [(set_attr "type" "insert_word")])
3685 (define_insn "insvdi"
3686 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3687 (match_operand:SI 1 "const_int_operand" "i")
3688 (match_operand:SI 2 "const_int_operand" "i"))
3689 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3693 int start = INTVAL (operands[2]) & 63;
3694 int size = INTVAL (operands[1]) & 63;
3696 operands[1] = GEN_INT (64 - start - size);
3697 return \"rldimi %0,%3,%H1,%H2\";
3699 [(set_attr "type" "insert_dword")])
3701 (define_insn "*insvdi_internal2"
3702 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3703 (match_operand:SI 1 "const_int_operand" "i")
3704 (match_operand:SI 2 "const_int_operand" "i"))
3705 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3706 (match_operand:SI 4 "const_int_operand" "i")))]
3708 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3711 int shift = INTVAL (operands[4]) & 63;
3712 int start = (INTVAL (operands[2]) & 63) - 32;
3713 int size = INTVAL (operands[1]) & 63;
3715 operands[4] = GEN_INT (64 - shift - start - size);
3716 operands[2] = GEN_INT (start);
3717 operands[1] = GEN_INT (start + size - 1);
3718 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3721 (define_insn "*insvdi_internal3"
3722 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3723 (match_operand:SI 1 "const_int_operand" "i")
3724 (match_operand:SI 2 "const_int_operand" "i"))
3725 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3726 (match_operand:SI 4 "const_int_operand" "i")))]
3728 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3731 int shift = INTVAL (operands[4]) & 63;
3732 int start = (INTVAL (operands[2]) & 63) - 32;
3733 int size = INTVAL (operands[1]) & 63;
3735 operands[4] = GEN_INT (64 - shift - start - size);
3736 operands[2] = GEN_INT (start);
3737 operands[1] = GEN_INT (start + size - 1);
3738 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3741 (define_expand "extzv"
3742 [(set (match_operand 0 "gpc_reg_operand" "")
3743 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3744 (match_operand:SI 2 "const_int_operand" "")
3745 (match_operand:SI 3 "const_int_operand" "")))]
3749 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3750 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3751 compiler if the address of the structure is taken later. */
3752 if (GET_CODE (operands[0]) == SUBREG
3753 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3756 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3757 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3759 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3763 (define_insn "extzvsi"
3764 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3765 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3766 (match_operand:SI 2 "const_int_operand" "i")
3767 (match_operand:SI 3 "const_int_operand" "i")))]
3771 int start = INTVAL (operands[3]) & 31;
3772 int size = INTVAL (operands[2]) & 31;
3774 if (start + size >= 32)
3775 operands[3] = const0_rtx;
3777 operands[3] = GEN_INT (start + size);
3778 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3781 (define_insn "*extzvsi_internal1"
3782 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3783 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3784 (match_operand:SI 2 "const_int_operand" "i,i")
3785 (match_operand:SI 3 "const_int_operand" "i,i"))
3787 (clobber (match_scratch:SI 4 "=r,r"))]
3791 int start = INTVAL (operands[3]) & 31;
3792 int size = INTVAL (operands[2]) & 31;
3794 /* Force split for non-cc0 compare. */
3795 if (which_alternative == 1)
3798 /* If the bit-field being tested fits in the upper or lower half of a
3799 word, it is possible to use andiu. or andil. to test it. This is
3800 useful because the condition register set-use delay is smaller for
3801 andi[ul]. than for rlinm. This doesn't work when the starting bit
3802 position is 0 because the LT and GT bits may be set wrong. */
3804 if ((start > 0 && start + size <= 16) || start >= 16)
3806 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3807 - (1 << (16 - (start & 15) - size))));
3809 return \"{andiu.|andis.} %4,%1,%3\";
3811 return \"{andil.|andi.} %4,%1,%3\";
3814 if (start + size >= 32)
3815 operands[3] = const0_rtx;
3817 operands[3] = GEN_INT (start + size);
3818 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3820 [(set_attr "type" "delayed_compare")
3821 (set_attr "length" "4,8")])
3824 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3825 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3826 (match_operand:SI 2 "const_int_operand" "")
3827 (match_operand:SI 3 "const_int_operand" ""))
3829 (clobber (match_scratch:SI 4 ""))]
3832 (zero_extract:SI (match_dup 1) (match_dup 2)
3835 (compare:CC (match_dup 4)
3839 (define_insn "*extzvsi_internal2"
3840 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3841 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3842 (match_operand:SI 2 "const_int_operand" "i,i")
3843 (match_operand:SI 3 "const_int_operand" "i,i"))
3845 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3846 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3850 int start = INTVAL (operands[3]) & 31;
3851 int size = INTVAL (operands[2]) & 31;
3853 /* Force split for non-cc0 compare. */
3854 if (which_alternative == 1)
3857 /* Since we are using the output value, we can't ignore any need for
3858 a shift. The bit-field must end at the LSB. */
3859 if (start >= 16 && start + size == 32)
3861 operands[3] = GEN_INT ((1 << size) - 1);
3862 return \"{andil.|andi.} %0,%1,%3\";
3865 if (start + size >= 32)
3866 operands[3] = const0_rtx;
3868 operands[3] = GEN_INT (start + size);
3869 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3871 [(set_attr "type" "delayed_compare")
3872 (set_attr "length" "4,8")])
3875 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3876 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3877 (match_operand:SI 2 "const_int_operand" "")
3878 (match_operand:SI 3 "const_int_operand" ""))
3880 (set (match_operand:SI 0 "gpc_reg_operand" "")
3881 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3884 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3886 (compare:CC (match_dup 0)
3890 (define_insn "extzvdi"
3891 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3892 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3893 (match_operand:SI 2 "const_int_operand" "i")
3894 (match_operand:SI 3 "const_int_operand" "i")))]
3898 int start = INTVAL (operands[3]) & 63;
3899 int size = INTVAL (operands[2]) & 63;
3901 if (start + size >= 64)
3902 operands[3] = const0_rtx;
3904 operands[3] = GEN_INT (start + size);
3905 operands[2] = GEN_INT (64 - size);
3906 return \"rldicl %0,%1,%3,%2\";
3909 (define_insn "*extzvdi_internal1"
3910 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3911 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3912 (match_operand:SI 2 "const_int_operand" "i")
3913 (match_operand:SI 3 "const_int_operand" "i"))
3915 (clobber (match_scratch:DI 4 "=r"))]
3916 "TARGET_64BIT && rs6000_gen_cell_microcode"
3919 int start = INTVAL (operands[3]) & 63;
3920 int size = INTVAL (operands[2]) & 63;
3922 if (start + size >= 64)
3923 operands[3] = const0_rtx;
3925 operands[3] = GEN_INT (start + size);
3926 operands[2] = GEN_INT (64 - size);
3927 return \"rldicl. %4,%1,%3,%2\";
3929 [(set_attr "type" "compare")])
3931 (define_insn "*extzvdi_internal2"
3932 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3933 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3934 (match_operand:SI 2 "const_int_operand" "i")
3935 (match_operand:SI 3 "const_int_operand" "i"))
3937 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3938 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3939 "TARGET_64BIT && rs6000_gen_cell_microcode"
3942 int start = INTVAL (operands[3]) & 63;
3943 int size = INTVAL (operands[2]) & 63;
3945 if (start + size >= 64)
3946 operands[3] = const0_rtx;
3948 operands[3] = GEN_INT (start + size);
3949 operands[2] = GEN_INT (64 - size);
3950 return \"rldicl. %0,%1,%3,%2\";
3952 [(set_attr "type" "compare")])
3954 (define_insn "rotlsi3"
3955 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3956 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3957 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
3960 {rlnm|rlwnm} %0,%1,%2,0xffffffff
3961 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
3962 [(set_attr "type" "var_shift_rotate,integer")])
3964 (define_insn "*rotlsi3_internal2"
3965 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3966 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3967 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3969 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3972 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
3973 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
3976 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3977 (set_attr "length" "4,4,8,8")])
3980 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3981 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3982 (match_operand:SI 2 "reg_or_cint_operand" ""))
3984 (clobber (match_scratch:SI 3 ""))]
3987 (rotate:SI (match_dup 1) (match_dup 2)))
3989 (compare:CC (match_dup 3)
3993 (define_insn "*rotlsi3_internal3"
3994 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3995 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3996 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3998 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3999 (rotate:SI (match_dup 1) (match_dup 2)))]
4002 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
4003 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
4006 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4007 (set_attr "length" "4,4,8,8")])
4010 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4011 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4012 (match_operand:SI 2 "reg_or_cint_operand" ""))
4014 (set (match_operand:SI 0 "gpc_reg_operand" "")
4015 (rotate:SI (match_dup 1) (match_dup 2)))]
4018 (rotate:SI (match_dup 1) (match_dup 2)))
4020 (compare:CC (match_dup 0)
4024 (define_insn "*rotlsi3_internal4"
4025 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4026 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4027 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
4028 (match_operand:SI 3 "mask_operand" "n,n")))]
4031 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
4032 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
4033 [(set_attr "type" "var_shift_rotate,integer")])
4035 (define_insn "*rotlsi3_internal5"
4036 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4038 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4039 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4040 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4042 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
4045 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
4046 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4049 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4050 (set_attr "length" "4,4,8,8")])
4053 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4055 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4056 (match_operand:SI 2 "reg_or_cint_operand" ""))
4057 (match_operand:SI 3 "mask_operand" ""))
4059 (clobber (match_scratch:SI 4 ""))]
4062 (and:SI (rotate:SI (match_dup 1)
4066 (compare:CC (match_dup 4)
4070 (define_insn "*rotlsi3_internal6"
4071 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
4073 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4074 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4075 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4077 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4078 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4081 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
4082 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4085 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4086 (set_attr "length" "4,4,8,8")])
4089 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4091 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4092 (match_operand:SI 2 "reg_or_cint_operand" ""))
4093 (match_operand:SI 3 "mask_operand" ""))
4095 (set (match_operand:SI 0 "gpc_reg_operand" "")
4096 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4099 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4101 (compare:CC (match_dup 0)
4105 (define_insn "*rotlsi3_internal7"
4106 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4109 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4110 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4112 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff"
4113 [(set (attr "cell_micro")
4114 (if_then_else (match_operand:SI 2 "const_int_operand" "")
4115 (const_string "not")
4116 (const_string "always")))])
4118 (define_insn "*rotlsi3_internal8"
4119 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4120 (compare:CC (zero_extend:SI
4122 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4123 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4125 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4128 {rlnm.|rlwnm.} %3,%1,%2,0xff
4129 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4132 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4133 (set_attr "length" "4,4,8,8")])
4136 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4137 (compare:CC (zero_extend:SI
4139 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4140 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4142 (clobber (match_scratch:SI 3 ""))]
4145 (zero_extend:SI (subreg:QI
4146 (rotate:SI (match_dup 1)
4149 (compare:CC (match_dup 3)
4153 (define_insn "*rotlsi3_internal9"
4154 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4155 (compare:CC (zero_extend:SI
4157 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4158 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4160 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4161 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4164 {rlnm.|rlwnm.} %0,%1,%2,0xff
4165 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4168 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4169 (set_attr "length" "4,4,8,8")])
4172 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4173 (compare:CC (zero_extend:SI
4175 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4176 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4178 (set (match_operand:SI 0 "gpc_reg_operand" "")
4179 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4182 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4184 (compare:CC (match_dup 0)
4188 (define_insn "*rotlsi3_internal10"
4189 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4192 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4193 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4196 {rlnm|rlwnm} %0,%1,%2,0xffff
4197 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4198 [(set_attr "type" "var_shift_rotate,integer")])
4201 (define_insn "*rotlsi3_internal11"
4202 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4203 (compare:CC (zero_extend:SI
4205 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4206 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4208 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4211 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4212 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4215 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4216 (set_attr "length" "4,4,8,8")])
4219 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4220 (compare:CC (zero_extend:SI
4222 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4223 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4225 (clobber (match_scratch:SI 3 ""))]
4228 (zero_extend:SI (subreg:HI
4229 (rotate:SI (match_dup 1)
4232 (compare:CC (match_dup 3)
4236 (define_insn "*rotlsi3_internal12"
4237 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4238 (compare:CC (zero_extend:SI
4240 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4241 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4243 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4244 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4247 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4248 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4251 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4252 (set_attr "length" "4,4,8,8")])
4255 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4256 (compare:CC (zero_extend:SI
4258 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4259 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4261 (set (match_operand:SI 0 "gpc_reg_operand" "")
4262 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4265 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4267 (compare:CC (match_dup 0)
4271 ;; Note that we use "sle." instead of "sl." so that we can set
4272 ;; SHIFT_COUNT_TRUNCATED.
4274 (define_expand "ashlsi3"
4275 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4276 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4277 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4282 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4284 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4288 (define_insn "ashlsi3_power"
4289 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4290 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4291 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4292 (clobber (match_scratch:SI 3 "=q,X"))]
4296 {sli|slwi} %0,%1,%h2")
4298 (define_insn "ashlsi3_no_power"
4299 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4300 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4301 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4305 {sli|slwi} %0,%1,%h2"
4306 [(set_attr "type" "var_shift_rotate,shift")])
4309 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4310 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4311 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4313 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4314 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4318 {sli.|slwi.} %3,%1,%h2
4321 [(set_attr "type" "delayed_compare")
4322 (set_attr "length" "4,4,8,8")])
4325 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4326 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4327 (match_operand:SI 2 "reg_or_cint_operand" ""))
4329 (clobber (match_scratch:SI 3 ""))
4330 (clobber (match_scratch:SI 4 ""))]
4331 "TARGET_POWER && reload_completed"
4332 [(parallel [(set (match_dup 3)
4333 (ashift:SI (match_dup 1) (match_dup 2)))
4334 (clobber (match_dup 4))])
4336 (compare:CC (match_dup 3)
4341 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4342 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4343 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4345 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4346 "! TARGET_POWER && TARGET_32BIT"
4349 {sli.|slwi.} %3,%1,%h2
4352 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4353 (set_attr "length" "4,4,8,8")])
4356 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4357 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4358 (match_operand:SI 2 "reg_or_cint_operand" ""))
4360 (clobber (match_scratch:SI 3 ""))]
4361 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4363 (ashift:SI (match_dup 1) (match_dup 2)))
4365 (compare:CC (match_dup 3)
4370 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4371 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4372 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4374 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4375 (ashift:SI (match_dup 1) (match_dup 2)))
4376 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4380 {sli.|slwi.} %0,%1,%h2
4383 [(set_attr "type" "delayed_compare")
4384 (set_attr "length" "4,4,8,8")])
4387 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4388 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4389 (match_operand:SI 2 "reg_or_cint_operand" ""))
4391 (set (match_operand:SI 0 "gpc_reg_operand" "")
4392 (ashift:SI (match_dup 1) (match_dup 2)))
4393 (clobber (match_scratch:SI 4 ""))]
4394 "TARGET_POWER && reload_completed"
4395 [(parallel [(set (match_dup 0)
4396 (ashift:SI (match_dup 1) (match_dup 2)))
4397 (clobber (match_dup 4))])
4399 (compare:CC (match_dup 0)
4404 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4405 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4406 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4408 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4409 (ashift:SI (match_dup 1) (match_dup 2)))]
4410 "! TARGET_POWER && TARGET_32BIT"
4413 {sli.|slwi.} %0,%1,%h2
4416 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4417 (set_attr "length" "4,4,8,8")])
4420 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4421 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4422 (match_operand:SI 2 "reg_or_cint_operand" ""))
4424 (set (match_operand:SI 0 "gpc_reg_operand" "")
4425 (ashift:SI (match_dup 1) (match_dup 2)))]
4426 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4428 (ashift:SI (match_dup 1) (match_dup 2)))
4430 (compare:CC (match_dup 0)
4434 (define_insn "rlwinm"
4435 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4436 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4437 (match_operand:SI 2 "const_int_operand" "i"))
4438 (match_operand:SI 3 "mask_operand" "n")))]
4439 "includes_lshift_p (operands[2], operands[3])"
4440 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4443 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4445 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4446 (match_operand:SI 2 "const_int_operand" "i,i"))
4447 (match_operand:SI 3 "mask_operand" "n,n"))
4449 (clobber (match_scratch:SI 4 "=r,r"))]
4450 "includes_lshift_p (operands[2], operands[3])"
4452 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4454 [(set_attr "type" "delayed_compare")
4455 (set_attr "length" "4,8")])
4458 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4460 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4461 (match_operand:SI 2 "const_int_operand" ""))
4462 (match_operand:SI 3 "mask_operand" ""))
4464 (clobber (match_scratch:SI 4 ""))]
4465 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4467 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4470 (compare:CC (match_dup 4)
4475 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4477 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4478 (match_operand:SI 2 "const_int_operand" "i,i"))
4479 (match_operand:SI 3 "mask_operand" "n,n"))
4481 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4482 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4483 "includes_lshift_p (operands[2], operands[3])"
4485 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4487 [(set_attr "type" "delayed_compare")
4488 (set_attr "length" "4,8")])
4491 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4493 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4494 (match_operand:SI 2 "const_int_operand" ""))
4495 (match_operand:SI 3 "mask_operand" ""))
4497 (set (match_operand:SI 0 "gpc_reg_operand" "")
4498 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4499 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4501 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4503 (compare:CC (match_dup 0)
4507 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
4509 (define_expand "lshrsi3"
4510 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4511 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4512 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4517 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4519 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
4523 (define_insn "lshrsi3_power"
4524 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4525 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4526 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4527 (clobber (match_scratch:SI 3 "=q,X,X"))]
4532 {s%A2i|s%A2wi} %0,%1,%h2")
4534 (define_insn "lshrsi3_no_power"
4535 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4536 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4537 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
4542 {sri|srwi} %0,%1,%h2"
4543 [(set_attr "type" "integer,var_shift_rotate,shift")])
4546 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4547 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4548 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4550 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4551 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4556 {s%A2i.|s%A2wi.} %3,%1,%h2
4560 [(set_attr "type" "delayed_compare")
4561 (set_attr "length" "4,4,4,8,8,8")])
4564 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4565 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4566 (match_operand:SI 2 "reg_or_cint_operand" ""))
4568 (clobber (match_scratch:SI 3 ""))
4569 (clobber (match_scratch:SI 4 ""))]
4570 "TARGET_POWER && reload_completed"
4571 [(parallel [(set (match_dup 3)
4572 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4573 (clobber (match_dup 4))])
4575 (compare:CC (match_dup 3)
4580 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4581 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4582 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4584 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4585 "! TARGET_POWER && TARGET_32BIT"
4589 {sri.|srwi.} %3,%1,%h2
4593 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4594 (set_attr "length" "4,4,4,8,8,8")])
4597 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4598 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4599 (match_operand:SI 2 "reg_or_cint_operand" ""))
4601 (clobber (match_scratch:SI 3 ""))]
4602 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4604 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4606 (compare:CC (match_dup 3)
4611 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4612 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4613 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4615 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4616 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4617 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4622 {s%A2i.|s%A2wi.} %0,%1,%h2
4626 [(set_attr "type" "delayed_compare")
4627 (set_attr "length" "4,4,4,8,8,8")])
4630 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4631 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4632 (match_operand:SI 2 "reg_or_cint_operand" ""))
4634 (set (match_operand:SI 0 "gpc_reg_operand" "")
4635 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4636 (clobber (match_scratch:SI 4 ""))]
4637 "TARGET_POWER && reload_completed"
4638 [(parallel [(set (match_dup 0)
4639 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4640 (clobber (match_dup 4))])
4642 (compare:CC (match_dup 0)
4647 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4648 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4649 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4651 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4652 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4653 "! TARGET_POWER && TARGET_32BIT"
4657 {sri.|srwi.} %0,%1,%h2
4661 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4662 (set_attr "length" "4,4,4,8,8,8")])
4665 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4666 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4667 (match_operand:SI 2 "reg_or_cint_operand" ""))
4669 (set (match_operand:SI 0 "gpc_reg_operand" "")
4670 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4671 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4673 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4675 (compare:CC (match_dup 0)
4680 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4681 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4682 (match_operand:SI 2 "const_int_operand" "i"))
4683 (match_operand:SI 3 "mask_operand" "n")))]
4684 "includes_rshift_p (operands[2], operands[3])"
4685 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4688 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4690 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4691 (match_operand:SI 2 "const_int_operand" "i,i"))
4692 (match_operand:SI 3 "mask_operand" "n,n"))
4694 (clobber (match_scratch:SI 4 "=r,r"))]
4695 "includes_rshift_p (operands[2], operands[3])"
4697 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4699 [(set_attr "type" "delayed_compare")
4700 (set_attr "length" "4,8")])
4703 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4705 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4706 (match_operand:SI 2 "const_int_operand" ""))
4707 (match_operand:SI 3 "mask_operand" ""))
4709 (clobber (match_scratch:SI 4 ""))]
4710 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4712 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4715 (compare:CC (match_dup 4)
4720 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4722 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4723 (match_operand:SI 2 "const_int_operand" "i,i"))
4724 (match_operand:SI 3 "mask_operand" "n,n"))
4726 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4727 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4728 "includes_rshift_p (operands[2], operands[3])"
4730 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4732 [(set_attr "type" "delayed_compare")
4733 (set_attr "length" "4,8")])
4736 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4738 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4739 (match_operand:SI 2 "const_int_operand" ""))
4740 (match_operand:SI 3 "mask_operand" ""))
4742 (set (match_operand:SI 0 "gpc_reg_operand" "")
4743 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4744 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4746 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4748 (compare:CC (match_dup 0)
4753 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4756 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4757 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4758 "includes_rshift_p (operands[2], GEN_INT (255))"
4759 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4762 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4766 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4767 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4769 (clobber (match_scratch:SI 3 "=r,r"))]
4770 "includes_rshift_p (operands[2], GEN_INT (255))"
4772 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4774 [(set_attr "type" "delayed_compare")
4775 (set_attr "length" "4,8")])
4778 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4782 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4783 (match_operand:SI 2 "const_int_operand" "")) 0))
4785 (clobber (match_scratch:SI 3 ""))]
4786 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4788 (zero_extend:SI (subreg:QI
4789 (lshiftrt:SI (match_dup 1)
4792 (compare:CC (match_dup 3)
4797 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4801 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4802 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4804 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4805 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4806 "includes_rshift_p (operands[2], GEN_INT (255))"
4808 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4810 [(set_attr "type" "delayed_compare")
4811 (set_attr "length" "4,8")])
4814 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4818 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4819 (match_operand:SI 2 "const_int_operand" "")) 0))
4821 (set (match_operand:SI 0 "gpc_reg_operand" "")
4822 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4823 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4825 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4827 (compare:CC (match_dup 0)
4832 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4835 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4836 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4837 "includes_rshift_p (operands[2], GEN_INT (65535))"
4838 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4841 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4845 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4846 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4848 (clobber (match_scratch:SI 3 "=r,r"))]
4849 "includes_rshift_p (operands[2], GEN_INT (65535))"
4851 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4853 [(set_attr "type" "delayed_compare")
4854 (set_attr "length" "4,8")])
4857 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4861 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4862 (match_operand:SI 2 "const_int_operand" "")) 0))
4864 (clobber (match_scratch:SI 3 ""))]
4865 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4867 (zero_extend:SI (subreg:HI
4868 (lshiftrt:SI (match_dup 1)
4871 (compare:CC (match_dup 3)
4876 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4880 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4881 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4883 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4884 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4885 "includes_rshift_p (operands[2], GEN_INT (65535))"
4887 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4889 [(set_attr "type" "delayed_compare")
4890 (set_attr "length" "4,8")])
4893 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4897 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4898 (match_operand:SI 2 "const_int_operand" "")) 0))
4900 (set (match_operand:SI 0 "gpc_reg_operand" "")
4901 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4902 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4904 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4906 (compare:CC (match_dup 0)
4911 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4913 (match_operand:SI 1 "gpc_reg_operand" "r"))
4914 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4920 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4922 (match_operand:SI 1 "gpc_reg_operand" "r"))
4923 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4929 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4931 (match_operand:SI 1 "gpc_reg_operand" "r"))
4932 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4938 (define_expand "ashrsi3"
4939 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4940 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4941 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4946 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4948 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4952 (define_insn "ashrsi3_power"
4953 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4954 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4955 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4956 (clobber (match_scratch:SI 3 "=q,X"))]
4960 {srai|srawi} %0,%1,%h2"
4961 [(set_attr "type" "shift")])
4963 (define_insn "ashrsi3_no_power"
4964 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4965 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4966 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4970 {srai|srawi} %0,%1,%h2"
4971 [(set_attr "type" "var_shift_rotate,shift")])
4974 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4975 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4976 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4978 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4979 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4983 {srai.|srawi.} %3,%1,%h2
4986 [(set_attr "type" "delayed_compare")
4987 (set_attr "length" "4,4,8,8")])
4990 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4991 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4992 (match_operand:SI 2 "reg_or_cint_operand" ""))
4994 (clobber (match_scratch:SI 3 ""))
4995 (clobber (match_scratch:SI 4 ""))]
4996 "TARGET_POWER && reload_completed"
4997 [(parallel [(set (match_dup 3)
4998 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4999 (clobber (match_dup 4))])
5001 (compare:CC (match_dup 3)
5006 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5007 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5008 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5010 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
5013 {sra.|sraw.} %3,%1,%2
5014 {srai.|srawi.} %3,%1,%h2
5017 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5018 (set_attr "length" "4,4,8,8")])
5021 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5022 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5023 (match_operand:SI 2 "reg_or_cint_operand" ""))
5025 (clobber (match_scratch:SI 3 ""))]
5026 "! TARGET_POWER && reload_completed"
5028 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5030 (compare:CC (match_dup 3)
5035 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5036 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5037 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5039 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5040 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5041 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5045 {srai.|srawi.} %0,%1,%h2
5048 [(set_attr "type" "delayed_compare")
5049 (set_attr "length" "4,4,8,8")])
5052 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5053 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5054 (match_operand:SI 2 "reg_or_cint_operand" ""))
5056 (set (match_operand:SI 0 "gpc_reg_operand" "")
5057 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5058 (clobber (match_scratch:SI 4 ""))]
5059 "TARGET_POWER && reload_completed"
5060 [(parallel [(set (match_dup 0)
5061 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5062 (clobber (match_dup 4))])
5064 (compare:CC (match_dup 0)
5069 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5070 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5071 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5073 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5074 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5077 {sra.|sraw.} %0,%1,%2
5078 {srai.|srawi.} %0,%1,%h2
5081 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5082 (set_attr "length" "4,4,8,8")])
5085 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5086 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5087 (match_operand:SI 2 "reg_or_cint_operand" ""))
5089 (set (match_operand:SI 0 "gpc_reg_operand" "")
5090 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5091 "! TARGET_POWER && reload_completed"
5093 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5095 (compare:CC (match_dup 0)
5099 ;; Floating-point insns, excluding normal data motion.
5101 ;; PowerPC has a full set of single-precision floating point instructions.
5103 ;; For the POWER architecture, we pretend that we have both SFmode and
5104 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
5105 ;; The only conversions we will do will be when storing to memory. In that
5106 ;; case, we will use the "frsp" instruction before storing.
5108 ;; Note that when we store into a single-precision memory location, we need to
5109 ;; use the frsp insn first. If the register being stored isn't dead, we
5110 ;; need a scratch register for the frsp. But this is difficult when the store
5111 ;; is done by reload. It is not incorrect to do the frsp on the register in
5112 ;; this case, we just lose precision that we would have otherwise gotten but
5113 ;; is not guaranteed. Perhaps this should be tightened up at some point.
5115 (define_expand "extendsfdf2"
5116 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5117 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5118 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5121 (define_insn_and_split "*extendsfdf2_fpr"
5122 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
5123 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
5124 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5129 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5132 emit_note (NOTE_INSN_DELETED);
5135 [(set_attr "type" "fp,fp,fpload")])
5137 (define_expand "truncdfsf2"
5138 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5139 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5140 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5143 (define_insn "*truncdfsf2_fpr"
5144 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5145 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5146 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5148 [(set_attr "type" "fp")])
5150 (define_insn "aux_truncdfsf2"
5151 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5152 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
5153 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5155 [(set_attr "type" "fp")])
5157 (define_expand "negsf2"
5158 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5159 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5160 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5163 (define_insn "*negsf2"
5164 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5165 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5166 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5168 [(set_attr "type" "fp")])
5170 (define_expand "abssf2"
5171 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5172 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5173 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5176 (define_insn "*abssf2"
5177 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5178 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5179 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5181 [(set_attr "type" "fp")])
5184 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5185 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
5186 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5188 [(set_attr "type" "fp")])
5190 (define_expand "addsf3"
5191 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5192 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5193 (match_operand:SF 2 "gpc_reg_operand" "")))]
5194 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5198 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5199 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5200 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5201 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5203 [(set_attr "type" "fp")
5204 (set_attr "fp_type" "fp_addsub_s")])
5207 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5208 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5209 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5210 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5211 "{fa|fadd} %0,%1,%2"
5212 [(set_attr "type" "fp")])
5214 (define_expand "subsf3"
5215 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5216 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5217 (match_operand:SF 2 "gpc_reg_operand" "")))]
5218 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5222 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5223 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5224 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5225 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5227 [(set_attr "type" "fp")
5228 (set_attr "fp_type" "fp_addsub_s")])
5231 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5232 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5233 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5234 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5235 "{fs|fsub} %0,%1,%2"
5236 [(set_attr "type" "fp")])
5238 (define_expand "mulsf3"
5239 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5240 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5241 (match_operand:SF 2 "gpc_reg_operand" "")))]
5242 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5246 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5247 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5248 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5249 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5251 [(set_attr "type" "fp")
5252 (set_attr "fp_type" "fp_mul_s")])
5255 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5256 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5257 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5258 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5259 "{fm|fmul} %0,%1,%2"
5260 [(set_attr "type" "dmul")])
5262 (define_expand "divsf3"
5263 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5264 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5265 (match_operand:SF 2 "gpc_reg_operand" "")))]
5266 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5270 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5271 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5272 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5273 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5274 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5276 [(set_attr "type" "sdiv")])
5279 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5280 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5281 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5282 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5283 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5284 "{fd|fdiv} %0,%1,%2"
5285 [(set_attr "type" "ddiv")])
5287 (define_expand "recipsf3"
5288 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5289 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")
5290 (match_operand:SF 2 "gpc_reg_operand" "f")]
5292 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5293 && flag_finite_math_only && !flag_trapping_math"
5295 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5300 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5301 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5302 "TARGET_PPC_GFXOPT && flag_finite_math_only"
5304 [(set_attr "type" "fp")])
5307 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5308 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5309 (match_operand:SF 2 "gpc_reg_operand" "f"))
5310 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5311 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5312 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5313 "fmadds %0,%1,%2,%3"
5314 [(set_attr "type" "fp")
5315 (set_attr "fp_type" "fp_maddsub_s")])
5318 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5319 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5320 (match_operand:SF 2 "gpc_reg_operand" "f"))
5321 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5322 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5323 "{fma|fmadd} %0,%1,%2,%3"
5324 [(set_attr "type" "dmul")])
5327 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5328 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5329 (match_operand:SF 2 "gpc_reg_operand" "f"))
5330 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5331 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5332 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5333 "fmsubs %0,%1,%2,%3"
5334 [(set_attr "type" "fp")
5335 (set_attr "fp_type" "fp_maddsub_s")])
5338 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5339 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5340 (match_operand:SF 2 "gpc_reg_operand" "f"))
5341 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5342 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5343 "{fms|fmsub} %0,%1,%2,%3"
5344 [(set_attr "type" "dmul")])
5347 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5348 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5349 (match_operand:SF 2 "gpc_reg_operand" "f"))
5350 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5351 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5352 && TARGET_SINGLE_FLOAT && HONOR_SIGNED_ZEROS (SFmode)"
5353 "fnmadds %0,%1,%2,%3"
5354 [(set_attr "type" "fp")
5355 (set_attr "fp_type" "fp_maddsub_s")])
5358 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5359 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5360 (match_operand:SF 2 "gpc_reg_operand" "f"))
5361 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5362 "TARGET_POWERPC && TARGET_SINGLE_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5363 && ! HONOR_SIGNED_ZEROS (SFmode)"
5364 "fnmadds %0,%1,%2,%3"
5365 [(set_attr "type" "fp")
5366 (set_attr "fp_type" "fp_maddsub_s")])
5369 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5370 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5371 (match_operand:SF 2 "gpc_reg_operand" "f"))
5372 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5373 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5374 "{fnma|fnmadd} %0,%1,%2,%3"
5375 [(set_attr "type" "dmul")])
5378 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5379 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5380 (match_operand:SF 2 "gpc_reg_operand" "f"))
5381 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5382 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5383 && ! HONOR_SIGNED_ZEROS (SFmode)"
5384 "{fnma|fnmadd} %0,%1,%2,%3"
5385 [(set_attr "type" "dmul")])
5388 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5389 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5390 (match_operand:SF 2 "gpc_reg_operand" "f"))
5391 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5392 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5393 && TARGET_SINGLE_FLOAT && HONOR_SIGNED_ZEROS (SFmode)"
5394 "fnmsubs %0,%1,%2,%3"
5395 [(set_attr "type" "fp")
5396 (set_attr "fp_type" "fp_maddsub_s")])
5399 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5400 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5401 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5402 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5403 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5404 && TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)"
5405 "fnmsubs %0,%1,%2,%3"
5406 [(set_attr "type" "fp")
5407 (set_attr "fp_type" "fp_maddsub_s")])
5410 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5411 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5412 (match_operand:SF 2 "gpc_reg_operand" "f"))
5413 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5414 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5415 "{fnms|fnmsub} %0,%1,%2,%3"
5416 [(set_attr "type" "dmul")])
5419 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5420 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5421 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5422 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5423 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5424 && ! HONOR_SIGNED_ZEROS (SFmode)"
5425 "{fnms|fnmsub} %0,%1,%2,%3"
5426 [(set_attr "type" "dmul")])
5428 (define_expand "sqrtsf2"
5429 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5430 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5431 "(TARGET_PPC_GPOPT || TARGET_POWER2 || TARGET_XILINX_FPU)
5432 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5433 && !TARGET_SIMPLE_FPU"
5437 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5438 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5439 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT
5440 && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5442 [(set_attr "type" "ssqrt")])
5445 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5446 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5447 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS
5448 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5450 [(set_attr "type" "dsqrt")])
5452 (define_expand "rsqrtsf2"
5453 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5454 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5456 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5457 && flag_finite_math_only && !flag_trapping_math"
5459 rs6000_emit_swrsqrtsf (operands[0], operands[1]);
5463 (define_insn "*rsqrt_internal1"
5464 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5465 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5467 "TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT"
5469 [(set_attr "type" "fp")])
5471 (define_expand "copysignsf3"
5473 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5475 (neg:SF (abs:SF (match_dup 1))))
5476 (set (match_operand:SF 0 "gpc_reg_operand" "")
5477 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5481 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5482 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
5484 operands[3] = gen_reg_rtx (SFmode);
5485 operands[4] = gen_reg_rtx (SFmode);
5486 operands[5] = CONST0_RTX (SFmode);
5489 (define_expand "copysigndf3"
5491 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5493 (neg:DF (abs:DF (match_dup 1))))
5494 (set (match_operand:DF 0 "gpc_reg_operand" "")
5495 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5499 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5500 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
5502 operands[3] = gen_reg_rtx (DFmode);
5503 operands[4] = gen_reg_rtx (DFmode);
5504 operands[5] = CONST0_RTX (DFmode);
5507 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5508 ;; fsel instruction and some auxiliary computations. Then we just have a
5509 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5511 (define_expand "smaxsf3"
5512 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5513 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5514 (match_operand:SF 2 "gpc_reg_operand" ""))
5517 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5518 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5519 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5521 (define_expand "sminsf3"
5522 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5523 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5524 (match_operand:SF 2 "gpc_reg_operand" ""))
5527 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5528 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5529 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5532 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5533 (match_operator:SF 3 "min_max_operator"
5534 [(match_operand:SF 1 "gpc_reg_operand" "")
5535 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5536 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5537 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5540 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5541 operands[1], operands[2]);
5545 (define_expand "movsicc"
5546 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5547 (if_then_else:SI (match_operand 1 "comparison_operator" "")
5548 (match_operand:SI 2 "gpc_reg_operand" "")
5549 (match_operand:SI 3 "gpc_reg_operand" "")))]
5553 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5559 ;; We use the BASE_REGS for the isel input operands because, if rA is
5560 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5561 ;; because we may switch the operands and rB may end up being rA.
5563 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5564 ;; leave out the mode in operand 4 and use one pattern, but reload can
5565 ;; change the mode underneath our feet and then gets confused trying
5566 ;; to reload the value.
5567 (define_insn "isel_signed"
5568 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5570 (match_operator 1 "comparison_operator"
5571 [(match_operand:CC 4 "cc_reg_operand" "y")
5573 (match_operand:SI 2 "gpc_reg_operand" "b")
5574 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5577 { return output_isel (operands); }"
5578 [(set_attr "length" "4")])
5580 (define_insn "isel_unsigned"
5581 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5583 (match_operator 1 "comparison_operator"
5584 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5586 (match_operand:SI 2 "gpc_reg_operand" "b")
5587 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5590 { return output_isel (operands); }"
5591 [(set_attr "length" "4")])
5593 (define_expand "movsfcc"
5594 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5595 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5596 (match_operand:SF 2 "gpc_reg_operand" "")
5597 (match_operand:SF 3 "gpc_reg_operand" "")))]
5598 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5601 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5607 (define_insn "*fselsfsf4"
5608 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5609 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5610 (match_operand:SF 4 "zero_fp_constant" "F"))
5611 (match_operand:SF 2 "gpc_reg_operand" "f")
5612 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5613 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5615 [(set_attr "type" "fp")])
5617 (define_insn "*fseldfsf4"
5618 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5619 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5620 (match_operand:DF 4 "zero_fp_constant" "F"))
5621 (match_operand:SF 2 "gpc_reg_operand" "f")
5622 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5623 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5625 [(set_attr "type" "fp")])
5627 (define_expand "negdf2"
5628 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5629 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5630 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5633 (define_insn "*negdf2_fpr"
5634 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5635 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5636 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5638 [(set_attr "type" "fp")])
5640 (define_expand "absdf2"
5641 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5642 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5643 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5646 (define_insn "*absdf2_fpr"
5647 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5648 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5649 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5651 [(set_attr "type" "fp")])
5653 (define_insn "*nabsdf2_fpr"
5654 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5655 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
5656 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5658 [(set_attr "type" "fp")])
5660 (define_expand "adddf3"
5661 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5662 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5663 (match_operand:DF 2 "gpc_reg_operand" "")))]
5664 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5667 (define_insn "*adddf3_fpr"
5668 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5669 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5670 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5671 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5672 "{fa|fadd} %0,%1,%2"
5673 [(set_attr "type" "fp")
5674 (set_attr "fp_type" "fp_addsub_d")])
5676 (define_expand "subdf3"
5677 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5678 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5679 (match_operand:DF 2 "gpc_reg_operand" "")))]
5680 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5683 (define_insn "*subdf3_fpr"
5684 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5685 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5686 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5687 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5688 "{fs|fsub} %0,%1,%2"
5689 [(set_attr "type" "fp")
5690 (set_attr "fp_type" "fp_addsub_d")])
5692 (define_expand "muldf3"
5693 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5694 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5695 (match_operand:DF 2 "gpc_reg_operand" "")))]
5696 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5699 (define_insn "*muldf3_fpr"
5700 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5701 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5702 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5703 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5704 "{fm|fmul} %0,%1,%2"
5705 [(set_attr "type" "dmul")
5706 (set_attr "fp_type" "fp_mul_d")])
5708 (define_expand "divdf3"
5709 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5710 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5711 (match_operand:DF 2 "gpc_reg_operand" "")))]
5713 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)
5714 && !TARGET_SIMPLE_FPU"
5717 (define_insn "*divdf3_fpr"
5718 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5719 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5720 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5721 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU"
5722 "{fd|fdiv} %0,%1,%2"
5723 [(set_attr "type" "ddiv")])
5725 (define_expand "recipdf3"
5726 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5727 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")
5728 (match_operand:DF 2 "gpc_reg_operand" "f")]
5730 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_POPCNTB && !optimize_size
5731 && flag_finite_math_only && !flag_trapping_math"
5733 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5738 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5739 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5740 "TARGET_POPCNTB && flag_finite_math_only"
5742 [(set_attr "type" "fp")])
5745 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5746 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5747 (match_operand:DF 2 "gpc_reg_operand" "f"))
5748 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5749 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT"
5750 "{fma|fmadd} %0,%1,%2,%3"
5751 [(set_attr "type" "dmul")
5752 (set_attr "fp_type" "fp_maddsub_d")])
5755 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5756 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5757 (match_operand:DF 2 "gpc_reg_operand" "f"))
5758 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5759 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT"
5760 "{fms|fmsub} %0,%1,%2,%3"
5761 [(set_attr "type" "dmul")
5762 (set_attr "fp_type" "fp_maddsub_d")])
5765 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5766 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5767 (match_operand:DF 2 "gpc_reg_operand" "f"))
5768 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5769 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
5770 && HONOR_SIGNED_ZEROS (DFmode)"
5771 "{fnma|fnmadd} %0,%1,%2,%3"
5772 [(set_attr "type" "dmul")
5773 (set_attr "fp_type" "fp_maddsub_d")])
5776 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5777 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5778 (match_operand:DF 2 "gpc_reg_operand" "f"))
5779 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5780 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
5781 && ! HONOR_SIGNED_ZEROS (DFmode)"
5782 "{fnma|fnmadd} %0,%1,%2,%3"
5783 [(set_attr "type" "dmul")
5784 (set_attr "fp_type" "fp_maddsub_d")])
5787 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5788 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5789 (match_operand:DF 2 "gpc_reg_operand" "f"))
5790 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5791 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
5792 && HONOR_SIGNED_ZEROS (DFmode)"
5793 "{fnms|fnmsub} %0,%1,%2,%3"
5794 [(set_attr "type" "dmul")
5795 (set_attr "fp_type" "fp_maddsub_d")])
5798 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5799 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5800 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5801 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5802 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
5803 && ! HONOR_SIGNED_ZEROS (DFmode)"
5804 "{fnms|fnmsub} %0,%1,%2,%3"
5805 [(set_attr "type" "dmul")
5806 (set_attr "fp_type" "fp_maddsub_d")])
5808 (define_insn "sqrtdf2"
5809 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5810 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5811 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
5812 && TARGET_DOUBLE_FLOAT"
5814 [(set_attr "type" "dsqrt")])
5816 ;; The conditional move instructions allow us to perform max and min
5817 ;; operations even when
5819 (define_expand "smaxdf3"
5820 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5821 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5822 (match_operand:DF 2 "gpc_reg_operand" ""))
5825 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5826 && !flag_trapping_math"
5827 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5829 (define_expand "smindf3"
5830 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5831 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5832 (match_operand:DF 2 "gpc_reg_operand" ""))
5835 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5836 && !flag_trapping_math"
5837 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5840 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5841 (match_operator:DF 3 "min_max_operator"
5842 [(match_operand:DF 1 "gpc_reg_operand" "")
5843 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5844 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5845 && !flag_trapping_math"
5848 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5849 operands[1], operands[2]);
5853 (define_expand "movdfcc"
5854 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5855 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5856 (match_operand:DF 2 "gpc_reg_operand" "")
5857 (match_operand:DF 3 "gpc_reg_operand" "")))]
5858 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5861 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5867 (define_insn "*fseldfdf4"
5868 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5869 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5870 (match_operand:DF 4 "zero_fp_constant" "F"))
5871 (match_operand:DF 2 "gpc_reg_operand" "f")
5872 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5873 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5875 [(set_attr "type" "fp")])
5877 (define_insn "*fselsfdf4"
5878 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5879 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5880 (match_operand:SF 4 "zero_fp_constant" "F"))
5881 (match_operand:DF 2 "gpc_reg_operand" "f")
5882 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5883 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5885 [(set_attr "type" "fp")])
5887 ;; Conversions to and from floating-point.
5889 (define_expand "fixuns_truncsfsi2"
5890 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5891 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5892 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
5895 (define_expand "fix_truncsfsi2"
5896 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5897 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5898 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
5901 ; For each of these conversions, there is a define_expand, a define_insn
5902 ; with a '#' template, and a define_split (with C code). The idea is
5903 ; to allow constant folding with the template of the define_insn,
5904 ; then to have the insns split later (between sched1 and final).
5906 (define_expand "floatsidf2"
5907 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5908 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5911 (clobber (match_dup 4))
5912 (clobber (match_dup 5))
5913 (clobber (match_dup 6))])]
5915 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5918 if (TARGET_E500_DOUBLE)
5920 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5923 if (TARGET_POWERPC64)
5925 rtx x = convert_to_mode (DImode, operands[1], 0);
5926 emit_insn (gen_floatdidf2 (operands[0], x));
5930 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5931 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5932 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5933 operands[5] = gen_reg_rtx (DFmode);
5934 operands[6] = gen_reg_rtx (SImode);
5937 (define_insn_and_split "*floatsidf2_internal"
5938 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5939 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5940 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5941 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5942 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5943 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5944 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5945 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5947 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
5951 rtx lowword, highword;
5952 gcc_assert (MEM_P (operands[4]));
5953 highword = adjust_address (operands[4], SImode, 0);
5954 lowword = adjust_address (operands[4], SImode, 4);
5955 if (! WORDS_BIG_ENDIAN)
5958 tmp = highword; highword = lowword; lowword = tmp;
5961 emit_insn (gen_xorsi3 (operands[6], operands[1],
5962 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5963 emit_move_insn (lowword, operands[6]);
5964 emit_move_insn (highword, operands[2]);
5965 emit_move_insn (operands[5], operands[4]);
5966 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5969 [(set_attr "length" "24")])
5971 (define_expand "floatunssisf2"
5972 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5973 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5974 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
5977 (define_expand "floatunssidf2"
5978 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5979 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5982 (clobber (match_dup 4))
5983 (clobber (match_dup 5))])]
5984 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5987 if (TARGET_E500_DOUBLE)
5989 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5992 if (TARGET_POWERPC64)
5994 rtx x = convert_to_mode (DImode, operands[1], 1);
5995 emit_insn (gen_floatdidf2 (operands[0], x));
5999 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
6000 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
6001 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
6002 operands[5] = gen_reg_rtx (DFmode);
6005 (define_insn_and_split "*floatunssidf2_internal"
6006 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
6007 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6008 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6009 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
6010 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6011 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
6012 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6014 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
6018 rtx lowword, highword;
6019 gcc_assert (MEM_P (operands[4]));
6020 highword = adjust_address (operands[4], SImode, 0);
6021 lowword = adjust_address (operands[4], SImode, 4);
6022 if (! WORDS_BIG_ENDIAN)
6025 tmp = highword; highword = lowword; lowword = tmp;
6028 emit_move_insn (lowword, operands[1]);
6029 emit_move_insn (highword, operands[2]);
6030 emit_move_insn (operands[5], operands[4]);
6031 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6034 [(set_attr "length" "20")])
6036 (define_expand "fix_truncdfsi2"
6037 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
6038 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
6039 (clobber (match_dup 2))
6040 (clobber (match_dup 3))])]
6041 "(TARGET_POWER2 || TARGET_POWERPC)
6042 && TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6045 if (TARGET_E500_DOUBLE)
6047 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
6050 operands[2] = gen_reg_rtx (DImode);
6051 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
6052 && gpc_reg_operand(operands[0], GET_MODE (operands[0])))
6054 operands[3] = gen_reg_rtx (DImode);
6055 emit_insn (gen_fix_truncdfsi2_mfpgpr (operands[0], operands[1],
6056 operands[2], operands[3]));
6059 if (TARGET_PPC_GFXOPT)
6061 rtx orig_dest = operands[0];
6062 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
6063 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
6064 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
6066 if (operands[0] != orig_dest)
6067 emit_move_insn (orig_dest, operands[0]);
6070 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
6073 (define_insn_and_split "*fix_truncdfsi2_internal"
6074 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6075 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
6076 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
6077 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))]
6078 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6079 && TARGET_DOUBLE_FLOAT"
6081 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[3]))"
6086 gcc_assert (MEM_P (operands[3]));
6087 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
6089 emit_insn (gen_fctiwz (operands[2], operands[1]));
6090 emit_move_insn (operands[3], operands[2]);
6091 emit_move_insn (operands[0], lowword);
6094 [(set_attr "length" "16")])
6096 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
6097 [(set (match_operand:SI 0 "memory_operand" "=Z")
6098 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
6099 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
6100 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6101 && TARGET_DOUBLE_FLOAT
6102 && TARGET_PPC_GFXOPT"
6108 emit_insn (gen_fctiwz (operands[2], operands[1]));
6109 emit_insn (gen_stfiwx (operands[0], operands[2]));
6112 [(set_attr "length" "16")])
6114 (define_insn_and_split "fix_truncdfsi2_mfpgpr"
6115 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6116 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
6117 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
6118 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
6119 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
6120 && TARGET_DOUBLE_FLOAT"
6123 [(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
6124 (set (match_dup 3) (match_dup 2))
6125 (set (match_dup 0) (subreg:SI (match_dup 3) 4))]
6127 [(set_attr "length" "12")])
6129 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6130 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6131 ; because the first makes it clear that operand 0 is not live
6132 ; before the instruction.
6133 (define_insn "fctiwz"
6134 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
6135 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
6137 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6138 && TARGET_DOUBLE_FLOAT"
6139 "{fcirz|fctiwz} %0,%1"
6140 [(set_attr "type" "fp")])
6142 (define_insn "btruncdf2"
6143 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6144 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6145 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6147 [(set_attr "type" "fp")])
6149 (define_insn "btruncsf2"
6150 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6151 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6152 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6154 [(set_attr "type" "fp")])
6156 (define_insn "ceildf2"
6157 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6158 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6159 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6161 [(set_attr "type" "fp")])
6163 (define_insn "ceilsf2"
6164 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6165 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6166 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6168 [(set_attr "type" "fp")])
6170 (define_insn "floordf2"
6171 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6172 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6173 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6175 [(set_attr "type" "fp")])
6177 (define_insn "floorsf2"
6178 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6179 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6180 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6182 [(set_attr "type" "fp")])
6184 (define_insn "rounddf2"
6185 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6186 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6187 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6189 [(set_attr "type" "fp")])
6191 (define_insn "roundsf2"
6192 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6193 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6194 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6196 [(set_attr "type" "fp")])
6198 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6199 (define_insn "stfiwx"
6200 [(set (match_operand:SI 0 "memory_operand" "=Z")
6201 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
6205 [(set_attr "type" "fpstore")])
6207 (define_expand "floatsisf2"
6208 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6209 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6210 "TARGET_HARD_FLOAT && !TARGET_FPRS"
6213 (define_insn "floatdidf2"
6214 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6215 (float:DF (match_operand:DI 1 "gpc_reg_operand" "!f#r")))]
6216 "(TARGET_POWERPC64 || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6218 [(set_attr "type" "fp")])
6220 (define_insn "fix_truncdfdi2"
6221 [(set (match_operand:DI 0 "gpc_reg_operand" "=!f#r")
6222 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
6223 "(TARGET_POWERPC64 || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6225 [(set_attr "type" "fp")])
6227 (define_expand "floatdisf2"
6228 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6229 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6230 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6233 rtx val = operands[1];
6234 if (!flag_unsafe_math_optimizations)
6236 rtx label = gen_label_rtx ();
6237 val = gen_reg_rtx (DImode);
6238 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6241 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6245 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6246 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6247 ;; from double rounding.
6248 (define_insn_and_split "floatdisf2_internal1"
6249 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6250 (float:SF (match_operand:DI 1 "gpc_reg_operand" "!f#r")))
6251 (clobber (match_scratch:DF 2 "=f"))]
6252 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6254 "&& reload_completed"
6256 (float:DF (match_dup 1)))
6258 (float_truncate:SF (match_dup 2)))]
6261 ;; Twiddles bits to avoid double rounding.
6262 ;; Bits that might be truncated when converting to DFmode are replaced
6263 ;; by a bit that won't be lost at that stage, but is below the SFmode
6264 ;; rounding position.
6265 (define_expand "floatdisf2_internal2"
6266 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6268 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6270 (clobber (scratch:CC))])
6271 (set (match_dup 3) (plus:DI (match_dup 3)
6273 (set (match_dup 0) (plus:DI (match_dup 0)
6275 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6277 (set (match_dup 0) (ior:DI (match_dup 0)
6279 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6281 (clobber (scratch:CC))])
6282 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6283 (label_ref (match_operand:DI 2 "" ""))
6285 (set (match_dup 0) (match_dup 1))]
6286 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6289 operands[3] = gen_reg_rtx (DImode);
6290 operands[4] = gen_reg_rtx (CCUNSmode);
6293 ;; Define the DImode operations that can be done in a small number
6294 ;; of instructions. The & constraints are to prevent the register
6295 ;; allocator from allocating registers that overlap with the inputs
6296 ;; (for example, having an input in 7,8 and an output in 6,7). We
6297 ;; also allow for the output being the same as one of the inputs.
6299 (define_insn "*adddi3_noppc64"
6300 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6301 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6302 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6303 "! TARGET_POWERPC64"
6306 if (WORDS_BIG_ENDIAN)
6307 return (GET_CODE (operands[2])) != CONST_INT
6308 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6309 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6311 return (GET_CODE (operands[2])) != CONST_INT
6312 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6313 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6315 [(set_attr "type" "two")
6316 (set_attr "length" "8")])
6318 (define_insn "*subdi3_noppc64"
6319 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6320 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6321 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6322 "! TARGET_POWERPC64"
6325 if (WORDS_BIG_ENDIAN)
6326 return (GET_CODE (operands[1]) != CONST_INT)
6327 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6328 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6330 return (GET_CODE (operands[1]) != CONST_INT)
6331 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6332 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
6334 [(set_attr "type" "two")
6335 (set_attr "length" "8")])
6337 (define_insn "*negdi2_noppc64"
6338 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6339 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6340 "! TARGET_POWERPC64"
6343 return (WORDS_BIG_ENDIAN)
6344 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6345 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6347 [(set_attr "type" "two")
6348 (set_attr "length" "8")])
6350 (define_expand "mulsidi3"
6351 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6352 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6353 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6354 "! TARGET_POWERPC64"
6357 if (! TARGET_POWER && ! TARGET_POWERPC)
6359 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6360 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6361 emit_insn (gen_mull_call ());
6362 if (WORDS_BIG_ENDIAN)
6363 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
6366 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
6367 gen_rtx_REG (SImode, 3));
6368 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
6369 gen_rtx_REG (SImode, 4));
6373 else if (TARGET_POWER)
6375 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6380 (define_insn "mulsidi3_mq"
6381 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6382 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6383 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6384 (clobber (match_scratch:SI 3 "=q"))]
6386 "mul %0,%1,%2\;mfmq %L0"
6387 [(set_attr "type" "imul")
6388 (set_attr "length" "8")])
6390 (define_insn "*mulsidi3_no_mq"
6391 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6392 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6393 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6394 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6397 return (WORDS_BIG_ENDIAN)
6398 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6399 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6401 [(set_attr "type" "imul")
6402 (set_attr "length" "8")])
6405 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6406 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6407 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6408 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6411 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6412 (sign_extend:DI (match_dup 2)))
6415 (mult:SI (match_dup 1)
6419 int endian = (WORDS_BIG_ENDIAN == 0);
6420 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6421 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6424 (define_expand "umulsidi3"
6425 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6426 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6427 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6428 "TARGET_POWERPC && ! TARGET_POWERPC64"
6433 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6438 (define_insn "umulsidi3_mq"
6439 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6440 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6441 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6442 (clobber (match_scratch:SI 3 "=q"))]
6443 "TARGET_POWERPC && TARGET_POWER"
6446 return (WORDS_BIG_ENDIAN)
6447 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6448 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6450 [(set_attr "type" "imul")
6451 (set_attr "length" "8")])
6453 (define_insn "*umulsidi3_no_mq"
6454 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6455 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6456 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6457 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6460 return (WORDS_BIG_ENDIAN)
6461 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6462 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6464 [(set_attr "type" "imul")
6465 (set_attr "length" "8")])
6468 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6469 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6470 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6471 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6474 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6475 (zero_extend:DI (match_dup 2)))
6478 (mult:SI (match_dup 1)
6482 int endian = (WORDS_BIG_ENDIAN == 0);
6483 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6484 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6487 (define_expand "smulsi3_highpart"
6488 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6490 (lshiftrt:DI (mult:DI (sign_extend:DI
6491 (match_operand:SI 1 "gpc_reg_operand" ""))
6493 (match_operand:SI 2 "gpc_reg_operand" "")))
6498 if (! TARGET_POWER && ! TARGET_POWERPC)
6500 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6501 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6502 emit_insn (gen_mulh_call ());
6503 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
6506 else if (TARGET_POWER)
6508 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6513 (define_insn "smulsi3_highpart_mq"
6514 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6516 (lshiftrt:DI (mult:DI (sign_extend:DI
6517 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6519 (match_operand:SI 2 "gpc_reg_operand" "r")))
6521 (clobber (match_scratch:SI 3 "=q"))]
6524 [(set_attr "type" "imul")])
6526 (define_insn "*smulsi3_highpart_no_mq"
6527 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6529 (lshiftrt:DI (mult:DI (sign_extend:DI
6530 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6532 (match_operand:SI 2 "gpc_reg_operand" "r")))
6534 "TARGET_POWERPC && ! TARGET_POWER"
6536 [(set_attr "type" "imul")])
6538 (define_expand "umulsi3_highpart"
6539 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6541 (lshiftrt:DI (mult:DI (zero_extend:DI
6542 (match_operand:SI 1 "gpc_reg_operand" ""))
6544 (match_operand:SI 2 "gpc_reg_operand" "")))
6551 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6556 (define_insn "umulsi3_highpart_mq"
6557 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6559 (lshiftrt:DI (mult:DI (zero_extend:DI
6560 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6562 (match_operand:SI 2 "gpc_reg_operand" "r")))
6564 (clobber (match_scratch:SI 3 "=q"))]
6565 "TARGET_POWERPC && TARGET_POWER"
6567 [(set_attr "type" "imul")])
6569 (define_insn "*umulsi3_highpart_no_mq"
6570 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6572 (lshiftrt:DI (mult:DI (zero_extend:DI
6573 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6575 (match_operand:SI 2 "gpc_reg_operand" "r")))
6577 "TARGET_POWERPC && ! TARGET_POWER"
6579 [(set_attr "type" "imul")])
6581 ;; If operands 0 and 2 are in the same register, we have a problem. But
6582 ;; operands 0 and 1 (the usual case) can be in the same register. That's
6583 ;; why we have the strange constraints below.
6584 (define_insn "ashldi3_power"
6585 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6586 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6587 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6588 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6591 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
6592 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6593 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6594 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
6595 [(set_attr "length" "8")])
6597 (define_insn "lshrdi3_power"
6598 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6599 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6600 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6601 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6604 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
6605 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6606 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6607 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
6608 [(set_attr "length" "8")])
6610 ;; Shift by a variable amount is too complex to be worth open-coding. We
6611 ;; just handle shifts by constants.
6612 (define_insn "ashrdi3_power"
6613 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6614 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6615 (match_operand:SI 2 "const_int_operand" "M,i")))
6616 (clobber (match_scratch:SI 3 "=X,q"))]
6619 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6620 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
6621 [(set_attr "type" "shift")
6622 (set_attr "length" "8")])
6624 (define_insn "ashrdi3_no_power"
6625 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6626 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6627 (match_operand:SI 2 "const_int_operand" "M,i")))]
6628 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
6630 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6631 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
6632 [(set_attr "type" "two,three")
6633 (set_attr "length" "8,12")])
6635 (define_insn "*ashrdisi3_noppc64"
6636 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6637 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6638 (const_int 32)) 4))]
6639 "TARGET_32BIT && !TARGET_POWERPC64"
6642 if (REGNO (operands[0]) == REGNO (operands[1]))
6645 return \"mr %0,%1\";
6647 [(set_attr "length" "4")])
6650 ;; PowerPC64 DImode operations.
6652 (define_insn_and_split "absdi2"
6653 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6654 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6655 (clobber (match_scratch:DI 2 "=&r,&r"))]
6658 "&& reload_completed"
6659 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6660 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6661 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6664 (define_insn_and_split "*nabsdi2"
6665 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6666 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6667 (clobber (match_scratch:DI 2 "=&r,&r"))]
6670 "&& reload_completed"
6671 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6672 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6673 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
6676 (define_insn "muldi3"
6677 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6678 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6679 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6685 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6686 (const_string "imul3")
6687 (match_operand:SI 2 "short_cint_operand" "")
6688 (const_string "imul2")]
6689 (const_string "lmul")))])
6691 (define_insn "*muldi3_internal1"
6692 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6693 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6694 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6696 (clobber (match_scratch:DI 3 "=r,r"))]
6701 [(set_attr "type" "lmul_compare")
6702 (set_attr "length" "4,8")])
6705 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6706 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6707 (match_operand:DI 2 "gpc_reg_operand" ""))
6709 (clobber (match_scratch:DI 3 ""))]
6710 "TARGET_POWERPC64 && reload_completed"
6712 (mult:DI (match_dup 1) (match_dup 2)))
6714 (compare:CC (match_dup 3)
6718 (define_insn "*muldi3_internal2"
6719 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6720 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6721 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6723 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6724 (mult:DI (match_dup 1) (match_dup 2)))]
6729 [(set_attr "type" "lmul_compare")
6730 (set_attr "length" "4,8")])
6733 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6734 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6735 (match_operand:DI 2 "gpc_reg_operand" ""))
6737 (set (match_operand:DI 0 "gpc_reg_operand" "")
6738 (mult:DI (match_dup 1) (match_dup 2)))]
6739 "TARGET_POWERPC64 && reload_completed"
6741 (mult:DI (match_dup 1) (match_dup 2)))
6743 (compare:CC (match_dup 0)
6747 (define_insn "smuldi3_highpart"
6748 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6750 (lshiftrt:TI (mult:TI (sign_extend:TI
6751 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6753 (match_operand:DI 2 "gpc_reg_operand" "r")))
6757 [(set_attr "type" "lmul")])
6759 (define_insn "umuldi3_highpart"
6760 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6762 (lshiftrt:TI (mult:TI (zero_extend:TI
6763 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6765 (match_operand:DI 2 "gpc_reg_operand" "r")))
6769 [(set_attr "type" "lmul")])
6771 (define_insn "rotldi3"
6772 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6773 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6774 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
6779 [(set_attr "type" "var_shift_rotate,integer")])
6781 (define_insn "*rotldi3_internal2"
6782 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6783 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6784 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6786 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6793 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6794 (set_attr "length" "4,4,8,8")])
6797 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6798 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6799 (match_operand:DI 2 "reg_or_cint_operand" ""))
6801 (clobber (match_scratch:DI 3 ""))]
6802 "TARGET_POWERPC64 && reload_completed"
6804 (rotate:DI (match_dup 1) (match_dup 2)))
6806 (compare:CC (match_dup 3)
6810 (define_insn "*rotldi3_internal3"
6811 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6812 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6813 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6815 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6816 (rotate:DI (match_dup 1) (match_dup 2)))]
6823 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6824 (set_attr "length" "4,4,8,8")])
6827 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6828 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6829 (match_operand:DI 2 "reg_or_cint_operand" ""))
6831 (set (match_operand:DI 0 "gpc_reg_operand" "")
6832 (rotate:DI (match_dup 1) (match_dup 2)))]
6833 "TARGET_POWERPC64 && reload_completed"
6835 (rotate:DI (match_dup 1) (match_dup 2)))
6837 (compare:CC (match_dup 0)
6841 (define_insn "*rotldi3_internal4"
6842 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6843 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6844 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6845 (match_operand:DI 3 "mask64_operand" "n,n")))]
6848 rldc%B3 %0,%1,%2,%S3
6849 rldic%B3 %0,%1,%H2,%S3"
6850 [(set_attr "type" "var_shift_rotate,integer")])
6852 (define_insn "*rotldi3_internal5"
6853 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6855 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6856 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6857 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6859 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
6862 rldc%B3. %4,%1,%2,%S3
6863 rldic%B3. %4,%1,%H2,%S3
6866 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6867 (set_attr "length" "4,4,8,8")])
6870 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6872 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6873 (match_operand:DI 2 "reg_or_cint_operand" ""))
6874 (match_operand:DI 3 "mask64_operand" ""))
6876 (clobber (match_scratch:DI 4 ""))]
6877 "TARGET_POWERPC64 && reload_completed"
6879 (and:DI (rotate:DI (match_dup 1)
6883 (compare:CC (match_dup 4)
6887 (define_insn "*rotldi3_internal6"
6888 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
6890 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6891 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6892 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6894 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6895 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6898 rldc%B3. %0,%1,%2,%S3
6899 rldic%B3. %0,%1,%H2,%S3
6902 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6903 (set_attr "length" "4,4,8,8")])
6906 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
6908 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6909 (match_operand:DI 2 "reg_or_cint_operand" ""))
6910 (match_operand:DI 3 "mask64_operand" ""))
6912 (set (match_operand:DI 0 "gpc_reg_operand" "")
6913 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6914 "TARGET_POWERPC64 && reload_completed"
6916 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6918 (compare:CC (match_dup 0)
6922 (define_insn "*rotldi3_internal7"
6923 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6926 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6927 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6931 rldicl %0,%1,%H2,56"
6932 [(set_attr "type" "var_shift_rotate,integer")])
6934 (define_insn "*rotldi3_internal8"
6935 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6936 (compare:CC (zero_extend:DI
6938 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6939 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6941 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6945 rldicl. %3,%1,%H2,56
6948 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6949 (set_attr "length" "4,4,8,8")])
6952 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6953 (compare:CC (zero_extend:DI
6955 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6956 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6958 (clobber (match_scratch:DI 3 ""))]
6959 "TARGET_POWERPC64 && reload_completed"
6961 (zero_extend:DI (subreg:QI
6962 (rotate:DI (match_dup 1)
6965 (compare:CC (match_dup 3)
6969 (define_insn "*rotldi3_internal9"
6970 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6971 (compare:CC (zero_extend:DI
6973 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6974 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6976 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6977 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6981 rldicl. %0,%1,%H2,56
6984 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6985 (set_attr "length" "4,4,8,8")])
6988 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6989 (compare:CC (zero_extend:DI
6991 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6992 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6994 (set (match_operand:DI 0 "gpc_reg_operand" "")
6995 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6996 "TARGET_POWERPC64 && reload_completed"
6998 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7000 (compare:CC (match_dup 0)
7004 (define_insn "*rotldi3_internal10"
7005 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7008 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7009 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7013 rldicl %0,%1,%H2,48"
7014 [(set_attr "type" "var_shift_rotate,integer")])
7016 (define_insn "*rotldi3_internal11"
7017 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7018 (compare:CC (zero_extend:DI
7020 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7021 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7023 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7027 rldicl. %3,%1,%H2,48
7030 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7031 (set_attr "length" "4,4,8,8")])
7034 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7035 (compare:CC (zero_extend:DI
7037 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7038 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7040 (clobber (match_scratch:DI 3 ""))]
7041 "TARGET_POWERPC64 && reload_completed"
7043 (zero_extend:DI (subreg:HI
7044 (rotate:DI (match_dup 1)
7047 (compare:CC (match_dup 3)
7051 (define_insn "*rotldi3_internal12"
7052 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7053 (compare:CC (zero_extend:DI
7055 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7056 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7058 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7059 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7063 rldicl. %0,%1,%H2,48
7066 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7067 (set_attr "length" "4,4,8,8")])
7070 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7071 (compare:CC (zero_extend:DI
7073 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7074 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7076 (set (match_operand:DI 0 "gpc_reg_operand" "")
7077 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7078 "TARGET_POWERPC64 && reload_completed"
7080 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7082 (compare:CC (match_dup 0)
7086 (define_insn "*rotldi3_internal13"
7087 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7090 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7091 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7095 rldicl %0,%1,%H2,32"
7096 [(set_attr "type" "var_shift_rotate,integer")])
7098 (define_insn "*rotldi3_internal14"
7099 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7100 (compare:CC (zero_extend:DI
7102 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7103 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7105 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7109 rldicl. %3,%1,%H2,32
7112 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7113 (set_attr "length" "4,4,8,8")])
7116 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7117 (compare:CC (zero_extend:DI
7119 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7120 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7122 (clobber (match_scratch:DI 3 ""))]
7123 "TARGET_POWERPC64 && reload_completed"
7125 (zero_extend:DI (subreg:SI
7126 (rotate:DI (match_dup 1)
7129 (compare:CC (match_dup 3)
7133 (define_insn "*rotldi3_internal15"
7134 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7135 (compare:CC (zero_extend:DI
7137 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7138 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7140 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7141 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7145 rldicl. %0,%1,%H2,32
7148 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7149 (set_attr "length" "4,4,8,8")])
7152 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7153 (compare:CC (zero_extend:DI
7155 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7156 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7158 (set (match_operand:DI 0 "gpc_reg_operand" "")
7159 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7160 "TARGET_POWERPC64 && reload_completed"
7162 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7164 (compare:CC (match_dup 0)
7168 (define_expand "ashldi3"
7169 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7170 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7171 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7172 "TARGET_POWERPC64 || TARGET_POWER"
7175 if (TARGET_POWERPC64)
7177 else if (TARGET_POWER)
7179 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
7186 (define_insn "*ashldi3_internal1"
7187 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7188 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7189 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7194 [(set_attr "type" "var_shift_rotate,shift")])
7196 (define_insn "*ashldi3_internal2"
7197 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7198 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7199 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7201 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7208 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7209 (set_attr "length" "4,4,8,8")])
7212 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7213 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7214 (match_operand:SI 2 "reg_or_cint_operand" ""))
7216 (clobber (match_scratch:DI 3 ""))]
7217 "TARGET_POWERPC64 && reload_completed"
7219 (ashift:DI (match_dup 1) (match_dup 2)))
7221 (compare:CC (match_dup 3)
7225 (define_insn "*ashldi3_internal3"
7226 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7227 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7228 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7230 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7231 (ashift:DI (match_dup 1) (match_dup 2)))]
7238 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7239 (set_attr "length" "4,4,8,8")])
7242 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7243 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7244 (match_operand:SI 2 "reg_or_cint_operand" ""))
7246 (set (match_operand:DI 0 "gpc_reg_operand" "")
7247 (ashift:DI (match_dup 1) (match_dup 2)))]
7248 "TARGET_POWERPC64 && reload_completed"
7250 (ashift:DI (match_dup 1) (match_dup 2)))
7252 (compare:CC (match_dup 0)
7256 (define_insn "*ashldi3_internal4"
7257 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7258 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7259 (match_operand:SI 2 "const_int_operand" "i"))
7260 (match_operand:DI 3 "const_int_operand" "n")))]
7261 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7262 "rldic %0,%1,%H2,%W3")
7264 (define_insn "ashldi3_internal5"
7265 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7267 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7268 (match_operand:SI 2 "const_int_operand" "i,i"))
7269 (match_operand:DI 3 "const_int_operand" "n,n"))
7271 (clobber (match_scratch:DI 4 "=r,r"))]
7272 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7274 rldic. %4,%1,%H2,%W3
7276 [(set_attr "type" "compare")
7277 (set_attr "length" "4,8")])
7280 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7282 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7283 (match_operand:SI 2 "const_int_operand" ""))
7284 (match_operand:DI 3 "const_int_operand" ""))
7286 (clobber (match_scratch:DI 4 ""))]
7287 "TARGET_POWERPC64 && reload_completed
7288 && includes_rldic_lshift_p (operands[2], operands[3])"
7290 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7293 (compare:CC (match_dup 4)
7297 (define_insn "*ashldi3_internal6"
7298 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7300 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7301 (match_operand:SI 2 "const_int_operand" "i,i"))
7302 (match_operand:DI 3 "const_int_operand" "n,n"))
7304 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7305 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7306 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7308 rldic. %0,%1,%H2,%W3
7310 [(set_attr "type" "compare")
7311 (set_attr "length" "4,8")])
7314 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7316 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7317 (match_operand:SI 2 "const_int_operand" ""))
7318 (match_operand:DI 3 "const_int_operand" ""))
7320 (set (match_operand:DI 0 "gpc_reg_operand" "")
7321 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7322 "TARGET_POWERPC64 && reload_completed
7323 && includes_rldic_lshift_p (operands[2], operands[3])"
7325 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7328 (compare:CC (match_dup 0)
7332 (define_insn "*ashldi3_internal7"
7333 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7334 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7335 (match_operand:SI 2 "const_int_operand" "i"))
7336 (match_operand:DI 3 "mask64_operand" "n")))]
7337 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7338 "rldicr %0,%1,%H2,%S3")
7340 (define_insn "ashldi3_internal8"
7341 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7343 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7344 (match_operand:SI 2 "const_int_operand" "i,i"))
7345 (match_operand:DI 3 "mask64_operand" "n,n"))
7347 (clobber (match_scratch:DI 4 "=r,r"))]
7348 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7350 rldicr. %4,%1,%H2,%S3
7352 [(set_attr "type" "compare")
7353 (set_attr "length" "4,8")])
7356 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7358 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7359 (match_operand:SI 2 "const_int_operand" ""))
7360 (match_operand:DI 3 "mask64_operand" ""))
7362 (clobber (match_scratch:DI 4 ""))]
7363 "TARGET_POWERPC64 && reload_completed
7364 && includes_rldicr_lshift_p (operands[2], operands[3])"
7366 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7369 (compare:CC (match_dup 4)
7373 (define_insn "*ashldi3_internal9"
7374 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7376 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7377 (match_operand:SI 2 "const_int_operand" "i,i"))
7378 (match_operand:DI 3 "mask64_operand" "n,n"))
7380 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7381 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7382 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7384 rldicr. %0,%1,%H2,%S3
7386 [(set_attr "type" "compare")
7387 (set_attr "length" "4,8")])
7390 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7392 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7393 (match_operand:SI 2 "const_int_operand" ""))
7394 (match_operand:DI 3 "mask64_operand" ""))
7396 (set (match_operand:DI 0 "gpc_reg_operand" "")
7397 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7398 "TARGET_POWERPC64 && reload_completed
7399 && includes_rldicr_lshift_p (operands[2], operands[3])"
7401 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7404 (compare:CC (match_dup 0)
7408 (define_expand "lshrdi3"
7409 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7410 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7411 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7412 "TARGET_POWERPC64 || TARGET_POWER"
7415 if (TARGET_POWERPC64)
7417 else if (TARGET_POWER)
7419 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7426 (define_insn "*lshrdi3_internal1"
7427 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7428 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7429 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7434 [(set_attr "type" "var_shift_rotate,shift")])
7436 (define_insn "*lshrdi3_internal2"
7437 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7438 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7439 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7441 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7448 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7449 (set_attr "length" "4,4,8,8")])
7452 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7453 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7454 (match_operand:SI 2 "reg_or_cint_operand" ""))
7456 (clobber (match_scratch:DI 3 ""))]
7457 "TARGET_POWERPC64 && reload_completed"
7459 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7461 (compare:CC (match_dup 3)
7465 (define_insn "*lshrdi3_internal3"
7466 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7467 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7468 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7470 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7471 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7478 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7479 (set_attr "length" "4,4,8,8")])
7482 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7483 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7484 (match_operand:SI 2 "reg_or_cint_operand" ""))
7486 (set (match_operand:DI 0 "gpc_reg_operand" "")
7487 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7488 "TARGET_POWERPC64 && reload_completed"
7490 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7492 (compare:CC (match_dup 0)
7496 (define_expand "ashrdi3"
7497 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7498 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7499 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7503 if (TARGET_POWERPC64)
7505 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7507 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7510 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7511 && WORDS_BIG_ENDIAN)
7513 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7520 (define_insn "*ashrdi3_internal1"
7521 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7522 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7523 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7528 [(set_attr "type" "var_shift_rotate,shift")])
7530 (define_insn "*ashrdi3_internal2"
7531 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7532 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7533 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7535 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7542 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7543 (set_attr "length" "4,4,8,8")])
7546 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7547 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7548 (match_operand:SI 2 "reg_or_cint_operand" ""))
7550 (clobber (match_scratch:DI 3 ""))]
7551 "TARGET_POWERPC64 && reload_completed"
7553 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7555 (compare:CC (match_dup 3)
7559 (define_insn "*ashrdi3_internal3"
7560 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7561 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7562 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7564 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7565 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7572 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7573 (set_attr "length" "4,4,8,8")])
7576 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7577 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7578 (match_operand:SI 2 "reg_or_cint_operand" ""))
7580 (set (match_operand:DI 0 "gpc_reg_operand" "")
7581 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7582 "TARGET_POWERPC64 && reload_completed"
7584 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7586 (compare:CC (match_dup 0)
7590 (define_expand "anddi3"
7592 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7593 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7594 (match_operand:DI 2 "and64_2_operand" "")))
7595 (clobber (match_scratch:CC 3 ""))])]
7599 (define_insn "anddi3_mc"
7600 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7601 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7602 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7603 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7604 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
7607 rldic%B2 %0,%1,0,%S2
7608 rlwinm %0,%1,0,%m2,%M2
7612 [(set_attr "type" "*,*,*,compare,compare,*")
7613 (set_attr "length" "4,4,4,4,4,8")])
7615 (define_insn "anddi3_nomc"
7616 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7617 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
7618 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
7619 (clobber (match_scratch:CC 3 "=X,X,X,X"))]
7620 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
7623 rldic%B2 %0,%1,0,%S2
7624 rlwinm %0,%1,0,%m2,%M2
7626 [(set_attr "length" "4,4,4,8")])
7629 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7630 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7631 (match_operand:DI 2 "mask64_2_operand" "")))
7632 (clobber (match_scratch:CC 3 ""))]
7634 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7635 && !mask_operand (operands[2], DImode)
7636 && !mask64_operand (operands[2], DImode)"
7638 (and:DI (rotate:DI (match_dup 1)
7642 (and:DI (rotate:DI (match_dup 0)
7646 build_mask64_2_operands (operands[2], &operands[4]);
7649 (define_insn "*anddi3_internal2_mc"
7650 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7651 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7652 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7654 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7655 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7656 "TARGET_64BIT && rs6000_gen_cell_microcode"
7659 rldic%B2. %3,%1,0,%S2
7660 rlwinm. %3,%1,0,%m2,%M2
7670 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7671 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7674 [(set (match_operand:CC 0 "cc_reg_operand" "")
7675 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7676 (match_operand:DI 2 "mask64_2_operand" ""))
7678 (clobber (match_scratch:DI 3 ""))
7679 (clobber (match_scratch:CC 4 ""))]
7680 "TARGET_64BIT && reload_completed
7681 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7682 && !mask_operand (operands[2], DImode)
7683 && !mask64_operand (operands[2], DImode)"
7685 (and:DI (rotate:DI (match_dup 1)
7688 (parallel [(set (match_dup 0)
7689 (compare:CC (and:DI (rotate:DI (match_dup 3)
7693 (clobber (match_dup 3))])]
7696 build_mask64_2_operands (operands[2], &operands[5]);
7699 (define_insn "*anddi3_internal3_mc"
7700 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7701 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7702 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7704 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
7705 (and:DI (match_dup 1) (match_dup 2)))
7706 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7707 "TARGET_64BIT && rs6000_gen_cell_microcode"
7710 rldic%B2. %0,%1,0,%S2
7711 rlwinm. %0,%1,0,%m2,%M2
7721 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7722 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7725 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7726 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7727 (match_operand:DI 2 "and64_2_operand" ""))
7729 (set (match_operand:DI 0 "gpc_reg_operand" "")
7730 (and:DI (match_dup 1) (match_dup 2)))
7731 (clobber (match_scratch:CC 4 ""))]
7732 "TARGET_64BIT && reload_completed"
7733 [(parallel [(set (match_dup 0)
7734 (and:DI (match_dup 1) (match_dup 2)))
7735 (clobber (match_dup 4))])
7737 (compare:CC (match_dup 0)
7742 [(set (match_operand:CC 3 "cc_reg_operand" "")
7743 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7744 (match_operand:DI 2 "mask64_2_operand" ""))
7746 (set (match_operand:DI 0 "gpc_reg_operand" "")
7747 (and:DI (match_dup 1) (match_dup 2)))
7748 (clobber (match_scratch:CC 4 ""))]
7749 "TARGET_64BIT && reload_completed
7750 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7751 && !mask_operand (operands[2], DImode)
7752 && !mask64_operand (operands[2], DImode)"
7754 (and:DI (rotate:DI (match_dup 1)
7757 (parallel [(set (match_dup 3)
7758 (compare:CC (and:DI (rotate:DI (match_dup 0)
7763 (and:DI (rotate:DI (match_dup 0)
7768 build_mask64_2_operands (operands[2], &operands[5]);
7771 (define_expand "iordi3"
7772 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7773 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7774 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7778 if (non_logical_cint_operand (operands[2], DImode))
7780 HOST_WIDE_INT value;
7781 rtx tmp = ((!can_create_pseudo_p ()
7782 || rtx_equal_p (operands[0], operands[1]))
7783 ? operands[0] : gen_reg_rtx (DImode));
7785 if (GET_CODE (operands[2]) == CONST_INT)
7787 value = INTVAL (operands[2]);
7788 emit_insn (gen_iordi3 (tmp, operands[1],
7789 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7793 value = CONST_DOUBLE_LOW (operands[2]);
7794 emit_insn (gen_iordi3 (tmp, operands[1],
7795 immed_double_const (value
7796 & (~ (HOST_WIDE_INT) 0xffff),
7800 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7805 (define_expand "xordi3"
7806 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7807 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7808 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7812 if (non_logical_cint_operand (operands[2], DImode))
7814 HOST_WIDE_INT value;
7815 rtx tmp = ((!can_create_pseudo_p ()
7816 || rtx_equal_p (operands[0], operands[1]))
7817 ? operands[0] : gen_reg_rtx (DImode));
7819 if (GET_CODE (operands[2]) == CONST_INT)
7821 value = INTVAL (operands[2]);
7822 emit_insn (gen_xordi3 (tmp, operands[1],
7823 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7827 value = CONST_DOUBLE_LOW (operands[2]);
7828 emit_insn (gen_xordi3 (tmp, operands[1],
7829 immed_double_const (value
7830 & (~ (HOST_WIDE_INT) 0xffff),
7834 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7839 (define_insn "*booldi3_internal1"
7840 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7841 (match_operator:DI 3 "boolean_or_operator"
7842 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7843 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7850 (define_insn "*booldi3_internal2"
7851 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7852 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7853 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7854 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7856 (clobber (match_scratch:DI 3 "=r,r"))]
7861 [(set_attr "type" "compare")
7862 (set_attr "length" "4,8")])
7865 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7866 (compare:CC (match_operator:DI 4 "boolean_operator"
7867 [(match_operand:DI 1 "gpc_reg_operand" "")
7868 (match_operand:DI 2 "gpc_reg_operand" "")])
7870 (clobber (match_scratch:DI 3 ""))]
7871 "TARGET_POWERPC64 && reload_completed"
7872 [(set (match_dup 3) (match_dup 4))
7874 (compare:CC (match_dup 3)
7878 (define_insn "*booldi3_internal3"
7879 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7880 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7881 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7882 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7884 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7890 [(set_attr "type" "compare")
7891 (set_attr "length" "4,8")])
7894 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7895 (compare:CC (match_operator:DI 4 "boolean_operator"
7896 [(match_operand:DI 1 "gpc_reg_operand" "")
7897 (match_operand:DI 2 "gpc_reg_operand" "")])
7899 (set (match_operand:DI 0 "gpc_reg_operand" "")
7901 "TARGET_POWERPC64 && reload_completed"
7902 [(set (match_dup 0) (match_dup 4))
7904 (compare:CC (match_dup 0)
7908 ;; Split a logical operation that we can't do in one insn into two insns,
7909 ;; each of which does one 16-bit part. This is used by combine.
7912 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7913 (match_operator:DI 3 "boolean_or_operator"
7914 [(match_operand:DI 1 "gpc_reg_operand" "")
7915 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7917 [(set (match_dup 0) (match_dup 4))
7918 (set (match_dup 0) (match_dup 5))]
7923 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7925 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7926 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7928 i4 = GEN_INT (value & 0xffff);
7932 i3 = GEN_INT (INTVAL (operands[2])
7933 & (~ (HOST_WIDE_INT) 0xffff));
7934 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7936 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7938 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7942 (define_insn "*boolcdi3_internal1"
7943 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7944 (match_operator:DI 3 "boolean_operator"
7945 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7946 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7950 (define_insn "*boolcdi3_internal2"
7951 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7952 (compare:CC (match_operator:DI 4 "boolean_operator"
7953 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7954 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7956 (clobber (match_scratch:DI 3 "=r,r"))]
7961 [(set_attr "type" "compare")
7962 (set_attr "length" "4,8")])
7965 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7966 (compare:CC (match_operator:DI 4 "boolean_operator"
7967 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7968 (match_operand:DI 2 "gpc_reg_operand" "")])
7970 (clobber (match_scratch:DI 3 ""))]
7971 "TARGET_POWERPC64 && reload_completed"
7972 [(set (match_dup 3) (match_dup 4))
7974 (compare:CC (match_dup 3)
7978 (define_insn "*boolcdi3_internal3"
7979 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7980 (compare:CC (match_operator:DI 4 "boolean_operator"
7981 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7982 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7984 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7990 [(set_attr "type" "compare")
7991 (set_attr "length" "4,8")])
7994 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7995 (compare:CC (match_operator:DI 4 "boolean_operator"
7996 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7997 (match_operand:DI 2 "gpc_reg_operand" "")])
7999 (set (match_operand:DI 0 "gpc_reg_operand" "")
8001 "TARGET_POWERPC64 && reload_completed"
8002 [(set (match_dup 0) (match_dup 4))
8004 (compare:CC (match_dup 0)
8008 (define_insn "*boolccdi3_internal1"
8009 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8010 (match_operator:DI 3 "boolean_operator"
8011 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8012 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
8016 (define_insn "*boolccdi3_internal2"
8017 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8018 (compare:CC (match_operator:DI 4 "boolean_operator"
8019 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8020 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8022 (clobber (match_scratch:DI 3 "=r,r"))]
8027 [(set_attr "type" "compare")
8028 (set_attr "length" "4,8")])
8031 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8032 (compare:CC (match_operator:DI 4 "boolean_operator"
8033 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8034 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8036 (clobber (match_scratch:DI 3 ""))]
8037 "TARGET_POWERPC64 && reload_completed"
8038 [(set (match_dup 3) (match_dup 4))
8040 (compare:CC (match_dup 3)
8044 (define_insn "*boolccdi3_internal3"
8045 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8046 (compare:CC (match_operator:DI 4 "boolean_operator"
8047 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8048 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8050 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8056 [(set_attr "type" "compare")
8057 (set_attr "length" "4,8")])
8060 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8061 (compare:CC (match_operator:DI 4 "boolean_operator"
8062 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8063 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8065 (set (match_operand:DI 0 "gpc_reg_operand" "")
8067 "TARGET_POWERPC64 && reload_completed"
8068 [(set (match_dup 0) (match_dup 4))
8070 (compare:CC (match_dup 0)
8074 ;; Now define ways of moving data around.
8076 ;; Set up a register with a value from the GOT table
8078 (define_expand "movsi_got"
8079 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8080 (unspec:SI [(match_operand:SI 1 "got_operand" "")
8081 (match_dup 2)] UNSPEC_MOVSI_GOT))]
8082 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8085 if (GET_CODE (operands[1]) == CONST)
8087 rtx offset = const0_rtx;
8088 HOST_WIDE_INT value;
8090 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8091 value = INTVAL (offset);
8094 rtx tmp = (!can_create_pseudo_p ()
8096 : gen_reg_rtx (Pmode));
8097 emit_insn (gen_movsi_got (tmp, operands[1]));
8098 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8103 operands[2] = rs6000_got_register (operands[1]);
8106 (define_insn "*movsi_got_internal"
8107 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8108 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8109 (match_operand:SI 2 "gpc_reg_operand" "b")]
8111 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8112 "{l|lwz} %0,%a1@got(%2)"
8113 [(set_attr "type" "load")])
8115 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
8116 ;; didn't get allocated to a hard register.
8118 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8119 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8120 (match_operand:SI 2 "memory_operand" "")]
8122 "DEFAULT_ABI == ABI_V4
8124 && (reload_in_progress || reload_completed)"
8125 [(set (match_dup 0) (match_dup 2))
8126 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8130 ;; For SI, we special-case integers that can't be loaded in one insn. We
8131 ;; do the load 16-bits at a time. We could do this by loading from memory,
8132 ;; and this is even supposed to be faster, but it is simpler not to get
8133 ;; integers in the TOC.
8134 (define_insn "movsi_low"
8135 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8136 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
8137 (match_operand 2 "" ""))))]
8138 "TARGET_MACHO && ! TARGET_64BIT"
8139 "{l|lwz} %0,lo16(%2)(%1)"
8140 [(set_attr "type" "load")
8141 (set_attr "length" "4")])
8143 (define_insn "*movsi_internal1"
8144 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
8145 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
8146 "!TARGET_SINGLE_FPU &&
8147 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8151 {l%U1%X1|lwz%U1%X1} %0,%1
8152 {st%U0%X0|stw%U0%X0} %1,%0
8162 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
8163 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
8165 (define_insn "*movsi_internal1_single"
8166 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h,m,*f")
8167 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0,f,m"))]
8168 "TARGET_SINGLE_FPU &&
8169 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8173 {l%U1%X1|lwz%U1%X1} %0,%1
8174 {st%U0%X0|stw%U0%X0} %1,%0
8186 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*,*,*")
8187 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4,4,4")])
8189 ;; Split a load of a large constant into the appropriate two-insn
8193 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8194 (match_operand:SI 1 "const_int_operand" ""))]
8195 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
8196 && (INTVAL (operands[1]) & 0xffff) != 0"
8200 (ior:SI (match_dup 0)
8203 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8205 if (tem == operands[0])
8211 (define_insn "*mov<mode>_internal2"
8212 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8213 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
8215 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8218 {cmpi|cmp<wd>i} %2,%0,0
8221 [(set_attr "type" "cmp,compare,cmp")
8222 (set_attr "length" "4,4,8")])
8225 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
8226 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
8228 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8230 [(set (match_dup 0) (match_dup 1))
8232 (compare:CC (match_dup 0)
8236 (define_insn "*movhi_internal"
8237 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8238 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8239 "gpc_reg_operand (operands[0], HImode)
8240 || gpc_reg_operand (operands[1], HImode)"
8250 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8252 (define_expand "mov<mode>"
8253 [(set (match_operand:INT 0 "general_operand" "")
8254 (match_operand:INT 1 "any_operand" ""))]
8256 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8258 (define_insn "*movqi_internal"
8259 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8260 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8261 "gpc_reg_operand (operands[0], QImode)
8262 || gpc_reg_operand (operands[1], QImode)"
8272 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8274 ;; Here is how to move condition codes around. When we store CC data in
8275 ;; an integer register or memory, we store just the high-order 4 bits.
8276 ;; This lets us not shift in the most common case of CR0.
8277 (define_expand "movcc"
8278 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8279 (match_operand:CC 1 "nonimmediate_operand" ""))]
8283 (define_insn "*movcc_internal1"
8284 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
8285 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
8286 "register_operand (operands[0], CCmode)
8287 || register_operand (operands[1], CCmode)"
8291 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
8294 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
8300 {l%U1%X1|lwz%U1%X1} %0,%1
8301 {st%U0%U1|stw%U0%U1} %1,%0"
8303 (cond [(eq_attr "alternative" "0,3")
8304 (const_string "cr_logical")
8305 (eq_attr "alternative" "1,2")
8306 (const_string "mtcr")
8307 (eq_attr "alternative" "6,7,9")
8308 (const_string "integer")
8309 (eq_attr "alternative" "8")
8310 (const_string "mfjmpr")
8311 (eq_attr "alternative" "10")
8312 (const_string "mtjmpr")
8313 (eq_attr "alternative" "11")
8314 (const_string "load")
8315 (eq_attr "alternative" "12")
8316 (const_string "store")
8317 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
8318 (const_string "mfcrf")
8320 (const_string "mfcr")))
8321 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
8323 ;; For floating-point, we normally deal with the floating-point registers
8324 ;; unless -msoft-float is used. The sole exception is that parameter passing
8325 ;; can produce floating-point values in fixed-point registers. Unless the
8326 ;; value is a simple constant or already in memory, we deal with this by
8327 ;; allocating memory and copying the value explicitly via that memory location.
8328 (define_expand "movsf"
8329 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8330 (match_operand:SF 1 "any_operand" ""))]
8332 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
8335 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8336 (match_operand:SF 1 "const_double_operand" ""))]
8338 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8339 || (GET_CODE (operands[0]) == SUBREG
8340 && GET_CODE (SUBREG_REG (operands[0])) == REG
8341 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8342 [(set (match_dup 2) (match_dup 3))]
8348 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8349 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
8351 if (! TARGET_POWERPC64)
8352 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
8354 operands[2] = gen_lowpart (SImode, operands[0]);
8356 operands[3] = gen_int_mode (l, SImode);
8359 (define_insn "*movsf_hardfloat"
8360 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
8361 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
8362 "(gpc_reg_operand (operands[0], SFmode)
8363 || gpc_reg_operand (operands[1], SFmode))
8364 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
8367 {l%U1%X1|lwz%U1%X1} %0,%1
8368 {st%U0%X0|stw%U0%X0} %1,%0
8378 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
8379 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
8381 (define_insn "*movsf_softfloat"
8382 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
8383 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
8384 "(gpc_reg_operand (operands[0], SFmode)
8385 || gpc_reg_operand (operands[1], SFmode))
8386 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
8392 {l%U1%X1|lwz%U1%X1} %0,%1
8393 {st%U0%X0|stw%U0%X0} %1,%0
8400 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
8401 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
8404 (define_expand "movdf"
8405 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8406 (match_operand:DF 1 "any_operand" ""))]
8408 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
8411 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8412 (match_operand:DF 1 "const_int_operand" ""))]
8413 "! TARGET_POWERPC64 && reload_completed
8414 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8415 || (GET_CODE (operands[0]) == SUBREG
8416 && GET_CODE (SUBREG_REG (operands[0])) == REG
8417 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8418 [(set (match_dup 2) (match_dup 4))
8419 (set (match_dup 3) (match_dup 1))]
8422 int endian = (WORDS_BIG_ENDIAN == 0);
8423 HOST_WIDE_INT value = INTVAL (operands[1]);
8425 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8426 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8427 #if HOST_BITS_PER_WIDE_INT == 32
8428 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8430 operands[4] = GEN_INT (value >> 32);
8431 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8436 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8437 (match_operand:DF 1 "const_double_operand" ""))]
8438 "! TARGET_POWERPC64 && reload_completed
8439 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8440 || (GET_CODE (operands[0]) == SUBREG
8441 && GET_CODE (SUBREG_REG (operands[0])) == REG
8442 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8443 [(set (match_dup 2) (match_dup 4))
8444 (set (match_dup 3) (match_dup 5))]
8447 int endian = (WORDS_BIG_ENDIAN == 0);
8451 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8452 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8454 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8455 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8456 operands[4] = gen_int_mode (l[endian], SImode);
8457 operands[5] = gen_int_mode (l[1 - endian], SImode);
8461 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8462 (match_operand:DF 1 "const_double_operand" ""))]
8463 "TARGET_POWERPC64 && reload_completed
8464 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8465 || (GET_CODE (operands[0]) == SUBREG
8466 && GET_CODE (SUBREG_REG (operands[0])) == REG
8467 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8468 [(set (match_dup 2) (match_dup 3))]
8471 int endian = (WORDS_BIG_ENDIAN == 0);
8474 #if HOST_BITS_PER_WIDE_INT >= 64
8478 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8479 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8481 operands[2] = gen_lowpart (DImode, operands[0]);
8482 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8483 #if HOST_BITS_PER_WIDE_INT >= 64
8484 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8485 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8487 operands[3] = gen_int_mode (val, DImode);
8489 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8493 ;; Don't have reload use general registers to load a constant. First,
8494 ;; it might not work if the output operand is the equivalent of
8495 ;; a non-offsettable memref, but also it is less efficient than loading
8496 ;; the constant into an FP register, since it will probably be used there.
8497 ;; The "??" is a kludge until we can figure out a more reasonable way
8498 ;; of handling these non-offsettable values.
8499 (define_insn "*movdf_hardfloat32"
8500 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8501 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
8502 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8503 && (gpc_reg_operand (operands[0], DFmode)
8504 || gpc_reg_operand (operands[1], DFmode))"
8507 switch (which_alternative)
8512 /* We normally copy the low-numbered register first. However, if
8513 the first register operand 0 is the same as the second register
8514 of operand 1, we must copy in the opposite order. */
8515 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8516 return \"mr %L0,%L1\;mr %0,%1\";
8518 return \"mr %0,%1\;mr %L0,%L1\";
8520 if (rs6000_offsettable_memref_p (operands[1])
8521 || (GET_CODE (operands[1]) == MEM
8522 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8523 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8524 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC
8525 || GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)))
8527 /* If the low-address word is used in the address, we must load
8528 it last. Otherwise, load it first. Note that we cannot have
8529 auto-increment in that case since the address register is
8530 known to be dead. */
8531 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8533 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8535 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
8541 addreg = find_addr_reg (XEXP (operands[1], 0));
8542 if (refers_to_regno_p (REGNO (operands[0]),
8543 REGNO (operands[0]) + 1,
8546 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8547 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
8548 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8549 return \"{l%X1|lwz%X1} %0,%1\";
8553 output_asm_insn (\"{l%X1|lwz%X1} %0,%1\", operands);
8554 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8555 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
8556 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8561 if (rs6000_offsettable_memref_p (operands[0])
8562 || (GET_CODE (operands[0]) == MEM
8563 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8564 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8565 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
8566 || GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)))
8567 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
8572 addreg = find_addr_reg (XEXP (operands[0], 0));
8573 output_asm_insn (\"{st%X0|stw%X0} %1,%0\", operands);
8574 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8575 output_asm_insn (\"{st%X0|stw%X0} %L1,%0\", operands);
8576 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8580 return \"fmr %0,%1\";
8582 return \"lfd%U1%X1 %0,%1\";
8584 return \"stfd%U0%X0 %1,%0\";
8591 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
8592 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
8594 (define_insn "*movdf_softfloat32"
8595 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8596 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8598 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
8599 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8600 && (gpc_reg_operand (operands[0], DFmode)
8601 || gpc_reg_operand (operands[1], DFmode))"
8604 switch (which_alternative)
8609 /* We normally copy the low-numbered register first. However, if
8610 the first register operand 0 is the same as the second register of
8611 operand 1, we must copy in the opposite order. */
8612 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8613 return \"mr %L0,%L1\;mr %0,%1\";
8615 return \"mr %0,%1\;mr %L0,%L1\";
8617 /* If the low-address word is used in the address, we must load
8618 it last. Otherwise, load it first. Note that we cannot have
8619 auto-increment in that case since the address register is
8620 known to be dead. */
8621 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8623 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8625 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
8627 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
8634 [(set_attr "type" "two,load,store,*,*,*")
8635 (set_attr "length" "8,8,8,8,12,16")])
8637 ; ld/std require word-aligned displacements -> 'Y' constraint.
8638 ; List Y->r and r->Y before r->r for reload.
8639 (define_insn "*movdf_hardfloat64_mfpgpr"
8640 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f")
8641 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))]
8642 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8643 && TARGET_DOUBLE_FLOAT
8644 && (gpc_reg_operand (operands[0], DFmode)
8645 || gpc_reg_operand (operands[1], DFmode))"
8661 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
8662 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
8664 ; ld/std require word-aligned displacements -> 'Y' constraint.
8665 ; List Y->r and r->Y before r->r for reload.
8666 (define_insn "*movdf_hardfloat64"
8667 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
8668 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
8669 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8670 && TARGET_DOUBLE_FLOAT
8671 && (gpc_reg_operand (operands[0], DFmode)
8672 || gpc_reg_operand (operands[1], DFmode))"
8686 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
8687 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
8689 (define_insn "*movdf_softfloat64"
8690 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8691 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
8692 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8693 && (gpc_reg_operand (operands[0], DFmode)
8694 || gpc_reg_operand (operands[1], DFmode))"
8705 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
8706 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8708 (define_expand "movtf"
8709 [(set (match_operand:TF 0 "general_operand" "")
8710 (match_operand:TF 1 "any_operand" ""))]
8711 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
8712 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8714 ; It's important to list the o->f and f->o moves before f->f because
8715 ; otherwise reload, given m->f, will try to pick f->f and reload it,
8716 ; which doesn't make progress. Likewise r->Y must be before r->r.
8717 (define_insn_and_split "*movtf_internal"
8718 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
8719 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
8721 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8722 && (gpc_reg_operand (operands[0], TFmode)
8723 || gpc_reg_operand (operands[1], TFmode))"
8725 "&& reload_completed"
8727 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8728 [(set_attr "length" "8,8,8,20,20,16")])
8730 (define_insn_and_split "*movtf_softfloat"
8731 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
8732 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
8734 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
8735 && (gpc_reg_operand (operands[0], TFmode)
8736 || gpc_reg_operand (operands[1], TFmode))"
8738 "&& reload_completed"
8740 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8741 [(set_attr "length" "20,20,16")])
8743 (define_expand "extenddftf2"
8744 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8745 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8747 && TARGET_HARD_FLOAT
8748 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8749 && TARGET_LONG_DOUBLE_128"
8751 if (TARGET_E500_DOUBLE)
8752 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8754 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8758 (define_expand "extenddftf2_fprs"
8759 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8760 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8761 (use (match_dup 2))])]
8763 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8764 && TARGET_LONG_DOUBLE_128"
8766 operands[2] = CONST0_RTX (DFmode);
8767 /* Generate GOT reference early for SVR4 PIC. */
8768 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8769 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8772 (define_insn_and_split "*extenddftf2_internal"
8773 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8774 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8775 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
8777 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8778 && TARGET_LONG_DOUBLE_128"
8780 "&& reload_completed"
8783 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8784 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8785 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8787 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8792 (define_expand "extendsftf2"
8793 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8794 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8796 && TARGET_HARD_FLOAT
8797 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8798 && TARGET_LONG_DOUBLE_128"
8800 rtx tmp = gen_reg_rtx (DFmode);
8801 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8802 emit_insn (gen_extenddftf2 (operands[0], tmp));
8806 (define_expand "trunctfdf2"
8807 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8808 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8810 && TARGET_HARD_FLOAT
8811 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8812 && TARGET_LONG_DOUBLE_128"
8815 (define_insn_and_split "trunctfdf2_internal1"
8816 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8817 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
8818 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8819 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8823 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8826 emit_note (NOTE_INSN_DELETED);
8829 [(set_attr "type" "fp")])
8831 (define_insn "trunctfdf2_internal2"
8832 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8833 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8834 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8835 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8836 && TARGET_LONG_DOUBLE_128"
8838 [(set_attr "type" "fp")
8839 (set_attr "fp_type" "fp_addsub_d")])
8841 (define_expand "trunctfsf2"
8842 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8843 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8845 && TARGET_HARD_FLOAT
8846 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8847 && TARGET_LONG_DOUBLE_128"
8849 if (TARGET_E500_DOUBLE)
8850 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8852 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8856 (define_insn_and_split "trunctfsf2_fprs"
8857 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8858 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8859 (clobber (match_scratch:DF 2 "=f"))]
8861 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
8862 && TARGET_LONG_DOUBLE_128"
8864 "&& reload_completed"
8866 (float_truncate:DF (match_dup 1)))
8868 (float_truncate:SF (match_dup 2)))]
8871 (define_expand "floatsitf2"
8872 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8873 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
8875 && TARGET_HARD_FLOAT
8876 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8877 && TARGET_LONG_DOUBLE_128"
8879 rtx tmp = gen_reg_rtx (DFmode);
8880 expand_float (tmp, operands[1], false);
8881 emit_insn (gen_extenddftf2 (operands[0], tmp));
8885 ; fadd, but rounding towards zero.
8886 ; This is probably not the optimal code sequence.
8887 (define_insn "fix_trunc_helper"
8888 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8889 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8890 UNSPEC_FIX_TRUNC_TF))
8891 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8892 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
8893 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8894 [(set_attr "type" "fp")
8895 (set_attr "length" "20")])
8897 (define_expand "fix_trunctfsi2"
8898 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8899 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8901 && (TARGET_POWER2 || TARGET_POWERPC)
8902 && TARGET_HARD_FLOAT
8903 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8904 && TARGET_LONG_DOUBLE_128"
8906 if (TARGET_E500_DOUBLE)
8907 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8909 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8913 (define_expand "fix_trunctfsi2_fprs"
8914 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8915 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8916 (clobber (match_dup 2))
8917 (clobber (match_dup 3))
8918 (clobber (match_dup 4))
8919 (clobber (match_dup 5))])]
8921 && (TARGET_POWER2 || TARGET_POWERPC)
8922 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8924 operands[2] = gen_reg_rtx (DFmode);
8925 operands[3] = gen_reg_rtx (DFmode);
8926 operands[4] = gen_reg_rtx (DImode);
8927 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8930 (define_insn_and_split "*fix_trunctfsi2_internal"
8931 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8932 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8933 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8934 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8935 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8936 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
8938 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8940 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[5]))"
8944 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8946 gcc_assert (MEM_P (operands[5]));
8947 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8949 emit_insn (gen_fctiwz (operands[4], operands[2]));
8950 emit_move_insn (operands[5], operands[4]);
8951 emit_move_insn (operands[0], lowword);
8955 (define_expand "negtf2"
8956 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8957 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8959 && TARGET_HARD_FLOAT
8960 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8961 && TARGET_LONG_DOUBLE_128"
8964 (define_insn "negtf2_internal"
8965 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8966 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8968 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8971 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8972 return \"fneg %L0,%L1\;fneg %0,%1\";
8974 return \"fneg %0,%1\;fneg %L0,%L1\";
8976 [(set_attr "type" "fp")
8977 (set_attr "length" "8")])
8979 (define_expand "abstf2"
8980 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8981 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8983 && TARGET_HARD_FLOAT
8984 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8985 && TARGET_LONG_DOUBLE_128"
8988 rtx label = gen_label_rtx ();
8989 if (TARGET_E500_DOUBLE)
8991 if (flag_finite_math_only && !flag_trapping_math)
8992 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
8994 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
8997 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
9002 (define_expand "abstf2_internal"
9003 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9004 (match_operand:TF 1 "gpc_reg_operand" ""))
9005 (set (match_dup 3) (match_dup 5))
9006 (set (match_dup 5) (abs:DF (match_dup 5)))
9007 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
9008 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
9009 (label_ref (match_operand 2 "" ""))
9011 (set (match_dup 6) (neg:DF (match_dup 6)))]
9013 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9014 && TARGET_LONG_DOUBLE_128"
9017 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9018 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9019 operands[3] = gen_reg_rtx (DFmode);
9020 operands[4] = gen_reg_rtx (CCFPmode);
9021 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
9022 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
9025 ;; Next come the multi-word integer load and store and the load and store
9028 ; List r->r after r->"o<>", otherwise reload will try to reload a
9029 ; non-offsettable address by using r->r which won't make progress.
9030 (define_insn "*movdi_internal32"
9031 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
9032 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
9034 && (gpc_reg_operand (operands[0], DImode)
9035 || gpc_reg_operand (operands[1], DImode))"
9044 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
9047 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9048 (match_operand:DI 1 "const_int_operand" ""))]
9049 "! TARGET_POWERPC64 && reload_completed"
9050 [(set (match_dup 2) (match_dup 4))
9051 (set (match_dup 3) (match_dup 1))]
9054 HOST_WIDE_INT value = INTVAL (operands[1]);
9055 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9057 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9059 #if HOST_BITS_PER_WIDE_INT == 32
9060 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
9062 operands[4] = GEN_INT (value >> 32);
9063 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9068 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "")
9069 (match_operand:DI 1 "input_operand" ""))]
9070 "reload_completed && !TARGET_POWERPC64
9071 && gpr_or_gpr_p (operands[0], operands[1])"
9073 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9075 (define_insn "*movdi_mfpgpr"
9076 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h,r,*f")
9077 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0,*f,r"))]
9078 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9079 && (gpc_reg_operand (operands[0], DImode)
9080 || gpc_reg_operand (operands[1], DImode))"
9097 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
9098 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
9100 (define_insn "*movdi_internal64"
9101 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
9102 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
9103 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
9104 && (gpc_reg_operand (operands[0], DImode)
9105 || gpc_reg_operand (operands[1], DImode))"
9120 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
9121 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
9123 ;; immediate value valid for a single instruction hiding in a const_double
9125 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9126 (match_operand:DI 1 "const_double_operand" "F"))]
9127 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
9128 && GET_CODE (operands[1]) == CONST_DOUBLE
9129 && num_insns_constant (operands[1], DImode) == 1"
9132 return ((unsigned HOST_WIDE_INT)
9133 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
9134 ? \"li %0,%1\" : \"lis %0,%v1\";
9137 ;; Generate all one-bits and clear left or right.
9138 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9140 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9141 (match_operand:DI 1 "mask64_operand" ""))]
9142 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9143 [(set (match_dup 0) (const_int -1))
9145 (and:DI (rotate:DI (match_dup 0)
9150 ;; Split a load of a large constant into the appropriate five-instruction
9151 ;; sequence. Handle anything in a constant number of insns.
9152 ;; When non-easy constants can go in the TOC, this should use
9153 ;; easy_fp_constant predicate.
9155 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9156 (match_operand:DI 1 "const_int_operand" ""))]
9157 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9158 [(set (match_dup 0) (match_dup 2))
9159 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9161 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9163 if (tem == operands[0])
9170 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9171 (match_operand:DI 1 "const_double_operand" ""))]
9172 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9173 [(set (match_dup 0) (match_dup 2))
9174 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9176 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9178 if (tem == operands[0])
9184 ;; TImode is similar, except that we usually want to compute the address into
9185 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
9186 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
9188 ;; We say that MQ is clobbered in the last alternative because the first
9189 ;; alternative would never get used otherwise since it would need a reload
9190 ;; while the 2nd alternative would not. We put memory cases first so they
9191 ;; are preferred. Otherwise, we'd try to reload the output instead of
9192 ;; giving the SCRATCH mq.
9194 (define_insn "*movti_power"
9195 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
9196 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
9197 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
9198 "TARGET_POWER && ! TARGET_POWERPC64
9199 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9202 switch (which_alternative)
9209 return \"{stsi|stswi} %1,%P0,16\";
9214 /* If the address is not used in the output, we can use lsi. Otherwise,
9215 fall through to generating four loads. */
9217 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9218 return \"{lsi|lswi} %0,%P1,16\";
9219 /* ... fall through ... */
9225 [(set_attr "type" "store,store,*,load,load,*")])
9227 (define_insn "*movti_string"
9228 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
9229 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
9230 "! TARGET_POWER && ! TARGET_POWERPC64
9231 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9234 switch (which_alternative)
9240 return \"{stsi|stswi} %1,%P0,16\";
9245 /* If the address is not used in the output, we can use lsi. Otherwise,
9246 fall through to generating four loads. */
9248 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9249 return \"{lsi|lswi} %0,%P1,16\";
9250 /* ... fall through ... */
9256 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")
9257 (set (attr "cell_micro") (if_then_else (eq (symbol_ref "TARGET_STRING") (const_int 1))
9258 (const_string "always")
9259 (const_string "conditional")))])
9261 (define_insn "*movti_ppc64"
9262 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
9263 (match_operand:TI 1 "input_operand" "r,r,m"))]
9264 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
9265 || gpc_reg_operand (operands[1], TImode))"
9267 [(set_attr "type" "*,store,load")])
9270 [(set (match_operand:TI 0 "gpc_reg_operand" "")
9271 (match_operand:TI 1 "const_double_operand" ""))]
9273 [(set (match_dup 2) (match_dup 4))
9274 (set (match_dup 3) (match_dup 5))]
9277 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9279 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9281 if (GET_CODE (operands[1]) == CONST_DOUBLE)
9283 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9284 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9286 else if (GET_CODE (operands[1]) == CONST_INT)
9288 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9289 operands[5] = operands[1];
9296 [(set (match_operand:TI 0 "nonimmediate_operand" "")
9297 (match_operand:TI 1 "input_operand" ""))]
9299 && gpr_or_gpr_p (operands[0], operands[1])"
9301 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9303 (define_expand "load_multiple"
9304 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9305 (match_operand:SI 1 "" ""))
9306 (use (match_operand:SI 2 "" ""))])]
9307 "TARGET_STRING && !TARGET_POWERPC64"
9315 /* Support only loading a constant number of fixed-point registers from
9316 memory and only bother with this if more than two; the machine
9317 doesn't support more than eight. */
9318 if (GET_CODE (operands[2]) != CONST_INT
9319 || INTVAL (operands[2]) <= 2
9320 || INTVAL (operands[2]) > 8
9321 || GET_CODE (operands[1]) != MEM
9322 || GET_CODE (operands[0]) != REG
9323 || REGNO (operands[0]) >= 32)
9326 count = INTVAL (operands[2]);
9327 regno = REGNO (operands[0]);
9329 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9330 op1 = replace_equiv_address (operands[1],
9331 force_reg (SImode, XEXP (operands[1], 0)));
9333 for (i = 0; i < count; i++)
9334 XVECEXP (operands[3], 0, i)
9335 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
9336 adjust_address_nv (op1, SImode, i * 4));
9339 (define_insn "*ldmsi8"
9340 [(match_parallel 0 "load_multiple_operation"
9341 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9342 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9343 (set (match_operand:SI 3 "gpc_reg_operand" "")
9344 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9345 (set (match_operand:SI 4 "gpc_reg_operand" "")
9346 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9347 (set (match_operand:SI 5 "gpc_reg_operand" "")
9348 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9349 (set (match_operand:SI 6 "gpc_reg_operand" "")
9350 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9351 (set (match_operand:SI 7 "gpc_reg_operand" "")
9352 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9353 (set (match_operand:SI 8 "gpc_reg_operand" "")
9354 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9355 (set (match_operand:SI 9 "gpc_reg_operand" "")
9356 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9357 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9359 { return rs6000_output_load_multiple (operands); }"
9360 [(set_attr "type" "load_ux")
9361 (set_attr "length" "32")])
9363 (define_insn "*ldmsi7"
9364 [(match_parallel 0 "load_multiple_operation"
9365 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9366 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9367 (set (match_operand:SI 3 "gpc_reg_operand" "")
9368 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9369 (set (match_operand:SI 4 "gpc_reg_operand" "")
9370 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9371 (set (match_operand:SI 5 "gpc_reg_operand" "")
9372 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9373 (set (match_operand:SI 6 "gpc_reg_operand" "")
9374 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9375 (set (match_operand:SI 7 "gpc_reg_operand" "")
9376 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9377 (set (match_operand:SI 8 "gpc_reg_operand" "")
9378 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9379 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9381 { return rs6000_output_load_multiple (operands); }"
9382 [(set_attr "type" "load_ux")
9383 (set_attr "length" "32")])
9385 (define_insn "*ldmsi6"
9386 [(match_parallel 0 "load_multiple_operation"
9387 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9388 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9389 (set (match_operand:SI 3 "gpc_reg_operand" "")
9390 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9391 (set (match_operand:SI 4 "gpc_reg_operand" "")
9392 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9393 (set (match_operand:SI 5 "gpc_reg_operand" "")
9394 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9395 (set (match_operand:SI 6 "gpc_reg_operand" "")
9396 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9397 (set (match_operand:SI 7 "gpc_reg_operand" "")
9398 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9399 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9401 { return rs6000_output_load_multiple (operands); }"
9402 [(set_attr "type" "load_ux")
9403 (set_attr "length" "32")])
9405 (define_insn "*ldmsi5"
9406 [(match_parallel 0 "load_multiple_operation"
9407 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9408 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9409 (set (match_operand:SI 3 "gpc_reg_operand" "")
9410 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9411 (set (match_operand:SI 4 "gpc_reg_operand" "")
9412 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9413 (set (match_operand:SI 5 "gpc_reg_operand" "")
9414 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9415 (set (match_operand:SI 6 "gpc_reg_operand" "")
9416 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9417 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9419 { return rs6000_output_load_multiple (operands); }"
9420 [(set_attr "type" "load_ux")
9421 (set_attr "length" "32")])
9423 (define_insn "*ldmsi4"
9424 [(match_parallel 0 "load_multiple_operation"
9425 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9426 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9427 (set (match_operand:SI 3 "gpc_reg_operand" "")
9428 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9429 (set (match_operand:SI 4 "gpc_reg_operand" "")
9430 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9431 (set (match_operand:SI 5 "gpc_reg_operand" "")
9432 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9433 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9435 { return rs6000_output_load_multiple (operands); }"
9436 [(set_attr "type" "load_ux")
9437 (set_attr "length" "32")])
9439 (define_insn "*ldmsi3"
9440 [(match_parallel 0 "load_multiple_operation"
9441 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9442 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9443 (set (match_operand:SI 3 "gpc_reg_operand" "")
9444 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9445 (set (match_operand:SI 4 "gpc_reg_operand" "")
9446 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9447 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9449 { return rs6000_output_load_multiple (operands); }"
9450 [(set_attr "type" "load_ux")
9451 (set_attr "length" "32")])
9453 (define_expand "store_multiple"
9454 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9455 (match_operand:SI 1 "" ""))
9456 (clobber (scratch:SI))
9457 (use (match_operand:SI 2 "" ""))])]
9458 "TARGET_STRING && !TARGET_POWERPC64"
9467 /* Support only storing a constant number of fixed-point registers to
9468 memory and only bother with this if more than two; the machine
9469 doesn't support more than eight. */
9470 if (GET_CODE (operands[2]) != CONST_INT
9471 || INTVAL (operands[2]) <= 2
9472 || INTVAL (operands[2]) > 8
9473 || GET_CODE (operands[0]) != MEM
9474 || GET_CODE (operands[1]) != REG
9475 || REGNO (operands[1]) >= 32)
9478 count = INTVAL (operands[2]);
9479 regno = REGNO (operands[1]);
9481 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
9482 to = force_reg (SImode, XEXP (operands[0], 0));
9483 op0 = replace_equiv_address (operands[0], to);
9485 XVECEXP (operands[3], 0, 0)
9486 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
9487 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
9488 gen_rtx_SCRATCH (SImode));
9490 for (i = 1; i < count; i++)
9491 XVECEXP (operands[3], 0, i + 1)
9492 = gen_rtx_SET (VOIDmode,
9493 adjust_address_nv (op0, SImode, i * 4),
9494 gen_rtx_REG (SImode, regno + i));
9497 (define_insn "*stmsi8"
9498 [(match_parallel 0 "store_multiple_operation"
9499 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9500 (match_operand:SI 2 "gpc_reg_operand" "r"))
9501 (clobber (match_scratch:SI 3 "=X"))
9502 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9503 (match_operand:SI 4 "gpc_reg_operand" "r"))
9504 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9505 (match_operand:SI 5 "gpc_reg_operand" "r"))
9506 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9507 (match_operand:SI 6 "gpc_reg_operand" "r"))
9508 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9509 (match_operand:SI 7 "gpc_reg_operand" "r"))
9510 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9511 (match_operand:SI 8 "gpc_reg_operand" "r"))
9512 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9513 (match_operand:SI 9 "gpc_reg_operand" "r"))
9514 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9515 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9516 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9517 "{stsi|stswi} %2,%1,%O0"
9518 [(set_attr "type" "store_ux")
9519 (set_attr "cell_micro" "always")])
9521 (define_insn "*stmsi7"
9522 [(match_parallel 0 "store_multiple_operation"
9523 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9524 (match_operand:SI 2 "gpc_reg_operand" "r"))
9525 (clobber (match_scratch:SI 3 "=X"))
9526 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9527 (match_operand:SI 4 "gpc_reg_operand" "r"))
9528 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9529 (match_operand:SI 5 "gpc_reg_operand" "r"))
9530 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9531 (match_operand:SI 6 "gpc_reg_operand" "r"))
9532 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9533 (match_operand:SI 7 "gpc_reg_operand" "r"))
9534 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9535 (match_operand:SI 8 "gpc_reg_operand" "r"))
9536 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9537 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9538 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9539 "{stsi|stswi} %2,%1,%O0"
9540 [(set_attr "type" "store_ux")
9541 (set_attr "cell_micro" "always")])
9543 (define_insn "*stmsi6"
9544 [(match_parallel 0 "store_multiple_operation"
9545 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9546 (match_operand:SI 2 "gpc_reg_operand" "r"))
9547 (clobber (match_scratch:SI 3 "=X"))
9548 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9549 (match_operand:SI 4 "gpc_reg_operand" "r"))
9550 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9551 (match_operand:SI 5 "gpc_reg_operand" "r"))
9552 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9553 (match_operand:SI 6 "gpc_reg_operand" "r"))
9554 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9555 (match_operand:SI 7 "gpc_reg_operand" "r"))
9556 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9557 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9558 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9559 "{stsi|stswi} %2,%1,%O0"
9560 [(set_attr "type" "store_ux")
9561 (set_attr "cell_micro" "always")])
9563 (define_insn "*stmsi5"
9564 [(match_parallel 0 "store_multiple_operation"
9565 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9566 (match_operand:SI 2 "gpc_reg_operand" "r"))
9567 (clobber (match_scratch:SI 3 "=X"))
9568 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9569 (match_operand:SI 4 "gpc_reg_operand" "r"))
9570 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9571 (match_operand:SI 5 "gpc_reg_operand" "r"))
9572 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9573 (match_operand:SI 6 "gpc_reg_operand" "r"))
9574 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9575 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9576 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9577 "{stsi|stswi} %2,%1,%O0"
9578 [(set_attr "type" "store_ux")
9579 (set_attr "cell_micro" "always")])
9581 (define_insn "*stmsi4"
9582 [(match_parallel 0 "store_multiple_operation"
9583 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9584 (match_operand:SI 2 "gpc_reg_operand" "r"))
9585 (clobber (match_scratch:SI 3 "=X"))
9586 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9587 (match_operand:SI 4 "gpc_reg_operand" "r"))
9588 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9589 (match_operand:SI 5 "gpc_reg_operand" "r"))
9590 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9591 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9592 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9593 "{stsi|stswi} %2,%1,%O0"
9594 [(set_attr "type" "store_ux")
9595 (set_attr "cell_micro" "always")])
9597 (define_insn "*stmsi3"
9598 [(match_parallel 0 "store_multiple_operation"
9599 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9600 (match_operand:SI 2 "gpc_reg_operand" "r"))
9601 (clobber (match_scratch:SI 3 "=X"))
9602 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9603 (match_operand:SI 4 "gpc_reg_operand" "r"))
9604 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9605 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9606 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9607 "{stsi|stswi} %2,%1,%O0"
9608 [(set_attr "type" "store_ux")
9609 (set_attr "cell_micro" "always")])
9611 (define_insn "*stmsi8_power"
9612 [(match_parallel 0 "store_multiple_operation"
9613 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9614 (match_operand:SI 2 "gpc_reg_operand" "r"))
9615 (clobber (match_scratch:SI 3 "=q"))
9616 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9617 (match_operand:SI 4 "gpc_reg_operand" "r"))
9618 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9619 (match_operand:SI 5 "gpc_reg_operand" "r"))
9620 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9621 (match_operand:SI 6 "gpc_reg_operand" "r"))
9622 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9623 (match_operand:SI 7 "gpc_reg_operand" "r"))
9624 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9625 (match_operand:SI 8 "gpc_reg_operand" "r"))
9626 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9627 (match_operand:SI 9 "gpc_reg_operand" "r"))
9628 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9629 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9630 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9631 "{stsi|stswi} %2,%1,%O0"
9632 [(set_attr "type" "store_ux")
9633 (set_attr "cell_micro" "always")])
9635 (define_insn "*stmsi7_power"
9636 [(match_parallel 0 "store_multiple_operation"
9637 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9638 (match_operand:SI 2 "gpc_reg_operand" "r"))
9639 (clobber (match_scratch:SI 3 "=q"))
9640 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9641 (match_operand:SI 4 "gpc_reg_operand" "r"))
9642 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9643 (match_operand:SI 5 "gpc_reg_operand" "r"))
9644 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9645 (match_operand:SI 6 "gpc_reg_operand" "r"))
9646 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9647 (match_operand:SI 7 "gpc_reg_operand" "r"))
9648 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9649 (match_operand:SI 8 "gpc_reg_operand" "r"))
9650 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9651 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9652 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9653 "{stsi|stswi} %2,%1,%O0"
9654 [(set_attr "type" "store_ux")
9655 (set_attr "cell_micro" "always")])
9657 (define_insn "*stmsi6_power"
9658 [(match_parallel 0 "store_multiple_operation"
9659 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9660 (match_operand:SI 2 "gpc_reg_operand" "r"))
9661 (clobber (match_scratch:SI 3 "=q"))
9662 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9663 (match_operand:SI 4 "gpc_reg_operand" "r"))
9664 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9665 (match_operand:SI 5 "gpc_reg_operand" "r"))
9666 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9667 (match_operand:SI 6 "gpc_reg_operand" "r"))
9668 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9669 (match_operand:SI 7 "gpc_reg_operand" "r"))
9670 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9671 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9672 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9673 "{stsi|stswi} %2,%1,%O0"
9674 [(set_attr "type" "store_ux")
9675 (set_attr "cell_micro" "always")])
9677 (define_insn "*stmsi5_power"
9678 [(match_parallel 0 "store_multiple_operation"
9679 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9680 (match_operand:SI 2 "gpc_reg_operand" "r"))
9681 (clobber (match_scratch:SI 3 "=q"))
9682 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9683 (match_operand:SI 4 "gpc_reg_operand" "r"))
9684 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9685 (match_operand:SI 5 "gpc_reg_operand" "r"))
9686 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9687 (match_operand:SI 6 "gpc_reg_operand" "r"))
9688 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9689 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9690 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9691 "{stsi|stswi} %2,%1,%O0"
9692 [(set_attr "type" "store_ux")
9693 (set_attr "cell_micro" "always")])
9695 (define_insn "*stmsi4_power"
9696 [(match_parallel 0 "store_multiple_operation"
9697 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9698 (match_operand:SI 2 "gpc_reg_operand" "r"))
9699 (clobber (match_scratch:SI 3 "=q"))
9700 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9701 (match_operand:SI 4 "gpc_reg_operand" "r"))
9702 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9703 (match_operand:SI 5 "gpc_reg_operand" "r"))
9704 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9705 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9706 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9707 "{stsi|stswi} %2,%1,%O0"
9708 [(set_attr "type" "store_ux")
9709 (set_attr "cell_micro" "always")])
9711 (define_insn "*stmsi3_power"
9712 [(match_parallel 0 "store_multiple_operation"
9713 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9714 (match_operand:SI 2 "gpc_reg_operand" "r"))
9715 (clobber (match_scratch:SI 3 "=q"))
9716 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9717 (match_operand:SI 4 "gpc_reg_operand" "r"))
9718 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9719 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9720 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9721 "{stsi|stswi} %2,%1,%O0"
9722 [(set_attr "type" "store_ux")
9723 (set_attr "cell_micro" "always")])
9725 (define_expand "setmemsi"
9726 [(parallel [(set (match_operand:BLK 0 "" "")
9727 (match_operand 2 "const_int_operand" ""))
9728 (use (match_operand:SI 1 "" ""))
9729 (use (match_operand:SI 3 "" ""))])]
9733 /* If value to set is not zero, use the library routine. */
9734 if (operands[2] != const0_rtx)
9737 if (expand_block_clear (operands))
9743 ;; String/block move insn.
9744 ;; Argument 0 is the destination
9745 ;; Argument 1 is the source
9746 ;; Argument 2 is the length
9747 ;; Argument 3 is the alignment
9749 (define_expand "movmemsi"
9750 [(parallel [(set (match_operand:BLK 0 "" "")
9751 (match_operand:BLK 1 "" ""))
9752 (use (match_operand:SI 2 "" ""))
9753 (use (match_operand:SI 3 "" ""))])]
9757 if (expand_block_move (operands))
9763 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9764 ;; register allocator doesn't have a clue about allocating 8 word registers.
9765 ;; rD/rS = r5 is preferred, efficient form.
9766 (define_expand "movmemsi_8reg"
9767 [(parallel [(set (match_operand 0 "" "")
9768 (match_operand 1 "" ""))
9769 (use (match_operand 2 "" ""))
9770 (use (match_operand 3 "" ""))
9771 (clobber (reg:SI 5))
9772 (clobber (reg:SI 6))
9773 (clobber (reg:SI 7))
9774 (clobber (reg:SI 8))
9775 (clobber (reg:SI 9))
9776 (clobber (reg:SI 10))
9777 (clobber (reg:SI 11))
9778 (clobber (reg:SI 12))
9779 (clobber (match_scratch:SI 4 ""))])]
9784 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9785 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9786 (use (match_operand:SI 2 "immediate_operand" "i"))
9787 (use (match_operand:SI 3 "immediate_operand" "i"))
9788 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9789 (clobber (reg:SI 6))
9790 (clobber (reg:SI 7))
9791 (clobber (reg:SI 8))
9792 (clobber (reg:SI 9))
9793 (clobber (reg:SI 10))
9794 (clobber (reg:SI 11))
9795 (clobber (reg:SI 12))
9796 (clobber (match_scratch:SI 5 "=q"))]
9797 "TARGET_STRING && TARGET_POWER
9798 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9799 || INTVAL (operands[2]) == 0)
9800 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9801 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9802 && REGNO (operands[4]) == 5"
9803 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9804 [(set_attr "type" "store_ux")
9805 (set_attr "cell_micro" "always")
9806 (set_attr "length" "8")])
9809 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9810 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9811 (use (match_operand:SI 2 "immediate_operand" "i"))
9812 (use (match_operand:SI 3 "immediate_operand" "i"))
9813 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9814 (clobber (reg:SI 6))
9815 (clobber (reg:SI 7))
9816 (clobber (reg:SI 8))
9817 (clobber (reg:SI 9))
9818 (clobber (reg:SI 10))
9819 (clobber (reg:SI 11))
9820 (clobber (reg:SI 12))
9821 (clobber (match_scratch:SI 5 "=X"))]
9822 "TARGET_STRING && ! TARGET_POWER
9823 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9824 || INTVAL (operands[2]) == 0)
9825 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9826 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9827 && REGNO (operands[4]) == 5"
9828 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9829 [(set_attr "type" "store_ux")
9830 (set_attr "cell_micro" "always")
9831 (set_attr "length" "8")])
9833 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9834 ;; register allocator doesn't have a clue about allocating 6 word registers.
9835 ;; rD/rS = r5 is preferred, efficient form.
9836 (define_expand "movmemsi_6reg"
9837 [(parallel [(set (match_operand 0 "" "")
9838 (match_operand 1 "" ""))
9839 (use (match_operand 2 "" ""))
9840 (use (match_operand 3 "" ""))
9841 (clobber (reg:SI 5))
9842 (clobber (reg:SI 6))
9843 (clobber (reg:SI 7))
9844 (clobber (reg:SI 8))
9845 (clobber (reg:SI 9))
9846 (clobber (reg:SI 10))
9847 (clobber (match_scratch:SI 4 ""))])]
9852 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9853 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9854 (use (match_operand:SI 2 "immediate_operand" "i"))
9855 (use (match_operand:SI 3 "immediate_operand" "i"))
9856 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9857 (clobber (reg:SI 6))
9858 (clobber (reg:SI 7))
9859 (clobber (reg:SI 8))
9860 (clobber (reg:SI 9))
9861 (clobber (reg:SI 10))
9862 (clobber (match_scratch:SI 5 "=q"))]
9863 "TARGET_STRING && TARGET_POWER
9864 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9865 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9866 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9867 && REGNO (operands[4]) == 5"
9868 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9869 [(set_attr "type" "store_ux")
9870 (set_attr "cell_micro" "always")
9871 (set_attr "length" "8")])
9874 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9875 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9876 (use (match_operand:SI 2 "immediate_operand" "i"))
9877 (use (match_operand:SI 3 "immediate_operand" "i"))
9878 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9879 (clobber (reg:SI 6))
9880 (clobber (reg:SI 7))
9881 (clobber (reg:SI 8))
9882 (clobber (reg:SI 9))
9883 (clobber (reg:SI 10))
9884 (clobber (match_scratch:SI 5 "=X"))]
9885 "TARGET_STRING && ! TARGET_POWER
9886 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9887 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9888 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9889 && REGNO (operands[4]) == 5"
9890 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9891 [(set_attr "type" "store_ux")
9892 (set_attr "cell_micro" "always")
9893 (set_attr "length" "8")])
9895 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9896 ;; problems with TImode.
9897 ;; rD/rS = r5 is preferred, efficient form.
9898 (define_expand "movmemsi_4reg"
9899 [(parallel [(set (match_operand 0 "" "")
9900 (match_operand 1 "" ""))
9901 (use (match_operand 2 "" ""))
9902 (use (match_operand 3 "" ""))
9903 (clobber (reg:SI 5))
9904 (clobber (reg:SI 6))
9905 (clobber (reg:SI 7))
9906 (clobber (reg:SI 8))
9907 (clobber (match_scratch:SI 4 ""))])]
9912 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9913 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9914 (use (match_operand:SI 2 "immediate_operand" "i"))
9915 (use (match_operand:SI 3 "immediate_operand" "i"))
9916 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9917 (clobber (reg:SI 6))
9918 (clobber (reg:SI 7))
9919 (clobber (reg:SI 8))
9920 (clobber (match_scratch:SI 5 "=q"))]
9921 "TARGET_STRING && TARGET_POWER
9922 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9923 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9924 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9925 && REGNO (operands[4]) == 5"
9926 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9927 [(set_attr "type" "store_ux")
9928 (set_attr "cell_micro" "always")
9929 (set_attr "length" "8")])
9932 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9933 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9934 (use (match_operand:SI 2 "immediate_operand" "i"))
9935 (use (match_operand:SI 3 "immediate_operand" "i"))
9936 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9937 (clobber (reg:SI 6))
9938 (clobber (reg:SI 7))
9939 (clobber (reg:SI 8))
9940 (clobber (match_scratch:SI 5 "=X"))]
9941 "TARGET_STRING && ! TARGET_POWER
9942 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9943 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9944 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9945 && REGNO (operands[4]) == 5"
9946 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9947 [(set_attr "type" "store_ux")
9948 (set_attr "cell_micro" "always")
9949 (set_attr "length" "8")])
9951 ;; Move up to 8 bytes at a time.
9952 (define_expand "movmemsi_2reg"
9953 [(parallel [(set (match_operand 0 "" "")
9954 (match_operand 1 "" ""))
9955 (use (match_operand 2 "" ""))
9956 (use (match_operand 3 "" ""))
9957 (clobber (match_scratch:DI 4 ""))
9958 (clobber (match_scratch:SI 5 ""))])]
9959 "TARGET_STRING && ! TARGET_POWERPC64"
9963 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9964 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9965 (use (match_operand:SI 2 "immediate_operand" "i"))
9966 (use (match_operand:SI 3 "immediate_operand" "i"))
9967 (clobber (match_scratch:DI 4 "=&r"))
9968 (clobber (match_scratch:SI 5 "=q"))]
9969 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9970 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9971 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9972 [(set_attr "type" "store_ux")
9973 (set_attr "cell_micro" "always")
9974 (set_attr "length" "8")])
9977 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9978 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9979 (use (match_operand:SI 2 "immediate_operand" "i"))
9980 (use (match_operand:SI 3 "immediate_operand" "i"))
9981 (clobber (match_scratch:DI 4 "=&r"))
9982 (clobber (match_scratch:SI 5 "=X"))]
9983 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9984 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9985 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9986 [(set_attr "type" "store_ux")
9987 (set_attr "cell_micro" "always")
9988 (set_attr "length" "8")])
9990 ;; Move up to 4 bytes at a time.
9991 (define_expand "movmemsi_1reg"
9992 [(parallel [(set (match_operand 0 "" "")
9993 (match_operand 1 "" ""))
9994 (use (match_operand 2 "" ""))
9995 (use (match_operand 3 "" ""))
9996 (clobber (match_scratch:SI 4 ""))
9997 (clobber (match_scratch:SI 5 ""))])]
10002 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10003 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10004 (use (match_operand:SI 2 "immediate_operand" "i"))
10005 (use (match_operand:SI 3 "immediate_operand" "i"))
10006 (clobber (match_scratch:SI 4 "=&r"))
10007 (clobber (match_scratch:SI 5 "=q"))]
10008 "TARGET_STRING && TARGET_POWER
10009 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
10010 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10011 [(set_attr "type" "store_ux")
10012 (set_attr "cell_micro" "always")
10013 (set_attr "length" "8")])
10016 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10017 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10018 (use (match_operand:SI 2 "immediate_operand" "i"))
10019 (use (match_operand:SI 3 "immediate_operand" "i"))
10020 (clobber (match_scratch:SI 4 "=&r"))
10021 (clobber (match_scratch:SI 5 "=X"))]
10022 "TARGET_STRING && ! TARGET_POWER
10023 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
10024 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10025 [(set_attr "type" "store_ux")
10026 (set_attr "cell_micro" "always")
10027 (set_attr "length" "8")])
10029 ;; Define insns that do load or store with update. Some of these we can
10030 ;; get by using pre-decrement or pre-increment, but the hardware can also
10031 ;; do cases where the increment is not the size of the object.
10033 ;; In all these cases, we use operands 0 and 1 for the register being
10034 ;; incremented because those are the operands that local-alloc will
10035 ;; tie and these are the pair most likely to be tieable (and the ones
10036 ;; that will benefit the most).
10038 (define_insn "*movdi_update1"
10039 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
10040 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
10041 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
10042 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
10043 (plus:DI (match_dup 1) (match_dup 2)))]
10044 "TARGET_POWERPC64 && TARGET_UPDATE
10045 && (!avoiding_indexed_address_p (DImode)
10046 || !gpc_reg_operand (operands[2], DImode))"
10050 [(set_attr "type" "load_ux,load_u")])
10052 (define_insn "movdi_<mode>_update"
10053 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10054 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10055 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10056 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10057 (plus:P (match_dup 1) (match_dup 2)))]
10058 "TARGET_POWERPC64 && TARGET_UPDATE
10059 && (!avoiding_indexed_address_p (Pmode)
10060 || !gpc_reg_operand (operands[2], Pmode)
10061 || (REG_P (operands[0])
10062 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10066 [(set_attr "type" "store_ux,store_u")])
10068 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
10069 ;; needed for stack allocation, even if the user passes -mno-update.
10070 (define_insn "movdi_<mode>_update_stack"
10071 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10072 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10073 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10074 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10075 (plus:P (match_dup 1) (match_dup 2)))]
10080 [(set_attr "type" "store_ux,store_u")])
10082 (define_insn "*movsi_update1"
10083 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10084 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10085 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10086 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10087 (plus:SI (match_dup 1) (match_dup 2)))]
10089 && (!avoiding_indexed_address_p (SImode)
10090 || !gpc_reg_operand (operands[2], SImode))"
10092 {lux|lwzux} %3,%0,%2
10093 {lu|lwzu} %3,%2(%0)"
10094 [(set_attr "type" "load_ux,load_u")])
10096 (define_insn "*movsi_update2"
10097 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
10099 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
10100 (match_operand:DI 2 "gpc_reg_operand" "r")))))
10101 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
10102 (plus:DI (match_dup 1) (match_dup 2)))]
10103 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
10104 && !avoiding_indexed_address_p (DImode)"
10106 [(set_attr "type" "load_ext_ux")])
10108 (define_insn "movsi_update"
10109 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10110 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10111 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10112 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10113 (plus:SI (match_dup 1) (match_dup 2)))]
10115 && (!avoiding_indexed_address_p (SImode)
10116 || !gpc_reg_operand (operands[2], SImode)
10117 || (REG_P (operands[0])
10118 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10120 {stux|stwux} %3,%0,%2
10121 {stu|stwu} %3,%2(%0)"
10122 [(set_attr "type" "store_ux,store_u")])
10124 ;; This is an unconditional pattern; needed for stack allocation, even
10125 ;; if the user passes -mno-update.
10126 (define_insn "movsi_update_stack"
10127 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10128 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10129 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10130 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10131 (plus:SI (match_dup 1) (match_dup 2)))]
10134 {stux|stwux} %3,%0,%2
10135 {stu|stwu} %3,%2(%0)"
10136 [(set_attr "type" "store_ux,store_u")])
10138 (define_insn "*movhi_update1"
10139 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
10140 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10141 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10142 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10143 (plus:SI (match_dup 1) (match_dup 2)))]
10145 && (!avoiding_indexed_address_p (SImode)
10146 || !gpc_reg_operand (operands[2], SImode))"
10150 [(set_attr "type" "load_ux,load_u")])
10152 (define_insn "*movhi_update2"
10153 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10155 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10156 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10157 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10158 (plus:SI (match_dup 1) (match_dup 2)))]
10160 && (!avoiding_indexed_address_p (SImode)
10161 || !gpc_reg_operand (operands[2], SImode))"
10165 [(set_attr "type" "load_ux,load_u")])
10167 (define_insn "*movhi_update3"
10168 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10170 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10171 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10172 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10173 (plus:SI (match_dup 1) (match_dup 2)))]
10174 "TARGET_UPDATE && rs6000_gen_cell_microcode
10175 && (!avoiding_indexed_address_p (SImode)
10176 || !gpc_reg_operand (operands[2], SImode))"
10180 [(set_attr "type" "load_ext_ux,load_ext_u")])
10182 (define_insn "*movhi_update4"
10183 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10184 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10185 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
10186 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10187 (plus:SI (match_dup 1) (match_dup 2)))]
10189 && (!avoiding_indexed_address_p (SImode)
10190 || !gpc_reg_operand (operands[2], SImode))"
10194 [(set_attr "type" "store_ux,store_u")])
10196 (define_insn "*movqi_update1"
10197 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
10198 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10199 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10200 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10201 (plus:SI (match_dup 1) (match_dup 2)))]
10203 && (!avoiding_indexed_address_p (SImode)
10204 || !gpc_reg_operand (operands[2], SImode))"
10208 [(set_attr "type" "load_ux,load_u")])
10210 (define_insn "*movqi_update2"
10211 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10213 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10214 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10215 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10216 (plus:SI (match_dup 1) (match_dup 2)))]
10218 && (!avoiding_indexed_address_p (SImode)
10219 || !gpc_reg_operand (operands[2], SImode))"
10223 [(set_attr "type" "load_ux,load_u")])
10225 (define_insn "*movqi_update3"
10226 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10227 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10228 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
10229 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10230 (plus:SI (match_dup 1) (match_dup 2)))]
10232 && (!avoiding_indexed_address_p (SImode)
10233 || !gpc_reg_operand (operands[2], SImode))"
10237 [(set_attr "type" "store_ux,store_u")])
10239 (define_insn "*movsf_update1"
10240 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
10241 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10242 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10243 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10244 (plus:SI (match_dup 1) (match_dup 2)))]
10245 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10246 && (!avoiding_indexed_address_p (SImode)
10247 || !gpc_reg_operand (operands[2], SImode))"
10251 [(set_attr "type" "fpload_ux,fpload_u")])
10253 (define_insn "*movsf_update2"
10254 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10255 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10256 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10257 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10258 (plus:SI (match_dup 1) (match_dup 2)))]
10259 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10260 && (!avoiding_indexed_address_p (SImode)
10261 || !gpc_reg_operand (operands[2], SImode))"
10265 [(set_attr "type" "fpstore_ux,fpstore_u")])
10267 (define_insn "*movsf_update3"
10268 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10269 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10270 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10271 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10272 (plus:SI (match_dup 1) (match_dup 2)))]
10273 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10274 && (!avoiding_indexed_address_p (SImode)
10275 || !gpc_reg_operand (operands[2], SImode))"
10277 {lux|lwzux} %3,%0,%2
10278 {lu|lwzu} %3,%2(%0)"
10279 [(set_attr "type" "load_ux,load_u")])
10281 (define_insn "*movsf_update4"
10282 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10283 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10284 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10285 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10286 (plus:SI (match_dup 1) (match_dup 2)))]
10287 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10288 && (!avoiding_indexed_address_p (SImode)
10289 || !gpc_reg_operand (operands[2], SImode))"
10291 {stux|stwux} %3,%0,%2
10292 {stu|stwu} %3,%2(%0)"
10293 [(set_attr "type" "store_ux,store_u")])
10295 (define_insn "*movdf_update1"
10296 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
10297 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10298 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10299 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10300 (plus:SI (match_dup 1) (match_dup 2)))]
10301 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10302 && (!avoiding_indexed_address_p (SImode)
10303 || !gpc_reg_operand (operands[2], SImode))"
10307 [(set_attr "type" "fpload_ux,fpload_u")])
10309 (define_insn "*movdf_update2"
10310 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10311 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10312 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
10313 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10314 (plus:SI (match_dup 1) (match_dup 2)))]
10315 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10316 && (!avoiding_indexed_address_p (SImode)
10317 || !gpc_reg_operand (operands[2], SImode))"
10321 [(set_attr "type" "fpstore_ux,fpstore_u")])
10323 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
10325 (define_insn "*lfq_power2"
10326 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
10327 (match_operand:V2DF 1 "memory_operand" ""))]
10329 && TARGET_HARD_FLOAT && TARGET_FPRS"
10333 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10334 (match_operand:DF 1 "memory_operand" ""))
10335 (set (match_operand:DF 2 "gpc_reg_operand" "")
10336 (match_operand:DF 3 "memory_operand" ""))]
10338 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
10339 && registers_ok_for_quad_peep (operands[0], operands[2])
10340 && mems_ok_for_quad_peep (operands[1], operands[3])"
10341 [(set (match_dup 0)
10343 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
10344 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
10346 (define_insn "*stfq_power2"
10347 [(set (match_operand:V2DF 0 "memory_operand" "")
10348 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
10350 && TARGET_HARD_FLOAT && TARGET_FPRS"
10351 "stfq%U0%X0 %1,%0")
10355 [(set (match_operand:DF 0 "memory_operand" "")
10356 (match_operand:DF 1 "gpc_reg_operand" ""))
10357 (set (match_operand:DF 2 "memory_operand" "")
10358 (match_operand:DF 3 "gpc_reg_operand" ""))]
10360 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
10361 && registers_ok_for_quad_peep (operands[1], operands[3])
10362 && mems_ok_for_quad_peep (operands[0], operands[2])"
10363 [(set (match_dup 0)
10365 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
10366 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
10368 ;; After inserting conditional returns we can sometimes have
10369 ;; unnecessary register moves. Unfortunately we cannot have a
10370 ;; modeless peephole here, because some single SImode sets have early
10371 ;; clobber outputs. Although those sets expand to multi-ppc-insn
10372 ;; sequences, using get_attr_length here will smash the operands
10373 ;; array. Neither is there an early_cobbler_p predicate.
10374 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
10376 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10377 (match_operand:DF 1 "any_operand" ""))
10378 (set (match_operand:DF 2 "gpc_reg_operand" "")
10380 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10381 && peep2_reg_dead_p (2, operands[0])"
10382 [(set (match_dup 2) (match_dup 1))])
10385 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10386 (match_operand:SF 1 "any_operand" ""))
10387 (set (match_operand:SF 2 "gpc_reg_operand" "")
10389 "peep2_reg_dead_p (2, operands[0])"
10390 [(set (match_dup 2) (match_dup 1))])
10395 ;; Mode attributes for different ABIs.
10396 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
10397 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
10398 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
10399 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
10401 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
10402 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10403 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10404 (match_operand 4 "" "g")))
10405 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10406 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10408 (clobber (reg:SI LR_REGNO))]
10409 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10410 "addi %0,%1,%2@got@tlsgd\;bl %z3\;%."
10411 "&& TARGET_TLS_MARKERS"
10412 [(set (match_dup 0)
10413 (unspec:TLSmode [(match_dup 1)
10416 (parallel [(set (match_dup 0)
10417 (call (mem:TLSmode (match_dup 3))
10419 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
10420 (clobber (reg:SI LR_REGNO))])]
10422 [(set_attr "type" "two")
10423 (set_attr "length" "12")])
10425 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
10426 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10427 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10428 (match_operand 4 "" "g")))
10429 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10430 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10432 (clobber (reg:SI LR_REGNO))]
10433 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10437 if (TARGET_SECURE_PLT && flag_pic == 2)
10438 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
10440 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
10443 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
10445 "&& TARGET_TLS_MARKERS"
10446 [(set (match_dup 0)
10447 (unspec:TLSmode [(match_dup 1)
10450 (parallel [(set (match_dup 0)
10451 (call (mem:TLSmode (match_dup 3))
10453 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
10454 (clobber (reg:SI LR_REGNO))])]
10456 [(set_attr "type" "two")
10457 (set_attr "length" "8")])
10459 (define_insn "*tls_gd<TLSmode:tls_abi_suffix>"
10460 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10461 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10462 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10464 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
10465 "addi %0,%1,%2@got@tlsgd"
10466 [(set_attr "length" "4")])
10468 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
10469 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10470 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10471 (match_operand 2 "" "g")))
10472 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
10474 (clobber (reg:SI LR_REGNO))]
10475 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
10476 "bl %z1(%3@tlsgd)\;%."
10477 [(set_attr "type" "branch")
10478 (set_attr "length" "8")])
10480 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
10481 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10482 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10483 (match_operand 2 "" "g")))
10484 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
10486 (clobber (reg:SI LR_REGNO))]
10487 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
10491 if (TARGET_SECURE_PLT && flag_pic == 2)
10492 return "bl %z1+32768(%3@tlsgd)@plt";
10493 return "bl %z1(%3@tlsgd)@plt";
10495 return "bl %z1(%3@tlsgd)";
10497 [(set_attr "type" "branch")
10498 (set_attr "length" "4")])
10500 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
10501 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10502 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10503 (match_operand 3 "" "g")))
10504 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10506 (clobber (reg:SI LR_REGNO))]
10507 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10508 "addi %0,%1,%&@got@tlsld\;bl %z2\;%."
10509 "&& TARGET_TLS_MARKERS"
10510 [(set (match_dup 0)
10511 (unspec:TLSmode [(match_dup 1)]
10513 (parallel [(set (match_dup 0)
10514 (call (mem:TLSmode (match_dup 2))
10516 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10517 (clobber (reg:SI LR_REGNO))])]
10519 [(set_attr "length" "12")])
10521 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
10522 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10523 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10524 (match_operand 3 "" "g")))
10525 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10527 (clobber (reg:SI LR_REGNO))]
10528 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10532 if (TARGET_SECURE_PLT && flag_pic == 2)
10533 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
10535 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
10538 return "addi %0,%1,%&@got@tlsld\;bl %z2";
10540 "&& TARGET_TLS_MARKERS"
10541 [(set (match_dup 0)
10542 (unspec:TLSmode [(match_dup 1)]
10544 (parallel [(set (match_dup 0)
10545 (call (mem:TLSmode (match_dup 2))
10547 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10548 (clobber (reg:SI LR_REGNO))])]
10550 [(set_attr "length" "8")])
10552 (define_insn "*tls_ld<TLSmode:tls_abi_suffix>"
10553 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10554 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10556 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
10557 "addi %0,%1,%&@got@tlsld"
10558 [(set_attr "length" "4")])
10560 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
10561 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10562 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10563 (match_operand 2 "" "g")))
10564 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10565 (clobber (reg:SI LR_REGNO))]
10566 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
10567 "bl %z1(%&@tlsld)\;%."
10568 [(set_attr "type" "branch")
10569 (set_attr "length" "8")])
10571 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
10572 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10573 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10574 (match_operand 2 "" "g")))
10575 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10576 (clobber (reg:SI LR_REGNO))]
10577 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
10581 if (TARGET_SECURE_PLT && flag_pic == 2)
10582 return "bl %z1+32768(%&@tlsld)@plt";
10583 return "bl %z1(%&@tlsld)@plt";
10585 return "bl %z1(%&@tlsld)";
10587 [(set_attr "type" "branch")
10588 (set_attr "length" "4")])
10590 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
10591 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10592 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10593 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10594 UNSPEC_TLSDTPREL))]
10596 "addi %0,%1,%2@dtprel")
10598 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
10599 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10600 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10601 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10602 UNSPEC_TLSDTPRELHA))]
10604 "addis %0,%1,%2@dtprel@ha")
10606 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
10607 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10608 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10609 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10610 UNSPEC_TLSDTPRELLO))]
10612 "addi %0,%1,%2@dtprel@l")
10614 (define_insn "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
10615 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10616 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10617 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10618 UNSPEC_TLSGOTDTPREL))]
10620 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)")
10622 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
10623 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10624 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10625 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10628 "addi %0,%1,%2@tprel")
10630 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
10631 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10632 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10633 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10634 UNSPEC_TLSTPRELHA))]
10636 "addis %0,%1,%2@tprel@ha")
10638 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
10639 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10640 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10641 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10642 UNSPEC_TLSTPRELLO))]
10644 "addi %0,%1,%2@tprel@l")
10646 ;; "b" output constraint here and on tls_tls input to support linker tls
10647 ;; optimization. The linker may edit the instructions emitted by a
10648 ;; tls_got_tprel/tls_tls pair to addis,addi.
10649 (define_insn "tls_got_tprel_<TLSmode:tls_abi_suffix>"
10650 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10651 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10652 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10653 UNSPEC_TLSGOTTPREL))]
10655 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)")
10657 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
10658 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10659 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10660 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10663 "add %0,%1,%2@tls")
10666 ;; Next come insns related to the calling sequence.
10668 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
10669 ;; We move the back-chain and decrement the stack pointer.
10671 (define_expand "allocate_stack"
10672 [(set (match_operand 0 "gpc_reg_operand" "")
10673 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10675 (minus (reg 1) (match_dup 1)))]
10678 { rtx chain = gen_reg_rtx (Pmode);
10679 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
10681 rtx insn, par, set, mem;
10683 emit_move_insn (chain, stack_bot);
10685 /* Check stack bounds if necessary. */
10686 if (crtl->limit_stack)
10689 available = expand_binop (Pmode, sub_optab,
10690 stack_pointer_rtx, stack_limit_rtx,
10691 NULL_RTX, 1, OPTAB_WIDEN);
10692 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10695 if (GET_CODE (operands[1]) != CONST_INT
10696 || INTVAL (operands[1]) < -32767
10697 || INTVAL (operands[1]) > 32768)
10699 neg_op0 = gen_reg_rtx (Pmode);
10701 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10703 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10706 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10708 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
10709 : gen_movdi_di_update_stack))
10710 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
10712 /* Since we didn't use gen_frame_mem to generate the MEM, grab
10713 it now and set the alias set/attributes. The above gen_*_update
10714 calls will generate a PARALLEL with the MEM set being the first
10716 par = PATTERN (insn);
10717 gcc_assert (GET_CODE (par) == PARALLEL);
10718 set = XVECEXP (par, 0, 0);
10719 gcc_assert (GET_CODE (set) == SET);
10720 mem = SET_DEST (set);
10721 gcc_assert (MEM_P (mem));
10722 MEM_NOTRAP_P (mem) = 1;
10723 set_mem_alias_set (mem, get_frame_alias_set ());
10725 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10729 ;; These patterns say how to save and restore the stack pointer. We need not
10730 ;; save the stack pointer at function level since we are careful to
10731 ;; preserve the backchain. At block level, we have to restore the backchain
10732 ;; when we restore the stack pointer.
10734 ;; For nonlocal gotos, we must save both the stack pointer and its
10735 ;; backchain and restore both. Note that in the nonlocal case, the
10736 ;; save area is a memory location.
10738 (define_expand "save_stack_function"
10739 [(match_operand 0 "any_operand" "")
10740 (match_operand 1 "any_operand" "")]
10744 (define_expand "restore_stack_function"
10745 [(match_operand 0 "any_operand" "")
10746 (match_operand 1 "any_operand" "")]
10750 ;; Adjust stack pointer (op0) to a new value (op1).
10751 ;; First copy old stack backchain to new location, and ensure that the
10752 ;; scheduler won't reorder the sp assignment before the backchain write.
10753 (define_expand "restore_stack_block"
10754 [(set (match_dup 2) (match_dup 3))
10755 (set (match_dup 4) (match_dup 2))
10756 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
10757 (set (match_operand 0 "register_operand" "")
10758 (match_operand 1 "register_operand" ""))]
10762 operands[1] = force_reg (Pmode, operands[1]);
10763 operands[2] = gen_reg_rtx (Pmode);
10764 operands[3] = gen_frame_mem (Pmode, operands[0]);
10765 operands[4] = gen_frame_mem (Pmode, operands[1]);
10766 operands[5] = gen_frame_mem (BLKmode, operands[0]);
10769 (define_expand "save_stack_nonlocal"
10770 [(set (match_dup 3) (match_dup 4))
10771 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10772 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
10776 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10778 /* Copy the backchain to the first word, sp to the second. */
10779 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10780 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10781 operands[3] = gen_reg_rtx (Pmode);
10782 operands[4] = gen_frame_mem (Pmode, operands[1]);
10785 (define_expand "restore_stack_nonlocal"
10786 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10787 (set (match_dup 3) (match_dup 4))
10788 (set (match_dup 5) (match_dup 2))
10789 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
10790 (set (match_operand 0 "register_operand" "") (match_dup 3))]
10794 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10796 /* Restore the backchain from the first word, sp from the second. */
10797 operands[2] = gen_reg_rtx (Pmode);
10798 operands[3] = gen_reg_rtx (Pmode);
10799 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10800 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10801 operands[5] = gen_frame_mem (Pmode, operands[3]);
10802 operands[6] = gen_frame_mem (BLKmode, operands[0]);
10805 ;; TOC register handling.
10807 ;; Code to initialize the TOC register...
10809 (define_insn "load_toc_aix_si"
10810 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10811 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10812 (use (reg:SI 2))])]
10813 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10817 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10818 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10819 operands[2] = gen_rtx_REG (Pmode, 2);
10820 return \"{l|lwz} %0,%1(%2)\";
10822 [(set_attr "type" "load")])
10824 (define_insn "load_toc_aix_di"
10825 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10826 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10827 (use (reg:DI 2))])]
10828 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10832 #ifdef TARGET_RELOCATABLE
10833 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10834 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10836 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10839 strcat (buf, \"@toc\");
10840 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10841 operands[2] = gen_rtx_REG (Pmode, 2);
10842 return \"ld %0,%1(%2)\";
10844 [(set_attr "type" "load")])
10846 (define_insn "load_toc_v4_pic_si"
10847 [(set (reg:SI LR_REGNO)
10848 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10849 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10850 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10851 [(set_attr "type" "branch")
10852 (set_attr "length" "4")])
10854 (define_insn "load_toc_v4_PIC_1"
10855 [(set (reg:SI LR_REGNO)
10856 (match_operand:SI 0 "immediate_operand" "s"))
10857 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10858 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
10859 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10860 "bcl 20,31,%0\\n%0:"
10861 [(set_attr "type" "branch")
10862 (set_attr "length" "4")])
10864 (define_insn "load_toc_v4_PIC_1b"
10865 [(set (reg:SI LR_REGNO)
10866 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")]
10868 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10869 "bcl 20,31,$+8\\n\\t.long %0-$"
10870 [(set_attr "type" "branch")
10871 (set_attr "length" "8")])
10873 (define_insn "load_toc_v4_PIC_2"
10874 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10875 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10876 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10877 (match_operand:SI 3 "immediate_operand" "s")))))]
10878 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10879 "{l|lwz} %0,%2-%3(%1)"
10880 [(set_attr "type" "load")])
10882 (define_insn "load_toc_v4_PIC_3b"
10883 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10884 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10886 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10887 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10888 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10889 "{cau|addis} %0,%1,%2-%3@ha")
10891 (define_insn "load_toc_v4_PIC_3c"
10892 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10893 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10894 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10895 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10896 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10897 "{cal|addi} %0,%1,%2-%3@l")
10899 ;; If the TOC is shared over a translation unit, as happens with all
10900 ;; the kinds of PIC that we support, we need to restore the TOC
10901 ;; pointer only when jumping over units of translation.
10902 ;; On Darwin, we need to reload the picbase.
10904 (define_expand "builtin_setjmp_receiver"
10905 [(use (label_ref (match_operand 0 "" "")))]
10906 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10907 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10908 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10912 if (DEFAULT_ABI == ABI_DARWIN)
10914 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
10915 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10919 crtl->uses_pic_offset_table = 1;
10920 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10921 CODE_LABEL_NUMBER (operands[0]));
10922 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10924 emit_insn (gen_load_macho_picbase (tmplabrtx));
10925 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
10926 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10930 rs6000_emit_load_toc_table (FALSE);
10934 ;; Elf specific ways of loading addresses for non-PIC code.
10935 ;; The output of this could be r0, but we make a very strong
10936 ;; preference for a base register because it will usually
10937 ;; be needed there.
10938 (define_insn "elf_high"
10939 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10940 (high:SI (match_operand 1 "" "")))]
10941 "TARGET_ELF && ! TARGET_64BIT"
10942 "{liu|lis} %0,%1@ha")
10944 (define_insn "elf_low"
10945 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10946 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10947 (match_operand 2 "" "")))]
10948 "TARGET_ELF && ! TARGET_64BIT"
10950 {cal|la} %0,%2@l(%1)
10951 {ai|addic} %0,%1,%K2")
10953 ;; A function pointer under AIX is a pointer to a data area whose first word
10954 ;; contains the actual address of the function, whose second word contains a
10955 ;; pointer to its TOC, and whose third word contains a value to place in the
10956 ;; static chain register (r11). Note that if we load the static chain, our
10957 ;; "trampoline" need not have any executable code.
10959 (define_expand "call_indirect_aix32"
10960 [(set (match_dup 2)
10961 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10962 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10965 (mem:SI (plus:SI (match_dup 0)
10967 (parallel [(call (mem:SI (match_dup 2))
10968 (match_operand 1 "" ""))
10969 (use (mem:SI (plus:SI (match_dup 0) (const_int 4))))
10971 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10972 (clobber (reg:SI LR_REGNO))])]
10975 { operands[2] = gen_reg_rtx (SImode); }")
10977 (define_expand "call_indirect_aix64"
10978 [(set (match_dup 2)
10979 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10980 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10983 (mem:DI (plus:DI (match_dup 0)
10985 (parallel [(call (mem:SI (match_dup 2))
10986 (match_operand 1 "" ""))
10987 (use (mem:DI (plus:DI (match_dup 0) (const_int 8))))
10989 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10990 (clobber (reg:SI LR_REGNO))])]
10993 { operands[2] = gen_reg_rtx (DImode); }")
10995 (define_expand "call_value_indirect_aix32"
10996 [(set (match_dup 3)
10997 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10998 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
11001 (mem:SI (plus:SI (match_dup 1)
11003 (parallel [(set (match_operand 0 "" "")
11004 (call (mem:SI (match_dup 3))
11005 (match_operand 2 "" "")))
11006 (use (mem:SI (plus:SI (match_dup 1) (const_int 4))))
11008 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11009 (clobber (reg:SI LR_REGNO))])]
11012 { operands[3] = gen_reg_rtx (SImode); }")
11014 (define_expand "call_value_indirect_aix64"
11015 [(set (match_dup 3)
11016 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11017 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
11020 (mem:DI (plus:DI (match_dup 1)
11022 (parallel [(set (match_operand 0 "" "")
11023 (call (mem:SI (match_dup 3))
11024 (match_operand 2 "" "")))
11025 (use (mem:DI (plus:DI (match_dup 1) (const_int 8))))
11027 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11028 (clobber (reg:SI LR_REGNO))])]
11031 { operands[3] = gen_reg_rtx (DImode); }")
11033 ;; Now the definitions for the call and call_value insns
11034 (define_expand "call"
11035 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11036 (match_operand 1 "" ""))
11037 (use (match_operand 2 "" ""))
11038 (clobber (reg:SI LR_REGNO))])]
11043 if (MACHOPIC_INDIRECT)
11044 operands[0] = machopic_indirect_call_target (operands[0]);
11047 gcc_assert (GET_CODE (operands[0]) == MEM);
11048 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11050 operands[0] = XEXP (operands[0], 0);
11052 if (GET_CODE (operands[0]) != SYMBOL_REF
11053 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
11054 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
11056 if (INTVAL (operands[2]) & CALL_LONG)
11057 operands[0] = rs6000_longcall_ref (operands[0]);
11059 switch (DEFAULT_ABI)
11063 operands[0] = force_reg (Pmode, operands[0]);
11067 /* AIX function pointers are really pointers to a three word
11069 emit_call_insn (TARGET_32BIT
11070 ? gen_call_indirect_aix32 (force_reg (SImode,
11073 : gen_call_indirect_aix64 (force_reg (DImode,
11079 gcc_unreachable ();
11084 (define_expand "call_value"
11085 [(parallel [(set (match_operand 0 "" "")
11086 (call (mem:SI (match_operand 1 "address_operand" ""))
11087 (match_operand 2 "" "")))
11088 (use (match_operand 3 "" ""))
11089 (clobber (reg:SI LR_REGNO))])]
11094 if (MACHOPIC_INDIRECT)
11095 operands[1] = machopic_indirect_call_target (operands[1]);
11098 gcc_assert (GET_CODE (operands[1]) == MEM);
11099 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11101 operands[1] = XEXP (operands[1], 0);
11103 if (GET_CODE (operands[1]) != SYMBOL_REF
11104 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
11105 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
11107 if (INTVAL (operands[3]) & CALL_LONG)
11108 operands[1] = rs6000_longcall_ref (operands[1]);
11110 switch (DEFAULT_ABI)
11114 operands[1] = force_reg (Pmode, operands[1]);
11118 /* AIX function pointers are really pointers to a three word
11120 emit_call_insn (TARGET_32BIT
11121 ? gen_call_value_indirect_aix32 (operands[0],
11125 : gen_call_value_indirect_aix64 (operands[0],
11132 gcc_unreachable ();
11137 ;; Call to function in current module. No TOC pointer reload needed.
11138 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
11139 ;; either the function was not prototyped, or it was prototyped as a
11140 ;; variable argument function. It is > 0 if FP registers were passed
11141 ;; and < 0 if they were not.
11143 (define_insn "*call_local32"
11144 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11145 (match_operand 1 "" "g,g"))
11146 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11147 (clobber (reg:SI LR_REGNO))]
11148 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11151 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11152 output_asm_insn (\"crxor 6,6,6\", operands);
11154 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11155 output_asm_insn (\"creqv 6,6,6\", operands);
11157 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11159 [(set_attr "type" "branch")
11160 (set_attr "length" "4,8")])
11162 (define_insn "*call_local64"
11163 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11164 (match_operand 1 "" "g,g"))
11165 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11166 (clobber (reg:SI LR_REGNO))]
11167 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11170 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11171 output_asm_insn (\"crxor 6,6,6\", operands);
11173 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11174 output_asm_insn (\"creqv 6,6,6\", operands);
11176 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11178 [(set_attr "type" "branch")
11179 (set_attr "length" "4,8")])
11181 (define_insn "*call_value_local32"
11182 [(set (match_operand 0 "" "")
11183 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11184 (match_operand 2 "" "g,g")))
11185 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11186 (clobber (reg:SI LR_REGNO))]
11187 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11190 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11191 output_asm_insn (\"crxor 6,6,6\", operands);
11193 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11194 output_asm_insn (\"creqv 6,6,6\", operands);
11196 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11198 [(set_attr "type" "branch")
11199 (set_attr "length" "4,8")])
11202 (define_insn "*call_value_local64"
11203 [(set (match_operand 0 "" "")
11204 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11205 (match_operand 2 "" "g,g")))
11206 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11207 (clobber (reg:SI LR_REGNO))]
11208 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11211 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11212 output_asm_insn (\"crxor 6,6,6\", operands);
11214 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11215 output_asm_insn (\"creqv 6,6,6\", operands);
11217 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11219 [(set_attr "type" "branch")
11220 (set_attr "length" "4,8")])
11222 ;; Call to function which may be in another module. Restore the TOC
11223 ;; pointer (r2) after the call unless this is System V.
11224 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
11225 ;; either the function was not prototyped, or it was prototyped as a
11226 ;; variable argument function. It is > 0 if FP registers were passed
11227 ;; and < 0 if they were not.
11229 (define_insn_and_split "*call_indirect_nonlocal_aix32_internal"
11230 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
11231 (match_operand 1 "" "g,g"))
11232 (use (mem:SI (plus:SI (match_operand:SI 2 "register_operand" "b,b") (const_int 4))))
11234 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11235 (clobber (reg:SI LR_REGNO))]
11236 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11238 "&& reload_completed"
11240 (mem:SI (plus:SI (match_dup 2) (const_int 4))))
11241 (parallel [(call (mem:SI (match_dup 0))
11246 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11247 (clobber (reg:SI LR_REGNO))])]
11249 [(set_attr "type" "jmpreg")
11250 (set_attr "length" "12")])
11252 (define_insn "*call_indirect_nonlocal_aix32"
11253 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
11254 (match_operand 1 "" "g,g"))
11258 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11259 (clobber (reg:SI LR_REGNO))]
11260 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11261 "b%T0l\;{l|lwz} 2,20(1)"
11262 [(set_attr "type" "jmpreg")
11263 (set_attr "length" "8")])
11265 (define_insn "*call_nonlocal_aix32"
11266 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11267 (match_operand 1 "" "g"))
11268 (use (match_operand:SI 2 "immediate_operand" "O"))
11269 (clobber (reg:SI LR_REGNO))]
11271 && DEFAULT_ABI == ABI_AIX
11272 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11274 [(set_attr "type" "branch")
11275 (set_attr "length" "8")])
11277 (define_insn_and_split "*call_indirect_nonlocal_aix64_internal"
11278 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
11279 (match_operand 1 "" "g,g"))
11280 (use (mem:DI (plus:DI (match_operand:DI 2 "register_operand" "b,b")
11283 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11284 (clobber (reg:SI LR_REGNO))]
11285 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11287 "&& reload_completed"
11289 (mem:DI (plus:DI (match_dup 2) (const_int 8))))
11290 (parallel [(call (mem:SI (match_dup 0))
11295 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11296 (clobber (reg:SI LR_REGNO))])]
11298 [(set_attr "type" "jmpreg")
11299 (set_attr "length" "12")])
11301 (define_insn "*call_indirect_nonlocal_aix64"
11302 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
11303 (match_operand 1 "" "g,g"))
11307 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11308 (clobber (reg:SI LR_REGNO))]
11309 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11310 "b%T0l\;ld 2,40(1)"
11311 [(set_attr "type" "jmpreg")
11312 (set_attr "length" "8")])
11314 (define_insn "*call_nonlocal_aix64"
11315 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11316 (match_operand 1 "" "g"))
11317 (use (match_operand:SI 2 "immediate_operand" "O"))
11318 (clobber (reg:SI LR_REGNO))]
11320 && DEFAULT_ABI == ABI_AIX
11321 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11323 [(set_attr "type" "branch")
11324 (set_attr "length" "8")])
11326 (define_insn_and_split "*call_value_indirect_nonlocal_aix32_internal"
11327 [(set (match_operand 0 "" "")
11328 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
11329 (match_operand 2 "" "g,g")))
11330 (use (mem:SI (plus:SI (match_operand:SI 3 "register_operand" "b,b")
11333 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11334 (clobber (reg:SI LR_REGNO))]
11335 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11337 "&& reload_completed"
11339 (mem:SI (plus:SI (match_dup 3) (const_int 4))))
11340 (parallel [(set (match_dup 0) (call (mem:SI (match_dup 1))
11345 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11346 (clobber (reg:SI LR_REGNO))])]
11348 [(set_attr "type" "jmpreg")
11349 (set_attr "length" "12")])
11351 (define_insn "*call_value_indirect_nonlocal_aix32"
11352 [(set (match_operand 0 "" "")
11353 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
11354 (match_operand 2 "" "g,g")))
11358 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11359 (clobber (reg:SI LR_REGNO))]
11360 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11361 "b%T1l\;{l|lwz} 2,20(1)"
11362 [(set_attr "type" "jmpreg")
11363 (set_attr "length" "8")])
11365 (define_insn "*call_value_nonlocal_aix32"
11366 [(set (match_operand 0 "" "")
11367 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11368 (match_operand 2 "" "g")))
11369 (use (match_operand:SI 3 "immediate_operand" "O"))
11370 (clobber (reg:SI LR_REGNO))]
11372 && DEFAULT_ABI == ABI_AIX
11373 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11375 [(set_attr "type" "branch")
11376 (set_attr "length" "8")])
11378 (define_insn_and_split "*call_value_indirect_nonlocal_aix64_internal"
11379 [(set (match_operand 0 "" "")
11380 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
11381 (match_operand 2 "" "g,g")))
11382 (use (mem:DI (plus:DI (match_operand:DI 3 "register_operand" "b,b")
11385 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11386 (clobber (reg:SI LR_REGNO))]
11387 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11389 "&& reload_completed"
11391 (mem:DI (plus:DI (match_dup 3) (const_int 8))))
11392 (parallel [(set (match_dup 0) (call (mem:SI (match_dup 1))
11397 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11398 (clobber (reg:SI LR_REGNO))])]
11400 [(set_attr "type" "jmpreg")
11401 (set_attr "length" "12")])
11403 (define_insn "*call_value_indirect_nonlocal_aix64"
11404 [(set (match_operand 0 "" "")
11405 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
11406 (match_operand 2 "" "g,g")))
11410 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11411 (clobber (reg:SI LR_REGNO))]
11412 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11413 "b%T1l\;ld 2,40(1)"
11414 [(set_attr "type" "jmpreg")
11415 (set_attr "length" "8")])
11417 (define_insn "*call_value_nonlocal_aix64"
11418 [(set (match_operand 0 "" "")
11419 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11420 (match_operand 2 "" "g")))
11421 (use (match_operand:SI 3 "immediate_operand" "O"))
11422 (clobber (reg:SI LR_REGNO))]
11424 && DEFAULT_ABI == ABI_AIX
11425 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11427 [(set_attr "type" "branch")
11428 (set_attr "length" "8")])
11430 ;; A function pointer under System V is just a normal pointer
11431 ;; operands[0] is the function pointer
11432 ;; operands[1] is the stack size to clean up
11433 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
11434 ;; which indicates how to set cr1
11436 (define_insn "*call_indirect_nonlocal_sysv<mode>"
11437 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
11438 (match_operand 1 "" "g,g,g,g"))
11439 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
11440 (clobber (reg:SI LR_REGNO))]
11441 "DEFAULT_ABI == ABI_V4
11442 || DEFAULT_ABI == ABI_DARWIN"
11444 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11445 output_asm_insn ("crxor 6,6,6", operands);
11447 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11448 output_asm_insn ("creqv 6,6,6", operands);
11452 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11453 (set_attr "length" "4,4,8,8")])
11455 (define_insn_and_split "*call_nonlocal_sysv<mode>"
11456 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11457 (match_operand 1 "" "g,g"))
11458 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11459 (clobber (reg:SI LR_REGNO))]
11460 "(DEFAULT_ABI == ABI_DARWIN
11461 || (DEFAULT_ABI == ABI_V4
11462 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
11464 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11465 output_asm_insn ("crxor 6,6,6", operands);
11467 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11468 output_asm_insn ("creqv 6,6,6", operands);
11471 return output_call(insn, operands, 0, 2);
11473 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11475 gcc_assert (!TARGET_SECURE_PLT);
11476 return "bl %z0@plt";
11482 "DEFAULT_ABI == ABI_V4
11483 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11484 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11485 [(parallel [(call (mem:SI (match_dup 0))
11487 (use (match_dup 2))
11488 (use (match_dup 3))
11489 (clobber (reg:SI LR_REGNO))])]
11491 operands[3] = pic_offset_table_rtx;
11493 [(set_attr "type" "branch,branch")
11494 (set_attr "length" "4,8")])
11496 (define_insn "*call_nonlocal_sysv_secure<mode>"
11497 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11498 (match_operand 1 "" "g,g"))
11499 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11500 (use (match_operand:SI 3 "register_operand" "r,r"))
11501 (clobber (reg:SI LR_REGNO))]
11502 "(DEFAULT_ABI == ABI_V4
11503 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11504 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
11506 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11507 output_asm_insn ("crxor 6,6,6", operands);
11509 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11510 output_asm_insn ("creqv 6,6,6", operands);
11513 /* The magic 32768 offset here and in the other sysv call insns
11514 corresponds to the offset of r30 in .got2, as given by LCTOC1.
11515 See sysv4.h:toc_section. */
11516 return "bl %z0+32768@plt";
11518 return "bl %z0@plt";
11520 [(set_attr "type" "branch,branch")
11521 (set_attr "length" "4,8")])
11523 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
11524 [(set (match_operand 0 "" "")
11525 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
11526 (match_operand 2 "" "g,g,g,g")))
11527 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
11528 (clobber (reg:SI LR_REGNO))]
11529 "DEFAULT_ABI == ABI_V4
11530 || DEFAULT_ABI == ABI_DARWIN"
11532 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11533 output_asm_insn ("crxor 6,6,6", operands);
11535 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11536 output_asm_insn ("creqv 6,6,6", operands);
11540 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11541 (set_attr "length" "4,4,8,8")])
11543 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
11544 [(set (match_operand 0 "" "")
11545 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11546 (match_operand 2 "" "g,g")))
11547 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11548 (clobber (reg:SI LR_REGNO))]
11549 "(DEFAULT_ABI == ABI_DARWIN
11550 || (DEFAULT_ABI == ABI_V4
11551 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
11553 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11554 output_asm_insn ("crxor 6,6,6", operands);
11556 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11557 output_asm_insn ("creqv 6,6,6", operands);
11560 return output_call(insn, operands, 1, 3);
11562 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11564 gcc_assert (!TARGET_SECURE_PLT);
11565 return "bl %z1@plt";
11571 "DEFAULT_ABI == ABI_V4
11572 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11573 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11574 [(parallel [(set (match_dup 0)
11575 (call (mem:SI (match_dup 1))
11577 (use (match_dup 3))
11578 (use (match_dup 4))
11579 (clobber (reg:SI LR_REGNO))])]
11581 operands[4] = pic_offset_table_rtx;
11583 [(set_attr "type" "branch,branch")
11584 (set_attr "length" "4,8")])
11586 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
11587 [(set (match_operand 0 "" "")
11588 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11589 (match_operand 2 "" "g,g")))
11590 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11591 (use (match_operand:SI 4 "register_operand" "r,r"))
11592 (clobber (reg:SI LR_REGNO))]
11593 "(DEFAULT_ABI == ABI_V4
11594 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11595 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
11597 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11598 output_asm_insn ("crxor 6,6,6", operands);
11600 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11601 output_asm_insn ("creqv 6,6,6", operands);
11604 return "bl %z1+32768@plt";
11606 return "bl %z1@plt";
11608 [(set_attr "type" "branch,branch")
11609 (set_attr "length" "4,8")])
11611 ;; Call subroutine returning any type.
11612 (define_expand "untyped_call"
11613 [(parallel [(call (match_operand 0 "" "")
11615 (match_operand 1 "" "")
11616 (match_operand 2 "" "")])]
11622 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
11624 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11626 rtx set = XVECEXP (operands[2], 0, i);
11627 emit_move_insn (SET_DEST (set), SET_SRC (set));
11630 /* The optimizer does not know that the call sets the function value
11631 registers we stored in the result block. We avoid problems by
11632 claiming that all hard registers are used and clobbered at this
11634 emit_insn (gen_blockage ());
11639 ;; sibling call patterns
11640 (define_expand "sibcall"
11641 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11642 (match_operand 1 "" ""))
11643 (use (match_operand 2 "" ""))
11644 (use (reg:SI LR_REGNO))
11650 if (MACHOPIC_INDIRECT)
11651 operands[0] = machopic_indirect_call_target (operands[0]);
11654 gcc_assert (GET_CODE (operands[0]) == MEM);
11655 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11657 operands[0] = XEXP (operands[0], 0);
11660 ;; this and similar patterns must be marked as using LR, otherwise
11661 ;; dataflow will try to delete the store into it. This is true
11662 ;; even when the actual reg to jump to is in CTR, when LR was
11663 ;; saved and restored around the PIC-setting BCL.
11664 (define_insn "*sibcall_local32"
11665 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11666 (match_operand 1 "" "g,g"))
11667 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11668 (use (reg:SI LR_REGNO))
11670 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11673 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11674 output_asm_insn (\"crxor 6,6,6\", operands);
11676 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11677 output_asm_insn (\"creqv 6,6,6\", operands);
11679 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11681 [(set_attr "type" "branch")
11682 (set_attr "length" "4,8")])
11684 (define_insn "*sibcall_local64"
11685 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11686 (match_operand 1 "" "g,g"))
11687 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11688 (use (reg:SI LR_REGNO))
11690 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11693 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11694 output_asm_insn (\"crxor 6,6,6\", operands);
11696 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11697 output_asm_insn (\"creqv 6,6,6\", operands);
11699 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11701 [(set_attr "type" "branch")
11702 (set_attr "length" "4,8")])
11704 (define_insn "*sibcall_value_local32"
11705 [(set (match_operand 0 "" "")
11706 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11707 (match_operand 2 "" "g,g")))
11708 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11709 (use (reg:SI LR_REGNO))
11711 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11714 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11715 output_asm_insn (\"crxor 6,6,6\", operands);
11717 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11718 output_asm_insn (\"creqv 6,6,6\", operands);
11720 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11722 [(set_attr "type" "branch")
11723 (set_attr "length" "4,8")])
11726 (define_insn "*sibcall_value_local64"
11727 [(set (match_operand 0 "" "")
11728 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11729 (match_operand 2 "" "g,g")))
11730 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11731 (use (reg:SI LR_REGNO))
11733 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11736 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11737 output_asm_insn (\"crxor 6,6,6\", operands);
11739 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11740 output_asm_insn (\"creqv 6,6,6\", operands);
11742 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11744 [(set_attr "type" "branch")
11745 (set_attr "length" "4,8")])
11747 (define_insn "*sibcall_nonlocal_aix32"
11748 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11749 (match_operand 1 "" "g"))
11750 (use (match_operand:SI 2 "immediate_operand" "O"))
11751 (use (reg:SI LR_REGNO))
11754 && DEFAULT_ABI == ABI_AIX
11755 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11757 [(set_attr "type" "branch")
11758 (set_attr "length" "4")])
11760 (define_insn "*sibcall_nonlocal_aix64"
11761 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11762 (match_operand 1 "" "g"))
11763 (use (match_operand:SI 2 "immediate_operand" "O"))
11764 (use (reg:SI LR_REGNO))
11767 && DEFAULT_ABI == ABI_AIX
11768 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11770 [(set_attr "type" "branch")
11771 (set_attr "length" "4")])
11773 (define_insn "*sibcall_value_nonlocal_aix32"
11774 [(set (match_operand 0 "" "")
11775 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11776 (match_operand 2 "" "g")))
11777 (use (match_operand:SI 3 "immediate_operand" "O"))
11778 (use (reg:SI LR_REGNO))
11781 && DEFAULT_ABI == ABI_AIX
11782 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11784 [(set_attr "type" "branch")
11785 (set_attr "length" "4")])
11787 (define_insn "*sibcall_value_nonlocal_aix64"
11788 [(set (match_operand 0 "" "")
11789 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11790 (match_operand 2 "" "g")))
11791 (use (match_operand:SI 3 "immediate_operand" "O"))
11792 (use (reg:SI LR_REGNO))
11795 && DEFAULT_ABI == ABI_AIX
11796 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11798 [(set_attr "type" "branch")
11799 (set_attr "length" "4")])
11801 (define_insn "*sibcall_nonlocal_sysv<mode>"
11802 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11803 (match_operand 1 "" ""))
11804 (use (match_operand 2 "immediate_operand" "O,n"))
11805 (use (reg:SI LR_REGNO))
11807 "(DEFAULT_ABI == ABI_DARWIN
11808 || DEFAULT_ABI == ABI_V4)
11809 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11812 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11813 output_asm_insn (\"crxor 6,6,6\", operands);
11815 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11816 output_asm_insn (\"creqv 6,6,6\", operands);
11818 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11820 gcc_assert (!TARGET_SECURE_PLT);
11821 return \"b %z0@plt\";
11826 [(set_attr "type" "branch,branch")
11827 (set_attr "length" "4,8")])
11829 (define_expand "sibcall_value"
11830 [(parallel [(set (match_operand 0 "register_operand" "")
11831 (call (mem:SI (match_operand 1 "address_operand" ""))
11832 (match_operand 2 "" "")))
11833 (use (match_operand 3 "" ""))
11834 (use (reg:SI LR_REGNO))
11840 if (MACHOPIC_INDIRECT)
11841 operands[1] = machopic_indirect_call_target (operands[1]);
11844 gcc_assert (GET_CODE (operands[1]) == MEM);
11845 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11847 operands[1] = XEXP (operands[1], 0);
11850 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
11851 [(set (match_operand 0 "" "")
11852 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11853 (match_operand 2 "" "")))
11854 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11855 (use (reg:SI LR_REGNO))
11857 "(DEFAULT_ABI == ABI_DARWIN
11858 || DEFAULT_ABI == ABI_V4)
11859 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11862 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11863 output_asm_insn (\"crxor 6,6,6\", operands);
11865 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11866 output_asm_insn (\"creqv 6,6,6\", operands);
11868 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11870 gcc_assert (!TARGET_SECURE_PLT);
11871 return \"b %z1@plt\";
11876 [(set_attr "type" "branch,branch")
11877 (set_attr "length" "4,8")])
11879 (define_expand "sibcall_epilogue"
11880 [(use (const_int 0))]
11881 "TARGET_SCHED_PROLOG"
11884 rs6000_emit_epilogue (TRUE);
11888 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11889 ;; all of memory. This blocks insns from being moved across this point.
11891 (define_insn "blockage"
11892 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
11896 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
11897 ;; signed & unsigned, and one type of branch.
11899 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11900 ;; insns, and branches. We store the operands of compares until we see
11902 (define_expand "cmp<mode>"
11904 (compare (match_operand:GPR 0 "gpc_reg_operand" "")
11905 (match_operand:GPR 1 "reg_or_short_operand" "")))]
11909 /* Take care of the possibility that operands[1] might be negative but
11910 this might be a logical operation. That insn doesn't exist. */
11911 if (GET_CODE (operands[1]) == CONST_INT
11912 && INTVAL (operands[1]) < 0)
11913 operands[1] = force_reg (<MODE>mode, operands[1]);
11915 rs6000_compare_op0 = operands[0];
11916 rs6000_compare_op1 = operands[1];
11917 rs6000_compare_fp_p = 0;
11921 (define_expand "cmp<mode>"
11922 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
11923 (match_operand:FP 1 "gpc_reg_operand" "")))]
11927 rs6000_compare_op0 = operands[0];
11928 rs6000_compare_op1 = operands[1];
11929 rs6000_compare_fp_p = 1;
11933 (define_expand "beq"
11934 [(use (match_operand 0 "" ""))]
11936 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
11938 (define_expand "bne"
11939 [(use (match_operand 0 "" ""))]
11941 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
11943 (define_expand "bge"
11944 [(use (match_operand 0 "" ""))]
11946 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
11948 (define_expand "bgt"
11949 [(use (match_operand 0 "" ""))]
11951 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
11953 (define_expand "ble"
11954 [(use (match_operand 0 "" ""))]
11956 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
11958 (define_expand "blt"
11959 [(use (match_operand 0 "" ""))]
11961 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
11963 (define_expand "bgeu"
11964 [(use (match_operand 0 "" ""))]
11966 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
11968 (define_expand "bgtu"
11969 [(use (match_operand 0 "" ""))]
11971 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
11973 (define_expand "bleu"
11974 [(use (match_operand 0 "" ""))]
11976 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
11978 (define_expand "bltu"
11979 [(use (match_operand 0 "" ""))]
11981 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
11983 (define_expand "bunordered"
11984 [(use (match_operand 0 "" ""))]
11985 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11986 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
11988 (define_expand "bordered"
11989 [(use (match_operand 0 "" ""))]
11990 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11991 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
11993 (define_expand "buneq"
11994 [(use (match_operand 0 "" ""))]
11995 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11996 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
11998 (define_expand "bunge"
11999 [(use (match_operand 0 "" ""))]
12000 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
12001 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
12003 (define_expand "bungt"
12004 [(use (match_operand 0 "" ""))]
12005 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
12006 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
12008 (define_expand "bunle"
12009 [(use (match_operand 0 "" ""))]
12010 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
12011 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
12013 (define_expand "bunlt"
12014 [(use (match_operand 0 "" ""))]
12015 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
12016 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
12018 (define_expand "bltgt"
12019 [(use (match_operand 0 "" ""))]
12020 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
12021 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
12023 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
12024 ;; For SEQ, likewise, except that comparisons with zero should be done
12025 ;; with an scc insns. However, due to the order that combine see the
12026 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
12027 ;; the cases we don't want to handle.
12028 (define_expand "seq"
12029 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12031 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
12033 (define_expand "sne"
12034 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12038 if (! rs6000_compare_fp_p)
12041 rs6000_emit_sCOND (NE, operands[0]);
12045 ;; A >= 0 is best done the portable way for A an integer.
12046 (define_expand "sge"
12047 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12051 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
12054 rs6000_emit_sCOND (GE, operands[0]);
12058 ;; A > 0 is best done using the portable sequence, so fail in that case.
12059 (define_expand "sgt"
12060 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12064 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
12067 rs6000_emit_sCOND (GT, operands[0]);
12071 ;; A <= 0 is best done the portable way for A an integer.
12072 (define_expand "sle"
12073 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12077 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
12080 rs6000_emit_sCOND (LE, operands[0]);
12084 ;; A < 0 is best done in the portable way for A an integer.
12085 (define_expand "slt"
12086 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12090 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
12093 rs6000_emit_sCOND (LT, operands[0]);
12097 (define_expand "sgeu"
12098 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12100 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
12102 (define_expand "sgtu"
12103 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12105 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
12107 (define_expand "sleu"
12108 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12110 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
12112 (define_expand "sltu"
12113 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12115 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
12117 (define_expand "sunordered"
12118 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12119 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
12120 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
12122 (define_expand "sordered"
12123 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12124 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
12125 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
12127 (define_expand "suneq"
12128 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12129 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
12130 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
12132 (define_expand "sunge"
12133 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12134 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
12135 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
12137 (define_expand "sungt"
12138 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12139 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
12140 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
12142 (define_expand "sunle"
12143 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12144 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
12145 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
12147 (define_expand "sunlt"
12148 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12149 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
12150 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
12152 (define_expand "sltgt"
12153 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12154 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
12155 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
12157 (define_expand "stack_protect_set"
12158 [(match_operand 0 "memory_operand" "")
12159 (match_operand 1 "memory_operand" "")]
12162 #ifdef TARGET_THREAD_SSP_OFFSET
12163 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12164 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12165 operands[1] = gen_rtx_MEM (Pmode, addr);
12168 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
12170 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
12174 (define_insn "stack_protect_setsi"
12175 [(set (match_operand:SI 0 "memory_operand" "=m")
12176 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12177 (set (match_scratch:SI 2 "=&r") (const_int 0))]
12179 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
12180 [(set_attr "type" "three")
12181 (set_attr "length" "12")])
12183 (define_insn "stack_protect_setdi"
12184 [(set (match_operand:DI 0 "memory_operand" "=m")
12185 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12186 (set (match_scratch:DI 2 "=&r") (const_int 0))]
12188 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
12189 [(set_attr "type" "three")
12190 (set_attr "length" "12")])
12192 (define_expand "stack_protect_test"
12193 [(match_operand 0 "memory_operand" "")
12194 (match_operand 1 "memory_operand" "")
12195 (match_operand 2 "" "")]
12198 #ifdef TARGET_THREAD_SSP_OFFSET
12199 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12200 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12201 operands[1] = gen_rtx_MEM (Pmode, addr);
12203 rs6000_compare_op0 = operands[0];
12204 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
12206 rs6000_compare_fp_p = 0;
12207 emit_jump_insn (gen_beq (operands[2]));
12211 (define_insn "stack_protect_testsi"
12212 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12213 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
12214 (match_operand:SI 2 "memory_operand" "m,m")]
12216 (set (match_scratch:SI 4 "=r,r") (const_int 0))
12217 (clobber (match_scratch:SI 3 "=&r,&r"))]
12220 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
12221 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
12222 [(set_attr "length" "16,20")])
12224 (define_insn "stack_protect_testdi"
12225 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12226 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
12227 (match_operand:DI 2 "memory_operand" "m,m")]
12229 (set (match_scratch:DI 4 "=r,r") (const_int 0))
12230 (clobber (match_scratch:DI 3 "=&r,&r"))]
12233 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
12234 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
12235 [(set_attr "length" "16,20")])
12238 ;; Here are the actual compare insns.
12239 (define_insn "*cmp<mode>_internal1"
12240 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
12241 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
12242 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
12244 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
12245 [(set_attr "type" "cmp")])
12247 ;; If we are comparing a register for equality with a large constant,
12248 ;; we can do this with an XOR followed by a compare. But this is profitable
12249 ;; only if the large constant is only used for the comparison (and in this
12250 ;; case we already have a register to reuse as scratch).
12252 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
12253 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
12256 [(set (match_operand:SI 0 "register_operand")
12257 (match_operand:SI 1 "logical_const_operand" ""))
12258 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
12260 (match_operand:SI 2 "logical_const_operand" "")]))
12261 (set (match_operand:CC 4 "cc_reg_operand" "")
12262 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
12265 (if_then_else (match_operator 6 "equality_operator"
12266 [(match_dup 4) (const_int 0)])
12267 (match_operand 7 "" "")
12268 (match_operand 8 "" "")))]
12269 "peep2_reg_dead_p (3, operands[0])
12270 && peep2_reg_dead_p (4, operands[4])"
12271 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
12272 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
12273 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
12276 /* Get the constant we are comparing against, and see what it looks like
12277 when sign-extended from 16 to 32 bits. Then see what constant we could
12278 XOR with SEXTC to get the sign-extended value. */
12279 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
12281 operands[1], operands[2]);
12282 HOST_WIDE_INT c = INTVAL (cnst);
12283 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
12284 HOST_WIDE_INT xorv = c ^ sextc;
12286 operands[9] = GEN_INT (xorv);
12287 operands[10] = GEN_INT (sextc);
12290 (define_insn "*cmpsi_internal2"
12291 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12292 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12293 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
12295 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
12296 [(set_attr "type" "cmp")])
12298 (define_insn "*cmpdi_internal2"
12299 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12300 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
12301 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
12303 "cmpld%I2 %0,%1,%b2"
12304 [(set_attr "type" "cmp")])
12306 ;; The following two insns don't exist as single insns, but if we provide
12307 ;; them, we can swap an add and compare, which will enable us to overlap more
12308 ;; of the required delay between a compare and branch. We generate code for
12309 ;; them by splitting.
12312 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12313 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
12314 (match_operand:SI 2 "short_cint_operand" "i")))
12315 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12316 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12319 [(set_attr "length" "8")])
12322 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
12323 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12324 (match_operand:SI 2 "u_short_cint_operand" "i")))
12325 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12326 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12329 [(set_attr "length" "8")])
12332 [(set (match_operand:CC 3 "cc_reg_operand" "")
12333 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
12334 (match_operand:SI 2 "short_cint_operand" "")))
12335 (set (match_operand:SI 0 "gpc_reg_operand" "")
12336 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12338 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
12339 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12342 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
12343 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
12344 (match_operand:SI 2 "u_short_cint_operand" "")))
12345 (set (match_operand:SI 0 "gpc_reg_operand" "")
12346 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12348 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
12349 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12351 (define_insn "*cmpsf_internal1"
12352 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12353 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
12354 (match_operand:SF 2 "gpc_reg_operand" "f")))]
12355 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
12357 [(set_attr "type" "fpcompare")])
12359 (define_insn "*cmpdf_internal1"
12360 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12361 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
12362 (match_operand:DF 2 "gpc_reg_operand" "f")))]
12363 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
12365 [(set_attr "type" "fpcompare")])
12367 ;; Only need to compare second words if first words equal
12368 (define_insn "*cmptf_internal1"
12369 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12370 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
12371 (match_operand:TF 2 "gpc_reg_operand" "f")))]
12372 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
12373 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12374 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
12375 [(set_attr "type" "fpcompare")
12376 (set_attr "length" "12")])
12378 (define_insn_and_split "*cmptf_internal2"
12379 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12380 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
12381 (match_operand:TF 2 "gpc_reg_operand" "f")))
12382 (clobber (match_scratch:DF 3 "=f"))
12383 (clobber (match_scratch:DF 4 "=f"))
12384 (clobber (match_scratch:DF 5 "=f"))
12385 (clobber (match_scratch:DF 6 "=f"))
12386 (clobber (match_scratch:DF 7 "=f"))
12387 (clobber (match_scratch:DF 8 "=f"))
12388 (clobber (match_scratch:DF 9 "=f"))
12389 (clobber (match_scratch:DF 10 "=f"))]
12390 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
12391 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12393 "&& reload_completed"
12394 [(set (match_dup 3) (match_dup 13))
12395 (set (match_dup 4) (match_dup 14))
12396 (set (match_dup 9) (abs:DF (match_dup 5)))
12397 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
12398 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
12399 (label_ref (match_dup 11))
12401 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
12402 (set (pc) (label_ref (match_dup 12)))
12404 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
12405 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
12406 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
12407 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
12410 REAL_VALUE_TYPE rv;
12411 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
12412 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
12414 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
12415 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
12416 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
12417 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
12418 operands[11] = gen_label_rtx ();
12419 operands[12] = gen_label_rtx ();
12421 operands[13] = force_const_mem (DFmode,
12422 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
12423 operands[14] = force_const_mem (DFmode,
12424 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
12428 operands[13] = gen_const_mem (DFmode,
12429 create_TOC_reference (XEXP (operands[13], 0)));
12430 operands[14] = gen_const_mem (DFmode,
12431 create_TOC_reference (XEXP (operands[14], 0)));
12432 set_mem_alias_set (operands[13], get_TOC_alias_set ());
12433 set_mem_alias_set (operands[14], get_TOC_alias_set ());
12437 ;; Now we have the scc insns. We can do some combinations because of the
12438 ;; way the machine works.
12440 ;; Note that this is probably faster if we can put an insn between the
12441 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
12442 ;; cases the insns below which don't use an intermediate CR field will
12443 ;; be used instead.
12445 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12446 (match_operator:SI 1 "scc_comparison_operator"
12447 [(match_operand 2 "cc_reg_operand" "y")
12450 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12451 [(set (attr "type")
12452 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12453 (const_string "mfcrf")
12455 (const_string "mfcr")))
12456 (set_attr "length" "8")])
12458 ;; Same as above, but get the GT bit.
12459 (define_insn "move_from_CR_gt_bit"
12460 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12461 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
12462 "TARGET_HARD_FLOAT && !TARGET_FPRS"
12463 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
12464 [(set_attr "type" "mfcr")
12465 (set_attr "length" "8")])
12467 ;; Same as above, but get the OV/ORDERED bit.
12468 (define_insn "move_from_CR_ov_bit"
12469 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12470 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
12472 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
12473 [(set_attr "type" "mfcr")
12474 (set_attr "length" "8")])
12477 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12478 (match_operator:DI 1 "scc_comparison_operator"
12479 [(match_operand 2 "cc_reg_operand" "y")
12482 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12483 [(set (attr "type")
12484 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12485 (const_string "mfcrf")
12487 (const_string "mfcr")))
12488 (set_attr "length" "8")])
12491 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12492 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12493 [(match_operand 2 "cc_reg_operand" "y,y")
12496 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
12497 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12500 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
12502 [(set_attr "type" "delayed_compare")
12503 (set_attr "length" "8,16")])
12506 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12507 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12508 [(match_operand 2 "cc_reg_operand" "")
12511 (set (match_operand:SI 3 "gpc_reg_operand" "")
12512 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12513 "TARGET_32BIT && reload_completed"
12514 [(set (match_dup 3)
12515 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12517 (compare:CC (match_dup 3)
12522 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12523 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12524 [(match_operand 2 "cc_reg_operand" "y")
12526 (match_operand:SI 3 "const_int_operand" "n")))]
12530 int is_bit = ccr_bit (operands[1], 1);
12531 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12534 if (is_bit >= put_bit)
12535 count = is_bit - put_bit;
12537 count = 32 - (put_bit - is_bit);
12539 operands[4] = GEN_INT (count);
12540 operands[5] = GEN_INT (put_bit);
12542 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
12544 [(set (attr "type")
12545 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12546 (const_string "mfcrf")
12548 (const_string "mfcr")))
12549 (set_attr "length" "8")])
12552 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12554 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12555 [(match_operand 2 "cc_reg_operand" "y,y")
12557 (match_operand:SI 3 "const_int_operand" "n,n"))
12559 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
12560 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12565 int is_bit = ccr_bit (operands[1], 1);
12566 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12569 /* Force split for non-cc0 compare. */
12570 if (which_alternative == 1)
12573 if (is_bit >= put_bit)
12574 count = is_bit - put_bit;
12576 count = 32 - (put_bit - is_bit);
12578 operands[5] = GEN_INT (count);
12579 operands[6] = GEN_INT (put_bit);
12581 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
12583 [(set_attr "type" "delayed_compare")
12584 (set_attr "length" "8,16")])
12587 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12589 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12590 [(match_operand 2 "cc_reg_operand" "")
12592 (match_operand:SI 3 "const_int_operand" ""))
12594 (set (match_operand:SI 4 "gpc_reg_operand" "")
12595 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12598 [(set (match_dup 4)
12599 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12602 (compare:CC (match_dup 4)
12606 ;; There is a 3 cycle delay between consecutive mfcr instructions
12607 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
12610 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12611 (match_operator:SI 1 "scc_comparison_operator"
12612 [(match_operand 2 "cc_reg_operand" "y")
12614 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
12615 (match_operator:SI 4 "scc_comparison_operator"
12616 [(match_operand 5 "cc_reg_operand" "y")
12618 "REGNO (operands[2]) != REGNO (operands[5])"
12619 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
12620 [(set_attr "type" "mfcr")
12621 (set_attr "length" "12")])
12624 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12625 (match_operator:DI 1 "scc_comparison_operator"
12626 [(match_operand 2 "cc_reg_operand" "y")
12628 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12629 (match_operator:DI 4 "scc_comparison_operator"
12630 [(match_operand 5 "cc_reg_operand" "y")
12632 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
12633 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
12634 [(set_attr "type" "mfcr")
12635 (set_attr "length" "12")])
12637 ;; There are some scc insns that can be done directly, without a compare.
12638 ;; These are faster because they don't involve the communications between
12639 ;; the FXU and branch units. In fact, we will be replacing all of the
12640 ;; integer scc insns here or in the portable methods in emit_store_flag.
12642 ;; Also support (neg (scc ..)) since that construct is used to replace
12643 ;; branches, (plus (scc ..) ..) since that construct is common and
12644 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12645 ;; cases where it is no more expensive than (neg (scc ..)).
12647 ;; Have reload force a constant into a register for the simple insns that
12648 ;; otherwise won't accept constants. We do this because it is faster than
12649 ;; the cmp/mfcr sequence we would otherwise generate.
12651 (define_mode_attr scc_eq_op2 [(SI "rKLI")
12654 (define_insn_and_split "*eq<mode>"
12655 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12656 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
12657 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
12661 [(set (match_dup 0)
12662 (clz:GPR (match_dup 3)))
12664 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
12666 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12668 /* Use output operand as intermediate. */
12669 operands[3] = operands[0];
12671 if (logical_operand (operands[2], <MODE>mode))
12672 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12673 gen_rtx_XOR (<MODE>mode,
12674 operands[1], operands[2])));
12676 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12677 gen_rtx_PLUS (<MODE>mode, operands[1],
12678 negate_rtx (<MODE>mode,
12682 operands[3] = operands[1];
12684 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12687 (define_insn_and_split "*eq<mode>_compare"
12688 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12690 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12691 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
12693 (set (match_operand:P 0 "gpc_reg_operand" "=r")
12694 (eq:P (match_dup 1) (match_dup 2)))]
12695 "!TARGET_POWER && optimize_size"
12697 "!TARGET_POWER && optimize_size"
12698 [(set (match_dup 0)
12699 (clz:P (match_dup 4)))
12700 (parallel [(set (match_dup 3)
12701 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
12704 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
12706 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12708 /* Use output operand as intermediate. */
12709 operands[4] = operands[0];
12711 if (logical_operand (operands[2], <MODE>mode))
12712 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12713 gen_rtx_XOR (<MODE>mode,
12714 operands[1], operands[2])));
12716 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12717 gen_rtx_PLUS (<MODE>mode, operands[1],
12718 negate_rtx (<MODE>mode,
12722 operands[4] = operands[1];
12724 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12727 (define_insn "*eqsi_power"
12728 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
12729 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12730 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
12731 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
12734 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12735 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
12736 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12737 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12738 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
12739 [(set_attr "type" "three,two,three,three,three")
12740 (set_attr "length" "12,8,12,12,12")])
12742 ;; We have insns of the form shown by the first define_insn below. If
12743 ;; there is something inside the comparison operation, we must split it.
12745 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12746 (plus:SI (match_operator 1 "comparison_operator"
12747 [(match_operand:SI 2 "" "")
12748 (match_operand:SI 3
12749 "reg_or_cint_operand" "")])
12750 (match_operand:SI 4 "gpc_reg_operand" "")))
12751 (clobber (match_operand:SI 5 "register_operand" ""))]
12752 "! gpc_reg_operand (operands[2], SImode)"
12753 [(set (match_dup 5) (match_dup 2))
12754 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
12757 (define_insn "*plus_eqsi"
12758 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
12759 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12760 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
12761 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
12764 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12765 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
12766 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12767 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12768 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12769 [(set_attr "type" "three,two,three,three,three")
12770 (set_attr "length" "12,8,12,12,12")])
12772 (define_insn "*compare_plus_eqsi"
12773 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12776 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12777 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12778 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12780 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
12781 "TARGET_32BIT && optimize_size"
12783 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12784 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
12785 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12786 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12787 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12793 [(set_attr "type" "compare")
12794 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12797 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12800 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12801 (match_operand:SI 2 "scc_eq_operand" ""))
12802 (match_operand:SI 3 "gpc_reg_operand" ""))
12804 (clobber (match_scratch:SI 4 ""))]
12805 "TARGET_32BIT && optimize_size && reload_completed"
12806 [(set (match_dup 4)
12807 (plus:SI (eq:SI (match_dup 1)
12811 (compare:CC (match_dup 4)
12815 (define_insn "*plus_eqsi_compare"
12816 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12819 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12820 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12821 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12823 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12824 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12825 "TARGET_32BIT && optimize_size"
12827 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12828 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
12829 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12830 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12831 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12837 [(set_attr "type" "compare")
12838 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12841 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12844 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12845 (match_operand:SI 2 "scc_eq_operand" ""))
12846 (match_operand:SI 3 "gpc_reg_operand" ""))
12848 (set (match_operand:SI 0 "gpc_reg_operand" "")
12849 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12850 "TARGET_32BIT && optimize_size && reload_completed"
12851 [(set (match_dup 0)
12852 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12854 (compare:CC (match_dup 0)
12858 (define_insn "*neg_eq0<mode>"
12859 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12860 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12863 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
12864 [(set_attr "type" "two")
12865 (set_attr "length" "8")])
12867 (define_insn_and_split "*neg_eq<mode>"
12868 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12869 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12870 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
12874 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12876 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12878 /* Use output operand as intermediate. */
12879 operands[3] = operands[0];
12881 if (logical_operand (operands[2], <MODE>mode))
12882 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12883 gen_rtx_XOR (<MODE>mode,
12884 operands[1], operands[2])));
12886 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12887 gen_rtx_PLUS (<MODE>mode, operands[1],
12888 negate_rtx (<MODE>mode,
12892 operands[3] = operands[1];
12895 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
12896 ;; since it nabs/sr is just as fast.
12897 (define_insn "*ne0si"
12898 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12899 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12901 (clobber (match_scratch:SI 2 "=&r"))]
12902 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
12903 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
12904 [(set_attr "type" "two")
12905 (set_attr "length" "8")])
12907 (define_insn "*ne0di"
12908 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12909 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12911 (clobber (match_scratch:DI 2 "=&r"))]
12913 "addic %2,%1,-1\;subfe %0,%2,%1"
12914 [(set_attr "type" "two")
12915 (set_attr "length" "8")])
12917 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
12918 (define_insn "*plus_ne0si"
12919 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12920 (plus:SI (lshiftrt:SI
12921 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12923 (match_operand:SI 2 "gpc_reg_operand" "r")))
12924 (clobber (match_scratch:SI 3 "=&r"))]
12926 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
12927 [(set_attr "type" "two")
12928 (set_attr "length" "8")])
12930 (define_insn "*plus_ne0di"
12931 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12932 (plus:DI (lshiftrt:DI
12933 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12935 (match_operand:DI 2 "gpc_reg_operand" "r")))
12936 (clobber (match_scratch:DI 3 "=&r"))]
12938 "addic %3,%1,-1\;addze %0,%2"
12939 [(set_attr "type" "two")
12940 (set_attr "length" "8")])
12942 (define_insn "*compare_plus_ne0si"
12943 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12945 (plus:SI (lshiftrt:SI
12946 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12948 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12950 (clobber (match_scratch:SI 3 "=&r,&r"))
12951 (clobber (match_scratch:SI 4 "=X,&r"))]
12954 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
12956 [(set_attr "type" "compare")
12957 (set_attr "length" "8,12")])
12960 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12962 (plus:SI (lshiftrt:SI
12963 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12965 (match_operand:SI 2 "gpc_reg_operand" ""))
12967 (clobber (match_scratch:SI 3 ""))
12968 (clobber (match_scratch:SI 4 ""))]
12969 "TARGET_32BIT && reload_completed"
12970 [(parallel [(set (match_dup 3)
12971 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
12974 (clobber (match_dup 4))])
12976 (compare:CC (match_dup 3)
12980 (define_insn "*compare_plus_ne0di"
12981 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12983 (plus:DI (lshiftrt:DI
12984 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12986 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12988 (clobber (match_scratch:DI 3 "=&r,&r"))]
12991 addic %3,%1,-1\;addze. %3,%2
12993 [(set_attr "type" "compare")
12994 (set_attr "length" "8,12")])
12997 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12999 (plus:DI (lshiftrt:DI
13000 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
13002 (match_operand:DI 2 "gpc_reg_operand" ""))
13004 (clobber (match_scratch:DI 3 ""))]
13005 "TARGET_64BIT && reload_completed"
13006 [(set (match_dup 3)
13007 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
13011 (compare:CC (match_dup 3)
13015 (define_insn "*plus_ne0si_compare"
13016 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13018 (plus:SI (lshiftrt:SI
13019 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
13021 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13023 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13024 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
13026 (clobber (match_scratch:SI 3 "=&r,&r"))]
13029 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
13031 [(set_attr "type" "compare")
13032 (set_attr "length" "8,12")])
13035 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13037 (plus:SI (lshiftrt:SI
13038 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
13040 (match_operand:SI 2 "gpc_reg_operand" ""))
13042 (set (match_operand:SI 0 "gpc_reg_operand" "")
13043 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
13045 (clobber (match_scratch:SI 3 ""))]
13046 "TARGET_32BIT && reload_completed"
13047 [(parallel [(set (match_dup 0)
13048 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
13050 (clobber (match_dup 3))])
13052 (compare:CC (match_dup 0)
13056 (define_insn "*plus_ne0di_compare"
13057 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13059 (plus:DI (lshiftrt:DI
13060 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
13062 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13064 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13065 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
13067 (clobber (match_scratch:DI 3 "=&r,&r"))]
13070 addic %3,%1,-1\;addze. %0,%2
13072 [(set_attr "type" "compare")
13073 (set_attr "length" "8,12")])
13076 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
13078 (plus:DI (lshiftrt:DI
13079 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
13081 (match_operand:DI 2 "gpc_reg_operand" ""))
13083 (set (match_operand:DI 0 "gpc_reg_operand" "")
13084 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
13086 (clobber (match_scratch:DI 3 ""))]
13087 "TARGET_64BIT && reload_completed"
13088 [(parallel [(set (match_dup 0)
13089 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
13091 (clobber (match_dup 3))])
13093 (compare:CC (match_dup 0)
13098 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13099 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13100 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
13101 (clobber (match_scratch:SI 3 "=r,X"))]
13104 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
13105 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
13106 [(set_attr "length" "12")])
13109 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13111 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13112 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13114 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
13115 (le:SI (match_dup 1) (match_dup 2)))
13116 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
13119 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13120 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
13123 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
13124 (set_attr "length" "12,12,16,16")])
13127 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13129 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13130 (match_operand:SI 2 "reg_or_short_operand" ""))
13132 (set (match_operand:SI 0 "gpc_reg_operand" "")
13133 (le:SI (match_dup 1) (match_dup 2)))
13134 (clobber (match_scratch:SI 3 ""))]
13135 "TARGET_POWER && reload_completed"
13136 [(parallel [(set (match_dup 0)
13137 (le:SI (match_dup 1) (match_dup 2)))
13138 (clobber (match_dup 3))])
13140 (compare:CC (match_dup 0)
13145 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13146 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13147 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
13148 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
13151 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13152 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
13153 [(set_attr "length" "12")])
13156 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13158 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13159 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13160 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13162 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13165 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13166 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
13169 [(set_attr "type" "compare")
13170 (set_attr "length" "12,12,16,16")])
13173 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13175 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13176 (match_operand:SI 2 "reg_or_short_operand" ""))
13177 (match_operand:SI 3 "gpc_reg_operand" ""))
13179 (clobber (match_scratch:SI 4 ""))]
13180 "TARGET_POWER && reload_completed"
13181 [(set (match_dup 4)
13182 (plus:SI (le:SI (match_dup 1) (match_dup 2))
13185 (compare:CC (match_dup 4)
13190 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13192 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13193 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13194 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13196 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13197 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13200 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13201 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
13204 [(set_attr "type" "compare")
13205 (set_attr "length" "12,12,16,16")])
13208 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13210 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13211 (match_operand:SI 2 "reg_or_short_operand" ""))
13212 (match_operand:SI 3 "gpc_reg_operand" ""))
13214 (set (match_operand:SI 0 "gpc_reg_operand" "")
13215 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13216 "TARGET_POWER && reload_completed"
13217 [(set (match_dup 0)
13218 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13220 (compare:CC (match_dup 0)
13225 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13226 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13227 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
13230 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
13231 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
13232 [(set_attr "length" "12")])
13234 (define_insn "*leu<mode>"
13235 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13236 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13237 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13239 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
13240 [(set_attr "type" "three")
13241 (set_attr "length" "12")])
13243 (define_insn "*leu<mode>_compare"
13244 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13246 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13247 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13249 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13250 (leu:P (match_dup 1) (match_dup 2)))]
13253 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13255 [(set_attr "type" "compare")
13256 (set_attr "length" "12,16")])
13259 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13261 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
13262 (match_operand:P 2 "reg_or_short_operand" ""))
13264 (set (match_operand:P 0 "gpc_reg_operand" "")
13265 (leu:P (match_dup 1) (match_dup 2)))]
13267 [(set (match_dup 0)
13268 (leu:P (match_dup 1) (match_dup 2)))
13270 (compare:CC (match_dup 0)
13274 (define_insn "*plus_leu<mode>"
13275 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13276 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13277 (match_operand:P 2 "reg_or_short_operand" "rI"))
13278 (match_operand:P 3 "gpc_reg_operand" "r")))]
13280 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
13281 [(set_attr "type" "two")
13282 (set_attr "length" "8")])
13285 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13287 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13288 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13289 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13291 (clobber (match_scratch:SI 4 "=&r,&r"))]
13294 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
13296 [(set_attr "type" "compare")
13297 (set_attr "length" "8,12")])
13300 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13302 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13303 (match_operand:SI 2 "reg_or_short_operand" ""))
13304 (match_operand:SI 3 "gpc_reg_operand" ""))
13306 (clobber (match_scratch:SI 4 ""))]
13307 "TARGET_32BIT && reload_completed"
13308 [(set (match_dup 4)
13309 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
13312 (compare:CC (match_dup 4)
13317 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13319 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13320 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13321 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13323 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13324 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13327 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
13329 [(set_attr "type" "compare")
13330 (set_attr "length" "8,12")])
13333 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13335 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13336 (match_operand:SI 2 "reg_or_short_operand" ""))
13337 (match_operand:SI 3 "gpc_reg_operand" ""))
13339 (set (match_operand:SI 0 "gpc_reg_operand" "")
13340 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13341 "TARGET_32BIT && reload_completed"
13342 [(set (match_dup 0)
13343 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13345 (compare:CC (match_dup 0)
13349 (define_insn "*neg_leu<mode>"
13350 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13351 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13352 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13354 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
13355 [(set_attr "type" "three")
13356 (set_attr "length" "12")])
13358 (define_insn "*and_neg_leu<mode>"
13359 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13361 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13362 (match_operand:P 2 "reg_or_short_operand" "rI")))
13363 (match_operand:P 3 "gpc_reg_operand" "r")))]
13365 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13366 [(set_attr "type" "three")
13367 (set_attr "length" "12")])
13370 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13373 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13374 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13375 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13377 (clobber (match_scratch:SI 4 "=&r,&r"))]
13380 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13382 [(set_attr "type" "compare")
13383 (set_attr "length" "12,16")])
13386 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13389 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13390 (match_operand:SI 2 "reg_or_short_operand" "")))
13391 (match_operand:SI 3 "gpc_reg_operand" ""))
13393 (clobber (match_scratch:SI 4 ""))]
13394 "TARGET_32BIT && reload_completed"
13395 [(set (match_dup 4)
13396 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13399 (compare:CC (match_dup 4)
13404 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13407 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13408 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13409 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13411 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13412 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13415 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13417 [(set_attr "type" "compare")
13418 (set_attr "length" "12,16")])
13421 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13424 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13425 (match_operand:SI 2 "reg_or_short_operand" "")))
13426 (match_operand:SI 3 "gpc_reg_operand" ""))
13428 (set (match_operand:SI 0 "gpc_reg_operand" "")
13429 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13430 "TARGET_32BIT && reload_completed"
13431 [(set (match_dup 0)
13432 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13435 (compare:CC (match_dup 0)
13440 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13441 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13442 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13444 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13445 [(set_attr "length" "12")])
13448 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13450 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13451 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13453 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13454 (lt:SI (match_dup 1) (match_dup 2)))]
13457 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13459 [(set_attr "type" "delayed_compare")
13460 (set_attr "length" "12,16")])
13463 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13465 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13466 (match_operand:SI 2 "reg_or_short_operand" ""))
13468 (set (match_operand:SI 0 "gpc_reg_operand" "")
13469 (lt:SI (match_dup 1) (match_dup 2)))]
13470 "TARGET_POWER && reload_completed"
13471 [(set (match_dup 0)
13472 (lt:SI (match_dup 1) (match_dup 2)))
13474 (compare:CC (match_dup 0)
13479 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13480 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13481 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13482 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13484 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13485 [(set_attr "length" "12")])
13488 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13490 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13491 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13492 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13494 (clobber (match_scratch:SI 4 "=&r,&r"))]
13497 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13499 [(set_attr "type" "compare")
13500 (set_attr "length" "12,16")])
13503 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13505 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13506 (match_operand:SI 2 "reg_or_short_operand" ""))
13507 (match_operand:SI 3 "gpc_reg_operand" ""))
13509 (clobber (match_scratch:SI 4 ""))]
13510 "TARGET_POWER && reload_completed"
13511 [(set (match_dup 4)
13512 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
13515 (compare:CC (match_dup 4)
13520 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13522 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13523 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13524 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13526 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13527 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13530 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13532 [(set_attr "type" "compare")
13533 (set_attr "length" "12,16")])
13536 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13538 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13539 (match_operand:SI 2 "reg_or_short_operand" ""))
13540 (match_operand:SI 3 "gpc_reg_operand" ""))
13542 (set (match_operand:SI 0 "gpc_reg_operand" "")
13543 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13544 "TARGET_POWER && reload_completed"
13545 [(set (match_dup 0)
13546 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13548 (compare:CC (match_dup 0)
13553 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13554 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13555 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13557 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13558 [(set_attr "length" "12")])
13560 (define_insn_and_split "*ltu<mode>"
13561 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13562 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13563 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13567 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13568 (set (match_dup 0) (neg:P (match_dup 0)))]
13571 (define_insn_and_split "*ltu<mode>_compare"
13572 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13574 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13575 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13577 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13578 (ltu:P (match_dup 1) (match_dup 2)))]
13582 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13583 (parallel [(set (match_dup 3)
13584 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13585 (set (match_dup 0) (neg:P (match_dup 0)))])]
13588 (define_insn_and_split "*plus_ltu<mode>"
13589 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
13590 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13591 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13592 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
13595 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13596 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13597 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13600 (define_insn_and_split "*plus_ltu<mode>_compare"
13601 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13603 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13604 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13605 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13607 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13608 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13611 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13612 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13613 (parallel [(set (match_dup 4)
13614 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13616 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13619 (define_insn "*neg_ltu<mode>"
13620 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13621 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13622 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
13625 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
13626 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
13627 [(set_attr "type" "two")
13628 (set_attr "length" "8")])
13631 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13632 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13633 (match_operand:SI 2 "reg_or_short_operand" "rI")))
13634 (clobber (match_scratch:SI 3 "=r"))]
13636 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
13637 [(set_attr "length" "12")])
13640 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13642 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13643 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13645 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13646 (ge:SI (match_dup 1) (match_dup 2)))
13647 (clobber (match_scratch:SI 3 "=r,r"))]
13650 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13652 [(set_attr "type" "compare")
13653 (set_attr "length" "12,16")])
13656 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13658 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13659 (match_operand:SI 2 "reg_or_short_operand" ""))
13661 (set (match_operand:SI 0 "gpc_reg_operand" "")
13662 (ge:SI (match_dup 1) (match_dup 2)))
13663 (clobber (match_scratch:SI 3 ""))]
13664 "TARGET_POWER && reload_completed"
13665 [(parallel [(set (match_dup 0)
13666 (ge:SI (match_dup 1) (match_dup 2)))
13667 (clobber (match_dup 3))])
13669 (compare:CC (match_dup 0)
13674 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13675 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13676 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13677 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13679 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
13680 [(set_attr "length" "12")])
13683 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13685 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13686 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13687 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13689 (clobber (match_scratch:SI 4 "=&r,&r"))]
13692 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13694 [(set_attr "type" "compare")
13695 (set_attr "length" "12,16")])
13698 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13700 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13701 (match_operand:SI 2 "reg_or_short_operand" ""))
13702 (match_operand:SI 3 "gpc_reg_operand" ""))
13704 (clobber (match_scratch:SI 4 ""))]
13705 "TARGET_POWER && reload_completed"
13706 [(set (match_dup 4)
13707 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
13710 (compare:CC (match_dup 4)
13715 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13717 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13718 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13719 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13721 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13722 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13725 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13727 [(set_attr "type" "compare")
13728 (set_attr "length" "12,16")])
13731 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13733 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13734 (match_operand:SI 2 "reg_or_short_operand" ""))
13735 (match_operand:SI 3 "gpc_reg_operand" ""))
13737 (set (match_operand:SI 0 "gpc_reg_operand" "")
13738 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13739 "TARGET_POWER && reload_completed"
13740 [(set (match_dup 0)
13741 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13743 (compare:CC (match_dup 0)
13748 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13749 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13750 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13752 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
13753 [(set_attr "length" "12")])
13755 (define_insn "*geu<mode>"
13756 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13757 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13758 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13761 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
13762 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
13763 [(set_attr "type" "three")
13764 (set_attr "length" "12")])
13766 (define_insn "*geu<mode>_compare"
13767 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13769 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13770 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13772 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13773 (geu:P (match_dup 1) (match_dup 2)))]
13776 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13777 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13780 [(set_attr "type" "compare")
13781 (set_attr "length" "12,12,16,16")])
13784 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
13786 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
13787 (match_operand:P 2 "reg_or_neg_short_operand" ""))
13789 (set (match_operand:P 0 "gpc_reg_operand" "")
13790 (geu:P (match_dup 1) (match_dup 2)))]
13792 [(set (match_dup 0)
13793 (geu:P (match_dup 1) (match_dup 2)))
13795 (compare:CC (match_dup 0)
13799 (define_insn "*plus_geu<mode>"
13800 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13801 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13802 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13803 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13806 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
13807 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
13808 [(set_attr "type" "two")
13809 (set_attr "length" "8")])
13812 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13814 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13815 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13816 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13818 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13821 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
13822 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
13825 [(set_attr "type" "compare")
13826 (set_attr "length" "8,8,12,12")])
13829 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13831 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13832 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13833 (match_operand:SI 3 "gpc_reg_operand" ""))
13835 (clobber (match_scratch:SI 4 ""))]
13836 "TARGET_32BIT && reload_completed"
13837 [(set (match_dup 4)
13838 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13841 (compare:CC (match_dup 4)
13846 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13848 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13849 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13850 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13852 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13853 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13856 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
13857 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
13860 [(set_attr "type" "compare")
13861 (set_attr "length" "8,8,12,12")])
13864 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13866 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13867 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13868 (match_operand:SI 3 "gpc_reg_operand" ""))
13870 (set (match_operand:SI 0 "gpc_reg_operand" "")
13871 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13872 "TARGET_32BIT && reload_completed"
13873 [(set (match_dup 0)
13874 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13876 (compare:CC (match_dup 0)
13880 (define_insn "*neg_geu<mode>"
13881 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13882 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13883 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13886 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
13887 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
13888 [(set_attr "type" "three")
13889 (set_attr "length" "12")])
13891 (define_insn "*and_neg_geu<mode>"
13892 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13894 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13895 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13896 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13899 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
13900 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13901 [(set_attr "type" "three")
13902 (set_attr "length" "12")])
13905 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13908 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13909 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13910 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13912 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13915 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13916 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13919 [(set_attr "type" "compare")
13920 (set_attr "length" "12,12,16,16")])
13923 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13926 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13927 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13928 (match_operand:SI 3 "gpc_reg_operand" ""))
13930 (clobber (match_scratch:SI 4 ""))]
13931 "TARGET_32BIT && reload_completed"
13932 [(set (match_dup 4)
13933 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13936 (compare:CC (match_dup 4)
13941 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13944 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13945 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13946 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13948 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13949 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13952 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13953 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13956 [(set_attr "type" "compare")
13957 (set_attr "length" "12,12,16,16")])
13960 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13963 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13964 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13965 (match_operand:SI 3 "gpc_reg_operand" ""))
13967 (set (match_operand:SI 0 "gpc_reg_operand" "")
13968 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13969 "TARGET_32BIT && reload_completed"
13970 [(set (match_dup 0)
13971 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13973 (compare:CC (match_dup 0)
13978 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13979 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13980 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13982 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13983 [(set_attr "length" "12")])
13986 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13988 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13989 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13991 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13992 (gt:SI (match_dup 1) (match_dup 2)))]
13995 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13997 [(set_attr "type" "delayed_compare")
13998 (set_attr "length" "12,16")])
14001 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14003 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14004 (match_operand:SI 2 "reg_or_short_operand" ""))
14006 (set (match_operand:SI 0 "gpc_reg_operand" "")
14007 (gt:SI (match_dup 1) (match_dup 2)))]
14008 "TARGET_POWER && reload_completed"
14009 [(set (match_dup 0)
14010 (gt:SI (match_dup 1) (match_dup 2)))
14012 (compare:CC (match_dup 0)
14016 (define_insn "*plus_gt0<mode>"
14017 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14018 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
14020 (match_operand:P 2 "gpc_reg_operand" "r")))]
14022 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
14023 [(set_attr "type" "three")
14024 (set_attr "length" "12")])
14027 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14029 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14031 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14033 (clobber (match_scratch:SI 3 "=&r,&r"))]
14036 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
14038 [(set_attr "type" "compare")
14039 (set_attr "length" "12,16")])
14042 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14044 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14046 (match_operand:SI 2 "gpc_reg_operand" ""))
14048 (clobber (match_scratch:SI 3 ""))]
14049 "TARGET_32BIT && reload_completed"
14050 [(set (match_dup 3)
14051 (plus:SI (gt:SI (match_dup 1) (const_int 0))
14054 (compare:CC (match_dup 3)
14059 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14061 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
14063 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14065 (clobber (match_scratch:DI 3 "=&r,&r"))]
14068 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
14070 [(set_attr "type" "compare")
14071 (set_attr "length" "12,16")])
14074 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
14076 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
14078 (match_operand:DI 2 "gpc_reg_operand" ""))
14080 (clobber (match_scratch:DI 3 ""))]
14081 "TARGET_64BIT && reload_completed"
14082 [(set (match_dup 3)
14083 (plus:DI (gt:DI (match_dup 1) (const_int 0))
14086 (compare:CC (match_dup 3)
14091 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14093 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14095 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14097 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14098 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
14101 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
14103 [(set_attr "type" "compare")
14104 (set_attr "length" "12,16")])
14107 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14109 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14111 (match_operand:SI 2 "gpc_reg_operand" ""))
14113 (set (match_operand:SI 0 "gpc_reg_operand" "")
14114 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
14115 "TARGET_32BIT && reload_completed"
14116 [(set (match_dup 0)
14117 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
14119 (compare:CC (match_dup 0)
14124 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14126 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
14128 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14130 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
14131 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
14134 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
14136 [(set_attr "type" "compare")
14137 (set_attr "length" "12,16")])
14140 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14142 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
14144 (match_operand:DI 2 "gpc_reg_operand" ""))
14146 (set (match_operand:DI 0 "gpc_reg_operand" "")
14147 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
14148 "TARGET_64BIT && reload_completed"
14149 [(set (match_dup 0)
14150 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
14152 (compare:CC (match_dup 0)
14157 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
14158 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14159 (match_operand:SI 2 "reg_or_short_operand" "r"))
14160 (match_operand:SI 3 "gpc_reg_operand" "r")))]
14162 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
14163 [(set_attr "length" "12")])
14166 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14168 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14169 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14170 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14172 (clobber (match_scratch:SI 4 "=&r,&r"))]
14175 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
14177 [(set_attr "type" "compare")
14178 (set_attr "length" "12,16")])
14181 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14183 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14184 (match_operand:SI 2 "reg_or_short_operand" ""))
14185 (match_operand:SI 3 "gpc_reg_operand" ""))
14187 (clobber (match_scratch:SI 4 ""))]
14188 "TARGET_POWER && reload_completed"
14189 [(set (match_dup 4)
14190 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14192 (compare:CC (match_dup 4)
14197 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14199 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14200 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14201 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14203 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14204 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14207 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
14209 [(set_attr "type" "compare")
14210 (set_attr "length" "12,16")])
14213 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14215 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14216 (match_operand:SI 2 "reg_or_short_operand" ""))
14217 (match_operand:SI 3 "gpc_reg_operand" ""))
14219 (set (match_operand:SI 0 "gpc_reg_operand" "")
14220 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14221 "TARGET_POWER && reload_completed"
14222 [(set (match_dup 0)
14223 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14225 (compare:CC (match_dup 0)
14230 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14231 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14232 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
14234 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
14235 [(set_attr "length" "12")])
14237 (define_insn_and_split "*gtu<mode>"
14238 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14239 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14240 (match_operand:P 2 "reg_or_short_operand" "rI")))]
14244 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14245 (set (match_dup 0) (neg:P (match_dup 0)))]
14248 (define_insn_and_split "*gtu<mode>_compare"
14249 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14251 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14252 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
14254 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14255 (gtu:P (match_dup 1) (match_dup 2)))]
14259 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14260 (parallel [(set (match_dup 3)
14261 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
14262 (set (match_dup 0) (neg:P (match_dup 0)))])]
14265 (define_insn_and_split "*plus_gtu<mode>"
14266 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14267 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14268 (match_operand:P 2 "reg_or_short_operand" "rI"))
14269 (match_operand:P 3 "reg_or_short_operand" "rI")))]
14272 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14273 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14274 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
14277 (define_insn_and_split "*plus_gtu<mode>_compare"
14278 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14280 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14281 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
14282 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14284 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14285 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14288 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14289 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14290 (parallel [(set (match_dup 4)
14291 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14293 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14296 (define_insn "*neg_gtu<mode>"
14297 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14298 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14299 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
14301 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
14302 [(set_attr "type" "two")
14303 (set_attr "length" "8")])
14306 ;; Define both directions of branch and return. If we need a reload
14307 ;; register, we'd rather use CR0 since it is much easier to copy a
14308 ;; register CC value to there.
14312 (if_then_else (match_operator 1 "branch_comparison_operator"
14314 "cc_reg_operand" "y")
14316 (label_ref (match_operand 0 "" ""))
14321 return output_cbranch (operands[1], \"%l0\", 0, insn);
14323 [(set_attr "type" "branch")])
14327 (if_then_else (match_operator 0 "branch_comparison_operator"
14329 "cc_reg_operand" "y")
14336 return output_cbranch (operands[0], NULL, 0, insn);
14338 [(set_attr "type" "jmpreg")
14339 (set_attr "length" "4")])
14343 (if_then_else (match_operator 1 "branch_comparison_operator"
14345 "cc_reg_operand" "y")
14348 (label_ref (match_operand 0 "" ""))))]
14352 return output_cbranch (operands[1], \"%l0\", 1, insn);
14354 [(set_attr "type" "branch")])
14358 (if_then_else (match_operator 0 "branch_comparison_operator"
14360 "cc_reg_operand" "y")
14367 return output_cbranch (operands[0], NULL, 1, insn);
14369 [(set_attr "type" "jmpreg")
14370 (set_attr "length" "4")])
14372 ;; Logic on condition register values.
14374 ; This pattern matches things like
14375 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
14376 ; (eq:SI (reg:CCFP 68) (const_int 0)))
14378 ; which are generated by the branch logic.
14379 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
14381 (define_insn "*cceq_ior_compare"
14382 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14383 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
14384 [(match_operator:SI 2
14385 "branch_positive_comparison_operator"
14387 "cc_reg_operand" "y,y")
14389 (match_operator:SI 4
14390 "branch_positive_comparison_operator"
14392 "cc_reg_operand" "0,y")
14396 "cr%q1 %E0,%j2,%j4"
14397 [(set_attr "type" "cr_logical,delayed_cr")])
14399 ; Why is the constant -1 here, but 1 in the previous pattern?
14400 ; Because ~1 has all but the low bit set.
14402 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14403 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
14404 [(not:SI (match_operator:SI 2
14405 "branch_positive_comparison_operator"
14407 "cc_reg_operand" "y,y")
14409 (match_operator:SI 4
14410 "branch_positive_comparison_operator"
14412 "cc_reg_operand" "0,y")
14416 "cr%q1 %E0,%j2,%j4"
14417 [(set_attr "type" "cr_logical,delayed_cr")])
14419 (define_insn "*cceq_rev_compare"
14420 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14421 (compare:CCEQ (match_operator:SI 1
14422 "branch_positive_comparison_operator"
14424 "cc_reg_operand" "0,y")
14428 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
14429 [(set_attr "type" "cr_logical,delayed_cr")])
14431 ;; If we are comparing the result of two comparisons, this can be done
14432 ;; using creqv or crxor.
14434 (define_insn_and_split ""
14435 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14436 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
14437 [(match_operand 2 "cc_reg_operand" "y")
14439 (match_operator 3 "branch_comparison_operator"
14440 [(match_operand 4 "cc_reg_operand" "y")
14445 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14449 int positive_1, positive_2;
14451 positive_1 = branch_positive_comparison_operator (operands[1],
14452 GET_MODE (operands[1]));
14453 positive_2 = branch_positive_comparison_operator (operands[3],
14454 GET_MODE (operands[3]));
14457 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
14458 GET_CODE (operands[1])),
14460 operands[2], const0_rtx);
14461 else if (GET_MODE (operands[1]) != SImode)
14462 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14463 operands[2], const0_rtx);
14466 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
14467 GET_CODE (operands[3])),
14469 operands[4], const0_rtx);
14470 else if (GET_MODE (operands[3]) != SImode)
14471 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14472 operands[4], const0_rtx);
14474 if (positive_1 == positive_2)
14476 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14477 operands[5] = constm1_rtx;
14481 operands[5] = const1_rtx;
14485 ;; Unconditional branch and return.
14487 (define_insn "jump"
14489 (label_ref (match_operand 0 "" "")))]
14492 [(set_attr "type" "branch")])
14494 (define_insn "return"
14498 [(set_attr "type" "jmpreg")])
14500 (define_expand "indirect_jump"
14501 [(set (pc) (match_operand 0 "register_operand" ""))])
14503 (define_insn "*indirect_jump<mode>"
14504 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14509 [(set_attr "type" "jmpreg")])
14511 ;; Table jump for switch statements:
14512 (define_expand "tablejump"
14513 [(use (match_operand 0 "" ""))
14514 (use (label_ref (match_operand 1 "" "")))]
14519 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14521 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14525 (define_expand "tablejumpsi"
14526 [(set (match_dup 3)
14527 (plus:SI (match_operand:SI 0 "" "")
14529 (parallel [(set (pc) (match_dup 3))
14530 (use (label_ref (match_operand 1 "" "")))])]
14533 { operands[0] = force_reg (SImode, operands[0]);
14534 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
14535 operands[3] = gen_reg_rtx (SImode);
14538 (define_expand "tablejumpdi"
14539 [(set (match_dup 4)
14540 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
14542 (plus:DI (match_dup 4)
14544 (parallel [(set (pc) (match_dup 3))
14545 (use (label_ref (match_operand 1 "" "")))])]
14548 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
14549 operands[3] = gen_reg_rtx (DImode);
14550 operands[4] = gen_reg_rtx (DImode);
14553 (define_insn "*tablejump<mode>_internal1"
14555 (match_operand:P 0 "register_operand" "c,*l"))
14556 (use (label_ref (match_operand 1 "" "")))]
14561 [(set_attr "type" "jmpreg")])
14566 "{cror 0,0,0|nop}")
14568 ;; Define the subtract-one-and-jump insns, starting with the template
14569 ;; so loop.c knows what to generate.
14571 (define_expand "doloop_end"
14572 [(use (match_operand 0 "" "")) ; loop pseudo
14573 (use (match_operand 1 "" "")) ; iterations; zero if unknown
14574 (use (match_operand 2 "" "")) ; max iterations
14575 (use (match_operand 3 "" "")) ; loop level
14576 (use (match_operand 4 "" ""))] ; label
14580 /* Only use this on innermost loops. */
14581 if (INTVAL (operands[3]) > 1)
14585 if (GET_MODE (operands[0]) != DImode)
14587 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
14591 if (GET_MODE (operands[0]) != SImode)
14593 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
14598 (define_expand "ctr<mode>"
14599 [(parallel [(set (pc)
14600 (if_then_else (ne (match_operand:P 0 "register_operand" "")
14602 (label_ref (match_operand 1 "" ""))
14605 (plus:P (match_dup 0)
14607 (clobber (match_scratch:CC 2 ""))
14608 (clobber (match_scratch:P 3 ""))])]
14612 ;; We need to be able to do this for any operand, including MEM, or we
14613 ;; will cause reload to blow up since we don't allow output reloads on
14615 ;; For the length attribute to be calculated correctly, the
14616 ;; label MUST be operand 0.
14618 (define_insn "*ctr<mode>_internal1"
14620 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14622 (label_ref (match_operand 0 "" ""))
14624 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14625 (plus:P (match_dup 1)
14627 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14628 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14632 if (which_alternative != 0)
14634 else if (get_attr_length (insn) == 4)
14635 return \"{bdn|bdnz} %l0\";
14637 return \"bdz $+8\;b %l0\";
14639 [(set_attr "type" "branch")
14640 (set_attr "length" "*,12,16,16")])
14642 (define_insn "*ctr<mode>_internal2"
14644 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14647 (label_ref (match_operand 0 "" ""))))
14648 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14649 (plus:P (match_dup 1)
14651 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14652 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14656 if (which_alternative != 0)
14658 else if (get_attr_length (insn) == 4)
14659 return \"bdz %l0\";
14661 return \"{bdn|bdnz} $+8\;b %l0\";
14663 [(set_attr "type" "branch")
14664 (set_attr "length" "*,12,16,16")])
14666 ;; Similar but use EQ
14668 (define_insn "*ctr<mode>_internal5"
14670 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14672 (label_ref (match_operand 0 "" ""))
14674 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14675 (plus:P (match_dup 1)
14677 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14678 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14682 if (which_alternative != 0)
14684 else if (get_attr_length (insn) == 4)
14685 return \"bdz %l0\";
14687 return \"{bdn|bdnz} $+8\;b %l0\";
14689 [(set_attr "type" "branch")
14690 (set_attr "length" "*,12,16,16")])
14692 (define_insn "*ctr<mode>_internal6"
14694 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14697 (label_ref (match_operand 0 "" ""))))
14698 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14699 (plus:P (match_dup 1)
14701 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14702 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14706 if (which_alternative != 0)
14708 else if (get_attr_length (insn) == 4)
14709 return \"{bdn|bdnz} %l0\";
14711 return \"bdz $+8\;b %l0\";
14713 [(set_attr "type" "branch")
14714 (set_attr "length" "*,12,16,16")])
14716 ;; Now the splitters if we could not allocate the CTR register
14720 (if_then_else (match_operator 2 "comparison_operator"
14721 [(match_operand:P 1 "gpc_reg_operand" "")
14723 (match_operand 5 "" "")
14724 (match_operand 6 "" "")))
14725 (set (match_operand:P 0 "gpc_reg_operand" "")
14726 (plus:P (match_dup 1) (const_int -1)))
14727 (clobber (match_scratch:CC 3 ""))
14728 (clobber (match_scratch:P 4 ""))]
14730 [(parallel [(set (match_dup 3)
14731 (compare:CC (plus:P (match_dup 1)
14735 (plus:P (match_dup 1)
14737 (set (pc) (if_then_else (match_dup 7)
14741 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14742 operands[3], const0_rtx); }")
14746 (if_then_else (match_operator 2 "comparison_operator"
14747 [(match_operand:P 1 "gpc_reg_operand" "")
14749 (match_operand 5 "" "")
14750 (match_operand 6 "" "")))
14751 (set (match_operand:P 0 "nonimmediate_operand" "")
14752 (plus:P (match_dup 1) (const_int -1)))
14753 (clobber (match_scratch:CC 3 ""))
14754 (clobber (match_scratch:P 4 ""))]
14755 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
14756 [(parallel [(set (match_dup 3)
14757 (compare:CC (plus:P (match_dup 1)
14761 (plus:P (match_dup 1)
14765 (set (pc) (if_then_else (match_dup 7)
14769 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14770 operands[3], const0_rtx); }")
14772 (define_insn "trap"
14773 [(trap_if (const_int 1) (const_int 0))]
14776 [(set_attr "type" "trap")])
14778 (define_expand "conditional_trap"
14779 [(trap_if (match_operator 0 "trap_comparison_operator"
14780 [(match_dup 2) (match_dup 3)])
14781 (match_operand 1 "const_int_operand" ""))]
14783 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14784 operands[2] = rs6000_compare_op0;
14785 operands[3] = rs6000_compare_op1;")
14788 [(trap_if (match_operator 0 "trap_comparison_operator"
14789 [(match_operand:GPR 1 "register_operand" "r")
14790 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
14793 "{t|t<wd>}%V0%I2 %1,%2"
14794 [(set_attr "type" "trap")])
14796 ;; Insns related to generating the function prologue and epilogue.
14798 (define_expand "prologue"
14799 [(use (const_int 0))]
14800 "TARGET_SCHED_PROLOG"
14803 rs6000_emit_prologue ();
14807 (define_insn "*movesi_from_cr_one"
14808 [(match_parallel 0 "mfcr_operation"
14809 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14810 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14811 (match_operand 3 "immediate_operand" "n")]
14812 UNSPEC_MOVESI_FROM_CR))])]
14818 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14820 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14821 operands[4] = GEN_INT (mask);
14822 output_asm_insn (\"mfcr %1,%4\", operands);
14826 [(set_attr "type" "mfcrf")])
14828 (define_insn "movesi_from_cr"
14829 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14830 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
14831 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
14832 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
14833 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
14834 UNSPEC_MOVESI_FROM_CR))]
14837 [(set_attr "type" "mfcr")])
14839 (define_insn "*stmw"
14840 [(match_parallel 0 "stmw_operation"
14841 [(set (match_operand:SI 1 "memory_operand" "=m")
14842 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14845 [(set_attr "type" "store_ux")])
14847 (define_insn "*save_gpregs_<mode>"
14848 [(match_parallel 0 "any_parallel_operand"
14849 [(clobber (reg:P 65))
14850 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14851 (use (match_operand:P 2 "gpc_reg_operand" "r"))
14852 (set (match_operand:P 3 "memory_operand" "=m")
14853 (match_operand:P 4 "gpc_reg_operand" "r"))])]
14856 [(set_attr "type" "branch")
14857 (set_attr "length" "4")])
14859 (define_insn "*save_fpregs_<mode>"
14860 [(match_parallel 0 "any_parallel_operand"
14861 [(clobber (reg:P 65))
14862 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14863 (use (match_operand:P 2 "gpc_reg_operand" "r"))
14864 (set (match_operand:DF 3 "memory_operand" "=m")
14865 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14868 [(set_attr "type" "branch")
14869 (set_attr "length" "4")])
14871 ; These are to explain that changes to the stack pointer should
14872 ; not be moved over stores to stack memory.
14873 (define_insn "stack_tie"
14874 [(set (match_operand:BLK 0 "memory_operand" "+m")
14875 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
14878 [(set_attr "length" "0")])
14881 (define_expand "epilogue"
14882 [(use (const_int 0))]
14883 "TARGET_SCHED_PROLOG"
14886 rs6000_emit_epilogue (FALSE);
14890 ; On some processors, doing the mtcrf one CC register at a time is
14891 ; faster (like on the 604e). On others, doing them all at once is
14892 ; faster; for instance, on the 601 and 750.
14894 (define_expand "movsi_to_cr_one"
14895 [(set (match_operand:CC 0 "cc_reg_operand" "")
14896 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
14897 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14899 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14901 (define_insn "*movsi_to_cr"
14902 [(match_parallel 0 "mtcrf_operation"
14903 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14904 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14905 (match_operand 3 "immediate_operand" "n")]
14906 UNSPEC_MOVESI_TO_CR))])]
14912 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14913 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14914 operands[4] = GEN_INT (mask);
14915 return \"mtcrf %4,%2\";
14917 [(set_attr "type" "mtcr")])
14919 (define_insn "*mtcrfsi"
14920 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14921 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14922 (match_operand 2 "immediate_operand" "n")]
14923 UNSPEC_MOVESI_TO_CR))]
14924 "GET_CODE (operands[0]) == REG
14925 && CR_REGNO_P (REGNO (operands[0]))
14926 && GET_CODE (operands[2]) == CONST_INT
14927 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14929 [(set_attr "type" "mtcr")])
14931 ; The load-multiple instructions have similar properties.
14932 ; Note that "load_multiple" is a name known to the machine-independent
14933 ; code that actually corresponds to the PowerPC load-string.
14935 (define_insn "*lmw"
14936 [(match_parallel 0 "lmw_operation"
14937 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14938 (match_operand:SI 2 "memory_operand" "m"))])]
14941 [(set_attr "type" "load_ux")
14942 (set_attr "cell_micro" "always")])
14944 (define_insn "*return_internal_<mode>"
14946 (use (match_operand:P 0 "register_operand" "lc"))]
14949 [(set_attr "type" "jmpreg")])
14951 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14952 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14954 (define_insn "*restore_gpregs_<mode>"
14955 [(match_parallel 0 "any_parallel_operand"
14956 [(clobber (match_operand:P 1 "register_operand" "=l"))
14957 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14958 (use (match_operand:P 3 "gpc_reg_operand" "r"))
14959 (set (match_operand:P 4 "gpc_reg_operand" "=r")
14960 (match_operand:P 5 "memory_operand" "m"))])]
14963 [(set_attr "type" "branch")
14964 (set_attr "length" "4")])
14966 (define_insn "*return_and_restore_gpregs_<mode>"
14967 [(match_parallel 0 "any_parallel_operand"
14969 (clobber (match_operand:P 1 "register_operand" "=l"))
14970 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14971 (use (match_operand:P 3 "gpc_reg_operand" "r"))
14972 (set (match_operand:P 4 "gpc_reg_operand" "=r")
14973 (match_operand:P 5 "memory_operand" "m"))])]
14976 [(set_attr "type" "branch")
14977 (set_attr "length" "4")])
14979 (define_insn "*return_and_restore_fpregs_<mode>"
14980 [(match_parallel 0 "any_parallel_operand"
14982 (clobber (match_operand:P 1 "register_operand" "=l"))
14983 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14984 (use (match_operand:P 3 "gpc_reg_operand" "r"))
14985 (set (match_operand:DF 4 "gpc_reg_operand" "=f")
14986 (match_operand:DF 5 "memory_operand" "m"))])]
14989 [(set_attr "type" "branch")
14990 (set_attr "length" "4")])
14992 ; This is used in compiling the unwind routines.
14993 (define_expand "eh_return"
14994 [(use (match_operand 0 "general_operand" ""))]
14999 emit_insn (gen_eh_set_lr_si (operands[0]));
15001 emit_insn (gen_eh_set_lr_di (operands[0]));
15005 ; We can't expand this before we know where the link register is stored.
15006 (define_insn "eh_set_lr_<mode>"
15007 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
15009 (clobber (match_scratch:P 1 "=&b"))]
15014 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
15015 (clobber (match_scratch 1 ""))]
15020 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
15024 (define_insn "prefetch"
15025 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
15026 (match_operand:SI 1 "const_int_operand" "n")
15027 (match_operand:SI 2 "const_int_operand" "n"))]
15031 if (GET_CODE (operands[0]) == REG)
15032 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
15033 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
15035 [(set_attr "type" "load")])
15038 (include "sync.md")
15039 (include "altivec.md")
15042 (include "paired.md")