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darwin-ldouble.c (__gcc_qunord): Define if __NO_FPRS__, not just if _SOFT_DOUBLE.
[thirdparty/gcc.git] / gcc / config / rs6000 / rs6000.md
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6
7 ;; This file is part of GCC.
8
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 2, or (at your
12 ;; option) any later version.
13
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
18
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the
21 ;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
22 ;; MA 02110-1301, USA.
23
24 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25
26 ;;
27 ;; UNSPEC usage
28 ;;
29
30 (define_constants
31 [(UNSPEC_FRSP 0) ; frsp for POWER machines
32 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
33 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
34 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
35 (UNSPEC_MOVSI_GOT 8)
36 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
37 (UNSPEC_FCTIWZ 10)
38 (UNSPEC_FRIM 11)
39 (UNSPEC_FRIN 12)
40 (UNSPEC_FRIP 13)
41 (UNSPEC_FRIZ 14)
42 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
43 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
44 (UNSPEC_TLSGD 17)
45 (UNSPEC_TLSLD 18)
46 (UNSPEC_MOVESI_FROM_CR 19)
47 (UNSPEC_MOVESI_TO_CR 20)
48 (UNSPEC_TLSDTPREL 21)
49 (UNSPEC_TLSDTPRELHA 22)
50 (UNSPEC_TLSDTPRELLO 23)
51 (UNSPEC_TLSGOTDTPREL 24)
52 (UNSPEC_TLSTPREL 25)
53 (UNSPEC_TLSTPRELHA 26)
54 (UNSPEC_TLSTPRELLO 27)
55 (UNSPEC_TLSGOTTPREL 28)
56 (UNSPEC_TLSTLS 29)
57 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
58 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
59 (UNSPEC_STFIWX 32)
60 (UNSPEC_POPCNTB 33)
61 (UNSPEC_FRES 34)
62 (UNSPEC_SP_SET 35)
63 (UNSPEC_SP_TEST 36)
64 (UNSPEC_SYNC 37)
65 (UNSPEC_LWSYNC 38)
66 (UNSPEC_ISYNC 39)
67 (UNSPEC_SYNC_OP 40)
68 (UNSPEC_ATOMIC 41)
69 (UNSPEC_CMPXCHG 42)
70 (UNSPEC_XCHG 43)
71 (UNSPEC_AND 44)
72 (UNSPEC_DLMZB 45)
73 (UNSPEC_DLMZB_CR 46)
74 (UNSPEC_DLMZB_STRLEN 47)
75 ])
76
77 ;;
78 ;; UNSPEC_VOLATILE usage
79 ;;
80
81 (define_constants
82 [(UNSPECV_BLOCK 0)
83 (UNSPECV_LL 1) ; load-locked
84 (UNSPECV_SC 2) ; store-conditional
85 (UNSPECV_EH_RR 9) ; eh_reg_restore
86 ])
87 \f
88 ;; Define an insn type attribute. This is used in function unit delay
89 ;; computations.
90 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr"
91 (const_string "integer"))
92
93 ;; Length (in bytes).
94 ; '(pc)' in the following doesn't include the instruction itself; it is
95 ; calculated as if the instruction had zero size.
96 (define_attr "length" ""
97 (if_then_else (eq_attr "type" "branch")
98 (if_then_else (and (ge (minus (match_dup 0) (pc))
99 (const_int -32768))
100 (lt (minus (match_dup 0) (pc))
101 (const_int 32764)))
102 (const_int 4)
103 (const_int 8))
104 (const_int 4)))
105
106 ;; Processor type -- this attribute must exactly match the processor_type
107 ;; enumeration in rs6000.h.
108
109 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5,power6,cell"
110 (const (symbol_ref "rs6000_cpu_attr")))
111
112
113 ;; If this instruction is microcoded on the CELL processor
114 ; The default for load and stores is conditional
115 ; The default for load extended and the recorded instructions is always microcoded
116 (define_attr "cell_micro" "not,conditional,always"
117 (if_then_else (ior (ior (eq_attr "type" "load")
118 (eq_attr "type" "store"))
119 (ior (eq_attr "type" "fpload")
120 (eq_attr "type" "fpstore")))
121 (const_string "conditional")
122 (if_then_else (ior (eq_attr "type" "load_ext")
123 (ior (eq_attr "type" "compare")
124 (eq_attr "type" "delayed_compare")))
125 (const_string "always")
126 (const_string "not"))))
127
128
129 (automata_option "ndfa")
130
131 (include "rios1.md")
132 (include "rios2.md")
133 (include "rs64.md")
134 (include "mpc.md")
135 (include "40x.md")
136 (include "440.md")
137 (include "603.md")
138 (include "6xx.md")
139 (include "7xx.md")
140 (include "7450.md")
141 (include "8540.md")
142 (include "power4.md")
143 (include "power5.md")
144 (include "power6.md")
145 (include "cell.md")
146
147 (include "predicates.md")
148 (include "constraints.md")
149
150 (include "darwin.md")
151
152 \f
153 ;; Mode macros
154
155 ; This mode macro allows :GPR to be used to indicate the allowable size
156 ; of whole values in GPRs.
157 (define_mode_macro GPR [SI (DI "TARGET_POWERPC64")])
158
159 ; Any supported integer mode.
160 (define_mode_macro INT [QI HI SI DI TI])
161
162 ; Any supported integer mode that fits in one register.
163 (define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")])
164
165 ; extend modes for DImode
166 (define_mode_macro QHSI [QI HI SI])
167
168 ; SImode or DImode, even if DImode doesn't fit in GPRs.
169 (define_mode_macro SDI [SI DI])
170
171 ; The size of a pointer. Also, the size of the value that a record-condition
172 ; (one with a '.') will compare.
173 (define_mode_macro P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
174
175 ; Any hardware-supported floating-point mode
176 (define_mode_macro FP [(SF "TARGET_HARD_FLOAT")
177 (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
178 (TF "!TARGET_IEEEQUAD
179 && TARGET_HARD_FLOAT
180 && (TARGET_FPRS || TARGET_E500_DOUBLE)
181 && TARGET_LONG_DOUBLE_128")])
182
183 ; Various instructions that come in SI and DI forms.
184 ; A generic w/d attribute, for things like cmpw/cmpd.
185 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
186
187 ; DImode bits
188 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
189
190 \f
191 ;; Start with fixed-point load and store insns. Here we put only the more
192 ;; complex forms. Basic data transfer is done later.
193
194 (define_expand "zero_extend<mode>di2"
195 [(set (match_operand:DI 0 "gpc_reg_operand" "")
196 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
197 "TARGET_POWERPC64"
198 "")
199
200 (define_insn "*zero_extend<mode>di2_internal1"
201 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
202 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
203 "TARGET_POWERPC64"
204 "@
205 l<wd>z%U1%X1 %0,%1
206 rldicl %0,%1,0,<dbits>"
207 [(set_attr "type" "load,*")])
208
209 (define_insn "*zero_extend<mode>di2_internal2"
210 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
211 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
212 (const_int 0)))
213 (clobber (match_scratch:DI 2 "=r,r"))]
214 "TARGET_64BIT"
215 "@
216 rldicl. %2,%1,0,<dbits>
217 #"
218 [(set_attr "type" "compare")
219 (set_attr "length" "4,8")])
220
221 (define_split
222 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
223 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
224 (const_int 0)))
225 (clobber (match_scratch:DI 2 ""))]
226 "TARGET_POWERPC64 && reload_completed"
227 [(set (match_dup 2)
228 (zero_extend:DI (match_dup 1)))
229 (set (match_dup 0)
230 (compare:CC (match_dup 2)
231 (const_int 0)))]
232 "")
233
234 (define_insn "*zero_extend<mode>di2_internal3"
235 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
236 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
237 (const_int 0)))
238 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
239 (zero_extend:DI (match_dup 1)))]
240 "TARGET_64BIT"
241 "@
242 rldicl. %0,%1,0,<dbits>
243 #"
244 [(set_attr "type" "compare")
245 (set_attr "length" "4,8")])
246
247 (define_split
248 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
249 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
250 (const_int 0)))
251 (set (match_operand:DI 0 "gpc_reg_operand" "")
252 (zero_extend:DI (match_dup 1)))]
253 "TARGET_POWERPC64 && reload_completed"
254 [(set (match_dup 0)
255 (zero_extend:DI (match_dup 1)))
256 (set (match_dup 2)
257 (compare:CC (match_dup 0)
258 (const_int 0)))]
259 "")
260
261 (define_insn "extendqidi2"
262 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
263 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
264 "TARGET_POWERPC64"
265 "extsb %0,%1"
266 [(set_attr "type" "exts")])
267
268 (define_insn ""
269 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
270 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
271 (const_int 0)))
272 (clobber (match_scratch:DI 2 "=r,r"))]
273 "TARGET_64BIT"
274 "@
275 extsb. %2,%1
276 #"
277 [(set_attr "type" "compare")
278 (set_attr "length" "4,8")])
279
280 (define_split
281 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
282 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
283 (const_int 0)))
284 (clobber (match_scratch:DI 2 ""))]
285 "TARGET_POWERPC64 && reload_completed"
286 [(set (match_dup 2)
287 (sign_extend:DI (match_dup 1)))
288 (set (match_dup 0)
289 (compare:CC (match_dup 2)
290 (const_int 0)))]
291 "")
292
293 (define_insn ""
294 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
295 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
296 (const_int 0)))
297 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
298 (sign_extend:DI (match_dup 1)))]
299 "TARGET_64BIT"
300 "@
301 extsb. %0,%1
302 #"
303 [(set_attr "type" "compare")
304 (set_attr "length" "4,8")])
305
306 (define_split
307 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
308 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
309 (const_int 0)))
310 (set (match_operand:DI 0 "gpc_reg_operand" "")
311 (sign_extend:DI (match_dup 1)))]
312 "TARGET_POWERPC64 && reload_completed"
313 [(set (match_dup 0)
314 (sign_extend:DI (match_dup 1)))
315 (set (match_dup 2)
316 (compare:CC (match_dup 0)
317 (const_int 0)))]
318 "")
319
320 (define_expand "extendhidi2"
321 [(set (match_operand:DI 0 "gpc_reg_operand" "")
322 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
323 "TARGET_POWERPC64"
324 "")
325
326 (define_insn ""
327 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
328 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
329 "TARGET_POWERPC64"
330 "@
331 lha%U1%X1 %0,%1
332 extsh %0,%1"
333 [(set_attr "type" "load_ext,exts")])
334
335 (define_insn ""
336 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
337 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
338 (const_int 0)))
339 (clobber (match_scratch:DI 2 "=r,r"))]
340 "TARGET_64BIT"
341 "@
342 extsh. %2,%1
343 #"
344 [(set_attr "type" "compare")
345 (set_attr "length" "4,8")])
346
347 (define_split
348 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
349 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
350 (const_int 0)))
351 (clobber (match_scratch:DI 2 ""))]
352 "TARGET_POWERPC64 && reload_completed"
353 [(set (match_dup 2)
354 (sign_extend:DI (match_dup 1)))
355 (set (match_dup 0)
356 (compare:CC (match_dup 2)
357 (const_int 0)))]
358 "")
359
360 (define_insn ""
361 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
362 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
363 (const_int 0)))
364 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
365 (sign_extend:DI (match_dup 1)))]
366 "TARGET_64BIT"
367 "@
368 extsh. %0,%1
369 #"
370 [(set_attr "type" "compare")
371 (set_attr "length" "4,8")])
372
373 (define_split
374 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
375 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
376 (const_int 0)))
377 (set (match_operand:DI 0 "gpc_reg_operand" "")
378 (sign_extend:DI (match_dup 1)))]
379 "TARGET_POWERPC64 && reload_completed"
380 [(set (match_dup 0)
381 (sign_extend:DI (match_dup 1)))
382 (set (match_dup 2)
383 (compare:CC (match_dup 0)
384 (const_int 0)))]
385 "")
386
387 (define_expand "extendsidi2"
388 [(set (match_operand:DI 0 "gpc_reg_operand" "")
389 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
390 "TARGET_POWERPC64"
391 "")
392
393 (define_insn ""
394 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
395 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
396 "TARGET_POWERPC64"
397 "@
398 lwa%U1%X1 %0,%1
399 extsw %0,%1"
400 [(set_attr "type" "load_ext,exts")])
401
402 (define_insn ""
403 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
404 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
405 (const_int 0)))
406 (clobber (match_scratch:DI 2 "=r,r"))]
407 "TARGET_64BIT"
408 "@
409 extsw. %2,%1
410 #"
411 [(set_attr "type" "compare")
412 (set_attr "length" "4,8")])
413
414 (define_split
415 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
416 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
417 (const_int 0)))
418 (clobber (match_scratch:DI 2 ""))]
419 "TARGET_POWERPC64 && reload_completed"
420 [(set (match_dup 2)
421 (sign_extend:DI (match_dup 1)))
422 (set (match_dup 0)
423 (compare:CC (match_dup 2)
424 (const_int 0)))]
425 "")
426
427 (define_insn ""
428 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
429 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
430 (const_int 0)))
431 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
432 (sign_extend:DI (match_dup 1)))]
433 "TARGET_64BIT"
434 "@
435 extsw. %0,%1
436 #"
437 [(set_attr "type" "compare")
438 (set_attr "length" "4,8")])
439
440 (define_split
441 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
442 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
443 (const_int 0)))
444 (set (match_operand:DI 0 "gpc_reg_operand" "")
445 (sign_extend:DI (match_dup 1)))]
446 "TARGET_POWERPC64 && reload_completed"
447 [(set (match_dup 0)
448 (sign_extend:DI (match_dup 1)))
449 (set (match_dup 2)
450 (compare:CC (match_dup 0)
451 (const_int 0)))]
452 "")
453
454 (define_expand "zero_extendqisi2"
455 [(set (match_operand:SI 0 "gpc_reg_operand" "")
456 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
457 ""
458 "")
459
460 (define_insn ""
461 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
462 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
463 ""
464 "@
465 lbz%U1%X1 %0,%1
466 {rlinm|rlwinm} %0,%1,0,0xff"
467 [(set_attr "type" "load,*")])
468
469 (define_insn ""
470 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
471 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
472 (const_int 0)))
473 (clobber (match_scratch:SI 2 "=r,r"))]
474 ""
475 "@
476 {andil.|andi.} %2,%1,0xff
477 #"
478 [(set_attr "type" "compare")
479 (set_attr "length" "4,8")])
480
481 (define_split
482 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
483 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
484 (const_int 0)))
485 (clobber (match_scratch:SI 2 ""))]
486 "reload_completed"
487 [(set (match_dup 2)
488 (zero_extend:SI (match_dup 1)))
489 (set (match_dup 0)
490 (compare:CC (match_dup 2)
491 (const_int 0)))]
492 "")
493
494 (define_insn ""
495 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
496 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
497 (const_int 0)))
498 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
499 (zero_extend:SI (match_dup 1)))]
500 ""
501 "@
502 {andil.|andi.} %0,%1,0xff
503 #"
504 [(set_attr "type" "compare")
505 (set_attr "length" "4,8")])
506
507 (define_split
508 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
509 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
510 (const_int 0)))
511 (set (match_operand:SI 0 "gpc_reg_operand" "")
512 (zero_extend:SI (match_dup 1)))]
513 "reload_completed"
514 [(set (match_dup 0)
515 (zero_extend:SI (match_dup 1)))
516 (set (match_dup 2)
517 (compare:CC (match_dup 0)
518 (const_int 0)))]
519 "")
520
521 (define_expand "extendqisi2"
522 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
523 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
524 ""
525 "
526 {
527 if (TARGET_POWERPC)
528 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
529 else if (TARGET_POWER)
530 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
531 else
532 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
533 DONE;
534 }")
535
536 (define_insn "extendqisi2_ppc"
537 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
538 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
539 "TARGET_POWERPC"
540 "extsb %0,%1"
541 [(set_attr "type" "exts")])
542
543 (define_insn ""
544 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
545 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
546 (const_int 0)))
547 (clobber (match_scratch:SI 2 "=r,r"))]
548 "TARGET_POWERPC"
549 "@
550 extsb. %2,%1
551 #"
552 [(set_attr "type" "compare")
553 (set_attr "length" "4,8")])
554
555 (define_split
556 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
557 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
558 (const_int 0)))
559 (clobber (match_scratch:SI 2 ""))]
560 "TARGET_POWERPC && reload_completed"
561 [(set (match_dup 2)
562 (sign_extend:SI (match_dup 1)))
563 (set (match_dup 0)
564 (compare:CC (match_dup 2)
565 (const_int 0)))]
566 "")
567
568 (define_insn ""
569 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
570 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
571 (const_int 0)))
572 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
573 (sign_extend:SI (match_dup 1)))]
574 "TARGET_POWERPC"
575 "@
576 extsb. %0,%1
577 #"
578 [(set_attr "type" "compare")
579 (set_attr "length" "4,8")])
580
581 (define_split
582 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
583 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
584 (const_int 0)))
585 (set (match_operand:SI 0 "gpc_reg_operand" "")
586 (sign_extend:SI (match_dup 1)))]
587 "TARGET_POWERPC && reload_completed"
588 [(set (match_dup 0)
589 (sign_extend:SI (match_dup 1)))
590 (set (match_dup 2)
591 (compare:CC (match_dup 0)
592 (const_int 0)))]
593 "")
594
595 (define_expand "extendqisi2_power"
596 [(parallel [(set (match_dup 2)
597 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
598 (const_int 24)))
599 (clobber (scratch:SI))])
600 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
601 (ashiftrt:SI (match_dup 2)
602 (const_int 24)))
603 (clobber (scratch:SI))])]
604 "TARGET_POWER"
605 "
606 { operands[1] = gen_lowpart (SImode, operands[1]);
607 operands[2] = gen_reg_rtx (SImode); }")
608
609 (define_expand "extendqisi2_no_power"
610 [(set (match_dup 2)
611 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
612 (const_int 24)))
613 (set (match_operand:SI 0 "gpc_reg_operand" "")
614 (ashiftrt:SI (match_dup 2)
615 (const_int 24)))]
616 "! TARGET_POWER && ! TARGET_POWERPC"
617 "
618 { operands[1] = gen_lowpart (SImode, operands[1]);
619 operands[2] = gen_reg_rtx (SImode); }")
620
621 (define_expand "zero_extendqihi2"
622 [(set (match_operand:HI 0 "gpc_reg_operand" "")
623 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
624 ""
625 "")
626
627 (define_insn ""
628 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
629 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
630 ""
631 "@
632 lbz%U1%X1 %0,%1
633 {rlinm|rlwinm} %0,%1,0,0xff"
634 [(set_attr "type" "load,*")])
635
636 (define_insn ""
637 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
638 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
639 (const_int 0)))
640 (clobber (match_scratch:HI 2 "=r,r"))]
641 ""
642 "@
643 {andil.|andi.} %2,%1,0xff
644 #"
645 [(set_attr "type" "compare")
646 (set_attr "length" "4,8")])
647
648 (define_split
649 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
650 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
651 (const_int 0)))
652 (clobber (match_scratch:HI 2 ""))]
653 "reload_completed"
654 [(set (match_dup 2)
655 (zero_extend:HI (match_dup 1)))
656 (set (match_dup 0)
657 (compare:CC (match_dup 2)
658 (const_int 0)))]
659 "")
660
661 (define_insn ""
662 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
663 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
664 (const_int 0)))
665 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
666 (zero_extend:HI (match_dup 1)))]
667 ""
668 "@
669 {andil.|andi.} %0,%1,0xff
670 #"
671 [(set_attr "type" "compare")
672 (set_attr "length" "4,8")])
673
674 (define_split
675 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
676 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
677 (const_int 0)))
678 (set (match_operand:HI 0 "gpc_reg_operand" "")
679 (zero_extend:HI (match_dup 1)))]
680 "reload_completed"
681 [(set (match_dup 0)
682 (zero_extend:HI (match_dup 1)))
683 (set (match_dup 2)
684 (compare:CC (match_dup 0)
685 (const_int 0)))]
686 "")
687
688 (define_expand "extendqihi2"
689 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
690 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
691 ""
692 "
693 {
694 if (TARGET_POWERPC)
695 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
696 else if (TARGET_POWER)
697 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
698 else
699 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
700 DONE;
701 }")
702
703 (define_insn "extendqihi2_ppc"
704 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
705 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
706 "TARGET_POWERPC"
707 "extsb %0,%1"
708 [(set_attr "type" "exts")])
709
710 (define_insn ""
711 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
712 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
713 (const_int 0)))
714 (clobber (match_scratch:HI 2 "=r,r"))]
715 "TARGET_POWERPC"
716 "@
717 extsb. %2,%1
718 #"
719 [(set_attr "type" "compare")
720 (set_attr "length" "4,8")])
721
722 (define_split
723 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
724 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
725 (const_int 0)))
726 (clobber (match_scratch:HI 2 ""))]
727 "TARGET_POWERPC && reload_completed"
728 [(set (match_dup 2)
729 (sign_extend:HI (match_dup 1)))
730 (set (match_dup 0)
731 (compare:CC (match_dup 2)
732 (const_int 0)))]
733 "")
734
735 (define_insn ""
736 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
737 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
738 (const_int 0)))
739 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
740 (sign_extend:HI (match_dup 1)))]
741 "TARGET_POWERPC"
742 "@
743 extsb. %0,%1
744 #"
745 [(set_attr "type" "compare")
746 (set_attr "length" "4,8")])
747
748 (define_split
749 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
750 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
751 (const_int 0)))
752 (set (match_operand:HI 0 "gpc_reg_operand" "")
753 (sign_extend:HI (match_dup 1)))]
754 "TARGET_POWERPC && reload_completed"
755 [(set (match_dup 0)
756 (sign_extend:HI (match_dup 1)))
757 (set (match_dup 2)
758 (compare:CC (match_dup 0)
759 (const_int 0)))]
760 "")
761
762 (define_expand "extendqihi2_power"
763 [(parallel [(set (match_dup 2)
764 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
765 (const_int 24)))
766 (clobber (scratch:SI))])
767 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
768 (ashiftrt:SI (match_dup 2)
769 (const_int 24)))
770 (clobber (scratch:SI))])]
771 "TARGET_POWER"
772 "
773 { operands[0] = gen_lowpart (SImode, operands[0]);
774 operands[1] = gen_lowpart (SImode, operands[1]);
775 operands[2] = gen_reg_rtx (SImode); }")
776
777 (define_expand "extendqihi2_no_power"
778 [(set (match_dup 2)
779 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
780 (const_int 24)))
781 (set (match_operand:HI 0 "gpc_reg_operand" "")
782 (ashiftrt:SI (match_dup 2)
783 (const_int 24)))]
784 "! TARGET_POWER && ! TARGET_POWERPC"
785 "
786 { operands[0] = gen_lowpart (SImode, operands[0]);
787 operands[1] = gen_lowpart (SImode, operands[1]);
788 operands[2] = gen_reg_rtx (SImode); }")
789
790 (define_expand "zero_extendhisi2"
791 [(set (match_operand:SI 0 "gpc_reg_operand" "")
792 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
793 ""
794 "")
795
796 (define_insn ""
797 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
798 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
799 ""
800 "@
801 lhz%U1%X1 %0,%1
802 {rlinm|rlwinm} %0,%1,0,0xffff"
803 [(set_attr "type" "load,*")])
804
805 (define_insn ""
806 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
807 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
808 (const_int 0)))
809 (clobber (match_scratch:SI 2 "=r,r"))]
810 ""
811 "@
812 {andil.|andi.} %2,%1,0xffff
813 #"
814 [(set_attr "type" "compare")
815 (set_attr "length" "4,8")])
816
817 (define_split
818 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
819 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
820 (const_int 0)))
821 (clobber (match_scratch:SI 2 ""))]
822 "reload_completed"
823 [(set (match_dup 2)
824 (zero_extend:SI (match_dup 1)))
825 (set (match_dup 0)
826 (compare:CC (match_dup 2)
827 (const_int 0)))]
828 "")
829
830 (define_insn ""
831 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
832 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
833 (const_int 0)))
834 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
835 (zero_extend:SI (match_dup 1)))]
836 ""
837 "@
838 {andil.|andi.} %0,%1,0xffff
839 #"
840 [(set_attr "type" "compare")
841 (set_attr "length" "4,8")])
842
843 (define_split
844 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
845 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
846 (const_int 0)))
847 (set (match_operand:SI 0 "gpc_reg_operand" "")
848 (zero_extend:SI (match_dup 1)))]
849 "reload_completed"
850 [(set (match_dup 0)
851 (zero_extend:SI (match_dup 1)))
852 (set (match_dup 2)
853 (compare:CC (match_dup 0)
854 (const_int 0)))]
855 "")
856
857 (define_expand "extendhisi2"
858 [(set (match_operand:SI 0 "gpc_reg_operand" "")
859 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
860 ""
861 "")
862
863 (define_insn ""
864 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
865 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
866 ""
867 "@
868 lha%U1%X1 %0,%1
869 {exts|extsh} %0,%1"
870 [(set_attr "type" "load_ext,exts")])
871
872 (define_insn ""
873 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
874 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
875 (const_int 0)))
876 (clobber (match_scratch:SI 2 "=r,r"))]
877 ""
878 "@
879 {exts.|extsh.} %2,%1
880 #"
881 [(set_attr "type" "compare")
882 (set_attr "length" "4,8")])
883
884 (define_split
885 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
886 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
887 (const_int 0)))
888 (clobber (match_scratch:SI 2 ""))]
889 "reload_completed"
890 [(set (match_dup 2)
891 (sign_extend:SI (match_dup 1)))
892 (set (match_dup 0)
893 (compare:CC (match_dup 2)
894 (const_int 0)))]
895 "")
896
897 (define_insn ""
898 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
899 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
900 (const_int 0)))
901 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
902 (sign_extend:SI (match_dup 1)))]
903 ""
904 "@
905 {exts.|extsh.} %0,%1
906 #"
907 [(set_attr "type" "compare")
908 (set_attr "length" "4,8")])
909 \f
910 ;; IBM 405 and 440 half-word multiplication operations.
911
912 (define_insn "*macchwc"
913 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
914 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
915 (match_operand:SI 2 "gpc_reg_operand" "r")
916 (const_int 16))
917 (sign_extend:SI
918 (match_operand:HI 1 "gpc_reg_operand" "r")))
919 (match_operand:SI 4 "gpc_reg_operand" "0"))
920 (const_int 0)))
921 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
922 (plus:SI (mult:SI (ashiftrt:SI
923 (match_dup 2)
924 (const_int 16))
925 (sign_extend:SI
926 (match_dup 1)))
927 (match_dup 4)))]
928 "TARGET_MULHW"
929 "macchw. %0, %1, %2"
930 [(set_attr "type" "imul3")])
931
932 (define_insn "*macchw"
933 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
934 (plus:SI (mult:SI (ashiftrt:SI
935 (match_operand:SI 2 "gpc_reg_operand" "r")
936 (const_int 16))
937 (sign_extend:SI
938 (match_operand:HI 1 "gpc_reg_operand" "r")))
939 (match_operand:SI 3 "gpc_reg_operand" "0")))]
940 "TARGET_MULHW"
941 "macchw %0, %1, %2"
942 [(set_attr "type" "imul3")])
943
944 (define_insn "*macchwuc"
945 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
946 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
947 (match_operand:SI 2 "gpc_reg_operand" "r")
948 (const_int 16))
949 (zero_extend:SI
950 (match_operand:HI 1 "gpc_reg_operand" "r")))
951 (match_operand:SI 4 "gpc_reg_operand" "0"))
952 (const_int 0)))
953 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
954 (plus:SI (mult:SI (lshiftrt:SI
955 (match_dup 2)
956 (const_int 16))
957 (zero_extend:SI
958 (match_dup 1)))
959 (match_dup 4)))]
960 "TARGET_MULHW"
961 "macchwu. %0, %1, %2"
962 [(set_attr "type" "imul3")])
963
964 (define_insn "*macchwu"
965 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
966 (plus:SI (mult:SI (lshiftrt:SI
967 (match_operand:SI 2 "gpc_reg_operand" "r")
968 (const_int 16))
969 (zero_extend:SI
970 (match_operand:HI 1 "gpc_reg_operand" "r")))
971 (match_operand:SI 3 "gpc_reg_operand" "0")))]
972 "TARGET_MULHW"
973 "macchwu %0, %1, %2"
974 [(set_attr "type" "imul3")])
975
976 (define_insn "*machhwc"
977 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
978 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
979 (match_operand:SI 1 "gpc_reg_operand" "%r")
980 (const_int 16))
981 (ashiftrt:SI
982 (match_operand:SI 2 "gpc_reg_operand" "r")
983 (const_int 16)))
984 (match_operand:SI 4 "gpc_reg_operand" "0"))
985 (const_int 0)))
986 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
987 (plus:SI (mult:SI (ashiftrt:SI
988 (match_dup 1)
989 (const_int 16))
990 (ashiftrt:SI
991 (match_dup 2)
992 (const_int 16)))
993 (match_dup 4)))]
994 "TARGET_MULHW"
995 "machhw. %0, %1, %2"
996 [(set_attr "type" "imul3")])
997
998 (define_insn "*machhw"
999 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1000 (plus:SI (mult:SI (ashiftrt:SI
1001 (match_operand:SI 1 "gpc_reg_operand" "%r")
1002 (const_int 16))
1003 (ashiftrt:SI
1004 (match_operand:SI 2 "gpc_reg_operand" "r")
1005 (const_int 16)))
1006 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1007 "TARGET_MULHW"
1008 "machhw %0, %1, %2"
1009 [(set_attr "type" "imul3")])
1010
1011 (define_insn "*machhwuc"
1012 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1013 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1014 (match_operand:SI 1 "gpc_reg_operand" "%r")
1015 (const_int 16))
1016 (lshiftrt:SI
1017 (match_operand:SI 2 "gpc_reg_operand" "r")
1018 (const_int 16)))
1019 (match_operand:SI 4 "gpc_reg_operand" "0"))
1020 (const_int 0)))
1021 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1022 (plus:SI (mult:SI (lshiftrt:SI
1023 (match_dup 1)
1024 (const_int 16))
1025 (lshiftrt:SI
1026 (match_dup 2)
1027 (const_int 16)))
1028 (match_dup 4)))]
1029 "TARGET_MULHW"
1030 "machhwu. %0, %1, %2"
1031 [(set_attr "type" "imul3")])
1032
1033 (define_insn "*machhwu"
1034 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1035 (plus:SI (mult:SI (lshiftrt:SI
1036 (match_operand:SI 1 "gpc_reg_operand" "%r")
1037 (const_int 16))
1038 (lshiftrt:SI
1039 (match_operand:SI 2 "gpc_reg_operand" "r")
1040 (const_int 16)))
1041 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1042 "TARGET_MULHW"
1043 "machhwu %0, %1, %2"
1044 [(set_attr "type" "imul3")])
1045
1046 (define_insn "*maclhwc"
1047 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1048 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1049 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1050 (sign_extend:SI
1051 (match_operand:HI 2 "gpc_reg_operand" "r")))
1052 (match_operand:SI 4 "gpc_reg_operand" "0"))
1053 (const_int 0)))
1054 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1055 (plus:SI (mult:SI (sign_extend:SI
1056 (match_dup 1))
1057 (sign_extend:SI
1058 (match_dup 2)))
1059 (match_dup 4)))]
1060 "TARGET_MULHW"
1061 "maclhw. %0, %1, %2"
1062 [(set_attr "type" "imul3")])
1063
1064 (define_insn "*maclhw"
1065 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1066 (plus:SI (mult:SI (sign_extend:SI
1067 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1068 (sign_extend:SI
1069 (match_operand:HI 2 "gpc_reg_operand" "r")))
1070 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1071 "TARGET_MULHW"
1072 "maclhw %0, %1, %2"
1073 [(set_attr "type" "imul3")])
1074
1075 (define_insn "*maclhwuc"
1076 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1077 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1078 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1079 (zero_extend:SI
1080 (match_operand:HI 2 "gpc_reg_operand" "r")))
1081 (match_operand:SI 4 "gpc_reg_operand" "0"))
1082 (const_int 0)))
1083 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1084 (plus:SI (mult:SI (zero_extend:SI
1085 (match_dup 1))
1086 (zero_extend:SI
1087 (match_dup 2)))
1088 (match_dup 4)))]
1089 "TARGET_MULHW"
1090 "maclhwu. %0, %1, %2"
1091 [(set_attr "type" "imul3")])
1092
1093 (define_insn "*maclhwu"
1094 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1095 (plus:SI (mult:SI (zero_extend:SI
1096 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1097 (zero_extend:SI
1098 (match_operand:HI 2 "gpc_reg_operand" "r")))
1099 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1100 "TARGET_MULHW"
1101 "maclhwu %0, %1, %2"
1102 [(set_attr "type" "imul3")])
1103
1104 (define_insn "*nmacchwc"
1105 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1106 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1107 (mult:SI (ashiftrt:SI
1108 (match_operand:SI 2 "gpc_reg_operand" "r")
1109 (const_int 16))
1110 (sign_extend:SI
1111 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1112 (const_int 0)))
1113 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1114 (minus:SI (match_dup 4)
1115 (mult:SI (ashiftrt:SI
1116 (match_dup 2)
1117 (const_int 16))
1118 (sign_extend:SI
1119 (match_dup 1)))))]
1120 "TARGET_MULHW"
1121 "nmacchw. %0, %1, %2"
1122 [(set_attr "type" "imul3")])
1123
1124 (define_insn "*nmacchw"
1125 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1126 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1127 (mult:SI (ashiftrt:SI
1128 (match_operand:SI 2 "gpc_reg_operand" "r")
1129 (const_int 16))
1130 (sign_extend:SI
1131 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1132 "TARGET_MULHW"
1133 "nmacchw %0, %1, %2"
1134 [(set_attr "type" "imul3")])
1135
1136 (define_insn "*nmachhwc"
1137 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1138 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1139 (mult:SI (ashiftrt:SI
1140 (match_operand:SI 1 "gpc_reg_operand" "%r")
1141 (const_int 16))
1142 (ashiftrt:SI
1143 (match_operand:SI 2 "gpc_reg_operand" "r")
1144 (const_int 16))))
1145 (const_int 0)))
1146 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1147 (minus:SI (match_dup 4)
1148 (mult:SI (ashiftrt:SI
1149 (match_dup 1)
1150 (const_int 16))
1151 (ashiftrt:SI
1152 (match_dup 2)
1153 (const_int 16)))))]
1154 "TARGET_MULHW"
1155 "nmachhw. %0, %1, %2"
1156 [(set_attr "type" "imul3")])
1157
1158 (define_insn "*nmachhw"
1159 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1160 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1161 (mult:SI (ashiftrt:SI
1162 (match_operand:SI 1 "gpc_reg_operand" "%r")
1163 (const_int 16))
1164 (ashiftrt:SI
1165 (match_operand:SI 2 "gpc_reg_operand" "r")
1166 (const_int 16)))))]
1167 "TARGET_MULHW"
1168 "nmachhw %0, %1, %2"
1169 [(set_attr "type" "imul3")])
1170
1171 (define_insn "*nmaclhwc"
1172 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1173 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1174 (mult:SI (sign_extend:SI
1175 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1176 (sign_extend:SI
1177 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1178 (const_int 0)))
1179 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1180 (minus:SI (match_dup 4)
1181 (mult:SI (sign_extend:SI
1182 (match_dup 1))
1183 (sign_extend:SI
1184 (match_dup 2)))))]
1185 "TARGET_MULHW"
1186 "nmaclhw. %0, %1, %2"
1187 [(set_attr "type" "imul3")])
1188
1189 (define_insn "*nmaclhw"
1190 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1191 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1192 (mult:SI (sign_extend:SI
1193 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1194 (sign_extend:SI
1195 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1196 "TARGET_MULHW"
1197 "nmaclhw %0, %1, %2"
1198 [(set_attr "type" "imul3")])
1199
1200 (define_insn "*mulchwc"
1201 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1202 (compare:CC (mult:SI (ashiftrt:SI
1203 (match_operand:SI 2 "gpc_reg_operand" "r")
1204 (const_int 16))
1205 (sign_extend:SI
1206 (match_operand:HI 1 "gpc_reg_operand" "r")))
1207 (const_int 0)))
1208 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1209 (mult:SI (ashiftrt:SI
1210 (match_dup 2)
1211 (const_int 16))
1212 (sign_extend:SI
1213 (match_dup 1))))]
1214 "TARGET_MULHW"
1215 "mulchw. %0, %1, %2"
1216 [(set_attr "type" "imul3")])
1217
1218 (define_insn "*mulchw"
1219 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1220 (mult:SI (ashiftrt:SI
1221 (match_operand:SI 2 "gpc_reg_operand" "r")
1222 (const_int 16))
1223 (sign_extend:SI
1224 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1225 "TARGET_MULHW"
1226 "mulchw %0, %1, %2"
1227 [(set_attr "type" "imul3")])
1228
1229 (define_insn "*mulchwuc"
1230 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1231 (compare:CC (mult:SI (lshiftrt:SI
1232 (match_operand:SI 2 "gpc_reg_operand" "r")
1233 (const_int 16))
1234 (zero_extend:SI
1235 (match_operand:HI 1 "gpc_reg_operand" "r")))
1236 (const_int 0)))
1237 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1238 (mult:SI (lshiftrt:SI
1239 (match_dup 2)
1240 (const_int 16))
1241 (zero_extend:SI
1242 (match_dup 1))))]
1243 "TARGET_MULHW"
1244 "mulchwu. %0, %1, %2"
1245 [(set_attr "type" "imul3")])
1246
1247 (define_insn "*mulchwu"
1248 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1249 (mult:SI (lshiftrt:SI
1250 (match_operand:SI 2 "gpc_reg_operand" "r")
1251 (const_int 16))
1252 (zero_extend:SI
1253 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1254 "TARGET_MULHW"
1255 "mulchwu %0, %1, %2"
1256 [(set_attr "type" "imul3")])
1257
1258 (define_insn "*mulhhwc"
1259 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1260 (compare:CC (mult:SI (ashiftrt:SI
1261 (match_operand:SI 1 "gpc_reg_operand" "%r")
1262 (const_int 16))
1263 (ashiftrt:SI
1264 (match_operand:SI 2 "gpc_reg_operand" "r")
1265 (const_int 16)))
1266 (const_int 0)))
1267 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1268 (mult:SI (ashiftrt:SI
1269 (match_dup 1)
1270 (const_int 16))
1271 (ashiftrt:SI
1272 (match_dup 2)
1273 (const_int 16))))]
1274 "TARGET_MULHW"
1275 "mulhhw. %0, %1, %2"
1276 [(set_attr "type" "imul3")])
1277
1278 (define_insn "*mulhhw"
1279 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1280 (mult:SI (ashiftrt:SI
1281 (match_operand:SI 1 "gpc_reg_operand" "%r")
1282 (const_int 16))
1283 (ashiftrt:SI
1284 (match_operand:SI 2 "gpc_reg_operand" "r")
1285 (const_int 16))))]
1286 "TARGET_MULHW"
1287 "mulhhw %0, %1, %2"
1288 [(set_attr "type" "imul3")])
1289
1290 (define_insn "*mulhhwuc"
1291 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1292 (compare:CC (mult:SI (lshiftrt:SI
1293 (match_operand:SI 1 "gpc_reg_operand" "%r")
1294 (const_int 16))
1295 (lshiftrt:SI
1296 (match_operand:SI 2 "gpc_reg_operand" "r")
1297 (const_int 16)))
1298 (const_int 0)))
1299 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1300 (mult:SI (lshiftrt:SI
1301 (match_dup 1)
1302 (const_int 16))
1303 (lshiftrt:SI
1304 (match_dup 2)
1305 (const_int 16))))]
1306 "TARGET_MULHW"
1307 "mulhhwu. %0, %1, %2"
1308 [(set_attr "type" "imul3")])
1309
1310 (define_insn "*mulhhwu"
1311 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1312 (mult:SI (lshiftrt:SI
1313 (match_operand:SI 1 "gpc_reg_operand" "%r")
1314 (const_int 16))
1315 (lshiftrt:SI
1316 (match_operand:SI 2 "gpc_reg_operand" "r")
1317 (const_int 16))))]
1318 "TARGET_MULHW"
1319 "mulhhwu %0, %1, %2"
1320 [(set_attr "type" "imul3")])
1321
1322 (define_insn "*mullhwc"
1323 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1324 (compare:CC (mult:SI (sign_extend:SI
1325 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1326 (sign_extend:SI
1327 (match_operand:HI 2 "gpc_reg_operand" "r")))
1328 (const_int 0)))
1329 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1330 (mult:SI (sign_extend:SI
1331 (match_dup 1))
1332 (sign_extend:SI
1333 (match_dup 2))))]
1334 "TARGET_MULHW"
1335 "mullhw. %0, %1, %2"
1336 [(set_attr "type" "imul3")])
1337
1338 (define_insn "*mullhw"
1339 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1340 (mult:SI (sign_extend:SI
1341 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1342 (sign_extend:SI
1343 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1344 "TARGET_MULHW"
1345 "mullhw %0, %1, %2"
1346 [(set_attr "type" "imul3")])
1347
1348 (define_insn "*mullhwuc"
1349 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1350 (compare:CC (mult:SI (zero_extend:SI
1351 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1352 (zero_extend:SI
1353 (match_operand:HI 2 "gpc_reg_operand" "r")))
1354 (const_int 0)))
1355 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1356 (mult:SI (zero_extend:SI
1357 (match_dup 1))
1358 (zero_extend:SI
1359 (match_dup 2))))]
1360 "TARGET_MULHW"
1361 "mullhwu. %0, %1, %2"
1362 [(set_attr "type" "imul3")])
1363
1364 (define_insn "*mullhwu"
1365 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1366 (mult:SI (zero_extend:SI
1367 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1368 (zero_extend:SI
1369 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1370 "TARGET_MULHW"
1371 "mullhwu %0, %1, %2"
1372 [(set_attr "type" "imul3")])
1373 \f
1374 ;; IBM 405 and 440 string-search dlmzb instruction support.
1375 (define_insn "dlmzb"
1376 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1377 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1378 (match_operand:SI 2 "gpc_reg_operand" "r")]
1379 UNSPEC_DLMZB_CR))
1380 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1381 (unspec:SI [(match_dup 1)
1382 (match_dup 2)]
1383 UNSPEC_DLMZB))]
1384 "TARGET_DLMZB"
1385 "dlmzb. %0, %1, %2")
1386
1387 (define_expand "strlensi"
1388 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1389 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1390 (match_operand:QI 2 "const_int_operand" "")
1391 (match_operand 3 "const_int_operand" "")]
1392 UNSPEC_DLMZB_STRLEN))
1393 (clobber (match_scratch:CC 4 "=x"))]
1394 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1395 {
1396 rtx result = operands[0];
1397 rtx src = operands[1];
1398 rtx search_char = operands[2];
1399 rtx align = operands[3];
1400 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1401 rtx loop_label, end_label, mem, cr0, cond;
1402 if (search_char != const0_rtx
1403 || GET_CODE (align) != CONST_INT
1404 || INTVAL (align) < 8)
1405 FAIL;
1406 word1 = gen_reg_rtx (SImode);
1407 word2 = gen_reg_rtx (SImode);
1408 scratch_dlmzb = gen_reg_rtx (SImode);
1409 scratch_string = gen_reg_rtx (Pmode);
1410 loop_label = gen_label_rtx ();
1411 end_label = gen_label_rtx ();
1412 addr = force_reg (Pmode, XEXP (src, 0));
1413 emit_move_insn (scratch_string, addr);
1414 emit_label (loop_label);
1415 mem = change_address (src, SImode, scratch_string);
1416 emit_move_insn (word1, mem);
1417 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1418 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1419 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1420 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1421 emit_jump_insn (gen_rtx_SET (VOIDmode,
1422 pc_rtx,
1423 gen_rtx_IF_THEN_ELSE (VOIDmode,
1424 cond,
1425 gen_rtx_LABEL_REF
1426 (VOIDmode,
1427 end_label),
1428 pc_rtx)));
1429 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1430 emit_jump_insn (gen_rtx_SET (VOIDmode,
1431 pc_rtx,
1432 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1433 emit_barrier ();
1434 emit_label (end_label);
1435 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1436 emit_insn (gen_subsi3 (result, scratch_string, addr));
1437 emit_insn (gen_subsi3 (result, result, const1_rtx));
1438 DONE;
1439 })
1440 \f
1441 (define_split
1442 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1443 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1444 (const_int 0)))
1445 (set (match_operand:SI 0 "gpc_reg_operand" "")
1446 (sign_extend:SI (match_dup 1)))]
1447 "reload_completed"
1448 [(set (match_dup 0)
1449 (sign_extend:SI (match_dup 1)))
1450 (set (match_dup 2)
1451 (compare:CC (match_dup 0)
1452 (const_int 0)))]
1453 "")
1454
1455 ;; Fixed-point arithmetic insns.
1456
1457 (define_expand "add<mode>3"
1458 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1459 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1460 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1461 ""
1462 {
1463 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1464 {
1465 if (non_short_cint_operand (operands[2], DImode))
1466 FAIL;
1467 }
1468 else if (GET_CODE (operands[2]) == CONST_INT
1469 && ! add_operand (operands[2], <MODE>mode))
1470 {
1471 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
1472 ? operands[0] : gen_reg_rtx (<MODE>mode));
1473
1474 HOST_WIDE_INT val = INTVAL (operands[2]);
1475 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1476 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1477
1478 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1479 FAIL;
1480
1481 /* The ordering here is important for the prolog expander.
1482 When space is allocated from the stack, adding 'low' first may
1483 produce a temporary deallocation (which would be bad). */
1484 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1485 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1486 DONE;
1487 }
1488 })
1489
1490 ;; Discourage ai/addic because of carry but provide it in an alternative
1491 ;; allowing register zero as source.
1492 (define_insn "*add<mode>3_internal1"
1493 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1494 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1495 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1496 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1497 "@
1498 {cax|add} %0,%1,%2
1499 {cal %0,%2(%1)|addi %0,%1,%2}
1500 {ai|addic} %0,%1,%2
1501 {cau|addis} %0,%1,%v2"
1502 [(set_attr "length" "4,4,4,4")])
1503
1504 (define_insn "addsi3_high"
1505 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1506 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1507 (high:SI (match_operand 2 "" ""))))]
1508 "TARGET_MACHO && !TARGET_64BIT"
1509 "{cau|addis} %0,%1,ha16(%2)"
1510 [(set_attr "length" "4")])
1511
1512 (define_insn "*add<mode>3_internal2"
1513 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1514 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1515 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1516 (const_int 0)))
1517 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1518 ""
1519 "@
1520 {cax.|add.} %3,%1,%2
1521 {ai.|addic.} %3,%1,%2
1522 #
1523 #"
1524 [(set_attr "type" "fast_compare,compare,compare,compare")
1525 (set_attr "length" "4,4,8,8")])
1526
1527 (define_split
1528 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1529 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1530 (match_operand:GPR 2 "reg_or_short_operand" ""))
1531 (const_int 0)))
1532 (clobber (match_scratch:GPR 3 ""))]
1533 "reload_completed"
1534 [(set (match_dup 3)
1535 (plus:GPR (match_dup 1)
1536 (match_dup 2)))
1537 (set (match_dup 0)
1538 (compare:CC (match_dup 3)
1539 (const_int 0)))]
1540 "")
1541
1542 (define_insn "*add<mode>3_internal3"
1543 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1544 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1545 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1546 (const_int 0)))
1547 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1548 (plus:P (match_dup 1)
1549 (match_dup 2)))]
1550 ""
1551 "@
1552 {cax.|add.} %0,%1,%2
1553 {ai.|addic.} %0,%1,%2
1554 #
1555 #"
1556 [(set_attr "type" "fast_compare,compare,compare,compare")
1557 (set_attr "length" "4,4,8,8")])
1558
1559 (define_split
1560 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1561 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1562 (match_operand:P 2 "reg_or_short_operand" ""))
1563 (const_int 0)))
1564 (set (match_operand:P 0 "gpc_reg_operand" "")
1565 (plus:P (match_dup 1) (match_dup 2)))]
1566 "reload_completed"
1567 [(set (match_dup 0)
1568 (plus:P (match_dup 1)
1569 (match_dup 2)))
1570 (set (match_dup 3)
1571 (compare:CC (match_dup 0)
1572 (const_int 0)))]
1573 "")
1574
1575 ;; Split an add that we can't do in one insn into two insns, each of which
1576 ;; does one 16-bit part. This is used by combine. Note that the low-order
1577 ;; add should be last in case the result gets used in an address.
1578
1579 (define_split
1580 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1581 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1582 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1583 ""
1584 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1585 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1586 {
1587 HOST_WIDE_INT val = INTVAL (operands[2]);
1588 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1589 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1590
1591 operands[4] = GEN_INT (low);
1592 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1593 operands[3] = GEN_INT (rest);
1594 else if (! no_new_pseudos)
1595 {
1596 operands[3] = gen_reg_rtx (DImode);
1597 emit_move_insn (operands[3], operands[2]);
1598 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1599 DONE;
1600 }
1601 else
1602 FAIL;
1603 })
1604
1605 (define_insn "one_cmpl<mode>2"
1606 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1607 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1608 ""
1609 "nor %0,%1,%1")
1610
1611 (define_insn ""
1612 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1613 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1614 (const_int 0)))
1615 (clobber (match_scratch:P 2 "=r,r"))]
1616 ""
1617 "@
1618 nor. %2,%1,%1
1619 #"
1620 [(set_attr "type" "compare")
1621 (set_attr "length" "4,8")])
1622
1623 (define_split
1624 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1625 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1626 (const_int 0)))
1627 (clobber (match_scratch:P 2 ""))]
1628 "reload_completed"
1629 [(set (match_dup 2)
1630 (not:P (match_dup 1)))
1631 (set (match_dup 0)
1632 (compare:CC (match_dup 2)
1633 (const_int 0)))]
1634 "")
1635
1636 (define_insn ""
1637 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1638 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1639 (const_int 0)))
1640 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1641 (not:P (match_dup 1)))]
1642 ""
1643 "@
1644 nor. %0,%1,%1
1645 #"
1646 [(set_attr "type" "compare")
1647 (set_attr "length" "4,8")])
1648
1649 (define_split
1650 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1651 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1652 (const_int 0)))
1653 (set (match_operand:P 0 "gpc_reg_operand" "")
1654 (not:P (match_dup 1)))]
1655 "reload_completed"
1656 [(set (match_dup 0)
1657 (not:P (match_dup 1)))
1658 (set (match_dup 2)
1659 (compare:CC (match_dup 0)
1660 (const_int 0)))]
1661 "")
1662
1663 (define_insn ""
1664 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1665 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1666 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1667 "! TARGET_POWERPC"
1668 "{sf%I1|subf%I1c} %0,%2,%1")
1669
1670 (define_insn ""
1671 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1672 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1673 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1674 "TARGET_POWERPC"
1675 "@
1676 subf %0,%2,%1
1677 subfic %0,%2,%1")
1678
1679 (define_insn ""
1680 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1681 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1682 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1683 (const_int 0)))
1684 (clobber (match_scratch:SI 3 "=r,r"))]
1685 "! TARGET_POWERPC"
1686 "@
1687 {sf.|subfc.} %3,%2,%1
1688 #"
1689 [(set_attr "type" "compare")
1690 (set_attr "length" "4,8")])
1691
1692 (define_insn ""
1693 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1694 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1695 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1696 (const_int 0)))
1697 (clobber (match_scratch:P 3 "=r,r"))]
1698 "TARGET_POWERPC"
1699 "@
1700 subf. %3,%2,%1
1701 #"
1702 [(set_attr "type" "fast_compare")
1703 (set_attr "length" "4,8")])
1704
1705 (define_split
1706 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1707 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1708 (match_operand:P 2 "gpc_reg_operand" ""))
1709 (const_int 0)))
1710 (clobber (match_scratch:P 3 ""))]
1711 "reload_completed"
1712 [(set (match_dup 3)
1713 (minus:P (match_dup 1)
1714 (match_dup 2)))
1715 (set (match_dup 0)
1716 (compare:CC (match_dup 3)
1717 (const_int 0)))]
1718 "")
1719
1720 (define_insn ""
1721 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1722 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1723 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1724 (const_int 0)))
1725 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1726 (minus:SI (match_dup 1) (match_dup 2)))]
1727 "! TARGET_POWERPC"
1728 "@
1729 {sf.|subfc.} %0,%2,%1
1730 #"
1731 [(set_attr "type" "compare")
1732 (set_attr "length" "4,8")])
1733
1734 (define_insn ""
1735 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1736 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1737 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1738 (const_int 0)))
1739 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1740 (minus:P (match_dup 1)
1741 (match_dup 2)))]
1742 "TARGET_POWERPC"
1743 "@
1744 subf. %0,%2,%1
1745 #"
1746 [(set_attr "type" "fast_compare")
1747 (set_attr "length" "4,8")])
1748
1749 (define_split
1750 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1751 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1752 (match_operand:P 2 "gpc_reg_operand" ""))
1753 (const_int 0)))
1754 (set (match_operand:P 0 "gpc_reg_operand" "")
1755 (minus:P (match_dup 1)
1756 (match_dup 2)))]
1757 "reload_completed"
1758 [(set (match_dup 0)
1759 (minus:P (match_dup 1)
1760 (match_dup 2)))
1761 (set (match_dup 3)
1762 (compare:CC (match_dup 0)
1763 (const_int 0)))]
1764 "")
1765
1766 (define_expand "sub<mode>3"
1767 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1768 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1769 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1770 ""
1771 "
1772 {
1773 if (GET_CODE (operands[2]) == CONST_INT)
1774 {
1775 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1776 negate_rtx (<MODE>mode, operands[2])));
1777 DONE;
1778 }
1779 }")
1780
1781 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1782 ;; instruction and some auxiliary computations. Then we just have a single
1783 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1784 ;; combine.
1785
1786 (define_expand "sminsi3"
1787 [(set (match_dup 3)
1788 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1789 (match_operand:SI 2 "reg_or_short_operand" ""))
1790 (const_int 0)
1791 (minus:SI (match_dup 2) (match_dup 1))))
1792 (set (match_operand:SI 0 "gpc_reg_operand" "")
1793 (minus:SI (match_dup 2) (match_dup 3)))]
1794 "TARGET_POWER || TARGET_ISEL"
1795 "
1796 {
1797 if (TARGET_ISEL)
1798 {
1799 operands[2] = force_reg (SImode, operands[2]);
1800 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1801 DONE;
1802 }
1803
1804 operands[3] = gen_reg_rtx (SImode);
1805 }")
1806
1807 (define_split
1808 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1809 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1810 (match_operand:SI 2 "reg_or_short_operand" "")))
1811 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1812 "TARGET_POWER"
1813 [(set (match_dup 3)
1814 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1815 (const_int 0)
1816 (minus:SI (match_dup 2) (match_dup 1))))
1817 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1818 "")
1819
1820 (define_expand "smaxsi3"
1821 [(set (match_dup 3)
1822 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1823 (match_operand:SI 2 "reg_or_short_operand" ""))
1824 (const_int 0)
1825 (minus:SI (match_dup 2) (match_dup 1))))
1826 (set (match_operand:SI 0 "gpc_reg_operand" "")
1827 (plus:SI (match_dup 3) (match_dup 1)))]
1828 "TARGET_POWER || TARGET_ISEL"
1829 "
1830 {
1831 if (TARGET_ISEL)
1832 {
1833 operands[2] = force_reg (SImode, operands[2]);
1834 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1835 DONE;
1836 }
1837 operands[3] = gen_reg_rtx (SImode);
1838 }")
1839
1840 (define_split
1841 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1842 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1843 (match_operand:SI 2 "reg_or_short_operand" "")))
1844 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1845 "TARGET_POWER"
1846 [(set (match_dup 3)
1847 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1848 (const_int 0)
1849 (minus:SI (match_dup 2) (match_dup 1))))
1850 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1851 "")
1852
1853 (define_expand "uminsi3"
1854 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1855 (match_dup 5)))
1856 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1857 (match_dup 5)))
1858 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1859 (const_int 0)
1860 (minus:SI (match_dup 4) (match_dup 3))))
1861 (set (match_operand:SI 0 "gpc_reg_operand" "")
1862 (minus:SI (match_dup 2) (match_dup 3)))]
1863 "TARGET_POWER || TARGET_ISEL"
1864 "
1865 {
1866 if (TARGET_ISEL)
1867 {
1868 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1869 DONE;
1870 }
1871 operands[3] = gen_reg_rtx (SImode);
1872 operands[4] = gen_reg_rtx (SImode);
1873 operands[5] = GEN_INT (-2147483647 - 1);
1874 }")
1875
1876 (define_expand "umaxsi3"
1877 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1878 (match_dup 5)))
1879 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1880 (match_dup 5)))
1881 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1882 (const_int 0)
1883 (minus:SI (match_dup 4) (match_dup 3))))
1884 (set (match_operand:SI 0 "gpc_reg_operand" "")
1885 (plus:SI (match_dup 3) (match_dup 1)))]
1886 "TARGET_POWER || TARGET_ISEL"
1887 "
1888 {
1889 if (TARGET_ISEL)
1890 {
1891 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1892 DONE;
1893 }
1894 operands[3] = gen_reg_rtx (SImode);
1895 operands[4] = gen_reg_rtx (SImode);
1896 operands[5] = GEN_INT (-2147483647 - 1);
1897 }")
1898
1899 (define_insn ""
1900 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1901 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1902 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1903 (const_int 0)
1904 (minus:SI (match_dup 2) (match_dup 1))))]
1905 "TARGET_POWER"
1906 "doz%I2 %0,%1,%2")
1907
1908 (define_insn ""
1909 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1910 (compare:CC
1911 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1912 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1913 (const_int 0)
1914 (minus:SI (match_dup 2) (match_dup 1)))
1915 (const_int 0)))
1916 (clobber (match_scratch:SI 3 "=r,r"))]
1917 "TARGET_POWER"
1918 "@
1919 doz%I2. %3,%1,%2
1920 #"
1921 [(set_attr "type" "delayed_compare")
1922 (set_attr "length" "4,8")])
1923
1924 (define_split
1925 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1926 (compare:CC
1927 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1928 (match_operand:SI 2 "reg_or_short_operand" ""))
1929 (const_int 0)
1930 (minus:SI (match_dup 2) (match_dup 1)))
1931 (const_int 0)))
1932 (clobber (match_scratch:SI 3 ""))]
1933 "TARGET_POWER && reload_completed"
1934 [(set (match_dup 3)
1935 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1936 (const_int 0)
1937 (minus:SI (match_dup 2) (match_dup 1))))
1938 (set (match_dup 0)
1939 (compare:CC (match_dup 3)
1940 (const_int 0)))]
1941 "")
1942
1943 (define_insn ""
1944 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1945 (compare:CC
1946 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1947 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1948 (const_int 0)
1949 (minus:SI (match_dup 2) (match_dup 1)))
1950 (const_int 0)))
1951 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1952 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1953 (const_int 0)
1954 (minus:SI (match_dup 2) (match_dup 1))))]
1955 "TARGET_POWER"
1956 "@
1957 doz%I2. %0,%1,%2
1958 #"
1959 [(set_attr "type" "delayed_compare")
1960 (set_attr "length" "4,8")])
1961
1962 (define_split
1963 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1964 (compare:CC
1965 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1966 (match_operand:SI 2 "reg_or_short_operand" ""))
1967 (const_int 0)
1968 (minus:SI (match_dup 2) (match_dup 1)))
1969 (const_int 0)))
1970 (set (match_operand:SI 0 "gpc_reg_operand" "")
1971 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1972 (const_int 0)
1973 (minus:SI (match_dup 2) (match_dup 1))))]
1974 "TARGET_POWER && reload_completed"
1975 [(set (match_dup 0)
1976 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1977 (const_int 0)
1978 (minus:SI (match_dup 2) (match_dup 1))))
1979 (set (match_dup 3)
1980 (compare:CC (match_dup 0)
1981 (const_int 0)))]
1982 "")
1983
1984 ;; We don't need abs with condition code because such comparisons should
1985 ;; never be done.
1986 (define_expand "abssi2"
1987 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1988 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1989 ""
1990 "
1991 {
1992 if (TARGET_ISEL)
1993 {
1994 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1995 DONE;
1996 }
1997 else if (! TARGET_POWER)
1998 {
1999 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2000 DONE;
2001 }
2002 }")
2003
2004 (define_insn "*abssi2_power"
2005 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2006 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2007 "TARGET_POWER"
2008 "abs %0,%1")
2009
2010 (define_insn_and_split "abssi2_isel"
2011 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2012 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
2013 (clobber (match_scratch:SI 2 "=&b"))
2014 (clobber (match_scratch:CC 3 "=y"))]
2015 "TARGET_ISEL"
2016 "#"
2017 "&& reload_completed"
2018 [(set (match_dup 2) (neg:SI (match_dup 1)))
2019 (set (match_dup 3)
2020 (compare:CC (match_dup 1)
2021 (const_int 0)))
2022 (set (match_dup 0)
2023 (if_then_else:SI (ge (match_dup 3)
2024 (const_int 0))
2025 (match_dup 1)
2026 (match_dup 2)))]
2027 "")
2028
2029 (define_insn_and_split "abssi2_nopower"
2030 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2031 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2032 (clobber (match_scratch:SI 2 "=&r,&r"))]
2033 "! TARGET_POWER && ! TARGET_ISEL"
2034 "#"
2035 "&& reload_completed"
2036 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2037 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2038 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2039 "")
2040
2041 (define_insn "*nabs_power"
2042 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2043 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2044 "TARGET_POWER"
2045 "nabs %0,%1")
2046
2047 (define_insn_and_split "*nabs_nopower"
2048 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2049 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2050 (clobber (match_scratch:SI 2 "=&r,&r"))]
2051 "! TARGET_POWER"
2052 "#"
2053 "&& reload_completed"
2054 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2055 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2056 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2057 "")
2058
2059 (define_expand "neg<mode>2"
2060 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2061 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2062 ""
2063 "")
2064
2065 (define_insn "*neg<mode>2_internal"
2066 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2067 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2068 ""
2069 "neg %0,%1")
2070
2071 (define_insn ""
2072 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2073 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2074 (const_int 0)))
2075 (clobber (match_scratch:P 2 "=r,r"))]
2076 ""
2077 "@
2078 neg. %2,%1
2079 #"
2080 [(set_attr "type" "fast_compare")
2081 (set_attr "length" "4,8")])
2082
2083 (define_split
2084 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2085 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2086 (const_int 0)))
2087 (clobber (match_scratch:P 2 ""))]
2088 "reload_completed"
2089 [(set (match_dup 2)
2090 (neg:P (match_dup 1)))
2091 (set (match_dup 0)
2092 (compare:CC (match_dup 2)
2093 (const_int 0)))]
2094 "")
2095
2096 (define_insn ""
2097 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2098 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2099 (const_int 0)))
2100 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2101 (neg:P (match_dup 1)))]
2102 ""
2103 "@
2104 neg. %0,%1
2105 #"
2106 [(set_attr "type" "fast_compare")
2107 (set_attr "length" "4,8")])
2108
2109 (define_split
2110 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2111 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2112 (const_int 0)))
2113 (set (match_operand:P 0 "gpc_reg_operand" "")
2114 (neg:P (match_dup 1)))]
2115 "reload_completed"
2116 [(set (match_dup 0)
2117 (neg:P (match_dup 1)))
2118 (set (match_dup 2)
2119 (compare:CC (match_dup 0)
2120 (const_int 0)))]
2121 "")
2122
2123 (define_insn "clz<mode>2"
2124 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2125 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2126 ""
2127 "{cntlz|cntlz<wd>} %0,%1"
2128 [(set_attr "type" "cntlz")])
2129
2130 (define_expand "ctz<mode>2"
2131 [(set (match_dup 2)
2132 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2133 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2134 (match_dup 2)))
2135 (clobber (scratch:CC))])
2136 (set (match_dup 4) (clz:GPR (match_dup 3)))
2137 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2138 (minus:GPR (match_dup 5) (match_dup 4)))]
2139 ""
2140 {
2141 operands[2] = gen_reg_rtx (<MODE>mode);
2142 operands[3] = gen_reg_rtx (<MODE>mode);
2143 operands[4] = gen_reg_rtx (<MODE>mode);
2144 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2145 })
2146
2147 (define_expand "ffs<mode>2"
2148 [(set (match_dup 2)
2149 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2150 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2151 (match_dup 2)))
2152 (clobber (scratch:CC))])
2153 (set (match_dup 4) (clz:GPR (match_dup 3)))
2154 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2155 (minus:GPR (match_dup 5) (match_dup 4)))]
2156 ""
2157 {
2158 operands[2] = gen_reg_rtx (<MODE>mode);
2159 operands[3] = gen_reg_rtx (<MODE>mode);
2160 operands[4] = gen_reg_rtx (<MODE>mode);
2161 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2162 })
2163
2164 (define_insn "popcntb<mode>2"
2165 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2166 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2167 UNSPEC_POPCNTB))]
2168 "TARGET_POPCNTB"
2169 "popcntb %0,%1")
2170
2171 (define_expand "popcount<mode>2"
2172 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2173 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2174 "TARGET_POPCNTB"
2175 {
2176 rs6000_emit_popcount (operands[0], operands[1]);
2177 DONE;
2178 })
2179
2180 (define_expand "parity<mode>2"
2181 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2182 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2183 "TARGET_POPCNTB"
2184 {
2185 rs6000_emit_parity (operands[0], operands[1]);
2186 DONE;
2187 })
2188
2189 (define_insn "bswapsi2"
2190 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2191 (bswap:SI (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2192 ""
2193 "@
2194 {lbrx|lwbrx} %0,%y1
2195 {stbrx|stwbrx} %1,%y0
2196 #"
2197 [(set_attr "length" "4,4,12")])
2198
2199 (define_split
2200 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2201 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2202 "reload_completed"
2203 [(set (match_dup 0)
2204 (rotate:SI (match_dup 1) (const_int 8)))
2205 (set (zero_extract:SI (match_dup 0)
2206 (const_int 8)
2207 (const_int 0))
2208 (match_dup 1))
2209 (set (zero_extract:SI (match_dup 0)
2210 (const_int 8)
2211 (const_int 16))
2212 (rotate:SI (match_dup 1)
2213 (const_int 16)))]
2214 "")
2215
2216 (define_expand "mulsi3"
2217 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2218 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2219 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2220 ""
2221 "
2222 {
2223 if (TARGET_POWER)
2224 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2225 else
2226 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2227 DONE;
2228 }")
2229
2230 (define_insn "mulsi3_mq"
2231 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2232 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2233 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2234 (clobber (match_scratch:SI 3 "=q,q"))]
2235 "TARGET_POWER"
2236 "@
2237 {muls|mullw} %0,%1,%2
2238 {muli|mulli} %0,%1,%2"
2239 [(set (attr "type")
2240 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2241 (const_string "imul3")
2242 (match_operand:SI 2 "short_cint_operand" "")
2243 (const_string "imul2")]
2244 (const_string "imul")))])
2245
2246 (define_insn "mulsi3_no_mq"
2247 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2248 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2249 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2250 "! TARGET_POWER"
2251 "@
2252 {muls|mullw} %0,%1,%2
2253 {muli|mulli} %0,%1,%2"
2254 [(set (attr "type")
2255 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2256 (const_string "imul3")
2257 (match_operand:SI 2 "short_cint_operand" "")
2258 (const_string "imul2")]
2259 (const_string "imul")))])
2260
2261 (define_insn "*mulsi3_mq_internal1"
2262 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2263 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2264 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2265 (const_int 0)))
2266 (clobber (match_scratch:SI 3 "=r,r"))
2267 (clobber (match_scratch:SI 4 "=q,q"))]
2268 "TARGET_POWER"
2269 "@
2270 {muls.|mullw.} %3,%1,%2
2271 #"
2272 [(set_attr "type" "imul_compare")
2273 (set_attr "length" "4,8")])
2274
2275 (define_split
2276 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2277 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2278 (match_operand:SI 2 "gpc_reg_operand" ""))
2279 (const_int 0)))
2280 (clobber (match_scratch:SI 3 ""))
2281 (clobber (match_scratch:SI 4 ""))]
2282 "TARGET_POWER && reload_completed"
2283 [(parallel [(set (match_dup 3)
2284 (mult:SI (match_dup 1) (match_dup 2)))
2285 (clobber (match_dup 4))])
2286 (set (match_dup 0)
2287 (compare:CC (match_dup 3)
2288 (const_int 0)))]
2289 "")
2290
2291 (define_insn "*mulsi3_no_mq_internal1"
2292 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2293 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2294 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2295 (const_int 0)))
2296 (clobber (match_scratch:SI 3 "=r,r"))]
2297 "! TARGET_POWER"
2298 "@
2299 {muls.|mullw.} %3,%1,%2
2300 #"
2301 [(set_attr "type" "imul_compare")
2302 (set_attr "length" "4,8")])
2303
2304 (define_split
2305 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2306 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2307 (match_operand:SI 2 "gpc_reg_operand" ""))
2308 (const_int 0)))
2309 (clobber (match_scratch:SI 3 ""))]
2310 "! TARGET_POWER && reload_completed"
2311 [(set (match_dup 3)
2312 (mult:SI (match_dup 1) (match_dup 2)))
2313 (set (match_dup 0)
2314 (compare:CC (match_dup 3)
2315 (const_int 0)))]
2316 "")
2317
2318 (define_insn "*mulsi3_mq_internal2"
2319 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2320 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2321 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2322 (const_int 0)))
2323 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2324 (mult:SI (match_dup 1) (match_dup 2)))
2325 (clobber (match_scratch:SI 4 "=q,q"))]
2326 "TARGET_POWER"
2327 "@
2328 {muls.|mullw.} %0,%1,%2
2329 #"
2330 [(set_attr "type" "imul_compare")
2331 (set_attr "length" "4,8")])
2332
2333 (define_split
2334 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2335 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2336 (match_operand:SI 2 "gpc_reg_operand" ""))
2337 (const_int 0)))
2338 (set (match_operand:SI 0 "gpc_reg_operand" "")
2339 (mult:SI (match_dup 1) (match_dup 2)))
2340 (clobber (match_scratch:SI 4 ""))]
2341 "TARGET_POWER && reload_completed"
2342 [(parallel [(set (match_dup 0)
2343 (mult:SI (match_dup 1) (match_dup 2)))
2344 (clobber (match_dup 4))])
2345 (set (match_dup 3)
2346 (compare:CC (match_dup 0)
2347 (const_int 0)))]
2348 "")
2349
2350 (define_insn "*mulsi3_no_mq_internal2"
2351 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2352 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2353 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2354 (const_int 0)))
2355 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2356 (mult:SI (match_dup 1) (match_dup 2)))]
2357 "! TARGET_POWER"
2358 "@
2359 {muls.|mullw.} %0,%1,%2
2360 #"
2361 [(set_attr "type" "imul_compare")
2362 (set_attr "length" "4,8")])
2363
2364 (define_split
2365 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2366 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2367 (match_operand:SI 2 "gpc_reg_operand" ""))
2368 (const_int 0)))
2369 (set (match_operand:SI 0 "gpc_reg_operand" "")
2370 (mult:SI (match_dup 1) (match_dup 2)))]
2371 "! TARGET_POWER && reload_completed"
2372 [(set (match_dup 0)
2373 (mult:SI (match_dup 1) (match_dup 2)))
2374 (set (match_dup 3)
2375 (compare:CC (match_dup 0)
2376 (const_int 0)))]
2377 "")
2378
2379 ;; Operand 1 is divided by operand 2; quotient goes to operand
2380 ;; 0 and remainder to operand 3.
2381 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2382
2383 (define_expand "divmodsi4"
2384 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2385 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2386 (match_operand:SI 2 "gpc_reg_operand" "")))
2387 (set (match_operand:SI 3 "register_operand" "")
2388 (mod:SI (match_dup 1) (match_dup 2)))])]
2389 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2390 "
2391 {
2392 if (! TARGET_POWER && ! TARGET_POWERPC)
2393 {
2394 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2395 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2396 emit_insn (gen_divss_call ());
2397 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2398 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2399 DONE;
2400 }
2401 }")
2402
2403 (define_insn "*divmodsi4_internal"
2404 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2405 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2406 (match_operand:SI 2 "gpc_reg_operand" "r")))
2407 (set (match_operand:SI 3 "register_operand" "=q")
2408 (mod:SI (match_dup 1) (match_dup 2)))]
2409 "TARGET_POWER"
2410 "divs %0,%1,%2"
2411 [(set_attr "type" "idiv")])
2412
2413 (define_expand "udiv<mode>3"
2414 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2415 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2416 (match_operand:GPR 2 "gpc_reg_operand" "")))]
2417 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2418 "
2419 {
2420 if (! TARGET_POWER && ! TARGET_POWERPC)
2421 {
2422 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2423 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2424 emit_insn (gen_quous_call ());
2425 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2426 DONE;
2427 }
2428 else if (TARGET_POWER)
2429 {
2430 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2431 DONE;
2432 }
2433 }")
2434
2435 (define_insn "udivsi3_mq"
2436 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2437 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2438 (match_operand:SI 2 "gpc_reg_operand" "r")))
2439 (clobber (match_scratch:SI 3 "=q"))]
2440 "TARGET_POWERPC && TARGET_POWER"
2441 "divwu %0,%1,%2"
2442 [(set_attr "type" "idiv")])
2443
2444 (define_insn "*udivsi3_no_mq"
2445 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2446 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2447 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2448 "TARGET_POWERPC && ! TARGET_POWER"
2449 "div<wd>u %0,%1,%2"
2450 [(set (attr "type")
2451 (cond [(match_operand:SI 0 "" "")
2452 (const_string "idiv")]
2453 (const_string "ldiv")))])
2454
2455
2456 ;; For powers of two we can do srai/aze for divide and then adjust for
2457 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2458 ;; used; for PowerPC, force operands into register and do a normal divide;
2459 ;; for AIX common-mode, use quoss call on register operands.
2460 (define_expand "div<mode>3"
2461 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2462 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2463 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2464 ""
2465 "
2466 {
2467 if (GET_CODE (operands[2]) == CONST_INT
2468 && INTVAL (operands[2]) > 0
2469 && exact_log2 (INTVAL (operands[2])) >= 0)
2470 ;
2471 else if (TARGET_POWERPC)
2472 {
2473 operands[2] = force_reg (<MODE>mode, operands[2]);
2474 if (TARGET_POWER)
2475 {
2476 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2477 DONE;
2478 }
2479 }
2480 else if (TARGET_POWER)
2481 FAIL;
2482 else
2483 {
2484 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2485 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2486 emit_insn (gen_quoss_call ());
2487 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2488 DONE;
2489 }
2490 }")
2491
2492 (define_insn "divsi3_mq"
2493 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2494 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2495 (match_operand:SI 2 "gpc_reg_operand" "r")))
2496 (clobber (match_scratch:SI 3 "=q"))]
2497 "TARGET_POWERPC && TARGET_POWER"
2498 "divw %0,%1,%2"
2499 [(set_attr "type" "idiv")])
2500
2501 (define_insn "*div<mode>3_no_mq"
2502 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2503 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2504 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2505 "TARGET_POWERPC && ! TARGET_POWER"
2506 "div<wd> %0,%1,%2"
2507 [(set (attr "type")
2508 (cond [(match_operand:SI 0 "" "")
2509 (const_string "idiv")]
2510 (const_string "ldiv")))])
2511
2512 (define_expand "mod<mode>3"
2513 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2514 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2515 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2516 ""
2517 "
2518 {
2519 int i;
2520 rtx temp1;
2521 rtx temp2;
2522
2523 if (GET_CODE (operands[2]) != CONST_INT
2524 || INTVAL (operands[2]) <= 0
2525 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2526 FAIL;
2527
2528 temp1 = gen_reg_rtx (<MODE>mode);
2529 temp2 = gen_reg_rtx (<MODE>mode);
2530
2531 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2532 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2533 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2534 DONE;
2535 }")
2536
2537 (define_insn ""
2538 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2539 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2540 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2541 ""
2542 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
2543 [(set_attr "type" "two")
2544 (set_attr "length" "8")])
2545
2546 (define_insn ""
2547 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2548 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2549 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2550 (const_int 0)))
2551 (clobber (match_scratch:P 3 "=r,r"))]
2552 ""
2553 "@
2554 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
2555 #"
2556 [(set_attr "type" "compare")
2557 (set_attr "length" "8,12")])
2558
2559 (define_split
2560 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2561 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2562 (match_operand:GPR 2 "exact_log2_cint_operand"
2563 ""))
2564 (const_int 0)))
2565 (clobber (match_scratch:GPR 3 ""))]
2566 "reload_completed"
2567 [(set (match_dup 3)
2568 (div:<MODE> (match_dup 1) (match_dup 2)))
2569 (set (match_dup 0)
2570 (compare:CC (match_dup 3)
2571 (const_int 0)))]
2572 "")
2573
2574 (define_insn ""
2575 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2576 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2577 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2578 (const_int 0)))
2579 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2580 (div:P (match_dup 1) (match_dup 2)))]
2581 ""
2582 "@
2583 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
2584 #"
2585 [(set_attr "type" "compare")
2586 (set_attr "length" "8,12")])
2587
2588 (define_split
2589 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2590 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2591 (match_operand:GPR 2 "exact_log2_cint_operand"
2592 ""))
2593 (const_int 0)))
2594 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2595 (div:GPR (match_dup 1) (match_dup 2)))]
2596 "reload_completed"
2597 [(set (match_dup 0)
2598 (div:<MODE> (match_dup 1) (match_dup 2)))
2599 (set (match_dup 3)
2600 (compare:CC (match_dup 0)
2601 (const_int 0)))]
2602 "")
2603
2604 (define_insn ""
2605 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2606 (udiv:SI
2607 (plus:DI (ashift:DI
2608 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2609 (const_int 32))
2610 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2611 (match_operand:SI 3 "gpc_reg_operand" "r")))
2612 (set (match_operand:SI 2 "register_operand" "=*q")
2613 (umod:SI
2614 (plus:DI (ashift:DI
2615 (zero_extend:DI (match_dup 1)) (const_int 32))
2616 (zero_extend:DI (match_dup 4)))
2617 (match_dup 3)))]
2618 "TARGET_POWER"
2619 "div %0,%1,%3"
2620 [(set_attr "type" "idiv")])
2621
2622 ;; To do unsigned divide we handle the cases of the divisor looking like a
2623 ;; negative number. If it is a constant that is less than 2**31, we don't
2624 ;; have to worry about the branches. So make a few subroutines here.
2625 ;;
2626 ;; First comes the normal case.
2627 (define_expand "udivmodsi4_normal"
2628 [(set (match_dup 4) (const_int 0))
2629 (parallel [(set (match_operand:SI 0 "" "")
2630 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2631 (const_int 32))
2632 (zero_extend:DI (match_operand:SI 1 "" "")))
2633 (match_operand:SI 2 "" "")))
2634 (set (match_operand:SI 3 "" "")
2635 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2636 (const_int 32))
2637 (zero_extend:DI (match_dup 1)))
2638 (match_dup 2)))])]
2639 "TARGET_POWER"
2640 "
2641 { operands[4] = gen_reg_rtx (SImode); }")
2642
2643 ;; This handles the branches.
2644 (define_expand "udivmodsi4_tests"
2645 [(set (match_operand:SI 0 "" "") (const_int 0))
2646 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2647 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2648 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2649 (label_ref (match_operand:SI 4 "" "")) (pc)))
2650 (set (match_dup 0) (const_int 1))
2651 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2652 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2653 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2654 (label_ref (match_dup 4)) (pc)))]
2655 "TARGET_POWER"
2656 "
2657 { operands[5] = gen_reg_rtx (CCUNSmode);
2658 operands[6] = gen_reg_rtx (CCmode);
2659 }")
2660
2661 (define_expand "udivmodsi4"
2662 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2663 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2664 (match_operand:SI 2 "reg_or_cint_operand" "")))
2665 (set (match_operand:SI 3 "gpc_reg_operand" "")
2666 (umod:SI (match_dup 1) (match_dup 2)))])]
2667 ""
2668 "
2669 {
2670 rtx label = 0;
2671
2672 if (! TARGET_POWER)
2673 {
2674 if (! TARGET_POWERPC)
2675 {
2676 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2677 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2678 emit_insn (gen_divus_call ());
2679 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2680 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2681 DONE;
2682 }
2683 else
2684 FAIL;
2685 }
2686
2687 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2688 {
2689 operands[2] = force_reg (SImode, operands[2]);
2690 label = gen_label_rtx ();
2691 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2692 operands[3], label));
2693 }
2694 else
2695 operands[2] = force_reg (SImode, operands[2]);
2696
2697 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2698 operands[3]));
2699 if (label)
2700 emit_label (label);
2701
2702 DONE;
2703 }")
2704
2705 ;; AIX architecture-independent common-mode multiply (DImode),
2706 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2707 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2708 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2709 ;; assumed unused if generating common-mode, so ignore.
2710 (define_insn "mulh_call"
2711 [(set (reg:SI 3)
2712 (truncate:SI
2713 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2714 (sign_extend:DI (reg:SI 4)))
2715 (const_int 32))))
2716 (clobber (reg:SI 65))]
2717 "! TARGET_POWER && ! TARGET_POWERPC"
2718 "bla __mulh"
2719 [(set_attr "type" "imul")])
2720
2721 (define_insn "mull_call"
2722 [(set (reg:DI 3)
2723 (mult:DI (sign_extend:DI (reg:SI 3))
2724 (sign_extend:DI (reg:SI 4))))
2725 (clobber (reg:SI 65))
2726 (clobber (reg:SI 0))]
2727 "! TARGET_POWER && ! TARGET_POWERPC"
2728 "bla __mull"
2729 [(set_attr "type" "imul")])
2730
2731 (define_insn "divss_call"
2732 [(set (reg:SI 3)
2733 (div:SI (reg:SI 3) (reg:SI 4)))
2734 (set (reg:SI 4)
2735 (mod:SI (reg:SI 3) (reg:SI 4)))
2736 (clobber (reg:SI 65))
2737 (clobber (reg:SI 0))]
2738 "! TARGET_POWER && ! TARGET_POWERPC"
2739 "bla __divss"
2740 [(set_attr "type" "idiv")])
2741
2742 (define_insn "divus_call"
2743 [(set (reg:SI 3)
2744 (udiv:SI (reg:SI 3) (reg:SI 4)))
2745 (set (reg:SI 4)
2746 (umod:SI (reg:SI 3) (reg:SI 4)))
2747 (clobber (reg:SI 65))
2748 (clobber (reg:SI 0))
2749 (clobber (match_scratch:CC 0 "=x"))
2750 (clobber (reg:CC 69))]
2751 "! TARGET_POWER && ! TARGET_POWERPC"
2752 "bla __divus"
2753 [(set_attr "type" "idiv")])
2754
2755 (define_insn "quoss_call"
2756 [(set (reg:SI 3)
2757 (div:SI (reg:SI 3) (reg:SI 4)))
2758 (clobber (reg:SI 65))]
2759 "! TARGET_POWER && ! TARGET_POWERPC"
2760 "bla __quoss"
2761 [(set_attr "type" "idiv")])
2762
2763 (define_insn "quous_call"
2764 [(set (reg:SI 3)
2765 (udiv:SI (reg:SI 3) (reg:SI 4)))
2766 (clobber (reg:SI 65))
2767 (clobber (reg:SI 0))
2768 (clobber (match_scratch:CC 0 "=x"))
2769 (clobber (reg:CC 69))]
2770 "! TARGET_POWER && ! TARGET_POWERPC"
2771 "bla __quous"
2772 [(set_attr "type" "idiv")])
2773 \f
2774 ;; Logical instructions
2775 ;; The logical instructions are mostly combined by using match_operator,
2776 ;; but the plain AND insns are somewhat different because there is no
2777 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2778 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2779
2780 (define_insn "andsi3"
2781 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2782 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2783 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2784 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2785 ""
2786 "@
2787 and %0,%1,%2
2788 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2789 {andil.|andi.} %0,%1,%b2
2790 {andiu.|andis.} %0,%1,%u2"
2791 [(set_attr "type" "*,*,compare,compare")])
2792
2793 ;; Note to set cr's other than cr0 we do the and immediate and then
2794 ;; the test again -- this avoids a mfcr which on the higher end
2795 ;; machines causes an execution serialization
2796
2797 (define_insn "*andsi3_internal2"
2798 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2799 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2800 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2801 (const_int 0)))
2802 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2803 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2804 "TARGET_32BIT"
2805 "@
2806 and. %3,%1,%2
2807 {andil.|andi.} %3,%1,%b2
2808 {andiu.|andis.} %3,%1,%u2
2809 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2810 #
2811 #
2812 #
2813 #"
2814 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2815 (set_attr "length" "4,4,4,4,8,8,8,8")])
2816
2817 (define_insn "*andsi3_internal3"
2818 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2819 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2820 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2821 (const_int 0)))
2822 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2823 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2824 "TARGET_64BIT"
2825 "@
2826 #
2827 {andil.|andi.} %3,%1,%b2
2828 {andiu.|andis.} %3,%1,%u2
2829 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2830 #
2831 #
2832 #
2833 #"
2834 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2835 (set_attr "length" "8,4,4,4,8,8,8,8")])
2836
2837 (define_split
2838 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2839 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2840 (match_operand:GPR 2 "and_operand" ""))
2841 (const_int 0)))
2842 (clobber (match_scratch:GPR 3 ""))
2843 (clobber (match_scratch:CC 4 ""))]
2844 "reload_completed"
2845 [(parallel [(set (match_dup 3)
2846 (and:<MODE> (match_dup 1)
2847 (match_dup 2)))
2848 (clobber (match_dup 4))])
2849 (set (match_dup 0)
2850 (compare:CC (match_dup 3)
2851 (const_int 0)))]
2852 "")
2853
2854 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2855 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2856
2857 (define_split
2858 [(set (match_operand:CC 0 "cc_reg_operand" "")
2859 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2860 (match_operand:SI 2 "gpc_reg_operand" ""))
2861 (const_int 0)))
2862 (clobber (match_scratch:SI 3 ""))
2863 (clobber (match_scratch:CC 4 ""))]
2864 "TARGET_POWERPC64 && reload_completed"
2865 [(parallel [(set (match_dup 3)
2866 (and:SI (match_dup 1)
2867 (match_dup 2)))
2868 (clobber (match_dup 4))])
2869 (set (match_dup 0)
2870 (compare:CC (match_dup 3)
2871 (const_int 0)))]
2872 "")
2873
2874 (define_insn "*andsi3_internal4"
2875 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2876 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2877 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2878 (const_int 0)))
2879 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2880 (and:SI (match_dup 1)
2881 (match_dup 2)))
2882 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2883 "TARGET_32BIT"
2884 "@
2885 and. %0,%1,%2
2886 {andil.|andi.} %0,%1,%b2
2887 {andiu.|andis.} %0,%1,%u2
2888 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2889 #
2890 #
2891 #
2892 #"
2893 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2894 (set_attr "length" "4,4,4,4,8,8,8,8")])
2895
2896 (define_insn "*andsi3_internal5"
2897 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2898 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2899 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2900 (const_int 0)))
2901 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2902 (and:SI (match_dup 1)
2903 (match_dup 2)))
2904 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2905 "TARGET_64BIT"
2906 "@
2907 #
2908 {andil.|andi.} %0,%1,%b2
2909 {andiu.|andis.} %0,%1,%u2
2910 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2911 #
2912 #
2913 #
2914 #"
2915 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2916 (set_attr "length" "8,4,4,4,8,8,8,8")])
2917
2918 (define_split
2919 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2920 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2921 (match_operand:SI 2 "and_operand" ""))
2922 (const_int 0)))
2923 (set (match_operand:SI 0 "gpc_reg_operand" "")
2924 (and:SI (match_dup 1)
2925 (match_dup 2)))
2926 (clobber (match_scratch:CC 4 ""))]
2927 "reload_completed"
2928 [(parallel [(set (match_dup 0)
2929 (and:SI (match_dup 1)
2930 (match_dup 2)))
2931 (clobber (match_dup 4))])
2932 (set (match_dup 3)
2933 (compare:CC (match_dup 0)
2934 (const_int 0)))]
2935 "")
2936
2937 (define_split
2938 [(set (match_operand:CC 3 "cc_reg_operand" "")
2939 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2940 (match_operand:SI 2 "gpc_reg_operand" ""))
2941 (const_int 0)))
2942 (set (match_operand:SI 0 "gpc_reg_operand" "")
2943 (and:SI (match_dup 1)
2944 (match_dup 2)))
2945 (clobber (match_scratch:CC 4 ""))]
2946 "TARGET_POWERPC64 && reload_completed"
2947 [(parallel [(set (match_dup 0)
2948 (and:SI (match_dup 1)
2949 (match_dup 2)))
2950 (clobber (match_dup 4))])
2951 (set (match_dup 3)
2952 (compare:CC (match_dup 0)
2953 (const_int 0)))]
2954 "")
2955
2956 ;; Handle the PowerPC64 rlwinm corner case
2957
2958 (define_insn_and_split "*andsi3_internal6"
2959 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2960 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2961 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2962 "TARGET_POWERPC64"
2963 "#"
2964 "TARGET_POWERPC64"
2965 [(set (match_dup 0)
2966 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2967 (match_dup 4)))
2968 (set (match_dup 0)
2969 (rotate:SI (match_dup 0) (match_dup 5)))]
2970 "
2971 {
2972 int mb = extract_MB (operands[2]);
2973 int me = extract_ME (operands[2]);
2974 operands[3] = GEN_INT (me + 1);
2975 operands[5] = GEN_INT (32 - (me + 1));
2976 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2977 }"
2978 [(set_attr "length" "8")])
2979
2980 (define_expand "iorsi3"
2981 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2982 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2983 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2984 ""
2985 "
2986 {
2987 if (GET_CODE (operands[2]) == CONST_INT
2988 && ! logical_operand (operands[2], SImode))
2989 {
2990 HOST_WIDE_INT value = INTVAL (operands[2]);
2991 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2992 ? operands[0] : gen_reg_rtx (SImode));
2993
2994 emit_insn (gen_iorsi3 (tmp, operands[1],
2995 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2996 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2997 DONE;
2998 }
2999 }")
3000
3001 (define_expand "xorsi3"
3002 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3003 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3004 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3005 ""
3006 "
3007 {
3008 if (GET_CODE (operands[2]) == CONST_INT
3009 && ! logical_operand (operands[2], SImode))
3010 {
3011 HOST_WIDE_INT value = INTVAL (operands[2]);
3012 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
3013 ? operands[0] : gen_reg_rtx (SImode));
3014
3015 emit_insn (gen_xorsi3 (tmp, operands[1],
3016 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3017 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3018 DONE;
3019 }
3020 }")
3021
3022 (define_insn "*boolsi3_internal1"
3023 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3024 (match_operator:SI 3 "boolean_or_operator"
3025 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3026 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3027 ""
3028 "@
3029 %q3 %0,%1,%2
3030 {%q3il|%q3i} %0,%1,%b2
3031 {%q3iu|%q3is} %0,%1,%u2")
3032
3033 (define_insn "*boolsi3_internal2"
3034 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3035 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3036 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3037 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3038 (const_int 0)))
3039 (clobber (match_scratch:SI 3 "=r,r"))]
3040 "TARGET_32BIT"
3041 "@
3042 %q4. %3,%1,%2
3043 #"
3044 [(set_attr "type" "compare")
3045 (set_attr "length" "4,8")])
3046
3047 (define_split
3048 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3049 (compare:CC (match_operator:SI 4 "boolean_operator"
3050 [(match_operand:SI 1 "gpc_reg_operand" "")
3051 (match_operand:SI 2 "gpc_reg_operand" "")])
3052 (const_int 0)))
3053 (clobber (match_scratch:SI 3 ""))]
3054 "TARGET_32BIT && reload_completed"
3055 [(set (match_dup 3) (match_dup 4))
3056 (set (match_dup 0)
3057 (compare:CC (match_dup 3)
3058 (const_int 0)))]
3059 "")
3060
3061 (define_insn "*boolsi3_internal3"
3062 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3063 (compare:CC (match_operator:SI 4 "boolean_operator"
3064 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3065 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3066 (const_int 0)))
3067 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3068 (match_dup 4))]
3069 "TARGET_32BIT"
3070 "@
3071 %q4. %0,%1,%2
3072 #"
3073 [(set_attr "type" "compare")
3074 (set_attr "length" "4,8")])
3075
3076 (define_split
3077 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3078 (compare:CC (match_operator:SI 4 "boolean_operator"
3079 [(match_operand:SI 1 "gpc_reg_operand" "")
3080 (match_operand:SI 2 "gpc_reg_operand" "")])
3081 (const_int 0)))
3082 (set (match_operand:SI 0 "gpc_reg_operand" "")
3083 (match_dup 4))]
3084 "TARGET_32BIT && reload_completed"
3085 [(set (match_dup 0) (match_dup 4))
3086 (set (match_dup 3)
3087 (compare:CC (match_dup 0)
3088 (const_int 0)))]
3089 "")
3090
3091 ;; Split a logical operation that we can't do in one insn into two insns,
3092 ;; each of which does one 16-bit part. This is used by combine.
3093
3094 (define_split
3095 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3096 (match_operator:SI 3 "boolean_or_operator"
3097 [(match_operand:SI 1 "gpc_reg_operand" "")
3098 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3099 ""
3100 [(set (match_dup 0) (match_dup 4))
3101 (set (match_dup 0) (match_dup 5))]
3102 "
3103 {
3104 rtx i;
3105 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3106 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3107 operands[1], i);
3108 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3109 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3110 operands[0], i);
3111 }")
3112
3113 (define_insn "*boolcsi3_internal1"
3114 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3115 (match_operator:SI 3 "boolean_operator"
3116 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3117 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3118 ""
3119 "%q3 %0,%2,%1")
3120
3121 (define_insn "*boolcsi3_internal2"
3122 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3123 (compare:CC (match_operator:SI 4 "boolean_operator"
3124 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3125 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3126 (const_int 0)))
3127 (clobber (match_scratch:SI 3 "=r,r"))]
3128 "TARGET_32BIT"
3129 "@
3130 %q4. %3,%2,%1
3131 #"
3132 [(set_attr "type" "compare")
3133 (set_attr "length" "4,8")])
3134
3135 (define_split
3136 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3137 (compare:CC (match_operator:SI 4 "boolean_operator"
3138 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3139 (match_operand:SI 2 "gpc_reg_operand" "")])
3140 (const_int 0)))
3141 (clobber (match_scratch:SI 3 ""))]
3142 "TARGET_32BIT && reload_completed"
3143 [(set (match_dup 3) (match_dup 4))
3144 (set (match_dup 0)
3145 (compare:CC (match_dup 3)
3146 (const_int 0)))]
3147 "")
3148
3149 (define_insn "*boolcsi3_internal3"
3150 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3151 (compare:CC (match_operator:SI 4 "boolean_operator"
3152 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3153 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3154 (const_int 0)))
3155 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3156 (match_dup 4))]
3157 "TARGET_32BIT"
3158 "@
3159 %q4. %0,%2,%1
3160 #"
3161 [(set_attr "type" "compare")
3162 (set_attr "length" "4,8")])
3163
3164 (define_split
3165 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3166 (compare:CC (match_operator:SI 4 "boolean_operator"
3167 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3168 (match_operand:SI 2 "gpc_reg_operand" "")])
3169 (const_int 0)))
3170 (set (match_operand:SI 0 "gpc_reg_operand" "")
3171 (match_dup 4))]
3172 "TARGET_32BIT && reload_completed"
3173 [(set (match_dup 0) (match_dup 4))
3174 (set (match_dup 3)
3175 (compare:CC (match_dup 0)
3176 (const_int 0)))]
3177 "")
3178
3179 (define_insn "*boolccsi3_internal1"
3180 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3181 (match_operator:SI 3 "boolean_operator"
3182 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3183 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3184 ""
3185 "%q3 %0,%1,%2")
3186
3187 (define_insn "*boolccsi3_internal2"
3188 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3189 (compare:CC (match_operator:SI 4 "boolean_operator"
3190 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3191 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3192 (const_int 0)))
3193 (clobber (match_scratch:SI 3 "=r,r"))]
3194 "TARGET_32BIT"
3195 "@
3196 %q4. %3,%1,%2
3197 #"
3198 [(set_attr "type" "compare")
3199 (set_attr "length" "4,8")])
3200
3201 (define_split
3202 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3203 (compare:CC (match_operator:SI 4 "boolean_operator"
3204 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3205 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3206 (const_int 0)))
3207 (clobber (match_scratch:SI 3 ""))]
3208 "TARGET_32BIT && reload_completed"
3209 [(set (match_dup 3) (match_dup 4))
3210 (set (match_dup 0)
3211 (compare:CC (match_dup 3)
3212 (const_int 0)))]
3213 "")
3214
3215 (define_insn "*boolccsi3_internal3"
3216 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3217 (compare:CC (match_operator:SI 4 "boolean_operator"
3218 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3219 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3220 (const_int 0)))
3221 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3222 (match_dup 4))]
3223 "TARGET_32BIT"
3224 "@
3225 %q4. %0,%1,%2
3226 #"
3227 [(set_attr "type" "compare")
3228 (set_attr "length" "4,8")])
3229
3230 (define_split
3231 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3232 (compare:CC (match_operator:SI 4 "boolean_operator"
3233 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3234 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3235 (const_int 0)))
3236 (set (match_operand:SI 0 "gpc_reg_operand" "")
3237 (match_dup 4))]
3238 "TARGET_32BIT && reload_completed"
3239 [(set (match_dup 0) (match_dup 4))
3240 (set (match_dup 3)
3241 (compare:CC (match_dup 0)
3242 (const_int 0)))]
3243 "")
3244
3245 ;; maskir insn. We need four forms because things might be in arbitrary
3246 ;; orders. Don't define forms that only set CR fields because these
3247 ;; would modify an input register.
3248
3249 (define_insn "*maskir_internal1"
3250 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3251 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3252 (match_operand:SI 1 "gpc_reg_operand" "0"))
3253 (and:SI (match_dup 2)
3254 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3255 "TARGET_POWER"
3256 "maskir %0,%3,%2")
3257
3258 (define_insn "*maskir_internal2"
3259 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3260 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3261 (match_operand:SI 1 "gpc_reg_operand" "0"))
3262 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3263 (match_dup 2))))]
3264 "TARGET_POWER"
3265 "maskir %0,%3,%2")
3266
3267 (define_insn "*maskir_internal3"
3268 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3269 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3270 (match_operand:SI 3 "gpc_reg_operand" "r"))
3271 (and:SI (not:SI (match_dup 2))
3272 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3273 "TARGET_POWER"
3274 "maskir %0,%3,%2")
3275
3276 (define_insn "*maskir_internal4"
3277 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3278 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3279 (match_operand:SI 2 "gpc_reg_operand" "r"))
3280 (and:SI (not:SI (match_dup 2))
3281 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3282 "TARGET_POWER"
3283 "maskir %0,%3,%2")
3284
3285 (define_insn "*maskir_internal5"
3286 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3287 (compare:CC
3288 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3289 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3290 (and:SI (match_dup 2)
3291 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3292 (const_int 0)))
3293 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3294 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3295 (and:SI (match_dup 2) (match_dup 3))))]
3296 "TARGET_POWER"
3297 "@
3298 maskir. %0,%3,%2
3299 #"
3300 [(set_attr "type" "compare")
3301 (set_attr "length" "4,8")])
3302
3303 (define_split
3304 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3305 (compare:CC
3306 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3307 (match_operand:SI 1 "gpc_reg_operand" ""))
3308 (and:SI (match_dup 2)
3309 (match_operand:SI 3 "gpc_reg_operand" "")))
3310 (const_int 0)))
3311 (set (match_operand:SI 0 "gpc_reg_operand" "")
3312 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3313 (and:SI (match_dup 2) (match_dup 3))))]
3314 "TARGET_POWER && reload_completed"
3315 [(set (match_dup 0)
3316 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3317 (and:SI (match_dup 2) (match_dup 3))))
3318 (set (match_dup 4)
3319 (compare:CC (match_dup 0)
3320 (const_int 0)))]
3321 "")
3322
3323 (define_insn "*maskir_internal6"
3324 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3325 (compare:CC
3326 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3327 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3328 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3329 (match_dup 2)))
3330 (const_int 0)))
3331 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3332 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3333 (and:SI (match_dup 3) (match_dup 2))))]
3334 "TARGET_POWER"
3335 "@
3336 maskir. %0,%3,%2
3337 #"
3338 [(set_attr "type" "compare")
3339 (set_attr "length" "4,8")])
3340
3341 (define_split
3342 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3343 (compare:CC
3344 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3345 (match_operand:SI 1 "gpc_reg_operand" ""))
3346 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3347 (match_dup 2)))
3348 (const_int 0)))
3349 (set (match_operand:SI 0 "gpc_reg_operand" "")
3350 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3351 (and:SI (match_dup 3) (match_dup 2))))]
3352 "TARGET_POWER && reload_completed"
3353 [(set (match_dup 0)
3354 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3355 (and:SI (match_dup 3) (match_dup 2))))
3356 (set (match_dup 4)
3357 (compare:CC (match_dup 0)
3358 (const_int 0)))]
3359 "")
3360
3361 (define_insn "*maskir_internal7"
3362 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3363 (compare:CC
3364 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3365 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3366 (and:SI (not:SI (match_dup 2))
3367 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3368 (const_int 0)))
3369 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3370 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3371 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3372 "TARGET_POWER"
3373 "@
3374 maskir. %0,%3,%2
3375 #"
3376 [(set_attr "type" "compare")
3377 (set_attr "length" "4,8")])
3378
3379 (define_split
3380 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3381 (compare:CC
3382 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3383 (match_operand:SI 3 "gpc_reg_operand" ""))
3384 (and:SI (not:SI (match_dup 2))
3385 (match_operand:SI 1 "gpc_reg_operand" "")))
3386 (const_int 0)))
3387 (set (match_operand:SI 0 "gpc_reg_operand" "")
3388 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3389 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3390 "TARGET_POWER && reload_completed"
3391 [(set (match_dup 0)
3392 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3393 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3394 (set (match_dup 4)
3395 (compare:CC (match_dup 0)
3396 (const_int 0)))]
3397 "")
3398
3399 (define_insn "*maskir_internal8"
3400 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3401 (compare:CC
3402 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3403 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3404 (and:SI (not:SI (match_dup 2))
3405 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3406 (const_int 0)))
3407 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3408 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3409 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3410 "TARGET_POWER"
3411 "@
3412 maskir. %0,%3,%2
3413 #"
3414 [(set_attr "type" "compare")
3415 (set_attr "length" "4,8")])
3416
3417 (define_split
3418 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3419 (compare:CC
3420 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3421 (match_operand:SI 2 "gpc_reg_operand" ""))
3422 (and:SI (not:SI (match_dup 2))
3423 (match_operand:SI 1 "gpc_reg_operand" "")))
3424 (const_int 0)))
3425 (set (match_operand:SI 0 "gpc_reg_operand" "")
3426 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3427 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3428 "TARGET_POWER && reload_completed"
3429 [(set (match_dup 0)
3430 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3431 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3432 (set (match_dup 4)
3433 (compare:CC (match_dup 0)
3434 (const_int 0)))]
3435 "")
3436 \f
3437 ;; Rotate and shift insns, in all their variants. These support shifts,
3438 ;; field inserts and extracts, and various combinations thereof.
3439 (define_expand "insv"
3440 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3441 (match_operand:SI 1 "const_int_operand" "")
3442 (match_operand:SI 2 "const_int_operand" ""))
3443 (match_operand 3 "gpc_reg_operand" ""))]
3444 ""
3445 "
3446 {
3447 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3448 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3449 compiler if the address of the structure is taken later. Likewise, do
3450 not handle invalid E500 subregs. */
3451 if (GET_CODE (operands[0]) == SUBREG
3452 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3453 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3454 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3455 FAIL;
3456
3457 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3458 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3459 else
3460 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3461 DONE;
3462 }")
3463
3464 (define_insn "insvsi"
3465 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3466 (match_operand:SI 1 "const_int_operand" "i")
3467 (match_operand:SI 2 "const_int_operand" "i"))
3468 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3469 ""
3470 "*
3471 {
3472 int start = INTVAL (operands[2]) & 31;
3473 int size = INTVAL (operands[1]) & 31;
3474
3475 operands[4] = GEN_INT (32 - start - size);
3476 operands[1] = GEN_INT (start + size - 1);
3477 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3478 }"
3479 [(set_attr "type" "insert_word")])
3480
3481 (define_insn "*insvsi_internal1"
3482 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3483 (match_operand:SI 1 "const_int_operand" "i")
3484 (match_operand:SI 2 "const_int_operand" "i"))
3485 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3486 (match_operand:SI 4 "const_int_operand" "i")))]
3487 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3488 "*
3489 {
3490 int shift = INTVAL (operands[4]) & 31;
3491 int start = INTVAL (operands[2]) & 31;
3492 int size = INTVAL (operands[1]) & 31;
3493
3494 operands[4] = GEN_INT (shift - start - size);
3495 operands[1] = GEN_INT (start + size - 1);
3496 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3497 }"
3498 [(set_attr "type" "insert_word")])
3499
3500 (define_insn "*insvsi_internal2"
3501 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3502 (match_operand:SI 1 "const_int_operand" "i")
3503 (match_operand:SI 2 "const_int_operand" "i"))
3504 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3505 (match_operand:SI 4 "const_int_operand" "i")))]
3506 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3507 "*
3508 {
3509 int shift = INTVAL (operands[4]) & 31;
3510 int start = INTVAL (operands[2]) & 31;
3511 int size = INTVAL (operands[1]) & 31;
3512
3513 operands[4] = GEN_INT (32 - shift - start - size);
3514 operands[1] = GEN_INT (start + size - 1);
3515 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3516 }"
3517 [(set_attr "type" "insert_word")])
3518
3519 (define_insn "*insvsi_internal3"
3520 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3521 (match_operand:SI 1 "const_int_operand" "i")
3522 (match_operand:SI 2 "const_int_operand" "i"))
3523 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3524 (match_operand:SI 4 "const_int_operand" "i")))]
3525 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3526 "*
3527 {
3528 int shift = INTVAL (operands[4]) & 31;
3529 int start = INTVAL (operands[2]) & 31;
3530 int size = INTVAL (operands[1]) & 31;
3531
3532 operands[4] = GEN_INT (32 - shift - start - size);
3533 operands[1] = GEN_INT (start + size - 1);
3534 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3535 }"
3536 [(set_attr "type" "insert_word")])
3537
3538 (define_insn "*insvsi_internal4"
3539 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3540 (match_operand:SI 1 "const_int_operand" "i")
3541 (match_operand:SI 2 "const_int_operand" "i"))
3542 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3543 (match_operand:SI 4 "const_int_operand" "i")
3544 (match_operand:SI 5 "const_int_operand" "i")))]
3545 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3546 "*
3547 {
3548 int extract_start = INTVAL (operands[5]) & 31;
3549 int extract_size = INTVAL (operands[4]) & 31;
3550 int insert_start = INTVAL (operands[2]) & 31;
3551 int insert_size = INTVAL (operands[1]) & 31;
3552
3553 /* Align extract field with insert field */
3554 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3555 operands[1] = GEN_INT (insert_start + insert_size - 1);
3556 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3557 }"
3558 [(set_attr "type" "insert_word")])
3559
3560 ;; combine patterns for rlwimi
3561 (define_insn "*insvsi_internal5"
3562 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3563 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3564 (match_operand:SI 1 "mask_operand" "i"))
3565 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3566 (match_operand:SI 2 "const_int_operand" "i"))
3567 (match_operand:SI 5 "mask_operand" "i"))))]
3568 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3569 "*
3570 {
3571 int me = extract_ME(operands[5]);
3572 int mb = extract_MB(operands[5]);
3573 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3574 operands[2] = GEN_INT(mb);
3575 operands[1] = GEN_INT(me);
3576 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3577 }"
3578 [(set_attr "type" "insert_word")])
3579
3580 (define_insn "*insvsi_internal6"
3581 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3582 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3583 (match_operand:SI 2 "const_int_operand" "i"))
3584 (match_operand:SI 5 "mask_operand" "i"))
3585 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3586 (match_operand:SI 1 "mask_operand" "i"))))]
3587 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3588 "*
3589 {
3590 int me = extract_ME(operands[5]);
3591 int mb = extract_MB(operands[5]);
3592 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3593 operands[2] = GEN_INT(mb);
3594 operands[1] = GEN_INT(me);
3595 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3596 }"
3597 [(set_attr "type" "insert_word")])
3598
3599 (define_insn "insvdi"
3600 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3601 (match_operand:SI 1 "const_int_operand" "i")
3602 (match_operand:SI 2 "const_int_operand" "i"))
3603 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3604 "TARGET_POWERPC64"
3605 "*
3606 {
3607 int start = INTVAL (operands[2]) & 63;
3608 int size = INTVAL (operands[1]) & 63;
3609
3610 operands[1] = GEN_INT (64 - start - size);
3611 return \"rldimi %0,%3,%H1,%H2\";
3612 }"
3613 [(set_attr "type" "insert_dword")])
3614
3615 (define_insn "*insvdi_internal2"
3616 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3617 (match_operand:SI 1 "const_int_operand" "i")
3618 (match_operand:SI 2 "const_int_operand" "i"))
3619 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3620 (match_operand:SI 4 "const_int_operand" "i")))]
3621 "TARGET_POWERPC64
3622 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3623 "*
3624 {
3625 int shift = INTVAL (operands[4]) & 63;
3626 int start = (INTVAL (operands[2]) & 63) - 32;
3627 int size = INTVAL (operands[1]) & 63;
3628
3629 operands[4] = GEN_INT (64 - shift - start - size);
3630 operands[2] = GEN_INT (start);
3631 operands[1] = GEN_INT (start + size - 1);
3632 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3633 }")
3634
3635 (define_insn "*insvdi_internal3"
3636 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3637 (match_operand:SI 1 "const_int_operand" "i")
3638 (match_operand:SI 2 "const_int_operand" "i"))
3639 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3640 (match_operand:SI 4 "const_int_operand" "i")))]
3641 "TARGET_POWERPC64
3642 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3643 "*
3644 {
3645 int shift = INTVAL (operands[4]) & 63;
3646 int start = (INTVAL (operands[2]) & 63) - 32;
3647 int size = INTVAL (operands[1]) & 63;
3648
3649 operands[4] = GEN_INT (64 - shift - start - size);
3650 operands[2] = GEN_INT (start);
3651 operands[1] = GEN_INT (start + size - 1);
3652 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3653 }")
3654
3655 (define_expand "extzv"
3656 [(set (match_operand 0 "gpc_reg_operand" "")
3657 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3658 (match_operand:SI 2 "const_int_operand" "")
3659 (match_operand:SI 3 "const_int_operand" "")))]
3660 ""
3661 "
3662 {
3663 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3664 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3665 compiler if the address of the structure is taken later. */
3666 if (GET_CODE (operands[0]) == SUBREG
3667 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3668 FAIL;
3669
3670 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3671 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3672 else
3673 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3674 DONE;
3675 }")
3676
3677 (define_insn "extzvsi"
3678 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3679 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3680 (match_operand:SI 2 "const_int_operand" "i")
3681 (match_operand:SI 3 "const_int_operand" "i")))]
3682 ""
3683 "*
3684 {
3685 int start = INTVAL (operands[3]) & 31;
3686 int size = INTVAL (operands[2]) & 31;
3687
3688 if (start + size >= 32)
3689 operands[3] = const0_rtx;
3690 else
3691 operands[3] = GEN_INT (start + size);
3692 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3693 }")
3694
3695 (define_insn "*extzvsi_internal1"
3696 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3697 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3698 (match_operand:SI 2 "const_int_operand" "i,i")
3699 (match_operand:SI 3 "const_int_operand" "i,i"))
3700 (const_int 0)))
3701 (clobber (match_scratch:SI 4 "=r,r"))]
3702 ""
3703 "*
3704 {
3705 int start = INTVAL (operands[3]) & 31;
3706 int size = INTVAL (operands[2]) & 31;
3707
3708 /* Force split for non-cc0 compare. */
3709 if (which_alternative == 1)
3710 return \"#\";
3711
3712 /* If the bit-field being tested fits in the upper or lower half of a
3713 word, it is possible to use andiu. or andil. to test it. This is
3714 useful because the condition register set-use delay is smaller for
3715 andi[ul]. than for rlinm. This doesn't work when the starting bit
3716 position is 0 because the LT and GT bits may be set wrong. */
3717
3718 if ((start > 0 && start + size <= 16) || start >= 16)
3719 {
3720 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3721 - (1 << (16 - (start & 15) - size))));
3722 if (start < 16)
3723 return \"{andiu.|andis.} %4,%1,%3\";
3724 else
3725 return \"{andil.|andi.} %4,%1,%3\";
3726 }
3727
3728 if (start + size >= 32)
3729 operands[3] = const0_rtx;
3730 else
3731 operands[3] = GEN_INT (start + size);
3732 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3733 }"
3734 [(set_attr "type" "delayed_compare")
3735 (set_attr "length" "4,8")])
3736
3737 (define_split
3738 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3739 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3740 (match_operand:SI 2 "const_int_operand" "")
3741 (match_operand:SI 3 "const_int_operand" ""))
3742 (const_int 0)))
3743 (clobber (match_scratch:SI 4 ""))]
3744 "reload_completed"
3745 [(set (match_dup 4)
3746 (zero_extract:SI (match_dup 1) (match_dup 2)
3747 (match_dup 3)))
3748 (set (match_dup 0)
3749 (compare:CC (match_dup 4)
3750 (const_int 0)))]
3751 "")
3752
3753 (define_insn "*extzvsi_internal2"
3754 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3755 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3756 (match_operand:SI 2 "const_int_operand" "i,i")
3757 (match_operand:SI 3 "const_int_operand" "i,i"))
3758 (const_int 0)))
3759 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3760 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3761 ""
3762 "*
3763 {
3764 int start = INTVAL (operands[3]) & 31;
3765 int size = INTVAL (operands[2]) & 31;
3766
3767 /* Force split for non-cc0 compare. */
3768 if (which_alternative == 1)
3769 return \"#\";
3770
3771 /* Since we are using the output value, we can't ignore any need for
3772 a shift. The bit-field must end at the LSB. */
3773 if (start >= 16 && start + size == 32)
3774 {
3775 operands[3] = GEN_INT ((1 << size) - 1);
3776 return \"{andil.|andi.} %0,%1,%3\";
3777 }
3778
3779 if (start + size >= 32)
3780 operands[3] = const0_rtx;
3781 else
3782 operands[3] = GEN_INT (start + size);
3783 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3784 }"
3785 [(set_attr "type" "delayed_compare")
3786 (set_attr "length" "4,8")])
3787
3788 (define_split
3789 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3790 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3791 (match_operand:SI 2 "const_int_operand" "")
3792 (match_operand:SI 3 "const_int_operand" ""))
3793 (const_int 0)))
3794 (set (match_operand:SI 0 "gpc_reg_operand" "")
3795 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3796 "reload_completed"
3797 [(set (match_dup 0)
3798 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3799 (set (match_dup 4)
3800 (compare:CC (match_dup 0)
3801 (const_int 0)))]
3802 "")
3803
3804 (define_insn "extzvdi"
3805 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3806 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3807 (match_operand:SI 2 "const_int_operand" "i")
3808 (match_operand:SI 3 "const_int_operand" "i")))]
3809 "TARGET_POWERPC64"
3810 "*
3811 {
3812 int start = INTVAL (operands[3]) & 63;
3813 int size = INTVAL (operands[2]) & 63;
3814
3815 if (start + size >= 64)
3816 operands[3] = const0_rtx;
3817 else
3818 operands[3] = GEN_INT (start + size);
3819 operands[2] = GEN_INT (64 - size);
3820 return \"rldicl %0,%1,%3,%2\";
3821 }")
3822
3823 (define_insn "*extzvdi_internal1"
3824 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3825 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3826 (match_operand:SI 2 "const_int_operand" "i")
3827 (match_operand:SI 3 "const_int_operand" "i"))
3828 (const_int 0)))
3829 (clobber (match_scratch:DI 4 "=r"))]
3830 "TARGET_64BIT"
3831 "*
3832 {
3833 int start = INTVAL (operands[3]) & 63;
3834 int size = INTVAL (operands[2]) & 63;
3835
3836 if (start + size >= 64)
3837 operands[3] = const0_rtx;
3838 else
3839 operands[3] = GEN_INT (start + size);
3840 operands[2] = GEN_INT (64 - size);
3841 return \"rldicl. %4,%1,%3,%2\";
3842 }"
3843 [(set_attr "type" "compare")])
3844
3845 (define_insn "*extzvdi_internal2"
3846 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3847 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3848 (match_operand:SI 2 "const_int_operand" "i")
3849 (match_operand:SI 3 "const_int_operand" "i"))
3850 (const_int 0)))
3851 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3852 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3853 "TARGET_64BIT"
3854 "*
3855 {
3856 int start = INTVAL (operands[3]) & 63;
3857 int size = INTVAL (operands[2]) & 63;
3858
3859 if (start + size >= 64)
3860 operands[3] = const0_rtx;
3861 else
3862 operands[3] = GEN_INT (start + size);
3863 operands[2] = GEN_INT (64 - size);
3864 return \"rldicl. %0,%1,%3,%2\";
3865 }"
3866 [(set_attr "type" "compare")])
3867
3868 (define_insn "rotlsi3"
3869 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3870 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3871 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
3872 ""
3873 "@
3874 {rlnm|rlwnm} %0,%1,%2,0xffffffff
3875 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
3876 [(set_attr "type" "var_shift_rotate,integer")])
3877
3878 (define_insn "*rotlsi3_internal2"
3879 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3880 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3881 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3882 (const_int 0)))
3883 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3884 ""
3885 "@
3886 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
3887 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
3888 #
3889 #"
3890 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3891 (set_attr "length" "4,4,8,8")])
3892
3893 (define_split
3894 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3895 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3896 (match_operand:SI 2 "reg_or_cint_operand" ""))
3897 (const_int 0)))
3898 (clobber (match_scratch:SI 3 ""))]
3899 "reload_completed"
3900 [(set (match_dup 3)
3901 (rotate:SI (match_dup 1) (match_dup 2)))
3902 (set (match_dup 0)
3903 (compare:CC (match_dup 3)
3904 (const_int 0)))]
3905 "")
3906
3907 (define_insn "*rotlsi3_internal3"
3908 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3909 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3910 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3911 (const_int 0)))
3912 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3913 (rotate:SI (match_dup 1) (match_dup 2)))]
3914 ""
3915 "@
3916 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
3917 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
3918 #
3919 #"
3920 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3921 (set_attr "length" "4,4,8,8")])
3922
3923 (define_split
3924 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3925 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3926 (match_operand:SI 2 "reg_or_cint_operand" ""))
3927 (const_int 0)))
3928 (set (match_operand:SI 0 "gpc_reg_operand" "")
3929 (rotate:SI (match_dup 1) (match_dup 2)))]
3930 "reload_completed"
3931 [(set (match_dup 0)
3932 (rotate:SI (match_dup 1) (match_dup 2)))
3933 (set (match_dup 3)
3934 (compare:CC (match_dup 0)
3935 (const_int 0)))]
3936 "")
3937
3938 (define_insn "*rotlsi3_internal4"
3939 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3940 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3941 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
3942 (match_operand:SI 3 "mask_operand" "n,n")))]
3943 ""
3944 "@
3945 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
3946 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
3947 [(set_attr "type" "var_shift_rotate,integer")])
3948
3949 (define_insn "*rotlsi3_internal5"
3950 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3951 (compare:CC (and:SI
3952 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3953 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3954 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3955 (const_int 0)))
3956 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
3957 ""
3958 "@
3959 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
3960 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3961 #
3962 #"
3963 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3964 (set_attr "length" "4,4,8,8")])
3965
3966 (define_split
3967 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3968 (compare:CC (and:SI
3969 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3970 (match_operand:SI 2 "reg_or_cint_operand" ""))
3971 (match_operand:SI 3 "mask_operand" ""))
3972 (const_int 0)))
3973 (clobber (match_scratch:SI 4 ""))]
3974 "reload_completed"
3975 [(set (match_dup 4)
3976 (and:SI (rotate:SI (match_dup 1)
3977 (match_dup 2))
3978 (match_dup 3)))
3979 (set (match_dup 0)
3980 (compare:CC (match_dup 4)
3981 (const_int 0)))]
3982 "")
3983
3984 (define_insn "*rotlsi3_internal6"
3985 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
3986 (compare:CC (and:SI
3987 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3988 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3989 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3990 (const_int 0)))
3991 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3992 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3993 ""
3994 "@
3995 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
3996 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3997 #
3998 #"
3999 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4000 (set_attr "length" "4,4,8,8")])
4001
4002 (define_split
4003 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4004 (compare:CC (and:SI
4005 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4006 (match_operand:SI 2 "reg_or_cint_operand" ""))
4007 (match_operand:SI 3 "mask_operand" ""))
4008 (const_int 0)))
4009 (set (match_operand:SI 0 "gpc_reg_operand" "")
4010 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4011 "reload_completed"
4012 [(set (match_dup 0)
4013 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4014 (set (match_dup 4)
4015 (compare:CC (match_dup 0)
4016 (const_int 0)))]
4017 "")
4018
4019 (define_insn "*rotlsi3_internal7"
4020 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4021 (zero_extend:SI
4022 (subreg:QI
4023 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4024 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4025 ""
4026 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
4027
4028 (define_insn "*rotlsi3_internal8"
4029 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4030 (compare:CC (zero_extend:SI
4031 (subreg:QI
4032 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4033 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4034 (const_int 0)))
4035 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4036 ""
4037 "@
4038 {rlnm.|rlwnm.} %3,%1,%2,0xff
4039 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4040 #
4041 #"
4042 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4043 (set_attr "length" "4,4,8,8")])
4044
4045 (define_split
4046 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4047 (compare:CC (zero_extend:SI
4048 (subreg:QI
4049 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4050 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4051 (const_int 0)))
4052 (clobber (match_scratch:SI 3 ""))]
4053 "reload_completed"
4054 [(set (match_dup 3)
4055 (zero_extend:SI (subreg:QI
4056 (rotate:SI (match_dup 1)
4057 (match_dup 2)) 0)))
4058 (set (match_dup 0)
4059 (compare:CC (match_dup 3)
4060 (const_int 0)))]
4061 "")
4062
4063 (define_insn "*rotlsi3_internal9"
4064 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4065 (compare:CC (zero_extend:SI
4066 (subreg:QI
4067 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4068 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4069 (const_int 0)))
4070 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4071 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4072 ""
4073 "@
4074 {rlnm.|rlwnm.} %0,%1,%2,0xff
4075 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4076 #
4077 #"
4078 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4079 (set_attr "length" "4,4,8,8")])
4080
4081 (define_split
4082 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4083 (compare:CC (zero_extend:SI
4084 (subreg:QI
4085 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4086 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4087 (const_int 0)))
4088 (set (match_operand:SI 0 "gpc_reg_operand" "")
4089 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4090 "reload_completed"
4091 [(set (match_dup 0)
4092 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4093 (set (match_dup 3)
4094 (compare:CC (match_dup 0)
4095 (const_int 0)))]
4096 "")
4097
4098 (define_insn "*rotlsi3_internal10"
4099 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4100 (zero_extend:SI
4101 (subreg:HI
4102 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4103 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4104 ""
4105 "@
4106 {rlnm|rlwnm} %0,%1,%2,0xffff
4107 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4108 [(set_attr "type" "var_shift_rotate,integer")])
4109
4110
4111 (define_insn "*rotlsi3_internal11"
4112 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4113 (compare:CC (zero_extend:SI
4114 (subreg:HI
4115 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4116 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4117 (const_int 0)))
4118 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4119 ""
4120 "@
4121 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4122 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4123 #
4124 #"
4125 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4126 (set_attr "length" "4,4,8,8")])
4127
4128 (define_split
4129 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4130 (compare:CC (zero_extend:SI
4131 (subreg:HI
4132 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4133 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4134 (const_int 0)))
4135 (clobber (match_scratch:SI 3 ""))]
4136 "reload_completed"
4137 [(set (match_dup 3)
4138 (zero_extend:SI (subreg:HI
4139 (rotate:SI (match_dup 1)
4140 (match_dup 2)) 0)))
4141 (set (match_dup 0)
4142 (compare:CC (match_dup 3)
4143 (const_int 0)))]
4144 "")
4145
4146 (define_insn "*rotlsi3_internal12"
4147 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4148 (compare:CC (zero_extend:SI
4149 (subreg:HI
4150 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4151 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4152 (const_int 0)))
4153 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4154 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4155 ""
4156 "@
4157 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4158 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4159 #
4160 #"
4161 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4162 (set_attr "length" "4,4,8,8")])
4163
4164 (define_split
4165 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4166 (compare:CC (zero_extend:SI
4167 (subreg:HI
4168 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4169 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4170 (const_int 0)))
4171 (set (match_operand:SI 0 "gpc_reg_operand" "")
4172 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4173 "reload_completed"
4174 [(set (match_dup 0)
4175 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4176 (set (match_dup 3)
4177 (compare:CC (match_dup 0)
4178 (const_int 0)))]
4179 "")
4180
4181 ;; Note that we use "sle." instead of "sl." so that we can set
4182 ;; SHIFT_COUNT_TRUNCATED.
4183
4184 (define_expand "ashlsi3"
4185 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4186 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4187 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4188 ""
4189 "
4190 {
4191 if (TARGET_POWER)
4192 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4193 else
4194 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4195 DONE;
4196 }")
4197
4198 (define_insn "ashlsi3_power"
4199 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4200 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4201 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4202 (clobber (match_scratch:SI 3 "=q,X"))]
4203 "TARGET_POWER"
4204 "@
4205 sle %0,%1,%2
4206 {sli|slwi} %0,%1,%h2")
4207
4208 (define_insn "ashlsi3_no_power"
4209 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4210 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4211 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4212 "! TARGET_POWER"
4213 "@
4214 {sl|slw} %0,%1,%2
4215 {sli|slwi} %0,%1,%h2"
4216 [(set_attr "type" "var_shift_rotate,shift")])
4217
4218 (define_insn ""
4219 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4220 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4221 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4222 (const_int 0)))
4223 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4224 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4225 "TARGET_POWER"
4226 "@
4227 sle. %3,%1,%2
4228 {sli.|slwi.} %3,%1,%h2
4229 #
4230 #"
4231 [(set_attr "type" "delayed_compare")
4232 (set_attr "length" "4,4,8,8")])
4233
4234 (define_split
4235 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4236 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4237 (match_operand:SI 2 "reg_or_cint_operand" ""))
4238 (const_int 0)))
4239 (clobber (match_scratch:SI 3 ""))
4240 (clobber (match_scratch:SI 4 ""))]
4241 "TARGET_POWER && reload_completed"
4242 [(parallel [(set (match_dup 3)
4243 (ashift:SI (match_dup 1) (match_dup 2)))
4244 (clobber (match_dup 4))])
4245 (set (match_dup 0)
4246 (compare:CC (match_dup 3)
4247 (const_int 0)))]
4248 "")
4249
4250 (define_insn ""
4251 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4252 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4253 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4254 (const_int 0)))
4255 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4256 "! TARGET_POWER && TARGET_32BIT"
4257 "@
4258 {sl.|slw.} %3,%1,%2
4259 {sli.|slwi.} %3,%1,%h2
4260 #
4261 #"
4262 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4263 (set_attr "length" "4,4,8,8")])
4264
4265 (define_split
4266 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4267 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4268 (match_operand:SI 2 "reg_or_cint_operand" ""))
4269 (const_int 0)))
4270 (clobber (match_scratch:SI 3 ""))]
4271 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4272 [(set (match_dup 3)
4273 (ashift:SI (match_dup 1) (match_dup 2)))
4274 (set (match_dup 0)
4275 (compare:CC (match_dup 3)
4276 (const_int 0)))]
4277 "")
4278
4279 (define_insn ""
4280 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4281 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4282 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4283 (const_int 0)))
4284 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4285 (ashift:SI (match_dup 1) (match_dup 2)))
4286 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4287 "TARGET_POWER"
4288 "@
4289 sle. %0,%1,%2
4290 {sli.|slwi.} %0,%1,%h2
4291 #
4292 #"
4293 [(set_attr "type" "delayed_compare")
4294 (set_attr "length" "4,4,8,8")])
4295
4296 (define_split
4297 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4298 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4299 (match_operand:SI 2 "reg_or_cint_operand" ""))
4300 (const_int 0)))
4301 (set (match_operand:SI 0 "gpc_reg_operand" "")
4302 (ashift:SI (match_dup 1) (match_dup 2)))
4303 (clobber (match_scratch:SI 4 ""))]
4304 "TARGET_POWER && reload_completed"
4305 [(parallel [(set (match_dup 0)
4306 (ashift:SI (match_dup 1) (match_dup 2)))
4307 (clobber (match_dup 4))])
4308 (set (match_dup 3)
4309 (compare:CC (match_dup 0)
4310 (const_int 0)))]
4311 "")
4312
4313 (define_insn ""
4314 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4315 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4316 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4317 (const_int 0)))
4318 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4319 (ashift:SI (match_dup 1) (match_dup 2)))]
4320 "! TARGET_POWER && TARGET_32BIT"
4321 "@
4322 {sl.|slw.} %0,%1,%2
4323 {sli.|slwi.} %0,%1,%h2
4324 #
4325 #"
4326 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4327 (set_attr "length" "4,4,8,8")])
4328
4329 (define_split
4330 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4331 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4332 (match_operand:SI 2 "reg_or_cint_operand" ""))
4333 (const_int 0)))
4334 (set (match_operand:SI 0 "gpc_reg_operand" "")
4335 (ashift:SI (match_dup 1) (match_dup 2)))]
4336 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4337 [(set (match_dup 0)
4338 (ashift:SI (match_dup 1) (match_dup 2)))
4339 (set (match_dup 3)
4340 (compare:CC (match_dup 0)
4341 (const_int 0)))]
4342 "")
4343
4344 (define_insn "rlwinm"
4345 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4346 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4347 (match_operand:SI 2 "const_int_operand" "i"))
4348 (match_operand:SI 3 "mask_operand" "n")))]
4349 "includes_lshift_p (operands[2], operands[3])"
4350 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4351
4352 (define_insn ""
4353 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4354 (compare:CC
4355 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4356 (match_operand:SI 2 "const_int_operand" "i,i"))
4357 (match_operand:SI 3 "mask_operand" "n,n"))
4358 (const_int 0)))
4359 (clobber (match_scratch:SI 4 "=r,r"))]
4360 "includes_lshift_p (operands[2], operands[3])"
4361 "@
4362 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4363 #"
4364 [(set_attr "type" "delayed_compare")
4365 (set_attr "length" "4,8")])
4366
4367 (define_split
4368 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4369 (compare:CC
4370 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4371 (match_operand:SI 2 "const_int_operand" ""))
4372 (match_operand:SI 3 "mask_operand" ""))
4373 (const_int 0)))
4374 (clobber (match_scratch:SI 4 ""))]
4375 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4376 [(set (match_dup 4)
4377 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4378 (match_dup 3)))
4379 (set (match_dup 0)
4380 (compare:CC (match_dup 4)
4381 (const_int 0)))]
4382 "")
4383
4384 (define_insn ""
4385 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4386 (compare:CC
4387 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4388 (match_operand:SI 2 "const_int_operand" "i,i"))
4389 (match_operand:SI 3 "mask_operand" "n,n"))
4390 (const_int 0)))
4391 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4392 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4393 "includes_lshift_p (operands[2], operands[3])"
4394 "@
4395 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4396 #"
4397 [(set_attr "type" "delayed_compare")
4398 (set_attr "length" "4,8")])
4399
4400 (define_split
4401 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4402 (compare:CC
4403 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4404 (match_operand:SI 2 "const_int_operand" ""))
4405 (match_operand:SI 3 "mask_operand" ""))
4406 (const_int 0)))
4407 (set (match_operand:SI 0 "gpc_reg_operand" "")
4408 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4409 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4410 [(set (match_dup 0)
4411 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4412 (set (match_dup 4)
4413 (compare:CC (match_dup 0)
4414 (const_int 0)))]
4415 "")
4416
4417 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
4418 ;; "sli x,x,0".
4419 (define_expand "lshrsi3"
4420 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4421 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4422 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4423 ""
4424 "
4425 {
4426 if (TARGET_POWER)
4427 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4428 else
4429 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
4430 DONE;
4431 }")
4432
4433 (define_insn "lshrsi3_power"
4434 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4435 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4436 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4437 (clobber (match_scratch:SI 3 "=q,X,X"))]
4438 "TARGET_POWER"
4439 "@
4440 sre %0,%1,%2
4441 mr %0,%1
4442 {s%A2i|s%A2wi} %0,%1,%h2")
4443
4444 (define_insn "lshrsi3_no_power"
4445 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4446 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4447 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
4448 "! TARGET_POWER"
4449 "@
4450 mr %0,%1
4451 {sr|srw} %0,%1,%2
4452 {sri|srwi} %0,%1,%h2"
4453 [(set_attr "type" "integer,var_shift_rotate,shift")])
4454
4455 (define_insn ""
4456 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4457 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4458 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4459 (const_int 0)))
4460 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4461 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4462 "TARGET_POWER"
4463 "@
4464 sre. %3,%1,%2
4465 mr. %1,%1
4466 {s%A2i.|s%A2wi.} %3,%1,%h2
4467 #
4468 #
4469 #"
4470 [(set_attr "type" "delayed_compare")
4471 (set_attr "length" "4,4,4,8,8,8")])
4472
4473 (define_split
4474 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4475 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4476 (match_operand:SI 2 "reg_or_cint_operand" ""))
4477 (const_int 0)))
4478 (clobber (match_scratch:SI 3 ""))
4479 (clobber (match_scratch:SI 4 ""))]
4480 "TARGET_POWER && reload_completed"
4481 [(parallel [(set (match_dup 3)
4482 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4483 (clobber (match_dup 4))])
4484 (set (match_dup 0)
4485 (compare:CC (match_dup 3)
4486 (const_int 0)))]
4487 "")
4488
4489 (define_insn ""
4490 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4491 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4492 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4493 (const_int 0)))
4494 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4495 "! TARGET_POWER && TARGET_32BIT"
4496 "@
4497 mr. %1,%1
4498 {sr.|srw.} %3,%1,%2
4499 {sri.|srwi.} %3,%1,%h2
4500 #
4501 #
4502 #"
4503 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4504 (set_attr "length" "4,4,4,8,8,8")])
4505
4506 (define_split
4507 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4508 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4509 (match_operand:SI 2 "reg_or_cint_operand" ""))
4510 (const_int 0)))
4511 (clobber (match_scratch:SI 3 ""))]
4512 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4513 [(set (match_dup 3)
4514 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4515 (set (match_dup 0)
4516 (compare:CC (match_dup 3)
4517 (const_int 0)))]
4518 "")
4519
4520 (define_insn ""
4521 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4522 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4523 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4524 (const_int 0)))
4525 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4526 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4527 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4528 "TARGET_POWER"
4529 "@
4530 sre. %0,%1,%2
4531 mr. %0,%1
4532 {s%A2i.|s%A2wi.} %0,%1,%h2
4533 #
4534 #
4535 #"
4536 [(set_attr "type" "delayed_compare")
4537 (set_attr "length" "4,4,4,8,8,8")])
4538
4539 (define_split
4540 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4541 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4542 (match_operand:SI 2 "reg_or_cint_operand" ""))
4543 (const_int 0)))
4544 (set (match_operand:SI 0 "gpc_reg_operand" "")
4545 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4546 (clobber (match_scratch:SI 4 ""))]
4547 "TARGET_POWER && reload_completed"
4548 [(parallel [(set (match_dup 0)
4549 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4550 (clobber (match_dup 4))])
4551 (set (match_dup 3)
4552 (compare:CC (match_dup 0)
4553 (const_int 0)))]
4554 "")
4555
4556 (define_insn ""
4557 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4558 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4559 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4560 (const_int 0)))
4561 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4562 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4563 "! TARGET_POWER && TARGET_32BIT"
4564 "@
4565 mr. %0,%1
4566 {sr.|srw.} %0,%1,%2
4567 {sri.|srwi.} %0,%1,%h2
4568 #
4569 #
4570 #"
4571 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4572 (set_attr "length" "4,4,4,8,8,8")])
4573
4574 (define_split
4575 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4576 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4577 (match_operand:SI 2 "reg_or_cint_operand" ""))
4578 (const_int 0)))
4579 (set (match_operand:SI 0 "gpc_reg_operand" "")
4580 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4581 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4582 [(set (match_dup 0)
4583 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4584 (set (match_dup 3)
4585 (compare:CC (match_dup 0)
4586 (const_int 0)))]
4587 "")
4588
4589 (define_insn ""
4590 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4591 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4592 (match_operand:SI 2 "const_int_operand" "i"))
4593 (match_operand:SI 3 "mask_operand" "n")))]
4594 "includes_rshift_p (operands[2], operands[3])"
4595 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4596
4597 (define_insn ""
4598 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4599 (compare:CC
4600 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4601 (match_operand:SI 2 "const_int_operand" "i,i"))
4602 (match_operand:SI 3 "mask_operand" "n,n"))
4603 (const_int 0)))
4604 (clobber (match_scratch:SI 4 "=r,r"))]
4605 "includes_rshift_p (operands[2], operands[3])"
4606 "@
4607 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4608 #"
4609 [(set_attr "type" "delayed_compare")
4610 (set_attr "length" "4,8")])
4611
4612 (define_split
4613 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4614 (compare:CC
4615 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4616 (match_operand:SI 2 "const_int_operand" ""))
4617 (match_operand:SI 3 "mask_operand" ""))
4618 (const_int 0)))
4619 (clobber (match_scratch:SI 4 ""))]
4620 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4621 [(set (match_dup 4)
4622 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4623 (match_dup 3)))
4624 (set (match_dup 0)
4625 (compare:CC (match_dup 4)
4626 (const_int 0)))]
4627 "")
4628
4629 (define_insn ""
4630 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4631 (compare:CC
4632 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4633 (match_operand:SI 2 "const_int_operand" "i,i"))
4634 (match_operand:SI 3 "mask_operand" "n,n"))
4635 (const_int 0)))
4636 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4637 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4638 "includes_rshift_p (operands[2], operands[3])"
4639 "@
4640 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4641 #"
4642 [(set_attr "type" "delayed_compare")
4643 (set_attr "length" "4,8")])
4644
4645 (define_split
4646 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4647 (compare:CC
4648 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4649 (match_operand:SI 2 "const_int_operand" ""))
4650 (match_operand:SI 3 "mask_operand" ""))
4651 (const_int 0)))
4652 (set (match_operand:SI 0 "gpc_reg_operand" "")
4653 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4654 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4655 [(set (match_dup 0)
4656 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4657 (set (match_dup 4)
4658 (compare:CC (match_dup 0)
4659 (const_int 0)))]
4660 "")
4661
4662 (define_insn ""
4663 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4664 (zero_extend:SI
4665 (subreg:QI
4666 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4667 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4668 "includes_rshift_p (operands[2], GEN_INT (255))"
4669 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4670
4671 (define_insn ""
4672 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4673 (compare:CC
4674 (zero_extend:SI
4675 (subreg:QI
4676 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4677 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4678 (const_int 0)))
4679 (clobber (match_scratch:SI 3 "=r,r"))]
4680 "includes_rshift_p (operands[2], GEN_INT (255))"
4681 "@
4682 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4683 #"
4684 [(set_attr "type" "delayed_compare")
4685 (set_attr "length" "4,8")])
4686
4687 (define_split
4688 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4689 (compare:CC
4690 (zero_extend:SI
4691 (subreg:QI
4692 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4693 (match_operand:SI 2 "const_int_operand" "")) 0))
4694 (const_int 0)))
4695 (clobber (match_scratch:SI 3 ""))]
4696 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4697 [(set (match_dup 3)
4698 (zero_extend:SI (subreg:QI
4699 (lshiftrt:SI (match_dup 1)
4700 (match_dup 2)) 0)))
4701 (set (match_dup 0)
4702 (compare:CC (match_dup 3)
4703 (const_int 0)))]
4704 "")
4705
4706 (define_insn ""
4707 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4708 (compare:CC
4709 (zero_extend:SI
4710 (subreg:QI
4711 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4712 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4713 (const_int 0)))
4714 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4715 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4716 "includes_rshift_p (operands[2], GEN_INT (255))"
4717 "@
4718 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4719 #"
4720 [(set_attr "type" "delayed_compare")
4721 (set_attr "length" "4,8")])
4722
4723 (define_split
4724 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4725 (compare:CC
4726 (zero_extend:SI
4727 (subreg:QI
4728 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4729 (match_operand:SI 2 "const_int_operand" "")) 0))
4730 (const_int 0)))
4731 (set (match_operand:SI 0 "gpc_reg_operand" "")
4732 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4733 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4734 [(set (match_dup 0)
4735 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4736 (set (match_dup 3)
4737 (compare:CC (match_dup 0)
4738 (const_int 0)))]
4739 "")
4740
4741 (define_insn ""
4742 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4743 (zero_extend:SI
4744 (subreg:HI
4745 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4746 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4747 "includes_rshift_p (operands[2], GEN_INT (65535))"
4748 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4749
4750 (define_insn ""
4751 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4752 (compare:CC
4753 (zero_extend:SI
4754 (subreg:HI
4755 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4756 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4757 (const_int 0)))
4758 (clobber (match_scratch:SI 3 "=r,r"))]
4759 "includes_rshift_p (operands[2], GEN_INT (65535))"
4760 "@
4761 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4762 #"
4763 [(set_attr "type" "delayed_compare")
4764 (set_attr "length" "4,8")])
4765
4766 (define_split
4767 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4768 (compare:CC
4769 (zero_extend:SI
4770 (subreg:HI
4771 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4772 (match_operand:SI 2 "const_int_operand" "")) 0))
4773 (const_int 0)))
4774 (clobber (match_scratch:SI 3 ""))]
4775 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4776 [(set (match_dup 3)
4777 (zero_extend:SI (subreg:HI
4778 (lshiftrt:SI (match_dup 1)
4779 (match_dup 2)) 0)))
4780 (set (match_dup 0)
4781 (compare:CC (match_dup 3)
4782 (const_int 0)))]
4783 "")
4784
4785 (define_insn ""
4786 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4787 (compare:CC
4788 (zero_extend:SI
4789 (subreg:HI
4790 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4791 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4792 (const_int 0)))
4793 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4794 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4795 "includes_rshift_p (operands[2], GEN_INT (65535))"
4796 "@
4797 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4798 #"
4799 [(set_attr "type" "delayed_compare")
4800 (set_attr "length" "4,8")])
4801
4802 (define_split
4803 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4804 (compare:CC
4805 (zero_extend:SI
4806 (subreg:HI
4807 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4808 (match_operand:SI 2 "const_int_operand" "")) 0))
4809 (const_int 0)))
4810 (set (match_operand:SI 0 "gpc_reg_operand" "")
4811 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4812 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4813 [(set (match_dup 0)
4814 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4815 (set (match_dup 3)
4816 (compare:CC (match_dup 0)
4817 (const_int 0)))]
4818 "")
4819
4820 (define_insn ""
4821 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4822 (const_int 1)
4823 (match_operand:SI 1 "gpc_reg_operand" "r"))
4824 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4825 (const_int 31)))]
4826 "TARGET_POWER"
4827 "rrib %0,%1,%2")
4828
4829 (define_insn ""
4830 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4831 (const_int 1)
4832 (match_operand:SI 1 "gpc_reg_operand" "r"))
4833 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4834 (const_int 31)))]
4835 "TARGET_POWER"
4836 "rrib %0,%1,%2")
4837
4838 (define_insn ""
4839 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4840 (const_int 1)
4841 (match_operand:SI 1 "gpc_reg_operand" "r"))
4842 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4843 (const_int 1)
4844 (const_int 0)))]
4845 "TARGET_POWER"
4846 "rrib %0,%1,%2")
4847
4848 (define_expand "ashrsi3"
4849 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4850 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4851 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4852 ""
4853 "
4854 {
4855 if (TARGET_POWER)
4856 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4857 else
4858 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4859 DONE;
4860 }")
4861
4862 (define_insn "ashrsi3_power"
4863 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4864 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4865 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4866 (clobber (match_scratch:SI 3 "=q,X"))]
4867 "TARGET_POWER"
4868 "@
4869 srea %0,%1,%2
4870 {srai|srawi} %0,%1,%h2"
4871 [(set_attr "type" "shift")])
4872
4873 (define_insn "ashrsi3_no_power"
4874 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4875 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4876 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4877 "! TARGET_POWER"
4878 "@
4879 {sra|sraw} %0,%1,%2
4880 {srai|srawi} %0,%1,%h2"
4881 [(set_attr "type" "var_shift_rotate,shift")])
4882
4883 (define_insn ""
4884 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4885 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4886 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4887 (const_int 0)))
4888 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4889 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4890 "TARGET_POWER"
4891 "@
4892 srea. %3,%1,%2
4893 {srai.|srawi.} %3,%1,%h2
4894 #
4895 #"
4896 [(set_attr "type" "delayed_compare")
4897 (set_attr "length" "4,4,8,8")])
4898
4899 (define_split
4900 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4901 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4902 (match_operand:SI 2 "reg_or_cint_operand" ""))
4903 (const_int 0)))
4904 (clobber (match_scratch:SI 3 ""))
4905 (clobber (match_scratch:SI 4 ""))]
4906 "TARGET_POWER && reload_completed"
4907 [(parallel [(set (match_dup 3)
4908 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4909 (clobber (match_dup 4))])
4910 (set (match_dup 0)
4911 (compare:CC (match_dup 3)
4912 (const_int 0)))]
4913 "")
4914
4915 (define_insn ""
4916 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4917 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4918 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4919 (const_int 0)))
4920 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4921 "! TARGET_POWER"
4922 "@
4923 {sra.|sraw.} %3,%1,%2
4924 {srai.|srawi.} %3,%1,%h2
4925 #
4926 #"
4927 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4928 (set_attr "length" "4,4,8,8")])
4929
4930 (define_split
4931 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4932 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4933 (match_operand:SI 2 "reg_or_cint_operand" ""))
4934 (const_int 0)))
4935 (clobber (match_scratch:SI 3 ""))]
4936 "! TARGET_POWER && reload_completed"
4937 [(set (match_dup 3)
4938 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4939 (set (match_dup 0)
4940 (compare:CC (match_dup 3)
4941 (const_int 0)))]
4942 "")
4943
4944 (define_insn ""
4945 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4946 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4947 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4948 (const_int 0)))
4949 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4950 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4951 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4952 "TARGET_POWER"
4953 "@
4954 srea. %0,%1,%2
4955 {srai.|srawi.} %0,%1,%h2
4956 #
4957 #"
4958 [(set_attr "type" "delayed_compare")
4959 (set_attr "length" "4,4,8,8")])
4960
4961 (define_split
4962 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4963 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4964 (match_operand:SI 2 "reg_or_cint_operand" ""))
4965 (const_int 0)))
4966 (set (match_operand:SI 0 "gpc_reg_operand" "")
4967 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4968 (clobber (match_scratch:SI 4 ""))]
4969 "TARGET_POWER && reload_completed"
4970 [(parallel [(set (match_dup 0)
4971 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4972 (clobber (match_dup 4))])
4973 (set (match_dup 3)
4974 (compare:CC (match_dup 0)
4975 (const_int 0)))]
4976 "")
4977
4978 (define_insn ""
4979 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4980 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4981 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4982 (const_int 0)))
4983 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4984 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4985 "! TARGET_POWER"
4986 "@
4987 {sra.|sraw.} %0,%1,%2
4988 {srai.|srawi.} %0,%1,%h2
4989 #
4990 #"
4991 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4992 (set_attr "length" "4,4,8,8")])
4993 \f
4994 (define_split
4995 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4996 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4997 (match_operand:SI 2 "reg_or_cint_operand" ""))
4998 (const_int 0)))
4999 (set (match_operand:SI 0 "gpc_reg_operand" "")
5000 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5001 "! TARGET_POWER && reload_completed"
5002 [(set (match_dup 0)
5003 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5004 (set (match_dup 3)
5005 (compare:CC (match_dup 0)
5006 (const_int 0)))]
5007 "")
5008
5009 ;; Floating-point insns, excluding normal data motion.
5010 ;;
5011 ;; PowerPC has a full set of single-precision floating point instructions.
5012 ;;
5013 ;; For the POWER architecture, we pretend that we have both SFmode and
5014 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
5015 ;; The only conversions we will do will be when storing to memory. In that
5016 ;; case, we will use the "frsp" instruction before storing.
5017 ;;
5018 ;; Note that when we store into a single-precision memory location, we need to
5019 ;; use the frsp insn first. If the register being stored isn't dead, we
5020 ;; need a scratch register for the frsp. But this is difficult when the store
5021 ;; is done by reload. It is not incorrect to do the frsp on the register in
5022 ;; this case, we just lose precision that we would have otherwise gotten but
5023 ;; is not guaranteed. Perhaps this should be tightened up at some point.
5024
5025 (define_expand "extendsfdf2"
5026 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5027 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5028 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5029 "")
5030
5031 (define_insn_and_split "*extendsfdf2_fpr"
5032 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
5033 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
5034 "TARGET_HARD_FLOAT && TARGET_FPRS"
5035 "@
5036 #
5037 fmr %0,%1
5038 lfs%U1%X1 %0,%1"
5039 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5040 [(const_int 0)]
5041 {
5042 emit_note (NOTE_INSN_DELETED);
5043 DONE;
5044 }
5045 [(set_attr "type" "fp,fp,fpload")])
5046
5047 (define_expand "truncdfsf2"
5048 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5049 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5050 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5051 "")
5052
5053 (define_insn "*truncdfsf2_fpr"
5054 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5055 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5056 "TARGET_HARD_FLOAT && TARGET_FPRS"
5057 "frsp %0,%1"
5058 [(set_attr "type" "fp")])
5059
5060 (define_insn "aux_truncdfsf2"
5061 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5062 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
5063 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5064 "frsp %0,%1"
5065 [(set_attr "type" "fp")])
5066
5067 (define_expand "negsf2"
5068 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5069 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5070 "TARGET_HARD_FLOAT"
5071 "")
5072
5073 (define_insn "*negsf2"
5074 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5075 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5076 "TARGET_HARD_FLOAT && TARGET_FPRS"
5077 "fneg %0,%1"
5078 [(set_attr "type" "fp")])
5079
5080 (define_expand "abssf2"
5081 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5082 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5083 "TARGET_HARD_FLOAT"
5084 "")
5085
5086 (define_insn "*abssf2"
5087 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5088 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5089 "TARGET_HARD_FLOAT && TARGET_FPRS"
5090 "fabs %0,%1"
5091 [(set_attr "type" "fp")])
5092
5093 (define_insn ""
5094 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5095 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
5096 "TARGET_HARD_FLOAT && TARGET_FPRS"
5097 "fnabs %0,%1"
5098 [(set_attr "type" "fp")])
5099
5100 (define_expand "addsf3"
5101 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5102 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5103 (match_operand:SF 2 "gpc_reg_operand" "")))]
5104 "TARGET_HARD_FLOAT"
5105 "")
5106
5107 (define_insn ""
5108 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5109 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5110 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5111 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5112 "fadds %0,%1,%2"
5113 [(set_attr "type" "fp")])
5114
5115 (define_insn ""
5116 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5117 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5118 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5119 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5120 "{fa|fadd} %0,%1,%2"
5121 [(set_attr "type" "fp")])
5122
5123 (define_expand "subsf3"
5124 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5125 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5126 (match_operand:SF 2 "gpc_reg_operand" "")))]
5127 "TARGET_HARD_FLOAT"
5128 "")
5129
5130 (define_insn ""
5131 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5132 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5133 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5134 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5135 "fsubs %0,%1,%2"
5136 [(set_attr "type" "fp")])
5137
5138 (define_insn ""
5139 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5140 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5141 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5142 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5143 "{fs|fsub} %0,%1,%2"
5144 [(set_attr "type" "fp")])
5145
5146 (define_expand "mulsf3"
5147 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5148 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5149 (match_operand:SF 2 "gpc_reg_operand" "")))]
5150 "TARGET_HARD_FLOAT"
5151 "")
5152
5153 (define_insn ""
5154 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5155 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5156 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5157 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5158 "fmuls %0,%1,%2"
5159 [(set_attr "type" "fp")])
5160
5161 (define_insn ""
5162 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5163 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5164 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5165 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5166 "{fm|fmul} %0,%1,%2"
5167 [(set_attr "type" "dmul")])
5168
5169 (define_insn "fres"
5170 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5171 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5172 "TARGET_PPC_GFXOPT && flag_finite_math_only"
5173 "fres %0,%1"
5174 [(set_attr "type" "fp")])
5175
5176 (define_expand "divsf3"
5177 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5178 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5179 (match_operand:SF 2 "gpc_reg_operand" "")))]
5180 "TARGET_HARD_FLOAT"
5181 {
5182 if (swdiv && !optimize_size && TARGET_PPC_GFXOPT
5183 && flag_finite_math_only && !flag_trapping_math)
5184 {
5185 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5186 DONE;
5187 }
5188 })
5189
5190 (define_insn ""
5191 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5192 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5193 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5194 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5195 "fdivs %0,%1,%2"
5196 [(set_attr "type" "sdiv")])
5197
5198 (define_insn ""
5199 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5200 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5201 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5202 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5203 "{fd|fdiv} %0,%1,%2"
5204 [(set_attr "type" "ddiv")])
5205
5206 (define_insn ""
5207 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5208 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5209 (match_operand:SF 2 "gpc_reg_operand" "f"))
5210 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5211 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5212 "fmadds %0,%1,%2,%3"
5213 [(set_attr "type" "fp")])
5214
5215 (define_insn ""
5216 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5217 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5218 (match_operand:SF 2 "gpc_reg_operand" "f"))
5219 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5220 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5221 "{fma|fmadd} %0,%1,%2,%3"
5222 [(set_attr "type" "dmul")])
5223
5224 (define_insn ""
5225 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5226 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5227 (match_operand:SF 2 "gpc_reg_operand" "f"))
5228 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5229 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5230 "fmsubs %0,%1,%2,%3"
5231 [(set_attr "type" "fp")])
5232
5233 (define_insn ""
5234 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5235 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5236 (match_operand:SF 2 "gpc_reg_operand" "f"))
5237 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5238 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5239 "{fms|fmsub} %0,%1,%2,%3"
5240 [(set_attr "type" "dmul")])
5241
5242 (define_insn ""
5243 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5244 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5245 (match_operand:SF 2 "gpc_reg_operand" "f"))
5246 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5247 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5248 && HONOR_SIGNED_ZEROS (SFmode)"
5249 "fnmadds %0,%1,%2,%3"
5250 [(set_attr "type" "fp")])
5251
5252 (define_insn ""
5253 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5254 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5255 (match_operand:SF 2 "gpc_reg_operand" "f"))
5256 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5257 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5258 && ! HONOR_SIGNED_ZEROS (SFmode)"
5259 "fnmadds %0,%1,%2,%3"
5260 [(set_attr "type" "fp")])
5261
5262 (define_insn ""
5263 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5264 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5265 (match_operand:SF 2 "gpc_reg_operand" "f"))
5266 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5267 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5268 "{fnma|fnmadd} %0,%1,%2,%3"
5269 [(set_attr "type" "dmul")])
5270
5271 (define_insn ""
5272 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5273 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5274 (match_operand:SF 2 "gpc_reg_operand" "f"))
5275 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5276 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5277 && ! HONOR_SIGNED_ZEROS (SFmode)"
5278 "{fnma|fnmadd} %0,%1,%2,%3"
5279 [(set_attr "type" "dmul")])
5280
5281 (define_insn ""
5282 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5283 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5284 (match_operand:SF 2 "gpc_reg_operand" "f"))
5285 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5286 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5287 && HONOR_SIGNED_ZEROS (SFmode)"
5288 "fnmsubs %0,%1,%2,%3"
5289 [(set_attr "type" "fp")])
5290
5291 (define_insn ""
5292 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5293 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5294 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5295 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5296 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5297 && ! HONOR_SIGNED_ZEROS (SFmode)"
5298 "fnmsubs %0,%1,%2,%3"
5299 [(set_attr "type" "fp")])
5300
5301 (define_insn ""
5302 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5303 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5304 (match_operand:SF 2 "gpc_reg_operand" "f"))
5305 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5306 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5307 "{fnms|fnmsub} %0,%1,%2,%3"
5308 [(set_attr "type" "dmul")])
5309
5310 (define_insn ""
5311 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5312 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5313 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5314 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5315 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5316 && ! HONOR_SIGNED_ZEROS (SFmode)"
5317 "{fnms|fnmsub} %0,%1,%2,%3"
5318 [(set_attr "type" "dmul")])
5319
5320 (define_expand "sqrtsf2"
5321 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5322 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5323 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5324 "")
5325
5326 (define_insn ""
5327 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5328 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5329 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5330 "fsqrts %0,%1"
5331 [(set_attr "type" "ssqrt")])
5332
5333 (define_insn ""
5334 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5335 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5336 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
5337 "fsqrt %0,%1"
5338 [(set_attr "type" "dsqrt")])
5339
5340 (define_expand "copysignsf3"
5341 [(set (match_dup 3)
5342 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5343 (set (match_dup 4)
5344 (neg:SF (abs:SF (match_dup 1))))
5345 (set (match_operand:SF 0 "gpc_reg_operand" "")
5346 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5347 (match_dup 5))
5348 (match_dup 3)
5349 (match_dup 4)))]
5350 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5351 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
5352 {
5353 operands[3] = gen_reg_rtx (SFmode);
5354 operands[4] = gen_reg_rtx (SFmode);
5355 operands[5] = CONST0_RTX (SFmode);
5356 })
5357
5358 (define_expand "copysigndf3"
5359 [(set (match_dup 3)
5360 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5361 (set (match_dup 4)
5362 (neg:DF (abs:DF (match_dup 1))))
5363 (set (match_operand:DF 0 "gpc_reg_operand" "")
5364 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5365 (match_dup 5))
5366 (match_dup 3)
5367 (match_dup 4)))]
5368 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5369 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
5370 {
5371 operands[3] = gen_reg_rtx (DFmode);
5372 operands[4] = gen_reg_rtx (DFmode);
5373 operands[5] = CONST0_RTX (DFmode);
5374 })
5375
5376 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5377 ;; fsel instruction and some auxiliary computations. Then we just have a
5378 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5379 ;; combine.
5380 (define_expand "smaxsf3"
5381 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5382 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5383 (match_operand:SF 2 "gpc_reg_operand" ""))
5384 (match_dup 1)
5385 (match_dup 2)))]
5386 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5387 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5388
5389 (define_expand "sminsf3"
5390 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5391 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5392 (match_operand:SF 2 "gpc_reg_operand" ""))
5393 (match_dup 2)
5394 (match_dup 1)))]
5395 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5396 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5397
5398 (define_split
5399 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5400 (match_operator:SF 3 "min_max_operator"
5401 [(match_operand:SF 1 "gpc_reg_operand" "")
5402 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5403 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5404 [(const_int 0)]
5405 "
5406 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5407 operands[1], operands[2]);
5408 DONE;
5409 }")
5410
5411 (define_expand "movsicc"
5412 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5413 (if_then_else:SI (match_operand 1 "comparison_operator" "")
5414 (match_operand:SI 2 "gpc_reg_operand" "")
5415 (match_operand:SI 3 "gpc_reg_operand" "")))]
5416 "TARGET_ISEL"
5417 "
5418 {
5419 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5420 DONE;
5421 else
5422 FAIL;
5423 }")
5424
5425 ;; We use the BASE_REGS for the isel input operands because, if rA is
5426 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5427 ;; because we may switch the operands and rB may end up being rA.
5428 ;;
5429 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5430 ;; leave out the mode in operand 4 and use one pattern, but reload can
5431 ;; change the mode underneath our feet and then gets confused trying
5432 ;; to reload the value.
5433 (define_insn "isel_signed"
5434 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5435 (if_then_else:SI
5436 (match_operator 1 "comparison_operator"
5437 [(match_operand:CC 4 "cc_reg_operand" "y")
5438 (const_int 0)])
5439 (match_operand:SI 2 "gpc_reg_operand" "b")
5440 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5441 "TARGET_ISEL"
5442 "*
5443 { return output_isel (operands); }"
5444 [(set_attr "length" "4")])
5445
5446 (define_insn "isel_unsigned"
5447 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5448 (if_then_else:SI
5449 (match_operator 1 "comparison_operator"
5450 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5451 (const_int 0)])
5452 (match_operand:SI 2 "gpc_reg_operand" "b")
5453 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5454 "TARGET_ISEL"
5455 "*
5456 { return output_isel (operands); }"
5457 [(set_attr "length" "4")])
5458
5459 (define_expand "movsfcc"
5460 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5461 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5462 (match_operand:SF 2 "gpc_reg_operand" "")
5463 (match_operand:SF 3 "gpc_reg_operand" "")))]
5464 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5465 "
5466 {
5467 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5468 DONE;
5469 else
5470 FAIL;
5471 }")
5472
5473 (define_insn "*fselsfsf4"
5474 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5475 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5476 (match_operand:SF 4 "zero_fp_constant" "F"))
5477 (match_operand:SF 2 "gpc_reg_operand" "f")
5478 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5479 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5480 "fsel %0,%1,%2,%3"
5481 [(set_attr "type" "fp")])
5482
5483 (define_insn "*fseldfsf4"
5484 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5485 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5486 (match_operand:DF 4 "zero_fp_constant" "F"))
5487 (match_operand:SF 2 "gpc_reg_operand" "f")
5488 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5489 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5490 "fsel %0,%1,%2,%3"
5491 [(set_attr "type" "fp")])
5492
5493 (define_expand "negdf2"
5494 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5495 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5496 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5497 "")
5498
5499 (define_insn "*negdf2_fpr"
5500 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5501 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5502 "TARGET_HARD_FLOAT && TARGET_FPRS"
5503 "fneg %0,%1"
5504 [(set_attr "type" "fp")])
5505
5506 (define_expand "absdf2"
5507 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5508 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5509 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5510 "")
5511
5512 (define_insn "*absdf2_fpr"
5513 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5514 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5515 "TARGET_HARD_FLOAT && TARGET_FPRS"
5516 "fabs %0,%1"
5517 [(set_attr "type" "fp")])
5518
5519 (define_insn "*nabsdf2_fpr"
5520 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5521 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
5522 "TARGET_HARD_FLOAT && TARGET_FPRS"
5523 "fnabs %0,%1"
5524 [(set_attr "type" "fp")])
5525
5526 (define_expand "adddf3"
5527 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5528 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5529 (match_operand:DF 2 "gpc_reg_operand" "")))]
5530 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5531 "")
5532
5533 (define_insn "*adddf3_fpr"
5534 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5535 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5536 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5537 "TARGET_HARD_FLOAT && TARGET_FPRS"
5538 "{fa|fadd} %0,%1,%2"
5539 [(set_attr "type" "fp")])
5540
5541 (define_expand "subdf3"
5542 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5543 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5544 (match_operand:DF 2 "gpc_reg_operand" "")))]
5545 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5546 "")
5547
5548 (define_insn "*subdf3_fpr"
5549 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5550 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5551 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5552 "TARGET_HARD_FLOAT && TARGET_FPRS"
5553 "{fs|fsub} %0,%1,%2"
5554 [(set_attr "type" "fp")])
5555
5556 (define_expand "muldf3"
5557 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5558 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5559 (match_operand:DF 2 "gpc_reg_operand" "")))]
5560 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5561 "")
5562
5563 (define_insn "*muldf3_fpr"
5564 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5565 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5566 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5567 "TARGET_HARD_FLOAT && TARGET_FPRS"
5568 "{fm|fmul} %0,%1,%2"
5569 [(set_attr "type" "dmul")])
5570
5571 (define_insn "fred"
5572 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5573 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5574 "TARGET_POPCNTB && flag_finite_math_only"
5575 "fre %0,%1"
5576 [(set_attr "type" "fp")])
5577
5578 (define_expand "divdf3"
5579 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5580 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5581 (match_operand:DF 2 "gpc_reg_operand" "")))]
5582 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5583 {
5584 if (swdiv && !optimize_size && TARGET_POPCNTB
5585 && flag_finite_math_only && !flag_trapping_math)
5586 {
5587 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5588 DONE;
5589 }
5590 })
5591
5592 (define_insn "*divdf3_fpr"
5593 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5594 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5595 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5596 "TARGET_HARD_FLOAT && TARGET_FPRS"
5597 "{fd|fdiv} %0,%1,%2"
5598 [(set_attr "type" "ddiv")])
5599
5600 (define_insn ""
5601 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5602 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5603 (match_operand:DF 2 "gpc_reg_operand" "f"))
5604 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5605 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5606 "{fma|fmadd} %0,%1,%2,%3"
5607 [(set_attr "type" "dmul")])
5608
5609 (define_insn ""
5610 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5611 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5612 (match_operand:DF 2 "gpc_reg_operand" "f"))
5613 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5614 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5615 "{fms|fmsub} %0,%1,%2,%3"
5616 [(set_attr "type" "dmul")])
5617
5618 (define_insn ""
5619 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5620 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5621 (match_operand:DF 2 "gpc_reg_operand" "f"))
5622 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5623 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5624 && HONOR_SIGNED_ZEROS (DFmode)"
5625 "{fnma|fnmadd} %0,%1,%2,%3"
5626 [(set_attr "type" "dmul")])
5627
5628 (define_insn ""
5629 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5630 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5631 (match_operand:DF 2 "gpc_reg_operand" "f"))
5632 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5633 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5634 && ! HONOR_SIGNED_ZEROS (DFmode)"
5635 "{fnma|fnmadd} %0,%1,%2,%3"
5636 [(set_attr "type" "dmul")])
5637
5638 (define_insn ""
5639 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5640 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5641 (match_operand:DF 2 "gpc_reg_operand" "f"))
5642 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5643 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5644 && HONOR_SIGNED_ZEROS (DFmode)"
5645 "{fnms|fnmsub} %0,%1,%2,%3"
5646 [(set_attr "type" "dmul")])
5647
5648 (define_insn ""
5649 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5650 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5651 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5652 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5653 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5654 && ! HONOR_SIGNED_ZEROS (DFmode)"
5655 "{fnms|fnmsub} %0,%1,%2,%3"
5656 [(set_attr "type" "dmul")])
5657
5658 (define_insn "sqrtdf2"
5659 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5660 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5661 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5662 "fsqrt %0,%1"
5663 [(set_attr "type" "dsqrt")])
5664
5665 ;; The conditional move instructions allow us to perform max and min
5666 ;; operations even when
5667
5668 (define_expand "smaxdf3"
5669 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5670 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5671 (match_operand:DF 2 "gpc_reg_operand" ""))
5672 (match_dup 1)
5673 (match_dup 2)))]
5674 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5675 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5676
5677 (define_expand "smindf3"
5678 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5679 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5680 (match_operand:DF 2 "gpc_reg_operand" ""))
5681 (match_dup 2)
5682 (match_dup 1)))]
5683 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5684 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5685
5686 (define_split
5687 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5688 (match_operator:DF 3 "min_max_operator"
5689 [(match_operand:DF 1 "gpc_reg_operand" "")
5690 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5691 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5692 [(const_int 0)]
5693 "
5694 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5695 operands[1], operands[2]);
5696 DONE;
5697 }")
5698
5699 (define_expand "movdfcc"
5700 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5701 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5702 (match_operand:DF 2 "gpc_reg_operand" "")
5703 (match_operand:DF 3 "gpc_reg_operand" "")))]
5704 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5705 "
5706 {
5707 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5708 DONE;
5709 else
5710 FAIL;
5711 }")
5712
5713 (define_insn "*fseldfdf4"
5714 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5715 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5716 (match_operand:DF 4 "zero_fp_constant" "F"))
5717 (match_operand:DF 2 "gpc_reg_operand" "f")
5718 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5719 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5720 "fsel %0,%1,%2,%3"
5721 [(set_attr "type" "fp")])
5722
5723 (define_insn "*fselsfdf4"
5724 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5725 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5726 (match_operand:SF 4 "zero_fp_constant" "F"))
5727 (match_operand:DF 2 "gpc_reg_operand" "f")
5728 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5729 "TARGET_PPC_GFXOPT"
5730 "fsel %0,%1,%2,%3"
5731 [(set_attr "type" "fp")])
5732 \f
5733 ;; Conversions to and from floating-point.
5734
5735 (define_expand "fixuns_truncsfsi2"
5736 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5737 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5738 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5739 "")
5740
5741 (define_expand "fix_truncsfsi2"
5742 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5743 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5744 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5745 "")
5746
5747 ; For each of these conversions, there is a define_expand, a define_insn
5748 ; with a '#' template, and a define_split (with C code). The idea is
5749 ; to allow constant folding with the template of the define_insn,
5750 ; then to have the insns split later (between sched1 and final).
5751
5752 (define_expand "floatsidf2"
5753 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5754 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5755 (use (match_dup 2))
5756 (use (match_dup 3))
5757 (clobber (match_dup 4))
5758 (clobber (match_dup 5))
5759 (clobber (match_dup 6))])]
5760 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5761 "
5762 {
5763 if (TARGET_E500_DOUBLE)
5764 {
5765 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5766 DONE;
5767 }
5768 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS)
5769 {
5770 rtx t1 = gen_reg_rtx (DImode);
5771 emit_insn (gen_floatsidf_ppc64_mfpgpr (operands[0], operands[1], t1));
5772 DONE;
5773 }
5774 if (TARGET_POWERPC64)
5775 {
5776 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5777 rtx t1 = gen_reg_rtx (DImode);
5778 rtx t2 = gen_reg_rtx (DImode);
5779 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5780 DONE;
5781 }
5782
5783 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5784 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5785 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5786 operands[5] = gen_reg_rtx (DFmode);
5787 operands[6] = gen_reg_rtx (SImode);
5788 }")
5789
5790 (define_insn_and_split "*floatsidf2_internal"
5791 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5792 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5793 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5794 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5795 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5796 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5797 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5798 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5799 "#"
5800 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5801 [(pc)]
5802 "
5803 {
5804 rtx lowword, highword;
5805 gcc_assert (MEM_P (operands[4]));
5806 highword = adjust_address (operands[4], SImode, 0);
5807 lowword = adjust_address (operands[4], SImode, 4);
5808 if (! WORDS_BIG_ENDIAN)
5809 {
5810 rtx tmp;
5811 tmp = highword; highword = lowword; lowword = tmp;
5812 }
5813
5814 emit_insn (gen_xorsi3 (operands[6], operands[1],
5815 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5816 emit_move_insn (lowword, operands[6]);
5817 emit_move_insn (highword, operands[2]);
5818 emit_move_insn (operands[5], operands[4]);
5819 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5820 DONE;
5821 }"
5822 [(set_attr "length" "24")])
5823
5824 (define_expand "floatunssisf2"
5825 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5826 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5827 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5828 "")
5829
5830 (define_expand "floatunssidf2"
5831 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5832 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5833 (use (match_dup 2))
5834 (use (match_dup 3))
5835 (clobber (match_dup 4))
5836 (clobber (match_dup 5))])]
5837 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5838 "
5839 {
5840 if (TARGET_E500_DOUBLE)
5841 {
5842 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5843 DONE;
5844 }
5845 if (TARGET_POWERPC64)
5846 {
5847 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5848 rtx t1 = gen_reg_rtx (DImode);
5849 rtx t2 = gen_reg_rtx (DImode);
5850 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5851 t1, t2));
5852 DONE;
5853 }
5854
5855 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5856 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5857 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5858 operands[5] = gen_reg_rtx (DFmode);
5859 }")
5860
5861 (define_insn_and_split "*floatunssidf2_internal"
5862 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5863 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5864 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5865 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5866 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5867 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5868 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5869 "#"
5870 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5871 [(pc)]
5872 "
5873 {
5874 rtx lowword, highword;
5875 gcc_assert (MEM_P (operands[4]));
5876 highword = adjust_address (operands[4], SImode, 0);
5877 lowword = adjust_address (operands[4], SImode, 4);
5878 if (! WORDS_BIG_ENDIAN)
5879 {
5880 rtx tmp;
5881 tmp = highword; highword = lowword; lowword = tmp;
5882 }
5883
5884 emit_move_insn (lowword, operands[1]);
5885 emit_move_insn (highword, operands[2]);
5886 emit_move_insn (operands[5], operands[4]);
5887 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5888 DONE;
5889 }"
5890 [(set_attr "length" "20")])
5891
5892 (define_expand "fix_truncdfsi2"
5893 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
5894 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5895 (clobber (match_dup 2))
5896 (clobber (match_dup 3))])]
5897 "(TARGET_POWER2 || TARGET_POWERPC)
5898 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5899 "
5900 {
5901 if (TARGET_E500_DOUBLE)
5902 {
5903 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5904 DONE;
5905 }
5906 operands[2] = gen_reg_rtx (DImode);
5907 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
5908 && gpc_reg_operand(operands[0], GET_MODE (operands[0])))
5909 {
5910 operands[3] = gen_reg_rtx (DImode);
5911 emit_insn (gen_fix_truncdfsi2_mfpgpr (operands[0], operands[1],
5912 operands[2], operands[3]));
5913 DONE;
5914 }
5915 if (TARGET_PPC_GFXOPT)
5916 {
5917 rtx orig_dest = operands[0];
5918 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
5919 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5920 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5921 operands[2]));
5922 if (operands[0] != orig_dest)
5923 emit_move_insn (orig_dest, operands[0]);
5924 DONE;
5925 }
5926 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5927 }")
5928
5929 (define_insn_and_split "*fix_truncdfsi2_internal"
5930 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5931 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5932 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5933 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5934 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5935 "#"
5936 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[3]))"
5937 [(pc)]
5938 "
5939 {
5940 rtx lowword;
5941 gcc_assert (MEM_P (operands[3]));
5942 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5943
5944 emit_insn (gen_fctiwz (operands[2], operands[1]));
5945 emit_move_insn (operands[3], operands[2]);
5946 emit_move_insn (operands[0], lowword);
5947 DONE;
5948 }"
5949 [(set_attr "length" "16")])
5950
5951 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
5952 [(set (match_operand:SI 0 "memory_operand" "=Z")
5953 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5954 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
5955 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
5956 && TARGET_PPC_GFXOPT"
5957 "#"
5958 "&& 1"
5959 [(pc)]
5960 "
5961 {
5962 emit_insn (gen_fctiwz (operands[2], operands[1]));
5963 emit_insn (gen_stfiwx (operands[0], operands[2]));
5964 DONE;
5965 }"
5966 [(set_attr "length" "16")])
5967
5968 (define_insn_and_split "fix_truncdfsi2_mfpgpr"
5969 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5970 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5971 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5972 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
5973 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
5974 "#"
5975 "&& 1"
5976 [(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
5977 (set (match_dup 3) (match_dup 2))
5978 (set (match_dup 0) (subreg:SI (match_dup 3) 4))]
5979 ""
5980 [(set_attr "length" "12")])
5981
5982 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5983 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5984 ; because the first makes it clear that operand 0 is not live
5985 ; before the instruction.
5986 (define_insn "fctiwz"
5987 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
5988 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5989 UNSPEC_FCTIWZ))]
5990 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5991 "{fcirz|fctiwz} %0,%1"
5992 [(set_attr "type" "fp")])
5993
5994 (define_insn "btruncdf2"
5995 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5996 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
5997 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5998 "friz %0,%1"
5999 [(set_attr "type" "fp")])
6000
6001 (define_insn "btruncsf2"
6002 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6003 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6004 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6005 "friz %0,%1"
6006 [(set_attr "type" "fp")])
6007
6008 (define_insn "ceildf2"
6009 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6010 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6011 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6012 "frip %0,%1"
6013 [(set_attr "type" "fp")])
6014
6015 (define_insn "ceilsf2"
6016 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6017 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6018 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6019 "frip %0,%1"
6020 [(set_attr "type" "fp")])
6021
6022 (define_insn "floordf2"
6023 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6024 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6025 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6026 "frim %0,%1"
6027 [(set_attr "type" "fp")])
6028
6029 (define_insn "floorsf2"
6030 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6031 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6032 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6033 "frim %0,%1"
6034 [(set_attr "type" "fp")])
6035
6036 (define_insn "rounddf2"
6037 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6038 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6039 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6040 "frin %0,%1"
6041 [(set_attr "type" "fp")])
6042
6043 (define_insn "roundsf2"
6044 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6045 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6046 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6047 "frin %0,%1"
6048 [(set_attr "type" "fp")])
6049
6050 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6051 (define_insn "stfiwx"
6052 [(set (match_operand:SI 0 "memory_operand" "=Z")
6053 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
6054 UNSPEC_STFIWX))]
6055 "TARGET_PPC_GFXOPT"
6056 "stfiwx %1,%y0"
6057 [(set_attr "type" "fpstore")])
6058
6059 (define_expand "floatsisf2"
6060 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6061 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6062 "TARGET_HARD_FLOAT && !TARGET_FPRS"
6063 "")
6064
6065 (define_insn "floatdidf2"
6066 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6067 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
6068 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6069 "fcfid %0,%1"
6070 [(set_attr "type" "fp")])
6071
6072 (define_insn_and_split "floatsidf_ppc64_mfpgpr"
6073 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6074 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6075 (clobber (match_operand:DI 2 "gpc_reg_operand" "=r"))]
6076 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
6077 "#"
6078 "&& 1"
6079 [(set (match_dup 2) (sign_extend:DI (match_dup 1)))
6080 (set (match_dup 0) (float:DF (match_dup 2)))]
6081 "")
6082
6083 (define_insn_and_split "floatsidf_ppc64"
6084 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6085 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6086 (clobber (match_operand:DI 2 "memory_operand" "=o"))
6087 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
6088 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
6089 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
6090 "#"
6091 "&& 1"
6092 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
6093 (set (match_dup 2) (match_dup 3))
6094 (set (match_dup 4) (match_dup 2))
6095 (set (match_dup 0) (float:DF (match_dup 4)))]
6096 "")
6097
6098 (define_insn_and_split "floatunssidf_ppc64"
6099 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6100 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6101 (clobber (match_operand:DI 2 "memory_operand" "=o"))
6102 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
6103 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
6104 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6105 "#"
6106 "&& 1"
6107 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
6108 (set (match_dup 2) (match_dup 3))
6109 (set (match_dup 4) (match_dup 2))
6110 (set (match_dup 0) (float:DF (match_dup 4)))]
6111 "")
6112
6113 (define_insn "fix_truncdfdi2"
6114 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
6115 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
6116 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6117 "fctidz %0,%1"
6118 [(set_attr "type" "fp")])
6119
6120 (define_expand "floatdisf2"
6121 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6122 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6123 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6124 "
6125 {
6126 rtx val = operands[1];
6127 if (!flag_unsafe_math_optimizations)
6128 {
6129 rtx label = gen_label_rtx ();
6130 val = gen_reg_rtx (DImode);
6131 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6132 emit_label (label);
6133 }
6134 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6135 DONE;
6136 }")
6137
6138 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6139 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6140 ;; from double rounding.
6141 (define_insn_and_split "floatdisf2_internal1"
6142 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6143 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
6144 (clobber (match_scratch:DF 2 "=f"))]
6145 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6146 "#"
6147 "&& reload_completed"
6148 [(set (match_dup 2)
6149 (float:DF (match_dup 1)))
6150 (set (match_dup 0)
6151 (float_truncate:SF (match_dup 2)))]
6152 "")
6153
6154 ;; Twiddles bits to avoid double rounding.
6155 ;; Bits that might be truncated when converting to DFmode are replaced
6156 ;; by a bit that won't be lost at that stage, but is below the SFmode
6157 ;; rounding position.
6158 (define_expand "floatdisf2_internal2"
6159 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6160 (const_int 53)))
6161 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6162 (const_int 2047)))
6163 (clobber (scratch:CC))])
6164 (set (match_dup 3) (plus:DI (match_dup 3)
6165 (const_int 1)))
6166 (set (match_dup 0) (plus:DI (match_dup 0)
6167 (const_int 2047)))
6168 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6169 (const_int 2)))
6170 (set (match_dup 0) (ior:DI (match_dup 0)
6171 (match_dup 1)))
6172 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6173 (const_int -2048)))
6174 (clobber (scratch:CC))])
6175 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6176 (label_ref (match_operand:DI 2 "" ""))
6177 (pc)))
6178 (set (match_dup 0) (match_dup 1))]
6179 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6180 "
6181 {
6182 operands[3] = gen_reg_rtx (DImode);
6183 operands[4] = gen_reg_rtx (CCUNSmode);
6184 }")
6185 \f
6186 ;; Define the DImode operations that can be done in a small number
6187 ;; of instructions. The & constraints are to prevent the register
6188 ;; allocator from allocating registers that overlap with the inputs
6189 ;; (for example, having an input in 7,8 and an output in 6,7). We
6190 ;; also allow for the output being the same as one of the inputs.
6191
6192 (define_insn "*adddi3_noppc64"
6193 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6194 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6195 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6196 "! TARGET_POWERPC64"
6197 "*
6198 {
6199 if (WORDS_BIG_ENDIAN)
6200 return (GET_CODE (operands[2])) != CONST_INT
6201 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6202 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6203 else
6204 return (GET_CODE (operands[2])) != CONST_INT
6205 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6206 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6207 }"
6208 [(set_attr "type" "two")
6209 (set_attr "length" "8")])
6210
6211 (define_insn "*subdi3_noppc64"
6212 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6213 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6214 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6215 "! TARGET_POWERPC64"
6216 "*
6217 {
6218 if (WORDS_BIG_ENDIAN)
6219 return (GET_CODE (operands[1]) != CONST_INT)
6220 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6221 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6222 else
6223 return (GET_CODE (operands[1]) != CONST_INT)
6224 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6225 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
6226 }"
6227 [(set_attr "type" "two")
6228 (set_attr "length" "8")])
6229
6230 (define_insn "*negdi2_noppc64"
6231 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6232 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6233 "! TARGET_POWERPC64"
6234 "*
6235 {
6236 return (WORDS_BIG_ENDIAN)
6237 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6238 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6239 }"
6240 [(set_attr "type" "two")
6241 (set_attr "length" "8")])
6242
6243 (define_expand "mulsidi3"
6244 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6245 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6246 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6247 "! TARGET_POWERPC64"
6248 "
6249 {
6250 if (! TARGET_POWER && ! TARGET_POWERPC)
6251 {
6252 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6253 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6254 emit_insn (gen_mull_call ());
6255 if (WORDS_BIG_ENDIAN)
6256 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
6257 else
6258 {
6259 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
6260 gen_rtx_REG (SImode, 3));
6261 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
6262 gen_rtx_REG (SImode, 4));
6263 }
6264 DONE;
6265 }
6266 else if (TARGET_POWER)
6267 {
6268 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6269 DONE;
6270 }
6271 }")
6272
6273 (define_insn "mulsidi3_mq"
6274 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6275 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6276 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6277 (clobber (match_scratch:SI 3 "=q"))]
6278 "TARGET_POWER"
6279 "mul %0,%1,%2\;mfmq %L0"
6280 [(set_attr "type" "imul")
6281 (set_attr "length" "8")])
6282
6283 (define_insn "*mulsidi3_no_mq"
6284 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6285 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6286 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6287 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6288 "*
6289 {
6290 return (WORDS_BIG_ENDIAN)
6291 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6292 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6293 }"
6294 [(set_attr "type" "imul")
6295 (set_attr "length" "8")])
6296
6297 (define_split
6298 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6299 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6300 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6301 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6302 [(set (match_dup 3)
6303 (truncate:SI
6304 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6305 (sign_extend:DI (match_dup 2)))
6306 (const_int 32))))
6307 (set (match_dup 4)
6308 (mult:SI (match_dup 1)
6309 (match_dup 2)))]
6310 "
6311 {
6312 int endian = (WORDS_BIG_ENDIAN == 0);
6313 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6314 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6315 }")
6316
6317 (define_expand "umulsidi3"
6318 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6319 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6320 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6321 "TARGET_POWERPC && ! TARGET_POWERPC64"
6322 "
6323 {
6324 if (TARGET_POWER)
6325 {
6326 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6327 DONE;
6328 }
6329 }")
6330
6331 (define_insn "umulsidi3_mq"
6332 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6333 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6334 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6335 (clobber (match_scratch:SI 3 "=q"))]
6336 "TARGET_POWERPC && TARGET_POWER"
6337 "*
6338 {
6339 return (WORDS_BIG_ENDIAN)
6340 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6341 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6342 }"
6343 [(set_attr "type" "imul")
6344 (set_attr "length" "8")])
6345
6346 (define_insn "*umulsidi3_no_mq"
6347 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6348 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6349 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6350 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6351 "*
6352 {
6353 return (WORDS_BIG_ENDIAN)
6354 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6355 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6356 }"
6357 [(set_attr "type" "imul")
6358 (set_attr "length" "8")])
6359
6360 (define_split
6361 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6362 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6363 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6364 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6365 [(set (match_dup 3)
6366 (truncate:SI
6367 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6368 (zero_extend:DI (match_dup 2)))
6369 (const_int 32))))
6370 (set (match_dup 4)
6371 (mult:SI (match_dup 1)
6372 (match_dup 2)))]
6373 "
6374 {
6375 int endian = (WORDS_BIG_ENDIAN == 0);
6376 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6377 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6378 }")
6379
6380 (define_expand "smulsi3_highpart"
6381 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6382 (truncate:SI
6383 (lshiftrt:DI (mult:DI (sign_extend:DI
6384 (match_operand:SI 1 "gpc_reg_operand" ""))
6385 (sign_extend:DI
6386 (match_operand:SI 2 "gpc_reg_operand" "")))
6387 (const_int 32))))]
6388 ""
6389 "
6390 {
6391 if (! TARGET_POWER && ! TARGET_POWERPC)
6392 {
6393 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6394 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6395 emit_insn (gen_mulh_call ());
6396 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
6397 DONE;
6398 }
6399 else if (TARGET_POWER)
6400 {
6401 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6402 DONE;
6403 }
6404 }")
6405
6406 (define_insn "smulsi3_highpart_mq"
6407 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6408 (truncate:SI
6409 (lshiftrt:DI (mult:DI (sign_extend:DI
6410 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6411 (sign_extend:DI
6412 (match_operand:SI 2 "gpc_reg_operand" "r")))
6413 (const_int 32))))
6414 (clobber (match_scratch:SI 3 "=q"))]
6415 "TARGET_POWER"
6416 "mul %0,%1,%2"
6417 [(set_attr "type" "imul")])
6418
6419 (define_insn "*smulsi3_highpart_no_mq"
6420 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6421 (truncate:SI
6422 (lshiftrt:DI (mult:DI (sign_extend:DI
6423 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6424 (sign_extend:DI
6425 (match_operand:SI 2 "gpc_reg_operand" "r")))
6426 (const_int 32))))]
6427 "TARGET_POWERPC && ! TARGET_POWER"
6428 "mulhw %0,%1,%2"
6429 [(set_attr "type" "imul")])
6430
6431 (define_expand "umulsi3_highpart"
6432 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6433 (truncate:SI
6434 (lshiftrt:DI (mult:DI (zero_extend:DI
6435 (match_operand:SI 1 "gpc_reg_operand" ""))
6436 (zero_extend:DI
6437 (match_operand:SI 2 "gpc_reg_operand" "")))
6438 (const_int 32))))]
6439 "TARGET_POWERPC"
6440 "
6441 {
6442 if (TARGET_POWER)
6443 {
6444 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6445 DONE;
6446 }
6447 }")
6448
6449 (define_insn "umulsi3_highpart_mq"
6450 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6451 (truncate:SI
6452 (lshiftrt:DI (mult:DI (zero_extend:DI
6453 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6454 (zero_extend:DI
6455 (match_operand:SI 2 "gpc_reg_operand" "r")))
6456 (const_int 32))))
6457 (clobber (match_scratch:SI 3 "=q"))]
6458 "TARGET_POWERPC && TARGET_POWER"
6459 "mulhwu %0,%1,%2"
6460 [(set_attr "type" "imul")])
6461
6462 (define_insn "*umulsi3_highpart_no_mq"
6463 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6464 (truncate:SI
6465 (lshiftrt:DI (mult:DI (zero_extend:DI
6466 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6467 (zero_extend:DI
6468 (match_operand:SI 2 "gpc_reg_operand" "r")))
6469 (const_int 32))))]
6470 "TARGET_POWERPC && ! TARGET_POWER"
6471 "mulhwu %0,%1,%2"
6472 [(set_attr "type" "imul")])
6473
6474 ;; If operands 0 and 2 are in the same register, we have a problem. But
6475 ;; operands 0 and 1 (the usual case) can be in the same register. That's
6476 ;; why we have the strange constraints below.
6477 (define_insn "ashldi3_power"
6478 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6479 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6480 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6481 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6482 "TARGET_POWER"
6483 "@
6484 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
6485 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6486 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6487 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
6488 [(set_attr "length" "8")])
6489
6490 (define_insn "lshrdi3_power"
6491 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6492 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6493 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6494 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6495 "TARGET_POWER"
6496 "@
6497 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
6498 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6499 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6500 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
6501 [(set_attr "length" "8")])
6502
6503 ;; Shift by a variable amount is too complex to be worth open-coding. We
6504 ;; just handle shifts by constants.
6505 (define_insn "ashrdi3_power"
6506 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6507 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6508 (match_operand:SI 2 "const_int_operand" "M,i")))
6509 (clobber (match_scratch:SI 3 "=X,q"))]
6510 "TARGET_POWER"
6511 "@
6512 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6513 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
6514 [(set_attr "type" "shift")
6515 (set_attr "length" "8")])
6516
6517 (define_insn "ashrdi3_no_power"
6518 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6519 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6520 (match_operand:SI 2 "const_int_operand" "M,i")))]
6521 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
6522 "@
6523 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6524 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
6525 [(set_attr "type" "two,three")
6526 (set_attr "length" "8,12")])
6527
6528 (define_insn "*ashrdisi3_noppc64"
6529 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6530 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6531 (const_int 32)) 4))]
6532 "TARGET_32BIT && !TARGET_POWERPC64"
6533 "*
6534 {
6535 if (REGNO (operands[0]) == REGNO (operands[1]))
6536 return \"\";
6537 else
6538 return \"mr %0,%1\";
6539 }"
6540 [(set_attr "length" "4")])
6541
6542 \f
6543 ;; PowerPC64 DImode operations.
6544
6545 (define_insn_and_split "absdi2"
6546 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6547 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6548 (clobber (match_scratch:DI 2 "=&r,&r"))]
6549 "TARGET_POWERPC64"
6550 "#"
6551 "&& reload_completed"
6552 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6553 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6554 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6555 "")
6556
6557 (define_insn_and_split "*nabsdi2"
6558 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6559 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6560 (clobber (match_scratch:DI 2 "=&r,&r"))]
6561 "TARGET_POWERPC64"
6562 "#"
6563 "&& reload_completed"
6564 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6565 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6566 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
6567 "")
6568
6569 (define_insn "muldi3"
6570 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6571 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6572 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6573 "TARGET_POWERPC64"
6574 "@
6575 mulld %0,%1,%2
6576 mulli %0,%1,%2"
6577 [(set (attr "type")
6578 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6579 (const_string "imul3")
6580 (match_operand:SI 2 "short_cint_operand" "")
6581 (const_string "imul2")]
6582 (const_string "lmul")))])
6583
6584 (define_insn "*muldi3_internal1"
6585 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6586 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6587 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6588 (const_int 0)))
6589 (clobber (match_scratch:DI 3 "=r,r"))]
6590 "TARGET_POWERPC64"
6591 "@
6592 mulld. %3,%1,%2
6593 #"
6594 [(set_attr "type" "lmul_compare")
6595 (set_attr "length" "4,8")])
6596
6597 (define_split
6598 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6599 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6600 (match_operand:DI 2 "gpc_reg_operand" ""))
6601 (const_int 0)))
6602 (clobber (match_scratch:DI 3 ""))]
6603 "TARGET_POWERPC64 && reload_completed"
6604 [(set (match_dup 3)
6605 (mult:DI (match_dup 1) (match_dup 2)))
6606 (set (match_dup 0)
6607 (compare:CC (match_dup 3)
6608 (const_int 0)))]
6609 "")
6610
6611 (define_insn "*muldi3_internal2"
6612 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6613 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6614 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6615 (const_int 0)))
6616 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6617 (mult:DI (match_dup 1) (match_dup 2)))]
6618 "TARGET_POWERPC64"
6619 "@
6620 mulld. %0,%1,%2
6621 #"
6622 [(set_attr "type" "lmul_compare")
6623 (set_attr "length" "4,8")])
6624
6625 (define_split
6626 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6627 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6628 (match_operand:DI 2 "gpc_reg_operand" ""))
6629 (const_int 0)))
6630 (set (match_operand:DI 0 "gpc_reg_operand" "")
6631 (mult:DI (match_dup 1) (match_dup 2)))]
6632 "TARGET_POWERPC64 && reload_completed"
6633 [(set (match_dup 0)
6634 (mult:DI (match_dup 1) (match_dup 2)))
6635 (set (match_dup 3)
6636 (compare:CC (match_dup 0)
6637 (const_int 0)))]
6638 "")
6639
6640 (define_insn "smuldi3_highpart"
6641 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6642 (truncate:DI
6643 (lshiftrt:TI (mult:TI (sign_extend:TI
6644 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6645 (sign_extend:TI
6646 (match_operand:DI 2 "gpc_reg_operand" "r")))
6647 (const_int 64))))]
6648 "TARGET_POWERPC64"
6649 "mulhd %0,%1,%2"
6650 [(set_attr "type" "lmul")])
6651
6652 (define_insn "umuldi3_highpart"
6653 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6654 (truncate:DI
6655 (lshiftrt:TI (mult:TI (zero_extend:TI
6656 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6657 (zero_extend:TI
6658 (match_operand:DI 2 "gpc_reg_operand" "r")))
6659 (const_int 64))))]
6660 "TARGET_POWERPC64"
6661 "mulhdu %0,%1,%2"
6662 [(set_attr "type" "lmul")])
6663
6664 (define_insn "rotldi3"
6665 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6666 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6667 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
6668 "TARGET_POWERPC64"
6669 "@
6670 rldcl %0,%1,%2,0
6671 rldicl %0,%1,%H2,0"
6672 [(set_attr "type" "var_shift_rotate,integer")])
6673
6674 (define_insn "*rotldi3_internal2"
6675 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6676 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6677 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6678 (const_int 0)))
6679 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6680 "TARGET_64BIT"
6681 "@
6682 rldcl. %3,%1,%2,0
6683 rldicl. %3,%1,%H2,0
6684 #
6685 #"
6686 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6687 (set_attr "length" "4,4,8,8")])
6688
6689 (define_split
6690 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6691 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6692 (match_operand:DI 2 "reg_or_cint_operand" ""))
6693 (const_int 0)))
6694 (clobber (match_scratch:DI 3 ""))]
6695 "TARGET_POWERPC64 && reload_completed"
6696 [(set (match_dup 3)
6697 (rotate:DI (match_dup 1) (match_dup 2)))
6698 (set (match_dup 0)
6699 (compare:CC (match_dup 3)
6700 (const_int 0)))]
6701 "")
6702
6703 (define_insn "*rotldi3_internal3"
6704 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6705 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6706 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6707 (const_int 0)))
6708 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6709 (rotate:DI (match_dup 1) (match_dup 2)))]
6710 "TARGET_64BIT"
6711 "@
6712 rldcl. %0,%1,%2,0
6713 rldicl. %0,%1,%H2,0
6714 #
6715 #"
6716 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6717 (set_attr "length" "4,4,8,8")])
6718
6719 (define_split
6720 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6721 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6722 (match_operand:DI 2 "reg_or_cint_operand" ""))
6723 (const_int 0)))
6724 (set (match_operand:DI 0 "gpc_reg_operand" "")
6725 (rotate:DI (match_dup 1) (match_dup 2)))]
6726 "TARGET_POWERPC64 && reload_completed"
6727 [(set (match_dup 0)
6728 (rotate:DI (match_dup 1) (match_dup 2)))
6729 (set (match_dup 3)
6730 (compare:CC (match_dup 0)
6731 (const_int 0)))]
6732 "")
6733
6734 (define_insn "*rotldi3_internal4"
6735 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6736 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6737 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6738 (match_operand:DI 3 "mask64_operand" "n,n")))]
6739 "TARGET_POWERPC64"
6740 "@
6741 rldc%B3 %0,%1,%2,%S3
6742 rldic%B3 %0,%1,%H2,%S3"
6743 [(set_attr "type" "var_shift_rotate,integer")])
6744
6745 (define_insn "*rotldi3_internal5"
6746 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6747 (compare:CC (and:DI
6748 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6749 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6750 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6751 (const_int 0)))
6752 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
6753 "TARGET_64BIT"
6754 "@
6755 rldc%B3. %4,%1,%2,%S3
6756 rldic%B3. %4,%1,%H2,%S3
6757 #
6758 #"
6759 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6760 (set_attr "length" "4,4,8,8")])
6761
6762 (define_split
6763 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6764 (compare:CC (and:DI
6765 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6766 (match_operand:DI 2 "reg_or_cint_operand" ""))
6767 (match_operand:DI 3 "mask64_operand" ""))
6768 (const_int 0)))
6769 (clobber (match_scratch:DI 4 ""))]
6770 "TARGET_POWERPC64 && reload_completed"
6771 [(set (match_dup 4)
6772 (and:DI (rotate:DI (match_dup 1)
6773 (match_dup 2))
6774 (match_dup 3)))
6775 (set (match_dup 0)
6776 (compare:CC (match_dup 4)
6777 (const_int 0)))]
6778 "")
6779
6780 (define_insn "*rotldi3_internal6"
6781 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
6782 (compare:CC (and:DI
6783 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6784 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6785 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6786 (const_int 0)))
6787 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6788 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6789 "TARGET_64BIT"
6790 "@
6791 rldc%B3. %0,%1,%2,%S3
6792 rldic%B3. %0,%1,%H2,%S3
6793 #
6794 #"
6795 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6796 (set_attr "length" "4,4,8,8")])
6797
6798 (define_split
6799 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6800 (compare:CC (and:DI
6801 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6802 (match_operand:DI 2 "reg_or_cint_operand" ""))
6803 (match_operand:DI 3 "mask64_operand" ""))
6804 (const_int 0)))
6805 (set (match_operand:DI 0 "gpc_reg_operand" "")
6806 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6807 "TARGET_POWERPC64 && reload_completed"
6808 [(set (match_dup 0)
6809 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6810 (set (match_dup 4)
6811 (compare:CC (match_dup 0)
6812 (const_int 0)))]
6813 "")
6814
6815 (define_insn "*rotldi3_internal7"
6816 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6817 (zero_extend:DI
6818 (subreg:QI
6819 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6820 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6821 "TARGET_POWERPC64"
6822 "@
6823 rldcl %0,%1,%2,56
6824 rldicl %0,%1,%H2,56"
6825 [(set_attr "type" "var_shift_rotate,integer")])
6826
6827 (define_insn "*rotldi3_internal8"
6828 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6829 (compare:CC (zero_extend:DI
6830 (subreg:QI
6831 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6832 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6833 (const_int 0)))
6834 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6835 "TARGET_64BIT"
6836 "@
6837 rldcl. %3,%1,%2,56
6838 rldicl. %3,%1,%H2,56
6839 #
6840 #"
6841 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6842 (set_attr "length" "4,4,8,8")])
6843
6844 (define_split
6845 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6846 (compare:CC (zero_extend:DI
6847 (subreg:QI
6848 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6849 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6850 (const_int 0)))
6851 (clobber (match_scratch:DI 3 ""))]
6852 "TARGET_POWERPC64 && reload_completed"
6853 [(set (match_dup 3)
6854 (zero_extend:DI (subreg:QI
6855 (rotate:DI (match_dup 1)
6856 (match_dup 2)) 0)))
6857 (set (match_dup 0)
6858 (compare:CC (match_dup 3)
6859 (const_int 0)))]
6860 "")
6861
6862 (define_insn "*rotldi3_internal9"
6863 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6864 (compare:CC (zero_extend:DI
6865 (subreg:QI
6866 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6867 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6868 (const_int 0)))
6869 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6870 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6871 "TARGET_64BIT"
6872 "@
6873 rldcl. %0,%1,%2,56
6874 rldicl. %0,%1,%H2,56
6875 #
6876 #"
6877 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6878 (set_attr "length" "4,4,8,8")])
6879
6880 (define_split
6881 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6882 (compare:CC (zero_extend:DI
6883 (subreg:QI
6884 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6885 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6886 (const_int 0)))
6887 (set (match_operand:DI 0 "gpc_reg_operand" "")
6888 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6889 "TARGET_POWERPC64 && reload_completed"
6890 [(set (match_dup 0)
6891 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6892 (set (match_dup 3)
6893 (compare:CC (match_dup 0)
6894 (const_int 0)))]
6895 "")
6896
6897 (define_insn "*rotldi3_internal10"
6898 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6899 (zero_extend:DI
6900 (subreg:HI
6901 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6902 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6903 "TARGET_POWERPC64"
6904 "@
6905 rldcl %0,%1,%2,48
6906 rldicl %0,%1,%H2,48"
6907 [(set_attr "type" "var_shift_rotate,integer")])
6908
6909 (define_insn "*rotldi3_internal11"
6910 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6911 (compare:CC (zero_extend:DI
6912 (subreg:HI
6913 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6914 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6915 (const_int 0)))
6916 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6917 "TARGET_64BIT"
6918 "@
6919 rldcl. %3,%1,%2,48
6920 rldicl. %3,%1,%H2,48
6921 #
6922 #"
6923 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6924 (set_attr "length" "4,4,8,8")])
6925
6926 (define_split
6927 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6928 (compare:CC (zero_extend:DI
6929 (subreg:HI
6930 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6931 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6932 (const_int 0)))
6933 (clobber (match_scratch:DI 3 ""))]
6934 "TARGET_POWERPC64 && reload_completed"
6935 [(set (match_dup 3)
6936 (zero_extend:DI (subreg:HI
6937 (rotate:DI (match_dup 1)
6938 (match_dup 2)) 0)))
6939 (set (match_dup 0)
6940 (compare:CC (match_dup 3)
6941 (const_int 0)))]
6942 "")
6943
6944 (define_insn "*rotldi3_internal12"
6945 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6946 (compare:CC (zero_extend:DI
6947 (subreg:HI
6948 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6949 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6950 (const_int 0)))
6951 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6952 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6953 "TARGET_64BIT"
6954 "@
6955 rldcl. %0,%1,%2,48
6956 rldicl. %0,%1,%H2,48
6957 #
6958 #"
6959 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6960 (set_attr "length" "4,4,8,8")])
6961
6962 (define_split
6963 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6964 (compare:CC (zero_extend:DI
6965 (subreg:HI
6966 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6967 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6968 (const_int 0)))
6969 (set (match_operand:DI 0 "gpc_reg_operand" "")
6970 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6971 "TARGET_POWERPC64 && reload_completed"
6972 [(set (match_dup 0)
6973 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6974 (set (match_dup 3)
6975 (compare:CC (match_dup 0)
6976 (const_int 0)))]
6977 "")
6978
6979 (define_insn "*rotldi3_internal13"
6980 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6981 (zero_extend:DI
6982 (subreg:SI
6983 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6984 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6985 "TARGET_POWERPC64"
6986 "@
6987 rldcl %0,%1,%2,32
6988 rldicl %0,%1,%H2,32"
6989 [(set_attr "type" "var_shift_rotate,integer")])
6990
6991 (define_insn "*rotldi3_internal14"
6992 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6993 (compare:CC (zero_extend:DI
6994 (subreg:SI
6995 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6996 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6997 (const_int 0)))
6998 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6999 "TARGET_64BIT"
7000 "@
7001 rldcl. %3,%1,%2,32
7002 rldicl. %3,%1,%H2,32
7003 #
7004 #"
7005 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7006 (set_attr "length" "4,4,8,8")])
7007
7008 (define_split
7009 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7010 (compare:CC (zero_extend:DI
7011 (subreg:SI
7012 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7013 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7014 (const_int 0)))
7015 (clobber (match_scratch:DI 3 ""))]
7016 "TARGET_POWERPC64 && reload_completed"
7017 [(set (match_dup 3)
7018 (zero_extend:DI (subreg:SI
7019 (rotate:DI (match_dup 1)
7020 (match_dup 2)) 0)))
7021 (set (match_dup 0)
7022 (compare:CC (match_dup 3)
7023 (const_int 0)))]
7024 "")
7025
7026 (define_insn "*rotldi3_internal15"
7027 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7028 (compare:CC (zero_extend:DI
7029 (subreg:SI
7030 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7031 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7032 (const_int 0)))
7033 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7034 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7035 "TARGET_64BIT"
7036 "@
7037 rldcl. %0,%1,%2,32
7038 rldicl. %0,%1,%H2,32
7039 #
7040 #"
7041 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7042 (set_attr "length" "4,4,8,8")])
7043
7044 (define_split
7045 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7046 (compare:CC (zero_extend:DI
7047 (subreg:SI
7048 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7049 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7050 (const_int 0)))
7051 (set (match_operand:DI 0 "gpc_reg_operand" "")
7052 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7053 "TARGET_POWERPC64 && reload_completed"
7054 [(set (match_dup 0)
7055 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7056 (set (match_dup 3)
7057 (compare:CC (match_dup 0)
7058 (const_int 0)))]
7059 "")
7060
7061 (define_expand "ashldi3"
7062 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7063 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7064 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7065 "TARGET_POWERPC64 || TARGET_POWER"
7066 "
7067 {
7068 if (TARGET_POWERPC64)
7069 ;
7070 else if (TARGET_POWER)
7071 {
7072 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
7073 DONE;
7074 }
7075 else
7076 FAIL;
7077 }")
7078
7079 (define_insn "*ashldi3_internal1"
7080 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7081 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7082 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7083 "TARGET_POWERPC64"
7084 "@
7085 sld %0,%1,%2
7086 sldi %0,%1,%H2"
7087 [(set_attr "type" "var_shift_rotate,shift")])
7088
7089 (define_insn "*ashldi3_internal2"
7090 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7091 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7092 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7093 (const_int 0)))
7094 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7095 "TARGET_64BIT"
7096 "@
7097 sld. %3,%1,%2
7098 sldi. %3,%1,%H2
7099 #
7100 #"
7101 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7102 (set_attr "length" "4,4,8,8")])
7103
7104 (define_split
7105 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7106 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7107 (match_operand:SI 2 "reg_or_cint_operand" ""))
7108 (const_int 0)))
7109 (clobber (match_scratch:DI 3 ""))]
7110 "TARGET_POWERPC64 && reload_completed"
7111 [(set (match_dup 3)
7112 (ashift:DI (match_dup 1) (match_dup 2)))
7113 (set (match_dup 0)
7114 (compare:CC (match_dup 3)
7115 (const_int 0)))]
7116 "")
7117
7118 (define_insn "*ashldi3_internal3"
7119 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7120 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7121 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7122 (const_int 0)))
7123 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7124 (ashift:DI (match_dup 1) (match_dup 2)))]
7125 "TARGET_64BIT"
7126 "@
7127 sld. %0,%1,%2
7128 sldi. %0,%1,%H2
7129 #
7130 #"
7131 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7132 (set_attr "length" "4,4,8,8")])
7133
7134 (define_split
7135 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7136 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7137 (match_operand:SI 2 "reg_or_cint_operand" ""))
7138 (const_int 0)))
7139 (set (match_operand:DI 0 "gpc_reg_operand" "")
7140 (ashift:DI (match_dup 1) (match_dup 2)))]
7141 "TARGET_POWERPC64 && reload_completed"
7142 [(set (match_dup 0)
7143 (ashift:DI (match_dup 1) (match_dup 2)))
7144 (set (match_dup 3)
7145 (compare:CC (match_dup 0)
7146 (const_int 0)))]
7147 "")
7148
7149 (define_insn "*ashldi3_internal4"
7150 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7151 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7152 (match_operand:SI 2 "const_int_operand" "i"))
7153 (match_operand:DI 3 "const_int_operand" "n")))]
7154 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7155 "rldic %0,%1,%H2,%W3")
7156
7157 (define_insn "ashldi3_internal5"
7158 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7159 (compare:CC
7160 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7161 (match_operand:SI 2 "const_int_operand" "i,i"))
7162 (match_operand:DI 3 "const_int_operand" "n,n"))
7163 (const_int 0)))
7164 (clobber (match_scratch:DI 4 "=r,r"))]
7165 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7166 "@
7167 rldic. %4,%1,%H2,%W3
7168 #"
7169 [(set_attr "type" "compare")
7170 (set_attr "length" "4,8")])
7171
7172 (define_split
7173 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7174 (compare:CC
7175 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7176 (match_operand:SI 2 "const_int_operand" ""))
7177 (match_operand:DI 3 "const_int_operand" ""))
7178 (const_int 0)))
7179 (clobber (match_scratch:DI 4 ""))]
7180 "TARGET_POWERPC64 && reload_completed
7181 && includes_rldic_lshift_p (operands[2], operands[3])"
7182 [(set (match_dup 4)
7183 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7184 (match_dup 3)))
7185 (set (match_dup 0)
7186 (compare:CC (match_dup 4)
7187 (const_int 0)))]
7188 "")
7189
7190 (define_insn "*ashldi3_internal6"
7191 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7192 (compare:CC
7193 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7194 (match_operand:SI 2 "const_int_operand" "i,i"))
7195 (match_operand:DI 3 "const_int_operand" "n,n"))
7196 (const_int 0)))
7197 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7198 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7199 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7200 "@
7201 rldic. %0,%1,%H2,%W3
7202 #"
7203 [(set_attr "type" "compare")
7204 (set_attr "length" "4,8")])
7205
7206 (define_split
7207 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7208 (compare:CC
7209 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7210 (match_operand:SI 2 "const_int_operand" ""))
7211 (match_operand:DI 3 "const_int_operand" ""))
7212 (const_int 0)))
7213 (set (match_operand:DI 0 "gpc_reg_operand" "")
7214 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7215 "TARGET_POWERPC64 && reload_completed
7216 && includes_rldic_lshift_p (operands[2], operands[3])"
7217 [(set (match_dup 0)
7218 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7219 (match_dup 3)))
7220 (set (match_dup 4)
7221 (compare:CC (match_dup 0)
7222 (const_int 0)))]
7223 "")
7224
7225 (define_insn "*ashldi3_internal7"
7226 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7227 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7228 (match_operand:SI 2 "const_int_operand" "i"))
7229 (match_operand:DI 3 "mask64_operand" "n")))]
7230 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7231 "rldicr %0,%1,%H2,%S3")
7232
7233 (define_insn "ashldi3_internal8"
7234 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7235 (compare:CC
7236 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7237 (match_operand:SI 2 "const_int_operand" "i,i"))
7238 (match_operand:DI 3 "mask64_operand" "n,n"))
7239 (const_int 0)))
7240 (clobber (match_scratch:DI 4 "=r,r"))]
7241 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7242 "@
7243 rldicr. %4,%1,%H2,%S3
7244 #"
7245 [(set_attr "type" "compare")
7246 (set_attr "length" "4,8")])
7247
7248 (define_split
7249 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7250 (compare:CC
7251 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7252 (match_operand:SI 2 "const_int_operand" ""))
7253 (match_operand:DI 3 "mask64_operand" ""))
7254 (const_int 0)))
7255 (clobber (match_scratch:DI 4 ""))]
7256 "TARGET_POWERPC64 && reload_completed
7257 && includes_rldicr_lshift_p (operands[2], operands[3])"
7258 [(set (match_dup 4)
7259 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7260 (match_dup 3)))
7261 (set (match_dup 0)
7262 (compare:CC (match_dup 4)
7263 (const_int 0)))]
7264 "")
7265
7266 (define_insn "*ashldi3_internal9"
7267 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7268 (compare:CC
7269 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7270 (match_operand:SI 2 "const_int_operand" "i,i"))
7271 (match_operand:DI 3 "mask64_operand" "n,n"))
7272 (const_int 0)))
7273 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7274 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7275 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7276 "@
7277 rldicr. %0,%1,%H2,%S3
7278 #"
7279 [(set_attr "type" "compare")
7280 (set_attr "length" "4,8")])
7281
7282 (define_split
7283 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7284 (compare:CC
7285 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7286 (match_operand:SI 2 "const_int_operand" ""))
7287 (match_operand:DI 3 "mask64_operand" ""))
7288 (const_int 0)))
7289 (set (match_operand:DI 0 "gpc_reg_operand" "")
7290 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7291 "TARGET_POWERPC64 && reload_completed
7292 && includes_rldicr_lshift_p (operands[2], operands[3])"
7293 [(set (match_dup 0)
7294 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7295 (match_dup 3)))
7296 (set (match_dup 4)
7297 (compare:CC (match_dup 0)
7298 (const_int 0)))]
7299 "")
7300
7301 (define_expand "lshrdi3"
7302 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7303 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7304 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7305 "TARGET_POWERPC64 || TARGET_POWER"
7306 "
7307 {
7308 if (TARGET_POWERPC64)
7309 ;
7310 else if (TARGET_POWER)
7311 {
7312 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7313 DONE;
7314 }
7315 else
7316 FAIL;
7317 }")
7318
7319 (define_insn "*lshrdi3_internal1"
7320 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7321 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7322 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7323 "TARGET_POWERPC64"
7324 "@
7325 srd %0,%1,%2
7326 srdi %0,%1,%H2"
7327 [(set_attr "type" "var_shift_rotate,shift")])
7328
7329 (define_insn "*lshrdi3_internal2"
7330 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7331 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7332 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7333 (const_int 0)))
7334 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7335 "TARGET_64BIT "
7336 "@
7337 srd. %3,%1,%2
7338 srdi. %3,%1,%H2
7339 #
7340 #"
7341 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7342 (set_attr "length" "4,4,8,8")])
7343
7344 (define_split
7345 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7346 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7347 (match_operand:SI 2 "reg_or_cint_operand" ""))
7348 (const_int 0)))
7349 (clobber (match_scratch:DI 3 ""))]
7350 "TARGET_POWERPC64 && reload_completed"
7351 [(set (match_dup 3)
7352 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7353 (set (match_dup 0)
7354 (compare:CC (match_dup 3)
7355 (const_int 0)))]
7356 "")
7357
7358 (define_insn "*lshrdi3_internal3"
7359 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7360 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7361 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7362 (const_int 0)))
7363 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7364 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7365 "TARGET_64BIT"
7366 "@
7367 srd. %0,%1,%2
7368 srdi. %0,%1,%H2
7369 #
7370 #"
7371 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7372 (set_attr "length" "4,4,8,8")])
7373
7374 (define_split
7375 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7376 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7377 (match_operand:SI 2 "reg_or_cint_operand" ""))
7378 (const_int 0)))
7379 (set (match_operand:DI 0 "gpc_reg_operand" "")
7380 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7381 "TARGET_POWERPC64 && reload_completed"
7382 [(set (match_dup 0)
7383 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7384 (set (match_dup 3)
7385 (compare:CC (match_dup 0)
7386 (const_int 0)))]
7387 "")
7388
7389 (define_expand "ashrdi3"
7390 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7391 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7392 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7393 "WORDS_BIG_ENDIAN"
7394 "
7395 {
7396 if (TARGET_POWERPC64)
7397 ;
7398 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7399 {
7400 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7401 DONE;
7402 }
7403 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7404 && WORDS_BIG_ENDIAN)
7405 {
7406 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7407 DONE;
7408 }
7409 else
7410 FAIL;
7411 }")
7412
7413 (define_insn "*ashrdi3_internal1"
7414 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7415 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7416 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7417 "TARGET_POWERPC64"
7418 "@
7419 srad %0,%1,%2
7420 sradi %0,%1,%H2"
7421 [(set_attr "type" "var_shift_rotate,shift")])
7422
7423 (define_insn "*ashrdi3_internal2"
7424 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7425 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7426 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7427 (const_int 0)))
7428 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7429 "TARGET_64BIT"
7430 "@
7431 srad. %3,%1,%2
7432 sradi. %3,%1,%H2
7433 #
7434 #"
7435 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7436 (set_attr "length" "4,4,8,8")])
7437
7438 (define_split
7439 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7440 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7441 (match_operand:SI 2 "reg_or_cint_operand" ""))
7442 (const_int 0)))
7443 (clobber (match_scratch:DI 3 ""))]
7444 "TARGET_POWERPC64 && reload_completed"
7445 [(set (match_dup 3)
7446 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7447 (set (match_dup 0)
7448 (compare:CC (match_dup 3)
7449 (const_int 0)))]
7450 "")
7451
7452 (define_insn "*ashrdi3_internal3"
7453 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7454 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7455 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7456 (const_int 0)))
7457 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7458 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7459 "TARGET_64BIT"
7460 "@
7461 srad. %0,%1,%2
7462 sradi. %0,%1,%H2
7463 #
7464 #"
7465 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7466 (set_attr "length" "4,4,8,8")])
7467
7468 (define_split
7469 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7470 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7471 (match_operand:SI 2 "reg_or_cint_operand" ""))
7472 (const_int 0)))
7473 (set (match_operand:DI 0 "gpc_reg_operand" "")
7474 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7475 "TARGET_POWERPC64 && reload_completed"
7476 [(set (match_dup 0)
7477 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7478 (set (match_dup 3)
7479 (compare:CC (match_dup 0)
7480 (const_int 0)))]
7481 "")
7482
7483 (define_insn "anddi3"
7484 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7485 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7486 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7487 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7488 "TARGET_POWERPC64"
7489 "@
7490 and %0,%1,%2
7491 rldic%B2 %0,%1,0,%S2
7492 rlwinm %0,%1,0,%m2,%M2
7493 andi. %0,%1,%b2
7494 andis. %0,%1,%u2
7495 #"
7496 [(set_attr "type" "*,*,*,compare,compare,*")
7497 (set_attr "length" "4,4,4,4,4,8")])
7498
7499 (define_split
7500 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7501 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7502 (match_operand:DI 2 "mask64_2_operand" "")))
7503 (clobber (match_scratch:CC 3 ""))]
7504 "TARGET_POWERPC64
7505 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7506 && !mask_operand (operands[2], DImode)
7507 && !mask64_operand (operands[2], DImode)"
7508 [(set (match_dup 0)
7509 (and:DI (rotate:DI (match_dup 1)
7510 (match_dup 4))
7511 (match_dup 5)))
7512 (set (match_dup 0)
7513 (and:DI (rotate:DI (match_dup 0)
7514 (match_dup 6))
7515 (match_dup 7)))]
7516 {
7517 build_mask64_2_operands (operands[2], &operands[4]);
7518 })
7519
7520 (define_insn "*anddi3_internal2"
7521 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7522 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7523 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7524 (const_int 0)))
7525 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7526 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7527 "TARGET_64BIT"
7528 "@
7529 and. %3,%1,%2
7530 rldic%B2. %3,%1,0,%S2
7531 rlwinm. %3,%1,0,%m2,%M2
7532 andi. %3,%1,%b2
7533 andis. %3,%1,%u2
7534 #
7535 #
7536 #
7537 #
7538 #
7539 #
7540 #"
7541 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7542 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7543
7544 (define_split
7545 [(set (match_operand:CC 0 "cc_reg_operand" "")
7546 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7547 (match_operand:DI 2 "mask64_2_operand" ""))
7548 (const_int 0)))
7549 (clobber (match_scratch:DI 3 ""))
7550 (clobber (match_scratch:CC 4 ""))]
7551 "TARGET_64BIT && reload_completed
7552 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7553 && !mask_operand (operands[2], DImode)
7554 && !mask64_operand (operands[2], DImode)"
7555 [(set (match_dup 3)
7556 (and:DI (rotate:DI (match_dup 1)
7557 (match_dup 5))
7558 (match_dup 6)))
7559 (parallel [(set (match_dup 0)
7560 (compare:CC (and:DI (rotate:DI (match_dup 3)
7561 (match_dup 7))
7562 (match_dup 8))
7563 (const_int 0)))
7564 (clobber (match_dup 3))])]
7565 "
7566 {
7567 build_mask64_2_operands (operands[2], &operands[5]);
7568 }")
7569
7570 (define_insn "*anddi3_internal3"
7571 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7572 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7573 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7574 (const_int 0)))
7575 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
7576 (and:DI (match_dup 1) (match_dup 2)))
7577 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7578 "TARGET_64BIT"
7579 "@
7580 and. %0,%1,%2
7581 rldic%B2. %0,%1,0,%S2
7582 rlwinm. %0,%1,0,%m2,%M2
7583 andi. %0,%1,%b2
7584 andis. %0,%1,%u2
7585 #
7586 #
7587 #
7588 #
7589 #
7590 #
7591 #"
7592 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7593 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7594
7595 (define_split
7596 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7597 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7598 (match_operand:DI 2 "and64_2_operand" ""))
7599 (const_int 0)))
7600 (set (match_operand:DI 0 "gpc_reg_operand" "")
7601 (and:DI (match_dup 1) (match_dup 2)))
7602 (clobber (match_scratch:CC 4 ""))]
7603 "TARGET_64BIT && reload_completed"
7604 [(parallel [(set (match_dup 0)
7605 (and:DI (match_dup 1) (match_dup 2)))
7606 (clobber (match_dup 4))])
7607 (set (match_dup 3)
7608 (compare:CC (match_dup 0)
7609 (const_int 0)))]
7610 "")
7611
7612 (define_split
7613 [(set (match_operand:CC 3 "cc_reg_operand" "")
7614 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7615 (match_operand:DI 2 "mask64_2_operand" ""))
7616 (const_int 0)))
7617 (set (match_operand:DI 0 "gpc_reg_operand" "")
7618 (and:DI (match_dup 1) (match_dup 2)))
7619 (clobber (match_scratch:CC 4 ""))]
7620 "TARGET_64BIT && reload_completed
7621 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7622 && !mask_operand (operands[2], DImode)
7623 && !mask64_operand (operands[2], DImode)"
7624 [(set (match_dup 0)
7625 (and:DI (rotate:DI (match_dup 1)
7626 (match_dup 5))
7627 (match_dup 6)))
7628 (parallel [(set (match_dup 3)
7629 (compare:CC (and:DI (rotate:DI (match_dup 0)
7630 (match_dup 7))
7631 (match_dup 8))
7632 (const_int 0)))
7633 (set (match_dup 0)
7634 (and:DI (rotate:DI (match_dup 0)
7635 (match_dup 7))
7636 (match_dup 8)))])]
7637 "
7638 {
7639 build_mask64_2_operands (operands[2], &operands[5]);
7640 }")
7641
7642 (define_expand "iordi3"
7643 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7644 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7645 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7646 "TARGET_POWERPC64"
7647 "
7648 {
7649 if (non_logical_cint_operand (operands[2], DImode))
7650 {
7651 HOST_WIDE_INT value;
7652 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7653 ? operands[0] : gen_reg_rtx (DImode));
7654
7655 if (GET_CODE (operands[2]) == CONST_INT)
7656 {
7657 value = INTVAL (operands[2]);
7658 emit_insn (gen_iordi3 (tmp, operands[1],
7659 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7660 }
7661 else
7662 {
7663 value = CONST_DOUBLE_LOW (operands[2]);
7664 emit_insn (gen_iordi3 (tmp, operands[1],
7665 immed_double_const (value
7666 & (~ (HOST_WIDE_INT) 0xffff),
7667 0, DImode)));
7668 }
7669
7670 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7671 DONE;
7672 }
7673 }")
7674
7675 (define_expand "xordi3"
7676 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7677 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7678 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7679 "TARGET_POWERPC64"
7680 "
7681 {
7682 if (non_logical_cint_operand (operands[2], DImode))
7683 {
7684 HOST_WIDE_INT value;
7685 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7686 ? operands[0] : gen_reg_rtx (DImode));
7687
7688 if (GET_CODE (operands[2]) == CONST_INT)
7689 {
7690 value = INTVAL (operands[2]);
7691 emit_insn (gen_xordi3 (tmp, operands[1],
7692 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7693 }
7694 else
7695 {
7696 value = CONST_DOUBLE_LOW (operands[2]);
7697 emit_insn (gen_xordi3 (tmp, operands[1],
7698 immed_double_const (value
7699 & (~ (HOST_WIDE_INT) 0xffff),
7700 0, DImode)));
7701 }
7702
7703 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7704 DONE;
7705 }
7706 }")
7707
7708 (define_insn "*booldi3_internal1"
7709 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7710 (match_operator:DI 3 "boolean_or_operator"
7711 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7712 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7713 "TARGET_POWERPC64"
7714 "@
7715 %q3 %0,%1,%2
7716 %q3i %0,%1,%b2
7717 %q3is %0,%1,%u2")
7718
7719 (define_insn "*booldi3_internal2"
7720 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7721 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7722 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7723 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7724 (const_int 0)))
7725 (clobber (match_scratch:DI 3 "=r,r"))]
7726 "TARGET_64BIT"
7727 "@
7728 %q4. %3,%1,%2
7729 #"
7730 [(set_attr "type" "compare")
7731 (set_attr "length" "4,8")])
7732
7733 (define_split
7734 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7735 (compare:CC (match_operator:DI 4 "boolean_operator"
7736 [(match_operand:DI 1 "gpc_reg_operand" "")
7737 (match_operand:DI 2 "gpc_reg_operand" "")])
7738 (const_int 0)))
7739 (clobber (match_scratch:DI 3 ""))]
7740 "TARGET_POWERPC64 && reload_completed"
7741 [(set (match_dup 3) (match_dup 4))
7742 (set (match_dup 0)
7743 (compare:CC (match_dup 3)
7744 (const_int 0)))]
7745 "")
7746
7747 (define_insn "*booldi3_internal3"
7748 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7749 (compare:CC (match_operator:DI 4 "boolean_operator"
7750 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7751 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7752 (const_int 0)))
7753 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7754 (match_dup 4))]
7755 "TARGET_64BIT"
7756 "@
7757 %q4. %0,%1,%2
7758 #"
7759 [(set_attr "type" "compare")
7760 (set_attr "length" "4,8")])
7761
7762 (define_split
7763 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7764 (compare:CC (match_operator:DI 4 "boolean_operator"
7765 [(match_operand:DI 1 "gpc_reg_operand" "")
7766 (match_operand:DI 2 "gpc_reg_operand" "")])
7767 (const_int 0)))
7768 (set (match_operand:DI 0 "gpc_reg_operand" "")
7769 (match_dup 4))]
7770 "TARGET_POWERPC64 && reload_completed"
7771 [(set (match_dup 0) (match_dup 4))
7772 (set (match_dup 3)
7773 (compare:CC (match_dup 0)
7774 (const_int 0)))]
7775 "")
7776
7777 ;; Split a logical operation that we can't do in one insn into two insns,
7778 ;; each of which does one 16-bit part. This is used by combine.
7779
7780 (define_split
7781 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7782 (match_operator:DI 3 "boolean_or_operator"
7783 [(match_operand:DI 1 "gpc_reg_operand" "")
7784 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7785 "TARGET_POWERPC64"
7786 [(set (match_dup 0) (match_dup 4))
7787 (set (match_dup 0) (match_dup 5))]
7788 "
7789 {
7790 rtx i3,i4;
7791
7792 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7793 {
7794 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7795 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7796 0, DImode);
7797 i4 = GEN_INT (value & 0xffff);
7798 }
7799 else
7800 {
7801 i3 = GEN_INT (INTVAL (operands[2])
7802 & (~ (HOST_WIDE_INT) 0xffff));
7803 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7804 }
7805 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7806 operands[1], i3);
7807 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7808 operands[0], i4);
7809 }")
7810
7811 (define_insn "*boolcdi3_internal1"
7812 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7813 (match_operator:DI 3 "boolean_operator"
7814 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7815 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7816 "TARGET_POWERPC64"
7817 "%q3 %0,%2,%1")
7818
7819 (define_insn "*boolcdi3_internal2"
7820 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7821 (compare:CC (match_operator:DI 4 "boolean_operator"
7822 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7823 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7824 (const_int 0)))
7825 (clobber (match_scratch:DI 3 "=r,r"))]
7826 "TARGET_64BIT"
7827 "@
7828 %q4. %3,%2,%1
7829 #"
7830 [(set_attr "type" "compare")
7831 (set_attr "length" "4,8")])
7832
7833 (define_split
7834 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7835 (compare:CC (match_operator:DI 4 "boolean_operator"
7836 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7837 (match_operand:DI 2 "gpc_reg_operand" "")])
7838 (const_int 0)))
7839 (clobber (match_scratch:DI 3 ""))]
7840 "TARGET_POWERPC64 && reload_completed"
7841 [(set (match_dup 3) (match_dup 4))
7842 (set (match_dup 0)
7843 (compare:CC (match_dup 3)
7844 (const_int 0)))]
7845 "")
7846
7847 (define_insn "*boolcdi3_internal3"
7848 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7849 (compare:CC (match_operator:DI 4 "boolean_operator"
7850 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7851 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7852 (const_int 0)))
7853 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7854 (match_dup 4))]
7855 "TARGET_64BIT"
7856 "@
7857 %q4. %0,%2,%1
7858 #"
7859 [(set_attr "type" "compare")
7860 (set_attr "length" "4,8")])
7861
7862 (define_split
7863 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7864 (compare:CC (match_operator:DI 4 "boolean_operator"
7865 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7866 (match_operand:DI 2 "gpc_reg_operand" "")])
7867 (const_int 0)))
7868 (set (match_operand:DI 0 "gpc_reg_operand" "")
7869 (match_dup 4))]
7870 "TARGET_POWERPC64 && reload_completed"
7871 [(set (match_dup 0) (match_dup 4))
7872 (set (match_dup 3)
7873 (compare:CC (match_dup 0)
7874 (const_int 0)))]
7875 "")
7876
7877 (define_insn "*boolccdi3_internal1"
7878 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7879 (match_operator:DI 3 "boolean_operator"
7880 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7881 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7882 "TARGET_POWERPC64"
7883 "%q3 %0,%1,%2")
7884
7885 (define_insn "*boolccdi3_internal2"
7886 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7887 (compare:CC (match_operator:DI 4 "boolean_operator"
7888 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7889 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7890 (const_int 0)))
7891 (clobber (match_scratch:DI 3 "=r,r"))]
7892 "TARGET_64BIT"
7893 "@
7894 %q4. %3,%1,%2
7895 #"
7896 [(set_attr "type" "compare")
7897 (set_attr "length" "4,8")])
7898
7899 (define_split
7900 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7901 (compare:CC (match_operator:DI 4 "boolean_operator"
7902 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7903 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7904 (const_int 0)))
7905 (clobber (match_scratch:DI 3 ""))]
7906 "TARGET_POWERPC64 && reload_completed"
7907 [(set (match_dup 3) (match_dup 4))
7908 (set (match_dup 0)
7909 (compare:CC (match_dup 3)
7910 (const_int 0)))]
7911 "")
7912
7913 (define_insn "*boolccdi3_internal3"
7914 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7915 (compare:CC (match_operator:DI 4 "boolean_operator"
7916 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7917 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7918 (const_int 0)))
7919 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7920 (match_dup 4))]
7921 "TARGET_64BIT"
7922 "@
7923 %q4. %0,%1,%2
7924 #"
7925 [(set_attr "type" "compare")
7926 (set_attr "length" "4,8")])
7927
7928 (define_split
7929 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7930 (compare:CC (match_operator:DI 4 "boolean_operator"
7931 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7932 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7933 (const_int 0)))
7934 (set (match_operand:DI 0 "gpc_reg_operand" "")
7935 (match_dup 4))]
7936 "TARGET_POWERPC64 && reload_completed"
7937 [(set (match_dup 0) (match_dup 4))
7938 (set (match_dup 3)
7939 (compare:CC (match_dup 0)
7940 (const_int 0)))]
7941 "")
7942 \f
7943 ;; Now define ways of moving data around.
7944
7945 ;; Set up a register with a value from the GOT table
7946
7947 (define_expand "movsi_got"
7948 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7949 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7950 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7951 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7952 "
7953 {
7954 if (GET_CODE (operands[1]) == CONST)
7955 {
7956 rtx offset = const0_rtx;
7957 HOST_WIDE_INT value;
7958
7959 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7960 value = INTVAL (offset);
7961 if (value != 0)
7962 {
7963 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7964 emit_insn (gen_movsi_got (tmp, operands[1]));
7965 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7966 DONE;
7967 }
7968 }
7969
7970 operands[2] = rs6000_got_register (operands[1]);
7971 }")
7972
7973 (define_insn "*movsi_got_internal"
7974 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7975 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7976 (match_operand:SI 2 "gpc_reg_operand" "b")]
7977 UNSPEC_MOVSI_GOT))]
7978 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7979 "{l|lwz} %0,%a1@got(%2)"
7980 [(set_attr "type" "load")])
7981
7982 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7983 ;; didn't get allocated to a hard register.
7984 (define_split
7985 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7986 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7987 (match_operand:SI 2 "memory_operand" "")]
7988 UNSPEC_MOVSI_GOT))]
7989 "DEFAULT_ABI == ABI_V4
7990 && flag_pic == 1
7991 && (reload_in_progress || reload_completed)"
7992 [(set (match_dup 0) (match_dup 2))
7993 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7994 UNSPEC_MOVSI_GOT))]
7995 "")
7996
7997 ;; For SI, we special-case integers that can't be loaded in one insn. We
7998 ;; do the load 16-bits at a time. We could do this by loading from memory,
7999 ;; and this is even supposed to be faster, but it is simpler not to get
8000 ;; integers in the TOC.
8001 (define_insn "movsi_low"
8002 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8003 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
8004 (match_operand 2 "" ""))))]
8005 "TARGET_MACHO && ! TARGET_64BIT"
8006 "{l|lwz} %0,lo16(%2)(%1)"
8007 [(set_attr "type" "load")
8008 (set_attr "length" "4")])
8009
8010 (define_insn "*movsi_internal1"
8011 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
8012 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
8013 "gpc_reg_operand (operands[0], SImode)
8014 || gpc_reg_operand (operands[1], SImode)"
8015 "@
8016 mr %0,%1
8017 {cal|la} %0,%a1
8018 {l%U1%X1|lwz%U1%X1} %0,%1
8019 {st%U0%X0|stw%U0%X0} %1,%0
8020 {lil|li} %0,%1
8021 {liu|lis} %0,%v1
8022 #
8023 {cal|la} %0,%a1
8024 mf%1 %0
8025 mt%0 %1
8026 mt%0 %1
8027 mt%0 %1
8028 {cror 0,0,0|nop}"
8029 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
8030 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
8031
8032 ;; Split a load of a large constant into the appropriate two-insn
8033 ;; sequence.
8034
8035 (define_split
8036 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8037 (match_operand:SI 1 "const_int_operand" ""))]
8038 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
8039 && (INTVAL (operands[1]) & 0xffff) != 0"
8040 [(set (match_dup 0)
8041 (match_dup 2))
8042 (set (match_dup 0)
8043 (ior:SI (match_dup 0)
8044 (match_dup 3)))]
8045 "
8046 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8047
8048 if (tem == operands[0])
8049 DONE;
8050 else
8051 FAIL;
8052 }")
8053
8054 (define_insn "*mov<mode>_internal2"
8055 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8056 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
8057 (const_int 0)))
8058 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8059 ""
8060 "@
8061 {cmpi|cmp<wd>i} %2,%0,0
8062 mr. %0,%1
8063 #"
8064 [(set_attr "type" "cmp,compare,cmp")
8065 (set_attr "length" "4,4,8")])
8066
8067 (define_split
8068 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8069 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
8070 (const_int 0)))
8071 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8072 "reload_completed"
8073 [(set (match_dup 0) (match_dup 1))
8074 (set (match_dup 2)
8075 (compare:CC (match_dup 0)
8076 (const_int 0)))]
8077 "")
8078 \f
8079 (define_insn "*movhi_internal"
8080 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8081 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8082 "gpc_reg_operand (operands[0], HImode)
8083 || gpc_reg_operand (operands[1], HImode)"
8084 "@
8085 mr %0,%1
8086 lhz%U1%X1 %0,%1
8087 sth%U0%X0 %1,%0
8088 {lil|li} %0,%w1
8089 mf%1 %0
8090 mt%0 %1
8091 mt%0 %1
8092 {cror 0,0,0|nop}"
8093 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8094
8095 (define_expand "mov<mode>"
8096 [(set (match_operand:INT 0 "general_operand" "")
8097 (match_operand:INT 1 "any_operand" ""))]
8098 ""
8099 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8100
8101 (define_insn "*movqi_internal"
8102 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8103 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8104 "gpc_reg_operand (operands[0], QImode)
8105 || gpc_reg_operand (operands[1], QImode)"
8106 "@
8107 mr %0,%1
8108 lbz%U1%X1 %0,%1
8109 stb%U0%X0 %1,%0
8110 {lil|li} %0,%1
8111 mf%1 %0
8112 mt%0 %1
8113 mt%0 %1
8114 {cror 0,0,0|nop}"
8115 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8116 \f
8117 ;; Here is how to move condition codes around. When we store CC data in
8118 ;; an integer register or memory, we store just the high-order 4 bits.
8119 ;; This lets us not shift in the most common case of CR0.
8120 (define_expand "movcc"
8121 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8122 (match_operand:CC 1 "nonimmediate_operand" ""))]
8123 ""
8124 "")
8125
8126 (define_insn "*movcc_internal1"
8127 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
8128 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
8129 "register_operand (operands[0], CCmode)
8130 || register_operand (operands[1], CCmode)"
8131 "@
8132 mcrf %0,%1
8133 mtcrf 128,%1
8134 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
8135 crxor %0,%0,%0
8136 mfcr %0%Q1
8137 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
8138 mr %0,%1
8139 {lil|li} %0,%1
8140 mf%1 %0
8141 mt%0 %1
8142 mt%0 %1
8143 {l%U1%X1|lwz%U1%X1} %0,%1
8144 {st%U0%U1|stw%U0%U1} %1,%0"
8145 [(set (attr "type")
8146 (cond [(eq_attr "alternative" "0,3")
8147 (const_string "cr_logical")
8148 (eq_attr "alternative" "1,2")
8149 (const_string "mtcr")
8150 (eq_attr "alternative" "6,7,9")
8151 (const_string "integer")
8152 (eq_attr "alternative" "8")
8153 (const_string "mfjmpr")
8154 (eq_attr "alternative" "10")
8155 (const_string "mtjmpr")
8156 (eq_attr "alternative" "11")
8157 (const_string "load")
8158 (eq_attr "alternative" "12")
8159 (const_string "store")
8160 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
8161 (const_string "mfcrf")
8162 ]
8163 (const_string "mfcr")))
8164 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
8165 \f
8166 ;; For floating-point, we normally deal with the floating-point registers
8167 ;; unless -msoft-float is used. The sole exception is that parameter passing
8168 ;; can produce floating-point values in fixed-point registers. Unless the
8169 ;; value is a simple constant or already in memory, we deal with this by
8170 ;; allocating memory and copying the value explicitly via that memory location.
8171 (define_expand "movsf"
8172 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8173 (match_operand:SF 1 "any_operand" ""))]
8174 ""
8175 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
8176
8177 (define_split
8178 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8179 (match_operand:SF 1 "const_double_operand" ""))]
8180 "reload_completed
8181 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8182 || (GET_CODE (operands[0]) == SUBREG
8183 && GET_CODE (SUBREG_REG (operands[0])) == REG
8184 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8185 [(set (match_dup 2) (match_dup 3))]
8186 "
8187 {
8188 long l;
8189 REAL_VALUE_TYPE rv;
8190
8191 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8192 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
8193
8194 if (! TARGET_POWERPC64)
8195 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
8196 else
8197 operands[2] = gen_lowpart (SImode, operands[0]);
8198
8199 operands[3] = gen_int_mode (l, SImode);
8200 }")
8201
8202 (define_insn "*movsf_hardfloat"
8203 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
8204 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
8205 "(gpc_reg_operand (operands[0], SFmode)
8206 || gpc_reg_operand (operands[1], SFmode))
8207 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
8208 "@
8209 mr %0,%1
8210 {l%U1%X1|lwz%U1%X1} %0,%1
8211 {st%U0%X0|stw%U0%X0} %1,%0
8212 fmr %0,%1
8213 lfs%U1%X1 %0,%1
8214 stfs%U0%X0 %1,%0
8215 mt%0 %1
8216 mt%0 %1
8217 mf%1 %0
8218 {cror 0,0,0|nop}
8219 #
8220 #"
8221 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
8222 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
8223
8224 (define_insn "*movsf_softfloat"
8225 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
8226 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
8227 "(gpc_reg_operand (operands[0], SFmode)
8228 || gpc_reg_operand (operands[1], SFmode))
8229 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
8230 "@
8231 mr %0,%1
8232 mt%0 %1
8233 mt%0 %1
8234 mf%1 %0
8235 {l%U1%X1|lwz%U1%X1} %0,%1
8236 {st%U0%X0|stw%U0%X0} %1,%0
8237 {lil|li} %0,%1
8238 {liu|lis} %0,%v1
8239 {cal|la} %0,%a1
8240 #
8241 #
8242 {cror 0,0,0|nop}"
8243 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
8244 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
8245
8246 \f
8247 (define_expand "movdf"
8248 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8249 (match_operand:DF 1 "any_operand" ""))]
8250 ""
8251 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
8252
8253 (define_split
8254 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8255 (match_operand:DF 1 "const_int_operand" ""))]
8256 "! TARGET_POWERPC64 && reload_completed
8257 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8258 || (GET_CODE (operands[0]) == SUBREG
8259 && GET_CODE (SUBREG_REG (operands[0])) == REG
8260 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8261 [(set (match_dup 2) (match_dup 4))
8262 (set (match_dup 3) (match_dup 1))]
8263 "
8264 {
8265 int endian = (WORDS_BIG_ENDIAN == 0);
8266 HOST_WIDE_INT value = INTVAL (operands[1]);
8267
8268 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8269 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8270 #if HOST_BITS_PER_WIDE_INT == 32
8271 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8272 #else
8273 operands[4] = GEN_INT (value >> 32);
8274 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8275 #endif
8276 }")
8277
8278 (define_split
8279 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8280 (match_operand:DF 1 "const_double_operand" ""))]
8281 "! TARGET_POWERPC64 && reload_completed
8282 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8283 || (GET_CODE (operands[0]) == SUBREG
8284 && GET_CODE (SUBREG_REG (operands[0])) == REG
8285 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8286 [(set (match_dup 2) (match_dup 4))
8287 (set (match_dup 3) (match_dup 5))]
8288 "
8289 {
8290 int endian = (WORDS_BIG_ENDIAN == 0);
8291 long l[2];
8292 REAL_VALUE_TYPE rv;
8293
8294 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8295 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8296
8297 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8298 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8299 operands[4] = gen_int_mode (l[endian], SImode);
8300 operands[5] = gen_int_mode (l[1 - endian], SImode);
8301 }")
8302
8303 (define_split
8304 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8305 (match_operand:DF 1 "const_double_operand" ""))]
8306 "TARGET_POWERPC64 && reload_completed
8307 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8308 || (GET_CODE (operands[0]) == SUBREG
8309 && GET_CODE (SUBREG_REG (operands[0])) == REG
8310 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8311 [(set (match_dup 2) (match_dup 3))]
8312 "
8313 {
8314 int endian = (WORDS_BIG_ENDIAN == 0);
8315 long l[2];
8316 REAL_VALUE_TYPE rv;
8317 #if HOST_BITS_PER_WIDE_INT >= 64
8318 HOST_WIDE_INT val;
8319 #endif
8320
8321 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8322 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8323
8324 operands[2] = gen_lowpart (DImode, operands[0]);
8325 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8326 #if HOST_BITS_PER_WIDE_INT >= 64
8327 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8328 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8329
8330 operands[3] = gen_int_mode (val, DImode);
8331 #else
8332 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8333 #endif
8334 }")
8335
8336 ;; Don't have reload use general registers to load a constant. First,
8337 ;; it might not work if the output operand is the equivalent of
8338 ;; a non-offsettable memref, but also it is less efficient than loading
8339 ;; the constant into an FP register, since it will probably be used there.
8340 ;; The "??" is a kludge until we can figure out a more reasonable way
8341 ;; of handling these non-offsettable values.
8342 (define_insn "*movdf_hardfloat32"
8343 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8344 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
8345 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8346 && (gpc_reg_operand (operands[0], DFmode)
8347 || gpc_reg_operand (operands[1], DFmode))"
8348 "*
8349 {
8350 switch (which_alternative)
8351 {
8352 default:
8353 gcc_unreachable ();
8354 case 0:
8355 /* We normally copy the low-numbered register first. However, if
8356 the first register operand 0 is the same as the second register
8357 of operand 1, we must copy in the opposite order. */
8358 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8359 return \"mr %L0,%L1\;mr %0,%1\";
8360 else
8361 return \"mr %0,%1\;mr %L0,%L1\";
8362 case 1:
8363 if (rs6000_offsettable_memref_p (operands[1])
8364 || (GET_CODE (operands[1]) == MEM
8365 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8366 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8367 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)))
8368 {
8369 /* If the low-address word is used in the address, we must load
8370 it last. Otherwise, load it first. Note that we cannot have
8371 auto-increment in that case since the address register is
8372 known to be dead. */
8373 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8374 operands[1], 0))
8375 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8376 else
8377 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8378 }
8379 else
8380 {
8381 rtx addreg;
8382
8383 addreg = find_addr_reg (XEXP (operands[1], 0));
8384 if (refers_to_regno_p (REGNO (operands[0]),
8385 REGNO (operands[0]) + 1,
8386 operands[1], 0))
8387 {
8388 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8389 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
8390 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8391 return \"{l%X1|lwz%X1} %0,%1\";
8392 }
8393 else
8394 {
8395 output_asm_insn (\"{l%X1|lwz%X1} %0,%1\", operands);
8396 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8397 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
8398 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8399 return \"\";
8400 }
8401 }
8402 case 2:
8403 if (rs6000_offsettable_memref_p (operands[0])
8404 || (GET_CODE (operands[0]) == MEM
8405 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8406 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8407 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)))
8408 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8409 else
8410 {
8411 rtx addreg;
8412
8413 addreg = find_addr_reg (XEXP (operands[0], 0));
8414 output_asm_insn (\"{st%X0|stw%X0} %1,%0\", operands);
8415 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8416 output_asm_insn (\"{st%X0|stw%X0} %L1,%0\", operands);
8417 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8418 return \"\";
8419 }
8420 case 3:
8421 return \"fmr %0,%1\";
8422 case 4:
8423 return \"lfd%U1%X1 %0,%1\";
8424 case 5:
8425 return \"stfd%U0%X0 %1,%0\";
8426 case 6:
8427 case 7:
8428 case 8:
8429 return \"#\";
8430 }
8431 }"
8432 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
8433 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
8434
8435 (define_insn "*movdf_softfloat32"
8436 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8437 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8438 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8439 && (gpc_reg_operand (operands[0], DFmode)
8440 || gpc_reg_operand (operands[1], DFmode))"
8441 "*
8442 {
8443 switch (which_alternative)
8444 {
8445 default:
8446 gcc_unreachable ();
8447 case 0:
8448 /* We normally copy the low-numbered register first. However, if
8449 the first register operand 0 is the same as the second register of
8450 operand 1, we must copy in the opposite order. */
8451 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8452 return \"mr %L0,%L1\;mr %0,%1\";
8453 else
8454 return \"mr %0,%1\;mr %L0,%L1\";
8455 case 1:
8456 /* If the low-address word is used in the address, we must load
8457 it last. Otherwise, load it first. Note that we cannot have
8458 auto-increment in that case since the address register is
8459 known to be dead. */
8460 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8461 operands[1], 0))
8462 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8463 else
8464 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8465 case 2:
8466 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8467 case 3:
8468 case 4:
8469 case 5:
8470 return \"#\";
8471 }
8472 }"
8473 [(set_attr "type" "two,load,store,*,*,*")
8474 (set_attr "length" "8,8,8,8,12,16")])
8475
8476 ; ld/std require word-aligned displacements -> 'Y' constraint.
8477 ; List Y->r and r->Y before r->r for reload.
8478 (define_insn "*movdf_hardfloat64_mfpgpr"
8479 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f")
8480 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))]
8481 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8482 && (gpc_reg_operand (operands[0], DFmode)
8483 || gpc_reg_operand (operands[1], DFmode))"
8484 "@
8485 std%U0%X0 %1,%0
8486 ld%U1%X1 %0,%1
8487 mr %0,%1
8488 fmr %0,%1
8489 lfd%U1%X1 %0,%1
8490 stfd%U0%X0 %1,%0
8491 mt%0 %1
8492 mf%1 %0
8493 {cror 0,0,0|nop}
8494 #
8495 #
8496 #
8497 mftgpr %0,%1
8498 mffgpr %0,%1"
8499 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
8500 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
8501
8502 ; ld/std require word-aligned displacements -> 'Y' constraint.
8503 ; List Y->r and r->Y before r->r for reload.
8504 (define_insn "*movdf_hardfloat64"
8505 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
8506 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
8507 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8508 && (gpc_reg_operand (operands[0], DFmode)
8509 || gpc_reg_operand (operands[1], DFmode))"
8510 "@
8511 std%U0%X0 %1,%0
8512 ld%U1%X1 %0,%1
8513 mr %0,%1
8514 fmr %0,%1
8515 lfd%U1%X1 %0,%1
8516 stfd%U0%X0 %1,%0
8517 mt%0 %1
8518 mf%1 %0
8519 {cror 0,0,0|nop}
8520 #
8521 #
8522 #"
8523 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
8524 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
8525
8526 (define_insn "*movdf_softfloat64"
8527 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8528 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
8529 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8530 && (gpc_reg_operand (operands[0], DFmode)
8531 || gpc_reg_operand (operands[1], DFmode))"
8532 "@
8533 ld%U1%X1 %0,%1
8534 std%U0%X0 %1,%0
8535 mr %0,%1
8536 mt%0 %1
8537 mf%1 %0
8538 #
8539 #
8540 #
8541 {cror 0,0,0|nop}"
8542 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
8543 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8544 \f
8545 (define_expand "movtf"
8546 [(set (match_operand:TF 0 "general_operand" "")
8547 (match_operand:TF 1 "any_operand" ""))]
8548 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
8549 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8550
8551 ; It's important to list the o->f and f->o moves before f->f because
8552 ; otherwise reload, given m->f, will try to pick f->f and reload it,
8553 ; which doesn't make progress. Likewise r->Y must be before r->r.
8554 (define_insn_and_split "*movtf_internal"
8555 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
8556 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
8557 "!TARGET_IEEEQUAD
8558 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8559 && (gpc_reg_operand (operands[0], TFmode)
8560 || gpc_reg_operand (operands[1], TFmode))"
8561 "#"
8562 "&& reload_completed"
8563 [(pc)]
8564 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8565 [(set_attr "length" "8,8,8,20,20,16")])
8566
8567 (define_insn_and_split "*movtf_softfloat"
8568 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
8569 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
8570 "!TARGET_IEEEQUAD
8571 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
8572 && (gpc_reg_operand (operands[0], TFmode)
8573 || gpc_reg_operand (operands[1], TFmode))"
8574 "#"
8575 "&& reload_completed"
8576 [(pc)]
8577 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8578 [(set_attr "length" "20,20,16")])
8579
8580 (define_expand "extenddftf2"
8581 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8582 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8583 "!TARGET_IEEEQUAD
8584 && TARGET_HARD_FLOAT
8585 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8586 && TARGET_LONG_DOUBLE_128"
8587 {
8588 if (TARGET_E500_DOUBLE)
8589 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8590 else
8591 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8592 DONE;
8593 })
8594
8595 (define_expand "extenddftf2_fprs"
8596 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8597 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8598 (use (match_dup 2))])]
8599 "!TARGET_IEEEQUAD
8600 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8601 {
8602 operands[2] = CONST0_RTX (DFmode);
8603 /* Generate GOT reference early for SVR4 PIC. */
8604 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8605 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8606 })
8607
8608 (define_insn_and_split "*extenddftf2_internal"
8609 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8610 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8611 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
8612 "!TARGET_IEEEQUAD
8613 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8614 "#"
8615 "&& reload_completed"
8616 [(pc)]
8617 {
8618 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8619 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8620 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8621 operands[1]);
8622 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8623 operands[2]);
8624 DONE;
8625 })
8626
8627 (define_expand "extendsftf2"
8628 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8629 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8630 "!TARGET_IEEEQUAD
8631 && TARGET_HARD_FLOAT
8632 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8633 && TARGET_LONG_DOUBLE_128"
8634 {
8635 rtx tmp = gen_reg_rtx (DFmode);
8636 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8637 emit_insn (gen_extenddftf2 (operands[0], tmp));
8638 DONE;
8639 })
8640
8641 (define_expand "trunctfdf2"
8642 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8643 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8644 "!TARGET_IEEEQUAD
8645 && TARGET_HARD_FLOAT
8646 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8647 && TARGET_LONG_DOUBLE_128"
8648 "")
8649
8650 (define_insn_and_split "trunctfdf2_internal1"
8651 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8652 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
8653 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8654 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8655 "@
8656 #
8657 fmr %0,%1"
8658 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8659 [(const_int 0)]
8660 {
8661 emit_note (NOTE_INSN_DELETED);
8662 DONE;
8663 }
8664 [(set_attr "type" "fp")])
8665
8666 (define_insn "trunctfdf2_internal2"
8667 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8668 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8669 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8670 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8671 "fadd %0,%1,%L1"
8672 [(set_attr "type" "fp")])
8673
8674 (define_expand "trunctfsf2"
8675 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8676 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8677 "!TARGET_IEEEQUAD
8678 && TARGET_HARD_FLOAT
8679 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8680 && TARGET_LONG_DOUBLE_128"
8681 {
8682 if (TARGET_E500_DOUBLE)
8683 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8684 else
8685 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8686 DONE;
8687 })
8688
8689 (define_insn_and_split "trunctfsf2_fprs"
8690 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8691 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8692 (clobber (match_scratch:DF 2 "=f"))]
8693 "!TARGET_IEEEQUAD
8694 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8695 "#"
8696 "&& reload_completed"
8697 [(set (match_dup 2)
8698 (float_truncate:DF (match_dup 1)))
8699 (set (match_dup 0)
8700 (float_truncate:SF (match_dup 2)))]
8701 "")
8702
8703 (define_expand "floatsitf2"
8704 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8705 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
8706 "!TARGET_IEEEQUAD
8707 && TARGET_HARD_FLOAT
8708 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8709 && TARGET_LONG_DOUBLE_128"
8710 {
8711 rtx tmp = gen_reg_rtx (DFmode);
8712 expand_float (tmp, operands[1], false);
8713 emit_insn (gen_extenddftf2 (operands[0], tmp));
8714 DONE;
8715 })
8716
8717 ; fadd, but rounding towards zero.
8718 ; This is probably not the optimal code sequence.
8719 (define_insn "fix_trunc_helper"
8720 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8721 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8722 UNSPEC_FIX_TRUNC_TF))
8723 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8724 "TARGET_HARD_FLOAT && TARGET_FPRS"
8725 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8726 [(set_attr "type" "fp")
8727 (set_attr "length" "20")])
8728
8729 (define_expand "fix_trunctfsi2"
8730 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8731 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8732 "!TARGET_IEEEQUAD
8733 && (TARGET_POWER2 || TARGET_POWERPC)
8734 && TARGET_HARD_FLOAT
8735 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8736 && TARGET_LONG_DOUBLE_128"
8737 {
8738 if (TARGET_E500_DOUBLE)
8739 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8740 else
8741 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8742 DONE;
8743 })
8744
8745 (define_expand "fix_trunctfsi2_fprs"
8746 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8747 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8748 (clobber (match_dup 2))
8749 (clobber (match_dup 3))
8750 (clobber (match_dup 4))
8751 (clobber (match_dup 5))])]
8752 "!TARGET_IEEEQUAD
8753 && (TARGET_POWER2 || TARGET_POWERPC)
8754 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8755 {
8756 operands[2] = gen_reg_rtx (DFmode);
8757 operands[3] = gen_reg_rtx (DFmode);
8758 operands[4] = gen_reg_rtx (DImode);
8759 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8760 })
8761
8762 (define_insn_and_split "*fix_trunctfsi2_internal"
8763 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8764 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8765 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8766 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8767 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8768 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
8769 "!TARGET_IEEEQUAD
8770 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8771 "#"
8772 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[5]))"
8773 [(pc)]
8774 {
8775 rtx lowword;
8776 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8777
8778 gcc_assert (MEM_P (operands[5]));
8779 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8780
8781 emit_insn (gen_fctiwz (operands[4], operands[2]));
8782 emit_move_insn (operands[5], operands[4]);
8783 emit_move_insn (operands[0], lowword);
8784 DONE;
8785 })
8786
8787 (define_expand "negtf2"
8788 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8789 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8790 "!TARGET_IEEEQUAD
8791 && TARGET_HARD_FLOAT
8792 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8793 && TARGET_LONG_DOUBLE_128"
8794 "")
8795
8796 (define_insn "negtf2_internal"
8797 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8798 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8799 "!TARGET_IEEEQUAD
8800 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8801 "*
8802 {
8803 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8804 return \"fneg %L0,%L1\;fneg %0,%1\";
8805 else
8806 return \"fneg %0,%1\;fneg %L0,%L1\";
8807 }"
8808 [(set_attr "type" "fp")
8809 (set_attr "length" "8")])
8810
8811 (define_expand "abstf2"
8812 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8813 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8814 "!TARGET_IEEEQUAD
8815 && TARGET_HARD_FLOAT
8816 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8817 && TARGET_LONG_DOUBLE_128"
8818 "
8819 {
8820 rtx label = gen_label_rtx ();
8821 if (TARGET_E500_DOUBLE)
8822 {
8823 if (flag_unsafe_math_optimizations)
8824 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
8825 else
8826 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
8827 }
8828 else
8829 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8830 emit_label (label);
8831 DONE;
8832 }")
8833
8834 (define_expand "abstf2_internal"
8835 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8836 (match_operand:TF 1 "gpc_reg_operand" ""))
8837 (set (match_dup 3) (match_dup 5))
8838 (set (match_dup 5) (abs:DF (match_dup 5)))
8839 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8840 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8841 (label_ref (match_operand 2 "" ""))
8842 (pc)))
8843 (set (match_dup 6) (neg:DF (match_dup 6)))]
8844 "!TARGET_IEEEQUAD
8845 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8846 "
8847 {
8848 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8849 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8850 operands[3] = gen_reg_rtx (DFmode);
8851 operands[4] = gen_reg_rtx (CCFPmode);
8852 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8853 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8854 }")
8855 \f
8856 ;; Next come the multi-word integer load and store and the load and store
8857 ;; multiple insns.
8858
8859 ; List r->r after r->"o<>", otherwise reload will try to reload a
8860 ; non-offsettable address by using r->r which won't make progress.
8861 (define_insn "*movdi_internal32"
8862 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
8863 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
8864 "! TARGET_POWERPC64
8865 && (gpc_reg_operand (operands[0], DImode)
8866 || gpc_reg_operand (operands[1], DImode))"
8867 "@
8868 #
8869 #
8870 #
8871 fmr %0,%1
8872 lfd%U1%X1 %0,%1
8873 stfd%U0%X0 %1,%0
8874 #"
8875 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
8876
8877 (define_split
8878 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8879 (match_operand:DI 1 "const_int_operand" ""))]
8880 "! TARGET_POWERPC64 && reload_completed"
8881 [(set (match_dup 2) (match_dup 4))
8882 (set (match_dup 3) (match_dup 1))]
8883 "
8884 {
8885 HOST_WIDE_INT value = INTVAL (operands[1]);
8886 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8887 DImode);
8888 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8889 DImode);
8890 #if HOST_BITS_PER_WIDE_INT == 32
8891 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8892 #else
8893 operands[4] = GEN_INT (value >> 32);
8894 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8895 #endif
8896 }")
8897
8898 (define_split
8899 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "")
8900 (match_operand:DI 1 "input_operand" ""))]
8901 "reload_completed && !TARGET_POWERPC64
8902 && gpr_or_gpr_p (operands[0], operands[1])"
8903 [(pc)]
8904 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8905
8906 (define_insn "*movdi_mfpgpr"
8907 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h,r,*f")
8908 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0,*f,r"))]
8909 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8910 && (gpc_reg_operand (operands[0], DImode)
8911 || gpc_reg_operand (operands[1], DImode))"
8912 "@
8913 mr %0,%1
8914 ld%U1%X1 %0,%1
8915 std%U0%X0 %1,%0
8916 li %0,%1
8917 lis %0,%v1
8918 #
8919 {cal|la} %0,%a1
8920 fmr %0,%1
8921 lfd%U1%X1 %0,%1
8922 stfd%U0%X0 %1,%0
8923 mf%1 %0
8924 mt%0 %1
8925 {cror 0,0,0|nop}
8926 mftgpr %0,%1
8927 mffgpr %0,%1"
8928 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
8929 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
8930
8931 (define_insn "*movdi_internal64"
8932 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
8933 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8934 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
8935 && (gpc_reg_operand (operands[0], DImode)
8936 || gpc_reg_operand (operands[1], DImode))"
8937 "@
8938 mr %0,%1
8939 ld%U1%X1 %0,%1
8940 std%U0%X0 %1,%0
8941 li %0,%1
8942 lis %0,%v1
8943 #
8944 {cal|la} %0,%a1
8945 fmr %0,%1
8946 lfd%U1%X1 %0,%1
8947 stfd%U0%X0 %1,%0
8948 mf%1 %0
8949 mt%0 %1
8950 {cror 0,0,0|nop}"
8951 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
8952 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8953
8954 ;; immediate value valid for a single instruction hiding in a const_double
8955 (define_insn ""
8956 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8957 (match_operand:DI 1 "const_double_operand" "F"))]
8958 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8959 && GET_CODE (operands[1]) == CONST_DOUBLE
8960 && num_insns_constant (operands[1], DImode) == 1"
8961 "*
8962 {
8963 return ((unsigned HOST_WIDE_INT)
8964 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8965 ? \"li %0,%1\" : \"lis %0,%v1\";
8966 }")
8967
8968 ;; Generate all one-bits and clear left or right.
8969 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8970 (define_split
8971 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8972 (match_operand:DI 1 "mask64_operand" ""))]
8973 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8974 [(set (match_dup 0) (const_int -1))
8975 (set (match_dup 0)
8976 (and:DI (rotate:DI (match_dup 0)
8977 (const_int 0))
8978 (match_dup 1)))]
8979 "")
8980
8981 ;; Split a load of a large constant into the appropriate five-instruction
8982 ;; sequence. Handle anything in a constant number of insns.
8983 ;; When non-easy constants can go in the TOC, this should use
8984 ;; easy_fp_constant predicate.
8985 (define_split
8986 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8987 (match_operand:DI 1 "const_int_operand" ""))]
8988 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8989 [(set (match_dup 0) (match_dup 2))
8990 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8991 "
8992 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8993
8994 if (tem == operands[0])
8995 DONE;
8996 else
8997 FAIL;
8998 }")
8999
9000 (define_split
9001 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9002 (match_operand:DI 1 "const_double_operand" ""))]
9003 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9004 [(set (match_dup 0) (match_dup 2))
9005 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9006 "
9007 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9008
9009 if (tem == operands[0])
9010 DONE;
9011 else
9012 FAIL;
9013 }")
9014 \f
9015 ;; TImode is similar, except that we usually want to compute the address into
9016 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
9017 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
9018
9019 ;; We say that MQ is clobbered in the last alternative because the first
9020 ;; alternative would never get used otherwise since it would need a reload
9021 ;; while the 2nd alternative would not. We put memory cases first so they
9022 ;; are preferred. Otherwise, we'd try to reload the output instead of
9023 ;; giving the SCRATCH mq.
9024
9025 (define_insn "*movti_power"
9026 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
9027 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
9028 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
9029 "TARGET_POWER && ! TARGET_POWERPC64
9030 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9031 "*
9032 {
9033 switch (which_alternative)
9034 {
9035 default:
9036 gcc_unreachable ();
9037
9038 case 0:
9039 if (TARGET_STRING)
9040 return \"{stsi|stswi} %1,%P0,16\";
9041 case 1:
9042 case 2:
9043 return \"#\";
9044 case 3:
9045 /* If the address is not used in the output, we can use lsi. Otherwise,
9046 fall through to generating four loads. */
9047 if (TARGET_STRING
9048 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9049 return \"{lsi|lswi} %0,%P1,16\";
9050 /* ... fall through ... */
9051 case 4:
9052 case 5:
9053 return \"#\";
9054 }
9055 }"
9056 [(set_attr "type" "store,store,*,load,load,*")])
9057
9058 (define_insn "*movti_string"
9059 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
9060 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
9061 "! TARGET_POWER && ! TARGET_POWERPC64
9062 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9063 "*
9064 {
9065 switch (which_alternative)
9066 {
9067 default:
9068 gcc_unreachable ();
9069 case 0:
9070 if (TARGET_STRING)
9071 return \"{stsi|stswi} %1,%P0,16\";
9072 case 1:
9073 case 2:
9074 return \"#\";
9075 case 3:
9076 /* If the address is not used in the output, we can use lsi. Otherwise,
9077 fall through to generating four loads. */
9078 if (TARGET_STRING
9079 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9080 return \"{lsi|lswi} %0,%P1,16\";
9081 /* ... fall through ... */
9082 case 4:
9083 case 5:
9084 return \"#\";
9085 }
9086 }"
9087 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")])
9088
9089 (define_insn "*movti_ppc64"
9090 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
9091 (match_operand:TI 1 "input_operand" "r,r,m"))]
9092 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
9093 || gpc_reg_operand (operands[1], TImode))"
9094 "#"
9095 [(set_attr "type" "*,load,store")])
9096
9097 (define_split
9098 [(set (match_operand:TI 0 "gpc_reg_operand" "")
9099 (match_operand:TI 1 "const_double_operand" ""))]
9100 "TARGET_POWERPC64"
9101 [(set (match_dup 2) (match_dup 4))
9102 (set (match_dup 3) (match_dup 5))]
9103 "
9104 {
9105 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9106 TImode);
9107 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9108 TImode);
9109 if (GET_CODE (operands[1]) == CONST_DOUBLE)
9110 {
9111 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9112 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9113 }
9114 else if (GET_CODE (operands[1]) == CONST_INT)
9115 {
9116 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9117 operands[5] = operands[1];
9118 }
9119 else
9120 FAIL;
9121 }")
9122
9123 (define_split
9124 [(set (match_operand:TI 0 "nonimmediate_operand" "")
9125 (match_operand:TI 1 "input_operand" ""))]
9126 "reload_completed
9127 && gpr_or_gpr_p (operands[0], operands[1])"
9128 [(pc)]
9129 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9130 \f
9131 (define_expand "load_multiple"
9132 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9133 (match_operand:SI 1 "" ""))
9134 (use (match_operand:SI 2 "" ""))])]
9135 "TARGET_STRING && !TARGET_POWERPC64"
9136 "
9137 {
9138 int regno;
9139 int count;
9140 rtx op1;
9141 int i;
9142
9143 /* Support only loading a constant number of fixed-point registers from
9144 memory and only bother with this if more than two; the machine
9145 doesn't support more than eight. */
9146 if (GET_CODE (operands[2]) != CONST_INT
9147 || INTVAL (operands[2]) <= 2
9148 || INTVAL (operands[2]) > 8
9149 || GET_CODE (operands[1]) != MEM
9150 || GET_CODE (operands[0]) != REG
9151 || REGNO (operands[0]) >= 32)
9152 FAIL;
9153
9154 count = INTVAL (operands[2]);
9155 regno = REGNO (operands[0]);
9156
9157 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9158 op1 = replace_equiv_address (operands[1],
9159 force_reg (SImode, XEXP (operands[1], 0)));
9160
9161 for (i = 0; i < count; i++)
9162 XVECEXP (operands[3], 0, i)
9163 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
9164 adjust_address_nv (op1, SImode, i * 4));
9165 }")
9166
9167 (define_insn "*ldmsi8"
9168 [(match_parallel 0 "load_multiple_operation"
9169 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9170 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9171 (set (match_operand:SI 3 "gpc_reg_operand" "")
9172 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9173 (set (match_operand:SI 4 "gpc_reg_operand" "")
9174 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9175 (set (match_operand:SI 5 "gpc_reg_operand" "")
9176 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9177 (set (match_operand:SI 6 "gpc_reg_operand" "")
9178 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9179 (set (match_operand:SI 7 "gpc_reg_operand" "")
9180 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9181 (set (match_operand:SI 8 "gpc_reg_operand" "")
9182 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9183 (set (match_operand:SI 9 "gpc_reg_operand" "")
9184 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9185 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9186 "*
9187 { return rs6000_output_load_multiple (operands); }"
9188 [(set_attr "type" "load_ux")
9189 (set_attr "length" "32")])
9190
9191 (define_insn "*ldmsi7"
9192 [(match_parallel 0 "load_multiple_operation"
9193 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9194 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9195 (set (match_operand:SI 3 "gpc_reg_operand" "")
9196 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9197 (set (match_operand:SI 4 "gpc_reg_operand" "")
9198 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9199 (set (match_operand:SI 5 "gpc_reg_operand" "")
9200 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9201 (set (match_operand:SI 6 "gpc_reg_operand" "")
9202 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9203 (set (match_operand:SI 7 "gpc_reg_operand" "")
9204 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9205 (set (match_operand:SI 8 "gpc_reg_operand" "")
9206 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9207 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9208 "*
9209 { return rs6000_output_load_multiple (operands); }"
9210 [(set_attr "type" "load_ux")
9211 (set_attr "length" "32")])
9212
9213 (define_insn "*ldmsi6"
9214 [(match_parallel 0 "load_multiple_operation"
9215 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9216 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9217 (set (match_operand:SI 3 "gpc_reg_operand" "")
9218 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9219 (set (match_operand:SI 4 "gpc_reg_operand" "")
9220 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9221 (set (match_operand:SI 5 "gpc_reg_operand" "")
9222 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9223 (set (match_operand:SI 6 "gpc_reg_operand" "")
9224 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9225 (set (match_operand:SI 7 "gpc_reg_operand" "")
9226 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9227 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9228 "*
9229 { return rs6000_output_load_multiple (operands); }"
9230 [(set_attr "type" "load_ux")
9231 (set_attr "length" "32")])
9232
9233 (define_insn "*ldmsi5"
9234 [(match_parallel 0 "load_multiple_operation"
9235 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9236 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9237 (set (match_operand:SI 3 "gpc_reg_operand" "")
9238 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9239 (set (match_operand:SI 4 "gpc_reg_operand" "")
9240 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9241 (set (match_operand:SI 5 "gpc_reg_operand" "")
9242 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9243 (set (match_operand:SI 6 "gpc_reg_operand" "")
9244 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9245 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9246 "*
9247 { return rs6000_output_load_multiple (operands); }"
9248 [(set_attr "type" "load_ux")
9249 (set_attr "length" "32")])
9250
9251 (define_insn "*ldmsi4"
9252 [(match_parallel 0 "load_multiple_operation"
9253 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9254 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9255 (set (match_operand:SI 3 "gpc_reg_operand" "")
9256 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9257 (set (match_operand:SI 4 "gpc_reg_operand" "")
9258 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9259 (set (match_operand:SI 5 "gpc_reg_operand" "")
9260 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9261 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9262 "*
9263 { return rs6000_output_load_multiple (operands); }"
9264 [(set_attr "type" "load_ux")
9265 (set_attr "length" "32")])
9266
9267 (define_insn "*ldmsi3"
9268 [(match_parallel 0 "load_multiple_operation"
9269 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9270 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9271 (set (match_operand:SI 3 "gpc_reg_operand" "")
9272 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9273 (set (match_operand:SI 4 "gpc_reg_operand" "")
9274 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9275 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9276 "*
9277 { return rs6000_output_load_multiple (operands); }"
9278 [(set_attr "type" "load_ux")
9279 (set_attr "length" "32")])
9280
9281 (define_expand "store_multiple"
9282 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9283 (match_operand:SI 1 "" ""))
9284 (clobber (scratch:SI))
9285 (use (match_operand:SI 2 "" ""))])]
9286 "TARGET_STRING && !TARGET_POWERPC64"
9287 "
9288 {
9289 int regno;
9290 int count;
9291 rtx to;
9292 rtx op0;
9293 int i;
9294
9295 /* Support only storing a constant number of fixed-point registers to
9296 memory and only bother with this if more than two; the machine
9297 doesn't support more than eight. */
9298 if (GET_CODE (operands[2]) != CONST_INT
9299 || INTVAL (operands[2]) <= 2
9300 || INTVAL (operands[2]) > 8
9301 || GET_CODE (operands[0]) != MEM
9302 || GET_CODE (operands[1]) != REG
9303 || REGNO (operands[1]) >= 32)
9304 FAIL;
9305
9306 count = INTVAL (operands[2]);
9307 regno = REGNO (operands[1]);
9308
9309 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
9310 to = force_reg (SImode, XEXP (operands[0], 0));
9311 op0 = replace_equiv_address (operands[0], to);
9312
9313 XVECEXP (operands[3], 0, 0)
9314 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
9315 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
9316 gen_rtx_SCRATCH (SImode));
9317
9318 for (i = 1; i < count; i++)
9319 XVECEXP (operands[3], 0, i + 1)
9320 = gen_rtx_SET (VOIDmode,
9321 adjust_address_nv (op0, SImode, i * 4),
9322 gen_rtx_REG (SImode, regno + i));
9323 }")
9324
9325 (define_insn "*stmsi8"
9326 [(match_parallel 0 "store_multiple_operation"
9327 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9328 (match_operand:SI 2 "gpc_reg_operand" "r"))
9329 (clobber (match_scratch:SI 3 "=X"))
9330 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9331 (match_operand:SI 4 "gpc_reg_operand" "r"))
9332 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9333 (match_operand:SI 5 "gpc_reg_operand" "r"))
9334 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9335 (match_operand:SI 6 "gpc_reg_operand" "r"))
9336 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9337 (match_operand:SI 7 "gpc_reg_operand" "r"))
9338 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9339 (match_operand:SI 8 "gpc_reg_operand" "r"))
9340 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9341 (match_operand:SI 9 "gpc_reg_operand" "r"))
9342 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9343 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9344 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9345 "{stsi|stswi} %2,%1,%O0"
9346 [(set_attr "type" "store_ux")])
9347
9348 (define_insn "*stmsi7"
9349 [(match_parallel 0 "store_multiple_operation"
9350 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9351 (match_operand:SI 2 "gpc_reg_operand" "r"))
9352 (clobber (match_scratch:SI 3 "=X"))
9353 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9354 (match_operand:SI 4 "gpc_reg_operand" "r"))
9355 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9356 (match_operand:SI 5 "gpc_reg_operand" "r"))
9357 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9358 (match_operand:SI 6 "gpc_reg_operand" "r"))
9359 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9360 (match_operand:SI 7 "gpc_reg_operand" "r"))
9361 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9362 (match_operand:SI 8 "gpc_reg_operand" "r"))
9363 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9364 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9365 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9366 "{stsi|stswi} %2,%1,%O0"
9367 [(set_attr "type" "store_ux")])
9368
9369 (define_insn "*stmsi6"
9370 [(match_parallel 0 "store_multiple_operation"
9371 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9372 (match_operand:SI 2 "gpc_reg_operand" "r"))
9373 (clobber (match_scratch:SI 3 "=X"))
9374 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9375 (match_operand:SI 4 "gpc_reg_operand" "r"))
9376 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9377 (match_operand:SI 5 "gpc_reg_operand" "r"))
9378 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9379 (match_operand:SI 6 "gpc_reg_operand" "r"))
9380 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9381 (match_operand:SI 7 "gpc_reg_operand" "r"))
9382 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9383 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9384 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9385 "{stsi|stswi} %2,%1,%O0"
9386 [(set_attr "type" "store_ux")])
9387
9388 (define_insn "*stmsi5"
9389 [(match_parallel 0 "store_multiple_operation"
9390 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9391 (match_operand:SI 2 "gpc_reg_operand" "r"))
9392 (clobber (match_scratch:SI 3 "=X"))
9393 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9394 (match_operand:SI 4 "gpc_reg_operand" "r"))
9395 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9396 (match_operand:SI 5 "gpc_reg_operand" "r"))
9397 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9398 (match_operand:SI 6 "gpc_reg_operand" "r"))
9399 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9400 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9401 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9402 "{stsi|stswi} %2,%1,%O0"
9403 [(set_attr "type" "store_ux")])
9404
9405 (define_insn "*stmsi4"
9406 [(match_parallel 0 "store_multiple_operation"
9407 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9408 (match_operand:SI 2 "gpc_reg_operand" "r"))
9409 (clobber (match_scratch:SI 3 "=X"))
9410 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9411 (match_operand:SI 4 "gpc_reg_operand" "r"))
9412 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9413 (match_operand:SI 5 "gpc_reg_operand" "r"))
9414 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9415 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9416 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9417 "{stsi|stswi} %2,%1,%O0"
9418 [(set_attr "type" "store_ux")])
9419
9420 (define_insn "*stmsi3"
9421 [(match_parallel 0 "store_multiple_operation"
9422 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9423 (match_operand:SI 2 "gpc_reg_operand" "r"))
9424 (clobber (match_scratch:SI 3 "=X"))
9425 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9426 (match_operand:SI 4 "gpc_reg_operand" "r"))
9427 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9428 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9429 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9430 "{stsi|stswi} %2,%1,%O0"
9431 [(set_attr "type" "store_ux")])
9432
9433 (define_insn "*stmsi8_power"
9434 [(match_parallel 0 "store_multiple_operation"
9435 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9436 (match_operand:SI 2 "gpc_reg_operand" "r"))
9437 (clobber (match_scratch:SI 3 "=q"))
9438 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9439 (match_operand:SI 4 "gpc_reg_operand" "r"))
9440 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9441 (match_operand:SI 5 "gpc_reg_operand" "r"))
9442 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9443 (match_operand:SI 6 "gpc_reg_operand" "r"))
9444 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9445 (match_operand:SI 7 "gpc_reg_operand" "r"))
9446 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9447 (match_operand:SI 8 "gpc_reg_operand" "r"))
9448 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9449 (match_operand:SI 9 "gpc_reg_operand" "r"))
9450 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9451 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9452 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9453 "{stsi|stswi} %2,%1,%O0"
9454 [(set_attr "type" "store_ux")])
9455
9456 (define_insn "*stmsi7_power"
9457 [(match_parallel 0 "store_multiple_operation"
9458 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9459 (match_operand:SI 2 "gpc_reg_operand" "r"))
9460 (clobber (match_scratch:SI 3 "=q"))
9461 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9462 (match_operand:SI 4 "gpc_reg_operand" "r"))
9463 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9464 (match_operand:SI 5 "gpc_reg_operand" "r"))
9465 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9466 (match_operand:SI 6 "gpc_reg_operand" "r"))
9467 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9468 (match_operand:SI 7 "gpc_reg_operand" "r"))
9469 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9470 (match_operand:SI 8 "gpc_reg_operand" "r"))
9471 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9472 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9473 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9474 "{stsi|stswi} %2,%1,%O0"
9475 [(set_attr "type" "store_ux")])
9476
9477 (define_insn "*stmsi6_power"
9478 [(match_parallel 0 "store_multiple_operation"
9479 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9480 (match_operand:SI 2 "gpc_reg_operand" "r"))
9481 (clobber (match_scratch:SI 3 "=q"))
9482 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9483 (match_operand:SI 4 "gpc_reg_operand" "r"))
9484 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9485 (match_operand:SI 5 "gpc_reg_operand" "r"))
9486 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9487 (match_operand:SI 6 "gpc_reg_operand" "r"))
9488 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9489 (match_operand:SI 7 "gpc_reg_operand" "r"))
9490 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9491 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9492 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9493 "{stsi|stswi} %2,%1,%O0"
9494 [(set_attr "type" "store_ux")])
9495
9496 (define_insn "*stmsi5_power"
9497 [(match_parallel 0 "store_multiple_operation"
9498 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9499 (match_operand:SI 2 "gpc_reg_operand" "r"))
9500 (clobber (match_scratch:SI 3 "=q"))
9501 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9502 (match_operand:SI 4 "gpc_reg_operand" "r"))
9503 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9504 (match_operand:SI 5 "gpc_reg_operand" "r"))
9505 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9506 (match_operand:SI 6 "gpc_reg_operand" "r"))
9507 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9508 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9509 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9510 "{stsi|stswi} %2,%1,%O0"
9511 [(set_attr "type" "store_ux")])
9512
9513 (define_insn "*stmsi4_power"
9514 [(match_parallel 0 "store_multiple_operation"
9515 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9516 (match_operand:SI 2 "gpc_reg_operand" "r"))
9517 (clobber (match_scratch:SI 3 "=q"))
9518 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9519 (match_operand:SI 4 "gpc_reg_operand" "r"))
9520 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9521 (match_operand:SI 5 "gpc_reg_operand" "r"))
9522 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9523 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9524 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9525 "{stsi|stswi} %2,%1,%O0"
9526 [(set_attr "type" "store_ux")])
9527
9528 (define_insn "*stmsi3_power"
9529 [(match_parallel 0 "store_multiple_operation"
9530 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9531 (match_operand:SI 2 "gpc_reg_operand" "r"))
9532 (clobber (match_scratch:SI 3 "=q"))
9533 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9534 (match_operand:SI 4 "gpc_reg_operand" "r"))
9535 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9536 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9537 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9538 "{stsi|stswi} %2,%1,%O0"
9539 [(set_attr "type" "store_ux")])
9540 \f
9541 (define_expand "setmemsi"
9542 [(parallel [(set (match_operand:BLK 0 "" "")
9543 (match_operand 2 "const_int_operand" ""))
9544 (use (match_operand:SI 1 "" ""))
9545 (use (match_operand:SI 3 "" ""))])]
9546 ""
9547 "
9548 {
9549 /* If value to set is not zero, use the library routine. */
9550 if (operands[2] != const0_rtx)
9551 FAIL;
9552
9553 if (expand_block_clear (operands))
9554 DONE;
9555 else
9556 FAIL;
9557 }")
9558
9559 ;; String/block move insn.
9560 ;; Argument 0 is the destination
9561 ;; Argument 1 is the source
9562 ;; Argument 2 is the length
9563 ;; Argument 3 is the alignment
9564
9565 (define_expand "movmemsi"
9566 [(parallel [(set (match_operand:BLK 0 "" "")
9567 (match_operand:BLK 1 "" ""))
9568 (use (match_operand:SI 2 "" ""))
9569 (use (match_operand:SI 3 "" ""))])]
9570 ""
9571 "
9572 {
9573 if (expand_block_move (operands))
9574 DONE;
9575 else
9576 FAIL;
9577 }")
9578
9579 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9580 ;; register allocator doesn't have a clue about allocating 8 word registers.
9581 ;; rD/rS = r5 is preferred, efficient form.
9582 (define_expand "movmemsi_8reg"
9583 [(parallel [(set (match_operand 0 "" "")
9584 (match_operand 1 "" ""))
9585 (use (match_operand 2 "" ""))
9586 (use (match_operand 3 "" ""))
9587 (clobber (reg:SI 5))
9588 (clobber (reg:SI 6))
9589 (clobber (reg:SI 7))
9590 (clobber (reg:SI 8))
9591 (clobber (reg:SI 9))
9592 (clobber (reg:SI 10))
9593 (clobber (reg:SI 11))
9594 (clobber (reg:SI 12))
9595 (clobber (match_scratch:SI 4 ""))])]
9596 "TARGET_STRING"
9597 "")
9598
9599 (define_insn ""
9600 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9601 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9602 (use (match_operand:SI 2 "immediate_operand" "i"))
9603 (use (match_operand:SI 3 "immediate_operand" "i"))
9604 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9605 (clobber (reg:SI 6))
9606 (clobber (reg:SI 7))
9607 (clobber (reg:SI 8))
9608 (clobber (reg:SI 9))
9609 (clobber (reg:SI 10))
9610 (clobber (reg:SI 11))
9611 (clobber (reg:SI 12))
9612 (clobber (match_scratch:SI 5 "=q"))]
9613 "TARGET_STRING && TARGET_POWER
9614 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9615 || INTVAL (operands[2]) == 0)
9616 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9617 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9618 && REGNO (operands[4]) == 5"
9619 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9620 [(set_attr "type" "store_ux")
9621 (set_attr "length" "8")])
9622
9623 (define_insn ""
9624 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9625 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9626 (use (match_operand:SI 2 "immediate_operand" "i"))
9627 (use (match_operand:SI 3 "immediate_operand" "i"))
9628 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9629 (clobber (reg:SI 6))
9630 (clobber (reg:SI 7))
9631 (clobber (reg:SI 8))
9632 (clobber (reg:SI 9))
9633 (clobber (reg:SI 10))
9634 (clobber (reg:SI 11))
9635 (clobber (reg:SI 12))
9636 (clobber (match_scratch:SI 5 "=X"))]
9637 "TARGET_STRING && ! TARGET_POWER
9638 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9639 || INTVAL (operands[2]) == 0)
9640 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9641 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9642 && REGNO (operands[4]) == 5"
9643 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9644 [(set_attr "type" "store_ux")
9645 (set_attr "length" "8")])
9646
9647 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9648 ;; register allocator doesn't have a clue about allocating 6 word registers.
9649 ;; rD/rS = r5 is preferred, efficient form.
9650 (define_expand "movmemsi_6reg"
9651 [(parallel [(set (match_operand 0 "" "")
9652 (match_operand 1 "" ""))
9653 (use (match_operand 2 "" ""))
9654 (use (match_operand 3 "" ""))
9655 (clobber (reg:SI 5))
9656 (clobber (reg:SI 6))
9657 (clobber (reg:SI 7))
9658 (clobber (reg:SI 8))
9659 (clobber (reg:SI 9))
9660 (clobber (reg:SI 10))
9661 (clobber (match_scratch:SI 4 ""))])]
9662 "TARGET_STRING"
9663 "")
9664
9665 (define_insn ""
9666 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9667 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9668 (use (match_operand:SI 2 "immediate_operand" "i"))
9669 (use (match_operand:SI 3 "immediate_operand" "i"))
9670 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9671 (clobber (reg:SI 6))
9672 (clobber (reg:SI 7))
9673 (clobber (reg:SI 8))
9674 (clobber (reg:SI 9))
9675 (clobber (reg:SI 10))
9676 (clobber (match_scratch:SI 5 "=q"))]
9677 "TARGET_STRING && TARGET_POWER
9678 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9679 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9680 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9681 && REGNO (operands[4]) == 5"
9682 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9683 [(set_attr "type" "store_ux")
9684 (set_attr "length" "8")])
9685
9686 (define_insn ""
9687 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9688 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9689 (use (match_operand:SI 2 "immediate_operand" "i"))
9690 (use (match_operand:SI 3 "immediate_operand" "i"))
9691 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9692 (clobber (reg:SI 6))
9693 (clobber (reg:SI 7))
9694 (clobber (reg:SI 8))
9695 (clobber (reg:SI 9))
9696 (clobber (reg:SI 10))
9697 (clobber (match_scratch:SI 5 "=X"))]
9698 "TARGET_STRING && ! TARGET_POWER
9699 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9700 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9701 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9702 && REGNO (operands[4]) == 5"
9703 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9704 [(set_attr "type" "store_ux")
9705 (set_attr "length" "8")])
9706
9707 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9708 ;; problems with TImode.
9709 ;; rD/rS = r5 is preferred, efficient form.
9710 (define_expand "movmemsi_4reg"
9711 [(parallel [(set (match_operand 0 "" "")
9712 (match_operand 1 "" ""))
9713 (use (match_operand 2 "" ""))
9714 (use (match_operand 3 "" ""))
9715 (clobber (reg:SI 5))
9716 (clobber (reg:SI 6))
9717 (clobber (reg:SI 7))
9718 (clobber (reg:SI 8))
9719 (clobber (match_scratch:SI 4 ""))])]
9720 "TARGET_STRING"
9721 "")
9722
9723 (define_insn ""
9724 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9725 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9726 (use (match_operand:SI 2 "immediate_operand" "i"))
9727 (use (match_operand:SI 3 "immediate_operand" "i"))
9728 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9729 (clobber (reg:SI 6))
9730 (clobber (reg:SI 7))
9731 (clobber (reg:SI 8))
9732 (clobber (match_scratch:SI 5 "=q"))]
9733 "TARGET_STRING && TARGET_POWER
9734 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9735 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9736 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9737 && REGNO (operands[4]) == 5"
9738 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9739 [(set_attr "type" "store_ux")
9740 (set_attr "length" "8")])
9741
9742 (define_insn ""
9743 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9744 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9745 (use (match_operand:SI 2 "immediate_operand" "i"))
9746 (use (match_operand:SI 3 "immediate_operand" "i"))
9747 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9748 (clobber (reg:SI 6))
9749 (clobber (reg:SI 7))
9750 (clobber (reg:SI 8))
9751 (clobber (match_scratch:SI 5 "=X"))]
9752 "TARGET_STRING && ! TARGET_POWER
9753 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9754 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9755 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9756 && REGNO (operands[4]) == 5"
9757 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9758 [(set_attr "type" "store_ux")
9759 (set_attr "length" "8")])
9760
9761 ;; Move up to 8 bytes at a time.
9762 (define_expand "movmemsi_2reg"
9763 [(parallel [(set (match_operand 0 "" "")
9764 (match_operand 1 "" ""))
9765 (use (match_operand 2 "" ""))
9766 (use (match_operand 3 "" ""))
9767 (clobber (match_scratch:DI 4 ""))
9768 (clobber (match_scratch:SI 5 ""))])]
9769 "TARGET_STRING && ! TARGET_POWERPC64"
9770 "")
9771
9772 (define_insn ""
9773 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9774 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9775 (use (match_operand:SI 2 "immediate_operand" "i"))
9776 (use (match_operand:SI 3 "immediate_operand" "i"))
9777 (clobber (match_scratch:DI 4 "=&r"))
9778 (clobber (match_scratch:SI 5 "=q"))]
9779 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9780 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9781 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9782 [(set_attr "type" "store_ux")
9783 (set_attr "length" "8")])
9784
9785 (define_insn ""
9786 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9787 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9788 (use (match_operand:SI 2 "immediate_operand" "i"))
9789 (use (match_operand:SI 3 "immediate_operand" "i"))
9790 (clobber (match_scratch:DI 4 "=&r"))
9791 (clobber (match_scratch:SI 5 "=X"))]
9792 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9793 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9794 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9795 [(set_attr "type" "store_ux")
9796 (set_attr "length" "8")])
9797
9798 ;; Move up to 4 bytes at a time.
9799 (define_expand "movmemsi_1reg"
9800 [(parallel [(set (match_operand 0 "" "")
9801 (match_operand 1 "" ""))
9802 (use (match_operand 2 "" ""))
9803 (use (match_operand 3 "" ""))
9804 (clobber (match_scratch:SI 4 ""))
9805 (clobber (match_scratch:SI 5 ""))])]
9806 "TARGET_STRING"
9807 "")
9808
9809 (define_insn ""
9810 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9811 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9812 (use (match_operand:SI 2 "immediate_operand" "i"))
9813 (use (match_operand:SI 3 "immediate_operand" "i"))
9814 (clobber (match_scratch:SI 4 "=&r"))
9815 (clobber (match_scratch:SI 5 "=q"))]
9816 "TARGET_STRING && TARGET_POWER
9817 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9818 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9819 [(set_attr "type" "store_ux")
9820 (set_attr "length" "8")])
9821
9822 (define_insn ""
9823 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9824 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9825 (use (match_operand:SI 2 "immediate_operand" "i"))
9826 (use (match_operand:SI 3 "immediate_operand" "i"))
9827 (clobber (match_scratch:SI 4 "=&r"))
9828 (clobber (match_scratch:SI 5 "=X"))]
9829 "TARGET_STRING && ! TARGET_POWER
9830 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9831 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9832 [(set_attr "type" "store_ux")
9833 (set_attr "length" "8")])
9834 \f
9835 ;; Define insns that do load or store with update. Some of these we can
9836 ;; get by using pre-decrement or pre-increment, but the hardware can also
9837 ;; do cases where the increment is not the size of the object.
9838 ;;
9839 ;; In all these cases, we use operands 0 and 1 for the register being
9840 ;; incremented because those are the operands that local-alloc will
9841 ;; tie and these are the pair most likely to be tieable (and the ones
9842 ;; that will benefit the most).
9843
9844 (define_insn "*movdi_update1"
9845 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9846 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9847 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9848 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9849 (plus:DI (match_dup 1) (match_dup 2)))]
9850 "TARGET_POWERPC64 && TARGET_UPDATE"
9851 "@
9852 ldux %3,%0,%2
9853 ldu %3,%2(%0)"
9854 [(set_attr "type" "load_ux,load_u")])
9855
9856 (define_insn "movdi_<mode>_update"
9857 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9858 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9859 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9860 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9861 (plus:P (match_dup 1) (match_dup 2)))]
9862 "TARGET_POWERPC64 && TARGET_UPDATE"
9863 "@
9864 stdux %3,%0,%2
9865 stdu %3,%2(%0)"
9866 [(set_attr "type" "store_ux,store_u")])
9867
9868 (define_insn "*movsi_update1"
9869 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9870 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9871 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9872 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9873 (plus:SI (match_dup 1) (match_dup 2)))]
9874 "TARGET_UPDATE"
9875 "@
9876 {lux|lwzux} %3,%0,%2
9877 {lu|lwzu} %3,%2(%0)"
9878 [(set_attr "type" "load_ux,load_u")])
9879
9880 (define_insn "*movsi_update2"
9881 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9882 (sign_extend:DI
9883 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9884 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9885 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9886 (plus:DI (match_dup 1) (match_dup 2)))]
9887 "TARGET_POWERPC64"
9888 "lwaux %3,%0,%2"
9889 [(set_attr "type" "load_ext_ux")])
9890
9891 (define_insn "movsi_update"
9892 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9893 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9894 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9895 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9896 (plus:SI (match_dup 1) (match_dup 2)))]
9897 "TARGET_UPDATE"
9898 "@
9899 {stux|stwux} %3,%0,%2
9900 {stu|stwu} %3,%2(%0)"
9901 [(set_attr "type" "store_ux,store_u")])
9902
9903 (define_insn "*movhi_update1"
9904 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9905 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9906 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9907 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9908 (plus:SI (match_dup 1) (match_dup 2)))]
9909 "TARGET_UPDATE"
9910 "@
9911 lhzux %3,%0,%2
9912 lhzu %3,%2(%0)"
9913 [(set_attr "type" "load_ux,load_u")])
9914
9915 (define_insn "*movhi_update2"
9916 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9917 (zero_extend:SI
9918 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9919 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9920 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9921 (plus:SI (match_dup 1) (match_dup 2)))]
9922 "TARGET_UPDATE"
9923 "@
9924 lhzux %3,%0,%2
9925 lhzu %3,%2(%0)"
9926 [(set_attr "type" "load_ux,load_u")])
9927
9928 (define_insn "*movhi_update3"
9929 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9930 (sign_extend:SI
9931 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9932 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9933 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9934 (plus:SI (match_dup 1) (match_dup 2)))]
9935 "TARGET_UPDATE"
9936 "@
9937 lhaux %3,%0,%2
9938 lhau %3,%2(%0)"
9939 [(set_attr "type" "load_ext_ux,load_ext_u")])
9940
9941 (define_insn "*movhi_update4"
9942 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9943 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9944 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9945 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9946 (plus:SI (match_dup 1) (match_dup 2)))]
9947 "TARGET_UPDATE"
9948 "@
9949 sthux %3,%0,%2
9950 sthu %3,%2(%0)"
9951 [(set_attr "type" "store_ux,store_u")])
9952
9953 (define_insn "*movqi_update1"
9954 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9955 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9956 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9957 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9958 (plus:SI (match_dup 1) (match_dup 2)))]
9959 "TARGET_UPDATE"
9960 "@
9961 lbzux %3,%0,%2
9962 lbzu %3,%2(%0)"
9963 [(set_attr "type" "load_ux,load_u")])
9964
9965 (define_insn "*movqi_update2"
9966 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9967 (zero_extend:SI
9968 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9969 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9970 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9971 (plus:SI (match_dup 1) (match_dup 2)))]
9972 "TARGET_UPDATE"
9973 "@
9974 lbzux %3,%0,%2
9975 lbzu %3,%2(%0)"
9976 [(set_attr "type" "load_ux,load_u")])
9977
9978 (define_insn "*movqi_update3"
9979 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9980 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9981 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9982 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9983 (plus:SI (match_dup 1) (match_dup 2)))]
9984 "TARGET_UPDATE"
9985 "@
9986 stbux %3,%0,%2
9987 stbu %3,%2(%0)"
9988 [(set_attr "type" "store_ux,store_u")])
9989
9990 (define_insn "*movsf_update1"
9991 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9992 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9993 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9994 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9995 (plus:SI (match_dup 1) (match_dup 2)))]
9996 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9997 "@
9998 lfsux %3,%0,%2
9999 lfsu %3,%2(%0)"
10000 [(set_attr "type" "fpload_ux,fpload_u")])
10001
10002 (define_insn "*movsf_update2"
10003 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10004 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10005 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10006 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10007 (plus:SI (match_dup 1) (match_dup 2)))]
10008 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
10009 "@
10010 stfsux %3,%0,%2
10011 stfsu %3,%2(%0)"
10012 [(set_attr "type" "fpstore_ux,fpstore_u")])
10013
10014 (define_insn "*movsf_update3"
10015 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10016 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10017 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10018 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10019 (plus:SI (match_dup 1) (match_dup 2)))]
10020 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
10021 "@
10022 {lux|lwzux} %3,%0,%2
10023 {lu|lwzu} %3,%2(%0)"
10024 [(set_attr "type" "load_ux,load_u")])
10025
10026 (define_insn "*movsf_update4"
10027 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10028 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10029 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10030 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10031 (plus:SI (match_dup 1) (match_dup 2)))]
10032 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
10033 "@
10034 {stux|stwux} %3,%0,%2
10035 {stu|stwu} %3,%2(%0)"
10036 [(set_attr "type" "store_ux,store_u")])
10037
10038 (define_insn "*movdf_update1"
10039 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
10040 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10041 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10042 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10043 (plus:SI (match_dup 1) (match_dup 2)))]
10044 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
10045 "@
10046 lfdux %3,%0,%2
10047 lfdu %3,%2(%0)"
10048 [(set_attr "type" "fpload_ux,fpload_u")])
10049
10050 (define_insn "*movdf_update2"
10051 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10052 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10053 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
10054 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10055 (plus:SI (match_dup 1) (match_dup 2)))]
10056 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
10057 "@
10058 stfdux %3,%0,%2
10059 stfdu %3,%2(%0)"
10060 [(set_attr "type" "fpstore_ux,fpstore_u")])
10061
10062 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
10063
10064 (define_insn "*lfq_power2"
10065 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
10066 (match_operand:V2DF 1 "memory_operand" ""))]
10067 "TARGET_POWER2
10068 && TARGET_HARD_FLOAT && TARGET_FPRS"
10069 "lfq%U1%X1 %0,%1")
10070
10071 (define_peephole2
10072 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10073 (match_operand:DF 1 "memory_operand" ""))
10074 (set (match_operand:DF 2 "gpc_reg_operand" "")
10075 (match_operand:DF 3 "memory_operand" ""))]
10076 "TARGET_POWER2
10077 && TARGET_HARD_FLOAT && TARGET_FPRS
10078 && registers_ok_for_quad_peep (operands[0], operands[2])
10079 && mems_ok_for_quad_peep (operands[1], operands[3])"
10080 [(set (match_dup 0)
10081 (match_dup 1))]
10082 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
10083 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
10084
10085 (define_insn "*stfq_power2"
10086 [(set (match_operand:V2DF 0 "memory_operand" "")
10087 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
10088 "TARGET_POWER2
10089 && TARGET_HARD_FLOAT && TARGET_FPRS"
10090 "stfq%U0%X0 %1,%0")
10091
10092
10093 (define_peephole2
10094 [(set (match_operand:DF 0 "memory_operand" "")
10095 (match_operand:DF 1 "gpc_reg_operand" ""))
10096 (set (match_operand:DF 2 "memory_operand" "")
10097 (match_operand:DF 3 "gpc_reg_operand" ""))]
10098 "TARGET_POWER2
10099 && TARGET_HARD_FLOAT && TARGET_FPRS
10100 && registers_ok_for_quad_peep (operands[1], operands[3])
10101 && mems_ok_for_quad_peep (operands[0], operands[2])"
10102 [(set (match_dup 0)
10103 (match_dup 1))]
10104 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
10105 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
10106
10107 ;; After inserting conditional returns we can sometimes have
10108 ;; unnecessary register moves. Unfortunately we cannot have a
10109 ;; modeless peephole here, because some single SImode sets have early
10110 ;; clobber outputs. Although those sets expand to multi-ppc-insn
10111 ;; sequences, using get_attr_length here will smash the operands
10112 ;; array. Neither is there an early_cobbler_p predicate.
10113 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
10114 (define_peephole2
10115 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10116 (match_operand:DF 1 "any_operand" ""))
10117 (set (match_operand:DF 2 "gpc_reg_operand" "")
10118 (match_dup 0))]
10119 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10120 && peep2_reg_dead_p (2, operands[0])"
10121 [(set (match_dup 2) (match_dup 1))])
10122
10123 (define_peephole2
10124 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10125 (match_operand:SF 1 "any_operand" ""))
10126 (set (match_operand:SF 2 "gpc_reg_operand" "")
10127 (match_dup 0))]
10128 "peep2_reg_dead_p (2, operands[0])"
10129 [(set (match_dup 2) (match_dup 1))])
10130
10131 \f
10132 ;; TLS support.
10133
10134 ;; "b" output constraint here and on tls_ld to support tls linker optimization.
10135 (define_insn "tls_gd_32"
10136 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10137 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10138 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10139 UNSPEC_TLSGD))]
10140 "HAVE_AS_TLS && !TARGET_64BIT"
10141 "addi %0,%1,%2@got@tlsgd")
10142
10143 (define_insn "tls_gd_64"
10144 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10145 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10146 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10147 UNSPEC_TLSGD))]
10148 "HAVE_AS_TLS && TARGET_64BIT"
10149 "addi %0,%1,%2@got@tlsgd")
10150
10151 (define_insn "tls_ld_32"
10152 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10153 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
10154 UNSPEC_TLSLD))]
10155 "HAVE_AS_TLS && !TARGET_64BIT"
10156 "addi %0,%1,%&@got@tlsld")
10157
10158 (define_insn "tls_ld_64"
10159 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10160 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
10161 UNSPEC_TLSLD))]
10162 "HAVE_AS_TLS && TARGET_64BIT"
10163 "addi %0,%1,%&@got@tlsld")
10164
10165 (define_insn "tls_dtprel_32"
10166 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10167 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10168 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10169 UNSPEC_TLSDTPREL))]
10170 "HAVE_AS_TLS && !TARGET_64BIT"
10171 "addi %0,%1,%2@dtprel")
10172
10173 (define_insn "tls_dtprel_64"
10174 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10175 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10176 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10177 UNSPEC_TLSDTPREL))]
10178 "HAVE_AS_TLS && TARGET_64BIT"
10179 "addi %0,%1,%2@dtprel")
10180
10181 (define_insn "tls_dtprel_ha_32"
10182 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10183 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10184 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10185 UNSPEC_TLSDTPRELHA))]
10186 "HAVE_AS_TLS && !TARGET_64BIT"
10187 "addis %0,%1,%2@dtprel@ha")
10188
10189 (define_insn "tls_dtprel_ha_64"
10190 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10191 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10192 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10193 UNSPEC_TLSDTPRELHA))]
10194 "HAVE_AS_TLS && TARGET_64BIT"
10195 "addis %0,%1,%2@dtprel@ha")
10196
10197 (define_insn "tls_dtprel_lo_32"
10198 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10199 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10200 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10201 UNSPEC_TLSDTPRELLO))]
10202 "HAVE_AS_TLS && !TARGET_64BIT"
10203 "addi %0,%1,%2@dtprel@l")
10204
10205 (define_insn "tls_dtprel_lo_64"
10206 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10207 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10208 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10209 UNSPEC_TLSDTPRELLO))]
10210 "HAVE_AS_TLS && TARGET_64BIT"
10211 "addi %0,%1,%2@dtprel@l")
10212
10213 (define_insn "tls_got_dtprel_32"
10214 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10215 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10216 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10217 UNSPEC_TLSGOTDTPREL))]
10218 "HAVE_AS_TLS && !TARGET_64BIT"
10219 "lwz %0,%2@got@dtprel(%1)")
10220
10221 (define_insn "tls_got_dtprel_64"
10222 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10223 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10224 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10225 UNSPEC_TLSGOTDTPREL))]
10226 "HAVE_AS_TLS && TARGET_64BIT"
10227 "ld %0,%2@got@dtprel(%1)")
10228
10229 (define_insn "tls_tprel_32"
10230 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10231 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10232 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10233 UNSPEC_TLSTPREL))]
10234 "HAVE_AS_TLS && !TARGET_64BIT"
10235 "addi %0,%1,%2@tprel")
10236
10237 (define_insn "tls_tprel_64"
10238 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10239 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10240 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10241 UNSPEC_TLSTPREL))]
10242 "HAVE_AS_TLS && TARGET_64BIT"
10243 "addi %0,%1,%2@tprel")
10244
10245 (define_insn "tls_tprel_ha_32"
10246 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10247 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10248 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10249 UNSPEC_TLSTPRELHA))]
10250 "HAVE_AS_TLS && !TARGET_64BIT"
10251 "addis %0,%1,%2@tprel@ha")
10252
10253 (define_insn "tls_tprel_ha_64"
10254 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10255 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10256 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10257 UNSPEC_TLSTPRELHA))]
10258 "HAVE_AS_TLS && TARGET_64BIT"
10259 "addis %0,%1,%2@tprel@ha")
10260
10261 (define_insn "tls_tprel_lo_32"
10262 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10263 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10264 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10265 UNSPEC_TLSTPRELLO))]
10266 "HAVE_AS_TLS && !TARGET_64BIT"
10267 "addi %0,%1,%2@tprel@l")
10268
10269 (define_insn "tls_tprel_lo_64"
10270 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10271 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10272 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10273 UNSPEC_TLSTPRELLO))]
10274 "HAVE_AS_TLS && TARGET_64BIT"
10275 "addi %0,%1,%2@tprel@l")
10276
10277 ;; "b" output constraint here and on tls_tls input to support linker tls
10278 ;; optimization. The linker may edit the instructions emitted by a
10279 ;; tls_got_tprel/tls_tls pair to addis,addi.
10280 (define_insn "tls_got_tprel_32"
10281 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10282 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10283 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10284 UNSPEC_TLSGOTTPREL))]
10285 "HAVE_AS_TLS && !TARGET_64BIT"
10286 "lwz %0,%2@got@tprel(%1)")
10287
10288 (define_insn "tls_got_tprel_64"
10289 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10290 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10291 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10292 UNSPEC_TLSGOTTPREL))]
10293 "HAVE_AS_TLS && TARGET_64BIT"
10294 "ld %0,%2@got@tprel(%1)")
10295
10296 (define_insn "tls_tls_32"
10297 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10298 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10299 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10300 UNSPEC_TLSTLS))]
10301 "HAVE_AS_TLS && !TARGET_64BIT"
10302 "add %0,%1,%2@tls")
10303
10304 (define_insn "tls_tls_64"
10305 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10306 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10307 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10308 UNSPEC_TLSTLS))]
10309 "HAVE_AS_TLS && TARGET_64BIT"
10310 "add %0,%1,%2@tls")
10311 \f
10312 ;; Next come insns related to the calling sequence.
10313 ;;
10314 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
10315 ;; We move the back-chain and decrement the stack pointer.
10316
10317 (define_expand "allocate_stack"
10318 [(set (match_operand 0 "gpc_reg_operand" "")
10319 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10320 (set (reg 1)
10321 (minus (reg 1) (match_dup 1)))]
10322 ""
10323 "
10324 { rtx chain = gen_reg_rtx (Pmode);
10325 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
10326 rtx neg_op0;
10327
10328 emit_move_insn (chain, stack_bot);
10329
10330 /* Check stack bounds if necessary. */
10331 if (current_function_limit_stack)
10332 {
10333 rtx available;
10334 available = expand_binop (Pmode, sub_optab,
10335 stack_pointer_rtx, stack_limit_rtx,
10336 NULL_RTX, 1, OPTAB_WIDEN);
10337 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10338 }
10339
10340 if (GET_CODE (operands[1]) != CONST_INT
10341 || INTVAL (operands[1]) < -32767
10342 || INTVAL (operands[1]) > 32768)
10343 {
10344 neg_op0 = gen_reg_rtx (Pmode);
10345 if (TARGET_32BIT)
10346 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10347 else
10348 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10349 }
10350 else
10351 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10352
10353 if (TARGET_UPDATE)
10354 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
10355 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
10356
10357 else
10358 {
10359 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
10360 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
10361 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
10362 }
10363
10364 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10365 DONE;
10366 }")
10367
10368 ;; These patterns say how to save and restore the stack pointer. We need not
10369 ;; save the stack pointer at function level since we are careful to
10370 ;; preserve the backchain. At block level, we have to restore the backchain
10371 ;; when we restore the stack pointer.
10372 ;;
10373 ;; For nonlocal gotos, we must save both the stack pointer and its
10374 ;; backchain and restore both. Note that in the nonlocal case, the
10375 ;; save area is a memory location.
10376
10377 (define_expand "save_stack_function"
10378 [(match_operand 0 "any_operand" "")
10379 (match_operand 1 "any_operand" "")]
10380 ""
10381 "DONE;")
10382
10383 (define_expand "restore_stack_function"
10384 [(match_operand 0 "any_operand" "")
10385 (match_operand 1 "any_operand" "")]
10386 ""
10387 "DONE;")
10388
10389 ;; Adjust stack pointer (op0) to a new value (op1).
10390 ;; First copy old stack backchain to new location, and ensure that the
10391 ;; scheduler won't reorder the sp assignment before the backchain write.
10392 (define_expand "restore_stack_block"
10393 [(set (match_dup 2) (match_dup 3))
10394 (set (match_dup 4) (match_dup 2))
10395 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
10396 (set (match_operand 0 "register_operand" "")
10397 (match_operand 1 "register_operand" ""))]
10398 ""
10399 "
10400 {
10401 operands[2] = gen_reg_rtx (Pmode);
10402 operands[3] = gen_frame_mem (Pmode, operands[0]);
10403 operands[4] = gen_frame_mem (Pmode, operands[1]);
10404 operands[5] = gen_frame_mem (BLKmode, operands[0]);
10405 }")
10406
10407 (define_expand "save_stack_nonlocal"
10408 [(set (match_dup 3) (match_dup 4))
10409 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10410 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
10411 ""
10412 "
10413 {
10414 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10415
10416 /* Copy the backchain to the first word, sp to the second. */
10417 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10418 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10419 operands[3] = gen_reg_rtx (Pmode);
10420 operands[4] = gen_frame_mem (Pmode, operands[1]);
10421 }")
10422
10423 (define_expand "restore_stack_nonlocal"
10424 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10425 (set (match_dup 3) (match_dup 4))
10426 (set (match_dup 5) (match_dup 2))
10427 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
10428 (set (match_operand 0 "register_operand" "") (match_dup 3))]
10429 ""
10430 "
10431 {
10432 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10433
10434 /* Restore the backchain from the first word, sp from the second. */
10435 operands[2] = gen_reg_rtx (Pmode);
10436 operands[3] = gen_reg_rtx (Pmode);
10437 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10438 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10439 operands[5] = gen_frame_mem (Pmode, operands[3]);
10440 operands[6] = gen_frame_mem (BLKmode, operands[0]);
10441 }")
10442 \f
10443 ;; TOC register handling.
10444
10445 ;; Code to initialize the TOC register...
10446
10447 (define_insn "load_toc_aix_si"
10448 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10449 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10450 (use (reg:SI 2))])]
10451 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10452 "*
10453 {
10454 char buf[30];
10455 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10456 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10457 operands[2] = gen_rtx_REG (Pmode, 2);
10458 return \"{l|lwz} %0,%1(%2)\";
10459 }"
10460 [(set_attr "type" "load")])
10461
10462 (define_insn "load_toc_aix_di"
10463 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10464 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10465 (use (reg:DI 2))])]
10466 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10467 "*
10468 {
10469 char buf[30];
10470 #ifdef TARGET_RELOCATABLE
10471 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10472 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10473 #else
10474 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10475 #endif
10476 if (TARGET_ELF)
10477 strcat (buf, \"@toc\");
10478 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10479 operands[2] = gen_rtx_REG (Pmode, 2);
10480 return \"ld %0,%1(%2)\";
10481 }"
10482 [(set_attr "type" "load")])
10483
10484 (define_insn "load_toc_v4_pic_si"
10485 [(set (reg:SI 65)
10486 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10487 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10488 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10489 [(set_attr "type" "branch")
10490 (set_attr "length" "4")])
10491
10492 (define_insn "load_toc_v4_PIC_1"
10493 [(set (reg:SI 65)
10494 (match_operand:SI 0 "immediate_operand" "s"))
10495 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10496 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
10497 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10498 "bcl 20,31,%0\\n%0:"
10499 [(set_attr "type" "branch")
10500 (set_attr "length" "4")])
10501
10502 (define_insn "load_toc_v4_PIC_1b"
10503 [(set (reg:SI 65)
10504 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")]
10505 UNSPEC_TOCPTR))]
10506 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10507 "bcl 20,31,$+8\\n\\t.long %0-$"
10508 [(set_attr "type" "branch")
10509 (set_attr "length" "8")])
10510
10511 (define_insn "load_toc_v4_PIC_2"
10512 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10513 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10514 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10515 (match_operand:SI 3 "immediate_operand" "s")))))]
10516 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10517 "{l|lwz} %0,%2-%3(%1)"
10518 [(set_attr "type" "load")])
10519
10520 (define_insn "load_toc_v4_PIC_3b"
10521 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10522 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10523 (high:SI
10524 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10525 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10526 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10527 "{cau|addis} %0,%1,%2-%3@ha")
10528
10529 (define_insn "load_toc_v4_PIC_3c"
10530 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10531 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10532 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10533 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10534 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10535 "{cal|addi} %0,%1,%2-%3@l")
10536
10537 ;; If the TOC is shared over a translation unit, as happens with all
10538 ;; the kinds of PIC that we support, we need to restore the TOC
10539 ;; pointer only when jumping over units of translation.
10540 ;; On Darwin, we need to reload the picbase.
10541
10542 (define_expand "builtin_setjmp_receiver"
10543 [(use (label_ref (match_operand 0 "" "")))]
10544 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10545 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10546 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10547 "
10548 {
10549 #if TARGET_MACHO
10550 if (DEFAULT_ABI == ABI_DARWIN)
10551 {
10552 const char *picbase = machopic_function_base_name ();
10553 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
10554 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10555 rtx tmplabrtx;
10556 char tmplab[20];
10557
10558 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10559 CODE_LABEL_NUMBER (operands[0]));
10560 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10561
10562 emit_insn (gen_load_macho_picbase (tmplabrtx));
10563 emit_move_insn (picreg, gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
10564 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10565 }
10566 else
10567 #endif
10568 rs6000_emit_load_toc_table (FALSE);
10569 DONE;
10570 }")
10571
10572 ;; Elf specific ways of loading addresses for non-PIC code.
10573 ;; The output of this could be r0, but we make a very strong
10574 ;; preference for a base register because it will usually
10575 ;; be needed there.
10576 (define_insn "elf_high"
10577 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10578 (high:SI (match_operand 1 "" "")))]
10579 "TARGET_ELF && ! TARGET_64BIT"
10580 "{liu|lis} %0,%1@ha")
10581
10582 (define_insn "elf_low"
10583 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10584 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10585 (match_operand 2 "" "")))]
10586 "TARGET_ELF && ! TARGET_64BIT"
10587 "@
10588 {cal|la} %0,%2@l(%1)
10589 {ai|addic} %0,%1,%K2")
10590 \f
10591 ;; A function pointer under AIX is a pointer to a data area whose first word
10592 ;; contains the actual address of the function, whose second word contains a
10593 ;; pointer to its TOC, and whose third word contains a value to place in the
10594 ;; static chain register (r11). Note that if we load the static chain, our
10595 ;; "trampoline" need not have any executable code.
10596
10597 (define_expand "call_indirect_aix32"
10598 [(set (match_dup 2)
10599 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10600 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10601 (reg:SI 2))
10602 (set (reg:SI 2)
10603 (mem:SI (plus:SI (match_dup 0)
10604 (const_int 4))))
10605 (set (reg:SI 11)
10606 (mem:SI (plus:SI (match_dup 0)
10607 (const_int 8))))
10608 (parallel [(call (mem:SI (match_dup 2))
10609 (match_operand 1 "" ""))
10610 (use (reg:SI 2))
10611 (use (reg:SI 11))
10612 (set (reg:SI 2)
10613 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10614 (clobber (reg:SI 65))])]
10615 "TARGET_32BIT"
10616 "
10617 { operands[2] = gen_reg_rtx (SImode); }")
10618
10619 (define_expand "call_indirect_aix64"
10620 [(set (match_dup 2)
10621 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10622 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10623 (reg:DI 2))
10624 (set (reg:DI 2)
10625 (mem:DI (plus:DI (match_dup 0)
10626 (const_int 8))))
10627 (set (reg:DI 11)
10628 (mem:DI (plus:DI (match_dup 0)
10629 (const_int 16))))
10630 (parallel [(call (mem:SI (match_dup 2))
10631 (match_operand 1 "" ""))
10632 (use (reg:DI 2))
10633 (use (reg:DI 11))
10634 (set (reg:DI 2)
10635 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10636 (clobber (reg:SI 65))])]
10637 "TARGET_64BIT"
10638 "
10639 { operands[2] = gen_reg_rtx (DImode); }")
10640
10641 (define_expand "call_value_indirect_aix32"
10642 [(set (match_dup 3)
10643 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10644 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10645 (reg:SI 2))
10646 (set (reg:SI 2)
10647 (mem:SI (plus:SI (match_dup 1)
10648 (const_int 4))))
10649 (set (reg:SI 11)
10650 (mem:SI (plus:SI (match_dup 1)
10651 (const_int 8))))
10652 (parallel [(set (match_operand 0 "" "")
10653 (call (mem:SI (match_dup 3))
10654 (match_operand 2 "" "")))
10655 (use (reg:SI 2))
10656 (use (reg:SI 11))
10657 (set (reg:SI 2)
10658 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10659 (clobber (reg:SI 65))])]
10660 "TARGET_32BIT"
10661 "
10662 { operands[3] = gen_reg_rtx (SImode); }")
10663
10664 (define_expand "call_value_indirect_aix64"
10665 [(set (match_dup 3)
10666 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10667 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10668 (reg:DI 2))
10669 (set (reg:DI 2)
10670 (mem:DI (plus:DI (match_dup 1)
10671 (const_int 8))))
10672 (set (reg:DI 11)
10673 (mem:DI (plus:DI (match_dup 1)
10674 (const_int 16))))
10675 (parallel [(set (match_operand 0 "" "")
10676 (call (mem:SI (match_dup 3))
10677 (match_operand 2 "" "")))
10678 (use (reg:DI 2))
10679 (use (reg:DI 11))
10680 (set (reg:DI 2)
10681 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10682 (clobber (reg:SI 65))])]
10683 "TARGET_64BIT"
10684 "
10685 { operands[3] = gen_reg_rtx (DImode); }")
10686
10687 ;; Now the definitions for the call and call_value insns
10688 (define_expand "call"
10689 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10690 (match_operand 1 "" ""))
10691 (use (match_operand 2 "" ""))
10692 (clobber (reg:SI 65))])]
10693 ""
10694 "
10695 {
10696 #if TARGET_MACHO
10697 if (MACHOPIC_INDIRECT)
10698 operands[0] = machopic_indirect_call_target (operands[0]);
10699 #endif
10700
10701 gcc_assert (GET_CODE (operands[0]) == MEM);
10702 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10703
10704 operands[0] = XEXP (operands[0], 0);
10705
10706 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10707 && flag_pic
10708 && GET_CODE (operands[0]) == SYMBOL_REF
10709 && !SYMBOL_REF_LOCAL_P (operands[0]))
10710 {
10711 rtx call;
10712 rtvec tmp;
10713
10714 tmp = gen_rtvec (3,
10715 gen_rtx_CALL (VOIDmode,
10716 gen_rtx_MEM (SImode, operands[0]),
10717 operands[1]),
10718 gen_rtx_USE (VOIDmode, operands[2]),
10719 gen_rtx_CLOBBER (VOIDmode,
10720 gen_rtx_REG (Pmode,
10721 LINK_REGISTER_REGNUM)));
10722 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10723 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10724 DONE;
10725 }
10726
10727 if (GET_CODE (operands[0]) != SYMBOL_REF
10728 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10729 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10730 {
10731 if (INTVAL (operands[2]) & CALL_LONG)
10732 operands[0] = rs6000_longcall_ref (operands[0]);
10733
10734 switch (DEFAULT_ABI)
10735 {
10736 case ABI_V4:
10737 case ABI_DARWIN:
10738 operands[0] = force_reg (Pmode, operands[0]);
10739 break;
10740
10741 case ABI_AIX:
10742 /* AIX function pointers are really pointers to a three word
10743 area. */
10744 emit_call_insn (TARGET_32BIT
10745 ? gen_call_indirect_aix32 (force_reg (SImode,
10746 operands[0]),
10747 operands[1])
10748 : gen_call_indirect_aix64 (force_reg (DImode,
10749 operands[0]),
10750 operands[1]));
10751 DONE;
10752
10753 default:
10754 gcc_unreachable ();
10755 }
10756 }
10757 }")
10758
10759 (define_expand "call_value"
10760 [(parallel [(set (match_operand 0 "" "")
10761 (call (mem:SI (match_operand 1 "address_operand" ""))
10762 (match_operand 2 "" "")))
10763 (use (match_operand 3 "" ""))
10764 (clobber (reg:SI 65))])]
10765 ""
10766 "
10767 {
10768 #if TARGET_MACHO
10769 if (MACHOPIC_INDIRECT)
10770 operands[1] = machopic_indirect_call_target (operands[1]);
10771 #endif
10772
10773 gcc_assert (GET_CODE (operands[1]) == MEM);
10774 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10775
10776 operands[1] = XEXP (operands[1], 0);
10777
10778 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10779 && flag_pic
10780 && GET_CODE (operands[1]) == SYMBOL_REF
10781 && !SYMBOL_REF_LOCAL_P (operands[1]))
10782 {
10783 rtx call;
10784 rtvec tmp;
10785
10786 tmp = gen_rtvec (3,
10787 gen_rtx_SET (VOIDmode,
10788 operands[0],
10789 gen_rtx_CALL (VOIDmode,
10790 gen_rtx_MEM (SImode,
10791 operands[1]),
10792 operands[2])),
10793 gen_rtx_USE (VOIDmode, operands[3]),
10794 gen_rtx_CLOBBER (VOIDmode,
10795 gen_rtx_REG (Pmode,
10796 LINK_REGISTER_REGNUM)));
10797 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10798 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10799 DONE;
10800 }
10801
10802 if (GET_CODE (operands[1]) != SYMBOL_REF
10803 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10804 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10805 {
10806 if (INTVAL (operands[3]) & CALL_LONG)
10807 operands[1] = rs6000_longcall_ref (operands[1]);
10808
10809 switch (DEFAULT_ABI)
10810 {
10811 case ABI_V4:
10812 case ABI_DARWIN:
10813 operands[1] = force_reg (Pmode, operands[1]);
10814 break;
10815
10816 case ABI_AIX:
10817 /* AIX function pointers are really pointers to a three word
10818 area. */
10819 emit_call_insn (TARGET_32BIT
10820 ? gen_call_value_indirect_aix32 (operands[0],
10821 force_reg (SImode,
10822 operands[1]),
10823 operands[2])
10824 : gen_call_value_indirect_aix64 (operands[0],
10825 force_reg (DImode,
10826 operands[1]),
10827 operands[2]));
10828 DONE;
10829
10830 default:
10831 gcc_unreachable ();
10832 }
10833 }
10834 }")
10835
10836 ;; Call to function in current module. No TOC pointer reload needed.
10837 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10838 ;; either the function was not prototyped, or it was prototyped as a
10839 ;; variable argument function. It is > 0 if FP registers were passed
10840 ;; and < 0 if they were not.
10841
10842 (define_insn "*call_local32"
10843 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10844 (match_operand 1 "" "g,g"))
10845 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10846 (clobber (reg:SI 65))]
10847 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10848 "*
10849 {
10850 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10851 output_asm_insn (\"crxor 6,6,6\", operands);
10852
10853 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10854 output_asm_insn (\"creqv 6,6,6\", operands);
10855
10856 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10857 }"
10858 [(set_attr "type" "branch")
10859 (set_attr "length" "4,8")])
10860
10861 (define_insn "*call_local64"
10862 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10863 (match_operand 1 "" "g,g"))
10864 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10865 (clobber (reg:SI 65))]
10866 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10867 "*
10868 {
10869 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10870 output_asm_insn (\"crxor 6,6,6\", operands);
10871
10872 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10873 output_asm_insn (\"creqv 6,6,6\", operands);
10874
10875 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10876 }"
10877 [(set_attr "type" "branch")
10878 (set_attr "length" "4,8")])
10879
10880 (define_insn "*call_value_local32"
10881 [(set (match_operand 0 "" "")
10882 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10883 (match_operand 2 "" "g,g")))
10884 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10885 (clobber (reg:SI 65))]
10886 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10887 "*
10888 {
10889 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10890 output_asm_insn (\"crxor 6,6,6\", operands);
10891
10892 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10893 output_asm_insn (\"creqv 6,6,6\", operands);
10894
10895 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10896 }"
10897 [(set_attr "type" "branch")
10898 (set_attr "length" "4,8")])
10899
10900
10901 (define_insn "*call_value_local64"
10902 [(set (match_operand 0 "" "")
10903 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10904 (match_operand 2 "" "g,g")))
10905 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10906 (clobber (reg:SI 65))]
10907 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10908 "*
10909 {
10910 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10911 output_asm_insn (\"crxor 6,6,6\", operands);
10912
10913 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10914 output_asm_insn (\"creqv 6,6,6\", operands);
10915
10916 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10917 }"
10918 [(set_attr "type" "branch")
10919 (set_attr "length" "4,8")])
10920
10921 ;; Call to function which may be in another module. Restore the TOC
10922 ;; pointer (r2) after the call unless this is System V.
10923 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10924 ;; either the function was not prototyped, or it was prototyped as a
10925 ;; variable argument function. It is > 0 if FP registers were passed
10926 ;; and < 0 if they were not.
10927
10928 (define_insn "*call_indirect_nonlocal_aix32"
10929 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
10930 (match_operand 1 "" "g,g"))
10931 (use (reg:SI 2))
10932 (use (reg:SI 11))
10933 (set (reg:SI 2)
10934 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10935 (clobber (reg:SI 65))]
10936 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10937 "b%T0l\;{l|lwz} 2,20(1)"
10938 [(set_attr "type" "jmpreg")
10939 (set_attr "length" "8")])
10940
10941 (define_insn "*call_nonlocal_aix32"
10942 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10943 (match_operand 1 "" "g"))
10944 (use (match_operand:SI 2 "immediate_operand" "O"))
10945 (clobber (reg:SI 65))]
10946 "TARGET_32BIT
10947 && DEFAULT_ABI == ABI_AIX
10948 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10949 "bl %z0\;%."
10950 [(set_attr "type" "branch")
10951 (set_attr "length" "8")])
10952
10953 (define_insn "*call_indirect_nonlocal_aix64"
10954 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
10955 (match_operand 1 "" "g,g"))
10956 (use (reg:DI 2))
10957 (use (reg:DI 11))
10958 (set (reg:DI 2)
10959 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10960 (clobber (reg:SI 65))]
10961 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10962 "b%T0l\;ld 2,40(1)"
10963 [(set_attr "type" "jmpreg")
10964 (set_attr "length" "8")])
10965
10966 (define_insn "*call_nonlocal_aix64"
10967 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10968 (match_operand 1 "" "g"))
10969 (use (match_operand:SI 2 "immediate_operand" "O"))
10970 (clobber (reg:SI 65))]
10971 "TARGET_64BIT
10972 && DEFAULT_ABI == ABI_AIX
10973 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10974 "bl %z0\;%."
10975 [(set_attr "type" "branch")
10976 (set_attr "length" "8")])
10977
10978 (define_insn "*call_value_indirect_nonlocal_aix32"
10979 [(set (match_operand 0 "" "")
10980 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
10981 (match_operand 2 "" "g,g")))
10982 (use (reg:SI 2))
10983 (use (reg:SI 11))
10984 (set (reg:SI 2)
10985 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10986 (clobber (reg:SI 65))]
10987 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10988 "b%T1l\;{l|lwz} 2,20(1)"
10989 [(set_attr "type" "jmpreg")
10990 (set_attr "length" "8")])
10991
10992 (define_insn "*call_value_nonlocal_aix32"
10993 [(set (match_operand 0 "" "")
10994 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10995 (match_operand 2 "" "g")))
10996 (use (match_operand:SI 3 "immediate_operand" "O"))
10997 (clobber (reg:SI 65))]
10998 "TARGET_32BIT
10999 && DEFAULT_ABI == ABI_AIX
11000 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11001 "bl %z1\;%."
11002 [(set_attr "type" "branch")
11003 (set_attr "length" "8")])
11004
11005 (define_insn "*call_value_indirect_nonlocal_aix64"
11006 [(set (match_operand 0 "" "")
11007 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
11008 (match_operand 2 "" "g,g")))
11009 (use (reg:DI 2))
11010 (use (reg:DI 11))
11011 (set (reg:DI 2)
11012 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11013 (clobber (reg:SI 65))]
11014 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11015 "b%T1l\;ld 2,40(1)"
11016 [(set_attr "type" "jmpreg")
11017 (set_attr "length" "8")])
11018
11019 (define_insn "*call_value_nonlocal_aix64"
11020 [(set (match_operand 0 "" "")
11021 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11022 (match_operand 2 "" "g")))
11023 (use (match_operand:SI 3 "immediate_operand" "O"))
11024 (clobber (reg:SI 65))]
11025 "TARGET_64BIT
11026 && DEFAULT_ABI == ABI_AIX
11027 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11028 "bl %z1\;%."
11029 [(set_attr "type" "branch")
11030 (set_attr "length" "8")])
11031
11032 ;; A function pointer under System V is just a normal pointer
11033 ;; operands[0] is the function pointer
11034 ;; operands[1] is the stack size to clean up
11035 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
11036 ;; which indicates how to set cr1
11037
11038 (define_insn "*call_indirect_nonlocal_sysv<mode>"
11039 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
11040 (match_operand 1 "" "g,g,g,g"))
11041 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
11042 (clobber (reg:SI 65))]
11043 "DEFAULT_ABI == ABI_V4
11044 || DEFAULT_ABI == ABI_DARWIN"
11045 {
11046 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11047 output_asm_insn ("crxor 6,6,6", operands);
11048
11049 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11050 output_asm_insn ("creqv 6,6,6", operands);
11051
11052 return "b%T0l";
11053 }
11054 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11055 (set_attr "length" "4,4,8,8")])
11056
11057 (define_insn "*call_nonlocal_sysv<mode>"
11058 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11059 (match_operand 1 "" "g,g"))
11060 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11061 (clobber (reg:SI 65))]
11062 "(DEFAULT_ABI == ABI_DARWIN
11063 || (DEFAULT_ABI == ABI_V4
11064 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
11065 {
11066 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11067 output_asm_insn ("crxor 6,6,6", operands);
11068
11069 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11070 output_asm_insn ("creqv 6,6,6", operands);
11071
11072 #if TARGET_MACHO
11073 return output_call(insn, operands, 0, 2);
11074 #else
11075 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11076 {
11077 if (TARGET_SECURE_PLT && flag_pic == 2)
11078 /* The magic 32768 offset here and in the other sysv call insns
11079 corresponds to the offset of r30 in .got2, as given by LCTOC1.
11080 See sysv4.h:toc_section. */
11081 return "bl %z0+32768@plt";
11082 else
11083 return "bl %z0@plt";
11084 }
11085 else
11086 return "bl %z0";
11087 #endif
11088 }
11089 [(set_attr "type" "branch,branch")
11090 (set_attr "length" "4,8")])
11091
11092 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
11093 [(set (match_operand 0 "" "")
11094 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
11095 (match_operand 2 "" "g,g,g,g")))
11096 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
11097 (clobber (reg:SI 65))]
11098 "DEFAULT_ABI == ABI_V4
11099 || DEFAULT_ABI == ABI_DARWIN"
11100 {
11101 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11102 output_asm_insn ("crxor 6,6,6", operands);
11103
11104 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11105 output_asm_insn ("creqv 6,6,6", operands);
11106
11107 return "b%T1l";
11108 }
11109 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11110 (set_attr "length" "4,4,8,8")])
11111
11112 (define_insn "*call_value_nonlocal_sysv<mode>"
11113 [(set (match_operand 0 "" "")
11114 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11115 (match_operand 2 "" "g,g")))
11116 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11117 (clobber (reg:SI 65))]
11118 "(DEFAULT_ABI == ABI_DARWIN
11119 || (DEFAULT_ABI == ABI_V4
11120 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
11121 {
11122 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11123 output_asm_insn ("crxor 6,6,6", operands);
11124
11125 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11126 output_asm_insn ("creqv 6,6,6", operands);
11127
11128 #if TARGET_MACHO
11129 return output_call(insn, operands, 1, 3);
11130 #else
11131 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11132 {
11133 if (TARGET_SECURE_PLT && flag_pic == 2)
11134 return "bl %z1+32768@plt";
11135 else
11136 return "bl %z1@plt";
11137 }
11138 else
11139 return "bl %z1";
11140 #endif
11141 }
11142 [(set_attr "type" "branch,branch")
11143 (set_attr "length" "4,8")])
11144
11145 ;; Call subroutine returning any type.
11146 (define_expand "untyped_call"
11147 [(parallel [(call (match_operand 0 "" "")
11148 (const_int 0))
11149 (match_operand 1 "" "")
11150 (match_operand 2 "" "")])]
11151 ""
11152 "
11153 {
11154 int i;
11155
11156 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
11157
11158 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11159 {
11160 rtx set = XVECEXP (operands[2], 0, i);
11161 emit_move_insn (SET_DEST (set), SET_SRC (set));
11162 }
11163
11164 /* The optimizer does not know that the call sets the function value
11165 registers we stored in the result block. We avoid problems by
11166 claiming that all hard registers are used and clobbered at this
11167 point. */
11168 emit_insn (gen_blockage ());
11169
11170 DONE;
11171 }")
11172
11173 ;; sibling call patterns
11174 (define_expand "sibcall"
11175 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11176 (match_operand 1 "" ""))
11177 (use (match_operand 2 "" ""))
11178 (use (reg:SI 65))
11179 (return)])]
11180 ""
11181 "
11182 {
11183 #if TARGET_MACHO
11184 if (MACHOPIC_INDIRECT)
11185 operands[0] = machopic_indirect_call_target (operands[0]);
11186 #endif
11187
11188 gcc_assert (GET_CODE (operands[0]) == MEM);
11189 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11190
11191 operands[0] = XEXP (operands[0], 0);
11192 }")
11193
11194 ;; this and similar patterns must be marked as using LR, otherwise
11195 ;; dataflow will try to delete the store into it. This is true
11196 ;; even when the actual reg to jump to is in CTR, when LR was
11197 ;; saved and restored around the PIC-setting BCL.
11198 (define_insn "*sibcall_local32"
11199 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11200 (match_operand 1 "" "g,g"))
11201 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11202 (use (reg:SI 65))
11203 (return)]
11204 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11205 "*
11206 {
11207 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11208 output_asm_insn (\"crxor 6,6,6\", operands);
11209
11210 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11211 output_asm_insn (\"creqv 6,6,6\", operands);
11212
11213 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11214 }"
11215 [(set_attr "type" "branch")
11216 (set_attr "length" "4,8")])
11217
11218 (define_insn "*sibcall_local64"
11219 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11220 (match_operand 1 "" "g,g"))
11221 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11222 (use (reg:SI 65))
11223 (return)]
11224 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11225 "*
11226 {
11227 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11228 output_asm_insn (\"crxor 6,6,6\", operands);
11229
11230 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11231 output_asm_insn (\"creqv 6,6,6\", operands);
11232
11233 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11234 }"
11235 [(set_attr "type" "branch")
11236 (set_attr "length" "4,8")])
11237
11238 (define_insn "*sibcall_value_local32"
11239 [(set (match_operand 0 "" "")
11240 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11241 (match_operand 2 "" "g,g")))
11242 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11243 (use (reg:SI 65))
11244 (return)]
11245 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11246 "*
11247 {
11248 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11249 output_asm_insn (\"crxor 6,6,6\", operands);
11250
11251 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11252 output_asm_insn (\"creqv 6,6,6\", operands);
11253
11254 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11255 }"
11256 [(set_attr "type" "branch")
11257 (set_attr "length" "4,8")])
11258
11259
11260 (define_insn "*sibcall_value_local64"
11261 [(set (match_operand 0 "" "")
11262 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11263 (match_operand 2 "" "g,g")))
11264 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11265 (use (reg:SI 65))
11266 (return)]
11267 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11268 "*
11269 {
11270 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11271 output_asm_insn (\"crxor 6,6,6\", operands);
11272
11273 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11274 output_asm_insn (\"creqv 6,6,6\", operands);
11275
11276 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11277 }"
11278 [(set_attr "type" "branch")
11279 (set_attr "length" "4,8")])
11280
11281 (define_insn "*sibcall_nonlocal_aix32"
11282 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11283 (match_operand 1 "" "g"))
11284 (use (match_operand:SI 2 "immediate_operand" "O"))
11285 (use (reg:SI 65))
11286 (return)]
11287 "TARGET_32BIT
11288 && DEFAULT_ABI == ABI_AIX
11289 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11290 "b %z0"
11291 [(set_attr "type" "branch")
11292 (set_attr "length" "4")])
11293
11294 (define_insn "*sibcall_nonlocal_aix64"
11295 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11296 (match_operand 1 "" "g"))
11297 (use (match_operand:SI 2 "immediate_operand" "O"))
11298 (use (reg:SI 65))
11299 (return)]
11300 "TARGET_64BIT
11301 && DEFAULT_ABI == ABI_AIX
11302 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11303 "b %z0"
11304 [(set_attr "type" "branch")
11305 (set_attr "length" "4")])
11306
11307 (define_insn "*sibcall_value_nonlocal_aix32"
11308 [(set (match_operand 0 "" "")
11309 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11310 (match_operand 2 "" "g")))
11311 (use (match_operand:SI 3 "immediate_operand" "O"))
11312 (use (reg:SI 65))
11313 (return)]
11314 "TARGET_32BIT
11315 && DEFAULT_ABI == ABI_AIX
11316 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11317 "b %z1"
11318 [(set_attr "type" "branch")
11319 (set_attr "length" "4")])
11320
11321 (define_insn "*sibcall_value_nonlocal_aix64"
11322 [(set (match_operand 0 "" "")
11323 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11324 (match_operand 2 "" "g")))
11325 (use (match_operand:SI 3 "immediate_operand" "O"))
11326 (use (reg:SI 65))
11327 (return)]
11328 "TARGET_64BIT
11329 && DEFAULT_ABI == ABI_AIX
11330 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11331 "b %z1"
11332 [(set_attr "type" "branch")
11333 (set_attr "length" "4")])
11334
11335 (define_insn "*sibcall_nonlocal_sysv<mode>"
11336 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11337 (match_operand 1 "" ""))
11338 (use (match_operand 2 "immediate_operand" "O,n"))
11339 (use (reg:SI 65))
11340 (return)]
11341 "(DEFAULT_ABI == ABI_DARWIN
11342 || DEFAULT_ABI == ABI_V4)
11343 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11344 "*
11345 {
11346 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11347 output_asm_insn (\"crxor 6,6,6\", operands);
11348
11349 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11350 output_asm_insn (\"creqv 6,6,6\", operands);
11351
11352 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11353 {
11354 if (TARGET_SECURE_PLT && flag_pic == 2)
11355 return \"b %z0+32768@plt\";
11356 else
11357 return \"b %z0@plt\";
11358 }
11359 else
11360 return \"b %z0\";
11361 }"
11362 [(set_attr "type" "branch,branch")
11363 (set_attr "length" "4,8")])
11364
11365 (define_expand "sibcall_value"
11366 [(parallel [(set (match_operand 0 "register_operand" "")
11367 (call (mem:SI (match_operand 1 "address_operand" ""))
11368 (match_operand 2 "" "")))
11369 (use (match_operand 3 "" ""))
11370 (use (reg:SI 65))
11371 (return)])]
11372 ""
11373 "
11374 {
11375 #if TARGET_MACHO
11376 if (MACHOPIC_INDIRECT)
11377 operands[1] = machopic_indirect_call_target (operands[1]);
11378 #endif
11379
11380 gcc_assert (GET_CODE (operands[1]) == MEM);
11381 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11382
11383 operands[1] = XEXP (operands[1], 0);
11384 }")
11385
11386 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
11387 [(set (match_operand 0 "" "")
11388 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11389 (match_operand 2 "" "")))
11390 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11391 (use (reg:SI 65))
11392 (return)]
11393 "(DEFAULT_ABI == ABI_DARWIN
11394 || DEFAULT_ABI == ABI_V4)
11395 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11396 "*
11397 {
11398 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11399 output_asm_insn (\"crxor 6,6,6\", operands);
11400
11401 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11402 output_asm_insn (\"creqv 6,6,6\", operands);
11403
11404 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11405 {
11406 if (TARGET_SECURE_PLT && flag_pic == 2)
11407 return \"b %z1+32768@plt\";
11408 else
11409 return \"b %z1@plt\";
11410 }
11411 else
11412 return \"b %z1\";
11413 }"
11414 [(set_attr "type" "branch,branch")
11415 (set_attr "length" "4,8")])
11416
11417 (define_expand "sibcall_epilogue"
11418 [(use (const_int 0))]
11419 "TARGET_SCHED_PROLOG"
11420 "
11421 {
11422 rs6000_emit_epilogue (TRUE);
11423 DONE;
11424 }")
11425
11426 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11427 ;; all of memory. This blocks insns from being moved across this point.
11428
11429 (define_insn "blockage"
11430 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
11431 ""
11432 "")
11433 \f
11434 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
11435 ;; signed & unsigned, and one type of branch.
11436 ;;
11437 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11438 ;; insns, and branches. We store the operands of compares until we see
11439 ;; how it is used.
11440 (define_expand "cmp<mode>"
11441 [(set (cc0)
11442 (compare (match_operand:GPR 0 "gpc_reg_operand" "")
11443 (match_operand:GPR 1 "reg_or_short_operand" "")))]
11444 ""
11445 "
11446 {
11447 /* Take care of the possibility that operands[1] might be negative but
11448 this might be a logical operation. That insn doesn't exist. */
11449 if (GET_CODE (operands[1]) == CONST_INT
11450 && INTVAL (operands[1]) < 0)
11451 operands[1] = force_reg (<MODE>mode, operands[1]);
11452
11453 rs6000_compare_op0 = operands[0];
11454 rs6000_compare_op1 = operands[1];
11455 rs6000_compare_fp_p = 0;
11456 DONE;
11457 }")
11458
11459 (define_expand "cmp<mode>"
11460 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
11461 (match_operand:FP 1 "gpc_reg_operand" "")))]
11462 ""
11463 "
11464 {
11465 rs6000_compare_op0 = operands[0];
11466 rs6000_compare_op1 = operands[1];
11467 rs6000_compare_fp_p = 1;
11468 DONE;
11469 }")
11470
11471 (define_expand "beq"
11472 [(use (match_operand 0 "" ""))]
11473 ""
11474 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
11475
11476 (define_expand "bne"
11477 [(use (match_operand 0 "" ""))]
11478 ""
11479 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
11480
11481 (define_expand "bge"
11482 [(use (match_operand 0 "" ""))]
11483 ""
11484 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
11485
11486 (define_expand "bgt"
11487 [(use (match_operand 0 "" ""))]
11488 ""
11489 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
11490
11491 (define_expand "ble"
11492 [(use (match_operand 0 "" ""))]
11493 ""
11494 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
11495
11496 (define_expand "blt"
11497 [(use (match_operand 0 "" ""))]
11498 ""
11499 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
11500
11501 (define_expand "bgeu"
11502 [(use (match_operand 0 "" ""))]
11503 ""
11504 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
11505
11506 (define_expand "bgtu"
11507 [(use (match_operand 0 "" ""))]
11508 ""
11509 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
11510
11511 (define_expand "bleu"
11512 [(use (match_operand 0 "" ""))]
11513 ""
11514 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
11515
11516 (define_expand "bltu"
11517 [(use (match_operand 0 "" ""))]
11518 ""
11519 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
11520
11521 (define_expand "bunordered"
11522 [(use (match_operand 0 "" ""))]
11523 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11524 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
11525
11526 (define_expand "bordered"
11527 [(use (match_operand 0 "" ""))]
11528 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11529 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
11530
11531 (define_expand "buneq"
11532 [(use (match_operand 0 "" ""))]
11533 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11534 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
11535
11536 (define_expand "bunge"
11537 [(use (match_operand 0 "" ""))]
11538 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11539 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
11540
11541 (define_expand "bungt"
11542 [(use (match_operand 0 "" ""))]
11543 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11544 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
11545
11546 (define_expand "bunle"
11547 [(use (match_operand 0 "" ""))]
11548 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11549 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
11550
11551 (define_expand "bunlt"
11552 [(use (match_operand 0 "" ""))]
11553 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11554 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
11555
11556 (define_expand "bltgt"
11557 [(use (match_operand 0 "" ""))]
11558 ""
11559 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
11560
11561 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11562 ;; For SEQ, likewise, except that comparisons with zero should be done
11563 ;; with an scc insns. However, due to the order that combine see the
11564 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11565 ;; the cases we don't want to handle.
11566 (define_expand "seq"
11567 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11568 ""
11569 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
11570
11571 (define_expand "sne"
11572 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11573 ""
11574 "
11575 {
11576 if (! rs6000_compare_fp_p)
11577 FAIL;
11578
11579 rs6000_emit_sCOND (NE, operands[0]);
11580 DONE;
11581 }")
11582
11583 ;; A >= 0 is best done the portable way for A an integer.
11584 (define_expand "sge"
11585 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11586 ""
11587 "
11588 {
11589 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11590 FAIL;
11591
11592 rs6000_emit_sCOND (GE, operands[0]);
11593 DONE;
11594 }")
11595
11596 ;; A > 0 is best done using the portable sequence, so fail in that case.
11597 (define_expand "sgt"
11598 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11599 ""
11600 "
11601 {
11602 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11603 FAIL;
11604
11605 rs6000_emit_sCOND (GT, operands[0]);
11606 DONE;
11607 }")
11608
11609 ;; A <= 0 is best done the portable way for A an integer.
11610 (define_expand "sle"
11611 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11612 ""
11613 "
11614 {
11615 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11616 FAIL;
11617
11618 rs6000_emit_sCOND (LE, operands[0]);
11619 DONE;
11620 }")
11621
11622 ;; A < 0 is best done in the portable way for A an integer.
11623 (define_expand "slt"
11624 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11625 ""
11626 "
11627 {
11628 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11629 FAIL;
11630
11631 rs6000_emit_sCOND (LT, operands[0]);
11632 DONE;
11633 }")
11634
11635 (define_expand "sgeu"
11636 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11637 ""
11638 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11639
11640 (define_expand "sgtu"
11641 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11642 ""
11643 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
11644
11645 (define_expand "sleu"
11646 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11647 ""
11648 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11649
11650 (define_expand "sltu"
11651 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11652 ""
11653 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
11654
11655 (define_expand "sunordered"
11656 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11657 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11658 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
11659
11660 (define_expand "sordered"
11661 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11662 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11663 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11664
11665 (define_expand "suneq"
11666 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11667 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11668 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11669
11670 (define_expand "sunge"
11671 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11672 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11673 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11674
11675 (define_expand "sungt"
11676 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11677 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11678 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11679
11680 (define_expand "sunle"
11681 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11682 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11683 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11684
11685 (define_expand "sunlt"
11686 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11687 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11688 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11689
11690 (define_expand "sltgt"
11691 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11692 ""
11693 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11694
11695 (define_expand "stack_protect_set"
11696 [(match_operand 0 "memory_operand" "")
11697 (match_operand 1 "memory_operand" "")]
11698 ""
11699 {
11700 #ifdef TARGET_THREAD_SSP_OFFSET
11701 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11702 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11703 operands[1] = gen_rtx_MEM (Pmode, addr);
11704 #endif
11705 if (TARGET_64BIT)
11706 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11707 else
11708 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11709 DONE;
11710 })
11711
11712 (define_insn "stack_protect_setsi"
11713 [(set (match_operand:SI 0 "memory_operand" "=m")
11714 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11715 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11716 "TARGET_32BIT"
11717 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
11718 [(set_attr "type" "three")
11719 (set_attr "length" "12")])
11720
11721 (define_insn "stack_protect_setdi"
11722 [(set (match_operand:DI 0 "memory_operand" "=m")
11723 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11724 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11725 "TARGET_64BIT"
11726 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
11727 [(set_attr "type" "three")
11728 (set_attr "length" "12")])
11729
11730 (define_expand "stack_protect_test"
11731 [(match_operand 0 "memory_operand" "")
11732 (match_operand 1 "memory_operand" "")
11733 (match_operand 2 "" "")]
11734 ""
11735 {
11736 #ifdef TARGET_THREAD_SSP_OFFSET
11737 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11738 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11739 operands[1] = gen_rtx_MEM (Pmode, addr);
11740 #endif
11741 rs6000_compare_op0 = operands[0];
11742 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
11743 UNSPEC_SP_TEST);
11744 rs6000_compare_fp_p = 0;
11745 emit_jump_insn (gen_beq (operands[2]));
11746 DONE;
11747 })
11748
11749 (define_insn "stack_protect_testsi"
11750 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11751 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11752 (match_operand:SI 2 "memory_operand" "m,m")]
11753 UNSPEC_SP_TEST))
11754 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11755 (clobber (match_scratch:SI 3 "=&r,&r"))]
11756 "TARGET_32BIT"
11757 "@
11758 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11759 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11760 [(set_attr "length" "16,20")])
11761
11762 (define_insn "stack_protect_testdi"
11763 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11764 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
11765 (match_operand:DI 2 "memory_operand" "m,m")]
11766 UNSPEC_SP_TEST))
11767 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11768 (clobber (match_scratch:DI 3 "=&r,&r"))]
11769 "TARGET_64BIT"
11770 "@
11771 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11772 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11773 [(set_attr "length" "16,20")])
11774
11775 \f
11776 ;; Here are the actual compare insns.
11777 (define_insn "*cmp<mode>_internal1"
11778 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11779 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11780 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
11781 ""
11782 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
11783 [(set_attr "type" "cmp")])
11784
11785 ;; If we are comparing a register for equality with a large constant,
11786 ;; we can do this with an XOR followed by a compare. But this is profitable
11787 ;; only if the large constant is only used for the comparison (and in this
11788 ;; case we already have a register to reuse as scratch).
11789 ;;
11790 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11791 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
11792
11793 (define_peephole2
11794 [(set (match_operand:SI 0 "register_operand")
11795 (match_operand:SI 1 "logical_const_operand" ""))
11796 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
11797 [(match_dup 0)
11798 (match_operand:SI 2 "logical_const_operand" "")]))
11799 (set (match_operand:CC 4 "cc_reg_operand" "")
11800 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
11801 (match_dup 0)))
11802 (set (pc)
11803 (if_then_else (match_operator 6 "equality_operator"
11804 [(match_dup 4) (const_int 0)])
11805 (match_operand 7 "" "")
11806 (match_operand 8 "" "")))]
11807 "peep2_reg_dead_p (3, operands[0])
11808 && peep2_reg_dead_p (4, operands[4])"
11809 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
11810 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11811 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11812
11813 {
11814 /* Get the constant we are comparing against, and see what it looks like
11815 when sign-extended from 16 to 32 bits. Then see what constant we could
11816 XOR with SEXTC to get the sign-extended value. */
11817 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
11818 SImode,
11819 operands[1], operands[2]);
11820 HOST_WIDE_INT c = INTVAL (cnst);
11821 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11822 HOST_WIDE_INT xorv = c ^ sextc;
11823
11824 operands[9] = GEN_INT (xorv);
11825 operands[10] = GEN_INT (sextc);
11826 })
11827
11828 (define_insn "*cmpsi_internal2"
11829 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11830 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11831 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11832 ""
11833 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
11834 [(set_attr "type" "cmp")])
11835
11836 (define_insn "*cmpdi_internal2"
11837 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11838 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11839 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11840 ""
11841 "cmpld%I2 %0,%1,%b2"
11842 [(set_attr "type" "cmp")])
11843
11844 ;; The following two insns don't exist as single insns, but if we provide
11845 ;; them, we can swap an add and compare, which will enable us to overlap more
11846 ;; of the required delay between a compare and branch. We generate code for
11847 ;; them by splitting.
11848
11849 (define_insn ""
11850 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11851 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11852 (match_operand:SI 2 "short_cint_operand" "i")))
11853 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11854 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11855 ""
11856 "#"
11857 [(set_attr "length" "8")])
11858
11859 (define_insn ""
11860 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11861 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11862 (match_operand:SI 2 "u_short_cint_operand" "i")))
11863 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11864 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11865 ""
11866 "#"
11867 [(set_attr "length" "8")])
11868
11869 (define_split
11870 [(set (match_operand:CC 3 "cc_reg_operand" "")
11871 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11872 (match_operand:SI 2 "short_cint_operand" "")))
11873 (set (match_operand:SI 0 "gpc_reg_operand" "")
11874 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11875 ""
11876 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11877 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11878
11879 (define_split
11880 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11881 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11882 (match_operand:SI 2 "u_short_cint_operand" "")))
11883 (set (match_operand:SI 0 "gpc_reg_operand" "")
11884 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11885 ""
11886 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11887 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11888
11889 (define_insn "*cmpsf_internal1"
11890 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11891 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11892 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11893 "TARGET_HARD_FLOAT && TARGET_FPRS"
11894 "fcmpu %0,%1,%2"
11895 [(set_attr "type" "fpcompare")])
11896
11897 (define_insn "*cmpdf_internal1"
11898 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11899 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11900 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11901 "TARGET_HARD_FLOAT && TARGET_FPRS"
11902 "fcmpu %0,%1,%2"
11903 [(set_attr "type" "fpcompare")])
11904
11905 ;; Only need to compare second words if first words equal
11906 (define_insn "*cmptf_internal1"
11907 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11908 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11909 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11910 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
11911 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11912 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11913 [(set_attr "type" "fpcompare")
11914 (set_attr "length" "12")])
11915
11916 (define_insn_and_split "*cmptf_internal2"
11917 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11918 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11919 (match_operand:TF 2 "gpc_reg_operand" "f")))
11920 (clobber (match_scratch:DF 3 "=f"))
11921 (clobber (match_scratch:DF 4 "=f"))
11922 (clobber (match_scratch:DF 5 "=f"))
11923 (clobber (match_scratch:DF 6 "=f"))
11924 (clobber (match_scratch:DF 7 "=f"))
11925 (clobber (match_scratch:DF 8 "=f"))
11926 (clobber (match_scratch:DF 9 "=f"))
11927 (clobber (match_scratch:DF 10 "=f"))]
11928 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
11929 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11930 "#"
11931 "&& reload_completed"
11932 [(set (match_dup 3) (match_dup 13))
11933 (set (match_dup 4) (match_dup 14))
11934 (set (match_dup 9) (abs:DF (match_dup 5)))
11935 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11936 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11937 (label_ref (match_dup 11))
11938 (pc)))
11939 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11940 (set (pc) (label_ref (match_dup 12)))
11941 (match_dup 11)
11942 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11943 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11944 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11945 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
11946 (match_dup 12)]
11947 {
11948 REAL_VALUE_TYPE rv;
11949 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
11950 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
11951
11952 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11953 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11954 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11955 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11956 operands[11] = gen_label_rtx ();
11957 operands[12] = gen_label_rtx ();
11958 real_inf (&rv);
11959 operands[13] = force_const_mem (DFmode,
11960 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11961 operands[14] = force_const_mem (DFmode,
11962 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11963 DFmode));
11964 if (TARGET_TOC)
11965 {
11966 operands[13] = gen_const_mem (DFmode,
11967 create_TOC_reference (XEXP (operands[13], 0)));
11968 operands[14] = gen_const_mem (DFmode,
11969 create_TOC_reference (XEXP (operands[14], 0)));
11970 set_mem_alias_set (operands[13], get_TOC_alias_set ());
11971 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11972 }
11973 })
11974 \f
11975 ;; Now we have the scc insns. We can do some combinations because of the
11976 ;; way the machine works.
11977 ;;
11978 ;; Note that this is probably faster if we can put an insn between the
11979 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11980 ;; cases the insns below which don't use an intermediate CR field will
11981 ;; be used instead.
11982 (define_insn ""
11983 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11984 (match_operator:SI 1 "scc_comparison_operator"
11985 [(match_operand 2 "cc_reg_operand" "y")
11986 (const_int 0)]))]
11987 ""
11988 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11989 [(set (attr "type")
11990 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11991 (const_string "mfcrf")
11992 ]
11993 (const_string "mfcr")))
11994 (set_attr "length" "8")])
11995
11996 ;; Same as above, but get the GT bit.
11997 (define_insn "move_from_CR_gt_bit"
11998 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11999 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
12000 "TARGET_E500"
12001 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
12002 [(set_attr "type" "mfcr")
12003 (set_attr "length" "8")])
12004
12005 ;; Same as above, but get the OV/ORDERED bit.
12006 (define_insn "move_from_CR_ov_bit"
12007 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12008 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
12009 "TARGET_ISEL"
12010 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
12011 [(set_attr "type" "mfcr")
12012 (set_attr "length" "8")])
12013
12014 (define_insn ""
12015 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12016 (match_operator:DI 1 "scc_comparison_operator"
12017 [(match_operand 2 "cc_reg_operand" "y")
12018 (const_int 0)]))]
12019 "TARGET_POWERPC64"
12020 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12021 [(set (attr "type")
12022 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12023 (const_string "mfcrf")
12024 ]
12025 (const_string "mfcr")))
12026 (set_attr "length" "8")])
12027
12028 (define_insn ""
12029 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12030 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12031 [(match_operand 2 "cc_reg_operand" "y,y")
12032 (const_int 0)])
12033 (const_int 0)))
12034 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
12035 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12036 "TARGET_32BIT"
12037 "@
12038 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
12039 #"
12040 [(set_attr "type" "delayed_compare")
12041 (set_attr "length" "8,16")])
12042
12043 (define_split
12044 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12045 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12046 [(match_operand 2 "cc_reg_operand" "")
12047 (const_int 0)])
12048 (const_int 0)))
12049 (set (match_operand:SI 3 "gpc_reg_operand" "")
12050 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12051 "TARGET_32BIT && reload_completed"
12052 [(set (match_dup 3)
12053 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12054 (set (match_dup 0)
12055 (compare:CC (match_dup 3)
12056 (const_int 0)))]
12057 "")
12058
12059 (define_insn ""
12060 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12061 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12062 [(match_operand 2 "cc_reg_operand" "y")
12063 (const_int 0)])
12064 (match_operand:SI 3 "const_int_operand" "n")))]
12065 ""
12066 "*
12067 {
12068 int is_bit = ccr_bit (operands[1], 1);
12069 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12070 int count;
12071
12072 if (is_bit >= put_bit)
12073 count = is_bit - put_bit;
12074 else
12075 count = 32 - (put_bit - is_bit);
12076
12077 operands[4] = GEN_INT (count);
12078 operands[5] = GEN_INT (put_bit);
12079
12080 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
12081 }"
12082 [(set (attr "type")
12083 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12084 (const_string "mfcrf")
12085 ]
12086 (const_string "mfcr")))
12087 (set_attr "length" "8")])
12088
12089 (define_insn ""
12090 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12091 (compare:CC
12092 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12093 [(match_operand 2 "cc_reg_operand" "y,y")
12094 (const_int 0)])
12095 (match_operand:SI 3 "const_int_operand" "n,n"))
12096 (const_int 0)))
12097 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
12098 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12099 (match_dup 3)))]
12100 ""
12101 "*
12102 {
12103 int is_bit = ccr_bit (operands[1], 1);
12104 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12105 int count;
12106
12107 /* Force split for non-cc0 compare. */
12108 if (which_alternative == 1)
12109 return \"#\";
12110
12111 if (is_bit >= put_bit)
12112 count = is_bit - put_bit;
12113 else
12114 count = 32 - (put_bit - is_bit);
12115
12116 operands[5] = GEN_INT (count);
12117 operands[6] = GEN_INT (put_bit);
12118
12119 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
12120 }"
12121 [(set_attr "type" "delayed_compare")
12122 (set_attr "length" "8,16")])
12123
12124 (define_split
12125 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12126 (compare:CC
12127 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12128 [(match_operand 2 "cc_reg_operand" "")
12129 (const_int 0)])
12130 (match_operand:SI 3 "const_int_operand" ""))
12131 (const_int 0)))
12132 (set (match_operand:SI 4 "gpc_reg_operand" "")
12133 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12134 (match_dup 3)))]
12135 "reload_completed"
12136 [(set (match_dup 4)
12137 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12138 (match_dup 3)))
12139 (set (match_dup 0)
12140 (compare:CC (match_dup 4)
12141 (const_int 0)))]
12142 "")
12143
12144 ;; There is a 3 cycle delay between consecutive mfcr instructions
12145 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
12146
12147 (define_peephole
12148 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12149 (match_operator:SI 1 "scc_comparison_operator"
12150 [(match_operand 2 "cc_reg_operand" "y")
12151 (const_int 0)]))
12152 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
12153 (match_operator:SI 4 "scc_comparison_operator"
12154 [(match_operand 5 "cc_reg_operand" "y")
12155 (const_int 0)]))]
12156 "REGNO (operands[2]) != REGNO (operands[5])"
12157 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
12158 [(set_attr "type" "mfcr")
12159 (set_attr "length" "12")])
12160
12161 (define_peephole
12162 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12163 (match_operator:DI 1 "scc_comparison_operator"
12164 [(match_operand 2 "cc_reg_operand" "y")
12165 (const_int 0)]))
12166 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12167 (match_operator:DI 4 "scc_comparison_operator"
12168 [(match_operand 5 "cc_reg_operand" "y")
12169 (const_int 0)]))]
12170 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
12171 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
12172 [(set_attr "type" "mfcr")
12173 (set_attr "length" "12")])
12174
12175 ;; There are some scc insns that can be done directly, without a compare.
12176 ;; These are faster because they don't involve the communications between
12177 ;; the FXU and branch units. In fact, we will be replacing all of the
12178 ;; integer scc insns here or in the portable methods in emit_store_flag.
12179 ;;
12180 ;; Also support (neg (scc ..)) since that construct is used to replace
12181 ;; branches, (plus (scc ..) ..) since that construct is common and
12182 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12183 ;; cases where it is no more expensive than (neg (scc ..)).
12184
12185 ;; Have reload force a constant into a register for the simple insns that
12186 ;; otherwise won't accept constants. We do this because it is faster than
12187 ;; the cmp/mfcr sequence we would otherwise generate.
12188
12189 (define_mode_attr scc_eq_op2 [(SI "rKLI")
12190 (DI "rKJI")])
12191
12192 (define_insn_and_split "*eq<mode>"
12193 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12194 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
12195 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
12196 "!TARGET_POWER"
12197 "#"
12198 "!TARGET_POWER"
12199 [(set (match_dup 0)
12200 (clz:GPR (match_dup 3)))
12201 (set (match_dup 0)
12202 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
12203 {
12204 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12205 {
12206 /* Use output operand as intermediate. */
12207 operands[3] = operands[0];
12208
12209 if (logical_operand (operands[2], <MODE>mode))
12210 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12211 gen_rtx_XOR (<MODE>mode,
12212 operands[1], operands[2])));
12213 else
12214 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12215 gen_rtx_PLUS (<MODE>mode, operands[1],
12216 negate_rtx (<MODE>mode,
12217 operands[2]))));
12218 }
12219 else
12220 operands[3] = operands[1];
12221
12222 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12223 })
12224
12225 (define_insn_and_split "*eq<mode>_compare"
12226 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12227 (compare:CC
12228 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12229 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
12230 (const_int 0)))
12231 (set (match_operand:P 0 "gpc_reg_operand" "=r")
12232 (eq:P (match_dup 1) (match_dup 2)))]
12233 "!TARGET_POWER && optimize_size"
12234 "#"
12235 "!TARGET_POWER && optimize_size"
12236 [(set (match_dup 0)
12237 (clz:P (match_dup 4)))
12238 (parallel [(set (match_dup 3)
12239 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
12240 (const_int 0)))
12241 (set (match_dup 0)
12242 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
12243 {
12244 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12245 {
12246 /* Use output operand as intermediate. */
12247 operands[4] = operands[0];
12248
12249 if (logical_operand (operands[2], <MODE>mode))
12250 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12251 gen_rtx_XOR (<MODE>mode,
12252 operands[1], operands[2])));
12253 else
12254 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12255 gen_rtx_PLUS (<MODE>mode, operands[1],
12256 negate_rtx (<MODE>mode,
12257 operands[2]))));
12258 }
12259 else
12260 operands[4] = operands[1];
12261
12262 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12263 })
12264
12265 (define_insn "*eqsi_power"
12266 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
12267 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12268 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
12269 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
12270 "TARGET_POWER"
12271 "@
12272 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12273 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
12274 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12275 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12276 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
12277 [(set_attr "type" "three,two,three,three,three")
12278 (set_attr "length" "12,8,12,12,12")])
12279
12280 ;; We have insns of the form shown by the first define_insn below. If
12281 ;; there is something inside the comparison operation, we must split it.
12282 (define_split
12283 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12284 (plus:SI (match_operator 1 "comparison_operator"
12285 [(match_operand:SI 2 "" "")
12286 (match_operand:SI 3
12287 "reg_or_cint_operand" "")])
12288 (match_operand:SI 4 "gpc_reg_operand" "")))
12289 (clobber (match_operand:SI 5 "register_operand" ""))]
12290 "! gpc_reg_operand (operands[2], SImode)"
12291 [(set (match_dup 5) (match_dup 2))
12292 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
12293 (match_dup 4)))])
12294
12295 (define_insn "*plus_eqsi"
12296 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
12297 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12298 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
12299 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
12300 "TARGET_32BIT"
12301 "@
12302 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12303 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
12304 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12305 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12306 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12307 [(set_attr "type" "three,two,three,three,three")
12308 (set_attr "length" "12,8,12,12,12")])
12309
12310 (define_insn "*compare_plus_eqsi"
12311 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12312 (compare:CC
12313 (plus:SI
12314 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12315 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12316 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12317 (const_int 0)))
12318 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
12319 "TARGET_32BIT && optimize_size"
12320 "@
12321 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12322 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
12323 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12324 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12325 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12326 #
12327 #
12328 #
12329 #
12330 #"
12331 [(set_attr "type" "compare")
12332 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12333
12334 (define_split
12335 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12336 (compare:CC
12337 (plus:SI
12338 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12339 (match_operand:SI 2 "scc_eq_operand" ""))
12340 (match_operand:SI 3 "gpc_reg_operand" ""))
12341 (const_int 0)))
12342 (clobber (match_scratch:SI 4 ""))]
12343 "TARGET_32BIT && optimize_size && reload_completed"
12344 [(set (match_dup 4)
12345 (plus:SI (eq:SI (match_dup 1)
12346 (match_dup 2))
12347 (match_dup 3)))
12348 (set (match_dup 0)
12349 (compare:CC (match_dup 4)
12350 (const_int 0)))]
12351 "")
12352
12353 (define_insn "*plus_eqsi_compare"
12354 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12355 (compare:CC
12356 (plus:SI
12357 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12358 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12359 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12360 (const_int 0)))
12361 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12362 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12363 "TARGET_32BIT && optimize_size"
12364 "@
12365 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12366 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
12367 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12368 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12369 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12370 #
12371 #
12372 #
12373 #
12374 #"
12375 [(set_attr "type" "compare")
12376 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12377
12378 (define_split
12379 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12380 (compare:CC
12381 (plus:SI
12382 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12383 (match_operand:SI 2 "scc_eq_operand" ""))
12384 (match_operand:SI 3 "gpc_reg_operand" ""))
12385 (const_int 0)))
12386 (set (match_operand:SI 0 "gpc_reg_operand" "")
12387 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12388 "TARGET_32BIT && optimize_size && reload_completed"
12389 [(set (match_dup 0)
12390 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12391 (set (match_dup 4)
12392 (compare:CC (match_dup 0)
12393 (const_int 0)))]
12394 "")
12395
12396 (define_insn "*neg_eq0<mode>"
12397 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12398 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12399 (const_int 0))))]
12400 ""
12401 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
12402 [(set_attr "type" "two")
12403 (set_attr "length" "8")])
12404
12405 (define_insn_and_split "*neg_eq<mode>"
12406 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12407 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12408 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
12409 ""
12410 "#"
12411 ""
12412 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12413 {
12414 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12415 {
12416 /* Use output operand as intermediate. */
12417 operands[3] = operands[0];
12418
12419 if (logical_operand (operands[2], <MODE>mode))
12420 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12421 gen_rtx_XOR (<MODE>mode,
12422 operands[1], operands[2])));
12423 else
12424 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12425 gen_rtx_PLUS (<MODE>mode, operands[1],
12426 negate_rtx (<MODE>mode,
12427 operands[2]))));
12428 }
12429 else
12430 operands[3] = operands[1];
12431 })
12432
12433 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
12434 ;; since it nabs/sr is just as fast.
12435 (define_insn "*ne0si"
12436 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12437 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12438 (const_int 31)))
12439 (clobber (match_scratch:SI 2 "=&r"))]
12440 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
12441 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
12442 [(set_attr "type" "two")
12443 (set_attr "length" "8")])
12444
12445 (define_insn "*ne0di"
12446 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12447 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12448 (const_int 63)))
12449 (clobber (match_scratch:DI 2 "=&r"))]
12450 "TARGET_64BIT"
12451 "addic %2,%1,-1\;subfe %0,%2,%1"
12452 [(set_attr "type" "two")
12453 (set_attr "length" "8")])
12454
12455 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
12456 (define_insn "*plus_ne0si"
12457 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12458 (plus:SI (lshiftrt:SI
12459 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12460 (const_int 31))
12461 (match_operand:SI 2 "gpc_reg_operand" "r")))
12462 (clobber (match_scratch:SI 3 "=&r"))]
12463 "TARGET_32BIT"
12464 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
12465 [(set_attr "type" "two")
12466 (set_attr "length" "8")])
12467
12468 (define_insn "*plus_ne0di"
12469 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12470 (plus:DI (lshiftrt:DI
12471 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12472 (const_int 63))
12473 (match_operand:DI 2 "gpc_reg_operand" "r")))
12474 (clobber (match_scratch:DI 3 "=&r"))]
12475 "TARGET_64BIT"
12476 "addic %3,%1,-1\;addze %0,%2"
12477 [(set_attr "type" "two")
12478 (set_attr "length" "8")])
12479
12480 (define_insn "*compare_plus_ne0si"
12481 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12482 (compare:CC
12483 (plus:SI (lshiftrt:SI
12484 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12485 (const_int 31))
12486 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12487 (const_int 0)))
12488 (clobber (match_scratch:SI 3 "=&r,&r"))
12489 (clobber (match_scratch:SI 4 "=X,&r"))]
12490 "TARGET_32BIT"
12491 "@
12492 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
12493 #"
12494 [(set_attr "type" "compare")
12495 (set_attr "length" "8,12")])
12496
12497 (define_split
12498 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12499 (compare:CC
12500 (plus:SI (lshiftrt:SI
12501 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12502 (const_int 31))
12503 (match_operand:SI 2 "gpc_reg_operand" ""))
12504 (const_int 0)))
12505 (clobber (match_scratch:SI 3 ""))
12506 (clobber (match_scratch:SI 4 ""))]
12507 "TARGET_32BIT && reload_completed"
12508 [(parallel [(set (match_dup 3)
12509 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
12510 (const_int 31))
12511 (match_dup 2)))
12512 (clobber (match_dup 4))])
12513 (set (match_dup 0)
12514 (compare:CC (match_dup 3)
12515 (const_int 0)))]
12516 "")
12517
12518 (define_insn "*compare_plus_ne0di"
12519 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12520 (compare:CC
12521 (plus:DI (lshiftrt:DI
12522 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12523 (const_int 63))
12524 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12525 (const_int 0)))
12526 (clobber (match_scratch:DI 3 "=&r,&r"))]
12527 "TARGET_64BIT"
12528 "@
12529 addic %3,%1,-1\;addze. %3,%2
12530 #"
12531 [(set_attr "type" "compare")
12532 (set_attr "length" "8,12")])
12533
12534 (define_split
12535 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12536 (compare:CC
12537 (plus:DI (lshiftrt:DI
12538 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12539 (const_int 63))
12540 (match_operand:DI 2 "gpc_reg_operand" ""))
12541 (const_int 0)))
12542 (clobber (match_scratch:DI 3 ""))]
12543 "TARGET_64BIT && reload_completed"
12544 [(set (match_dup 3)
12545 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12546 (const_int 63))
12547 (match_dup 2)))
12548 (set (match_dup 0)
12549 (compare:CC (match_dup 3)
12550 (const_int 0)))]
12551 "")
12552
12553 (define_insn "*plus_ne0si_compare"
12554 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12555 (compare:CC
12556 (plus:SI (lshiftrt:SI
12557 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12558 (const_int 31))
12559 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12560 (const_int 0)))
12561 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12562 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12563 (match_dup 2)))
12564 (clobber (match_scratch:SI 3 "=&r,&r"))]
12565 "TARGET_32BIT"
12566 "@
12567 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
12568 #"
12569 [(set_attr "type" "compare")
12570 (set_attr "length" "8,12")])
12571
12572 (define_split
12573 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12574 (compare:CC
12575 (plus:SI (lshiftrt:SI
12576 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12577 (const_int 31))
12578 (match_operand:SI 2 "gpc_reg_operand" ""))
12579 (const_int 0)))
12580 (set (match_operand:SI 0 "gpc_reg_operand" "")
12581 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12582 (match_dup 2)))
12583 (clobber (match_scratch:SI 3 ""))]
12584 "TARGET_32BIT && reload_completed"
12585 [(parallel [(set (match_dup 0)
12586 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12587 (match_dup 2)))
12588 (clobber (match_dup 3))])
12589 (set (match_dup 4)
12590 (compare:CC (match_dup 0)
12591 (const_int 0)))]
12592 "")
12593
12594 (define_insn "*plus_ne0di_compare"
12595 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12596 (compare:CC
12597 (plus:DI (lshiftrt:DI
12598 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12599 (const_int 63))
12600 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12601 (const_int 0)))
12602 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12603 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12604 (match_dup 2)))
12605 (clobber (match_scratch:DI 3 "=&r,&r"))]
12606 "TARGET_64BIT"
12607 "@
12608 addic %3,%1,-1\;addze. %0,%2
12609 #"
12610 [(set_attr "type" "compare")
12611 (set_attr "length" "8,12")])
12612
12613 (define_split
12614 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12615 (compare:CC
12616 (plus:DI (lshiftrt:DI
12617 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12618 (const_int 63))
12619 (match_operand:DI 2 "gpc_reg_operand" ""))
12620 (const_int 0)))
12621 (set (match_operand:DI 0 "gpc_reg_operand" "")
12622 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12623 (match_dup 2)))
12624 (clobber (match_scratch:DI 3 ""))]
12625 "TARGET_64BIT && reload_completed"
12626 [(parallel [(set (match_dup 0)
12627 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12628 (match_dup 2)))
12629 (clobber (match_dup 3))])
12630 (set (match_dup 4)
12631 (compare:CC (match_dup 0)
12632 (const_int 0)))]
12633 "")
12634
12635 (define_insn ""
12636 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12637 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12638 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12639 (clobber (match_scratch:SI 3 "=r,X"))]
12640 "TARGET_POWER"
12641 "@
12642 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
12643 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
12644 [(set_attr "length" "12")])
12645
12646 (define_insn ""
12647 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12648 (compare:CC
12649 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12650 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12651 (const_int 0)))
12652 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12653 (le:SI (match_dup 1) (match_dup 2)))
12654 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
12655 "TARGET_POWER"
12656 "@
12657 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12658 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
12659 #
12660 #"
12661 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
12662 (set_attr "length" "12,12,16,16")])
12663
12664 (define_split
12665 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12666 (compare:CC
12667 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12668 (match_operand:SI 2 "reg_or_short_operand" ""))
12669 (const_int 0)))
12670 (set (match_operand:SI 0 "gpc_reg_operand" "")
12671 (le:SI (match_dup 1) (match_dup 2)))
12672 (clobber (match_scratch:SI 3 ""))]
12673 "TARGET_POWER && reload_completed"
12674 [(parallel [(set (match_dup 0)
12675 (le:SI (match_dup 1) (match_dup 2)))
12676 (clobber (match_dup 3))])
12677 (set (match_dup 4)
12678 (compare:CC (match_dup 0)
12679 (const_int 0)))]
12680 "")
12681
12682 (define_insn ""
12683 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12684 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12685 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
12686 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12687 "TARGET_POWER"
12688 "@
12689 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12690 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
12691 [(set_attr "length" "12")])
12692
12693 (define_insn ""
12694 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12695 (compare:CC
12696 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12697 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12698 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12699 (const_int 0)))
12700 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12701 "TARGET_POWER"
12702 "@
12703 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12704 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12705 #
12706 #"
12707 [(set_attr "type" "compare")
12708 (set_attr "length" "12,12,16,16")])
12709
12710 (define_split
12711 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12712 (compare:CC
12713 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12714 (match_operand:SI 2 "reg_or_short_operand" ""))
12715 (match_operand:SI 3 "gpc_reg_operand" ""))
12716 (const_int 0)))
12717 (clobber (match_scratch:SI 4 ""))]
12718 "TARGET_POWER && reload_completed"
12719 [(set (match_dup 4)
12720 (plus:SI (le:SI (match_dup 1) (match_dup 2))
12721 (match_dup 3)))
12722 (set (match_dup 0)
12723 (compare:CC (match_dup 4)
12724 (const_int 0)))]
12725 "")
12726
12727 (define_insn ""
12728 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12729 (compare:CC
12730 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12731 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12732 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12733 (const_int 0)))
12734 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12735 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12736 "TARGET_POWER"
12737 "@
12738 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12739 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
12740 #
12741 #"
12742 [(set_attr "type" "compare")
12743 (set_attr "length" "12,12,16,16")])
12744
12745 (define_split
12746 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12747 (compare:CC
12748 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12749 (match_operand:SI 2 "reg_or_short_operand" ""))
12750 (match_operand:SI 3 "gpc_reg_operand" ""))
12751 (const_int 0)))
12752 (set (match_operand:SI 0 "gpc_reg_operand" "")
12753 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12754 "TARGET_POWER && reload_completed"
12755 [(set (match_dup 0)
12756 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12757 (set (match_dup 4)
12758 (compare:CC (match_dup 0)
12759 (const_int 0)))]
12760 "")
12761
12762 (define_insn ""
12763 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12764 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12765 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
12766 "TARGET_POWER"
12767 "@
12768 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12769 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
12770 [(set_attr "length" "12")])
12771
12772 (define_insn "*leu<mode>"
12773 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12774 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12775 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12776 ""
12777 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12778 [(set_attr "type" "three")
12779 (set_attr "length" "12")])
12780
12781 (define_insn "*leu<mode>_compare"
12782 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12783 (compare:CC
12784 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12785 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12786 (const_int 0)))
12787 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12788 (leu:P (match_dup 1) (match_dup 2)))]
12789 ""
12790 "@
12791 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12792 #"
12793 [(set_attr "type" "compare")
12794 (set_attr "length" "12,16")])
12795
12796 (define_split
12797 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12798 (compare:CC
12799 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12800 (match_operand:P 2 "reg_or_short_operand" ""))
12801 (const_int 0)))
12802 (set (match_operand:P 0 "gpc_reg_operand" "")
12803 (leu:P (match_dup 1) (match_dup 2)))]
12804 "reload_completed"
12805 [(set (match_dup 0)
12806 (leu:P (match_dup 1) (match_dup 2)))
12807 (set (match_dup 3)
12808 (compare:CC (match_dup 0)
12809 (const_int 0)))]
12810 "")
12811
12812 (define_insn "*plus_leu<mode>"
12813 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12814 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12815 (match_operand:P 2 "reg_or_short_operand" "rI"))
12816 (match_operand:P 3 "gpc_reg_operand" "r")))]
12817 ""
12818 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12819 [(set_attr "type" "two")
12820 (set_attr "length" "8")])
12821
12822 (define_insn ""
12823 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12824 (compare:CC
12825 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12826 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12827 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12828 (const_int 0)))
12829 (clobber (match_scratch:SI 4 "=&r,&r"))]
12830 "TARGET_32BIT"
12831 "@
12832 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12833 #"
12834 [(set_attr "type" "compare")
12835 (set_attr "length" "8,12")])
12836
12837 (define_split
12838 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12839 (compare:CC
12840 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12841 (match_operand:SI 2 "reg_or_short_operand" ""))
12842 (match_operand:SI 3 "gpc_reg_operand" ""))
12843 (const_int 0)))
12844 (clobber (match_scratch:SI 4 ""))]
12845 "TARGET_32BIT && reload_completed"
12846 [(set (match_dup 4)
12847 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12848 (match_dup 3)))
12849 (set (match_dup 0)
12850 (compare:CC (match_dup 4)
12851 (const_int 0)))]
12852 "")
12853
12854 (define_insn ""
12855 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12856 (compare:CC
12857 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12858 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12859 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12860 (const_int 0)))
12861 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12862 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12863 "TARGET_32BIT"
12864 "@
12865 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12866 #"
12867 [(set_attr "type" "compare")
12868 (set_attr "length" "8,12")])
12869
12870 (define_split
12871 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12872 (compare:CC
12873 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12874 (match_operand:SI 2 "reg_or_short_operand" ""))
12875 (match_operand:SI 3 "gpc_reg_operand" ""))
12876 (const_int 0)))
12877 (set (match_operand:SI 0 "gpc_reg_operand" "")
12878 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12879 "TARGET_32BIT && reload_completed"
12880 [(set (match_dup 0)
12881 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12882 (set (match_dup 4)
12883 (compare:CC (match_dup 0)
12884 (const_int 0)))]
12885 "")
12886
12887 (define_insn "*neg_leu<mode>"
12888 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12889 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12890 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12891 ""
12892 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12893 [(set_attr "type" "three")
12894 (set_attr "length" "12")])
12895
12896 (define_insn "*and_neg_leu<mode>"
12897 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12898 (and:P (neg:P
12899 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12900 (match_operand:P 2 "reg_or_short_operand" "rI")))
12901 (match_operand:P 3 "gpc_reg_operand" "r")))]
12902 ""
12903 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12904 [(set_attr "type" "three")
12905 (set_attr "length" "12")])
12906
12907 (define_insn ""
12908 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12909 (compare:CC
12910 (and:SI (neg:SI
12911 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12912 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12913 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12914 (const_int 0)))
12915 (clobber (match_scratch:SI 4 "=&r,&r"))]
12916 "TARGET_32BIT"
12917 "@
12918 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12919 #"
12920 [(set_attr "type" "compare")
12921 (set_attr "length" "12,16")])
12922
12923 (define_split
12924 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12925 (compare:CC
12926 (and:SI (neg:SI
12927 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12928 (match_operand:SI 2 "reg_or_short_operand" "")))
12929 (match_operand:SI 3 "gpc_reg_operand" ""))
12930 (const_int 0)))
12931 (clobber (match_scratch:SI 4 ""))]
12932 "TARGET_32BIT && reload_completed"
12933 [(set (match_dup 4)
12934 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12935 (match_dup 3)))
12936 (set (match_dup 0)
12937 (compare:CC (match_dup 4)
12938 (const_int 0)))]
12939 "")
12940
12941 (define_insn ""
12942 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12943 (compare:CC
12944 (and:SI (neg:SI
12945 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12946 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12947 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12948 (const_int 0)))
12949 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12950 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12951 "TARGET_32BIT"
12952 "@
12953 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12954 #"
12955 [(set_attr "type" "compare")
12956 (set_attr "length" "12,16")])
12957
12958 (define_split
12959 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12960 (compare:CC
12961 (and:SI (neg:SI
12962 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12963 (match_operand:SI 2 "reg_or_short_operand" "")))
12964 (match_operand:SI 3 "gpc_reg_operand" ""))
12965 (const_int 0)))
12966 (set (match_operand:SI 0 "gpc_reg_operand" "")
12967 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12968 "TARGET_32BIT && reload_completed"
12969 [(set (match_dup 0)
12970 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12971 (match_dup 3)))
12972 (set (match_dup 4)
12973 (compare:CC (match_dup 0)
12974 (const_int 0)))]
12975 "")
12976
12977 (define_insn ""
12978 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12979 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12980 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12981 "TARGET_POWER"
12982 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12983 [(set_attr "length" "12")])
12984
12985 (define_insn ""
12986 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12987 (compare:CC
12988 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12989 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12990 (const_int 0)))
12991 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12992 (lt:SI (match_dup 1) (match_dup 2)))]
12993 "TARGET_POWER"
12994 "@
12995 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12996 #"
12997 [(set_attr "type" "delayed_compare")
12998 (set_attr "length" "12,16")])
12999
13000 (define_split
13001 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13002 (compare:CC
13003 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13004 (match_operand:SI 2 "reg_or_short_operand" ""))
13005 (const_int 0)))
13006 (set (match_operand:SI 0 "gpc_reg_operand" "")
13007 (lt:SI (match_dup 1) (match_dup 2)))]
13008 "TARGET_POWER && reload_completed"
13009 [(set (match_dup 0)
13010 (lt:SI (match_dup 1) (match_dup 2)))
13011 (set (match_dup 3)
13012 (compare:CC (match_dup 0)
13013 (const_int 0)))]
13014 "")
13015
13016 (define_insn ""
13017 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13018 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13019 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13020 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13021 "TARGET_POWER"
13022 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13023 [(set_attr "length" "12")])
13024
13025 (define_insn ""
13026 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13027 (compare:CC
13028 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13029 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13030 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13031 (const_int 0)))
13032 (clobber (match_scratch:SI 4 "=&r,&r"))]
13033 "TARGET_POWER"
13034 "@
13035 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13036 #"
13037 [(set_attr "type" "compare")
13038 (set_attr "length" "12,16")])
13039
13040 (define_split
13041 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13042 (compare:CC
13043 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13044 (match_operand:SI 2 "reg_or_short_operand" ""))
13045 (match_operand:SI 3 "gpc_reg_operand" ""))
13046 (const_int 0)))
13047 (clobber (match_scratch:SI 4 ""))]
13048 "TARGET_POWER && reload_completed"
13049 [(set (match_dup 4)
13050 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
13051 (match_dup 3)))
13052 (set (match_dup 0)
13053 (compare:CC (match_dup 4)
13054 (const_int 0)))]
13055 "")
13056
13057 (define_insn ""
13058 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13059 (compare:CC
13060 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13061 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13062 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13063 (const_int 0)))
13064 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13065 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13066 "TARGET_POWER"
13067 "@
13068 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13069 #"
13070 [(set_attr "type" "compare")
13071 (set_attr "length" "12,16")])
13072
13073 (define_split
13074 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13075 (compare:CC
13076 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13077 (match_operand:SI 2 "reg_or_short_operand" ""))
13078 (match_operand:SI 3 "gpc_reg_operand" ""))
13079 (const_int 0)))
13080 (set (match_operand:SI 0 "gpc_reg_operand" "")
13081 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13082 "TARGET_POWER && reload_completed"
13083 [(set (match_dup 0)
13084 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13085 (set (match_dup 4)
13086 (compare:CC (match_dup 0)
13087 (const_int 0)))]
13088 "")
13089
13090 (define_insn ""
13091 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13092 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13093 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13094 "TARGET_POWER"
13095 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13096 [(set_attr "length" "12")])
13097
13098 (define_insn_and_split "*ltu<mode>"
13099 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13100 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13101 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13102 ""
13103 "#"
13104 ""
13105 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13106 (set (match_dup 0) (neg:P (match_dup 0)))]
13107 "")
13108
13109 (define_insn_and_split "*ltu<mode>_compare"
13110 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13111 (compare:CC
13112 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13113 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13114 (const_int 0)))
13115 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13116 (ltu:P (match_dup 1) (match_dup 2)))]
13117 ""
13118 "#"
13119 ""
13120 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13121 (parallel [(set (match_dup 3)
13122 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13123 (set (match_dup 0) (neg:P (match_dup 0)))])]
13124 "")
13125
13126 (define_insn_and_split "*plus_ltu<mode>"
13127 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
13128 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13129 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13130 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
13131 ""
13132 "#"
13133 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13134 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13135 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13136 "")
13137
13138 (define_insn_and_split "*plus_ltu<mode>_compare"
13139 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13140 (compare:CC
13141 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13142 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13143 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13144 (const_int 0)))
13145 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13146 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13147 ""
13148 "#"
13149 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13150 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13151 (parallel [(set (match_dup 4)
13152 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13153 (const_int 0)))
13154 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13155 "")
13156
13157 (define_insn "*neg_ltu<mode>"
13158 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13159 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13160 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
13161 ""
13162 "@
13163 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
13164 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
13165 [(set_attr "type" "two")
13166 (set_attr "length" "8")])
13167
13168 (define_insn ""
13169 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13170 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13171 (match_operand:SI 2 "reg_or_short_operand" "rI")))
13172 (clobber (match_scratch:SI 3 "=r"))]
13173 "TARGET_POWER"
13174 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
13175 [(set_attr "length" "12")])
13176
13177 (define_insn ""
13178 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13179 (compare:CC
13180 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13181 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13182 (const_int 0)))
13183 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13184 (ge:SI (match_dup 1) (match_dup 2)))
13185 (clobber (match_scratch:SI 3 "=r,r"))]
13186 "TARGET_POWER"
13187 "@
13188 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13189 #"
13190 [(set_attr "type" "compare")
13191 (set_attr "length" "12,16")])
13192
13193 (define_split
13194 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13195 (compare:CC
13196 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13197 (match_operand:SI 2 "reg_or_short_operand" ""))
13198 (const_int 0)))
13199 (set (match_operand:SI 0 "gpc_reg_operand" "")
13200 (ge:SI (match_dup 1) (match_dup 2)))
13201 (clobber (match_scratch:SI 3 ""))]
13202 "TARGET_POWER && reload_completed"
13203 [(parallel [(set (match_dup 0)
13204 (ge:SI (match_dup 1) (match_dup 2)))
13205 (clobber (match_dup 3))])
13206 (set (match_dup 4)
13207 (compare:CC (match_dup 0)
13208 (const_int 0)))]
13209 "")
13210
13211 (define_insn ""
13212 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13213 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13214 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13215 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13216 "TARGET_POWER"
13217 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
13218 [(set_attr "length" "12")])
13219
13220 (define_insn ""
13221 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13222 (compare:CC
13223 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13224 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13225 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13226 (const_int 0)))
13227 (clobber (match_scratch:SI 4 "=&r,&r"))]
13228 "TARGET_POWER"
13229 "@
13230 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13231 #"
13232 [(set_attr "type" "compare")
13233 (set_attr "length" "12,16")])
13234
13235 (define_split
13236 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13237 (compare:CC
13238 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13239 (match_operand:SI 2 "reg_or_short_operand" ""))
13240 (match_operand:SI 3 "gpc_reg_operand" ""))
13241 (const_int 0)))
13242 (clobber (match_scratch:SI 4 ""))]
13243 "TARGET_POWER && reload_completed"
13244 [(set (match_dup 4)
13245 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
13246 (match_dup 3)))
13247 (set (match_dup 0)
13248 (compare:CC (match_dup 4)
13249 (const_int 0)))]
13250 "")
13251
13252 (define_insn ""
13253 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13254 (compare:CC
13255 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13256 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13257 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13258 (const_int 0)))
13259 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13260 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13261 "TARGET_POWER"
13262 "@
13263 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13264 #"
13265 [(set_attr "type" "compare")
13266 (set_attr "length" "12,16")])
13267
13268 (define_split
13269 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13270 (compare:CC
13271 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13272 (match_operand:SI 2 "reg_or_short_operand" ""))
13273 (match_operand:SI 3 "gpc_reg_operand" ""))
13274 (const_int 0)))
13275 (set (match_operand:SI 0 "gpc_reg_operand" "")
13276 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13277 "TARGET_POWER && reload_completed"
13278 [(set (match_dup 0)
13279 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13280 (set (match_dup 4)
13281 (compare:CC (match_dup 0)
13282 (const_int 0)))]
13283 "")
13284
13285 (define_insn ""
13286 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13287 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13288 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13289 "TARGET_POWER"
13290 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
13291 [(set_attr "length" "12")])
13292
13293 (define_insn "*geu<mode>"
13294 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13295 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13296 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13297 ""
13298 "@
13299 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
13300 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
13301 [(set_attr "type" "three")
13302 (set_attr "length" "12")])
13303
13304 (define_insn "*geu<mode>_compare"
13305 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13306 (compare:CC
13307 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13308 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13309 (const_int 0)))
13310 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13311 (geu:P (match_dup 1) (match_dup 2)))]
13312 ""
13313 "@
13314 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13315 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13316 #
13317 #"
13318 [(set_attr "type" "compare")
13319 (set_attr "length" "12,12,16,16")])
13320
13321 (define_split
13322 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13323 (compare:CC
13324 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
13325 (match_operand:P 2 "reg_or_neg_short_operand" ""))
13326 (const_int 0)))
13327 (set (match_operand:P 0 "gpc_reg_operand" "")
13328 (geu:P (match_dup 1) (match_dup 2)))]
13329 "reload_completed"
13330 [(set (match_dup 0)
13331 (geu:P (match_dup 1) (match_dup 2)))
13332 (set (match_dup 3)
13333 (compare:CC (match_dup 0)
13334 (const_int 0)))]
13335 "")
13336
13337 (define_insn "*plus_geu<mode>"
13338 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13339 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13340 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13341 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13342 ""
13343 "@
13344 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
13345 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
13346 [(set_attr "type" "two")
13347 (set_attr "length" "8")])
13348
13349 (define_insn ""
13350 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13351 (compare:CC
13352 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13353 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13354 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13355 (const_int 0)))
13356 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13357 "TARGET_32BIT"
13358 "@
13359 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
13360 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
13361 #
13362 #"
13363 [(set_attr "type" "compare")
13364 (set_attr "length" "8,8,12,12")])
13365
13366 (define_split
13367 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13368 (compare:CC
13369 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13370 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13371 (match_operand:SI 3 "gpc_reg_operand" ""))
13372 (const_int 0)))
13373 (clobber (match_scratch:SI 4 ""))]
13374 "TARGET_32BIT && reload_completed"
13375 [(set (match_dup 4)
13376 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13377 (match_dup 3)))
13378 (set (match_dup 0)
13379 (compare:CC (match_dup 4)
13380 (const_int 0)))]
13381 "")
13382
13383 (define_insn ""
13384 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13385 (compare:CC
13386 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13387 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13388 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13389 (const_int 0)))
13390 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13391 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13392 "TARGET_32BIT"
13393 "@
13394 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
13395 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
13396 #
13397 #"
13398 [(set_attr "type" "compare")
13399 (set_attr "length" "8,8,12,12")])
13400
13401 (define_split
13402 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13403 (compare:CC
13404 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13405 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13406 (match_operand:SI 3 "gpc_reg_operand" ""))
13407 (const_int 0)))
13408 (set (match_operand:SI 0 "gpc_reg_operand" "")
13409 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13410 "TARGET_32BIT && reload_completed"
13411 [(set (match_dup 0)
13412 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13413 (set (match_dup 4)
13414 (compare:CC (match_dup 0)
13415 (const_int 0)))]
13416 "")
13417
13418 (define_insn "*neg_geu<mode>"
13419 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13420 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13421 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13422 ""
13423 "@
13424 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
13425 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
13426 [(set_attr "type" "three")
13427 (set_attr "length" "12")])
13428
13429 (define_insn "*and_neg_geu<mode>"
13430 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13431 (and:P (neg:P
13432 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13433 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13434 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13435 ""
13436 "@
13437 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
13438 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13439 [(set_attr "type" "three")
13440 (set_attr "length" "12")])
13441
13442 (define_insn ""
13443 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13444 (compare:CC
13445 (and:SI (neg:SI
13446 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13447 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13448 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13449 (const_int 0)))
13450 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13451 "TARGET_32BIT"
13452 "@
13453 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13454 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13455 #
13456 #"
13457 [(set_attr "type" "compare")
13458 (set_attr "length" "12,12,16,16")])
13459
13460 (define_split
13461 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13462 (compare:CC
13463 (and:SI (neg:SI
13464 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13465 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13466 (match_operand:SI 3 "gpc_reg_operand" ""))
13467 (const_int 0)))
13468 (clobber (match_scratch:SI 4 ""))]
13469 "TARGET_32BIT && reload_completed"
13470 [(set (match_dup 4)
13471 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13472 (match_dup 3)))
13473 (set (match_dup 0)
13474 (compare:CC (match_dup 4)
13475 (const_int 0)))]
13476 "")
13477
13478 (define_insn ""
13479 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13480 (compare:CC
13481 (and:SI (neg:SI
13482 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13483 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13484 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13485 (const_int 0)))
13486 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13487 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13488 "TARGET_32BIT"
13489 "@
13490 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13491 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13492 #
13493 #"
13494 [(set_attr "type" "compare")
13495 (set_attr "length" "12,12,16,16")])
13496
13497 (define_split
13498 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13499 (compare:CC
13500 (and:SI (neg:SI
13501 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13502 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13503 (match_operand:SI 3 "gpc_reg_operand" ""))
13504 (const_int 0)))
13505 (set (match_operand:SI 0 "gpc_reg_operand" "")
13506 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13507 "TARGET_32BIT && reload_completed"
13508 [(set (match_dup 0)
13509 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13510 (set (match_dup 4)
13511 (compare:CC (match_dup 0)
13512 (const_int 0)))]
13513 "")
13514
13515 (define_insn ""
13516 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13517 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13518 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13519 "TARGET_POWER"
13520 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13521 [(set_attr "length" "12")])
13522
13523 (define_insn ""
13524 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13525 (compare:CC
13526 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13527 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13528 (const_int 0)))
13529 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13530 (gt:SI (match_dup 1) (match_dup 2)))]
13531 "TARGET_POWER"
13532 "@
13533 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13534 #"
13535 [(set_attr "type" "delayed_compare")
13536 (set_attr "length" "12,16")])
13537
13538 (define_split
13539 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13540 (compare:CC
13541 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13542 (match_operand:SI 2 "reg_or_short_operand" ""))
13543 (const_int 0)))
13544 (set (match_operand:SI 0 "gpc_reg_operand" "")
13545 (gt:SI (match_dup 1) (match_dup 2)))]
13546 "TARGET_POWER && reload_completed"
13547 [(set (match_dup 0)
13548 (gt:SI (match_dup 1) (match_dup 2)))
13549 (set (match_dup 3)
13550 (compare:CC (match_dup 0)
13551 (const_int 0)))]
13552 "")
13553
13554 (define_insn "*plus_gt0<mode>"
13555 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13556 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13557 (const_int 0))
13558 (match_operand:P 2 "gpc_reg_operand" "r")))]
13559 ""
13560 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13561 [(set_attr "type" "three")
13562 (set_attr "length" "12")])
13563
13564 (define_insn ""
13565 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13566 (compare:CC
13567 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13568 (const_int 0))
13569 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13570 (const_int 0)))
13571 (clobber (match_scratch:SI 3 "=&r,&r"))]
13572 "TARGET_32BIT"
13573 "@
13574 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13575 #"
13576 [(set_attr "type" "compare")
13577 (set_attr "length" "12,16")])
13578
13579 (define_split
13580 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13581 (compare:CC
13582 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13583 (const_int 0))
13584 (match_operand:SI 2 "gpc_reg_operand" ""))
13585 (const_int 0)))
13586 (clobber (match_scratch:SI 3 ""))]
13587 "TARGET_32BIT && reload_completed"
13588 [(set (match_dup 3)
13589 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13590 (match_dup 2)))
13591 (set (match_dup 0)
13592 (compare:CC (match_dup 3)
13593 (const_int 0)))]
13594 "")
13595
13596 (define_insn ""
13597 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13598 (compare:CC
13599 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13600 (const_int 0))
13601 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13602 (const_int 0)))
13603 (clobber (match_scratch:DI 3 "=&r,&r"))]
13604 "TARGET_64BIT"
13605 "@
13606 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13607 #"
13608 [(set_attr "type" "compare")
13609 (set_attr "length" "12,16")])
13610
13611 (define_split
13612 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13613 (compare:CC
13614 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13615 (const_int 0))
13616 (match_operand:DI 2 "gpc_reg_operand" ""))
13617 (const_int 0)))
13618 (clobber (match_scratch:DI 3 ""))]
13619 "TARGET_64BIT && reload_completed"
13620 [(set (match_dup 3)
13621 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13622 (match_dup 2)))
13623 (set (match_dup 0)
13624 (compare:CC (match_dup 3)
13625 (const_int 0)))]
13626 "")
13627
13628 (define_insn ""
13629 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13630 (compare:CC
13631 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13632 (const_int 0))
13633 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13634 (const_int 0)))
13635 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13636 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13637 "TARGET_32BIT"
13638 "@
13639 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13640 #"
13641 [(set_attr "type" "compare")
13642 (set_attr "length" "12,16")])
13643
13644 (define_split
13645 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13646 (compare:CC
13647 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13648 (const_int 0))
13649 (match_operand:SI 2 "gpc_reg_operand" ""))
13650 (const_int 0)))
13651 (set (match_operand:SI 0 "gpc_reg_operand" "")
13652 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13653 "TARGET_32BIT && reload_completed"
13654 [(set (match_dup 0)
13655 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13656 (set (match_dup 3)
13657 (compare:CC (match_dup 0)
13658 (const_int 0)))]
13659 "")
13660
13661 (define_insn ""
13662 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13663 (compare:CC
13664 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13665 (const_int 0))
13666 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13667 (const_int 0)))
13668 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13669 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13670 "TARGET_64BIT"
13671 "@
13672 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13673 #"
13674 [(set_attr "type" "compare")
13675 (set_attr "length" "12,16")])
13676
13677 (define_split
13678 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13679 (compare:CC
13680 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13681 (const_int 0))
13682 (match_operand:DI 2 "gpc_reg_operand" ""))
13683 (const_int 0)))
13684 (set (match_operand:DI 0 "gpc_reg_operand" "")
13685 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13686 "TARGET_64BIT && reload_completed"
13687 [(set (match_dup 0)
13688 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13689 (set (match_dup 3)
13690 (compare:CC (match_dup 0)
13691 (const_int 0)))]
13692 "")
13693
13694 (define_insn ""
13695 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13696 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13697 (match_operand:SI 2 "reg_or_short_operand" "r"))
13698 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13699 "TARGET_POWER"
13700 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13701 [(set_attr "length" "12")])
13702
13703 (define_insn ""
13704 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13705 (compare:CC
13706 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13707 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13708 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13709 (const_int 0)))
13710 (clobber (match_scratch:SI 4 "=&r,&r"))]
13711 "TARGET_POWER"
13712 "@
13713 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13714 #"
13715 [(set_attr "type" "compare")
13716 (set_attr "length" "12,16")])
13717
13718 (define_split
13719 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13720 (compare:CC
13721 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13722 (match_operand:SI 2 "reg_or_short_operand" ""))
13723 (match_operand:SI 3 "gpc_reg_operand" ""))
13724 (const_int 0)))
13725 (clobber (match_scratch:SI 4 ""))]
13726 "TARGET_POWER && reload_completed"
13727 [(set (match_dup 4)
13728 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13729 (set (match_dup 0)
13730 (compare:CC (match_dup 4)
13731 (const_int 0)))]
13732 "")
13733
13734 (define_insn ""
13735 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13736 (compare:CC
13737 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13738 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13739 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13740 (const_int 0)))
13741 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13742 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13743 "TARGET_POWER"
13744 "@
13745 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13746 #"
13747 [(set_attr "type" "compare")
13748 (set_attr "length" "12,16")])
13749
13750 (define_split
13751 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13752 (compare:CC
13753 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13754 (match_operand:SI 2 "reg_or_short_operand" ""))
13755 (match_operand:SI 3 "gpc_reg_operand" ""))
13756 (const_int 0)))
13757 (set (match_operand:SI 0 "gpc_reg_operand" "")
13758 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13759 "TARGET_POWER && reload_completed"
13760 [(set (match_dup 0)
13761 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13762 (set (match_dup 4)
13763 (compare:CC (match_dup 0)
13764 (const_int 0)))]
13765 "")
13766
13767 (define_insn ""
13768 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13769 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13770 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13771 "TARGET_POWER"
13772 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13773 [(set_attr "length" "12")])
13774
13775 (define_insn_and_split "*gtu<mode>"
13776 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13777 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13778 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13779 ""
13780 "#"
13781 ""
13782 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13783 (set (match_dup 0) (neg:P (match_dup 0)))]
13784 "")
13785
13786 (define_insn_and_split "*gtu<mode>_compare"
13787 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13788 (compare:CC
13789 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13790 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13791 (const_int 0)))
13792 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13793 (gtu:P (match_dup 1) (match_dup 2)))]
13794 ""
13795 "#"
13796 ""
13797 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13798 (parallel [(set (match_dup 3)
13799 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13800 (set (match_dup 0) (neg:P (match_dup 0)))])]
13801 "")
13802
13803 (define_insn_and_split "*plus_gtu<mode>"
13804 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13805 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13806 (match_operand:P 2 "reg_or_short_operand" "rI"))
13807 (match_operand:P 3 "reg_or_short_operand" "rI")))]
13808 ""
13809 "#"
13810 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13811 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13812 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13813 "")
13814
13815 (define_insn_and_split "*plus_gtu<mode>_compare"
13816 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13817 (compare:CC
13818 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13819 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13820 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13821 (const_int 0)))
13822 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13823 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13824 ""
13825 "#"
13826 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13827 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13828 (parallel [(set (match_dup 4)
13829 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13830 (const_int 0)))
13831 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13832 "")
13833
13834 (define_insn "*neg_gtu<mode>"
13835 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13836 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13837 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13838 ""
13839 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13840 [(set_attr "type" "two")
13841 (set_attr "length" "8")])
13842
13843 \f
13844 ;; Define both directions of branch and return. If we need a reload
13845 ;; register, we'd rather use CR0 since it is much easier to copy a
13846 ;; register CC value to there.
13847
13848 (define_insn ""
13849 [(set (pc)
13850 (if_then_else (match_operator 1 "branch_comparison_operator"
13851 [(match_operand 2
13852 "cc_reg_operand" "y")
13853 (const_int 0)])
13854 (label_ref (match_operand 0 "" ""))
13855 (pc)))]
13856 ""
13857 "*
13858 {
13859 return output_cbranch (operands[1], \"%l0\", 0, insn);
13860 }"
13861 [(set_attr "type" "branch")])
13862
13863 (define_insn ""
13864 [(set (pc)
13865 (if_then_else (match_operator 0 "branch_comparison_operator"
13866 [(match_operand 1
13867 "cc_reg_operand" "y")
13868 (const_int 0)])
13869 (return)
13870 (pc)))]
13871 "direct_return ()"
13872 "*
13873 {
13874 return output_cbranch (operands[0], NULL, 0, insn);
13875 }"
13876 [(set_attr "type" "jmpreg")
13877 (set_attr "length" "4")])
13878
13879 (define_insn ""
13880 [(set (pc)
13881 (if_then_else (match_operator 1 "branch_comparison_operator"
13882 [(match_operand 2
13883 "cc_reg_operand" "y")
13884 (const_int 0)])
13885 (pc)
13886 (label_ref (match_operand 0 "" ""))))]
13887 ""
13888 "*
13889 {
13890 return output_cbranch (operands[1], \"%l0\", 1, insn);
13891 }"
13892 [(set_attr "type" "branch")])
13893
13894 (define_insn ""
13895 [(set (pc)
13896 (if_then_else (match_operator 0 "branch_comparison_operator"
13897 [(match_operand 1
13898 "cc_reg_operand" "y")
13899 (const_int 0)])
13900 (pc)
13901 (return)))]
13902 "direct_return ()"
13903 "*
13904 {
13905 return output_cbranch (operands[0], NULL, 1, insn);
13906 }"
13907 [(set_attr "type" "jmpreg")
13908 (set_attr "length" "4")])
13909
13910 ;; Logic on condition register values.
13911
13912 ; This pattern matches things like
13913 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13914 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13915 ; (const_int 1)))
13916 ; which are generated by the branch logic.
13917 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13918
13919 (define_insn "*cceq_ior_compare"
13920 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13921 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13922 [(match_operator:SI 2
13923 "branch_positive_comparison_operator"
13924 [(match_operand 3
13925 "cc_reg_operand" "y,y")
13926 (const_int 0)])
13927 (match_operator:SI 4
13928 "branch_positive_comparison_operator"
13929 [(match_operand 5
13930 "cc_reg_operand" "0,y")
13931 (const_int 0)])])
13932 (const_int 1)))]
13933 ""
13934 "cr%q1 %E0,%j2,%j4"
13935 [(set_attr "type" "cr_logical,delayed_cr")])
13936
13937 ; Why is the constant -1 here, but 1 in the previous pattern?
13938 ; Because ~1 has all but the low bit set.
13939 (define_insn ""
13940 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13941 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13942 [(not:SI (match_operator:SI 2
13943 "branch_positive_comparison_operator"
13944 [(match_operand 3
13945 "cc_reg_operand" "y,y")
13946 (const_int 0)]))
13947 (match_operator:SI 4
13948 "branch_positive_comparison_operator"
13949 [(match_operand 5
13950 "cc_reg_operand" "0,y")
13951 (const_int 0)])])
13952 (const_int -1)))]
13953 ""
13954 "cr%q1 %E0,%j2,%j4"
13955 [(set_attr "type" "cr_logical,delayed_cr")])
13956
13957 (define_insn "*cceq_rev_compare"
13958 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13959 (compare:CCEQ (match_operator:SI 1
13960 "branch_positive_comparison_operator"
13961 [(match_operand 2
13962 "cc_reg_operand" "0,y")
13963 (const_int 0)])
13964 (const_int 0)))]
13965 ""
13966 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
13967 [(set_attr "type" "cr_logical,delayed_cr")])
13968
13969 ;; If we are comparing the result of two comparisons, this can be done
13970 ;; using creqv or crxor.
13971
13972 (define_insn_and_split ""
13973 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13974 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13975 [(match_operand 2 "cc_reg_operand" "y")
13976 (const_int 0)])
13977 (match_operator 3 "branch_comparison_operator"
13978 [(match_operand 4 "cc_reg_operand" "y")
13979 (const_int 0)])))]
13980 ""
13981 "#"
13982 ""
13983 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13984 (match_dup 5)))]
13985 "
13986 {
13987 int positive_1, positive_2;
13988
13989 positive_1 = branch_positive_comparison_operator (operands[1],
13990 GET_MODE (operands[1]));
13991 positive_2 = branch_positive_comparison_operator (operands[3],
13992 GET_MODE (operands[3]));
13993
13994 if (! positive_1)
13995 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13996 GET_CODE (operands[1])),
13997 SImode,
13998 operands[2], const0_rtx);
13999 else if (GET_MODE (operands[1]) != SImode)
14000 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14001 operands[2], const0_rtx);
14002
14003 if (! positive_2)
14004 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
14005 GET_CODE (operands[3])),
14006 SImode,
14007 operands[4], const0_rtx);
14008 else if (GET_MODE (operands[3]) != SImode)
14009 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14010 operands[4], const0_rtx);
14011
14012 if (positive_1 == positive_2)
14013 {
14014 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14015 operands[5] = constm1_rtx;
14016 }
14017 else
14018 {
14019 operands[5] = const1_rtx;
14020 }
14021 }")
14022
14023 ;; Unconditional branch and return.
14024
14025 (define_insn "jump"
14026 [(set (pc)
14027 (label_ref (match_operand 0 "" "")))]
14028 ""
14029 "b %l0"
14030 [(set_attr "type" "branch")])
14031
14032 (define_insn "return"
14033 [(return)]
14034 "direct_return ()"
14035 "{br|blr}"
14036 [(set_attr "type" "jmpreg")])
14037
14038 (define_expand "indirect_jump"
14039 [(set (pc) (match_operand 0 "register_operand" ""))])
14040
14041 (define_insn "*indirect_jump<mode>"
14042 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14043 ""
14044 "@
14045 bctr
14046 {br|blr}"
14047 [(set_attr "type" "jmpreg")])
14048
14049 ;; Table jump for switch statements:
14050 (define_expand "tablejump"
14051 [(use (match_operand 0 "" ""))
14052 (use (label_ref (match_operand 1 "" "")))]
14053 ""
14054 "
14055 {
14056 if (TARGET_32BIT)
14057 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14058 else
14059 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14060 DONE;
14061 }")
14062
14063 (define_expand "tablejumpsi"
14064 [(set (match_dup 3)
14065 (plus:SI (match_operand:SI 0 "" "")
14066 (match_dup 2)))
14067 (parallel [(set (pc) (match_dup 3))
14068 (use (label_ref (match_operand 1 "" "")))])]
14069 "TARGET_32BIT"
14070 "
14071 { operands[0] = force_reg (SImode, operands[0]);
14072 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
14073 operands[3] = gen_reg_rtx (SImode);
14074 }")
14075
14076 (define_expand "tablejumpdi"
14077 [(set (match_dup 4)
14078 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
14079 (set (match_dup 3)
14080 (plus:DI (match_dup 4)
14081 (match_dup 2)))
14082 (parallel [(set (pc) (match_dup 3))
14083 (use (label_ref (match_operand 1 "" "")))])]
14084 "TARGET_64BIT"
14085 "
14086 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
14087 operands[3] = gen_reg_rtx (DImode);
14088 operands[4] = gen_reg_rtx (DImode);
14089 }")
14090
14091 (define_insn "*tablejump<mode>_internal1"
14092 [(set (pc)
14093 (match_operand:P 0 "register_operand" "c,*l"))
14094 (use (label_ref (match_operand 1 "" "")))]
14095 ""
14096 "@
14097 bctr
14098 {br|blr}"
14099 [(set_attr "type" "jmpreg")])
14100
14101 (define_insn "nop"
14102 [(const_int 0)]
14103 ""
14104 "{cror 0,0,0|nop}")
14105 \f
14106 ;; Define the subtract-one-and-jump insns, starting with the template
14107 ;; so loop.c knows what to generate.
14108
14109 (define_expand "doloop_end"
14110 [(use (match_operand 0 "" "")) ; loop pseudo
14111 (use (match_operand 1 "" "")) ; iterations; zero if unknown
14112 (use (match_operand 2 "" "")) ; max iterations
14113 (use (match_operand 3 "" "")) ; loop level
14114 (use (match_operand 4 "" ""))] ; label
14115 ""
14116 "
14117 {
14118 /* Only use this on innermost loops. */
14119 if (INTVAL (operands[3]) > 1)
14120 FAIL;
14121 if (TARGET_64BIT)
14122 {
14123 if (GET_MODE (operands[0]) != DImode)
14124 FAIL;
14125 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
14126 }
14127 else
14128 {
14129 if (GET_MODE (operands[0]) != SImode)
14130 FAIL;
14131 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
14132 }
14133 DONE;
14134 }")
14135
14136 (define_expand "ctr<mode>"
14137 [(parallel [(set (pc)
14138 (if_then_else (ne (match_operand:P 0 "register_operand" "")
14139 (const_int 1))
14140 (label_ref (match_operand 1 "" ""))
14141 (pc)))
14142 (set (match_dup 0)
14143 (plus:P (match_dup 0)
14144 (const_int -1)))
14145 (clobber (match_scratch:CC 2 ""))
14146 (clobber (match_scratch:P 3 ""))])]
14147 ""
14148 "")
14149
14150 ;; We need to be able to do this for any operand, including MEM, or we
14151 ;; will cause reload to blow up since we don't allow output reloads on
14152 ;; JUMP_INSNs.
14153 ;; For the length attribute to be calculated correctly, the
14154 ;; label MUST be operand 0.
14155
14156 (define_insn "*ctr<mode>_internal1"
14157 [(set (pc)
14158 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14159 (const_int 1))
14160 (label_ref (match_operand 0 "" ""))
14161 (pc)))
14162 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14163 (plus:P (match_dup 1)
14164 (const_int -1)))
14165 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14166 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14167 ""
14168 "*
14169 {
14170 if (which_alternative != 0)
14171 return \"#\";
14172 else if (get_attr_length (insn) == 4)
14173 return \"{bdn|bdnz} %l0\";
14174 else
14175 return \"bdz $+8\;b %l0\";
14176 }"
14177 [(set_attr "type" "branch")
14178 (set_attr "length" "*,12,16,16")])
14179
14180 (define_insn "*ctr<mode>_internal2"
14181 [(set (pc)
14182 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14183 (const_int 1))
14184 (pc)
14185 (label_ref (match_operand 0 "" ""))))
14186 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14187 (plus:P (match_dup 1)
14188 (const_int -1)))
14189 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14190 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14191 ""
14192 "*
14193 {
14194 if (which_alternative != 0)
14195 return \"#\";
14196 else if (get_attr_length (insn) == 4)
14197 return \"bdz %l0\";
14198 else
14199 return \"{bdn|bdnz} $+8\;b %l0\";
14200 }"
14201 [(set_attr "type" "branch")
14202 (set_attr "length" "*,12,16,16")])
14203
14204 ;; Similar but use EQ
14205
14206 (define_insn "*ctr<mode>_internal5"
14207 [(set (pc)
14208 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14209 (const_int 1))
14210 (label_ref (match_operand 0 "" ""))
14211 (pc)))
14212 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14213 (plus:P (match_dup 1)
14214 (const_int -1)))
14215 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14216 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14217 ""
14218 "*
14219 {
14220 if (which_alternative != 0)
14221 return \"#\";
14222 else if (get_attr_length (insn) == 4)
14223 return \"bdz %l0\";
14224 else
14225 return \"{bdn|bdnz} $+8\;b %l0\";
14226 }"
14227 [(set_attr "type" "branch")
14228 (set_attr "length" "*,12,16,16")])
14229
14230 (define_insn "*ctr<mode>_internal6"
14231 [(set (pc)
14232 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14233 (const_int 1))
14234 (pc)
14235 (label_ref (match_operand 0 "" ""))))
14236 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14237 (plus:P (match_dup 1)
14238 (const_int -1)))
14239 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14240 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14241 ""
14242 "*
14243 {
14244 if (which_alternative != 0)
14245 return \"#\";
14246 else if (get_attr_length (insn) == 4)
14247 return \"{bdn|bdnz} %l0\";
14248 else
14249 return \"bdz $+8\;b %l0\";
14250 }"
14251 [(set_attr "type" "branch")
14252 (set_attr "length" "*,12,16,16")])
14253
14254 ;; Now the splitters if we could not allocate the CTR register
14255
14256 (define_split
14257 [(set (pc)
14258 (if_then_else (match_operator 2 "comparison_operator"
14259 [(match_operand:P 1 "gpc_reg_operand" "")
14260 (const_int 1)])
14261 (match_operand 5 "" "")
14262 (match_operand 6 "" "")))
14263 (set (match_operand:P 0 "gpc_reg_operand" "")
14264 (plus:P (match_dup 1) (const_int -1)))
14265 (clobber (match_scratch:CC 3 ""))
14266 (clobber (match_scratch:P 4 ""))]
14267 "reload_completed"
14268 [(parallel [(set (match_dup 3)
14269 (compare:CC (plus:P (match_dup 1)
14270 (const_int -1))
14271 (const_int 0)))
14272 (set (match_dup 0)
14273 (plus:P (match_dup 1)
14274 (const_int -1)))])
14275 (set (pc) (if_then_else (match_dup 7)
14276 (match_dup 5)
14277 (match_dup 6)))]
14278 "
14279 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14280 operands[3], const0_rtx); }")
14281
14282 (define_split
14283 [(set (pc)
14284 (if_then_else (match_operator 2 "comparison_operator"
14285 [(match_operand:P 1 "gpc_reg_operand" "")
14286 (const_int 1)])
14287 (match_operand 5 "" "")
14288 (match_operand 6 "" "")))
14289 (set (match_operand:P 0 "nonimmediate_operand" "")
14290 (plus:P (match_dup 1) (const_int -1)))
14291 (clobber (match_scratch:CC 3 ""))
14292 (clobber (match_scratch:P 4 ""))]
14293 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
14294 [(parallel [(set (match_dup 3)
14295 (compare:CC (plus:P (match_dup 1)
14296 (const_int -1))
14297 (const_int 0)))
14298 (set (match_dup 4)
14299 (plus:P (match_dup 1)
14300 (const_int -1)))])
14301 (set (match_dup 0)
14302 (match_dup 4))
14303 (set (pc) (if_then_else (match_dup 7)
14304 (match_dup 5)
14305 (match_dup 6)))]
14306 "
14307 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14308 operands[3], const0_rtx); }")
14309 \f
14310 (define_insn "trap"
14311 [(trap_if (const_int 1) (const_int 0))]
14312 ""
14313 "{t 31,0,0|trap}"
14314 [(set_attr "type" "trap")])
14315
14316 (define_expand "conditional_trap"
14317 [(trap_if (match_operator 0 "trap_comparison_operator"
14318 [(match_dup 2) (match_dup 3)])
14319 (match_operand 1 "const_int_operand" ""))]
14320 ""
14321 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14322 operands[2] = rs6000_compare_op0;
14323 operands[3] = rs6000_compare_op1;")
14324
14325 (define_insn ""
14326 [(trap_if (match_operator 0 "trap_comparison_operator"
14327 [(match_operand:GPR 1 "register_operand" "r")
14328 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
14329 (const_int 0))]
14330 ""
14331 "{t|t<wd>}%V0%I2 %1,%2"
14332 [(set_attr "type" "trap")])
14333 \f
14334 ;; Insns related to generating the function prologue and epilogue.
14335
14336 (define_expand "prologue"
14337 [(use (const_int 0))]
14338 "TARGET_SCHED_PROLOG"
14339 "
14340 {
14341 rs6000_emit_prologue ();
14342 DONE;
14343 }")
14344
14345 (define_insn "*movesi_from_cr_one"
14346 [(match_parallel 0 "mfcr_operation"
14347 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14348 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14349 (match_operand 3 "immediate_operand" "n")]
14350 UNSPEC_MOVESI_FROM_CR))])]
14351 "TARGET_MFCRF"
14352 "*
14353 {
14354 int mask = 0;
14355 int i;
14356 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14357 {
14358 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14359 operands[4] = GEN_INT (mask);
14360 output_asm_insn (\"mfcr %1,%4\", operands);
14361 }
14362 return \"\";
14363 }"
14364 [(set_attr "type" "mfcrf")])
14365
14366 (define_insn "movesi_from_cr"
14367 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14368 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
14369 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
14370 UNSPEC_MOVESI_FROM_CR))]
14371 ""
14372 "mfcr %0"
14373 [(set_attr "type" "mfcr")])
14374
14375 (define_insn "*stmw"
14376 [(match_parallel 0 "stmw_operation"
14377 [(set (match_operand:SI 1 "memory_operand" "=m")
14378 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14379 "TARGET_MULTIPLE"
14380 "{stm|stmw} %2,%1"
14381 [(set_attr "type" "store_ux")])
14382
14383 (define_insn "*save_fpregs_<mode>"
14384 [(match_parallel 0 "any_parallel_operand"
14385 [(clobber (reg:P 65))
14386 (use (match_operand:P 1 "call_operand" "s"))
14387 (set (match_operand:DF 2 "memory_operand" "=m")
14388 (match_operand:DF 3 "gpc_reg_operand" "f"))])]
14389 ""
14390 "bl %z1"
14391 [(set_attr "type" "branch")
14392 (set_attr "length" "4")])
14393
14394 ; These are to explain that changes to the stack pointer should
14395 ; not be moved over stores to stack memory.
14396 (define_insn "stack_tie"
14397 [(set (match_operand:BLK 0 "memory_operand" "+m")
14398 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
14399 ""
14400 ""
14401 [(set_attr "length" "0")])
14402
14403
14404 (define_expand "epilogue"
14405 [(use (const_int 0))]
14406 "TARGET_SCHED_PROLOG"
14407 "
14408 {
14409 rs6000_emit_epilogue (FALSE);
14410 DONE;
14411 }")
14412
14413 ; On some processors, doing the mtcrf one CC register at a time is
14414 ; faster (like on the 604e). On others, doing them all at once is
14415 ; faster; for instance, on the 601 and 750.
14416
14417 (define_expand "movsi_to_cr_one"
14418 [(set (match_operand:CC 0 "cc_reg_operand" "")
14419 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
14420 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14421 ""
14422 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14423
14424 (define_insn "*movsi_to_cr"
14425 [(match_parallel 0 "mtcrf_operation"
14426 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14427 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14428 (match_operand 3 "immediate_operand" "n")]
14429 UNSPEC_MOVESI_TO_CR))])]
14430 ""
14431 "*
14432 {
14433 int mask = 0;
14434 int i;
14435 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14436 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14437 operands[4] = GEN_INT (mask);
14438 return \"mtcrf %4,%2\";
14439 }"
14440 [(set_attr "type" "mtcr")])
14441
14442 (define_insn "*mtcrfsi"
14443 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14444 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14445 (match_operand 2 "immediate_operand" "n")]
14446 UNSPEC_MOVESI_TO_CR))]
14447 "GET_CODE (operands[0]) == REG
14448 && CR_REGNO_P (REGNO (operands[0]))
14449 && GET_CODE (operands[2]) == CONST_INT
14450 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14451 "mtcrf %R0,%1"
14452 [(set_attr "type" "mtcr")])
14453
14454 ; The load-multiple instructions have similar properties.
14455 ; Note that "load_multiple" is a name known to the machine-independent
14456 ; code that actually corresponds to the PowerPC load-string.
14457
14458 (define_insn "*lmw"
14459 [(match_parallel 0 "lmw_operation"
14460 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14461 (match_operand:SI 2 "memory_operand" "m"))])]
14462 "TARGET_MULTIPLE"
14463 "{lm|lmw} %1,%2"
14464 [(set_attr "type" "load_ux")])
14465
14466 (define_insn "*return_internal_<mode>"
14467 [(return)
14468 (use (match_operand:P 0 "register_operand" "lc"))]
14469 ""
14470 "b%T0"
14471 [(set_attr "type" "jmpreg")])
14472
14473 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14474 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14475
14476 (define_insn "*return_and_restore_fpregs_<mode>"
14477 [(match_parallel 0 "any_parallel_operand"
14478 [(return)
14479 (use (reg:P 65))
14480 (use (match_operand:P 1 "call_operand" "s"))
14481 (set (match_operand:DF 2 "gpc_reg_operand" "=f")
14482 (match_operand:DF 3 "memory_operand" "m"))])]
14483 ""
14484 "b %z1")
14485
14486 ; This is used in compiling the unwind routines.
14487 (define_expand "eh_return"
14488 [(use (match_operand 0 "general_operand" ""))]
14489 ""
14490 "
14491 {
14492 if (TARGET_32BIT)
14493 emit_insn (gen_eh_set_lr_si (operands[0]));
14494 else
14495 emit_insn (gen_eh_set_lr_di (operands[0]));
14496 DONE;
14497 }")
14498
14499 ; We can't expand this before we know where the link register is stored.
14500 (define_insn "eh_set_lr_<mode>"
14501 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
14502 UNSPECV_EH_RR)
14503 (clobber (match_scratch:P 1 "=&b"))]
14504 ""
14505 "#")
14506
14507 (define_split
14508 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14509 (clobber (match_scratch 1 ""))]
14510 "reload_completed"
14511 [(const_int 0)]
14512 "
14513 {
14514 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14515 DONE;
14516 }")
14517
14518 (define_insn "prefetch"
14519 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
14520 (match_operand:SI 1 "const_int_operand" "n")
14521 (match_operand:SI 2 "const_int_operand" "n"))]
14522 "TARGET_POWERPC"
14523 "*
14524 {
14525 if (GET_CODE (operands[0]) == REG)
14526 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14527 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14528 }"
14529 [(set_attr "type" "load")])
14530 \f
14531
14532 (include "sync.md")
14533 (include "altivec.md")
14534 (include "spe.md")
14535 (include "dfp.md")
Mirror of https://gcc.gnu.org/git/gcc.git