1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 3, or (at your
12 ;; option) any later version.
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
43 (FIRST_ALTIVEC_REGNO 77)
44 (LAST_ALTIVEC_REGNO 108)
57 [(UNSPEC_FRSP 0) ; frsp for POWER machines
58 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
59 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
60 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
62 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
68 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
69 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
72 (UNSPEC_MOVESI_FROM_CR 19)
73 (UNSPEC_MOVESI_TO_CR 20)
75 (UNSPEC_TLSDTPRELHA 22)
76 (UNSPEC_TLSDTPRELLO 23)
77 (UNSPEC_TLSGOTDTPREL 24)
79 (UNSPEC_TLSTPRELHA 26)
80 (UNSPEC_TLSTPRELLO 27)
81 (UNSPEC_TLSGOTTPREL 28)
83 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
84 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
100 (UNSPEC_DLMZB_STRLEN 47)
105 ;; UNSPEC_VOLATILE usage
110 (UNSPECV_LL 1) ; load-locked
111 (UNSPECV_SC 2) ; store-conditional
112 (UNSPECV_EH_RR 9) ; eh_reg_restore
115 ;; Define an insn type attribute. This is used in function unit delay
117 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr"
118 (const_string "integer"))
120 ;; Length (in bytes).
121 ; '(pc)' in the following doesn't include the instruction itself; it is
122 ; calculated as if the instruction had zero size.
123 (define_attr "length" ""
124 (if_then_else (eq_attr "type" "branch")
125 (if_then_else (and (ge (minus (match_dup 0) (pc))
127 (lt (minus (match_dup 0) (pc))
133 ;; Processor type -- this attribute must exactly match the processor_type
134 ;; enumeration in rs6000.h.
136 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,power4,power5,power6,cell"
137 (const (symbol_ref "rs6000_cpu_attr")))
140 ;; If this instruction is microcoded on the CELL processor
141 ; The default for load and stores is conditional
142 ; The default for load extended and the recorded instructions is always microcoded
143 (define_attr "cell_micro" "not,conditional,always"
144 (if_then_else (ior (ior (eq_attr "type" "load")
145 (eq_attr "type" "store"))
146 (ior (eq_attr "type" "fpload")
147 (eq_attr "type" "fpstore")))
148 (const_string "conditional")
149 (if_then_else (ior (eq_attr "type" "load_ext")
150 (ior (eq_attr "type" "compare")
151 (eq_attr "type" "delayed_compare")))
152 (const_string "always")
153 (const_string "not"))))
156 (automata_option "ndfa")
169 (include "e300c2c3.md")
170 (include "e500mc.md")
171 (include "power4.md")
172 (include "power5.md")
173 (include "power6.md")
176 (include "predicates.md")
177 (include "constraints.md")
179 (include "darwin.md")
184 ; This mode iterator allows :GPR to be used to indicate the allowable size
185 ; of whole values in GPRs.
186 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
188 ; Any supported integer mode.
189 (define_mode_iterator INT [QI HI SI DI TI])
191 ; Any supported integer mode that fits in one register.
192 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
194 ; extend modes for DImode
195 (define_mode_iterator QHSI [QI HI SI])
197 ; SImode or DImode, even if DImode doesn't fit in GPRs.
198 (define_mode_iterator SDI [SI DI])
200 ; The size of a pointer. Also, the size of the value that a record-condition
201 ; (one with a '.') will compare.
202 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
204 ; Any hardware-supported floating-point mode
205 (define_mode_iterator FP [(SF "TARGET_HARD_FLOAT")
206 (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
207 (TF "!TARGET_IEEEQUAD
209 && (TARGET_FPRS || TARGET_E500_DOUBLE)
210 && TARGET_LONG_DOUBLE_128")
214 ; Various instructions that come in SI and DI forms.
215 ; A generic w/d attribute, for things like cmpw/cmpd.
216 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
219 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
222 ;; Start with fixed-point load and store insns. Here we put only the more
223 ;; complex forms. Basic data transfer is done later.
225 (define_expand "zero_extend<mode>di2"
226 [(set (match_operand:DI 0 "gpc_reg_operand" "")
227 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
231 (define_insn "*zero_extend<mode>di2_internal1"
232 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
233 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
237 rldicl %0,%1,0,<dbits>"
238 [(set_attr "type" "load,*")])
240 (define_insn "*zero_extend<mode>di2_internal2"
241 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
242 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
244 (clobber (match_scratch:DI 2 "=r,r"))]
247 rldicl. %2,%1,0,<dbits>
249 [(set_attr "type" "compare")
250 (set_attr "length" "4,8")])
253 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
254 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
256 (clobber (match_scratch:DI 2 ""))]
257 "TARGET_POWERPC64 && reload_completed"
259 (zero_extend:DI (match_dup 1)))
261 (compare:CC (match_dup 2)
265 (define_insn "*zero_extend<mode>di2_internal3"
266 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
267 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
269 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
270 (zero_extend:DI (match_dup 1)))]
273 rldicl. %0,%1,0,<dbits>
275 [(set_attr "type" "compare")
276 (set_attr "length" "4,8")])
279 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
280 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
282 (set (match_operand:DI 0 "gpc_reg_operand" "")
283 (zero_extend:DI (match_dup 1)))]
284 "TARGET_POWERPC64 && reload_completed"
286 (zero_extend:DI (match_dup 1)))
288 (compare:CC (match_dup 0)
292 (define_insn "extendqidi2"
293 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
294 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
297 [(set_attr "type" "exts")])
300 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
301 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
303 (clobber (match_scratch:DI 2 "=r,r"))]
308 [(set_attr "type" "compare")
309 (set_attr "length" "4,8")])
312 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
313 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
315 (clobber (match_scratch:DI 2 ""))]
316 "TARGET_POWERPC64 && reload_completed"
318 (sign_extend:DI (match_dup 1)))
320 (compare:CC (match_dup 2)
325 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
326 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
328 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
329 (sign_extend:DI (match_dup 1)))]
334 [(set_attr "type" "compare")
335 (set_attr "length" "4,8")])
338 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
339 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
341 (set (match_operand:DI 0 "gpc_reg_operand" "")
342 (sign_extend:DI (match_dup 1)))]
343 "TARGET_POWERPC64 && reload_completed"
345 (sign_extend:DI (match_dup 1)))
347 (compare:CC (match_dup 0)
351 (define_expand "extendhidi2"
352 [(set (match_operand:DI 0 "gpc_reg_operand" "")
353 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
358 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
359 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
364 [(set_attr "type" "load_ext,exts")])
367 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
368 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
370 (clobber (match_scratch:DI 2 "=r,r"))]
375 [(set_attr "type" "compare")
376 (set_attr "length" "4,8")])
379 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
380 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
382 (clobber (match_scratch:DI 2 ""))]
383 "TARGET_POWERPC64 && reload_completed"
385 (sign_extend:DI (match_dup 1)))
387 (compare:CC (match_dup 2)
392 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
393 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
395 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
396 (sign_extend:DI (match_dup 1)))]
401 [(set_attr "type" "compare")
402 (set_attr "length" "4,8")])
405 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
406 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
408 (set (match_operand:DI 0 "gpc_reg_operand" "")
409 (sign_extend:DI (match_dup 1)))]
410 "TARGET_POWERPC64 && reload_completed"
412 (sign_extend:DI (match_dup 1)))
414 (compare:CC (match_dup 0)
418 (define_expand "extendsidi2"
419 [(set (match_operand:DI 0 "gpc_reg_operand" "")
420 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
425 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
426 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
431 [(set_attr "type" "load_ext,exts")])
434 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
435 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
437 (clobber (match_scratch:DI 2 "=r,r"))]
442 [(set_attr "type" "compare")
443 (set_attr "length" "4,8")])
446 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
447 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
449 (clobber (match_scratch:DI 2 ""))]
450 "TARGET_POWERPC64 && reload_completed"
452 (sign_extend:DI (match_dup 1)))
454 (compare:CC (match_dup 2)
459 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
460 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
462 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
463 (sign_extend:DI (match_dup 1)))]
468 [(set_attr "type" "compare")
469 (set_attr "length" "4,8")])
472 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
473 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
475 (set (match_operand:DI 0 "gpc_reg_operand" "")
476 (sign_extend:DI (match_dup 1)))]
477 "TARGET_POWERPC64 && reload_completed"
479 (sign_extend:DI (match_dup 1)))
481 (compare:CC (match_dup 0)
485 (define_expand "zero_extendqisi2"
486 [(set (match_operand:SI 0 "gpc_reg_operand" "")
487 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
492 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
493 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
497 {rlinm|rlwinm} %0,%1,0,0xff"
498 [(set_attr "type" "load,*")])
501 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
502 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
504 (clobber (match_scratch:SI 2 "=r,r"))]
507 {andil.|andi.} %2,%1,0xff
509 [(set_attr "type" "compare")
510 (set_attr "length" "4,8")])
513 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
514 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
516 (clobber (match_scratch:SI 2 ""))]
519 (zero_extend:SI (match_dup 1)))
521 (compare:CC (match_dup 2)
526 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
527 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
529 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
530 (zero_extend:SI (match_dup 1)))]
533 {andil.|andi.} %0,%1,0xff
535 [(set_attr "type" "compare")
536 (set_attr "length" "4,8")])
539 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
540 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
542 (set (match_operand:SI 0 "gpc_reg_operand" "")
543 (zero_extend:SI (match_dup 1)))]
546 (zero_extend:SI (match_dup 1)))
548 (compare:CC (match_dup 0)
552 (define_expand "extendqisi2"
553 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
554 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
559 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
560 else if (TARGET_POWER)
561 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
563 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
567 (define_insn "extendqisi2_ppc"
568 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
569 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
572 [(set_attr "type" "exts")])
575 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
576 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
578 (clobber (match_scratch:SI 2 "=r,r"))]
583 [(set_attr "type" "compare")
584 (set_attr "length" "4,8")])
587 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
588 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
590 (clobber (match_scratch:SI 2 ""))]
591 "TARGET_POWERPC && reload_completed"
593 (sign_extend:SI (match_dup 1)))
595 (compare:CC (match_dup 2)
600 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
601 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
603 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
604 (sign_extend:SI (match_dup 1)))]
609 [(set_attr "type" "compare")
610 (set_attr "length" "4,8")])
613 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
614 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
616 (set (match_operand:SI 0 "gpc_reg_operand" "")
617 (sign_extend:SI (match_dup 1)))]
618 "TARGET_POWERPC && reload_completed"
620 (sign_extend:SI (match_dup 1)))
622 (compare:CC (match_dup 0)
626 (define_expand "extendqisi2_power"
627 [(parallel [(set (match_dup 2)
628 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
630 (clobber (scratch:SI))])
631 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
632 (ashiftrt:SI (match_dup 2)
634 (clobber (scratch:SI))])]
637 { operands[1] = gen_lowpart (SImode, operands[1]);
638 operands[2] = gen_reg_rtx (SImode); }")
640 (define_expand "extendqisi2_no_power"
642 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
644 (set (match_operand:SI 0 "gpc_reg_operand" "")
645 (ashiftrt:SI (match_dup 2)
647 "! TARGET_POWER && ! TARGET_POWERPC"
649 { operands[1] = gen_lowpart (SImode, operands[1]);
650 operands[2] = gen_reg_rtx (SImode); }")
652 (define_expand "zero_extendqihi2"
653 [(set (match_operand:HI 0 "gpc_reg_operand" "")
654 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
659 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
660 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
664 {rlinm|rlwinm} %0,%1,0,0xff"
665 [(set_attr "type" "load,*")])
668 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
669 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
671 (clobber (match_scratch:HI 2 "=r,r"))]
674 {andil.|andi.} %2,%1,0xff
676 [(set_attr "type" "compare")
677 (set_attr "length" "4,8")])
680 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
681 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
683 (clobber (match_scratch:HI 2 ""))]
686 (zero_extend:HI (match_dup 1)))
688 (compare:CC (match_dup 2)
693 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
694 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
696 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
697 (zero_extend:HI (match_dup 1)))]
700 {andil.|andi.} %0,%1,0xff
702 [(set_attr "type" "compare")
703 (set_attr "length" "4,8")])
706 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
707 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
709 (set (match_operand:HI 0 "gpc_reg_operand" "")
710 (zero_extend:HI (match_dup 1)))]
713 (zero_extend:HI (match_dup 1)))
715 (compare:CC (match_dup 0)
719 (define_expand "extendqihi2"
720 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
721 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
726 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
727 else if (TARGET_POWER)
728 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
730 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
734 (define_insn "extendqihi2_ppc"
735 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
736 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
739 [(set_attr "type" "exts")])
742 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
743 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
745 (clobber (match_scratch:HI 2 "=r,r"))]
750 [(set_attr "type" "compare")
751 (set_attr "length" "4,8")])
754 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
755 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
757 (clobber (match_scratch:HI 2 ""))]
758 "TARGET_POWERPC && reload_completed"
760 (sign_extend:HI (match_dup 1)))
762 (compare:CC (match_dup 2)
767 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
768 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
770 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
771 (sign_extend:HI (match_dup 1)))]
776 [(set_attr "type" "compare")
777 (set_attr "length" "4,8")])
780 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
781 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
783 (set (match_operand:HI 0 "gpc_reg_operand" "")
784 (sign_extend:HI (match_dup 1)))]
785 "TARGET_POWERPC && reload_completed"
787 (sign_extend:HI (match_dup 1)))
789 (compare:CC (match_dup 0)
793 (define_expand "extendqihi2_power"
794 [(parallel [(set (match_dup 2)
795 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
797 (clobber (scratch:SI))])
798 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
799 (ashiftrt:SI (match_dup 2)
801 (clobber (scratch:SI))])]
804 { operands[0] = gen_lowpart (SImode, operands[0]);
805 operands[1] = gen_lowpart (SImode, operands[1]);
806 operands[2] = gen_reg_rtx (SImode); }")
808 (define_expand "extendqihi2_no_power"
810 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
812 (set (match_operand:HI 0 "gpc_reg_operand" "")
813 (ashiftrt:SI (match_dup 2)
815 "! TARGET_POWER && ! TARGET_POWERPC"
817 { operands[0] = gen_lowpart (SImode, operands[0]);
818 operands[1] = gen_lowpart (SImode, operands[1]);
819 operands[2] = gen_reg_rtx (SImode); }")
821 (define_expand "zero_extendhisi2"
822 [(set (match_operand:SI 0 "gpc_reg_operand" "")
823 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
828 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
829 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
833 {rlinm|rlwinm} %0,%1,0,0xffff"
834 [(set_attr "type" "load,*")])
837 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
838 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
840 (clobber (match_scratch:SI 2 "=r,r"))]
843 {andil.|andi.} %2,%1,0xffff
845 [(set_attr "type" "compare")
846 (set_attr "length" "4,8")])
849 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
850 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
852 (clobber (match_scratch:SI 2 ""))]
855 (zero_extend:SI (match_dup 1)))
857 (compare:CC (match_dup 2)
862 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
863 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
865 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
866 (zero_extend:SI (match_dup 1)))]
869 {andil.|andi.} %0,%1,0xffff
871 [(set_attr "type" "compare")
872 (set_attr "length" "4,8")])
875 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
876 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
878 (set (match_operand:SI 0 "gpc_reg_operand" "")
879 (zero_extend:SI (match_dup 1)))]
882 (zero_extend:SI (match_dup 1)))
884 (compare:CC (match_dup 0)
888 (define_expand "extendhisi2"
889 [(set (match_operand:SI 0 "gpc_reg_operand" "")
890 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
895 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
896 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
901 [(set_attr "type" "load_ext,exts")])
904 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
905 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
907 (clobber (match_scratch:SI 2 "=r,r"))]
912 [(set_attr "type" "compare")
913 (set_attr "length" "4,8")])
916 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
917 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
919 (clobber (match_scratch:SI 2 ""))]
922 (sign_extend:SI (match_dup 1)))
924 (compare:CC (match_dup 2)
929 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
930 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
932 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
933 (sign_extend:SI (match_dup 1)))]
938 [(set_attr "type" "compare")
939 (set_attr "length" "4,8")])
941 ;; IBM 405, 440 and 464 half-word multiplication operations.
943 (define_insn "*macchwc"
944 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
945 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
946 (match_operand:SI 2 "gpc_reg_operand" "r")
949 (match_operand:HI 1 "gpc_reg_operand" "r")))
950 (match_operand:SI 4 "gpc_reg_operand" "0"))
952 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
953 (plus:SI (mult:SI (ashiftrt:SI
961 [(set_attr "type" "imul3")])
963 (define_insn "*macchw"
964 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
965 (plus:SI (mult:SI (ashiftrt:SI
966 (match_operand:SI 2 "gpc_reg_operand" "r")
969 (match_operand:HI 1 "gpc_reg_operand" "r")))
970 (match_operand:SI 3 "gpc_reg_operand" "0")))]
973 [(set_attr "type" "imul3")])
975 (define_insn "*macchwuc"
976 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
977 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
978 (match_operand:SI 2 "gpc_reg_operand" "r")
981 (match_operand:HI 1 "gpc_reg_operand" "r")))
982 (match_operand:SI 4 "gpc_reg_operand" "0"))
984 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
985 (plus:SI (mult:SI (lshiftrt:SI
992 "macchwu. %0, %1, %2"
993 [(set_attr "type" "imul3")])
995 (define_insn "*macchwu"
996 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
997 (plus:SI (mult:SI (lshiftrt:SI
998 (match_operand:SI 2 "gpc_reg_operand" "r")
1001 (match_operand:HI 1 "gpc_reg_operand" "r")))
1002 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1004 "macchwu %0, %1, %2"
1005 [(set_attr "type" "imul3")])
1007 (define_insn "*machhwc"
1008 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1009 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1010 (match_operand:SI 1 "gpc_reg_operand" "%r")
1013 (match_operand:SI 2 "gpc_reg_operand" "r")
1015 (match_operand:SI 4 "gpc_reg_operand" "0"))
1017 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1018 (plus:SI (mult:SI (ashiftrt:SI
1026 "machhw. %0, %1, %2"
1027 [(set_attr "type" "imul3")])
1029 (define_insn "*machhw"
1030 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1031 (plus:SI (mult:SI (ashiftrt:SI
1032 (match_operand:SI 1 "gpc_reg_operand" "%r")
1035 (match_operand:SI 2 "gpc_reg_operand" "r")
1037 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1040 [(set_attr "type" "imul3")])
1042 (define_insn "*machhwuc"
1043 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1044 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1045 (match_operand:SI 1 "gpc_reg_operand" "%r")
1048 (match_operand:SI 2 "gpc_reg_operand" "r")
1050 (match_operand:SI 4 "gpc_reg_operand" "0"))
1052 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1053 (plus:SI (mult:SI (lshiftrt:SI
1061 "machhwu. %0, %1, %2"
1062 [(set_attr "type" "imul3")])
1064 (define_insn "*machhwu"
1065 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1066 (plus:SI (mult:SI (lshiftrt:SI
1067 (match_operand:SI 1 "gpc_reg_operand" "%r")
1070 (match_operand:SI 2 "gpc_reg_operand" "r")
1072 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1074 "machhwu %0, %1, %2"
1075 [(set_attr "type" "imul3")])
1077 (define_insn "*maclhwc"
1078 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1079 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1080 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1082 (match_operand:HI 2 "gpc_reg_operand" "r")))
1083 (match_operand:SI 4 "gpc_reg_operand" "0"))
1085 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1086 (plus:SI (mult:SI (sign_extend:SI
1092 "maclhw. %0, %1, %2"
1093 [(set_attr "type" "imul3")])
1095 (define_insn "*maclhw"
1096 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1097 (plus:SI (mult:SI (sign_extend:SI
1098 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1100 (match_operand:HI 2 "gpc_reg_operand" "r")))
1101 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1104 [(set_attr "type" "imul3")])
1106 (define_insn "*maclhwuc"
1107 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1108 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1109 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1111 (match_operand:HI 2 "gpc_reg_operand" "r")))
1112 (match_operand:SI 4 "gpc_reg_operand" "0"))
1114 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1115 (plus:SI (mult:SI (zero_extend:SI
1121 "maclhwu. %0, %1, %2"
1122 [(set_attr "type" "imul3")])
1124 (define_insn "*maclhwu"
1125 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1126 (plus:SI (mult:SI (zero_extend:SI
1127 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1129 (match_operand:HI 2 "gpc_reg_operand" "r")))
1130 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1132 "maclhwu %0, %1, %2"
1133 [(set_attr "type" "imul3")])
1135 (define_insn "*nmacchwc"
1136 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1137 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1138 (mult:SI (ashiftrt:SI
1139 (match_operand:SI 2 "gpc_reg_operand" "r")
1142 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1144 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1145 (minus:SI (match_dup 4)
1146 (mult:SI (ashiftrt:SI
1152 "nmacchw. %0, %1, %2"
1153 [(set_attr "type" "imul3")])
1155 (define_insn "*nmacchw"
1156 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1157 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1158 (mult:SI (ashiftrt:SI
1159 (match_operand:SI 2 "gpc_reg_operand" "r")
1162 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1164 "nmacchw %0, %1, %2"
1165 [(set_attr "type" "imul3")])
1167 (define_insn "*nmachhwc"
1168 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1169 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1170 (mult:SI (ashiftrt:SI
1171 (match_operand:SI 1 "gpc_reg_operand" "%r")
1174 (match_operand:SI 2 "gpc_reg_operand" "r")
1177 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1178 (minus:SI (match_dup 4)
1179 (mult:SI (ashiftrt:SI
1186 "nmachhw. %0, %1, %2"
1187 [(set_attr "type" "imul3")])
1189 (define_insn "*nmachhw"
1190 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1191 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1192 (mult:SI (ashiftrt:SI
1193 (match_operand:SI 1 "gpc_reg_operand" "%r")
1196 (match_operand:SI 2 "gpc_reg_operand" "r")
1199 "nmachhw %0, %1, %2"
1200 [(set_attr "type" "imul3")])
1202 (define_insn "*nmaclhwc"
1203 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1204 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1205 (mult:SI (sign_extend:SI
1206 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1208 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1210 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1211 (minus:SI (match_dup 4)
1212 (mult:SI (sign_extend:SI
1217 "nmaclhw. %0, %1, %2"
1218 [(set_attr "type" "imul3")])
1220 (define_insn "*nmaclhw"
1221 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1222 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1223 (mult:SI (sign_extend:SI
1224 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1226 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1228 "nmaclhw %0, %1, %2"
1229 [(set_attr "type" "imul3")])
1231 (define_insn "*mulchwc"
1232 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1233 (compare:CC (mult:SI (ashiftrt:SI
1234 (match_operand:SI 2 "gpc_reg_operand" "r")
1237 (match_operand:HI 1 "gpc_reg_operand" "r")))
1239 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1240 (mult:SI (ashiftrt:SI
1246 "mulchw. %0, %1, %2"
1247 [(set_attr "type" "imul3")])
1249 (define_insn "*mulchw"
1250 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1251 (mult:SI (ashiftrt:SI
1252 (match_operand:SI 2 "gpc_reg_operand" "r")
1255 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1258 [(set_attr "type" "imul3")])
1260 (define_insn "*mulchwuc"
1261 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1262 (compare:CC (mult:SI (lshiftrt:SI
1263 (match_operand:SI 2 "gpc_reg_operand" "r")
1266 (match_operand:HI 1 "gpc_reg_operand" "r")))
1268 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1269 (mult:SI (lshiftrt:SI
1275 "mulchwu. %0, %1, %2"
1276 [(set_attr "type" "imul3")])
1278 (define_insn "*mulchwu"
1279 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1280 (mult:SI (lshiftrt:SI
1281 (match_operand:SI 2 "gpc_reg_operand" "r")
1284 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1286 "mulchwu %0, %1, %2"
1287 [(set_attr "type" "imul3")])
1289 (define_insn "*mulhhwc"
1290 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1291 (compare:CC (mult:SI (ashiftrt:SI
1292 (match_operand:SI 1 "gpc_reg_operand" "%r")
1295 (match_operand:SI 2 "gpc_reg_operand" "r")
1298 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1299 (mult:SI (ashiftrt:SI
1306 "mulhhw. %0, %1, %2"
1307 [(set_attr "type" "imul3")])
1309 (define_insn "*mulhhw"
1310 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1311 (mult:SI (ashiftrt:SI
1312 (match_operand:SI 1 "gpc_reg_operand" "%r")
1315 (match_operand:SI 2 "gpc_reg_operand" "r")
1319 [(set_attr "type" "imul3")])
1321 (define_insn "*mulhhwuc"
1322 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1323 (compare:CC (mult:SI (lshiftrt:SI
1324 (match_operand:SI 1 "gpc_reg_operand" "%r")
1327 (match_operand:SI 2 "gpc_reg_operand" "r")
1330 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1331 (mult:SI (lshiftrt:SI
1338 "mulhhwu. %0, %1, %2"
1339 [(set_attr "type" "imul3")])
1341 (define_insn "*mulhhwu"
1342 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1343 (mult:SI (lshiftrt:SI
1344 (match_operand:SI 1 "gpc_reg_operand" "%r")
1347 (match_operand:SI 2 "gpc_reg_operand" "r")
1350 "mulhhwu %0, %1, %2"
1351 [(set_attr "type" "imul3")])
1353 (define_insn "*mullhwc"
1354 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1355 (compare:CC (mult:SI (sign_extend:SI
1356 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1358 (match_operand:HI 2 "gpc_reg_operand" "r")))
1360 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1361 (mult:SI (sign_extend:SI
1366 "mullhw. %0, %1, %2"
1367 [(set_attr "type" "imul3")])
1369 (define_insn "*mullhw"
1370 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1371 (mult:SI (sign_extend:SI
1372 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1374 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1377 [(set_attr "type" "imul3")])
1379 (define_insn "*mullhwuc"
1380 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1381 (compare:CC (mult:SI (zero_extend:SI
1382 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1384 (match_operand:HI 2 "gpc_reg_operand" "r")))
1386 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1387 (mult:SI (zero_extend:SI
1392 "mullhwu. %0, %1, %2"
1393 [(set_attr "type" "imul3")])
1395 (define_insn "*mullhwu"
1396 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1397 (mult:SI (zero_extend:SI
1398 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1400 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1402 "mullhwu %0, %1, %2"
1403 [(set_attr "type" "imul3")])
1405 ;; IBM 405, 440 and 464 string-search dlmzb instruction support.
1406 (define_insn "dlmzb"
1407 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1408 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1409 (match_operand:SI 2 "gpc_reg_operand" "r")]
1411 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1412 (unspec:SI [(match_dup 1)
1416 "dlmzb. %0, %1, %2")
1418 (define_expand "strlensi"
1419 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1420 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1421 (match_operand:QI 2 "const_int_operand" "")
1422 (match_operand 3 "const_int_operand" "")]
1423 UNSPEC_DLMZB_STRLEN))
1424 (clobber (match_scratch:CC 4 "=x"))]
1425 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1427 rtx result = operands[0];
1428 rtx src = operands[1];
1429 rtx search_char = operands[2];
1430 rtx align = operands[3];
1431 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1432 rtx loop_label, end_label, mem, cr0, cond;
1433 if (search_char != const0_rtx
1434 || GET_CODE (align) != CONST_INT
1435 || INTVAL (align) < 8)
1437 word1 = gen_reg_rtx (SImode);
1438 word2 = gen_reg_rtx (SImode);
1439 scratch_dlmzb = gen_reg_rtx (SImode);
1440 scratch_string = gen_reg_rtx (Pmode);
1441 loop_label = gen_label_rtx ();
1442 end_label = gen_label_rtx ();
1443 addr = force_reg (Pmode, XEXP (src, 0));
1444 emit_move_insn (scratch_string, addr);
1445 emit_label (loop_label);
1446 mem = change_address (src, SImode, scratch_string);
1447 emit_move_insn (word1, mem);
1448 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1449 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1450 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1451 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1452 emit_jump_insn (gen_rtx_SET (VOIDmode,
1454 gen_rtx_IF_THEN_ELSE (VOIDmode,
1460 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1461 emit_jump_insn (gen_rtx_SET (VOIDmode,
1463 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1465 emit_label (end_label);
1466 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1467 emit_insn (gen_subsi3 (result, scratch_string, addr));
1468 emit_insn (gen_subsi3 (result, result, const1_rtx));
1473 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1474 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1476 (set (match_operand:SI 0 "gpc_reg_operand" "")
1477 (sign_extend:SI (match_dup 1)))]
1480 (sign_extend:SI (match_dup 1)))
1482 (compare:CC (match_dup 0)
1486 ;; Fixed-point arithmetic insns.
1488 (define_expand "add<mode>3"
1489 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1490 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1491 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1494 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1496 if (non_short_cint_operand (operands[2], DImode))
1499 else if (GET_CODE (operands[2]) == CONST_INT
1500 && ! add_operand (operands[2], <MODE>mode))
1502 rtx tmp = ((!can_create_pseudo_p ()
1503 || rtx_equal_p (operands[0], operands[1]))
1504 ? operands[0] : gen_reg_rtx (<MODE>mode));
1506 HOST_WIDE_INT val = INTVAL (operands[2]);
1507 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1508 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1510 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1513 /* The ordering here is important for the prolog expander.
1514 When space is allocated from the stack, adding 'low' first may
1515 produce a temporary deallocation (which would be bad). */
1516 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1517 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1522 ;; Discourage ai/addic because of carry but provide it in an alternative
1523 ;; allowing register zero as source.
1524 (define_insn "*add<mode>3_internal1"
1525 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1526 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1527 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1528 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1531 {cal %0,%2(%1)|addi %0,%1,%2}
1533 {cau|addis} %0,%1,%v2"
1534 [(set_attr "length" "4,4,4,4")])
1536 (define_insn "addsi3_high"
1537 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1538 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1539 (high:SI (match_operand 2 "" ""))))]
1540 "TARGET_MACHO && !TARGET_64BIT"
1541 "{cau|addis} %0,%1,ha16(%2)"
1542 [(set_attr "length" "4")])
1544 (define_insn "*add<mode>3_internal2"
1545 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1546 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1547 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1549 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1552 {cax.|add.} %3,%1,%2
1553 {ai.|addic.} %3,%1,%2
1556 [(set_attr "type" "fast_compare,compare,compare,compare")
1557 (set_attr "length" "4,4,8,8")])
1560 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1561 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1562 (match_operand:GPR 2 "reg_or_short_operand" ""))
1564 (clobber (match_scratch:GPR 3 ""))]
1567 (plus:GPR (match_dup 1)
1570 (compare:CC (match_dup 3)
1574 (define_insn "*add<mode>3_internal3"
1575 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1576 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1577 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1579 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1580 (plus:P (match_dup 1)
1584 {cax.|add.} %0,%1,%2
1585 {ai.|addic.} %0,%1,%2
1588 [(set_attr "type" "fast_compare,compare,compare,compare")
1589 (set_attr "length" "4,4,8,8")])
1592 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1593 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1594 (match_operand:P 2 "reg_or_short_operand" ""))
1596 (set (match_operand:P 0 "gpc_reg_operand" "")
1597 (plus:P (match_dup 1) (match_dup 2)))]
1600 (plus:P (match_dup 1)
1603 (compare:CC (match_dup 0)
1607 ;; Split an add that we can't do in one insn into two insns, each of which
1608 ;; does one 16-bit part. This is used by combine. Note that the low-order
1609 ;; add should be last in case the result gets used in an address.
1612 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1613 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1614 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1616 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1617 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1619 HOST_WIDE_INT val = INTVAL (operands[2]);
1620 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1621 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1623 operands[4] = GEN_INT (low);
1624 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1625 operands[3] = GEN_INT (rest);
1626 else if (can_create_pseudo_p ())
1628 operands[3] = gen_reg_rtx (DImode);
1629 emit_move_insn (operands[3], operands[2]);
1630 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1637 (define_insn "one_cmpl<mode>2"
1638 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1639 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1644 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1645 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1647 (clobber (match_scratch:P 2 "=r,r"))]
1652 [(set_attr "type" "compare")
1653 (set_attr "length" "4,8")])
1656 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1657 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1659 (clobber (match_scratch:P 2 ""))]
1662 (not:P (match_dup 1)))
1664 (compare:CC (match_dup 2)
1669 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1670 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1672 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1673 (not:P (match_dup 1)))]
1678 [(set_attr "type" "compare")
1679 (set_attr "length" "4,8")])
1682 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1683 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1685 (set (match_operand:P 0 "gpc_reg_operand" "")
1686 (not:P (match_dup 1)))]
1689 (not:P (match_dup 1)))
1691 (compare:CC (match_dup 0)
1696 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1697 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1698 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1700 "{sf%I1|subf%I1c} %0,%2,%1")
1703 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1704 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1705 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1712 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1713 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1714 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1716 (clobber (match_scratch:SI 3 "=r,r"))]
1719 {sf.|subfc.} %3,%2,%1
1721 [(set_attr "type" "compare")
1722 (set_attr "length" "4,8")])
1725 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1726 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1727 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1729 (clobber (match_scratch:P 3 "=r,r"))]
1734 [(set_attr "type" "fast_compare")
1735 (set_attr "length" "4,8")])
1738 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1739 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1740 (match_operand:P 2 "gpc_reg_operand" ""))
1742 (clobber (match_scratch:P 3 ""))]
1745 (minus:P (match_dup 1)
1748 (compare:CC (match_dup 3)
1753 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1754 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1755 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1757 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1758 (minus:SI (match_dup 1) (match_dup 2)))]
1761 {sf.|subfc.} %0,%2,%1
1763 [(set_attr "type" "compare")
1764 (set_attr "length" "4,8")])
1767 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1768 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1769 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1771 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1772 (minus:P (match_dup 1)
1778 [(set_attr "type" "fast_compare")
1779 (set_attr "length" "4,8")])
1782 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1783 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1784 (match_operand:P 2 "gpc_reg_operand" ""))
1786 (set (match_operand:P 0 "gpc_reg_operand" "")
1787 (minus:P (match_dup 1)
1791 (minus:P (match_dup 1)
1794 (compare:CC (match_dup 0)
1798 (define_expand "sub<mode>3"
1799 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1800 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1801 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1805 if (GET_CODE (operands[2]) == CONST_INT)
1807 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1808 negate_rtx (<MODE>mode, operands[2])));
1813 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1814 ;; instruction and some auxiliary computations. Then we just have a single
1815 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1818 (define_expand "sminsi3"
1820 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1821 (match_operand:SI 2 "reg_or_short_operand" ""))
1823 (minus:SI (match_dup 2) (match_dup 1))))
1824 (set (match_operand:SI 0 "gpc_reg_operand" "")
1825 (minus:SI (match_dup 2) (match_dup 3)))]
1826 "TARGET_POWER || TARGET_ISEL"
1831 operands[2] = force_reg (SImode, operands[2]);
1832 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1836 operands[3] = gen_reg_rtx (SImode);
1840 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1841 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1842 (match_operand:SI 2 "reg_or_short_operand" "")))
1843 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1846 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1848 (minus:SI (match_dup 2) (match_dup 1))))
1849 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1852 (define_expand "smaxsi3"
1854 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1855 (match_operand:SI 2 "reg_or_short_operand" ""))
1857 (minus:SI (match_dup 2) (match_dup 1))))
1858 (set (match_operand:SI 0 "gpc_reg_operand" "")
1859 (plus:SI (match_dup 3) (match_dup 1)))]
1860 "TARGET_POWER || TARGET_ISEL"
1865 operands[2] = force_reg (SImode, operands[2]);
1866 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1869 operands[3] = gen_reg_rtx (SImode);
1873 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1874 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1875 (match_operand:SI 2 "reg_or_short_operand" "")))
1876 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1879 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1881 (minus:SI (match_dup 2) (match_dup 1))))
1882 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1885 (define_expand "uminsi3"
1886 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1888 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1890 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1892 (minus:SI (match_dup 4) (match_dup 3))))
1893 (set (match_operand:SI 0 "gpc_reg_operand" "")
1894 (minus:SI (match_dup 2) (match_dup 3)))]
1895 "TARGET_POWER || TARGET_ISEL"
1900 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1903 operands[3] = gen_reg_rtx (SImode);
1904 operands[4] = gen_reg_rtx (SImode);
1905 operands[5] = GEN_INT (-2147483647 - 1);
1908 (define_expand "umaxsi3"
1909 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1911 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1913 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1915 (minus:SI (match_dup 4) (match_dup 3))))
1916 (set (match_operand:SI 0 "gpc_reg_operand" "")
1917 (plus:SI (match_dup 3) (match_dup 1)))]
1918 "TARGET_POWER || TARGET_ISEL"
1923 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1926 operands[3] = gen_reg_rtx (SImode);
1927 operands[4] = gen_reg_rtx (SImode);
1928 operands[5] = GEN_INT (-2147483647 - 1);
1932 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1933 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1934 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1936 (minus:SI (match_dup 2) (match_dup 1))))]
1941 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1943 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1944 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1946 (minus:SI (match_dup 2) (match_dup 1)))
1948 (clobber (match_scratch:SI 3 "=r,r"))]
1953 [(set_attr "type" "delayed_compare")
1954 (set_attr "length" "4,8")])
1957 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1959 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1960 (match_operand:SI 2 "reg_or_short_operand" ""))
1962 (minus:SI (match_dup 2) (match_dup 1)))
1964 (clobber (match_scratch:SI 3 ""))]
1965 "TARGET_POWER && reload_completed"
1967 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1969 (minus:SI (match_dup 2) (match_dup 1))))
1971 (compare:CC (match_dup 3)
1976 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1978 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1979 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1981 (minus:SI (match_dup 2) (match_dup 1)))
1983 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1984 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1986 (minus:SI (match_dup 2) (match_dup 1))))]
1991 [(set_attr "type" "delayed_compare")
1992 (set_attr "length" "4,8")])
1995 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1997 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1998 (match_operand:SI 2 "reg_or_short_operand" ""))
2000 (minus:SI (match_dup 2) (match_dup 1)))
2002 (set (match_operand:SI 0 "gpc_reg_operand" "")
2003 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2005 (minus:SI (match_dup 2) (match_dup 1))))]
2006 "TARGET_POWER && reload_completed"
2008 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2010 (minus:SI (match_dup 2) (match_dup 1))))
2012 (compare:CC (match_dup 0)
2016 ;; We don't need abs with condition code because such comparisons should
2018 (define_expand "abssi2"
2019 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2020 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2026 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
2029 else if (! TARGET_POWER)
2031 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2036 (define_insn "*abssi2_power"
2037 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2038 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2042 (define_insn_and_split "abssi2_isel"
2043 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2044 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
2045 (clobber (match_scratch:SI 2 "=&b"))
2046 (clobber (match_scratch:CC 3 "=y"))]
2049 "&& reload_completed"
2050 [(set (match_dup 2) (neg:SI (match_dup 1)))
2052 (compare:CC (match_dup 1)
2055 (if_then_else:SI (ge (match_dup 3)
2061 (define_insn_and_split "abssi2_nopower"
2062 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2063 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2064 (clobber (match_scratch:SI 2 "=&r,&r"))]
2065 "! TARGET_POWER && ! TARGET_ISEL"
2067 "&& reload_completed"
2068 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2069 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2070 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2073 (define_insn "*nabs_power"
2074 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2075 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2079 (define_insn_and_split "*nabs_nopower"
2080 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2081 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2082 (clobber (match_scratch:SI 2 "=&r,&r"))]
2085 "&& reload_completed"
2086 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2087 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2088 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2091 (define_expand "neg<mode>2"
2092 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2093 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2097 (define_insn "*neg<mode>2_internal"
2098 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2099 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2104 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2105 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2107 (clobber (match_scratch:P 2 "=r,r"))]
2112 [(set_attr "type" "fast_compare")
2113 (set_attr "length" "4,8")])
2116 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2117 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2119 (clobber (match_scratch:P 2 ""))]
2122 (neg:P (match_dup 1)))
2124 (compare:CC (match_dup 2)
2129 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2130 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2132 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2133 (neg:P (match_dup 1)))]
2138 [(set_attr "type" "fast_compare")
2139 (set_attr "length" "4,8")])
2142 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2143 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2145 (set (match_operand:P 0 "gpc_reg_operand" "")
2146 (neg:P (match_dup 1)))]
2149 (neg:P (match_dup 1)))
2151 (compare:CC (match_dup 0)
2155 (define_insn "clz<mode>2"
2156 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2157 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2159 "{cntlz|cntlz<wd>} %0,%1"
2160 [(set_attr "type" "cntlz")])
2162 (define_expand "ctz<mode>2"
2164 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2165 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2167 (clobber (scratch:CC))])
2168 (set (match_dup 4) (clz:GPR (match_dup 3)))
2169 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2170 (minus:GPR (match_dup 5) (match_dup 4)))]
2173 operands[2] = gen_reg_rtx (<MODE>mode);
2174 operands[3] = gen_reg_rtx (<MODE>mode);
2175 operands[4] = gen_reg_rtx (<MODE>mode);
2176 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2179 (define_expand "ffs<mode>2"
2181 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2182 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2184 (clobber (scratch:CC))])
2185 (set (match_dup 4) (clz:GPR (match_dup 3)))
2186 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2187 (minus:GPR (match_dup 5) (match_dup 4)))]
2190 operands[2] = gen_reg_rtx (<MODE>mode);
2191 operands[3] = gen_reg_rtx (<MODE>mode);
2192 operands[4] = gen_reg_rtx (<MODE>mode);
2193 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2196 (define_insn "popcntb<mode>2"
2197 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2198 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2203 (define_expand "popcount<mode>2"
2204 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2205 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2208 rs6000_emit_popcount (operands[0], operands[1]);
2212 (define_expand "parity<mode>2"
2213 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2214 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2217 rs6000_emit_parity (operands[0], operands[1]);
2221 (define_insn "bswapsi2"
2222 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2223 (bswap:SI (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2227 {stbrx|stwbrx} %1,%y0
2229 [(set_attr "length" "4,4,12")])
2232 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2233 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2236 (rotate:SI (match_dup 1) (const_int 8)))
2237 (set (zero_extract:SI (match_dup 0)
2241 (set (zero_extract:SI (match_dup 0)
2244 (rotate:SI (match_dup 1)
2248 (define_expand "mulsi3"
2249 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2250 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2251 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2256 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2258 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2262 (define_insn "mulsi3_mq"
2263 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2264 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2265 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2266 (clobber (match_scratch:SI 3 "=q,q"))]
2269 {muls|mullw} %0,%1,%2
2270 {muli|mulli} %0,%1,%2"
2272 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2273 (const_string "imul3")
2274 (match_operand:SI 2 "short_cint_operand" "")
2275 (const_string "imul2")]
2276 (const_string "imul")))])
2278 (define_insn "mulsi3_no_mq"
2279 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2280 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2281 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2284 {muls|mullw} %0,%1,%2
2285 {muli|mulli} %0,%1,%2"
2287 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2288 (const_string "imul3")
2289 (match_operand:SI 2 "short_cint_operand" "")
2290 (const_string "imul2")]
2291 (const_string "imul")))])
2293 (define_insn "*mulsi3_mq_internal1"
2294 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2295 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2296 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2298 (clobber (match_scratch:SI 3 "=r,r"))
2299 (clobber (match_scratch:SI 4 "=q,q"))]
2302 {muls.|mullw.} %3,%1,%2
2304 [(set_attr "type" "imul_compare")
2305 (set_attr "length" "4,8")])
2308 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2309 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2310 (match_operand:SI 2 "gpc_reg_operand" ""))
2312 (clobber (match_scratch:SI 3 ""))
2313 (clobber (match_scratch:SI 4 ""))]
2314 "TARGET_POWER && reload_completed"
2315 [(parallel [(set (match_dup 3)
2316 (mult:SI (match_dup 1) (match_dup 2)))
2317 (clobber (match_dup 4))])
2319 (compare:CC (match_dup 3)
2323 (define_insn "*mulsi3_no_mq_internal1"
2324 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2325 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2326 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2328 (clobber (match_scratch:SI 3 "=r,r"))]
2331 {muls.|mullw.} %3,%1,%2
2333 [(set_attr "type" "imul_compare")
2334 (set_attr "length" "4,8")])
2337 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2338 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2339 (match_operand:SI 2 "gpc_reg_operand" ""))
2341 (clobber (match_scratch:SI 3 ""))]
2342 "! TARGET_POWER && reload_completed"
2344 (mult:SI (match_dup 1) (match_dup 2)))
2346 (compare:CC (match_dup 3)
2350 (define_insn "*mulsi3_mq_internal2"
2351 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2352 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2353 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2355 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2356 (mult:SI (match_dup 1) (match_dup 2)))
2357 (clobber (match_scratch:SI 4 "=q,q"))]
2360 {muls.|mullw.} %0,%1,%2
2362 [(set_attr "type" "imul_compare")
2363 (set_attr "length" "4,8")])
2366 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2367 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2368 (match_operand:SI 2 "gpc_reg_operand" ""))
2370 (set (match_operand:SI 0 "gpc_reg_operand" "")
2371 (mult:SI (match_dup 1) (match_dup 2)))
2372 (clobber (match_scratch:SI 4 ""))]
2373 "TARGET_POWER && reload_completed"
2374 [(parallel [(set (match_dup 0)
2375 (mult:SI (match_dup 1) (match_dup 2)))
2376 (clobber (match_dup 4))])
2378 (compare:CC (match_dup 0)
2382 (define_insn "*mulsi3_no_mq_internal2"
2383 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2384 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2385 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2387 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2388 (mult:SI (match_dup 1) (match_dup 2)))]
2391 {muls.|mullw.} %0,%1,%2
2393 [(set_attr "type" "imul_compare")
2394 (set_attr "length" "4,8")])
2397 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2398 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2399 (match_operand:SI 2 "gpc_reg_operand" ""))
2401 (set (match_operand:SI 0 "gpc_reg_operand" "")
2402 (mult:SI (match_dup 1) (match_dup 2)))]
2403 "! TARGET_POWER && reload_completed"
2405 (mult:SI (match_dup 1) (match_dup 2)))
2407 (compare:CC (match_dup 0)
2411 ;; Operand 1 is divided by operand 2; quotient goes to operand
2412 ;; 0 and remainder to operand 3.
2413 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2415 (define_expand "divmodsi4"
2416 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2417 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2418 (match_operand:SI 2 "gpc_reg_operand" "")))
2419 (set (match_operand:SI 3 "register_operand" "")
2420 (mod:SI (match_dup 1) (match_dup 2)))])]
2421 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2424 if (! TARGET_POWER && ! TARGET_POWERPC)
2426 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2427 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2428 emit_insn (gen_divss_call ());
2429 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2430 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2435 (define_insn "*divmodsi4_internal"
2436 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2437 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2438 (match_operand:SI 2 "gpc_reg_operand" "r")))
2439 (set (match_operand:SI 3 "register_operand" "=q")
2440 (mod:SI (match_dup 1) (match_dup 2)))]
2443 [(set_attr "type" "idiv")])
2445 (define_expand "udiv<mode>3"
2446 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2447 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2448 (match_operand:GPR 2 "gpc_reg_operand" "")))]
2449 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2452 if (! TARGET_POWER && ! TARGET_POWERPC)
2454 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2455 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2456 emit_insn (gen_quous_call ());
2457 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2460 else if (TARGET_POWER)
2462 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2467 (define_insn "udivsi3_mq"
2468 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2469 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2470 (match_operand:SI 2 "gpc_reg_operand" "r")))
2471 (clobber (match_scratch:SI 3 "=q"))]
2472 "TARGET_POWERPC && TARGET_POWER"
2474 [(set_attr "type" "idiv")])
2476 (define_insn "*udivsi3_no_mq"
2477 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2478 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2479 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2480 "TARGET_POWERPC && ! TARGET_POWER"
2483 (cond [(match_operand:SI 0 "" "")
2484 (const_string "idiv")]
2485 (const_string "ldiv")))])
2488 ;; For powers of two we can do srai/aze for divide and then adjust for
2489 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2490 ;; used; for PowerPC, force operands into register and do a normal divide;
2491 ;; for AIX common-mode, use quoss call on register operands.
2492 (define_expand "div<mode>3"
2493 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2494 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2495 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2499 if (GET_CODE (operands[2]) == CONST_INT
2500 && INTVAL (operands[2]) > 0
2501 && exact_log2 (INTVAL (operands[2])) >= 0)
2503 else if (TARGET_POWERPC)
2505 operands[2] = force_reg (<MODE>mode, operands[2]);
2508 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2512 else if (TARGET_POWER)
2516 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2517 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2518 emit_insn (gen_quoss_call ());
2519 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2524 (define_insn "divsi3_mq"
2525 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2526 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2527 (match_operand:SI 2 "gpc_reg_operand" "r")))
2528 (clobber (match_scratch:SI 3 "=q"))]
2529 "TARGET_POWERPC && TARGET_POWER"
2531 [(set_attr "type" "idiv")])
2533 (define_insn "*div<mode>3_no_mq"
2534 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2535 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2536 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2537 "TARGET_POWERPC && ! TARGET_POWER"
2540 (cond [(match_operand:SI 0 "" "")
2541 (const_string "idiv")]
2542 (const_string "ldiv")))])
2544 (define_expand "mod<mode>3"
2545 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2546 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2547 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2555 if (GET_CODE (operands[2]) != CONST_INT
2556 || INTVAL (operands[2]) <= 0
2557 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2560 temp1 = gen_reg_rtx (<MODE>mode);
2561 temp2 = gen_reg_rtx (<MODE>mode);
2563 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2564 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2565 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2570 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2571 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2572 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2574 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
2575 [(set_attr "type" "two")
2576 (set_attr "length" "8")])
2579 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2580 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2581 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2583 (clobber (match_scratch:P 3 "=r,r"))]
2586 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
2588 [(set_attr "type" "compare")
2589 (set_attr "length" "8,12")])
2592 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2593 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2594 (match_operand:GPR 2 "exact_log2_cint_operand"
2597 (clobber (match_scratch:GPR 3 ""))]
2600 (div:<MODE> (match_dup 1) (match_dup 2)))
2602 (compare:CC (match_dup 3)
2607 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2608 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2609 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2611 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2612 (div:P (match_dup 1) (match_dup 2)))]
2615 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
2617 [(set_attr "type" "compare")
2618 (set_attr "length" "8,12")])
2621 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2622 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2623 (match_operand:GPR 2 "exact_log2_cint_operand"
2626 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2627 (div:GPR (match_dup 1) (match_dup 2)))]
2630 (div:<MODE> (match_dup 1) (match_dup 2)))
2632 (compare:CC (match_dup 0)
2637 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2640 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2642 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2643 (match_operand:SI 3 "gpc_reg_operand" "r")))
2644 (set (match_operand:SI 2 "register_operand" "=*q")
2647 (zero_extend:DI (match_dup 1)) (const_int 32))
2648 (zero_extend:DI (match_dup 4)))
2652 [(set_attr "type" "idiv")])
2654 ;; To do unsigned divide we handle the cases of the divisor looking like a
2655 ;; negative number. If it is a constant that is less than 2**31, we don't
2656 ;; have to worry about the branches. So make a few subroutines here.
2658 ;; First comes the normal case.
2659 (define_expand "udivmodsi4_normal"
2660 [(set (match_dup 4) (const_int 0))
2661 (parallel [(set (match_operand:SI 0 "" "")
2662 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2664 (zero_extend:DI (match_operand:SI 1 "" "")))
2665 (match_operand:SI 2 "" "")))
2666 (set (match_operand:SI 3 "" "")
2667 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2669 (zero_extend:DI (match_dup 1)))
2673 { operands[4] = gen_reg_rtx (SImode); }")
2675 ;; This handles the branches.
2676 (define_expand "udivmodsi4_tests"
2677 [(set (match_operand:SI 0 "" "") (const_int 0))
2678 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2679 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2680 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2681 (label_ref (match_operand:SI 4 "" "")) (pc)))
2682 (set (match_dup 0) (const_int 1))
2683 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2684 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2685 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2686 (label_ref (match_dup 4)) (pc)))]
2689 { operands[5] = gen_reg_rtx (CCUNSmode);
2690 operands[6] = gen_reg_rtx (CCmode);
2693 (define_expand "udivmodsi4"
2694 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2695 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2696 (match_operand:SI 2 "reg_or_cint_operand" "")))
2697 (set (match_operand:SI 3 "gpc_reg_operand" "")
2698 (umod:SI (match_dup 1) (match_dup 2)))])]
2706 if (! TARGET_POWERPC)
2708 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2709 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2710 emit_insn (gen_divus_call ());
2711 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2712 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2719 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2721 operands[2] = force_reg (SImode, operands[2]);
2722 label = gen_label_rtx ();
2723 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2724 operands[3], label));
2727 operands[2] = force_reg (SImode, operands[2]);
2729 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2737 ;; AIX architecture-independent common-mode multiply (DImode),
2738 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2739 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2740 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2741 ;; assumed unused if generating common-mode, so ignore.
2742 (define_insn "mulh_call"
2745 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2746 (sign_extend:DI (reg:SI 4)))
2748 (clobber (reg:SI LR_REGNO))]
2749 "! TARGET_POWER && ! TARGET_POWERPC"
2751 [(set_attr "type" "imul")])
2753 (define_insn "mull_call"
2755 (mult:DI (sign_extend:DI (reg:SI 3))
2756 (sign_extend:DI (reg:SI 4))))
2757 (clobber (reg:SI LR_REGNO))
2758 (clobber (reg:SI 0))]
2759 "! TARGET_POWER && ! TARGET_POWERPC"
2761 [(set_attr "type" "imul")])
2763 (define_insn "divss_call"
2765 (div:SI (reg:SI 3) (reg:SI 4)))
2767 (mod:SI (reg:SI 3) (reg:SI 4)))
2768 (clobber (reg:SI LR_REGNO))
2769 (clobber (reg:SI 0))]
2770 "! TARGET_POWER && ! TARGET_POWERPC"
2772 [(set_attr "type" "idiv")])
2774 (define_insn "divus_call"
2776 (udiv:SI (reg:SI 3) (reg:SI 4)))
2778 (umod:SI (reg:SI 3) (reg:SI 4)))
2779 (clobber (reg:SI LR_REGNO))
2780 (clobber (reg:SI 0))
2781 (clobber (match_scratch:CC 0 "=x"))
2782 (clobber (reg:CC CR1_REGNO))]
2783 "! TARGET_POWER && ! TARGET_POWERPC"
2785 [(set_attr "type" "idiv")])
2787 (define_insn "quoss_call"
2789 (div:SI (reg:SI 3) (reg:SI 4)))
2790 (clobber (reg:SI LR_REGNO))]
2791 "! TARGET_POWER && ! TARGET_POWERPC"
2793 [(set_attr "type" "idiv")])
2795 (define_insn "quous_call"
2797 (udiv:SI (reg:SI 3) (reg:SI 4)))
2798 (clobber (reg:SI LR_REGNO))
2799 (clobber (reg:SI 0))
2800 (clobber (match_scratch:CC 0 "=x"))
2801 (clobber (reg:CC CR1_REGNO))]
2802 "! TARGET_POWER && ! TARGET_POWERPC"
2804 [(set_attr "type" "idiv")])
2806 ;; Logical instructions
2807 ;; The logical instructions are mostly combined by using match_operator,
2808 ;; but the plain AND insns are somewhat different because there is no
2809 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2810 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2812 (define_insn "andsi3"
2813 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2814 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2815 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2816 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2820 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2821 {andil.|andi.} %0,%1,%b2
2822 {andiu.|andis.} %0,%1,%u2"
2823 [(set_attr "type" "*,*,compare,compare")])
2825 ;; Note to set cr's other than cr0 we do the and immediate and then
2826 ;; the test again -- this avoids a mfcr which on the higher end
2827 ;; machines causes an execution serialization
2829 (define_insn "*andsi3_internal2"
2830 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2831 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2832 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2834 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2835 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2839 {andil.|andi.} %3,%1,%b2
2840 {andiu.|andis.} %3,%1,%u2
2841 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2846 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2847 (set_attr "length" "4,4,4,4,8,8,8,8")])
2849 (define_insn "*andsi3_internal3"
2850 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2851 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2852 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2854 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2855 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2859 {andil.|andi.} %3,%1,%b2
2860 {andiu.|andis.} %3,%1,%u2
2861 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2866 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2867 (set_attr "length" "8,4,4,4,8,8,8,8")])
2870 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2871 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2872 (match_operand:GPR 2 "and_operand" ""))
2874 (clobber (match_scratch:GPR 3 ""))
2875 (clobber (match_scratch:CC 4 ""))]
2877 [(parallel [(set (match_dup 3)
2878 (and:<MODE> (match_dup 1)
2880 (clobber (match_dup 4))])
2882 (compare:CC (match_dup 3)
2886 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2887 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2890 [(set (match_operand:CC 0 "cc_reg_operand" "")
2891 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2892 (match_operand:SI 2 "gpc_reg_operand" ""))
2894 (clobber (match_scratch:SI 3 ""))
2895 (clobber (match_scratch:CC 4 ""))]
2896 "TARGET_POWERPC64 && reload_completed"
2897 [(parallel [(set (match_dup 3)
2898 (and:SI (match_dup 1)
2900 (clobber (match_dup 4))])
2902 (compare:CC (match_dup 3)
2906 (define_insn "*andsi3_internal4"
2907 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2908 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2909 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2911 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2912 (and:SI (match_dup 1)
2914 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2918 {andil.|andi.} %0,%1,%b2
2919 {andiu.|andis.} %0,%1,%u2
2920 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2925 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2926 (set_attr "length" "4,4,4,4,8,8,8,8")])
2928 (define_insn "*andsi3_internal5"
2929 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2930 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2931 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2933 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2934 (and:SI (match_dup 1)
2936 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2940 {andil.|andi.} %0,%1,%b2
2941 {andiu.|andis.} %0,%1,%u2
2942 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2947 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2948 (set_attr "length" "8,4,4,4,8,8,8,8")])
2951 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2952 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2953 (match_operand:SI 2 "and_operand" ""))
2955 (set (match_operand:SI 0 "gpc_reg_operand" "")
2956 (and:SI (match_dup 1)
2958 (clobber (match_scratch:CC 4 ""))]
2960 [(parallel [(set (match_dup 0)
2961 (and:SI (match_dup 1)
2963 (clobber (match_dup 4))])
2965 (compare:CC (match_dup 0)
2970 [(set (match_operand:CC 3 "cc_reg_operand" "")
2971 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2972 (match_operand:SI 2 "gpc_reg_operand" ""))
2974 (set (match_operand:SI 0 "gpc_reg_operand" "")
2975 (and:SI (match_dup 1)
2977 (clobber (match_scratch:CC 4 ""))]
2978 "TARGET_POWERPC64 && reload_completed"
2979 [(parallel [(set (match_dup 0)
2980 (and:SI (match_dup 1)
2982 (clobber (match_dup 4))])
2984 (compare:CC (match_dup 0)
2988 ;; Handle the PowerPC64 rlwinm corner case
2990 (define_insn_and_split "*andsi3_internal6"
2991 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2992 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2993 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2998 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3001 (rotate:SI (match_dup 0) (match_dup 5)))]
3004 int mb = extract_MB (operands[2]);
3005 int me = extract_ME (operands[2]);
3006 operands[3] = GEN_INT (me + 1);
3007 operands[5] = GEN_INT (32 - (me + 1));
3008 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3010 [(set_attr "length" "8")])
3012 (define_expand "iorsi3"
3013 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3014 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
3015 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3019 if (GET_CODE (operands[2]) == CONST_INT
3020 && ! logical_operand (operands[2], SImode))
3022 HOST_WIDE_INT value = INTVAL (operands[2]);
3023 rtx tmp = ((!can_create_pseudo_p ()
3024 || rtx_equal_p (operands[0], operands[1]))
3025 ? operands[0] : gen_reg_rtx (SImode));
3027 emit_insn (gen_iorsi3 (tmp, operands[1],
3028 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3029 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3034 (define_expand "xorsi3"
3035 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3036 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3037 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3041 if (GET_CODE (operands[2]) == CONST_INT
3042 && ! logical_operand (operands[2], SImode))
3044 HOST_WIDE_INT value = INTVAL (operands[2]);
3045 rtx tmp = ((!can_create_pseudo_p ()
3046 || rtx_equal_p (operands[0], operands[1]))
3047 ? operands[0] : gen_reg_rtx (SImode));
3049 emit_insn (gen_xorsi3 (tmp, operands[1],
3050 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3051 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3056 (define_insn "*boolsi3_internal1"
3057 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3058 (match_operator:SI 3 "boolean_or_operator"
3059 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3060 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3064 {%q3il|%q3i} %0,%1,%b2
3065 {%q3iu|%q3is} %0,%1,%u2")
3067 (define_insn "*boolsi3_internal2"
3068 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3069 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3070 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3071 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3073 (clobber (match_scratch:SI 3 "=r,r"))]
3078 [(set_attr "type" "compare")
3079 (set_attr "length" "4,8")])
3082 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3083 (compare:CC (match_operator:SI 4 "boolean_operator"
3084 [(match_operand:SI 1 "gpc_reg_operand" "")
3085 (match_operand:SI 2 "gpc_reg_operand" "")])
3087 (clobber (match_scratch:SI 3 ""))]
3088 "TARGET_32BIT && reload_completed"
3089 [(set (match_dup 3) (match_dup 4))
3091 (compare:CC (match_dup 3)
3095 (define_insn "*boolsi3_internal3"
3096 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3097 (compare:CC (match_operator:SI 4 "boolean_operator"
3098 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3099 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3101 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3107 [(set_attr "type" "compare")
3108 (set_attr "length" "4,8")])
3111 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3112 (compare:CC (match_operator:SI 4 "boolean_operator"
3113 [(match_operand:SI 1 "gpc_reg_operand" "")
3114 (match_operand:SI 2 "gpc_reg_operand" "")])
3116 (set (match_operand:SI 0 "gpc_reg_operand" "")
3118 "TARGET_32BIT && reload_completed"
3119 [(set (match_dup 0) (match_dup 4))
3121 (compare:CC (match_dup 0)
3125 ;; Split a logical operation that we can't do in one insn into two insns,
3126 ;; each of which does one 16-bit part. This is used by combine.
3129 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3130 (match_operator:SI 3 "boolean_or_operator"
3131 [(match_operand:SI 1 "gpc_reg_operand" "")
3132 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3134 [(set (match_dup 0) (match_dup 4))
3135 (set (match_dup 0) (match_dup 5))]
3139 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3140 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3142 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3143 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3147 (define_insn "*boolcsi3_internal1"
3148 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3149 (match_operator:SI 3 "boolean_operator"
3150 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3151 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3155 (define_insn "*boolcsi3_internal2"
3156 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3157 (compare:CC (match_operator:SI 4 "boolean_operator"
3158 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3159 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3161 (clobber (match_scratch:SI 3 "=r,r"))]
3166 [(set_attr "type" "compare")
3167 (set_attr "length" "4,8")])
3170 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3171 (compare:CC (match_operator:SI 4 "boolean_operator"
3172 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3173 (match_operand:SI 2 "gpc_reg_operand" "")])
3175 (clobber (match_scratch:SI 3 ""))]
3176 "TARGET_32BIT && reload_completed"
3177 [(set (match_dup 3) (match_dup 4))
3179 (compare:CC (match_dup 3)
3183 (define_insn "*boolcsi3_internal3"
3184 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3185 (compare:CC (match_operator:SI 4 "boolean_operator"
3186 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3187 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3189 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3195 [(set_attr "type" "compare")
3196 (set_attr "length" "4,8")])
3199 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3200 (compare:CC (match_operator:SI 4 "boolean_operator"
3201 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3202 (match_operand:SI 2 "gpc_reg_operand" "")])
3204 (set (match_operand:SI 0 "gpc_reg_operand" "")
3206 "TARGET_32BIT && reload_completed"
3207 [(set (match_dup 0) (match_dup 4))
3209 (compare:CC (match_dup 0)
3213 (define_insn "*boolccsi3_internal1"
3214 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3215 (match_operator:SI 3 "boolean_operator"
3216 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3217 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3221 (define_insn "*boolccsi3_internal2"
3222 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3223 (compare:CC (match_operator:SI 4 "boolean_operator"
3224 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3225 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3227 (clobber (match_scratch:SI 3 "=r,r"))]
3232 [(set_attr "type" "compare")
3233 (set_attr "length" "4,8")])
3236 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3237 (compare:CC (match_operator:SI 4 "boolean_operator"
3238 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3239 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3241 (clobber (match_scratch:SI 3 ""))]
3242 "TARGET_32BIT && reload_completed"
3243 [(set (match_dup 3) (match_dup 4))
3245 (compare:CC (match_dup 3)
3249 (define_insn "*boolccsi3_internal3"
3250 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3251 (compare:CC (match_operator:SI 4 "boolean_operator"
3252 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3253 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3255 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3261 [(set_attr "type" "compare")
3262 (set_attr "length" "4,8")])
3265 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3266 (compare:CC (match_operator:SI 4 "boolean_operator"
3267 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3268 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3270 (set (match_operand:SI 0 "gpc_reg_operand" "")
3272 "TARGET_32BIT && reload_completed"
3273 [(set (match_dup 0) (match_dup 4))
3275 (compare:CC (match_dup 0)
3279 ;; maskir insn. We need four forms because things might be in arbitrary
3280 ;; orders. Don't define forms that only set CR fields because these
3281 ;; would modify an input register.
3283 (define_insn "*maskir_internal1"
3284 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3285 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3286 (match_operand:SI 1 "gpc_reg_operand" "0"))
3287 (and:SI (match_dup 2)
3288 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3292 (define_insn "*maskir_internal2"
3293 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3294 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3295 (match_operand:SI 1 "gpc_reg_operand" "0"))
3296 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3301 (define_insn "*maskir_internal3"
3302 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3303 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3304 (match_operand:SI 3 "gpc_reg_operand" "r"))
3305 (and:SI (not:SI (match_dup 2))
3306 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3310 (define_insn "*maskir_internal4"
3311 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3312 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3313 (match_operand:SI 2 "gpc_reg_operand" "r"))
3314 (and:SI (not:SI (match_dup 2))
3315 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3319 (define_insn "*maskir_internal5"
3320 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3322 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3323 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3324 (and:SI (match_dup 2)
3325 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3327 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3328 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3329 (and:SI (match_dup 2) (match_dup 3))))]
3334 [(set_attr "type" "compare")
3335 (set_attr "length" "4,8")])
3338 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3340 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3341 (match_operand:SI 1 "gpc_reg_operand" ""))
3342 (and:SI (match_dup 2)
3343 (match_operand:SI 3 "gpc_reg_operand" "")))
3345 (set (match_operand:SI 0 "gpc_reg_operand" "")
3346 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3347 (and:SI (match_dup 2) (match_dup 3))))]
3348 "TARGET_POWER && reload_completed"
3350 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3351 (and:SI (match_dup 2) (match_dup 3))))
3353 (compare:CC (match_dup 0)
3357 (define_insn "*maskir_internal6"
3358 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3360 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3361 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3362 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3365 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3366 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3367 (and:SI (match_dup 3) (match_dup 2))))]
3372 [(set_attr "type" "compare")
3373 (set_attr "length" "4,8")])
3376 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3378 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3379 (match_operand:SI 1 "gpc_reg_operand" ""))
3380 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3383 (set (match_operand:SI 0 "gpc_reg_operand" "")
3384 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3385 (and:SI (match_dup 3) (match_dup 2))))]
3386 "TARGET_POWER && reload_completed"
3388 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3389 (and:SI (match_dup 3) (match_dup 2))))
3391 (compare:CC (match_dup 0)
3395 (define_insn "*maskir_internal7"
3396 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3398 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3399 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3400 (and:SI (not:SI (match_dup 2))
3401 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3403 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3404 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3405 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3410 [(set_attr "type" "compare")
3411 (set_attr "length" "4,8")])
3414 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3416 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3417 (match_operand:SI 3 "gpc_reg_operand" ""))
3418 (and:SI (not:SI (match_dup 2))
3419 (match_operand:SI 1 "gpc_reg_operand" "")))
3421 (set (match_operand:SI 0 "gpc_reg_operand" "")
3422 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3423 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3424 "TARGET_POWER && reload_completed"
3426 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3427 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3429 (compare:CC (match_dup 0)
3433 (define_insn "*maskir_internal8"
3434 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3436 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3437 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3438 (and:SI (not:SI (match_dup 2))
3439 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3441 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3442 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3443 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3448 [(set_attr "type" "compare")
3449 (set_attr "length" "4,8")])
3452 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3454 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3455 (match_operand:SI 2 "gpc_reg_operand" ""))
3456 (and:SI (not:SI (match_dup 2))
3457 (match_operand:SI 1 "gpc_reg_operand" "")))
3459 (set (match_operand:SI 0 "gpc_reg_operand" "")
3460 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3461 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3462 "TARGET_POWER && reload_completed"
3464 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3465 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3467 (compare:CC (match_dup 0)
3471 ;; Rotate and shift insns, in all their variants. These support shifts,
3472 ;; field inserts and extracts, and various combinations thereof.
3473 (define_expand "insv"
3474 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3475 (match_operand:SI 1 "const_int_operand" "")
3476 (match_operand:SI 2 "const_int_operand" ""))
3477 (match_operand 3 "gpc_reg_operand" ""))]
3481 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3482 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3483 compiler if the address of the structure is taken later. Likewise, do
3484 not handle invalid E500 subregs. */
3485 if (GET_CODE (operands[0]) == SUBREG
3486 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3487 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3488 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3491 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3492 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3494 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3498 (define_insn "insvsi"
3499 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3500 (match_operand:SI 1 "const_int_operand" "i")
3501 (match_operand:SI 2 "const_int_operand" "i"))
3502 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3506 int start = INTVAL (operands[2]) & 31;
3507 int size = INTVAL (operands[1]) & 31;
3509 operands[4] = GEN_INT (32 - start - size);
3510 operands[1] = GEN_INT (start + size - 1);
3511 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3513 [(set_attr "type" "insert_word")])
3515 (define_insn "*insvsi_internal1"
3516 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3517 (match_operand:SI 1 "const_int_operand" "i")
3518 (match_operand:SI 2 "const_int_operand" "i"))
3519 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3520 (match_operand:SI 4 "const_int_operand" "i")))]
3521 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3524 int shift = INTVAL (operands[4]) & 31;
3525 int start = INTVAL (operands[2]) & 31;
3526 int size = INTVAL (operands[1]) & 31;
3528 operands[4] = GEN_INT (shift - start - size);
3529 operands[1] = GEN_INT (start + size - 1);
3530 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3532 [(set_attr "type" "insert_word")])
3534 (define_insn "*insvsi_internal2"
3535 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3536 (match_operand:SI 1 "const_int_operand" "i")
3537 (match_operand:SI 2 "const_int_operand" "i"))
3538 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3539 (match_operand:SI 4 "const_int_operand" "i")))]
3540 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3543 int shift = INTVAL (operands[4]) & 31;
3544 int start = INTVAL (operands[2]) & 31;
3545 int size = INTVAL (operands[1]) & 31;
3547 operands[4] = GEN_INT (32 - shift - start - size);
3548 operands[1] = GEN_INT (start + size - 1);
3549 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3551 [(set_attr "type" "insert_word")])
3553 (define_insn "*insvsi_internal3"
3554 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3555 (match_operand:SI 1 "const_int_operand" "i")
3556 (match_operand:SI 2 "const_int_operand" "i"))
3557 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3558 (match_operand:SI 4 "const_int_operand" "i")))]
3559 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3562 int shift = INTVAL (operands[4]) & 31;
3563 int start = INTVAL (operands[2]) & 31;
3564 int size = INTVAL (operands[1]) & 31;
3566 operands[4] = GEN_INT (32 - shift - start - size);
3567 operands[1] = GEN_INT (start + size - 1);
3568 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3570 [(set_attr "type" "insert_word")])
3572 (define_insn "*insvsi_internal4"
3573 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3574 (match_operand:SI 1 "const_int_operand" "i")
3575 (match_operand:SI 2 "const_int_operand" "i"))
3576 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3577 (match_operand:SI 4 "const_int_operand" "i")
3578 (match_operand:SI 5 "const_int_operand" "i")))]
3579 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3582 int extract_start = INTVAL (operands[5]) & 31;
3583 int extract_size = INTVAL (operands[4]) & 31;
3584 int insert_start = INTVAL (operands[2]) & 31;
3585 int insert_size = INTVAL (operands[1]) & 31;
3587 /* Align extract field with insert field */
3588 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3589 operands[1] = GEN_INT (insert_start + insert_size - 1);
3590 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3592 [(set_attr "type" "insert_word")])
3594 ;; combine patterns for rlwimi
3595 (define_insn "*insvsi_internal5"
3596 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3597 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3598 (match_operand:SI 1 "mask_operand" "i"))
3599 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3600 (match_operand:SI 2 "const_int_operand" "i"))
3601 (match_operand:SI 5 "mask_operand" "i"))))]
3602 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3605 int me = extract_ME(operands[5]);
3606 int mb = extract_MB(operands[5]);
3607 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3608 operands[2] = GEN_INT(mb);
3609 operands[1] = GEN_INT(me);
3610 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3612 [(set_attr "type" "insert_word")])
3614 (define_insn "*insvsi_internal6"
3615 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3616 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3617 (match_operand:SI 2 "const_int_operand" "i"))
3618 (match_operand:SI 5 "mask_operand" "i"))
3619 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3620 (match_operand:SI 1 "mask_operand" "i"))))]
3621 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3624 int me = extract_ME(operands[5]);
3625 int mb = extract_MB(operands[5]);
3626 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3627 operands[2] = GEN_INT(mb);
3628 operands[1] = GEN_INT(me);
3629 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3631 [(set_attr "type" "insert_word")])
3633 (define_insn "insvdi"
3634 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3635 (match_operand:SI 1 "const_int_operand" "i")
3636 (match_operand:SI 2 "const_int_operand" "i"))
3637 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3641 int start = INTVAL (operands[2]) & 63;
3642 int size = INTVAL (operands[1]) & 63;
3644 operands[1] = GEN_INT (64 - start - size);
3645 return \"rldimi %0,%3,%H1,%H2\";
3647 [(set_attr "type" "insert_dword")])
3649 (define_insn "*insvdi_internal2"
3650 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3651 (match_operand:SI 1 "const_int_operand" "i")
3652 (match_operand:SI 2 "const_int_operand" "i"))
3653 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3654 (match_operand:SI 4 "const_int_operand" "i")))]
3656 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3659 int shift = INTVAL (operands[4]) & 63;
3660 int start = (INTVAL (operands[2]) & 63) - 32;
3661 int size = INTVAL (operands[1]) & 63;
3663 operands[4] = GEN_INT (64 - shift - start - size);
3664 operands[2] = GEN_INT (start);
3665 operands[1] = GEN_INT (start + size - 1);
3666 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3669 (define_insn "*insvdi_internal3"
3670 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3671 (match_operand:SI 1 "const_int_operand" "i")
3672 (match_operand:SI 2 "const_int_operand" "i"))
3673 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3674 (match_operand:SI 4 "const_int_operand" "i")))]
3676 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3679 int shift = INTVAL (operands[4]) & 63;
3680 int start = (INTVAL (operands[2]) & 63) - 32;
3681 int size = INTVAL (operands[1]) & 63;
3683 operands[4] = GEN_INT (64 - shift - start - size);
3684 operands[2] = GEN_INT (start);
3685 operands[1] = GEN_INT (start + size - 1);
3686 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3689 (define_expand "extzv"
3690 [(set (match_operand 0 "gpc_reg_operand" "")
3691 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3692 (match_operand:SI 2 "const_int_operand" "")
3693 (match_operand:SI 3 "const_int_operand" "")))]
3697 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3698 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3699 compiler if the address of the structure is taken later. */
3700 if (GET_CODE (operands[0]) == SUBREG
3701 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3704 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3705 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3707 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3711 (define_insn "extzvsi"
3712 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3713 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3714 (match_operand:SI 2 "const_int_operand" "i")
3715 (match_operand:SI 3 "const_int_operand" "i")))]
3719 int start = INTVAL (operands[3]) & 31;
3720 int size = INTVAL (operands[2]) & 31;
3722 if (start + size >= 32)
3723 operands[3] = const0_rtx;
3725 operands[3] = GEN_INT (start + size);
3726 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3729 (define_insn "*extzvsi_internal1"
3730 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3731 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3732 (match_operand:SI 2 "const_int_operand" "i,i")
3733 (match_operand:SI 3 "const_int_operand" "i,i"))
3735 (clobber (match_scratch:SI 4 "=r,r"))]
3739 int start = INTVAL (operands[3]) & 31;
3740 int size = INTVAL (operands[2]) & 31;
3742 /* Force split for non-cc0 compare. */
3743 if (which_alternative == 1)
3746 /* If the bit-field being tested fits in the upper or lower half of a
3747 word, it is possible to use andiu. or andil. to test it. This is
3748 useful because the condition register set-use delay is smaller for
3749 andi[ul]. than for rlinm. This doesn't work when the starting bit
3750 position is 0 because the LT and GT bits may be set wrong. */
3752 if ((start > 0 && start + size <= 16) || start >= 16)
3754 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3755 - (1 << (16 - (start & 15) - size))));
3757 return \"{andiu.|andis.} %4,%1,%3\";
3759 return \"{andil.|andi.} %4,%1,%3\";
3762 if (start + size >= 32)
3763 operands[3] = const0_rtx;
3765 operands[3] = GEN_INT (start + size);
3766 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3768 [(set_attr "type" "delayed_compare")
3769 (set_attr "length" "4,8")])
3772 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3773 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3774 (match_operand:SI 2 "const_int_operand" "")
3775 (match_operand:SI 3 "const_int_operand" ""))
3777 (clobber (match_scratch:SI 4 ""))]
3780 (zero_extract:SI (match_dup 1) (match_dup 2)
3783 (compare:CC (match_dup 4)
3787 (define_insn "*extzvsi_internal2"
3788 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3789 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3790 (match_operand:SI 2 "const_int_operand" "i,i")
3791 (match_operand:SI 3 "const_int_operand" "i,i"))
3793 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3794 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3798 int start = INTVAL (operands[3]) & 31;
3799 int size = INTVAL (operands[2]) & 31;
3801 /* Force split for non-cc0 compare. */
3802 if (which_alternative == 1)
3805 /* Since we are using the output value, we can't ignore any need for
3806 a shift. The bit-field must end at the LSB. */
3807 if (start >= 16 && start + size == 32)
3809 operands[3] = GEN_INT ((1 << size) - 1);
3810 return \"{andil.|andi.} %0,%1,%3\";
3813 if (start + size >= 32)
3814 operands[3] = const0_rtx;
3816 operands[3] = GEN_INT (start + size);
3817 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3819 [(set_attr "type" "delayed_compare")
3820 (set_attr "length" "4,8")])
3823 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3824 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3825 (match_operand:SI 2 "const_int_operand" "")
3826 (match_operand:SI 3 "const_int_operand" ""))
3828 (set (match_operand:SI 0 "gpc_reg_operand" "")
3829 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3832 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3834 (compare:CC (match_dup 0)
3838 (define_insn "extzvdi"
3839 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3840 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3841 (match_operand:SI 2 "const_int_operand" "i")
3842 (match_operand:SI 3 "const_int_operand" "i")))]
3846 int start = INTVAL (operands[3]) & 63;
3847 int size = INTVAL (operands[2]) & 63;
3849 if (start + size >= 64)
3850 operands[3] = const0_rtx;
3852 operands[3] = GEN_INT (start + size);
3853 operands[2] = GEN_INT (64 - size);
3854 return \"rldicl %0,%1,%3,%2\";
3857 (define_insn "*extzvdi_internal1"
3858 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3859 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3860 (match_operand:SI 2 "const_int_operand" "i")
3861 (match_operand:SI 3 "const_int_operand" "i"))
3863 (clobber (match_scratch:DI 4 "=r"))]
3867 int start = INTVAL (operands[3]) & 63;
3868 int size = INTVAL (operands[2]) & 63;
3870 if (start + size >= 64)
3871 operands[3] = const0_rtx;
3873 operands[3] = GEN_INT (start + size);
3874 operands[2] = GEN_INT (64 - size);
3875 return \"rldicl. %4,%1,%3,%2\";
3877 [(set_attr "type" "compare")])
3879 (define_insn "*extzvdi_internal2"
3880 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3881 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3882 (match_operand:SI 2 "const_int_operand" "i")
3883 (match_operand:SI 3 "const_int_operand" "i"))
3885 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3886 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3890 int start = INTVAL (operands[3]) & 63;
3891 int size = INTVAL (operands[2]) & 63;
3893 if (start + size >= 64)
3894 operands[3] = const0_rtx;
3896 operands[3] = GEN_INT (start + size);
3897 operands[2] = GEN_INT (64 - size);
3898 return \"rldicl. %0,%1,%3,%2\";
3900 [(set_attr "type" "compare")])
3902 (define_insn "rotlsi3"
3903 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3904 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3905 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
3908 {rlnm|rlwnm} %0,%1,%2,0xffffffff
3909 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
3910 [(set_attr "type" "var_shift_rotate,integer")])
3912 (define_insn "*rotlsi3_internal2"
3913 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3914 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3915 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3917 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3920 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
3921 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
3924 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3925 (set_attr "length" "4,4,8,8")])
3928 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3929 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3930 (match_operand:SI 2 "reg_or_cint_operand" ""))
3932 (clobber (match_scratch:SI 3 ""))]
3935 (rotate:SI (match_dup 1) (match_dup 2)))
3937 (compare:CC (match_dup 3)
3941 (define_insn "*rotlsi3_internal3"
3942 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3943 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3944 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3946 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3947 (rotate:SI (match_dup 1) (match_dup 2)))]
3950 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
3951 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
3954 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3955 (set_attr "length" "4,4,8,8")])
3958 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3959 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3960 (match_operand:SI 2 "reg_or_cint_operand" ""))
3962 (set (match_operand:SI 0 "gpc_reg_operand" "")
3963 (rotate:SI (match_dup 1) (match_dup 2)))]
3966 (rotate:SI (match_dup 1) (match_dup 2)))
3968 (compare:CC (match_dup 0)
3972 (define_insn "*rotlsi3_internal4"
3973 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3974 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3975 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
3976 (match_operand:SI 3 "mask_operand" "n,n")))]
3979 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
3980 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
3981 [(set_attr "type" "var_shift_rotate,integer")])
3983 (define_insn "*rotlsi3_internal5"
3984 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3986 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3987 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3988 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3990 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
3993 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
3994 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3997 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3998 (set_attr "length" "4,4,8,8")])
4001 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4003 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4004 (match_operand:SI 2 "reg_or_cint_operand" ""))
4005 (match_operand:SI 3 "mask_operand" ""))
4007 (clobber (match_scratch:SI 4 ""))]
4010 (and:SI (rotate:SI (match_dup 1)
4014 (compare:CC (match_dup 4)
4018 (define_insn "*rotlsi3_internal6"
4019 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
4021 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4022 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4023 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4025 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4026 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4029 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
4030 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4033 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4034 (set_attr "length" "4,4,8,8")])
4037 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4039 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4040 (match_operand:SI 2 "reg_or_cint_operand" ""))
4041 (match_operand:SI 3 "mask_operand" ""))
4043 (set (match_operand:SI 0 "gpc_reg_operand" "")
4044 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4047 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4049 (compare:CC (match_dup 0)
4053 (define_insn "*rotlsi3_internal7"
4054 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4057 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4058 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4060 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
4062 (define_insn "*rotlsi3_internal8"
4063 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4064 (compare:CC (zero_extend:SI
4066 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4067 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4069 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4072 {rlnm.|rlwnm.} %3,%1,%2,0xff
4073 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4076 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4077 (set_attr "length" "4,4,8,8")])
4080 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4081 (compare:CC (zero_extend:SI
4083 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4084 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4086 (clobber (match_scratch:SI 3 ""))]
4089 (zero_extend:SI (subreg:QI
4090 (rotate:SI (match_dup 1)
4093 (compare:CC (match_dup 3)
4097 (define_insn "*rotlsi3_internal9"
4098 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4099 (compare:CC (zero_extend:SI
4101 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4102 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4104 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4105 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4108 {rlnm.|rlwnm.} %0,%1,%2,0xff
4109 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4112 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4113 (set_attr "length" "4,4,8,8")])
4116 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4117 (compare:CC (zero_extend:SI
4119 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4120 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4122 (set (match_operand:SI 0 "gpc_reg_operand" "")
4123 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4126 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4128 (compare:CC (match_dup 0)
4132 (define_insn "*rotlsi3_internal10"
4133 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4136 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4137 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4140 {rlnm|rlwnm} %0,%1,%2,0xffff
4141 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4142 [(set_attr "type" "var_shift_rotate,integer")])
4145 (define_insn "*rotlsi3_internal11"
4146 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4147 (compare:CC (zero_extend:SI
4149 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4150 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4152 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4155 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4156 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4159 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4160 (set_attr "length" "4,4,8,8")])
4163 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4164 (compare:CC (zero_extend:SI
4166 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4167 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4169 (clobber (match_scratch:SI 3 ""))]
4172 (zero_extend:SI (subreg:HI
4173 (rotate:SI (match_dup 1)
4176 (compare:CC (match_dup 3)
4180 (define_insn "*rotlsi3_internal12"
4181 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4182 (compare:CC (zero_extend:SI
4184 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4185 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4187 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4188 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4191 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4192 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4195 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4196 (set_attr "length" "4,4,8,8")])
4199 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4200 (compare:CC (zero_extend:SI
4202 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4203 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4205 (set (match_operand:SI 0 "gpc_reg_operand" "")
4206 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4209 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4211 (compare:CC (match_dup 0)
4215 ;; Note that we use "sle." instead of "sl." so that we can set
4216 ;; SHIFT_COUNT_TRUNCATED.
4218 (define_expand "ashlsi3"
4219 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4220 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4221 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4226 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4228 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4232 (define_insn "ashlsi3_power"
4233 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4234 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4235 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4236 (clobber (match_scratch:SI 3 "=q,X"))]
4240 {sli|slwi} %0,%1,%h2")
4242 (define_insn "ashlsi3_no_power"
4243 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4244 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4245 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4249 {sli|slwi} %0,%1,%h2"
4250 [(set_attr "type" "var_shift_rotate,shift")])
4253 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4254 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4255 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4257 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4258 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4262 {sli.|slwi.} %3,%1,%h2
4265 [(set_attr "type" "delayed_compare")
4266 (set_attr "length" "4,4,8,8")])
4269 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4270 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4271 (match_operand:SI 2 "reg_or_cint_operand" ""))
4273 (clobber (match_scratch:SI 3 ""))
4274 (clobber (match_scratch:SI 4 ""))]
4275 "TARGET_POWER && reload_completed"
4276 [(parallel [(set (match_dup 3)
4277 (ashift:SI (match_dup 1) (match_dup 2)))
4278 (clobber (match_dup 4))])
4280 (compare:CC (match_dup 3)
4285 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4286 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4287 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4289 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4290 "! TARGET_POWER && TARGET_32BIT"
4293 {sli.|slwi.} %3,%1,%h2
4296 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4297 (set_attr "length" "4,4,8,8")])
4300 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4301 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4302 (match_operand:SI 2 "reg_or_cint_operand" ""))
4304 (clobber (match_scratch:SI 3 ""))]
4305 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4307 (ashift:SI (match_dup 1) (match_dup 2)))
4309 (compare:CC (match_dup 3)
4314 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4315 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4316 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4318 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4319 (ashift:SI (match_dup 1) (match_dup 2)))
4320 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4324 {sli.|slwi.} %0,%1,%h2
4327 [(set_attr "type" "delayed_compare")
4328 (set_attr "length" "4,4,8,8")])
4331 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4332 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4333 (match_operand:SI 2 "reg_or_cint_operand" ""))
4335 (set (match_operand:SI 0 "gpc_reg_operand" "")
4336 (ashift:SI (match_dup 1) (match_dup 2)))
4337 (clobber (match_scratch:SI 4 ""))]
4338 "TARGET_POWER && reload_completed"
4339 [(parallel [(set (match_dup 0)
4340 (ashift:SI (match_dup 1) (match_dup 2)))
4341 (clobber (match_dup 4))])
4343 (compare:CC (match_dup 0)
4348 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4349 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4350 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4352 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4353 (ashift:SI (match_dup 1) (match_dup 2)))]
4354 "! TARGET_POWER && TARGET_32BIT"
4357 {sli.|slwi.} %0,%1,%h2
4360 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4361 (set_attr "length" "4,4,8,8")])
4364 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4365 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4366 (match_operand:SI 2 "reg_or_cint_operand" ""))
4368 (set (match_operand:SI 0 "gpc_reg_operand" "")
4369 (ashift:SI (match_dup 1) (match_dup 2)))]
4370 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4372 (ashift:SI (match_dup 1) (match_dup 2)))
4374 (compare:CC (match_dup 0)
4378 (define_insn "rlwinm"
4379 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4380 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4381 (match_operand:SI 2 "const_int_operand" "i"))
4382 (match_operand:SI 3 "mask_operand" "n")))]
4383 "includes_lshift_p (operands[2], operands[3])"
4384 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4387 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4389 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4390 (match_operand:SI 2 "const_int_operand" "i,i"))
4391 (match_operand:SI 3 "mask_operand" "n,n"))
4393 (clobber (match_scratch:SI 4 "=r,r"))]
4394 "includes_lshift_p (operands[2], operands[3])"
4396 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4398 [(set_attr "type" "delayed_compare")
4399 (set_attr "length" "4,8")])
4402 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4404 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4405 (match_operand:SI 2 "const_int_operand" ""))
4406 (match_operand:SI 3 "mask_operand" ""))
4408 (clobber (match_scratch:SI 4 ""))]
4409 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4411 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4414 (compare:CC (match_dup 4)
4419 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4421 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4422 (match_operand:SI 2 "const_int_operand" "i,i"))
4423 (match_operand:SI 3 "mask_operand" "n,n"))
4425 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4426 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4427 "includes_lshift_p (operands[2], operands[3])"
4429 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4431 [(set_attr "type" "delayed_compare")
4432 (set_attr "length" "4,8")])
4435 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4437 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4438 (match_operand:SI 2 "const_int_operand" ""))
4439 (match_operand:SI 3 "mask_operand" ""))
4441 (set (match_operand:SI 0 "gpc_reg_operand" "")
4442 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4443 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4445 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4447 (compare:CC (match_dup 0)
4451 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
4453 (define_expand "lshrsi3"
4454 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4455 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4456 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4461 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4463 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
4467 (define_insn "lshrsi3_power"
4468 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4469 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4470 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4471 (clobber (match_scratch:SI 3 "=q,X,X"))]
4476 {s%A2i|s%A2wi} %0,%1,%h2")
4478 (define_insn "lshrsi3_no_power"
4479 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4480 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4481 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
4486 {sri|srwi} %0,%1,%h2"
4487 [(set_attr "type" "integer,var_shift_rotate,shift")])
4490 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4491 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4492 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4494 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4495 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4500 {s%A2i.|s%A2wi.} %3,%1,%h2
4504 [(set_attr "type" "delayed_compare")
4505 (set_attr "length" "4,4,4,8,8,8")])
4508 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4509 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4510 (match_operand:SI 2 "reg_or_cint_operand" ""))
4512 (clobber (match_scratch:SI 3 ""))
4513 (clobber (match_scratch:SI 4 ""))]
4514 "TARGET_POWER && reload_completed"
4515 [(parallel [(set (match_dup 3)
4516 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4517 (clobber (match_dup 4))])
4519 (compare:CC (match_dup 3)
4524 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4525 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4526 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4528 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4529 "! TARGET_POWER && TARGET_32BIT"
4533 {sri.|srwi.} %3,%1,%h2
4537 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4538 (set_attr "length" "4,4,4,8,8,8")])
4541 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4542 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4543 (match_operand:SI 2 "reg_or_cint_operand" ""))
4545 (clobber (match_scratch:SI 3 ""))]
4546 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4548 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4550 (compare:CC (match_dup 3)
4555 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4556 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4557 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4559 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4560 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4561 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4566 {s%A2i.|s%A2wi.} %0,%1,%h2
4570 [(set_attr "type" "delayed_compare")
4571 (set_attr "length" "4,4,4,8,8,8")])
4574 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4575 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4576 (match_operand:SI 2 "reg_or_cint_operand" ""))
4578 (set (match_operand:SI 0 "gpc_reg_operand" "")
4579 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4580 (clobber (match_scratch:SI 4 ""))]
4581 "TARGET_POWER && reload_completed"
4582 [(parallel [(set (match_dup 0)
4583 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4584 (clobber (match_dup 4))])
4586 (compare:CC (match_dup 0)
4591 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4592 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4593 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4595 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4596 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4597 "! TARGET_POWER && TARGET_32BIT"
4601 {sri.|srwi.} %0,%1,%h2
4605 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4606 (set_attr "length" "4,4,4,8,8,8")])
4609 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4610 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4611 (match_operand:SI 2 "reg_or_cint_operand" ""))
4613 (set (match_operand:SI 0 "gpc_reg_operand" "")
4614 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4615 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4617 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4619 (compare:CC (match_dup 0)
4624 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4625 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4626 (match_operand:SI 2 "const_int_operand" "i"))
4627 (match_operand:SI 3 "mask_operand" "n")))]
4628 "includes_rshift_p (operands[2], operands[3])"
4629 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4632 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4634 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4635 (match_operand:SI 2 "const_int_operand" "i,i"))
4636 (match_operand:SI 3 "mask_operand" "n,n"))
4638 (clobber (match_scratch:SI 4 "=r,r"))]
4639 "includes_rshift_p (operands[2], operands[3])"
4641 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4643 [(set_attr "type" "delayed_compare")
4644 (set_attr "length" "4,8")])
4647 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4649 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4650 (match_operand:SI 2 "const_int_operand" ""))
4651 (match_operand:SI 3 "mask_operand" ""))
4653 (clobber (match_scratch:SI 4 ""))]
4654 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4656 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4659 (compare:CC (match_dup 4)
4664 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4666 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4667 (match_operand:SI 2 "const_int_operand" "i,i"))
4668 (match_operand:SI 3 "mask_operand" "n,n"))
4670 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4671 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4672 "includes_rshift_p (operands[2], operands[3])"
4674 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4676 [(set_attr "type" "delayed_compare")
4677 (set_attr "length" "4,8")])
4680 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4682 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4683 (match_operand:SI 2 "const_int_operand" ""))
4684 (match_operand:SI 3 "mask_operand" ""))
4686 (set (match_operand:SI 0 "gpc_reg_operand" "")
4687 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4688 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4690 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4692 (compare:CC (match_dup 0)
4697 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4700 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4701 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4702 "includes_rshift_p (operands[2], GEN_INT (255))"
4703 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4706 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4710 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4711 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4713 (clobber (match_scratch:SI 3 "=r,r"))]
4714 "includes_rshift_p (operands[2], GEN_INT (255))"
4716 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4718 [(set_attr "type" "delayed_compare")
4719 (set_attr "length" "4,8")])
4722 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4726 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4727 (match_operand:SI 2 "const_int_operand" "")) 0))
4729 (clobber (match_scratch:SI 3 ""))]
4730 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4732 (zero_extend:SI (subreg:QI
4733 (lshiftrt:SI (match_dup 1)
4736 (compare:CC (match_dup 3)
4741 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4745 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4746 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4748 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4749 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4750 "includes_rshift_p (operands[2], GEN_INT (255))"
4752 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4754 [(set_attr "type" "delayed_compare")
4755 (set_attr "length" "4,8")])
4758 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4762 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4763 (match_operand:SI 2 "const_int_operand" "")) 0))
4765 (set (match_operand:SI 0 "gpc_reg_operand" "")
4766 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4767 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4769 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4771 (compare:CC (match_dup 0)
4776 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4779 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4780 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4781 "includes_rshift_p (operands[2], GEN_INT (65535))"
4782 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4785 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4789 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4790 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4792 (clobber (match_scratch:SI 3 "=r,r"))]
4793 "includes_rshift_p (operands[2], GEN_INT (65535))"
4795 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4797 [(set_attr "type" "delayed_compare")
4798 (set_attr "length" "4,8")])
4801 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4805 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4806 (match_operand:SI 2 "const_int_operand" "")) 0))
4808 (clobber (match_scratch:SI 3 ""))]
4809 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4811 (zero_extend:SI (subreg:HI
4812 (lshiftrt:SI (match_dup 1)
4815 (compare:CC (match_dup 3)
4820 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4824 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4825 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4827 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4828 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4829 "includes_rshift_p (operands[2], GEN_INT (65535))"
4831 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4833 [(set_attr "type" "delayed_compare")
4834 (set_attr "length" "4,8")])
4837 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4841 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4842 (match_operand:SI 2 "const_int_operand" "")) 0))
4844 (set (match_operand:SI 0 "gpc_reg_operand" "")
4845 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4846 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4848 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4850 (compare:CC (match_dup 0)
4855 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4857 (match_operand:SI 1 "gpc_reg_operand" "r"))
4858 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4864 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4866 (match_operand:SI 1 "gpc_reg_operand" "r"))
4867 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4873 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4875 (match_operand:SI 1 "gpc_reg_operand" "r"))
4876 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4882 (define_expand "ashrsi3"
4883 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4884 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4885 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4890 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4892 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4896 (define_insn "ashrsi3_power"
4897 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4898 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4899 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4900 (clobber (match_scratch:SI 3 "=q,X"))]
4904 {srai|srawi} %0,%1,%h2"
4905 [(set_attr "type" "shift")])
4907 (define_insn "ashrsi3_no_power"
4908 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4909 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4910 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4914 {srai|srawi} %0,%1,%h2"
4915 [(set_attr "type" "var_shift_rotate,shift")])
4918 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4919 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4920 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4922 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4923 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4927 {srai.|srawi.} %3,%1,%h2
4930 [(set_attr "type" "delayed_compare")
4931 (set_attr "length" "4,4,8,8")])
4934 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4935 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4936 (match_operand:SI 2 "reg_or_cint_operand" ""))
4938 (clobber (match_scratch:SI 3 ""))
4939 (clobber (match_scratch:SI 4 ""))]
4940 "TARGET_POWER && reload_completed"
4941 [(parallel [(set (match_dup 3)
4942 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4943 (clobber (match_dup 4))])
4945 (compare:CC (match_dup 3)
4950 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4951 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4952 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4954 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4957 {sra.|sraw.} %3,%1,%2
4958 {srai.|srawi.} %3,%1,%h2
4961 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4962 (set_attr "length" "4,4,8,8")])
4965 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4966 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4967 (match_operand:SI 2 "reg_or_cint_operand" ""))
4969 (clobber (match_scratch:SI 3 ""))]
4970 "! TARGET_POWER && reload_completed"
4972 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4974 (compare:CC (match_dup 3)
4979 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4980 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4981 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4983 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4984 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4985 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4989 {srai.|srawi.} %0,%1,%h2
4992 [(set_attr "type" "delayed_compare")
4993 (set_attr "length" "4,4,8,8")])
4996 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4997 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4998 (match_operand:SI 2 "reg_or_cint_operand" ""))
5000 (set (match_operand:SI 0 "gpc_reg_operand" "")
5001 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5002 (clobber (match_scratch:SI 4 ""))]
5003 "TARGET_POWER && reload_completed"
5004 [(parallel [(set (match_dup 0)
5005 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5006 (clobber (match_dup 4))])
5008 (compare:CC (match_dup 0)
5013 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5014 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5015 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5017 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5018 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5021 {sra.|sraw.} %0,%1,%2
5022 {srai.|srawi.} %0,%1,%h2
5025 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5026 (set_attr "length" "4,4,8,8")])
5029 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5030 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5031 (match_operand:SI 2 "reg_or_cint_operand" ""))
5033 (set (match_operand:SI 0 "gpc_reg_operand" "")
5034 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5035 "! TARGET_POWER && reload_completed"
5037 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5039 (compare:CC (match_dup 0)
5043 ;; Floating-point insns, excluding normal data motion.
5045 ;; PowerPC has a full set of single-precision floating point instructions.
5047 ;; For the POWER architecture, we pretend that we have both SFmode and
5048 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
5049 ;; The only conversions we will do will be when storing to memory. In that
5050 ;; case, we will use the "frsp" instruction before storing.
5052 ;; Note that when we store into a single-precision memory location, we need to
5053 ;; use the frsp insn first. If the register being stored isn't dead, we
5054 ;; need a scratch register for the frsp. But this is difficult when the store
5055 ;; is done by reload. It is not incorrect to do the frsp on the register in
5056 ;; this case, we just lose precision that we would have otherwise gotten but
5057 ;; is not guaranteed. Perhaps this should be tightened up at some point.
5059 (define_expand "extendsfdf2"
5060 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5061 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5062 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5065 (define_insn_and_split "*extendsfdf2_fpr"
5066 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
5067 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
5068 "TARGET_HARD_FLOAT && TARGET_FPRS"
5073 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5076 emit_note (NOTE_INSN_DELETED);
5079 [(set_attr "type" "fp,fp,fpload")])
5081 (define_expand "truncdfsf2"
5082 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5083 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5084 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5087 (define_insn "*truncdfsf2_fpr"
5088 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5089 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5090 "TARGET_HARD_FLOAT && TARGET_FPRS"
5092 [(set_attr "type" "fp")])
5094 (define_insn "aux_truncdfsf2"
5095 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5096 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
5097 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5099 [(set_attr "type" "fp")])
5101 (define_expand "negsf2"
5102 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5103 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5107 (define_insn "*negsf2"
5108 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5109 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5110 "TARGET_HARD_FLOAT && TARGET_FPRS"
5112 [(set_attr "type" "fp")])
5114 (define_expand "abssf2"
5115 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5116 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5120 (define_insn "*abssf2"
5121 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5122 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5123 "TARGET_HARD_FLOAT && TARGET_FPRS"
5125 [(set_attr "type" "fp")])
5128 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5129 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
5130 "TARGET_HARD_FLOAT && TARGET_FPRS"
5132 [(set_attr "type" "fp")])
5134 (define_expand "addsf3"
5135 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5136 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5137 (match_operand:SF 2 "gpc_reg_operand" "")))]
5142 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5143 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5144 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5145 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5147 [(set_attr "type" "fp")])
5150 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5151 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5152 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5153 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5154 "{fa|fadd} %0,%1,%2"
5155 [(set_attr "type" "fp")])
5157 (define_expand "subsf3"
5158 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5159 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5160 (match_operand:SF 2 "gpc_reg_operand" "")))]
5165 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5166 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5167 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5168 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5170 [(set_attr "type" "fp")])
5173 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5174 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5175 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5176 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5177 "{fs|fsub} %0,%1,%2"
5178 [(set_attr "type" "fp")])
5180 (define_expand "mulsf3"
5181 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5182 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5183 (match_operand:SF 2 "gpc_reg_operand" "")))]
5188 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5189 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5190 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5191 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5193 [(set_attr "type" "fp")])
5196 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5197 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5198 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5199 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5200 "{fm|fmul} %0,%1,%2"
5201 [(set_attr "type" "dmul")])
5203 (define_expand "divsf3"
5204 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5205 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5206 (match_operand:SF 2 "gpc_reg_operand" "")))]
5211 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5212 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5213 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5214 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5216 [(set_attr "type" "sdiv")])
5219 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5220 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5221 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5222 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5223 "{fd|fdiv} %0,%1,%2"
5224 [(set_attr "type" "ddiv")])
5226 (define_expand "recipsf3"
5227 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5228 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")
5229 (match_operand:SF 2 "gpc_reg_operand" "f")]
5231 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5232 && flag_finite_math_only && !flag_trapping_math"
5234 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5239 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5240 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5241 "TARGET_PPC_GFXOPT && flag_finite_math_only"
5243 [(set_attr "type" "fp")])
5246 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5247 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5248 (match_operand:SF 2 "gpc_reg_operand" "f"))
5249 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5250 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5251 "fmadds %0,%1,%2,%3"
5252 [(set_attr "type" "fp")])
5255 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5256 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5257 (match_operand:SF 2 "gpc_reg_operand" "f"))
5258 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5259 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5260 "{fma|fmadd} %0,%1,%2,%3"
5261 [(set_attr "type" "dmul")])
5264 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5265 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5266 (match_operand:SF 2 "gpc_reg_operand" "f"))
5267 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5268 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5269 "fmsubs %0,%1,%2,%3"
5270 [(set_attr "type" "fp")])
5273 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5274 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5275 (match_operand:SF 2 "gpc_reg_operand" "f"))
5276 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5277 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5278 "{fms|fmsub} %0,%1,%2,%3"
5279 [(set_attr "type" "dmul")])
5282 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5283 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5284 (match_operand:SF 2 "gpc_reg_operand" "f"))
5285 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5286 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5287 && HONOR_SIGNED_ZEROS (SFmode)"
5288 "fnmadds %0,%1,%2,%3"
5289 [(set_attr "type" "fp")])
5292 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5293 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5294 (match_operand:SF 2 "gpc_reg_operand" "f"))
5295 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5296 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5297 && ! HONOR_SIGNED_ZEROS (SFmode)"
5298 "fnmadds %0,%1,%2,%3"
5299 [(set_attr "type" "fp")])
5302 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5303 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5304 (match_operand:SF 2 "gpc_reg_operand" "f"))
5305 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5306 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5307 "{fnma|fnmadd} %0,%1,%2,%3"
5308 [(set_attr "type" "dmul")])
5311 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5312 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5313 (match_operand:SF 2 "gpc_reg_operand" "f"))
5314 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5315 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5316 && ! HONOR_SIGNED_ZEROS (SFmode)"
5317 "{fnma|fnmadd} %0,%1,%2,%3"
5318 [(set_attr "type" "dmul")])
5321 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5322 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5323 (match_operand:SF 2 "gpc_reg_operand" "f"))
5324 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5325 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5326 && HONOR_SIGNED_ZEROS (SFmode)"
5327 "fnmsubs %0,%1,%2,%3"
5328 [(set_attr "type" "fp")])
5331 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5332 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5333 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5334 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5335 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5336 && ! HONOR_SIGNED_ZEROS (SFmode)"
5337 "fnmsubs %0,%1,%2,%3"
5338 [(set_attr "type" "fp")])
5341 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5342 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5343 (match_operand:SF 2 "gpc_reg_operand" "f"))
5344 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5345 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5346 "{fnms|fnmsub} %0,%1,%2,%3"
5347 [(set_attr "type" "dmul")])
5350 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5351 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5352 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5353 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5354 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5355 && ! HONOR_SIGNED_ZEROS (SFmode)"
5356 "{fnms|fnmsub} %0,%1,%2,%3"
5357 [(set_attr "type" "dmul")])
5359 (define_expand "sqrtsf2"
5360 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5361 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5362 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5366 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5367 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5368 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5370 [(set_attr "type" "ssqrt")])
5373 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5374 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5375 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
5377 [(set_attr "type" "dsqrt")])
5379 (define_expand "rsqrtsf2"
5380 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5381 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5383 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5384 && flag_finite_math_only && !flag_trapping_math"
5386 rs6000_emit_swrsqrtsf (operands[0], operands[1]);
5390 (define_insn "*rsqrt_internal1"
5391 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5392 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5394 "TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT"
5396 [(set_attr "type" "fp")])
5398 (define_expand "copysignsf3"
5400 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5402 (neg:SF (abs:SF (match_dup 1))))
5403 (set (match_operand:SF 0 "gpc_reg_operand" "")
5404 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5408 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5409 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
5411 operands[3] = gen_reg_rtx (SFmode);
5412 operands[4] = gen_reg_rtx (SFmode);
5413 operands[5] = CONST0_RTX (SFmode);
5416 (define_expand "copysigndf3"
5418 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5420 (neg:DF (abs:DF (match_dup 1))))
5421 (set (match_operand:DF 0 "gpc_reg_operand" "")
5422 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5426 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5427 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
5429 operands[3] = gen_reg_rtx (DFmode);
5430 operands[4] = gen_reg_rtx (DFmode);
5431 operands[5] = CONST0_RTX (DFmode);
5434 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5435 ;; fsel instruction and some auxiliary computations. Then we just have a
5436 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5438 (define_expand "smaxsf3"
5439 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5440 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5441 (match_operand:SF 2 "gpc_reg_operand" ""))
5444 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5445 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5447 (define_expand "sminsf3"
5448 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5449 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5450 (match_operand:SF 2 "gpc_reg_operand" ""))
5453 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5454 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5457 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5458 (match_operator:SF 3 "min_max_operator"
5459 [(match_operand:SF 1 "gpc_reg_operand" "")
5460 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5461 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5464 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5465 operands[1], operands[2]);
5469 (define_expand "movsicc"
5470 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5471 (if_then_else:SI (match_operand 1 "comparison_operator" "")
5472 (match_operand:SI 2 "gpc_reg_operand" "")
5473 (match_operand:SI 3 "gpc_reg_operand" "")))]
5477 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5483 ;; We use the BASE_REGS for the isel input operands because, if rA is
5484 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5485 ;; because we may switch the operands and rB may end up being rA.
5487 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5488 ;; leave out the mode in operand 4 and use one pattern, but reload can
5489 ;; change the mode underneath our feet and then gets confused trying
5490 ;; to reload the value.
5491 (define_insn "isel_signed"
5492 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5494 (match_operator 1 "comparison_operator"
5495 [(match_operand:CC 4 "cc_reg_operand" "y")
5497 (match_operand:SI 2 "gpc_reg_operand" "b")
5498 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5501 { return output_isel (operands); }"
5502 [(set_attr "length" "4")])
5504 (define_insn "isel_unsigned"
5505 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5507 (match_operator 1 "comparison_operator"
5508 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5510 (match_operand:SI 2 "gpc_reg_operand" "b")
5511 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5514 { return output_isel (operands); }"
5515 [(set_attr "length" "4")])
5517 (define_expand "movsfcc"
5518 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5519 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5520 (match_operand:SF 2 "gpc_reg_operand" "")
5521 (match_operand:SF 3 "gpc_reg_operand" "")))]
5522 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5525 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5531 (define_insn "*fselsfsf4"
5532 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5533 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5534 (match_operand:SF 4 "zero_fp_constant" "F"))
5535 (match_operand:SF 2 "gpc_reg_operand" "f")
5536 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5537 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5539 [(set_attr "type" "fp")])
5541 (define_insn "*fseldfsf4"
5542 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5543 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5544 (match_operand:DF 4 "zero_fp_constant" "F"))
5545 (match_operand:SF 2 "gpc_reg_operand" "f")
5546 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5547 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5549 [(set_attr "type" "fp")])
5551 (define_expand "negdf2"
5552 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5553 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5554 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5557 (define_insn "*negdf2_fpr"
5558 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5559 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5560 "TARGET_HARD_FLOAT && TARGET_FPRS"
5562 [(set_attr "type" "fp")])
5564 (define_expand "absdf2"
5565 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5566 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5567 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5570 (define_insn "*absdf2_fpr"
5571 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5572 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5573 "TARGET_HARD_FLOAT && TARGET_FPRS"
5575 [(set_attr "type" "fp")])
5577 (define_insn "*nabsdf2_fpr"
5578 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5579 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
5580 "TARGET_HARD_FLOAT && TARGET_FPRS"
5582 [(set_attr "type" "fp")])
5584 (define_expand "adddf3"
5585 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5586 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5587 (match_operand:DF 2 "gpc_reg_operand" "")))]
5588 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5591 (define_insn "*adddf3_fpr"
5592 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5593 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5594 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5595 "TARGET_HARD_FLOAT && TARGET_FPRS"
5596 "{fa|fadd} %0,%1,%2"
5597 [(set_attr "type" "fp")])
5599 (define_expand "subdf3"
5600 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5601 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5602 (match_operand:DF 2 "gpc_reg_operand" "")))]
5603 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5606 (define_insn "*subdf3_fpr"
5607 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5608 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5609 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5610 "TARGET_HARD_FLOAT && TARGET_FPRS"
5611 "{fs|fsub} %0,%1,%2"
5612 [(set_attr "type" "fp")])
5614 (define_expand "muldf3"
5615 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5616 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5617 (match_operand:DF 2 "gpc_reg_operand" "")))]
5618 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5621 (define_insn "*muldf3_fpr"
5622 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5623 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5624 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5625 "TARGET_HARD_FLOAT && TARGET_FPRS"
5626 "{fm|fmul} %0,%1,%2"
5627 [(set_attr "type" "dmul")])
5629 (define_expand "divdf3"
5630 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5631 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5632 (match_operand:DF 2 "gpc_reg_operand" "")))]
5633 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5636 (define_insn "*divdf3_fpr"
5637 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5638 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5639 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5640 "TARGET_HARD_FLOAT && TARGET_FPRS"
5641 "{fd|fdiv} %0,%1,%2"
5642 [(set_attr "type" "ddiv")])
5644 (define_expand "recipdf3"
5645 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5646 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")
5647 (match_operand:DF 2 "gpc_reg_operand" "f")]
5649 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_POPCNTB && !optimize_size
5650 && flag_finite_math_only && !flag_trapping_math"
5652 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5657 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5658 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5659 "TARGET_POPCNTB && flag_finite_math_only"
5661 [(set_attr "type" "fp")])
5664 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5665 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5666 (match_operand:DF 2 "gpc_reg_operand" "f"))
5667 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5668 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5669 "{fma|fmadd} %0,%1,%2,%3"
5670 [(set_attr "type" "dmul")])
5673 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5674 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5675 (match_operand:DF 2 "gpc_reg_operand" "f"))
5676 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5677 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5678 "{fms|fmsub} %0,%1,%2,%3"
5679 [(set_attr "type" "dmul")])
5682 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5683 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5684 (match_operand:DF 2 "gpc_reg_operand" "f"))
5685 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5686 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5687 && HONOR_SIGNED_ZEROS (DFmode)"
5688 "{fnma|fnmadd} %0,%1,%2,%3"
5689 [(set_attr "type" "dmul")])
5692 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5693 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5694 (match_operand:DF 2 "gpc_reg_operand" "f"))
5695 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5696 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5697 && ! HONOR_SIGNED_ZEROS (DFmode)"
5698 "{fnma|fnmadd} %0,%1,%2,%3"
5699 [(set_attr "type" "dmul")])
5702 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5703 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5704 (match_operand:DF 2 "gpc_reg_operand" "f"))
5705 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5706 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5707 && HONOR_SIGNED_ZEROS (DFmode)"
5708 "{fnms|fnmsub} %0,%1,%2,%3"
5709 [(set_attr "type" "dmul")])
5712 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5713 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5714 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5715 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5716 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5717 && ! HONOR_SIGNED_ZEROS (DFmode)"
5718 "{fnms|fnmsub} %0,%1,%2,%3"
5719 [(set_attr "type" "dmul")])
5721 (define_insn "sqrtdf2"
5722 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5723 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5724 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5726 [(set_attr "type" "dsqrt")])
5728 ;; The conditional move instructions allow us to perform max and min
5729 ;; operations even when
5731 (define_expand "smaxdf3"
5732 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5733 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5734 (match_operand:DF 2 "gpc_reg_operand" ""))
5737 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5738 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5740 (define_expand "smindf3"
5741 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5742 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5743 (match_operand:DF 2 "gpc_reg_operand" ""))
5746 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5747 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5750 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5751 (match_operator:DF 3 "min_max_operator"
5752 [(match_operand:DF 1 "gpc_reg_operand" "")
5753 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5754 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5757 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5758 operands[1], operands[2]);
5762 (define_expand "movdfcc"
5763 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5764 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5765 (match_operand:DF 2 "gpc_reg_operand" "")
5766 (match_operand:DF 3 "gpc_reg_operand" "")))]
5767 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5770 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5776 (define_insn "*fseldfdf4"
5777 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5778 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5779 (match_operand:DF 4 "zero_fp_constant" "F"))
5780 (match_operand:DF 2 "gpc_reg_operand" "f")
5781 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5782 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5784 [(set_attr "type" "fp")])
5786 (define_insn "*fselsfdf4"
5787 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5788 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5789 (match_operand:SF 4 "zero_fp_constant" "F"))
5790 (match_operand:DF 2 "gpc_reg_operand" "f")
5791 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5794 [(set_attr "type" "fp")])
5796 ;; Conversions to and from floating-point.
5798 (define_expand "fixuns_truncsfsi2"
5799 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5800 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5801 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5804 (define_expand "fix_truncsfsi2"
5805 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5806 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5807 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5810 ; For each of these conversions, there is a define_expand, a define_insn
5811 ; with a '#' template, and a define_split (with C code). The idea is
5812 ; to allow constant folding with the template of the define_insn,
5813 ; then to have the insns split later (between sched1 and final).
5815 (define_expand "floatsidf2"
5816 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5817 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5820 (clobber (match_dup 4))
5821 (clobber (match_dup 5))
5822 (clobber (match_dup 6))])]
5823 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5826 if (TARGET_E500_DOUBLE)
5828 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5831 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS)
5833 rtx t1 = gen_reg_rtx (DImode);
5834 emit_insn (gen_floatsidf_ppc64_mfpgpr (operands[0], operands[1], t1));
5837 if (TARGET_POWERPC64)
5839 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5840 rtx t1 = gen_reg_rtx (DImode);
5841 rtx t2 = gen_reg_rtx (DImode);
5842 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5846 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5847 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5848 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5849 operands[5] = gen_reg_rtx (DFmode);
5850 operands[6] = gen_reg_rtx (SImode);
5853 (define_insn_and_split "*floatsidf2_internal"
5854 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5855 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5856 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5857 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5858 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5859 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5860 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5861 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5863 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
5867 rtx lowword, highword;
5868 gcc_assert (MEM_P (operands[4]));
5869 highword = adjust_address (operands[4], SImode, 0);
5870 lowword = adjust_address (operands[4], SImode, 4);
5871 if (! WORDS_BIG_ENDIAN)
5874 tmp = highword; highword = lowword; lowword = tmp;
5877 emit_insn (gen_xorsi3 (operands[6], operands[1],
5878 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5879 emit_move_insn (lowword, operands[6]);
5880 emit_move_insn (highword, operands[2]);
5881 emit_move_insn (operands[5], operands[4]);
5882 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5885 [(set_attr "length" "24")])
5887 (define_expand "floatunssisf2"
5888 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5889 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5890 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5893 (define_expand "floatunssidf2"
5894 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5895 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5898 (clobber (match_dup 4))
5899 (clobber (match_dup 5))])]
5900 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5903 if (TARGET_E500_DOUBLE)
5905 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5908 if (TARGET_POWERPC64)
5910 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5911 rtx t1 = gen_reg_rtx (DImode);
5912 rtx t2 = gen_reg_rtx (DImode);
5913 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5918 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5919 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5920 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5921 operands[5] = gen_reg_rtx (DFmode);
5924 (define_insn_and_split "*floatunssidf2_internal"
5925 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5926 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5927 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5928 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5929 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5930 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5931 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5933 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
5937 rtx lowword, highword;
5938 gcc_assert (MEM_P (operands[4]));
5939 highword = adjust_address (operands[4], SImode, 0);
5940 lowword = adjust_address (operands[4], SImode, 4);
5941 if (! WORDS_BIG_ENDIAN)
5944 tmp = highword; highword = lowword; lowword = tmp;
5947 emit_move_insn (lowword, operands[1]);
5948 emit_move_insn (highword, operands[2]);
5949 emit_move_insn (operands[5], operands[4]);
5950 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5953 [(set_attr "length" "20")])
5955 (define_expand "fix_truncdfsi2"
5956 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
5957 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5958 (clobber (match_dup 2))
5959 (clobber (match_dup 3))])]
5960 "(TARGET_POWER2 || TARGET_POWERPC)
5961 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5964 if (TARGET_E500_DOUBLE)
5966 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5969 operands[2] = gen_reg_rtx (DImode);
5970 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
5971 && gpc_reg_operand(operands[0], GET_MODE (operands[0])))
5973 operands[3] = gen_reg_rtx (DImode);
5974 emit_insn (gen_fix_truncdfsi2_mfpgpr (operands[0], operands[1],
5975 operands[2], operands[3]));
5978 if (TARGET_PPC_GFXOPT)
5980 rtx orig_dest = operands[0];
5981 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
5982 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5983 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5985 if (operands[0] != orig_dest)
5986 emit_move_insn (orig_dest, operands[0]);
5989 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5992 (define_insn_and_split "*fix_truncdfsi2_internal"
5993 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5994 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5995 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5996 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))]
5997 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5999 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[3]))"
6004 gcc_assert (MEM_P (operands[3]));
6005 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
6007 emit_insn (gen_fctiwz (operands[2], operands[1]));
6008 emit_move_insn (operands[3], operands[2]);
6009 emit_move_insn (operands[0], lowword);
6012 [(set_attr "length" "16")])
6014 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
6015 [(set (match_operand:SI 0 "memory_operand" "=Z")
6016 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
6017 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
6018 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6019 && TARGET_PPC_GFXOPT"
6025 emit_insn (gen_fctiwz (operands[2], operands[1]));
6026 emit_insn (gen_stfiwx (operands[0], operands[2]));
6029 [(set_attr "length" "16")])
6031 (define_insn_and_split "fix_truncdfsi2_mfpgpr"
6032 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6033 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
6034 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
6035 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
6036 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
6039 [(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
6040 (set (match_dup 3) (match_dup 2))
6041 (set (match_dup 0) (subreg:SI (match_dup 3) 4))]
6043 [(set_attr "length" "12")])
6045 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6046 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6047 ; because the first makes it clear that operand 0 is not live
6048 ; before the instruction.
6049 (define_insn "fctiwz"
6050 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
6051 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
6053 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
6054 "{fcirz|fctiwz} %0,%1"
6055 [(set_attr "type" "fp")])
6057 (define_insn "btruncdf2"
6058 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6059 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6060 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6062 [(set_attr "type" "fp")])
6064 (define_insn "btruncsf2"
6065 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6066 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6067 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6069 [(set_attr "type" "fp")])
6071 (define_insn "ceildf2"
6072 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6073 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6074 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6076 [(set_attr "type" "fp")])
6078 (define_insn "ceilsf2"
6079 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6080 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6081 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6083 [(set_attr "type" "fp")])
6085 (define_insn "floordf2"
6086 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6087 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6088 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6090 [(set_attr "type" "fp")])
6092 (define_insn "floorsf2"
6093 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6094 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6095 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6097 [(set_attr "type" "fp")])
6099 (define_insn "rounddf2"
6100 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6101 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6102 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6104 [(set_attr "type" "fp")])
6106 (define_insn "roundsf2"
6107 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6108 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6109 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6111 [(set_attr "type" "fp")])
6113 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6114 (define_insn "stfiwx"
6115 [(set (match_operand:SI 0 "memory_operand" "=Z")
6116 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
6120 [(set_attr "type" "fpstore")])
6122 (define_expand "floatsisf2"
6123 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6124 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6125 "TARGET_HARD_FLOAT && !TARGET_FPRS"
6128 (define_insn "floatdidf2"
6129 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6130 (float:DF (match_operand:DI 1 "gpc_reg_operand" "!f#r")))]
6131 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6133 [(set_attr "type" "fp")])
6135 (define_insn_and_split "floatsidf_ppc64_mfpgpr"
6136 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6137 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6138 (clobber (match_operand:DI 2 "gpc_reg_operand" "=r"))]
6139 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
6142 [(set (match_dup 2) (sign_extend:DI (match_dup 1)))
6143 (set (match_dup 0) (float:DF (match_dup 2)))]
6146 (define_insn_and_split "floatsidf_ppc64"
6147 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6148 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6149 (clobber (match_operand:DI 2 "offsettable_mem_operand" "=o"))
6150 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
6151 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
6152 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
6155 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
6156 (set (match_dup 2) (match_dup 3))
6157 (set (match_dup 4) (match_dup 2))
6158 (set (match_dup 0) (float:DF (match_dup 4)))]
6161 (define_insn_and_split "floatunssidf_ppc64"
6162 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6163 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6164 (clobber (match_operand:DI 2 "offsettable_mem_operand" "=o"))
6165 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
6166 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
6167 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6170 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
6171 (set (match_dup 2) (match_dup 3))
6172 (set (match_dup 4) (match_dup 2))
6173 (set (match_dup 0) (float:DF (match_dup 4)))]
6176 (define_insn "fix_truncdfdi2"
6177 [(set (match_operand:DI 0 "gpc_reg_operand" "=!f#r")
6178 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
6179 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6181 [(set_attr "type" "fp")])
6183 (define_expand "floatdisf2"
6184 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6185 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6186 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6189 rtx val = operands[1];
6190 if (!flag_unsafe_math_optimizations)
6192 rtx label = gen_label_rtx ();
6193 val = gen_reg_rtx (DImode);
6194 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6197 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6201 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6202 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6203 ;; from double rounding.
6204 (define_insn_and_split "floatdisf2_internal1"
6205 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6206 (float:SF (match_operand:DI 1 "gpc_reg_operand" "!f#r")))
6207 (clobber (match_scratch:DF 2 "=f"))]
6208 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6210 "&& reload_completed"
6212 (float:DF (match_dup 1)))
6214 (float_truncate:SF (match_dup 2)))]
6217 ;; Twiddles bits to avoid double rounding.
6218 ;; Bits that might be truncated when converting to DFmode are replaced
6219 ;; by a bit that won't be lost at that stage, but is below the SFmode
6220 ;; rounding position.
6221 (define_expand "floatdisf2_internal2"
6222 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6224 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6226 (clobber (scratch:CC))])
6227 (set (match_dup 3) (plus:DI (match_dup 3)
6229 (set (match_dup 0) (plus:DI (match_dup 0)
6231 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6233 (set (match_dup 0) (ior:DI (match_dup 0)
6235 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6237 (clobber (scratch:CC))])
6238 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6239 (label_ref (match_operand:DI 2 "" ""))
6241 (set (match_dup 0) (match_dup 1))]
6242 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6245 operands[3] = gen_reg_rtx (DImode);
6246 operands[4] = gen_reg_rtx (CCUNSmode);
6249 ;; Define the DImode operations that can be done in a small number
6250 ;; of instructions. The & constraints are to prevent the register
6251 ;; allocator from allocating registers that overlap with the inputs
6252 ;; (for example, having an input in 7,8 and an output in 6,7). We
6253 ;; also allow for the output being the same as one of the inputs.
6255 (define_insn "*adddi3_noppc64"
6256 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6257 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6258 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6259 "! TARGET_POWERPC64"
6262 if (WORDS_BIG_ENDIAN)
6263 return (GET_CODE (operands[2])) != CONST_INT
6264 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6265 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6267 return (GET_CODE (operands[2])) != CONST_INT
6268 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6269 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6271 [(set_attr "type" "two")
6272 (set_attr "length" "8")])
6274 (define_insn "*subdi3_noppc64"
6275 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6276 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6277 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6278 "! TARGET_POWERPC64"
6281 if (WORDS_BIG_ENDIAN)
6282 return (GET_CODE (operands[1]) != CONST_INT)
6283 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6284 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6286 return (GET_CODE (operands[1]) != CONST_INT)
6287 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6288 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
6290 [(set_attr "type" "two")
6291 (set_attr "length" "8")])
6293 (define_insn "*negdi2_noppc64"
6294 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6295 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6296 "! TARGET_POWERPC64"
6299 return (WORDS_BIG_ENDIAN)
6300 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6301 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6303 [(set_attr "type" "two")
6304 (set_attr "length" "8")])
6306 (define_expand "mulsidi3"
6307 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6308 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6309 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6310 "! TARGET_POWERPC64"
6313 if (! TARGET_POWER && ! TARGET_POWERPC)
6315 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6316 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6317 emit_insn (gen_mull_call ());
6318 if (WORDS_BIG_ENDIAN)
6319 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
6322 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
6323 gen_rtx_REG (SImode, 3));
6324 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
6325 gen_rtx_REG (SImode, 4));
6329 else if (TARGET_POWER)
6331 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6336 (define_insn "mulsidi3_mq"
6337 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6338 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6339 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6340 (clobber (match_scratch:SI 3 "=q"))]
6342 "mul %0,%1,%2\;mfmq %L0"
6343 [(set_attr "type" "imul")
6344 (set_attr "length" "8")])
6346 (define_insn "*mulsidi3_no_mq"
6347 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6348 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6349 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6350 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6353 return (WORDS_BIG_ENDIAN)
6354 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6355 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6357 [(set_attr "type" "imul")
6358 (set_attr "length" "8")])
6361 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6362 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6363 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6364 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6367 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6368 (sign_extend:DI (match_dup 2)))
6371 (mult:SI (match_dup 1)
6375 int endian = (WORDS_BIG_ENDIAN == 0);
6376 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6377 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6380 (define_expand "umulsidi3"
6381 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6382 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6383 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6384 "TARGET_POWERPC && ! TARGET_POWERPC64"
6389 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6394 (define_insn "umulsidi3_mq"
6395 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6396 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6397 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6398 (clobber (match_scratch:SI 3 "=q"))]
6399 "TARGET_POWERPC && TARGET_POWER"
6402 return (WORDS_BIG_ENDIAN)
6403 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6404 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6406 [(set_attr "type" "imul")
6407 (set_attr "length" "8")])
6409 (define_insn "*umulsidi3_no_mq"
6410 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6411 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6412 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6413 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6416 return (WORDS_BIG_ENDIAN)
6417 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6418 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6420 [(set_attr "type" "imul")
6421 (set_attr "length" "8")])
6424 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6425 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6426 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6427 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6430 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6431 (zero_extend:DI (match_dup 2)))
6434 (mult:SI (match_dup 1)
6438 int endian = (WORDS_BIG_ENDIAN == 0);
6439 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6440 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6443 (define_expand "smulsi3_highpart"
6444 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6446 (lshiftrt:DI (mult:DI (sign_extend:DI
6447 (match_operand:SI 1 "gpc_reg_operand" ""))
6449 (match_operand:SI 2 "gpc_reg_operand" "")))
6454 if (! TARGET_POWER && ! TARGET_POWERPC)
6456 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6457 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6458 emit_insn (gen_mulh_call ());
6459 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
6462 else if (TARGET_POWER)
6464 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6469 (define_insn "smulsi3_highpart_mq"
6470 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6472 (lshiftrt:DI (mult:DI (sign_extend:DI
6473 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6475 (match_operand:SI 2 "gpc_reg_operand" "r")))
6477 (clobber (match_scratch:SI 3 "=q"))]
6480 [(set_attr "type" "imul")])
6482 (define_insn "*smulsi3_highpart_no_mq"
6483 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6485 (lshiftrt:DI (mult:DI (sign_extend:DI
6486 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6488 (match_operand:SI 2 "gpc_reg_operand" "r")))
6490 "TARGET_POWERPC && ! TARGET_POWER"
6492 [(set_attr "type" "imul")])
6494 (define_expand "umulsi3_highpart"
6495 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6497 (lshiftrt:DI (mult:DI (zero_extend:DI
6498 (match_operand:SI 1 "gpc_reg_operand" ""))
6500 (match_operand:SI 2 "gpc_reg_operand" "")))
6507 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6512 (define_insn "umulsi3_highpart_mq"
6513 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6515 (lshiftrt:DI (mult:DI (zero_extend:DI
6516 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6518 (match_operand:SI 2 "gpc_reg_operand" "r")))
6520 (clobber (match_scratch:SI 3 "=q"))]
6521 "TARGET_POWERPC && TARGET_POWER"
6523 [(set_attr "type" "imul")])
6525 (define_insn "*umulsi3_highpart_no_mq"
6526 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6528 (lshiftrt:DI (mult:DI (zero_extend:DI
6529 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6531 (match_operand:SI 2 "gpc_reg_operand" "r")))
6533 "TARGET_POWERPC && ! TARGET_POWER"
6535 [(set_attr "type" "imul")])
6537 ;; If operands 0 and 2 are in the same register, we have a problem. But
6538 ;; operands 0 and 1 (the usual case) can be in the same register. That's
6539 ;; why we have the strange constraints below.
6540 (define_insn "ashldi3_power"
6541 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6542 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6543 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6544 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6547 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
6548 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6549 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6550 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
6551 [(set_attr "length" "8")])
6553 (define_insn "lshrdi3_power"
6554 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6555 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6556 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6557 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6560 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
6561 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6562 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6563 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
6564 [(set_attr "length" "8")])
6566 ;; Shift by a variable amount is too complex to be worth open-coding. We
6567 ;; just handle shifts by constants.
6568 (define_insn "ashrdi3_power"
6569 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6570 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6571 (match_operand:SI 2 "const_int_operand" "M,i")))
6572 (clobber (match_scratch:SI 3 "=X,q"))]
6575 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6576 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
6577 [(set_attr "type" "shift")
6578 (set_attr "length" "8")])
6580 (define_insn "ashrdi3_no_power"
6581 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6582 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6583 (match_operand:SI 2 "const_int_operand" "M,i")))]
6584 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
6586 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6587 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
6588 [(set_attr "type" "two,three")
6589 (set_attr "length" "8,12")])
6591 (define_insn "*ashrdisi3_noppc64"
6592 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6593 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6594 (const_int 32)) 4))]
6595 "TARGET_32BIT && !TARGET_POWERPC64"
6598 if (REGNO (operands[0]) == REGNO (operands[1]))
6601 return \"mr %0,%1\";
6603 [(set_attr "length" "4")])
6606 ;; PowerPC64 DImode operations.
6608 (define_insn_and_split "absdi2"
6609 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6610 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6611 (clobber (match_scratch:DI 2 "=&r,&r"))]
6614 "&& reload_completed"
6615 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6616 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6617 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6620 (define_insn_and_split "*nabsdi2"
6621 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6622 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6623 (clobber (match_scratch:DI 2 "=&r,&r"))]
6626 "&& reload_completed"
6627 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6628 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6629 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
6632 (define_insn "muldi3"
6633 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6634 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6635 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6641 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6642 (const_string "imul3")
6643 (match_operand:SI 2 "short_cint_operand" "")
6644 (const_string "imul2")]
6645 (const_string "lmul")))])
6647 (define_insn "*muldi3_internal1"
6648 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6649 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6650 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6652 (clobber (match_scratch:DI 3 "=r,r"))]
6657 [(set_attr "type" "lmul_compare")
6658 (set_attr "length" "4,8")])
6661 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6662 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6663 (match_operand:DI 2 "gpc_reg_operand" ""))
6665 (clobber (match_scratch:DI 3 ""))]
6666 "TARGET_POWERPC64 && reload_completed"
6668 (mult:DI (match_dup 1) (match_dup 2)))
6670 (compare:CC (match_dup 3)
6674 (define_insn "*muldi3_internal2"
6675 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6676 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6677 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6679 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6680 (mult:DI (match_dup 1) (match_dup 2)))]
6685 [(set_attr "type" "lmul_compare")
6686 (set_attr "length" "4,8")])
6689 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6690 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6691 (match_operand:DI 2 "gpc_reg_operand" ""))
6693 (set (match_operand:DI 0 "gpc_reg_operand" "")
6694 (mult:DI (match_dup 1) (match_dup 2)))]
6695 "TARGET_POWERPC64 && reload_completed"
6697 (mult:DI (match_dup 1) (match_dup 2)))
6699 (compare:CC (match_dup 0)
6703 (define_insn "smuldi3_highpart"
6704 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6706 (lshiftrt:TI (mult:TI (sign_extend:TI
6707 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6709 (match_operand:DI 2 "gpc_reg_operand" "r")))
6713 [(set_attr "type" "lmul")])
6715 (define_insn "umuldi3_highpart"
6716 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6718 (lshiftrt:TI (mult:TI (zero_extend:TI
6719 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6721 (match_operand:DI 2 "gpc_reg_operand" "r")))
6725 [(set_attr "type" "lmul")])
6727 (define_insn "rotldi3"
6728 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6729 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6730 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
6735 [(set_attr "type" "var_shift_rotate,integer")])
6737 (define_insn "*rotldi3_internal2"
6738 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6739 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6740 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6742 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6749 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6750 (set_attr "length" "4,4,8,8")])
6753 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6754 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6755 (match_operand:DI 2 "reg_or_cint_operand" ""))
6757 (clobber (match_scratch:DI 3 ""))]
6758 "TARGET_POWERPC64 && reload_completed"
6760 (rotate:DI (match_dup 1) (match_dup 2)))
6762 (compare:CC (match_dup 3)
6766 (define_insn "*rotldi3_internal3"
6767 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6768 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6769 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6771 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6772 (rotate:DI (match_dup 1) (match_dup 2)))]
6779 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6780 (set_attr "length" "4,4,8,8")])
6783 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6784 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6785 (match_operand:DI 2 "reg_or_cint_operand" ""))
6787 (set (match_operand:DI 0 "gpc_reg_operand" "")
6788 (rotate:DI (match_dup 1) (match_dup 2)))]
6789 "TARGET_POWERPC64 && reload_completed"
6791 (rotate:DI (match_dup 1) (match_dup 2)))
6793 (compare:CC (match_dup 0)
6797 (define_insn "*rotldi3_internal4"
6798 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6799 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6800 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6801 (match_operand:DI 3 "mask64_operand" "n,n")))]
6804 rldc%B3 %0,%1,%2,%S3
6805 rldic%B3 %0,%1,%H2,%S3"
6806 [(set_attr "type" "var_shift_rotate,integer")])
6808 (define_insn "*rotldi3_internal5"
6809 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6811 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6812 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6813 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6815 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
6818 rldc%B3. %4,%1,%2,%S3
6819 rldic%B3. %4,%1,%H2,%S3
6822 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6823 (set_attr "length" "4,4,8,8")])
6826 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6828 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6829 (match_operand:DI 2 "reg_or_cint_operand" ""))
6830 (match_operand:DI 3 "mask64_operand" ""))
6832 (clobber (match_scratch:DI 4 ""))]
6833 "TARGET_POWERPC64 && reload_completed"
6835 (and:DI (rotate:DI (match_dup 1)
6839 (compare:CC (match_dup 4)
6843 (define_insn "*rotldi3_internal6"
6844 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
6846 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6847 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6848 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6850 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6851 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6854 rldc%B3. %0,%1,%2,%S3
6855 rldic%B3. %0,%1,%H2,%S3
6858 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6859 (set_attr "length" "4,4,8,8")])
6862 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6864 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6865 (match_operand:DI 2 "reg_or_cint_operand" ""))
6866 (match_operand:DI 3 "mask64_operand" ""))
6868 (set (match_operand:DI 0 "gpc_reg_operand" "")
6869 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6870 "TARGET_POWERPC64 && reload_completed"
6872 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6874 (compare:CC (match_dup 0)
6878 (define_insn "*rotldi3_internal7"
6879 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6882 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6883 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6887 rldicl %0,%1,%H2,56"
6888 [(set_attr "type" "var_shift_rotate,integer")])
6890 (define_insn "*rotldi3_internal8"
6891 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6892 (compare:CC (zero_extend:DI
6894 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6895 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6897 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6901 rldicl. %3,%1,%H2,56
6904 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6905 (set_attr "length" "4,4,8,8")])
6908 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6909 (compare:CC (zero_extend:DI
6911 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6912 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6914 (clobber (match_scratch:DI 3 ""))]
6915 "TARGET_POWERPC64 && reload_completed"
6917 (zero_extend:DI (subreg:QI
6918 (rotate:DI (match_dup 1)
6921 (compare:CC (match_dup 3)
6925 (define_insn "*rotldi3_internal9"
6926 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6927 (compare:CC (zero_extend:DI
6929 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6930 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6932 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6933 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6937 rldicl. %0,%1,%H2,56
6940 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6941 (set_attr "length" "4,4,8,8")])
6944 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6945 (compare:CC (zero_extend:DI
6947 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6948 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6950 (set (match_operand:DI 0 "gpc_reg_operand" "")
6951 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6952 "TARGET_POWERPC64 && reload_completed"
6954 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6956 (compare:CC (match_dup 0)
6960 (define_insn "*rotldi3_internal10"
6961 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6964 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6965 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6969 rldicl %0,%1,%H2,48"
6970 [(set_attr "type" "var_shift_rotate,integer")])
6972 (define_insn "*rotldi3_internal11"
6973 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6974 (compare:CC (zero_extend:DI
6976 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6977 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6979 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6983 rldicl. %3,%1,%H2,48
6986 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6987 (set_attr "length" "4,4,8,8")])
6990 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6991 (compare:CC (zero_extend:DI
6993 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6994 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6996 (clobber (match_scratch:DI 3 ""))]
6997 "TARGET_POWERPC64 && reload_completed"
6999 (zero_extend:DI (subreg:HI
7000 (rotate:DI (match_dup 1)
7003 (compare:CC (match_dup 3)
7007 (define_insn "*rotldi3_internal12"
7008 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7009 (compare:CC (zero_extend:DI
7011 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7012 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7014 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7015 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7019 rldicl. %0,%1,%H2,48
7022 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7023 (set_attr "length" "4,4,8,8")])
7026 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7027 (compare:CC (zero_extend:DI
7029 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7030 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7032 (set (match_operand:DI 0 "gpc_reg_operand" "")
7033 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7034 "TARGET_POWERPC64 && reload_completed"
7036 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7038 (compare:CC (match_dup 0)
7042 (define_insn "*rotldi3_internal13"
7043 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7046 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7047 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7051 rldicl %0,%1,%H2,32"
7052 [(set_attr "type" "var_shift_rotate,integer")])
7054 (define_insn "*rotldi3_internal14"
7055 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7056 (compare:CC (zero_extend:DI
7058 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7059 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7061 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7065 rldicl. %3,%1,%H2,32
7068 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7069 (set_attr "length" "4,4,8,8")])
7072 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7073 (compare:CC (zero_extend:DI
7075 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7076 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7078 (clobber (match_scratch:DI 3 ""))]
7079 "TARGET_POWERPC64 && reload_completed"
7081 (zero_extend:DI (subreg:SI
7082 (rotate:DI (match_dup 1)
7085 (compare:CC (match_dup 3)
7089 (define_insn "*rotldi3_internal15"
7090 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7091 (compare:CC (zero_extend:DI
7093 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7094 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7096 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7097 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7101 rldicl. %0,%1,%H2,32
7104 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7105 (set_attr "length" "4,4,8,8")])
7108 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7109 (compare:CC (zero_extend:DI
7111 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7112 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7114 (set (match_operand:DI 0 "gpc_reg_operand" "")
7115 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7116 "TARGET_POWERPC64 && reload_completed"
7118 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7120 (compare:CC (match_dup 0)
7124 (define_expand "ashldi3"
7125 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7126 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7127 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7128 "TARGET_POWERPC64 || TARGET_POWER"
7131 if (TARGET_POWERPC64)
7133 else if (TARGET_POWER)
7135 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
7142 (define_insn "*ashldi3_internal1"
7143 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7144 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7145 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7150 [(set_attr "type" "var_shift_rotate,shift")])
7152 (define_insn "*ashldi3_internal2"
7153 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7154 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7155 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7157 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7164 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7165 (set_attr "length" "4,4,8,8")])
7168 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7169 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7170 (match_operand:SI 2 "reg_or_cint_operand" ""))
7172 (clobber (match_scratch:DI 3 ""))]
7173 "TARGET_POWERPC64 && reload_completed"
7175 (ashift:DI (match_dup 1) (match_dup 2)))
7177 (compare:CC (match_dup 3)
7181 (define_insn "*ashldi3_internal3"
7182 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7183 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7184 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7186 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7187 (ashift:DI (match_dup 1) (match_dup 2)))]
7194 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7195 (set_attr "length" "4,4,8,8")])
7198 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7199 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7200 (match_operand:SI 2 "reg_or_cint_operand" ""))
7202 (set (match_operand:DI 0 "gpc_reg_operand" "")
7203 (ashift:DI (match_dup 1) (match_dup 2)))]
7204 "TARGET_POWERPC64 && reload_completed"
7206 (ashift:DI (match_dup 1) (match_dup 2)))
7208 (compare:CC (match_dup 0)
7212 (define_insn "*ashldi3_internal4"
7213 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7214 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7215 (match_operand:SI 2 "const_int_operand" "i"))
7216 (match_operand:DI 3 "const_int_operand" "n")))]
7217 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7218 "rldic %0,%1,%H2,%W3")
7220 (define_insn "ashldi3_internal5"
7221 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7223 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7224 (match_operand:SI 2 "const_int_operand" "i,i"))
7225 (match_operand:DI 3 "const_int_operand" "n,n"))
7227 (clobber (match_scratch:DI 4 "=r,r"))]
7228 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7230 rldic. %4,%1,%H2,%W3
7232 [(set_attr "type" "compare")
7233 (set_attr "length" "4,8")])
7236 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7238 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7239 (match_operand:SI 2 "const_int_operand" ""))
7240 (match_operand:DI 3 "const_int_operand" ""))
7242 (clobber (match_scratch:DI 4 ""))]
7243 "TARGET_POWERPC64 && reload_completed
7244 && includes_rldic_lshift_p (operands[2], operands[3])"
7246 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7249 (compare:CC (match_dup 4)
7253 (define_insn "*ashldi3_internal6"
7254 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7256 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7257 (match_operand:SI 2 "const_int_operand" "i,i"))
7258 (match_operand:DI 3 "const_int_operand" "n,n"))
7260 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7261 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7262 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7264 rldic. %0,%1,%H2,%W3
7266 [(set_attr "type" "compare")
7267 (set_attr "length" "4,8")])
7270 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7272 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7273 (match_operand:SI 2 "const_int_operand" ""))
7274 (match_operand:DI 3 "const_int_operand" ""))
7276 (set (match_operand:DI 0 "gpc_reg_operand" "")
7277 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7278 "TARGET_POWERPC64 && reload_completed
7279 && includes_rldic_lshift_p (operands[2], operands[3])"
7281 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7284 (compare:CC (match_dup 0)
7288 (define_insn "*ashldi3_internal7"
7289 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7290 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7291 (match_operand:SI 2 "const_int_operand" "i"))
7292 (match_operand:DI 3 "mask64_operand" "n")))]
7293 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7294 "rldicr %0,%1,%H2,%S3")
7296 (define_insn "ashldi3_internal8"
7297 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7299 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7300 (match_operand:SI 2 "const_int_operand" "i,i"))
7301 (match_operand:DI 3 "mask64_operand" "n,n"))
7303 (clobber (match_scratch:DI 4 "=r,r"))]
7304 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7306 rldicr. %4,%1,%H2,%S3
7308 [(set_attr "type" "compare")
7309 (set_attr "length" "4,8")])
7312 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7314 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7315 (match_operand:SI 2 "const_int_operand" ""))
7316 (match_operand:DI 3 "mask64_operand" ""))
7318 (clobber (match_scratch:DI 4 ""))]
7319 "TARGET_POWERPC64 && reload_completed
7320 && includes_rldicr_lshift_p (operands[2], operands[3])"
7322 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7325 (compare:CC (match_dup 4)
7329 (define_insn "*ashldi3_internal9"
7330 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7332 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7333 (match_operand:SI 2 "const_int_operand" "i,i"))
7334 (match_operand:DI 3 "mask64_operand" "n,n"))
7336 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7337 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7338 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7340 rldicr. %0,%1,%H2,%S3
7342 [(set_attr "type" "compare")
7343 (set_attr "length" "4,8")])
7346 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7348 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7349 (match_operand:SI 2 "const_int_operand" ""))
7350 (match_operand:DI 3 "mask64_operand" ""))
7352 (set (match_operand:DI 0 "gpc_reg_operand" "")
7353 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7354 "TARGET_POWERPC64 && reload_completed
7355 && includes_rldicr_lshift_p (operands[2], operands[3])"
7357 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7360 (compare:CC (match_dup 0)
7364 (define_expand "lshrdi3"
7365 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7366 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7367 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7368 "TARGET_POWERPC64 || TARGET_POWER"
7371 if (TARGET_POWERPC64)
7373 else if (TARGET_POWER)
7375 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7382 (define_insn "*lshrdi3_internal1"
7383 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7384 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7385 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7390 [(set_attr "type" "var_shift_rotate,shift")])
7392 (define_insn "*lshrdi3_internal2"
7393 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7394 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7395 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7397 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7404 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7405 (set_attr "length" "4,4,8,8")])
7408 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7409 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7410 (match_operand:SI 2 "reg_or_cint_operand" ""))
7412 (clobber (match_scratch:DI 3 ""))]
7413 "TARGET_POWERPC64 && reload_completed"
7415 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7417 (compare:CC (match_dup 3)
7421 (define_insn "*lshrdi3_internal3"
7422 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7423 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7424 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7426 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7427 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7434 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7435 (set_attr "length" "4,4,8,8")])
7438 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7439 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7440 (match_operand:SI 2 "reg_or_cint_operand" ""))
7442 (set (match_operand:DI 0 "gpc_reg_operand" "")
7443 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7444 "TARGET_POWERPC64 && reload_completed"
7446 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7448 (compare:CC (match_dup 0)
7452 (define_expand "ashrdi3"
7453 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7454 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7455 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7459 if (TARGET_POWERPC64)
7461 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7463 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7466 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7467 && WORDS_BIG_ENDIAN)
7469 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7476 (define_insn "*ashrdi3_internal1"
7477 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7478 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7479 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7484 [(set_attr "type" "var_shift_rotate,shift")])
7486 (define_insn "*ashrdi3_internal2"
7487 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7488 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7489 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7491 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7498 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7499 (set_attr "length" "4,4,8,8")])
7502 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7503 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7504 (match_operand:SI 2 "reg_or_cint_operand" ""))
7506 (clobber (match_scratch:DI 3 ""))]
7507 "TARGET_POWERPC64 && reload_completed"
7509 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7511 (compare:CC (match_dup 3)
7515 (define_insn "*ashrdi3_internal3"
7516 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7517 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7518 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7520 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7521 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7528 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7529 (set_attr "length" "4,4,8,8")])
7532 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7533 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7534 (match_operand:SI 2 "reg_or_cint_operand" ""))
7536 (set (match_operand:DI 0 "gpc_reg_operand" "")
7537 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7538 "TARGET_POWERPC64 && reload_completed"
7540 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7542 (compare:CC (match_dup 0)
7546 (define_insn "anddi3"
7547 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7548 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7549 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7550 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7554 rldic%B2 %0,%1,0,%S2
7555 rlwinm %0,%1,0,%m2,%M2
7559 [(set_attr "type" "*,*,*,compare,compare,*")
7560 (set_attr "length" "4,4,4,4,4,8")])
7563 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7564 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7565 (match_operand:DI 2 "mask64_2_operand" "")))
7566 (clobber (match_scratch:CC 3 ""))]
7568 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7569 && !mask_operand (operands[2], DImode)
7570 && !mask64_operand (operands[2], DImode)"
7572 (and:DI (rotate:DI (match_dup 1)
7576 (and:DI (rotate:DI (match_dup 0)
7580 build_mask64_2_operands (operands[2], &operands[4]);
7583 (define_insn "*anddi3_internal2"
7584 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7585 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7586 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7588 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7589 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7593 rldic%B2. %3,%1,0,%S2
7594 rlwinm. %3,%1,0,%m2,%M2
7604 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7605 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7608 [(set (match_operand:CC 0 "cc_reg_operand" "")
7609 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7610 (match_operand:DI 2 "mask64_2_operand" ""))
7612 (clobber (match_scratch:DI 3 ""))
7613 (clobber (match_scratch:CC 4 ""))]
7614 "TARGET_64BIT && reload_completed
7615 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7616 && !mask_operand (operands[2], DImode)
7617 && !mask64_operand (operands[2], DImode)"
7619 (and:DI (rotate:DI (match_dup 1)
7622 (parallel [(set (match_dup 0)
7623 (compare:CC (and:DI (rotate:DI (match_dup 3)
7627 (clobber (match_dup 3))])]
7630 build_mask64_2_operands (operands[2], &operands[5]);
7633 (define_insn "*anddi3_internal3"
7634 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7635 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7636 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7638 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
7639 (and:DI (match_dup 1) (match_dup 2)))
7640 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7644 rldic%B2. %0,%1,0,%S2
7645 rlwinm. %0,%1,0,%m2,%M2
7655 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7656 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7659 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7660 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7661 (match_operand:DI 2 "and64_2_operand" ""))
7663 (set (match_operand:DI 0 "gpc_reg_operand" "")
7664 (and:DI (match_dup 1) (match_dup 2)))
7665 (clobber (match_scratch:CC 4 ""))]
7666 "TARGET_64BIT && reload_completed"
7667 [(parallel [(set (match_dup 0)
7668 (and:DI (match_dup 1) (match_dup 2)))
7669 (clobber (match_dup 4))])
7671 (compare:CC (match_dup 0)
7676 [(set (match_operand:CC 3 "cc_reg_operand" "")
7677 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7678 (match_operand:DI 2 "mask64_2_operand" ""))
7680 (set (match_operand:DI 0 "gpc_reg_operand" "")
7681 (and:DI (match_dup 1) (match_dup 2)))
7682 (clobber (match_scratch:CC 4 ""))]
7683 "TARGET_64BIT && reload_completed
7684 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7685 && !mask_operand (operands[2], DImode)
7686 && !mask64_operand (operands[2], DImode)"
7688 (and:DI (rotate:DI (match_dup 1)
7691 (parallel [(set (match_dup 3)
7692 (compare:CC (and:DI (rotate:DI (match_dup 0)
7697 (and:DI (rotate:DI (match_dup 0)
7702 build_mask64_2_operands (operands[2], &operands[5]);
7705 (define_expand "iordi3"
7706 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7707 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7708 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7712 if (non_logical_cint_operand (operands[2], DImode))
7714 HOST_WIDE_INT value;
7715 rtx tmp = ((!can_create_pseudo_p ()
7716 || rtx_equal_p (operands[0], operands[1]))
7717 ? operands[0] : gen_reg_rtx (DImode));
7719 if (GET_CODE (operands[2]) == CONST_INT)
7721 value = INTVAL (operands[2]);
7722 emit_insn (gen_iordi3 (tmp, operands[1],
7723 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7727 value = CONST_DOUBLE_LOW (operands[2]);
7728 emit_insn (gen_iordi3 (tmp, operands[1],
7729 immed_double_const (value
7730 & (~ (HOST_WIDE_INT) 0xffff),
7734 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7739 (define_expand "xordi3"
7740 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7741 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7742 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7746 if (non_logical_cint_operand (operands[2], DImode))
7748 HOST_WIDE_INT value;
7749 rtx tmp = ((!can_create_pseudo_p ()
7750 || rtx_equal_p (operands[0], operands[1]))
7751 ? operands[0] : gen_reg_rtx (DImode));
7753 if (GET_CODE (operands[2]) == CONST_INT)
7755 value = INTVAL (operands[2]);
7756 emit_insn (gen_xordi3 (tmp, operands[1],
7757 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7761 value = CONST_DOUBLE_LOW (operands[2]);
7762 emit_insn (gen_xordi3 (tmp, operands[1],
7763 immed_double_const (value
7764 & (~ (HOST_WIDE_INT) 0xffff),
7768 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7773 (define_insn "*booldi3_internal1"
7774 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7775 (match_operator:DI 3 "boolean_or_operator"
7776 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7777 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7784 (define_insn "*booldi3_internal2"
7785 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7786 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7787 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7788 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7790 (clobber (match_scratch:DI 3 "=r,r"))]
7795 [(set_attr "type" "compare")
7796 (set_attr "length" "4,8")])
7799 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7800 (compare:CC (match_operator:DI 4 "boolean_operator"
7801 [(match_operand:DI 1 "gpc_reg_operand" "")
7802 (match_operand:DI 2 "gpc_reg_operand" "")])
7804 (clobber (match_scratch:DI 3 ""))]
7805 "TARGET_POWERPC64 && reload_completed"
7806 [(set (match_dup 3) (match_dup 4))
7808 (compare:CC (match_dup 3)
7812 (define_insn "*booldi3_internal3"
7813 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7814 (compare:CC (match_operator:DI 4 "boolean_operator"
7815 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7816 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7818 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7824 [(set_attr "type" "compare")
7825 (set_attr "length" "4,8")])
7828 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7829 (compare:CC (match_operator:DI 4 "boolean_operator"
7830 [(match_operand:DI 1 "gpc_reg_operand" "")
7831 (match_operand:DI 2 "gpc_reg_operand" "")])
7833 (set (match_operand:DI 0 "gpc_reg_operand" "")
7835 "TARGET_POWERPC64 && reload_completed"
7836 [(set (match_dup 0) (match_dup 4))
7838 (compare:CC (match_dup 0)
7842 ;; Split a logical operation that we can't do in one insn into two insns,
7843 ;; each of which does one 16-bit part. This is used by combine.
7846 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7847 (match_operator:DI 3 "boolean_or_operator"
7848 [(match_operand:DI 1 "gpc_reg_operand" "")
7849 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7851 [(set (match_dup 0) (match_dup 4))
7852 (set (match_dup 0) (match_dup 5))]
7857 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7859 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7860 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7862 i4 = GEN_INT (value & 0xffff);
7866 i3 = GEN_INT (INTVAL (operands[2])
7867 & (~ (HOST_WIDE_INT) 0xffff));
7868 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7870 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7872 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7876 (define_insn "*boolcdi3_internal1"
7877 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7878 (match_operator:DI 3 "boolean_operator"
7879 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7880 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7884 (define_insn "*boolcdi3_internal2"
7885 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7886 (compare:CC (match_operator:DI 4 "boolean_operator"
7887 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7888 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7890 (clobber (match_scratch:DI 3 "=r,r"))]
7895 [(set_attr "type" "compare")
7896 (set_attr "length" "4,8")])
7899 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7900 (compare:CC (match_operator:DI 4 "boolean_operator"
7901 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7902 (match_operand:DI 2 "gpc_reg_operand" "")])
7904 (clobber (match_scratch:DI 3 ""))]
7905 "TARGET_POWERPC64 && reload_completed"
7906 [(set (match_dup 3) (match_dup 4))
7908 (compare:CC (match_dup 3)
7912 (define_insn "*boolcdi3_internal3"
7913 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7914 (compare:CC (match_operator:DI 4 "boolean_operator"
7915 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7916 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7918 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7924 [(set_attr "type" "compare")
7925 (set_attr "length" "4,8")])
7928 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7929 (compare:CC (match_operator:DI 4 "boolean_operator"
7930 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7931 (match_operand:DI 2 "gpc_reg_operand" "")])
7933 (set (match_operand:DI 0 "gpc_reg_operand" "")
7935 "TARGET_POWERPC64 && reload_completed"
7936 [(set (match_dup 0) (match_dup 4))
7938 (compare:CC (match_dup 0)
7942 (define_insn "*boolccdi3_internal1"
7943 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7944 (match_operator:DI 3 "boolean_operator"
7945 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7946 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7950 (define_insn "*boolccdi3_internal2"
7951 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7952 (compare:CC (match_operator:DI 4 "boolean_operator"
7953 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7954 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7956 (clobber (match_scratch:DI 3 "=r,r"))]
7961 [(set_attr "type" "compare")
7962 (set_attr "length" "4,8")])
7965 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7966 (compare:CC (match_operator:DI 4 "boolean_operator"
7967 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7968 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7970 (clobber (match_scratch:DI 3 ""))]
7971 "TARGET_POWERPC64 && reload_completed"
7972 [(set (match_dup 3) (match_dup 4))
7974 (compare:CC (match_dup 3)
7978 (define_insn "*boolccdi3_internal3"
7979 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7980 (compare:CC (match_operator:DI 4 "boolean_operator"
7981 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7982 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7984 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7990 [(set_attr "type" "compare")
7991 (set_attr "length" "4,8")])
7994 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7995 (compare:CC (match_operator:DI 4 "boolean_operator"
7996 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7997 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7999 (set (match_operand:DI 0 "gpc_reg_operand" "")
8001 "TARGET_POWERPC64 && reload_completed"
8002 [(set (match_dup 0) (match_dup 4))
8004 (compare:CC (match_dup 0)
8008 ;; Now define ways of moving data around.
8010 ;; Set up a register with a value from the GOT table
8012 (define_expand "movsi_got"
8013 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8014 (unspec:SI [(match_operand:SI 1 "got_operand" "")
8015 (match_dup 2)] UNSPEC_MOVSI_GOT))]
8016 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8019 if (GET_CODE (operands[1]) == CONST)
8021 rtx offset = const0_rtx;
8022 HOST_WIDE_INT value;
8024 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8025 value = INTVAL (offset);
8028 rtx tmp = (!can_create_pseudo_p ()
8030 : gen_reg_rtx (Pmode));
8031 emit_insn (gen_movsi_got (tmp, operands[1]));
8032 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8037 operands[2] = rs6000_got_register (operands[1]);
8040 (define_insn "*movsi_got_internal"
8041 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8042 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8043 (match_operand:SI 2 "gpc_reg_operand" "b")]
8045 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8046 "{l|lwz} %0,%a1@got(%2)"
8047 [(set_attr "type" "load")])
8049 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
8050 ;; didn't get allocated to a hard register.
8052 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8053 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8054 (match_operand:SI 2 "memory_operand" "")]
8056 "DEFAULT_ABI == ABI_V4
8058 && (reload_in_progress || reload_completed)"
8059 [(set (match_dup 0) (match_dup 2))
8060 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8064 ;; For SI, we special-case integers that can't be loaded in one insn. We
8065 ;; do the load 16-bits at a time. We could do this by loading from memory,
8066 ;; and this is even supposed to be faster, but it is simpler not to get
8067 ;; integers in the TOC.
8068 (define_insn "movsi_low"
8069 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8070 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
8071 (match_operand 2 "" ""))))]
8072 "TARGET_MACHO && ! TARGET_64BIT"
8073 "{l|lwz} %0,lo16(%2)(%1)"
8074 [(set_attr "type" "load")
8075 (set_attr "length" "4")])
8077 (define_insn "*movsi_internal1"
8078 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
8079 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
8080 "gpc_reg_operand (operands[0], SImode)
8081 || gpc_reg_operand (operands[1], SImode)"
8085 {l%U1%X1|lwz%U1%X1} %0,%1
8086 {st%U0%X0|stw%U0%X0} %1,%0
8096 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
8097 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
8099 ;; Split a load of a large constant into the appropriate two-insn
8103 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8104 (match_operand:SI 1 "const_int_operand" ""))]
8105 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
8106 && (INTVAL (operands[1]) & 0xffff) != 0"
8110 (ior:SI (match_dup 0)
8113 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8115 if (tem == operands[0])
8121 (define_insn "*mov<mode>_internal2"
8122 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8123 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
8125 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8128 {cmpi|cmp<wd>i} %2,%0,0
8131 [(set_attr "type" "cmp,compare,cmp")
8132 (set_attr "length" "4,4,8")])
8135 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8136 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
8138 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8140 [(set (match_dup 0) (match_dup 1))
8142 (compare:CC (match_dup 0)
8146 (define_insn "*movhi_internal"
8147 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8148 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8149 "gpc_reg_operand (operands[0], HImode)
8150 || gpc_reg_operand (operands[1], HImode)"
8160 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8162 (define_expand "mov<mode>"
8163 [(set (match_operand:INT 0 "general_operand" "")
8164 (match_operand:INT 1 "any_operand" ""))]
8166 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8168 (define_insn "*movqi_internal"
8169 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8170 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8171 "gpc_reg_operand (operands[0], QImode)
8172 || gpc_reg_operand (operands[1], QImode)"
8182 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8184 ;; Here is how to move condition codes around. When we store CC data in
8185 ;; an integer register or memory, we store just the high-order 4 bits.
8186 ;; This lets us not shift in the most common case of CR0.
8187 (define_expand "movcc"
8188 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8189 (match_operand:CC 1 "nonimmediate_operand" ""))]
8193 (define_insn "*movcc_internal1"
8194 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
8195 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
8196 "register_operand (operands[0], CCmode)
8197 || register_operand (operands[1], CCmode)"
8201 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
8204 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
8210 {l%U1%X1|lwz%U1%X1} %0,%1
8211 {st%U0%U1|stw%U0%U1} %1,%0"
8213 (cond [(eq_attr "alternative" "0,3")
8214 (const_string "cr_logical")
8215 (eq_attr "alternative" "1,2")
8216 (const_string "mtcr")
8217 (eq_attr "alternative" "6,7,9")
8218 (const_string "integer")
8219 (eq_attr "alternative" "8")
8220 (const_string "mfjmpr")
8221 (eq_attr "alternative" "10")
8222 (const_string "mtjmpr")
8223 (eq_attr "alternative" "11")
8224 (const_string "load")
8225 (eq_attr "alternative" "12")
8226 (const_string "store")
8227 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
8228 (const_string "mfcrf")
8230 (const_string "mfcr")))
8231 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
8233 ;; For floating-point, we normally deal with the floating-point registers
8234 ;; unless -msoft-float is used. The sole exception is that parameter passing
8235 ;; can produce floating-point values in fixed-point registers. Unless the
8236 ;; value is a simple constant or already in memory, we deal with this by
8237 ;; allocating memory and copying the value explicitly via that memory location.
8238 (define_expand "movsf"
8239 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8240 (match_operand:SF 1 "any_operand" ""))]
8242 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
8245 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8246 (match_operand:SF 1 "const_double_operand" ""))]
8248 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8249 || (GET_CODE (operands[0]) == SUBREG
8250 && GET_CODE (SUBREG_REG (operands[0])) == REG
8251 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8252 [(set (match_dup 2) (match_dup 3))]
8258 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8259 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
8261 if (! TARGET_POWERPC64)
8262 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
8264 operands[2] = gen_lowpart (SImode, operands[0]);
8266 operands[3] = gen_int_mode (l, SImode);
8269 (define_insn "*movsf_hardfloat"
8270 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
8271 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
8272 "(gpc_reg_operand (operands[0], SFmode)
8273 || gpc_reg_operand (operands[1], SFmode))
8274 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
8277 {l%U1%X1|lwz%U1%X1} %0,%1
8278 {st%U0%X0|stw%U0%X0} %1,%0
8288 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
8289 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
8291 (define_insn "*movsf_softfloat"
8292 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
8293 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
8294 "(gpc_reg_operand (operands[0], SFmode)
8295 || gpc_reg_operand (operands[1], SFmode))
8296 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
8302 {l%U1%X1|lwz%U1%X1} %0,%1
8303 {st%U0%X0|stw%U0%X0} %1,%0
8310 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
8311 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
8314 (define_expand "movdf"
8315 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8316 (match_operand:DF 1 "any_operand" ""))]
8318 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
8321 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8322 (match_operand:DF 1 "const_int_operand" ""))]
8323 "! TARGET_POWERPC64 && reload_completed
8324 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8325 || (GET_CODE (operands[0]) == SUBREG
8326 && GET_CODE (SUBREG_REG (operands[0])) == REG
8327 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8328 [(set (match_dup 2) (match_dup 4))
8329 (set (match_dup 3) (match_dup 1))]
8332 int endian = (WORDS_BIG_ENDIAN == 0);
8333 HOST_WIDE_INT value = INTVAL (operands[1]);
8335 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8336 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8337 #if HOST_BITS_PER_WIDE_INT == 32
8338 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8340 operands[4] = GEN_INT (value >> 32);
8341 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8346 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8347 (match_operand:DF 1 "const_double_operand" ""))]
8348 "! TARGET_POWERPC64 && reload_completed
8349 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8350 || (GET_CODE (operands[0]) == SUBREG
8351 && GET_CODE (SUBREG_REG (operands[0])) == REG
8352 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8353 [(set (match_dup 2) (match_dup 4))
8354 (set (match_dup 3) (match_dup 5))]
8357 int endian = (WORDS_BIG_ENDIAN == 0);
8361 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8362 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8364 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8365 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8366 operands[4] = gen_int_mode (l[endian], SImode);
8367 operands[5] = gen_int_mode (l[1 - endian], SImode);
8371 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8372 (match_operand:DF 1 "const_double_operand" ""))]
8373 "TARGET_POWERPC64 && reload_completed
8374 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8375 || (GET_CODE (operands[0]) == SUBREG
8376 && GET_CODE (SUBREG_REG (operands[0])) == REG
8377 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8378 [(set (match_dup 2) (match_dup 3))]
8381 int endian = (WORDS_BIG_ENDIAN == 0);
8384 #if HOST_BITS_PER_WIDE_INT >= 64
8388 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8389 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8391 operands[2] = gen_lowpart (DImode, operands[0]);
8392 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8393 #if HOST_BITS_PER_WIDE_INT >= 64
8394 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8395 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8397 operands[3] = gen_int_mode (val, DImode);
8399 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8403 ;; Don't have reload use general registers to load a constant. First,
8404 ;; it might not work if the output operand is the equivalent of
8405 ;; a non-offsettable memref, but also it is less efficient than loading
8406 ;; the constant into an FP register, since it will probably be used there.
8407 ;; The "??" is a kludge until we can figure out a more reasonable way
8408 ;; of handling these non-offsettable values.
8409 (define_insn "*movdf_hardfloat32"
8410 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8411 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
8412 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8413 && (gpc_reg_operand (operands[0], DFmode)
8414 || gpc_reg_operand (operands[1], DFmode))"
8417 switch (which_alternative)
8422 /* We normally copy the low-numbered register first. However, if
8423 the first register operand 0 is the same as the second register
8424 of operand 1, we must copy in the opposite order. */
8425 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8426 return \"mr %L0,%L1\;mr %0,%1\";
8428 return \"mr %0,%1\;mr %L0,%L1\";
8430 if (rs6000_offsettable_memref_p (operands[1])
8431 || (GET_CODE (operands[1]) == MEM
8432 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8433 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8434 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC
8435 || GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)))
8437 /* If the low-address word is used in the address, we must load
8438 it last. Otherwise, load it first. Note that we cannot have
8439 auto-increment in that case since the address register is
8440 known to be dead. */
8441 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8443 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8445 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
8451 addreg = find_addr_reg (XEXP (operands[1], 0));
8452 if (refers_to_regno_p (REGNO (operands[0]),
8453 REGNO (operands[0]) + 1,
8456 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8457 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
8458 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8459 return \"{l%X1|lwz%X1} %0,%1\";
8463 output_asm_insn (\"{l%X1|lwz%X1} %0,%1\", operands);
8464 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8465 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
8466 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8471 if (rs6000_offsettable_memref_p (operands[0])
8472 || (GET_CODE (operands[0]) == MEM
8473 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8474 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8475 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
8476 || GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)))
8477 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
8482 addreg = find_addr_reg (XEXP (operands[0], 0));
8483 output_asm_insn (\"{st%X0|stw%X0} %1,%0\", operands);
8484 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8485 output_asm_insn (\"{st%X0|stw%X0} %L1,%0\", operands);
8486 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8490 return \"fmr %0,%1\";
8492 return \"lfd%U1%X1 %0,%1\";
8494 return \"stfd%U0%X0 %1,%0\";
8501 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
8502 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
8504 (define_insn "*movdf_softfloat32"
8505 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8506 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8507 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8508 && (gpc_reg_operand (operands[0], DFmode)
8509 || gpc_reg_operand (operands[1], DFmode))"
8512 switch (which_alternative)
8517 /* We normally copy the low-numbered register first. However, if
8518 the first register operand 0 is the same as the second register of
8519 operand 1, we must copy in the opposite order. */
8520 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8521 return \"mr %L0,%L1\;mr %0,%1\";
8523 return \"mr %0,%1\;mr %L0,%L1\";
8525 /* If the low-address word is used in the address, we must load
8526 it last. Otherwise, load it first. Note that we cannot have
8527 auto-increment in that case since the address register is
8528 known to be dead. */
8529 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8531 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8533 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
8535 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
8542 [(set_attr "type" "two,load,store,*,*,*")
8543 (set_attr "length" "8,8,8,8,12,16")])
8545 ; ld/std require word-aligned displacements -> 'Y' constraint.
8546 ; List Y->r and r->Y before r->r for reload.
8547 (define_insn "*movdf_hardfloat64_mfpgpr"
8548 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f")
8549 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))]
8550 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8551 && (gpc_reg_operand (operands[0], DFmode)
8552 || gpc_reg_operand (operands[1], DFmode))"
8568 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
8569 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
8571 ; ld/std require word-aligned displacements -> 'Y' constraint.
8572 ; List Y->r and r->Y before r->r for reload.
8573 (define_insn "*movdf_hardfloat64"
8574 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
8575 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
8576 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8577 && (gpc_reg_operand (operands[0], DFmode)
8578 || gpc_reg_operand (operands[1], DFmode))"
8592 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
8593 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
8595 (define_insn "*movdf_softfloat64"
8596 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8597 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
8598 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8599 && (gpc_reg_operand (operands[0], DFmode)
8600 || gpc_reg_operand (operands[1], DFmode))"
8611 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
8612 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8614 (define_expand "movtf"
8615 [(set (match_operand:TF 0 "general_operand" "")
8616 (match_operand:TF 1 "any_operand" ""))]
8617 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
8618 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8620 ; It's important to list the o->f and f->o moves before f->f because
8621 ; otherwise reload, given m->f, will try to pick f->f and reload it,
8622 ; which doesn't make progress. Likewise r->Y must be before r->r.
8623 (define_insn_and_split "*movtf_internal"
8624 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
8625 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
8627 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8628 && (gpc_reg_operand (operands[0], TFmode)
8629 || gpc_reg_operand (operands[1], TFmode))"
8631 "&& reload_completed"
8633 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8634 [(set_attr "length" "8,8,8,20,20,16")])
8636 (define_insn_and_split "*movtf_softfloat"
8637 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
8638 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
8640 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
8641 && (gpc_reg_operand (operands[0], TFmode)
8642 || gpc_reg_operand (operands[1], TFmode))"
8644 "&& reload_completed"
8646 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8647 [(set_attr "length" "20,20,16")])
8649 (define_expand "extenddftf2"
8650 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8651 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8653 && TARGET_HARD_FLOAT
8654 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8655 && TARGET_LONG_DOUBLE_128"
8657 if (TARGET_E500_DOUBLE)
8658 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8660 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8664 (define_expand "extenddftf2_fprs"
8665 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8666 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8667 (use (match_dup 2))])]
8669 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8671 operands[2] = CONST0_RTX (DFmode);
8672 /* Generate GOT reference early for SVR4 PIC. */
8673 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8674 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8677 (define_insn_and_split "*extenddftf2_internal"
8678 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8679 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8680 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
8682 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8684 "&& reload_completed"
8687 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8688 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8689 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8691 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8696 (define_expand "extendsftf2"
8697 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8698 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8700 && TARGET_HARD_FLOAT
8701 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8702 && TARGET_LONG_DOUBLE_128"
8704 rtx tmp = gen_reg_rtx (DFmode);
8705 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8706 emit_insn (gen_extenddftf2 (operands[0], tmp));
8710 (define_expand "trunctfdf2"
8711 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8712 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8714 && TARGET_HARD_FLOAT
8715 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8716 && TARGET_LONG_DOUBLE_128"
8719 (define_insn_and_split "trunctfdf2_internal1"
8720 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8721 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
8722 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8723 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8727 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8730 emit_note (NOTE_INSN_DELETED);
8733 [(set_attr "type" "fp")])
8735 (define_insn "trunctfdf2_internal2"
8736 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8737 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8738 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8739 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8741 [(set_attr "type" "fp")])
8743 (define_expand "trunctfsf2"
8744 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8745 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8747 && TARGET_HARD_FLOAT
8748 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8749 && TARGET_LONG_DOUBLE_128"
8751 if (TARGET_E500_DOUBLE)
8752 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8754 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8758 (define_insn_and_split "trunctfsf2_fprs"
8759 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8760 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8761 (clobber (match_scratch:DF 2 "=f"))]
8763 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8765 "&& reload_completed"
8767 (float_truncate:DF (match_dup 1)))
8769 (float_truncate:SF (match_dup 2)))]
8772 (define_expand "floatsitf2"
8773 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8774 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
8776 && TARGET_HARD_FLOAT
8777 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8778 && TARGET_LONG_DOUBLE_128"
8780 rtx tmp = gen_reg_rtx (DFmode);
8781 expand_float (tmp, operands[1], false);
8782 emit_insn (gen_extenddftf2 (operands[0], tmp));
8786 ; fadd, but rounding towards zero.
8787 ; This is probably not the optimal code sequence.
8788 (define_insn "fix_trunc_helper"
8789 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8790 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8791 UNSPEC_FIX_TRUNC_TF))
8792 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8793 "TARGET_HARD_FLOAT && TARGET_FPRS"
8794 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8795 [(set_attr "type" "fp")
8796 (set_attr "length" "20")])
8798 (define_expand "fix_trunctfsi2"
8799 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8800 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8802 && (TARGET_POWER2 || TARGET_POWERPC)
8803 && TARGET_HARD_FLOAT
8804 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8805 && TARGET_LONG_DOUBLE_128"
8807 if (TARGET_E500_DOUBLE)
8808 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8810 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8814 (define_expand "fix_trunctfsi2_fprs"
8815 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8816 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8817 (clobber (match_dup 2))
8818 (clobber (match_dup 3))
8819 (clobber (match_dup 4))
8820 (clobber (match_dup 5))])]
8822 && (TARGET_POWER2 || TARGET_POWERPC)
8823 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8825 operands[2] = gen_reg_rtx (DFmode);
8826 operands[3] = gen_reg_rtx (DFmode);
8827 operands[4] = gen_reg_rtx (DImode);
8828 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8831 (define_insn_and_split "*fix_trunctfsi2_internal"
8832 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8833 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8834 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8835 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8836 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8837 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
8839 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8841 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[5]))"
8845 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8847 gcc_assert (MEM_P (operands[5]));
8848 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8850 emit_insn (gen_fctiwz (operands[4], operands[2]));
8851 emit_move_insn (operands[5], operands[4]);
8852 emit_move_insn (operands[0], lowword);
8856 (define_expand "negtf2"
8857 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8858 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8860 && TARGET_HARD_FLOAT
8861 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8862 && TARGET_LONG_DOUBLE_128"
8865 (define_insn "negtf2_internal"
8866 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8867 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8869 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8872 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8873 return \"fneg %L0,%L1\;fneg %0,%1\";
8875 return \"fneg %0,%1\;fneg %L0,%L1\";
8877 [(set_attr "type" "fp")
8878 (set_attr "length" "8")])
8880 (define_expand "abstf2"
8881 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8882 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8884 && TARGET_HARD_FLOAT
8885 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8886 && TARGET_LONG_DOUBLE_128"
8889 rtx label = gen_label_rtx ();
8890 if (TARGET_E500_DOUBLE)
8892 if (flag_unsafe_math_optimizations)
8893 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
8895 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
8898 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8903 (define_expand "abstf2_internal"
8904 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8905 (match_operand:TF 1 "gpc_reg_operand" ""))
8906 (set (match_dup 3) (match_dup 5))
8907 (set (match_dup 5) (abs:DF (match_dup 5)))
8908 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8909 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8910 (label_ref (match_operand 2 "" ""))
8912 (set (match_dup 6) (neg:DF (match_dup 6)))]
8914 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8917 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8918 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8919 operands[3] = gen_reg_rtx (DFmode);
8920 operands[4] = gen_reg_rtx (CCFPmode);
8921 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8922 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8925 ;; Next come the multi-word integer load and store and the load and store
8928 ; List r->r after r->"o<>", otherwise reload will try to reload a
8929 ; non-offsettable address by using r->r which won't make progress.
8930 (define_insn "*movdi_internal32"
8931 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
8932 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
8934 && (gpc_reg_operand (operands[0], DImode)
8935 || gpc_reg_operand (operands[1], DImode))"
8944 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
8947 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8948 (match_operand:DI 1 "const_int_operand" ""))]
8949 "! TARGET_POWERPC64 && reload_completed"
8950 [(set (match_dup 2) (match_dup 4))
8951 (set (match_dup 3) (match_dup 1))]
8954 HOST_WIDE_INT value = INTVAL (operands[1]);
8955 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8957 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8959 #if HOST_BITS_PER_WIDE_INT == 32
8960 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8962 operands[4] = GEN_INT (value >> 32);
8963 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8968 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "")
8969 (match_operand:DI 1 "input_operand" ""))]
8970 "reload_completed && !TARGET_POWERPC64
8971 && gpr_or_gpr_p (operands[0], operands[1])"
8973 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8975 (define_insn "*movdi_mfpgpr"
8976 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h,r,*f")
8977 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0,*f,r"))]
8978 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8979 && (gpc_reg_operand (operands[0], DImode)
8980 || gpc_reg_operand (operands[1], DImode))"
8997 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
8998 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
9000 (define_insn "*movdi_internal64"
9001 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
9002 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
9003 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
9004 && (gpc_reg_operand (operands[0], DImode)
9005 || gpc_reg_operand (operands[1], DImode))"
9020 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
9021 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
9023 ;; immediate value valid for a single instruction hiding in a const_double
9025 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9026 (match_operand:DI 1 "const_double_operand" "F"))]
9027 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
9028 && GET_CODE (operands[1]) == CONST_DOUBLE
9029 && num_insns_constant (operands[1], DImode) == 1"
9032 return ((unsigned HOST_WIDE_INT)
9033 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
9034 ? \"li %0,%1\" : \"lis %0,%v1\";
9037 ;; Generate all one-bits and clear left or right.
9038 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9040 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9041 (match_operand:DI 1 "mask64_operand" ""))]
9042 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9043 [(set (match_dup 0) (const_int -1))
9045 (and:DI (rotate:DI (match_dup 0)
9050 ;; Split a load of a large constant into the appropriate five-instruction
9051 ;; sequence. Handle anything in a constant number of insns.
9052 ;; When non-easy constants can go in the TOC, this should use
9053 ;; easy_fp_constant predicate.
9055 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9056 (match_operand:DI 1 "const_int_operand" ""))]
9057 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9058 [(set (match_dup 0) (match_dup 2))
9059 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9061 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9063 if (tem == operands[0])
9070 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9071 (match_operand:DI 1 "const_double_operand" ""))]
9072 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9073 [(set (match_dup 0) (match_dup 2))
9074 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9076 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9078 if (tem == operands[0])
9084 ;; TImode is similar, except that we usually want to compute the address into
9085 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
9086 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
9088 ;; We say that MQ is clobbered in the last alternative because the first
9089 ;; alternative would never get used otherwise since it would need a reload
9090 ;; while the 2nd alternative would not. We put memory cases first so they
9091 ;; are preferred. Otherwise, we'd try to reload the output instead of
9092 ;; giving the SCRATCH mq.
9094 (define_insn "*movti_power"
9095 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
9096 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
9097 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
9098 "TARGET_POWER && ! TARGET_POWERPC64
9099 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9102 switch (which_alternative)
9109 return \"{stsi|stswi} %1,%P0,16\";
9114 /* If the address is not used in the output, we can use lsi. Otherwise,
9115 fall through to generating four loads. */
9117 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9118 return \"{lsi|lswi} %0,%P1,16\";
9119 /* ... fall through ... */
9125 [(set_attr "type" "store,store,*,load,load,*")])
9127 (define_insn "*movti_string"
9128 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
9129 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
9130 "! TARGET_POWER && ! TARGET_POWERPC64
9131 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9134 switch (which_alternative)
9140 return \"{stsi|stswi} %1,%P0,16\";
9145 /* If the address is not used in the output, we can use lsi. Otherwise,
9146 fall through to generating four loads. */
9148 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9149 return \"{lsi|lswi} %0,%P1,16\";
9150 /* ... fall through ... */
9156 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")])
9158 (define_insn "*movti_ppc64"
9159 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
9160 (match_operand:TI 1 "input_operand" "r,r,m"))]
9161 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
9162 || gpc_reg_operand (operands[1], TImode))"
9164 [(set_attr "type" "*,load,store")])
9167 [(set (match_operand:TI 0 "gpc_reg_operand" "")
9168 (match_operand:TI 1 "const_double_operand" ""))]
9170 [(set (match_dup 2) (match_dup 4))
9171 (set (match_dup 3) (match_dup 5))]
9174 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9176 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9178 if (GET_CODE (operands[1]) == CONST_DOUBLE)
9180 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9181 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9183 else if (GET_CODE (operands[1]) == CONST_INT)
9185 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9186 operands[5] = operands[1];
9193 [(set (match_operand:TI 0 "nonimmediate_operand" "")
9194 (match_operand:TI 1 "input_operand" ""))]
9196 && gpr_or_gpr_p (operands[0], operands[1])"
9198 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9200 (define_expand "load_multiple"
9201 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9202 (match_operand:SI 1 "" ""))
9203 (use (match_operand:SI 2 "" ""))])]
9204 "TARGET_STRING && !TARGET_POWERPC64"
9212 /* Support only loading a constant number of fixed-point registers from
9213 memory and only bother with this if more than two; the machine
9214 doesn't support more than eight. */
9215 if (GET_CODE (operands[2]) != CONST_INT
9216 || INTVAL (operands[2]) <= 2
9217 || INTVAL (operands[2]) > 8
9218 || GET_CODE (operands[1]) != MEM
9219 || GET_CODE (operands[0]) != REG
9220 || REGNO (operands[0]) >= 32)
9223 count = INTVAL (operands[2]);
9224 regno = REGNO (operands[0]);
9226 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9227 op1 = replace_equiv_address (operands[1],
9228 force_reg (SImode, XEXP (operands[1], 0)));
9230 for (i = 0; i < count; i++)
9231 XVECEXP (operands[3], 0, i)
9232 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
9233 adjust_address_nv (op1, SImode, i * 4));
9236 (define_insn "*ldmsi8"
9237 [(match_parallel 0 "load_multiple_operation"
9238 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9239 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9240 (set (match_operand:SI 3 "gpc_reg_operand" "")
9241 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9242 (set (match_operand:SI 4 "gpc_reg_operand" "")
9243 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9244 (set (match_operand:SI 5 "gpc_reg_operand" "")
9245 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9246 (set (match_operand:SI 6 "gpc_reg_operand" "")
9247 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9248 (set (match_operand:SI 7 "gpc_reg_operand" "")
9249 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9250 (set (match_operand:SI 8 "gpc_reg_operand" "")
9251 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9252 (set (match_operand:SI 9 "gpc_reg_operand" "")
9253 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9254 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9256 { return rs6000_output_load_multiple (operands); }"
9257 [(set_attr "type" "load_ux")
9258 (set_attr "length" "32")])
9260 (define_insn "*ldmsi7"
9261 [(match_parallel 0 "load_multiple_operation"
9262 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9263 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9264 (set (match_operand:SI 3 "gpc_reg_operand" "")
9265 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9266 (set (match_operand:SI 4 "gpc_reg_operand" "")
9267 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9268 (set (match_operand:SI 5 "gpc_reg_operand" "")
9269 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9270 (set (match_operand:SI 6 "gpc_reg_operand" "")
9271 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9272 (set (match_operand:SI 7 "gpc_reg_operand" "")
9273 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9274 (set (match_operand:SI 8 "gpc_reg_operand" "")
9275 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9276 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9278 { return rs6000_output_load_multiple (operands); }"
9279 [(set_attr "type" "load_ux")
9280 (set_attr "length" "32")])
9282 (define_insn "*ldmsi6"
9283 [(match_parallel 0 "load_multiple_operation"
9284 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9285 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9286 (set (match_operand:SI 3 "gpc_reg_operand" "")
9287 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9288 (set (match_operand:SI 4 "gpc_reg_operand" "")
9289 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9290 (set (match_operand:SI 5 "gpc_reg_operand" "")
9291 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9292 (set (match_operand:SI 6 "gpc_reg_operand" "")
9293 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9294 (set (match_operand:SI 7 "gpc_reg_operand" "")
9295 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9296 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9298 { return rs6000_output_load_multiple (operands); }"
9299 [(set_attr "type" "load_ux")
9300 (set_attr "length" "32")])
9302 (define_insn "*ldmsi5"
9303 [(match_parallel 0 "load_multiple_operation"
9304 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9305 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9306 (set (match_operand:SI 3 "gpc_reg_operand" "")
9307 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9308 (set (match_operand:SI 4 "gpc_reg_operand" "")
9309 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9310 (set (match_operand:SI 5 "gpc_reg_operand" "")
9311 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9312 (set (match_operand:SI 6 "gpc_reg_operand" "")
9313 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9314 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9316 { return rs6000_output_load_multiple (operands); }"
9317 [(set_attr "type" "load_ux")
9318 (set_attr "length" "32")])
9320 (define_insn "*ldmsi4"
9321 [(match_parallel 0 "load_multiple_operation"
9322 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9323 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9324 (set (match_operand:SI 3 "gpc_reg_operand" "")
9325 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9326 (set (match_operand:SI 4 "gpc_reg_operand" "")
9327 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9328 (set (match_operand:SI 5 "gpc_reg_operand" "")
9329 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9330 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9332 { return rs6000_output_load_multiple (operands); }"
9333 [(set_attr "type" "load_ux")
9334 (set_attr "length" "32")])
9336 (define_insn "*ldmsi3"
9337 [(match_parallel 0 "load_multiple_operation"
9338 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9339 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9340 (set (match_operand:SI 3 "gpc_reg_operand" "")
9341 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9342 (set (match_operand:SI 4 "gpc_reg_operand" "")
9343 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9344 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9346 { return rs6000_output_load_multiple (operands); }"
9347 [(set_attr "type" "load_ux")
9348 (set_attr "length" "32")])
9350 (define_expand "store_multiple"
9351 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9352 (match_operand:SI 1 "" ""))
9353 (clobber (scratch:SI))
9354 (use (match_operand:SI 2 "" ""))])]
9355 "TARGET_STRING && !TARGET_POWERPC64"
9364 /* Support only storing a constant number of fixed-point registers to
9365 memory and only bother with this if more than two; the machine
9366 doesn't support more than eight. */
9367 if (GET_CODE (operands[2]) != CONST_INT
9368 || INTVAL (operands[2]) <= 2
9369 || INTVAL (operands[2]) > 8
9370 || GET_CODE (operands[0]) != MEM
9371 || GET_CODE (operands[1]) != REG
9372 || REGNO (operands[1]) >= 32)
9375 count = INTVAL (operands[2]);
9376 regno = REGNO (operands[1]);
9378 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
9379 to = force_reg (SImode, XEXP (operands[0], 0));
9380 op0 = replace_equiv_address (operands[0], to);
9382 XVECEXP (operands[3], 0, 0)
9383 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
9384 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
9385 gen_rtx_SCRATCH (SImode));
9387 for (i = 1; i < count; i++)
9388 XVECEXP (operands[3], 0, i + 1)
9389 = gen_rtx_SET (VOIDmode,
9390 adjust_address_nv (op0, SImode, i * 4),
9391 gen_rtx_REG (SImode, regno + i));
9394 (define_insn "*stmsi8"
9395 [(match_parallel 0 "store_multiple_operation"
9396 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9397 (match_operand:SI 2 "gpc_reg_operand" "r"))
9398 (clobber (match_scratch:SI 3 "=X"))
9399 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9400 (match_operand:SI 4 "gpc_reg_operand" "r"))
9401 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9402 (match_operand:SI 5 "gpc_reg_operand" "r"))
9403 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9404 (match_operand:SI 6 "gpc_reg_operand" "r"))
9405 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9406 (match_operand:SI 7 "gpc_reg_operand" "r"))
9407 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9408 (match_operand:SI 8 "gpc_reg_operand" "r"))
9409 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9410 (match_operand:SI 9 "gpc_reg_operand" "r"))
9411 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9412 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9413 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9414 "{stsi|stswi} %2,%1,%O0"
9415 [(set_attr "type" "store_ux")])
9417 (define_insn "*stmsi7"
9418 [(match_parallel 0 "store_multiple_operation"
9419 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9420 (match_operand:SI 2 "gpc_reg_operand" "r"))
9421 (clobber (match_scratch:SI 3 "=X"))
9422 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9423 (match_operand:SI 4 "gpc_reg_operand" "r"))
9424 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9425 (match_operand:SI 5 "gpc_reg_operand" "r"))
9426 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9427 (match_operand:SI 6 "gpc_reg_operand" "r"))
9428 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9429 (match_operand:SI 7 "gpc_reg_operand" "r"))
9430 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9431 (match_operand:SI 8 "gpc_reg_operand" "r"))
9432 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9433 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9434 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9435 "{stsi|stswi} %2,%1,%O0"
9436 [(set_attr "type" "store_ux")])
9438 (define_insn "*stmsi6"
9439 [(match_parallel 0 "store_multiple_operation"
9440 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9441 (match_operand:SI 2 "gpc_reg_operand" "r"))
9442 (clobber (match_scratch:SI 3 "=X"))
9443 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9444 (match_operand:SI 4 "gpc_reg_operand" "r"))
9445 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9446 (match_operand:SI 5 "gpc_reg_operand" "r"))
9447 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9448 (match_operand:SI 6 "gpc_reg_operand" "r"))
9449 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9450 (match_operand:SI 7 "gpc_reg_operand" "r"))
9451 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9452 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9453 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9454 "{stsi|stswi} %2,%1,%O0"
9455 [(set_attr "type" "store_ux")])
9457 (define_insn "*stmsi5"
9458 [(match_parallel 0 "store_multiple_operation"
9459 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9460 (match_operand:SI 2 "gpc_reg_operand" "r"))
9461 (clobber (match_scratch:SI 3 "=X"))
9462 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9463 (match_operand:SI 4 "gpc_reg_operand" "r"))
9464 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9465 (match_operand:SI 5 "gpc_reg_operand" "r"))
9466 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9467 (match_operand:SI 6 "gpc_reg_operand" "r"))
9468 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9469 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9470 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9471 "{stsi|stswi} %2,%1,%O0"
9472 [(set_attr "type" "store_ux")])
9474 (define_insn "*stmsi4"
9475 [(match_parallel 0 "store_multiple_operation"
9476 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9477 (match_operand:SI 2 "gpc_reg_operand" "r"))
9478 (clobber (match_scratch:SI 3 "=X"))
9479 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9480 (match_operand:SI 4 "gpc_reg_operand" "r"))
9481 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9482 (match_operand:SI 5 "gpc_reg_operand" "r"))
9483 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9484 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9485 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9486 "{stsi|stswi} %2,%1,%O0"
9487 [(set_attr "type" "store_ux")])
9489 (define_insn "*stmsi3"
9490 [(match_parallel 0 "store_multiple_operation"
9491 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9492 (match_operand:SI 2 "gpc_reg_operand" "r"))
9493 (clobber (match_scratch:SI 3 "=X"))
9494 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9495 (match_operand:SI 4 "gpc_reg_operand" "r"))
9496 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9497 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9498 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9499 "{stsi|stswi} %2,%1,%O0"
9500 [(set_attr "type" "store_ux")])
9502 (define_insn "*stmsi8_power"
9503 [(match_parallel 0 "store_multiple_operation"
9504 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9505 (match_operand:SI 2 "gpc_reg_operand" "r"))
9506 (clobber (match_scratch:SI 3 "=q"))
9507 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9508 (match_operand:SI 4 "gpc_reg_operand" "r"))
9509 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9510 (match_operand:SI 5 "gpc_reg_operand" "r"))
9511 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9512 (match_operand:SI 6 "gpc_reg_operand" "r"))
9513 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9514 (match_operand:SI 7 "gpc_reg_operand" "r"))
9515 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9516 (match_operand:SI 8 "gpc_reg_operand" "r"))
9517 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9518 (match_operand:SI 9 "gpc_reg_operand" "r"))
9519 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9520 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9521 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9522 "{stsi|stswi} %2,%1,%O0"
9523 [(set_attr "type" "store_ux")])
9525 (define_insn "*stmsi7_power"
9526 [(match_parallel 0 "store_multiple_operation"
9527 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9528 (match_operand:SI 2 "gpc_reg_operand" "r"))
9529 (clobber (match_scratch:SI 3 "=q"))
9530 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9531 (match_operand:SI 4 "gpc_reg_operand" "r"))
9532 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9533 (match_operand:SI 5 "gpc_reg_operand" "r"))
9534 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9535 (match_operand:SI 6 "gpc_reg_operand" "r"))
9536 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9537 (match_operand:SI 7 "gpc_reg_operand" "r"))
9538 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9539 (match_operand:SI 8 "gpc_reg_operand" "r"))
9540 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9541 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9542 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9543 "{stsi|stswi} %2,%1,%O0"
9544 [(set_attr "type" "store_ux")])
9546 (define_insn "*stmsi6_power"
9547 [(match_parallel 0 "store_multiple_operation"
9548 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9549 (match_operand:SI 2 "gpc_reg_operand" "r"))
9550 (clobber (match_scratch:SI 3 "=q"))
9551 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9552 (match_operand:SI 4 "gpc_reg_operand" "r"))
9553 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9554 (match_operand:SI 5 "gpc_reg_operand" "r"))
9555 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9556 (match_operand:SI 6 "gpc_reg_operand" "r"))
9557 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9558 (match_operand:SI 7 "gpc_reg_operand" "r"))
9559 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9560 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9561 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9562 "{stsi|stswi} %2,%1,%O0"
9563 [(set_attr "type" "store_ux")])
9565 (define_insn "*stmsi5_power"
9566 [(match_parallel 0 "store_multiple_operation"
9567 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9568 (match_operand:SI 2 "gpc_reg_operand" "r"))
9569 (clobber (match_scratch:SI 3 "=q"))
9570 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9571 (match_operand:SI 4 "gpc_reg_operand" "r"))
9572 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9573 (match_operand:SI 5 "gpc_reg_operand" "r"))
9574 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9575 (match_operand:SI 6 "gpc_reg_operand" "r"))
9576 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9577 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9578 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9579 "{stsi|stswi} %2,%1,%O0"
9580 [(set_attr "type" "store_ux")])
9582 (define_insn "*stmsi4_power"
9583 [(match_parallel 0 "store_multiple_operation"
9584 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9585 (match_operand:SI 2 "gpc_reg_operand" "r"))
9586 (clobber (match_scratch:SI 3 "=q"))
9587 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9588 (match_operand:SI 4 "gpc_reg_operand" "r"))
9589 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9590 (match_operand:SI 5 "gpc_reg_operand" "r"))
9591 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9592 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9593 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9594 "{stsi|stswi} %2,%1,%O0"
9595 [(set_attr "type" "store_ux")])
9597 (define_insn "*stmsi3_power"
9598 [(match_parallel 0 "store_multiple_operation"
9599 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9600 (match_operand:SI 2 "gpc_reg_operand" "r"))
9601 (clobber (match_scratch:SI 3 "=q"))
9602 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9603 (match_operand:SI 4 "gpc_reg_operand" "r"))
9604 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9605 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9606 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9607 "{stsi|stswi} %2,%1,%O0"
9608 [(set_attr "type" "store_ux")])
9610 (define_expand "setmemsi"
9611 [(parallel [(set (match_operand:BLK 0 "" "")
9612 (match_operand 2 "const_int_operand" ""))
9613 (use (match_operand:SI 1 "" ""))
9614 (use (match_operand:SI 3 "" ""))])]
9618 /* If value to set is not zero, use the library routine. */
9619 if (operands[2] != const0_rtx)
9622 if (expand_block_clear (operands))
9628 ;; String/block move insn.
9629 ;; Argument 0 is the destination
9630 ;; Argument 1 is the source
9631 ;; Argument 2 is the length
9632 ;; Argument 3 is the alignment
9634 (define_expand "movmemsi"
9635 [(parallel [(set (match_operand:BLK 0 "" "")
9636 (match_operand:BLK 1 "" ""))
9637 (use (match_operand:SI 2 "" ""))
9638 (use (match_operand:SI 3 "" ""))])]
9642 if (expand_block_move (operands))
9648 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9649 ;; register allocator doesn't have a clue about allocating 8 word registers.
9650 ;; rD/rS = r5 is preferred, efficient form.
9651 (define_expand "movmemsi_8reg"
9652 [(parallel [(set (match_operand 0 "" "")
9653 (match_operand 1 "" ""))
9654 (use (match_operand 2 "" ""))
9655 (use (match_operand 3 "" ""))
9656 (clobber (reg:SI 5))
9657 (clobber (reg:SI 6))
9658 (clobber (reg:SI 7))
9659 (clobber (reg:SI 8))
9660 (clobber (reg:SI 9))
9661 (clobber (reg:SI 10))
9662 (clobber (reg:SI 11))
9663 (clobber (reg:SI 12))
9664 (clobber (match_scratch:SI 4 ""))])]
9669 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9670 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9671 (use (match_operand:SI 2 "immediate_operand" "i"))
9672 (use (match_operand:SI 3 "immediate_operand" "i"))
9673 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9674 (clobber (reg:SI 6))
9675 (clobber (reg:SI 7))
9676 (clobber (reg:SI 8))
9677 (clobber (reg:SI 9))
9678 (clobber (reg:SI 10))
9679 (clobber (reg:SI 11))
9680 (clobber (reg:SI 12))
9681 (clobber (match_scratch:SI 5 "=q"))]
9682 "TARGET_STRING && TARGET_POWER
9683 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9684 || INTVAL (operands[2]) == 0)
9685 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9686 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9687 && REGNO (operands[4]) == 5"
9688 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9689 [(set_attr "type" "store_ux")
9690 (set_attr "length" "8")])
9693 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9694 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9695 (use (match_operand:SI 2 "immediate_operand" "i"))
9696 (use (match_operand:SI 3 "immediate_operand" "i"))
9697 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9698 (clobber (reg:SI 6))
9699 (clobber (reg:SI 7))
9700 (clobber (reg:SI 8))
9701 (clobber (reg:SI 9))
9702 (clobber (reg:SI 10))
9703 (clobber (reg:SI 11))
9704 (clobber (reg:SI 12))
9705 (clobber (match_scratch:SI 5 "=X"))]
9706 "TARGET_STRING && ! TARGET_POWER
9707 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9708 || INTVAL (operands[2]) == 0)
9709 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9710 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9711 && REGNO (operands[4]) == 5"
9712 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9713 [(set_attr "type" "store_ux")
9714 (set_attr "length" "8")])
9716 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9717 ;; register allocator doesn't have a clue about allocating 6 word registers.
9718 ;; rD/rS = r5 is preferred, efficient form.
9719 (define_expand "movmemsi_6reg"
9720 [(parallel [(set (match_operand 0 "" "")
9721 (match_operand 1 "" ""))
9722 (use (match_operand 2 "" ""))
9723 (use (match_operand 3 "" ""))
9724 (clobber (reg:SI 5))
9725 (clobber (reg:SI 6))
9726 (clobber (reg:SI 7))
9727 (clobber (reg:SI 8))
9728 (clobber (reg:SI 9))
9729 (clobber (reg:SI 10))
9730 (clobber (match_scratch:SI 4 ""))])]
9735 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9736 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9737 (use (match_operand:SI 2 "immediate_operand" "i"))
9738 (use (match_operand:SI 3 "immediate_operand" "i"))
9739 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9740 (clobber (reg:SI 6))
9741 (clobber (reg:SI 7))
9742 (clobber (reg:SI 8))
9743 (clobber (reg:SI 9))
9744 (clobber (reg:SI 10))
9745 (clobber (match_scratch:SI 5 "=q"))]
9746 "TARGET_STRING && TARGET_POWER
9747 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9748 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9749 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9750 && REGNO (operands[4]) == 5"
9751 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9752 [(set_attr "type" "store_ux")
9753 (set_attr "length" "8")])
9756 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9757 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9758 (use (match_operand:SI 2 "immediate_operand" "i"))
9759 (use (match_operand:SI 3 "immediate_operand" "i"))
9760 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9761 (clobber (reg:SI 6))
9762 (clobber (reg:SI 7))
9763 (clobber (reg:SI 8))
9764 (clobber (reg:SI 9))
9765 (clobber (reg:SI 10))
9766 (clobber (match_scratch:SI 5 "=X"))]
9767 "TARGET_STRING && ! TARGET_POWER
9768 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9769 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9770 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9771 && REGNO (operands[4]) == 5"
9772 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9773 [(set_attr "type" "store_ux")
9774 (set_attr "length" "8")])
9776 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9777 ;; problems with TImode.
9778 ;; rD/rS = r5 is preferred, efficient form.
9779 (define_expand "movmemsi_4reg"
9780 [(parallel [(set (match_operand 0 "" "")
9781 (match_operand 1 "" ""))
9782 (use (match_operand 2 "" ""))
9783 (use (match_operand 3 "" ""))
9784 (clobber (reg:SI 5))
9785 (clobber (reg:SI 6))
9786 (clobber (reg:SI 7))
9787 (clobber (reg:SI 8))
9788 (clobber (match_scratch:SI 4 ""))])]
9793 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9794 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9795 (use (match_operand:SI 2 "immediate_operand" "i"))
9796 (use (match_operand:SI 3 "immediate_operand" "i"))
9797 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9798 (clobber (reg:SI 6))
9799 (clobber (reg:SI 7))
9800 (clobber (reg:SI 8))
9801 (clobber (match_scratch:SI 5 "=q"))]
9802 "TARGET_STRING && TARGET_POWER
9803 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9804 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9805 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9806 && REGNO (operands[4]) == 5"
9807 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9808 [(set_attr "type" "store_ux")
9809 (set_attr "length" "8")])
9812 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9813 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9814 (use (match_operand:SI 2 "immediate_operand" "i"))
9815 (use (match_operand:SI 3 "immediate_operand" "i"))
9816 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9817 (clobber (reg:SI 6))
9818 (clobber (reg:SI 7))
9819 (clobber (reg:SI 8))
9820 (clobber (match_scratch:SI 5 "=X"))]
9821 "TARGET_STRING && ! TARGET_POWER
9822 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9823 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9824 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9825 && REGNO (operands[4]) == 5"
9826 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9827 [(set_attr "type" "store_ux")
9828 (set_attr "length" "8")])
9830 ;; Move up to 8 bytes at a time.
9831 (define_expand "movmemsi_2reg"
9832 [(parallel [(set (match_operand 0 "" "")
9833 (match_operand 1 "" ""))
9834 (use (match_operand 2 "" ""))
9835 (use (match_operand 3 "" ""))
9836 (clobber (match_scratch:DI 4 ""))
9837 (clobber (match_scratch:SI 5 ""))])]
9838 "TARGET_STRING && ! TARGET_POWERPC64"
9842 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9843 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9844 (use (match_operand:SI 2 "immediate_operand" "i"))
9845 (use (match_operand:SI 3 "immediate_operand" "i"))
9846 (clobber (match_scratch:DI 4 "=&r"))
9847 (clobber (match_scratch:SI 5 "=q"))]
9848 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9849 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9850 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9851 [(set_attr "type" "store_ux")
9852 (set_attr "length" "8")])
9855 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9856 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9857 (use (match_operand:SI 2 "immediate_operand" "i"))
9858 (use (match_operand:SI 3 "immediate_operand" "i"))
9859 (clobber (match_scratch:DI 4 "=&r"))
9860 (clobber (match_scratch:SI 5 "=X"))]
9861 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9862 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9863 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9864 [(set_attr "type" "store_ux")
9865 (set_attr "length" "8")])
9867 ;; Move up to 4 bytes at a time.
9868 (define_expand "movmemsi_1reg"
9869 [(parallel [(set (match_operand 0 "" "")
9870 (match_operand 1 "" ""))
9871 (use (match_operand 2 "" ""))
9872 (use (match_operand 3 "" ""))
9873 (clobber (match_scratch:SI 4 ""))
9874 (clobber (match_scratch:SI 5 ""))])]
9879 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9880 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9881 (use (match_operand:SI 2 "immediate_operand" "i"))
9882 (use (match_operand:SI 3 "immediate_operand" "i"))
9883 (clobber (match_scratch:SI 4 "=&r"))
9884 (clobber (match_scratch:SI 5 "=q"))]
9885 "TARGET_STRING && TARGET_POWER
9886 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9887 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9888 [(set_attr "type" "store_ux")
9889 (set_attr "length" "8")])
9892 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9893 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9894 (use (match_operand:SI 2 "immediate_operand" "i"))
9895 (use (match_operand:SI 3 "immediate_operand" "i"))
9896 (clobber (match_scratch:SI 4 "=&r"))
9897 (clobber (match_scratch:SI 5 "=X"))]
9898 "TARGET_STRING && ! TARGET_POWER
9899 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9900 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9901 [(set_attr "type" "store_ux")
9902 (set_attr "length" "8")])
9904 ;; Define insns that do load or store with update. Some of these we can
9905 ;; get by using pre-decrement or pre-increment, but the hardware can also
9906 ;; do cases where the increment is not the size of the object.
9908 ;; In all these cases, we use operands 0 and 1 for the register being
9909 ;; incremented because those are the operands that local-alloc will
9910 ;; tie and these are the pair most likely to be tieable (and the ones
9911 ;; that will benefit the most).
9913 (define_insn "*movdi_update1"
9914 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9915 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9916 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9917 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9918 (plus:DI (match_dup 1) (match_dup 2)))]
9919 "TARGET_POWERPC64 && TARGET_UPDATE"
9923 [(set_attr "type" "load_ux,load_u")])
9925 (define_insn "movdi_<mode>_update"
9926 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9927 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9928 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9929 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9930 (plus:P (match_dup 1) (match_dup 2)))]
9931 "TARGET_POWERPC64 && TARGET_UPDATE"
9935 [(set_attr "type" "store_ux,store_u")])
9937 (define_insn "*movsi_update1"
9938 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9939 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9940 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9941 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9942 (plus:SI (match_dup 1) (match_dup 2)))]
9945 {lux|lwzux} %3,%0,%2
9946 {lu|lwzu} %3,%2(%0)"
9947 [(set_attr "type" "load_ux,load_u")])
9949 (define_insn "*movsi_update2"
9950 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9952 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9953 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9954 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9955 (plus:DI (match_dup 1) (match_dup 2)))]
9958 [(set_attr "type" "load_ext_ux")])
9960 (define_insn "movsi_update"
9961 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9962 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9963 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9964 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9965 (plus:SI (match_dup 1) (match_dup 2)))]
9968 {stux|stwux} %3,%0,%2
9969 {stu|stwu} %3,%2(%0)"
9970 [(set_attr "type" "store_ux,store_u")])
9972 (define_insn "*movhi_update1"
9973 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9974 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9975 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9976 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9977 (plus:SI (match_dup 1) (match_dup 2)))]
9982 [(set_attr "type" "load_ux,load_u")])
9984 (define_insn "*movhi_update2"
9985 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9987 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9988 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9989 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9990 (plus:SI (match_dup 1) (match_dup 2)))]
9995 [(set_attr "type" "load_ux,load_u")])
9997 (define_insn "*movhi_update3"
9998 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10000 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10001 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10002 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10003 (plus:SI (match_dup 1) (match_dup 2)))]
10008 [(set_attr "type" "load_ext_ux,load_ext_u")])
10010 (define_insn "*movhi_update4"
10011 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10012 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10013 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
10014 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10015 (plus:SI (match_dup 1) (match_dup 2)))]
10020 [(set_attr "type" "store_ux,store_u")])
10022 (define_insn "*movqi_update1"
10023 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
10024 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10025 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10026 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10027 (plus:SI (match_dup 1) (match_dup 2)))]
10032 [(set_attr "type" "load_ux,load_u")])
10034 (define_insn "*movqi_update2"
10035 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10037 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10038 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10039 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10040 (plus:SI (match_dup 1) (match_dup 2)))]
10045 [(set_attr "type" "load_ux,load_u")])
10047 (define_insn "*movqi_update3"
10048 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10049 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10050 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
10051 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10052 (plus:SI (match_dup 1) (match_dup 2)))]
10057 [(set_attr "type" "store_ux,store_u")])
10059 (define_insn "*movsf_update1"
10060 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
10061 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10062 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10063 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10064 (plus:SI (match_dup 1) (match_dup 2)))]
10065 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
10069 [(set_attr "type" "fpload_ux,fpload_u")])
10071 (define_insn "*movsf_update2"
10072 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10073 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10074 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10075 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10076 (plus:SI (match_dup 1) (match_dup 2)))]
10077 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
10081 [(set_attr "type" "fpstore_ux,fpstore_u")])
10083 (define_insn "*movsf_update3"
10084 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10085 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10086 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10087 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10088 (plus:SI (match_dup 1) (match_dup 2)))]
10089 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
10091 {lux|lwzux} %3,%0,%2
10092 {lu|lwzu} %3,%2(%0)"
10093 [(set_attr "type" "load_ux,load_u")])
10095 (define_insn "*movsf_update4"
10096 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10097 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10098 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10099 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10100 (plus:SI (match_dup 1) (match_dup 2)))]
10101 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
10103 {stux|stwux} %3,%0,%2
10104 {stu|stwu} %3,%2(%0)"
10105 [(set_attr "type" "store_ux,store_u")])
10107 (define_insn "*movdf_update1"
10108 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
10109 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10110 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10111 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10112 (plus:SI (match_dup 1) (match_dup 2)))]
10113 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
10117 [(set_attr "type" "fpload_ux,fpload_u")])
10119 (define_insn "*movdf_update2"
10120 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10121 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10122 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
10123 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10124 (plus:SI (match_dup 1) (match_dup 2)))]
10125 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
10129 [(set_attr "type" "fpstore_ux,fpstore_u")])
10131 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
10133 (define_insn "*lfq_power2"
10134 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
10135 (match_operand:V2DF 1 "memory_operand" ""))]
10137 && TARGET_HARD_FLOAT && TARGET_FPRS"
10141 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10142 (match_operand:DF 1 "memory_operand" ""))
10143 (set (match_operand:DF 2 "gpc_reg_operand" "")
10144 (match_operand:DF 3 "memory_operand" ""))]
10146 && TARGET_HARD_FLOAT && TARGET_FPRS
10147 && registers_ok_for_quad_peep (operands[0], operands[2])
10148 && mems_ok_for_quad_peep (operands[1], operands[3])"
10149 [(set (match_dup 0)
10151 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
10152 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
10154 (define_insn "*stfq_power2"
10155 [(set (match_operand:V2DF 0 "memory_operand" "")
10156 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
10158 && TARGET_HARD_FLOAT && TARGET_FPRS"
10159 "stfq%U0%X0 %1,%0")
10163 [(set (match_operand:DF 0 "memory_operand" "")
10164 (match_operand:DF 1 "gpc_reg_operand" ""))
10165 (set (match_operand:DF 2 "memory_operand" "")
10166 (match_operand:DF 3 "gpc_reg_operand" ""))]
10168 && TARGET_HARD_FLOAT && TARGET_FPRS
10169 && registers_ok_for_quad_peep (operands[1], operands[3])
10170 && mems_ok_for_quad_peep (operands[0], operands[2])"
10171 [(set (match_dup 0)
10173 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
10174 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
10176 ;; After inserting conditional returns we can sometimes have
10177 ;; unnecessary register moves. Unfortunately we cannot have a
10178 ;; modeless peephole here, because some single SImode sets have early
10179 ;; clobber outputs. Although those sets expand to multi-ppc-insn
10180 ;; sequences, using get_attr_length here will smash the operands
10181 ;; array. Neither is there an early_cobbler_p predicate.
10182 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
10184 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10185 (match_operand:DF 1 "any_operand" ""))
10186 (set (match_operand:DF 2 "gpc_reg_operand" "")
10188 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10189 && peep2_reg_dead_p (2, operands[0])"
10190 [(set (match_dup 2) (match_dup 1))])
10193 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10194 (match_operand:SF 1 "any_operand" ""))
10195 (set (match_operand:SF 2 "gpc_reg_operand" "")
10197 "peep2_reg_dead_p (2, operands[0])"
10198 [(set (match_dup 2) (match_dup 1))])
10203 ;; Mode attributes for different ABIs.
10204 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
10205 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
10206 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
10207 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
10209 (define_insn "tls_gd_aix<TLSmode:tls_abi_suffix>"
10210 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10211 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10212 (match_operand 4 "" "g")))
10213 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10214 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10216 (clobber (reg:SI LR_REGNO))]
10217 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10218 "addi %0,%1,%2@got@tlsgd\;bl %z3\;%."
10219 [(set_attr "type" "two")
10220 (set_attr "length" "12")])
10222 (define_insn "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
10223 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10224 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10225 (match_operand 4 "" "g")))
10226 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10227 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10229 (clobber (reg:SI LR_REGNO))]
10230 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10234 if (TARGET_SECURE_PLT && flag_pic == 2)
10235 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
10237 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
10240 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
10242 [(set_attr "type" "two")
10243 (set_attr "length" "8")])
10245 (define_insn "tls_ld_aix<TLSmode:tls_abi_suffix>"
10246 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10247 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10248 (match_operand 3 "" "g")))
10249 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10251 (clobber (reg:SI LR_REGNO))]
10252 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10253 "addi %0,%1,%&@got@tlsld\;bl %z2\;%."
10254 [(set_attr "length" "12")])
10256 (define_insn "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
10257 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10258 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10259 (match_operand 3 "" "g")))
10260 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10262 (clobber (reg:SI LR_REGNO))]
10263 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10267 if (TARGET_SECURE_PLT && flag_pic == 2)
10268 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
10270 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
10273 return "addi %0,%1,%&@got@tlsld\;bl %z2";
10275 [(set_attr "length" "8")])
10277 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
10278 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10279 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10280 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10281 UNSPEC_TLSDTPREL))]
10283 "addi %0,%1,%2@dtprel")
10285 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
10286 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10287 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10288 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10289 UNSPEC_TLSDTPRELHA))]
10291 "addis %0,%1,%2@dtprel@ha")
10293 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
10294 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10295 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10296 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10297 UNSPEC_TLSDTPRELLO))]
10299 "addi %0,%1,%2@dtprel@l")
10301 (define_insn "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
10302 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10303 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10304 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10305 UNSPEC_TLSGOTDTPREL))]
10307 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)")
10309 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
10310 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10311 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10312 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10315 "addi %0,%1,%2@tprel")
10317 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
10318 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10319 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10320 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10321 UNSPEC_TLSTPRELHA))]
10323 "addis %0,%1,%2@tprel@ha")
10325 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
10326 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10327 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10328 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10329 UNSPEC_TLSTPRELLO))]
10331 "addi %0,%1,%2@tprel@l")
10333 ;; "b" output constraint here and on tls_tls input to support linker tls
10334 ;; optimization. The linker may edit the instructions emitted by a
10335 ;; tls_got_tprel/tls_tls pair to addis,addi.
10336 (define_insn "tls_got_tprel_<TLSmode:tls_abi_suffix>"
10337 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10338 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10339 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10340 UNSPEC_TLSGOTTPREL))]
10342 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)")
10344 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
10345 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10346 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10347 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10350 "add %0,%1,%2@tls")
10353 ;; Next come insns related to the calling sequence.
10355 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
10356 ;; We move the back-chain and decrement the stack pointer.
10358 (define_expand "allocate_stack"
10359 [(set (match_operand 0 "gpc_reg_operand" "")
10360 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10362 (minus (reg 1) (match_dup 1)))]
10365 { rtx chain = gen_reg_rtx (Pmode);
10366 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
10369 emit_move_insn (chain, stack_bot);
10371 /* Check stack bounds if necessary. */
10372 if (crtl->limit_stack)
10375 available = expand_binop (Pmode, sub_optab,
10376 stack_pointer_rtx, stack_limit_rtx,
10377 NULL_RTX, 1, OPTAB_WIDEN);
10378 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10381 if (GET_CODE (operands[1]) != CONST_INT
10382 || INTVAL (operands[1]) < -32767
10383 || INTVAL (operands[1]) > 32768)
10385 neg_op0 = gen_reg_rtx (Pmode);
10387 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10389 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10392 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10395 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
10396 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
10400 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
10401 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
10402 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
10405 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10409 ;; These patterns say how to save and restore the stack pointer. We need not
10410 ;; save the stack pointer at function level since we are careful to
10411 ;; preserve the backchain. At block level, we have to restore the backchain
10412 ;; when we restore the stack pointer.
10414 ;; For nonlocal gotos, we must save both the stack pointer and its
10415 ;; backchain and restore both. Note that in the nonlocal case, the
10416 ;; save area is a memory location.
10418 (define_expand "save_stack_function"
10419 [(match_operand 0 "any_operand" "")
10420 (match_operand 1 "any_operand" "")]
10424 (define_expand "restore_stack_function"
10425 [(match_operand 0 "any_operand" "")
10426 (match_operand 1 "any_operand" "")]
10430 ;; Adjust stack pointer (op0) to a new value (op1).
10431 ;; First copy old stack backchain to new location, and ensure that the
10432 ;; scheduler won't reorder the sp assignment before the backchain write.
10433 (define_expand "restore_stack_block"
10434 [(set (match_dup 2) (match_dup 3))
10435 (set (match_dup 4) (match_dup 2))
10436 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
10437 (set (match_operand 0 "register_operand" "")
10438 (match_operand 1 "register_operand" ""))]
10442 operands[1] = force_reg (Pmode, operands[1]);
10443 operands[2] = gen_reg_rtx (Pmode);
10444 operands[3] = gen_frame_mem (Pmode, operands[0]);
10445 operands[4] = gen_frame_mem (Pmode, operands[1]);
10446 operands[5] = gen_frame_mem (BLKmode, operands[0]);
10449 (define_expand "save_stack_nonlocal"
10450 [(set (match_dup 3) (match_dup 4))
10451 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10452 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
10456 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10458 /* Copy the backchain to the first word, sp to the second. */
10459 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10460 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10461 operands[3] = gen_reg_rtx (Pmode);
10462 operands[4] = gen_frame_mem (Pmode, operands[1]);
10465 (define_expand "restore_stack_nonlocal"
10466 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10467 (set (match_dup 3) (match_dup 4))
10468 (set (match_dup 5) (match_dup 2))
10469 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
10470 (set (match_operand 0 "register_operand" "") (match_dup 3))]
10474 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10476 /* Restore the backchain from the first word, sp from the second. */
10477 operands[2] = gen_reg_rtx (Pmode);
10478 operands[3] = gen_reg_rtx (Pmode);
10479 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10480 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10481 operands[5] = gen_frame_mem (Pmode, operands[3]);
10482 operands[6] = gen_frame_mem (BLKmode, operands[0]);
10485 ;; TOC register handling.
10487 ;; Code to initialize the TOC register...
10489 (define_insn "load_toc_aix_si"
10490 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10491 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10492 (use (reg:SI 2))])]
10493 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10497 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10498 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10499 operands[2] = gen_rtx_REG (Pmode, 2);
10500 return \"{l|lwz} %0,%1(%2)\";
10502 [(set_attr "type" "load")])
10504 (define_insn "load_toc_aix_di"
10505 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10506 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10507 (use (reg:DI 2))])]
10508 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10512 #ifdef TARGET_RELOCATABLE
10513 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10514 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10516 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10519 strcat (buf, \"@toc\");
10520 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10521 operands[2] = gen_rtx_REG (Pmode, 2);
10522 return \"ld %0,%1(%2)\";
10524 [(set_attr "type" "load")])
10526 (define_insn "load_toc_v4_pic_si"
10527 [(set (reg:SI LR_REGNO)
10528 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10529 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10530 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10531 [(set_attr "type" "branch")
10532 (set_attr "length" "4")])
10534 (define_insn "load_toc_v4_PIC_1"
10535 [(set (reg:SI LR_REGNO)
10536 (match_operand:SI 0 "immediate_operand" "s"))
10537 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10538 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
10539 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10540 "bcl 20,31,%0\\n%0:"
10541 [(set_attr "type" "branch")
10542 (set_attr "length" "4")])
10544 (define_insn "load_toc_v4_PIC_1b"
10545 [(set (reg:SI LR_REGNO)
10546 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")]
10548 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10549 "bcl 20,31,$+8\\n\\t.long %0-$"
10550 [(set_attr "type" "branch")
10551 (set_attr "length" "8")])
10553 (define_insn "load_toc_v4_PIC_2"
10554 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10555 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10556 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10557 (match_operand:SI 3 "immediate_operand" "s")))))]
10558 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10559 "{l|lwz} %0,%2-%3(%1)"
10560 [(set_attr "type" "load")])
10562 (define_insn "load_toc_v4_PIC_3b"
10563 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10564 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10566 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10567 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10568 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10569 "{cau|addis} %0,%1,%2-%3@ha")
10571 (define_insn "load_toc_v4_PIC_3c"
10572 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10573 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10574 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10575 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10576 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10577 "{cal|addi} %0,%1,%2-%3@l")
10579 ;; If the TOC is shared over a translation unit, as happens with all
10580 ;; the kinds of PIC that we support, we need to restore the TOC
10581 ;; pointer only when jumping over units of translation.
10582 ;; On Darwin, we need to reload the picbase.
10584 (define_expand "builtin_setjmp_receiver"
10585 [(use (label_ref (match_operand 0 "" "")))]
10586 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10587 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10588 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10592 if (DEFAULT_ABI == ABI_DARWIN)
10594 const char *picbase = machopic_function_base_name ();
10595 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
10596 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10600 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10601 CODE_LABEL_NUMBER (operands[0]));
10602 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10604 emit_insn (gen_load_macho_picbase (tmplabrtx));
10605 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
10606 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10610 rs6000_emit_load_toc_table (FALSE);
10614 ;; Elf specific ways of loading addresses for non-PIC code.
10615 ;; The output of this could be r0, but we make a very strong
10616 ;; preference for a base register because it will usually
10617 ;; be needed there.
10618 (define_insn "elf_high"
10619 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10620 (high:SI (match_operand 1 "" "")))]
10621 "TARGET_ELF && ! TARGET_64BIT"
10622 "{liu|lis} %0,%1@ha")
10624 (define_insn "elf_low"
10625 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10626 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10627 (match_operand 2 "" "")))]
10628 "TARGET_ELF && ! TARGET_64BIT"
10630 {cal|la} %0,%2@l(%1)
10631 {ai|addic} %0,%1,%K2")
10633 ;; A function pointer under AIX is a pointer to a data area whose first word
10634 ;; contains the actual address of the function, whose second word contains a
10635 ;; pointer to its TOC, and whose third word contains a value to place in the
10636 ;; static chain register (r11). Note that if we load the static chain, our
10637 ;; "trampoline" need not have any executable code.
10639 (define_expand "call_indirect_aix32"
10640 [(set (match_dup 2)
10641 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10642 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10645 (mem:SI (plus:SI (match_dup 0)
10648 (mem:SI (plus:SI (match_dup 0)
10650 (parallel [(call (mem:SI (match_dup 2))
10651 (match_operand 1 "" ""))
10655 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10656 (clobber (reg:SI LR_REGNO))])]
10659 { operands[2] = gen_reg_rtx (SImode); }")
10661 (define_expand "call_indirect_aix64"
10662 [(set (match_dup 2)
10663 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10664 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10667 (mem:DI (plus:DI (match_dup 0)
10670 (mem:DI (plus:DI (match_dup 0)
10672 (parallel [(call (mem:SI (match_dup 2))
10673 (match_operand 1 "" ""))
10677 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10678 (clobber (reg:SI LR_REGNO))])]
10681 { operands[2] = gen_reg_rtx (DImode); }")
10683 (define_expand "call_value_indirect_aix32"
10684 [(set (match_dup 3)
10685 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10686 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10689 (mem:SI (plus:SI (match_dup 1)
10692 (mem:SI (plus:SI (match_dup 1)
10694 (parallel [(set (match_operand 0 "" "")
10695 (call (mem:SI (match_dup 3))
10696 (match_operand 2 "" "")))
10700 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10701 (clobber (reg:SI LR_REGNO))])]
10704 { operands[3] = gen_reg_rtx (SImode); }")
10706 (define_expand "call_value_indirect_aix64"
10707 [(set (match_dup 3)
10708 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10709 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10712 (mem:DI (plus:DI (match_dup 1)
10715 (mem:DI (plus:DI (match_dup 1)
10717 (parallel [(set (match_operand 0 "" "")
10718 (call (mem:SI (match_dup 3))
10719 (match_operand 2 "" "")))
10723 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10724 (clobber (reg:SI LR_REGNO))])]
10727 { operands[3] = gen_reg_rtx (DImode); }")
10729 ;; Now the definitions for the call and call_value insns
10730 (define_expand "call"
10731 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10732 (match_operand 1 "" ""))
10733 (use (match_operand 2 "" ""))
10734 (clobber (reg:SI LR_REGNO))])]
10739 if (MACHOPIC_INDIRECT)
10740 operands[0] = machopic_indirect_call_target (operands[0]);
10743 gcc_assert (GET_CODE (operands[0]) == MEM);
10744 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10746 operands[0] = XEXP (operands[0], 0);
10748 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10750 && GET_CODE (operands[0]) == SYMBOL_REF
10751 && !SYMBOL_REF_LOCAL_P (operands[0]))
10756 tmp = gen_rtvec (3,
10757 gen_rtx_CALL (VOIDmode,
10758 gen_rtx_MEM (SImode, operands[0]),
10760 gen_rtx_USE (VOIDmode, operands[2]),
10761 gen_rtx_CLOBBER (VOIDmode,
10762 gen_rtx_REG (Pmode, LR_REGNO)));
10763 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10764 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10768 if (GET_CODE (operands[0]) != SYMBOL_REF
10769 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10770 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10772 if (INTVAL (operands[2]) & CALL_LONG)
10773 operands[0] = rs6000_longcall_ref (operands[0]);
10775 switch (DEFAULT_ABI)
10779 operands[0] = force_reg (Pmode, operands[0]);
10783 /* AIX function pointers are really pointers to a three word
10785 emit_call_insn (TARGET_32BIT
10786 ? gen_call_indirect_aix32 (force_reg (SImode,
10789 : gen_call_indirect_aix64 (force_reg (DImode,
10795 gcc_unreachable ();
10800 (define_expand "call_value"
10801 [(parallel [(set (match_operand 0 "" "")
10802 (call (mem:SI (match_operand 1 "address_operand" ""))
10803 (match_operand 2 "" "")))
10804 (use (match_operand 3 "" ""))
10805 (clobber (reg:SI LR_REGNO))])]
10810 if (MACHOPIC_INDIRECT)
10811 operands[1] = machopic_indirect_call_target (operands[1]);
10814 gcc_assert (GET_CODE (operands[1]) == MEM);
10815 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10817 operands[1] = XEXP (operands[1], 0);
10819 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10821 && GET_CODE (operands[1]) == SYMBOL_REF
10822 && !SYMBOL_REF_LOCAL_P (operands[1]))
10827 tmp = gen_rtvec (3,
10828 gen_rtx_SET (VOIDmode,
10830 gen_rtx_CALL (VOIDmode,
10831 gen_rtx_MEM (SImode,
10834 gen_rtx_USE (VOIDmode, operands[3]),
10835 gen_rtx_CLOBBER (VOIDmode,
10836 gen_rtx_REG (Pmode, LR_REGNO)));
10837 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10838 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10842 if (GET_CODE (operands[1]) != SYMBOL_REF
10843 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10844 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10846 if (INTVAL (operands[3]) & CALL_LONG)
10847 operands[1] = rs6000_longcall_ref (operands[1]);
10849 switch (DEFAULT_ABI)
10853 operands[1] = force_reg (Pmode, operands[1]);
10857 /* AIX function pointers are really pointers to a three word
10859 emit_call_insn (TARGET_32BIT
10860 ? gen_call_value_indirect_aix32 (operands[0],
10864 : gen_call_value_indirect_aix64 (operands[0],
10871 gcc_unreachable ();
10876 ;; Call to function in current module. No TOC pointer reload needed.
10877 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10878 ;; either the function was not prototyped, or it was prototyped as a
10879 ;; variable argument function. It is > 0 if FP registers were passed
10880 ;; and < 0 if they were not.
10882 (define_insn "*call_local32"
10883 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10884 (match_operand 1 "" "g,g"))
10885 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10886 (clobber (reg:SI LR_REGNO))]
10887 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10890 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10891 output_asm_insn (\"crxor 6,6,6\", operands);
10893 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10894 output_asm_insn (\"creqv 6,6,6\", operands);
10896 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10898 [(set_attr "type" "branch")
10899 (set_attr "length" "4,8")])
10901 (define_insn "*call_local64"
10902 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10903 (match_operand 1 "" "g,g"))
10904 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10905 (clobber (reg:SI LR_REGNO))]
10906 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10909 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10910 output_asm_insn (\"crxor 6,6,6\", operands);
10912 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10913 output_asm_insn (\"creqv 6,6,6\", operands);
10915 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10917 [(set_attr "type" "branch")
10918 (set_attr "length" "4,8")])
10920 (define_insn "*call_value_local32"
10921 [(set (match_operand 0 "" "")
10922 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10923 (match_operand 2 "" "g,g")))
10924 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10925 (clobber (reg:SI LR_REGNO))]
10926 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10929 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10930 output_asm_insn (\"crxor 6,6,6\", operands);
10932 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10933 output_asm_insn (\"creqv 6,6,6\", operands);
10935 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10937 [(set_attr "type" "branch")
10938 (set_attr "length" "4,8")])
10941 (define_insn "*call_value_local64"
10942 [(set (match_operand 0 "" "")
10943 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10944 (match_operand 2 "" "g,g")))
10945 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10946 (clobber (reg:SI LR_REGNO))]
10947 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10950 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10951 output_asm_insn (\"crxor 6,6,6\", operands);
10953 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10954 output_asm_insn (\"creqv 6,6,6\", operands);
10956 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10958 [(set_attr "type" "branch")
10959 (set_attr "length" "4,8")])
10961 ;; Call to function which may be in another module. Restore the TOC
10962 ;; pointer (r2) after the call unless this is System V.
10963 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10964 ;; either the function was not prototyped, or it was prototyped as a
10965 ;; variable argument function. It is > 0 if FP registers were passed
10966 ;; and < 0 if they were not.
10968 (define_insn "*call_indirect_nonlocal_aix32"
10969 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
10970 (match_operand 1 "" "g,g"))
10974 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10975 (clobber (reg:SI LR_REGNO))]
10976 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10977 "b%T0l\;{l|lwz} 2,20(1)"
10978 [(set_attr "type" "jmpreg")
10979 (set_attr "length" "8")])
10981 (define_insn "*call_nonlocal_aix32"
10982 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10983 (match_operand 1 "" "g"))
10984 (use (match_operand:SI 2 "immediate_operand" "O"))
10985 (clobber (reg:SI LR_REGNO))]
10987 && DEFAULT_ABI == ABI_AIX
10988 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10990 [(set_attr "type" "branch")
10991 (set_attr "length" "8")])
10993 (define_insn "*call_indirect_nonlocal_aix64"
10994 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
10995 (match_operand 1 "" "g,g"))
10999 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11000 (clobber (reg:SI LR_REGNO))]
11001 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11002 "b%T0l\;ld 2,40(1)"
11003 [(set_attr "type" "jmpreg")
11004 (set_attr "length" "8")])
11006 (define_insn "*call_nonlocal_aix64"
11007 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11008 (match_operand 1 "" "g"))
11009 (use (match_operand:SI 2 "immediate_operand" "O"))
11010 (clobber (reg:SI LR_REGNO))]
11012 && DEFAULT_ABI == ABI_AIX
11013 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11015 [(set_attr "type" "branch")
11016 (set_attr "length" "8")])
11018 (define_insn "*call_value_indirect_nonlocal_aix32"
11019 [(set (match_operand 0 "" "")
11020 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
11021 (match_operand 2 "" "g,g")))
11025 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11026 (clobber (reg:SI LR_REGNO))]
11027 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11028 "b%T1l\;{l|lwz} 2,20(1)"
11029 [(set_attr "type" "jmpreg")
11030 (set_attr "length" "8")])
11032 (define_insn "*call_value_nonlocal_aix32"
11033 [(set (match_operand 0 "" "")
11034 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11035 (match_operand 2 "" "g")))
11036 (use (match_operand:SI 3 "immediate_operand" "O"))
11037 (clobber (reg:SI LR_REGNO))]
11039 && DEFAULT_ABI == ABI_AIX
11040 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11042 [(set_attr "type" "branch")
11043 (set_attr "length" "8")])
11045 (define_insn "*call_value_indirect_nonlocal_aix64"
11046 [(set (match_operand 0 "" "")
11047 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
11048 (match_operand 2 "" "g,g")))
11052 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11053 (clobber (reg:SI LR_REGNO))]
11054 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11055 "b%T1l\;ld 2,40(1)"
11056 [(set_attr "type" "jmpreg")
11057 (set_attr "length" "8")])
11059 (define_insn "*call_value_nonlocal_aix64"
11060 [(set (match_operand 0 "" "")
11061 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11062 (match_operand 2 "" "g")))
11063 (use (match_operand:SI 3 "immediate_operand" "O"))
11064 (clobber (reg:SI LR_REGNO))]
11066 && DEFAULT_ABI == ABI_AIX
11067 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11069 [(set_attr "type" "branch")
11070 (set_attr "length" "8")])
11072 ;; A function pointer under System V is just a normal pointer
11073 ;; operands[0] is the function pointer
11074 ;; operands[1] is the stack size to clean up
11075 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
11076 ;; which indicates how to set cr1
11078 (define_insn "*call_indirect_nonlocal_sysv<mode>"
11079 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
11080 (match_operand 1 "" "g,g,g,g"))
11081 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
11082 (clobber (reg:SI LR_REGNO))]
11083 "DEFAULT_ABI == ABI_V4
11084 || DEFAULT_ABI == ABI_DARWIN"
11086 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11087 output_asm_insn ("crxor 6,6,6", operands);
11089 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11090 output_asm_insn ("creqv 6,6,6", operands);
11094 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11095 (set_attr "length" "4,4,8,8")])
11097 (define_insn "*call_nonlocal_sysv<mode>"
11098 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11099 (match_operand 1 "" "g,g"))
11100 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11101 (clobber (reg:SI LR_REGNO))]
11102 "(DEFAULT_ABI == ABI_DARWIN
11103 || (DEFAULT_ABI == ABI_V4
11104 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
11106 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11107 output_asm_insn ("crxor 6,6,6", operands);
11109 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11110 output_asm_insn ("creqv 6,6,6", operands);
11113 return output_call(insn, operands, 0, 2);
11115 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11117 if (TARGET_SECURE_PLT && flag_pic == 2)
11118 /* The magic 32768 offset here and in the other sysv call insns
11119 corresponds to the offset of r30 in .got2, as given by LCTOC1.
11120 See sysv4.h:toc_section. */
11121 return "bl %z0+32768@plt";
11123 return "bl %z0@plt";
11129 [(set_attr "type" "branch,branch")
11130 (set_attr "length" "4,8")])
11132 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
11133 [(set (match_operand 0 "" "")
11134 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
11135 (match_operand 2 "" "g,g,g,g")))
11136 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
11137 (clobber (reg:SI LR_REGNO))]
11138 "DEFAULT_ABI == ABI_V4
11139 || DEFAULT_ABI == ABI_DARWIN"
11141 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11142 output_asm_insn ("crxor 6,6,6", operands);
11144 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11145 output_asm_insn ("creqv 6,6,6", operands);
11149 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11150 (set_attr "length" "4,4,8,8")])
11152 (define_insn "*call_value_nonlocal_sysv<mode>"
11153 [(set (match_operand 0 "" "")
11154 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11155 (match_operand 2 "" "g,g")))
11156 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11157 (clobber (reg:SI LR_REGNO))]
11158 "(DEFAULT_ABI == ABI_DARWIN
11159 || (DEFAULT_ABI == ABI_V4
11160 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
11162 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11163 output_asm_insn ("crxor 6,6,6", operands);
11165 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11166 output_asm_insn ("creqv 6,6,6", operands);
11169 return output_call(insn, operands, 1, 3);
11171 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11173 if (TARGET_SECURE_PLT && flag_pic == 2)
11174 return "bl %z1+32768@plt";
11176 return "bl %z1@plt";
11182 [(set_attr "type" "branch,branch")
11183 (set_attr "length" "4,8")])
11185 ;; Call subroutine returning any type.
11186 (define_expand "untyped_call"
11187 [(parallel [(call (match_operand 0 "" "")
11189 (match_operand 1 "" "")
11190 (match_operand 2 "" "")])]
11196 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
11198 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11200 rtx set = XVECEXP (operands[2], 0, i);
11201 emit_move_insn (SET_DEST (set), SET_SRC (set));
11204 /* The optimizer does not know that the call sets the function value
11205 registers we stored in the result block. We avoid problems by
11206 claiming that all hard registers are used and clobbered at this
11208 emit_insn (gen_blockage ());
11213 ;; sibling call patterns
11214 (define_expand "sibcall"
11215 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11216 (match_operand 1 "" ""))
11217 (use (match_operand 2 "" ""))
11218 (use (reg:SI LR_REGNO))
11224 if (MACHOPIC_INDIRECT)
11225 operands[0] = machopic_indirect_call_target (operands[0]);
11228 gcc_assert (GET_CODE (operands[0]) == MEM);
11229 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11231 operands[0] = XEXP (operands[0], 0);
11234 ;; this and similar patterns must be marked as using LR, otherwise
11235 ;; dataflow will try to delete the store into it. This is true
11236 ;; even when the actual reg to jump to is in CTR, when LR was
11237 ;; saved and restored around the PIC-setting BCL.
11238 (define_insn "*sibcall_local32"
11239 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11240 (match_operand 1 "" "g,g"))
11241 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11242 (use (reg:SI LR_REGNO))
11244 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11247 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11248 output_asm_insn (\"crxor 6,6,6\", operands);
11250 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11251 output_asm_insn (\"creqv 6,6,6\", operands);
11253 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11255 [(set_attr "type" "branch")
11256 (set_attr "length" "4,8")])
11258 (define_insn "*sibcall_local64"
11259 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11260 (match_operand 1 "" "g,g"))
11261 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11262 (use (reg:SI LR_REGNO))
11264 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11267 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11268 output_asm_insn (\"crxor 6,6,6\", operands);
11270 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11271 output_asm_insn (\"creqv 6,6,6\", operands);
11273 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11275 [(set_attr "type" "branch")
11276 (set_attr "length" "4,8")])
11278 (define_insn "*sibcall_value_local32"
11279 [(set (match_operand 0 "" "")
11280 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11281 (match_operand 2 "" "g,g")))
11282 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11283 (use (reg:SI LR_REGNO))
11285 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11288 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11289 output_asm_insn (\"crxor 6,6,6\", operands);
11291 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11292 output_asm_insn (\"creqv 6,6,6\", operands);
11294 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11296 [(set_attr "type" "branch")
11297 (set_attr "length" "4,8")])
11300 (define_insn "*sibcall_value_local64"
11301 [(set (match_operand 0 "" "")
11302 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11303 (match_operand 2 "" "g,g")))
11304 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11305 (use (reg:SI LR_REGNO))
11307 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11310 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11311 output_asm_insn (\"crxor 6,6,6\", operands);
11313 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11314 output_asm_insn (\"creqv 6,6,6\", operands);
11316 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11318 [(set_attr "type" "branch")
11319 (set_attr "length" "4,8")])
11321 (define_insn "*sibcall_nonlocal_aix32"
11322 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11323 (match_operand 1 "" "g"))
11324 (use (match_operand:SI 2 "immediate_operand" "O"))
11325 (use (reg:SI LR_REGNO))
11328 && DEFAULT_ABI == ABI_AIX
11329 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11331 [(set_attr "type" "branch")
11332 (set_attr "length" "4")])
11334 (define_insn "*sibcall_nonlocal_aix64"
11335 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11336 (match_operand 1 "" "g"))
11337 (use (match_operand:SI 2 "immediate_operand" "O"))
11338 (use (reg:SI LR_REGNO))
11341 && DEFAULT_ABI == ABI_AIX
11342 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11344 [(set_attr "type" "branch")
11345 (set_attr "length" "4")])
11347 (define_insn "*sibcall_value_nonlocal_aix32"
11348 [(set (match_operand 0 "" "")
11349 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11350 (match_operand 2 "" "g")))
11351 (use (match_operand:SI 3 "immediate_operand" "O"))
11352 (use (reg:SI LR_REGNO))
11355 && DEFAULT_ABI == ABI_AIX
11356 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11358 [(set_attr "type" "branch")
11359 (set_attr "length" "4")])
11361 (define_insn "*sibcall_value_nonlocal_aix64"
11362 [(set (match_operand 0 "" "")
11363 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11364 (match_operand 2 "" "g")))
11365 (use (match_operand:SI 3 "immediate_operand" "O"))
11366 (use (reg:SI LR_REGNO))
11369 && DEFAULT_ABI == ABI_AIX
11370 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11372 [(set_attr "type" "branch")
11373 (set_attr "length" "4")])
11375 (define_insn "*sibcall_nonlocal_sysv<mode>"
11376 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11377 (match_operand 1 "" ""))
11378 (use (match_operand 2 "immediate_operand" "O,n"))
11379 (use (reg:SI LR_REGNO))
11381 "(DEFAULT_ABI == ABI_DARWIN
11382 || DEFAULT_ABI == ABI_V4)
11383 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11386 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11387 output_asm_insn (\"crxor 6,6,6\", operands);
11389 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11390 output_asm_insn (\"creqv 6,6,6\", operands);
11392 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11394 if (TARGET_SECURE_PLT && flag_pic == 2)
11395 return \"b %z0+32768@plt\";
11397 return \"b %z0@plt\";
11402 [(set_attr "type" "branch,branch")
11403 (set_attr "length" "4,8")])
11405 (define_expand "sibcall_value"
11406 [(parallel [(set (match_operand 0 "register_operand" "")
11407 (call (mem:SI (match_operand 1 "address_operand" ""))
11408 (match_operand 2 "" "")))
11409 (use (match_operand 3 "" ""))
11410 (use (reg:SI LR_REGNO))
11416 if (MACHOPIC_INDIRECT)
11417 operands[1] = machopic_indirect_call_target (operands[1]);
11420 gcc_assert (GET_CODE (operands[1]) == MEM);
11421 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11423 operands[1] = XEXP (operands[1], 0);
11426 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
11427 [(set (match_operand 0 "" "")
11428 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11429 (match_operand 2 "" "")))
11430 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11431 (use (reg:SI LR_REGNO))
11433 "(DEFAULT_ABI == ABI_DARWIN
11434 || DEFAULT_ABI == ABI_V4)
11435 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11438 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11439 output_asm_insn (\"crxor 6,6,6\", operands);
11441 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11442 output_asm_insn (\"creqv 6,6,6\", operands);
11444 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11446 if (TARGET_SECURE_PLT && flag_pic == 2)
11447 return \"b %z1+32768@plt\";
11449 return \"b %z1@plt\";
11454 [(set_attr "type" "branch,branch")
11455 (set_attr "length" "4,8")])
11457 (define_expand "sibcall_epilogue"
11458 [(use (const_int 0))]
11459 "TARGET_SCHED_PROLOG"
11462 rs6000_emit_epilogue (TRUE);
11466 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11467 ;; all of memory. This blocks insns from being moved across this point.
11469 (define_insn "blockage"
11470 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
11474 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
11475 ;; signed & unsigned, and one type of branch.
11477 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11478 ;; insns, and branches. We store the operands of compares until we see
11480 (define_expand "cmp<mode>"
11482 (compare (match_operand:GPR 0 "gpc_reg_operand" "")
11483 (match_operand:GPR 1 "reg_or_short_operand" "")))]
11487 /* Take care of the possibility that operands[1] might be negative but
11488 this might be a logical operation. That insn doesn't exist. */
11489 if (GET_CODE (operands[1]) == CONST_INT
11490 && INTVAL (operands[1]) < 0)
11491 operands[1] = force_reg (<MODE>mode, operands[1]);
11493 rs6000_compare_op0 = operands[0];
11494 rs6000_compare_op1 = operands[1];
11495 rs6000_compare_fp_p = 0;
11499 (define_expand "cmp<mode>"
11500 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
11501 (match_operand:FP 1 "gpc_reg_operand" "")))]
11505 rs6000_compare_op0 = operands[0];
11506 rs6000_compare_op1 = operands[1];
11507 rs6000_compare_fp_p = 1;
11511 (define_expand "beq"
11512 [(use (match_operand 0 "" ""))]
11514 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
11516 (define_expand "bne"
11517 [(use (match_operand 0 "" ""))]
11519 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
11521 (define_expand "bge"
11522 [(use (match_operand 0 "" ""))]
11524 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
11526 (define_expand "bgt"
11527 [(use (match_operand 0 "" ""))]
11529 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
11531 (define_expand "ble"
11532 [(use (match_operand 0 "" ""))]
11534 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
11536 (define_expand "blt"
11537 [(use (match_operand 0 "" ""))]
11539 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
11541 (define_expand "bgeu"
11542 [(use (match_operand 0 "" ""))]
11544 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
11546 (define_expand "bgtu"
11547 [(use (match_operand 0 "" ""))]
11549 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
11551 (define_expand "bleu"
11552 [(use (match_operand 0 "" ""))]
11554 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
11556 (define_expand "bltu"
11557 [(use (match_operand 0 "" ""))]
11559 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
11561 (define_expand "bunordered"
11562 [(use (match_operand 0 "" ""))]
11563 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11564 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
11566 (define_expand "bordered"
11567 [(use (match_operand 0 "" ""))]
11568 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11569 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
11571 (define_expand "buneq"
11572 [(use (match_operand 0 "" ""))]
11573 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11574 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
11576 (define_expand "bunge"
11577 [(use (match_operand 0 "" ""))]
11578 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11579 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
11581 (define_expand "bungt"
11582 [(use (match_operand 0 "" ""))]
11583 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11584 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
11586 (define_expand "bunle"
11587 [(use (match_operand 0 "" ""))]
11588 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11589 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
11591 (define_expand "bunlt"
11592 [(use (match_operand 0 "" ""))]
11593 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11594 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
11596 (define_expand "bltgt"
11597 [(use (match_operand 0 "" ""))]
11599 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
11601 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11602 ;; For SEQ, likewise, except that comparisons with zero should be done
11603 ;; with an scc insns. However, due to the order that combine see the
11604 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11605 ;; the cases we don't want to handle.
11606 (define_expand "seq"
11607 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11609 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
11611 (define_expand "sne"
11612 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11616 if (! rs6000_compare_fp_p)
11619 rs6000_emit_sCOND (NE, operands[0]);
11623 ;; A >= 0 is best done the portable way for A an integer.
11624 (define_expand "sge"
11625 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11629 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11632 rs6000_emit_sCOND (GE, operands[0]);
11636 ;; A > 0 is best done using the portable sequence, so fail in that case.
11637 (define_expand "sgt"
11638 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11642 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11645 rs6000_emit_sCOND (GT, operands[0]);
11649 ;; A <= 0 is best done the portable way for A an integer.
11650 (define_expand "sle"
11651 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11655 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11658 rs6000_emit_sCOND (LE, operands[0]);
11662 ;; A < 0 is best done in the portable way for A an integer.
11663 (define_expand "slt"
11664 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11668 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11671 rs6000_emit_sCOND (LT, operands[0]);
11675 (define_expand "sgeu"
11676 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11678 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11680 (define_expand "sgtu"
11681 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11683 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
11685 (define_expand "sleu"
11686 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11688 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11690 (define_expand "sltu"
11691 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11693 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
11695 (define_expand "sunordered"
11696 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11697 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11698 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
11700 (define_expand "sordered"
11701 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11702 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11703 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11705 (define_expand "suneq"
11706 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11707 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11708 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11710 (define_expand "sunge"
11711 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11712 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11713 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11715 (define_expand "sungt"
11716 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11717 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11718 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11720 (define_expand "sunle"
11721 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11722 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11723 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11725 (define_expand "sunlt"
11726 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11727 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11728 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11730 (define_expand "sltgt"
11731 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11733 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11735 (define_expand "stack_protect_set"
11736 [(match_operand 0 "memory_operand" "")
11737 (match_operand 1 "memory_operand" "")]
11740 #ifdef TARGET_THREAD_SSP_OFFSET
11741 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11742 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11743 operands[1] = gen_rtx_MEM (Pmode, addr);
11746 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11748 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11752 (define_insn "stack_protect_setsi"
11753 [(set (match_operand:SI 0 "memory_operand" "=m")
11754 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11755 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11757 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
11758 [(set_attr "type" "three")
11759 (set_attr "length" "12")])
11761 (define_insn "stack_protect_setdi"
11762 [(set (match_operand:DI 0 "memory_operand" "=m")
11763 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11764 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11766 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
11767 [(set_attr "type" "three")
11768 (set_attr "length" "12")])
11770 (define_expand "stack_protect_test"
11771 [(match_operand 0 "memory_operand" "")
11772 (match_operand 1 "memory_operand" "")
11773 (match_operand 2 "" "")]
11776 #ifdef TARGET_THREAD_SSP_OFFSET
11777 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11778 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11779 operands[1] = gen_rtx_MEM (Pmode, addr);
11781 rs6000_compare_op0 = operands[0];
11782 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
11784 rs6000_compare_fp_p = 0;
11785 emit_jump_insn (gen_beq (operands[2]));
11789 (define_insn "stack_protect_testsi"
11790 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11791 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11792 (match_operand:SI 2 "memory_operand" "m,m")]
11794 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11795 (clobber (match_scratch:SI 3 "=&r,&r"))]
11798 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11799 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11800 [(set_attr "length" "16,20")])
11802 (define_insn "stack_protect_testdi"
11803 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11804 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
11805 (match_operand:DI 2 "memory_operand" "m,m")]
11807 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11808 (clobber (match_scratch:DI 3 "=&r,&r"))]
11811 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11812 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11813 [(set_attr "length" "16,20")])
11816 ;; Here are the actual compare insns.
11817 (define_insn "*cmp<mode>_internal1"
11818 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11819 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11820 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
11822 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
11823 [(set_attr "type" "cmp")])
11825 ;; If we are comparing a register for equality with a large constant,
11826 ;; we can do this with an XOR followed by a compare. But this is profitable
11827 ;; only if the large constant is only used for the comparison (and in this
11828 ;; case we already have a register to reuse as scratch).
11830 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11831 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
11834 [(set (match_operand:SI 0 "register_operand")
11835 (match_operand:SI 1 "logical_const_operand" ""))
11836 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
11838 (match_operand:SI 2 "logical_const_operand" "")]))
11839 (set (match_operand:CC 4 "cc_reg_operand" "")
11840 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
11843 (if_then_else (match_operator 6 "equality_operator"
11844 [(match_dup 4) (const_int 0)])
11845 (match_operand 7 "" "")
11846 (match_operand 8 "" "")))]
11847 "peep2_reg_dead_p (3, operands[0])
11848 && peep2_reg_dead_p (4, operands[4])"
11849 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
11850 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11851 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11854 /* Get the constant we are comparing against, and see what it looks like
11855 when sign-extended from 16 to 32 bits. Then see what constant we could
11856 XOR with SEXTC to get the sign-extended value. */
11857 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
11859 operands[1], operands[2]);
11860 HOST_WIDE_INT c = INTVAL (cnst);
11861 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11862 HOST_WIDE_INT xorv = c ^ sextc;
11864 operands[9] = GEN_INT (xorv);
11865 operands[10] = GEN_INT (sextc);
11868 (define_insn "*cmpsi_internal2"
11869 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11870 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11871 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11873 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
11874 [(set_attr "type" "cmp")])
11876 (define_insn "*cmpdi_internal2"
11877 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11878 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11879 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11881 "cmpld%I2 %0,%1,%b2"
11882 [(set_attr "type" "cmp")])
11884 ;; The following two insns don't exist as single insns, but if we provide
11885 ;; them, we can swap an add and compare, which will enable us to overlap more
11886 ;; of the required delay between a compare and branch. We generate code for
11887 ;; them by splitting.
11890 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11891 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11892 (match_operand:SI 2 "short_cint_operand" "i")))
11893 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11894 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11897 [(set_attr "length" "8")])
11900 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11901 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11902 (match_operand:SI 2 "u_short_cint_operand" "i")))
11903 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11904 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11907 [(set_attr "length" "8")])
11910 [(set (match_operand:CC 3 "cc_reg_operand" "")
11911 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11912 (match_operand:SI 2 "short_cint_operand" "")))
11913 (set (match_operand:SI 0 "gpc_reg_operand" "")
11914 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11916 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11917 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11920 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11921 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11922 (match_operand:SI 2 "u_short_cint_operand" "")))
11923 (set (match_operand:SI 0 "gpc_reg_operand" "")
11924 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11926 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11927 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11929 (define_insn "*cmpsf_internal1"
11930 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11931 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11932 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11933 "TARGET_HARD_FLOAT && TARGET_FPRS"
11935 [(set_attr "type" "fpcompare")])
11937 (define_insn "*cmpdf_internal1"
11938 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11939 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11940 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11941 "TARGET_HARD_FLOAT && TARGET_FPRS"
11943 [(set_attr "type" "fpcompare")])
11945 ;; Only need to compare second words if first words equal
11946 (define_insn "*cmptf_internal1"
11947 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11948 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11949 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11950 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
11951 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11952 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11953 [(set_attr "type" "fpcompare")
11954 (set_attr "length" "12")])
11956 (define_insn_and_split "*cmptf_internal2"
11957 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11958 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11959 (match_operand:TF 2 "gpc_reg_operand" "f")))
11960 (clobber (match_scratch:DF 3 "=f"))
11961 (clobber (match_scratch:DF 4 "=f"))
11962 (clobber (match_scratch:DF 5 "=f"))
11963 (clobber (match_scratch:DF 6 "=f"))
11964 (clobber (match_scratch:DF 7 "=f"))
11965 (clobber (match_scratch:DF 8 "=f"))
11966 (clobber (match_scratch:DF 9 "=f"))
11967 (clobber (match_scratch:DF 10 "=f"))]
11968 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
11969 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11971 "&& reload_completed"
11972 [(set (match_dup 3) (match_dup 13))
11973 (set (match_dup 4) (match_dup 14))
11974 (set (match_dup 9) (abs:DF (match_dup 5)))
11975 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11976 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11977 (label_ref (match_dup 11))
11979 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11980 (set (pc) (label_ref (match_dup 12)))
11982 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11983 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11984 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11985 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
11988 REAL_VALUE_TYPE rv;
11989 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
11990 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
11992 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11993 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11994 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11995 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11996 operands[11] = gen_label_rtx ();
11997 operands[12] = gen_label_rtx ();
11999 operands[13] = force_const_mem (DFmode,
12000 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
12001 operands[14] = force_const_mem (DFmode,
12002 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
12006 operands[13] = gen_const_mem (DFmode,
12007 create_TOC_reference (XEXP (operands[13], 0)));
12008 operands[14] = gen_const_mem (DFmode,
12009 create_TOC_reference (XEXP (operands[14], 0)));
12010 set_mem_alias_set (operands[13], get_TOC_alias_set ());
12011 set_mem_alias_set (operands[14], get_TOC_alias_set ());
12015 ;; Now we have the scc insns. We can do some combinations because of the
12016 ;; way the machine works.
12018 ;; Note that this is probably faster if we can put an insn between the
12019 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
12020 ;; cases the insns below which don't use an intermediate CR field will
12021 ;; be used instead.
12023 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12024 (match_operator:SI 1 "scc_comparison_operator"
12025 [(match_operand 2 "cc_reg_operand" "y")
12028 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12029 [(set (attr "type")
12030 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12031 (const_string "mfcrf")
12033 (const_string "mfcr")))
12034 (set_attr "length" "8")])
12036 ;; Same as above, but get the GT bit.
12037 (define_insn "move_from_CR_gt_bit"
12038 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12039 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
12041 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
12042 [(set_attr "type" "mfcr")
12043 (set_attr "length" "8")])
12045 ;; Same as above, but get the OV/ORDERED bit.
12046 (define_insn "move_from_CR_ov_bit"
12047 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12048 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
12050 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
12051 [(set_attr "type" "mfcr")
12052 (set_attr "length" "8")])
12055 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12056 (match_operator:DI 1 "scc_comparison_operator"
12057 [(match_operand 2 "cc_reg_operand" "y")
12060 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12061 [(set (attr "type")
12062 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12063 (const_string "mfcrf")
12065 (const_string "mfcr")))
12066 (set_attr "length" "8")])
12069 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12070 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12071 [(match_operand 2 "cc_reg_operand" "y,y")
12074 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
12075 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12078 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
12080 [(set_attr "type" "delayed_compare")
12081 (set_attr "length" "8,16")])
12084 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12085 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12086 [(match_operand 2 "cc_reg_operand" "")
12089 (set (match_operand:SI 3 "gpc_reg_operand" "")
12090 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12091 "TARGET_32BIT && reload_completed"
12092 [(set (match_dup 3)
12093 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12095 (compare:CC (match_dup 3)
12100 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12101 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12102 [(match_operand 2 "cc_reg_operand" "y")
12104 (match_operand:SI 3 "const_int_operand" "n")))]
12108 int is_bit = ccr_bit (operands[1], 1);
12109 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12112 if (is_bit >= put_bit)
12113 count = is_bit - put_bit;
12115 count = 32 - (put_bit - is_bit);
12117 operands[4] = GEN_INT (count);
12118 operands[5] = GEN_INT (put_bit);
12120 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
12122 [(set (attr "type")
12123 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12124 (const_string "mfcrf")
12126 (const_string "mfcr")))
12127 (set_attr "length" "8")])
12130 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12132 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12133 [(match_operand 2 "cc_reg_operand" "y,y")
12135 (match_operand:SI 3 "const_int_operand" "n,n"))
12137 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
12138 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12143 int is_bit = ccr_bit (operands[1], 1);
12144 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12147 /* Force split for non-cc0 compare. */
12148 if (which_alternative == 1)
12151 if (is_bit >= put_bit)
12152 count = is_bit - put_bit;
12154 count = 32 - (put_bit - is_bit);
12156 operands[5] = GEN_INT (count);
12157 operands[6] = GEN_INT (put_bit);
12159 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
12161 [(set_attr "type" "delayed_compare")
12162 (set_attr "length" "8,16")])
12165 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12167 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12168 [(match_operand 2 "cc_reg_operand" "")
12170 (match_operand:SI 3 "const_int_operand" ""))
12172 (set (match_operand:SI 4 "gpc_reg_operand" "")
12173 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12176 [(set (match_dup 4)
12177 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12180 (compare:CC (match_dup 4)
12184 ;; There is a 3 cycle delay between consecutive mfcr instructions
12185 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
12188 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12189 (match_operator:SI 1 "scc_comparison_operator"
12190 [(match_operand 2 "cc_reg_operand" "y")
12192 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
12193 (match_operator:SI 4 "scc_comparison_operator"
12194 [(match_operand 5 "cc_reg_operand" "y")
12196 "REGNO (operands[2]) != REGNO (operands[5])"
12197 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
12198 [(set_attr "type" "mfcr")
12199 (set_attr "length" "12")])
12202 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12203 (match_operator:DI 1 "scc_comparison_operator"
12204 [(match_operand 2 "cc_reg_operand" "y")
12206 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12207 (match_operator:DI 4 "scc_comparison_operator"
12208 [(match_operand 5 "cc_reg_operand" "y")
12210 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
12211 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
12212 [(set_attr "type" "mfcr")
12213 (set_attr "length" "12")])
12215 ;; There are some scc insns that can be done directly, without a compare.
12216 ;; These are faster because they don't involve the communications between
12217 ;; the FXU and branch units. In fact, we will be replacing all of the
12218 ;; integer scc insns here or in the portable methods in emit_store_flag.
12220 ;; Also support (neg (scc ..)) since that construct is used to replace
12221 ;; branches, (plus (scc ..) ..) since that construct is common and
12222 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12223 ;; cases where it is no more expensive than (neg (scc ..)).
12225 ;; Have reload force a constant into a register for the simple insns that
12226 ;; otherwise won't accept constants. We do this because it is faster than
12227 ;; the cmp/mfcr sequence we would otherwise generate.
12229 (define_mode_attr scc_eq_op2 [(SI "rKLI")
12232 (define_insn_and_split "*eq<mode>"
12233 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12234 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
12235 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
12239 [(set (match_dup 0)
12240 (clz:GPR (match_dup 3)))
12242 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
12244 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12246 /* Use output operand as intermediate. */
12247 operands[3] = operands[0];
12249 if (logical_operand (operands[2], <MODE>mode))
12250 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12251 gen_rtx_XOR (<MODE>mode,
12252 operands[1], operands[2])));
12254 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12255 gen_rtx_PLUS (<MODE>mode, operands[1],
12256 negate_rtx (<MODE>mode,
12260 operands[3] = operands[1];
12262 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12265 (define_insn_and_split "*eq<mode>_compare"
12266 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12268 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12269 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
12271 (set (match_operand:P 0 "gpc_reg_operand" "=r")
12272 (eq:P (match_dup 1) (match_dup 2)))]
12273 "!TARGET_POWER && optimize_size"
12275 "!TARGET_POWER && optimize_size"
12276 [(set (match_dup 0)
12277 (clz:P (match_dup 4)))
12278 (parallel [(set (match_dup 3)
12279 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
12282 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
12284 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12286 /* Use output operand as intermediate. */
12287 operands[4] = operands[0];
12289 if (logical_operand (operands[2], <MODE>mode))
12290 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12291 gen_rtx_XOR (<MODE>mode,
12292 operands[1], operands[2])));
12294 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12295 gen_rtx_PLUS (<MODE>mode, operands[1],
12296 negate_rtx (<MODE>mode,
12300 operands[4] = operands[1];
12302 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12305 (define_insn "*eqsi_power"
12306 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
12307 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12308 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
12309 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
12312 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12313 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
12314 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12315 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12316 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
12317 [(set_attr "type" "three,two,three,three,three")
12318 (set_attr "length" "12,8,12,12,12")])
12320 ;; We have insns of the form shown by the first define_insn below. If
12321 ;; there is something inside the comparison operation, we must split it.
12323 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12324 (plus:SI (match_operator 1 "comparison_operator"
12325 [(match_operand:SI 2 "" "")
12326 (match_operand:SI 3
12327 "reg_or_cint_operand" "")])
12328 (match_operand:SI 4 "gpc_reg_operand" "")))
12329 (clobber (match_operand:SI 5 "register_operand" ""))]
12330 "! gpc_reg_operand (operands[2], SImode)"
12331 [(set (match_dup 5) (match_dup 2))
12332 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
12335 (define_insn "*plus_eqsi"
12336 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
12337 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12338 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
12339 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
12342 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12343 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
12344 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12345 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12346 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12347 [(set_attr "type" "three,two,three,three,three")
12348 (set_attr "length" "12,8,12,12,12")])
12350 (define_insn "*compare_plus_eqsi"
12351 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12354 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12355 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12356 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12358 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
12359 "TARGET_32BIT && optimize_size"
12361 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12362 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
12363 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12364 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12365 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12371 [(set_attr "type" "compare")
12372 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12375 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12378 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12379 (match_operand:SI 2 "scc_eq_operand" ""))
12380 (match_operand:SI 3 "gpc_reg_operand" ""))
12382 (clobber (match_scratch:SI 4 ""))]
12383 "TARGET_32BIT && optimize_size && reload_completed"
12384 [(set (match_dup 4)
12385 (plus:SI (eq:SI (match_dup 1)
12389 (compare:CC (match_dup 4)
12393 (define_insn "*plus_eqsi_compare"
12394 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12397 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12398 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12399 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12401 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12402 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12403 "TARGET_32BIT && optimize_size"
12405 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12406 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
12407 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12408 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12409 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12415 [(set_attr "type" "compare")
12416 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12419 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12422 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12423 (match_operand:SI 2 "scc_eq_operand" ""))
12424 (match_operand:SI 3 "gpc_reg_operand" ""))
12426 (set (match_operand:SI 0 "gpc_reg_operand" "")
12427 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12428 "TARGET_32BIT && optimize_size && reload_completed"
12429 [(set (match_dup 0)
12430 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12432 (compare:CC (match_dup 0)
12436 (define_insn "*neg_eq0<mode>"
12437 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12438 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12441 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
12442 [(set_attr "type" "two")
12443 (set_attr "length" "8")])
12445 (define_insn_and_split "*neg_eq<mode>"
12446 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12447 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12448 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
12452 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12454 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12456 /* Use output operand as intermediate. */
12457 operands[3] = operands[0];
12459 if (logical_operand (operands[2], <MODE>mode))
12460 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12461 gen_rtx_XOR (<MODE>mode,
12462 operands[1], operands[2])));
12464 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12465 gen_rtx_PLUS (<MODE>mode, operands[1],
12466 negate_rtx (<MODE>mode,
12470 operands[3] = operands[1];
12473 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
12474 ;; since it nabs/sr is just as fast.
12475 (define_insn "*ne0si"
12476 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12477 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12479 (clobber (match_scratch:SI 2 "=&r"))]
12480 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
12481 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
12482 [(set_attr "type" "two")
12483 (set_attr "length" "8")])
12485 (define_insn "*ne0di"
12486 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12487 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12489 (clobber (match_scratch:DI 2 "=&r"))]
12491 "addic %2,%1,-1\;subfe %0,%2,%1"
12492 [(set_attr "type" "two")
12493 (set_attr "length" "8")])
12495 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
12496 (define_insn "*plus_ne0si"
12497 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12498 (plus:SI (lshiftrt:SI
12499 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12501 (match_operand:SI 2 "gpc_reg_operand" "r")))
12502 (clobber (match_scratch:SI 3 "=&r"))]
12504 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
12505 [(set_attr "type" "two")
12506 (set_attr "length" "8")])
12508 (define_insn "*plus_ne0di"
12509 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12510 (plus:DI (lshiftrt:DI
12511 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12513 (match_operand:DI 2 "gpc_reg_operand" "r")))
12514 (clobber (match_scratch:DI 3 "=&r"))]
12516 "addic %3,%1,-1\;addze %0,%2"
12517 [(set_attr "type" "two")
12518 (set_attr "length" "8")])
12520 (define_insn "*compare_plus_ne0si"
12521 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12523 (plus:SI (lshiftrt:SI
12524 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12526 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12528 (clobber (match_scratch:SI 3 "=&r,&r"))
12529 (clobber (match_scratch:SI 4 "=X,&r"))]
12532 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
12534 [(set_attr "type" "compare")
12535 (set_attr "length" "8,12")])
12538 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12540 (plus:SI (lshiftrt:SI
12541 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12543 (match_operand:SI 2 "gpc_reg_operand" ""))
12545 (clobber (match_scratch:SI 3 ""))
12546 (clobber (match_scratch:SI 4 ""))]
12547 "TARGET_32BIT && reload_completed"
12548 [(parallel [(set (match_dup 3)
12549 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
12552 (clobber (match_dup 4))])
12554 (compare:CC (match_dup 3)
12558 (define_insn "*compare_plus_ne0di"
12559 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12561 (plus:DI (lshiftrt:DI
12562 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12564 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12566 (clobber (match_scratch:DI 3 "=&r,&r"))]
12569 addic %3,%1,-1\;addze. %3,%2
12571 [(set_attr "type" "compare")
12572 (set_attr "length" "8,12")])
12575 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12577 (plus:DI (lshiftrt:DI
12578 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12580 (match_operand:DI 2 "gpc_reg_operand" ""))
12582 (clobber (match_scratch:DI 3 ""))]
12583 "TARGET_64BIT && reload_completed"
12584 [(set (match_dup 3)
12585 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12589 (compare:CC (match_dup 3)
12593 (define_insn "*plus_ne0si_compare"
12594 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12596 (plus:SI (lshiftrt:SI
12597 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12599 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12601 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12602 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12604 (clobber (match_scratch:SI 3 "=&r,&r"))]
12607 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
12609 [(set_attr "type" "compare")
12610 (set_attr "length" "8,12")])
12613 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12615 (plus:SI (lshiftrt:SI
12616 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12618 (match_operand:SI 2 "gpc_reg_operand" ""))
12620 (set (match_operand:SI 0 "gpc_reg_operand" "")
12621 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12623 (clobber (match_scratch:SI 3 ""))]
12624 "TARGET_32BIT && reload_completed"
12625 [(parallel [(set (match_dup 0)
12626 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12628 (clobber (match_dup 3))])
12630 (compare:CC (match_dup 0)
12634 (define_insn "*plus_ne0di_compare"
12635 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12637 (plus:DI (lshiftrt:DI
12638 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12640 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12642 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12643 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12645 (clobber (match_scratch:DI 3 "=&r,&r"))]
12648 addic %3,%1,-1\;addze. %0,%2
12650 [(set_attr "type" "compare")
12651 (set_attr "length" "8,12")])
12654 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12656 (plus:DI (lshiftrt:DI
12657 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12659 (match_operand:DI 2 "gpc_reg_operand" ""))
12661 (set (match_operand:DI 0 "gpc_reg_operand" "")
12662 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12664 (clobber (match_scratch:DI 3 ""))]
12665 "TARGET_64BIT && reload_completed"
12666 [(parallel [(set (match_dup 0)
12667 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12669 (clobber (match_dup 3))])
12671 (compare:CC (match_dup 0)
12676 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12677 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12678 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12679 (clobber (match_scratch:SI 3 "=r,X"))]
12682 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
12683 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
12684 [(set_attr "length" "12")])
12687 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12689 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12690 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12692 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12693 (le:SI (match_dup 1) (match_dup 2)))
12694 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
12697 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12698 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
12701 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
12702 (set_attr "length" "12,12,16,16")])
12705 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12707 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12708 (match_operand:SI 2 "reg_or_short_operand" ""))
12710 (set (match_operand:SI 0 "gpc_reg_operand" "")
12711 (le:SI (match_dup 1) (match_dup 2)))
12712 (clobber (match_scratch:SI 3 ""))]
12713 "TARGET_POWER && reload_completed"
12714 [(parallel [(set (match_dup 0)
12715 (le:SI (match_dup 1) (match_dup 2)))
12716 (clobber (match_dup 3))])
12718 (compare:CC (match_dup 0)
12723 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12724 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12725 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
12726 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12729 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12730 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
12731 [(set_attr "length" "12")])
12734 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12736 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12737 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12738 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12740 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12743 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12744 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12747 [(set_attr "type" "compare")
12748 (set_attr "length" "12,12,16,16")])
12751 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12753 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12754 (match_operand:SI 2 "reg_or_short_operand" ""))
12755 (match_operand:SI 3 "gpc_reg_operand" ""))
12757 (clobber (match_scratch:SI 4 ""))]
12758 "TARGET_POWER && reload_completed"
12759 [(set (match_dup 4)
12760 (plus:SI (le:SI (match_dup 1) (match_dup 2))
12763 (compare:CC (match_dup 4)
12768 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12770 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12771 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12772 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12774 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12775 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12778 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12779 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
12782 [(set_attr "type" "compare")
12783 (set_attr "length" "12,12,16,16")])
12786 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12788 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12789 (match_operand:SI 2 "reg_or_short_operand" ""))
12790 (match_operand:SI 3 "gpc_reg_operand" ""))
12792 (set (match_operand:SI 0 "gpc_reg_operand" "")
12793 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12794 "TARGET_POWER && reload_completed"
12795 [(set (match_dup 0)
12796 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12798 (compare:CC (match_dup 0)
12803 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12804 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12805 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
12808 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12809 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
12810 [(set_attr "length" "12")])
12812 (define_insn "*leu<mode>"
12813 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12814 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12815 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12817 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12818 [(set_attr "type" "three")
12819 (set_attr "length" "12")])
12821 (define_insn "*leu<mode>_compare"
12822 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12824 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12825 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12827 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12828 (leu:P (match_dup 1) (match_dup 2)))]
12831 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12833 [(set_attr "type" "compare")
12834 (set_attr "length" "12,16")])
12837 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12839 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12840 (match_operand:P 2 "reg_or_short_operand" ""))
12842 (set (match_operand:P 0 "gpc_reg_operand" "")
12843 (leu:P (match_dup 1) (match_dup 2)))]
12845 [(set (match_dup 0)
12846 (leu:P (match_dup 1) (match_dup 2)))
12848 (compare:CC (match_dup 0)
12852 (define_insn "*plus_leu<mode>"
12853 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12854 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12855 (match_operand:P 2 "reg_or_short_operand" "rI"))
12856 (match_operand:P 3 "gpc_reg_operand" "r")))]
12858 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12859 [(set_attr "type" "two")
12860 (set_attr "length" "8")])
12863 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12865 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12866 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12867 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12869 (clobber (match_scratch:SI 4 "=&r,&r"))]
12872 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12874 [(set_attr "type" "compare")
12875 (set_attr "length" "8,12")])
12878 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12880 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12881 (match_operand:SI 2 "reg_or_short_operand" ""))
12882 (match_operand:SI 3 "gpc_reg_operand" ""))
12884 (clobber (match_scratch:SI 4 ""))]
12885 "TARGET_32BIT && reload_completed"
12886 [(set (match_dup 4)
12887 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12890 (compare:CC (match_dup 4)
12895 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12897 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12898 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12899 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12901 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12902 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12905 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12907 [(set_attr "type" "compare")
12908 (set_attr "length" "8,12")])
12911 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12913 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12914 (match_operand:SI 2 "reg_or_short_operand" ""))
12915 (match_operand:SI 3 "gpc_reg_operand" ""))
12917 (set (match_operand:SI 0 "gpc_reg_operand" "")
12918 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12919 "TARGET_32BIT && reload_completed"
12920 [(set (match_dup 0)
12921 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12923 (compare:CC (match_dup 0)
12927 (define_insn "*neg_leu<mode>"
12928 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12929 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12930 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12932 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12933 [(set_attr "type" "three")
12934 (set_attr "length" "12")])
12936 (define_insn "*and_neg_leu<mode>"
12937 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12939 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12940 (match_operand:P 2 "reg_or_short_operand" "rI")))
12941 (match_operand:P 3 "gpc_reg_operand" "r")))]
12943 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12944 [(set_attr "type" "three")
12945 (set_attr "length" "12")])
12948 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12951 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12952 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12953 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12955 (clobber (match_scratch:SI 4 "=&r,&r"))]
12958 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12960 [(set_attr "type" "compare")
12961 (set_attr "length" "12,16")])
12964 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12967 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12968 (match_operand:SI 2 "reg_or_short_operand" "")))
12969 (match_operand:SI 3 "gpc_reg_operand" ""))
12971 (clobber (match_scratch:SI 4 ""))]
12972 "TARGET_32BIT && reload_completed"
12973 [(set (match_dup 4)
12974 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12977 (compare:CC (match_dup 4)
12982 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12985 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12986 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12987 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12989 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12990 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12993 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12995 [(set_attr "type" "compare")
12996 (set_attr "length" "12,16")])
12999 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13002 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13003 (match_operand:SI 2 "reg_or_short_operand" "")))
13004 (match_operand:SI 3 "gpc_reg_operand" ""))
13006 (set (match_operand:SI 0 "gpc_reg_operand" "")
13007 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13008 "TARGET_32BIT && reload_completed"
13009 [(set (match_dup 0)
13010 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13013 (compare:CC (match_dup 0)
13018 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13019 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13020 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13022 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13023 [(set_attr "length" "12")])
13026 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13028 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13029 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13031 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13032 (lt:SI (match_dup 1) (match_dup 2)))]
13035 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13037 [(set_attr "type" "delayed_compare")
13038 (set_attr "length" "12,16")])
13041 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13043 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13044 (match_operand:SI 2 "reg_or_short_operand" ""))
13046 (set (match_operand:SI 0 "gpc_reg_operand" "")
13047 (lt:SI (match_dup 1) (match_dup 2)))]
13048 "TARGET_POWER && reload_completed"
13049 [(set (match_dup 0)
13050 (lt:SI (match_dup 1) (match_dup 2)))
13052 (compare:CC (match_dup 0)
13057 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13058 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13059 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13060 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13062 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13063 [(set_attr "length" "12")])
13066 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13068 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13069 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13070 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13072 (clobber (match_scratch:SI 4 "=&r,&r"))]
13075 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13077 [(set_attr "type" "compare")
13078 (set_attr "length" "12,16")])
13081 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13083 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13084 (match_operand:SI 2 "reg_or_short_operand" ""))
13085 (match_operand:SI 3 "gpc_reg_operand" ""))
13087 (clobber (match_scratch:SI 4 ""))]
13088 "TARGET_POWER && reload_completed"
13089 [(set (match_dup 4)
13090 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
13093 (compare:CC (match_dup 4)
13098 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13100 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13101 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13102 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13104 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13105 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13108 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13110 [(set_attr "type" "compare")
13111 (set_attr "length" "12,16")])
13114 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13116 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13117 (match_operand:SI 2 "reg_or_short_operand" ""))
13118 (match_operand:SI 3 "gpc_reg_operand" ""))
13120 (set (match_operand:SI 0 "gpc_reg_operand" "")
13121 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13122 "TARGET_POWER && reload_completed"
13123 [(set (match_dup 0)
13124 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13126 (compare:CC (match_dup 0)
13131 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13132 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13133 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13135 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13136 [(set_attr "length" "12")])
13138 (define_insn_and_split "*ltu<mode>"
13139 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13140 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13141 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13145 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13146 (set (match_dup 0) (neg:P (match_dup 0)))]
13149 (define_insn_and_split "*ltu<mode>_compare"
13150 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13152 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13153 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13155 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13156 (ltu:P (match_dup 1) (match_dup 2)))]
13160 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13161 (parallel [(set (match_dup 3)
13162 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13163 (set (match_dup 0) (neg:P (match_dup 0)))])]
13166 (define_insn_and_split "*plus_ltu<mode>"
13167 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
13168 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13169 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13170 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
13173 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13174 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13175 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13178 (define_insn_and_split "*plus_ltu<mode>_compare"
13179 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13181 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13182 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13183 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13185 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13186 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13189 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13190 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13191 (parallel [(set (match_dup 4)
13192 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13194 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13197 (define_insn "*neg_ltu<mode>"
13198 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13199 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13200 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
13203 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
13204 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
13205 [(set_attr "type" "two")
13206 (set_attr "length" "8")])
13209 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13210 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13211 (match_operand:SI 2 "reg_or_short_operand" "rI")))
13212 (clobber (match_scratch:SI 3 "=r"))]
13214 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
13215 [(set_attr "length" "12")])
13218 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13220 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13221 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13223 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13224 (ge:SI (match_dup 1) (match_dup 2)))
13225 (clobber (match_scratch:SI 3 "=r,r"))]
13228 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13230 [(set_attr "type" "compare")
13231 (set_attr "length" "12,16")])
13234 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13236 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13237 (match_operand:SI 2 "reg_or_short_operand" ""))
13239 (set (match_operand:SI 0 "gpc_reg_operand" "")
13240 (ge:SI (match_dup 1) (match_dup 2)))
13241 (clobber (match_scratch:SI 3 ""))]
13242 "TARGET_POWER && reload_completed"
13243 [(parallel [(set (match_dup 0)
13244 (ge:SI (match_dup 1) (match_dup 2)))
13245 (clobber (match_dup 3))])
13247 (compare:CC (match_dup 0)
13252 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13253 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13254 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13255 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13257 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
13258 [(set_attr "length" "12")])
13261 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13263 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13264 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13265 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13267 (clobber (match_scratch:SI 4 "=&r,&r"))]
13270 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13272 [(set_attr "type" "compare")
13273 (set_attr "length" "12,16")])
13276 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13278 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13279 (match_operand:SI 2 "reg_or_short_operand" ""))
13280 (match_operand:SI 3 "gpc_reg_operand" ""))
13282 (clobber (match_scratch:SI 4 ""))]
13283 "TARGET_POWER && reload_completed"
13284 [(set (match_dup 4)
13285 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
13288 (compare:CC (match_dup 4)
13293 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13295 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13296 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13297 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13299 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13300 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13303 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13305 [(set_attr "type" "compare")
13306 (set_attr "length" "12,16")])
13309 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13311 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13312 (match_operand:SI 2 "reg_or_short_operand" ""))
13313 (match_operand:SI 3 "gpc_reg_operand" ""))
13315 (set (match_operand:SI 0 "gpc_reg_operand" "")
13316 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13317 "TARGET_POWER && reload_completed"
13318 [(set (match_dup 0)
13319 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13321 (compare:CC (match_dup 0)
13326 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13327 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13328 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13330 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
13331 [(set_attr "length" "12")])
13333 (define_insn "*geu<mode>"
13334 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13335 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13336 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13339 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
13340 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
13341 [(set_attr "type" "three")
13342 (set_attr "length" "12")])
13344 (define_insn "*geu<mode>_compare"
13345 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13347 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13348 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13350 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13351 (geu:P (match_dup 1) (match_dup 2)))]
13354 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13355 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13358 [(set_attr "type" "compare")
13359 (set_attr "length" "12,12,16,16")])
13362 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13364 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
13365 (match_operand:P 2 "reg_or_neg_short_operand" ""))
13367 (set (match_operand:P 0 "gpc_reg_operand" "")
13368 (geu:P (match_dup 1) (match_dup 2)))]
13370 [(set (match_dup 0)
13371 (geu:P (match_dup 1) (match_dup 2)))
13373 (compare:CC (match_dup 0)
13377 (define_insn "*plus_geu<mode>"
13378 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13379 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13380 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13381 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13384 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
13385 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
13386 [(set_attr "type" "two")
13387 (set_attr "length" "8")])
13390 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13392 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13393 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13394 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13396 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13399 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
13400 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
13403 [(set_attr "type" "compare")
13404 (set_attr "length" "8,8,12,12")])
13407 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13409 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13410 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13411 (match_operand:SI 3 "gpc_reg_operand" ""))
13413 (clobber (match_scratch:SI 4 ""))]
13414 "TARGET_32BIT && reload_completed"
13415 [(set (match_dup 4)
13416 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13419 (compare:CC (match_dup 4)
13424 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13426 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13427 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13428 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13430 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13431 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13434 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
13435 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
13438 [(set_attr "type" "compare")
13439 (set_attr "length" "8,8,12,12")])
13442 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13444 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13445 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13446 (match_operand:SI 3 "gpc_reg_operand" ""))
13448 (set (match_operand:SI 0 "gpc_reg_operand" "")
13449 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13450 "TARGET_32BIT && reload_completed"
13451 [(set (match_dup 0)
13452 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13454 (compare:CC (match_dup 0)
13458 (define_insn "*neg_geu<mode>"
13459 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13460 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13461 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13464 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
13465 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
13466 [(set_attr "type" "three")
13467 (set_attr "length" "12")])
13469 (define_insn "*and_neg_geu<mode>"
13470 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13472 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13473 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13474 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13477 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
13478 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13479 [(set_attr "type" "three")
13480 (set_attr "length" "12")])
13483 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13486 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13487 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13488 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13490 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13493 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13494 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13497 [(set_attr "type" "compare")
13498 (set_attr "length" "12,12,16,16")])
13501 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13504 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13505 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13506 (match_operand:SI 3 "gpc_reg_operand" ""))
13508 (clobber (match_scratch:SI 4 ""))]
13509 "TARGET_32BIT && reload_completed"
13510 [(set (match_dup 4)
13511 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13514 (compare:CC (match_dup 4)
13519 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13522 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13523 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13524 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13526 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13527 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13530 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13531 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13534 [(set_attr "type" "compare")
13535 (set_attr "length" "12,12,16,16")])
13538 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13541 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13542 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13543 (match_operand:SI 3 "gpc_reg_operand" ""))
13545 (set (match_operand:SI 0 "gpc_reg_operand" "")
13546 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13547 "TARGET_32BIT && reload_completed"
13548 [(set (match_dup 0)
13549 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13551 (compare:CC (match_dup 0)
13556 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13557 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13558 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13560 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13561 [(set_attr "length" "12")])
13564 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13566 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13567 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13569 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13570 (gt:SI (match_dup 1) (match_dup 2)))]
13573 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13575 [(set_attr "type" "delayed_compare")
13576 (set_attr "length" "12,16")])
13579 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13581 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13582 (match_operand:SI 2 "reg_or_short_operand" ""))
13584 (set (match_operand:SI 0 "gpc_reg_operand" "")
13585 (gt:SI (match_dup 1) (match_dup 2)))]
13586 "TARGET_POWER && reload_completed"
13587 [(set (match_dup 0)
13588 (gt:SI (match_dup 1) (match_dup 2)))
13590 (compare:CC (match_dup 0)
13594 (define_insn "*plus_gt0<mode>"
13595 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13596 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13598 (match_operand:P 2 "gpc_reg_operand" "r")))]
13600 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13601 [(set_attr "type" "three")
13602 (set_attr "length" "12")])
13605 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13607 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13609 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13611 (clobber (match_scratch:SI 3 "=&r,&r"))]
13614 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13616 [(set_attr "type" "compare")
13617 (set_attr "length" "12,16")])
13620 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13622 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13624 (match_operand:SI 2 "gpc_reg_operand" ""))
13626 (clobber (match_scratch:SI 3 ""))]
13627 "TARGET_32BIT && reload_completed"
13628 [(set (match_dup 3)
13629 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13632 (compare:CC (match_dup 3)
13637 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13639 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13641 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13643 (clobber (match_scratch:DI 3 "=&r,&r"))]
13646 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13648 [(set_attr "type" "compare")
13649 (set_attr "length" "12,16")])
13652 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13654 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13656 (match_operand:DI 2 "gpc_reg_operand" ""))
13658 (clobber (match_scratch:DI 3 ""))]
13659 "TARGET_64BIT && reload_completed"
13660 [(set (match_dup 3)
13661 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13664 (compare:CC (match_dup 3)
13669 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13671 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13673 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13675 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13676 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13679 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13681 [(set_attr "type" "compare")
13682 (set_attr "length" "12,16")])
13685 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13687 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13689 (match_operand:SI 2 "gpc_reg_operand" ""))
13691 (set (match_operand:SI 0 "gpc_reg_operand" "")
13692 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13693 "TARGET_32BIT && reload_completed"
13694 [(set (match_dup 0)
13695 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13697 (compare:CC (match_dup 0)
13702 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13704 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13706 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13708 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13709 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13712 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13714 [(set_attr "type" "compare")
13715 (set_attr "length" "12,16")])
13718 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13720 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13722 (match_operand:DI 2 "gpc_reg_operand" ""))
13724 (set (match_operand:DI 0 "gpc_reg_operand" "")
13725 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13726 "TARGET_64BIT && reload_completed"
13727 [(set (match_dup 0)
13728 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13730 (compare:CC (match_dup 0)
13735 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13736 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13737 (match_operand:SI 2 "reg_or_short_operand" "r"))
13738 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13740 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13741 [(set_attr "length" "12")])
13744 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13746 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13747 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13748 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13750 (clobber (match_scratch:SI 4 "=&r,&r"))]
13753 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13755 [(set_attr "type" "compare")
13756 (set_attr "length" "12,16")])
13759 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13761 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13762 (match_operand:SI 2 "reg_or_short_operand" ""))
13763 (match_operand:SI 3 "gpc_reg_operand" ""))
13765 (clobber (match_scratch:SI 4 ""))]
13766 "TARGET_POWER && reload_completed"
13767 [(set (match_dup 4)
13768 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13770 (compare:CC (match_dup 4)
13775 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13777 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13778 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13779 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13781 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13782 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13785 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13787 [(set_attr "type" "compare")
13788 (set_attr "length" "12,16")])
13791 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13793 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13794 (match_operand:SI 2 "reg_or_short_operand" ""))
13795 (match_operand:SI 3 "gpc_reg_operand" ""))
13797 (set (match_operand:SI 0 "gpc_reg_operand" "")
13798 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13799 "TARGET_POWER && reload_completed"
13800 [(set (match_dup 0)
13801 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13803 (compare:CC (match_dup 0)
13808 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13809 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13810 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13812 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13813 [(set_attr "length" "12")])
13815 (define_insn_and_split "*gtu<mode>"
13816 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13817 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13818 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13822 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13823 (set (match_dup 0) (neg:P (match_dup 0)))]
13826 (define_insn_and_split "*gtu<mode>_compare"
13827 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13829 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13830 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13832 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13833 (gtu:P (match_dup 1) (match_dup 2)))]
13837 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13838 (parallel [(set (match_dup 3)
13839 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13840 (set (match_dup 0) (neg:P (match_dup 0)))])]
13843 (define_insn_and_split "*plus_gtu<mode>"
13844 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13845 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13846 (match_operand:P 2 "reg_or_short_operand" "rI"))
13847 (match_operand:P 3 "reg_or_short_operand" "rI")))]
13850 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13851 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13852 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13855 (define_insn_and_split "*plus_gtu<mode>_compare"
13856 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13858 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13859 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13860 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13862 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13863 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13866 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13867 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13868 (parallel [(set (match_dup 4)
13869 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13871 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13874 (define_insn "*neg_gtu<mode>"
13875 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13876 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13877 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13879 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13880 [(set_attr "type" "two")
13881 (set_attr "length" "8")])
13884 ;; Define both directions of branch and return. If we need a reload
13885 ;; register, we'd rather use CR0 since it is much easier to copy a
13886 ;; register CC value to there.
13890 (if_then_else (match_operator 1 "branch_comparison_operator"
13892 "cc_reg_operand" "y")
13894 (label_ref (match_operand 0 "" ""))
13899 return output_cbranch (operands[1], \"%l0\", 0, insn);
13901 [(set_attr "type" "branch")])
13905 (if_then_else (match_operator 0 "branch_comparison_operator"
13907 "cc_reg_operand" "y")
13914 return output_cbranch (operands[0], NULL, 0, insn);
13916 [(set_attr "type" "jmpreg")
13917 (set_attr "length" "4")])
13921 (if_then_else (match_operator 1 "branch_comparison_operator"
13923 "cc_reg_operand" "y")
13926 (label_ref (match_operand 0 "" ""))))]
13930 return output_cbranch (operands[1], \"%l0\", 1, insn);
13932 [(set_attr "type" "branch")])
13936 (if_then_else (match_operator 0 "branch_comparison_operator"
13938 "cc_reg_operand" "y")
13945 return output_cbranch (operands[0], NULL, 1, insn);
13947 [(set_attr "type" "jmpreg")
13948 (set_attr "length" "4")])
13950 ;; Logic on condition register values.
13952 ; This pattern matches things like
13953 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13954 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13956 ; which are generated by the branch logic.
13957 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13959 (define_insn "*cceq_ior_compare"
13960 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13961 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13962 [(match_operator:SI 2
13963 "branch_positive_comparison_operator"
13965 "cc_reg_operand" "y,y")
13967 (match_operator:SI 4
13968 "branch_positive_comparison_operator"
13970 "cc_reg_operand" "0,y")
13974 "cr%q1 %E0,%j2,%j4"
13975 [(set_attr "type" "cr_logical,delayed_cr")])
13977 ; Why is the constant -1 here, but 1 in the previous pattern?
13978 ; Because ~1 has all but the low bit set.
13980 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13981 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13982 [(not:SI (match_operator:SI 2
13983 "branch_positive_comparison_operator"
13985 "cc_reg_operand" "y,y")
13987 (match_operator:SI 4
13988 "branch_positive_comparison_operator"
13990 "cc_reg_operand" "0,y")
13994 "cr%q1 %E0,%j2,%j4"
13995 [(set_attr "type" "cr_logical,delayed_cr")])
13997 (define_insn "*cceq_rev_compare"
13998 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13999 (compare:CCEQ (match_operator:SI 1
14000 "branch_positive_comparison_operator"
14002 "cc_reg_operand" "0,y")
14006 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
14007 [(set_attr "type" "cr_logical,delayed_cr")])
14009 ;; If we are comparing the result of two comparisons, this can be done
14010 ;; using creqv or crxor.
14012 (define_insn_and_split ""
14013 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14014 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
14015 [(match_operand 2 "cc_reg_operand" "y")
14017 (match_operator 3 "branch_comparison_operator"
14018 [(match_operand 4 "cc_reg_operand" "y")
14023 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14027 int positive_1, positive_2;
14029 positive_1 = branch_positive_comparison_operator (operands[1],
14030 GET_MODE (operands[1]));
14031 positive_2 = branch_positive_comparison_operator (operands[3],
14032 GET_MODE (operands[3]));
14035 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
14036 GET_CODE (operands[1])),
14038 operands[2], const0_rtx);
14039 else if (GET_MODE (operands[1]) != SImode)
14040 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14041 operands[2], const0_rtx);
14044 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
14045 GET_CODE (operands[3])),
14047 operands[4], const0_rtx);
14048 else if (GET_MODE (operands[3]) != SImode)
14049 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14050 operands[4], const0_rtx);
14052 if (positive_1 == positive_2)
14054 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14055 operands[5] = constm1_rtx;
14059 operands[5] = const1_rtx;
14063 ;; Unconditional branch and return.
14065 (define_insn "jump"
14067 (label_ref (match_operand 0 "" "")))]
14070 [(set_attr "type" "branch")])
14072 (define_insn "return"
14076 [(set_attr "type" "jmpreg")])
14078 (define_expand "indirect_jump"
14079 [(set (pc) (match_operand 0 "register_operand" ""))])
14081 (define_insn "*indirect_jump<mode>"
14082 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14087 [(set_attr "type" "jmpreg")])
14089 ;; Table jump for switch statements:
14090 (define_expand "tablejump"
14091 [(use (match_operand 0 "" ""))
14092 (use (label_ref (match_operand 1 "" "")))]
14097 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14099 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14103 (define_expand "tablejumpsi"
14104 [(set (match_dup 3)
14105 (plus:SI (match_operand:SI 0 "" "")
14107 (parallel [(set (pc) (match_dup 3))
14108 (use (label_ref (match_operand 1 "" "")))])]
14111 { operands[0] = force_reg (SImode, operands[0]);
14112 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
14113 operands[3] = gen_reg_rtx (SImode);
14116 (define_expand "tablejumpdi"
14117 [(set (match_dup 4)
14118 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
14120 (plus:DI (match_dup 4)
14122 (parallel [(set (pc) (match_dup 3))
14123 (use (label_ref (match_operand 1 "" "")))])]
14126 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
14127 operands[3] = gen_reg_rtx (DImode);
14128 operands[4] = gen_reg_rtx (DImode);
14131 (define_insn "*tablejump<mode>_internal1"
14133 (match_operand:P 0 "register_operand" "c,*l"))
14134 (use (label_ref (match_operand 1 "" "")))]
14139 [(set_attr "type" "jmpreg")])
14144 "{cror 0,0,0|nop}")
14146 ;; Define the subtract-one-and-jump insns, starting with the template
14147 ;; so loop.c knows what to generate.
14149 (define_expand "doloop_end"
14150 [(use (match_operand 0 "" "")) ; loop pseudo
14151 (use (match_operand 1 "" "")) ; iterations; zero if unknown
14152 (use (match_operand 2 "" "")) ; max iterations
14153 (use (match_operand 3 "" "")) ; loop level
14154 (use (match_operand 4 "" ""))] ; label
14158 /* Only use this on innermost loops. */
14159 if (INTVAL (operands[3]) > 1)
14163 if (GET_MODE (operands[0]) != DImode)
14165 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
14169 if (GET_MODE (operands[0]) != SImode)
14171 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
14176 (define_expand "ctr<mode>"
14177 [(parallel [(set (pc)
14178 (if_then_else (ne (match_operand:P 0 "register_operand" "")
14180 (label_ref (match_operand 1 "" ""))
14183 (plus:P (match_dup 0)
14185 (clobber (match_scratch:CC 2 ""))
14186 (clobber (match_scratch:P 3 ""))])]
14190 ;; We need to be able to do this for any operand, including MEM, or we
14191 ;; will cause reload to blow up since we don't allow output reloads on
14193 ;; For the length attribute to be calculated correctly, the
14194 ;; label MUST be operand 0.
14196 (define_insn "*ctr<mode>_internal1"
14198 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14200 (label_ref (match_operand 0 "" ""))
14202 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14203 (plus:P (match_dup 1)
14205 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14206 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14210 if (which_alternative != 0)
14212 else if (get_attr_length (insn) == 4)
14213 return \"{bdn|bdnz} %l0\";
14215 return \"bdz $+8\;b %l0\";
14217 [(set_attr "type" "branch")
14218 (set_attr "length" "*,12,16,16")])
14220 (define_insn "*ctr<mode>_internal2"
14222 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14225 (label_ref (match_operand 0 "" ""))))
14226 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14227 (plus:P (match_dup 1)
14229 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14230 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14234 if (which_alternative != 0)
14236 else if (get_attr_length (insn) == 4)
14237 return \"bdz %l0\";
14239 return \"{bdn|bdnz} $+8\;b %l0\";
14241 [(set_attr "type" "branch")
14242 (set_attr "length" "*,12,16,16")])
14244 ;; Similar but use EQ
14246 (define_insn "*ctr<mode>_internal5"
14248 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14250 (label_ref (match_operand 0 "" ""))
14252 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14253 (plus:P (match_dup 1)
14255 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14256 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14260 if (which_alternative != 0)
14262 else if (get_attr_length (insn) == 4)
14263 return \"bdz %l0\";
14265 return \"{bdn|bdnz} $+8\;b %l0\";
14267 [(set_attr "type" "branch")
14268 (set_attr "length" "*,12,16,16")])
14270 (define_insn "*ctr<mode>_internal6"
14272 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14275 (label_ref (match_operand 0 "" ""))))
14276 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14277 (plus:P (match_dup 1)
14279 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14280 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14284 if (which_alternative != 0)
14286 else if (get_attr_length (insn) == 4)
14287 return \"{bdn|bdnz} %l0\";
14289 return \"bdz $+8\;b %l0\";
14291 [(set_attr "type" "branch")
14292 (set_attr "length" "*,12,16,16")])
14294 ;; Now the splitters if we could not allocate the CTR register
14298 (if_then_else (match_operator 2 "comparison_operator"
14299 [(match_operand:P 1 "gpc_reg_operand" "")
14301 (match_operand 5 "" "")
14302 (match_operand 6 "" "")))
14303 (set (match_operand:P 0 "gpc_reg_operand" "")
14304 (plus:P (match_dup 1) (const_int -1)))
14305 (clobber (match_scratch:CC 3 ""))
14306 (clobber (match_scratch:P 4 ""))]
14308 [(parallel [(set (match_dup 3)
14309 (compare:CC (plus:P (match_dup 1)
14313 (plus:P (match_dup 1)
14315 (set (pc) (if_then_else (match_dup 7)
14319 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14320 operands[3], const0_rtx); }")
14324 (if_then_else (match_operator 2 "comparison_operator"
14325 [(match_operand:P 1 "gpc_reg_operand" "")
14327 (match_operand 5 "" "")
14328 (match_operand 6 "" "")))
14329 (set (match_operand:P 0 "nonimmediate_operand" "")
14330 (plus:P (match_dup 1) (const_int -1)))
14331 (clobber (match_scratch:CC 3 ""))
14332 (clobber (match_scratch:P 4 ""))]
14333 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
14334 [(parallel [(set (match_dup 3)
14335 (compare:CC (plus:P (match_dup 1)
14339 (plus:P (match_dup 1)
14343 (set (pc) (if_then_else (match_dup 7)
14347 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14348 operands[3], const0_rtx); }")
14350 (define_insn "trap"
14351 [(trap_if (const_int 1) (const_int 0))]
14354 [(set_attr "type" "trap")])
14356 (define_expand "conditional_trap"
14357 [(trap_if (match_operator 0 "trap_comparison_operator"
14358 [(match_dup 2) (match_dup 3)])
14359 (match_operand 1 "const_int_operand" ""))]
14361 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14362 operands[2] = rs6000_compare_op0;
14363 operands[3] = rs6000_compare_op1;")
14366 [(trap_if (match_operator 0 "trap_comparison_operator"
14367 [(match_operand:GPR 1 "register_operand" "r")
14368 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
14371 "{t|t<wd>}%V0%I2 %1,%2"
14372 [(set_attr "type" "trap")])
14374 ;; Insns related to generating the function prologue and epilogue.
14376 (define_expand "prologue"
14377 [(use (const_int 0))]
14378 "TARGET_SCHED_PROLOG"
14381 rs6000_emit_prologue ();
14385 (define_insn "*movesi_from_cr_one"
14386 [(match_parallel 0 "mfcr_operation"
14387 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14388 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14389 (match_operand 3 "immediate_operand" "n")]
14390 UNSPEC_MOVESI_FROM_CR))])]
14396 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14398 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14399 operands[4] = GEN_INT (mask);
14400 output_asm_insn (\"mfcr %1,%4\", operands);
14404 [(set_attr "type" "mfcrf")])
14406 (define_insn "movesi_from_cr"
14407 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14408 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
14409 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
14410 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
14411 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
14412 UNSPEC_MOVESI_FROM_CR))]
14415 [(set_attr "type" "mfcr")])
14417 (define_insn "*stmw"
14418 [(match_parallel 0 "stmw_operation"
14419 [(set (match_operand:SI 1 "memory_operand" "=m")
14420 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14423 [(set_attr "type" "store_ux")])
14425 (define_insn "*save_gpregs_<mode>"
14426 [(match_parallel 0 "any_parallel_operand"
14427 [(clobber (reg:P 65))
14428 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14429 (use (match_operand:P 2 "gpc_reg_operand" "r"))
14430 (set (match_operand:P 3 "memory_operand" "=m")
14431 (match_operand:P 4 "gpc_reg_operand" "r"))])]
14434 [(set_attr "type" "branch")
14435 (set_attr "length" "4")])
14437 (define_insn "*save_fpregs_<mode>"
14438 [(match_parallel 0 "any_parallel_operand"
14439 [(clobber (reg:P 65))
14440 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14441 (use (match_operand:P 2 "gpc_reg_operand" "r"))
14442 (set (match_operand:DF 3 "memory_operand" "=m")
14443 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14446 [(set_attr "type" "branch")
14447 (set_attr "length" "4")])
14449 ; These are to explain that changes to the stack pointer should
14450 ; not be moved over stores to stack memory.
14451 (define_insn "stack_tie"
14452 [(set (match_operand:BLK 0 "memory_operand" "+m")
14453 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
14456 [(set_attr "length" "0")])
14459 (define_expand "epilogue"
14460 [(use (const_int 0))]
14461 "TARGET_SCHED_PROLOG"
14464 rs6000_emit_epilogue (FALSE);
14468 ; On some processors, doing the mtcrf one CC register at a time is
14469 ; faster (like on the 604e). On others, doing them all at once is
14470 ; faster; for instance, on the 601 and 750.
14472 (define_expand "movsi_to_cr_one"
14473 [(set (match_operand:CC 0 "cc_reg_operand" "")
14474 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
14475 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14477 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14479 (define_insn "*movsi_to_cr"
14480 [(match_parallel 0 "mtcrf_operation"
14481 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14482 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14483 (match_operand 3 "immediate_operand" "n")]
14484 UNSPEC_MOVESI_TO_CR))])]
14490 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14491 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14492 operands[4] = GEN_INT (mask);
14493 return \"mtcrf %4,%2\";
14495 [(set_attr "type" "mtcr")])
14497 (define_insn "*mtcrfsi"
14498 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14499 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14500 (match_operand 2 "immediate_operand" "n")]
14501 UNSPEC_MOVESI_TO_CR))]
14502 "GET_CODE (operands[0]) == REG
14503 && CR_REGNO_P (REGNO (operands[0]))
14504 && GET_CODE (operands[2]) == CONST_INT
14505 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14507 [(set_attr "type" "mtcr")])
14509 ; The load-multiple instructions have similar properties.
14510 ; Note that "load_multiple" is a name known to the machine-independent
14511 ; code that actually corresponds to the PowerPC load-string.
14513 (define_insn "*lmw"
14514 [(match_parallel 0 "lmw_operation"
14515 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14516 (match_operand:SI 2 "memory_operand" "m"))])]
14519 [(set_attr "type" "load_ux")])
14521 (define_insn "*return_internal_<mode>"
14523 (use (match_operand:P 0 "register_operand" "lc"))]
14526 [(set_attr "type" "jmpreg")])
14528 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14529 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14531 (define_insn "*restore_gpregs_<mode>"
14532 [(match_parallel 0 "any_parallel_operand"
14533 [(clobber (match_operand:P 1 "register_operand" "=l"))
14534 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14535 (use (match_operand:P 3 "gpc_reg_operand" "r"))
14536 (set (match_operand:P 4 "gpc_reg_operand" "=r")
14537 (match_operand:P 5 "memory_operand" "m"))])]
14540 [(set_attr "type" "branch")
14541 (set_attr "length" "4")])
14543 (define_insn "*return_and_restore_gpregs_<mode>"
14544 [(match_parallel 0 "any_parallel_operand"
14546 (clobber (match_operand:P 1 "register_operand" "=l"))
14547 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14548 (use (match_operand:P 3 "gpc_reg_operand" "r"))
14549 (set (match_operand:P 4 "gpc_reg_operand" "=r")
14550 (match_operand:P 5 "memory_operand" "m"))])]
14553 [(set_attr "type" "branch")
14554 (set_attr "length" "4")])
14556 (define_insn "*return_and_restore_fpregs_<mode>"
14557 [(match_parallel 0 "any_parallel_operand"
14559 (clobber (match_operand:P 1 "register_operand" "=l"))
14560 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14561 (use (match_operand:P 3 "gpc_reg_operand" "r"))
14562 (set (match_operand:DF 4 "gpc_reg_operand" "=f")
14563 (match_operand:DF 5 "memory_operand" "m"))])]
14566 [(set_attr "type" "branch")
14567 (set_attr "length" "4")])
14569 ; This is used in compiling the unwind routines.
14570 (define_expand "eh_return"
14571 [(use (match_operand 0 "general_operand" ""))]
14576 emit_insn (gen_eh_set_lr_si (operands[0]));
14578 emit_insn (gen_eh_set_lr_di (operands[0]));
14582 ; We can't expand this before we know where the link register is stored.
14583 (define_insn "eh_set_lr_<mode>"
14584 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
14586 (clobber (match_scratch:P 1 "=&b"))]
14591 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14592 (clobber (match_scratch 1 ""))]
14597 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14601 (define_insn "prefetch"
14602 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
14603 (match_operand:SI 1 "const_int_operand" "n")
14604 (match_operand:SI 2 "const_int_operand" "n"))]
14608 if (GET_CODE (operands[0]) == REG)
14609 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14610 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14612 [(set_attr "type" "load")])
14615 (include "sync.md")
14616 (include "altivec.md")
14619 (include "paired.md")