gcc/config/rs6000/rs6000.opt

   1 ; Options for the rs6000 port of the compiler
   2 ;
   3 ; Copyright (C) 2005-2016 Free Software Foundation, Inc.
   4 ; Contributed by Aldy Hernandez <aldy@quesejoda.com>.
   5 ;
   6 ; This file is part of GCC.
   7 ;
   8 ; GCC is free software; you can redistribute it and/or modify it under
   9 ; the terms of the GNU General Public License as published by the Free
  10 ; Software Foundation; either version 3, or (at your option) any later
  11 ; version.
  12 ;
  13 ; GCC is distributed in the hope that it will be useful, but WITHOUT
  14 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15 ; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16 ; License for more details.
  17 ;
  18 ; You should have received a copy of the GNU General Public License
  19 ; along with GCC; see the file COPYING3.  If not see
  20 ; <http://www.gnu.org/licenses/>.
  21
  22 HeaderInclude
  23 config/rs6000/rs6000-opts.h
  24
  25 ;; ISA flag bits (on/off)
  26 Variable
  27 HOST_WIDE_INT rs6000_isa_flags = TARGET_DEFAULT
  28
  29 TargetSave
  30 HOST_WIDE_INT x_rs6000_isa_flags
  31
  32 ;; Miscellaneous flag bits that were set explicitly by the user
  33 Variable
  34 HOST_WIDE_INT rs6000_isa_flags_explicit
  35
  36 TargetSave
  37 HOST_WIDE_INT x_rs6000_isa_flags_explicit
  38
  39 ;; Current processor
  40 TargetVariable
  41 enum processor_type rs6000_cpu = PROCESSOR_PPC603
  42
  43 ;; Always emit branch hint bits.
  44 TargetVariable
  45 unsigned char rs6000_always_hint
  46
  47 ;; Schedule instructions for group formation.
  48 TargetVariable
  49 unsigned char rs6000_sched_groups
  50
  51 ;; Align branch targets.
  52 TargetVariable
  53 unsigned char rs6000_align_branch_targets
  54
  55 ;; Support for -msched-costly-dep option.
  56 TargetVariable
  57 enum rs6000_dependence_cost rs6000_sched_costly_dep = no_dep_costly
  58
  59 ;; Support for -minsert-sched-nops option.
  60 TargetVariable
  61 enum rs6000_nop_insertion rs6000_sched_insert_nops = sched_finish_none
  62
  63 ;; Non-zero to allow overriding loop alignment.
  64 TargetVariable
  65 unsigned char can_override_loop_align
  66
  67 ;; Which small data model to use (for System V targets only)
  68 TargetVariable
  69 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA
  70
  71 ;; Bit size of immediate TLS offsets and string from which it is decoded.
  72 TargetVariable
  73 int rs6000_tls_size = 32
  74
  75 ;; ABI enumeration available for subtarget to use.
  76 TargetVariable
  77 enum rs6000_abi rs6000_current_abi = ABI_NONE
  78
  79 ;; Type of traceback to use.
  80 TargetVariable
  81 enum rs6000_traceback_type rs6000_traceback = traceback_default
  82
  83 ;; Control alignment for fields within structures.
  84 TargetVariable
  85 unsigned char rs6000_alignment_flags
  86
  87 ;; Code model for 64-bit linux.
  88 TargetVariable
  89 enum rs6000_cmodel rs6000_current_cmodel = CMODEL_SMALL
  90
  91 ;; What type of reciprocal estimation instructions to generate
  92 TargetVariable
  93 unsigned int rs6000_recip_control
  94
  95 ;; Mask of what builtin functions are allowed
  96 TargetVariable
  97 HOST_WIDE_INT rs6000_builtin_mask
  98
  99 ;; Debug flags
 100 TargetVariable
 101 unsigned int rs6000_debug
 102
 103 ;; This option existed in the past, but now is always on.
 104 mpowerpc
 105 Target RejectNegative Undocumented Ignore
 106
 107 mpowerpc64
 108 Target Report Mask(POWERPC64) Var(rs6000_isa_flags)
 109 Use PowerPC-64 instruction set.
 110
 111 mpowerpc-gpopt
 112 Target Report Mask(PPC_GPOPT) Var(rs6000_isa_flags)
 113 Use PowerPC General Purpose group optional instructions.
 114
 115 mpowerpc-gfxopt
 116 Target Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags)
 117 Use PowerPC Graphics group optional instructions.
 118
 119 mmfcrf
 120 Target Report Mask(MFCRF) Var(rs6000_isa_flags)
 121 Use PowerPC V2.01 single field mfcr instruction.
 122
 123 mpopcntb
 124 Target Report Mask(POPCNTB) Var(rs6000_isa_flags)
 125 Use PowerPC V2.02 popcntb instruction.
 126
 127 mfprnd
 128 Target Report Mask(FPRND) Var(rs6000_isa_flags)
 129 Use PowerPC V2.02 floating point rounding instructions.
 130
 131 mcmpb
 132 Target Report Mask(CMPB) Var(rs6000_isa_flags)
 133 Use PowerPC V2.05 compare bytes instruction.
 134
 135 mmfpgpr
 136 Target Report Mask(MFPGPR) Var(rs6000_isa_flags)
 137 Use extended PowerPC V2.05 move floating point to/from GPR instructions.
 138
 139 maltivec
 140 Target Report Mask(ALTIVEC) Var(rs6000_isa_flags)
 141 Use AltiVec instructions.
 142
 143 maltivec=le
 144 Target Report RejectNegative Var(rs6000_altivec_element_order, 1) Save
 145 Generate Altivec instructions using little-endian element order.
 146
 147 maltivec=be
 148 Target Report RejectNegative Var(rs6000_altivec_element_order, 2)
 149 Generate Altivec instructions using big-endian element order.
 150
 151 mhard-dfp
 152 Target Report Mask(DFP) Var(rs6000_isa_flags)
 153 Use decimal floating point instructions.
 154
 155 mmulhw
 156 Target Report Mask(MULHW) Var(rs6000_isa_flags)
 157 Use 4xx half-word multiply instructions.
 158
 159 mdlmzb
 160 Target Report Mask(DLMZB) Var(rs6000_isa_flags)
 161 Use 4xx string-search dlmzb instruction.
 162
 163 mmultiple
 164 Target Report Mask(MULTIPLE) Var(rs6000_isa_flags)
 165 Generate load/store multiple instructions.
 166
 167 mstring
 168 Target Report Mask(STRING) Var(rs6000_isa_flags)
 169 Generate string instructions for block moves.
 170
 171 msoft-float
 172 Target Report RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags)
 173 Do not use hardware floating point.
 174
 175 mhard-float
 176 Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags)
 177 Use hardware floating point.
 178
 179 mpopcntd
 180 Target Report Mask(POPCNTD) Var(rs6000_isa_flags)
 181 Use PowerPC V2.06 popcntd instruction.
 182
 183 mfriz
 184 Target Report Var(TARGET_FRIZ) Init(-1) Save
 185 Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions.
 186
 187 mveclibabi=
 188 Target RejectNegative Joined Var(rs6000_veclibabi_name)
 189 Vector library ABI to use.
 190
 191 mvsx
 192 Target Report Mask(VSX) Var(rs6000_isa_flags)
 193 Use vector/scalar (VSX) instructions.
 194
 195 mvsx-scalar-float
 196 Target Undocumented Report Var(TARGET_VSX_SCALAR_FLOAT) Init(1)
 197 ; If -mpower8-vector, use VSX arithmetic instructions for SFmode (on by default)
 198
 199 mvsx-scalar-double
 200 Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(1)
 201 ; If -mvsx, use VSX arithmetic instructions for DFmode (on by default)
 202
 203 mvsx-scalar-memory
 204 Target Undocumented Report Alias(mupper-regs-df)
 205
 206 mvsx-align-128
 207 Target Undocumented Report Var(TARGET_VSX_ALIGN_128) Save
 208 ; If -mvsx, set alignment to 128 bits instead of 32/64
 209
 210 mallow-movmisalign
 211 Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1) Save
 212 ; Allow/disallow the movmisalign in DF/DI vectors
 213
 214 mefficient-unaligned-vector
 215 Target Undocumented Report Mask(EFFICIENT_UNALIGNED_VSX) Var(rs6000_isa_flags)
 216 ; Consider unaligned VSX accesses to be efficient/inefficient
 217
 218 mallow-df-permute
 219 Target Undocumented Var(TARGET_ALLOW_DF_PERMUTE) Save
 220 ; Allow/disallow permutation of DF/DI vectors
 221
 222 msched-groups
 223 Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1) Save
 224 ; Explicitly set/unset whether rs6000_sched_groups is set
 225
 226 malways-hint
 227 Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1) Save
 228 ; Explicitly set/unset whether rs6000_always_hint is set
 229
 230 malign-branch-targets
 231 Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1) Save
 232 ; Explicitly set/unset whether rs6000_align_branch_targets is set
 233
 234 mvectorize-builtins
 235 Target Undocumented Report Var(TARGET_VECTORIZE_BUILTINS) Init(-1) Save
 236 ; Explicitly control whether we vectorize the builtins or not.
 237
 238 mno-update
 239 Target Report RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags)
 240 Do not generate load/store with update instructions.
 241
 242 mupdate
 243 Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags)
 244 Generate load/store with update instructions.
 245
 246 msingle-pic-base
 247 Target Report Var(TARGET_SINGLE_PIC_BASE) Init(0)
 248 Do not load the PIC register in function prologues.
 249
 250 mavoid-indexed-addresses
 251 Target Report Var(TARGET_AVOID_XFORM) Init(-1) Save
 252 Avoid generation of indexed load/store instructions when possible.
 253
 254 mtls-markers
 255 Target Report Var(tls_markers) Init(1) Save
 256 Mark __tls_get_addr calls with argument info.
 257
 258 msched-epilog
 259 Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) Save
 260
 261 msched-prolog
 262 Target Report Var(TARGET_SCHED_PROLOG) Save
 263 Schedule the start and end of the procedure.
 264
 265 maix-struct-return
 266 Target Report RejectNegative Var(aix_struct_return) Save
 267 Return all structures in memory (AIX default).
 268
 269 msvr4-struct-return
 270 Target Report RejectNegative Var(aix_struct_return,0) Save
 271 Return small structures in registers (SVR4 default).
 272
 273 mxl-compat
 274 Target Report Var(TARGET_XL_COMPAT) Save
 275 Conform more closely to IBM XLC semantics.
 276
 277 mrecip
 278 Target Report
 279 Generate software reciprocal divide and square root for better throughput.
 280
 281 mrecip=
 282 Target Report RejectNegative Joined Var(rs6000_recip_name)
 283 Generate software reciprocal divide and square root for better throughput.
 284
 285 mrecip-precision
 286 Target Report Mask(RECIP_PRECISION) Var(rs6000_isa_flags)
 287 Assume that the reciprocal estimate instructions provide more accuracy.
 288
 289 mno-fp-in-toc
 290 Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC) Save
 291 Do not place floating point constants in TOC.
 292
 293 mfp-in-toc
 294 Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0) Save
 295 Place floating point constants in TOC.
 296
 297 mno-sum-in-toc
 298 Target RejectNegative Var(TARGET_NO_SUM_IN_TOC) Save
 299 Do not place symbol+offset constants in TOC.
 300
 301 msum-in-toc
 302 Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) Save
 303 Place symbol+offset constants in TOC.
 304
 305 ;  Output only one TOC entry per module.  Normally linking fails if
 306 ;   there are more than 16K unique variables/constants in an executable.  With
 307 ;   this option, linking fails only if there are more than 16K modules, or
 308 ;   if there are more than 16K unique variables/constant in a single module.
 309 ;
 310 ;   This is at the cost of having 2 extra loads and one extra store per
 311 ;   function, and one less allocable register.
 312 mminimal-toc
 313 Target Report Mask(MINIMAL_TOC) Var(rs6000_isa_flags)
 314 Use only one TOC entry per procedure.
 315
 316 mfull-toc
 317 Target Report
 318 Put everything in the regular TOC.
 319
 320 mvrsave
 321 Target Report Var(TARGET_ALTIVEC_VRSAVE) Save
 322 Generate VRSAVE instructions when generating AltiVec code.
 323
 324 mvrsave=no
 325 Target RejectNegative Alias(mvrsave) NegativeAlias
 326 Deprecated option.  Use -mno-vrsave instead.
 327
 328 mvrsave=yes
 329 Target RejectNegative Alias(mvrsave)
 330 Deprecated option.  Use -mvrsave instead.
 331
 332 mblock-move-inline-limit=
 333 Target Report Var(rs6000_block_move_inline_limit) Init(0) RejectNegative Joined UInteger Save
 334 Specify how many bytes should be moved inline before calling out to memcpy/memmove.
 335
 336 misel
 337 Target Report Mask(ISEL) Var(rs6000_isa_flags)
 338 Generate isel instructions.
 339
 340 misel=no
 341 Target RejectNegative Alias(misel) NegativeAlias
 342 Deprecated option.  Use -mno-isel instead.
 343
 344 misel=yes
 345 Target RejectNegative Alias(misel)
 346 Deprecated option.  Use -misel instead.
 347
 348 mspe
 349 Target Var(rs6000_spe) Save
 350 Generate SPE SIMD instructions on E500.
 351
 352 mpaired
 353 Target Var(rs6000_paired_float) Save
 354 Generate PPC750CL paired-single instructions.
 355
 356 mspe=no
 357 Target RejectNegative Alias(mspe) NegativeAlias
 358 Deprecated option.  Use -mno-spe instead.
 359
 360 mspe=yes
 361 Target RejectNegative Alias(mspe)
 362 Deprecated option.  Use -mspe instead.
 363
 364 mdebug=
 365 Target RejectNegative Joined
 366 -mdebug=        Enable debug output.
 367
 368 mabi=altivec
 369 Target RejectNegative Var(rs6000_altivec_abi) Save
 370 Use the AltiVec ABI extensions.
 371
 372 mabi=no-altivec
 373 Target RejectNegative Var(rs6000_altivec_abi, 0)
 374 Do not use the AltiVec ABI extensions.
 375
 376 mabi=spe
 377 Target RejectNegative Var(rs6000_spe_abi) Save
 378 Use the SPE ABI extensions.
 379
 380 mabi=no-spe
 381 Target RejectNegative Var(rs6000_spe_abi, 0)
 382 Do not use the SPE ABI extensions.
 383
 384 mabi=elfv1
 385 Target RejectNegative Var(rs6000_elf_abi, 1) Save
 386 Use the ELFv1 ABI.
 387
 388 mabi=elfv2
 389 Target RejectNegative Var(rs6000_elf_abi, 2)
 390 Use the ELFv2 ABI.
 391
 392 ; These are here for testing during development only, do not document
 393 ; in the manual please.
 394
 395 ; If we want Darwin's struct-by-value-in-regs ABI.
 396 mabi=d64
 397 Target RejectNegative Undocumented Warn(using darwin64 ABI) Var(rs6000_darwin64_abi) Save
 398
 399 mabi=d32
 400 Target RejectNegative Undocumented Warn(using old darwin ABI) Var(rs6000_darwin64_abi, 0)
 401
 402 mabi=ieeelongdouble
 403 Target RejectNegative Undocumented Warn(using IEEE extended precision long double) Var(rs6000_ieeequad) Save
 404
 405 mabi=ibmlongdouble
 406 Target RejectNegative Undocumented Warn(using IBM extended precision long double) Var(rs6000_ieeequad, 0)
 407
 408 mcpu=
 409 Target RejectNegative Joined Var(rs6000_cpu_index) Init(-1) Enum(rs6000_cpu_opt_value) Save
 410 -mcpu=  Use features of and schedule code for given CPU.
 411
 412 mtune=
 413 Target RejectNegative Joined Var(rs6000_tune_index) Init(-1) Enum(rs6000_cpu_opt_value) Save
 414 -mtune= Schedule code for given CPU.
 415
 416 mtraceback=
 417 Target RejectNegative Joined Enum(rs6000_traceback_type) Var(rs6000_traceback)
 418 -mtraceback=    Select full, part, or no traceback table.
 419
 420 Enum
 421 Name(rs6000_traceback_type) Type(enum rs6000_traceback_type)
 422
 423 EnumValue
 424 Enum(rs6000_traceback_type) String(full) Value(traceback_full)
 425
 426 EnumValue
 427 Enum(rs6000_traceback_type) String(part) Value(traceback_part)
 428
 429 EnumValue
 430 Enum(rs6000_traceback_type) String(no) Value(traceback_none)
 431
 432 mlongcall
 433 Target Report Var(rs6000_default_long_calls) Save
 434 Avoid all range limits on call instructions.
 435
 436 mgen-cell-microcode
 437 Target Report Var(rs6000_gen_cell_microcode) Init(-1) Save
 438 Generate Cell microcode.
 439
 440 mwarn-cell-microcode
 441 Target Var(rs6000_warn_cell_microcode) Init(0) Warning Save
 442 Warn when a Cell microcoded instruction is emitted.
 443
 444 mwarn-altivec-long
 445 Target Var(rs6000_warn_altivec_long) Init(1) Save
 446 Warn about deprecated 'vector long ...' AltiVec type usage.
 447
 448 mfloat-gprs=
 449 Target RejectNegative Joined Enum(rs6000_float_gprs) Var(rs6000_float_gprs) Save
 450 -mfloat-gprs=   Select GPR floating point method.
 451
 452 Enum
 453 Name(rs6000_float_gprs) Type(unsigned char)
 454 Valid arguments to -mfloat-gprs=:
 455
 456 EnumValue
 457 Enum(rs6000_float_gprs) String(yes) Value(1)
 458
 459 EnumValue
 460 Enum(rs6000_float_gprs) String(single) Value(1)
 461
 462 EnumValue
 463 Enum(rs6000_float_gprs) String(double) Value(2)
 464
 465 EnumValue
 466 Enum(rs6000_float_gprs) String(no) Value(0)
 467
 468 mlong-double-
 469 Target RejectNegative Joined UInteger Var(rs6000_long_double_type_size) Save
 470 -mlong-double-<n>       Specify size of long double (64 or 128 bits).
 471
 472 mlra
 473 Target Report Var(rs6000_lra_flag) Init(0) Save
 474 Use LRA instead of reload.
 475
 476 msched-costly-dep=
 477 Target RejectNegative Joined Var(rs6000_sched_costly_dep_str)
 478 Determine which dependences between insns are considered costly.
 479
 480 minsert-sched-nops=
 481 Target RejectNegative Joined Var(rs6000_sched_insert_nops_str)
 482 Specify which post scheduling nop insertion scheme to apply.
 483
 484 malign-
 485 Target RejectNegative Joined Enum(rs6000_alignment_flags) Var(rs6000_alignment_flags)
 486 Specify alignment of structure fields default/natural.
 487
 488 Enum
 489 Name(rs6000_alignment_flags) Type(unsigned char)
 490 Valid arguments to -malign-:
 491
 492 EnumValue
 493 Enum(rs6000_alignment_flags) String(power) Value(MASK_ALIGN_POWER)
 494
 495 EnumValue
 496 Enum(rs6000_alignment_flags) String(natural) Value(MASK_ALIGN_NATURAL)
 497
 498 mprioritize-restricted-insns=
 499 Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority) Save
 500 Specify scheduling priority for dispatch slot restricted insns.
 501
 502 msingle-float
 503 Target RejectNegative Var(rs6000_single_float) Save
 504 Single-precision floating point unit.
 505
 506 mdouble-float
 507 Target RejectNegative Var(rs6000_double_float) Save
 508 Double-precision floating point unit.
 509
 510 msimple-fpu
 511 Target RejectNegative Var(rs6000_simple_fpu) Save
 512 Floating point unit does not support divide & sqrt.
 513
 514 mfpu=
 515 Target RejectNegative Joined Enum(fpu_type_t) Var(rs6000_fpu_type) Init(FPU_NONE)
 516 -mfpu=  Specify FP (sp, dp, sp-lite, dp-lite) (implies -mxilinx-fpu).
 517
 518 Enum
 519 Name(fpu_type_t) Type(enum fpu_type_t)
 520
 521 EnumValue
 522 Enum(fpu_type_t) String(none) Value(FPU_NONE)
 523
 524 EnumValue
 525 Enum(fpu_type_t) String(sp_lite) Value(FPU_SF_LITE)
 526
 527 EnumValue
 528 Enum(fpu_type_t) String(dp_lite) Value(FPU_DF_LITE)
 529
 530 EnumValue
 531 Enum(fpu_type_t) String(sp_full) Value(FPU_SF_FULL)
 532
 533 EnumValue
 534 Enum(fpu_type_t) String(dp_full) Value(FPU_DF_FULL)
 535
 536 mxilinx-fpu
 537 Target Var(rs6000_xilinx_fpu) Save
 538 Specify Xilinx FPU.
 539
 540 mpointers-to-nested-functions
 541 Target Report Var(TARGET_POINTERS_TO_NESTED_FUNCTIONS) Init(1) Save
 542 Use/do not use r11 to hold the static link in calls to functions via pointers.
 543
 544 msave-toc-indirect
 545 Target Report Mask(SAVE_TOC_INDIRECT) Var(rs6000_isa_flags)
 546 Control whether we save the TOC in the prologue for indirect calls or generate the save inline.
 547
 548 mvsx-timode
 549 Target Undocumented Mask(VSX_TIMODE) Var(rs6000_isa_flags)
 550 Allow 128-bit integers in VSX registers.
 551
 552 mpower8-fusion
 553 Target Report Mask(P8_FUSION) Var(rs6000_isa_flags)
 554 Fuse certain integer operations together for better performance on power8.
 555
 556 mpower8-fusion-sign
 557 Target Undocumented Mask(P8_FUSION_SIGN) Var(rs6000_isa_flags)
 558 Allow sign extension in fusion operations.
 559
 560 mpower8-vector
 561 Target Report Mask(P8_VECTOR) Var(rs6000_isa_flags)
 562 Use/do not use vector and scalar instructions added in ISA 2.07.
 563
 564 mcrypto
 565 Target Report Mask(CRYPTO) Var(rs6000_isa_flags)
 566 Use ISA 2.07 Category:Vector.AES and Category:Vector.SHA2 instructions.
 567
 568 mdirect-move
 569 Target Report Mask(DIRECT_MOVE) Var(rs6000_isa_flags)
 570 Use ISA 2.07 direct move between GPR & VSX register instructions.
 571
 572 mhtm
 573 Target Report Mask(HTM) Var(rs6000_isa_flags)
 574 Use ISA 2.07 transactional memory (HTM) instructions.
 575
 576 mquad-memory
 577 Target Report Mask(QUAD_MEMORY) Var(rs6000_isa_flags)
 578 Generate the quad word memory instructions (lq/stq).
 579
 580 mquad-memory-atomic
 581 Target Report Mask(QUAD_MEMORY_ATOMIC) Var(rs6000_isa_flags)
 582 Generate the quad word memory atomic instructions (lqarx/stqcx).
 583
 584 mcompat-align-parm
 585 Target Report Var(rs6000_compat_align_parm) Init(0) Save
 586 Generate aggregate parameter passing code with at most 64-bit alignment.
 587
 588 mupper-regs-df
 589 Target Report Mask(UPPER_REGS_DF) Var(rs6000_isa_flags)
 590 Allow double variables in upper registers with -mcpu=power7 or -mvsx.
 591
 592 mupper-regs-sf
 593 Target Report Mask(UPPER_REGS_SF) Var(rs6000_isa_flags)
 594 Allow float variables in upper registers with -mcpu=power8 or -mpower8-vector.
 595
 596 mupper-regs
 597 Target Report Var(TARGET_UPPER_REGS) Init(-1) Save
 598 Allow float/double variables in upper registers if cpu allows it.
 599
 600 moptimize-swaps
 601 Target Undocumented Var(rs6000_optimize_swaps) Init(1) Save
 602 Analyze and remove doubleword swaps from VSX computations.
 603
 604 mpower9-fusion
 605 Target Report Mask(P9_FUSION) Var(rs6000_isa_flags)
 606 Fuse certain operations together for better performance on power9.
 607
 608 mpower9-vector
 609 Target Report Mask(P9_VECTOR) Var(rs6000_isa_flags)
 610 Use/do not use vector and scalar instructions added in ISA 3.0.
 611
 612 mpower9-dform
 613 Target Undocumented Mask(P9_DFORM) Var(rs6000_isa_flags)
 614 Use/do not use vector and scalar instructions added in ISA 3.0.
 615
 616 mpower9-minmax
 617 Target Undocumented Mask(P9_MINMAX) Var(rs6000_isa_flags)
 618 Use/do not use the new min/max instructions defined in ISA 3.0.
 619
 620 mtoc-fusion
 621 Target Undocumented Mask(TOC_FUSION) Var(rs6000_isa_flags)
 622 Fuse medium/large code model toc references with the memory instruction.
 623
 624 mmodulo
 625 Target Report Mask(MODULO) Var(rs6000_isa_flags)
 626 Generate the integer modulo instructions.
 627
 628 mfloat128
 629 Target Report Mask(FLOAT128) Var(rs6000_isa_flags)
 630 Enable/disable IEEE 128-bit floating point via the __float128 keyword.
 631
 632 mfloat128-hardware
 633 Target Report Mask(FLOAT128_HW) Var(rs6000_isa_flags)
 634 Enable/disable using IEEE 128-bit floating point instructions.
 635
 636 mfloat128-convert
 637 Target Undocumented Mask(FLOAT128_CVT) Var(rs6000_isa_flags)
 638 Enable/disable default conversions between __float128 & long double.