gcc/config/rs6000/vector.md

   1 ;; Expander definitions for vector support between altivec & vsx.  No
   2 ;; instructions are in this file, this file provides the generic vector
   3 ;; expander, and the actual vector instructions will be in altivec.md and
   4 ;; vsx.md
   5
   6 ;; Copyright (C) 2009-2015 Free Software Foundation, Inc.
   7 ;; Contributed by Michael Meissner <meissner@linux.vnet.ibm.com>
   8
   9 ;; This file is part of GCC.
  10
  11 ;; GCC is free software; you can redistribute it and/or modify it
  12 ;; under the terms of the GNU General Public License as published
  13 ;; by the Free Software Foundation; either version 3, or (at your
  14 ;; option) any later version.
  15
  16 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  17 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  18 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  19 ;; License for more details.
  20
  21 ;; You should have received a copy of the GNU General Public License
  22 ;; along with GCC; see the file COPYING3.  If not see
  23 ;; <http://www.gnu.org/licenses/>.
  24
  25
  26 ;; Vector int modes
  27 (define_mode_iterator VEC_I [V16QI V8HI V4SI V2DI])
  28
  29 ;; Vector float modes
  30 (define_mode_iterator VEC_F [V4SF V2DF])
  31
  32 ;; Vector arithmetic modes
  33 (define_mode_iterator VEC_A [V16QI V8HI V4SI V2DI V4SF V2DF])
  34
  35 ;; Vector modes that need alginment via permutes
  36 (define_mode_iterator VEC_K [V16QI V8HI V4SI V4SF])
  37
  38 ;; Vector logical modes
  39 (define_mode_iterator VEC_L [V16QI V8HI V4SI V2DI V4SF V2DF V1TI TI])
  40
  41 ;; Vector modes for moves.  Don't do TImode here.
  42 (define_mode_iterator VEC_M [V16QI V8HI V4SI V2DI V4SF V2DF V1TI])
  43
  44 ;; Vector modes for types that don't need a realignment under VSX
  45 (define_mode_iterator VEC_N [V4SI V4SF V2DI V2DF V1TI])
  46
  47 ;; Vector comparison modes
  48 (define_mode_iterator VEC_C [V16QI V8HI V4SI V2DI V4SF V2DF])
  49
  50 ;; Vector init/extract modes
  51 (define_mode_iterator VEC_E [V16QI V8HI V4SI V2DI V4SF V2DF])
  52
  53 ;; Vector modes for 64-bit base types
  54 (define_mode_iterator VEC_64 [V2DI V2DF])
  55
  56 ;; Base type from vector mode
  57 (define_mode_attr VEC_base [(V16QI "QI")
  58                             (V8HI  "HI")
  59                             (V4SI  "SI")
  60                             (V2DI  "DI")
  61                             (V4SF  "SF")
  62                             (V2DF  "DF")
  63                             (V1TI  "TI")
  64                             (TI    "TI")])
  65
  66 ;; Same size integer type for floating point data
  67 (define_mode_attr VEC_int [(V4SF  "v4si")
  68                            (V2DF  "v2di")])
  69
  70 (define_mode_attr VEC_INT [(V4SF  "V4SI")
  71                            (V2DF  "V2DI")])
  72
  73 ;; constants for unspec
  74 (define_c_enum "unspec" [UNSPEC_PREDICATE
  75                          UNSPEC_REDUC])
  76
  77 ;; Vector reduction code iterators
  78 (define_code_iterator VEC_reduc [plus smin smax])
  79
  80 (define_code_attr VEC_reduc_name [(plus "splus")
  81                                   (smin "smin")
  82                                   (smax "smax")])
  83
  84 (define_code_attr VEC_reduc_rtx [(plus "add")
  85                                  (smin "smin")
  86                                  (smax "smax")])
  87
  88 \f
  89 ;; Vector move instructions.  Little-endian VSX loads and stores require
  90 ;; special handling to circumvent "element endianness."
  91 (define_expand "mov<mode>"
  92   [(set (match_operand:VEC_M 0 "nonimmediate_operand" "")
  93         (match_operand:VEC_M 1 "any_operand" ""))]
  94   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
  95 {
  96   if (can_create_pseudo_p ())
  97     {
  98       if (CONSTANT_P (operands[1])
  99           && !easy_vector_constant (operands[1], <MODE>mode))
 100         operands[1] = force_const_mem (<MODE>mode, operands[1]);
 101
 102       else if (!vlogical_operand (operands[0], <MODE>mode)
 103                && !vlogical_operand (operands[1], <MODE>mode))
 104         operands[1] = force_reg (<MODE>mode, operands[1]);
 105     }
 106   if (!BYTES_BIG_ENDIAN
 107       && VECTOR_MEM_VSX_P (<MODE>mode)
 108       && !gpr_or_gpr_p (operands[0], operands[1])
 109       && (memory_operand (operands[0], <MODE>mode)
 110           ^ memory_operand (operands[1], <MODE>mode)))
 111     {
 112       rs6000_emit_le_vsx_move (operands[0], operands[1], <MODE>mode);
 113       DONE;
 114     }
 115 })
 116
 117 ;; Generic vector floating point load/store instructions.  These will match
 118 ;; insns defined in vsx.md or altivec.md depending on the switches.
 119 (define_expand "vector_load_<mode>"
 120   [(set (match_operand:VEC_M 0 "vfloat_operand" "")
 121         (match_operand:VEC_M 1 "memory_operand" ""))]
 122   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
 123   "")
 124
 125 (define_expand "vector_store_<mode>"
 126   [(set (match_operand:VEC_M 0 "memory_operand" "")
 127         (match_operand:VEC_M 1 "vfloat_operand" ""))]
 128   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
 129   "")
 130
 131 ;; Splits if a GPR register was chosen for the move
 132 (define_split
 133   [(set (match_operand:VEC_L 0 "nonimmediate_operand" "")
 134         (match_operand:VEC_L 1 "input_operand" ""))]
 135   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)
 136    && reload_completed
 137    && gpr_or_gpr_p (operands[0], operands[1])
 138    && !direct_move_p (operands[0], operands[1])
 139    && !quad_load_store_p (operands[0], operands[1])"
 140   [(pc)]
 141 {
 142   rs6000_split_multireg_move (operands[0], operands[1]);
 143   DONE;
 144 })
 145
 146 ;; Vector floating point load/store instructions that uses the Altivec
 147 ;; instructions even if we are compiling for VSX, since the Altivec
 148 ;; instructions silently ignore the bottom 3 bits of the address, and VSX does
 149 ;; not.
 150 (define_expand "vector_altivec_load_<mode>"
 151   [(set (match_operand:VEC_M 0 "vfloat_operand" "")
 152         (match_operand:VEC_M 1 "memory_operand" ""))]
 153   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
 154   "
 155 {
 156   gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode));
 157
 158   if (VECTOR_MEM_VSX_P (<MODE>mode))
 159     {
 160       operands[1] = rs6000_address_for_altivec (operands[1]);
 161       emit_insn (gen_altivec_lvx_<mode> (operands[0], operands[1]));
 162       DONE;
 163     }
 164 }")
 165
 166 (define_expand "vector_altivec_store_<mode>"
 167   [(set (match_operand:VEC_M 0 "memory_operand" "")
 168         (match_operand:VEC_M 1 "vfloat_operand" ""))]
 169   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
 170   "
 171 {
 172   gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode));
 173
 174   if (VECTOR_MEM_VSX_P (<MODE>mode))
 175     {
 176       operands[0] = rs6000_address_for_altivec (operands[0]);
 177       emit_insn (gen_altivec_stvx_<mode> (operands[0], operands[1]));
 178       DONE;
 179     }
 180 }")
 181
 182
 183 \f
 184 ;; Generic floating point vector arithmetic support
 185 (define_expand "add<mode>3"
 186   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 187         (plus:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
 188                     (match_operand:VEC_F 2 "vfloat_operand" "")))]
 189   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 190   "")
 191
 192 (define_expand "sub<mode>3"
 193   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 194         (minus:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
 195                      (match_operand:VEC_F 2 "vfloat_operand" "")))]
 196   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 197   "")
 198
 199 (define_expand "mul<mode>3"
 200   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 201         (mult:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
 202                     (match_operand:VEC_F 2 "vfloat_operand" "")))]
 203   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 204 {
 205   if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
 206     {
 207       emit_insn (gen_altivec_mulv4sf3 (operands[0], operands[1], operands[2]));
 208       DONE;
 209     }
 210 })
 211
 212 (define_expand "div<mode>3"
 213   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 214         (div:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
 215                    (match_operand:VEC_F 2 "vfloat_operand" "")))]
 216   "VECTOR_UNIT_VSX_P (<MODE>mode)"
 217   "")
 218
 219 (define_expand "neg<mode>2"
 220   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 221         (neg:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
 222   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 223   "
 224 {
 225   if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
 226     {
 227       emit_insn (gen_altivec_negv4sf2 (operands[0], operands[1]));
 228       DONE;
 229     }
 230 }")
 231
 232 (define_expand "abs<mode>2"
 233   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 234         (abs:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
 235   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 236   "
 237 {
 238   if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
 239     {
 240       emit_insn (gen_altivec_absv4sf2 (operands[0], operands[1]));
 241       DONE;
 242     }
 243 }")
 244
 245 (define_expand "smin<mode>3"
 246   [(set (match_operand:VEC_F 0 "register_operand" "")
 247         (smin:VEC_F (match_operand:VEC_F 1 "register_operand" "")
 248                     (match_operand:VEC_F 2 "register_operand" "")))]
 249   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 250   "")
 251
 252 (define_expand "smax<mode>3"
 253   [(set (match_operand:VEC_F 0 "register_operand" "")
 254         (smax:VEC_F (match_operand:VEC_F 1 "register_operand" "")
 255                     (match_operand:VEC_F 2 "register_operand" "")))]
 256   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 257   "")
 258
 259
 260 (define_expand "sqrt<mode>2"
 261   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 262         (sqrt:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
 263   "VECTOR_UNIT_VSX_P (<MODE>mode)"
 264   "")
 265
 266 (define_expand "rsqrte<mode>2"
 267   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 268         (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")]
 269                       UNSPEC_RSQRT))]
 270   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 271   "")
 272
 273 (define_expand "re<mode>2"
 274   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 275         (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "f")]
 276                       UNSPEC_FRES))]
 277   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 278   "")
 279
 280 (define_expand "ftrunc<mode>2"
 281   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 282         (fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
 283   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 284   "")
 285
 286 (define_expand "vector_ceil<mode>2"
 287   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 288         (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")]
 289                       UNSPEC_FRIP))]
 290   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 291   "")
 292
 293 (define_expand "vector_floor<mode>2"
 294   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 295         (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")]
 296                       UNSPEC_FRIM))]
 297   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 298   "")
 299
 300 (define_expand "vector_btrunc<mode>2"
 301   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 302         (fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
 303   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 304   "")
 305
 306 (define_expand "vector_copysign<mode>3"
 307   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 308         (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")
 309                        (match_operand:VEC_F 2 "vfloat_operand" "")] UNSPEC_COPYSIGN))]
 310   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 311   "
 312 {
 313   if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
 314     {
 315       emit_insn (gen_altivec_copysign_v4sf3 (operands[0], operands[1],
 316                                              operands[2]));
 317       DONE;
 318     }
 319 }")
 320
 321 \f
 322 ;; Vector comparisons
 323 (define_expand "vcond<mode><mode>"
 324   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 325         (if_then_else:VEC_F
 326          (match_operator 3 "comparison_operator"
 327                          [(match_operand:VEC_F 4 "vfloat_operand" "")
 328                           (match_operand:VEC_F 5 "vfloat_operand" "")])
 329          (match_operand:VEC_F 1 "vfloat_operand" "")
 330          (match_operand:VEC_F 2 "vfloat_operand" "")))]
 331   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 332   "
 333 {
 334   if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
 335                                     operands[3], operands[4], operands[5]))
 336     DONE;
 337   else
 338     FAIL;
 339 }")
 340
 341 (define_expand "vcond<mode><mode>"
 342   [(set (match_operand:VEC_I 0 "vint_operand" "")
 343         (if_then_else:VEC_I
 344          (match_operator 3 "comparison_operator"
 345                          [(match_operand:VEC_I 4 "vint_operand" "")
 346                           (match_operand:VEC_I 5 "vint_operand" "")])
 347          (match_operand:VEC_I 1 "vint_operand" "")
 348          (match_operand:VEC_I 2 "vint_operand" "")))]
 349   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 350   "
 351 {
 352   if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
 353                                     operands[3], operands[4], operands[5]))
 354     DONE;
 355   else
 356     FAIL;
 357 }")
 358
 359 (define_expand "vcondv4sfv4si"
 360   [(set (match_operand:V4SF 0 "vfloat_operand" "")
 361         (if_then_else:V4SF
 362          (match_operator 3 "comparison_operator"
 363                          [(match_operand:V4SI 4 "vint_operand" "")
 364                           (match_operand:V4SI 5 "vint_operand" "")])
 365          (match_operand:V4SF 1 "vfloat_operand" "")
 366          (match_operand:V4SF 2 "vfloat_operand" "")))]
 367   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
 368    && VECTOR_UNIT_ALTIVEC_P (V4SImode)"
 369   "
 370 {
 371   if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
 372                                     operands[3], operands[4], operands[5]))
 373     DONE;
 374   else
 375     FAIL;
 376 }")
 377
 378 (define_expand "vcondv4siv4sf"
 379   [(set (match_operand:V4SI 0 "vint_operand" "")
 380         (if_then_else:V4SI
 381          (match_operator 3 "comparison_operator"
 382                          [(match_operand:V4SF 4 "vfloat_operand" "")
 383                           (match_operand:V4SF 5 "vfloat_operand" "")])
 384          (match_operand:V4SI 1 "vint_operand" "")
 385          (match_operand:V4SI 2 "vint_operand" "")))]
 386   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
 387    && VECTOR_UNIT_ALTIVEC_P (V4SImode)"
 388   "
 389 {
 390   if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
 391                                     operands[3], operands[4], operands[5]))
 392     DONE;
 393   else
 394     FAIL;
 395 }")
 396
 397 (define_expand "vcondu<mode><mode>"
 398   [(set (match_operand:VEC_I 0 "vint_operand" "")
 399         (if_then_else:VEC_I
 400          (match_operator 3 "comparison_operator"
 401                          [(match_operand:VEC_I 4 "vint_operand" "")
 402                           (match_operand:VEC_I 5 "vint_operand" "")])
 403          (match_operand:VEC_I 1 "vint_operand" "")
 404          (match_operand:VEC_I 2 "vint_operand" "")))]
 405   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 406   "
 407 {
 408   if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
 409                                     operands[3], operands[4], operands[5]))
 410     DONE;
 411   else
 412     FAIL;
 413 }")
 414
 415 (define_expand "vconduv4sfv4si"
 416   [(set (match_operand:V4SF 0 "vfloat_operand" "")
 417         (if_then_else:V4SF
 418          (match_operator 3 "comparison_operator"
 419                          [(match_operand:V4SI 4 "vint_operand" "")
 420                           (match_operand:V4SI 5 "vint_operand" "")])
 421          (match_operand:V4SF 1 "vfloat_operand" "")
 422          (match_operand:V4SF 2 "vfloat_operand" "")))]
 423   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
 424    && VECTOR_UNIT_ALTIVEC_P (V4SImode)"
 425   "
 426 {
 427   if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
 428                                     operands[3], operands[4], operands[5]))
 429     DONE;
 430   else
 431     FAIL;
 432 }")
 433
 434 (define_expand "vector_eq<mode>"
 435   [(set (match_operand:VEC_C 0 "vlogical_operand" "")
 436         (eq:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "")
 437                   (match_operand:VEC_C 2 "vlogical_operand" "")))]
 438   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 439   "")
 440
 441 (define_expand "vector_gt<mode>"
 442   [(set (match_operand:VEC_C 0 "vlogical_operand" "")
 443         (gt:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "")
 444                   (match_operand:VEC_C 2 "vlogical_operand" "")))]
 445   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 446   "")
 447
 448 (define_expand "vector_ge<mode>"
 449   [(set (match_operand:VEC_C 0 "vlogical_operand" "")
 450         (ge:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "")
 451                   (match_operand:VEC_C 2 "vlogical_operand" "")))]
 452   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 453   "")
 454
 455 (define_expand "vector_gtu<mode>"
 456   [(set (match_operand:VEC_I 0 "vint_operand" "")
 457         (gtu:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
 458                    (match_operand:VEC_I 2 "vint_operand" "")))]
 459   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 460   "")
 461
 462 (define_expand "vector_geu<mode>"
 463   [(set (match_operand:VEC_I 0 "vint_operand" "")
 464         (geu:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
 465                    (match_operand:VEC_I 2 "vint_operand" "")))]
 466   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 467   "")
 468
 469 (define_insn_and_split "*vector_uneq<mode>"
 470   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 471         (uneq:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
 472                     (match_operand:VEC_F 2 "vfloat_operand" "")))]
 473   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 474   "#"
 475   ""
 476   [(set (match_dup 3)
 477         (gt:VEC_F (match_dup 1)
 478                   (match_dup 2)))
 479    (set (match_dup 4)
 480         (gt:VEC_F (match_dup 2)
 481                   (match_dup 1)))
 482    (set (match_dup 0)
 483         (not:VEC_F (ior:VEC_F (match_dup 3)
 484                               (match_dup 4))))]
 485   "
 486 {
 487   operands[3] = gen_reg_rtx (<MODE>mode);
 488   operands[4] = gen_reg_rtx (<MODE>mode);
 489 }")
 490
 491 (define_insn_and_split "*vector_ltgt<mode>"
 492   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 493         (ltgt:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
 494                     (match_operand:VEC_F 2 "vfloat_operand" "")))]
 495   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 496   "#"
 497   ""
 498   [(set (match_dup 3)
 499         (gt:VEC_F (match_dup 1)
 500                   (match_dup 2)))
 501    (set (match_dup 4)
 502         (gt:VEC_F (match_dup 2)
 503                   (match_dup 1)))
 504    (set (match_dup 0)
 505         (ior:VEC_F (match_dup 3)
 506                    (match_dup 4)))]
 507   "
 508 {
 509   operands[3] = gen_reg_rtx (<MODE>mode);
 510   operands[4] = gen_reg_rtx (<MODE>mode);
 511 }")
 512
 513 (define_insn_and_split "*vector_ordered<mode>"
 514   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 515         (ordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
 516                        (match_operand:VEC_F 2 "vfloat_operand" "")))]
 517   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 518   "#"
 519   ""
 520   [(set (match_dup 3)
 521         (ge:VEC_F (match_dup 1)
 522                   (match_dup 2)))
 523    (set (match_dup 4)
 524         (ge:VEC_F (match_dup 2)
 525                   (match_dup 1)))
 526    (set (match_dup 0)
 527         (ior:VEC_F (match_dup 3)
 528                    (match_dup 4)))]
 529   "
 530 {
 531   operands[3] = gen_reg_rtx (<MODE>mode);
 532   operands[4] = gen_reg_rtx (<MODE>mode);
 533 }")
 534
 535 (define_insn_and_split "*vector_unordered<mode>"
 536   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 537         (unordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
 538                          (match_operand:VEC_F 2 "vfloat_operand" "")))]
 539   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 540   "#"
 541   ""
 542   [(set (match_dup 3)
 543         (ge:VEC_F (match_dup 1)
 544                   (match_dup 2)))
 545    (set (match_dup 4)
 546         (ge:VEC_F (match_dup 2)
 547                   (match_dup 1)))
 548    (set (match_dup 0)
 549         (and:VEC_F (not:VEC_F (match_dup 3))
 550                    (not:VEC_F (match_dup 4))))]
 551   "
 552 {
 553   operands[3] = gen_reg_rtx (<MODE>mode);
 554   operands[4] = gen_reg_rtx (<MODE>mode);
 555 }")
 556
 557 ;; Note the arguments for __builtin_altivec_vsel are op2, op1, mask
 558 ;; which is in the reverse order that we want
 559 (define_expand "vector_select_<mode>"
 560   [(set (match_operand:VEC_L 0 "vlogical_operand" "")
 561         (if_then_else:VEC_L
 562          (ne:CC (match_operand:VEC_L 3 "vlogical_operand" "")
 563                 (match_dup 4))
 564          (match_operand:VEC_L 2 "vlogical_operand" "")
 565          (match_operand:VEC_L 1 "vlogical_operand" "")))]
 566   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 567   "operands[4] = CONST0_RTX (<MODE>mode);")
 568
 569 (define_expand "vector_select_<mode>_uns"
 570   [(set (match_operand:VEC_L 0 "vlogical_operand" "")
 571         (if_then_else:VEC_L
 572          (ne:CCUNS (match_operand:VEC_L 3 "vlogical_operand" "")
 573                    (match_dup 4))
 574          (match_operand:VEC_L 2 "vlogical_operand" "")
 575          (match_operand:VEC_L 1 "vlogical_operand" "")))]
 576   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 577   "operands[4] = CONST0_RTX (<MODE>mode);")
 578
 579 ;; Expansions that compare vectors producing a vector result and a predicate,
 580 ;; setting CR6 to indicate a combined status
 581 (define_expand "vector_eq_<mode>_p"
 582   [(parallel
 583     [(set (reg:CC 74)
 584           (unspec:CC [(eq:CC (match_operand:VEC_A 1 "vlogical_operand" "")
 585                              (match_operand:VEC_A 2 "vlogical_operand" ""))]
 586                      UNSPEC_PREDICATE))
 587      (set (match_operand:VEC_A 0 "vlogical_operand" "")
 588           (eq:VEC_A (match_dup 1)
 589                     (match_dup 2)))])]
 590   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 591   "")
 592
 593 (define_expand "vector_gt_<mode>_p"
 594   [(parallel
 595     [(set (reg:CC 74)
 596           (unspec:CC [(gt:CC (match_operand:VEC_A 1 "vlogical_operand" "")
 597                              (match_operand:VEC_A 2 "vlogical_operand" ""))]
 598                      UNSPEC_PREDICATE))
 599      (set (match_operand:VEC_A 0 "vlogical_operand" "")
 600           (gt:VEC_A (match_dup 1)
 601                     (match_dup 2)))])]
 602   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 603   "")
 604
 605 (define_expand "vector_ge_<mode>_p"
 606   [(parallel
 607     [(set (reg:CC 74)
 608           (unspec:CC [(ge:CC (match_operand:VEC_F 1 "vfloat_operand" "")
 609                              (match_operand:VEC_F 2 "vfloat_operand" ""))]
 610                      UNSPEC_PREDICATE))
 611      (set (match_operand:VEC_F 0 "vfloat_operand" "")
 612           (ge:VEC_F (match_dup 1)
 613                     (match_dup 2)))])]
 614   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 615   "")
 616
 617 (define_expand "vector_gtu_<mode>_p"
 618   [(parallel
 619     [(set (reg:CC 74)
 620           (unspec:CC [(gtu:CC (match_operand:VEC_I 1 "vint_operand" "")
 621                               (match_operand:VEC_I 2 "vint_operand" ""))]
 622                      UNSPEC_PREDICATE))
 623      (set (match_operand:VEC_I 0 "vlogical_operand" "")
 624           (gtu:VEC_I (match_dup 1)
 625                      (match_dup 2)))])]
 626   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 627   "")
 628
 629 ;; AltiVec/VSX predicates.
 630
 631 (define_expand "cr6_test_for_zero"
 632   [(set (match_operand:SI 0 "register_operand" "=r")
 633         (eq:SI (reg:CC 74)
 634                (const_int 0)))]
 635   "TARGET_ALTIVEC || TARGET_VSX"
 636   "")
 637
 638 (define_expand "cr6_test_for_zero_reverse"
 639   [(set (match_operand:SI 0 "register_operand" "=r")
 640         (eq:SI (reg:CC 74)
 641                (const_int 0)))
 642    (set (match_dup 0)
 643         (xor:SI (match_dup 0)
 644                 (const_int 1)))]
 645   "TARGET_ALTIVEC || TARGET_VSX"
 646   "")
 647
 648 (define_expand "cr6_test_for_lt"
 649   [(set (match_operand:SI 0 "register_operand" "=r")
 650         (lt:SI (reg:CC 74)
 651                (const_int 0)))]
 652   "TARGET_ALTIVEC || TARGET_VSX"
 653   "")
 654
 655 (define_expand "cr6_test_for_lt_reverse"
 656   [(set (match_operand:SI 0 "register_operand" "=r")
 657         (lt:SI (reg:CC 74)
 658                (const_int 0)))
 659    (set (match_dup 0)
 660         (xor:SI (match_dup 0)
 661                 (const_int 1)))]
 662   "TARGET_ALTIVEC || TARGET_VSX"
 663   "")
 664
 665 \f
 666 ;; Vector count leading zeros
 667 (define_expand "clz<mode>2"
 668   [(set (match_operand:VEC_I 0 "register_operand" "")
 669         (clz:VEC_I (match_operand:VEC_I 1 "register_operand" "")))]
 670   "TARGET_P8_VECTOR")
 671
 672 ;; Vector population count
 673 (define_expand "popcount<mode>2"
 674   [(set (match_operand:VEC_I 0 "register_operand" "")
 675         (popcount:VEC_I (match_operand:VEC_I 1 "register_operand" "")))]
 676   "TARGET_P8_VECTOR")
 677
 678 \f
 679 ;; Same size conversions
 680 (define_expand "float<VEC_int><mode>2"
 681   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 682         (float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand" "")))]
 683   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 684   "
 685 {
 686   if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
 687     {
 688       emit_insn (gen_altivec_vcfsx (operands[0], operands[1], const0_rtx));
 689       DONE;
 690     }
 691 }")
 692
 693 (define_expand "floatuns<VEC_int><mode>2"
 694   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 695         (unsigned_float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand" "")))]
 696   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 697   "
 698 {
 699   if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
 700     {
 701       emit_insn (gen_altivec_vcfux (operands[0], operands[1], const0_rtx));
 702       DONE;
 703     }
 704 }")
 705
 706 (define_expand "fix_trunc<mode><VEC_int>2"
 707   [(set (match_operand:<VEC_INT> 0 "vint_operand" "")
 708         (fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand" "")))]
 709   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 710   "
 711 {
 712   if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
 713     {
 714       emit_insn (gen_altivec_vctsxs (operands[0], operands[1], const0_rtx));
 715       DONE;
 716     }
 717 }")
 718
 719 (define_expand "fixuns_trunc<mode><VEC_int>2"
 720   [(set (match_operand:<VEC_INT> 0 "vint_operand" "")
 721         (unsigned_fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand" "")))]
 722   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 723   "
 724 {
 725   if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
 726     {
 727       emit_insn (gen_altivec_vctuxs (operands[0], operands[1], const0_rtx));
 728       DONE;
 729     }
 730 }")
 731
 732 \f
 733 ;; Vector initialization, set, extract
 734 (define_expand "vec_init<mode>"
 735   [(match_operand:VEC_E 0 "vlogical_operand" "")
 736    (match_operand:VEC_E 1 "" "")]
 737   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
 738 {
 739   rs6000_expand_vector_init (operands[0], operands[1]);
 740   DONE;
 741 })
 742
 743 (define_expand "vec_set<mode>"
 744   [(match_operand:VEC_E 0 "vlogical_operand" "")
 745    (match_operand:<VEC_base> 1 "register_operand" "")
 746    (match_operand 2 "const_int_operand" "")]
 747   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
 748 {
 749   rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
 750   DONE;
 751 })
 752
 753 (define_expand "vec_extract<mode>"
 754   [(match_operand:<VEC_base> 0 "register_operand" "")
 755    (match_operand:VEC_E 1 "vlogical_operand" "")
 756    (match_operand 2 "const_int_operand" "")]
 757   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
 758 {
 759   rs6000_expand_vector_extract (operands[0], operands[1],
 760                                 INTVAL (operands[2]));
 761   DONE;
 762 })
 763 \f
 764 ;; Convert double word types to single word types
 765 (define_expand "vec_pack_trunc_v2df"
 766   [(match_operand:V4SF 0 "vfloat_operand" "")
 767    (match_operand:V2DF 1 "vfloat_operand" "")
 768    (match_operand:V2DF 2 "vfloat_operand" "")]
 769   "VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
 770 {
 771   rtx r1 = gen_reg_rtx (V4SFmode);
 772   rtx r2 = gen_reg_rtx (V4SFmode);
 773
 774   emit_insn (gen_vsx_xvcvdpsp (r1, operands[1]));
 775   emit_insn (gen_vsx_xvcvdpsp (r2, operands[2]));
 776   rs6000_expand_extract_even (operands[0], r1, r2);
 777   DONE;
 778 })
 779
 780 (define_expand "vec_pack_sfix_trunc_v2df"
 781   [(match_operand:V4SI 0 "vint_operand" "")
 782    (match_operand:V2DF 1 "vfloat_operand" "")
 783    (match_operand:V2DF 2 "vfloat_operand" "")]
 784   "VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
 785 {
 786   rtx r1 = gen_reg_rtx (V4SImode);
 787   rtx r2 = gen_reg_rtx (V4SImode);
 788
 789   emit_insn (gen_vsx_xvcvdpsxws (r1, operands[1]));
 790   emit_insn (gen_vsx_xvcvdpsxws (r2, operands[2]));
 791   rs6000_expand_extract_even (operands[0], r1, r2);
 792   DONE;
 793 })
 794
 795 (define_expand "vec_pack_ufix_trunc_v2df"
 796   [(match_operand:V4SI 0 "vint_operand" "")
 797    (match_operand:V2DF 1 "vfloat_operand" "")
 798    (match_operand:V2DF 2 "vfloat_operand" "")]
 799   "VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
 800 {
 801   rtx r1 = gen_reg_rtx (V4SImode);
 802   rtx r2 = gen_reg_rtx (V4SImode);
 803
 804   emit_insn (gen_vsx_xvcvdpuxws (r1, operands[1]));
 805   emit_insn (gen_vsx_xvcvdpuxws (r2, operands[2]));
 806   rs6000_expand_extract_even (operands[0], r1, r2);
 807   DONE;
 808 })
 809
 810 ;; Convert single word types to double word
 811 (define_expand "vec_unpacks_hi_v4sf"
 812   [(match_operand:V2DF 0 "vfloat_operand" "")
 813    (match_operand:V4SF 1 "vfloat_operand" "")]
 814   "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
 815 {
 816   rtx reg = gen_reg_rtx (V4SFmode);
 817
 818   rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN);
 819   emit_insn (gen_vsx_xvcvspdp (operands[0], reg));
 820   DONE;
 821 })
 822
 823 (define_expand "vec_unpacks_lo_v4sf"
 824   [(match_operand:V2DF 0 "vfloat_operand" "")
 825    (match_operand:V4SF 1 "vfloat_operand" "")]
 826   "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
 827 {
 828   rtx reg = gen_reg_rtx (V4SFmode);
 829
 830   rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN);
 831   emit_insn (gen_vsx_xvcvspdp (operands[0], reg));
 832   DONE;
 833 })
 834
 835 (define_expand "vec_unpacks_float_hi_v4si"
 836   [(match_operand:V2DF 0 "vfloat_operand" "")
 837    (match_operand:V4SI 1 "vint_operand" "")]
 838   "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
 839 {
 840   rtx reg = gen_reg_rtx (V4SImode);
 841
 842   rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN);
 843   emit_insn (gen_vsx_xvcvsxwdp (operands[0], reg));
 844   DONE;
 845 })
 846
 847 (define_expand "vec_unpacks_float_lo_v4si"
 848   [(match_operand:V2DF 0 "vfloat_operand" "")
 849    (match_operand:V4SI 1 "vint_operand" "")]
 850   "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
 851 {
 852   rtx reg = gen_reg_rtx (V4SImode);
 853
 854   rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN);
 855   emit_insn (gen_vsx_xvcvsxwdp (operands[0], reg));
 856   DONE;
 857 })
 858
 859 (define_expand "vec_unpacku_float_hi_v4si"
 860   [(match_operand:V2DF 0 "vfloat_operand" "")
 861    (match_operand:V4SI 1 "vint_operand" "")]
 862   "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
 863 {
 864   rtx reg = gen_reg_rtx (V4SImode);
 865
 866   rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN);
 867   emit_insn (gen_vsx_xvcvuxwdp (operands[0], reg));
 868   DONE;
 869 })
 870
 871 (define_expand "vec_unpacku_float_lo_v4si"
 872   [(match_operand:V2DF 0 "vfloat_operand" "")
 873    (match_operand:V4SI 1 "vint_operand" "")]
 874   "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
 875 {
 876   rtx reg = gen_reg_rtx (V4SImode);
 877
 878   rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN);
 879   emit_insn (gen_vsx_xvcvuxwdp (operands[0], reg));
 880   DONE;
 881 })
 882
 883 \f
 884 ;; Align vector loads with a permute.
 885 (define_expand "vec_realign_load_<mode>"
 886   [(match_operand:VEC_K 0 "vlogical_operand" "")
 887    (match_operand:VEC_K 1 "vlogical_operand" "")
 888    (match_operand:VEC_K 2 "vlogical_operand" "")
 889    (match_operand:V16QI 3 "vlogical_operand" "")]
 890   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
 891 {
 892   if (BYTES_BIG_ENDIAN)
 893     emit_insn (gen_altivec_vperm_<mode> (operands[0], operands[1],
 894                                          operands[2], operands[3]));
 895   else
 896     {
 897       /* We have changed lvsr to lvsl, so to complete the transformation
 898          of vperm for LE, we must swap the inputs.  */
 899       rtx unspec = gen_rtx_UNSPEC (<MODE>mode,
 900                                    gen_rtvec (3, operands[2],
 901                                               operands[1], operands[3]),
 902                                    UNSPEC_VPERM);
 903       emit_move_insn (operands[0], unspec);
 904     }
 905   DONE;
 906 })
 907
 908 ;; Under VSX, vectors of 4/8 byte alignments do not need to be aligned
 909 ;; since the load already handles it.
 910 (define_expand "movmisalign<mode>"
 911  [(set (match_operand:VEC_N 0 "nonimmediate_operand" "")
 912        (match_operand:VEC_N 1 "any_operand" ""))]
 913  "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_ALLOW_MOVMISALIGN"
 914  "")
 915
 916 ;; Vector shift right in bits. Currently supported ony for shift
 917 ;; amounts that can be expressed as byte shifts (divisible by 8).
 918 ;; General shift amounts can be supported using vsro + vsr. We're
 919 ;; not expecting to see these yet (the vectorizer currently
 920 ;; generates only shifts by a whole number of vector elements).
 921 (define_expand "vec_shr_<mode>"
 922   [(match_operand:VEC_L 0 "vlogical_operand" "")
 923    (match_operand:VEC_L 1 "vlogical_operand" "")
 924    (match_operand:QI 2 "reg_or_short_operand" "")]
 925   "TARGET_ALTIVEC"
 926   "
 927 {
 928   rtx bitshift = operands[2];
 929   rtx shift;
 930   rtx insn;
 931   HOST_WIDE_INT bitshift_val;
 932   HOST_WIDE_INT byteshift_val;
 933
 934   if (! CONSTANT_P (bitshift))
 935     FAIL;
 936   bitshift_val = INTVAL (bitshift);
 937   if (bitshift_val & 0x7)
 938     FAIL;
 939   byteshift_val = (bitshift_val >> 3);
 940   if (!BYTES_BIG_ENDIAN)
 941     byteshift_val = 16 - byteshift_val;
 942   if (TARGET_VSX && (byteshift_val & 0x3) == 0)
 943     {
 944       shift = gen_rtx_CONST_INT (QImode, byteshift_val >> 2);
 945       insn = gen_vsx_xxsldwi_<mode> (operands[0], operands[1], operands[1],
 946                                      shift);
 947     }
 948   else
 949     {
 950       shift = gen_rtx_CONST_INT (QImode, byteshift_val);
 951       insn = gen_altivec_vsldoi_<mode> (operands[0], operands[1], operands[1],
 952                                         shift);
 953     }
 954
 955   emit_insn (insn);
 956   DONE;
 957 }")
 958
 959 ;; Expanders for rotate each element in a vector
 960 (define_expand "vrotl<mode>3"
 961   [(set (match_operand:VEC_I 0 "vint_operand" "")
 962         (rotate:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
 963                       (match_operand:VEC_I 2 "vint_operand" "")))]
 964   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 965   "")
 966
 967 ;; Expanders for arithmetic shift left on each vector element
 968 (define_expand "vashl<mode>3"
 969   [(set (match_operand:VEC_I 0 "vint_operand" "")
 970         (ashift:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
 971                       (match_operand:VEC_I 2 "vint_operand" "")))]
 972   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 973   "")
 974
 975 ;; Expanders for logical shift right on each vector element
 976 (define_expand "vlshr<mode>3"
 977   [(set (match_operand:VEC_I 0 "vint_operand" "")
 978         (lshiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
 979                         (match_operand:VEC_I 2 "vint_operand" "")))]
 980   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 981   "")
 982
 983 ;; Expanders for arithmetic shift right on each vector element
 984 (define_expand "vashr<mode>3"
 985   [(set (match_operand:VEC_I 0 "vint_operand" "")
 986         (ashiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
 987                         (match_operand:VEC_I 2 "vint_operand" "")))]
 988   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 989   "")
 990 \f
 991 ;; Vector reduction expanders for VSX
 992
 993 (define_expand "reduc_<VEC_reduc_name>_v2df"
 994   [(parallel [(set (match_operand:V2DF 0 "vfloat_operand" "")
 995                    (VEC_reduc:V2DF
 996                     (vec_concat:V2DF
 997                      (vec_select:DF
 998                       (match_operand:V2DF 1 "vfloat_operand" "")
 999                       (parallel [(const_int 1)]))
1000                      (vec_select:DF
1001                       (match_dup 1)
1002                       (parallel [(const_int 0)])))
1003                     (match_dup 1)))
1004               (clobber (match_scratch:V2DF 2 ""))])]
1005   "VECTOR_UNIT_VSX_P (V2DFmode)"
1006   "")
1007
1008 ; The (VEC_reduc:V4SF
1009 ;       (op1)
1010 ;       (unspec:V4SF [(const_int 0)] UNSPEC_REDUC))
1011 ;
1012 ; is to allow us to use a code iterator, but not completely list all of the
1013 ; vector rotates, etc. to prevent canonicalization
1014
1015 (define_expand "reduc_<VEC_reduc_name>_v4sf"
1016   [(parallel [(set (match_operand:V4SF 0 "vfloat_operand" "")
1017                    (VEC_reduc:V4SF
1018                     (unspec:V4SF [(const_int 0)] UNSPEC_REDUC)
1019                     (match_operand:V4SF 1 "vfloat_operand" "")))
1020               (clobber (match_scratch:V4SF 2 ""))
1021               (clobber (match_scratch:V4SF 3 ""))])]
1022   "VECTOR_UNIT_VSX_P (V4SFmode)"
1023   "")
1024
1025 \f
1026 ;;; Expanders for vector insn patterns shared between the SPE and TARGET_PAIRED systems.
1027
1028 (define_expand "absv2sf2"
1029   [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
1030         (abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")))]
1031   "TARGET_PAIRED_FLOAT || TARGET_SPE"
1032   "")
1033
1034 (define_expand "negv2sf2"
1035   [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
1036         (neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")))]
1037   "TARGET_PAIRED_FLOAT || TARGET_SPE"
1038   "")
1039
1040 (define_expand "addv2sf3"
1041   [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
1042         (plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
1043                    (match_operand:V2SF 2 "gpc_reg_operand" "")))]
1044   "TARGET_PAIRED_FLOAT || TARGET_SPE"
1045   "
1046 {
1047   if (TARGET_SPE)
1048     {
1049       /* We need to make a note that we clobber SPEFSCR.  */
1050       rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
1051
1052       XVECEXP (par, 0, 0) = gen_rtx_SET (operands[0],
1053                                          gen_rtx_PLUS (V2SFmode, operands[1], operands[2]));
1054       XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
1055       emit_insn (par);
1056       DONE;
1057     }
1058 }")
1059
1060 (define_expand "subv2sf3"
1061   [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
1062         (minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
1063                     (match_operand:V2SF 2 "gpc_reg_operand" "")))]
1064   "TARGET_PAIRED_FLOAT || TARGET_SPE"
1065   "
1066 {
1067   if (TARGET_SPE)
1068     {
1069       /* We need to make a note that we clobber SPEFSCR.  */
1070       rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
1071
1072       XVECEXP (par, 0, 0) = gen_rtx_SET (operands[0],
1073                                          gen_rtx_MINUS (V2SFmode, operands[1], operands[2]));
1074       XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
1075       emit_insn (par);
1076       DONE;
1077     }
1078 }")
1079
1080 (define_expand "mulv2sf3"
1081   [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
1082         (mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
1083                    (match_operand:V2SF 2 "gpc_reg_operand" "")))]
1084   "TARGET_PAIRED_FLOAT || TARGET_SPE"
1085   "
1086 {
1087   if (TARGET_SPE)
1088     {
1089       /* We need to make a note that we clobber SPEFSCR.  */
1090       rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
1091
1092       XVECEXP (par, 0, 0) = gen_rtx_SET (operands[0],
1093                                          gen_rtx_MULT (V2SFmode, operands[1], operands[2]));
1094       XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
1095       emit_insn (par);
1096       DONE;
1097     }
1098 }")
1099
1100 (define_expand "divv2sf3"
1101   [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
1102         (div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
1103                   (match_operand:V2SF 2 "gpc_reg_operand" "")))]
1104   "TARGET_PAIRED_FLOAT || TARGET_SPE"
1105   "
1106 {
1107   if (TARGET_SPE)
1108     {
1109       /* We need to make a note that we clobber SPEFSCR.  */
1110       rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
1111
1112       XVECEXP (par, 0, 0) = gen_rtx_SET (operands[0],
1113                                          gen_rtx_DIV (V2SFmode, operands[1], operands[2]));
1114       XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
1115       emit_insn (par);
1116       DONE;
1117     }
1118 }")