gcc/config/rs6000/vector.md

   1 ;; Expander definitions for vector support between altivec & vsx.  No
   2 ;; instructions are in this file, this file provides the generic vector
   3 ;; expander, and the actual vector instructions will be in altivec.md and
   4 ;; vsx.md
   5
   6 ;; Copyright (C) 2009-2016 Free Software Foundation, Inc.
   7 ;; Contributed by Michael Meissner <meissner@linux.vnet.ibm.com>
   8
   9 ;; This file is part of GCC.
  10
  11 ;; GCC is free software; you can redistribute it and/or modify it
  12 ;; under the terms of the GNU General Public License as published
  13 ;; by the Free Software Foundation; either version 3, or (at your
  14 ;; option) any later version.
  15
  16 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  17 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  18 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  19 ;; License for more details.
  20
  21 ;; You should have received a copy of the GNU General Public License
  22 ;; along with GCC; see the file COPYING3.  If not see
  23 ;; <http://www.gnu.org/licenses/>.
  24
  25
  26 ;; Vector int modes
  27 (define_mode_iterator VEC_I [V16QI V8HI V4SI V2DI])
  28
  29 ;; Vector float modes
  30 (define_mode_iterator VEC_F [V4SF V2DF])
  31
  32 ;; Vector arithmetic modes
  33 (define_mode_iterator VEC_A [V16QI V8HI V4SI V2DI V4SF V2DF])
  34
  35 ;; Vector modes that need alginment via permutes
  36 (define_mode_iterator VEC_K [V16QI V8HI V4SI V4SF])
  37
  38 ;; Vector logical modes
  39 (define_mode_iterator VEC_L [V16QI V8HI V4SI V2DI V4SF V2DF V1TI TI KF TF])
  40
  41 ;; Vector modes for moves.  Don't do TImode or TFmode here, since their
  42 ;; moves are handled elsewhere.
  43 (define_mode_iterator VEC_M [V16QI V8HI V4SI V2DI V4SF V2DF V1TI KF])
  44
  45 ;; Vector modes for types that don't need a realignment under VSX
  46 (define_mode_iterator VEC_N [V4SI V4SF V2DI V2DF V1TI KF TF])
  47
  48 ;; Vector comparison modes
  49 (define_mode_iterator VEC_C [V16QI V8HI V4SI V2DI V4SF V2DF])
  50
  51 ;; Vector init/extract modes
  52 (define_mode_iterator VEC_E [V16QI V8HI V4SI V2DI V4SF V2DF])
  53
  54 ;; Vector modes for 64-bit base types
  55 (define_mode_iterator VEC_64 [V2DI V2DF])
  56
  57 ;; Base type from vector mode
  58 (define_mode_attr VEC_base [(V16QI "QI")
  59                             (V8HI  "HI")
  60                             (V4SI  "SI")
  61                             (V2DI  "DI")
  62                             (V4SF  "SF")
  63                             (V2DF  "DF")
  64                             (V1TI  "TI")
  65                             (TI    "TI")])
  66
  67 ;; Same size integer type for floating point data
  68 (define_mode_attr VEC_int [(V4SF  "v4si")
  69                            (V2DF  "v2di")])
  70
  71 (define_mode_attr VEC_INT [(V4SF  "V4SI")
  72                            (V2DF  "V2DI")])
  73
  74 ;; constants for unspec
  75 (define_c_enum "unspec" [UNSPEC_PREDICATE
  76                          UNSPEC_REDUC])
  77
  78 ;; Vector reduction code iterators
  79 (define_code_iterator VEC_reduc [plus smin smax])
  80
  81 (define_code_attr VEC_reduc_name [(plus "plus")
  82                                   (smin "smin")
  83                                   (smax "smax")])
  84
  85 (define_code_attr VEC_reduc_rtx [(plus "add")
  86                                  (smin "smin")
  87                                  (smax "smax")])
  88
  89 \f
  90 ;; Vector move instructions.  Little-endian VSX loads and stores require
  91 ;; special handling to circumvent "element endianness."
  92 (define_expand "mov<mode>"
  93   [(set (match_operand:VEC_M 0 "nonimmediate_operand" "")
  94         (match_operand:VEC_M 1 "any_operand" ""))]
  95   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
  96 {
  97   if (can_create_pseudo_p ())
  98     {
  99       if (CONSTANT_P (operands[1]))
 100         {
 101           if (FLOAT128_VECTOR_P (<MODE>mode))
 102             {
 103               if (!easy_fp_constant (operands[1], <MODE>mode))
 104                 operands[1] = force_const_mem (<MODE>mode, operands[1]);
 105             }
 106           else if (!easy_vector_constant (operands[1], <MODE>mode))
 107             operands[1] = force_const_mem (<MODE>mode, operands[1]);
 108         }
 109
 110       if (!vlogical_operand (operands[0], <MODE>mode)
 111           && !vlogical_operand (operands[1], <MODE>mode))
 112         operands[1] = force_reg (<MODE>mode, operands[1]);
 113     }
 114   if (!BYTES_BIG_ENDIAN
 115       && VECTOR_MEM_VSX_P (<MODE>mode)
 116       && !TARGET_P9_VECTOR
 117       && !gpr_or_gpr_p (operands[0], operands[1])
 118       && (memory_operand (operands[0], <MODE>mode)
 119           ^ memory_operand (operands[1], <MODE>mode)))
 120     {
 121       rs6000_emit_le_vsx_move (operands[0], operands[1], <MODE>mode);
 122       DONE;
 123     }
 124 })
 125
 126 ;; Generic vector floating point load/store instructions.  These will match
 127 ;; insns defined in vsx.md or altivec.md depending on the switches.
 128 (define_expand "vector_load_<mode>"
 129   [(set (match_operand:VEC_M 0 "vfloat_operand" "")
 130         (match_operand:VEC_M 1 "memory_operand" ""))]
 131   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
 132   "")
 133
 134 (define_expand "vector_store_<mode>"
 135   [(set (match_operand:VEC_M 0 "memory_operand" "")
 136         (match_operand:VEC_M 1 "vfloat_operand" ""))]
 137   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
 138   "")
 139
 140 ;; Splits if a GPR register was chosen for the move
 141 (define_split
 142   [(set (match_operand:VEC_L 0 "nonimmediate_operand" "")
 143         (match_operand:VEC_L 1 "input_operand" ""))]
 144   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)
 145    && reload_completed
 146    && gpr_or_gpr_p (operands[0], operands[1])
 147    && !direct_move_p (operands[0], operands[1])
 148    && !quad_load_store_p (operands[0], operands[1])"
 149   [(pc)]
 150 {
 151   rs6000_split_multireg_move (operands[0], operands[1]);
 152   DONE;
 153 })
 154
 155 ;; Vector floating point load/store instructions that uses the Altivec
 156 ;; instructions even if we are compiling for VSX, since the Altivec
 157 ;; instructions silently ignore the bottom 3 bits of the address, and VSX does
 158 ;; not.
 159 (define_expand "vector_altivec_load_<mode>"
 160   [(set (match_operand:VEC_M 0 "vfloat_operand" "")
 161         (match_operand:VEC_M 1 "memory_operand" ""))]
 162   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
 163   "
 164 {
 165   gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode));
 166
 167   if (VECTOR_MEM_VSX_P (<MODE>mode))
 168     {
 169       operands[1] = rs6000_address_for_altivec (operands[1]);
 170       emit_insn (gen_altivec_lvx_<mode> (operands[0], operands[1]));
 171       DONE;
 172     }
 173 }")
 174
 175 (define_expand "vector_altivec_store_<mode>"
 176   [(set (match_operand:VEC_M 0 "memory_operand" "")
 177         (match_operand:VEC_M 1 "vfloat_operand" ""))]
 178   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
 179   "
 180 {
 181   gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode));
 182
 183   if (VECTOR_MEM_VSX_P (<MODE>mode))
 184     {
 185       operands[0] = rs6000_address_for_altivec (operands[0]);
 186       emit_insn (gen_altivec_stvx_<mode> (operands[0], operands[1]));
 187       DONE;
 188     }
 189 }")
 190
 191
 192 \f
 193 ;; Generic floating point vector arithmetic support
 194 (define_expand "add<mode>3"
 195   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 196         (plus:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
 197                     (match_operand:VEC_F 2 "vfloat_operand" "")))]
 198   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 199   "")
 200
 201 (define_expand "sub<mode>3"
 202   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 203         (minus:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
 204                      (match_operand:VEC_F 2 "vfloat_operand" "")))]
 205   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 206   "")
 207
 208 (define_expand "mul<mode>3"
 209   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 210         (mult:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
 211                     (match_operand:VEC_F 2 "vfloat_operand" "")))]
 212   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 213 {
 214   if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
 215     {
 216       emit_insn (gen_altivec_mulv4sf3 (operands[0], operands[1], operands[2]));
 217       DONE;
 218     }
 219 })
 220
 221 (define_expand "div<mode>3"
 222   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 223         (div:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
 224                    (match_operand:VEC_F 2 "vfloat_operand" "")))]
 225   "VECTOR_UNIT_VSX_P (<MODE>mode)"
 226   "")
 227
 228 (define_expand "neg<mode>2"
 229   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 230         (neg:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
 231   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 232   "
 233 {
 234   if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
 235     {
 236       emit_insn (gen_altivec_negv4sf2 (operands[0], operands[1]));
 237       DONE;
 238     }
 239 }")
 240
 241 (define_expand "abs<mode>2"
 242   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 243         (abs:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
 244   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 245   "
 246 {
 247   if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
 248     {
 249       emit_insn (gen_altivec_absv4sf2 (operands[0], operands[1]));
 250       DONE;
 251     }
 252 }")
 253
 254 (define_expand "smin<mode>3"
 255   [(set (match_operand:VEC_F 0 "register_operand" "")
 256         (smin:VEC_F (match_operand:VEC_F 1 "register_operand" "")
 257                     (match_operand:VEC_F 2 "register_operand" "")))]
 258   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 259   "")
 260
 261 (define_expand "smax<mode>3"
 262   [(set (match_operand:VEC_F 0 "register_operand" "")
 263         (smax:VEC_F (match_operand:VEC_F 1 "register_operand" "")
 264                     (match_operand:VEC_F 2 "register_operand" "")))]
 265   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 266   "")
 267
 268
 269 (define_expand "sqrt<mode>2"
 270   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 271         (sqrt:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
 272   "VECTOR_UNIT_VSX_P (<MODE>mode)"
 273   "")
 274
 275 (define_expand "rsqrte<mode>2"
 276   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 277         (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")]
 278                       UNSPEC_RSQRT))]
 279   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 280   "")
 281
 282 (define_expand "re<mode>2"
 283   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 284         (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "f")]
 285                       UNSPEC_FRES))]
 286   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 287   "")
 288
 289 (define_expand "ftrunc<mode>2"
 290   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 291         (fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
 292   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 293   "")
 294
 295 (define_expand "vector_ceil<mode>2"
 296   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 297         (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")]
 298                       UNSPEC_FRIP))]
 299   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 300   "")
 301
 302 (define_expand "vector_floor<mode>2"
 303   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 304         (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")]
 305                       UNSPEC_FRIM))]
 306   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 307   "")
 308
 309 (define_expand "vector_btrunc<mode>2"
 310   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 311         (fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
 312   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 313   "")
 314
 315 (define_expand "vector_copysign<mode>3"
 316   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 317         (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")
 318                        (match_operand:VEC_F 2 "vfloat_operand" "")] UNSPEC_COPYSIGN))]
 319   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 320   "
 321 {
 322   if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
 323     {
 324       emit_insn (gen_altivec_copysign_v4sf3 (operands[0], operands[1],
 325                                              operands[2]));
 326       DONE;
 327     }
 328 }")
 329
 330 \f
 331 ;; Vector comparisons
 332 (define_expand "vcond<mode><mode>"
 333   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 334         (if_then_else:VEC_F
 335          (match_operator 3 "comparison_operator"
 336                          [(match_operand:VEC_F 4 "vfloat_operand" "")
 337                           (match_operand:VEC_F 5 "vfloat_operand" "")])
 338          (match_operand:VEC_F 1 "vfloat_operand" "")
 339          (match_operand:VEC_F 2 "vfloat_operand" "")))]
 340   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 341   "
 342 {
 343   if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
 344                                     operands[3], operands[4], operands[5]))
 345     DONE;
 346   else
 347     FAIL;
 348 }")
 349
 350 (define_expand "vcond<mode><mode>"
 351   [(set (match_operand:VEC_I 0 "vint_operand" "")
 352         (if_then_else:VEC_I
 353          (match_operator 3 "comparison_operator"
 354                          [(match_operand:VEC_I 4 "vint_operand" "")
 355                           (match_operand:VEC_I 5 "vint_operand" "")])
 356          (match_operand:VEC_I 1 "vint_operand" "")
 357          (match_operand:VEC_I 2 "vint_operand" "")))]
 358   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 359   "
 360 {
 361   if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
 362                                     operands[3], operands[4], operands[5]))
 363     DONE;
 364   else
 365     FAIL;
 366 }")
 367
 368 (define_expand "vcondv4sfv4si"
 369   [(set (match_operand:V4SF 0 "vfloat_operand" "")
 370         (if_then_else:V4SF
 371          (match_operator 3 "comparison_operator"
 372                          [(match_operand:V4SI 4 "vint_operand" "")
 373                           (match_operand:V4SI 5 "vint_operand" "")])
 374          (match_operand:V4SF 1 "vfloat_operand" "")
 375          (match_operand:V4SF 2 "vfloat_operand" "")))]
 376   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
 377    && VECTOR_UNIT_ALTIVEC_P (V4SImode)"
 378   "
 379 {
 380   if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
 381                                     operands[3], operands[4], operands[5]))
 382     DONE;
 383   else
 384     FAIL;
 385 }")
 386
 387 (define_expand "vcondv4siv4sf"
 388   [(set (match_operand:V4SI 0 "vint_operand" "")
 389         (if_then_else:V4SI
 390          (match_operator 3 "comparison_operator"
 391                          [(match_operand:V4SF 4 "vfloat_operand" "")
 392                           (match_operand:V4SF 5 "vfloat_operand" "")])
 393          (match_operand:V4SI 1 "vint_operand" "")
 394          (match_operand:V4SI 2 "vint_operand" "")))]
 395   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
 396    && VECTOR_UNIT_ALTIVEC_P (V4SImode)"
 397   "
 398 {
 399   if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
 400                                     operands[3], operands[4], operands[5]))
 401     DONE;
 402   else
 403     FAIL;
 404 }")
 405
 406 (define_expand "vcondu<mode><mode>"
 407   [(set (match_operand:VEC_I 0 "vint_operand" "")
 408         (if_then_else:VEC_I
 409          (match_operator 3 "comparison_operator"
 410                          [(match_operand:VEC_I 4 "vint_operand" "")
 411                           (match_operand:VEC_I 5 "vint_operand" "")])
 412          (match_operand:VEC_I 1 "vint_operand" "")
 413          (match_operand:VEC_I 2 "vint_operand" "")))]
 414   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 415   "
 416 {
 417   if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
 418                                     operands[3], operands[4], operands[5]))
 419     DONE;
 420   else
 421     FAIL;
 422 }")
 423
 424 (define_expand "vconduv4sfv4si"
 425   [(set (match_operand:V4SF 0 "vfloat_operand" "")
 426         (if_then_else:V4SF
 427          (match_operator 3 "comparison_operator"
 428                          [(match_operand:V4SI 4 "vint_operand" "")
 429                           (match_operand:V4SI 5 "vint_operand" "")])
 430          (match_operand:V4SF 1 "vfloat_operand" "")
 431          (match_operand:V4SF 2 "vfloat_operand" "")))]
 432   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
 433    && VECTOR_UNIT_ALTIVEC_P (V4SImode)"
 434   "
 435 {
 436   if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
 437                                     operands[3], operands[4], operands[5]))
 438     DONE;
 439   else
 440     FAIL;
 441 }")
 442
 443 (define_expand "vector_eq<mode>"
 444   [(set (match_operand:VEC_C 0 "vlogical_operand" "")
 445         (eq:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "")
 446                   (match_operand:VEC_C 2 "vlogical_operand" "")))]
 447   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 448   "")
 449
 450 (define_expand "vector_gt<mode>"
 451   [(set (match_operand:VEC_C 0 "vlogical_operand" "")
 452         (gt:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "")
 453                   (match_operand:VEC_C 2 "vlogical_operand" "")))]
 454   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 455   "")
 456
 457 (define_expand "vector_ge<mode>"
 458   [(set (match_operand:VEC_F 0 "vlogical_operand" "")
 459         (ge:VEC_F (match_operand:VEC_F 1 "vlogical_operand" "")
 460                   (match_operand:VEC_F 2 "vlogical_operand" "")))]
 461   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 462   "")
 463
 464 ; >= for integer vectors: swap operands and apply not-greater-than
 465 (define_expand "vector_nlt<mode>"
 466   [(set (match_operand:VEC_I 3 "vlogical_operand" "")
 467         (gt:VEC_I (match_operand:VEC_I 2 "vlogical_operand" "")
 468                   (match_operand:VEC_I 1 "vlogical_operand" "")))
 469    (set (match_operand:VEC_I 0 "vlogical_operand" "")
 470         (not:VEC_I (match_dup 3)))]
 471   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 472   "
 473 {
 474   operands[3] = gen_reg_rtx_and_attrs (operands[0]);
 475 }")
 476
 477 (define_expand "vector_gtu<mode>"
 478   [(set (match_operand:VEC_I 0 "vint_operand" "")
 479         (gtu:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
 480                    (match_operand:VEC_I 2 "vint_operand" "")))]
 481   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 482   "")
 483
 484 ; >= for integer vectors: swap operands and apply not-greater-than
 485 (define_expand "vector_nltu<mode>"
 486   [(set (match_operand:VEC_I 3 "vlogical_operand" "")
 487         (gtu:VEC_I (match_operand:VEC_I 2 "vlogical_operand" "")
 488                    (match_operand:VEC_I 1 "vlogical_operand" "")))
 489    (set (match_operand:VEC_I 0 "vlogical_operand" "")
 490         (not:VEC_I (match_dup 3)))]
 491   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 492   "
 493 {
 494   operands[3] = gen_reg_rtx_and_attrs (operands[0]);
 495 }")
 496
 497 (define_expand "vector_geu<mode>"
 498   [(set (match_operand:VEC_I 0 "vint_operand" "")
 499         (geu:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
 500                    (match_operand:VEC_I 2 "vint_operand" "")))]
 501   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 502   "")
 503
 504 ; <= for integer vectors: apply not-greater-than
 505 (define_expand "vector_ngt<mode>"
 506   [(set (match_operand:VEC_I 3 "vlogical_operand" "")
 507         (gt:VEC_I (match_operand:VEC_I 1 "vlogical_operand" "")
 508                   (match_operand:VEC_I 2 "vlogical_operand" "")))
 509    (set (match_operand:VEC_I 0 "vlogical_operand" "")
 510         (not:VEC_I (match_dup 3)))]
 511   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 512   "
 513 {
 514   operands[3] = gen_reg_rtx_and_attrs (operands[0]);
 515 }")
 516
 517 (define_expand "vector_ngtu<mode>"
 518   [(set (match_operand:VEC_I 3 "vlogical_operand" "")
 519         (gtu:VEC_I (match_operand:VEC_I 1 "vlogical_operand" "")
 520                    (match_operand:VEC_I 2 "vlogical_operand" "")))
 521    (set (match_operand:VEC_I 0 "vlogical_operand" "")
 522         (not:VEC_I (match_dup 3)))]
 523   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 524   "
 525 {
 526   operands[3] = gen_reg_rtx_and_attrs (operands[0]);
 527 }")
 528
 529 (define_insn_and_split "*vector_uneq<mode>"
 530   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 531         (uneq:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
 532                     (match_operand:VEC_F 2 "vfloat_operand" "")))]
 533   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 534   "#"
 535   ""
 536   [(set (match_dup 3)
 537         (gt:VEC_F (match_dup 1)
 538                   (match_dup 2)))
 539    (set (match_dup 4)
 540         (gt:VEC_F (match_dup 2)
 541                   (match_dup 1)))
 542    (set (match_dup 0)
 543         (not:VEC_F (ior:VEC_F (match_dup 3)
 544                               (match_dup 4))))]
 545   "
 546 {
 547   operands[3] = gen_reg_rtx (<MODE>mode);
 548   operands[4] = gen_reg_rtx (<MODE>mode);
 549 }")
 550
 551 (define_insn_and_split "*vector_ltgt<mode>"
 552   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 553         (ltgt:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
 554                     (match_operand:VEC_F 2 "vfloat_operand" "")))]
 555   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 556   "#"
 557   ""
 558   [(set (match_dup 3)
 559         (gt:VEC_F (match_dup 1)
 560                   (match_dup 2)))
 561    (set (match_dup 4)
 562         (gt:VEC_F (match_dup 2)
 563                   (match_dup 1)))
 564    (set (match_dup 0)
 565         (ior:VEC_F (match_dup 3)
 566                    (match_dup 4)))]
 567   "
 568 {
 569   operands[3] = gen_reg_rtx (<MODE>mode);
 570   operands[4] = gen_reg_rtx (<MODE>mode);
 571 }")
 572
 573 (define_insn_and_split "*vector_ordered<mode>"
 574   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 575         (ordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
 576                        (match_operand:VEC_F 2 "vfloat_operand" "")))]
 577   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 578   "#"
 579   ""
 580   [(set (match_dup 3)
 581         (ge:VEC_F (match_dup 1)
 582                   (match_dup 2)))
 583    (set (match_dup 4)
 584         (ge:VEC_F (match_dup 2)
 585                   (match_dup 1)))
 586    (set (match_dup 0)
 587         (ior:VEC_F (match_dup 3)
 588                    (match_dup 4)))]
 589   "
 590 {
 591   operands[3] = gen_reg_rtx (<MODE>mode);
 592   operands[4] = gen_reg_rtx (<MODE>mode);
 593 }")
 594
 595 (define_insn_and_split "*vector_unordered<mode>"
 596   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 597         (unordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
 598                          (match_operand:VEC_F 2 "vfloat_operand" "")))]
 599   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 600   "#"
 601   ""
 602   [(set (match_dup 3)
 603         (ge:VEC_F (match_dup 1)
 604                   (match_dup 2)))
 605    (set (match_dup 4)
 606         (ge:VEC_F (match_dup 2)
 607                   (match_dup 1)))
 608    (set (match_dup 0)
 609         (and:VEC_F (not:VEC_F (match_dup 3))
 610                    (not:VEC_F (match_dup 4))))]
 611   "
 612 {
 613   operands[3] = gen_reg_rtx (<MODE>mode);
 614   operands[4] = gen_reg_rtx (<MODE>mode);
 615 }")
 616
 617 ;; Note the arguments for __builtin_altivec_vsel are op2, op1, mask
 618 ;; which is in the reverse order that we want
 619 (define_expand "vector_select_<mode>"
 620   [(set (match_operand:VEC_L 0 "vlogical_operand" "")
 621         (if_then_else:VEC_L
 622          (ne:CC (match_operand:VEC_L 3 "vlogical_operand" "")
 623                 (match_dup 4))
 624          (match_operand:VEC_L 2 "vlogical_operand" "")
 625          (match_operand:VEC_L 1 "vlogical_operand" "")))]
 626   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 627   "operands[4] = CONST0_RTX (<MODE>mode);")
 628
 629 (define_expand "vector_select_<mode>_uns"
 630   [(set (match_operand:VEC_L 0 "vlogical_operand" "")
 631         (if_then_else:VEC_L
 632          (ne:CCUNS (match_operand:VEC_L 3 "vlogical_operand" "")
 633                    (match_dup 4))
 634          (match_operand:VEC_L 2 "vlogical_operand" "")
 635          (match_operand:VEC_L 1 "vlogical_operand" "")))]
 636   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 637   "operands[4] = CONST0_RTX (<MODE>mode);")
 638
 639 ;; Expansions that compare vectors producing a vector result and a predicate,
 640 ;; setting CR6 to indicate a combined status
 641 (define_expand "vector_eq_<mode>_p"
 642   [(parallel
 643     [(set (reg:CC 74)
 644           (unspec:CC [(eq:CC (match_operand:VEC_A 1 "vlogical_operand" "")
 645                              (match_operand:VEC_A 2 "vlogical_operand" ""))]
 646                      UNSPEC_PREDICATE))
 647      (set (match_operand:VEC_A 0 "vlogical_operand" "")
 648           (eq:VEC_A (match_dup 1)
 649                     (match_dup 2)))])]
 650   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 651   "")
 652
 653 (define_expand "vector_gt_<mode>_p"
 654   [(parallel
 655     [(set (reg:CC 74)
 656           (unspec:CC [(gt:CC (match_operand:VEC_A 1 "vlogical_operand" "")
 657                              (match_operand:VEC_A 2 "vlogical_operand" ""))]
 658                      UNSPEC_PREDICATE))
 659      (set (match_operand:VEC_A 0 "vlogical_operand" "")
 660           (gt:VEC_A (match_dup 1)
 661                     (match_dup 2)))])]
 662   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 663   "")
 664
 665 (define_expand "vector_ge_<mode>_p"
 666   [(parallel
 667     [(set (reg:CC 74)
 668           (unspec:CC [(ge:CC (match_operand:VEC_F 1 "vfloat_operand" "")
 669                              (match_operand:VEC_F 2 "vfloat_operand" ""))]
 670                      UNSPEC_PREDICATE))
 671      (set (match_operand:VEC_F 0 "vfloat_operand" "")
 672           (ge:VEC_F (match_dup 1)
 673                     (match_dup 2)))])]
 674   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 675   "")
 676
 677 (define_expand "vector_gtu_<mode>_p"
 678   [(parallel
 679     [(set (reg:CC 74)
 680           (unspec:CC [(gtu:CC (match_operand:VEC_I 1 "vint_operand" "")
 681                               (match_operand:VEC_I 2 "vint_operand" ""))]
 682                      UNSPEC_PREDICATE))
 683      (set (match_operand:VEC_I 0 "vlogical_operand" "")
 684           (gtu:VEC_I (match_dup 1)
 685                      (match_dup 2)))])]
 686   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 687   "")
 688
 689 ;; AltiVec/VSX predicates.
 690
 691 (define_expand "cr6_test_for_zero"
 692   [(set (match_operand:SI 0 "register_operand" "=r")
 693         (eq:SI (reg:CC 74)
 694                (const_int 0)))]
 695   "TARGET_ALTIVEC || TARGET_VSX"
 696   "")
 697
 698 (define_expand "cr6_test_for_zero_reverse"
 699   [(set (match_operand:SI 0 "register_operand" "=r")
 700         (eq:SI (reg:CC 74)
 701                (const_int 0)))
 702    (set (match_dup 0)
 703         (xor:SI (match_dup 0)
 704                 (const_int 1)))]
 705   "TARGET_ALTIVEC || TARGET_VSX"
 706   "")
 707
 708 (define_expand "cr6_test_for_lt"
 709   [(set (match_operand:SI 0 "register_operand" "=r")
 710         (lt:SI (reg:CC 74)
 711                (const_int 0)))]
 712   "TARGET_ALTIVEC || TARGET_VSX"
 713   "")
 714
 715 (define_expand "cr6_test_for_lt_reverse"
 716   [(set (match_operand:SI 0 "register_operand" "=r")
 717         (lt:SI (reg:CC 74)
 718                (const_int 0)))
 719    (set (match_dup 0)
 720         (xor:SI (match_dup 0)
 721                 (const_int 1)))]
 722   "TARGET_ALTIVEC || TARGET_VSX"
 723   "")
 724
 725 \f
 726 ;; Vector count leading zeros
 727 (define_expand "clz<mode>2"
 728   [(set (match_operand:VEC_I 0 "register_operand" "")
 729         (clz:VEC_I (match_operand:VEC_I 1 "register_operand" "")))]
 730   "TARGET_P8_VECTOR")
 731
 732 ;; Vector population count
 733 (define_expand "popcount<mode>2"
 734   [(set (match_operand:VEC_I 0 "register_operand" "")
 735         (popcount:VEC_I (match_operand:VEC_I 1 "register_operand" "")))]
 736   "TARGET_P8_VECTOR")
 737
 738 \f
 739 ;; Same size conversions
 740 (define_expand "float<VEC_int><mode>2"
 741   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 742         (float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand" "")))]
 743   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 744   "
 745 {
 746   if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
 747     {
 748       emit_insn (gen_altivec_vcfsx (operands[0], operands[1], const0_rtx));
 749       DONE;
 750     }
 751 }")
 752
 753 (define_expand "floatuns<VEC_int><mode>2"
 754   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 755         (unsigned_float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand" "")))]
 756   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 757   "
 758 {
 759   if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
 760     {
 761       emit_insn (gen_altivec_vcfux (operands[0], operands[1], const0_rtx));
 762       DONE;
 763     }
 764 }")
 765
 766 (define_expand "fix_trunc<mode><VEC_int>2"
 767   [(set (match_operand:<VEC_INT> 0 "vint_operand" "")
 768         (fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand" "")))]
 769   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 770   "
 771 {
 772   if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
 773     {
 774       emit_insn (gen_altivec_vctsxs (operands[0], operands[1], const0_rtx));
 775       DONE;
 776     }
 777 }")
 778
 779 (define_expand "fixuns_trunc<mode><VEC_int>2"
 780   [(set (match_operand:<VEC_INT> 0 "vint_operand" "")
 781         (unsigned_fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand" "")))]
 782   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 783   "
 784 {
 785   if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
 786     {
 787       emit_insn (gen_altivec_vctuxs (operands[0], operands[1], const0_rtx));
 788       DONE;
 789     }
 790 }")
 791
 792 \f
 793 ;; Vector initialization, set, extract
 794 (define_expand "vec_init<mode>"
 795   [(match_operand:VEC_E 0 "vlogical_operand" "")
 796    (match_operand:VEC_E 1 "" "")]
 797   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
 798 {
 799   rs6000_expand_vector_init (operands[0], operands[1]);
 800   DONE;
 801 })
 802
 803 (define_expand "vec_set<mode>"
 804   [(match_operand:VEC_E 0 "vlogical_operand" "")
 805    (match_operand:<VEC_base> 1 "register_operand" "")
 806    (match_operand 2 "const_int_operand" "")]
 807   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
 808 {
 809   rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
 810   DONE;
 811 })
 812
 813 (define_expand "vec_extract<mode>"
 814   [(match_operand:<VEC_base> 0 "register_operand" "")
 815    (match_operand:VEC_E 1 "vlogical_operand" "")
 816    (match_operand 2 "const_int_operand" "")]
 817   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
 818 {
 819   rs6000_expand_vector_extract (operands[0], operands[1],
 820                                 INTVAL (operands[2]));
 821   DONE;
 822 })
 823 \f
 824 ;; Convert double word types to single word types
 825 (define_expand "vec_pack_trunc_v2df"
 826   [(match_operand:V4SF 0 "vfloat_operand" "")
 827    (match_operand:V2DF 1 "vfloat_operand" "")
 828    (match_operand:V2DF 2 "vfloat_operand" "")]
 829   "VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
 830 {
 831   rtx r1 = gen_reg_rtx (V4SFmode);
 832   rtx r2 = gen_reg_rtx (V4SFmode);
 833
 834   emit_insn (gen_vsx_xvcvdpsp (r1, operands[1]));
 835   emit_insn (gen_vsx_xvcvdpsp (r2, operands[2]));
 836   rs6000_expand_extract_even (operands[0], r1, r2);
 837   DONE;
 838 })
 839
 840 (define_expand "vec_pack_sfix_trunc_v2df"
 841   [(match_operand:V4SI 0 "vint_operand" "")
 842    (match_operand:V2DF 1 "vfloat_operand" "")
 843    (match_operand:V2DF 2 "vfloat_operand" "")]
 844   "VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
 845 {
 846   rtx r1 = gen_reg_rtx (V4SImode);
 847   rtx r2 = gen_reg_rtx (V4SImode);
 848
 849   emit_insn (gen_vsx_xvcvdpsxws (r1, operands[1]));
 850   emit_insn (gen_vsx_xvcvdpsxws (r2, operands[2]));
 851   rs6000_expand_extract_even (operands[0], r1, r2);
 852   DONE;
 853 })
 854
 855 (define_expand "vec_pack_ufix_trunc_v2df"
 856   [(match_operand:V4SI 0 "vint_operand" "")
 857    (match_operand:V2DF 1 "vfloat_operand" "")
 858    (match_operand:V2DF 2 "vfloat_operand" "")]
 859   "VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
 860 {
 861   rtx r1 = gen_reg_rtx (V4SImode);
 862   rtx r2 = gen_reg_rtx (V4SImode);
 863
 864   emit_insn (gen_vsx_xvcvdpuxws (r1, operands[1]));
 865   emit_insn (gen_vsx_xvcvdpuxws (r2, operands[2]));
 866   rs6000_expand_extract_even (operands[0], r1, r2);
 867   DONE;
 868 })
 869
 870 ;; Convert single word types to double word
 871 (define_expand "vec_unpacks_hi_v4sf"
 872   [(match_operand:V2DF 0 "vfloat_operand" "")
 873    (match_operand:V4SF 1 "vfloat_operand" "")]
 874   "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
 875 {
 876   rtx reg = gen_reg_rtx (V4SFmode);
 877
 878   rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN);
 879   emit_insn (gen_vsx_xvcvspdp (operands[0], reg));
 880   DONE;
 881 })
 882
 883 (define_expand "vec_unpacks_lo_v4sf"
 884   [(match_operand:V2DF 0 "vfloat_operand" "")
 885    (match_operand:V4SF 1 "vfloat_operand" "")]
 886   "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
 887 {
 888   rtx reg = gen_reg_rtx (V4SFmode);
 889
 890   rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN);
 891   emit_insn (gen_vsx_xvcvspdp (operands[0], reg));
 892   DONE;
 893 })
 894
 895 (define_expand "vec_unpacks_float_hi_v4si"
 896   [(match_operand:V2DF 0 "vfloat_operand" "")
 897    (match_operand:V4SI 1 "vint_operand" "")]
 898   "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
 899 {
 900   rtx reg = gen_reg_rtx (V4SImode);
 901
 902   rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN);
 903   emit_insn (gen_vsx_xvcvsxwdp (operands[0], reg));
 904   DONE;
 905 })
 906
 907 (define_expand "vec_unpacks_float_lo_v4si"
 908   [(match_operand:V2DF 0 "vfloat_operand" "")
 909    (match_operand:V4SI 1 "vint_operand" "")]
 910   "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
 911 {
 912   rtx reg = gen_reg_rtx (V4SImode);
 913
 914   rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN);
 915   emit_insn (gen_vsx_xvcvsxwdp (operands[0], reg));
 916   DONE;
 917 })
 918
 919 (define_expand "vec_unpacku_float_hi_v4si"
 920   [(match_operand:V2DF 0 "vfloat_operand" "")
 921    (match_operand:V4SI 1 "vint_operand" "")]
 922   "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
 923 {
 924   rtx reg = gen_reg_rtx (V4SImode);
 925
 926   rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN);
 927   emit_insn (gen_vsx_xvcvuxwdp (operands[0], reg));
 928   DONE;
 929 })
 930
 931 (define_expand "vec_unpacku_float_lo_v4si"
 932   [(match_operand:V2DF 0 "vfloat_operand" "")
 933    (match_operand:V4SI 1 "vint_operand" "")]
 934   "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
 935 {
 936   rtx reg = gen_reg_rtx (V4SImode);
 937
 938   rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN);
 939   emit_insn (gen_vsx_xvcvuxwdp (operands[0], reg));
 940   DONE;
 941 })
 942
 943 \f
 944 ;; Align vector loads with a permute.
 945 (define_expand "vec_realign_load_<mode>"
 946   [(match_operand:VEC_K 0 "vlogical_operand" "")
 947    (match_operand:VEC_K 1 "vlogical_operand" "")
 948    (match_operand:VEC_K 2 "vlogical_operand" "")
 949    (match_operand:V16QI 3 "vlogical_operand" "")]
 950   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
 951 {
 952   if (BYTES_BIG_ENDIAN)
 953     emit_insn (gen_altivec_vperm_<mode> (operands[0], operands[1],
 954                                          operands[2], operands[3]));
 955   else
 956     {
 957       /* We have changed lvsr to lvsl, so to complete the transformation
 958          of vperm for LE, we must swap the inputs.  */
 959       rtx unspec = gen_rtx_UNSPEC (<MODE>mode,
 960                                    gen_rtvec (3, operands[2],
 961                                               operands[1], operands[3]),
 962                                    UNSPEC_VPERM);
 963       emit_move_insn (operands[0], unspec);
 964     }
 965   DONE;
 966 })
 967
 968 ;; Under VSX, vectors of 4/8 byte alignments do not need to be aligned
 969 ;; since the load already handles it.
 970 (define_expand "movmisalign<mode>"
 971  [(set (match_operand:VEC_N 0 "nonimmediate_operand" "")
 972        (match_operand:VEC_N 1 "any_operand" ""))]
 973  "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_ALLOW_MOVMISALIGN"
 974  "")
 975
 976 ;; Vector shift right in bits. Currently supported ony for shift
 977 ;; amounts that can be expressed as byte shifts (divisible by 8).
 978 ;; General shift amounts can be supported using vsro + vsr. We're
 979 ;; not expecting to see these yet (the vectorizer currently
 980 ;; generates only shifts by a whole number of vector elements).
 981 ;; Note that the vec_shr operation is actually defined as
 982 ;; 'shift toward element 0' so is a shr for LE and shl for BE.
 983 (define_expand "vec_shr_<mode>"
 984   [(match_operand:VEC_L 0 "vlogical_operand" "")
 985    (match_operand:VEC_L 1 "vlogical_operand" "")
 986    (match_operand:QI 2 "reg_or_short_operand" "")]
 987   "TARGET_ALTIVEC"
 988   "
 989 {
 990   rtx bitshift = operands[2];
 991   rtx shift;
 992   rtx insn;
 993   rtx zero_reg, op1, op2;
 994   HOST_WIDE_INT bitshift_val;
 995   HOST_WIDE_INT byteshift_val;
 996
 997   if (! CONSTANT_P (bitshift))
 998     FAIL;
 999   bitshift_val = INTVAL (bitshift);
1000   if (bitshift_val & 0x7)
1001     FAIL;
1002   byteshift_val = (bitshift_val >> 3);
1003   zero_reg = gen_reg_rtx (<MODE>mode);
1004   emit_move_insn (zero_reg, CONST0_RTX (<MODE>mode));
1005   if (!BYTES_BIG_ENDIAN)
1006     {
1007       byteshift_val = 16 - byteshift_val;
1008       op1 = zero_reg;
1009       op2 = operands[1];
1010     }
1011   else
1012     {
1013       op1 = operands[1];
1014       op2 = zero_reg;
1015     }
1016
1017   if (TARGET_VSX && (byteshift_val & 0x3) == 0)
1018     {
1019       shift = gen_rtx_CONST_INT (QImode, byteshift_val >> 2);
1020       insn = gen_vsx_xxsldwi_<mode> (operands[0], op1, op2, shift);
1021     }
1022   else
1023     {
1024       shift = gen_rtx_CONST_INT (QImode, byteshift_val);
1025       insn = gen_altivec_vsldoi_<mode> (operands[0], op1, op2, shift);
1026     }
1027
1028   emit_insn (insn);
1029   DONE;
1030 }")
1031
1032 ;; Expanders for rotate each element in a vector
1033 (define_expand "vrotl<mode>3"
1034   [(set (match_operand:VEC_I 0 "vint_operand" "")
1035         (rotate:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
1036                       (match_operand:VEC_I 2 "vint_operand" "")))]
1037   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
1038   "")
1039
1040 ;; Expanders for arithmetic shift left on each vector element
1041 (define_expand "vashl<mode>3"
1042   [(set (match_operand:VEC_I 0 "vint_operand" "")
1043         (ashift:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
1044                       (match_operand:VEC_I 2 "vint_operand" "")))]
1045   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
1046   "")
1047
1048 ;; Expanders for logical shift right on each vector element
1049 (define_expand "vlshr<mode>3"
1050   [(set (match_operand:VEC_I 0 "vint_operand" "")
1051         (lshiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
1052                         (match_operand:VEC_I 2 "vint_operand" "")))]
1053   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
1054   "")
1055
1056 ;; Expanders for arithmetic shift right on each vector element
1057 (define_expand "vashr<mode>3"
1058   [(set (match_operand:VEC_I 0 "vint_operand" "")
1059         (ashiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
1060                         (match_operand:VEC_I 2 "vint_operand" "")))]
1061   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
1062   "")
1063 \f
1064 ;; Vector reduction expanders for VSX
1065 ; The (VEC_reduc:...
1066 ;       (op1)
1067 ;       (unspec:... [(const_int 0)] UNSPEC_REDUC))
1068 ;
1069 ; is to allow us to use a code iterator, but not completely list all of the
1070 ; vector rotates, etc. to prevent canonicalization
1071
1072
1073 (define_expand "reduc_<VEC_reduc:VEC_reduc_name>_scal_<VEC_F:mode>"
1074   [(match_operand:<VEC_base> 0 "register_operand" "")
1075    (VEC_reduc:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
1076                     (unspec:VEC_F [(const_int 0)] UNSPEC_REDUC))]
1077   "VECTOR_UNIT_VSX_P (<VEC_F:MODE>mode)"
1078   {
1079     rtx vec = gen_reg_rtx (<VEC_F:MODE>mode);
1080     rtx elt = BYTES_BIG_ENDIAN
1081                 ? gen_int_mode (GET_MODE_NUNITS (<VEC_F:MODE>mode) - 1, QImode)
1082                 : const0_rtx;
1083     emit_insn (gen_vsx_reduc_<VEC_reduc:VEC_reduc_name>_<VEC_F:mode> (vec,
1084         operand1));
1085     emit_insn (gen_vsx_extract_<VEC_F:mode> (operand0, vec, elt));
1086     DONE;
1087   })
1088
1089 \f
1090 ;;; Expanders for vector insn patterns shared between the SPE and TARGET_PAIRED systems.
1091
1092 (define_expand "absv2sf2"
1093   [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
1094         (abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")))]
1095   "TARGET_PAIRED_FLOAT || TARGET_SPE"
1096   "")
1097
1098 (define_expand "negv2sf2"
1099   [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
1100         (neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")))]
1101   "TARGET_PAIRED_FLOAT || TARGET_SPE"
1102   "")
1103
1104 (define_expand "addv2sf3"
1105   [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
1106         (plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
1107                    (match_operand:V2SF 2 "gpc_reg_operand" "")))]
1108   "TARGET_PAIRED_FLOAT || TARGET_SPE"
1109   "
1110 {
1111   if (TARGET_SPE)
1112     {
1113       /* We need to make a note that we clobber SPEFSCR.  */
1114       rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
1115
1116       XVECEXP (par, 0, 0) = gen_rtx_SET (operands[0],
1117                                          gen_rtx_PLUS (V2SFmode, operands[1], operands[2]));
1118       XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
1119       emit_insn (par);
1120       DONE;
1121     }
1122 }")
1123
1124 (define_expand "subv2sf3"
1125   [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
1126         (minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
1127                     (match_operand:V2SF 2 "gpc_reg_operand" "")))]
1128   "TARGET_PAIRED_FLOAT || TARGET_SPE"
1129   "
1130 {
1131   if (TARGET_SPE)
1132     {
1133       /* We need to make a note that we clobber SPEFSCR.  */
1134       rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
1135
1136       XVECEXP (par, 0, 0) = gen_rtx_SET (operands[0],
1137                                          gen_rtx_MINUS (V2SFmode, operands[1], operands[2]));
1138       XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
1139       emit_insn (par);
1140       DONE;
1141     }
1142 }")
1143
1144 (define_expand "mulv2sf3"
1145   [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
1146         (mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
1147                    (match_operand:V2SF 2 "gpc_reg_operand" "")))]
1148   "TARGET_PAIRED_FLOAT || TARGET_SPE"
1149   "
1150 {
1151   if (TARGET_SPE)
1152     {
1153       /* We need to make a note that we clobber SPEFSCR.  */
1154       rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
1155
1156       XVECEXP (par, 0, 0) = gen_rtx_SET (operands[0],
1157                                          gen_rtx_MULT (V2SFmode, operands[1], operands[2]));
1158       XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
1159       emit_insn (par);
1160       DONE;
1161     }
1162 }")
1163
1164 (define_expand "divv2sf3"
1165   [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
1166         (div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
1167                   (match_operand:V2SF 2 "gpc_reg_operand" "")))]
1168   "TARGET_PAIRED_FLOAT || TARGET_SPE"
1169   "
1170 {
1171   if (TARGET_SPE)
1172     {
1173       /* We need to make a note that we clobber SPEFSCR.  */
1174       rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
1175
1176       XVECEXP (par, 0, 0) = gen_rtx_SET (operands[0],
1177                                          gen_rtx_DIV (V2SFmode, operands[1], operands[2]));
1178       XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
1179       emit_insn (par);
1180       DONE;
1181     }
1182 }")