gcc/config/rs6000/vector.md

   1 ;; Expander definitions for vector support between altivec & vsx.  No
   2 ;; instructions are in this file, this file provides the generic vector
   3 ;; expander, and the actual vector instructions will be in altivec.md and
   4 ;; vsx.md
   5
   6 ;; Copyright (C) 2009, 2010, 2011, 2012
   7 ;; Free Software Foundation, Inc.
   8 ;; Contributed by Michael Meissner <meissner@linux.vnet.ibm.com>
   9
  10 ;; This file is part of GCC.
  11
  12 ;; GCC is free software; you can redistribute it and/or modify it
  13 ;; under the terms of the GNU General Public License as published
  14 ;; by the Free Software Foundation; either version 3, or (at your
  15 ;; option) any later version.
  16
  17 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  18 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  19 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  20 ;; License for more details.
  21
  22 ;; You should have received a copy of the GNU General Public License
  23 ;; along with GCC; see the file COPYING3.  If not see
  24 ;; <http://www.gnu.org/licenses/>.
  25
  26
  27 ;; Vector int modes
  28 (define_mode_iterator VEC_I [V16QI V8HI V4SI])
  29
  30 ;; Vector float modes
  31 (define_mode_iterator VEC_F [V4SF V2DF])
  32
  33 ;; Vector arithmetic modes
  34 (define_mode_iterator VEC_A [V16QI V8HI V4SI V4SF V2DF])
  35
  36 ;; Vector modes that need alginment via permutes
  37 (define_mode_iterator VEC_K [V16QI V8HI V4SI V4SF])
  38
  39 ;; Vector logical modes
  40 (define_mode_iterator VEC_L [V16QI V8HI V4SI V2DI V4SF V2DF TI])
  41
  42 ;; Vector modes for moves.  Don't do TImode here.
  43 (define_mode_iterator VEC_M [V16QI V8HI V4SI V2DI V4SF V2DF])
  44
  45 ;; Vector modes for types that don't need a realignment under VSX
  46 (define_mode_iterator VEC_N [V4SI V4SF V2DI V2DF])
  47
  48 ;; Vector comparison modes
  49 (define_mode_iterator VEC_C [V16QI V8HI V4SI V4SF V2DF])
  50
  51 ;; Vector init/extract modes
  52 (define_mode_iterator VEC_E [V16QI V8HI V4SI V2DI V4SF V2DF])
  53
  54 ;; Vector modes for 64-bit base types
  55 (define_mode_iterator VEC_64 [V2DI V2DF])
  56
  57 ;; Vector reload iterator
  58 (define_mode_iterator VEC_R [V16QI V8HI V4SI V2DI V4SF V2DF DF TI])
  59
  60 ;; Base type from vector mode
  61 (define_mode_attr VEC_base [(V16QI "QI")
  62                             (V8HI  "HI")
  63                             (V4SI  "SI")
  64                             (V2DI  "DI")
  65                             (V4SF  "SF")
  66                             (V2DF  "DF")
  67                             (TI    "TI")])
  68
  69 ;; Same size integer type for floating point data
  70 (define_mode_attr VEC_int [(V4SF  "v4si")
  71                            (V2DF  "v2di")])
  72
  73 (define_mode_attr VEC_INT [(V4SF  "V4SI")
  74                            (V2DF  "V2DI")])
  75
  76 ;; constants for unspec
  77 (define_c_enum "unspec" [UNSPEC_PREDICATE
  78                          UNSPEC_REDUC])
  79
  80 ;; Vector reduction code iterators
  81 (define_code_iterator VEC_reduc [plus smin smax])
  82
  83 (define_code_attr VEC_reduc_name [(plus "splus")
  84                                   (smin "smin")
  85                                   (smax "smax")])
  86
  87 (define_code_attr VEC_reduc_rtx [(plus "add")
  88                                  (smin "smin")
  89                                  (smax "smax")])
  90
  91 \f
  92 ;; Vector move instructions.
  93 (define_expand "mov<mode>"
  94   [(set (match_operand:VEC_M 0 "nonimmediate_operand" "")
  95         (match_operand:VEC_M 1 "any_operand" ""))]
  96   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
  97 {
  98   if (can_create_pseudo_p ())
  99     {
 100       if (CONSTANT_P (operands[1])
 101           && !easy_vector_constant (operands[1], <MODE>mode))
 102         operands[1] = force_const_mem (<MODE>mode, operands[1]);
 103
 104       else if (!vlogical_operand (operands[0], <MODE>mode)
 105                && !vlogical_operand (operands[1], <MODE>mode))
 106         operands[1] = force_reg (<MODE>mode, operands[1]);
 107     }
 108 })
 109
 110 ;; Generic vector floating point load/store instructions.  These will match
 111 ;; insns defined in vsx.md or altivec.md depending on the switches.
 112 (define_expand "vector_load_<mode>"
 113   [(set (match_operand:VEC_M 0 "vfloat_operand" "")
 114         (match_operand:VEC_M 1 "memory_operand" ""))]
 115   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
 116   "")
 117
 118 (define_expand "vector_store_<mode>"
 119   [(set (match_operand:VEC_M 0 "memory_operand" "")
 120         (match_operand:VEC_M 1 "vfloat_operand" ""))]
 121   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
 122   "")
 123
 124 ;; Splits if a GPR register was chosen for the move
 125 (define_split
 126   [(set (match_operand:VEC_L 0 "nonimmediate_operand" "")
 127         (match_operand:VEC_L 1 "input_operand" ""))]
 128   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)
 129    && reload_completed
 130    && gpr_or_gpr_p (operands[0], operands[1])"
 131   [(pc)]
 132 {
 133   rs6000_split_multireg_move (operands[0], operands[1]);
 134   DONE;
 135 })
 136
 137 ;; Vector floating point load/store instructions that uses the Altivec
 138 ;; instructions even if we are compiling for VSX, since the Altivec
 139 ;; instructions silently ignore the bottom 3 bits of the address, and VSX does
 140 ;; not.
 141 (define_expand "vector_altivec_load_<mode>"
 142   [(set (match_operand:VEC_M 0 "vfloat_operand" "")
 143         (match_operand:VEC_M 1 "memory_operand" ""))]
 144   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
 145   "
 146 {
 147   gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode));
 148
 149   if (VECTOR_MEM_VSX_P (<MODE>mode))
 150     {
 151       operands[1] = rs6000_address_for_altivec (operands[1]);
 152       emit_insn (gen_altivec_lvx_<mode> (operands[0], operands[1]));
 153       DONE;
 154     }
 155 }")
 156
 157 (define_expand "vector_altivec_store_<mode>"
 158   [(set (match_operand:VEC_M 0 "memory_operand" "")
 159         (match_operand:VEC_M 1 "vfloat_operand" ""))]
 160   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
 161   "
 162 {
 163   gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode));
 164
 165   if (VECTOR_MEM_VSX_P (<MODE>mode))
 166     {
 167       operands[0] = rs6000_address_for_altivec (operands[0]);
 168       emit_insn (gen_altivec_stvx_<mode> (operands[0], operands[1]));
 169       DONE;
 170     }
 171 }")
 172
 173
 174 \f
 175 ;; Reload patterns for vector operations.  We may need an additional base
 176 ;; register to convert the reg+offset addressing to reg+reg for vector
 177 ;; registers and reg+reg or (reg+reg)&(-16) addressing to just an index
 178 ;; register for gpr registers.
 179 (define_expand "reload_<VEC_R:mode>_<P:mptrsize>_store"
 180   [(parallel [(match_operand:VEC_R 0 "memory_operand" "m")
 181               (match_operand:VEC_R 1 "gpc_reg_operand" "r")
 182               (match_operand:P 2 "register_operand" "=&b")])]
 183   "<P:tptrsize>"
 184 {
 185   rs6000_secondary_reload_inner (operands[1], operands[0], operands[2], true);
 186   DONE;
 187 })
 188
 189 (define_expand "reload_<VEC_R:mode>_<P:mptrsize>_load"
 190   [(parallel [(match_operand:VEC_R 0 "gpc_reg_operand" "=&r")
 191               (match_operand:VEC_R 1 "memory_operand" "m")
 192               (match_operand:P 2 "register_operand" "=&b")])]
 193   "<P:tptrsize>"
 194 {
 195   rs6000_secondary_reload_inner (operands[0], operands[1], operands[2], false);
 196   DONE;
 197 })
 198
 199 ;; Reload sometimes tries to move the address to a GPR, and can generate
 200 ;; invalid RTL for addresses involving AND -16.  Allow addresses involving
 201 ;; reg+reg, reg+small constant, or just reg, all wrapped in an AND -16.
 202
 203 (define_insn_and_split "*vec_reload_and_plus_<mptrsize>"
 204   [(set (match_operand:P 0 "gpc_reg_operand" "=b")
 205         (and:P (plus:P (match_operand:P 1 "gpc_reg_operand" "r")
 206                        (match_operand:P 2 "reg_or_cint_operand" "rI"))
 207                (const_int -16)))]
 208   "(TARGET_ALTIVEC || TARGET_VSX) && (reload_in_progress || reload_completed)"
 209   "#"
 210   "&& reload_completed"
 211   [(set (match_dup 0)
 212         (plus:P (match_dup 1)
 213                 (match_dup 2)))
 214    (parallel [(set (match_dup 0)
 215                    (and:P (match_dup 0)
 216                           (const_int -16)))
 217               (clobber:CC (scratch:CC))])])
 218
 219 ;; The normal ANDSI3/ANDDI3 won't match if reload decides to move an AND -16
 220 ;; address to a register because there is no clobber of a (scratch), so we add
 221 ;; it here.
 222 (define_insn_and_split "*vec_reload_and_reg_<mptrsize>"
 223   [(set (match_operand:P 0 "gpc_reg_operand" "=b")
 224         (and:P (match_operand:P 1 "gpc_reg_operand" "r")
 225                (const_int -16)))]
 226   "(TARGET_ALTIVEC || TARGET_VSX) && (reload_in_progress || reload_completed)"
 227   "#"
 228   "&& reload_completed"
 229   [(parallel [(set (match_dup 0)
 230                    (and:P (match_dup 1)
 231                           (const_int -16)))
 232               (clobber:CC (scratch:CC))])])
 233 \f
 234 ;; Generic floating point vector arithmetic support
 235 (define_expand "add<mode>3"
 236   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 237         (plus:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
 238                     (match_operand:VEC_F 2 "vfloat_operand" "")))]
 239   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 240   "")
 241
 242 (define_expand "sub<mode>3"
 243   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 244         (minus:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
 245                      (match_operand:VEC_F 2 "vfloat_operand" "")))]
 246   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 247   "")
 248
 249 (define_expand "mul<mode>3"
 250   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 251         (mult:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
 252                     (match_operand:VEC_F 2 "vfloat_operand" "")))]
 253   "VECTOR_UNIT_VSX_P (<MODE>mode) || VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
 254 {
 255   if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
 256     {
 257       emit_insn (gen_altivec_mulv4sf3 (operands[0], operands[1], operands[2]));
 258       DONE;
 259     }
 260 })
 261
 262 (define_expand "div<mode>3"
 263   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 264         (div:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
 265                    (match_operand:VEC_F 2 "vfloat_operand" "")))]
 266   "VECTOR_UNIT_VSX_P (<MODE>mode)"
 267   "")
 268
 269 (define_expand "neg<mode>2"
 270   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 271         (neg:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
 272   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 273   "
 274 {
 275   if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
 276     {
 277       emit_insn (gen_altivec_negv4sf2 (operands[0], operands[1]));
 278       DONE;
 279     }
 280 }")
 281
 282 (define_expand "abs<mode>2"
 283   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 284         (abs:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
 285   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 286   "
 287 {
 288   if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
 289     {
 290       emit_insn (gen_altivec_absv4sf2 (operands[0], operands[1]));
 291       DONE;
 292     }
 293 }")
 294
 295 (define_expand "smin<mode>3"
 296   [(set (match_operand:VEC_F 0 "register_operand" "")
 297         (smin:VEC_F (match_operand:VEC_F 1 "register_operand" "")
 298                     (match_operand:VEC_F 2 "register_operand" "")))]
 299   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 300   "")
 301
 302 (define_expand "smax<mode>3"
 303   [(set (match_operand:VEC_F 0 "register_operand" "")
 304         (smax:VEC_F (match_operand:VEC_F 1 "register_operand" "")
 305                     (match_operand:VEC_F 2 "register_operand" "")))]
 306   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 307   "")
 308
 309
 310 (define_expand "sqrt<mode>2"
 311   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 312         (sqrt:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
 313   "VECTOR_UNIT_VSX_P (<MODE>mode)"
 314   "")
 315
 316 (define_expand "rsqrte<mode>2"
 317   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 318         (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")]
 319                       UNSPEC_RSQRT))]
 320   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 321   "")
 322
 323 (define_expand "re<mode>2"
 324   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 325         (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "f")]
 326                       UNSPEC_FRES))]
 327   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 328   "")
 329
 330 (define_expand "ftrunc<mode>2"
 331   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 332         (fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
 333   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 334   "")
 335
 336 (define_expand "vector_ceil<mode>2"
 337   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 338         (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")]
 339                       UNSPEC_FRIP))]
 340   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 341   "")
 342
 343 (define_expand "vector_floor<mode>2"
 344   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 345         (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")]
 346                       UNSPEC_FRIM))]
 347   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 348   "")
 349
 350 (define_expand "vector_btrunc<mode>2"
 351   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 352         (fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
 353   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 354   "")
 355
 356 (define_expand "vector_copysign<mode>3"
 357   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 358         (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")
 359                        (match_operand:VEC_F 2 "vfloat_operand" "")] UNSPEC_COPYSIGN))]
 360   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 361   "
 362 {
 363   if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
 364     {
 365       emit_insn (gen_altivec_copysign_v4sf3 (operands[0], operands[1],
 366                                              operands[2]));
 367       DONE;
 368     }
 369 }")
 370
 371 \f
 372 ;; Vector comparisons
 373 (define_expand "vcond<mode><mode>"
 374   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 375         (if_then_else:VEC_F
 376          (match_operator 3 "comparison_operator"
 377                          [(match_operand:VEC_F 4 "vfloat_operand" "")
 378                           (match_operand:VEC_F 5 "vfloat_operand" "")])
 379          (match_operand:VEC_F 1 "vfloat_operand" "")
 380          (match_operand:VEC_F 2 "vfloat_operand" "")))]
 381   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 382   "
 383 {
 384   if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
 385                                     operands[3], operands[4], operands[5]))
 386     DONE;
 387   else
 388     FAIL;
 389 }")
 390
 391 (define_expand "vcond<mode><mode>"
 392   [(set (match_operand:VEC_I 0 "vint_operand" "")
 393         (if_then_else:VEC_I
 394          (match_operator 3 "comparison_operator"
 395                          [(match_operand:VEC_I 4 "vint_operand" "")
 396                           (match_operand:VEC_I 5 "vint_operand" "")])
 397          (match_operand:VEC_I 1 "vint_operand" "")
 398          (match_operand:VEC_I 2 "vint_operand" "")))]
 399   "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
 400   "
 401 {
 402   if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
 403                                     operands[3], operands[4], operands[5]))
 404     DONE;
 405   else
 406     FAIL;
 407 }")
 408
 409 (define_expand "vcondv4sfv4si"
 410   [(set (match_operand:V4SF 0 "vfloat_operand" "")
 411         (if_then_else:V4SF
 412          (match_operator 3 "comparison_operator"
 413                          [(match_operand:V4SI 4 "vint_operand" "")
 414                           (match_operand:V4SI 5 "vint_operand" "")])
 415          (match_operand:V4SF 1 "vfloat_operand" "")
 416          (match_operand:V4SF 2 "vfloat_operand" "")))]
 417   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
 418    && VECTOR_UNIT_ALTIVEC_P (V4SImode)"
 419   "
 420 {
 421   if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
 422                                     operands[3], operands[4], operands[5]))
 423     DONE;
 424   else
 425     FAIL;
 426 }")
 427
 428 (define_expand "vcondv4siv4sf"
 429   [(set (match_operand:V4SI 0 "vint_operand" "")
 430         (if_then_else:V4SI
 431          (match_operator 3 "comparison_operator"
 432                          [(match_operand:V4SF 4 "vfloat_operand" "")
 433                           (match_operand:V4SF 5 "vfloat_operand" "")])
 434          (match_operand:V4SI 1 "vint_operand" "")
 435          (match_operand:V4SI 2 "vint_operand" "")))]
 436   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
 437    && VECTOR_UNIT_ALTIVEC_P (V4SImode)"
 438   "
 439 {
 440   if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
 441                                     operands[3], operands[4], operands[5]))
 442     DONE;
 443   else
 444     FAIL;
 445 }")
 446
 447 (define_expand "vcondu<mode><mode>"
 448   [(set (match_operand:VEC_I 0 "vint_operand" "")
 449         (if_then_else:VEC_I
 450          (match_operator 3 "comparison_operator"
 451                          [(match_operand:VEC_I 4 "vint_operand" "")
 452                           (match_operand:VEC_I 5 "vint_operand" "")])
 453          (match_operand:VEC_I 1 "vint_operand" "")
 454          (match_operand:VEC_I 2 "vint_operand" "")))]
 455   "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
 456   "
 457 {
 458   if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
 459                                     operands[3], operands[4], operands[5]))
 460     DONE;
 461   else
 462     FAIL;
 463 }")
 464
 465 (define_expand "vconduv4sfv4si"
 466   [(set (match_operand:V4SF 0 "vfloat_operand" "")
 467         (if_then_else:V4SF
 468          (match_operator 3 "comparison_operator"
 469                          [(match_operand:V4SI 4 "vint_operand" "")
 470                           (match_operand:V4SI 5 "vint_operand" "")])
 471          (match_operand:V4SF 1 "vfloat_operand" "")
 472          (match_operand:V4SF 2 "vfloat_operand" "")))]
 473   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
 474    && VECTOR_UNIT_ALTIVEC_P (V4SImode)"
 475   "
 476 {
 477   if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
 478                                     operands[3], operands[4], operands[5]))
 479     DONE;
 480   else
 481     FAIL;
 482 }")
 483
 484 (define_expand "vector_eq<mode>"
 485   [(set (match_operand:VEC_C 0 "vlogical_operand" "")
 486         (eq:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "")
 487                   (match_operand:VEC_C 2 "vlogical_operand" "")))]
 488   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 489   "")
 490
 491 (define_expand "vector_gt<mode>"
 492   [(set (match_operand:VEC_C 0 "vlogical_operand" "")
 493         (gt:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "")
 494                   (match_operand:VEC_C 2 "vlogical_operand" "")))]
 495   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 496   "")
 497
 498 (define_expand "vector_ge<mode>"
 499   [(set (match_operand:VEC_C 0 "vlogical_operand" "")
 500         (ge:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "")
 501                   (match_operand:VEC_C 2 "vlogical_operand" "")))]
 502   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 503   "")
 504
 505 (define_expand "vector_gtu<mode>"
 506   [(set (match_operand:VEC_I 0 "vint_operand" "")
 507         (gtu:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
 508                    (match_operand:VEC_I 2 "vint_operand" "")))]
 509   "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
 510   "")
 511
 512 (define_expand "vector_geu<mode>"
 513   [(set (match_operand:VEC_I 0 "vint_operand" "")
 514         (geu:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
 515                    (match_operand:VEC_I 2 "vint_operand" "")))]
 516   "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
 517   "")
 518
 519 (define_insn_and_split "*vector_uneq<mode>"
 520   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 521         (uneq:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
 522                     (match_operand:VEC_F 2 "vfloat_operand" "")))]
 523   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 524   "#"
 525   ""
 526   [(set (match_dup 3)
 527         (gt:VEC_F (match_dup 1)
 528                   (match_dup 2)))
 529    (set (match_dup 4)
 530         (gt:VEC_F (match_dup 2)
 531                   (match_dup 1)))
 532    (set (match_dup 0)
 533         (not:VEC_F (ior:VEC_F (match_dup 3)
 534                               (match_dup 4))))]
 535   "
 536 {
 537   operands[3] = gen_reg_rtx (<MODE>mode);
 538   operands[4] = gen_reg_rtx (<MODE>mode);
 539 }")
 540
 541 (define_insn_and_split "*vector_ltgt<mode>"
 542   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 543         (ltgt:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
 544                     (match_operand:VEC_F 2 "vfloat_operand" "")))]
 545   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 546   "#"
 547   ""
 548   [(set (match_dup 3)
 549         (gt:VEC_F (match_dup 1)
 550                   (match_dup 2)))
 551    (set (match_dup 4)
 552         (gt:VEC_F (match_dup 2)
 553                   (match_dup 1)))
 554    (set (match_dup 0)
 555         (ior:VEC_F (match_dup 3)
 556                    (match_dup 4)))]
 557   "
 558 {
 559   operands[3] = gen_reg_rtx (<MODE>mode);
 560   operands[4] = gen_reg_rtx (<MODE>mode);
 561 }")
 562
 563 (define_insn_and_split "*vector_ordered<mode>"
 564   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 565         (ordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
 566                        (match_operand:VEC_F 2 "vfloat_operand" "")))]
 567   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 568   "#"
 569   ""
 570   [(set (match_dup 3)
 571         (ge:VEC_F (match_dup 1)
 572                   (match_dup 2)))
 573    (set (match_dup 4)
 574         (ge:VEC_F (match_dup 2)
 575                   (match_dup 1)))
 576    (set (match_dup 0)
 577         (ior:VEC_F (match_dup 3)
 578                    (match_dup 4)))]
 579   "
 580 {
 581   operands[3] = gen_reg_rtx (<MODE>mode);
 582   operands[4] = gen_reg_rtx (<MODE>mode);
 583 }")
 584
 585 (define_insn_and_split "*vector_unordered<mode>"
 586   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 587         (unordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
 588                          (match_operand:VEC_F 2 "vfloat_operand" "")))]
 589   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 590   "#"
 591   ""
 592   [(set (match_dup 3)
 593         (ge:VEC_F (match_dup 1)
 594                   (match_dup 2)))
 595    (set (match_dup 4)
 596         (ge:VEC_F (match_dup 2)
 597                   (match_dup 1)))
 598    (set (match_dup 0)
 599         (not:VEC_F (ior:VEC_F (match_dup 3)
 600                               (match_dup 4))))]
 601   "
 602 {
 603   operands[3] = gen_reg_rtx (<MODE>mode);
 604   operands[4] = gen_reg_rtx (<MODE>mode);
 605 }")
 606
 607 ;; Note the arguments for __builtin_altivec_vsel are op2, op1, mask
 608 ;; which is in the reverse order that we want
 609 (define_expand "vector_select_<mode>"
 610   [(set (match_operand:VEC_L 0 "vlogical_operand" "")
 611         (if_then_else:VEC_L
 612          (ne:CC (match_operand:VEC_L 3 "vlogical_operand" "")
 613                 (match_dup 4))
 614          (match_operand:VEC_L 2 "vlogical_operand" "")
 615          (match_operand:VEC_L 1 "vlogical_operand" "")))]
 616   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 617   "operands[4] = CONST0_RTX (<MODE>mode);")
 618
 619 (define_expand "vector_select_<mode>_uns"
 620   [(set (match_operand:VEC_L 0 "vlogical_operand" "")
 621         (if_then_else:VEC_L
 622          (ne:CCUNS (match_operand:VEC_L 3 "vlogical_operand" "")
 623                    (match_dup 4))
 624          (match_operand:VEC_L 2 "vlogical_operand" "")
 625          (match_operand:VEC_L 1 "vlogical_operand" "")))]
 626   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 627   "operands[4] = CONST0_RTX (<MODE>mode);")
 628
 629 ;; Expansions that compare vectors producing a vector result and a predicate,
 630 ;; setting CR6 to indicate a combined status
 631 (define_expand "vector_eq_<mode>_p"
 632   [(parallel
 633     [(set (reg:CC 74)
 634           (unspec:CC [(eq:CC (match_operand:VEC_A 1 "vlogical_operand" "")
 635                              (match_operand:VEC_A 2 "vlogical_operand" ""))]
 636                      UNSPEC_PREDICATE))
 637      (set (match_operand:VEC_A 0 "vlogical_operand" "")
 638           (eq:VEC_A (match_dup 1)
 639                     (match_dup 2)))])]
 640   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 641   "")
 642
 643 (define_expand "vector_gt_<mode>_p"
 644   [(parallel
 645     [(set (reg:CC 74)
 646           (unspec:CC [(gt:CC (match_operand:VEC_A 1 "vlogical_operand" "")
 647                              (match_operand:VEC_A 2 "vlogical_operand" ""))]
 648                      UNSPEC_PREDICATE))
 649      (set (match_operand:VEC_A 0 "vlogical_operand" "")
 650           (gt:VEC_A (match_dup 1)
 651                     (match_dup 2)))])]
 652   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 653   "")
 654
 655 (define_expand "vector_ge_<mode>_p"
 656   [(parallel
 657     [(set (reg:CC 74)
 658           (unspec:CC [(ge:CC (match_operand:VEC_F 1 "vfloat_operand" "")
 659                              (match_operand:VEC_F 2 "vfloat_operand" ""))]
 660                      UNSPEC_PREDICATE))
 661      (set (match_operand:VEC_F 0 "vfloat_operand" "")
 662           (ge:VEC_F (match_dup 1)
 663                     (match_dup 2)))])]
 664   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 665   "")
 666
 667 (define_expand "vector_gtu_<mode>_p"
 668   [(parallel
 669     [(set (reg:CC 74)
 670           (unspec:CC [(gtu:CC (match_operand:VEC_I 1 "vint_operand" "")
 671                               (match_operand:VEC_I 2 "vint_operand" ""))]
 672                      UNSPEC_PREDICATE))
 673      (set (match_operand:VEC_I 0 "vlogical_operand" "")
 674           (gtu:VEC_I (match_dup 1)
 675                      (match_dup 2)))])]
 676   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 677   "")
 678
 679 ;; AltiVec/VSX predicates.
 680
 681 (define_expand "cr6_test_for_zero"
 682   [(set (match_operand:SI 0 "register_operand" "=r")
 683         (eq:SI (reg:CC 74)
 684                (const_int 0)))]
 685   "TARGET_ALTIVEC || TARGET_VSX"
 686   "")
 687
 688 (define_expand "cr6_test_for_zero_reverse"
 689   [(set (match_operand:SI 0 "register_operand" "=r")
 690         (eq:SI (reg:CC 74)
 691                (const_int 0)))
 692    (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
 693   "TARGET_ALTIVEC || TARGET_VSX"
 694   "")
 695
 696 (define_expand "cr6_test_for_lt"
 697   [(set (match_operand:SI 0 "register_operand" "=r")
 698         (lt:SI (reg:CC 74)
 699                (const_int 0)))]
 700   "TARGET_ALTIVEC || TARGET_VSX"
 701   "")
 702
 703 (define_expand "cr6_test_for_lt_reverse"
 704   [(set (match_operand:SI 0 "register_operand" "=r")
 705         (lt:SI (reg:CC 74)
 706                (const_int 0)))
 707    (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
 708   "TARGET_ALTIVEC || TARGET_VSX"
 709   "")
 710
 711 \f
 712 ;; Vector logical instructions
 713 (define_expand "xor<mode>3"
 714   [(set (match_operand:VEC_L 0 "vlogical_operand" "")
 715         (xor:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")
 716                    (match_operand:VEC_L 2 "vlogical_operand" "")))]
 717   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
 718   "")
 719
 720 (define_expand "ior<mode>3"
 721   [(set (match_operand:VEC_L 0 "vlogical_operand" "")
 722         (ior:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")
 723                    (match_operand:VEC_L 2 "vlogical_operand" "")))]
 724   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
 725   "")
 726
 727 (define_expand "and<mode>3"
 728   [(set (match_operand:VEC_L 0 "vlogical_operand" "")
 729         (and:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")
 730                    (match_operand:VEC_L 2 "vlogical_operand" "")))]
 731   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
 732   "")
 733
 734 (define_expand "one_cmpl<mode>2"
 735   [(set (match_operand:VEC_L 0 "vlogical_operand" "")
 736         (not:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")))]
 737   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
 738   "")
 739
 740 (define_expand "nor<mode>3"
 741   [(set (match_operand:VEC_L 0 "vlogical_operand" "")
 742         (not:VEC_L (ior:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")
 743                               (match_operand:VEC_L 2 "vlogical_operand" ""))))]
 744   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
 745   "")
 746
 747 (define_expand "andc<mode>3"
 748   [(set (match_operand:VEC_L 0 "vlogical_operand" "")
 749         (and:VEC_L (not:VEC_L (match_operand:VEC_L 2 "vlogical_operand" ""))
 750                    (match_operand:VEC_L 1 "vlogical_operand" "")))]
 751   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
 752   "")
 753
 754 ;; Same size conversions
 755 (define_expand "float<VEC_int><mode>2"
 756   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 757         (float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand" "")))]
 758   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 759   "
 760 {
 761   if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
 762     {
 763       emit_insn (gen_altivec_vcfsx (operands[0], operands[1], const0_rtx));
 764       DONE;
 765     }
 766 }")
 767
 768 (define_expand "floatuns<VEC_int><mode>2"
 769   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
 770         (unsigned_float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand" "")))]
 771   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 772   "
 773 {
 774   if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
 775     {
 776       emit_insn (gen_altivec_vcfux (operands[0], operands[1], const0_rtx));
 777       DONE;
 778     }
 779 }")
 780
 781 (define_expand "fix_trunc<mode><VEC_int>2"
 782   [(set (match_operand:<VEC_INT> 0 "vint_operand" "")
 783         (fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand" "")))]
 784   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 785   "
 786 {
 787   if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
 788     {
 789       emit_insn (gen_altivec_vctsxs (operands[0], operands[1], const0_rtx));
 790       DONE;
 791     }
 792 }")
 793
 794 (define_expand "fixuns_trunc<mode><VEC_int>2"
 795   [(set (match_operand:<VEC_INT> 0 "vint_operand" "")
 796         (unsigned_fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand" "")))]
 797   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 798   "
 799 {
 800   if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
 801     {
 802       emit_insn (gen_altivec_vctuxs (operands[0], operands[1], const0_rtx));
 803       DONE;
 804     }
 805 }")
 806
 807 \f
 808 ;; Vector initialization, set, extract
 809 (define_expand "vec_init<mode>"
 810   [(match_operand:VEC_E 0 "vlogical_operand" "")
 811    (match_operand:VEC_E 1 "" "")]
 812   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
 813 {
 814   rs6000_expand_vector_init (operands[0], operands[1]);
 815   DONE;
 816 })
 817
 818 (define_expand "vec_set<mode>"
 819   [(match_operand:VEC_E 0 "vlogical_operand" "")
 820    (match_operand:<VEC_base> 1 "register_operand" "")
 821    (match_operand 2 "const_int_operand" "")]
 822   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
 823 {
 824   rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
 825   DONE;
 826 })
 827
 828 (define_expand "vec_extract<mode>"
 829   [(match_operand:<VEC_base> 0 "register_operand" "")
 830    (match_operand:VEC_E 1 "vlogical_operand" "")
 831    (match_operand 2 "const_int_operand" "")]
 832   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
 833 {
 834   rs6000_expand_vector_extract (operands[0], operands[1],
 835                                 INTVAL (operands[2]));
 836   DONE;
 837 })
 838 \f
 839 ;; Convert double word types to single word types
 840 (define_expand "vec_pack_trunc_v2df"
 841   [(match_operand:V4SF 0 "vfloat_operand" "")
 842    (match_operand:V2DF 1 "vfloat_operand" "")
 843    (match_operand:V2DF 2 "vfloat_operand" "")]
 844   "VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
 845 {
 846   rtx r1 = gen_reg_rtx (V4SFmode);
 847   rtx r2 = gen_reg_rtx (V4SFmode);
 848
 849   emit_insn (gen_vsx_xvcvdpsp (r1, operands[1]));
 850   emit_insn (gen_vsx_xvcvdpsp (r2, operands[2]));
 851   rs6000_expand_extract_even (operands[0], r1, r2);
 852   DONE;
 853 })
 854
 855 (define_expand "vec_pack_sfix_trunc_v2df"
 856   [(match_operand:V4SI 0 "vint_operand" "")
 857    (match_operand:V2DF 1 "vfloat_operand" "")
 858    (match_operand:V2DF 2 "vfloat_operand" "")]
 859   "VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
 860 {
 861   rtx r1 = gen_reg_rtx (V4SImode);
 862   rtx r2 = gen_reg_rtx (V4SImode);
 863
 864   emit_insn (gen_vsx_xvcvdpsxws (r1, operands[1]));
 865   emit_insn (gen_vsx_xvcvdpsxws (r2, operands[2]));
 866   rs6000_expand_extract_even (operands[0], r1, r2);
 867   DONE;
 868 })
 869
 870 (define_expand "vec_pack_ufix_trunc_v2df"
 871   [(match_operand:V4SI 0 "vint_operand" "")
 872    (match_operand:V2DF 1 "vfloat_operand" "")
 873    (match_operand:V2DF 2 "vfloat_operand" "")]
 874   "VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
 875 {
 876   rtx r1 = gen_reg_rtx (V4SImode);
 877   rtx r2 = gen_reg_rtx (V4SImode);
 878
 879   emit_insn (gen_vsx_xvcvdpuxws (r1, operands[1]));
 880   emit_insn (gen_vsx_xvcvdpuxws (r2, operands[2]));
 881   rs6000_expand_extract_even (operands[0], r1, r2);
 882   DONE;
 883 })
 884
 885 ;; Convert single word types to double word
 886 (define_expand "vec_unpacks_hi_v4sf"
 887   [(match_operand:V2DF 0 "vfloat_operand" "")
 888    (match_operand:V4SF 1 "vfloat_operand" "")]
 889   "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
 890 {
 891   rtx reg = gen_reg_rtx (V4SFmode);
 892
 893   rs6000_expand_interleave (reg, operands[1], operands[1], true);
 894   emit_insn (gen_vsx_xvcvspdp (operands[0], reg));
 895   DONE;
 896 })
 897
 898 (define_expand "vec_unpacks_lo_v4sf"
 899   [(match_operand:V2DF 0 "vfloat_operand" "")
 900    (match_operand:V4SF 1 "vfloat_operand" "")]
 901   "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
 902 {
 903   rtx reg = gen_reg_rtx (V4SFmode);
 904
 905   rs6000_expand_interleave (reg, operands[1], operands[1], false);
 906   emit_insn (gen_vsx_xvcvspdp (operands[0], reg));
 907   DONE;
 908 })
 909
 910 (define_expand "vec_unpacks_float_hi_v4si"
 911   [(match_operand:V2DF 0 "vfloat_operand" "")
 912    (match_operand:V4SI 1 "vint_operand" "")]
 913   "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
 914 {
 915   rtx reg = gen_reg_rtx (V4SImode);
 916
 917   rs6000_expand_interleave (reg, operands[1], operands[1], true);
 918   emit_insn (gen_vsx_xvcvsxwdp (operands[0], reg));
 919   DONE;
 920 })
 921
 922 (define_expand "vec_unpacks_float_lo_v4si"
 923   [(match_operand:V2DF 0 "vfloat_operand" "")
 924    (match_operand:V4SI 1 "vint_operand" "")]
 925   "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
 926 {
 927   rtx reg = gen_reg_rtx (V4SImode);
 928
 929   rs6000_expand_interleave (reg, operands[1], operands[1], false);
 930   emit_insn (gen_vsx_xvcvsxwdp (operands[0], reg));
 931   DONE;
 932 })
 933
 934 (define_expand "vec_unpacku_float_hi_v4si"
 935   [(match_operand:V2DF 0 "vfloat_operand" "")
 936    (match_operand:V4SI 1 "vint_operand" "")]
 937   "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
 938 {
 939   rtx reg = gen_reg_rtx (V4SImode);
 940
 941   rs6000_expand_interleave (reg, operands[1], operands[1], true);
 942   emit_insn (gen_vsx_xvcvuxwdp (operands[0], reg));
 943   DONE;
 944 })
 945
 946 (define_expand "vec_unpacku_float_lo_v4si"
 947   [(match_operand:V2DF 0 "vfloat_operand" "")
 948    (match_operand:V4SI 1 "vint_operand" "")]
 949   "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
 950 {
 951   rtx reg = gen_reg_rtx (V4SImode);
 952
 953   rs6000_expand_interleave (reg, operands[1], operands[1], false);
 954   emit_insn (gen_vsx_xvcvuxwdp (operands[0], reg));
 955   DONE;
 956 })
 957
 958 \f
 959 ;; Align vector loads with a permute.
 960 (define_expand "vec_realign_load_<mode>"
 961   [(match_operand:VEC_K 0 "vlogical_operand" "")
 962    (match_operand:VEC_K 1 "vlogical_operand" "")
 963    (match_operand:VEC_K 2 "vlogical_operand" "")
 964    (match_operand:V16QI 3 "vlogical_operand" "")]
 965   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
 966 {
 967   emit_insn (gen_altivec_vperm_<mode> (operands[0], operands[1], operands[2],
 968                                        operands[3]));
 969   DONE;
 970 })
 971
 972 ;; Under VSX, vectors of 4/8 byte alignments do not need to be aligned
 973 ;; since the load already handles it.
 974 (define_expand "movmisalign<mode>"
 975  [(set (match_operand:VEC_N 0 "nonimmediate_operand" "")
 976        (match_operand:VEC_N 1 "any_operand" ""))]
 977  "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_ALLOW_MOVMISALIGN"
 978  "")
 979
 980 \f
 981 ;; Vector shift left in bits.  Currently supported ony for shift
 982 ;; amounts that can be expressed as byte shifts (divisible by 8).
 983 ;; General shift amounts can be supported using vslo + vsl. We're
 984 ;; not expecting to see these yet (the vectorizer currently
 985 ;; generates only shifts divisible by byte_size).
 986 (define_expand "vec_shl_<mode>"
 987   [(match_operand:VEC_L 0 "vlogical_operand" "")
 988    (match_operand:VEC_L 1 "vlogical_operand" "")
 989    (match_operand:QI 2 "reg_or_short_operand" "")]
 990   "TARGET_ALTIVEC"
 991   "
 992 {
 993   rtx bitshift = operands[2];
 994   rtx shift;
 995   rtx insn;
 996   HOST_WIDE_INT bitshift_val;
 997   HOST_WIDE_INT byteshift_val;
 998
 999   if (! CONSTANT_P (bitshift))
1000     FAIL;
1001   bitshift_val = INTVAL (bitshift);
1002   if (bitshift_val & 0x7)
1003     FAIL;
1004   byteshift_val = bitshift_val >> 3;
1005   if (TARGET_VSX && (byteshift_val & 0x3) == 0)
1006     {
1007       shift = gen_rtx_CONST_INT (QImode, byteshift_val >> 2);
1008       insn = gen_vsx_xxsldwi_<mode> (operands[0], operands[1], operands[1],
1009                                      shift);
1010     }
1011   else
1012     {
1013       shift = gen_rtx_CONST_INT (QImode, byteshift_val);
1014       insn = gen_altivec_vsldoi_<mode> (operands[0], operands[1], operands[1],
1015                                         shift);
1016     }
1017
1018   emit_insn (insn);
1019   DONE;
1020 }")
1021
1022 ;; Vector shift right in bits. Currently supported ony for shift
1023 ;; amounts that can be expressed as byte shifts (divisible by 8).
1024 ;; General shift amounts can be supported using vsro + vsr. We're
1025 ;; not expecting to see these yet (the vectorizer currently
1026 ;; generates only shifts divisible by byte_size).
1027 (define_expand "vec_shr_<mode>"
1028   [(match_operand:VEC_L 0 "vlogical_operand" "")
1029    (match_operand:VEC_L 1 "vlogical_operand" "")
1030    (match_operand:QI 2 "reg_or_short_operand" "")]
1031   "TARGET_ALTIVEC"
1032   "
1033 {
1034   rtx bitshift = operands[2];
1035   rtx shift;
1036   rtx insn;
1037   HOST_WIDE_INT bitshift_val;
1038   HOST_WIDE_INT byteshift_val;
1039
1040   if (! CONSTANT_P (bitshift))
1041     FAIL;
1042   bitshift_val = INTVAL (bitshift);
1043   if (bitshift_val & 0x7)
1044     FAIL;
1045   byteshift_val = 16 - (bitshift_val >> 3);
1046   if (TARGET_VSX && (byteshift_val & 0x3) == 0)
1047     {
1048       shift = gen_rtx_CONST_INT (QImode, byteshift_val >> 2);
1049       insn = gen_vsx_xxsldwi_<mode> (operands[0], operands[1], operands[1],
1050                                      shift);
1051     }
1052   else
1053     {
1054       shift = gen_rtx_CONST_INT (QImode, byteshift_val);
1055       insn = gen_altivec_vsldoi_<mode> (operands[0], operands[1], operands[1],
1056                                         shift);
1057     }
1058
1059   emit_insn (insn);
1060   DONE;
1061 }")
1062
1063 ;; Expanders for rotate each element in a vector
1064 (define_expand "vrotl<mode>3"
1065   [(set (match_operand:VEC_I 0 "vint_operand" "")
1066         (rotate:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
1067                       (match_operand:VEC_I 2 "vint_operand" "")))]
1068   "TARGET_ALTIVEC"
1069   "")
1070
1071 ;; Expanders for arithmetic shift left on each vector element
1072 (define_expand "vashl<mode>3"
1073   [(set (match_operand:VEC_I 0 "vint_operand" "")
1074         (ashift:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
1075                       (match_operand:VEC_I 2 "vint_operand" "")))]
1076   "TARGET_ALTIVEC"
1077   "")
1078
1079 ;; Expanders for logical shift right on each vector element
1080 (define_expand "vlshr<mode>3"
1081   [(set (match_operand:VEC_I 0 "vint_operand" "")
1082         (lshiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
1083                         (match_operand:VEC_I 2 "vint_operand" "")))]
1084   "TARGET_ALTIVEC"
1085   "")
1086
1087 ;; Expanders for arithmetic shift right on each vector element
1088 (define_expand "vashr<mode>3"
1089   [(set (match_operand:VEC_I 0 "vint_operand" "")
1090         (ashiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
1091                         (match_operand:VEC_I 2 "vint_operand" "")))]
1092   "TARGET_ALTIVEC"
1093   "")
1094 \f
1095 ;; Vector reduction expanders for VSX
1096
1097 (define_expand "reduc_<VEC_reduc_name>_v2df"
1098   [(parallel [(set (match_operand:V2DF 0 "vfloat_operand" "")
1099                    (VEC_reduc:V2DF
1100                     (vec_concat:V2DF
1101                      (vec_select:DF
1102                       (match_operand:V2DF 1 "vfloat_operand" "")
1103                       (parallel [(const_int 1)]))
1104                      (vec_select:DF
1105                       (match_dup 1)
1106                       (parallel [(const_int 0)])))
1107                     (match_dup 1)))
1108               (clobber (match_scratch:V2DF 2 ""))])]
1109   "VECTOR_UNIT_VSX_P (V2DFmode)"
1110   "")
1111
1112 ; The (VEC_reduc:V4SF
1113 ;       (op1)
1114 ;       (unspec:V4SF [(const_int 0)] UNSPEC_REDUC))
1115 ;
1116 ; is to allow us to use a code iterator, but not completely list all of the
1117 ; vector rotates, etc. to prevent canonicalization
1118
1119 (define_expand "reduc_<VEC_reduc_name>_v4sf"
1120   [(parallel [(set (match_operand:V4SF 0 "vfloat_operand" "")
1121                    (VEC_reduc:V4SF
1122                     (unspec:V4SF [(const_int 0)] UNSPEC_REDUC)
1123                     (match_operand:V4SF 1 "vfloat_operand" "")))
1124               (clobber (match_scratch:V4SF 2 ""))
1125               (clobber (match_scratch:V4SF 3 ""))])]
1126   "VECTOR_UNIT_VSX_P (V4SFmode)"
1127   "")
1128
1129 \f
1130 ;;; Expanders for vector insn patterns shared between the SPE and TARGET_PAIRED systems.
1131
1132 (define_expand "absv2sf2"
1133   [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
1134         (abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")))]
1135   "TARGET_PAIRED_FLOAT || TARGET_SPE"
1136   "")
1137
1138 (define_expand "negv2sf2"
1139   [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
1140         (neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")))]
1141   "TARGET_PAIRED_FLOAT || TARGET_SPE"
1142   "")
1143
1144 (define_expand "addv2sf3"
1145   [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
1146         (plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
1147                    (match_operand:V2SF 2 "gpc_reg_operand" "")))]
1148   "TARGET_PAIRED_FLOAT || TARGET_SPE"
1149   "
1150 {
1151   if (TARGET_SPE)
1152     {
1153       /* We need to make a note that we clobber SPEFSCR.  */
1154       rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
1155
1156       XVECEXP (par, 0, 0) = gen_rtx_SET (VOIDmode, operands[0],
1157                                          gen_rtx_PLUS (V2SFmode, operands[1], operands[2]));
1158       XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
1159       emit_insn (par);
1160       DONE;
1161     }
1162 }")
1163
1164 (define_expand "subv2sf3"
1165   [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
1166         (minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
1167                     (match_operand:V2SF 2 "gpc_reg_operand" "")))]
1168   "TARGET_PAIRED_FLOAT || TARGET_SPE"
1169   "
1170 {
1171   if (TARGET_SPE)
1172     {
1173       /* We need to make a note that we clobber SPEFSCR.  */
1174       rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
1175
1176       XVECEXP (par, 0, 0) = gen_rtx_SET (VOIDmode, operands[0],
1177                                          gen_rtx_MINUS (V2SFmode, operands[1], operands[2]));
1178       XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
1179       emit_insn (par);
1180       DONE;
1181     }
1182 }")
1183
1184 (define_expand "mulv2sf3"
1185   [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
1186         (mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
1187                    (match_operand:V2SF 2 "gpc_reg_operand" "")))]
1188   "TARGET_PAIRED_FLOAT || TARGET_SPE"
1189   "
1190 {
1191   if (TARGET_SPE)
1192     {
1193       /* We need to make a note that we clobber SPEFSCR.  */
1194       rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
1195
1196       XVECEXP (par, 0, 0) = gen_rtx_SET (VOIDmode, operands[0],
1197                                          gen_rtx_MULT (V2SFmode, operands[1], operands[2]));
1198       XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
1199       emit_insn (par);
1200       DONE;
1201     }
1202 }")
1203
1204 (define_expand "divv2sf3"
1205   [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
1206         (div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
1207                   (match_operand:V2SF 2 "gpc_reg_operand" "")))]
1208   "TARGET_PAIRED_FLOAT || TARGET_SPE"
1209   "
1210 {
1211   if (TARGET_SPE)
1212     {
1213       /* We need to make a note that we clobber SPEFSCR.  */
1214       rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
1215
1216       XVECEXP (par, 0, 0) = gen_rtx_SET (VOIDmode, operands[0],
1217                                          gen_rtx_DIV (V2SFmode, operands[1], operands[2]));
1218       XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
1219       emit_insn (par);
1220       DONE;
1221     }
1222 }")